Split RAM and ROM to 8 banks.
This commit is contained in:
colin
parent
fd6791eb26
commit
d61bc07515
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@ -26,7 +26,8 @@ LOCATE COMP "jtag_trst_n" SITE "M3";
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IOBUF PORT "jtag_trst_n" IO_TYPE=LVCMOS33;
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FREQUENCY PORT "jtag_trst_n" 25 MHZ;
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LOCATE COMP "jtag_tdo" SITE "M4";
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IOBUF PORT "jtag_tdo" IO_TYPE=LVCMOS33;
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LOCATE COMP "clk_o" SITE "A3";
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IOBUF PORT "clk_o" IO_TYPE=LVCMOS33;
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212
soc/ahb_sif.sv
212
soc/ahb_sif.sv
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@ -53,34 +53,54 @@ module axi_slv #(
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output reg [TAGW-1:0] bid
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);
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parameter MEM_DEPTH = 15; // memory size = 0x8000 = 32k WIDTH=15
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parameter MEM_DEPTH_EACH = MEM_DEPTH - 3; // memory size = 0x8000 = 32k WIDTH=15
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parameter MEM_DEPTH = 15; // memory size = 0x8000 = 32k WIDTH=15
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parameter MEM_DEPTH_EACH = MEM_DEPTH - 3; // memory size = 0x8000 = 32k WIDTH=15
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bit [7:0] mem0[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem1[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem2[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem3[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem4[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem5[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem6[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem7[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem0[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem1[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem2[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem3[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem4[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem5[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem6[(1<<MEM_DEPTH_EACH)-1:0];
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bit [7:0] mem7[(1<<MEM_DEPTH_EACH)-1:0];
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bit [63:0] memdata;
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bit [63:0] memdata;
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wire [MEM_DEPTH-1:0] saraddr = araddr[MEM_DEPTH - 1:0];
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wire [MEM_DEPTH-1:0] sawaddr = awaddr[MEM_DEPTH - 1:0];
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wire [MEM_DEPTH-4:0] saraddr0 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h0 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr1 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h1 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr2 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h2 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr3 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h3 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr4 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h4 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr5 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h5 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr6 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h6 ? 1 : 0);
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wire [MEM_DEPTH-4:0] saraddr7 = araddr[MEM_DEPTH - 1:3];
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initial begin
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mem0[0]= 8'h0;
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mem0[1]= 8'h0;
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mem0[2]= 8'h0;
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mem0[3]= 8'h63;
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mem0[5]= 8'h0;
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mem0[6]= 8'h0;
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mem0[7]= 8'h0;
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mem0[8]= 8'h0;
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end
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always @(posedge aclk or negedge rst_l) begin
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wire [7:0] rm0 = mem0[saraddr0];
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wire [7:0] rm1 = mem1[saraddr1];
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wire [7:0] rm2 = mem2[saraddr2];
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wire [7:0] rm3 = mem3[saraddr3];
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wire [7:0] rm4 = mem4[saraddr4];
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wire [7:0] rm5 = mem5[saraddr5];
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wire [7:0] rm6 = mem6[saraddr6];
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wire [7:0] rm7 = mem7[saraddr7];
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wire [MEM_DEPTH-4:0] sawaddr0 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 0 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr1 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 1 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr2 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 2 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr3 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 3 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr4 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 4 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr5 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 5 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr6 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 6 ? 1 : 0);
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wire [MEM_DEPTH-4:0] sawaddr7 = awaddr[MEM_DEPTH - 1:3];
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initial begin
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mem0[0] = 8'h63;
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mem1[0] = 8'h0;
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mem2[0] = 8'h0;
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mem3[0] = 8'h0;
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end
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always @(posedge aclk or negedge rst_l) begin
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if (!rst_l) begin
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rvalid <= 0;
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bvalid <= 0;
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@ -91,38 +111,128 @@ module axi_slv #(
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bvalid <= awvalid;
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rdata <= memdata;
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end
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end
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end
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always @(negedge aclk) begin
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always @(negedge aclk) begin
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if (arvalid)
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memdata <= {
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mem7[saraddr + 7],
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mem6[saraddr + 6],
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mem5[saraddr + 5],
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mem4[saraddr + 4],
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mem3[saraddr + 3],
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mem2[saraddr + 2],
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mem1[saraddr + 1],
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mem0[saraddr]
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};
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case (araddr[2:0])
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3'h0: begin
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memdata <= {rm7, rm6, rm5, rm4, rm3, rm2, rm1, rm0};
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end
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3'h1: begin
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memdata <= {rm0, rm7, rm6, rm5, rm4, rm3, rm2, rm1};
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end
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3'h2: begin
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memdata <= {rm1, rm0, rm7, rm6, rm5, rm4, rm3, rm2};
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end
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3'h3: begin
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memdata <= {rm2, rm1, rm0, rm7, rm6, rm5, rm4, rm3};
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end
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3'h4: begin
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memdata <= {rm3, rm2, rm1, rm0, rm7, rm6, rm5, rm4};
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end
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3'h5: begin
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memdata <= {rm4, rm3, rm2, rm1, rm0, rm7, rm6, rm5};
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end
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3'h6: begin
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memdata <= {rm5, rm4, rm3, rm2, rm1, rm0, rm7, rm6};
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end
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3'h7: begin
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memdata <= {rm7, rm6, rm5, rm4, rm3, rm2, rm1, rm0};
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end
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endcase
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if (awvalid) begin
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if (wstrb[7]) mem7[sawaddr + 7] = wdata[63:56];
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if (wstrb[6]) mem6[sawaddr + 6] = wdata[55:48];
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if (wstrb[5]) mem5[sawaddr + 5] = wdata[47:40];
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if (wstrb[4]) mem4[sawaddr + 4] = wdata[39:32];
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if (wstrb[3]) mem3[sawaddr + 3] = wdata[31:24];
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if (wstrb[2]) mem2[sawaddr + 2] = wdata[23:16];
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if (wstrb[1]) mem1[sawaddr + 1] = wdata[15:08];
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if (wstrb[0]) mem0[sawaddr + 0] = wdata[07:00];
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case (awaddr[2:0])
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3'h0: begin
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if (wstrb[7]) mem7[sawaddr7] = wdata[63:56];
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if (wstrb[6]) mem6[sawaddr6] = wdata[55:48];
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if (wstrb[5]) mem5[sawaddr5] = wdata[47:40];
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if (wstrb[4]) mem4[sawaddr4] = wdata[39:32];
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if (wstrb[3]) mem3[sawaddr3] = wdata[31:24];
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if (wstrb[2]) mem2[sawaddr2] = wdata[23:16];
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if (wstrb[1]) mem1[sawaddr1] = wdata[15:08];
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if (wstrb[0]) mem0[sawaddr0] = wdata[07:00];
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end
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3'h1: begin
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if (wstrb[7]) mem0[sawaddr0] = wdata[63:56];
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if (wstrb[6]) mem7[sawaddr7] = wdata[55:48];
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if (wstrb[5]) mem6[sawaddr6] = wdata[47:40];
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if (wstrb[4]) mem5[sawaddr5] = wdata[39:32];
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if (wstrb[3]) mem4[sawaddr4] = wdata[31:24];
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if (wstrb[2]) mem3[sawaddr3] = wdata[23:16];
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if (wstrb[1]) mem2[sawaddr2] = wdata[15:08];
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if (wstrb[0]) mem1[sawaddr1] = wdata[07:00];
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end
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3'h2: begin
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if (wstrb[7]) mem1[sawaddr1] = wdata[63:56];
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if (wstrb[6]) mem0[sawaddr0] = wdata[55:48];
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if (wstrb[5]) mem7[sawaddr7] = wdata[47:40];
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if (wstrb[4]) mem6[sawaddr6] = wdata[39:32];
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if (wstrb[3]) mem5[sawaddr5] = wdata[31:24];
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if (wstrb[2]) mem4[sawaddr4] = wdata[23:16];
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if (wstrb[1]) mem3[sawaddr3] = wdata[15:08];
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if (wstrb[0]) mem2[sawaddr2] = wdata[07:00];
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end
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3'h3: begin
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if (wstrb[7]) mem2[sawaddr2] = wdata[63:56];
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if (wstrb[6]) mem1[sawaddr1] = wdata[55:48];
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if (wstrb[5]) mem0[sawaddr0] = wdata[47:40];
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if (wstrb[4]) mem7[sawaddr7] = wdata[39:32];
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if (wstrb[3]) mem6[sawaddr6] = wdata[31:24];
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if (wstrb[2]) mem5[sawaddr5] = wdata[23:16];
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if (wstrb[1]) mem4[sawaddr4] = wdata[15:08];
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if (wstrb[0]) mem3[sawaddr3] = wdata[07:00];
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end
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3'h4: begin
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if (wstrb[7]) mem3[sawaddr3] = wdata[63:56];
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if (wstrb[6]) mem2[sawaddr2] = wdata[55:48];
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if (wstrb[5]) mem1[sawaddr1] = wdata[47:40];
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if (wstrb[4]) mem0[sawaddr0] = wdata[39:32];
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if (wstrb[3]) mem7[sawaddr7] = wdata[31:24];
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if (wstrb[2]) mem6[sawaddr6] = wdata[23:16];
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if (wstrb[1]) mem5[sawaddr5] = wdata[15:08];
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if (wstrb[0]) mem4[sawaddr4] = wdata[07:00];
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end
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3'h5: begin
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if (wstrb[7]) mem4[sawaddr4] = wdata[63:56];
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if (wstrb[6]) mem3[sawaddr3] = wdata[55:48];
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if (wstrb[5]) mem2[sawaddr2] = wdata[47:40];
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if (wstrb[4]) mem1[sawaddr1] = wdata[39:32];
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if (wstrb[3]) mem0[sawaddr0] = wdata[31:24];
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if (wstrb[2]) mem7[sawaddr7] = wdata[23:16];
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if (wstrb[1]) mem6[sawaddr6] = wdata[15:08];
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if (wstrb[0]) mem5[sawaddr5] = wdata[07:00];
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end
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3'h6: begin
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if (wstrb[7]) mem5[sawaddr5] = wdata[63:56];
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if (wstrb[6]) mem4[sawaddr4] = wdata[55:48];
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if (wstrb[5]) mem3[sawaddr3] = wdata[47:40];
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if (wstrb[4]) mem2[sawaddr2] = wdata[39:32];
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if (wstrb[3]) mem1[sawaddr1] = wdata[31:24];
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if (wstrb[2]) mem0[sawaddr0] = wdata[23:16];
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if (wstrb[1]) mem7[sawaddr7] = wdata[15:08];
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if (wstrb[0]) mem6[sawaddr6] = wdata[07:00];
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end
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3'h7: begin
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if (wstrb[7]) mem6[sawaddr6] = wdata[63:56];
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if (wstrb[6]) mem5[sawaddr5] = wdata[55:48];
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if (wstrb[5]) mem4[sawaddr4] = wdata[47:40];
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if (wstrb[4]) mem3[sawaddr3] = wdata[39:32];
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if (wstrb[3]) mem2[sawaddr2] = wdata[31:24];
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if (wstrb[2]) mem1[sawaddr1] = wdata[23:16];
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if (wstrb[1]) mem0[sawaddr0] = wdata[15:08];
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if (wstrb[0]) mem7[sawaddr7] = wdata[07:00];
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end
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endcase
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end
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end
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assign arready = 1'b1;
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assign awready = 1'b1;
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assign wready = 1'b1;
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assign rresp = 2'b0;
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assign bresp = 2'b0;
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assign rlast = 1'b1;
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assign arready = 1'b1;
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assign awready = 1'b1;
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assign wready = 1'b1;
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assign rresp = 2'b0;
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assign bresp = 2'b0;
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assign rlast = 1'b1;
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endmodule
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288
soc/soc_sim.sv
288
soc/soc_sim.sv
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@ -1,36 +1,36 @@
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module soc_sim (
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input bit core_clk
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);
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wire clk_out;
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logic rst_l;
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logic dbg_rst_l;
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wire clk_out;
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logic rst_l;
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logic dbg_rst_l;
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wire jtag_tdo;
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wire jtag_tck;
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wire jtag_tms;
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wire jtag_tdi;
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wire jtag_trst_n;
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wire jtag_tdo;
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wire jtag_tck;
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wire jtag_tms;
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wire jtag_tdi;
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wire jtag_trst_n;
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bit [31:0] cycleCnt;
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logic mailbox_data_val;
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int commit_count;
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bit [31:0] cycleCnt;
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logic mailbox_data_val;
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int commit_count;
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logic wb_valid;
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logic [ 4:0] wb_dest;
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logic [31:0] wb_data;
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logic wb_valid;
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logic [ 4:0] wb_dest;
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logic [31:0] wb_data;
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wire [63:0] WriteData;
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string abi_reg [32]; // ABI register names
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wire [63:0] WriteData;
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string abi_reg [32]; // ABI register names
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assign WriteData = rvsoc.lsu_axi_wdata;
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assign mailbox_data_val = WriteData[7:0] > 8'h5 && WriteData[7:0] < 8'h7f;
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assign WriteData = rvsoc.lsu_axi_wdata;
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assign mailbox_data_val = WriteData[7:0] > 8'h5 && WriteData[7:0] < 8'h7f;
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parameter MAILBOX_ADDR = 32'hD0580000;
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logic write;
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logic [31:0] laddr;
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parameter MAILBOX_ADDR = 32'hD0580000;
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logic write;
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logic [31:0] laddr;
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wire mailbox_write = rvsoc.lmem_axi_awvalid && rvsoc.lsu_axi_awaddr == MAILBOX_ADDR && rst_l;
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always @(posedge core_clk or negedge rst_l) begin
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wire mailbox_write = rvsoc.lmem_axi_awvalid && rvsoc.lsu_axi_awaddr == MAILBOX_ADDR && rst_l;
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always @(posedge core_clk or negedge rst_l) begin
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if (~rst_l) begin
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laddr <= 32'b0;
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write <= 1'b0;
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@ -40,13 +40,13 @@ module soc_sim (
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write <= rvsoc.lsu_hwrite & |rvsoc.lsu_htrans;
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end
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end
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end
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end
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parameter MAX_CYCLES = 10_000_000_0;
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parameter MAX_CYCLES = 10_000_000_0;
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integer fd, tp, el, pic, lsu, ifu, dec, exu;
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integer fd, tp, el, pic, lsu, ifu, dec, exu;
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always @(posedge core_clk) begin
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always @(posedge core_clk) begin
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cycleCnt <= cycleCnt + 1;
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if (cycleCnt == MAX_CYCLES) begin
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@ -61,38 +61,34 @@ module soc_sim (
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$display("\nFinished : minstret = %0d, mcycle = %0d",
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rvsoc.rvtop.core.dec.tlu.csr.minstretl[31:0],
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rvsoc.rvtop.core.dec.tlu.csr.mcyclel[31:0]);
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$display(
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"See \"exec.log\" for execution trace with register updates..\n");
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$display("See \"exec.log\" for execution trace with register updates..\n");
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$display("TEST_PASSED");
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$finish;
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end else if (mailbox_write && WriteData[7:0] == 8'h1) begin
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$display("TEST_FAILED");
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$finish;
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end
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end
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end
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// trace monitor
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always @(posedge core_clk) begin
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// trace monitor
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always @(posedge core_clk) begin
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wb_valid <= rvsoc.rvtop.core.dec.decode_io_dec_i0_wen_r;
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wb_dest <= rvsoc.rvtop.core.dec.decode_io_dec_i0_waddr_r;
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wb_data <= rvsoc.rvtop.core.dec.decode_io_dec_i0_wdata_r;
|
||||
if (rvsoc.trace_rv_i_valid_ip) begin
|
||||
$fwrite(tp, "%b,%h,%h,%0h,%0h,3,%b,%h,%h,%b\n", rvsoc.trace_rv_i_valid_ip,
|
||||
0, rvsoc.trace_rv_i_address_ip, 0, rvsoc.trace_rv_i_insn_ip,
|
||||
rvsoc.trace_rv_i_exception_ip, rvsoc.trace_rv_i_ecause_ip,
|
||||
rvsoc.trace_rv_i_tval_ip, rvsoc.trace_rv_i_interrupt_ip);
|
||||
$fwrite(tp, "%b,%h,%h,%0h,%0h,3,%b,%h,%h,%b\n", rvsoc.trace_rv_i_valid_ip, 0,
|
||||
rvsoc.trace_rv_i_address_ip, 0, rvsoc.trace_rv_i_insn_ip,
|
||||
rvsoc.trace_rv_i_exception_ip, rvsoc.trace_rv_i_ecause_ip, rvsoc.trace_rv_i_tval_ip,
|
||||
rvsoc.trace_rv_i_interrupt_ip);
|
||||
// Basic trace - no exception register updates
|
||||
// #1 0 ee000000 b0201073 c 0b02 00000000
|
||||
commit_count++;
|
||||
$fwrite(el, "%10d : %8s 0 %h %h%13s ; %s\n", cycleCnt, $sformatf(
|
||||
"#%0d", commit_count), rvsoc.trace_rv_i_address_ip,
|
||||
rvsoc.trace_rv_i_insn_ip, (wb_dest != 0 && wb_valid) ? $sformatf(
|
||||
"%s=%h", abi_reg[wb_dest], wb_data) : " ", dasm(
|
||||
rvsoc.trace_rv_i_insn_ip,
|
||||
rvsoc.trace_rv_i_address_ip,
|
||||
wb_dest & {5{wb_valid}},
|
||||
wb_data
|
||||
));
|
||||
$fwrite(
|
||||
el, "%10d : %8s 0 %h %h%13s ; %s\n", cycleCnt, $sformatf("#%0d", commit_count),
|
||||
rvsoc.trace_rv_i_address_ip, rvsoc.trace_rv_i_insn_ip,
|
||||
(wb_dest != 0 && wb_valid) ? $sformatf("%s=%h", abi_reg[wb_dest], wb_data
|
||||
) : " ", dasm(
|
||||
rvsoc.trace_rv_i_insn_ip, rvsoc.trace_rv_i_address_ip, wb_dest & {5{wb_valid}}, wb_data));
|
||||
end
|
||||
if (rvsoc.rvtop.core.dec.decode_io_dec_nonblock_load_wen)
|
||||
$fwrite(el, "%10d : %32s=%h ; nbL\n", cycleCnt,
|
||||
|
|
@ -102,15 +98,14 @@ module soc_sim (
|
|||
$fwrite(el, "%10d : %32s=%h ; nbD\n", cycleCnt,
|
||||
abi_reg[rvsoc.rvtop.core.dec.decode_io_div_waddr_wb],
|
||||
rvsoc.rvtop.core.dec.io_exu_div_result);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//////////////////////////////////////////////////pic tracer///////////////////////////////////////////////////////
|
||||
always @(posedge core_clk) begin
|
||||
//////////////////////////////////////////////////pic tracer///////////////////////////////////////////////////////
|
||||
always @(posedge core_clk) begin
|
||||
|
||||
if (rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_wren == 1) begin
|
||||
$fwrite(pic, "%0d,%0d,%h\t",
|
||||
rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_wren,
|
||||
$fwrite(pic, "%0d,%0d,%h\t", rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_wren,
|
||||
rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_wraddr,
|
||||
rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_wr_data);
|
||||
|
||||
|
|
@ -118,51 +113,44 @@ module soc_sim (
|
|||
$fwrite(pic, "x\tx\tx\t");
|
||||
|
||||
if (rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_rden == 1) begin
|
||||
$fwrite(pic, "%0d,%0d,%h\n",
|
||||
rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_rden,
|
||||
$fwrite(pic, "%0d,%0d,%h\n", rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_rden,
|
||||
rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_rdaddr,
|
||||
rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_rd_data);
|
||||
|
||||
end else if (rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_wren == 1)
|
||||
$fwrite(pic, "x\tx\tx\t\n");
|
||||
end
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////LSU tracer///////////////////////////////////////////////////////
|
||||
always @(posedge core_clk) begin
|
||||
end
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////LSU tracer///////////////////////////////////////////////////////
|
||||
always @(posedge core_clk) begin
|
||||
|
||||
if (rvsoc.rvtop.core.lsu.io_dccm_wren == 1) begin
|
||||
$fwrite(lsu, "%0h,%0h,%0h,%0h,%0h\t", rvsoc.rvtop.core.lsu.io_dccm_wren,
|
||||
rvsoc.rvtop.core.lsu.io_dccm_wr_addr_hi,
|
||||
rvsoc.rvtop.core.lsu.io_dccm_wr_addr_lo,
|
||||
rvsoc.rvtop.core.lsu.io_dccm_wr_data_hi,
|
||||
rvsoc.rvtop.core.lsu.io_dccm_wr_data_lo);
|
||||
rvsoc.rvtop.core.lsu.io_dccm_wr_addr_hi, rvsoc.rvtop.core.lsu.io_dccm_wr_addr_lo,
|
||||
rvsoc.rvtop.core.lsu.io_dccm_wr_data_hi, rvsoc.rvtop.core.lsu.io_dccm_wr_data_lo);
|
||||
|
||||
end
|
||||
else if(rvsoc.rvtop.core.lsu.io_dccm_rden == 1 || rvsoc.rvtop.core.lsu.io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid)
|
||||
else if(rvsoc.rvtop.core.lsu.io_dccm_rden == 1 || rvsoc.rvtop.core.lsu.io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid)
|
||||
$fwrite(lsu, "x\tx\tx\tx\tx\t");
|
||||
|
||||
if (rvsoc.rvtop.core.lsu.io_dccm_rden == 1) begin
|
||||
$fwrite(lsu, "%0h,%0h,%0h,%0h,%0h\t", rvsoc.rvtop.core.lsu.io_dccm_rden,
|
||||
rvsoc.rvtop.core.lsu.io_dccm_rd_addr_hi,
|
||||
rvsoc.rvtop.core.lsu.io_dccm_rd_addr_lo,
|
||||
rvsoc.rvtop.core.lsu.io_dccm_rd_data_hi,
|
||||
rvsoc.rvtop.core.lsu.io_dccm_rd_data_lo);
|
||||
rvsoc.rvtop.core.lsu.io_dccm_rd_addr_hi, rvsoc.rvtop.core.lsu.io_dccm_rd_addr_lo,
|
||||
rvsoc.rvtop.core.lsu.io_dccm_rd_data_hi, rvsoc.rvtop.core.lsu.io_dccm_rd_data_lo);
|
||||
|
||||
end
|
||||
else if(rvsoc.rvtop.core.lsu.io_dccm_wren == 1 || rvsoc.rvtop.core.lsu.io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid)
|
||||
else if(rvsoc.rvtop.core.lsu.io_dccm_wren == 1 || rvsoc.rvtop.core.lsu.io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid)
|
||||
$fwrite(lsu, "x\tx\tx\tx\tx\t");
|
||||
|
||||
if (rvsoc.rvtop.core.lsu.io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid == 1) begin
|
||||
$fwrite(lsu, "%0h,%0h\n",
|
||||
rvsoc.rvtop.core.lsu.io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid,
|
||||
$fwrite(lsu, "%0h,%0h\n", rvsoc.rvtop.core.lsu.io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid,
|
||||
rvsoc.rvtop.core.lsu.io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata);
|
||||
end
|
||||
else if (rvsoc.rvtop.core.lsu.io_dccm_wren == 1 || rvsoc.rvtop.core.lsu.io_dccm_rden== 1)
|
||||
end else if (rvsoc.rvtop.core.lsu.io_dccm_wren == 1 || rvsoc.rvtop.core.lsu.io_dccm_rden == 1)
|
||||
$fwrite(lsu, "x\tx\n");
|
||||
end
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////IFU tracer////////////////////////////////////////////////////////
|
||||
always @(posedge core_clk) begin
|
||||
end
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////IFU tracer////////////////////////////////////////////////////////
|
||||
always @(posedge core_clk) begin
|
||||
|
||||
if (rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 && cycleCnt != 0) begin
|
||||
$fwrite(ifu, "%5d,%0h,%0h,%0h\t", cycleCnt,
|
||||
|
|
@ -171,44 +159,40 @@ module soc_sim (
|
|||
rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc);
|
||||
end
|
||||
|
||||
else if((rvsoc.rvtop.core.ifu.io_iccm_wren == 1 || rvsoc.rvtop.core.ifu.io_iccm_rden==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !==0 || rvsoc.rvtop.core.ifu.io_ic_rd_en ==1 || rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1) && cycleCnt != 0)
|
||||
else if((rvsoc.rvtop.core.ifu.io_iccm_wren == 1 || rvsoc.rvtop.core.ifu.io_iccm_rden==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !==0 || rvsoc.rvtop.core.ifu.io_ic_rd_en ==1 || rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1) && cycleCnt != 0)
|
||||
$fwrite(ifu, "%5d,x\tx\tx\t", cycleCnt);
|
||||
|
||||
if (rvsoc.rvtop.core.ifu.io_iccm_wren == 1 && cycleCnt != 0) begin
|
||||
$fwrite(ifu, "%0h,%0h,%0h\t", rvsoc.rvtop.core.ifu.io_iccm_wren,
|
||||
rvsoc.rvtop.core.ifu.io_iccm_rw_addr,
|
||||
rvsoc.rvtop.core.ifu.io_iccm_wr_data);
|
||||
rvsoc.rvtop.core.ifu.io_iccm_rw_addr, rvsoc.rvtop.core.ifu.io_iccm_wr_data);
|
||||
end
|
||||
|
||||
else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_rden==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !==0 || rvsoc.rvtop.core.ifu.io_ic_rd_en ==1 || rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1) && cycleCnt != 0)
|
||||
else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_rden==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !==0 || rvsoc.rvtop.core.ifu.io_ic_rd_en ==1 || rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1) && cycleCnt != 0)
|
||||
$fwrite(ifu, "\tx\tx\tx\t");
|
||||
|
||||
if (rvsoc.rvtop.core.ifu.io_iccm_rden == 1 && cycleCnt != 0) begin
|
||||
$fwrite(ifu, "%0h,%0h,%0h\t", rvsoc.rvtop.core.ifu.io_iccm_rden,
|
||||
rvsoc.rvtop.core.ifu.io_iccm_rw_addr,
|
||||
rvsoc.rvtop.core.ifu.io_iccm_rd_data_ecc);
|
||||
rvsoc.rvtop.core.ifu.io_iccm_rw_addr, rvsoc.rvtop.core.ifu.io_iccm_rd_data_ecc);
|
||||
end
|
||||
|
||||
else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_wren==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !==0 || rvsoc.rvtop.core.ifu.io_ic_rd_en ==1 || rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1)&& cycleCnt != 0)
|
||||
else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_wren==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !==0 || rvsoc.rvtop.core.ifu.io_ic_rd_en ==1 || rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1)&& cycleCnt != 0)
|
||||
$fwrite(ifu, "\tx\tx\tx\t");
|
||||
|
||||
if (rvsoc.rvtop.core.ifu.io_ic_wr_en !== 0 && cycleCnt != 0) begin
|
||||
$fwrite(ifu, "%0h,%0h,%0h\t", rvsoc.rvtop.core.ifu.io_ic_wr_en,
|
||||
rvsoc.rvtop.core.ifu.io_ic_rw_addr,
|
||||
rvsoc.rvtop.core.ifu.io_ic_wr_data_0,
|
||||
rvsoc.rvtop.core.ifu.io_ic_rw_addr, rvsoc.rvtop.core.ifu.io_ic_wr_data_0,
|
||||
rvsoc.rvtop.core.ifu.io_ic_wr_data_1);
|
||||
end
|
||||
|
||||
else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_wren==1 || rvsoc.rvtop.core.ifu.io_iccm_rden ==1 || rvsoc.rvtop.core.ifu.io_ic_rd_en ==1 || rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1)&& cycleCnt != 0)
|
||||
else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_wren==1 || rvsoc.rvtop.core.ifu.io_iccm_rden ==1 || rvsoc.rvtop.core.ifu.io_ic_rd_en ==1 || rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1)&& cycleCnt != 0)
|
||||
$fwrite(ifu, "\tx\tx\tx\tx\t");
|
||||
|
||||
if (rvsoc.rvtop.core.ifu.io_ic_rd_en == 1 && cycleCnt != 0) begin
|
||||
$fwrite(ifu, "%0h,%0h,%0h\t", rvsoc.rvtop.core.ifu.io_ic_rd_en,
|
||||
rvsoc.rvtop.core.ifu.io_ic_rw_addr,
|
||||
rvsoc.rvtop.core.ifu.io_ic_rd_data);
|
||||
rvsoc.rvtop.core.ifu.io_ic_rw_addr, rvsoc.rvtop.core.ifu.io_ic_rd_data);
|
||||
end
|
||||
|
||||
else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_wren==1 || rvsoc.rvtop.core.ifu.io_iccm_rden ==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !== 0 ||rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1)&& cycleCnt != 0)
|
||||
else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_wren==1 || rvsoc.rvtop.core.ifu.io_iccm_rden ==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !== 0 ||rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1)&& cycleCnt != 0)
|
||||
$fwrite(ifu, "\tx\tx\tx\t");
|
||||
|
||||
if (rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1 && cycleCnt != 0) begin
|
||||
|
|
@ -216,62 +200,56 @@ module soc_sim (
|
|||
rvsoc.rvtop.core.ifu.io_iccm_dma_rdata);
|
||||
end
|
||||
|
||||
else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_wren==1 || rvsoc.rvtop.core.ifu.io_iccm_rden ==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !== 0 || rvsoc.rvtop.core.ifu.io_ic_rd_en)&& cycleCnt != 0)
|
||||
else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_wren==1 || rvsoc.rvtop.core.ifu.io_iccm_rden ==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !== 0 || rvsoc.rvtop.core.ifu.io_ic_rd_en)&& cycleCnt != 0)
|
||||
$fwrite(ifu, "\tx\tx\n");
|
||||
end
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////DEC tracer////////////////////////////////////////////////////////
|
||||
always @(posedge core_clk) begin
|
||||
end
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////DEC tracer////////////////////////////////////////////////////////
|
||||
always @(posedge core_clk) begin
|
||||
|
||||
if (rvsoc.rvtop.core.dma_ctrl.io_dma_dbg_cmd_done == 1) begin
|
||||
$fwrite(dec, "%5d,\t%0h,%0h\t", cycleCnt,
|
||||
rvsoc.rvtop.core.dma_ctrl.io_dma_dbg_cmd_done,
|
||||
$fwrite(dec, "%5d,\t%0h,%0h\t", cycleCnt, rvsoc.rvtop.core.dma_ctrl.io_dma_dbg_cmd_done,
|
||||
rvsoc.rvtop.core.dec.io_dec_dbg_rddata);
|
||||
end
|
||||
|
||||
else if(rvsoc.rvtop.core.dec.io_dec_exu_dec_alu_dec_i0_alu_decode_d == 1 || rvsoc.rvtop.core.dec.decode_io_dec_csr_wen_r==1)
|
||||
else if(rvsoc.rvtop.core.dec.io_dec_exu_dec_alu_dec_i0_alu_decode_d == 1 || rvsoc.rvtop.core.dec.decode_io_dec_csr_wen_r==1)
|
||||
$fwrite(dec, "%5d,\tx\tx\t", cycleCnt);
|
||||
|
||||
if (rvsoc.rvtop.core.dec.io_dec_exu_dec_alu_dec_i0_alu_decode_d == 1) begin
|
||||
$fwrite(dec, "%0h,%0h,%0h,%0h,%0h,%0h\t",
|
||||
$fwrite(
|
||||
dec, "%0h,%0h,%0h,%0h,%0h,%0h\t",
|
||||
rvsoc.rvtop.core.dec.io_dec_exu_dec_alu_dec_i0_alu_decode_d,
|
||||
rvsoc.rvtop.core.dec.decode_io_decode_exu_dec_i0_rs1_en_d,
|
||||
rvsoc.rvtop.core.exu.i0_rs1_d,
|
||||
rvsoc.rvtop.core.dec.decode_io_decode_exu_dec_i0_rs2_en_d,
|
||||
rvsoc.rvtop.core.exu.i0_rs2_d,
|
||||
rvsoc.rvtop.core.dec.decode_io_decode_exu_dec_i0_rs1_en_d, rvsoc.rvtop.core.exu.i0_rs1_d,
|
||||
rvsoc.rvtop.core.dec.decode_io_decode_exu_dec_i0_rs2_en_d, rvsoc.rvtop.core.exu.i0_rs2_d,
|
||||
rvsoc.rvtop.core.exu.io_dec_exu_decode_exu_exu_i0_result_x);
|
||||
end
|
||||
|
||||
else if(rvsoc.rvtop.core.dma_ctrl.io_dma_dbg_cmd_done == 1 || rvsoc.rvtop.core.dec.decode_io_dec_csr_wen_r==1)
|
||||
else if(rvsoc.rvtop.core.dma_ctrl.io_dma_dbg_cmd_done == 1 || rvsoc.rvtop.core.dec.decode_io_dec_csr_wen_r==1)
|
||||
$fwrite(dec, "x\t,x\t,x\t,x\tx\tx\t");
|
||||
|
||||
if (rvsoc.rvtop.core.dec.decode_io_dec_csr_wen_r == 1) begin
|
||||
$fwrite(dec, "%0h,%0h,%0h,%0h,%0h\n",
|
||||
rvsoc.rvtop.core.dec.decode_io_dec_csr_wen_r,
|
||||
$fwrite(dec, "%0h,%0h,%0h,%0h,%0h\n", rvsoc.rvtop.core.dec.decode_io_dec_csr_wen_r,
|
||||
rvsoc.rvtop.core.dec.decode_io_dec_csr_wraddr_r,
|
||||
rvsoc.rvtop.core.dec.decode_io_dec_csr_wrdata_r,
|
||||
rvsoc.rvtop.core.dec.decode_io_dec_csr_rdaddr_d,
|
||||
rvsoc.rvtop.core.dec.decode_io_dec_csr_rddata_d);
|
||||
end
|
||||
|
||||
else if(rvsoc.rvtop.core.dma_ctrl.io_dma_dbg_cmd_done == 1 || rvsoc.rvtop.core.dec.io_dec_exu_dec_alu_dec_i0_alu_decode_d == 1 )
|
||||
else if(rvsoc.rvtop.core.dma_ctrl.io_dma_dbg_cmd_done == 1 || rvsoc.rvtop.core.dec.io_dec_exu_dec_alu_dec_i0_alu_decode_d == 1 )
|
||||
$fwrite(dec, "x\t,x\t,x\t,x\t,x\n");
|
||||
|
||||
end
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////////////////////////exu tracer///////////////////////////////////////////////////
|
||||
always @(posedge core_clk) begin
|
||||
end
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////////////////////////exu tracer///////////////////////////////////////////////////
|
||||
always @(posedge core_clk) begin
|
||||
|
||||
if (rvsoc.rvtop.core.exu.io_exu_div_wren == 1) begin
|
||||
$fwrite(exu, "%5d,\t%0h,%0h,%0h,%0h,%0h\t", cycleCnt,
|
||||
rvsoc.rvtop.core.exu.io_exu_div_wren,
|
||||
rvsoc.rvtop.core.exu.io_exu_div_result,
|
||||
rvsoc.rvtop.core.exu.i_div.io_dividend,
|
||||
rvsoc.rvtop.core.exu.i_div.io_divisor,
|
||||
rvsoc.rvtop.core.exu.i_div.io_exu_div_result);
|
||||
$fwrite(exu, "%5d,\t%0h,%0h,%0h,%0h,%0h\t", cycleCnt, rvsoc.rvtop.core.exu.io_exu_div_wren,
|
||||
rvsoc.rvtop.core.exu.io_exu_div_result, rvsoc.rvtop.core.exu.i_div.io_dividend,
|
||||
rvsoc.rvtop.core.exu.i_div.io_divisor, rvsoc.rvtop.core.exu.i_div.io_exu_div_result);
|
||||
end
|
||||
|
||||
else if(rvsoc.rvtop.core.exu.i0_rs1_bypass_en_d == 1 || rvsoc.rvtop.core.exu.i0_rs2_bypass_en_d == 1)
|
||||
else if(rvsoc.rvtop.core.exu.i0_rs1_bypass_en_d == 1 || rvsoc.rvtop.core.exu.i0_rs2_bypass_en_d == 1)
|
||||
$fwrite(exu, "%5d,\tx\tx\tx\tx\tx,\t", cycleCnt);
|
||||
|
||||
if (rvsoc.rvtop.core.exu.i0_rs1_bypass_en_d == 1) begin
|
||||
|
|
@ -279,7 +257,7 @@ module soc_sim (
|
|||
rvsoc.rvtop.core.exu.i0_rs1_bypass_data_d);
|
||||
end
|
||||
|
||||
else if(rvsoc.rvtop.core.exu.io_exu_div_wren == 1 || rvsoc.rvtop.core.exu.i0_rs2_bypass_en_d == 1)
|
||||
else if(rvsoc.rvtop.core.exu.io_exu_div_wren == 1 || rvsoc.rvtop.core.exu.i0_rs2_bypass_en_d == 1)
|
||||
$fwrite(exu, "\tx\tx\t");
|
||||
|
||||
if (rvsoc.rvtop.core.exu.i0_rs2_bypass_en_d == 1) begin
|
||||
|
|
@ -287,13 +265,14 @@ module soc_sim (
|
|||
rvsoc.rvtop.core.exu.i0_rs2_bypass_data_d);
|
||||
end
|
||||
|
||||
else if(rvsoc.rvtop.core.exu.io_exu_div_wren == 1 || rvsoc.rvtop.core.exu.i0_rs1_bypass_en_d == 1)
|
||||
else if(rvsoc.rvtop.core.exu.io_exu_div_wren == 1 || rvsoc.rvtop.core.exu.i0_rs1_bypass_en_d == 1)
|
||||
$fwrite(exu, "\tx\tx\n");
|
||||
end
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
end
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
reg [7:0] hex[(1<<rvsoc.imem.MEM_DEPTH)-1:0];
|
||||
|
||||
initial begin
|
||||
initial begin
|
||||
abi_reg[0] = "zero";
|
||||
abi_reg[1] = "ra";
|
||||
abi_reg[2] = "sp";
|
||||
|
|
@ -327,15 +306,38 @@ module soc_sim (
|
|||
abi_reg[30] = "t5";
|
||||
abi_reg[31] = "t6";
|
||||
|
||||
$readmemh("program.hex", rvsoc.lmem.mem);
|
||||
$readmemh("program.hex", rvsoc.imem.mem);
|
||||
|
||||
$readmemh("program.hex", hex);
|
||||
for (
|
||||
reg [rvsoc.imem.MEM_DEPTH-1:0] i = 0; i < (1 << (rvsoc.imem.MEM_DEPTH - 3)); i++
|
||||
) begin
|
||||
rvsoc.imem.mem0[i] = hex[(i<<3)+0];
|
||||
rvsoc.imem.mem1[i] = hex[(i<<3)+1];
|
||||
rvsoc.imem.mem2[i] = hex[(i<<3)+2];
|
||||
rvsoc.imem.mem3[i] = hex[(i<<3)+3];
|
||||
rvsoc.imem.mem4[i] = hex[(i<<3)+4];
|
||||
rvsoc.imem.mem5[i] = hex[(i<<3)+5];
|
||||
rvsoc.imem.mem6[i] = hex[(i<<3)+6];
|
||||
rvsoc.imem.mem7[i] = hex[(i<<3)+7];
|
||||
end
|
||||
for (
|
||||
reg [rvsoc.lmem.MEM_DEPTH-1:0] i = 0; i < (1 << (rvsoc.lmem.MEM_DEPTH - 3)); i++
|
||||
) begin
|
||||
rvsoc.lmem.mem0[i] = hex[(i<<3)+0];
|
||||
rvsoc.lmem.mem1[i] = hex[(i<<3)+1];
|
||||
rvsoc.lmem.mem2[i] = hex[(i<<3)+2];
|
||||
rvsoc.lmem.mem3[i] = hex[(i<<3)+3];
|
||||
rvsoc.lmem.mem4[i] = hex[(i<<3)+4];
|
||||
rvsoc.lmem.mem5[i] = hex[(i<<3)+5];
|
||||
rvsoc.lmem.mem6[i] = hex[(i<<3)+6];
|
||||
rvsoc.lmem.mem7[i] = hex[(i<<3)+7];
|
||||
end
|
||||
|
||||
tp = $fopen("trace_port.csv", "w");
|
||||
el = $fopen("exec.log", "w");
|
||||
//////////////////////////////////////////////////////////////////
|
||||
pic = $fopen("pic.log", "w");
|
||||
$fwrite(pic,
|
||||
" write enable, write addr , write data ,read enable, read address, read data \n");
|
||||
$fwrite(pic, " write enable, write addr , write data ,read enable, read address, read data \n");
|
||||
///////////////////////////////////////////////////////////////////
|
||||
lsu = $fopen("lsu.log", "w");
|
||||
$fwrite(lsu,
|
||||
|
|
@ -356,12 +358,12 @@ module soc_sim (
|
|||
fd = $fopen("console.log", "w");
|
||||
commit_count = 0;
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
assign rst_l = cycleCnt > 5;
|
||||
assign dbg_rst_l = cycleCnt > 2;
|
||||
assign rst_l = cycleCnt > 5;
|
||||
assign dbg_rst_l = cycleCnt > 2;
|
||||
|
||||
soc_top rvsoc (
|
||||
soc_top rvsoc (
|
||||
.clk(core_clk),
|
||||
.clk_o(clk_out),
|
||||
.rst(rst_l),
|
||||
|
|
@ -372,9 +374,9 @@ module soc_sim (
|
|||
.jtag_tms(jtag_tms),
|
||||
.jtag_tdi(jtag_tdi),
|
||||
.jtag_trst_n(jtag_trst_n)
|
||||
);
|
||||
);
|
||||
|
||||
jtagdpi jtagdpi (
|
||||
jtagdpi jtagdpi (
|
||||
.clk_i (core_clk),
|
||||
.rst_ni(rst_l),
|
||||
|
||||
|
|
@ -384,21 +386,21 @@ module soc_sim (
|
|||
.jtag_tdo(jtag_tdo),
|
||||
.jtag_trst_n(jtag_trst_n),
|
||||
.jtag_srst_n()
|
||||
);
|
||||
);
|
||||
|
||||
`define DRAM(bank) \
|
||||
rvsoc.rvtop.mem.Gen_dccm_enable.dccm.mem_bank[bank].dccm_bank.ram_core
|
||||
`define DRAM(bank) \
|
||||
rvsoc.rvtop.mem.Gen_dccm_enable.dccm.mem_bank[bank].dccm_bank.ram_core
|
||||
|
||||
`define ICCM_PATH `RV_TOP.mem.iccm
|
||||
`define IRAM0(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_lo0.ram_core
|
||||
`define IRAM1(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_lo1.ram_core
|
||||
`define IRAM2(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_hi0.ram_core
|
||||
`define IRAM3(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_hi1.ram_core
|
||||
`define ICCM_PATH `RV_TOP.mem.iccm
|
||||
`define IRAM0(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_lo0.ram_core
|
||||
`define IRAM1(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_lo1.ram_core
|
||||
`define IRAM2(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_hi0.ram_core
|
||||
`define IRAM3(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_hi1.ram_core
|
||||
|
||||
/* verilator lint_off WIDTH */
|
||||
/* verilator lint_off CASEINCOMPLETE */
|
||||
`include "dasm.svi"
|
||||
/* verilator lint_on CASEINCOMPLETE */
|
||||
/* verilator lint_on WIDTH */
|
||||
/* verilator lint_off WIDTH */
|
||||
/* verilator lint_off CASEINCOMPLETE */
|
||||
`include "dasm.svi"
|
||||
/* verilator lint_on CASEINCOMPLETE */
|
||||
/* verilator lint_on WIDTH */
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Reference in New Issue