AHB/AXI added
This commit is contained in:
Laraib Khan
parent
be9a487ba1
commit
d9dc8848f9
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@ -0,0 +1,34 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ahb_to_axi4|ahb_to_axi4>io_ahb_sig_in_hready",
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"sources":[
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"~ahb_to_axi4|ahb_to_axi4>io_ahb_sig_in_hresp",
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"~ahb_to_axi4|ahb_to_axi4>io_axi_aw_valid",
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"~ahb_to_axi4|ahb_to_axi4>io_axi_aw_ready",
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"~ahb_to_axi4|ahb_to_axi4>io_axi_ar_valid",
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"~ahb_to_axi4|ahb_to_axi4>io_axi_ar_ready"
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"ahb_to_axi4.gated_latch",
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"resourceId":"/vsrc/gated_latch.sv"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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},
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{
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"class":"firrtl.options.OutputAnnotationFileAnnotation",
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"file":"ahb_to_axi4"
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},
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{
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"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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"targetDir":"."
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}
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]
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit ahb_to_axi4 :
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extmodule gated_latch :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_1 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_1 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_1 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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module ahb_to_axi4 :
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input clock : Clock
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input reset : AsyncReset
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output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}}
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wire _T : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[ahb_to_axi4.scala 20:25]
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_T.r.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.r.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25]
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_T.r.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25]
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_T.r.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.r.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.r.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.ar.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.b.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.b.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25]
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_T.b.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.b.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.w.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.w.bits.strb <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25]
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_T.w.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25]
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_T.w.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.w.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.aw.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
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_T.r.bits.last <= io.axi.r.bits.last @[ahb_to_axi4.scala 20:10]
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_T.r.bits.resp <= io.axi.r.bits.resp @[ahb_to_axi4.scala 20:10]
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_T.r.bits.data <= io.axi.r.bits.data @[ahb_to_axi4.scala 20:10]
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_T.r.bits.id <= io.axi.r.bits.id @[ahb_to_axi4.scala 20:10]
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_T.r.valid <= io.axi.r.valid @[ahb_to_axi4.scala 20:10]
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io.axi.r.ready <= _T.r.ready @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.qos <= _T.ar.bits.qos @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.prot <= _T.ar.bits.prot @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.cache <= _T.ar.bits.cache @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.lock <= _T.ar.bits.lock @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.burst <= _T.ar.bits.burst @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.size <= _T.ar.bits.size @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.len <= _T.ar.bits.len @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.region <= _T.ar.bits.region @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.addr <= _T.ar.bits.addr @[ahb_to_axi4.scala 20:10]
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io.axi.ar.bits.id <= _T.ar.bits.id @[ahb_to_axi4.scala 20:10]
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io.axi.ar.valid <= _T.ar.valid @[ahb_to_axi4.scala 20:10]
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_T.ar.ready <= io.axi.ar.ready @[ahb_to_axi4.scala 20:10]
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_T.b.bits.id <= io.axi.b.bits.id @[ahb_to_axi4.scala 20:10]
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_T.b.bits.resp <= io.axi.b.bits.resp @[ahb_to_axi4.scala 20:10]
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_T.b.valid <= io.axi.b.valid @[ahb_to_axi4.scala 20:10]
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io.axi.b.ready <= _T.b.ready @[ahb_to_axi4.scala 20:10]
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io.axi.w.bits.last <= _T.w.bits.last @[ahb_to_axi4.scala 20:10]
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io.axi.w.bits.strb <= _T.w.bits.strb @[ahb_to_axi4.scala 20:10]
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io.axi.w.bits.data <= _T.w.bits.data @[ahb_to_axi4.scala 20:10]
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io.axi.w.valid <= _T.w.valid @[ahb_to_axi4.scala 20:10]
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_T.w.ready <= io.axi.w.ready @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.qos <= _T.aw.bits.qos @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.prot <= _T.aw.bits.prot @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.cache <= _T.aw.bits.cache @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.lock <= _T.aw.bits.lock @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.burst <= _T.aw.bits.burst @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.size <= _T.aw.bits.size @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.len <= _T.aw.bits.len @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.region <= _T.aw.bits.region @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.addr <= _T.aw.bits.addr @[ahb_to_axi4.scala 20:10]
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io.axi.aw.bits.id <= _T.aw.bits.id @[ahb_to_axi4.scala 20:10]
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io.axi.aw.valid <= _T.aw.valid @[ahb_to_axi4.scala 20:10]
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_T.aw.ready <= io.axi.aw.ready @[ahb_to_axi4.scala 20:10]
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wire master_wstrb : UInt<8>
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master_wstrb <= UInt<8>("h00")
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wire buf_state_en : UInt<1>
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buf_state_en <= UInt<1>("h00")
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wire buf_read_error_in : UInt<1>
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buf_read_error_in <= UInt<1>("h00")
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wire buf_read_error : UInt<1>
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buf_read_error <= UInt<1>("h00")
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wire buf_rdata : UInt<64>
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buf_rdata <= UInt<64>("h00")
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wire ahb_hready : UInt<1>
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ahb_hready <= UInt<1>("h00")
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wire ahb_hready_q : UInt<1>
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ahb_hready_q <= UInt<1>("h00")
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wire ahb_htrans_in : UInt<2>
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ahb_htrans_in <= UInt<2>("h00")
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wire ahb_htrans_q : UInt<2>
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ahb_htrans_q <= UInt<2>("h00")
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wire ahb_hsize_q : UInt<3>
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ahb_hsize_q <= UInt<3>("h00")
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wire ahb_hwrite_q : UInt<1>
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ahb_hwrite_q <= UInt<1>("h00")
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wire ahb_haddr_q : UInt<32>
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ahb_haddr_q <= UInt<32>("h00")
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wire ahb_hwdata_q : UInt<64>
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ahb_hwdata_q <= UInt<64>("h00")
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wire ahb_hresp_q : UInt<1>
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ahb_hresp_q <= UInt<1>("h00")
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wire buf_rdata_en : UInt<1>
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buf_rdata_en <= UInt<1>("h00")
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wire ahb_addr_clk_en : UInt<1>
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ahb_addr_clk_en <= UInt<1>("h00")
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wire buf_rdata_clk_en : UInt<1>
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buf_rdata_clk_en <= UInt<1>("h00")
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wire bus_clk : Clock @[ahb_to_axi4.scala 43:33]
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wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 44:33]
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wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 45:33]
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wire cmdbuf_wr_en : UInt<1>
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cmdbuf_wr_en <= UInt<1>("h00")
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wire cmdbuf_rst : UInt<1>
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cmdbuf_rst <= UInt<1>("h00")
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wire cmdbuf_full : UInt<1>
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cmdbuf_full <= UInt<1>("h00")
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wire cmdbuf_vld : UInt<1>
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cmdbuf_vld <= UInt<1>("h00")
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wire cmdbuf_write : UInt<1>
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cmdbuf_write <= UInt<1>("h00")
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wire cmdbuf_size : UInt<2>
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cmdbuf_size <= UInt<2>("h00")
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wire cmdbuf_wstrb : UInt<8>
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cmdbuf_wstrb <= UInt<8>("h00")
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wire cmdbuf_addr : UInt<32>
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cmdbuf_addr <= UInt<32>("h00")
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wire cmdbuf_wdata : UInt<64>
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cmdbuf_wdata <= UInt<64>("h00")
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node _T_1 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25]
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node ahb_addr_in_dccm_region_nc = eq(_T_1, UInt<4>("h0f")) @[lib.scala 84:47]
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node _T_2 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14]
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node ahb_addr_in_dccm = eq(_T_2, UInt<16>("h0f004")) @[lib.scala 87:29]
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node _T_3 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25]
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node ahb_addr_in_iccm_region_nc = eq(_T_3, UInt<4>("h0e")) @[lib.scala 84:47]
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node _T_4 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14]
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node ahb_addr_in_iccm = eq(_T_4, UInt<16>("h0ee00")) @[lib.scala 87:29]
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node _T_5 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25]
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node ahb_addr_in_pic_region_nc = eq(_T_5, UInt<4>("h0f")) @[lib.scala 84:47]
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node _T_6 = bits(ahb_haddr_q, 31, 15) @[lib.scala 87:14]
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node ahb_addr_in_pic = eq(_T_6, UInt<17>("h01e018")) @[lib.scala 87:29]
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wire buf_state : UInt<2>
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buf_state <= UInt<2>("h00")
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wire buf_nxtstate : UInt<2>
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buf_nxtstate <= UInt<2>("h00")
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buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 66:31]
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buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 67:31]
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buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 68:31]
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buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 69:31]
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cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 70:31]
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node _T_7 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30]
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when _T_7 : @[Conditional.scala 40:58]
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node _T_8 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 74:26]
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buf_nxtstate <= _T_8 @[ahb_to_axi4.scala 74:20]
|
||||
node _T_9 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 75:57]
|
||||
node _T_10 = and(ahb_hready, _T_9) @[ahb_to_axi4.scala 75:34]
|
||||
node _T_11 = and(_T_10, io.ahb.hsel) @[ahb_to_axi4.scala 75:61]
|
||||
buf_state_en <= _T_11 @[ahb_to_axi4.scala 75:20]
|
||||
skip @[Conditional.scala 40:58]
|
||||
else : @[Conditional.scala 39:67]
|
||||
node _T_12 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30]
|
||||
when _T_12 : @[Conditional.scala 39:67]
|
||||
node _T_13 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 78:72]
|
||||
node _T_14 = eq(_T_13, UInt<1>("h00")) @[ahb_to_axi4.scala 78:79]
|
||||
node _T_15 = or(io.ahb.sig.in.hresp, _T_14) @[ahb_to_axi4.scala 78:48]
|
||||
node _T_16 = eq(io.ahb.hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 78:93]
|
||||
node _T_17 = or(_T_15, _T_16) @[ahb_to_axi4.scala 78:91]
|
||||
node _T_18 = bits(_T_17, 0, 0) @[ahb_to_axi4.scala 78:107]
|
||||
node _T_19 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 78:124]
|
||||
node _T_20 = mux(_T_18, UInt<2>("h00"), _T_19) @[ahb_to_axi4.scala 78:26]
|
||||
buf_nxtstate <= _T_20 @[ahb_to_axi4.scala 78:20]
|
||||
node _T_21 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 79:24]
|
||||
node _T_22 = or(_T_21, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 79:37]
|
||||
buf_state_en <= _T_22 @[ahb_to_axi4.scala 79:20]
|
||||
node _T_23 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 80:23]
|
||||
node _T_24 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 80:85]
|
||||
node _T_25 = eq(_T_24, UInt<2>("h01")) @[ahb_to_axi4.scala 80:92]
|
||||
node _T_26 = and(_T_25, io.ahb.hsel) @[ahb_to_axi4.scala 80:110]
|
||||
node _T_27 = or(io.ahb.sig.in.hresp, _T_26) @[ahb_to_axi4.scala 80:60]
|
||||
node _T_28 = eq(_T_27, UInt<1>("h00")) @[ahb_to_axi4.scala 80:38]
|
||||
node _T_29 = and(_T_23, _T_28) @[ahb_to_axi4.scala 80:36]
|
||||
cmdbuf_wr_en <= _T_29 @[ahb_to_axi4.scala 80:20]
|
||||
skip @[Conditional.scala 39:67]
|
||||
else : @[Conditional.scala 39:67]
|
||||
node _T_30 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30]
|
||||
when _T_30 : @[Conditional.scala 39:67]
|
||||
node _T_31 = mux(io.ahb.sig.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 83:26]
|
||||
buf_nxtstate <= _T_31 @[ahb_to_axi4.scala 83:20]
|
||||
node _T_32 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 84:24]
|
||||
node _T_33 = or(_T_32, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 84:37]
|
||||
buf_state_en <= _T_33 @[ahb_to_axi4.scala 84:20]
|
||||
node _T_34 = eq(io.ahb.sig.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 85:23]
|
||||
node _T_35 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 85:46]
|
||||
node _T_36 = and(_T_34, _T_35) @[ahb_to_axi4.scala 85:44]
|
||||
cmdbuf_wr_en <= _T_36 @[ahb_to_axi4.scala 85:20]
|
||||
skip @[Conditional.scala 39:67]
|
||||
else : @[Conditional.scala 39:67]
|
||||
node _T_37 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30]
|
||||
when _T_37 : @[Conditional.scala 39:67]
|
||||
buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 88:20]
|
||||
node _T_38 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 89:40]
|
||||
node _T_39 = and(io.axi.r.valid, _T_38) @[ahb_to_axi4.scala 89:38]
|
||||
buf_state_en <= _T_39 @[ahb_to_axi4.scala 89:20]
|
||||
buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 90:20]
|
||||
node _T_40 = bits(io.axi.r.bits.resp, 1, 0) @[ahb_to_axi4.scala 91:61]
|
||||
node _T_41 = orr(_T_40) @[ahb_to_axi4.scala 91:68]
|
||||
node _T_42 = and(buf_state_en, _T_41) @[ahb_to_axi4.scala 91:41]
|
||||
buf_read_error_in <= _T_42 @[ahb_to_axi4.scala 91:25]
|
||||
skip @[Conditional.scala 39:67]
|
||||
node _T_43 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 94:78]
|
||||
node _T_44 = and(io.bus_clk_en, _T_43) @[lib.scala 383:57]
|
||||
reg _T_45 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_44 : @[Reg.scala 28:19]
|
||||
_T_45 <= buf_nxtstate @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
buf_state <= _T_45 @[ahb_to_axi4.scala 94:31]
|
||||
node _T_46 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 96:54]
|
||||
node _T_47 = eq(_T_46, UInt<1>("h00")) @[ahb_to_axi4.scala 96:60]
|
||||
node _T_48 = bits(_T_47, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_49 = mux(_T_48, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_50 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 96:92]
|
||||
node _T_51 = dshl(UInt<1>("h01"), _T_50) @[ahb_to_axi4.scala 96:78]
|
||||
node _T_52 = and(_T_49, _T_51) @[ahb_to_axi4.scala 96:70]
|
||||
node _T_53 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 97:24]
|
||||
node _T_54 = eq(_T_53, UInt<1>("h01")) @[ahb_to_axi4.scala 97:30]
|
||||
node _T_55 = bits(_T_54, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_56 = mux(_T_55, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_57 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 97:62]
|
||||
node _T_58 = dshl(UInt<2>("h03"), _T_57) @[ahb_to_axi4.scala 97:48]
|
||||
node _T_59 = and(_T_56, _T_58) @[ahb_to_axi4.scala 97:40]
|
||||
node _T_60 = or(_T_52, _T_59) @[ahb_to_axi4.scala 96:109]
|
||||
node _T_61 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 98:24]
|
||||
node _T_62 = eq(_T_61, UInt<2>("h02")) @[ahb_to_axi4.scala 98:30]
|
||||
node _T_63 = bits(_T_62, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_64 = mux(_T_63, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_65 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 98:62]
|
||||
node _T_66 = dshl(UInt<4>("h0f"), _T_65) @[ahb_to_axi4.scala 98:48]
|
||||
node _T_67 = and(_T_64, _T_66) @[ahb_to_axi4.scala 98:40]
|
||||
node _T_68 = or(_T_60, _T_67) @[ahb_to_axi4.scala 97:79]
|
||||
node _T_69 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 99:24]
|
||||
node _T_70 = eq(_T_69, UInt<2>("h03")) @[ahb_to_axi4.scala 99:30]
|
||||
node _T_71 = bits(_T_70, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_72 = mux(_T_71, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_73 = and(_T_72, UInt<8>("h0ff")) @[ahb_to_axi4.scala 99:40]
|
||||
node _T_74 = or(_T_68, _T_73) @[ahb_to_axi4.scala 98:79]
|
||||
master_wstrb <= _T_74 @[ahb_to_axi4.scala 96:31]
|
||||
node _T_75 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 102:80]
|
||||
node _T_76 = and(ahb_hresp_q, _T_75) @[ahb_to_axi4.scala 102:78]
|
||||
node _T_77 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 102:98]
|
||||
node _T_78 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 102:124]
|
||||
node _T_79 = or(_T_77, _T_78) @[ahb_to_axi4.scala 102:111]
|
||||
node _T_80 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 102:149]
|
||||
node _T_81 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 102:168]
|
||||
node _T_82 = or(_T_80, _T_81) @[ahb_to_axi4.scala 102:156]
|
||||
node _T_83 = eq(_T_82, UInt<1>("h00")) @[ahb_to_axi4.scala 102:137]
|
||||
node _T_84 = and(_T_79, _T_83) @[ahb_to_axi4.scala 102:135]
|
||||
node _T_85 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 102:181]
|
||||
node _T_86 = and(_T_84, _T_85) @[ahb_to_axi4.scala 102:179]
|
||||
node _T_87 = mux(io.ahb.sig.in.hresp, _T_76, _T_86) @[ahb_to_axi4.scala 102:44]
|
||||
io.ahb.sig.in.hready <= _T_87 @[ahb_to_axi4.scala 102:38]
|
||||
node _T_88 = and(io.ahb.sig.in.hready, io.ahb.hreadyin) @[ahb_to_axi4.scala 103:55]
|
||||
ahb_hready <= _T_88 @[ahb_to_axi4.scala 103:31]
|
||||
node _T_89 = bits(io.ahb.hsel, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_90 = mux(_T_89, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_91 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 104:77]
|
||||
node _T_92 = and(_T_90, _T_91) @[ahb_to_axi4.scala 104:54]
|
||||
ahb_htrans_in <= _T_92 @[ahb_to_axi4.scala 104:31]
|
||||
node _T_93 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 105:50]
|
||||
io.ahb.sig.in.hrdata <= _T_93 @[ahb_to_axi4.scala 105:38]
|
||||
node _T_94 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 106:55]
|
||||
node _T_95 = neq(_T_94, UInt<1>("h00")) @[ahb_to_axi4.scala 106:61]
|
||||
node _T_96 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 106:83]
|
||||
node _T_97 = and(_T_95, _T_96) @[ahb_to_axi4.scala 106:70]
|
||||
node _T_98 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 107:26]
|
||||
node _T_99 = eq(_T_98, UInt<1>("h00")) @[ahb_to_axi4.scala 107:7]
|
||||
node _T_100 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 108:46]
|
||||
node _T_101 = or(ahb_addr_in_iccm, _T_100) @[ahb_to_axi4.scala 108:26]
|
||||
node _T_102 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 108:80]
|
||||
node _T_103 = eq(_T_102, UInt<2>("h02")) @[ahb_to_axi4.scala 108:86]
|
||||
node _T_104 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 108:109]
|
||||
node _T_105 = eq(_T_104, UInt<2>("h03")) @[ahb_to_axi4.scala 108:115]
|
||||
node _T_106 = or(_T_103, _T_105) @[ahb_to_axi4.scala 108:95]
|
||||
node _T_107 = eq(_T_106, UInt<1>("h00")) @[ahb_to_axi4.scala 108:66]
|
||||
node _T_108 = and(_T_101, _T_107) @[ahb_to_axi4.scala 108:64]
|
||||
node _T_109 = or(_T_99, _T_108) @[ahb_to_axi4.scala 107:47]
|
||||
node _T_110 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 109:20]
|
||||
node _T_111 = eq(_T_110, UInt<1>("h01")) @[ahb_to_axi4.scala 109:26]
|
||||
node _T_112 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 109:48]
|
||||
node _T_113 = and(_T_111, _T_112) @[ahb_to_axi4.scala 109:35]
|
||||
node _T_114 = or(_T_109, _T_113) @[ahb_to_axi4.scala 108:126]
|
||||
node _T_115 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 110:20]
|
||||
node _T_116 = eq(_T_115, UInt<2>("h02")) @[ahb_to_axi4.scala 110:26]
|
||||
node _T_117 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 110:49]
|
||||
node _T_118 = orr(_T_117) @[ahb_to_axi4.scala 110:56]
|
||||
node _T_119 = and(_T_116, _T_118) @[ahb_to_axi4.scala 110:35]
|
||||
node _T_120 = or(_T_114, _T_119) @[ahb_to_axi4.scala 109:55]
|
||||
node _T_121 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 111:20]
|
||||
node _T_122 = eq(_T_121, UInt<2>("h03")) @[ahb_to_axi4.scala 111:26]
|
||||
node _T_123 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 111:49]
|
||||
node _T_124 = orr(_T_123) @[ahb_to_axi4.scala 111:56]
|
||||
node _T_125 = and(_T_122, _T_124) @[ahb_to_axi4.scala 111:35]
|
||||
node _T_126 = or(_T_120, _T_125) @[ahb_to_axi4.scala 110:61]
|
||||
node _T_127 = and(_T_97, _T_126) @[ahb_to_axi4.scala 106:94]
|
||||
node _T_128 = or(_T_127, buf_read_error) @[ahb_to_axi4.scala 111:63]
|
||||
node _T_129 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 113:20]
|
||||
node _T_130 = and(ahb_hresp_q, _T_129) @[ahb_to_axi4.scala 113:18]
|
||||
node _T_131 = or(_T_128, _T_130) @[ahb_to_axi4.scala 112:20]
|
||||
io.ahb.sig.in.hresp <= _T_131 @[ahb_to_axi4.scala 106:38]
|
||||
reg _T_132 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when buf_rdata_clk_en : @[Reg.scala 28:19]
|
||||
_T_132 <= io.axi.r.bits.data @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
buf_rdata <= _T_132 @[ahb_to_axi4.scala 116:31]
|
||||
reg _T_133 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when io.bus_clk_en : @[Reg.scala 28:19]
|
||||
_T_133 <= buf_read_error_in @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
buf_read_error <= _T_133 @[ahb_to_axi4.scala 117:31]
|
||||
reg _T_134 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when io.bus_clk_en : @[Reg.scala 28:19]
|
||||
_T_134 <= io.ahb.sig.in.hresp @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
ahb_hresp_q <= _T_134 @[ahb_to_axi4.scala 120:31]
|
||||
reg _T_135 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when io.bus_clk_en : @[Reg.scala 28:19]
|
||||
_T_135 <= ahb_hready @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
ahb_hready_q <= _T_135 @[ahb_to_axi4.scala 121:31]
|
||||
reg _T_136 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when io.bus_clk_en : @[Reg.scala 28:19]
|
||||
_T_136 <= ahb_htrans_in @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
ahb_htrans_q <= _T_136 @[ahb_to_axi4.scala 122:31]
|
||||
reg _T_137 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when ahb_addr_clk_en : @[Reg.scala 28:19]
|
||||
_T_137 <= io.ahb.sig.out.hsize @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
ahb_hsize_q <= _T_137 @[ahb_to_axi4.scala 123:31]
|
||||
reg _T_138 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when ahb_addr_clk_en : @[Reg.scala 28:19]
|
||||
_T_138 <= io.ahb.sig.out.hwrite @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
ahb_hwrite_q <= _T_138 @[ahb_to_axi4.scala 124:31]
|
||||
reg _T_139 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when ahb_addr_clk_en : @[Reg.scala 28:19]
|
||||
_T_139 <= io.ahb.sig.out.haddr @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
ahb_haddr_q <= _T_139 @[ahb_to_axi4.scala 125:31]
|
||||
node _T_140 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 128:81]
|
||||
node _T_141 = and(ahb_hready, _T_140) @[ahb_to_axi4.scala 128:58]
|
||||
node _T_142 = and(io.bus_clk_en, _T_141) @[ahb_to_axi4.scala 128:44]
|
||||
ahb_addr_clk_en <= _T_142 @[ahb_to_axi4.scala 128:27]
|
||||
node _T_143 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 129:48]
|
||||
buf_rdata_clk_en <= _T_143 @[ahb_to_axi4.scala 129:31]
|
||||
node _T_144 = asClock(UInt<1>("h00")) @[ahb_to_axi4.scala 132:34]
|
||||
bus_clk <= _T_144 @[ahb_to_axi4.scala 132:20]
|
||||
node _T_145 = asClock(UInt<1>("h00")) @[ahb_to_axi4.scala 133:34]
|
||||
ahb_addr_clk <= _T_145 @[ahb_to_axi4.scala 133:20]
|
||||
node _T_146 = asClock(UInt<1>("h00")) @[ahb_to_axi4.scala 134:34]
|
||||
buf_rdata_clk <= _T_146 @[ahb_to_axi4.scala 134:20]
|
||||
node _T_147 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 141:53]
|
||||
node _T_148 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 141:91]
|
||||
node _T_149 = or(_T_147, _T_148) @[ahb_to_axi4.scala 141:72]
|
||||
node _T_150 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 141:113]
|
||||
node _T_151 = and(_T_149, _T_150) @[ahb_to_axi4.scala 141:111]
|
||||
node _T_152 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 141:153]
|
||||
node _T_153 = and(io.ahb.sig.in.hresp, _T_152) @[ahb_to_axi4.scala 141:151]
|
||||
node _T_154 = or(_T_151, _T_153) @[ahb_to_axi4.scala 141:128]
|
||||
cmdbuf_rst <= _T_154 @[ahb_to_axi4.scala 141:31]
|
||||
node _T_155 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 142:67]
|
||||
node _T_156 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 142:105]
|
||||
node _T_157 = or(_T_155, _T_156) @[ahb_to_axi4.scala 142:86]
|
||||
node _T_158 = eq(_T_157, UInt<1>("h00")) @[ahb_to_axi4.scala 142:48]
|
||||
node _T_159 = and(cmdbuf_vld, _T_158) @[ahb_to_axi4.scala 142:46]
|
||||
cmdbuf_full <= _T_159 @[ahb_to_axi4.scala 142:31]
|
||||
node _T_160 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 144:73]
|
||||
wire _T_161 : UInt @[lib.scala 389:21]
|
||||
node _T_162 = eq(cmdbuf_rst, UInt<1>("h00")) @[lib.scala 391:75]
|
||||
node _T_163 = and(UInt<1>("h01"), _T_162) @[lib.scala 391:53]
|
||||
node _T_164 = or(_T_160, cmdbuf_rst) @[lib.scala 391:95]
|
||||
node _T_165 = and(_T_164, io.bus_clk_en) @[lib.scala 391:102]
|
||||
node _T_166 = bits(_T_165, 0, 0) @[lib.scala 8:44]
|
||||
reg _T_167 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_166 : @[Reg.scala 28:19]
|
||||
_T_167 <= _T_163 @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
_T_161 <= _T_167 @[lib.scala 391:14]
|
||||
cmdbuf_vld <= _T_161 @[ahb_to_axi4.scala 144:31]
|
||||
node _T_168 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 146:79]
|
||||
node _T_169 = and(io.bus_clk_en, _T_168) @[lib.scala 383:57]
|
||||
reg _T_170 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_169 : @[Reg.scala 28:19]
|
||||
_T_170 <= ahb_hwrite_q @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
cmdbuf_write <= _T_170 @[ahb_to_axi4.scala 146:31]
|
||||
node _T_171 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 147:78]
|
||||
node _T_172 = and(io.bus_clk_en, _T_171) @[lib.scala 383:57]
|
||||
reg _T_173 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_172 : @[Reg.scala 28:19]
|
||||
_T_173 <= ahb_hsize_q @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
cmdbuf_size <= _T_173 @[ahb_to_axi4.scala 147:31]
|
||||
node _T_174 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 148:79]
|
||||
node _T_175 = and(io.bus_clk_en, _T_174) @[lib.scala 383:57]
|
||||
reg _T_176 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_175 : @[Reg.scala 28:19]
|
||||
_T_176 <= master_wstrb @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
cmdbuf_wstrb <= _T_176 @[ahb_to_axi4.scala 148:31]
|
||||
node _T_177 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 150:57]
|
||||
node _T_178 = and(_T_177, io.bus_clk_en) @[ahb_to_axi4.scala 150:59]
|
||||
inst rvclkhdr of rvclkhdr @[lib.scala 399:23]
|
||||
rvclkhdr.clock <= clock
|
||||
rvclkhdr.reset <= reset
|
||||
rvclkhdr.io.clk <= clock @[lib.scala 401:18]
|
||||
rvclkhdr.io.en <= _T_178 @[lib.scala 402:17]
|
||||
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24]
|
||||
reg _T_179 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_178 : @[Reg.scala 28:19]
|
||||
_T_179 <= ahb_haddr_q @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
cmdbuf_addr <= _T_179 @[ahb_to_axi4.scala 150:15]
|
||||
node _T_180 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 151:68]
|
||||
node _T_181 = and(_T_180, io.bus_clk_en) @[ahb_to_axi4.scala 151:70]
|
||||
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 399:23]
|
||||
rvclkhdr_1.clock <= clock
|
||||
rvclkhdr_1.reset <= reset
|
||||
rvclkhdr_1.io.clk <= clock @[lib.scala 401:18]
|
||||
rvclkhdr_1.io.en <= _T_181 @[lib.scala 402:17]
|
||||
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24]
|
||||
reg _T_182 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_181 : @[Reg.scala 28:19]
|
||||
_T_182 <= io.ahb.sig.out.hwdata @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
cmdbuf_wdata <= _T_182 @[ahb_to_axi4.scala 151:16]
|
||||
node _T_183 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 154:42]
|
||||
io.axi.aw.valid <= _T_183 @[ahb_to_axi4.scala 154:28]
|
||||
io.axi.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 155:33]
|
||||
io.axi.aw.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 156:33]
|
||||
node _T_184 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 157:59]
|
||||
node _T_185 = cat(UInt<1>("h00"), _T_184) @[Cat.scala 29:58]
|
||||
io.axi.aw.bits.size <= _T_185 @[ahb_to_axi4.scala 157:33]
|
||||
node _T_186 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
||||
io.axi.aw.bits.prot <= _T_186 @[ahb_to_axi4.scala 158:33]
|
||||
node _T_187 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
||||
io.axi.aw.bits.len <= _T_187 @[ahb_to_axi4.scala 159:33]
|
||||
io.axi.aw.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 160:33]
|
||||
node _T_188 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 162:42]
|
||||
io.axi.w.valid <= _T_188 @[ahb_to_axi4.scala 162:28]
|
||||
io.axi.w.bits.data <= cmdbuf_wdata @[ahb_to_axi4.scala 163:33]
|
||||
io.axi.w.bits.strb <= cmdbuf_wstrb @[ahb_to_axi4.scala 164:33]
|
||||
io.axi.w.bits.last <= UInt<1>("h01") @[ahb_to_axi4.scala 165:33]
|
||||
io.axi.b.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 167:28]
|
||||
node _T_189 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 169:44]
|
||||
node _T_190 = and(cmdbuf_vld, _T_189) @[ahb_to_axi4.scala 169:42]
|
||||
io.axi.ar.valid <= _T_190 @[ahb_to_axi4.scala 169:28]
|
||||
io.axi.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 170:33]
|
||||
io.axi.ar.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 171:33]
|
||||
node _T_191 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 172:59]
|
||||
node _T_192 = cat(UInt<1>("h00"), _T_191) @[Cat.scala 29:58]
|
||||
io.axi.ar.bits.size <= _T_192 @[ahb_to_axi4.scala 172:33]
|
||||
node _T_193 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
||||
io.axi.ar.bits.prot <= _T_193 @[ahb_to_axi4.scala 173:33]
|
||||
node _T_194 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
|
||||
io.axi.ar.bits.len <= _T_194 @[ahb_to_axi4.scala 174:33]
|
||||
io.axi.ar.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 175:33]
|
||||
io.axi.r.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 177:28]
|
||||
|
||||
|
|
@ -0,0 +1,524 @@
|
|||
module rvclkhdr(
|
||||
input io_clk,
|
||||
input io_en
|
||||
);
|
||||
wire clkhdr_Q; // @[lib.scala 334:26]
|
||||
wire clkhdr_CK; // @[lib.scala 334:26]
|
||||
wire clkhdr_EN; // @[lib.scala 334:26]
|
||||
wire clkhdr_SE; // @[lib.scala 334:26]
|
||||
gated_latch clkhdr ( // @[lib.scala 334:26]
|
||||
.Q(clkhdr_Q),
|
||||
.CK(clkhdr_CK),
|
||||
.EN(clkhdr_EN),
|
||||
.SE(clkhdr_SE)
|
||||
);
|
||||
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
|
||||
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
|
||||
assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
|
||||
endmodule
|
||||
module ahb_to_axi4(
|
||||
input clock,
|
||||
input reset,
|
||||
input io_scan_mode,
|
||||
input io_bus_clk_en,
|
||||
input io_clk_override,
|
||||
input io_axi_aw_ready,
|
||||
output io_axi_aw_valid,
|
||||
output io_axi_aw_bits_id,
|
||||
output [31:0] io_axi_aw_bits_addr,
|
||||
output [3:0] io_axi_aw_bits_region,
|
||||
output [7:0] io_axi_aw_bits_len,
|
||||
output [2:0] io_axi_aw_bits_size,
|
||||
output [1:0] io_axi_aw_bits_burst,
|
||||
output io_axi_aw_bits_lock,
|
||||
output [3:0] io_axi_aw_bits_cache,
|
||||
output [2:0] io_axi_aw_bits_prot,
|
||||
output [3:0] io_axi_aw_bits_qos,
|
||||
input io_axi_w_ready,
|
||||
output io_axi_w_valid,
|
||||
output [63:0] io_axi_w_bits_data,
|
||||
output [7:0] io_axi_w_bits_strb,
|
||||
output io_axi_w_bits_last,
|
||||
output io_axi_b_ready,
|
||||
input io_axi_b_valid,
|
||||
input [1:0] io_axi_b_bits_resp,
|
||||
input io_axi_b_bits_id,
|
||||
input io_axi_ar_ready,
|
||||
output io_axi_ar_valid,
|
||||
output io_axi_ar_bits_id,
|
||||
output [31:0] io_axi_ar_bits_addr,
|
||||
output [3:0] io_axi_ar_bits_region,
|
||||
output [7:0] io_axi_ar_bits_len,
|
||||
output [2:0] io_axi_ar_bits_size,
|
||||
output [1:0] io_axi_ar_bits_burst,
|
||||
output io_axi_ar_bits_lock,
|
||||
output [3:0] io_axi_ar_bits_cache,
|
||||
output [2:0] io_axi_ar_bits_prot,
|
||||
output [3:0] io_axi_ar_bits_qos,
|
||||
output io_axi_r_ready,
|
||||
input io_axi_r_valid,
|
||||
input io_axi_r_bits_id,
|
||||
input [63:0] io_axi_r_bits_data,
|
||||
input [1:0] io_axi_r_bits_resp,
|
||||
input io_axi_r_bits_last,
|
||||
output [63:0] io_ahb_sig_in_hrdata,
|
||||
output io_ahb_sig_in_hready,
|
||||
output io_ahb_sig_in_hresp,
|
||||
input [31:0] io_ahb_sig_out_haddr,
|
||||
input [2:0] io_ahb_sig_out_hburst,
|
||||
input io_ahb_sig_out_hmastlock,
|
||||
input [3:0] io_ahb_sig_out_hprot,
|
||||
input [2:0] io_ahb_sig_out_hsize,
|
||||
input [1:0] io_ahb_sig_out_htrans,
|
||||
input io_ahb_sig_out_hwrite,
|
||||
input [63:0] io_ahb_sig_out_hwdata,
|
||||
input io_ahb_hsel,
|
||||
input io_ahb_hreadyin
|
||||
);
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
reg [31:0] _RAND_0;
|
||||
reg [31:0] _RAND_1;
|
||||
reg [31:0] _RAND_2;
|
||||
reg [31:0] _RAND_3;
|
||||
reg [31:0] _RAND_4;
|
||||
reg [31:0] _RAND_5;
|
||||
reg [31:0] _RAND_6;
|
||||
reg [31:0] _RAND_7;
|
||||
reg [63:0] _RAND_8;
|
||||
reg [31:0] _RAND_9;
|
||||
reg [31:0] _RAND_10;
|
||||
reg [31:0] _RAND_11;
|
||||
reg [31:0] _RAND_12;
|
||||
reg [31:0] _RAND_13;
|
||||
reg [63:0] _RAND_14;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
wire rvclkhdr_io_clk; // @[lib.scala 399:23]
|
||||
wire rvclkhdr_io_en; // @[lib.scala 399:23]
|
||||
wire rvclkhdr_1_io_clk; // @[lib.scala 399:23]
|
||||
wire rvclkhdr_1_io_en; // @[lib.scala 399:23]
|
||||
reg [31:0] ahb_haddr_q; // @[Reg.scala 27:20]
|
||||
wire ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[lib.scala 87:29]
|
||||
wire ahb_addr_in_iccm = ahb_haddr_q[31:16] == 16'hee00; // @[lib.scala 87:29]
|
||||
reg [1:0] buf_state; // @[Reg.scala 27:20]
|
||||
wire _T_7 = 2'h0 == buf_state; // @[Conditional.scala 37:30]
|
||||
wire ahb_hready = io_ahb_sig_in_hready & io_ahb_hreadyin; // @[ahb_to_axi4.scala 103:55]
|
||||
wire _T_10 = ahb_hready & io_ahb_sig_out_htrans[1]; // @[ahb_to_axi4.scala 75:34]
|
||||
wire _T_11 = _T_10 & io_ahb_hsel; // @[ahb_to_axi4.scala 75:61]
|
||||
wire _T_12 = 2'h1 == buf_state; // @[Conditional.scala 37:30]
|
||||
wire _T_14 = io_ahb_sig_out_htrans == 2'h0; // @[ahb_to_axi4.scala 78:79]
|
||||
wire _T_15 = io_ahb_sig_in_hresp | _T_14; // @[ahb_to_axi4.scala 78:48]
|
||||
wire _T_16 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 78:93]
|
||||
wire _T_17 = _T_15 | _T_16; // @[ahb_to_axi4.scala 78:91]
|
||||
reg cmdbuf_vld; // @[Reg.scala 27:20]
|
||||
wire _T_155 = io_axi_aw_valid & io_axi_aw_ready; // @[ahb_to_axi4.scala 142:67]
|
||||
wire _T_156 = io_axi_ar_valid & io_axi_ar_ready; // @[ahb_to_axi4.scala 142:105]
|
||||
wire _T_157 = _T_155 | _T_156; // @[ahb_to_axi4.scala 142:86]
|
||||
wire _T_158 = ~_T_157; // @[ahb_to_axi4.scala 142:48]
|
||||
wire cmdbuf_full = cmdbuf_vld & _T_158; // @[ahb_to_axi4.scala 142:46]
|
||||
wire _T_21 = ~cmdbuf_full; // @[ahb_to_axi4.scala 79:24]
|
||||
wire _T_22 = _T_21 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 79:37]
|
||||
wire _T_25 = io_ahb_sig_out_htrans == 2'h1; // @[ahb_to_axi4.scala 80:92]
|
||||
wire _T_26 = _T_25 & io_ahb_hsel; // @[ahb_to_axi4.scala 80:110]
|
||||
wire _T_27 = io_ahb_sig_in_hresp | _T_26; // @[ahb_to_axi4.scala 80:60]
|
||||
wire _T_28 = ~_T_27; // @[ahb_to_axi4.scala 80:38]
|
||||
wire _T_29 = _T_21 & _T_28; // @[ahb_to_axi4.scala 80:36]
|
||||
wire _T_30 = 2'h2 == buf_state; // @[Conditional.scala 37:30]
|
||||
wire _T_34 = ~io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 85:23]
|
||||
wire _T_36 = _T_34 & _T_21; // @[ahb_to_axi4.scala 85:44]
|
||||
wire _T_37 = 2'h3 == buf_state; // @[Conditional.scala 37:30]
|
||||
reg cmdbuf_write; // @[Reg.scala 27:20]
|
||||
wire _T_38 = ~cmdbuf_write; // @[ahb_to_axi4.scala 89:40]
|
||||
wire _T_39 = io_axi_r_valid & _T_38; // @[ahb_to_axi4.scala 89:38]
|
||||
wire _T_41 = |io_axi_r_bits_resp; // @[ahb_to_axi4.scala 91:68]
|
||||
wire _GEN_1 = _T_37 & _T_39; // @[Conditional.scala 39:67]
|
||||
wire _GEN_5 = _T_30 ? _T_22 : _GEN_1; // @[Conditional.scala 39:67]
|
||||
wire _GEN_10 = _T_12 ? _T_22 : _GEN_5; // @[Conditional.scala 39:67]
|
||||
wire buf_state_en = _T_7 ? _T_11 : _GEN_10; // @[Conditional.scala 40:58]
|
||||
wire _T_42 = buf_state_en & _T_41; // @[ahb_to_axi4.scala 91:41]
|
||||
wire _GEN_2 = _T_37 & buf_state_en; // @[Conditional.scala 39:67]
|
||||
wire _GEN_3 = _T_37 & _T_42; // @[Conditional.scala 39:67]
|
||||
wire _GEN_6 = _T_30 & _T_36; // @[Conditional.scala 39:67]
|
||||
wire _GEN_7 = _T_30 ? 1'h0 : _GEN_2; // @[Conditional.scala 39:67]
|
||||
wire _GEN_11 = _T_12 ? _T_29 : _GEN_6; // @[Conditional.scala 39:67]
|
||||
wire _GEN_12 = _T_12 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67]
|
||||
wire cmdbuf_wr_en = _T_7 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58]
|
||||
wire buf_rdata_en = _T_7 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58]
|
||||
wire _T_44 = io_bus_clk_en & buf_state_en; // @[lib.scala 383:57]
|
||||
reg [2:0] ahb_hsize_q; // @[Reg.scala 27:20]
|
||||
wire _T_47 = ahb_hsize_q == 3'h0; // @[ahb_to_axi4.scala 96:60]
|
||||
wire [7:0] _T_49 = _T_47 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
||||
wire [7:0] _T_51 = 8'h1 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 96:78]
|
||||
wire [7:0] _T_52 = _T_49 & _T_51; // @[ahb_to_axi4.scala 96:70]
|
||||
wire _T_54 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 97:30]
|
||||
wire [7:0] _T_56 = _T_54 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
||||
wire [8:0] _T_58 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 97:48]
|
||||
wire [8:0] _GEN_34 = {{1'd0}, _T_56}; // @[ahb_to_axi4.scala 97:40]
|
||||
wire [8:0] _T_59 = _GEN_34 & _T_58; // @[ahb_to_axi4.scala 97:40]
|
||||
wire [8:0] _GEN_35 = {{1'd0}, _T_52}; // @[ahb_to_axi4.scala 96:109]
|
||||
wire [8:0] _T_60 = _GEN_35 | _T_59; // @[ahb_to_axi4.scala 96:109]
|
||||
wire _T_62 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 98:30]
|
||||
wire [7:0] _T_64 = _T_62 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
||||
wire [10:0] _T_66 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 98:48]
|
||||
wire [10:0] _GEN_36 = {{3'd0}, _T_64}; // @[ahb_to_axi4.scala 98:40]
|
||||
wire [10:0] _T_67 = _GEN_36 & _T_66; // @[ahb_to_axi4.scala 98:40]
|
||||
wire [10:0] _GEN_37 = {{2'd0}, _T_60}; // @[ahb_to_axi4.scala 97:79]
|
||||
wire [10:0] _T_68 = _GEN_37 | _T_67; // @[ahb_to_axi4.scala 97:79]
|
||||
wire _T_70 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 99:30]
|
||||
wire [7:0] _T_72 = _T_70 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
|
||||
wire [10:0] _GEN_38 = {{3'd0}, _T_72}; // @[ahb_to_axi4.scala 98:79]
|
||||
wire [10:0] _T_74 = _T_68 | _GEN_38; // @[ahb_to_axi4.scala 98:79]
|
||||
reg ahb_hready_q; // @[Reg.scala 27:20]
|
||||
wire _T_75 = ~ahb_hready_q; // @[ahb_to_axi4.scala 102:80]
|
||||
reg ahb_hresp_q; // @[Reg.scala 27:20]
|
||||
wire _T_76 = ahb_hresp_q & _T_75; // @[ahb_to_axi4.scala 102:78]
|
||||
wire _T_78 = buf_state == 2'h0; // @[ahb_to_axi4.scala 102:124]
|
||||
wire _T_79 = _T_21 | _T_78; // @[ahb_to_axi4.scala 102:111]
|
||||
wire _T_80 = buf_state == 2'h2; // @[ahb_to_axi4.scala 102:149]
|
||||
wire _T_81 = buf_state == 2'h3; // @[ahb_to_axi4.scala 102:168]
|
||||
wire _T_82 = _T_80 | _T_81; // @[ahb_to_axi4.scala 102:156]
|
||||
wire _T_83 = ~_T_82; // @[ahb_to_axi4.scala 102:137]
|
||||
wire _T_84 = _T_79 & _T_83; // @[ahb_to_axi4.scala 102:135]
|
||||
reg buf_read_error; // @[Reg.scala 27:20]
|
||||
wire _T_85 = ~buf_read_error; // @[ahb_to_axi4.scala 102:181]
|
||||
wire _T_86 = _T_84 & _T_85; // @[ahb_to_axi4.scala 102:179]
|
||||
wire [1:0] _T_90 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||
wire [1:0] ahb_htrans_in = _T_90 & io_ahb_sig_out_htrans; // @[ahb_to_axi4.scala 104:54]
|
||||
reg [63:0] buf_rdata; // @[Reg.scala 27:20]
|
||||
reg [1:0] ahb_htrans_q; // @[Reg.scala 27:20]
|
||||
wire _T_95 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 106:61]
|
||||
wire _T_96 = buf_state != 2'h0; // @[ahb_to_axi4.scala 106:83]
|
||||
wire _T_97 = _T_95 & _T_96; // @[ahb_to_axi4.scala 106:70]
|
||||
wire _T_98 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 107:26]
|
||||
wire _T_99 = ~_T_98; // @[ahb_to_axi4.scala 107:7]
|
||||
reg ahb_hwrite_q; // @[Reg.scala 27:20]
|
||||
wire _T_100 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 108:46]
|
||||
wire _T_101 = ahb_addr_in_iccm | _T_100; // @[ahb_to_axi4.scala 108:26]
|
||||
wire _T_103 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 108:86]
|
||||
wire _T_105 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 108:115]
|
||||
wire _T_106 = _T_103 | _T_105; // @[ahb_to_axi4.scala 108:95]
|
||||
wire _T_107 = ~_T_106; // @[ahb_to_axi4.scala 108:66]
|
||||
wire _T_108 = _T_101 & _T_107; // @[ahb_to_axi4.scala 108:64]
|
||||
wire _T_109 = _T_99 | _T_108; // @[ahb_to_axi4.scala 107:47]
|
||||
wire _T_113 = _T_54 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 109:35]
|
||||
wire _T_114 = _T_109 | _T_113; // @[ahb_to_axi4.scala 108:126]
|
||||
wire _T_118 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 110:56]
|
||||
wire _T_119 = _T_62 & _T_118; // @[ahb_to_axi4.scala 110:35]
|
||||
wire _T_120 = _T_114 | _T_119; // @[ahb_to_axi4.scala 109:55]
|
||||
wire _T_124 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 111:56]
|
||||
wire _T_125 = _T_70 & _T_124; // @[ahb_to_axi4.scala 111:35]
|
||||
wire _T_126 = _T_120 | _T_125; // @[ahb_to_axi4.scala 110:61]
|
||||
wire _T_127 = _T_97 & _T_126; // @[ahb_to_axi4.scala 106:94]
|
||||
wire _T_128 = _T_127 | buf_read_error; // @[ahb_to_axi4.scala 111:63]
|
||||
wire buf_rdata_clk_en = io_bus_clk_en & buf_rdata_en; // @[ahb_to_axi4.scala 129:48]
|
||||
wire ahb_addr_clk_en = io_bus_clk_en & _T_10; // @[ahb_to_axi4.scala 128:44]
|
||||
wire _T_150 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 141:113]
|
||||
wire _T_151 = _T_157 & _T_150; // @[ahb_to_axi4.scala 141:111]
|
||||
wire _T_153 = io_ahb_sig_in_hresp & _T_38; // @[ahb_to_axi4.scala 141:151]
|
||||
wire cmdbuf_rst = _T_151 | _T_153; // @[ahb_to_axi4.scala 141:128]
|
||||
wire _T_162 = ~cmdbuf_rst; // @[lib.scala 391:75]
|
||||
wire _T_164 = cmdbuf_wr_en | cmdbuf_rst; // @[lib.scala 391:95]
|
||||
wire _T_165 = _T_164 & io_bus_clk_en; // @[lib.scala 391:102]
|
||||
wire _T_169 = io_bus_clk_en & cmdbuf_wr_en; // @[lib.scala 383:57]
|
||||
reg [2:0] _T_173; // @[Reg.scala 27:20]
|
||||
reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20]
|
||||
wire [7:0] master_wstrb = _T_74[7:0]; // @[ahb_to_axi4.scala 96:31]
|
||||
wire _T_178 = cmdbuf_wr_en & io_bus_clk_en; // @[ahb_to_axi4.scala 150:59]
|
||||
reg [31:0] cmdbuf_addr; // @[Reg.scala 27:20]
|
||||
reg [63:0] cmdbuf_wdata; // @[Reg.scala 27:20]
|
||||
wire [1:0] cmdbuf_size = _T_173[1:0]; // @[ahb_to_axi4.scala 147:31]
|
||||
rvclkhdr rvclkhdr ( // @[lib.scala 399:23]
|
||||
.io_clk(rvclkhdr_io_clk),
|
||||
.io_en(rvclkhdr_io_en)
|
||||
);
|
||||
rvclkhdr rvclkhdr_1 ( // @[lib.scala 399:23]
|
||||
.io_clk(rvclkhdr_1_io_clk),
|
||||
.io_en(rvclkhdr_1_io_en)
|
||||
);
|
||||
assign io_axi_aw_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 154:28]
|
||||
assign io_axi_aw_bits_id = 1'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 155:33]
|
||||
assign io_axi_aw_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 156:33]
|
||||
assign io_axi_aw_bits_region = 4'h0; // @[ahb_to_axi4.scala 20:10]
|
||||
assign io_axi_aw_bits_len = 8'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 159:33]
|
||||
assign io_axi_aw_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 157:33]
|
||||
assign io_axi_aw_bits_burst = 2'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 160:33]
|
||||
assign io_axi_aw_bits_lock = 1'h0; // @[ahb_to_axi4.scala 20:10]
|
||||
assign io_axi_aw_bits_cache = 4'h0; // @[ahb_to_axi4.scala 20:10]
|
||||
assign io_axi_aw_bits_prot = 3'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 158:33]
|
||||
assign io_axi_aw_bits_qos = 4'h0; // @[ahb_to_axi4.scala 20:10]
|
||||
assign io_axi_w_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 162:28]
|
||||
assign io_axi_w_bits_data = cmdbuf_wdata; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 163:33]
|
||||
assign io_axi_w_bits_strb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 164:33]
|
||||
assign io_axi_w_bits_last = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 165:33]
|
||||
assign io_axi_b_ready = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 167:28]
|
||||
assign io_axi_ar_valid = cmdbuf_vld & _T_38; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 169:28]
|
||||
assign io_axi_ar_bits_id = 1'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 170:33]
|
||||
assign io_axi_ar_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 171:33]
|
||||
assign io_axi_ar_bits_region = 4'h0; // @[ahb_to_axi4.scala 20:10]
|
||||
assign io_axi_ar_bits_len = 8'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 174:33]
|
||||
assign io_axi_ar_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 172:33]
|
||||
assign io_axi_ar_bits_burst = 2'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 175:33]
|
||||
assign io_axi_ar_bits_lock = 1'h0; // @[ahb_to_axi4.scala 20:10]
|
||||
assign io_axi_ar_bits_cache = 4'h0; // @[ahb_to_axi4.scala 20:10]
|
||||
assign io_axi_ar_bits_prot = 3'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 173:33]
|
||||
assign io_axi_ar_bits_qos = 4'h0; // @[ahb_to_axi4.scala 20:10]
|
||||
assign io_axi_r_ready = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 177:28]
|
||||
assign io_ahb_sig_in_hrdata = buf_rdata; // @[ahb_to_axi4.scala 105:38]
|
||||
assign io_ahb_sig_in_hready = io_ahb_sig_in_hresp ? _T_76 : _T_86; // @[ahb_to_axi4.scala 102:38]
|
||||
assign io_ahb_sig_in_hresp = _T_128 | _T_76; // @[ahb_to_axi4.scala 106:38]
|
||||
assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18]
|
||||
assign rvclkhdr_io_en = cmdbuf_wr_en & io_bus_clk_en; // @[lib.scala 402:17]
|
||||
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 401:18]
|
||||
assign rvclkhdr_1_io_en = cmdbuf_wr_en & io_bus_clk_en; // @[lib.scala 402:17]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_INVALID_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifndef RANDOM
|
||||
`define RANDOM $random
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
integer initvar;
|
||||
`endif
|
||||
`ifndef SYNTHESIS
|
||||
`ifdef FIRRTL_BEFORE_INITIAL
|
||||
`FIRRTL_BEFORE_INITIAL
|
||||
`endif
|
||||
initial begin
|
||||
`ifdef RANDOMIZE
|
||||
`ifdef INIT_RANDOM
|
||||
`INIT_RANDOM
|
||||
`endif
|
||||
`ifndef VERILATOR
|
||||
`ifdef RANDOMIZE_DELAY
|
||||
#`RANDOMIZE_DELAY begin end
|
||||
`else
|
||||
#0.002 begin end
|
||||
`endif
|
||||
`endif
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
_RAND_0 = {1{`RANDOM}};
|
||||
ahb_haddr_q = _RAND_0[31:0];
|
||||
_RAND_1 = {1{`RANDOM}};
|
||||
buf_state = _RAND_1[1:0];
|
||||
_RAND_2 = {1{`RANDOM}};
|
||||
cmdbuf_vld = _RAND_2[0:0];
|
||||
_RAND_3 = {1{`RANDOM}};
|
||||
cmdbuf_write = _RAND_3[0:0];
|
||||
_RAND_4 = {1{`RANDOM}};
|
||||
ahb_hsize_q = _RAND_4[2:0];
|
||||
_RAND_5 = {1{`RANDOM}};
|
||||
ahb_hready_q = _RAND_5[0:0];
|
||||
_RAND_6 = {1{`RANDOM}};
|
||||
ahb_hresp_q = _RAND_6[0:0];
|
||||
_RAND_7 = {1{`RANDOM}};
|
||||
buf_read_error = _RAND_7[0:0];
|
||||
_RAND_8 = {2{`RANDOM}};
|
||||
buf_rdata = _RAND_8[63:0];
|
||||
_RAND_9 = {1{`RANDOM}};
|
||||
ahb_htrans_q = _RAND_9[1:0];
|
||||
_RAND_10 = {1{`RANDOM}};
|
||||
ahb_hwrite_q = _RAND_10[0:0];
|
||||
_RAND_11 = {1{`RANDOM}};
|
||||
_T_173 = _RAND_11[2:0];
|
||||
_RAND_12 = {1{`RANDOM}};
|
||||
cmdbuf_wstrb = _RAND_12[7:0];
|
||||
_RAND_13 = {1{`RANDOM}};
|
||||
cmdbuf_addr = _RAND_13[31:0];
|
||||
_RAND_14 = {2{`RANDOM}};
|
||||
cmdbuf_wdata = _RAND_14[63:0];
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
if (reset) begin
|
||||
ahb_haddr_q = 32'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
buf_state = 2'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cmdbuf_vld = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cmdbuf_write = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
ahb_hsize_q = 3'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
ahb_hready_q = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
ahb_hresp_q = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
buf_read_error = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
buf_rdata = 64'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
ahb_htrans_q = 2'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
ahb_hwrite_q = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_173 = 3'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cmdbuf_wstrb = 8'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cmdbuf_addr = 32'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cmdbuf_wdata = 64'h0;
|
||||
end
|
||||
`endif // RANDOMIZE
|
||||
end // initial
|
||||
`ifdef FIRRTL_AFTER_INITIAL
|
||||
`FIRRTL_AFTER_INITIAL
|
||||
`endif
|
||||
`endif // SYNTHESIS
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
ahb_haddr_q <= 32'h0;
|
||||
end else if (ahb_addr_clk_en) begin
|
||||
ahb_haddr_q <= io_ahb_sig_out_haddr;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
buf_state <= 2'h0;
|
||||
end else if (_T_44) begin
|
||||
if (_T_7) begin
|
||||
if (io_ahb_sig_out_hwrite) begin
|
||||
buf_state <= 2'h1;
|
||||
end else begin
|
||||
buf_state <= 2'h2;
|
||||
end
|
||||
end else if (_T_12) begin
|
||||
if (_T_17) begin
|
||||
buf_state <= 2'h0;
|
||||
end else if (io_ahb_sig_out_hwrite) begin
|
||||
buf_state <= 2'h1;
|
||||
end else begin
|
||||
buf_state <= 2'h2;
|
||||
end
|
||||
end else if (_T_30) begin
|
||||
if (io_ahb_sig_in_hresp) begin
|
||||
buf_state <= 2'h0;
|
||||
end else begin
|
||||
buf_state <= 2'h3;
|
||||
end
|
||||
end else begin
|
||||
buf_state <= 2'h0;
|
||||
end
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
cmdbuf_vld <= 1'h0;
|
||||
end else if (_T_165) begin
|
||||
cmdbuf_vld <= _T_162;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
cmdbuf_write <= 1'h0;
|
||||
end else if (_T_169) begin
|
||||
cmdbuf_write <= ahb_hwrite_q;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
ahb_hsize_q <= 3'h0;
|
||||
end else if (ahb_addr_clk_en) begin
|
||||
ahb_hsize_q <= io_ahb_sig_out_hsize;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
ahb_hready_q <= 1'h0;
|
||||
end else if (io_bus_clk_en) begin
|
||||
ahb_hready_q <= ahb_hready;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
ahb_hresp_q <= 1'h0;
|
||||
end else if (io_bus_clk_en) begin
|
||||
ahb_hresp_q <= io_ahb_sig_in_hresp;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
buf_read_error <= 1'h0;
|
||||
end else if (io_bus_clk_en) begin
|
||||
if (_T_7) begin
|
||||
buf_read_error <= 1'h0;
|
||||
end else if (_T_12) begin
|
||||
buf_read_error <= 1'h0;
|
||||
end else if (_T_30) begin
|
||||
buf_read_error <= 1'h0;
|
||||
end else begin
|
||||
buf_read_error <= _GEN_3;
|
||||
end
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
buf_rdata <= 64'h0;
|
||||
end else if (buf_rdata_clk_en) begin
|
||||
buf_rdata <= io_axi_r_bits_data;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
ahb_htrans_q <= 2'h0;
|
||||
end else if (io_bus_clk_en) begin
|
||||
ahb_htrans_q <= ahb_htrans_in;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
ahb_hwrite_q <= 1'h0;
|
||||
end else if (ahb_addr_clk_en) begin
|
||||
ahb_hwrite_q <= io_ahb_sig_out_hwrite;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_173 <= 3'h0;
|
||||
end else if (_T_169) begin
|
||||
_T_173 <= ahb_hsize_q;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
cmdbuf_wstrb <= 8'h0;
|
||||
end else if (_T_169) begin
|
||||
cmdbuf_wstrb <= master_wstrb;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
cmdbuf_addr <= 32'h0;
|
||||
end else if (_T_178) begin
|
||||
cmdbuf_addr <= ahb_haddr_q;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
cmdbuf_wdata <= 64'h0;
|
||||
end else if (_T_178) begin
|
||||
cmdbuf_wdata <= io_ahb_sig_out_hwdata;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -16,7 +16,7 @@ class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset {
|
|||
val sig = Flipped(new ahb_channel())
|
||||
val hsel = Input(Bool())
|
||||
val hreadyin = Input(Bool())}
|
||||
})
|
||||
})
|
||||
io.axi <> 0.U.asTypeOf(io.axi)
|
||||
val idle:: wr :: rd :: pend :: Nil = Enum(4)
|
||||
val master_wstrb = WireInit(0.U(8.W))
|
||||
|
|
@ -38,9 +38,9 @@ class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset {
|
|||
|
||||
// signals needed for the read data coming back from the core and to block any further commands as AHB is a blocking bus
|
||||
val buf_rdata_en = WireInit(Bool(), false.B)
|
||||
val ahb_bus_addr_clk_en = WireInit(Bool(), false.B)
|
||||
val ahb_addr_clk_en = WireInit(Bool(), false.B)
|
||||
val buf_rdata_clk_en = WireInit(Bool(), false.B)
|
||||
val ahb_clk = Wire(Clock())
|
||||
val bus_clk = Wire(Clock())
|
||||
val ahb_addr_clk = Wire(Clock())
|
||||
val buf_rdata_clk = Wire(Clock())
|
||||
|
||||
|
|
@ -54,7 +54,6 @@ class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset {
|
|||
val cmdbuf_wstrb = WireInit(0.U(8.W))
|
||||
val cmdbuf_addr = WireInit(0.U(32.W))
|
||||
val cmdbuf_wdata = WireInit(0.U(64.W))
|
||||
val bus_clk = Wire(Clock())
|
||||
|
||||
// Address check dccm
|
||||
val (ahb_addr_in_dccm_region_nc,ahb_addr_in_dccm) = rvrangecheck(DCCM_SADR,DCCM_SIZE,ahb_haddr_q)
|
||||
|
|
@ -92,7 +91,7 @@ class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset {
|
|||
buf_read_error_in := buf_state_en & io.axi.r.bits.resp(1, 0).orR // buffer error flag if return has Error ( ECC )
|
||||
}
|
||||
}
|
||||
buf_state := withClock(ahb_clk){RegEnable(buf_nxtstate,0.U,buf_state_en.asBool())}
|
||||
buf_state := rvdffs_fpga(buf_nxtstate,buf_state_en.asBool(),bus_clk,io.bus_clk_en,clock)
|
||||
|
||||
master_wstrb := (Fill(8,ahb_hsize_q(2,0) === 0.U) & (1.U << ahb_haddr_q(2,0)).asUInt()) |
|
||||
(Fill(8,ahb_hsize_q(2,0) === 1.U) & (3.U << ahb_haddr_q(2,0)).asUInt()) |
|
||||
|
|
@ -114,43 +113,42 @@ class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset {
|
|||
(ahb_hresp_q & !ahb_hready_q)
|
||||
|
||||
// Buffer signals - needed for the read data and ECC error response
|
||||
buf_rdata := withClock(buf_rdata_clk){RegNext(io.axi.r.bits.data,0.U)}
|
||||
buf_read_error := withClock(ahb_clk){RegNext(buf_read_error_in,0.U)}
|
||||
buf_rdata := rvdff_fpga(io.axi.r.bits.data,buf_rdata_clk,buf_rdata_clk_en,clock)
|
||||
buf_read_error := rvdff_fpga(buf_read_error_in,bus_clk,io.bus_clk_en,clock)
|
||||
|
||||
// All the Master signals are captured before presenting it to the command buffer. We check for Hresp before sending it to the cmd buffer.
|
||||
ahb_hresp_q := withClock(ahb_clk){RegNext(io.ahb.sig.in.hresp,0.U)}
|
||||
ahb_hready_q := withClock(ahb_clk){RegNext(ahb_hready,0.U)}
|
||||
ahb_htrans_q := withClock(ahb_clk){RegNext(ahb_htrans_in,0.U)}
|
||||
ahb_hsize_q := withClock(ahb_addr_clk){RegNext(io.ahb.sig.out.hsize,0.U)}
|
||||
ahb_hwrite_q := withClock(ahb_addr_clk){RegNext(io.ahb.sig.out.hwrite,0.U)}
|
||||
ahb_haddr_q := withClock(ahb_addr_clk){RegNext(io.ahb.sig.out.haddr,0.U)}
|
||||
ahb_hresp_q := rvdff_fpga (io.ahb.sig.in.hresp,bus_clk,io.bus_clk_en,clock)
|
||||
ahb_hready_q := rvdff_fpga (ahb_hready,bus_clk,io.bus_clk_en,clock)
|
||||
ahb_htrans_q := rvdff_fpga (ahb_htrans_in,bus_clk,io.bus_clk_en,clock)
|
||||
ahb_hsize_q := rvdff_fpga (io.ahb.sig.out.hsize,ahb_addr_clk,ahb_addr_clk_en,clock)
|
||||
ahb_hwrite_q := rvdff_fpga (io.ahb.sig.out.hwrite,ahb_addr_clk,ahb_addr_clk_en,clock)
|
||||
ahb_haddr_q := rvdff_fpga (io.ahb.sig.out.haddr,ahb_addr_clk,ahb_addr_clk_en,clock)
|
||||
|
||||
// Clock header logic
|
||||
ahb_bus_addr_clk_en := io.bus_clk_en & (ahb_hready & io.ahb.sig.out.htrans(1))
|
||||
buf_rdata_clk_en := io.bus_clk_en & buf_rdata_en;
|
||||
|
||||
ahb_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
|
||||
ahb_addr_clk := rvclkhdr(clock, ahb_bus_addr_clk_en, io.scan_mode)
|
||||
buf_rdata_clk := rvclkhdr(clock, buf_rdata_clk_en, io.scan_mode)
|
||||
ahb_addr_clk_en := io.bus_clk_en & (ahb_hready & io.ahb.sig.out.htrans(1))
|
||||
buf_rdata_clk_en := io.bus_clk_en & buf_rdata_en
|
||||
|
||||
if(RV_FPGA_OPTIMIZE){
|
||||
bus_clk := 0.B.asClock()
|
||||
ahb_addr_clk := 0.B.asClock()
|
||||
buf_rdata_clk := 0.B.asClock()
|
||||
}
|
||||
else {
|
||||
bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
|
||||
ahb_addr_clk := rvclkhdr(clock, ahb_addr_clk_en, io.scan_mode)
|
||||
buf_rdata_clk := rvclkhdr(clock, buf_rdata_clk_en, io.scan_mode)
|
||||
}
|
||||
cmdbuf_rst := (((io.axi.aw.valid & io.axi.aw.ready) | (io.axi.ar.valid & io.axi.ar.ready)) & !cmdbuf_wr_en) | (io.ahb.sig.in.hresp & !cmdbuf_write)
|
||||
cmdbuf_full := (cmdbuf_vld & !((io.axi.aw.valid & io.axi.aw.ready) | (io.axi.ar.valid & io.axi.ar.ready)))
|
||||
//rvdffsc
|
||||
cmdbuf_vld := withClock(bus_clk) {RegNext((Mux(cmdbuf_wr_en.asBool(),"b1".U,cmdbuf_vld) & !cmdbuf_rst), 0.U)}
|
||||
|
||||
cmdbuf_vld := rvdffsc_fpga("b1".U,cmdbuf_wr_en.asBool(),cmdbuf_rst,bus_clk,io.bus_clk_en,clock)
|
||||
//dffs
|
||||
cmdbuf_write := withClock(bus_clk) {
|
||||
RegEnable(ahb_hwrite_q, 0.U, cmdbuf_wr_en.asBool())}
|
||||
|
||||
cmdbuf_size := withClock(bus_clk) {
|
||||
RegEnable(ahb_hsize_q, 0.U, cmdbuf_wr_en.asBool())}
|
||||
|
||||
cmdbuf_wstrb := withClock(bus_clk) {
|
||||
RegEnable(master_wstrb, 0.U, cmdbuf_wr_en.asBool())}
|
||||
|
||||
cmdbuf_write := rvdffs_fpga(ahb_hwrite_q, cmdbuf_wr_en.asBool(),bus_clk,io.bus_clk_en,clock)
|
||||
cmdbuf_size := rvdffs_fpga(ahb_hsize_q, cmdbuf_wr_en.asBool(),bus_clk,io.bus_clk_en,clock)
|
||||
cmdbuf_wstrb := rvdffs_fpga(master_wstrb, cmdbuf_wr_en.asBool(),bus_clk,io.bus_clk_en,clock)
|
||||
//rvdffe
|
||||
cmdbuf_addr := rvdffe(ahb_haddr_q, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode)
|
||||
cmdbuf_wdata := rvdffe(io.ahb.sig.out.hwdata, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode)
|
||||
cmdbuf_addr := rvdffe(ahb_haddr_q, cmdbuf_wr_en.asBool()& io.bus_clk_en,clock,io.scan_mode)
|
||||
cmdbuf_wdata := rvdffe(io.ahb.sig.out.hwdata, cmdbuf_wr_en.asBool()& io.bus_clk_en,clock,io.scan_mode)
|
||||
|
||||
// AXI Write Command Channel
|
||||
io.axi.aw.valid := cmdbuf_vld & cmdbuf_write
|
||||
|
|
@ -177,9 +175,8 @@ class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset {
|
|||
io.axi.ar.bits.burst := "b01".U
|
||||
// AXI Read Response Channel - Always ready as AHB reads are blocking and the the buffer is available for the read coming back always.
|
||||
io.axi.r.ready := true.B
|
||||
bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
|
||||
}
|
||||
|
||||
//object ahb_to_axi4 extends App {
|
||||
// println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4(3)))
|
||||
//}
|
||||
object ahb_to_axi4 extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4(1)))
|
||||
}
|
||||
|
|
@ -384,6 +384,15 @@ trait lib extends param{
|
|||
else withClock(clk) {RegEnable (din, 0.U,en)}
|
||||
}
|
||||
}
|
||||
object rvdffsc_fpga {
|
||||
def apply(din: UInt, en:Bool,clear: UInt, clk: Clock, clken: Bool,rawclk:Clock):UInt = {
|
||||
val dout =Wire(UInt())
|
||||
if (RV_FPGA_OPTIMIZE)
|
||||
dout := withClock (rawclk) {RegEnable ((din & Fill(clear.getWidth,!clear)) , 0.U, ((en|clear)& clken))}
|
||||
else dout := withClock(clk) {RegNext (Mux(en,din,dout) & !clear, 0.U)}
|
||||
dout
|
||||
}
|
||||
}
|
||||
////rvdffe ///////////////////////////////////////////////////////////////////////
|
||||
object rvdffe {
|
||||
def apply(din: UInt, en: Bool, clk: Clock, scan_mode: Bool): UInt = {
|
||||
|
|
|
|||
|
|
@ -132,7 +132,7 @@ trait param {
|
|||
val INST_ACCESS_MASK5 = 0xFFFFFFFF
|
||||
val INST_ACCESS_MASK6 = 0xFFFFFFFF
|
||||
val INST_ACCESS_MASK7 = 0xFFFFFFFF
|
||||
val LOAD_TO_USE_PLUS1 = 0x1
|
||||
val LOAD_TO_USE_PLUS1 = 0x0
|
||||
val LSU2DMA = 0x0
|
||||
val LSU_BUS_ID = 0x1
|
||||
val LSU_BUS_PRTY = 0x2
|
||||
|
|
|
|||
|
|
@ -103,6 +103,7 @@ class lsu extends Module with RequireAsyncReset with param with lib {
|
|||
// Indicates non-idle if there is a instruction valid in d-r or read/write buffers are non-empty since they can come with error
|
||||
// Store buffer now have only non-dma dccm stores
|
||||
// stbuf_empty not needed since it has only dccm stores
|
||||
|
||||
io.lsu_idle_any := !((lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma) | (lsu_lsc_ctl.io.lsu_pkt_r.valid & !lsu_lsc_ctl.io.lsu_pkt_r.bits.dma)) & bus_intf.io.lsu_bus_buffer_empty_any
|
||||
io.lsu_active := (lsu_lsc_ctl.io.lsu_pkt_m.valid | lsu_lsc_ctl.io.lsu_pkt_r.valid | dccm_ctl.io.ld_single_ecc_error_r_ff) | !bus_intf.io.lsu_bus_buffer_empty_any // This includes DMA. Used for gating top clock
|
||||
// Instantiate the store buffer
|
||||
|
|
|
|||
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Loading…
Reference in New Issue