diff --git a/el2_exu.anno.json b/el2_exu.anno.json new file mode 100644 index 00000000..ea719386 --- /dev/null +++ b/el2_exu.anno.json @@ -0,0 +1,131 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_exu|el2_exu>io_exu_div_wren", + "sources":[ + "~el2_exu|el2_exu>io_dec_div_cancel" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_exu|el2_exu>io_exu_mp_fghr", + "sources":[ + "~el2_exu|el2_exu>io_dec_tlu_flush_lower_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_exu|el2_exu>io_exu_lsu_rs1_d", + "sources":[ + "~el2_exu|el2_exu>io_gpr_i0_rs1_d", + "~el2_exu|el2_exu>io_dec_extint_stall", + "~el2_exu|el2_exu>io_dec_tlu_meihap", + "~el2_exu|el2_exu>io_dec_i0_rs1_en_d", + "~el2_exu|el2_exu>io_dec_i0_rs1_bypass_data_d", + "~el2_exu|el2_exu>io_exu_i0_result_x", + "~el2_exu|el2_exu>io_dec_i0_rs1_bypass_en_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_exu|el2_exu>io_exu_flush_final", + "sources":[ + "~el2_exu|el2_exu>io_dec_tlu_flush_lower_r", + "~el2_exu|el2_exu>io_dec_i0_alu_decode_d", + "~el2_exu|el2_exu>io_i0_ap_jal", + "~el2_exu|el2_exu>io_i0_ap_predict_t", + "~el2_exu|el2_exu>io_i0_ap_predict_nt", + "~el2_exu|el2_exu>io_i0_ap_bge", + "~el2_exu|el2_exu>io_i0_ap_sub", + "~el2_exu|el2_exu>io_i0_ap_blt", + "~el2_exu|el2_exu>io_i0_ap_beq", + "~el2_exu|el2_exu>io_i0_ap_bne", + "~el2_exu|el2_exu>io_i0_ap_unsign", + "~el2_exu|el2_exu>io_dec_i0_predict_p_d_pret", + "~el2_exu|el2_exu>io_dec_i0_predict_p_d_prett", + "~el2_exu|el2_exu>io_dec_i0_predict_p_d_pja", + "~el2_exu|el2_exu>io_dec_i0_predict_p_d_pcall", + "~el2_exu|el2_exu>io_gpr_i0_rs1_d", + "~el2_exu|el2_exu>io_gpr_i0_rs2_d", + "~el2_exu|el2_exu>io_dec_i0_immed_d", + "~el2_exu|el2_exu>io_dbg_cmd_wrdata", + "~el2_exu|el2_exu>io_dec_i0_rs1_en_d", + "~el2_exu|el2_exu>io_dec_i0_rs2_en_d", + "~el2_exu|el2_exu>io_dec_i0_rs2_bypass_en_d", + "~el2_exu|el2_exu>io_dec_i0_rs2_bypass_data_d", + "~el2_exu|el2_exu>io_exu_i0_result_x", + "~el2_exu|el2_exu>io_dec_i0_pc_d", + "~el2_exu|el2_exu>io_dec_debug_wdata_rs1_d", + "~el2_exu|el2_exu>io_dec_i0_select_pc_d", + "~el2_exu|el2_exu>io_dec_i0_rs1_bypass_en_d", + "~el2_exu|el2_exu>io_dec_i0_rs1_bypass_data_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_exu|el2_exu>io_exu_flush_path_final", + "sources":[ + "~el2_exu|el2_exu>io_dec_tlu_flush_path_r", + "~el2_exu|el2_exu>io_dec_tlu_flush_lower_r", + "~el2_exu|el2_exu>io_i0_ap_jal", + "~el2_exu|el2_exu>io_i0_ap_sub", + "~el2_exu|el2_exu>io_dec_i0_pc_d", + "~el2_exu|el2_exu>io_dec_i0_br_immed_d", + "~el2_exu|el2_exu>io_dec_i0_predict_p_d_pret", + "~el2_exu|el2_exu>io_dec_i0_predict_p_d_pja", + "~el2_exu|el2_exu>io_dec_i0_predict_p_d_pcall", + "~el2_exu|el2_exu>io_gpr_i0_rs2_d", + "~el2_exu|el2_exu>io_dec_i0_immed_d", + "~el2_exu|el2_exu>io_gpr_i0_rs1_d", + "~el2_exu|el2_exu>io_dbg_cmd_wrdata", + "~el2_exu|el2_exu>io_dec_i0_rs2_en_d", + "~el2_exu|el2_exu>io_dec_i0_rs2_bypass_en_d", + "~el2_exu|el2_exu>io_dec_i0_rs2_bypass_data_d", + "~el2_exu|el2_exu>io_exu_i0_result_x", + "~el2_exu|el2_exu>io_dec_i0_rs1_en_d", + "~el2_exu|el2_exu>io_dec_debug_wdata_rs1_d", + "~el2_exu|el2_exu>io_dec_i0_select_pc_d", + "~el2_exu|el2_exu>io_dec_i0_rs1_bypass_en_d", + "~el2_exu|el2_exu>io_dec_i0_rs1_bypass_data_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_exu|el2_exu>io_exu_lsu_rs2_d", + "sources":[ + "~el2_exu|el2_exu>io_gpr_i0_rs2_d", + "~el2_exu|el2_exu>io_dec_i0_rs2_en_d", + "~el2_exu|el2_exu>io_dec_extint_stall", + "~el2_exu|el2_exu>io_dec_i0_rs2_bypass_data_d", + "~el2_exu|el2_exu>io_exu_i0_result_x", + "~el2_exu|el2_exu>io_dec_i0_rs2_bypass_en_d" + ] + }, + { + "class":"logger.LogLevelAnnotation", + "globalLogLevel":{ + + } + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"el2_exu.TEC_RV_ICG", + "resourceId":"/vsrc/TEC_RV_ICG.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_exu" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_exu.fir b/el2_exu.fir new file mode 100644 index 00000000..cc4c0103 --- /dev/null +++ b/el2_exu.fir @@ -0,0 +1,3670 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_exu : + extmodule TEC_RV_ICG : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_1 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_2 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_3 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_4 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_5 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_6 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_7 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_8 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_9 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_10 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_11 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_12 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_12 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_12 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_13 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_13 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_13 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_14 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_14 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_14 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_15 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_15 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_15 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_16 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_16 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_16 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_17 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_17 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_17 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_18 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_18 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_18 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_19 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_19 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_19 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + module el2_exu_alu_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip flush_lower_r : UInt<1>, flip enable : UInt<1>, flip valid_in : UInt<1>, flip ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip csr_ren_in : UInt<1>, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pc_in : UInt<31>, flip pp_in : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, flip brimm_in : UInt<12>, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pc_ff : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}} + + node _T = bits(io.scan_mode, 0, 0) @[el2_exu_alu_ctl.scala 35:60] + inst rvclkhdr of rvclkhdr_18 @[el2_lib.scala 508:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= io.enable @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= _T @[el2_lib.scala 512:24] + reg _T_1 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1 <= io.pc_in @[el2_lib.scala 514:16] + io.pc_ff <= _T_1 @[el2_exu_alu_ctl.scala 35:12] + wire result : UInt<32> + result <= UInt<1>("h00") + node _T_2 = bits(io.scan_mode, 0, 0) @[el2_exu_alu_ctl.scala 37:62] + inst rvclkhdr_1 of rvclkhdr_19 @[el2_lib.scala 508:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= io.enable @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= _T_2 @[el2_lib.scala 512:24] + reg _T_3 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_3 <= result @[el2_lib.scala 514:16] + io.result_ff <= _T_3 @[el2_exu_alu_ctl.scala 37:16] + node _T_4 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 39:29] + node _T_5 = not(io.b_in) @[el2_exu_alu_ctl.scala 39:37] + node bm = mux(_T_4, _T_5, io.b_in) @[el2_exu_alu_ctl.scala 39:17] + wire aout : UInt<33> + aout <= UInt<1>("h00") + node _T_6 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 42:25] + node _T_7 = asUInt(io.a_in) @[Cat.scala 29:58] + node _T_8 = cat(UInt<1>("h00"), _T_7) @[Cat.scala 29:58] + node _T_9 = not(io.b_in) @[el2_exu_alu_ctl.scala 42:70] + node _T_10 = cat(UInt<1>("h00"), _T_9) @[Cat.scala 29:58] + node _T_11 = add(_T_8, _T_10) @[el2_exu_alu_ctl.scala 42:55] + node _T_12 = tail(_T_11, 1) @[el2_exu_alu_ctl.scala 42:55] + node _T_13 = cat(UInt<32>("h00"), io.ap.sub) @[Cat.scala 29:58] + node _T_14 = add(_T_12, _T_13) @[el2_exu_alu_ctl.scala 42:80] + node _T_15 = tail(_T_14, 1) @[el2_exu_alu_ctl.scala 42:80] + node _T_16 = asUInt(io.a_in) @[Cat.scala 29:58] + node _T_17 = cat(UInt<1>("h00"), _T_16) @[Cat.scala 29:58] + node _T_18 = cat(UInt<1>("h00"), io.b_in) @[Cat.scala 29:58] + node _T_19 = add(_T_17, _T_18) @[el2_exu_alu_ctl.scala 42:132] + node _T_20 = tail(_T_19, 1) @[el2_exu_alu_ctl.scala 42:132] + node _T_21 = cat(UInt<32>("h00"), io.ap.sub) @[Cat.scala 29:58] + node _T_22 = add(_T_20, _T_21) @[el2_exu_alu_ctl.scala 42:157] + node _T_23 = tail(_T_22, 1) @[el2_exu_alu_ctl.scala 42:157] + node _T_24 = mux(_T_6, _T_15, _T_23) @[el2_exu_alu_ctl.scala 42:14] + aout <= _T_24 @[el2_exu_alu_ctl.scala 42:8] + node cout = bits(aout, 32, 32) @[el2_exu_alu_ctl.scala 43:18] + node _T_25 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 45:22] + node _T_26 = not(_T_25) @[el2_exu_alu_ctl.scala 45:14] + node _T_27 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:32] + node _T_28 = not(_T_27) @[el2_exu_alu_ctl.scala 45:29] + node _T_29 = and(_T_26, _T_28) @[el2_exu_alu_ctl.scala 45:27] + node _T_30 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:44] + node _T_31 = and(_T_29, _T_30) @[el2_exu_alu_ctl.scala 45:37] + node _T_32 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 45:61] + node _T_33 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:71] + node _T_34 = and(_T_32, _T_33) @[el2_exu_alu_ctl.scala 45:66] + node _T_35 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:83] + node _T_36 = not(_T_35) @[el2_exu_alu_ctl.scala 45:78] + node _T_37 = and(_T_34, _T_36) @[el2_exu_alu_ctl.scala 45:76] + node ov = or(_T_31, _T_37) @[el2_exu_alu_ctl.scala 45:50] + node _T_38 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 47:50] + node eq = eq(io.a_in, _T_38) @[el2_exu_alu_ctl.scala 47:38] + node ne = not(eq) @[el2_exu_alu_ctl.scala 48:29] + node neg = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 49:34] + node _T_39 = not(io.ap.unsign) @[el2_exu_alu_ctl.scala 50:30] + node _T_40 = xor(neg, ov) @[el2_exu_alu_ctl.scala 50:51] + node _T_41 = and(_T_39, _T_40) @[el2_exu_alu_ctl.scala 50:44] + node _T_42 = not(cout) @[el2_exu_alu_ctl.scala 50:78] + node _T_43 = and(io.ap.unsign, _T_42) @[el2_exu_alu_ctl.scala 50:76] + node lt = or(_T_41, _T_43) @[el2_exu_alu_ctl.scala 50:58] + node ge = not(lt) @[el2_exu_alu_ctl.scala 51:29] + node _T_44 = bits(io.csr_ren_in, 0, 0) @[el2_exu_alu_ctl.scala 55:19] + node _T_45 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 55:50] + node _T_46 = bits(io.ap.land, 0, 0) @[el2_exu_alu_ctl.scala 56:16] + node _T_47 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 56:50] + node _T_48 = and(io.a_in, _T_47) @[el2_exu_alu_ctl.scala 56:39] + node _T_49 = asSInt(_T_48) @[el2_exu_alu_ctl.scala 56:39] + node _T_50 = bits(io.ap.lor, 0, 0) @[el2_exu_alu_ctl.scala 57:15] + node _T_51 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 57:50] + node _T_52 = or(io.a_in, _T_51) @[el2_exu_alu_ctl.scala 57:39] + node _T_53 = asSInt(_T_52) @[el2_exu_alu_ctl.scala 57:39] + node _T_54 = bits(io.ap.lxor, 0, 0) @[el2_exu_alu_ctl.scala 58:16] + node _T_55 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 58:50] + node _T_56 = xor(io.a_in, _T_55) @[el2_exu_alu_ctl.scala 58:39] + node _T_57 = asSInt(_T_56) @[el2_exu_alu_ctl.scala 58:39] + wire _T_58 : SInt<32> @[Mux.scala 27:72] + node _T_59 = asUInt(_T_45) @[Mux.scala 27:72] + node _T_60 = asSInt(_T_59) @[Mux.scala 27:72] + _T_58 <= _T_60 @[Mux.scala 27:72] + wire _T_61 : SInt<32> @[Mux.scala 27:72] + node _T_62 = asUInt(_T_49) @[Mux.scala 27:72] + node _T_63 = asSInt(_T_62) @[Mux.scala 27:72] + _T_61 <= _T_63 @[Mux.scala 27:72] + wire _T_64 : SInt<32> @[Mux.scala 27:72] + node _T_65 = asUInt(_T_53) @[Mux.scala 27:72] + node _T_66 = asSInt(_T_65) @[Mux.scala 27:72] + _T_64 <= _T_66 @[Mux.scala 27:72] + wire _T_67 : SInt<32> @[Mux.scala 27:72] + node _T_68 = asUInt(_T_57) @[Mux.scala 27:72] + node _T_69 = asSInt(_T_68) @[Mux.scala 27:72] + _T_67 <= _T_69 @[Mux.scala 27:72] + node _T_70 = mux(_T_44, _T_58, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72] + node _T_71 = mux(_T_46, _T_61, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72] + node _T_72 = mux(_T_50, _T_64, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72] + node _T_73 = mux(_T_54, _T_67, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72] + node _T_74 = or(_T_70, _T_71) @[Mux.scala 27:72] + node _T_75 = asSInt(_T_74) @[Mux.scala 27:72] + node _T_76 = or(_T_75, _T_72) @[Mux.scala 27:72] + node _T_77 = asSInt(_T_76) @[Mux.scala 27:72] + node _T_78 = or(_T_77, _T_73) @[Mux.scala 27:72] + node _T_79 = asSInt(_T_78) @[Mux.scala 27:72] + wire lout : SInt<32> @[Mux.scala 27:72] + node _T_80 = asUInt(_T_79) @[Mux.scala 27:72] + node _T_81 = asSInt(_T_80) @[Mux.scala 27:72] + lout <= _T_81 @[Mux.scala 27:72] + node _T_82 = bits(io.ap.sll, 0, 0) @[el2_exu_alu_ctl.scala 61:15] + node _T_83 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 61:60] + node _T_84 = cat(UInt<1>("h00"), _T_83) @[Cat.scala 29:58] + node _T_85 = sub(UInt<6>("h020"), _T_84) @[el2_exu_alu_ctl.scala 61:38] + node _T_86 = tail(_T_85, 1) @[el2_exu_alu_ctl.scala 61:38] + node _T_87 = bits(io.ap.srl, 0, 0) @[el2_exu_alu_ctl.scala 62:15] + node _T_88 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 62:60] + node _T_89 = cat(UInt<1>("h00"), _T_88) @[Cat.scala 29:58] + node _T_90 = bits(io.ap.sra, 0, 0) @[el2_exu_alu_ctl.scala 63:15] + node _T_91 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 63:60] + node _T_92 = cat(UInt<1>("h00"), _T_91) @[Cat.scala 29:58] + node _T_93 = mux(_T_82, _T_86, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_94 = mux(_T_87, _T_89, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_95 = mux(_T_90, _T_92, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_96 = or(_T_93, _T_94) @[Mux.scala 27:72] + node _T_97 = or(_T_96, _T_95) @[Mux.scala 27:72] + wire shift_amount : UInt<6> @[Mux.scala 27:72] + shift_amount <= _T_97 @[Mux.scala 27:72] + wire shift_mask : UInt<32> + shift_mask <= UInt<1>("h00") + wire _T_98 : UInt<1>[5] @[el2_lib.scala 161:48] + _T_98[0] <= io.ap.sll @[el2_lib.scala 161:48] + _T_98[1] <= io.ap.sll @[el2_lib.scala 161:48] + _T_98[2] <= io.ap.sll @[el2_lib.scala 161:48] + _T_98[3] <= io.ap.sll @[el2_lib.scala 161:48] + _T_98[4] <= io.ap.sll @[el2_lib.scala 161:48] + node _T_99 = cat(_T_98[0], _T_98[1]) @[Cat.scala 29:58] + node _T_100 = cat(_T_99, _T_98[2]) @[Cat.scala 29:58] + node _T_101 = cat(_T_100, _T_98[3]) @[Cat.scala 29:58] + node _T_102 = cat(_T_101, _T_98[4]) @[Cat.scala 29:58] + node _T_103 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 66:70] + node _T_104 = and(_T_102, _T_103) @[el2_exu_alu_ctl.scala 66:61] + node _T_105 = dshl(UInt<32>("h0ffffffff"), _T_104) @[el2_exu_alu_ctl.scala 66:39] + shift_mask <= _T_105 @[el2_exu_alu_ctl.scala 66:14] + wire shift_extend : UInt<63> + shift_extend <= UInt<1>("h00") + wire _T_106 : UInt<1>[31] @[el2_lib.scala 161:48] + _T_106[0] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[1] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[2] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[3] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[4] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[5] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[6] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[7] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[8] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[9] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[10] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[11] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[12] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[13] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[14] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[15] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[16] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[17] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[18] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[19] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[20] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[21] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[22] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[23] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[24] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[25] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[26] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[27] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[28] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[29] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[30] <= io.ap.sra @[el2_lib.scala 161:48] + node _T_107 = cat(_T_106[0], _T_106[1]) @[Cat.scala 29:58] + node _T_108 = cat(_T_107, _T_106[2]) @[Cat.scala 29:58] + node _T_109 = cat(_T_108, _T_106[3]) @[Cat.scala 29:58] + node _T_110 = cat(_T_109, _T_106[4]) @[Cat.scala 29:58] + node _T_111 = cat(_T_110, _T_106[5]) @[Cat.scala 29:58] + node _T_112 = cat(_T_111, _T_106[6]) @[Cat.scala 29:58] + node _T_113 = cat(_T_112, _T_106[7]) @[Cat.scala 29:58] + node _T_114 = cat(_T_113, _T_106[8]) @[Cat.scala 29:58] + node _T_115 = cat(_T_114, _T_106[9]) @[Cat.scala 29:58] + node _T_116 = cat(_T_115, _T_106[10]) @[Cat.scala 29:58] + node _T_117 = cat(_T_116, _T_106[11]) @[Cat.scala 29:58] + node _T_118 = cat(_T_117, _T_106[12]) @[Cat.scala 29:58] + node _T_119 = cat(_T_118, _T_106[13]) @[Cat.scala 29:58] + node _T_120 = cat(_T_119, _T_106[14]) @[Cat.scala 29:58] + node _T_121 = cat(_T_120, _T_106[15]) @[Cat.scala 29:58] + node _T_122 = cat(_T_121, _T_106[16]) @[Cat.scala 29:58] + node _T_123 = cat(_T_122, _T_106[17]) @[Cat.scala 29:58] + node _T_124 = cat(_T_123, _T_106[18]) @[Cat.scala 29:58] + node _T_125 = cat(_T_124, _T_106[19]) @[Cat.scala 29:58] + node _T_126 = cat(_T_125, _T_106[20]) @[Cat.scala 29:58] + node _T_127 = cat(_T_126, _T_106[21]) @[Cat.scala 29:58] + node _T_128 = cat(_T_127, _T_106[22]) @[Cat.scala 29:58] + node _T_129 = cat(_T_128, _T_106[23]) @[Cat.scala 29:58] + node _T_130 = cat(_T_129, _T_106[24]) @[Cat.scala 29:58] + node _T_131 = cat(_T_130, _T_106[25]) @[Cat.scala 29:58] + node _T_132 = cat(_T_131, _T_106[26]) @[Cat.scala 29:58] + node _T_133 = cat(_T_132, _T_106[27]) @[Cat.scala 29:58] + node _T_134 = cat(_T_133, _T_106[28]) @[Cat.scala 29:58] + node _T_135 = cat(_T_134, _T_106[29]) @[Cat.scala 29:58] + node _T_136 = cat(_T_135, _T_106[30]) @[Cat.scala 29:58] + node _T_137 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 69:61] + wire _T_138 : UInt<1>[31] @[el2_lib.scala 161:48] + _T_138[0] <= _T_137 @[el2_lib.scala 161:48] + _T_138[1] <= _T_137 @[el2_lib.scala 161:48] + _T_138[2] <= _T_137 @[el2_lib.scala 161:48] + _T_138[3] <= _T_137 @[el2_lib.scala 161:48] + _T_138[4] <= _T_137 @[el2_lib.scala 161:48] + _T_138[5] <= _T_137 @[el2_lib.scala 161:48] + _T_138[6] <= _T_137 @[el2_lib.scala 161:48] + _T_138[7] <= _T_137 @[el2_lib.scala 161:48] + _T_138[8] <= _T_137 @[el2_lib.scala 161:48] + _T_138[9] <= _T_137 @[el2_lib.scala 161:48] + _T_138[10] <= _T_137 @[el2_lib.scala 161:48] + _T_138[11] <= _T_137 @[el2_lib.scala 161:48] + _T_138[12] <= _T_137 @[el2_lib.scala 161:48] + _T_138[13] <= _T_137 @[el2_lib.scala 161:48] + _T_138[14] <= _T_137 @[el2_lib.scala 161:48] + _T_138[15] <= _T_137 @[el2_lib.scala 161:48] + _T_138[16] <= _T_137 @[el2_lib.scala 161:48] + _T_138[17] <= _T_137 @[el2_lib.scala 161:48] + _T_138[18] <= _T_137 @[el2_lib.scala 161:48] + _T_138[19] <= _T_137 @[el2_lib.scala 161:48] + _T_138[20] <= _T_137 @[el2_lib.scala 161:48] + _T_138[21] <= _T_137 @[el2_lib.scala 161:48] + _T_138[22] <= _T_137 @[el2_lib.scala 161:48] + _T_138[23] <= _T_137 @[el2_lib.scala 161:48] + _T_138[24] <= _T_137 @[el2_lib.scala 161:48] + _T_138[25] <= _T_137 @[el2_lib.scala 161:48] + _T_138[26] <= _T_137 @[el2_lib.scala 161:48] + _T_138[27] <= _T_137 @[el2_lib.scala 161:48] + _T_138[28] <= _T_137 @[el2_lib.scala 161:48] + _T_138[29] <= _T_137 @[el2_lib.scala 161:48] + _T_138[30] <= _T_137 @[el2_lib.scala 161:48] + node _T_139 = cat(_T_138[0], _T_138[1]) @[Cat.scala 29:58] + node _T_140 = cat(_T_139, _T_138[2]) @[Cat.scala 29:58] + node _T_141 = cat(_T_140, _T_138[3]) @[Cat.scala 29:58] + node _T_142 = cat(_T_141, _T_138[4]) @[Cat.scala 29:58] + node _T_143 = cat(_T_142, _T_138[5]) @[Cat.scala 29:58] + node _T_144 = cat(_T_143, _T_138[6]) @[Cat.scala 29:58] + node _T_145 = cat(_T_144, _T_138[7]) @[Cat.scala 29:58] + node _T_146 = cat(_T_145, _T_138[8]) @[Cat.scala 29:58] + node _T_147 = cat(_T_146, _T_138[9]) @[Cat.scala 29:58] + node _T_148 = cat(_T_147, _T_138[10]) @[Cat.scala 29:58] + node _T_149 = cat(_T_148, _T_138[11]) @[Cat.scala 29:58] + node _T_150 = cat(_T_149, _T_138[12]) @[Cat.scala 29:58] + node _T_151 = cat(_T_150, _T_138[13]) @[Cat.scala 29:58] + node _T_152 = cat(_T_151, _T_138[14]) @[Cat.scala 29:58] + node _T_153 = cat(_T_152, _T_138[15]) @[Cat.scala 29:58] + node _T_154 = cat(_T_153, _T_138[16]) @[Cat.scala 29:58] + node _T_155 = cat(_T_154, _T_138[17]) @[Cat.scala 29:58] + node _T_156 = cat(_T_155, _T_138[18]) @[Cat.scala 29:58] + node _T_157 = cat(_T_156, _T_138[19]) @[Cat.scala 29:58] + node _T_158 = cat(_T_157, _T_138[20]) @[Cat.scala 29:58] + node _T_159 = cat(_T_158, _T_138[21]) @[Cat.scala 29:58] + node _T_160 = cat(_T_159, _T_138[22]) @[Cat.scala 29:58] + node _T_161 = cat(_T_160, _T_138[23]) @[Cat.scala 29:58] + node _T_162 = cat(_T_161, _T_138[24]) @[Cat.scala 29:58] + node _T_163 = cat(_T_162, _T_138[25]) @[Cat.scala 29:58] + node _T_164 = cat(_T_163, _T_138[26]) @[Cat.scala 29:58] + node _T_165 = cat(_T_164, _T_138[27]) @[Cat.scala 29:58] + node _T_166 = cat(_T_165, _T_138[28]) @[Cat.scala 29:58] + node _T_167 = cat(_T_166, _T_138[29]) @[Cat.scala 29:58] + node _T_168 = cat(_T_167, _T_138[30]) @[Cat.scala 29:58] + node _T_169 = and(_T_136, _T_168) @[el2_exu_alu_ctl.scala 69:44] + wire _T_170 : UInt<1>[31] @[el2_lib.scala 161:48] + _T_170[0] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[1] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[2] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[3] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[4] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[5] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[6] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[7] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[8] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[9] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[10] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[11] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[12] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[13] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[14] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[15] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[16] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[17] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[18] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[19] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[20] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[21] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[22] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[23] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[24] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[25] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[26] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[27] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[28] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[29] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[30] <= io.ap.sll @[el2_lib.scala 161:48] + node _T_171 = cat(_T_170[0], _T_170[1]) @[Cat.scala 29:58] + node _T_172 = cat(_T_171, _T_170[2]) @[Cat.scala 29:58] + node _T_173 = cat(_T_172, _T_170[3]) @[Cat.scala 29:58] + node _T_174 = cat(_T_173, _T_170[4]) @[Cat.scala 29:58] + node _T_175 = cat(_T_174, _T_170[5]) @[Cat.scala 29:58] + node _T_176 = cat(_T_175, _T_170[6]) @[Cat.scala 29:58] + node _T_177 = cat(_T_176, _T_170[7]) @[Cat.scala 29:58] + node _T_178 = cat(_T_177, _T_170[8]) @[Cat.scala 29:58] + node _T_179 = cat(_T_178, _T_170[9]) @[Cat.scala 29:58] + node _T_180 = cat(_T_179, _T_170[10]) @[Cat.scala 29:58] + node _T_181 = cat(_T_180, _T_170[11]) @[Cat.scala 29:58] + node _T_182 = cat(_T_181, _T_170[12]) @[Cat.scala 29:58] + node _T_183 = cat(_T_182, _T_170[13]) @[Cat.scala 29:58] + node _T_184 = cat(_T_183, _T_170[14]) @[Cat.scala 29:58] + node _T_185 = cat(_T_184, _T_170[15]) @[Cat.scala 29:58] + node _T_186 = cat(_T_185, _T_170[16]) @[Cat.scala 29:58] + node _T_187 = cat(_T_186, _T_170[17]) @[Cat.scala 29:58] + node _T_188 = cat(_T_187, _T_170[18]) @[Cat.scala 29:58] + node _T_189 = cat(_T_188, _T_170[19]) @[Cat.scala 29:58] + node _T_190 = cat(_T_189, _T_170[20]) @[Cat.scala 29:58] + node _T_191 = cat(_T_190, _T_170[21]) @[Cat.scala 29:58] + node _T_192 = cat(_T_191, _T_170[22]) @[Cat.scala 29:58] + node _T_193 = cat(_T_192, _T_170[23]) @[Cat.scala 29:58] + node _T_194 = cat(_T_193, _T_170[24]) @[Cat.scala 29:58] + node _T_195 = cat(_T_194, _T_170[25]) @[Cat.scala 29:58] + node _T_196 = cat(_T_195, _T_170[26]) @[Cat.scala 29:58] + node _T_197 = cat(_T_196, _T_170[27]) @[Cat.scala 29:58] + node _T_198 = cat(_T_197, _T_170[28]) @[Cat.scala 29:58] + node _T_199 = cat(_T_198, _T_170[29]) @[Cat.scala 29:58] + node _T_200 = cat(_T_199, _T_170[30]) @[Cat.scala 29:58] + node _T_201 = bits(io.a_in, 30, 0) @[el2_exu_alu_ctl.scala 69:99] + node _T_202 = and(_T_200, _T_201) @[el2_exu_alu_ctl.scala 69:90] + node _T_203 = or(_T_169, _T_202) @[el2_exu_alu_ctl.scala 69:68] + node _T_204 = asUInt(io.a_in) @[Cat.scala 29:58] + node _T_205 = cat(_T_203, _T_204) @[Cat.scala 29:58] + shift_extend <= _T_205 @[el2_exu_alu_ctl.scala 69:16] + wire shift_long : UInt<63> + shift_long <= UInt<1>("h00") + node _T_206 = bits(shift_amount, 4, 0) @[el2_exu_alu_ctl.scala 72:47] + node _T_207 = dshr(shift_extend, _T_206) @[el2_exu_alu_ctl.scala 72:32] + shift_long <= _T_207 @[el2_exu_alu_ctl.scala 72:14] + node _T_208 = bits(shift_long, 31, 0) @[el2_exu_alu_ctl.scala 74:27] + node _T_209 = bits(shift_mask, 31, 0) @[el2_exu_alu_ctl.scala 74:46] + node sout = and(_T_208, _T_209) @[el2_exu_alu_ctl.scala 74:34] + node _T_210 = or(io.ap.sll, io.ap.srl) @[el2_exu_alu_ctl.scala 77:41] + node sel_shift = or(_T_210, io.ap.sra) @[el2_exu_alu_ctl.scala 77:53] + node _T_211 = or(io.ap.add, io.ap.sub) @[el2_exu_alu_ctl.scala 78:41] + node _T_212 = not(io.ap.slt) @[el2_exu_alu_ctl.scala 78:56] + node sel_adder = and(_T_211, _T_212) @[el2_exu_alu_ctl.scala 78:54] + node _T_213 = or(io.ap.jal, io.pp_in.pcall) @[el2_exu_alu_ctl.scala 79:41] + node _T_214 = or(_T_213, io.pp_in.pja) @[el2_exu_alu_ctl.scala 79:58] + node sel_pc = or(_T_214, io.pp_in.pret) @[el2_exu_alu_ctl.scala 79:73] + node _T_215 = bits(io.ap.csr_imm, 0, 0) @[el2_exu_alu_ctl.scala 80:47] + node _T_216 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 80:63] + node csr_write_data = mux(_T_215, _T_216, io.a_in) @[el2_exu_alu_ctl.scala 80:32] + node slt_one = and(io.ap.slt, lt) @[el2_exu_alu_ctl.scala 82:40] + node _T_217 = cat(io.pc_in, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_218 = cat(io.brimm_in, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_219 = bits(_T_217, 12, 1) @[el2_lib.scala 208:24] + node _T_220 = bits(_T_218, 12, 1) @[el2_lib.scala 208:40] + node _T_221 = add(_T_219, _T_220) @[el2_lib.scala 208:31] + node _T_222 = bits(_T_217, 31, 13) @[el2_lib.scala 209:20] + node _T_223 = add(_T_222, UInt<1>("h01")) @[el2_lib.scala 209:27] + node _T_224 = tail(_T_223, 1) @[el2_lib.scala 209:27] + node _T_225 = bits(_T_217, 31, 13) @[el2_lib.scala 210:20] + node _T_226 = sub(_T_225, UInt<1>("h01")) @[el2_lib.scala 210:27] + node _T_227 = tail(_T_226, 1) @[el2_lib.scala 210:27] + node _T_228 = bits(_T_218, 12, 12) @[el2_lib.scala 211:22] + node _T_229 = bits(_T_221, 12, 12) @[el2_lib.scala 212:39] + node _T_230 = eq(_T_229, UInt<1>("h00")) @[el2_lib.scala 212:28] + node _T_231 = xor(_T_228, _T_230) @[el2_lib.scala 212:26] + node _T_232 = bits(_T_231, 0, 0) @[el2_lib.scala 212:64] + node _T_233 = bits(_T_217, 31, 13) @[el2_lib.scala 212:76] + node _T_234 = eq(_T_228, UInt<1>("h00")) @[el2_lib.scala 213:20] + node _T_235 = bits(_T_221, 12, 12) @[el2_lib.scala 213:39] + node _T_236 = and(_T_234, _T_235) @[el2_lib.scala 213:26] + node _T_237 = bits(_T_236, 0, 0) @[el2_lib.scala 213:64] + node _T_238 = bits(_T_221, 12, 12) @[el2_lib.scala 214:39] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_lib.scala 214:28] + node _T_240 = and(_T_228, _T_239) @[el2_lib.scala 214:26] + node _T_241 = bits(_T_240, 0, 0) @[el2_lib.scala 214:64] + node _T_242 = mux(_T_232, _T_233, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_243 = mux(_T_237, _T_224, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_244 = mux(_T_241, _T_227, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_245 = or(_T_242, _T_243) @[Mux.scala 27:72] + node _T_246 = or(_T_245, _T_244) @[Mux.scala 27:72] + wire _T_247 : UInt<19> @[Mux.scala 27:72] + _T_247 <= _T_246 @[Mux.scala 27:72] + node _T_248 = bits(_T_221, 11, 0) @[el2_lib.scala 214:94] + node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58] + node pcout = cat(_T_249, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_250 = bits(lout, 31, 0) @[el2_exu_alu_ctl.scala 88:24] + node _T_251 = cat(UInt<31>("h00"), slt_one) @[Cat.scala 29:58] + node _T_252 = or(_T_250, _T_251) @[el2_exu_alu_ctl.scala 88:31] + node _T_253 = bits(sel_shift, 0, 0) @[el2_exu_alu_ctl.scala 89:15] + node _T_254 = bits(sout, 31, 0) @[el2_exu_alu_ctl.scala 89:41] + node _T_255 = bits(sel_adder, 0, 0) @[el2_exu_alu_ctl.scala 90:15] + node _T_256 = bits(aout, 31, 0) @[el2_exu_alu_ctl.scala 90:41] + node _T_257 = bits(sel_pc, 0, 0) @[el2_exu_alu_ctl.scala 91:12] + node _T_258 = bits(io.ap.csr_write, 0, 0) @[el2_exu_alu_ctl.scala 92:21] + node _T_259 = bits(csr_write_data, 31, 0) @[el2_exu_alu_ctl.scala 92:51] + node _T_260 = mux(_T_253, _T_254, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_261 = mux(_T_255, _T_256, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_262 = mux(_T_257, pcout, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_263 = mux(_T_258, _T_259, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_264 = or(_T_260, _T_261) @[Mux.scala 27:72] + node _T_265 = or(_T_264, _T_262) @[Mux.scala 27:72] + node _T_266 = or(_T_265, _T_263) @[Mux.scala 27:72] + wire _T_267 : UInt<32> @[Mux.scala 27:72] + _T_267 <= _T_266 @[Mux.scala 27:72] + node _T_268 = or(_T_252, _T_267) @[el2_exu_alu_ctl.scala 88:56] + result <= _T_268 @[el2_exu_alu_ctl.scala 88:16] + node _T_269 = or(io.ap.jal, io.pp_in.pcall) @[el2_exu_alu_ctl.scala 96:45] + node _T_270 = or(_T_269, io.pp_in.pja) @[el2_exu_alu_ctl.scala 97:20] + node any_jal = or(_T_270, io.pp_in.pret) @[el2_exu_alu_ctl.scala 98:20] + node _T_271 = and(io.ap.beq, eq) @[el2_exu_alu_ctl.scala 101:40] + node _T_272 = and(io.ap.bne, ne) @[el2_exu_alu_ctl.scala 101:59] + node _T_273 = or(_T_271, _T_272) @[el2_exu_alu_ctl.scala 101:46] + node _T_274 = and(io.ap.blt, lt) @[el2_exu_alu_ctl.scala 101:85] + node _T_275 = or(_T_273, _T_274) @[el2_exu_alu_ctl.scala 101:72] + node _T_276 = and(io.ap.bge, ge) @[el2_exu_alu_ctl.scala 101:104] + node _T_277 = or(_T_275, _T_276) @[el2_exu_alu_ctl.scala 101:91] + node actual_taken = or(_T_277, any_jal) @[el2_exu_alu_ctl.scala 101:110] + node _T_278 = and(io.valid_in, io.ap.predict_nt) @[el2_exu_alu_ctl.scala 106:42] + node _T_279 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:63] + node _T_280 = and(_T_278, _T_279) @[el2_exu_alu_ctl.scala 106:61] + node _T_281 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:79] + node _T_282 = and(_T_280, _T_281) @[el2_exu_alu_ctl.scala 106:77] + node _T_283 = and(io.valid_in, io.ap.predict_t) @[el2_exu_alu_ctl.scala 106:104] + node _T_284 = and(_T_283, actual_taken) @[el2_exu_alu_ctl.scala 106:123] + node _T_285 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:141] + node _T_286 = and(_T_284, _T_285) @[el2_exu_alu_ctl.scala 106:139] + node _T_287 = or(_T_282, _T_286) @[el2_exu_alu_ctl.scala 106:89] + io.pred_correct_out <= _T_287 @[el2_exu_alu_ctl.scala 106:26] + node _T_288 = bits(any_jal, 0, 0) @[el2_exu_alu_ctl.scala 108:37] + node _T_289 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 108:49] + node _T_290 = bits(pcout, 31, 1) @[el2_exu_alu_ctl.scala 108:62] + node _T_291 = mux(_T_288, _T_289, _T_290) @[el2_exu_alu_ctl.scala 108:28] + io.flush_path_out <= _T_291 @[el2_exu_alu_ctl.scala 108:22] + node _T_292 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 111:47] + node _T_293 = and(io.ap.predict_t, _T_292) @[el2_exu_alu_ctl.scala 111:45] + node _T_294 = and(io.ap.predict_nt, actual_taken) @[el2_exu_alu_ctl.scala 111:82] + node cond_mispredict = or(_T_293, _T_294) @[el2_exu_alu_ctl.scala 111:62] + node _T_295 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 114:70] + node _T_296 = neq(io.pp_in.prett, _T_295) @[el2_exu_alu_ctl.scala 114:62] + node target_mispredict = and(io.pp_in.pret, _T_296) @[el2_exu_alu_ctl.scala 114:44] + node _T_297 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 116:42] + node _T_298 = or(_T_297, target_mispredict) @[el2_exu_alu_ctl.scala 116:60] + node _T_299 = and(_T_298, io.valid_in) @[el2_exu_alu_ctl.scala 116:81] + node _T_300 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 116:97] + node _T_301 = and(_T_299, _T_300) @[el2_exu_alu_ctl.scala 116:95] + node _T_302 = eq(io.flush_lower_r, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 116:119] + node _T_303 = and(_T_301, _T_302) @[el2_exu_alu_ctl.scala 116:117] + io.flush_upper_out <= _T_303 @[el2_exu_alu_ctl.scala 116:26] + node _T_304 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 118:42] + node _T_305 = or(_T_304, target_mispredict) @[el2_exu_alu_ctl.scala 118:60] + node _T_306 = and(_T_305, io.valid_in) @[el2_exu_alu_ctl.scala 118:81] + node _T_307 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 118:97] + node _T_308 = and(_T_306, _T_307) @[el2_exu_alu_ctl.scala 118:95] + node _T_309 = or(_T_308, io.flush_lower_r) @[el2_exu_alu_ctl.scala 118:117] + io.flush_final_out <= _T_309 @[el2_exu_alu_ctl.scala 118:26] + wire newhist : UInt<2> + newhist <= UInt<1>("h00") + node _T_310 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 122:35] + node _T_311 = bits(io.pp_in.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:55] + node _T_312 = and(_T_310, _T_311) @[el2_exu_alu_ctl.scala 122:39] + node _T_313 = bits(io.pp_in.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:77] + node _T_314 = not(_T_313) @[el2_exu_alu_ctl.scala 122:63] + node _T_315 = and(_T_314, actual_taken) @[el2_exu_alu_ctl.scala 122:81] + node _T_316 = or(_T_312, _T_315) @[el2_exu_alu_ctl.scala 122:60] + node _T_317 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:20] + node _T_318 = not(_T_317) @[el2_exu_alu_ctl.scala 123:6] + node _T_319 = not(actual_taken) @[el2_exu_alu_ctl.scala 123:26] + node _T_320 = and(_T_318, _T_319) @[el2_exu_alu_ctl.scala 123:24] + node _T_321 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:58] + node _T_322 = and(_T_321, actual_taken) @[el2_exu_alu_ctl.scala 123:62] + node _T_323 = or(_T_320, _T_322) @[el2_exu_alu_ctl.scala 123:42] + node _T_324 = cat(_T_316, _T_323) @[Cat.scala 29:58] + newhist <= _T_324 @[el2_exu_alu_ctl.scala 122:14] + io.predict_p_out.way <= io.pp_in.way @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.pja <= io.pp_in.pja @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.pret <= io.pp_in.pret @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.pcall <= io.pp_in.pcall @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.prett <= io.pp_in.prett @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.br_start_error <= io.pp_in.br_start_error @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.br_error <= io.pp_in.br_error @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.valid <= io.pp_in.valid @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.toffset <= io.pp_in.toffset @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.hist <= io.pp_in.hist @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.pc4 <= io.pp_in.pc4 @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.boffset <= io.pp_in.boffset @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.ataken <= io.pp_in.ataken @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.misp <= io.pp_in.misp @[el2_exu_alu_ctl.scala 125:30] + node _T_325 = not(io.flush_upper_x) @[el2_exu_alu_ctl.scala 126:33] + node _T_326 = not(io.flush_lower_r) @[el2_exu_alu_ctl.scala 126:53] + node _T_327 = and(_T_325, _T_326) @[el2_exu_alu_ctl.scala 126:51] + node _T_328 = or(cond_mispredict, target_mispredict) @[el2_exu_alu_ctl.scala 126:90] + node _T_329 = and(_T_327, _T_328) @[el2_exu_alu_ctl.scala 126:71] + io.predict_p_out.misp <= _T_329 @[el2_exu_alu_ctl.scala 126:30] + io.predict_p_out.ataken <= actual_taken @[el2_exu_alu_ctl.scala 127:30] + io.predict_p_out.hist <= newhist @[el2_exu_alu_ctl.scala 128:30] + + extmodule TEC_RV_ICG_20 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_20 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_20 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_21 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_21 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_21 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_22 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_22 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_22 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + module el2_exu_mul_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip mul_p : {valid : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}, flip rs1_in : UInt<32>, flip rs2_in : UInt<32>, result_x : UInt<32>} + + wire rs1_ext_in : SInt<33> + rs1_ext_in <= asSInt(UInt<1>("h00")) + wire rs2_ext_in : SInt<33> + rs2_ext_in <= asSInt(UInt<1>("h00")) + wire rs1_x : SInt<33> + rs1_x <= asSInt(UInt<1>("h00")) + wire rs2_x : SInt<33> + rs2_x <= asSInt(UInt<1>("h00")) + wire prod_x : SInt<66> + prod_x <= asSInt(UInt<1>("h00")) + wire low_x : UInt<1> + low_x <= UInt<1>("h00") + node _T = bits(io.rs1_in, 31, 31) @[el2_exu_mul_ctl.scala 26:50] + node _T_1 = and(io.mul_p.rs1_sign, _T) @[el2_exu_mul_ctl.scala 26:39] + node _T_2 = cat(_T_1, io.rs1_in) @[Cat.scala 29:58] + node _T_3 = asSInt(_T_2) @[el2_exu_mul_ctl.scala 26:66] + rs1_ext_in <= _T_3 @[el2_exu_mul_ctl.scala 26:14] + node _T_4 = bits(io.rs2_in, 31, 31) @[el2_exu_mul_ctl.scala 27:50] + node _T_5 = and(io.mul_p.rs2_sign, _T_4) @[el2_exu_mul_ctl.scala 27:39] + node _T_6 = cat(_T_5, io.rs2_in) @[Cat.scala 29:58] + node _T_7 = asSInt(_T_6) @[el2_exu_mul_ctl.scala 27:66] + rs2_ext_in <= _T_7 @[el2_exu_mul_ctl.scala 27:14] + node _T_8 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 36:47] + inst rvclkhdr of rvclkhdr_20 @[el2_lib.scala 508:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= _T_8 @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_9 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_9 <= io.mul_p.low @[el2_lib.scala 514:16] + low_x <= _T_9 @[el2_exu_mul_ctl.scala 36:9] + node _T_10 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 37:44] + inst rvclkhdr_1 of rvclkhdr_21 @[el2_lib.scala 528:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 530:18] + rvclkhdr_1.io.en <= _T_10 @[el2_lib.scala 531:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 532:24] + reg _T_11 : SInt, rvclkhdr_1.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 534:16] + _T_11 <= rs1_ext_in @[el2_lib.scala 534:16] + rs1_x <= _T_11 @[el2_exu_mul_ctl.scala 37:9] + node _T_12 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 38:45] + inst rvclkhdr_2 of rvclkhdr_22 @[el2_lib.scala 528:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 530:18] + rvclkhdr_2.io.en <= _T_12 @[el2_lib.scala 531:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 532:24] + reg _T_13 : SInt, rvclkhdr_2.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 534:16] + _T_13 <= rs2_ext_in @[el2_lib.scala 534:16] + rs2_x <= _T_13 @[el2_exu_mul_ctl.scala 38:9] + node _T_14 = mul(rs1_x, rs2_x) @[el2_exu_mul_ctl.scala 40:20] + prod_x <= _T_14 @[el2_exu_mul_ctl.scala 40:10] + node _T_15 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 41:36] + node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_exu_mul_ctl.scala 41:29] + node _T_17 = bits(prod_x, 63, 32) @[el2_exu_mul_ctl.scala 41:52] + node _T_18 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 41:67] + node _T_19 = bits(prod_x, 31, 0) @[el2_exu_mul_ctl.scala 41:83] + node _T_20 = mux(_T_16, _T_17, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_21 = mux(_T_18, _T_19, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_22 = or(_T_20, _T_21) @[Mux.scala 27:72] + wire _T_23 : UInt<32> @[Mux.scala 27:72] + _T_23 <= _T_22 @[Mux.scala 27:72] + io.result_x <= _T_23 @[el2_exu_mul_ctl.scala 41:15] + + extmodule TEC_RV_ICG_23 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_23 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_23 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_24 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_24 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_24 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_25 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_25 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_25 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule TEC_RV_ICG_26 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_26 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_26 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + module el2_exu_div_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip dp : {valid : UInt<1>, unsign : UInt<1>, rem : UInt<1>}, flip dividend : UInt<32>, flip divisor : UInt<32>, flip cancel : UInt<1>, out : UInt<32>, finish_dly : UInt<1>} + + wire run_state : UInt<1> + run_state <= UInt<1>("h00") + wire count : UInt<6> + count <= UInt<6>("h00") + wire m_ff : UInt<33> + m_ff <= UInt<33>("h00") + wire q_in : UInt<33> + q_in <= UInt<33>("h00") + wire q_ff : UInt<33> + q_ff <= UInt<33>("h00") + wire a_in : UInt<33> + a_in <= UInt<33>("h00") + wire a_ff : UInt<33> + a_ff <= UInt<33>("h00") + wire m_eff : UInt<33> + m_eff <= UInt<33>("h00") + wire dividend_neg_ff : UInt<1> + dividend_neg_ff <= UInt<1>("h00") + wire divisor_neg_ff : UInt<1> + divisor_neg_ff <= UInt<1>("h00") + wire dividend_comp : UInt<32> + dividend_comp <= UInt<32>("h00") + wire q_ff_comp : UInt<32> + q_ff_comp <= UInt<32>("h00") + wire a_ff_comp : UInt<32> + a_ff_comp <= UInt<32>("h00") + wire sign_ff : UInt<1> + sign_ff <= UInt<1>("h00") + wire rem_ff : UInt<1> + rem_ff <= UInt<1>("h00") + wire add : UInt<1> + add <= UInt<1>("h00") + wire a_eff : UInt<33> + a_eff <= UInt<33>("h00") + wire a_eff_shift : UInt<56> + a_eff_shift <= UInt<56>("h00") + wire rem_correct : UInt<1> + rem_correct <= UInt<1>("h00") + wire valid_ff_x : UInt<1> + valid_ff_x <= UInt<1>("h00") + wire finish_ff : UInt<1> + finish_ff <= UInt<1>("h00") + wire smallnum_case_ff : UInt<1> + smallnum_case_ff <= UInt<1>("h00") + wire smallnum_ff : UInt<4> + smallnum_ff <= UInt<4>("h00") + wire smallnum_case : UInt<1> + smallnum_case <= UInt<1>("h00") + wire count_in : UInt<6> + count_in <= UInt<6>("h00") + wire dividend_eff : UInt<32> + dividend_eff <= UInt<32>("h00") + wire a_shift : UInt<33> + a_shift <= UInt<33>("h00") + io.out <= UInt<1>("h00") @[el2_exu_div_ctl.scala 50:10] + io.finish_dly <= UInt<1>("h00") @[el2_exu_div_ctl.scala 51:17] + node _T = eq(io.cancel, UInt<1>("h00")) @[el2_exu_div_ctl.scala 54:30] + node valid_x = and(valid_ff_x, _T) @[el2_exu_div_ctl.scala 54:28] + node _T_1 = bits(q_ff, 31, 4) @[el2_exu_div_ctl.scala 60:27] + node _T_2 = eq(_T_1, UInt<1>("h00")) @[el2_exu_div_ctl.scala 60:34] + node _T_3 = bits(m_ff, 31, 4) @[el2_exu_div_ctl.scala 60:50] + node _T_4 = eq(_T_3, UInt<1>("h00")) @[el2_exu_div_ctl.scala 60:57] + node _T_5 = and(_T_2, _T_4) @[el2_exu_div_ctl.scala 60:43] + node _T_6 = bits(m_ff, 31, 0) @[el2_exu_div_ctl.scala 60:73] + node _T_7 = neq(_T_6, UInt<1>("h00")) @[el2_exu_div_ctl.scala 60:80] + node _T_8 = and(_T_5, _T_7) @[el2_exu_div_ctl.scala 60:66] + node _T_9 = eq(rem_ff, UInt<1>("h00")) @[el2_exu_div_ctl.scala 60:91] + node _T_10 = and(_T_8, _T_9) @[el2_exu_div_ctl.scala 60:89] + node _T_11 = and(_T_10, valid_x) @[el2_exu_div_ctl.scala 60:99] + node _T_12 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 61:11] + node _T_13 = eq(_T_12, UInt<1>("h00")) @[el2_exu_div_ctl.scala 61:18] + node _T_14 = bits(m_ff, 31, 0) @[el2_exu_div_ctl.scala 61:34] + node _T_15 = neq(_T_14, UInt<1>("h00")) @[el2_exu_div_ctl.scala 61:41] + node _T_16 = and(_T_13, _T_15) @[el2_exu_div_ctl.scala 61:27] + node _T_17 = eq(rem_ff, UInt<1>("h00")) @[el2_exu_div_ctl.scala 61:52] + node _T_18 = and(_T_16, _T_17) @[el2_exu_div_ctl.scala 61:50] + node _T_19 = and(_T_18, valid_x) @[el2_exu_div_ctl.scala 61:60] + node _T_20 = or(_T_11, _T_19) @[el2_exu_div_ctl.scala 60:110] + smallnum_case <= _T_20 @[el2_exu_div_ctl.scala 60:17] + node pat1 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_21 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_23 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_25 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_26 = eq(_T_25, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_27 = and(_T_22, _T_24) @[el2_exu_div_ctl.scala 65:94] + node pat2 = and(_T_27, _T_26) @[el2_exu_div_ctl.scala 65:94] + node _T_28 = and(pat1, pat2) @[el2_exu_div_ctl.scala 66:10] + node pat1_1 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_29 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_31 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_32 = eq(_T_31, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node pat2_1 = and(_T_30, _T_32) @[el2_exu_div_ctl.scala 65:94] + node _T_33 = and(pat1_1, pat2_1) @[el2_exu_div_ctl.scala 66:10] + node _T_34 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 72:37] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_exu_div_ctl.scala 72:32] + node _T_36 = and(_T_33, _T_35) @[el2_exu_div_ctl.scala 72:30] + node pat1_2 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_37 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_38 = eq(_T_37, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_39 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_40 = eq(_T_39, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_41 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_42 = eq(_T_41, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_43 = and(_T_38, _T_40) @[el2_exu_div_ctl.scala 65:94] + node pat2_2 = and(_T_43, _T_42) @[el2_exu_div_ctl.scala 65:94] + node _T_44 = and(pat1_2, pat2_2) @[el2_exu_div_ctl.scala 66:10] + node _T_45 = or(_T_36, _T_44) @[el2_exu_div_ctl.scala 72:41] + node _T_46 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_47 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node pat1_3 = and(_T_46, _T_47) @[el2_exu_div_ctl.scala 64:94] + node _T_48 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_49 = eq(_T_48, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_50 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_51 = eq(_T_50, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node pat2_3 = and(_T_49, _T_51) @[el2_exu_div_ctl.scala 65:94] + node _T_52 = and(pat1_3, pat2_3) @[el2_exu_div_ctl.scala 66:10] + node _T_53 = or(_T_45, _T_52) @[el2_exu_div_ctl.scala 72:73] + node pat1_4 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_54 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_55 = eq(_T_54, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_56 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_57 = eq(_T_56, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node pat2_4 = and(_T_55, _T_57) @[el2_exu_div_ctl.scala 65:94] + node _T_58 = and(pat1_4, pat2_4) @[el2_exu_div_ctl.scala 66:10] + node _T_59 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 74:37] + node _T_60 = eq(_T_59, UInt<1>("h00")) @[el2_exu_div_ctl.scala 74:32] + node _T_61 = and(_T_58, _T_60) @[el2_exu_div_ctl.scala 74:30] + node pat1_5 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_62 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_63 = eq(_T_62, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_64 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_65 = eq(_T_64, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_66 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_67 = eq(_T_66, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_68 = and(_T_63, _T_65) @[el2_exu_div_ctl.scala 65:94] + node pat2_5 = and(_T_68, _T_67) @[el2_exu_div_ctl.scala 65:94] + node _T_69 = and(pat1_5, pat2_5) @[el2_exu_div_ctl.scala 66:10] + node _T_70 = or(_T_61, _T_69) @[el2_exu_div_ctl.scala 74:41] + node pat1_6 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_71 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_72 = eq(_T_71, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_73 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_74 = eq(_T_73, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node pat2_6 = and(_T_72, _T_74) @[el2_exu_div_ctl.scala 65:94] + node _T_75 = and(pat1_6, pat2_6) @[el2_exu_div_ctl.scala 66:10] + node _T_76 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 74:110] + node _T_77 = eq(_T_76, UInt<1>("h00")) @[el2_exu_div_ctl.scala 74:105] + node _T_78 = and(_T_75, _T_77) @[el2_exu_div_ctl.scala 74:103] + node _T_79 = or(_T_70, _T_78) @[el2_exu_div_ctl.scala 74:76] + node _T_80 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_81 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:74] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node pat1_7 = and(_T_80, _T_82) @[el2_exu_div_ctl.scala 64:94] + node _T_83 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_84 = eq(_T_83, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_85 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_86 = eq(_T_85, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_87 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:57] + node _T_88 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 65:57] + node _T_89 = and(_T_84, _T_86) @[el2_exu_div_ctl.scala 65:94] + node _T_90 = and(_T_89, _T_87) @[el2_exu_div_ctl.scala 65:94] + node pat2_7 = and(_T_90, _T_88) @[el2_exu_div_ctl.scala 65:94] + node _T_91 = and(pat1_7, pat2_7) @[el2_exu_div_ctl.scala 66:10] + node _T_92 = or(_T_79, _T_91) @[el2_exu_div_ctl.scala 74:114] + node _T_93 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:74] + node _T_94 = eq(_T_93, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_95 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_96 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_97 = and(_T_94, _T_95) @[el2_exu_div_ctl.scala 64:94] + node pat1_8 = and(_T_97, _T_96) @[el2_exu_div_ctl.scala 64:94] + node _T_98 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_99 = eq(_T_98, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_100 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_101 = eq(_T_100, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node pat2_8 = and(_T_99, _T_101) @[el2_exu_div_ctl.scala 65:94] + node _T_102 = and(pat1_8, pat2_8) @[el2_exu_div_ctl.scala 66:10] + node _T_103 = or(_T_92, _T_102) @[el2_exu_div_ctl.scala 75:43] + node _T_104 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_105 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node pat1_9 = and(_T_104, _T_105) @[el2_exu_div_ctl.scala 64:94] + node _T_106 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node pat2_9 = eq(_T_106, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_107 = and(pat1_9, pat2_9) @[el2_exu_div_ctl.scala 66:10] + node _T_108 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 75:111] + node _T_109 = eq(_T_108, UInt<1>("h00")) @[el2_exu_div_ctl.scala 75:106] + node _T_110 = and(_T_107, _T_109) @[el2_exu_div_ctl.scala 75:104] + node _T_111 = or(_T_103, _T_110) @[el2_exu_div_ctl.scala 75:78] + node _T_112 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_113 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node pat1_10 = and(_T_112, _T_113) @[el2_exu_div_ctl.scala 64:94] + node _T_114 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_115 = eq(_T_114, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_116 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57] + node _T_117 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_119 = and(_T_115, _T_116) @[el2_exu_div_ctl.scala 65:94] + node pat2_10 = and(_T_119, _T_118) @[el2_exu_div_ctl.scala 65:94] + node _T_120 = and(pat1_10, pat2_10) @[el2_exu_div_ctl.scala 66:10] + node _T_121 = or(_T_111, _T_120) @[el2_exu_div_ctl.scala 75:116] + node _T_122 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_123 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node pat1_11 = and(_T_122, _T_123) @[el2_exu_div_ctl.scala 64:94] + node _T_124 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_126 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_127 = eq(_T_126, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node pat2_11 = and(_T_125, _T_127) @[el2_exu_div_ctl.scala 65:94] + node _T_128 = and(pat1_11, pat2_11) @[el2_exu_div_ctl.scala 66:10] + node _T_129 = or(_T_121, _T_128) @[el2_exu_div_ctl.scala 76:43] + node _T_130 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_131 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_132 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_133 = and(_T_130, _T_131) @[el2_exu_div_ctl.scala 64:94] + node pat1_12 = and(_T_133, _T_132) @[el2_exu_div_ctl.scala 64:94] + node _T_134 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_135 = eq(_T_134, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_136 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57] + node pat2_12 = and(_T_135, _T_136) @[el2_exu_div_ctl.scala 65:94] + node _T_137 = and(pat1_12, pat2_12) @[el2_exu_div_ctl.scala 66:10] + node _T_138 = or(_T_129, _T_137) @[el2_exu_div_ctl.scala 76:77] + node _T_139 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_140 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_141 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node _T_142 = and(_T_139, _T_140) @[el2_exu_div_ctl.scala 64:94] + node pat1_13 = and(_T_142, _T_141) @[el2_exu_div_ctl.scala 64:94] + node _T_143 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_144 = eq(_T_143, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_145 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node pat2_13 = and(_T_144, _T_146) @[el2_exu_div_ctl.scala 65:94] + node _T_147 = and(pat1_13, pat2_13) @[el2_exu_div_ctl.scala 66:10] + node _T_148 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_149 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:74] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_151 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node _T_152 = and(_T_148, _T_150) @[el2_exu_div_ctl.scala 64:94] + node pat1_14 = and(_T_152, _T_151) @[el2_exu_div_ctl.scala 64:94] + node _T_153 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_154 = eq(_T_153, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_155 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:57] + node _T_156 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 65:57] + node _T_157 = and(_T_154, _T_155) @[el2_exu_div_ctl.scala 65:94] + node pat2_14 = and(_T_157, _T_156) @[el2_exu_div_ctl.scala 65:94] + node _T_158 = and(pat1_14, pat2_14) @[el2_exu_div_ctl.scala 66:10] + node _T_159 = or(_T_147, _T_158) @[el2_exu_div_ctl.scala 78:44] + node pat1_15 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_160 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_161 = eq(_T_160, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_162 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_163 = eq(_T_162, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node pat2_15 = and(_T_161, _T_163) @[el2_exu_div_ctl.scala 65:94] + node _T_164 = and(pat1_15, pat2_15) @[el2_exu_div_ctl.scala 66:10] + node _T_165 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 78:118] + node _T_166 = eq(_T_165, UInt<1>("h00")) @[el2_exu_div_ctl.scala 78:113] + node _T_167 = and(_T_164, _T_166) @[el2_exu_div_ctl.scala 78:111] + node _T_168 = or(_T_159, _T_167) @[el2_exu_div_ctl.scala 78:84] + node pat1_16 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_169 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_170 = eq(_T_169, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_171 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_172 = eq(_T_171, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node pat2_16 = and(_T_170, _T_172) @[el2_exu_div_ctl.scala 65:94] + node _T_173 = and(pat1_16, pat2_16) @[el2_exu_div_ctl.scala 66:10] + node _T_174 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 79:39] + node _T_175 = eq(_T_174, UInt<1>("h00")) @[el2_exu_div_ctl.scala 79:34] + node _T_176 = and(_T_173, _T_175) @[el2_exu_div_ctl.scala 79:32] + node _T_177 = or(_T_168, _T_176) @[el2_exu_div_ctl.scala 78:126] + node pat1_17 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node _T_178 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_180 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_181 = eq(_T_180, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_182 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_183 = eq(_T_182, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_184 = and(_T_179, _T_181) @[el2_exu_div_ctl.scala 65:94] + node pat2_17 = and(_T_184, _T_183) @[el2_exu_div_ctl.scala 65:94] + node _T_185 = and(pat1_17, pat2_17) @[el2_exu_div_ctl.scala 66:10] + node _T_186 = or(_T_177, _T_185) @[el2_exu_div_ctl.scala 79:46] + node _T_187 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:74] + node _T_188 = eq(_T_187, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_189 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_190 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:74] + node _T_191 = eq(_T_190, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_192 = and(_T_188, _T_189) @[el2_exu_div_ctl.scala 64:94] + node pat1_18 = and(_T_192, _T_191) @[el2_exu_div_ctl.scala 64:94] + node _T_193 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_194 = eq(_T_193, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_195 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_196 = eq(_T_195, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_197 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:57] + node _T_198 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 65:57] + node _T_199 = and(_T_194, _T_196) @[el2_exu_div_ctl.scala 65:94] + node _T_200 = and(_T_199, _T_197) @[el2_exu_div_ctl.scala 65:94] + node pat2_18 = and(_T_200, _T_198) @[el2_exu_div_ctl.scala 65:94] + node _T_201 = and(pat1_18, pat2_18) @[el2_exu_div_ctl.scala 66:10] + node _T_202 = or(_T_186, _T_201) @[el2_exu_div_ctl.scala 79:86] + node _T_203 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:74] + node _T_204 = eq(_T_203, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_205 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_206 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_207 = and(_T_204, _T_205) @[el2_exu_div_ctl.scala 64:94] + node pat1_19 = and(_T_207, _T_206) @[el2_exu_div_ctl.scala 64:94] + node _T_208 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node pat2_19 = eq(_T_208, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_209 = and(pat1_19, pat2_19) @[el2_exu_div_ctl.scala 66:10] + node _T_210 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 80:42] + node _T_211 = eq(_T_210, UInt<1>("h00")) @[el2_exu_div_ctl.scala 80:37] + node _T_212 = and(_T_209, _T_211) @[el2_exu_div_ctl.scala 80:35] + node _T_213 = or(_T_202, _T_212) @[el2_exu_div_ctl.scala 79:128] + node pat1_20 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_214 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_215 = eq(_T_214, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_216 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_217 = eq(_T_216, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node pat2_20 = and(_T_215, _T_217) @[el2_exu_div_ctl.scala 65:94] + node _T_218 = and(pat1_20, pat2_20) @[el2_exu_div_ctl.scala 66:10] + node _T_219 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 80:81] + node _T_220 = eq(_T_219, UInt<1>("h00")) @[el2_exu_div_ctl.scala 80:76] + node _T_221 = and(_T_218, _T_220) @[el2_exu_div_ctl.scala 80:74] + node _T_222 = or(_T_213, _T_221) @[el2_exu_div_ctl.scala 80:46] + node _T_223 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_224 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:74] + node _T_225 = eq(_T_224, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node pat1_21 = and(_T_223, _T_225) @[el2_exu_div_ctl.scala 64:94] + node _T_226 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_227 = eq(_T_226, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_228 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57] + node _T_229 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:57] + node _T_230 = and(_T_227, _T_228) @[el2_exu_div_ctl.scala 65:94] + node pat2_21 = and(_T_230, _T_229) @[el2_exu_div_ctl.scala 65:94] + node _T_231 = and(pat1_21, pat2_21) @[el2_exu_div_ctl.scala 66:10] + node _T_232 = or(_T_222, _T_231) @[el2_exu_div_ctl.scala 80:86] + node _T_233 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:74] + node _T_234 = eq(_T_233, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_235 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_236 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_237 = and(_T_234, _T_235) @[el2_exu_div_ctl.scala 64:94] + node pat1_22 = and(_T_237, _T_236) @[el2_exu_div_ctl.scala 64:94] + node _T_238 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_240 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57] + node _T_241 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_242 = eq(_T_241, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_243 = and(_T_239, _T_240) @[el2_exu_div_ctl.scala 65:94] + node pat2_22 = and(_T_243, _T_242) @[el2_exu_div_ctl.scala 65:94] + node _T_244 = and(pat1_22, pat2_22) @[el2_exu_div_ctl.scala 66:10] + node _T_245 = or(_T_232, _T_244) @[el2_exu_div_ctl.scala 80:128] + node _T_246 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:74] + node _T_247 = eq(_T_246, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_248 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_249 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node _T_250 = and(_T_247, _T_248) @[el2_exu_div_ctl.scala 64:94] + node pat1_23 = and(_T_250, _T_249) @[el2_exu_div_ctl.scala 64:94] + node _T_251 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_253 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_254 = eq(_T_253, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node pat2_23 = and(_T_252, _T_254) @[el2_exu_div_ctl.scala 65:94] + node _T_255 = and(pat1_23, pat2_23) @[el2_exu_div_ctl.scala 66:10] + node _T_256 = or(_T_245, _T_255) @[el2_exu_div_ctl.scala 81:46] + node _T_257 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_258 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:74] + node _T_259 = eq(_T_258, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_260 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:74] + node _T_261 = eq(_T_260, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_262 = and(_T_257, _T_259) @[el2_exu_div_ctl.scala 64:94] + node pat1_24 = and(_T_262, _T_261) @[el2_exu_div_ctl.scala 64:94] + node _T_263 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_264 = eq(_T_263, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_265 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57] + node _T_266 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 65:57] + node _T_267 = and(_T_264, _T_265) @[el2_exu_div_ctl.scala 65:94] + node pat2_24 = and(_T_267, _T_266) @[el2_exu_div_ctl.scala 65:94] + node _T_268 = and(pat1_24, pat2_24) @[el2_exu_div_ctl.scala 66:10] + node _T_269 = or(_T_256, _T_268) @[el2_exu_div_ctl.scala 81:86] + node _T_270 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:74] + node _T_271 = eq(_T_270, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_272 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_273 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node _T_274 = and(_T_271, _T_272) @[el2_exu_div_ctl.scala 64:94] + node pat1_25 = and(_T_274, _T_273) @[el2_exu_div_ctl.scala 64:94] + node _T_275 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_276 = eq(_T_275, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_277 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_278 = eq(_T_277, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node pat2_25 = and(_T_276, _T_278) @[el2_exu_div_ctl.scala 65:94] + node _T_279 = and(pat1_25, pat2_25) @[el2_exu_div_ctl.scala 66:10] + node _T_280 = or(_T_269, _T_279) @[el2_exu_div_ctl.scala 81:128] + node _T_281 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_282 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node pat1_26 = and(_T_281, _T_282) @[el2_exu_div_ctl.scala 64:94] + node _T_283 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node pat2_26 = eq(_T_283, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_284 = and(pat1_26, pat2_26) @[el2_exu_div_ctl.scala 66:10] + node _T_285 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 82:80] + node _T_286 = eq(_T_285, UInt<1>("h00")) @[el2_exu_div_ctl.scala 82:75] + node _T_287 = and(_T_284, _T_286) @[el2_exu_div_ctl.scala 82:73] + node _T_288 = or(_T_280, _T_287) @[el2_exu_div_ctl.scala 82:46] + node _T_289 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:74] + node _T_290 = eq(_T_289, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_291 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_292 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_293 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node _T_294 = and(_T_290, _T_291) @[el2_exu_div_ctl.scala 64:94] + node _T_295 = and(_T_294, _T_292) @[el2_exu_div_ctl.scala 64:94] + node pat1_27 = and(_T_295, _T_293) @[el2_exu_div_ctl.scala 64:94] + node _T_296 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_297 = eq(_T_296, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_298 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57] + node pat2_27 = and(_T_297, _T_298) @[el2_exu_div_ctl.scala 65:94] + node _T_299 = and(pat1_27, pat2_27) @[el2_exu_div_ctl.scala 66:10] + node _T_300 = or(_T_288, _T_299) @[el2_exu_div_ctl.scala 82:86] + node _T_301 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_302 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node pat1_28 = and(_T_301, _T_302) @[el2_exu_div_ctl.scala 64:94] + node _T_303 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:57] + node _T_304 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_305 = eq(_T_304, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node pat2_28 = and(_T_303, _T_305) @[el2_exu_div_ctl.scala 65:94] + node _T_306 = and(pat1_28, pat2_28) @[el2_exu_div_ctl.scala 66:10] + node _T_307 = or(_T_300, _T_306) @[el2_exu_div_ctl.scala 82:128] + node _T_308 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_309 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node pat1_29 = and(_T_308, _T_309) @[el2_exu_div_ctl.scala 64:94] + node _T_310 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:57] + node _T_311 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_312 = eq(_T_311, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_313 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_315 = and(_T_310, _T_312) @[el2_exu_div_ctl.scala 65:94] + node pat2_29 = and(_T_315, _T_314) @[el2_exu_div_ctl.scala 65:94] + node _T_316 = and(pat1_29, pat2_29) @[el2_exu_div_ctl.scala 66:10] + node _T_317 = or(_T_307, _T_316) @[el2_exu_div_ctl.scala 83:46] + node _T_318 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_319 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node pat1_30 = and(_T_318, _T_319) @[el2_exu_div_ctl.scala 64:94] + node _T_320 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_321 = eq(_T_320, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_322 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_323 = eq(_T_322, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node pat2_30 = and(_T_321, _T_323) @[el2_exu_div_ctl.scala 65:94] + node _T_324 = and(pat1_30, pat2_30) @[el2_exu_div_ctl.scala 66:10] + node _T_325 = or(_T_317, _T_324) @[el2_exu_div_ctl.scala 83:86] + node _T_326 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_327 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:74] + node _T_328 = eq(_T_327, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node pat1_31 = and(_T_326, _T_328) @[el2_exu_div_ctl.scala 64:94] + node _T_329 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_330 = eq(_T_329, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_331 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57] + node _T_332 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:57] + node _T_333 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 65:57] + node _T_334 = and(_T_330, _T_331) @[el2_exu_div_ctl.scala 65:94] + node _T_335 = and(_T_334, _T_332) @[el2_exu_div_ctl.scala 65:94] + node pat2_31 = and(_T_335, _T_333) @[el2_exu_div_ctl.scala 65:94] + node _T_336 = and(pat1_31, pat2_31) @[el2_exu_div_ctl.scala 66:10] + node _T_337 = or(_T_325, _T_336) @[el2_exu_div_ctl.scala 83:128] + node _T_338 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_339 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_340 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_341 = and(_T_338, _T_339) @[el2_exu_div_ctl.scala 64:94] + node pat1_32 = and(_T_341, _T_340) @[el2_exu_div_ctl.scala 64:94] + node pat2_32 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:57] + node _T_342 = and(pat1_32, pat2_32) @[el2_exu_div_ctl.scala 66:10] + node _T_343 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 84:82] + node _T_344 = eq(_T_343, UInt<1>("h00")) @[el2_exu_div_ctl.scala 84:77] + node _T_345 = and(_T_342, _T_344) @[el2_exu_div_ctl.scala 84:75] + node _T_346 = or(_T_337, _T_345) @[el2_exu_div_ctl.scala 84:46] + node _T_347 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_348 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_349 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_350 = and(_T_347, _T_348) @[el2_exu_div_ctl.scala 64:94] + node pat1_33 = and(_T_350, _T_349) @[el2_exu_div_ctl.scala 64:94] + node _T_351 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:57] + node _T_352 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node pat2_33 = and(_T_351, _T_353) @[el2_exu_div_ctl.scala 65:94] + node _T_354 = and(pat1_33, pat2_33) @[el2_exu_div_ctl.scala 66:10] + node _T_355 = or(_T_346, _T_354) @[el2_exu_div_ctl.scala 84:86] + node _T_356 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_357 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_358 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node _T_359 = and(_T_356, _T_357) @[el2_exu_div_ctl.scala 64:94] + node pat1_34 = and(_T_359, _T_358) @[el2_exu_div_ctl.scala 64:94] + node _T_360 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:57] + node _T_361 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node pat2_34 = and(_T_360, _T_362) @[el2_exu_div_ctl.scala 65:94] + node _T_363 = and(pat1_34, pat2_34) @[el2_exu_div_ctl.scala 66:10] + node _T_364 = or(_T_355, _T_363) @[el2_exu_div_ctl.scala 84:128] + node _T_365 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_366 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:74] + node _T_367 = eq(_T_366, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_368 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_369 = and(_T_365, _T_367) @[el2_exu_div_ctl.scala 64:94] + node pat1_35 = and(_T_369, _T_368) @[el2_exu_div_ctl.scala 64:94] + node _T_370 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_371 = eq(_T_370, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_372 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:57] + node pat2_35 = and(_T_371, _T_372) @[el2_exu_div_ctl.scala 65:94] + node _T_373 = and(pat1_35, pat2_35) @[el2_exu_div_ctl.scala 66:10] + node _T_374 = or(_T_364, _T_373) @[el2_exu_div_ctl.scala 85:46] + node _T_375 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_376 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_377 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node _T_378 = and(_T_375, _T_376) @[el2_exu_div_ctl.scala 64:94] + node pat1_36 = and(_T_378, _T_377) @[el2_exu_div_ctl.scala 64:94] + node _T_379 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node pat2_36 = eq(_T_379, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_380 = and(pat1_36, pat2_36) @[el2_exu_div_ctl.scala 66:10] + node _T_381 = or(_T_374, _T_380) @[el2_exu_div_ctl.scala 85:86] + node _T_382 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_383 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_384 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_385 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node _T_386 = and(_T_382, _T_383) @[el2_exu_div_ctl.scala 64:94] + node _T_387 = and(_T_386, _T_384) @[el2_exu_div_ctl.scala 64:94] + node pat1_37 = and(_T_387, _T_385) @[el2_exu_div_ctl.scala 64:94] + node pat2_37 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:57] + node _T_388 = and(pat1_37, pat2_37) @[el2_exu_div_ctl.scala 66:10] + node _T_389 = or(_T_381, _T_388) @[el2_exu_div_ctl.scala 85:128] + node _T_390 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_391 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node pat1_38 = and(_T_390, _T_391) @[el2_exu_div_ctl.scala 64:94] + node _T_392 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node pat2_38 = eq(_T_392, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_393 = and(pat1_38, pat2_38) @[el2_exu_div_ctl.scala 66:10] + node _T_394 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 86:79] + node _T_395 = eq(_T_394, UInt<1>("h00")) @[el2_exu_div_ctl.scala 86:74] + node _T_396 = and(_T_393, _T_395) @[el2_exu_div_ctl.scala 86:72] + node _T_397 = or(_T_389, _T_396) @[el2_exu_div_ctl.scala 86:46] + node _T_398 = cat(_T_138, _T_397) @[Cat.scala 29:58] + node _T_399 = cat(_T_28, _T_53) @[Cat.scala 29:58] + node smallnum = cat(_T_399, _T_398) @[Cat.scala 29:58] + wire shortq_enable_ff : UInt<1> + shortq_enable_ff <= UInt<1>("h00") + wire short_dividend : UInt<33> + short_dividend <= UInt<33>("h00") + wire shortq_shift_xx : UInt<4> + shortq_shift_xx <= UInt<4>("h00") + node _T_400 = bits(q_ff, 31, 31) @[el2_exu_div_ctl.scala 96:40] + node _T_401 = and(sign_ff, _T_400) @[el2_exu_div_ctl.scala 96:34] + node _T_402 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 96:49] + node _T_403 = cat(_T_401, _T_402) @[Cat.scala 29:58] + short_dividend <= _T_403 @[el2_exu_div_ctl.scala 96:18] + node _T_404 = bits(short_dividend, 32, 32) @[el2_exu_div_ctl.scala 101:22] + node _T_405 = bits(_T_404, 0, 0) @[el2_exu_div_ctl.scala 101:27] + node _T_406 = eq(_T_405, UInt<1>("h00")) @[el2_exu_div_ctl.scala 101:7] + node _T_407 = bits(short_dividend, 31, 24) @[el2_exu_div_ctl.scala 101:52] + node _T_408 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_409 = neq(_T_407, _T_408) @[el2_exu_div_ctl.scala 101:60] + node _T_410 = bits(short_dividend, 32, 32) @[el2_exu_div_ctl.scala 102:21] + node _T_411 = bits(_T_410, 0, 0) @[el2_exu_div_ctl.scala 102:26] + node _T_412 = bits(short_dividend, 31, 23) @[el2_exu_div_ctl.scala 102:51] + node _T_413 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12] + node _T_414 = neq(_T_412, _T_413) @[el2_exu_div_ctl.scala 102:59] + node _T_415 = mux(_T_406, _T_409, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_416 = mux(_T_411, _T_414, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_417 = or(_T_415, _T_416) @[Mux.scala 27:72] + wire _T_418 : UInt<1> @[Mux.scala 27:72] + _T_418 <= _T_417 @[Mux.scala 27:72] + node _T_419 = bits(short_dividend, 32, 32) @[el2_exu_div_ctl.scala 105:22] + node _T_420 = bits(_T_419, 0, 0) @[el2_exu_div_ctl.scala 105:27] + node _T_421 = eq(_T_420, UInt<1>("h00")) @[el2_exu_div_ctl.scala 105:7] + node _T_422 = bits(short_dividend, 23, 16) @[el2_exu_div_ctl.scala 105:52] + node _T_423 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_424 = neq(_T_422, _T_423) @[el2_exu_div_ctl.scala 105:60] + node _T_425 = bits(short_dividend, 32, 32) @[el2_exu_div_ctl.scala 106:21] + node _T_426 = bits(_T_425, 0, 0) @[el2_exu_div_ctl.scala 106:26] + node _T_427 = bits(short_dividend, 22, 15) @[el2_exu_div_ctl.scala 106:51] + node _T_428 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_429 = neq(_T_427, _T_428) @[el2_exu_div_ctl.scala 106:59] + node _T_430 = mux(_T_421, _T_424, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_431 = mux(_T_426, _T_429, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_432 = or(_T_430, _T_431) @[Mux.scala 27:72] + wire _T_433 : UInt<1> @[Mux.scala 27:72] + _T_433 <= _T_432 @[Mux.scala 27:72] + node _T_434 = bits(short_dividend, 32, 32) @[el2_exu_div_ctl.scala 109:22] + node _T_435 = bits(_T_434, 0, 0) @[el2_exu_div_ctl.scala 109:27] + node _T_436 = eq(_T_435, UInt<1>("h00")) @[el2_exu_div_ctl.scala 109:7] + node _T_437 = bits(short_dividend, 15, 8) @[el2_exu_div_ctl.scala 109:52] + node _T_438 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_439 = neq(_T_437, _T_438) @[el2_exu_div_ctl.scala 109:59] + node _T_440 = bits(short_dividend, 32, 32) @[el2_exu_div_ctl.scala 110:21] + node _T_441 = bits(_T_440, 0, 0) @[el2_exu_div_ctl.scala 110:26] + node _T_442 = bits(short_dividend, 14, 7) @[el2_exu_div_ctl.scala 110:51] + node _T_443 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_444 = neq(_T_442, _T_443) @[el2_exu_div_ctl.scala 110:58] + node _T_445 = mux(_T_436, _T_439, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_446 = mux(_T_441, _T_444, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_447 = or(_T_445, _T_446) @[Mux.scala 27:72] + wire _T_448 : UInt<1> @[Mux.scala 27:72] + _T_448 <= _T_447 @[Mux.scala 27:72] + node _T_449 = cat(_T_418, _T_433) @[Cat.scala 29:58] + node a_cls = cat(_T_449, _T_448) @[Cat.scala 29:58] + node _T_450 = bits(m_ff, 32, 32) @[el2_exu_div_ctl.scala 115:12] + node _T_451 = bits(_T_450, 0, 0) @[el2_exu_div_ctl.scala 115:17] + node _T_452 = eq(_T_451, UInt<1>("h00")) @[el2_exu_div_ctl.scala 115:7] + node _T_453 = bits(m_ff, 31, 24) @[el2_exu_div_ctl.scala 115:32] + node _T_454 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_455 = neq(_T_453, _T_454) @[el2_exu_div_ctl.scala 115:40] + node _T_456 = bits(m_ff, 32, 32) @[el2_exu_div_ctl.scala 116:11] + node _T_457 = bits(_T_456, 0, 0) @[el2_exu_div_ctl.scala 116:16] + node _T_458 = bits(m_ff, 31, 24) @[el2_exu_div_ctl.scala 116:31] + node _T_459 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_460 = neq(_T_458, _T_459) @[el2_exu_div_ctl.scala 116:39] + node _T_461 = mux(_T_452, _T_455, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_462 = mux(_T_457, _T_460, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_463 = or(_T_461, _T_462) @[Mux.scala 27:72] + wire _T_464 : UInt<1> @[Mux.scala 27:72] + _T_464 <= _T_463 @[Mux.scala 27:72] + node _T_465 = bits(m_ff, 32, 32) @[el2_exu_div_ctl.scala 119:12] + node _T_466 = bits(_T_465, 0, 0) @[el2_exu_div_ctl.scala 119:17] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_exu_div_ctl.scala 119:7] + node _T_468 = bits(m_ff, 23, 16) @[el2_exu_div_ctl.scala 119:32] + node _T_469 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_470 = neq(_T_468, _T_469) @[el2_exu_div_ctl.scala 119:40] + node _T_471 = bits(m_ff, 32, 32) @[el2_exu_div_ctl.scala 120:11] + node _T_472 = bits(_T_471, 0, 0) @[el2_exu_div_ctl.scala 120:16] + node _T_473 = bits(m_ff, 23, 16) @[el2_exu_div_ctl.scala 120:31] + node _T_474 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_475 = neq(_T_473, _T_474) @[el2_exu_div_ctl.scala 120:39] + node _T_476 = mux(_T_467, _T_470, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_477 = mux(_T_472, _T_475, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_478 = or(_T_476, _T_477) @[Mux.scala 27:72] + wire _T_479 : UInt<1> @[Mux.scala 27:72] + _T_479 <= _T_478 @[Mux.scala 27:72] + node _T_480 = bits(m_ff, 32, 32) @[el2_exu_div_ctl.scala 123:12] + node _T_481 = bits(_T_480, 0, 0) @[el2_exu_div_ctl.scala 123:17] + node _T_482 = eq(_T_481, UInt<1>("h00")) @[el2_exu_div_ctl.scala 123:7] + node _T_483 = bits(m_ff, 15, 8) @[el2_exu_div_ctl.scala 123:32] + node _T_484 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_485 = neq(_T_483, _T_484) @[el2_exu_div_ctl.scala 123:39] + node _T_486 = bits(m_ff, 32, 32) @[el2_exu_div_ctl.scala 124:11] + node _T_487 = bits(_T_486, 0, 0) @[el2_exu_div_ctl.scala 124:16] + node _T_488 = bits(m_ff, 15, 8) @[el2_exu_div_ctl.scala 124:31] + node _T_489 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_490 = neq(_T_488, _T_489) @[el2_exu_div_ctl.scala 124:38] + node _T_491 = mux(_T_482, _T_485, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_492 = mux(_T_487, _T_490, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_493 = or(_T_491, _T_492) @[Mux.scala 27:72] + wire _T_494 : UInt<1> @[Mux.scala 27:72] + _T_494 <= _T_493 @[Mux.scala 27:72] + node _T_495 = cat(_T_464, _T_479) @[Cat.scala 29:58] + node b_cls = cat(_T_495, _T_494) @[Cat.scala 29:58] + node _T_496 = bits(a_cls, 2, 1) @[el2_exu_div_ctl.scala 128:13] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[el2_exu_div_ctl.scala 128:19] + node _T_498 = bits(b_cls, 2, 2) @[el2_exu_div_ctl.scala 128:42] + node _T_499 = eq(_T_498, UInt<1>("h01")) @[el2_exu_div_ctl.scala 128:48] + node _T_500 = and(_T_497, _T_499) @[el2_exu_div_ctl.scala 128:34] + node _T_501 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 129:15] + node _T_502 = eq(_T_501, UInt<1>("h01")) @[el2_exu_div_ctl.scala 129:21] + node _T_503 = bits(b_cls, 2, 2) @[el2_exu_div_ctl.scala 129:44] + node _T_504 = eq(_T_503, UInt<1>("h01")) @[el2_exu_div_ctl.scala 129:50] + node _T_505 = and(_T_502, _T_504) @[el2_exu_div_ctl.scala 129:36] + node _T_506 = or(_T_500, _T_505) @[el2_exu_div_ctl.scala 128:65] + node _T_507 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 130:15] + node _T_508 = eq(_T_507, UInt<1>("h00")) @[el2_exu_div_ctl.scala 130:21] + node _T_509 = bits(b_cls, 2, 2) @[el2_exu_div_ctl.scala 130:44] + node _T_510 = eq(_T_509, UInt<1>("h01")) @[el2_exu_div_ctl.scala 130:50] + node _T_511 = and(_T_508, _T_510) @[el2_exu_div_ctl.scala 130:36] + node _T_512 = or(_T_506, _T_511) @[el2_exu_div_ctl.scala 129:67] + node _T_513 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 131:15] + node _T_514 = eq(_T_513, UInt<1>("h01")) @[el2_exu_div_ctl.scala 131:21] + node _T_515 = bits(b_cls, 2, 1) @[el2_exu_div_ctl.scala 131:44] + node _T_516 = eq(_T_515, UInt<1>("h01")) @[el2_exu_div_ctl.scala 131:50] + node _T_517 = and(_T_514, _T_516) @[el2_exu_div_ctl.scala 131:36] + node _T_518 = or(_T_512, _T_517) @[el2_exu_div_ctl.scala 130:67] + node _T_519 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 132:15] + node _T_520 = eq(_T_519, UInt<1>("h00")) @[el2_exu_div_ctl.scala 132:21] + node _T_521 = bits(b_cls, 2, 1) @[el2_exu_div_ctl.scala 132:44] + node _T_522 = eq(_T_521, UInt<1>("h01")) @[el2_exu_div_ctl.scala 132:50] + node _T_523 = and(_T_520, _T_522) @[el2_exu_div_ctl.scala 132:36] + node _T_524 = or(_T_518, _T_523) @[el2_exu_div_ctl.scala 131:67] + node _T_525 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 133:15] + node _T_526 = eq(_T_525, UInt<1>("h00")) @[el2_exu_div_ctl.scala 133:21] + node _T_527 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 133:44] + node _T_528 = eq(_T_527, UInt<1>("h01")) @[el2_exu_div_ctl.scala 133:50] + node _T_529 = and(_T_526, _T_528) @[el2_exu_div_ctl.scala 133:36] + node _T_530 = or(_T_524, _T_529) @[el2_exu_div_ctl.scala 132:67] + node _T_531 = bits(a_cls, 2, 2) @[el2_exu_div_ctl.scala 135:13] + node _T_532 = eq(_T_531, UInt<1>("h01")) @[el2_exu_div_ctl.scala 135:19] + node _T_533 = bits(b_cls, 2, 2) @[el2_exu_div_ctl.scala 135:42] + node _T_534 = eq(_T_533, UInt<1>("h01")) @[el2_exu_div_ctl.scala 135:48] + node _T_535 = and(_T_532, _T_534) @[el2_exu_div_ctl.scala 135:34] + node _T_536 = bits(a_cls, 2, 1) @[el2_exu_div_ctl.scala 136:15] + node _T_537 = eq(_T_536, UInt<1>("h01")) @[el2_exu_div_ctl.scala 136:21] + node _T_538 = bits(b_cls, 2, 1) @[el2_exu_div_ctl.scala 136:44] + node _T_539 = eq(_T_538, UInt<1>("h01")) @[el2_exu_div_ctl.scala 136:50] + node _T_540 = and(_T_537, _T_539) @[el2_exu_div_ctl.scala 136:36] + node _T_541 = or(_T_535, _T_540) @[el2_exu_div_ctl.scala 135:65] + node _T_542 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 137:15] + node _T_543 = eq(_T_542, UInt<1>("h01")) @[el2_exu_div_ctl.scala 137:21] + node _T_544 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 137:44] + node _T_545 = eq(_T_544, UInt<1>("h01")) @[el2_exu_div_ctl.scala 137:50] + node _T_546 = and(_T_543, _T_545) @[el2_exu_div_ctl.scala 137:36] + node _T_547 = or(_T_541, _T_546) @[el2_exu_div_ctl.scala 136:67] + node _T_548 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 138:15] + node _T_549 = eq(_T_548, UInt<1>("h00")) @[el2_exu_div_ctl.scala 138:21] + node _T_550 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 138:44] + node _T_551 = eq(_T_550, UInt<1>("h00")) @[el2_exu_div_ctl.scala 138:50] + node _T_552 = and(_T_549, _T_551) @[el2_exu_div_ctl.scala 138:36] + node _T_553 = or(_T_547, _T_552) @[el2_exu_div_ctl.scala 137:67] + node _T_554 = bits(a_cls, 2, 2) @[el2_exu_div_ctl.scala 140:13] + node _T_555 = eq(_T_554, UInt<1>("h01")) @[el2_exu_div_ctl.scala 140:19] + node _T_556 = bits(b_cls, 2, 1) @[el2_exu_div_ctl.scala 140:42] + node _T_557 = eq(_T_556, UInt<1>("h01")) @[el2_exu_div_ctl.scala 140:48] + node _T_558 = and(_T_555, _T_557) @[el2_exu_div_ctl.scala 140:34] + node _T_559 = bits(a_cls, 2, 1) @[el2_exu_div_ctl.scala 141:15] + node _T_560 = eq(_T_559, UInt<1>("h01")) @[el2_exu_div_ctl.scala 141:21] + node _T_561 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 141:44] + node _T_562 = eq(_T_561, UInt<1>("h01")) @[el2_exu_div_ctl.scala 141:50] + node _T_563 = and(_T_560, _T_562) @[el2_exu_div_ctl.scala 141:36] + node _T_564 = or(_T_558, _T_563) @[el2_exu_div_ctl.scala 140:65] + node _T_565 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 142:15] + node _T_566 = eq(_T_565, UInt<1>("h01")) @[el2_exu_div_ctl.scala 142:21] + node _T_567 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 142:44] + node _T_568 = eq(_T_567, UInt<1>("h00")) @[el2_exu_div_ctl.scala 142:50] + node _T_569 = and(_T_566, _T_568) @[el2_exu_div_ctl.scala 142:36] + node _T_570 = or(_T_564, _T_569) @[el2_exu_div_ctl.scala 141:67] + node _T_571 = bits(a_cls, 2, 2) @[el2_exu_div_ctl.scala 144:13] + node _T_572 = eq(_T_571, UInt<1>("h01")) @[el2_exu_div_ctl.scala 144:19] + node _T_573 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 144:42] + node _T_574 = eq(_T_573, UInt<1>("h01")) @[el2_exu_div_ctl.scala 144:48] + node _T_575 = and(_T_572, _T_574) @[el2_exu_div_ctl.scala 144:34] + node _T_576 = bits(a_cls, 2, 1) @[el2_exu_div_ctl.scala 145:15] + node _T_577 = eq(_T_576, UInt<1>("h01")) @[el2_exu_div_ctl.scala 145:21] + node _T_578 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 145:44] + node _T_579 = eq(_T_578, UInt<1>("h00")) @[el2_exu_div_ctl.scala 145:50] + node _T_580 = and(_T_577, _T_579) @[el2_exu_div_ctl.scala 145:36] + node _T_581 = or(_T_575, _T_580) @[el2_exu_div_ctl.scala 144:65] + node _T_582 = cat(_T_570, _T_581) @[Cat.scala 29:58] + node _T_583 = cat(_T_530, _T_553) @[Cat.scala 29:58] + node shortq_raw = cat(_T_583, _T_582) @[Cat.scala 29:58] + node _T_584 = bits(m_ff, 31, 0) @[el2_exu_div_ctl.scala 148:42] + node _T_585 = neq(_T_584, UInt<32>("h00")) @[el2_exu_div_ctl.scala 148:49] + node _T_586 = and(valid_ff_x, _T_585) @[el2_exu_div_ctl.scala 148:35] + node _T_587 = neq(shortq_raw, UInt<4>("h00")) @[el2_exu_div_ctl.scala 148:78] + node shortq_enable = and(_T_586, _T_587) @[el2_exu_div_ctl.scala 148:64] + node _T_588 = bits(shortq_enable, 0, 0) @[Bitwise.scala 72:15] + node _T_589 = mux(_T_588, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node shortq_shift = and(_T_589, shortq_raw) @[el2_exu_div_ctl.scala 149:44] + node _T_590 = bits(shortq_shift_xx, 3, 3) @[el2_exu_div_ctl.scala 152:20] + node _T_591 = bits(_T_590, 0, 0) @[el2_exu_div_ctl.scala 152:24] + node _T_592 = bits(shortq_shift_xx, 2, 2) @[el2_exu_div_ctl.scala 153:20] + node _T_593 = bits(_T_592, 0, 0) @[el2_exu_div_ctl.scala 153:24] + node _T_594 = bits(shortq_shift_xx, 1, 1) @[el2_exu_div_ctl.scala 154:20] + node _T_595 = bits(_T_594, 0, 0) @[el2_exu_div_ctl.scala 154:24] + node _T_596 = bits(shortq_shift_xx, 0, 0) @[el2_exu_div_ctl.scala 155:20] + node _T_597 = bits(_T_596, 0, 0) @[el2_exu_div_ctl.scala 155:24] + node _T_598 = mux(_T_591, UInt<5>("h01f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_599 = mux(_T_593, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_600 = mux(_T_595, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_601 = mux(_T_597, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_602 = or(_T_598, _T_599) @[Mux.scala 27:72] + node _T_603 = or(_T_602, _T_600) @[Mux.scala 27:72] + node _T_604 = or(_T_603, _T_601) @[Mux.scala 27:72] + wire shortq_shift_ff : UInt<5> @[Mux.scala 27:72] + shortq_shift_ff <= _T_604 @[Mux.scala 27:72] + node _T_605 = eq(rem_ff, UInt<1>("h00")) @[el2_exu_div_ctl.scala 159:40] + node _T_606 = eq(count, UInt<6>("h020")) @[el2_exu_div_ctl.scala 159:55] + node _T_607 = eq(count, UInt<6>("h021")) @[el2_exu_div_ctl.scala 159:76] + node _T_608 = mux(_T_605, _T_606, _T_607) @[el2_exu_div_ctl.scala 159:39] + node finish = or(smallnum_case, _T_608) @[el2_exu_div_ctl.scala 159:34] + node _T_609 = or(io.dp.valid, run_state) @[el2_exu_div_ctl.scala 160:32] + node _T_610 = or(_T_609, finish) @[el2_exu_div_ctl.scala 160:44] + node div_clken = or(_T_610, finish_ff) @[el2_exu_div_ctl.scala 160:53] + node _T_611 = or(io.dp.valid, run_state) @[el2_exu_div_ctl.scala 161:33] + node _T_612 = eq(finish, UInt<1>("h00")) @[el2_exu_div_ctl.scala 161:48] + node _T_613 = and(_T_611, _T_612) @[el2_exu_div_ctl.scala 161:46] + node _T_614 = eq(io.cancel, UInt<1>("h00")) @[el2_exu_div_ctl.scala 161:58] + node run_in = and(_T_613, _T_614) @[el2_exu_div_ctl.scala 161:56] + node _T_615 = eq(finish, UInt<1>("h00")) @[el2_exu_div_ctl.scala 162:37] + node _T_616 = and(run_state, _T_615) @[el2_exu_div_ctl.scala 162:35] + node _T_617 = eq(io.cancel, UInt<1>("h00")) @[el2_exu_div_ctl.scala 162:47] + node _T_618 = and(_T_616, _T_617) @[el2_exu_div_ctl.scala 162:45] + node _T_619 = eq(shortq_enable, UInt<1>("h00")) @[el2_exu_div_ctl.scala 162:60] + node _T_620 = and(_T_618, _T_619) @[el2_exu_div_ctl.scala 162:58] + node _T_621 = bits(_T_620, 0, 0) @[Bitwise.scala 72:15] + node _T_622 = mux(_T_621, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] + node _T_623 = cat(UInt<1>("h00"), shortq_shift_ff) @[Cat.scala 29:58] + node _T_624 = add(count, _T_623) @[el2_exu_div_ctl.scala 162:86] + node _T_625 = tail(_T_624, 1) @[el2_exu_div_ctl.scala 162:86] + node _T_626 = add(_T_625, UInt<6>("h01")) @[el2_exu_div_ctl.scala 162:113] + node _T_627 = tail(_T_626, 1) @[el2_exu_div_ctl.scala 162:113] + node _T_628 = and(_T_622, _T_627) @[el2_exu_div_ctl.scala 162:77] + count_in <= _T_628 @[el2_exu_div_ctl.scala 162:14] + node _T_629 = eq(io.cancel, UInt<1>("h00")) @[el2_exu_div_ctl.scala 165:34] + node _T_630 = and(finish_ff, _T_629) @[el2_exu_div_ctl.scala 165:32] + io.finish_dly <= _T_630 @[el2_exu_div_ctl.scala 165:18] + node _T_631 = eq(io.dp.unsign, UInt<1>("h00")) @[el2_exu_div_ctl.scala 166:20] + node _T_632 = neq(io.divisor, UInt<32>("h00")) @[el2_exu_div_ctl.scala 166:48] + node sign_eff = and(_T_631, _T_632) @[el2_exu_div_ctl.scala 166:34] + node _T_633 = eq(run_state, UInt<1>("h00")) @[el2_exu_div_ctl.scala 170:6] + node _T_634 = bits(_T_633, 0, 0) @[el2_exu_div_ctl.scala 170:18] + node _T_635 = cat(UInt<1>("h00"), io.dividend) @[Cat.scala 29:58] + node _T_636 = or(valid_ff_x, shortq_enable_ff) @[el2_exu_div_ctl.scala 171:30] + node _T_637 = and(run_state, _T_636) @[el2_exu_div_ctl.scala 171:16] + node _T_638 = bits(_T_637, 0, 0) @[el2_exu_div_ctl.scala 171:51] + node _T_639 = bits(dividend_eff, 31, 0) @[el2_exu_div_ctl.scala 171:78] + node _T_640 = bits(a_in, 32, 32) @[el2_exu_div_ctl.scala 171:90] + node _T_641 = eq(_T_640, UInt<1>("h00")) @[el2_exu_div_ctl.scala 171:85] + node _T_642 = cat(_T_639, _T_641) @[Cat.scala 29:58] + node _T_643 = dshl(_T_642, shortq_shift_ff) @[el2_exu_div_ctl.scala 171:96] + node _T_644 = or(valid_ff_x, shortq_enable_ff) @[el2_exu_div_ctl.scala 172:31] + node _T_645 = eq(_T_644, UInt<1>("h00")) @[el2_exu_div_ctl.scala 172:18] + node _T_646 = and(run_state, _T_645) @[el2_exu_div_ctl.scala 172:16] + node _T_647 = bits(_T_646, 0, 0) @[el2_exu_div_ctl.scala 172:52] + node _T_648 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 172:70] + node _T_649 = bits(a_in, 32, 32) @[el2_exu_div_ctl.scala 172:82] + node _T_650 = eq(_T_649, UInt<1>("h00")) @[el2_exu_div_ctl.scala 172:77] + node _T_651 = cat(_T_648, _T_650) @[Cat.scala 29:58] + node _T_652 = mux(_T_634, _T_635, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_653 = mux(_T_638, _T_643, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_654 = mux(_T_647, _T_651, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_655 = or(_T_652, _T_653) @[Mux.scala 27:72] + node _T_656 = or(_T_655, _T_654) @[Mux.scala 27:72] + wire _T_657 : UInt<64> @[Mux.scala 27:72] + _T_657 <= _T_656 @[Mux.scala 27:72] + q_in <= _T_657 @[el2_exu_div_ctl.scala 169:8] + node _T_658 = eq(shortq_enable, UInt<1>("h00")) @[el2_exu_div_ctl.scala 174:50] + node _T_659 = and(run_state, _T_658) @[el2_exu_div_ctl.scala 174:48] + node qff_enable = or(io.dp.valid, _T_659) @[el2_exu_div_ctl.scala 174:35] + node _T_660 = and(sign_ff, dividend_neg_ff) @[el2_exu_div_ctl.scala 175:32] + node _T_661 = bits(_T_660, 0, 0) @[el2_exu_div_ctl.scala 175:51] + node _T_662 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 175:74] + wire _T_663 : UInt<1>[31] @[el2_lib.scala 541:20] + node _T_664 = bits(_T_662, 0, 0) @[el2_lib.scala 543:27] + node _T_665 = orr(_T_664) @[el2_lib.scala 543:35] + node _T_666 = bits(_T_662, 1, 1) @[el2_lib.scala 543:44] + node _T_667 = not(_T_666) @[el2_lib.scala 543:40] + node _T_668 = bits(_T_662, 1, 1) @[el2_lib.scala 543:51] + node _T_669 = mux(_T_665, _T_667, _T_668) @[el2_lib.scala 543:23] + _T_663[0] <= _T_669 @[el2_lib.scala 543:17] + node _T_670 = bits(_T_662, 1, 0) @[el2_lib.scala 543:27] + node _T_671 = orr(_T_670) @[el2_lib.scala 543:35] + node _T_672 = bits(_T_662, 2, 2) @[el2_lib.scala 543:44] + node _T_673 = not(_T_672) @[el2_lib.scala 543:40] + node _T_674 = bits(_T_662, 2, 2) @[el2_lib.scala 543:51] + node _T_675 = mux(_T_671, _T_673, _T_674) @[el2_lib.scala 543:23] + _T_663[1] <= _T_675 @[el2_lib.scala 543:17] + node _T_676 = bits(_T_662, 2, 0) @[el2_lib.scala 543:27] + node _T_677 = orr(_T_676) @[el2_lib.scala 543:35] + node _T_678 = bits(_T_662, 3, 3) @[el2_lib.scala 543:44] + node _T_679 = not(_T_678) @[el2_lib.scala 543:40] + node _T_680 = bits(_T_662, 3, 3) @[el2_lib.scala 543:51] + node _T_681 = mux(_T_677, _T_679, _T_680) @[el2_lib.scala 543:23] + _T_663[2] <= _T_681 @[el2_lib.scala 543:17] + node _T_682 = bits(_T_662, 3, 0) @[el2_lib.scala 543:27] + node _T_683 = orr(_T_682) @[el2_lib.scala 543:35] + node _T_684 = bits(_T_662, 4, 4) @[el2_lib.scala 543:44] + node _T_685 = not(_T_684) @[el2_lib.scala 543:40] + node _T_686 = bits(_T_662, 4, 4) @[el2_lib.scala 543:51] + node _T_687 = mux(_T_683, _T_685, _T_686) @[el2_lib.scala 543:23] + _T_663[3] <= _T_687 @[el2_lib.scala 543:17] + node _T_688 = bits(_T_662, 4, 0) @[el2_lib.scala 543:27] + node _T_689 = orr(_T_688) @[el2_lib.scala 543:35] + node _T_690 = bits(_T_662, 5, 5) @[el2_lib.scala 543:44] + node _T_691 = not(_T_690) @[el2_lib.scala 543:40] + node _T_692 = bits(_T_662, 5, 5) @[el2_lib.scala 543:51] + node _T_693 = mux(_T_689, _T_691, _T_692) @[el2_lib.scala 543:23] + _T_663[4] <= _T_693 @[el2_lib.scala 543:17] + node _T_694 = bits(_T_662, 5, 0) @[el2_lib.scala 543:27] + node _T_695 = orr(_T_694) @[el2_lib.scala 543:35] + node _T_696 = bits(_T_662, 6, 6) @[el2_lib.scala 543:44] + node _T_697 = not(_T_696) @[el2_lib.scala 543:40] + node _T_698 = bits(_T_662, 6, 6) @[el2_lib.scala 543:51] + node _T_699 = mux(_T_695, _T_697, _T_698) @[el2_lib.scala 543:23] + _T_663[5] <= _T_699 @[el2_lib.scala 543:17] + node _T_700 = bits(_T_662, 6, 0) @[el2_lib.scala 543:27] + node _T_701 = orr(_T_700) @[el2_lib.scala 543:35] + node _T_702 = bits(_T_662, 7, 7) @[el2_lib.scala 543:44] + node _T_703 = not(_T_702) @[el2_lib.scala 543:40] + node _T_704 = bits(_T_662, 7, 7) @[el2_lib.scala 543:51] + node _T_705 = mux(_T_701, _T_703, _T_704) @[el2_lib.scala 543:23] + _T_663[6] <= _T_705 @[el2_lib.scala 543:17] + node _T_706 = bits(_T_662, 7, 0) @[el2_lib.scala 543:27] + node _T_707 = orr(_T_706) @[el2_lib.scala 543:35] + node _T_708 = bits(_T_662, 8, 8) @[el2_lib.scala 543:44] + node _T_709 = not(_T_708) @[el2_lib.scala 543:40] + node _T_710 = bits(_T_662, 8, 8) @[el2_lib.scala 543:51] + node _T_711 = mux(_T_707, _T_709, _T_710) @[el2_lib.scala 543:23] + _T_663[7] <= _T_711 @[el2_lib.scala 543:17] + node _T_712 = bits(_T_662, 8, 0) @[el2_lib.scala 543:27] + node _T_713 = orr(_T_712) @[el2_lib.scala 543:35] + node _T_714 = bits(_T_662, 9, 9) @[el2_lib.scala 543:44] + node _T_715 = not(_T_714) @[el2_lib.scala 543:40] + node _T_716 = bits(_T_662, 9, 9) @[el2_lib.scala 543:51] + node _T_717 = mux(_T_713, _T_715, _T_716) @[el2_lib.scala 543:23] + _T_663[8] <= _T_717 @[el2_lib.scala 543:17] + node _T_718 = bits(_T_662, 9, 0) @[el2_lib.scala 543:27] + node _T_719 = orr(_T_718) @[el2_lib.scala 543:35] + node _T_720 = bits(_T_662, 10, 10) @[el2_lib.scala 543:44] + node _T_721 = not(_T_720) @[el2_lib.scala 543:40] + node _T_722 = bits(_T_662, 10, 10) @[el2_lib.scala 543:51] + node _T_723 = mux(_T_719, _T_721, _T_722) @[el2_lib.scala 543:23] + _T_663[9] <= _T_723 @[el2_lib.scala 543:17] + node _T_724 = bits(_T_662, 10, 0) @[el2_lib.scala 543:27] + node _T_725 = orr(_T_724) @[el2_lib.scala 543:35] + node _T_726 = bits(_T_662, 11, 11) @[el2_lib.scala 543:44] + node _T_727 = not(_T_726) @[el2_lib.scala 543:40] + node _T_728 = bits(_T_662, 11, 11) @[el2_lib.scala 543:51] + node _T_729 = mux(_T_725, _T_727, _T_728) @[el2_lib.scala 543:23] + _T_663[10] <= _T_729 @[el2_lib.scala 543:17] + node _T_730 = bits(_T_662, 11, 0) @[el2_lib.scala 543:27] + node _T_731 = orr(_T_730) @[el2_lib.scala 543:35] + node _T_732 = bits(_T_662, 12, 12) @[el2_lib.scala 543:44] + node _T_733 = not(_T_732) @[el2_lib.scala 543:40] + node _T_734 = bits(_T_662, 12, 12) @[el2_lib.scala 543:51] + node _T_735 = mux(_T_731, _T_733, _T_734) @[el2_lib.scala 543:23] + _T_663[11] <= _T_735 @[el2_lib.scala 543:17] + node _T_736 = bits(_T_662, 12, 0) @[el2_lib.scala 543:27] + node _T_737 = orr(_T_736) @[el2_lib.scala 543:35] + node _T_738 = bits(_T_662, 13, 13) @[el2_lib.scala 543:44] + node _T_739 = not(_T_738) @[el2_lib.scala 543:40] + node _T_740 = bits(_T_662, 13, 13) @[el2_lib.scala 543:51] + node _T_741 = mux(_T_737, _T_739, _T_740) @[el2_lib.scala 543:23] + _T_663[12] <= _T_741 @[el2_lib.scala 543:17] + node _T_742 = bits(_T_662, 13, 0) @[el2_lib.scala 543:27] + node _T_743 = orr(_T_742) @[el2_lib.scala 543:35] + node _T_744 = bits(_T_662, 14, 14) @[el2_lib.scala 543:44] + node _T_745 = not(_T_744) @[el2_lib.scala 543:40] + node _T_746 = bits(_T_662, 14, 14) @[el2_lib.scala 543:51] + node _T_747 = mux(_T_743, _T_745, _T_746) @[el2_lib.scala 543:23] + _T_663[13] <= _T_747 @[el2_lib.scala 543:17] + node _T_748 = bits(_T_662, 14, 0) @[el2_lib.scala 543:27] + node _T_749 = orr(_T_748) @[el2_lib.scala 543:35] + node _T_750 = bits(_T_662, 15, 15) @[el2_lib.scala 543:44] + node _T_751 = not(_T_750) @[el2_lib.scala 543:40] + node _T_752 = bits(_T_662, 15, 15) @[el2_lib.scala 543:51] + node _T_753 = mux(_T_749, _T_751, _T_752) @[el2_lib.scala 543:23] + _T_663[14] <= _T_753 @[el2_lib.scala 543:17] + node _T_754 = bits(_T_662, 15, 0) @[el2_lib.scala 543:27] + node _T_755 = orr(_T_754) @[el2_lib.scala 543:35] + node _T_756 = bits(_T_662, 16, 16) @[el2_lib.scala 543:44] + node _T_757 = not(_T_756) @[el2_lib.scala 543:40] + node _T_758 = bits(_T_662, 16, 16) @[el2_lib.scala 543:51] + node _T_759 = mux(_T_755, _T_757, _T_758) @[el2_lib.scala 543:23] + _T_663[15] <= _T_759 @[el2_lib.scala 543:17] + node _T_760 = bits(_T_662, 16, 0) @[el2_lib.scala 543:27] + node _T_761 = orr(_T_760) @[el2_lib.scala 543:35] + node _T_762 = bits(_T_662, 17, 17) @[el2_lib.scala 543:44] + node _T_763 = not(_T_762) @[el2_lib.scala 543:40] + node _T_764 = bits(_T_662, 17, 17) @[el2_lib.scala 543:51] + node _T_765 = mux(_T_761, _T_763, _T_764) @[el2_lib.scala 543:23] + _T_663[16] <= _T_765 @[el2_lib.scala 543:17] + node _T_766 = bits(_T_662, 17, 0) @[el2_lib.scala 543:27] + node _T_767 = orr(_T_766) @[el2_lib.scala 543:35] + node _T_768 = bits(_T_662, 18, 18) @[el2_lib.scala 543:44] + node _T_769 = not(_T_768) @[el2_lib.scala 543:40] + node _T_770 = bits(_T_662, 18, 18) @[el2_lib.scala 543:51] + node _T_771 = mux(_T_767, _T_769, _T_770) @[el2_lib.scala 543:23] + _T_663[17] <= _T_771 @[el2_lib.scala 543:17] + node _T_772 = bits(_T_662, 18, 0) @[el2_lib.scala 543:27] + node _T_773 = orr(_T_772) @[el2_lib.scala 543:35] + node _T_774 = bits(_T_662, 19, 19) @[el2_lib.scala 543:44] + node _T_775 = not(_T_774) @[el2_lib.scala 543:40] + node _T_776 = bits(_T_662, 19, 19) @[el2_lib.scala 543:51] + node _T_777 = mux(_T_773, _T_775, _T_776) @[el2_lib.scala 543:23] + _T_663[18] <= _T_777 @[el2_lib.scala 543:17] + node _T_778 = bits(_T_662, 19, 0) @[el2_lib.scala 543:27] + node _T_779 = orr(_T_778) @[el2_lib.scala 543:35] + node _T_780 = bits(_T_662, 20, 20) @[el2_lib.scala 543:44] + node _T_781 = not(_T_780) @[el2_lib.scala 543:40] + node _T_782 = bits(_T_662, 20, 20) @[el2_lib.scala 543:51] + node _T_783 = mux(_T_779, _T_781, _T_782) @[el2_lib.scala 543:23] + _T_663[19] <= _T_783 @[el2_lib.scala 543:17] + node _T_784 = bits(_T_662, 20, 0) @[el2_lib.scala 543:27] + node _T_785 = orr(_T_784) @[el2_lib.scala 543:35] + node _T_786 = bits(_T_662, 21, 21) @[el2_lib.scala 543:44] + node _T_787 = not(_T_786) @[el2_lib.scala 543:40] + node _T_788 = bits(_T_662, 21, 21) @[el2_lib.scala 543:51] + node _T_789 = mux(_T_785, _T_787, _T_788) @[el2_lib.scala 543:23] + _T_663[20] <= _T_789 @[el2_lib.scala 543:17] + node _T_790 = bits(_T_662, 21, 0) @[el2_lib.scala 543:27] + node _T_791 = orr(_T_790) @[el2_lib.scala 543:35] + node _T_792 = bits(_T_662, 22, 22) @[el2_lib.scala 543:44] + node _T_793 = not(_T_792) @[el2_lib.scala 543:40] + node _T_794 = bits(_T_662, 22, 22) @[el2_lib.scala 543:51] + node _T_795 = mux(_T_791, _T_793, _T_794) @[el2_lib.scala 543:23] + _T_663[21] <= _T_795 @[el2_lib.scala 543:17] + node _T_796 = bits(_T_662, 22, 0) @[el2_lib.scala 543:27] + node _T_797 = orr(_T_796) @[el2_lib.scala 543:35] + node _T_798 = bits(_T_662, 23, 23) @[el2_lib.scala 543:44] + node _T_799 = not(_T_798) @[el2_lib.scala 543:40] + node _T_800 = bits(_T_662, 23, 23) @[el2_lib.scala 543:51] + node _T_801 = mux(_T_797, _T_799, _T_800) @[el2_lib.scala 543:23] + _T_663[22] <= _T_801 @[el2_lib.scala 543:17] + node _T_802 = bits(_T_662, 23, 0) @[el2_lib.scala 543:27] + node _T_803 = orr(_T_802) @[el2_lib.scala 543:35] + node _T_804 = bits(_T_662, 24, 24) @[el2_lib.scala 543:44] + node _T_805 = not(_T_804) @[el2_lib.scala 543:40] + node _T_806 = bits(_T_662, 24, 24) @[el2_lib.scala 543:51] + node _T_807 = mux(_T_803, _T_805, _T_806) @[el2_lib.scala 543:23] + _T_663[23] <= _T_807 @[el2_lib.scala 543:17] + node _T_808 = bits(_T_662, 24, 0) @[el2_lib.scala 543:27] + node _T_809 = orr(_T_808) @[el2_lib.scala 543:35] + node _T_810 = bits(_T_662, 25, 25) @[el2_lib.scala 543:44] + node _T_811 = not(_T_810) @[el2_lib.scala 543:40] + node _T_812 = bits(_T_662, 25, 25) @[el2_lib.scala 543:51] + node _T_813 = mux(_T_809, _T_811, _T_812) @[el2_lib.scala 543:23] + _T_663[24] <= _T_813 @[el2_lib.scala 543:17] + node _T_814 = bits(_T_662, 25, 0) @[el2_lib.scala 543:27] + node _T_815 = orr(_T_814) @[el2_lib.scala 543:35] + node _T_816 = bits(_T_662, 26, 26) @[el2_lib.scala 543:44] + node _T_817 = not(_T_816) @[el2_lib.scala 543:40] + node _T_818 = bits(_T_662, 26, 26) @[el2_lib.scala 543:51] + node _T_819 = mux(_T_815, _T_817, _T_818) @[el2_lib.scala 543:23] + _T_663[25] <= _T_819 @[el2_lib.scala 543:17] + node _T_820 = bits(_T_662, 26, 0) @[el2_lib.scala 543:27] + node _T_821 = orr(_T_820) @[el2_lib.scala 543:35] + node _T_822 = bits(_T_662, 27, 27) @[el2_lib.scala 543:44] + node _T_823 = not(_T_822) @[el2_lib.scala 543:40] + node _T_824 = bits(_T_662, 27, 27) @[el2_lib.scala 543:51] + node _T_825 = mux(_T_821, _T_823, _T_824) @[el2_lib.scala 543:23] + _T_663[26] <= _T_825 @[el2_lib.scala 543:17] + node _T_826 = bits(_T_662, 27, 0) @[el2_lib.scala 543:27] + node _T_827 = orr(_T_826) @[el2_lib.scala 543:35] + node _T_828 = bits(_T_662, 28, 28) @[el2_lib.scala 543:44] + node _T_829 = not(_T_828) @[el2_lib.scala 543:40] + node _T_830 = bits(_T_662, 28, 28) @[el2_lib.scala 543:51] + node _T_831 = mux(_T_827, _T_829, _T_830) @[el2_lib.scala 543:23] + _T_663[27] <= _T_831 @[el2_lib.scala 543:17] + node _T_832 = bits(_T_662, 28, 0) @[el2_lib.scala 543:27] + node _T_833 = orr(_T_832) @[el2_lib.scala 543:35] + node _T_834 = bits(_T_662, 29, 29) @[el2_lib.scala 543:44] + node _T_835 = not(_T_834) @[el2_lib.scala 543:40] + node _T_836 = bits(_T_662, 29, 29) @[el2_lib.scala 543:51] + node _T_837 = mux(_T_833, _T_835, _T_836) @[el2_lib.scala 543:23] + _T_663[28] <= _T_837 @[el2_lib.scala 543:17] + node _T_838 = bits(_T_662, 29, 0) @[el2_lib.scala 543:27] + node _T_839 = orr(_T_838) @[el2_lib.scala 543:35] + node _T_840 = bits(_T_662, 30, 30) @[el2_lib.scala 543:44] + node _T_841 = not(_T_840) @[el2_lib.scala 543:40] + node _T_842 = bits(_T_662, 30, 30) @[el2_lib.scala 543:51] + node _T_843 = mux(_T_839, _T_841, _T_842) @[el2_lib.scala 543:23] + _T_663[29] <= _T_843 @[el2_lib.scala 543:17] + node _T_844 = bits(_T_662, 30, 0) @[el2_lib.scala 543:27] + node _T_845 = orr(_T_844) @[el2_lib.scala 543:35] + node _T_846 = bits(_T_662, 31, 31) @[el2_lib.scala 543:44] + node _T_847 = not(_T_846) @[el2_lib.scala 543:40] + node _T_848 = bits(_T_662, 31, 31) @[el2_lib.scala 543:51] + node _T_849 = mux(_T_845, _T_847, _T_848) @[el2_lib.scala 543:23] + _T_663[30] <= _T_849 @[el2_lib.scala 543:17] + node _T_850 = cat(_T_663[2], _T_663[1]) @[el2_lib.scala 545:14] + node _T_851 = cat(_T_850, _T_663[0]) @[el2_lib.scala 545:14] + node _T_852 = cat(_T_663[4], _T_663[3]) @[el2_lib.scala 545:14] + node _T_853 = cat(_T_663[6], _T_663[5]) @[el2_lib.scala 545:14] + node _T_854 = cat(_T_853, _T_852) @[el2_lib.scala 545:14] + node _T_855 = cat(_T_854, _T_851) @[el2_lib.scala 545:14] + node _T_856 = cat(_T_663[8], _T_663[7]) @[el2_lib.scala 545:14] + node _T_857 = cat(_T_663[10], _T_663[9]) @[el2_lib.scala 545:14] + node _T_858 = cat(_T_857, _T_856) @[el2_lib.scala 545:14] + node _T_859 = cat(_T_663[12], _T_663[11]) @[el2_lib.scala 545:14] + node _T_860 = cat(_T_663[14], _T_663[13]) @[el2_lib.scala 545:14] + node _T_861 = cat(_T_860, _T_859) @[el2_lib.scala 545:14] + node _T_862 = cat(_T_861, _T_858) @[el2_lib.scala 545:14] + node _T_863 = cat(_T_862, _T_855) @[el2_lib.scala 545:14] + node _T_864 = cat(_T_663[16], _T_663[15]) @[el2_lib.scala 545:14] + node _T_865 = cat(_T_663[18], _T_663[17]) @[el2_lib.scala 545:14] + node _T_866 = cat(_T_865, _T_864) @[el2_lib.scala 545:14] + node _T_867 = cat(_T_663[20], _T_663[19]) @[el2_lib.scala 545:14] + node _T_868 = cat(_T_663[22], _T_663[21]) @[el2_lib.scala 545:14] + node _T_869 = cat(_T_868, _T_867) @[el2_lib.scala 545:14] + node _T_870 = cat(_T_869, _T_866) @[el2_lib.scala 545:14] + node _T_871 = cat(_T_663[24], _T_663[23]) @[el2_lib.scala 545:14] + node _T_872 = cat(_T_663[26], _T_663[25]) @[el2_lib.scala 545:14] + node _T_873 = cat(_T_872, _T_871) @[el2_lib.scala 545:14] + node _T_874 = cat(_T_663[28], _T_663[27]) @[el2_lib.scala 545:14] + node _T_875 = cat(_T_663[30], _T_663[29]) @[el2_lib.scala 545:14] + node _T_876 = cat(_T_875, _T_874) @[el2_lib.scala 545:14] + node _T_877 = cat(_T_876, _T_873) @[el2_lib.scala 545:14] + node _T_878 = cat(_T_877, _T_870) @[el2_lib.scala 545:14] + node _T_879 = cat(_T_878, _T_863) @[el2_lib.scala 545:14] + node _T_880 = bits(_T_662, 0, 0) @[el2_lib.scala 545:24] + node _T_881 = cat(_T_879, _T_880) @[Cat.scala 29:58] + node _T_882 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 175:86] + node _T_883 = mux(_T_661, _T_881, _T_882) @[el2_exu_div_ctl.scala 175:22] + dividend_eff <= _T_883 @[el2_exu_div_ctl.scala 175:16] + node _T_884 = bits(add, 0, 0) @[el2_exu_div_ctl.scala 178:20] + node _T_885 = not(m_ff) @[el2_exu_div_ctl.scala 178:35] + node _T_886 = mux(_T_884, m_ff, _T_885) @[el2_exu_div_ctl.scala 178:15] + m_eff <= _T_886 @[el2_exu_div_ctl.scala 178:9] + node _T_887 = cat(UInt<24>("h00"), dividend_eff) @[Cat.scala 29:58] + node _T_888 = dshl(_T_887, shortq_shift_ff) @[el2_exu_div_ctl.scala 179:47] + a_eff_shift <= _T_888 @[el2_exu_div_ctl.scala 179:15] + node _T_889 = bits(rem_correct, 0, 0) @[el2_exu_div_ctl.scala 181:17] + node _T_890 = eq(rem_correct, UInt<1>("h00")) @[el2_exu_div_ctl.scala 182:6] + node _T_891 = eq(shortq_enable_ff, UInt<1>("h00")) @[el2_exu_div_ctl.scala 182:21] + node _T_892 = and(_T_890, _T_891) @[el2_exu_div_ctl.scala 182:19] + node _T_893 = bits(_T_892, 0, 0) @[el2_exu_div_ctl.scala 182:40] + node _T_894 = bits(a_ff, 31, 0) @[el2_exu_div_ctl.scala 182:58] + node _T_895 = bits(q_ff, 32, 32) @[el2_exu_div_ctl.scala 182:70] + node _T_896 = cat(_T_894, _T_895) @[Cat.scala 29:58] + node _T_897 = eq(rem_correct, UInt<1>("h00")) @[el2_exu_div_ctl.scala 183:6] + node _T_898 = and(_T_897, shortq_enable_ff) @[el2_exu_div_ctl.scala 183:19] + node _T_899 = bits(_T_898, 0, 0) @[el2_exu_div_ctl.scala 183:40] + node _T_900 = bits(a_eff_shift, 55, 32) @[el2_exu_div_ctl.scala 183:74] + node _T_901 = cat(UInt<9>("h00"), _T_900) @[Cat.scala 29:58] + node _T_902 = mux(_T_889, a_ff, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_903 = mux(_T_893, _T_896, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_904 = mux(_T_899, _T_901, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_905 = or(_T_902, _T_903) @[Mux.scala 27:72] + node _T_906 = or(_T_905, _T_904) @[Mux.scala 27:72] + wire _T_907 : UInt<33> @[Mux.scala 27:72] + _T_907 <= _T_906 @[Mux.scala 27:72] + a_eff <= _T_907 @[el2_exu_div_ctl.scala 180:9] + node _T_908 = eq(shortq_enable, UInt<1>("h00")) @[el2_exu_div_ctl.scala 185:49] + node _T_909 = and(run_state, _T_908) @[el2_exu_div_ctl.scala 185:47] + node _T_910 = neq(count, UInt<6>("h021")) @[el2_exu_div_ctl.scala 185:73] + node _T_911 = and(_T_909, _T_910) @[el2_exu_div_ctl.scala 185:64] + node _T_912 = or(io.dp.valid, _T_911) @[el2_exu_div_ctl.scala 185:34] + node aff_enable = or(_T_912, rem_correct) @[el2_exu_div_ctl.scala 185:89] + node _T_913 = bits(run_state, 0, 0) @[Bitwise.scala 72:15] + node _T_914 = mux(_T_913, UInt<33>("h01ffffffff"), UInt<33>("h00")) @[Bitwise.scala 72:12] + node _T_915 = and(_T_914, a_eff) @[el2_exu_div_ctl.scala 186:33] + a_shift <= _T_915 @[el2_exu_div_ctl.scala 186:11] + node _T_916 = bits(run_state, 0, 0) @[Bitwise.scala 72:15] + node _T_917 = mux(_T_916, UInt<33>("h01ffffffff"), UInt<33>("h00")) @[Bitwise.scala 72:12] + node _T_918 = add(a_shift, m_eff) @[el2_exu_div_ctl.scala 187:41] + node _T_919 = tail(_T_918, 1) @[el2_exu_div_ctl.scala 187:41] + node _T_920 = eq(add, UInt<1>("h00")) @[el2_exu_div_ctl.scala 187:65] + node _T_921 = cat(UInt<32>("h00"), _T_920) @[Cat.scala 29:58] + node _T_922 = add(_T_919, _T_921) @[el2_exu_div_ctl.scala 187:49] + node _T_923 = tail(_T_922, 1) @[el2_exu_div_ctl.scala 187:49] + node _T_924 = and(_T_917, _T_923) @[el2_exu_div_ctl.scala 187:30] + a_in <= _T_924 @[el2_exu_div_ctl.scala 187:8] + node m_already_comp = and(divisor_neg_ff, sign_ff) @[el2_exu_div_ctl.scala 188:48] + node _T_925 = bits(a_ff, 32, 32) @[el2_exu_div_ctl.scala 190:16] + node _T_926 = or(_T_925, rem_correct) @[el2_exu_div_ctl.scala 190:21] + node _T_927 = xor(_T_926, m_already_comp) @[el2_exu_div_ctl.scala 190:36] + add <= _T_927 @[el2_exu_div_ctl.scala 190:8] + node _T_928 = eq(count, UInt<6>("h021")) @[el2_exu_div_ctl.scala 191:26] + node _T_929 = and(_T_928, rem_ff) @[el2_exu_div_ctl.scala 191:41] + node _T_930 = bits(a_ff, 32, 32) @[el2_exu_div_ctl.scala 191:56] + node _T_931 = and(_T_929, _T_930) @[el2_exu_div_ctl.scala 191:50] + rem_correct <= _T_931 @[el2_exu_div_ctl.scala 191:16] + node _T_932 = xor(dividend_neg_ff, divisor_neg_ff) @[el2_exu_div_ctl.scala 192:50] + node _T_933 = and(sign_ff, _T_932) @[el2_exu_div_ctl.scala 192:31] + node _T_934 = bits(_T_933, 0, 0) @[el2_exu_div_ctl.scala 192:69] + node _T_935 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 192:91] + wire _T_936 : UInt<1>[31] @[el2_lib.scala 541:20] + node _T_937 = bits(_T_935, 0, 0) @[el2_lib.scala 543:27] + node _T_938 = orr(_T_937) @[el2_lib.scala 543:35] + node _T_939 = bits(_T_935, 1, 1) @[el2_lib.scala 543:44] + node _T_940 = not(_T_939) @[el2_lib.scala 543:40] + node _T_941 = bits(_T_935, 1, 1) @[el2_lib.scala 543:51] + node _T_942 = mux(_T_938, _T_940, _T_941) @[el2_lib.scala 543:23] + _T_936[0] <= _T_942 @[el2_lib.scala 543:17] + node _T_943 = bits(_T_935, 1, 0) @[el2_lib.scala 543:27] + node _T_944 = orr(_T_943) @[el2_lib.scala 543:35] + node _T_945 = bits(_T_935, 2, 2) @[el2_lib.scala 543:44] + node _T_946 = not(_T_945) @[el2_lib.scala 543:40] + node _T_947 = bits(_T_935, 2, 2) @[el2_lib.scala 543:51] + node _T_948 = mux(_T_944, _T_946, _T_947) @[el2_lib.scala 543:23] + _T_936[1] <= _T_948 @[el2_lib.scala 543:17] + node _T_949 = bits(_T_935, 2, 0) @[el2_lib.scala 543:27] + node _T_950 = orr(_T_949) @[el2_lib.scala 543:35] + node _T_951 = bits(_T_935, 3, 3) @[el2_lib.scala 543:44] + node _T_952 = not(_T_951) @[el2_lib.scala 543:40] + node _T_953 = bits(_T_935, 3, 3) @[el2_lib.scala 543:51] + node _T_954 = mux(_T_950, _T_952, _T_953) @[el2_lib.scala 543:23] + _T_936[2] <= _T_954 @[el2_lib.scala 543:17] + node _T_955 = bits(_T_935, 3, 0) @[el2_lib.scala 543:27] + node _T_956 = orr(_T_955) @[el2_lib.scala 543:35] + node _T_957 = bits(_T_935, 4, 4) @[el2_lib.scala 543:44] + node _T_958 = not(_T_957) @[el2_lib.scala 543:40] + node _T_959 = bits(_T_935, 4, 4) @[el2_lib.scala 543:51] + node _T_960 = mux(_T_956, _T_958, _T_959) @[el2_lib.scala 543:23] + _T_936[3] <= _T_960 @[el2_lib.scala 543:17] + node _T_961 = bits(_T_935, 4, 0) @[el2_lib.scala 543:27] + node _T_962 = orr(_T_961) @[el2_lib.scala 543:35] + node _T_963 = bits(_T_935, 5, 5) @[el2_lib.scala 543:44] + node _T_964 = not(_T_963) @[el2_lib.scala 543:40] + node _T_965 = bits(_T_935, 5, 5) @[el2_lib.scala 543:51] + node _T_966 = mux(_T_962, _T_964, _T_965) @[el2_lib.scala 543:23] + _T_936[4] <= _T_966 @[el2_lib.scala 543:17] + node _T_967 = bits(_T_935, 5, 0) @[el2_lib.scala 543:27] + node _T_968 = orr(_T_967) @[el2_lib.scala 543:35] + node _T_969 = bits(_T_935, 6, 6) @[el2_lib.scala 543:44] + node _T_970 = not(_T_969) @[el2_lib.scala 543:40] + node _T_971 = bits(_T_935, 6, 6) @[el2_lib.scala 543:51] + node _T_972 = mux(_T_968, _T_970, _T_971) @[el2_lib.scala 543:23] + _T_936[5] <= _T_972 @[el2_lib.scala 543:17] + node _T_973 = bits(_T_935, 6, 0) @[el2_lib.scala 543:27] + node _T_974 = orr(_T_973) @[el2_lib.scala 543:35] + node _T_975 = bits(_T_935, 7, 7) @[el2_lib.scala 543:44] + node _T_976 = not(_T_975) @[el2_lib.scala 543:40] + node _T_977 = bits(_T_935, 7, 7) @[el2_lib.scala 543:51] + node _T_978 = mux(_T_974, _T_976, _T_977) @[el2_lib.scala 543:23] + _T_936[6] <= _T_978 @[el2_lib.scala 543:17] + node _T_979 = bits(_T_935, 7, 0) @[el2_lib.scala 543:27] + node _T_980 = orr(_T_979) @[el2_lib.scala 543:35] + node _T_981 = bits(_T_935, 8, 8) @[el2_lib.scala 543:44] + node _T_982 = not(_T_981) @[el2_lib.scala 543:40] + node _T_983 = bits(_T_935, 8, 8) @[el2_lib.scala 543:51] + node _T_984 = mux(_T_980, _T_982, _T_983) @[el2_lib.scala 543:23] + _T_936[7] <= _T_984 @[el2_lib.scala 543:17] + node _T_985 = bits(_T_935, 8, 0) @[el2_lib.scala 543:27] + node _T_986 = orr(_T_985) @[el2_lib.scala 543:35] + node _T_987 = bits(_T_935, 9, 9) @[el2_lib.scala 543:44] + node _T_988 = not(_T_987) @[el2_lib.scala 543:40] + node _T_989 = bits(_T_935, 9, 9) @[el2_lib.scala 543:51] + node _T_990 = mux(_T_986, _T_988, _T_989) @[el2_lib.scala 543:23] + _T_936[8] <= _T_990 @[el2_lib.scala 543:17] + node _T_991 = bits(_T_935, 9, 0) @[el2_lib.scala 543:27] + node _T_992 = orr(_T_991) @[el2_lib.scala 543:35] + node _T_993 = bits(_T_935, 10, 10) @[el2_lib.scala 543:44] + node _T_994 = not(_T_993) @[el2_lib.scala 543:40] + node _T_995 = bits(_T_935, 10, 10) @[el2_lib.scala 543:51] + node _T_996 = mux(_T_992, _T_994, _T_995) @[el2_lib.scala 543:23] + _T_936[9] <= _T_996 @[el2_lib.scala 543:17] + node _T_997 = bits(_T_935, 10, 0) @[el2_lib.scala 543:27] + node _T_998 = orr(_T_997) @[el2_lib.scala 543:35] + node _T_999 = bits(_T_935, 11, 11) @[el2_lib.scala 543:44] + node _T_1000 = not(_T_999) @[el2_lib.scala 543:40] + node _T_1001 = bits(_T_935, 11, 11) @[el2_lib.scala 543:51] + node _T_1002 = mux(_T_998, _T_1000, _T_1001) @[el2_lib.scala 543:23] + _T_936[10] <= _T_1002 @[el2_lib.scala 543:17] + node _T_1003 = bits(_T_935, 11, 0) @[el2_lib.scala 543:27] + node _T_1004 = orr(_T_1003) @[el2_lib.scala 543:35] + node _T_1005 = bits(_T_935, 12, 12) @[el2_lib.scala 543:44] + node _T_1006 = not(_T_1005) @[el2_lib.scala 543:40] + node _T_1007 = bits(_T_935, 12, 12) @[el2_lib.scala 543:51] + node _T_1008 = mux(_T_1004, _T_1006, _T_1007) @[el2_lib.scala 543:23] + _T_936[11] <= _T_1008 @[el2_lib.scala 543:17] + node _T_1009 = bits(_T_935, 12, 0) @[el2_lib.scala 543:27] + node _T_1010 = orr(_T_1009) @[el2_lib.scala 543:35] + node _T_1011 = bits(_T_935, 13, 13) @[el2_lib.scala 543:44] + node _T_1012 = not(_T_1011) @[el2_lib.scala 543:40] + node _T_1013 = bits(_T_935, 13, 13) @[el2_lib.scala 543:51] + node _T_1014 = mux(_T_1010, _T_1012, _T_1013) @[el2_lib.scala 543:23] + _T_936[12] <= _T_1014 @[el2_lib.scala 543:17] + node _T_1015 = bits(_T_935, 13, 0) @[el2_lib.scala 543:27] + node _T_1016 = orr(_T_1015) @[el2_lib.scala 543:35] + node _T_1017 = bits(_T_935, 14, 14) @[el2_lib.scala 543:44] + node _T_1018 = not(_T_1017) @[el2_lib.scala 543:40] + node _T_1019 = bits(_T_935, 14, 14) @[el2_lib.scala 543:51] + node _T_1020 = mux(_T_1016, _T_1018, _T_1019) @[el2_lib.scala 543:23] + _T_936[13] <= _T_1020 @[el2_lib.scala 543:17] + node _T_1021 = bits(_T_935, 14, 0) @[el2_lib.scala 543:27] + node _T_1022 = orr(_T_1021) @[el2_lib.scala 543:35] + node _T_1023 = bits(_T_935, 15, 15) @[el2_lib.scala 543:44] + node _T_1024 = not(_T_1023) @[el2_lib.scala 543:40] + node _T_1025 = bits(_T_935, 15, 15) @[el2_lib.scala 543:51] + node _T_1026 = mux(_T_1022, _T_1024, _T_1025) @[el2_lib.scala 543:23] + _T_936[14] <= _T_1026 @[el2_lib.scala 543:17] + node _T_1027 = bits(_T_935, 15, 0) @[el2_lib.scala 543:27] + node _T_1028 = orr(_T_1027) @[el2_lib.scala 543:35] + node _T_1029 = bits(_T_935, 16, 16) @[el2_lib.scala 543:44] + node _T_1030 = not(_T_1029) @[el2_lib.scala 543:40] + node _T_1031 = bits(_T_935, 16, 16) @[el2_lib.scala 543:51] + node _T_1032 = mux(_T_1028, _T_1030, _T_1031) @[el2_lib.scala 543:23] + _T_936[15] <= _T_1032 @[el2_lib.scala 543:17] + node _T_1033 = bits(_T_935, 16, 0) @[el2_lib.scala 543:27] + node _T_1034 = orr(_T_1033) @[el2_lib.scala 543:35] + node _T_1035 = bits(_T_935, 17, 17) @[el2_lib.scala 543:44] + node _T_1036 = not(_T_1035) @[el2_lib.scala 543:40] + node _T_1037 = bits(_T_935, 17, 17) @[el2_lib.scala 543:51] + node _T_1038 = mux(_T_1034, _T_1036, _T_1037) @[el2_lib.scala 543:23] + _T_936[16] <= _T_1038 @[el2_lib.scala 543:17] + node _T_1039 = bits(_T_935, 17, 0) @[el2_lib.scala 543:27] + node _T_1040 = orr(_T_1039) @[el2_lib.scala 543:35] + node _T_1041 = bits(_T_935, 18, 18) @[el2_lib.scala 543:44] + node _T_1042 = not(_T_1041) @[el2_lib.scala 543:40] + node _T_1043 = bits(_T_935, 18, 18) @[el2_lib.scala 543:51] + node _T_1044 = mux(_T_1040, _T_1042, _T_1043) @[el2_lib.scala 543:23] + _T_936[17] <= _T_1044 @[el2_lib.scala 543:17] + node _T_1045 = bits(_T_935, 18, 0) @[el2_lib.scala 543:27] + node _T_1046 = orr(_T_1045) @[el2_lib.scala 543:35] + node _T_1047 = bits(_T_935, 19, 19) @[el2_lib.scala 543:44] + node _T_1048 = not(_T_1047) @[el2_lib.scala 543:40] + node _T_1049 = bits(_T_935, 19, 19) @[el2_lib.scala 543:51] + node _T_1050 = mux(_T_1046, _T_1048, _T_1049) @[el2_lib.scala 543:23] + _T_936[18] <= _T_1050 @[el2_lib.scala 543:17] + node _T_1051 = bits(_T_935, 19, 0) @[el2_lib.scala 543:27] + node _T_1052 = orr(_T_1051) @[el2_lib.scala 543:35] + node _T_1053 = bits(_T_935, 20, 20) @[el2_lib.scala 543:44] + node _T_1054 = not(_T_1053) @[el2_lib.scala 543:40] + node _T_1055 = bits(_T_935, 20, 20) @[el2_lib.scala 543:51] + node _T_1056 = mux(_T_1052, _T_1054, _T_1055) @[el2_lib.scala 543:23] + _T_936[19] <= _T_1056 @[el2_lib.scala 543:17] + node _T_1057 = bits(_T_935, 20, 0) @[el2_lib.scala 543:27] + node _T_1058 = orr(_T_1057) @[el2_lib.scala 543:35] + node _T_1059 = bits(_T_935, 21, 21) @[el2_lib.scala 543:44] + node _T_1060 = not(_T_1059) @[el2_lib.scala 543:40] + node _T_1061 = bits(_T_935, 21, 21) @[el2_lib.scala 543:51] + node _T_1062 = mux(_T_1058, _T_1060, _T_1061) @[el2_lib.scala 543:23] + _T_936[20] <= _T_1062 @[el2_lib.scala 543:17] + node _T_1063 = bits(_T_935, 21, 0) @[el2_lib.scala 543:27] + node _T_1064 = orr(_T_1063) @[el2_lib.scala 543:35] + node _T_1065 = bits(_T_935, 22, 22) @[el2_lib.scala 543:44] + node _T_1066 = not(_T_1065) @[el2_lib.scala 543:40] + node _T_1067 = bits(_T_935, 22, 22) @[el2_lib.scala 543:51] + node _T_1068 = mux(_T_1064, _T_1066, _T_1067) @[el2_lib.scala 543:23] + _T_936[21] <= _T_1068 @[el2_lib.scala 543:17] + node _T_1069 = bits(_T_935, 22, 0) @[el2_lib.scala 543:27] + node _T_1070 = orr(_T_1069) @[el2_lib.scala 543:35] + node _T_1071 = bits(_T_935, 23, 23) @[el2_lib.scala 543:44] + node _T_1072 = not(_T_1071) @[el2_lib.scala 543:40] + node _T_1073 = bits(_T_935, 23, 23) @[el2_lib.scala 543:51] + node _T_1074 = mux(_T_1070, _T_1072, _T_1073) @[el2_lib.scala 543:23] + _T_936[22] <= _T_1074 @[el2_lib.scala 543:17] + node _T_1075 = bits(_T_935, 23, 0) @[el2_lib.scala 543:27] + node _T_1076 = orr(_T_1075) @[el2_lib.scala 543:35] + node _T_1077 = bits(_T_935, 24, 24) @[el2_lib.scala 543:44] + node _T_1078 = not(_T_1077) @[el2_lib.scala 543:40] + node _T_1079 = bits(_T_935, 24, 24) @[el2_lib.scala 543:51] + node _T_1080 = mux(_T_1076, _T_1078, _T_1079) @[el2_lib.scala 543:23] + _T_936[23] <= _T_1080 @[el2_lib.scala 543:17] + node _T_1081 = bits(_T_935, 24, 0) @[el2_lib.scala 543:27] + node _T_1082 = orr(_T_1081) @[el2_lib.scala 543:35] + node _T_1083 = bits(_T_935, 25, 25) @[el2_lib.scala 543:44] + node _T_1084 = not(_T_1083) @[el2_lib.scala 543:40] + node _T_1085 = bits(_T_935, 25, 25) @[el2_lib.scala 543:51] + node _T_1086 = mux(_T_1082, _T_1084, _T_1085) @[el2_lib.scala 543:23] + _T_936[24] <= _T_1086 @[el2_lib.scala 543:17] + node _T_1087 = bits(_T_935, 25, 0) @[el2_lib.scala 543:27] + node _T_1088 = orr(_T_1087) @[el2_lib.scala 543:35] + node _T_1089 = bits(_T_935, 26, 26) @[el2_lib.scala 543:44] + node _T_1090 = not(_T_1089) @[el2_lib.scala 543:40] + node _T_1091 = bits(_T_935, 26, 26) @[el2_lib.scala 543:51] + node _T_1092 = mux(_T_1088, _T_1090, _T_1091) @[el2_lib.scala 543:23] + _T_936[25] <= _T_1092 @[el2_lib.scala 543:17] + node _T_1093 = bits(_T_935, 26, 0) @[el2_lib.scala 543:27] + node _T_1094 = orr(_T_1093) @[el2_lib.scala 543:35] + node _T_1095 = bits(_T_935, 27, 27) @[el2_lib.scala 543:44] + node _T_1096 = not(_T_1095) @[el2_lib.scala 543:40] + node _T_1097 = bits(_T_935, 27, 27) @[el2_lib.scala 543:51] + node _T_1098 = mux(_T_1094, _T_1096, _T_1097) @[el2_lib.scala 543:23] + _T_936[26] <= _T_1098 @[el2_lib.scala 543:17] + node _T_1099 = bits(_T_935, 27, 0) @[el2_lib.scala 543:27] + node _T_1100 = orr(_T_1099) @[el2_lib.scala 543:35] + node _T_1101 = bits(_T_935, 28, 28) @[el2_lib.scala 543:44] + node _T_1102 = not(_T_1101) @[el2_lib.scala 543:40] + node _T_1103 = bits(_T_935, 28, 28) @[el2_lib.scala 543:51] + node _T_1104 = mux(_T_1100, _T_1102, _T_1103) @[el2_lib.scala 543:23] + _T_936[27] <= _T_1104 @[el2_lib.scala 543:17] + node _T_1105 = bits(_T_935, 28, 0) @[el2_lib.scala 543:27] + node _T_1106 = orr(_T_1105) @[el2_lib.scala 543:35] + node _T_1107 = bits(_T_935, 29, 29) @[el2_lib.scala 543:44] + node _T_1108 = not(_T_1107) @[el2_lib.scala 543:40] + node _T_1109 = bits(_T_935, 29, 29) @[el2_lib.scala 543:51] + node _T_1110 = mux(_T_1106, _T_1108, _T_1109) @[el2_lib.scala 543:23] + _T_936[28] <= _T_1110 @[el2_lib.scala 543:17] + node _T_1111 = bits(_T_935, 29, 0) @[el2_lib.scala 543:27] + node _T_1112 = orr(_T_1111) @[el2_lib.scala 543:35] + node _T_1113 = bits(_T_935, 30, 30) @[el2_lib.scala 543:44] + node _T_1114 = not(_T_1113) @[el2_lib.scala 543:40] + node _T_1115 = bits(_T_935, 30, 30) @[el2_lib.scala 543:51] + node _T_1116 = mux(_T_1112, _T_1114, _T_1115) @[el2_lib.scala 543:23] + _T_936[29] <= _T_1116 @[el2_lib.scala 543:17] + node _T_1117 = bits(_T_935, 30, 0) @[el2_lib.scala 543:27] + node _T_1118 = orr(_T_1117) @[el2_lib.scala 543:35] + node _T_1119 = bits(_T_935, 31, 31) @[el2_lib.scala 543:44] + node _T_1120 = not(_T_1119) @[el2_lib.scala 543:40] + node _T_1121 = bits(_T_935, 31, 31) @[el2_lib.scala 543:51] + node _T_1122 = mux(_T_1118, _T_1120, _T_1121) @[el2_lib.scala 543:23] + _T_936[30] <= _T_1122 @[el2_lib.scala 543:17] + node _T_1123 = cat(_T_936[2], _T_936[1]) @[el2_lib.scala 545:14] + node _T_1124 = cat(_T_1123, _T_936[0]) @[el2_lib.scala 545:14] + node _T_1125 = cat(_T_936[4], _T_936[3]) @[el2_lib.scala 545:14] + node _T_1126 = cat(_T_936[6], _T_936[5]) @[el2_lib.scala 545:14] + node _T_1127 = cat(_T_1126, _T_1125) @[el2_lib.scala 545:14] + node _T_1128 = cat(_T_1127, _T_1124) @[el2_lib.scala 545:14] + node _T_1129 = cat(_T_936[8], _T_936[7]) @[el2_lib.scala 545:14] + node _T_1130 = cat(_T_936[10], _T_936[9]) @[el2_lib.scala 545:14] + node _T_1131 = cat(_T_1130, _T_1129) @[el2_lib.scala 545:14] + node _T_1132 = cat(_T_936[12], _T_936[11]) @[el2_lib.scala 545:14] + node _T_1133 = cat(_T_936[14], _T_936[13]) @[el2_lib.scala 545:14] + node _T_1134 = cat(_T_1133, _T_1132) @[el2_lib.scala 545:14] + node _T_1135 = cat(_T_1134, _T_1131) @[el2_lib.scala 545:14] + node _T_1136 = cat(_T_1135, _T_1128) @[el2_lib.scala 545:14] + node _T_1137 = cat(_T_936[16], _T_936[15]) @[el2_lib.scala 545:14] + node _T_1138 = cat(_T_936[18], _T_936[17]) @[el2_lib.scala 545:14] + node _T_1139 = cat(_T_1138, _T_1137) @[el2_lib.scala 545:14] + node _T_1140 = cat(_T_936[20], _T_936[19]) @[el2_lib.scala 545:14] + node _T_1141 = cat(_T_936[22], _T_936[21]) @[el2_lib.scala 545:14] + node _T_1142 = cat(_T_1141, _T_1140) @[el2_lib.scala 545:14] + node _T_1143 = cat(_T_1142, _T_1139) @[el2_lib.scala 545:14] + node _T_1144 = cat(_T_936[24], _T_936[23]) @[el2_lib.scala 545:14] + node _T_1145 = cat(_T_936[26], _T_936[25]) @[el2_lib.scala 545:14] + node _T_1146 = cat(_T_1145, _T_1144) @[el2_lib.scala 545:14] + node _T_1147 = cat(_T_936[28], _T_936[27]) @[el2_lib.scala 545:14] + node _T_1148 = cat(_T_936[30], _T_936[29]) @[el2_lib.scala 545:14] + node _T_1149 = cat(_T_1148, _T_1147) @[el2_lib.scala 545:14] + node _T_1150 = cat(_T_1149, _T_1146) @[el2_lib.scala 545:14] + node _T_1151 = cat(_T_1150, _T_1143) @[el2_lib.scala 545:14] + node _T_1152 = cat(_T_1151, _T_1136) @[el2_lib.scala 545:14] + node _T_1153 = bits(_T_935, 0, 0) @[el2_lib.scala 545:24] + node _T_1154 = cat(_T_1152, _T_1153) @[Cat.scala 29:58] + node _T_1155 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 192:104] + node q_ff_eff = mux(_T_934, _T_1154, _T_1155) @[el2_exu_div_ctl.scala 192:21] + node _T_1156 = and(sign_ff, dividend_neg_ff) @[el2_exu_div_ctl.scala 193:31] + node _T_1157 = bits(_T_1156, 0, 0) @[el2_exu_div_ctl.scala 193:51] + node _T_1158 = bits(a_ff, 31, 0) @[el2_exu_div_ctl.scala 193:74] + wire _T_1159 : UInt<1>[31] @[el2_lib.scala 541:20] + node _T_1160 = bits(_T_1158, 0, 0) @[el2_lib.scala 543:27] + node _T_1161 = orr(_T_1160) @[el2_lib.scala 543:35] + node _T_1162 = bits(_T_1158, 1, 1) @[el2_lib.scala 543:44] + node _T_1163 = not(_T_1162) @[el2_lib.scala 543:40] + node _T_1164 = bits(_T_1158, 1, 1) @[el2_lib.scala 543:51] + node _T_1165 = mux(_T_1161, _T_1163, _T_1164) @[el2_lib.scala 543:23] + _T_1159[0] <= _T_1165 @[el2_lib.scala 543:17] + node _T_1166 = bits(_T_1158, 1, 0) @[el2_lib.scala 543:27] + node _T_1167 = orr(_T_1166) @[el2_lib.scala 543:35] + node _T_1168 = bits(_T_1158, 2, 2) @[el2_lib.scala 543:44] + node _T_1169 = not(_T_1168) @[el2_lib.scala 543:40] + node _T_1170 = bits(_T_1158, 2, 2) @[el2_lib.scala 543:51] + node _T_1171 = mux(_T_1167, _T_1169, _T_1170) @[el2_lib.scala 543:23] + _T_1159[1] <= _T_1171 @[el2_lib.scala 543:17] + node _T_1172 = bits(_T_1158, 2, 0) @[el2_lib.scala 543:27] + node _T_1173 = orr(_T_1172) @[el2_lib.scala 543:35] + node _T_1174 = bits(_T_1158, 3, 3) @[el2_lib.scala 543:44] + node _T_1175 = not(_T_1174) @[el2_lib.scala 543:40] + node _T_1176 = bits(_T_1158, 3, 3) @[el2_lib.scala 543:51] + node _T_1177 = mux(_T_1173, _T_1175, _T_1176) @[el2_lib.scala 543:23] + _T_1159[2] <= _T_1177 @[el2_lib.scala 543:17] + node _T_1178 = bits(_T_1158, 3, 0) @[el2_lib.scala 543:27] + node _T_1179 = orr(_T_1178) @[el2_lib.scala 543:35] + node _T_1180 = bits(_T_1158, 4, 4) @[el2_lib.scala 543:44] + node _T_1181 = not(_T_1180) @[el2_lib.scala 543:40] + node _T_1182 = bits(_T_1158, 4, 4) @[el2_lib.scala 543:51] + node _T_1183 = mux(_T_1179, _T_1181, _T_1182) @[el2_lib.scala 543:23] + _T_1159[3] <= _T_1183 @[el2_lib.scala 543:17] + node _T_1184 = bits(_T_1158, 4, 0) @[el2_lib.scala 543:27] + node _T_1185 = orr(_T_1184) @[el2_lib.scala 543:35] + node _T_1186 = bits(_T_1158, 5, 5) @[el2_lib.scala 543:44] + node _T_1187 = not(_T_1186) @[el2_lib.scala 543:40] + node _T_1188 = bits(_T_1158, 5, 5) @[el2_lib.scala 543:51] + node _T_1189 = mux(_T_1185, _T_1187, _T_1188) @[el2_lib.scala 543:23] + _T_1159[4] <= _T_1189 @[el2_lib.scala 543:17] + node _T_1190 = bits(_T_1158, 5, 0) @[el2_lib.scala 543:27] + node _T_1191 = orr(_T_1190) @[el2_lib.scala 543:35] + node _T_1192 = bits(_T_1158, 6, 6) @[el2_lib.scala 543:44] + node _T_1193 = not(_T_1192) @[el2_lib.scala 543:40] + node _T_1194 = bits(_T_1158, 6, 6) @[el2_lib.scala 543:51] + node _T_1195 = mux(_T_1191, _T_1193, _T_1194) @[el2_lib.scala 543:23] + _T_1159[5] <= _T_1195 @[el2_lib.scala 543:17] + node _T_1196 = bits(_T_1158, 6, 0) @[el2_lib.scala 543:27] + node _T_1197 = orr(_T_1196) @[el2_lib.scala 543:35] + node _T_1198 = bits(_T_1158, 7, 7) @[el2_lib.scala 543:44] + node _T_1199 = not(_T_1198) @[el2_lib.scala 543:40] + node _T_1200 = bits(_T_1158, 7, 7) @[el2_lib.scala 543:51] + node _T_1201 = mux(_T_1197, _T_1199, _T_1200) @[el2_lib.scala 543:23] + _T_1159[6] <= _T_1201 @[el2_lib.scala 543:17] + node _T_1202 = bits(_T_1158, 7, 0) @[el2_lib.scala 543:27] + node _T_1203 = orr(_T_1202) @[el2_lib.scala 543:35] + node _T_1204 = bits(_T_1158, 8, 8) @[el2_lib.scala 543:44] + node _T_1205 = not(_T_1204) @[el2_lib.scala 543:40] + node _T_1206 = bits(_T_1158, 8, 8) @[el2_lib.scala 543:51] + node _T_1207 = mux(_T_1203, _T_1205, _T_1206) @[el2_lib.scala 543:23] + _T_1159[7] <= _T_1207 @[el2_lib.scala 543:17] + node _T_1208 = bits(_T_1158, 8, 0) @[el2_lib.scala 543:27] + node _T_1209 = orr(_T_1208) @[el2_lib.scala 543:35] + node _T_1210 = bits(_T_1158, 9, 9) @[el2_lib.scala 543:44] + node _T_1211 = not(_T_1210) @[el2_lib.scala 543:40] + node _T_1212 = bits(_T_1158, 9, 9) @[el2_lib.scala 543:51] + node _T_1213 = mux(_T_1209, _T_1211, _T_1212) @[el2_lib.scala 543:23] + _T_1159[8] <= _T_1213 @[el2_lib.scala 543:17] + node _T_1214 = bits(_T_1158, 9, 0) @[el2_lib.scala 543:27] + node _T_1215 = orr(_T_1214) @[el2_lib.scala 543:35] + node _T_1216 = bits(_T_1158, 10, 10) @[el2_lib.scala 543:44] + node _T_1217 = not(_T_1216) @[el2_lib.scala 543:40] + node _T_1218 = bits(_T_1158, 10, 10) @[el2_lib.scala 543:51] + node _T_1219 = mux(_T_1215, _T_1217, _T_1218) @[el2_lib.scala 543:23] + _T_1159[9] <= _T_1219 @[el2_lib.scala 543:17] + node _T_1220 = bits(_T_1158, 10, 0) @[el2_lib.scala 543:27] + node _T_1221 = orr(_T_1220) @[el2_lib.scala 543:35] + node _T_1222 = bits(_T_1158, 11, 11) @[el2_lib.scala 543:44] + node _T_1223 = not(_T_1222) @[el2_lib.scala 543:40] + node _T_1224 = bits(_T_1158, 11, 11) @[el2_lib.scala 543:51] + node _T_1225 = mux(_T_1221, _T_1223, _T_1224) @[el2_lib.scala 543:23] + _T_1159[10] <= _T_1225 @[el2_lib.scala 543:17] + node _T_1226 = bits(_T_1158, 11, 0) @[el2_lib.scala 543:27] + node _T_1227 = orr(_T_1226) @[el2_lib.scala 543:35] + node _T_1228 = bits(_T_1158, 12, 12) @[el2_lib.scala 543:44] + node _T_1229 = not(_T_1228) @[el2_lib.scala 543:40] + node _T_1230 = bits(_T_1158, 12, 12) @[el2_lib.scala 543:51] + node _T_1231 = mux(_T_1227, _T_1229, _T_1230) @[el2_lib.scala 543:23] + _T_1159[11] <= _T_1231 @[el2_lib.scala 543:17] + node _T_1232 = bits(_T_1158, 12, 0) @[el2_lib.scala 543:27] + node _T_1233 = orr(_T_1232) @[el2_lib.scala 543:35] + node _T_1234 = bits(_T_1158, 13, 13) @[el2_lib.scala 543:44] + node _T_1235 = not(_T_1234) @[el2_lib.scala 543:40] + node _T_1236 = bits(_T_1158, 13, 13) @[el2_lib.scala 543:51] + node _T_1237 = mux(_T_1233, _T_1235, _T_1236) @[el2_lib.scala 543:23] + _T_1159[12] <= _T_1237 @[el2_lib.scala 543:17] + node _T_1238 = bits(_T_1158, 13, 0) @[el2_lib.scala 543:27] + node _T_1239 = orr(_T_1238) @[el2_lib.scala 543:35] + node _T_1240 = bits(_T_1158, 14, 14) @[el2_lib.scala 543:44] + node _T_1241 = not(_T_1240) @[el2_lib.scala 543:40] + node _T_1242 = bits(_T_1158, 14, 14) @[el2_lib.scala 543:51] + node _T_1243 = mux(_T_1239, _T_1241, _T_1242) @[el2_lib.scala 543:23] + _T_1159[13] <= _T_1243 @[el2_lib.scala 543:17] + node _T_1244 = bits(_T_1158, 14, 0) @[el2_lib.scala 543:27] + node _T_1245 = orr(_T_1244) @[el2_lib.scala 543:35] + node _T_1246 = bits(_T_1158, 15, 15) @[el2_lib.scala 543:44] + node _T_1247 = not(_T_1246) @[el2_lib.scala 543:40] + node _T_1248 = bits(_T_1158, 15, 15) @[el2_lib.scala 543:51] + node _T_1249 = mux(_T_1245, _T_1247, _T_1248) @[el2_lib.scala 543:23] + _T_1159[14] <= _T_1249 @[el2_lib.scala 543:17] + node _T_1250 = bits(_T_1158, 15, 0) @[el2_lib.scala 543:27] + node _T_1251 = orr(_T_1250) @[el2_lib.scala 543:35] + node _T_1252 = bits(_T_1158, 16, 16) @[el2_lib.scala 543:44] + node _T_1253 = not(_T_1252) @[el2_lib.scala 543:40] + node _T_1254 = bits(_T_1158, 16, 16) @[el2_lib.scala 543:51] + node _T_1255 = mux(_T_1251, _T_1253, _T_1254) @[el2_lib.scala 543:23] + _T_1159[15] <= _T_1255 @[el2_lib.scala 543:17] + node _T_1256 = bits(_T_1158, 16, 0) @[el2_lib.scala 543:27] + node _T_1257 = orr(_T_1256) @[el2_lib.scala 543:35] + node _T_1258 = bits(_T_1158, 17, 17) @[el2_lib.scala 543:44] + node _T_1259 = not(_T_1258) @[el2_lib.scala 543:40] + node _T_1260 = bits(_T_1158, 17, 17) @[el2_lib.scala 543:51] + node _T_1261 = mux(_T_1257, _T_1259, _T_1260) @[el2_lib.scala 543:23] + _T_1159[16] <= _T_1261 @[el2_lib.scala 543:17] + node _T_1262 = bits(_T_1158, 17, 0) @[el2_lib.scala 543:27] + node _T_1263 = orr(_T_1262) @[el2_lib.scala 543:35] + node _T_1264 = bits(_T_1158, 18, 18) @[el2_lib.scala 543:44] + node _T_1265 = not(_T_1264) @[el2_lib.scala 543:40] + node _T_1266 = bits(_T_1158, 18, 18) @[el2_lib.scala 543:51] + node _T_1267 = mux(_T_1263, _T_1265, _T_1266) @[el2_lib.scala 543:23] + _T_1159[17] <= _T_1267 @[el2_lib.scala 543:17] + node _T_1268 = bits(_T_1158, 18, 0) @[el2_lib.scala 543:27] + node _T_1269 = orr(_T_1268) @[el2_lib.scala 543:35] + node _T_1270 = bits(_T_1158, 19, 19) @[el2_lib.scala 543:44] + node _T_1271 = not(_T_1270) @[el2_lib.scala 543:40] + node _T_1272 = bits(_T_1158, 19, 19) @[el2_lib.scala 543:51] + node _T_1273 = mux(_T_1269, _T_1271, _T_1272) @[el2_lib.scala 543:23] + _T_1159[18] <= _T_1273 @[el2_lib.scala 543:17] + node _T_1274 = bits(_T_1158, 19, 0) @[el2_lib.scala 543:27] + node _T_1275 = orr(_T_1274) @[el2_lib.scala 543:35] + node _T_1276 = bits(_T_1158, 20, 20) @[el2_lib.scala 543:44] + node _T_1277 = not(_T_1276) @[el2_lib.scala 543:40] + node _T_1278 = bits(_T_1158, 20, 20) @[el2_lib.scala 543:51] + node _T_1279 = mux(_T_1275, _T_1277, _T_1278) @[el2_lib.scala 543:23] + _T_1159[19] <= _T_1279 @[el2_lib.scala 543:17] + node _T_1280 = bits(_T_1158, 20, 0) @[el2_lib.scala 543:27] + node _T_1281 = orr(_T_1280) @[el2_lib.scala 543:35] + node _T_1282 = bits(_T_1158, 21, 21) @[el2_lib.scala 543:44] + node _T_1283 = not(_T_1282) @[el2_lib.scala 543:40] + node _T_1284 = bits(_T_1158, 21, 21) @[el2_lib.scala 543:51] + node _T_1285 = mux(_T_1281, _T_1283, _T_1284) @[el2_lib.scala 543:23] + _T_1159[20] <= _T_1285 @[el2_lib.scala 543:17] + node _T_1286 = bits(_T_1158, 21, 0) @[el2_lib.scala 543:27] + node _T_1287 = orr(_T_1286) @[el2_lib.scala 543:35] + node _T_1288 = bits(_T_1158, 22, 22) @[el2_lib.scala 543:44] + node _T_1289 = not(_T_1288) @[el2_lib.scala 543:40] + node _T_1290 = bits(_T_1158, 22, 22) @[el2_lib.scala 543:51] + node _T_1291 = mux(_T_1287, _T_1289, _T_1290) @[el2_lib.scala 543:23] + _T_1159[21] <= _T_1291 @[el2_lib.scala 543:17] + node _T_1292 = bits(_T_1158, 22, 0) @[el2_lib.scala 543:27] + node _T_1293 = orr(_T_1292) @[el2_lib.scala 543:35] + node _T_1294 = bits(_T_1158, 23, 23) @[el2_lib.scala 543:44] + node _T_1295 = not(_T_1294) @[el2_lib.scala 543:40] + node _T_1296 = bits(_T_1158, 23, 23) @[el2_lib.scala 543:51] + node _T_1297 = mux(_T_1293, _T_1295, _T_1296) @[el2_lib.scala 543:23] + _T_1159[22] <= _T_1297 @[el2_lib.scala 543:17] + node _T_1298 = bits(_T_1158, 23, 0) @[el2_lib.scala 543:27] + node _T_1299 = orr(_T_1298) @[el2_lib.scala 543:35] + node _T_1300 = bits(_T_1158, 24, 24) @[el2_lib.scala 543:44] + node _T_1301 = not(_T_1300) @[el2_lib.scala 543:40] + node _T_1302 = bits(_T_1158, 24, 24) @[el2_lib.scala 543:51] + node _T_1303 = mux(_T_1299, _T_1301, _T_1302) @[el2_lib.scala 543:23] + _T_1159[23] <= _T_1303 @[el2_lib.scala 543:17] + node _T_1304 = bits(_T_1158, 24, 0) @[el2_lib.scala 543:27] + node _T_1305 = orr(_T_1304) @[el2_lib.scala 543:35] + node _T_1306 = bits(_T_1158, 25, 25) @[el2_lib.scala 543:44] + node _T_1307 = not(_T_1306) @[el2_lib.scala 543:40] + node _T_1308 = bits(_T_1158, 25, 25) @[el2_lib.scala 543:51] + node _T_1309 = mux(_T_1305, _T_1307, _T_1308) @[el2_lib.scala 543:23] + _T_1159[24] <= _T_1309 @[el2_lib.scala 543:17] + node _T_1310 = bits(_T_1158, 25, 0) @[el2_lib.scala 543:27] + node _T_1311 = orr(_T_1310) @[el2_lib.scala 543:35] + node _T_1312 = bits(_T_1158, 26, 26) @[el2_lib.scala 543:44] + node _T_1313 = not(_T_1312) @[el2_lib.scala 543:40] + node _T_1314 = bits(_T_1158, 26, 26) @[el2_lib.scala 543:51] + node _T_1315 = mux(_T_1311, _T_1313, _T_1314) @[el2_lib.scala 543:23] + _T_1159[25] <= _T_1315 @[el2_lib.scala 543:17] + node _T_1316 = bits(_T_1158, 26, 0) @[el2_lib.scala 543:27] + node _T_1317 = orr(_T_1316) @[el2_lib.scala 543:35] + node _T_1318 = bits(_T_1158, 27, 27) @[el2_lib.scala 543:44] + node _T_1319 = not(_T_1318) @[el2_lib.scala 543:40] + node _T_1320 = bits(_T_1158, 27, 27) @[el2_lib.scala 543:51] + node _T_1321 = mux(_T_1317, _T_1319, _T_1320) @[el2_lib.scala 543:23] + _T_1159[26] <= _T_1321 @[el2_lib.scala 543:17] + node _T_1322 = bits(_T_1158, 27, 0) @[el2_lib.scala 543:27] + node _T_1323 = orr(_T_1322) @[el2_lib.scala 543:35] + node _T_1324 = bits(_T_1158, 28, 28) @[el2_lib.scala 543:44] + node _T_1325 = not(_T_1324) @[el2_lib.scala 543:40] + node _T_1326 = bits(_T_1158, 28, 28) @[el2_lib.scala 543:51] + node _T_1327 = mux(_T_1323, _T_1325, _T_1326) @[el2_lib.scala 543:23] + _T_1159[27] <= _T_1327 @[el2_lib.scala 543:17] + node _T_1328 = bits(_T_1158, 28, 0) @[el2_lib.scala 543:27] + node _T_1329 = orr(_T_1328) @[el2_lib.scala 543:35] + node _T_1330 = bits(_T_1158, 29, 29) @[el2_lib.scala 543:44] + node _T_1331 = not(_T_1330) @[el2_lib.scala 543:40] + node _T_1332 = bits(_T_1158, 29, 29) @[el2_lib.scala 543:51] + node _T_1333 = mux(_T_1329, _T_1331, _T_1332) @[el2_lib.scala 543:23] + _T_1159[28] <= _T_1333 @[el2_lib.scala 543:17] + node _T_1334 = bits(_T_1158, 29, 0) @[el2_lib.scala 543:27] + node _T_1335 = orr(_T_1334) @[el2_lib.scala 543:35] + node _T_1336 = bits(_T_1158, 30, 30) @[el2_lib.scala 543:44] + node _T_1337 = not(_T_1336) @[el2_lib.scala 543:40] + node _T_1338 = bits(_T_1158, 30, 30) @[el2_lib.scala 543:51] + node _T_1339 = mux(_T_1335, _T_1337, _T_1338) @[el2_lib.scala 543:23] + _T_1159[29] <= _T_1339 @[el2_lib.scala 543:17] + node _T_1340 = bits(_T_1158, 30, 0) @[el2_lib.scala 543:27] + node _T_1341 = orr(_T_1340) @[el2_lib.scala 543:35] + node _T_1342 = bits(_T_1158, 31, 31) @[el2_lib.scala 543:44] + node _T_1343 = not(_T_1342) @[el2_lib.scala 543:40] + node _T_1344 = bits(_T_1158, 31, 31) @[el2_lib.scala 543:51] + node _T_1345 = mux(_T_1341, _T_1343, _T_1344) @[el2_lib.scala 543:23] + _T_1159[30] <= _T_1345 @[el2_lib.scala 543:17] + node _T_1346 = cat(_T_1159[2], _T_1159[1]) @[el2_lib.scala 545:14] + node _T_1347 = cat(_T_1346, _T_1159[0]) @[el2_lib.scala 545:14] + node _T_1348 = cat(_T_1159[4], _T_1159[3]) @[el2_lib.scala 545:14] + node _T_1349 = cat(_T_1159[6], _T_1159[5]) @[el2_lib.scala 545:14] + node _T_1350 = cat(_T_1349, _T_1348) @[el2_lib.scala 545:14] + node _T_1351 = cat(_T_1350, _T_1347) @[el2_lib.scala 545:14] + node _T_1352 = cat(_T_1159[8], _T_1159[7]) @[el2_lib.scala 545:14] + node _T_1353 = cat(_T_1159[10], _T_1159[9]) @[el2_lib.scala 545:14] + node _T_1354 = cat(_T_1353, _T_1352) @[el2_lib.scala 545:14] + node _T_1355 = cat(_T_1159[12], _T_1159[11]) @[el2_lib.scala 545:14] + node _T_1356 = cat(_T_1159[14], _T_1159[13]) @[el2_lib.scala 545:14] + node _T_1357 = cat(_T_1356, _T_1355) @[el2_lib.scala 545:14] + node _T_1358 = cat(_T_1357, _T_1354) @[el2_lib.scala 545:14] + node _T_1359 = cat(_T_1358, _T_1351) @[el2_lib.scala 545:14] + node _T_1360 = cat(_T_1159[16], _T_1159[15]) @[el2_lib.scala 545:14] + node _T_1361 = cat(_T_1159[18], _T_1159[17]) @[el2_lib.scala 545:14] + node _T_1362 = cat(_T_1361, _T_1360) @[el2_lib.scala 545:14] + node _T_1363 = cat(_T_1159[20], _T_1159[19]) @[el2_lib.scala 545:14] + node _T_1364 = cat(_T_1159[22], _T_1159[21]) @[el2_lib.scala 545:14] + node _T_1365 = cat(_T_1364, _T_1363) @[el2_lib.scala 545:14] + node _T_1366 = cat(_T_1365, _T_1362) @[el2_lib.scala 545:14] + node _T_1367 = cat(_T_1159[24], _T_1159[23]) @[el2_lib.scala 545:14] + node _T_1368 = cat(_T_1159[26], _T_1159[25]) @[el2_lib.scala 545:14] + node _T_1369 = cat(_T_1368, _T_1367) @[el2_lib.scala 545:14] + node _T_1370 = cat(_T_1159[28], _T_1159[27]) @[el2_lib.scala 545:14] + node _T_1371 = cat(_T_1159[30], _T_1159[29]) @[el2_lib.scala 545:14] + node _T_1372 = cat(_T_1371, _T_1370) @[el2_lib.scala 545:14] + node _T_1373 = cat(_T_1372, _T_1369) @[el2_lib.scala 545:14] + node _T_1374 = cat(_T_1373, _T_1366) @[el2_lib.scala 545:14] + node _T_1375 = cat(_T_1374, _T_1359) @[el2_lib.scala 545:14] + node _T_1376 = bits(_T_1158, 0, 0) @[el2_lib.scala 545:24] + node _T_1377 = cat(_T_1375, _T_1376) @[Cat.scala 29:58] + node _T_1378 = bits(a_ff, 31, 0) @[el2_exu_div_ctl.scala 193:87] + node a_ff_eff = mux(_T_1157, _T_1377, _T_1378) @[el2_exu_div_ctl.scala 193:21] + node _T_1379 = bits(smallnum_case_ff, 0, 0) @[el2_exu_div_ctl.scala 196:22] + node _T_1380 = cat(UInt<28>("h00"), smallnum_ff) @[Cat.scala 29:58] + node _T_1381 = bits(rem_ff, 0, 0) @[el2_exu_div_ctl.scala 197:12] + node _T_1382 = eq(smallnum_case_ff, UInt<1>("h00")) @[el2_exu_div_ctl.scala 198:6] + node _T_1383 = eq(rem_ff, UInt<1>("h00")) @[el2_exu_div_ctl.scala 198:26] + node _T_1384 = and(_T_1382, _T_1383) @[el2_exu_div_ctl.scala 198:24] + node _T_1385 = bits(_T_1384, 0, 0) @[el2_exu_div_ctl.scala 198:35] + node _T_1386 = mux(_T_1379, _T_1380, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1387 = mux(_T_1381, a_ff_eff, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1388 = mux(_T_1385, q_ff_eff, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1389 = or(_T_1386, _T_1387) @[Mux.scala 27:72] + node _T_1390 = or(_T_1389, _T_1388) @[Mux.scala 27:72] + wire _T_1391 : UInt<32> @[Mux.scala 27:72] + _T_1391 <= _T_1390 @[Mux.scala 27:72] + io.out <= _T_1391 @[el2_exu_div_ctl.scala 195:10] + node _T_1392 = bits(div_clken, 0, 0) @[el2_exu_div_ctl.scala 201:46] + inst rvclkhdr of rvclkhdr_23 @[el2_lib.scala 483:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr.io.en <= _T_1392 @[el2_lib.scala 485:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_1393 = eq(io.cancel, UInt<1>("h00")) @[el2_exu_div_ctl.scala 204:41] + node _T_1394 = and(io.dp.valid, _T_1393) @[el2_exu_div_ctl.scala 204:39] + reg _T_1395 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 204:26] + _T_1395 <= _T_1394 @[el2_exu_div_ctl.scala 204:26] + valid_ff_x <= _T_1395 @[el2_exu_div_ctl.scala 204:16] + node _T_1396 = eq(io.cancel, UInt<1>("h00")) @[el2_exu_div_ctl.scala 205:35] + node _T_1397 = and(finish, _T_1396) @[el2_exu_div_ctl.scala 205:33] + reg _T_1398 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 205:25] + _T_1398 <= _T_1397 @[el2_exu_div_ctl.scala 205:25] + finish_ff <= _T_1398 @[el2_exu_div_ctl.scala 205:15] + reg _T_1399 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 206:25] + _T_1399 <= run_in @[el2_exu_div_ctl.scala 206:25] + run_state <= _T_1399 @[el2_exu_div_ctl.scala 206:15] + reg _T_1400 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 207:21] + _T_1400 <= count_in @[el2_exu_div_ctl.scala 207:21] + count <= _T_1400 @[el2_exu_div_ctl.scala 207:11] + node _T_1401 = bits(io.dividend, 31, 31) @[el2_exu_div_ctl.scala 208:45] + node _T_1402 = bits(io.dp.valid, 0, 0) @[el2_exu_div_ctl.scala 208:68] + reg _T_1403 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1402 : @[Reg.scala 28:19] + _T_1403 <= _T_1401 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dividend_neg_ff <= _T_1403 @[el2_exu_div_ctl.scala 208:21] + node _T_1404 = bits(io.divisor, 31, 31) @[el2_exu_div_ctl.scala 209:43] + node _T_1405 = bits(io.dp.valid, 0, 0) @[el2_exu_div_ctl.scala 209:66] + reg _T_1406 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1405 : @[Reg.scala 28:19] + _T_1406 <= _T_1404 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + divisor_neg_ff <= _T_1406 @[el2_exu_div_ctl.scala 209:20] + node _T_1407 = bits(io.dp.valid, 0, 0) @[el2_exu_div_ctl.scala 210:53] + reg _T_1408 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1407 : @[Reg.scala 28:19] + _T_1408 <= sign_eff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + sign_ff <= _T_1408 @[el2_exu_div_ctl.scala 210:13] + node _T_1409 = bits(io.dp.valid, 0, 0) @[el2_exu_div_ctl.scala 211:53] + reg _T_1410 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1409 : @[Reg.scala 28:19] + _T_1410 <= io.dp.rem @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + rem_ff <= _T_1410 @[el2_exu_div_ctl.scala 211:12] + reg _T_1411 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 212:32] + _T_1411 <= smallnum_case @[el2_exu_div_ctl.scala 212:32] + smallnum_case_ff <= _T_1411 @[el2_exu_div_ctl.scala 212:22] + reg _T_1412 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 213:27] + _T_1412 <= smallnum @[el2_exu_div_ctl.scala 213:27] + smallnum_ff <= _T_1412 @[el2_exu_div_ctl.scala 213:17] + reg _T_1413 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 214:32] + _T_1413 <= shortq_enable @[el2_exu_div_ctl.scala 214:32] + shortq_enable_ff <= _T_1413 @[el2_exu_div_ctl.scala 214:22] + reg _T_1414 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 215:31] + _T_1414 <= shortq_shift @[el2_exu_div_ctl.scala 215:31] + shortq_shift_xx <= _T_1414 @[el2_exu_div_ctl.scala 215:21] + node _T_1415 = bits(qff_enable, 0, 0) @[el2_exu_div_ctl.scala 217:35] + inst rvclkhdr_1 of rvclkhdr_24 @[el2_lib.scala 508:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= _T_1415 @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1416 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1416 <= q_in @[el2_lib.scala 514:16] + q_ff <= _T_1416 @[el2_exu_div_ctl.scala 217:8] + node _T_1417 = bits(aff_enable, 0, 0) @[el2_exu_div_ctl.scala 218:35] + inst rvclkhdr_2 of rvclkhdr_25 @[el2_lib.scala 508:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_2.io.en <= _T_1417 @[el2_lib.scala 511:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1418 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1418 <= a_in @[el2_lib.scala 514:16] + a_ff <= _T_1418 @[el2_exu_div_ctl.scala 218:8] + node _T_1419 = eq(io.dp.unsign, UInt<1>("h00")) @[el2_exu_div_ctl.scala 219:22] + node _T_1420 = bits(io.divisor, 31, 31) @[el2_exu_div_ctl.scala 219:48] + node _T_1421 = and(_T_1419, _T_1420) @[el2_exu_div_ctl.scala 219:36] + node _T_1422 = cat(_T_1421, io.divisor) @[Cat.scala 29:58] + node _T_1423 = bits(io.dp.valid, 0, 0) @[el2_exu_div_ctl.scala 219:79] + inst rvclkhdr_3 of rvclkhdr_26 @[el2_lib.scala 508:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_3.io.en <= _T_1423 @[el2_lib.scala 511:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1424 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1424 <= _T_1422 @[el2_lib.scala 514:16] + m_ff <= _T_1424 @[el2_exu_div_ctl.scala 219:8] + + module el2_exu : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip dbg_cmd_wrdata : UInt<32>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_debug_wdata_rs1_d : UInt<1>, flip dec_i0_predict_p_d : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_br_immed_d : UInt<12>, flip dec_i0_alu_decode_d : UInt<1>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_pc_d : UInt<31>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip dec_csr_ren_d : UInt<1>, flip mul_p : {valid : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}, flip div_p : {valid : UInt<1>, unsign : UInt<1>, rem : UInt<1>}, flip dec_div_cancel : UInt<1>, flip pred_correct_npc_x : UInt<31>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, flip dec_extint_stall : UInt<1>, flip dec_tlu_meihap : UInt<30>, exu_lsu_rs1_d : UInt<32>, exu_lsu_rs2_d : UInt<32>, exu_flush_final : UInt<1>, exu_flush_path_final : UInt<31>, exu_i0_result_x : UInt<32>, exu_i0_pc_x : UInt<31>, exu_csr_rs1_x : UInt<32>, exu_npc_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_i0_br_fghr_r : UInt<8>, exu_i0_br_way_r : UInt<1>, exu_mp_pkt : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, exu_mp_eghr : UInt<8>, exu_mp_fghr : UInt<8>, exu_mp_index : UInt<8>, exu_mp_btag : UInt<5>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_div_result : UInt<32>, exu_div_wren : UInt<1>} + + wire ghr_x_ns : UInt<8> @[el2_exu.scala 11:47] + wire ghr_d_ns : UInt<8> @[el2_exu.scala 12:47] + wire ghr_d : UInt<8> @[el2_exu.scala 13:55] + wire i0_taken_d : UInt<1> @[el2_exu.scala 14:54] + wire mul_valid_x : UInt<1> @[el2_exu.scala 15:54] + wire i0_valid_d : UInt<1> @[el2_exu.scala 16:54] + wire flush_lower_ff : UInt<1> @[el2_exu.scala 17:46] + wire data_gate_en : UInt<1> @[el2_exu.scala 18:46] + wire csr_rs1_in_d : UInt<32> @[el2_exu.scala 19:46] + wire i0_predict_newp_d : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>} @[el2_exu.scala 20:46] + wire i0_flush_path_d : UInt<32> @[el2_exu.scala 21:46] + wire i0_predict_p_d : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>} @[el2_exu.scala 22:46] + wire i0_pp_r : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>} @[el2_exu.scala 23:54] + wire i0_predict_p_x : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>} @[el2_exu.scala 24:46] + wire final_predict_mp : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>} @[el2_exu.scala 25:38] + wire pred_correct_npc_r : UInt<32> @[el2_exu.scala 26:46] + wire i0_pred_correct_upper_d : UInt<1> @[el2_exu.scala 27:38] + wire i0_flush_upper_d : UInt<1> @[el2_exu.scala 28:38] + io.exu_mp_pkt.prett <= UInt<1>("h00") @[el2_exu.scala 29:41] + io.exu_mp_pkt.br_start_error <= UInt<1>("h00") @[el2_exu.scala 30:31] + io.exu_mp_pkt.br_error <= UInt<1>("h00") @[el2_exu.scala 31:41] + io.exu_mp_pkt.valid <= UInt<1>("h00") @[el2_exu.scala 32:41] + node x_data_en = bits(io.dec_data_en, 1, 1) @[el2_exu.scala 33:49] + node r_data_en = bits(io.dec_data_en, 0, 0) @[el2_exu.scala 34:49] + node x_ctl_en = bits(io.dec_ctl_en, 1, 1) @[el2_exu.scala 35:48] + node r_ctl_en = bits(io.dec_ctl_en, 0, 0) @[el2_exu.scala 36:48] + node _T = cat(io.i0_predict_fghr_d, io.i0_predict_index_d) @[Cat.scala 29:58] + node predpipe_d = cat(_T, io.i0_predict_btag_d) @[Cat.scala 29:58] + node _T_1 = bits(x_data_en, 0, 0) @[el2_exu.scala 40:67] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= _T_1 @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_flush_path_x : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_flush_path_x <= i0_flush_path_d @[el2_lib.scala 514:16] + node _T_2 = bits(x_data_en, 0, 0) @[el2_exu.scala 41:73] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= _T_2 @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_3 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_3 <= csr_rs1_in_d @[el2_lib.scala 514:16] + io.exu_csr_rs1_x <= _T_3 @[el2_exu.scala 41:41] + node _T_4 = bits(x_data_en, 0, 0) @[el2_exu.scala 42:83] + inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 518:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 520:18] + rvclkhdr_2.io.en <= _T_4 @[el2_lib.scala 521:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] + wire _T_5 : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>} @[el2_lib.scala 524:33] + _T_5.way <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.pja <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.pret <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.pcall <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.prett <= UInt<31>("h00") @[el2_lib.scala 524:33] + _T_5.br_start_error <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.br_error <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.toffset <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_5.hist <= UInt<2>("h00") @[el2_lib.scala 524:33] + _T_5.pc4 <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.boffset <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.ataken <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.misp <= UInt<1>("h00") @[el2_lib.scala 524:33] + reg _T_6 : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, rvclkhdr_2.io.l1clk with : (reset => (reset, _T_5)) @[el2_lib.scala 524:16] + _T_6.way <= i0_predict_p_d.way @[el2_lib.scala 524:16] + _T_6.pja <= i0_predict_p_d.pja @[el2_lib.scala 524:16] + _T_6.pret <= i0_predict_p_d.pret @[el2_lib.scala 524:16] + _T_6.pcall <= i0_predict_p_d.pcall @[el2_lib.scala 524:16] + _T_6.prett <= i0_predict_p_d.prett @[el2_lib.scala 524:16] + _T_6.br_start_error <= i0_predict_p_d.br_start_error @[el2_lib.scala 524:16] + _T_6.br_error <= i0_predict_p_d.br_error @[el2_lib.scala 524:16] + _T_6.valid <= i0_predict_p_d.valid @[el2_lib.scala 524:16] + _T_6.toffset <= i0_predict_p_d.toffset @[el2_lib.scala 524:16] + _T_6.hist <= i0_predict_p_d.hist @[el2_lib.scala 524:16] + _T_6.pc4 <= i0_predict_p_d.pc4 @[el2_lib.scala 524:16] + _T_6.boffset <= i0_predict_p_d.boffset @[el2_lib.scala 524:16] + _T_6.ataken <= i0_predict_p_d.ataken @[el2_lib.scala 524:16] + _T_6.misp <= i0_predict_p_d.misp @[el2_lib.scala 524:16] + i0_predict_p_x.way <= _T_6.way @[el2_exu.scala 42:49] + i0_predict_p_x.pja <= _T_6.pja @[el2_exu.scala 42:49] + i0_predict_p_x.pret <= _T_6.pret @[el2_exu.scala 42:49] + i0_predict_p_x.pcall <= _T_6.pcall @[el2_exu.scala 42:49] + i0_predict_p_x.prett <= _T_6.prett @[el2_exu.scala 42:49] + i0_predict_p_x.br_start_error <= _T_6.br_start_error @[el2_exu.scala 42:49] + i0_predict_p_x.br_error <= _T_6.br_error @[el2_exu.scala 42:49] + i0_predict_p_x.valid <= _T_6.valid @[el2_exu.scala 42:49] + i0_predict_p_x.toffset <= _T_6.toffset @[el2_exu.scala 42:49] + i0_predict_p_x.hist <= _T_6.hist @[el2_exu.scala 42:49] + i0_predict_p_x.pc4 <= _T_6.pc4 @[el2_exu.scala 42:49] + i0_predict_p_x.boffset <= _T_6.boffset @[el2_exu.scala 42:49] + i0_predict_p_x.ataken <= _T_6.ataken @[el2_exu.scala 42:49] + i0_predict_p_x.misp <= _T_6.misp @[el2_exu.scala 42:49] + node _T_7 = bits(x_data_en, 0, 0) @[el2_exu.scala 43:70] + inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_3.io.en <= _T_7 @[el2_lib.scala 511:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg predpipe_x : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + predpipe_x <= predpipe_d @[el2_lib.scala 514:16] + node _T_8 = bits(r_data_en, 0, 0) @[el2_exu.scala 44:79] + inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_4.io.en <= _T_8 @[el2_lib.scala 511:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg predpipe_r : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + predpipe_r <= predpipe_x @[el2_lib.scala 514:16] + node _T_9 = bits(x_ctl_en, 0, 0) @[el2_exu.scala 45:76] + inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_5.io.en <= _T_9 @[el2_lib.scala 511:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg ghr_x : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + ghr_x <= ghr_x_ns @[el2_lib.scala 514:16] + node _T_10 = bits(x_ctl_en, 0, 0) @[el2_exu.scala 46:75] + inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 508:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_6.io.en <= _T_10 @[el2_lib.scala 511:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_pred_correct_upper_x : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_pred_correct_upper_x <= i0_pred_correct_upper_d @[el2_lib.scala 514:16] + node _T_11 = bits(x_ctl_en, 0, 0) @[el2_exu.scala 47:68] + inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 508:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_7.io.en <= _T_11 @[el2_lib.scala 511:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_flush_upper_x : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_flush_upper_x <= i0_flush_upper_d @[el2_lib.scala 514:16] + node _T_12 = bits(x_ctl_en, 0, 0) @[el2_exu.scala 48:78] + inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 508:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_8.io.en <= _T_12 @[el2_lib.scala 511:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_taken_x : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_taken_x <= i0_taken_d @[el2_lib.scala 514:16] + node _T_13 = bits(x_ctl_en, 0, 0) @[el2_exu.scala 49:78] + inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 508:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_9.io.en <= _T_13 @[el2_lib.scala 511:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_valid_x : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_valid_x <= i0_valid_d @[el2_lib.scala 514:16] + node _T_14 = bits(r_ctl_en, 0, 0) @[el2_exu.scala 50:64] + inst rvclkhdr_10 of rvclkhdr_10 @[el2_lib.scala 518:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 520:18] + rvclkhdr_10.io.en <= _T_14 @[el2_lib.scala 521:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] + wire _T_15 : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>} @[el2_lib.scala 524:33] + _T_15.way <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.pja <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.pret <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.pcall <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.prett <= UInt<31>("h00") @[el2_lib.scala 524:33] + _T_15.br_start_error <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.br_error <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.toffset <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_15.hist <= UInt<2>("h00") @[el2_lib.scala 524:33] + _T_15.pc4 <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.boffset <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.ataken <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.misp <= UInt<1>("h00") @[el2_lib.scala 524:33] + reg _T_16 : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, rvclkhdr_10.io.l1clk with : (reset => (reset, _T_15)) @[el2_lib.scala 524:16] + _T_16.way <= i0_predict_p_x.way @[el2_lib.scala 524:16] + _T_16.pja <= i0_predict_p_x.pja @[el2_lib.scala 524:16] + _T_16.pret <= i0_predict_p_x.pret @[el2_lib.scala 524:16] + _T_16.pcall <= i0_predict_p_x.pcall @[el2_lib.scala 524:16] + _T_16.prett <= i0_predict_p_x.prett @[el2_lib.scala 524:16] + _T_16.br_start_error <= i0_predict_p_x.br_start_error @[el2_lib.scala 524:16] + _T_16.br_error <= i0_predict_p_x.br_error @[el2_lib.scala 524:16] + _T_16.valid <= i0_predict_p_x.valid @[el2_lib.scala 524:16] + _T_16.toffset <= i0_predict_p_x.toffset @[el2_lib.scala 524:16] + _T_16.hist <= i0_predict_p_x.hist @[el2_lib.scala 524:16] + _T_16.pc4 <= i0_predict_p_x.pc4 @[el2_lib.scala 524:16] + _T_16.boffset <= i0_predict_p_x.boffset @[el2_lib.scala 524:16] + _T_16.ataken <= i0_predict_p_x.ataken @[el2_lib.scala 524:16] + _T_16.misp <= i0_predict_p_x.misp @[el2_lib.scala 524:16] + i0_pp_r.way <= _T_16.way @[el2_exu.scala 50:31] + i0_pp_r.pja <= _T_16.pja @[el2_exu.scala 50:31] + i0_pp_r.pret <= _T_16.pret @[el2_exu.scala 50:31] + i0_pp_r.pcall <= _T_16.pcall @[el2_exu.scala 50:31] + i0_pp_r.prett <= _T_16.prett @[el2_exu.scala 50:31] + i0_pp_r.br_start_error <= _T_16.br_start_error @[el2_exu.scala 50:31] + i0_pp_r.br_error <= _T_16.br_error @[el2_exu.scala 50:31] + i0_pp_r.valid <= _T_16.valid @[el2_exu.scala 50:31] + i0_pp_r.toffset <= _T_16.toffset @[el2_exu.scala 50:31] + i0_pp_r.hist <= _T_16.hist @[el2_exu.scala 50:31] + i0_pp_r.pc4 <= _T_16.pc4 @[el2_exu.scala 50:31] + i0_pp_r.boffset <= _T_16.boffset @[el2_exu.scala 50:31] + i0_pp_r.ataken <= _T_16.ataken @[el2_exu.scala 50:31] + i0_pp_r.misp <= _T_16.misp @[el2_exu.scala 50:31] + node _T_17 = bits(io.pred_correct_npc_x, 5, 0) @[el2_exu.scala 51:70] + node _T_18 = bits(r_ctl_en, 0, 0) @[el2_exu.scala 51:86] + inst rvclkhdr_11 of rvclkhdr_11 @[el2_lib.scala 508:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_11.io.en <= _T_18 @[el2_lib.scala 511:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg pred_temp1 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + pred_temp1 <= _T_17 @[el2_lib.scala 514:16] + node _T_19 = bits(r_ctl_en, 0, 0) @[el2_exu.scala 52:75] + inst rvclkhdr_12 of rvclkhdr_12 @[el2_lib.scala 508:23] + rvclkhdr_12.clock <= clock + rvclkhdr_12.reset <= reset + rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_12.io.en <= _T_19 @[el2_lib.scala 511:17] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_pred_correct_upper_r : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_pred_correct_upper_r <= i0_pred_correct_upper_x @[el2_lib.scala 514:16] + node _T_20 = bits(r_data_en, 0, 0) @[el2_exu.scala 53:68] + inst rvclkhdr_13 of rvclkhdr_13 @[el2_lib.scala 508:23] + rvclkhdr_13.clock <= clock + rvclkhdr_13.reset <= reset + rvclkhdr_13.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_13.io.en <= _T_20 @[el2_lib.scala 511:17] + rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_flush_path_upper_r : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_flush_path_upper_r <= i0_flush_path_x @[el2_lib.scala 514:16] + node _T_21 = bits(io.pred_correct_npc_x, 30, 6) @[el2_exu.scala 54:78] + node _T_22 = bits(r_data_en, 0, 0) @[el2_exu.scala 54:96] + inst rvclkhdr_14 of rvclkhdr_14 @[el2_lib.scala 508:23] + rvclkhdr_14.clock <= clock + rvclkhdr_14.reset <= reset + rvclkhdr_14.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_14.io.en <= _T_22 @[el2_lib.scala 511:17] + rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg pred_temp2 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + pred_temp2 <= _T_21 @[el2_lib.scala 514:16] + node _T_23 = cat(pred_temp2, pred_temp1) @[Cat.scala 29:58] + pred_correct_npc_r <= _T_23 @[el2_exu.scala 55:41] + node _T_24 = eq(UInt<10>("h0200"), UInt<6>("h020")) @[el2_exu.scala 57:24] + node _T_25 = eq(UInt<10>("h0200"), UInt<7>("h040")) @[el2_exu.scala 57:50] + node _T_26 = or(_T_24, _T_25) @[el2_exu.scala 57:32] + when _T_26 : @[el2_exu.scala 57:58] + node _T_27 = bits(data_gate_en, 0, 0) @[el2_exu.scala 58:71] + reg _T_28 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_27 : @[Reg.scala 28:19] + _T_28 <= ghr_d_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ghr_d <= _T_28 @[el2_exu.scala 58:33] + node _T_29 = bits(data_gate_en, 0, 0) @[el2_exu.scala 59:69] + reg _T_30 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_29 : @[Reg.scala 28:19] + _T_30 <= io.mul_p.valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mul_valid_x <= _T_30 @[el2_exu.scala 59:25] + node _T_31 = bits(data_gate_en, 0, 0) @[el2_exu.scala 60:79] + reg _T_32 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_31 : @[Reg.scala 28:19] + _T_32 <= io.dec_tlu_flush_lower_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + flush_lower_ff <= _T_32 @[el2_exu.scala 60:25] + skip @[el2_exu.scala 57:58] + else : @[el2_exu.scala 61:14] + node _T_33 = bits(data_gate_en, 0, 0) @[el2_exu.scala 62:65] + inst rvclkhdr_15 of rvclkhdr_15 @[el2_lib.scala 508:23] + rvclkhdr_15.clock <= clock + rvclkhdr_15.reset <= reset + rvclkhdr_15.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_15.io.en <= _T_33 @[el2_lib.scala 511:17] + rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_34 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_34 <= ghr_d_ns @[el2_lib.scala 514:16] + ghr_d <= _T_34 @[el2_exu.scala 62:33] + node _T_35 = bits(data_gate_en, 0, 0) @[el2_exu.scala 63:63] + inst rvclkhdr_16 of rvclkhdr_16 @[el2_lib.scala 508:23] + rvclkhdr_16.clock <= clock + rvclkhdr_16.reset <= reset + rvclkhdr_16.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_16.io.en <= _T_35 @[el2_lib.scala 511:17] + rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_36 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_36 <= io.mul_p.valid @[el2_lib.scala 514:16] + mul_valid_x <= _T_36 @[el2_exu.scala 63:25] + node _T_37 = bits(data_gate_en, 0, 0) @[el2_exu.scala 64:73] + inst rvclkhdr_17 of rvclkhdr_17 @[el2_lib.scala 508:23] + rvclkhdr_17.clock <= clock + rvclkhdr_17.reset <= reset + rvclkhdr_17.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_17.io.en <= _T_37 @[el2_lib.scala 511:17] + rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_38 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_38 <= io.dec_tlu_flush_lower_r @[el2_lib.scala 514:16] + flush_lower_ff <= _T_38 @[el2_exu.scala 64:25] + skip @[el2_exu.scala 61:14] + node _T_39 = neq(ghr_d_ns, ghr_d) @[el2_exu.scala 68:39] + node _T_40 = neq(io.mul_p.valid, mul_valid_x) @[el2_exu.scala 68:70] + node _T_41 = or(_T_39, _T_40) @[el2_exu.scala 68:50] + node _T_42 = neq(io.dec_tlu_flush_lower_r, flush_lower_ff) @[el2_exu.scala 68:116] + node _T_43 = or(_T_41, _T_42) @[el2_exu.scala 68:87] + data_gate_en <= _T_43 @[el2_exu.scala 68:25] + node _T_44 = bits(io.dec_i0_rs1_bypass_en_d, 0, 0) @[el2_exu.scala 69:61] + node _T_45 = bits(io.dec_i0_rs1_bypass_en_d, 1, 1) @[el2_exu.scala 69:92] + node i0_rs1_bypass_en_d = or(_T_44, _T_45) @[el2_exu.scala 69:65] + node _T_46 = bits(io.dec_i0_rs2_bypass_en_d, 0, 0) @[el2_exu.scala 70:61] + node _T_47 = bits(io.dec_i0_rs2_bypass_en_d, 1, 1) @[el2_exu.scala 70:92] + node i0_rs2_bypass_en_d = or(_T_46, _T_47) @[el2_exu.scala 70:65] + node _T_48 = bits(io.dec_i0_rs1_bypass_en_d, 0, 0) @[el2_exu.scala 73:30] + node _T_49 = bits(_T_48, 0, 0) @[el2_exu.scala 73:34] + node _T_50 = bits(io.dec_i0_rs1_bypass_en_d, 1, 1) @[el2_exu.scala 74:30] + node _T_51 = bits(_T_50, 0, 0) @[el2_exu.scala 74:34] + node _T_52 = mux(_T_49, io.dec_i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_53 = mux(_T_51, io.exu_i0_result_x, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_54 = or(_T_52, _T_53) @[Mux.scala 27:72] + wire i0_rs1_bypass_data_d : UInt<32> @[Mux.scala 27:72] + i0_rs1_bypass_data_d <= _T_54 @[Mux.scala 27:72] + node _T_55 = bits(io.dec_i0_rs2_bypass_en_d, 0, 0) @[el2_exu.scala 78:30] + node _T_56 = bits(_T_55, 0, 0) @[el2_exu.scala 78:34] + node _T_57 = bits(io.dec_i0_rs2_bypass_en_d, 1, 1) @[el2_exu.scala 79:30] + node _T_58 = bits(_T_57, 0, 0) @[el2_exu.scala 79:34] + node _T_59 = mux(_T_56, io.dec_i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_60 = mux(_T_58, io.exu_i0_result_x, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_61 = or(_T_59, _T_60) @[Mux.scala 27:72] + wire i0_rs2_bypass_data_d : UInt<32> @[Mux.scala 27:72] + i0_rs2_bypass_data_d <= _T_61 @[Mux.scala 27:72] + node _T_62 = bits(i0_rs1_bypass_en_d, 0, 0) @[el2_exu.scala 83:24] + node _T_63 = not(i0_rs1_bypass_en_d) @[el2_exu.scala 84:6] + node _T_64 = and(_T_63, io.dec_i0_select_pc_d) @[el2_exu.scala 84:26] + node _T_65 = bits(_T_64, 0, 0) @[el2_exu.scala 84:52] + node _T_66 = cat(io.dec_i0_pc_d, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_67 = not(i0_rs1_bypass_en_d) @[el2_exu.scala 85:6] + node _T_68 = and(_T_67, io.dec_debug_wdata_rs1_d) @[el2_exu.scala 85:26] + node _T_69 = bits(_T_68, 0, 0) @[el2_exu.scala 85:55] + node _T_70 = not(i0_rs1_bypass_en_d) @[el2_exu.scala 86:6] + node _T_71 = not(io.dec_debug_wdata_rs1_d) @[el2_exu.scala 86:28] + node _T_72 = and(_T_70, _T_71) @[el2_exu.scala 86:26] + node _T_73 = and(_T_72, io.dec_i0_rs1_en_d) @[el2_exu.scala 86:54] + node _T_74 = bits(_T_73, 0, 0) @[el2_exu.scala 86:76] + node _T_75 = mux(_T_62, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_76 = mux(_T_65, _T_66, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_77 = mux(_T_69, io.dbg_cmd_wrdata, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_78 = mux(_T_74, io.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_79 = or(_T_75, _T_76) @[Mux.scala 27:72] + node _T_80 = or(_T_79, _T_77) @[Mux.scala 27:72] + node _T_81 = or(_T_80, _T_78) @[Mux.scala 27:72] + wire i0_rs1_d : UInt<32> @[Mux.scala 27:72] + i0_rs1_d <= _T_81 @[Mux.scala 27:72] + node _T_82 = not(i0_rs2_bypass_en_d) @[el2_exu.scala 90:6] + node _T_83 = and(_T_82, io.dec_i0_rs2_en_d) @[el2_exu.scala 90:26] + node _T_84 = bits(_T_83, 0, 0) @[el2_exu.scala 90:48] + node _T_85 = not(i0_rs2_bypass_en_d) @[el2_exu.scala 91:6] + node _T_86 = bits(_T_85, 0, 0) @[el2_exu.scala 91:27] + node _T_87 = bits(i0_rs2_bypass_en_d, 0, 0) @[el2_exu.scala 92:26] + node _T_88 = mux(_T_84, io.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_89 = mux(_T_86, io.dec_i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_90 = mux(_T_87, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_91 = or(_T_88, _T_89) @[Mux.scala 27:72] + node _T_92 = or(_T_91, _T_90) @[Mux.scala 27:72] + wire i0_rs2_d : UInt<32> @[Mux.scala 27:72] + i0_rs2_d <= _T_92 @[Mux.scala 27:72] + node _T_93 = not(i0_rs1_bypass_en_d) @[el2_exu.scala 96:6] + node _T_94 = not(io.dec_extint_stall) @[el2_exu.scala 96:28] + node _T_95 = and(_T_93, _T_94) @[el2_exu.scala 96:26] + node _T_96 = and(_T_95, io.dec_i0_rs1_en_d) @[el2_exu.scala 96:49] + node _T_97 = bits(_T_96, 0, 0) @[el2_exu.scala 96:71] + node _T_98 = not(io.dec_extint_stall) @[el2_exu.scala 97:27] + node _T_99 = and(i0_rs1_bypass_en_d, _T_98) @[el2_exu.scala 97:25] + node _T_100 = bits(_T_99, 0, 0) @[el2_exu.scala 97:49] + node _T_101 = bits(io.dec_extint_stall, 0, 0) @[el2_exu.scala 98:27] + node _T_102 = cat(io.dec_tlu_meihap, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_103 = mux(_T_97, io.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_104 = mux(_T_100, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_105 = mux(_T_101, _T_102, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_106 = or(_T_103, _T_104) @[Mux.scala 27:72] + node _T_107 = or(_T_106, _T_105) @[Mux.scala 27:72] + wire _T_108 : UInt<32> @[Mux.scala 27:72] + _T_108 <= _T_107 @[Mux.scala 27:72] + io.exu_lsu_rs1_d <= _T_108 @[el2_exu.scala 95:19] + node _T_109 = not(i0_rs2_bypass_en_d) @[el2_exu.scala 102:6] + node _T_110 = not(io.dec_extint_stall) @[el2_exu.scala 102:28] + node _T_111 = and(_T_109, _T_110) @[el2_exu.scala 102:26] + node _T_112 = and(_T_111, io.dec_i0_rs2_en_d) @[el2_exu.scala 102:49] + node _T_113 = bits(_T_112, 0, 0) @[el2_exu.scala 102:71] + node _T_114 = not(io.dec_extint_stall) @[el2_exu.scala 103:27] + node _T_115 = and(i0_rs2_bypass_en_d, _T_114) @[el2_exu.scala 103:25] + node _T_116 = bits(_T_115, 0, 0) @[el2_exu.scala 103:49] + node _T_117 = mux(_T_113, io.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_118 = mux(_T_116, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_119 = or(_T_117, _T_118) @[Mux.scala 27:72] + wire _T_120 : UInt<32> @[Mux.scala 27:72] + _T_120 <= _T_119 @[Mux.scala 27:72] + io.exu_lsu_rs2_d <= _T_120 @[el2_exu.scala 101:19] + node _T_121 = not(i0_rs1_bypass_en_d) @[el2_exu.scala 107:6] + node _T_122 = and(_T_121, io.dec_i0_rs1_en_d) @[el2_exu.scala 107:26] + node _T_123 = bits(_T_122, 0, 0) @[el2_exu.scala 107:48] + node _T_124 = bits(i0_rs1_bypass_en_d, 0, 0) @[el2_exu.scala 108:26] + node _T_125 = mux(_T_123, io.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_126 = mux(_T_124, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_127 = or(_T_125, _T_126) @[Mux.scala 27:72] + wire muldiv_rs1_d : UInt<32> @[Mux.scala 27:72] + muldiv_rs1_d <= _T_127 @[Mux.scala 27:72] + node _T_128 = not(i0_rs2_bypass_en_d) @[el2_exu.scala 112:6] + node _T_129 = and(_T_128, io.dec_i0_rs2_en_d) @[el2_exu.scala 112:26] + node _T_130 = bits(_T_129, 0, 0) @[el2_exu.scala 112:48] + node _T_131 = not(i0_rs2_bypass_en_d) @[el2_exu.scala 113:6] + node _T_132 = bits(_T_131, 0, 0) @[el2_exu.scala 113:27] + node _T_133 = bits(i0_rs2_bypass_en_d, 0, 0) @[el2_exu.scala 114:26] + node _T_134 = mux(_T_130, io.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_135 = mux(_T_132, io.dec_i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_136 = mux(_T_133, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_137 = or(_T_134, _T_135) @[Mux.scala 27:72] + node _T_138 = or(_T_137, _T_136) @[Mux.scala 27:72] + wire muldiv_rs2_d : UInt<32> @[Mux.scala 27:72] + muldiv_rs2_d <= _T_138 @[Mux.scala 27:72] + node _T_139 = bits(io.dec_csr_ren_d, 0, 0) @[el2_exu.scala 117:47] + node _T_140 = mux(_T_139, i0_rs1_d, io.exu_csr_rs1_x) @[el2_exu.scala 117:28] + csr_rs1_in_d <= _T_140 @[el2_exu.scala 117:22] + inst i_alu of el2_exu_alu_ctl @[el2_exu.scala 120:19] + i_alu.clock <= clock + i_alu.reset <= reset + i_alu.io.scan_mode <= io.scan_mode @[el2_exu.scala 121:33] + i_alu.io.enable <= x_ctl_en @[el2_exu.scala 122:41] + i_alu.io.pp_in.way <= i0_predict_newp_d.way @[el2_exu.scala 123:41] + i_alu.io.pp_in.pja <= i0_predict_newp_d.pja @[el2_exu.scala 123:41] + i_alu.io.pp_in.pret <= i0_predict_newp_d.pret @[el2_exu.scala 123:41] + i_alu.io.pp_in.pcall <= i0_predict_newp_d.pcall @[el2_exu.scala 123:41] + i_alu.io.pp_in.prett <= i0_predict_newp_d.prett @[el2_exu.scala 123:41] + i_alu.io.pp_in.br_start_error <= i0_predict_newp_d.br_start_error @[el2_exu.scala 123:41] + i_alu.io.pp_in.br_error <= i0_predict_newp_d.br_error @[el2_exu.scala 123:41] + i_alu.io.pp_in.valid <= i0_predict_newp_d.valid @[el2_exu.scala 123:41] + i_alu.io.pp_in.toffset <= i0_predict_newp_d.toffset @[el2_exu.scala 123:41] + i_alu.io.pp_in.hist <= i0_predict_newp_d.hist @[el2_exu.scala 123:41] + i_alu.io.pp_in.pc4 <= i0_predict_newp_d.pc4 @[el2_exu.scala 123:41] + i_alu.io.pp_in.boffset <= i0_predict_newp_d.boffset @[el2_exu.scala 123:41] + i_alu.io.pp_in.ataken <= i0_predict_newp_d.ataken @[el2_exu.scala 123:41] + i_alu.io.pp_in.misp <= i0_predict_newp_d.misp @[el2_exu.scala 123:41] + i_alu.io.valid_in <= io.dec_i0_alu_decode_d @[el2_exu.scala 124:33] + i_alu.io.flush_upper_x <= i0_flush_upper_x @[el2_exu.scala 125:33] + i_alu.io.flush_lower_r <= io.dec_tlu_flush_lower_r @[el2_exu.scala 126:33] + node _T_141 = asSInt(i0_rs1_d) @[el2_exu.scala 127:44] + i_alu.io.a_in <= _T_141 @[el2_exu.scala 127:33] + i_alu.io.b_in <= i0_rs2_d @[el2_exu.scala 128:33] + i_alu.io.pc_in <= io.dec_i0_pc_d @[el2_exu.scala 129:41] + i_alu.io.brimm_in <= io.dec_i0_br_immed_d @[el2_exu.scala 130:33] + i_alu.io.ap.csr_imm <= io.i0_ap.csr_imm @[el2_exu.scala 131:41] + i_alu.io.ap.csr_write <= io.i0_ap.csr_write @[el2_exu.scala 131:41] + i_alu.io.ap.predict_nt <= io.i0_ap.predict_nt @[el2_exu.scala 131:41] + i_alu.io.ap.predict_t <= io.i0_ap.predict_t @[el2_exu.scala 131:41] + i_alu.io.ap.jal <= io.i0_ap.jal @[el2_exu.scala 131:41] + i_alu.io.ap.unsign <= io.i0_ap.unsign @[el2_exu.scala 131:41] + i_alu.io.ap.slt <= io.i0_ap.slt @[el2_exu.scala 131:41] + i_alu.io.ap.sub <= io.i0_ap.sub @[el2_exu.scala 131:41] + i_alu.io.ap.add <= io.i0_ap.add @[el2_exu.scala 131:41] + i_alu.io.ap.bge <= io.i0_ap.bge @[el2_exu.scala 131:41] + i_alu.io.ap.blt <= io.i0_ap.blt @[el2_exu.scala 131:41] + i_alu.io.ap.bne <= io.i0_ap.bne @[el2_exu.scala 131:41] + i_alu.io.ap.beq <= io.i0_ap.beq @[el2_exu.scala 131:41] + i_alu.io.ap.sra <= io.i0_ap.sra @[el2_exu.scala 131:41] + i_alu.io.ap.srl <= io.i0_ap.srl @[el2_exu.scala 131:41] + i_alu.io.ap.sll <= io.i0_ap.sll @[el2_exu.scala 131:41] + i_alu.io.ap.lxor <= io.i0_ap.lxor @[el2_exu.scala 131:41] + i_alu.io.ap.lor <= io.i0_ap.lor @[el2_exu.scala 131:41] + i_alu.io.ap.land <= io.i0_ap.land @[el2_exu.scala 131:41] + i_alu.io.csr_ren_in <= io.dec_csr_ren_d @[el2_exu.scala 132:33] + i0_flush_upper_d <= i_alu.io.flush_upper_out @[el2_exu.scala 134:33] + io.exu_flush_final <= i_alu.io.flush_final_out @[el2_exu.scala 135:33] + i0_flush_path_d <= i_alu.io.flush_path_out @[el2_exu.scala 136:41] + i0_predict_p_d.way <= i_alu.io.predict_p_out.way @[el2_exu.scala 137:41] + i0_predict_p_d.pja <= i_alu.io.predict_p_out.pja @[el2_exu.scala 137:41] + i0_predict_p_d.pret <= i_alu.io.predict_p_out.pret @[el2_exu.scala 137:41] + i0_predict_p_d.pcall <= i_alu.io.predict_p_out.pcall @[el2_exu.scala 137:41] + i0_predict_p_d.prett <= i_alu.io.predict_p_out.prett @[el2_exu.scala 137:41] + i0_predict_p_d.br_start_error <= i_alu.io.predict_p_out.br_start_error @[el2_exu.scala 137:41] + i0_predict_p_d.br_error <= i_alu.io.predict_p_out.br_error @[el2_exu.scala 137:41] + i0_predict_p_d.valid <= i_alu.io.predict_p_out.valid @[el2_exu.scala 137:41] + i0_predict_p_d.toffset <= i_alu.io.predict_p_out.toffset @[el2_exu.scala 137:41] + i0_predict_p_d.hist <= i_alu.io.predict_p_out.hist @[el2_exu.scala 137:41] + i0_predict_p_d.pc4 <= i_alu.io.predict_p_out.pc4 @[el2_exu.scala 137:41] + i0_predict_p_d.boffset <= i_alu.io.predict_p_out.boffset @[el2_exu.scala 137:41] + i0_predict_p_d.ataken <= i_alu.io.predict_p_out.ataken @[el2_exu.scala 137:41] + i0_predict_p_d.misp <= i_alu.io.predict_p_out.misp @[el2_exu.scala 137:41] + i0_pred_correct_upper_d <= i_alu.io.pred_correct_out @[el2_exu.scala 138:27] + io.exu_i0_pc_x <= i_alu.io.pc_ff @[el2_exu.scala 139:41] + inst i_mul of el2_exu_mul_ctl @[el2_exu.scala 141:19] + i_mul.clock <= clock + i_mul.reset <= reset + i_mul.io.scan_mode <= io.scan_mode @[el2_exu.scala 142:33] + i_mul.io.mul_p.bfp <= io.mul_p.bfp @[el2_exu.scala 143:41] + i_mul.io.mul_p.crc32c_w <= io.mul_p.crc32c_w @[el2_exu.scala 143:41] + i_mul.io.mul_p.crc32c_h <= io.mul_p.crc32c_h @[el2_exu.scala 143:41] + i_mul.io.mul_p.crc32c_b <= io.mul_p.crc32c_b @[el2_exu.scala 143:41] + i_mul.io.mul_p.crc32_w <= io.mul_p.crc32_w @[el2_exu.scala 143:41] + i_mul.io.mul_p.crc32_h <= io.mul_p.crc32_h @[el2_exu.scala 143:41] + i_mul.io.mul_p.crc32_b <= io.mul_p.crc32_b @[el2_exu.scala 143:41] + i_mul.io.mul_p.unshfl <= io.mul_p.unshfl @[el2_exu.scala 143:41] + i_mul.io.mul_p.shfl <= io.mul_p.shfl @[el2_exu.scala 143:41] + i_mul.io.mul_p.grev <= io.mul_p.grev @[el2_exu.scala 143:41] + i_mul.io.mul_p.clmulr <= io.mul_p.clmulr @[el2_exu.scala 143:41] + i_mul.io.mul_p.clmulh <= io.mul_p.clmulh @[el2_exu.scala 143:41] + i_mul.io.mul_p.clmul <= io.mul_p.clmul @[el2_exu.scala 143:41] + i_mul.io.mul_p.bdep <= io.mul_p.bdep @[el2_exu.scala 143:41] + i_mul.io.mul_p.bext <= io.mul_p.bext @[el2_exu.scala 143:41] + i_mul.io.mul_p.low <= io.mul_p.low @[el2_exu.scala 143:41] + i_mul.io.mul_p.rs2_sign <= io.mul_p.rs2_sign @[el2_exu.scala 143:41] + i_mul.io.mul_p.rs1_sign <= io.mul_p.rs1_sign @[el2_exu.scala 143:41] + i_mul.io.mul_p.valid <= io.mul_p.valid @[el2_exu.scala 143:41] + i_mul.io.rs1_in <= muldiv_rs1_d @[el2_exu.scala 144:41] + i_mul.io.rs2_in <= muldiv_rs2_d @[el2_exu.scala 145:41] + inst i_div of el2_exu_div_ctl @[el2_exu.scala 148:19] + i_div.clock <= clock + i_div.reset <= reset + i_div.io.scan_mode <= io.scan_mode @[el2_exu.scala 149:33] + i_div.io.cancel <= io.dec_div_cancel @[el2_exu.scala 150:41] + i_div.io.dp.rem <= io.div_p.rem @[el2_exu.scala 151:41] + i_div.io.dp.unsign <= io.div_p.unsign @[el2_exu.scala 151:41] + i_div.io.dp.valid <= io.div_p.valid @[el2_exu.scala 151:41] + i_div.io.dividend <= muldiv_rs1_d @[el2_exu.scala 152:33] + i_div.io.divisor <= muldiv_rs2_d @[el2_exu.scala 153:33] + io.exu_div_wren <= i_div.io.finish_dly @[el2_exu.scala 154:41] + io.exu_div_result <= i_div.io.out @[el2_exu.scala 155:33] + node _T_142 = bits(mul_valid_x, 0, 0) @[el2_exu.scala 157:61] + node _T_143 = mux(_T_142, i_mul.io.result_x, i_alu.io.result_ff) @[el2_exu.scala 157:48] + io.exu_i0_result_x <= _T_143 @[el2_exu.scala 157:42] + i0_predict_newp_d.way <= io.dec_i0_predict_p_d.way @[el2_exu.scala 158:32] + i0_predict_newp_d.pja <= io.dec_i0_predict_p_d.pja @[el2_exu.scala 158:32] + i0_predict_newp_d.pret <= io.dec_i0_predict_p_d.pret @[el2_exu.scala 158:32] + i0_predict_newp_d.pcall <= io.dec_i0_predict_p_d.pcall @[el2_exu.scala 158:32] + i0_predict_newp_d.prett <= io.dec_i0_predict_p_d.prett @[el2_exu.scala 158:32] + i0_predict_newp_d.br_start_error <= io.dec_i0_predict_p_d.br_start_error @[el2_exu.scala 158:32] + i0_predict_newp_d.br_error <= io.dec_i0_predict_p_d.br_error @[el2_exu.scala 158:32] + i0_predict_newp_d.valid <= io.dec_i0_predict_p_d.valid @[el2_exu.scala 158:32] + i0_predict_newp_d.toffset <= io.dec_i0_predict_p_d.toffset @[el2_exu.scala 158:32] + i0_predict_newp_d.hist <= io.dec_i0_predict_p_d.hist @[el2_exu.scala 158:32] + i0_predict_newp_d.pc4 <= io.dec_i0_predict_p_d.pc4 @[el2_exu.scala 158:32] + i0_predict_newp_d.boffset <= io.dec_i0_predict_p_d.boffset @[el2_exu.scala 158:32] + i0_predict_newp_d.ataken <= io.dec_i0_predict_p_d.ataken @[el2_exu.scala 158:32] + i0_predict_newp_d.misp <= io.dec_i0_predict_p_d.misp @[el2_exu.scala 158:32] + node _T_144 = bits(io.dec_i0_pc_d, 0, 0) @[el2_exu.scala 159:50] + i0_predict_newp_d.boffset <= _T_144 @[el2_exu.scala 159:32] + io.exu_pmu_i0_br_misp <= i0_pp_r.misp @[el2_exu.scala 161:31] + io.exu_pmu_i0_br_ataken <= i0_pp_r.ataken @[el2_exu.scala 162:31] + io.exu_pmu_i0_pc4 <= i0_pp_r.pc4 @[el2_exu.scala 163:31] + node _T_145 = and(i0_predict_p_d.valid, io.dec_i0_alu_decode_d) @[el2_exu.scala 166:54] + node _T_146 = not(io.dec_tlu_flush_lower_r) @[el2_exu.scala 166:81] + node _T_147 = and(_T_145, _T_146) @[el2_exu.scala 166:79] + i0_valid_d <= _T_147 @[el2_exu.scala 166:28] + node _T_148 = and(i0_predict_p_d.ataken, io.dec_i0_alu_decode_d) @[el2_exu.scala 167:54] + i0_taken_d <= _T_148 @[el2_exu.scala 167:28] + node _T_149 = not(io.dec_tlu_flush_lower_r) @[el2_exu.scala 173:6] + node _T_150 = and(_T_149, i0_valid_d) @[el2_exu.scala 173:32] + node _T_151 = bits(_T_150, 0, 0) @[el2_exu.scala 173:47] + node _T_152 = bits(ghr_d, 6, 0) @[el2_exu.scala 173:78] + node _T_153 = cat(_T_152, i0_taken_d) @[Cat.scala 29:58] + node _T_154 = not(io.dec_tlu_flush_lower_r) @[el2_exu.scala 174:6] + node _T_155 = not(i0_valid_d) @[el2_exu.scala 174:34] + node _T_156 = and(_T_154, _T_155) @[el2_exu.scala 174:32] + node _T_157 = bits(_T_156, 0, 0) @[el2_exu.scala 174:47] + node _T_158 = bits(io.dec_tlu_flush_lower_r, 0, 0) @[el2_exu.scala 175:32] + node _T_159 = mux(_T_151, _T_153, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_160 = mux(_T_157, ghr_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_161 = mux(_T_158, ghr_x, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_162 = or(_T_159, _T_160) @[Mux.scala 27:72] + node _T_163 = or(_T_162, _T_161) @[Mux.scala 27:72] + wire _T_164 : UInt @[Mux.scala 27:72] + _T_164 <= _T_163 @[Mux.scala 27:72] + ghr_d_ns <= _T_164 @[el2_exu.scala 172:11] + node _T_165 = eq(i0_valid_x, UInt<1>("h01")) @[el2_exu.scala 179:27] + node _T_166 = bits(ghr_x, 6, 0) @[el2_exu.scala 179:44] + node _T_167 = cat(_T_166, i0_taken_x) @[Cat.scala 29:58] + node _T_168 = mux(_T_165, _T_167, ghr_x) @[el2_exu.scala 179:16] + ghr_x_ns <= _T_168 @[el2_exu.scala 179:11] + io.exu_i0_br_valid_r <= i0_pp_r.valid @[el2_exu.scala 181:36] + io.exu_i0_br_mp_r <= i0_pp_r.misp @[el2_exu.scala 182:36] + io.exu_i0_br_way_r <= i0_pp_r.way @[el2_exu.scala 183:36] + io.exu_i0_br_hist_r <= i0_pp_r.hist @[el2_exu.scala 184:50] + io.exu_i0_br_error_r <= i0_pp_r.br_error @[el2_exu.scala 185:42] + node _T_169 = xor(i0_pp_r.pc4, i0_pp_r.boffset) @[el2_exu.scala 186:52] + io.exu_i0_br_middle_r <= _T_169 @[el2_exu.scala 186:36] + io.exu_i0_br_start_error_r <= i0_pp_r.br_start_error @[el2_exu.scala 187:36] + node _T_170 = bits(predpipe_r, 20, 13) @[el2_exu.scala 188:64] + io.exu_i0_br_fghr_r <= _T_170 @[el2_exu.scala 188:50] + node _T_171 = bits(predpipe_r, 12, 5) @[el2_exu.scala 189:56] + io.exu_i0_br_index_r <= _T_171 @[el2_exu.scala 189:42] + node _T_172 = eq(i0_flush_upper_x, UInt<1>("h01")) @[el2_exu.scala 190:74] + wire _T_173 : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>} @[el2_exu.scala 190:108] + _T_173.way <= UInt<1>("h00") @[el2_exu.scala 190:108] + _T_173.pja <= UInt<1>("h00") @[el2_exu.scala 190:108] + _T_173.pret <= UInt<1>("h00") @[el2_exu.scala 190:108] + _T_173.pcall <= UInt<1>("h00") @[el2_exu.scala 190:108] + _T_173.prett <= UInt<31>("h00") @[el2_exu.scala 190:108] + _T_173.br_start_error <= UInt<1>("h00") @[el2_exu.scala 190:108] + _T_173.br_error <= UInt<1>("h00") @[el2_exu.scala 190:108] + _T_173.valid <= UInt<1>("h00") @[el2_exu.scala 190:108] + _T_173.toffset <= UInt<12>("h00") @[el2_exu.scala 190:108] + _T_173.hist <= UInt<2>("h00") @[el2_exu.scala 190:108] + _T_173.pc4 <= UInt<1>("h00") @[el2_exu.scala 190:108] + _T_173.boffset <= UInt<1>("h00") @[el2_exu.scala 190:108] + _T_173.ataken <= UInt<1>("h00") @[el2_exu.scala 190:108] + _T_173.misp <= UInt<1>("h00") @[el2_exu.scala 190:108] + node _T_174 = mux(_T_172, i0_predict_p_x, _T_173) @[el2_exu.scala 190:57] + final_predict_mp.way <= _T_174.way @[el2_exu.scala 190:50] + final_predict_mp.pja <= _T_174.pja @[el2_exu.scala 190:50] + final_predict_mp.pret <= _T_174.pret @[el2_exu.scala 190:50] + final_predict_mp.pcall <= _T_174.pcall @[el2_exu.scala 190:50] + final_predict_mp.prett <= _T_174.prett @[el2_exu.scala 190:50] + final_predict_mp.br_start_error <= _T_174.br_start_error @[el2_exu.scala 190:50] + final_predict_mp.br_error <= _T_174.br_error @[el2_exu.scala 190:50] + final_predict_mp.valid <= _T_174.valid @[el2_exu.scala 190:50] + final_predict_mp.toffset <= _T_174.toffset @[el2_exu.scala 190:50] + final_predict_mp.hist <= _T_174.hist @[el2_exu.scala 190:50] + final_predict_mp.pc4 <= _T_174.pc4 @[el2_exu.scala 190:50] + final_predict_mp.boffset <= _T_174.boffset @[el2_exu.scala 190:50] + final_predict_mp.ataken <= _T_174.ataken @[el2_exu.scala 190:50] + final_predict_mp.misp <= _T_174.misp @[el2_exu.scala 190:50] + node _T_175 = eq(i0_flush_upper_x, UInt<1>("h01")) @[el2_exu.scala 191:66] + node final_predpipe_mp = mux(_T_175, predpipe_x, UInt<1>("h00")) @[el2_exu.scala 191:49] + node _T_176 = eq(i0_flush_upper_x, UInt<1>("h01")) @[el2_exu.scala 193:60] + node _T_177 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h01")) @[el2_exu.scala 193:95] + node _T_178 = not(_T_177) @[el2_exu.scala 193:69] + node _T_179 = and(_T_176, _T_178) @[el2_exu.scala 193:67] + node after_flush_eghr = mux(_T_179, ghr_d, ghr_x) @[el2_exu.scala 193:42] + io.exu_mp_pkt.way <= final_predict_mp.way @[el2_exu.scala 196:36] + io.exu_mp_pkt.misp <= final_predict_mp.misp @[el2_exu.scala 197:36] + io.exu_mp_pkt.pcall <= final_predict_mp.pcall @[el2_exu.scala 198:36] + io.exu_mp_pkt.pja <= final_predict_mp.pja @[el2_exu.scala 199:36] + io.exu_mp_pkt.pret <= final_predict_mp.pret @[el2_exu.scala 200:36] + io.exu_mp_pkt.ataken <= final_predict_mp.ataken @[el2_exu.scala 201:36] + io.exu_mp_pkt.boffset <= final_predict_mp.boffset @[el2_exu.scala 202:36] + io.exu_mp_pkt.pc4 <= final_predict_mp.pc4 @[el2_exu.scala 203:36] + node _T_180 = bits(final_predict_mp.hist, 1, 0) @[el2_exu.scala 204:75] + io.exu_mp_pkt.hist <= _T_180 @[el2_exu.scala 204:50] + node _T_181 = bits(final_predict_mp.toffset, 11, 0) @[el2_exu.scala 205:70] + io.exu_mp_pkt.toffset <= _T_181 @[el2_exu.scala 205:42] + io.exu_mp_fghr <= after_flush_eghr @[el2_exu.scala 206:36] + node _T_182 = bits(final_predpipe_mp, 12, 5) @[el2_exu.scala 207:79] + io.exu_mp_index <= _T_182 @[el2_exu.scala 207:58] + node _T_183 = bits(final_predpipe_mp, 4, 0) @[el2_exu.scala 208:79] + io.exu_mp_btag <= _T_183 @[el2_exu.scala 208:58] + node _T_184 = bits(final_predpipe_mp, 20, 13) @[el2_exu.scala 209:57] + io.exu_mp_eghr <= _T_184 @[el2_exu.scala 209:36] + node _T_185 = bits(io.dec_tlu_flush_lower_r, 0, 0) @[el2_exu.scala 210:82] + node _T_186 = mux(_T_185, io.dec_tlu_flush_path_r, i0_flush_path_d) @[el2_exu.scala 210:56] + io.exu_flush_path_final <= _T_186 @[el2_exu.scala 210:50] + node _T_187 = eq(i0_pred_correct_upper_r, UInt<1>("h01")) @[el2_exu.scala 211:80] + node _T_188 = mux(_T_187, pred_correct_npc_r, i0_flush_path_upper_r) @[el2_exu.scala 211:56] + io.exu_npc_r <= _T_188 @[el2_exu.scala 211:50] + diff --git a/el2_exu.v b/el2_exu.v new file mode 100644 index 00000000..c840c350 --- /dev/null +++ b/el2_exu.v @@ -0,0 +1,2605 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + TEC_RV_ICG clkhdr ( // @[el2_lib.scala 474:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] +endmodule +module el2_exu_alu_ctl( + input clock, + input reset, + input io_scan_mode, + input io_flush_upper_x, + input io_flush_lower_r, + input io_enable, + input io_valid_in, + input io_ap_land, + input io_ap_lor, + input io_ap_lxor, + input io_ap_sll, + input io_ap_srl, + input io_ap_sra, + input io_ap_beq, + input io_ap_bne, + input io_ap_blt, + input io_ap_bge, + input io_ap_add, + input io_ap_sub, + input io_ap_slt, + input io_ap_unsign, + input io_ap_jal, + input io_ap_predict_t, + input io_ap_predict_nt, + input io_ap_csr_write, + input io_ap_csr_imm, + input io_csr_ren_in, + input [31:0] io_a_in, + input [31:0] io_b_in, + input [30:0] io_pc_in, + input io_pp_in_boffset, + input io_pp_in_pc4, + input [1:0] io_pp_in_hist, + input [11:0] io_pp_in_toffset, + input io_pp_in_valid, + input io_pp_in_br_error, + input io_pp_in_br_start_error, + input [30:0] io_pp_in_prett, + input io_pp_in_pcall, + input io_pp_in_pret, + input io_pp_in_pja, + input io_pp_in_way, + input [11:0] io_brimm_in, + output [31:0] io_result_ff, + output io_flush_upper_out, + output io_flush_final_out, + output [30:0] io_flush_path_out, + output [30:0] io_pc_ff, + output io_pred_correct_out, + output io_predict_p_out_misp, + output io_predict_p_out_ataken, + output io_predict_p_out_boffset, + output io_predict_p_out_pc4, + output [1:0] io_predict_p_out_hist, + output [11:0] io_predict_p_out_toffset, + output io_predict_p_out_valid, + output io_predict_p_out_br_error, + output io_predict_p_out_br_start_error, + output io_predict_p_out_pcall, + output io_predict_p_out_pret, + output io_predict_p_out_pja, + output io_predict_p_out_way +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + reg [30:0] _T_1; // @[el2_lib.scala 514:16] + reg [31:0] _T_3; // @[el2_lib.scala 514:16] + wire [31:0] _T_5 = ~io_b_in; // @[el2_exu_alu_ctl.scala 39:37] + wire [31:0] bm = io_ap_sub ? _T_5 : io_b_in; // @[el2_exu_alu_ctl.scala 39:17] + wire [32:0] _T_8 = {1'h0,io_a_in}; // @[Cat.scala 29:58] + wire [32:0] _T_10 = {1'h0,_T_5}; // @[Cat.scala 29:58] + wire [32:0] _T_12 = _T_8 + _T_10; // @[el2_exu_alu_ctl.scala 42:55] + wire [32:0] _T_13 = {32'h0,io_ap_sub}; // @[Cat.scala 29:58] + wire [32:0] _T_15 = _T_12 + _T_13; // @[el2_exu_alu_ctl.scala 42:80] + wire [32:0] _T_18 = {1'h0,io_b_in}; // @[Cat.scala 29:58] + wire [32:0] _T_20 = _T_8 + _T_18; // @[el2_exu_alu_ctl.scala 42:132] + wire [32:0] _T_23 = _T_20 + _T_13; // @[el2_exu_alu_ctl.scala 42:157] + wire [32:0] aout = io_ap_sub ? _T_15 : _T_23; // @[el2_exu_alu_ctl.scala 42:14] + wire cout = aout[32]; // @[el2_exu_alu_ctl.scala 43:18] + wire _T_26 = ~io_a_in[31]; // @[el2_exu_alu_ctl.scala 45:14] + wire _T_28 = ~bm[31]; // @[el2_exu_alu_ctl.scala 45:29] + wire _T_29 = _T_26 & _T_28; // @[el2_exu_alu_ctl.scala 45:27] + wire _T_31 = _T_29 & aout[31]; // @[el2_exu_alu_ctl.scala 45:37] + wire _T_34 = io_a_in[31] & bm[31]; // @[el2_exu_alu_ctl.scala 45:66] + wire _T_36 = ~aout[31]; // @[el2_exu_alu_ctl.scala 45:78] + wire _T_37 = _T_34 & _T_36; // @[el2_exu_alu_ctl.scala 45:76] + wire ov = _T_31 | _T_37; // @[el2_exu_alu_ctl.scala 45:50] + wire eq = $signed(io_a_in) == $signed(io_b_in); // @[el2_exu_alu_ctl.scala 47:38] + wire ne = ~eq; // @[el2_exu_alu_ctl.scala 48:29] + wire _T_39 = ~io_ap_unsign; // @[el2_exu_alu_ctl.scala 50:30] + wire _T_40 = aout[31] ^ ov; // @[el2_exu_alu_ctl.scala 50:51] + wire _T_41 = _T_39 & _T_40; // @[el2_exu_alu_ctl.scala 50:44] + wire _T_42 = ~cout; // @[el2_exu_alu_ctl.scala 50:78] + wire _T_43 = io_ap_unsign & _T_42; // @[el2_exu_alu_ctl.scala 50:76] + wire lt = _T_41 | _T_43; // @[el2_exu_alu_ctl.scala 50:58] + wire ge = ~lt; // @[el2_exu_alu_ctl.scala 51:29] + wire [31:0] _T_63 = $signed(io_a_in) & $signed(io_b_in); // @[Mux.scala 27:72] + wire [31:0] _T_66 = $signed(io_a_in) | $signed(io_b_in); // @[Mux.scala 27:72] + wire [31:0] _T_69 = $signed(io_a_in) ^ $signed(io_b_in); // @[Mux.scala 27:72] + wire [31:0] _T_70 = io_csr_ren_in ? $signed(io_b_in) : $signed(32'sh0); // @[Mux.scala 27:72] + wire [31:0] _T_71 = io_ap_land ? $signed(_T_63) : $signed(32'sh0); // @[Mux.scala 27:72] + wire [31:0] _T_72 = io_ap_lor ? $signed(_T_66) : $signed(32'sh0); // @[Mux.scala 27:72] + wire [31:0] _T_73 = io_ap_lxor ? $signed(_T_69) : $signed(32'sh0); // @[Mux.scala 27:72] + wire [31:0] _T_75 = $signed(_T_70) | $signed(_T_71); // @[Mux.scala 27:72] + wire [31:0] _T_77 = $signed(_T_75) | $signed(_T_72); // @[Mux.scala 27:72] + wire [5:0] _T_84 = {1'h0,io_b_in[4:0]}; // @[Cat.scala 29:58] + wire [5:0] _T_86 = 6'h20 - _T_84; // @[el2_exu_alu_ctl.scala 61:38] + wire [5:0] _T_93 = io_ap_sll ? _T_86 : 6'h0; // @[Mux.scala 27:72] + wire [5:0] _T_94 = io_ap_srl ? _T_84 : 6'h0; // @[Mux.scala 27:72] + wire [5:0] _T_95 = io_ap_sra ? _T_84 : 6'h0; // @[Mux.scala 27:72] + wire [5:0] _T_96 = _T_93 | _T_94; // @[Mux.scala 27:72] + wire [5:0] shift_amount = _T_96 | _T_95; // @[Mux.scala 27:72] + wire [4:0] _T_102 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] + wire [4:0] _T_104 = _T_102 & io_b_in[4:0]; // @[el2_exu_alu_ctl.scala 66:61] + wire [62:0] _T_105 = 63'hffffffff << _T_104; // @[el2_exu_alu_ctl.scala 66:39] + wire [9:0] _T_115 = {io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58] + wire [18:0] _T_124 = {_T_115,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58] + wire [27:0] _T_133 = {_T_124,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58] + wire [30:0] _T_136 = {_T_133,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58] + wire [9:0] _T_147 = {io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58] + wire [18:0] _T_156 = {_T_147,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58] + wire [27:0] _T_165 = {_T_156,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58] + wire [30:0] _T_168 = {_T_165,io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58] + wire [30:0] _T_169 = _T_136 & _T_168; // @[el2_exu_alu_ctl.scala 69:44] + wire [9:0] _T_179 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] + wire [18:0] _T_188 = {_T_179,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] + wire [27:0] _T_197 = {_T_188,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] + wire [30:0] _T_200 = {_T_197,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] + wire [30:0] _T_202 = _T_200 & io_a_in[30:0]; // @[el2_exu_alu_ctl.scala 69:90] + wire [30:0] _T_203 = _T_169 | _T_202; // @[el2_exu_alu_ctl.scala 69:68] + wire [62:0] shift_extend = {_T_203,io_a_in}; // @[Cat.scala 29:58] + wire [62:0] shift_long = shift_extend >> shift_amount[4:0]; // @[el2_exu_alu_ctl.scala 72:32] + wire [31:0] shift_mask = _T_105[31:0]; // @[el2_exu_alu_ctl.scala 66:14] + wire [31:0] sout = shift_long[31:0] & shift_mask; // @[el2_exu_alu_ctl.scala 74:34] + wire _T_210 = io_ap_sll | io_ap_srl; // @[el2_exu_alu_ctl.scala 77:41] + wire sel_shift = _T_210 | io_ap_sra; // @[el2_exu_alu_ctl.scala 77:53] + wire _T_211 = io_ap_add | io_ap_sub; // @[el2_exu_alu_ctl.scala 78:41] + wire _T_212 = ~io_ap_slt; // @[el2_exu_alu_ctl.scala 78:56] + wire sel_adder = _T_211 & _T_212; // @[el2_exu_alu_ctl.scala 78:54] + wire _T_213 = io_ap_jal | io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 79:41] + wire _T_214 = _T_213 | io_pp_in_pja; // @[el2_exu_alu_ctl.scala 79:58] + wire sel_pc = _T_214 | io_pp_in_pret; // @[el2_exu_alu_ctl.scala 79:73] + wire slt_one = io_ap_slt & lt; // @[el2_exu_alu_ctl.scala 82:40] + wire [31:0] _T_217 = {io_pc_in,1'h0}; // @[Cat.scala 29:58] + wire [12:0] _T_218 = {io_brimm_in,1'h0}; // @[Cat.scala 29:58] + wire [12:0] _T_221 = _T_217[12:1] + _T_218[12:1]; // @[el2_lib.scala 208:31] + wire [18:0] _T_224 = _T_217[31:13] + 19'h1; // @[el2_lib.scala 209:27] + wire [18:0] _T_227 = _T_217[31:13] - 19'h1; // @[el2_lib.scala 210:27] + wire _T_230 = ~_T_221[12]; // @[el2_lib.scala 212:28] + wire _T_231 = _T_218[12] ^ _T_230; // @[el2_lib.scala 212:26] + wire _T_234 = ~_T_218[12]; // @[el2_lib.scala 213:20] + wire _T_236 = _T_234 & _T_221[12]; // @[el2_lib.scala 213:26] + wire _T_240 = _T_218[12] & _T_230; // @[el2_lib.scala 214:26] + wire [18:0] _T_242 = _T_231 ? _T_217[31:13] : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_243 = _T_236 ? _T_224 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_244 = _T_240 ? _T_227 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_245 = _T_242 | _T_243; // @[Mux.scala 27:72] + wire [18:0] _T_246 = _T_245 | _T_244; // @[Mux.scala 27:72] + wire [31:0] pcout = {_T_246,_T_221[11:0],1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_250 = $signed(_T_77) | $signed(_T_73); // @[el2_exu_alu_ctl.scala 88:24] + wire [31:0] _T_251 = {31'h0,slt_one}; // @[Cat.scala 29:58] + wire [31:0] _T_252 = _T_250 | _T_251; // @[el2_exu_alu_ctl.scala 88:31] + wire [31:0] _T_259 = io_ap_csr_imm ? $signed(io_b_in) : $signed(io_a_in); // @[el2_exu_alu_ctl.scala 92:51] + wire [31:0] _T_260 = sel_shift ? sout : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_261 = sel_adder ? aout[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_262 = sel_pc ? pcout : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_263 = io_ap_csr_write ? _T_259 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_264 = _T_260 | _T_261; // @[Mux.scala 27:72] + wire [31:0] _T_265 = _T_264 | _T_262; // @[Mux.scala 27:72] + wire [31:0] _T_266 = _T_265 | _T_263; // @[Mux.scala 27:72] + wire _T_271 = io_ap_beq & eq; // @[el2_exu_alu_ctl.scala 101:40] + wire _T_272 = io_ap_bne & ne; // @[el2_exu_alu_ctl.scala 101:59] + wire _T_273 = _T_271 | _T_272; // @[el2_exu_alu_ctl.scala 101:46] + wire _T_274 = io_ap_blt & lt; // @[el2_exu_alu_ctl.scala 101:85] + wire _T_275 = _T_273 | _T_274; // @[el2_exu_alu_ctl.scala 101:72] + wire _T_276 = io_ap_bge & ge; // @[el2_exu_alu_ctl.scala 101:104] + wire _T_277 = _T_275 | _T_276; // @[el2_exu_alu_ctl.scala 101:91] + wire actual_taken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 101:110] + wire _T_278 = io_valid_in & io_ap_predict_nt; // @[el2_exu_alu_ctl.scala 106:42] + wire _T_279 = ~actual_taken; // @[el2_exu_alu_ctl.scala 106:63] + wire _T_280 = _T_278 & _T_279; // @[el2_exu_alu_ctl.scala 106:61] + wire _T_281 = ~sel_pc; // @[el2_exu_alu_ctl.scala 106:79] + wire _T_282 = _T_280 & _T_281; // @[el2_exu_alu_ctl.scala 106:77] + wire _T_283 = io_valid_in & io_ap_predict_t; // @[el2_exu_alu_ctl.scala 106:104] + wire _T_284 = _T_283 & actual_taken; // @[el2_exu_alu_ctl.scala 106:123] + wire _T_286 = _T_284 & _T_281; // @[el2_exu_alu_ctl.scala 106:139] + wire _T_293 = io_ap_predict_t & _T_279; // @[el2_exu_alu_ctl.scala 111:45] + wire _T_294 = io_ap_predict_nt & actual_taken; // @[el2_exu_alu_ctl.scala 111:82] + wire cond_mispredict = _T_293 | _T_294; // @[el2_exu_alu_ctl.scala 111:62] + wire _T_296 = io_pp_in_prett != aout[31:1]; // @[el2_exu_alu_ctl.scala 114:62] + wire target_mispredict = io_pp_in_pret & _T_296; // @[el2_exu_alu_ctl.scala 114:44] + wire _T_297 = io_ap_jal | cond_mispredict; // @[el2_exu_alu_ctl.scala 116:42] + wire _T_298 = _T_297 | target_mispredict; // @[el2_exu_alu_ctl.scala 116:60] + wire _T_299 = _T_298 & io_valid_in; // @[el2_exu_alu_ctl.scala 116:81] + wire _T_300 = ~io_flush_upper_x; // @[el2_exu_alu_ctl.scala 116:97] + wire _T_301 = _T_299 & _T_300; // @[el2_exu_alu_ctl.scala 116:95] + wire _T_302 = ~io_flush_lower_r; // @[el2_exu_alu_ctl.scala 116:119] + wire _T_312 = io_pp_in_hist[1] & io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 122:39] + wire _T_314 = ~io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 122:63] + wire _T_315 = _T_314 & actual_taken; // @[el2_exu_alu_ctl.scala 122:81] + wire _T_316 = _T_312 | _T_315; // @[el2_exu_alu_ctl.scala 122:60] + wire _T_318 = ~io_pp_in_hist[1]; // @[el2_exu_alu_ctl.scala 123:6] + wire _T_320 = _T_318 & _T_279; // @[el2_exu_alu_ctl.scala 123:24] + wire _T_322 = io_pp_in_hist[1] & actual_taken; // @[el2_exu_alu_ctl.scala 123:62] + wire _T_323 = _T_320 | _T_322; // @[el2_exu_alu_ctl.scala 123:42] + wire _T_327 = _T_300 & _T_302; // @[el2_exu_alu_ctl.scala 126:51] + wire _T_328 = cond_mispredict | target_mispredict; // @[el2_exu_alu_ctl.scala 126:90] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + assign io_result_ff = _T_3; // @[el2_exu_alu_ctl.scala 37:16] + assign io_flush_upper_out = _T_301 & _T_302; // @[el2_exu_alu_ctl.scala 116:26] + assign io_flush_final_out = _T_301 | io_flush_lower_r; // @[el2_exu_alu_ctl.scala 118:26] + assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[el2_exu_alu_ctl.scala 108:22] + assign io_pc_ff = _T_1; // @[el2_exu_alu_ctl.scala 35:12] + assign io_pred_correct_out = _T_282 | _T_286; // @[el2_exu_alu_ctl.scala 106:26] + assign io_predict_p_out_misp = _T_327 & _T_328; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 126:30] + assign io_predict_p_out_ataken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 127:30] + assign io_predict_p_out_boffset = io_pp_in_boffset; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_pc4 = io_pp_in_pc4; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_hist = {_T_316,_T_323}; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 128:30] + assign io_predict_p_out_toffset = io_pp_in_toffset; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_valid = io_pp_in_valid; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_br_error = io_pp_in_br_error; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_br_start_error = io_pp_in_br_start_error; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_pcall = io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_pret = io_pp_in_pret; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_pja = io_pp_in_pja; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_way = io_pp_in_way; // @[el2_exu_alu_ctl.scala 125:30] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = io_enable; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = io_enable; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T_1 = _RAND_0[30:0]; + _RAND_1 = {1{`RANDOM}}; + _T_3 = _RAND_1[31:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_1 = 31'h0; + end + if (reset) begin + _T_3 = 32'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + _T_1 <= 31'h0; + end else begin + _T_1 <= io_pc_in; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + _T_3 <= 32'h0; + end else begin + _T_3 <= _T_252 | _T_266; + end + end +endmodule +module el2_exu_mul_ctl( + input clock, + input reset, + input io_scan_mode, + input io_mul_p_valid, + input io_mul_p_rs1_sign, + input io_mul_p_rs2_sign, + input io_mul_p_low, + input [31:0] io_rs1_in, + input [31:0] io_rs2_in, + output [31:0] io_result_x +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [63:0] _RAND_1; + reg [63:0] _RAND_2; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 528:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 528:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 528:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 528:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 528:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 528:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 528:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 528:23] + wire _T_1 = io_mul_p_rs1_sign & io_rs1_in[31]; // @[el2_exu_mul_ctl.scala 26:39] + wire _T_5 = io_mul_p_rs2_sign & io_rs2_in[31]; // @[el2_exu_mul_ctl.scala 27:39] + reg low_x; // @[el2_lib.scala 514:16] + reg [32:0] rs1_x; // @[el2_lib.scala 534:16] + reg [32:0] rs2_x; // @[el2_lib.scala 534:16] + wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[el2_exu_mul_ctl.scala 40:20] + wire _T_16 = ~low_x; // @[el2_exu_mul_ctl.scala 41:29] + wire [31:0] _T_20 = _T_16 ? prod_x[63:32] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_21 = low_x ? prod_x[31:0] : 32'h0; // @[Mux.scala 27:72] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 528:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 528:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + assign io_result_x = _T_20 | _T_21; // @[el2_exu_mul_ctl.scala 41:15] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = io_mul_p_valid; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 530:18] + assign rvclkhdr_1_io_en = io_mul_p_valid; // @[el2_lib.scala 531:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 532:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 530:18] + assign rvclkhdr_2_io_en = io_mul_p_valid; // @[el2_lib.scala 531:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 532:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + low_x = _RAND_0[0:0]; + _RAND_1 = {2{`RANDOM}}; + rs1_x = _RAND_1[32:0]; + _RAND_2 = {2{`RANDOM}}; + rs2_x = _RAND_2[32:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + low_x = 1'h0; + end + if (reset) begin + rs1_x = 33'sh0; + end + if (reset) begin + rs2_x = 33'sh0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + low_x <= 1'h0; + end else begin + low_x <= io_mul_p_low; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + rs1_x <= 33'sh0; + end else begin + rs1_x <= {_T_1,io_rs1_in}; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + rs2_x <= 33'sh0; + end else begin + rs2_x <= {_T_5,io_rs2_in}; + end + end +endmodule +module el2_exu_div_ctl( + input clock, + input reset, + input io_scan_mode, + input io_dp_valid, + input io_dp_unsign, + input io_dp_rem, + input [31:0] io_dividend, + input [31:0] io_divisor, + input io_cancel, + output [31:0] io_out, + output io_finish_dly +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [63:0] _RAND_1; + reg [63:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [63:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] + wire _T = ~io_cancel; // @[el2_exu_div_ctl.scala 54:30] + reg valid_ff_x; // @[el2_exu_div_ctl.scala 204:26] + wire valid_x = valid_ff_x & _T; // @[el2_exu_div_ctl.scala 54:28] + reg [32:0] q_ff; // @[el2_lib.scala 514:16] + wire _T_2 = q_ff[31:4] == 28'h0; // @[el2_exu_div_ctl.scala 60:34] + reg [32:0] m_ff; // @[el2_lib.scala 514:16] + wire _T_4 = m_ff[31:4] == 28'h0; // @[el2_exu_div_ctl.scala 60:57] + wire _T_5 = _T_2 & _T_4; // @[el2_exu_div_ctl.scala 60:43] + wire _T_7 = m_ff[31:0] != 32'h0; // @[el2_exu_div_ctl.scala 60:80] + wire _T_8 = _T_5 & _T_7; // @[el2_exu_div_ctl.scala 60:66] + reg rem_ff; // @[Reg.scala 27:20] + wire _T_9 = ~rem_ff; // @[el2_exu_div_ctl.scala 60:91] + wire _T_10 = _T_8 & _T_9; // @[el2_exu_div_ctl.scala 60:89] + wire _T_11 = _T_10 & valid_x; // @[el2_exu_div_ctl.scala 60:99] + wire _T_13 = q_ff[31:0] == 32'h0; // @[el2_exu_div_ctl.scala 61:18] + wire _T_16 = _T_13 & _T_7; // @[el2_exu_div_ctl.scala 61:27] + wire _T_18 = _T_16 & _T_9; // @[el2_exu_div_ctl.scala 61:50] + wire _T_19 = _T_18 & valid_x; // @[el2_exu_div_ctl.scala 61:60] + wire smallnum_case = _T_11 | _T_19; // @[el2_exu_div_ctl.scala 60:110] + wire pat1 = q_ff[3]; // @[el2_exu_div_ctl.scala 64:57] + wire _T_22 = ~m_ff[3]; // @[el2_exu_div_ctl.scala 65:69] + wire _T_24 = ~m_ff[2]; // @[el2_exu_div_ctl.scala 65:69] + wire _T_26 = ~m_ff[1]; // @[el2_exu_div_ctl.scala 65:69] + wire _T_27 = _T_22 & _T_24; // @[el2_exu_div_ctl.scala 65:94] + wire pat2 = _T_27 & _T_26; // @[el2_exu_div_ctl.scala 65:94] + wire _T_28 = pat1 & pat2; // @[el2_exu_div_ctl.scala 66:10] + wire _T_33 = pat1 & _T_27; // @[el2_exu_div_ctl.scala 66:10] + wire _T_35 = ~m_ff[0]; // @[el2_exu_div_ctl.scala 72:32] + wire _T_36 = _T_33 & _T_35; // @[el2_exu_div_ctl.scala 72:30] + wire pat1_2 = q_ff[2]; // @[el2_exu_div_ctl.scala 64:57] + wire _T_44 = pat1_2 & pat2; // @[el2_exu_div_ctl.scala 66:10] + wire _T_45 = _T_36 | _T_44; // @[el2_exu_div_ctl.scala 72:41] + wire pat1_3 = pat1 & pat1_2; // @[el2_exu_div_ctl.scala 64:94] + wire _T_52 = pat1_3 & _T_27; // @[el2_exu_div_ctl.scala 66:10] + wire _T_53 = _T_45 | _T_52; // @[el2_exu_div_ctl.scala 72:73] + wire _T_58 = pat1_2 & _T_27; // @[el2_exu_div_ctl.scala 66:10] + wire _T_61 = _T_58 & _T_35; // @[el2_exu_div_ctl.scala 74:30] + wire pat1_5 = q_ff[1]; // @[el2_exu_div_ctl.scala 64:57] + wire _T_69 = pat1_5 & pat2; // @[el2_exu_div_ctl.scala 66:10] + wire _T_70 = _T_61 | _T_69; // @[el2_exu_div_ctl.scala 74:41] + wire pat2_6 = _T_22 & _T_26; // @[el2_exu_div_ctl.scala 65:94] + wire _T_75 = pat1 & pat2_6; // @[el2_exu_div_ctl.scala 66:10] + wire _T_78 = _T_75 & _T_35; // @[el2_exu_div_ctl.scala 74:103] + wire _T_79 = _T_70 | _T_78; // @[el2_exu_div_ctl.scala 74:76] + wire _T_82 = ~pat1_2; // @[el2_exu_div_ctl.scala 64:69] + wire pat1_7 = pat1 & _T_82; // @[el2_exu_div_ctl.scala 64:94] + wire _T_90 = _T_27 & m_ff[1]; // @[el2_exu_div_ctl.scala 65:94] + wire pat2_7 = _T_90 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94] + wire _T_91 = pat1_7 & pat2_7; // @[el2_exu_div_ctl.scala 66:10] + wire _T_92 = _T_79 | _T_91; // @[el2_exu_div_ctl.scala 74:114] + wire _T_94 = ~pat1; // @[el2_exu_div_ctl.scala 64:69] + wire _T_97 = _T_94 & pat1_2; // @[el2_exu_div_ctl.scala 64:94] + wire pat1_8 = _T_97 & pat1_5; // @[el2_exu_div_ctl.scala 64:94] + wire _T_102 = pat1_8 & _T_27; // @[el2_exu_div_ctl.scala 66:10] + wire _T_103 = _T_92 | _T_102; // @[el2_exu_div_ctl.scala 75:43] + wire _T_107 = pat1_3 & _T_22; // @[el2_exu_div_ctl.scala 66:10] + wire _T_110 = _T_107 & _T_35; // @[el2_exu_div_ctl.scala 75:104] + wire _T_111 = _T_103 | _T_110; // @[el2_exu_div_ctl.scala 75:78] + wire _T_119 = _T_22 & m_ff[2]; // @[el2_exu_div_ctl.scala 65:94] + wire pat2_10 = _T_119 & _T_26; // @[el2_exu_div_ctl.scala 65:94] + wire _T_120 = pat1_3 & pat2_10; // @[el2_exu_div_ctl.scala 66:10] + wire _T_121 = _T_111 | _T_120; // @[el2_exu_div_ctl.scala 75:116] + wire pat1_11 = pat1 & pat1_5; // @[el2_exu_div_ctl.scala 64:94] + wire _T_128 = pat1_11 & pat2_6; // @[el2_exu_div_ctl.scala 66:10] + wire _T_129 = _T_121 | _T_128; // @[el2_exu_div_ctl.scala 76:43] + wire pat1_12 = pat1_3 & pat1_5; // @[el2_exu_div_ctl.scala 64:94] + wire _T_137 = pat1_12 & _T_119; // @[el2_exu_div_ctl.scala 66:10] + wire _T_138 = _T_129 | _T_137; // @[el2_exu_div_ctl.scala 76:77] + wire _T_142 = pat1_2 & pat1_5; // @[el2_exu_div_ctl.scala 64:94] + wire pat1_13 = _T_142 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_147 = pat1_13 & pat2_6; // @[el2_exu_div_ctl.scala 66:10] + wire pat1_14 = pat1_7 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_157 = _T_22 & m_ff[1]; // @[el2_exu_div_ctl.scala 65:94] + wire pat2_14 = _T_157 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94] + wire _T_158 = pat1_14 & pat2_14; // @[el2_exu_div_ctl.scala 66:10] + wire _T_159 = _T_147 | _T_158; // @[el2_exu_div_ctl.scala 78:44] + wire _T_164 = pat1_2 & pat2_6; // @[el2_exu_div_ctl.scala 66:10] + wire _T_167 = _T_164 & _T_35; // @[el2_exu_div_ctl.scala 78:111] + wire _T_168 = _T_159 | _T_167; // @[el2_exu_div_ctl.scala 78:84] + wire _T_173 = pat1_5 & _T_27; // @[el2_exu_div_ctl.scala 66:10] + wire _T_176 = _T_173 & _T_35; // @[el2_exu_div_ctl.scala 79:32] + wire _T_177 = _T_168 | _T_176; // @[el2_exu_div_ctl.scala 78:126] + wire _T_185 = q_ff[0] & pat2; // @[el2_exu_div_ctl.scala 66:10] + wire _T_186 = _T_177 | _T_185; // @[el2_exu_div_ctl.scala 79:46] + wire _T_191 = ~pat1_5; // @[el2_exu_div_ctl.scala 64:69] + wire pat1_18 = _T_97 & _T_191; // @[el2_exu_div_ctl.scala 64:94] + wire _T_201 = pat1_18 & pat2_7; // @[el2_exu_div_ctl.scala 66:10] + wire _T_202 = _T_186 | _T_201; // @[el2_exu_div_ctl.scala 79:86] + wire _T_209 = pat1_8 & _T_22; // @[el2_exu_div_ctl.scala 66:10] + wire _T_212 = _T_209 & _T_35; // @[el2_exu_div_ctl.scala 80:35] + wire _T_213 = _T_202 | _T_212; // @[el2_exu_div_ctl.scala 79:128] + wire pat2_20 = _T_24 & _T_26; // @[el2_exu_div_ctl.scala 65:94] + wire _T_218 = pat1 & pat2_20; // @[el2_exu_div_ctl.scala 66:10] + wire _T_221 = _T_218 & _T_35; // @[el2_exu_div_ctl.scala 80:74] + wire _T_222 = _T_213 | _T_221; // @[el2_exu_div_ctl.scala 80:46] + wire pat2_21 = _T_119 & m_ff[1]; // @[el2_exu_div_ctl.scala 65:94] + wire _T_231 = pat1_7 & pat2_21; // @[el2_exu_div_ctl.scala 66:10] + wire _T_232 = _T_222 | _T_231; // @[el2_exu_div_ctl.scala 80:86] + wire _T_244 = pat1_8 & pat2_10; // @[el2_exu_div_ctl.scala 66:10] + wire _T_245 = _T_232 | _T_244; // @[el2_exu_div_ctl.scala 80:128] + wire pat1_23 = _T_97 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_255 = pat1_23 & pat2_6; // @[el2_exu_div_ctl.scala 66:10] + wire _T_256 = _T_245 | _T_255; // @[el2_exu_div_ctl.scala 81:46] + wire pat1_24 = pat1_7 & _T_191; // @[el2_exu_div_ctl.scala 64:94] + wire pat2_24 = _T_119 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94] + wire _T_268 = pat1_24 & pat2_24; // @[el2_exu_div_ctl.scala 66:10] + wire _T_269 = _T_256 | _T_268; // @[el2_exu_div_ctl.scala 81:86] + wire _T_274 = _T_82 & pat1_5; // @[el2_exu_div_ctl.scala 64:94] + wire pat1_25 = _T_274 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_279 = pat1_25 & _T_27; // @[el2_exu_div_ctl.scala 66:10] + wire _T_280 = _T_269 | _T_279; // @[el2_exu_div_ctl.scala 81:128] + wire _T_284 = pat1_3 & _T_26; // @[el2_exu_div_ctl.scala 66:10] + wire _T_287 = _T_284 & _T_35; // @[el2_exu_div_ctl.scala 82:73] + wire _T_288 = _T_280 | _T_287; // @[el2_exu_div_ctl.scala 82:46] + wire pat1_27 = pat1_8 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_299 = pat1_27 & _T_119; // @[el2_exu_div_ctl.scala 66:10] + wire _T_300 = _T_288 | _T_299; // @[el2_exu_div_ctl.scala 82:86] + wire pat2_28 = m_ff[3] & _T_24; // @[el2_exu_div_ctl.scala 65:94] + wire _T_306 = pat1_3 & pat2_28; // @[el2_exu_div_ctl.scala 66:10] + wire _T_307 = _T_300 | _T_306; // @[el2_exu_div_ctl.scala 82:128] + wire pat2_29 = pat2_28 & _T_26; // @[el2_exu_div_ctl.scala 65:94] + wire _T_316 = pat1_11 & pat2_29; // @[el2_exu_div_ctl.scala 66:10] + wire _T_317 = _T_307 | _T_316; // @[el2_exu_div_ctl.scala 83:46] + wire pat1_30 = pat1 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_324 = pat1_30 & pat2_20; // @[el2_exu_div_ctl.scala 66:10] + wire _T_325 = _T_317 | _T_324; // @[el2_exu_div_ctl.scala 83:86] + wire pat1_31 = pat1 & _T_191; // @[el2_exu_div_ctl.scala 64:94] + wire pat2_31 = pat2_21 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94] + wire _T_336 = pat1_31 & pat2_31; // @[el2_exu_div_ctl.scala 66:10] + wire _T_337 = _T_325 | _T_336; // @[el2_exu_div_ctl.scala 83:128] + wire _T_342 = pat1_12 & m_ff[3]; // @[el2_exu_div_ctl.scala 66:10] + wire _T_345 = _T_342 & _T_35; // @[el2_exu_div_ctl.scala 84:75] + wire _T_346 = _T_337 | _T_345; // @[el2_exu_div_ctl.scala 84:46] + wire pat2_33 = m_ff[3] & _T_26; // @[el2_exu_div_ctl.scala 65:94] + wire _T_354 = pat1_12 & pat2_33; // @[el2_exu_div_ctl.scala 66:10] + wire _T_355 = _T_346 | _T_354; // @[el2_exu_div_ctl.scala 84:86] + wire pat1_34 = pat1_3 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_363 = pat1_34 & pat2_33; // @[el2_exu_div_ctl.scala 66:10] + wire _T_364 = _T_355 | _T_363; // @[el2_exu_div_ctl.scala 84:128] + wire pat1_35 = pat1_7 & pat1_5; // @[el2_exu_div_ctl.scala 64:94] + wire _T_373 = pat1_35 & _T_157; // @[el2_exu_div_ctl.scala 66:10] + wire _T_374 = _T_364 | _T_373; // @[el2_exu_div_ctl.scala 85:46] + wire pat1_36 = pat1_11 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_380 = pat1_36 & _T_24; // @[el2_exu_div_ctl.scala 66:10] + wire _T_381 = _T_374 | _T_380; // @[el2_exu_div_ctl.scala 85:86] + wire pat1_37 = pat1_12 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_388 = pat1_37 & m_ff[3]; // @[el2_exu_div_ctl.scala 66:10] + wire _T_389 = _T_381 | _T_388; // @[el2_exu_div_ctl.scala 85:128] + wire _T_393 = pat1_11 & _T_24; // @[el2_exu_div_ctl.scala 66:10] + wire _T_396 = _T_393 & _T_35; // @[el2_exu_div_ctl.scala 86:72] + wire _T_397 = _T_389 | _T_396; // @[el2_exu_div_ctl.scala 86:46] + wire [1:0] _T_398 = {_T_138,_T_397}; // @[Cat.scala 29:58] + wire [1:0] _T_399 = {_T_28,_T_53}; // @[Cat.scala 29:58] + reg sign_ff; // @[Reg.scala 27:20] + wire _T_401 = sign_ff & q_ff[31]; // @[el2_exu_div_ctl.scala 96:34] + wire [32:0] short_dividend = {_T_401,q_ff[31:0]}; // @[Cat.scala 29:58] + wire _T_406 = ~short_dividend[32]; // @[el2_exu_div_ctl.scala 101:7] + wire _T_409 = short_dividend[31:24] != 8'h0; // @[el2_exu_div_ctl.scala 101:60] + wire _T_414 = short_dividend[31:23] != 9'h1ff; // @[el2_exu_div_ctl.scala 102:59] + wire _T_415 = _T_406 & _T_409; // @[Mux.scala 27:72] + wire _T_416 = short_dividend[32] & _T_414; // @[Mux.scala 27:72] + wire _T_417 = _T_415 | _T_416; // @[Mux.scala 27:72] + wire _T_424 = short_dividend[23:16] != 8'h0; // @[el2_exu_div_ctl.scala 105:60] + wire _T_429 = short_dividend[22:15] != 8'hff; // @[el2_exu_div_ctl.scala 106:59] + wire _T_430 = _T_406 & _T_424; // @[Mux.scala 27:72] + wire _T_431 = short_dividend[32] & _T_429; // @[Mux.scala 27:72] + wire _T_432 = _T_430 | _T_431; // @[Mux.scala 27:72] + wire _T_439 = short_dividend[15:8] != 8'h0; // @[el2_exu_div_ctl.scala 109:59] + wire _T_444 = short_dividend[14:7] != 8'hff; // @[el2_exu_div_ctl.scala 110:58] + wire _T_445 = _T_406 & _T_439; // @[Mux.scala 27:72] + wire _T_446 = short_dividend[32] & _T_444; // @[Mux.scala 27:72] + wire _T_447 = _T_445 | _T_446; // @[Mux.scala 27:72] + wire [2:0] a_cls = {_T_417,_T_432,_T_447}; // @[Cat.scala 29:58] + wire _T_452 = ~m_ff[32]; // @[el2_exu_div_ctl.scala 115:7] + wire _T_455 = m_ff[31:24] != 8'h0; // @[el2_exu_div_ctl.scala 115:40] + wire _T_460 = m_ff[31:24] != 8'hff; // @[el2_exu_div_ctl.scala 116:39] + wire _T_461 = _T_452 & _T_455; // @[Mux.scala 27:72] + wire _T_462 = m_ff[32] & _T_460; // @[Mux.scala 27:72] + wire _T_463 = _T_461 | _T_462; // @[Mux.scala 27:72] + wire _T_470 = m_ff[23:16] != 8'h0; // @[el2_exu_div_ctl.scala 119:40] + wire _T_475 = m_ff[23:16] != 8'hff; // @[el2_exu_div_ctl.scala 120:39] + wire _T_476 = _T_452 & _T_470; // @[Mux.scala 27:72] + wire _T_477 = m_ff[32] & _T_475; // @[Mux.scala 27:72] + wire _T_478 = _T_476 | _T_477; // @[Mux.scala 27:72] + wire _T_485 = m_ff[15:8] != 8'h0; // @[el2_exu_div_ctl.scala 123:39] + wire _T_490 = m_ff[15:8] != 8'hff; // @[el2_exu_div_ctl.scala 124:38] + wire _T_491 = _T_452 & _T_485; // @[Mux.scala 27:72] + wire _T_492 = m_ff[32] & _T_490; // @[Mux.scala 27:72] + wire _T_493 = _T_491 | _T_492; // @[Mux.scala 27:72] + wire [2:0] b_cls = {_T_463,_T_478,_T_493}; // @[Cat.scala 29:58] + wire _T_497 = a_cls[2:1] == 2'h1; // @[el2_exu_div_ctl.scala 128:19] + wire _T_500 = _T_497 & b_cls[2]; // @[el2_exu_div_ctl.scala 128:34] + wire _T_502 = a_cls == 3'h1; // @[el2_exu_div_ctl.scala 129:21] + wire _T_505 = _T_502 & b_cls[2]; // @[el2_exu_div_ctl.scala 129:36] + wire _T_506 = _T_500 | _T_505; // @[el2_exu_div_ctl.scala 128:65] + wire _T_508 = a_cls == 3'h0; // @[el2_exu_div_ctl.scala 130:21] + wire _T_511 = _T_508 & b_cls[2]; // @[el2_exu_div_ctl.scala 130:36] + wire _T_512 = _T_506 | _T_511; // @[el2_exu_div_ctl.scala 129:67] + wire _T_516 = b_cls[2:1] == 2'h1; // @[el2_exu_div_ctl.scala 131:50] + wire _T_517 = _T_502 & _T_516; // @[el2_exu_div_ctl.scala 131:36] + wire _T_518 = _T_512 | _T_517; // @[el2_exu_div_ctl.scala 130:67] + wire _T_523 = _T_508 & _T_516; // @[el2_exu_div_ctl.scala 132:36] + wire _T_524 = _T_518 | _T_523; // @[el2_exu_div_ctl.scala 131:67] + wire _T_528 = b_cls == 3'h1; // @[el2_exu_div_ctl.scala 133:50] + wire _T_529 = _T_508 & _T_528; // @[el2_exu_div_ctl.scala 133:36] + wire _T_530 = _T_524 | _T_529; // @[el2_exu_div_ctl.scala 132:67] + wire _T_535 = a_cls[2] & b_cls[2]; // @[el2_exu_div_ctl.scala 135:34] + wire _T_540 = _T_497 & _T_516; // @[el2_exu_div_ctl.scala 136:36] + wire _T_541 = _T_535 | _T_540; // @[el2_exu_div_ctl.scala 135:65] + wire _T_546 = _T_502 & _T_528; // @[el2_exu_div_ctl.scala 137:36] + wire _T_547 = _T_541 | _T_546; // @[el2_exu_div_ctl.scala 136:67] + wire _T_551 = b_cls == 3'h0; // @[el2_exu_div_ctl.scala 138:50] + wire _T_552 = _T_508 & _T_551; // @[el2_exu_div_ctl.scala 138:36] + wire _T_553 = _T_547 | _T_552; // @[el2_exu_div_ctl.scala 137:67] + wire _T_558 = a_cls[2] & _T_516; // @[el2_exu_div_ctl.scala 140:34] + wire _T_563 = _T_497 & _T_528; // @[el2_exu_div_ctl.scala 141:36] + wire _T_564 = _T_558 | _T_563; // @[el2_exu_div_ctl.scala 140:65] + wire _T_569 = _T_502 & _T_551; // @[el2_exu_div_ctl.scala 142:36] + wire _T_570 = _T_564 | _T_569; // @[el2_exu_div_ctl.scala 141:67] + wire _T_575 = a_cls[2] & _T_528; // @[el2_exu_div_ctl.scala 144:34] + wire _T_580 = _T_497 & _T_551; // @[el2_exu_div_ctl.scala 145:36] + wire _T_581 = _T_575 | _T_580; // @[el2_exu_div_ctl.scala 144:65] + wire [3:0] shortq_raw = {_T_530,_T_553,_T_570,_T_581}; // @[Cat.scala 29:58] + wire _T_586 = valid_ff_x & _T_7; // @[el2_exu_div_ctl.scala 148:35] + wire _T_587 = shortq_raw != 4'h0; // @[el2_exu_div_ctl.scala 148:78] + wire shortq_enable = _T_586 & _T_587; // @[el2_exu_div_ctl.scala 148:64] + wire [3:0] _T_589 = shortq_enable ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + reg [3:0] shortq_shift_xx; // @[el2_exu_div_ctl.scala 215:31] + wire [4:0] _T_598 = shortq_shift_xx[3] ? 5'h1f : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_599 = shortq_shift_xx[2] ? 5'h18 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_600 = shortq_shift_xx[1] ? 5'h10 : 5'h0; // @[Mux.scala 27:72] + wire [3:0] _T_601 = shortq_shift_xx[0] ? 4'h8 : 4'h0; // @[Mux.scala 27:72] + wire [4:0] _T_602 = _T_598 | _T_599; // @[Mux.scala 27:72] + wire [4:0] _T_603 = _T_602 | _T_600; // @[Mux.scala 27:72] + wire [4:0] _GEN_4 = {{1'd0}, _T_601}; // @[Mux.scala 27:72] + wire [4:0] shortq_shift_ff = _T_603 | _GEN_4; // @[Mux.scala 27:72] + reg [5:0] count; // @[el2_exu_div_ctl.scala 207:21] + wire _T_606 = count == 6'h20; // @[el2_exu_div_ctl.scala 159:55] + wire _T_607 = count == 6'h21; // @[el2_exu_div_ctl.scala 159:76] + wire _T_608 = _T_9 ? _T_606 : _T_607; // @[el2_exu_div_ctl.scala 159:39] + wire finish = smallnum_case | _T_608; // @[el2_exu_div_ctl.scala 159:34] + reg run_state; // @[el2_exu_div_ctl.scala 206:25] + wire _T_609 = io_dp_valid | run_state; // @[el2_exu_div_ctl.scala 160:32] + wire _T_610 = _T_609 | finish; // @[el2_exu_div_ctl.scala 160:44] + reg finish_ff; // @[el2_exu_div_ctl.scala 205:25] + wire _T_612 = ~finish; // @[el2_exu_div_ctl.scala 161:48] + wire _T_613 = _T_609 & _T_612; // @[el2_exu_div_ctl.scala 161:46] + wire _T_616 = run_state & _T_612; // @[el2_exu_div_ctl.scala 162:35] + wire _T_618 = _T_616 & _T; // @[el2_exu_div_ctl.scala 162:45] + wire _T_619 = ~shortq_enable; // @[el2_exu_div_ctl.scala 162:60] + wire _T_620 = _T_618 & _T_619; // @[el2_exu_div_ctl.scala 162:58] + wire [5:0] _T_622 = _T_620 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] + wire [5:0] _T_623 = {1'h0,shortq_shift_ff}; // @[Cat.scala 29:58] + wire [5:0] _T_625 = count + _T_623; // @[el2_exu_div_ctl.scala 162:86] + wire [5:0] _T_627 = _T_625 + 6'h1; // @[el2_exu_div_ctl.scala 162:113] + wire _T_631 = ~io_dp_unsign; // @[el2_exu_div_ctl.scala 166:20] + wire _T_632 = io_divisor != 32'h0; // @[el2_exu_div_ctl.scala 166:48] + wire sign_eff = _T_631 & _T_632; // @[el2_exu_div_ctl.scala 166:34] + wire _T_633 = ~run_state; // @[el2_exu_div_ctl.scala 170:6] + wire [32:0] _T_635 = {1'h0,io_dividend}; // @[Cat.scala 29:58] + reg shortq_enable_ff; // @[el2_exu_div_ctl.scala 214:32] + wire _T_636 = valid_ff_x | shortq_enable_ff; // @[el2_exu_div_ctl.scala 171:30] + wire _T_637 = run_state & _T_636; // @[el2_exu_div_ctl.scala 171:16] + reg dividend_neg_ff; // @[Reg.scala 27:20] + wire _T_660 = sign_ff & dividend_neg_ff; // @[el2_exu_div_ctl.scala 175:32] + wire _T_845 = |q_ff[30:0]; // @[el2_lib.scala 543:35] + wire _T_847 = ~q_ff[31]; // @[el2_lib.scala 543:40] + wire _T_849 = _T_845 ? _T_847 : q_ff[31]; // @[el2_lib.scala 543:23] + wire _T_839 = |q_ff[29:0]; // @[el2_lib.scala 543:35] + wire _T_841 = ~q_ff[30]; // @[el2_lib.scala 543:40] + wire _T_843 = _T_839 ? _T_841 : q_ff[30]; // @[el2_lib.scala 543:23] + wire _T_833 = |q_ff[28:0]; // @[el2_lib.scala 543:35] + wire _T_835 = ~q_ff[29]; // @[el2_lib.scala 543:40] + wire _T_837 = _T_833 ? _T_835 : q_ff[29]; // @[el2_lib.scala 543:23] + wire _T_827 = |q_ff[27:0]; // @[el2_lib.scala 543:35] + wire _T_829 = ~q_ff[28]; // @[el2_lib.scala 543:40] + wire _T_831 = _T_827 ? _T_829 : q_ff[28]; // @[el2_lib.scala 543:23] + wire _T_821 = |q_ff[26:0]; // @[el2_lib.scala 543:35] + wire _T_823 = ~q_ff[27]; // @[el2_lib.scala 543:40] + wire _T_825 = _T_821 ? _T_823 : q_ff[27]; // @[el2_lib.scala 543:23] + wire _T_815 = |q_ff[25:0]; // @[el2_lib.scala 543:35] + wire _T_817 = ~q_ff[26]; // @[el2_lib.scala 543:40] + wire _T_819 = _T_815 ? _T_817 : q_ff[26]; // @[el2_lib.scala 543:23] + wire _T_809 = |q_ff[24:0]; // @[el2_lib.scala 543:35] + wire _T_811 = ~q_ff[25]; // @[el2_lib.scala 543:40] + wire _T_813 = _T_809 ? _T_811 : q_ff[25]; // @[el2_lib.scala 543:23] + wire _T_803 = |q_ff[23:0]; // @[el2_lib.scala 543:35] + wire _T_805 = ~q_ff[24]; // @[el2_lib.scala 543:40] + wire _T_807 = _T_803 ? _T_805 : q_ff[24]; // @[el2_lib.scala 543:23] + wire _T_797 = |q_ff[22:0]; // @[el2_lib.scala 543:35] + wire _T_799 = ~q_ff[23]; // @[el2_lib.scala 543:40] + wire _T_801 = _T_797 ? _T_799 : q_ff[23]; // @[el2_lib.scala 543:23] + wire _T_791 = |q_ff[21:0]; // @[el2_lib.scala 543:35] + wire _T_793 = ~q_ff[22]; // @[el2_lib.scala 543:40] + wire _T_795 = _T_791 ? _T_793 : q_ff[22]; // @[el2_lib.scala 543:23] + wire _T_785 = |q_ff[20:0]; // @[el2_lib.scala 543:35] + wire _T_787 = ~q_ff[21]; // @[el2_lib.scala 543:40] + wire _T_789 = _T_785 ? _T_787 : q_ff[21]; // @[el2_lib.scala 543:23] + wire _T_779 = |q_ff[19:0]; // @[el2_lib.scala 543:35] + wire _T_781 = ~q_ff[20]; // @[el2_lib.scala 543:40] + wire _T_783 = _T_779 ? _T_781 : q_ff[20]; // @[el2_lib.scala 543:23] + wire _T_773 = |q_ff[18:0]; // @[el2_lib.scala 543:35] + wire _T_775 = ~q_ff[19]; // @[el2_lib.scala 543:40] + wire _T_777 = _T_773 ? _T_775 : q_ff[19]; // @[el2_lib.scala 543:23] + wire _T_767 = |q_ff[17:0]; // @[el2_lib.scala 543:35] + wire _T_769 = ~q_ff[18]; // @[el2_lib.scala 543:40] + wire _T_771 = _T_767 ? _T_769 : q_ff[18]; // @[el2_lib.scala 543:23] + wire _T_761 = |q_ff[16:0]; // @[el2_lib.scala 543:35] + wire _T_763 = ~q_ff[17]; // @[el2_lib.scala 543:40] + wire _T_765 = _T_761 ? _T_763 : q_ff[17]; // @[el2_lib.scala 543:23] + wire _T_755 = |q_ff[15:0]; // @[el2_lib.scala 543:35] + wire _T_757 = ~q_ff[16]; // @[el2_lib.scala 543:40] + wire _T_759 = _T_755 ? _T_757 : q_ff[16]; // @[el2_lib.scala 543:23] + wire [7:0] _T_870 = {_T_801,_T_795,_T_789,_T_783,_T_777,_T_771,_T_765,_T_759}; // @[el2_lib.scala 545:14] + wire _T_749 = |q_ff[14:0]; // @[el2_lib.scala 543:35] + wire _T_751 = ~q_ff[15]; // @[el2_lib.scala 543:40] + wire _T_753 = _T_749 ? _T_751 : q_ff[15]; // @[el2_lib.scala 543:23] + wire _T_743 = |q_ff[13:0]; // @[el2_lib.scala 543:35] + wire _T_745 = ~q_ff[14]; // @[el2_lib.scala 543:40] + wire _T_747 = _T_743 ? _T_745 : q_ff[14]; // @[el2_lib.scala 543:23] + wire _T_737 = |q_ff[12:0]; // @[el2_lib.scala 543:35] + wire _T_739 = ~q_ff[13]; // @[el2_lib.scala 543:40] + wire _T_741 = _T_737 ? _T_739 : q_ff[13]; // @[el2_lib.scala 543:23] + wire _T_731 = |q_ff[11:0]; // @[el2_lib.scala 543:35] + wire _T_733 = ~q_ff[12]; // @[el2_lib.scala 543:40] + wire _T_735 = _T_731 ? _T_733 : q_ff[12]; // @[el2_lib.scala 543:23] + wire _T_725 = |q_ff[10:0]; // @[el2_lib.scala 543:35] + wire _T_727 = ~q_ff[11]; // @[el2_lib.scala 543:40] + wire _T_729 = _T_725 ? _T_727 : q_ff[11]; // @[el2_lib.scala 543:23] + wire _T_719 = |q_ff[9:0]; // @[el2_lib.scala 543:35] + wire _T_721 = ~q_ff[10]; // @[el2_lib.scala 543:40] + wire _T_723 = _T_719 ? _T_721 : q_ff[10]; // @[el2_lib.scala 543:23] + wire _T_713 = |q_ff[8:0]; // @[el2_lib.scala 543:35] + wire _T_715 = ~q_ff[9]; // @[el2_lib.scala 543:40] + wire _T_717 = _T_713 ? _T_715 : q_ff[9]; // @[el2_lib.scala 543:23] + wire _T_707 = |q_ff[7:0]; // @[el2_lib.scala 543:35] + wire _T_709 = ~q_ff[8]; // @[el2_lib.scala 543:40] + wire _T_711 = _T_707 ? _T_709 : q_ff[8]; // @[el2_lib.scala 543:23] + wire _T_701 = |q_ff[6:0]; // @[el2_lib.scala 543:35] + wire _T_703 = ~q_ff[7]; // @[el2_lib.scala 543:40] + wire _T_705 = _T_701 ? _T_703 : q_ff[7]; // @[el2_lib.scala 543:23] + wire _T_695 = |q_ff[5:0]; // @[el2_lib.scala 543:35] + wire _T_697 = ~q_ff[6]; // @[el2_lib.scala 543:40] + wire _T_699 = _T_695 ? _T_697 : q_ff[6]; // @[el2_lib.scala 543:23] + wire _T_689 = |q_ff[4:0]; // @[el2_lib.scala 543:35] + wire _T_691 = ~q_ff[5]; // @[el2_lib.scala 543:40] + wire _T_693 = _T_689 ? _T_691 : q_ff[5]; // @[el2_lib.scala 543:23] + wire _T_683 = |q_ff[3:0]; // @[el2_lib.scala 543:35] + wire _T_685 = ~q_ff[4]; // @[el2_lib.scala 543:40] + wire _T_687 = _T_683 ? _T_685 : q_ff[4]; // @[el2_lib.scala 543:23] + wire _T_677 = |q_ff[2:0]; // @[el2_lib.scala 543:35] + wire _T_679 = ~q_ff[3]; // @[el2_lib.scala 543:40] + wire _T_681 = _T_677 ? _T_679 : q_ff[3]; // @[el2_lib.scala 543:23] + wire _T_671 = |q_ff[1:0]; // @[el2_lib.scala 543:35] + wire _T_673 = ~q_ff[2]; // @[el2_lib.scala 543:40] + wire _T_675 = _T_671 ? _T_673 : q_ff[2]; // @[el2_lib.scala 543:23] + wire _T_665 = |q_ff[0]; // @[el2_lib.scala 543:35] + wire _T_667 = ~q_ff[1]; // @[el2_lib.scala 543:40] + wire _T_669 = _T_665 ? _T_667 : q_ff[1]; // @[el2_lib.scala 543:23] + wire [6:0] _T_855 = {_T_705,_T_699,_T_693,_T_687,_T_681,_T_675,_T_669}; // @[el2_lib.scala 545:14] + wire [14:0] _T_863 = {_T_753,_T_747,_T_741,_T_735,_T_729,_T_723,_T_717,_T_711,_T_855}; // @[el2_lib.scala 545:14] + wire [30:0] _T_879 = {_T_849,_T_843,_T_837,_T_831,_T_825,_T_819,_T_813,_T_807,_T_870,_T_863}; // @[el2_lib.scala 545:14] + wire [31:0] _T_881 = {_T_879,q_ff[0]}; // @[Cat.scala 29:58] + wire [31:0] dividend_eff = _T_660 ? _T_881 : q_ff[31:0]; // @[el2_exu_div_ctl.scala 175:22] + wire [32:0] _T_917 = run_state ? 33'h1ffffffff : 33'h0; // @[Bitwise.scala 72:12] + wire _T_929 = _T_607 & rem_ff; // @[el2_exu_div_ctl.scala 191:41] + reg [32:0] a_ff; // @[el2_lib.scala 514:16] + wire rem_correct = _T_929 & a_ff[32]; // @[el2_exu_div_ctl.scala 191:50] + wire [32:0] _T_902 = rem_correct ? a_ff : 33'h0; // @[Mux.scala 27:72] + wire _T_890 = ~rem_correct; // @[el2_exu_div_ctl.scala 182:6] + wire _T_891 = ~shortq_enable_ff; // @[el2_exu_div_ctl.scala 182:21] + wire _T_892 = _T_890 & _T_891; // @[el2_exu_div_ctl.scala 182:19] + wire [32:0] _T_896 = {a_ff[31:0],q_ff[32]}; // @[Cat.scala 29:58] + wire [32:0] _T_903 = _T_892 ? _T_896 : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_905 = _T_902 | _T_903; // @[Mux.scala 27:72] + wire _T_898 = _T_890 & shortq_enable_ff; // @[el2_exu_div_ctl.scala 183:19] + wire [55:0] _T_887 = {24'h0,dividend_eff}; // @[Cat.scala 29:58] + wire [86:0] _GEN_5 = {{31'd0}, _T_887}; // @[el2_exu_div_ctl.scala 179:47] + wire [86:0] _T_888 = _GEN_5 << shortq_shift_ff; // @[el2_exu_div_ctl.scala 179:47] + wire [55:0] a_eff_shift = _T_888[55:0]; // @[el2_exu_div_ctl.scala 179:15] + wire [32:0] _T_901 = {9'h0,a_eff_shift[55:32]}; // @[Cat.scala 29:58] + wire [32:0] _T_904 = _T_898 ? _T_901 : 33'h0; // @[Mux.scala 27:72] + wire [32:0] a_eff = _T_905 | _T_904; // @[Mux.scala 27:72] + wire [32:0] a_shift = _T_917 & a_eff; // @[el2_exu_div_ctl.scala 186:33] + wire _T_926 = a_ff[32] | rem_correct; // @[el2_exu_div_ctl.scala 190:21] + reg divisor_neg_ff; // @[Reg.scala 27:20] + wire m_already_comp = divisor_neg_ff & sign_ff; // @[el2_exu_div_ctl.scala 188:48] + wire add = _T_926 ^ m_already_comp; // @[el2_exu_div_ctl.scala 190:36] + wire [32:0] _T_885 = ~m_ff; // @[el2_exu_div_ctl.scala 178:35] + wire [32:0] m_eff = add ? m_ff : _T_885; // @[el2_exu_div_ctl.scala 178:15] + wire [32:0] _T_919 = a_shift + m_eff; // @[el2_exu_div_ctl.scala 187:41] + wire _T_920 = ~add; // @[el2_exu_div_ctl.scala 187:65] + wire [32:0] _T_921 = {32'h0,_T_920}; // @[Cat.scala 29:58] + wire [32:0] _T_923 = _T_919 + _T_921; // @[el2_exu_div_ctl.scala 187:49] + wire [32:0] a_in = _T_917 & _T_923; // @[el2_exu_div_ctl.scala 187:30] + wire _T_641 = ~a_in[32]; // @[el2_exu_div_ctl.scala 171:85] + wire [32:0] _T_642 = {dividend_eff,_T_641}; // @[Cat.scala 29:58] + wire [63:0] _GEN_6 = {{31'd0}, _T_642}; // @[el2_exu_div_ctl.scala 171:96] + wire [63:0] _T_643 = _GEN_6 << shortq_shift_ff; // @[el2_exu_div_ctl.scala 171:96] + wire _T_645 = ~_T_636; // @[el2_exu_div_ctl.scala 172:18] + wire _T_646 = run_state & _T_645; // @[el2_exu_div_ctl.scala 172:16] + wire [32:0] _T_651 = {q_ff[31:0],_T_641}; // @[Cat.scala 29:58] + wire [32:0] _T_652 = _T_633 ? _T_635 : 33'h0; // @[Mux.scala 27:72] + wire [63:0] _T_653 = _T_637 ? _T_643 : 64'h0; // @[Mux.scala 27:72] + wire [32:0] _T_654 = _T_646 ? _T_651 : 33'h0; // @[Mux.scala 27:72] + wire [63:0] _GEN_7 = {{31'd0}, _T_652}; // @[Mux.scala 27:72] + wire [63:0] _T_655 = _GEN_7 | _T_653; // @[Mux.scala 27:72] + wire [63:0] _GEN_8 = {{31'd0}, _T_654}; // @[Mux.scala 27:72] + wire [63:0] _T_656 = _T_655 | _GEN_8; // @[Mux.scala 27:72] + wire _T_659 = run_state & _T_619; // @[el2_exu_div_ctl.scala 174:48] + wire _T_910 = count != 6'h21; // @[el2_exu_div_ctl.scala 185:73] + wire _T_911 = _T_659 & _T_910; // @[el2_exu_div_ctl.scala 185:64] + wire _T_912 = io_dp_valid | _T_911; // @[el2_exu_div_ctl.scala 185:34] + wire _T_932 = dividend_neg_ff ^ divisor_neg_ff; // @[el2_exu_div_ctl.scala 192:50] + wire _T_933 = sign_ff & _T_932; // @[el2_exu_div_ctl.scala 192:31] + wire [31:0] q_ff_eff = _T_933 ? _T_881 : q_ff[31:0]; // @[el2_exu_div_ctl.scala 192:21] + wire _T_1161 = |a_ff[0]; // @[el2_lib.scala 543:35] + wire _T_1163 = ~a_ff[1]; // @[el2_lib.scala 543:40] + wire _T_1165 = _T_1161 ? _T_1163 : a_ff[1]; // @[el2_lib.scala 543:23] + wire _T_1167 = |a_ff[1:0]; // @[el2_lib.scala 543:35] + wire _T_1169 = ~a_ff[2]; // @[el2_lib.scala 543:40] + wire _T_1171 = _T_1167 ? _T_1169 : a_ff[2]; // @[el2_lib.scala 543:23] + wire _T_1173 = |a_ff[2:0]; // @[el2_lib.scala 543:35] + wire _T_1175 = ~a_ff[3]; // @[el2_lib.scala 543:40] + wire _T_1177 = _T_1173 ? _T_1175 : a_ff[3]; // @[el2_lib.scala 543:23] + wire _T_1179 = |a_ff[3:0]; // @[el2_lib.scala 543:35] + wire _T_1181 = ~a_ff[4]; // @[el2_lib.scala 543:40] + wire _T_1183 = _T_1179 ? _T_1181 : a_ff[4]; // @[el2_lib.scala 543:23] + wire _T_1185 = |a_ff[4:0]; // @[el2_lib.scala 543:35] + wire _T_1187 = ~a_ff[5]; // @[el2_lib.scala 543:40] + wire _T_1189 = _T_1185 ? _T_1187 : a_ff[5]; // @[el2_lib.scala 543:23] + wire _T_1191 = |a_ff[5:0]; // @[el2_lib.scala 543:35] + wire _T_1193 = ~a_ff[6]; // @[el2_lib.scala 543:40] + wire _T_1195 = _T_1191 ? _T_1193 : a_ff[6]; // @[el2_lib.scala 543:23] + wire _T_1197 = |a_ff[6:0]; // @[el2_lib.scala 543:35] + wire _T_1199 = ~a_ff[7]; // @[el2_lib.scala 543:40] + wire _T_1201 = _T_1197 ? _T_1199 : a_ff[7]; // @[el2_lib.scala 543:23] + wire _T_1203 = |a_ff[7:0]; // @[el2_lib.scala 543:35] + wire _T_1205 = ~a_ff[8]; // @[el2_lib.scala 543:40] + wire _T_1207 = _T_1203 ? _T_1205 : a_ff[8]; // @[el2_lib.scala 543:23] + wire _T_1209 = |a_ff[8:0]; // @[el2_lib.scala 543:35] + wire _T_1211 = ~a_ff[9]; // @[el2_lib.scala 543:40] + wire _T_1213 = _T_1209 ? _T_1211 : a_ff[9]; // @[el2_lib.scala 543:23] + wire _T_1215 = |a_ff[9:0]; // @[el2_lib.scala 543:35] + wire _T_1217 = ~a_ff[10]; // @[el2_lib.scala 543:40] + wire _T_1219 = _T_1215 ? _T_1217 : a_ff[10]; // @[el2_lib.scala 543:23] + wire _T_1221 = |a_ff[10:0]; // @[el2_lib.scala 543:35] + wire _T_1223 = ~a_ff[11]; // @[el2_lib.scala 543:40] + wire _T_1225 = _T_1221 ? _T_1223 : a_ff[11]; // @[el2_lib.scala 543:23] + wire _T_1227 = |a_ff[11:0]; // @[el2_lib.scala 543:35] + wire _T_1229 = ~a_ff[12]; // @[el2_lib.scala 543:40] + wire _T_1231 = _T_1227 ? _T_1229 : a_ff[12]; // @[el2_lib.scala 543:23] + wire _T_1233 = |a_ff[12:0]; // @[el2_lib.scala 543:35] + wire _T_1235 = ~a_ff[13]; // @[el2_lib.scala 543:40] + wire _T_1237 = _T_1233 ? _T_1235 : a_ff[13]; // @[el2_lib.scala 543:23] + wire _T_1239 = |a_ff[13:0]; // @[el2_lib.scala 543:35] + wire _T_1241 = ~a_ff[14]; // @[el2_lib.scala 543:40] + wire _T_1243 = _T_1239 ? _T_1241 : a_ff[14]; // @[el2_lib.scala 543:23] + wire _T_1245 = |a_ff[14:0]; // @[el2_lib.scala 543:35] + wire _T_1247 = ~a_ff[15]; // @[el2_lib.scala 543:40] + wire _T_1249 = _T_1245 ? _T_1247 : a_ff[15]; // @[el2_lib.scala 543:23] + wire _T_1251 = |a_ff[15:0]; // @[el2_lib.scala 543:35] + wire _T_1253 = ~a_ff[16]; // @[el2_lib.scala 543:40] + wire _T_1255 = _T_1251 ? _T_1253 : a_ff[16]; // @[el2_lib.scala 543:23] + wire _T_1257 = |a_ff[16:0]; // @[el2_lib.scala 543:35] + wire _T_1259 = ~a_ff[17]; // @[el2_lib.scala 543:40] + wire _T_1261 = _T_1257 ? _T_1259 : a_ff[17]; // @[el2_lib.scala 543:23] + wire _T_1263 = |a_ff[17:0]; // @[el2_lib.scala 543:35] + wire _T_1265 = ~a_ff[18]; // @[el2_lib.scala 543:40] + wire _T_1267 = _T_1263 ? _T_1265 : a_ff[18]; // @[el2_lib.scala 543:23] + wire _T_1269 = |a_ff[18:0]; // @[el2_lib.scala 543:35] + wire _T_1271 = ~a_ff[19]; // @[el2_lib.scala 543:40] + wire _T_1273 = _T_1269 ? _T_1271 : a_ff[19]; // @[el2_lib.scala 543:23] + wire _T_1275 = |a_ff[19:0]; // @[el2_lib.scala 543:35] + wire _T_1277 = ~a_ff[20]; // @[el2_lib.scala 543:40] + wire _T_1279 = _T_1275 ? _T_1277 : a_ff[20]; // @[el2_lib.scala 543:23] + wire _T_1281 = |a_ff[20:0]; // @[el2_lib.scala 543:35] + wire _T_1283 = ~a_ff[21]; // @[el2_lib.scala 543:40] + wire _T_1285 = _T_1281 ? _T_1283 : a_ff[21]; // @[el2_lib.scala 543:23] + wire _T_1287 = |a_ff[21:0]; // @[el2_lib.scala 543:35] + wire _T_1289 = ~a_ff[22]; // @[el2_lib.scala 543:40] + wire _T_1291 = _T_1287 ? _T_1289 : a_ff[22]; // @[el2_lib.scala 543:23] + wire _T_1293 = |a_ff[22:0]; // @[el2_lib.scala 543:35] + wire _T_1295 = ~a_ff[23]; // @[el2_lib.scala 543:40] + wire _T_1297 = _T_1293 ? _T_1295 : a_ff[23]; // @[el2_lib.scala 543:23] + wire _T_1299 = |a_ff[23:0]; // @[el2_lib.scala 543:35] + wire _T_1301 = ~a_ff[24]; // @[el2_lib.scala 543:40] + wire _T_1303 = _T_1299 ? _T_1301 : a_ff[24]; // @[el2_lib.scala 543:23] + wire _T_1305 = |a_ff[24:0]; // @[el2_lib.scala 543:35] + wire _T_1307 = ~a_ff[25]; // @[el2_lib.scala 543:40] + wire _T_1309 = _T_1305 ? _T_1307 : a_ff[25]; // @[el2_lib.scala 543:23] + wire _T_1311 = |a_ff[25:0]; // @[el2_lib.scala 543:35] + wire _T_1313 = ~a_ff[26]; // @[el2_lib.scala 543:40] + wire _T_1315 = _T_1311 ? _T_1313 : a_ff[26]; // @[el2_lib.scala 543:23] + wire _T_1317 = |a_ff[26:0]; // @[el2_lib.scala 543:35] + wire _T_1319 = ~a_ff[27]; // @[el2_lib.scala 543:40] + wire _T_1321 = _T_1317 ? _T_1319 : a_ff[27]; // @[el2_lib.scala 543:23] + wire _T_1323 = |a_ff[27:0]; // @[el2_lib.scala 543:35] + wire _T_1325 = ~a_ff[28]; // @[el2_lib.scala 543:40] + wire _T_1327 = _T_1323 ? _T_1325 : a_ff[28]; // @[el2_lib.scala 543:23] + wire _T_1329 = |a_ff[28:0]; // @[el2_lib.scala 543:35] + wire _T_1331 = ~a_ff[29]; // @[el2_lib.scala 543:40] + wire _T_1333 = _T_1329 ? _T_1331 : a_ff[29]; // @[el2_lib.scala 543:23] + wire _T_1335 = |a_ff[29:0]; // @[el2_lib.scala 543:35] + wire _T_1337 = ~a_ff[30]; // @[el2_lib.scala 543:40] + wire _T_1339 = _T_1335 ? _T_1337 : a_ff[30]; // @[el2_lib.scala 543:23] + wire _T_1341 = |a_ff[30:0]; // @[el2_lib.scala 543:35] + wire _T_1343 = ~a_ff[31]; // @[el2_lib.scala 543:40] + wire _T_1345 = _T_1341 ? _T_1343 : a_ff[31]; // @[el2_lib.scala 543:23] + wire [6:0] _T_1351 = {_T_1201,_T_1195,_T_1189,_T_1183,_T_1177,_T_1171,_T_1165}; // @[el2_lib.scala 545:14] + wire [14:0] _T_1359 = {_T_1249,_T_1243,_T_1237,_T_1231,_T_1225,_T_1219,_T_1213,_T_1207,_T_1351}; // @[el2_lib.scala 545:14] + wire [7:0] _T_1366 = {_T_1297,_T_1291,_T_1285,_T_1279,_T_1273,_T_1267,_T_1261,_T_1255}; // @[el2_lib.scala 545:14] + wire [30:0] _T_1375 = {_T_1345,_T_1339,_T_1333,_T_1327,_T_1321,_T_1315,_T_1309,_T_1303,_T_1366,_T_1359}; // @[el2_lib.scala 545:14] + wire [31:0] _T_1377 = {_T_1375,a_ff[0]}; // @[Cat.scala 29:58] + wire [31:0] a_ff_eff = _T_660 ? _T_1377 : a_ff[31:0]; // @[el2_exu_div_ctl.scala 193:21] + reg smallnum_case_ff; // @[el2_exu_div_ctl.scala 212:32] + reg [3:0] smallnum_ff; // @[el2_exu_div_ctl.scala 213:27] + wire [31:0] _T_1380 = {28'h0,smallnum_ff}; // @[Cat.scala 29:58] + wire _T_1382 = ~smallnum_case_ff; // @[el2_exu_div_ctl.scala 198:6] + wire _T_1384 = _T_1382 & _T_9; // @[el2_exu_div_ctl.scala 198:24] + wire [31:0] _T_1386 = smallnum_case_ff ? _T_1380 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1387 = rem_ff ? a_ff_eff : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1388 = _T_1384 ? q_ff_eff : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1389 = _T_1386 | _T_1387; // @[Mux.scala 27:72] + wire _T_1421 = _T_631 & io_divisor[31]; // @[el2_exu_div_ctl.scala 219:36] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + assign io_out = _T_1389 | _T_1388; // @[el2_exu_div_ctl.scala 50:10 el2_exu_div_ctl.scala 195:10] + assign io_finish_dly = finish_ff & _T; // @[el2_exu_div_ctl.scala 51:17 el2_exu_div_ctl.scala 165:18] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_io_en = _T_610 | finish_ff; // @[el2_lib.scala 485:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = io_dp_valid | _T_659; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_2_io_en = _T_912 | rem_correct; // @[el2_lib.scala 511:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_3_io_en = io_dp_valid; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + valid_ff_x = _RAND_0[0:0]; + _RAND_1 = {2{`RANDOM}}; + q_ff = _RAND_1[32:0]; + _RAND_2 = {2{`RANDOM}}; + m_ff = _RAND_2[32:0]; + _RAND_3 = {1{`RANDOM}}; + rem_ff = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + sign_ff = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + shortq_shift_xx = _RAND_5[3:0]; + _RAND_6 = {1{`RANDOM}}; + count = _RAND_6[5:0]; + _RAND_7 = {1{`RANDOM}}; + run_state = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + finish_ff = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + shortq_enable_ff = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + dividend_neg_ff = _RAND_10[0:0]; + _RAND_11 = {2{`RANDOM}}; + a_ff = _RAND_11[32:0]; + _RAND_12 = {1{`RANDOM}}; + divisor_neg_ff = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + smallnum_case_ff = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + smallnum_ff = _RAND_14[3:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + valid_ff_x = 1'h0; + end + if (reset) begin + q_ff = 33'h0; + end + if (reset) begin + m_ff = 33'h0; + end + if (reset) begin + rem_ff = 1'h0; + end + if (reset) begin + sign_ff = 1'h0; + end + if (reset) begin + shortq_shift_xx = 4'h0; + end + if (reset) begin + count = 6'h0; + end + if (reset) begin + run_state = 1'h0; + end + if (reset) begin + finish_ff = 1'h0; + end + if (reset) begin + shortq_enable_ff = 1'h0; + end + if (reset) begin + dividend_neg_ff = 1'h0; + end + if (reset) begin + a_ff = 33'h0; + end + if (reset) begin + divisor_neg_ff = 1'h0; + end + if (reset) begin + smallnum_case_ff = 1'h0; + end + if (reset) begin + smallnum_ff = 4'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + valid_ff_x <= 1'h0; + end else begin + valid_ff_x <= io_dp_valid & _T; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + q_ff <= 33'h0; + end else begin + q_ff <= _T_656[32:0]; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + m_ff <= 33'h0; + end else begin + m_ff <= {_T_1421,io_divisor}; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + rem_ff <= 1'h0; + end else if (io_dp_valid) begin + rem_ff <= io_dp_rem; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + sign_ff <= 1'h0; + end else if (io_dp_valid) begin + sign_ff <= sign_eff; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + shortq_shift_xx <= 4'h0; + end else begin + shortq_shift_xx <= _T_589 & shortq_raw; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + count <= 6'h0; + end else begin + count <= _T_622 & _T_627; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + run_state <= 1'h0; + end else begin + run_state <= _T_613 & _T; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + finish_ff <= 1'h0; + end else begin + finish_ff <= finish & _T; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + shortq_enable_ff <= 1'h0; + end else begin + shortq_enable_ff <= _T_586 & _T_587; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + dividend_neg_ff <= 1'h0; + end else if (io_dp_valid) begin + dividend_neg_ff <= io_dividend[31]; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + a_ff <= 33'h0; + end else begin + a_ff <= _T_917 & _T_923; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + divisor_neg_ff <= 1'h0; + end else if (io_dp_valid) begin + divisor_neg_ff <= io_divisor[31]; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + smallnum_case_ff <= 1'h0; + end else begin + smallnum_case_ff <= _T_11 | _T_19; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + smallnum_ff <= 4'h0; + end else begin + smallnum_ff <= {_T_399,_T_398}; + end + end +endmodule +module el2_exu( + input clock, + input reset, + input io_scan_mode, + input [1:0] io_dec_data_en, + input [1:0] io_dec_ctl_en, + input [31:0] io_dbg_cmd_wrdata, + input io_i0_ap_land, + input io_i0_ap_lor, + input io_i0_ap_lxor, + input io_i0_ap_sll, + input io_i0_ap_srl, + input io_i0_ap_sra, + input io_i0_ap_beq, + input io_i0_ap_bne, + input io_i0_ap_blt, + input io_i0_ap_bge, + input io_i0_ap_add, + input io_i0_ap_sub, + input io_i0_ap_slt, + input io_i0_ap_unsign, + input io_i0_ap_jal, + input io_i0_ap_predict_t, + input io_i0_ap_predict_nt, + input io_i0_ap_csr_write, + input io_i0_ap_csr_imm, + input io_dec_debug_wdata_rs1_d, + input io_dec_i0_predict_p_d_misp, + input io_dec_i0_predict_p_d_ataken, + input io_dec_i0_predict_p_d_boffset, + input io_dec_i0_predict_p_d_pc4, + input [1:0] io_dec_i0_predict_p_d_hist, + input [11:0] io_dec_i0_predict_p_d_toffset, + input io_dec_i0_predict_p_d_valid, + input io_dec_i0_predict_p_d_br_error, + input io_dec_i0_predict_p_d_br_start_error, + input [30:0] io_dec_i0_predict_p_d_prett, + input io_dec_i0_predict_p_d_pcall, + input io_dec_i0_predict_p_d_pret, + input io_dec_i0_predict_p_d_pja, + input io_dec_i0_predict_p_d_way, + input [7:0] io_i0_predict_fghr_d, + input [7:0] io_i0_predict_index_d, + input [4:0] io_i0_predict_btag_d, + input io_dec_i0_rs1_en_d, + input io_dec_i0_rs2_en_d, + input [31:0] io_gpr_i0_rs1_d, + input [31:0] io_gpr_i0_rs2_d, + input [31:0] io_dec_i0_immed_d, + input [31:0] io_dec_i0_rs1_bypass_data_d, + input [31:0] io_dec_i0_rs2_bypass_data_d, + input [11:0] io_dec_i0_br_immed_d, + input io_dec_i0_alu_decode_d, + input io_dec_i0_select_pc_d, + input [30:0] io_dec_i0_pc_d, + input [1:0] io_dec_i0_rs1_bypass_en_d, + input [1:0] io_dec_i0_rs2_bypass_en_d, + input io_dec_csr_ren_d, + input io_mul_p_valid, + input io_mul_p_rs1_sign, + input io_mul_p_rs2_sign, + input io_mul_p_low, + input io_mul_p_bext, + input io_mul_p_bdep, + input io_mul_p_clmul, + input io_mul_p_clmulh, + input io_mul_p_clmulr, + input io_mul_p_grev, + input io_mul_p_shfl, + input io_mul_p_unshfl, + input io_mul_p_crc32_b, + input io_mul_p_crc32_h, + input io_mul_p_crc32_w, + input io_mul_p_crc32c_b, + input io_mul_p_crc32c_h, + input io_mul_p_crc32c_w, + input io_mul_p_bfp, + input io_div_p_valid, + input io_div_p_unsign, + input io_div_p_rem, + input io_dec_div_cancel, + input [30:0] io_pred_correct_npc_x, + input io_dec_tlu_flush_lower_r, + input [30:0] io_dec_tlu_flush_path_r, + input io_dec_extint_stall, + input [29:0] io_dec_tlu_meihap, + output [31:0] io_exu_lsu_rs1_d, + output [31:0] io_exu_lsu_rs2_d, + output io_exu_flush_final, + output [30:0] io_exu_flush_path_final, + output [31:0] io_exu_i0_result_x, + output [30:0] io_exu_i0_pc_x, + output [31:0] io_exu_csr_rs1_x, + output [30:0] io_exu_npc_r, + output [1:0] io_exu_i0_br_hist_r, + output io_exu_i0_br_error_r, + output io_exu_i0_br_start_error_r, + output [7:0] io_exu_i0_br_index_r, + output io_exu_i0_br_valid_r, + output io_exu_i0_br_mp_r, + output io_exu_i0_br_middle_r, + output [7:0] io_exu_i0_br_fghr_r, + output io_exu_i0_br_way_r, + output io_exu_mp_pkt_misp, + output io_exu_mp_pkt_ataken, + output io_exu_mp_pkt_boffset, + output io_exu_mp_pkt_pc4, + output [1:0] io_exu_mp_pkt_hist, + output [11:0] io_exu_mp_pkt_toffset, + output io_exu_mp_pkt_valid, + output io_exu_mp_pkt_br_error, + output io_exu_mp_pkt_br_start_error, + output [30:0] io_exu_mp_pkt_prett, + output io_exu_mp_pkt_pcall, + output io_exu_mp_pkt_pret, + output io_exu_mp_pkt_pja, + output io_exu_mp_pkt_way, + output [7:0] io_exu_mp_eghr, + output [7:0] io_exu_mp_fghr, + output [7:0] io_exu_mp_index, + output [4:0] io_exu_mp_btag, + output io_exu_pmu_i0_br_misp, + output io_exu_pmu_i0_br_ataken, + output io_exu_pmu_i0_pc4, + output [31:0] io_exu_div_result, + output io_exu_div_wren +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 518:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 518:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_10_io_clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_10_io_en; // @[el2_lib.scala 518:23] + wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 518:23] + wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 508:23] + wire i_alu_clock; // @[el2_exu.scala 120:19] + wire i_alu_reset; // @[el2_exu.scala 120:19] + wire i_alu_io_scan_mode; // @[el2_exu.scala 120:19] + wire i_alu_io_flush_upper_x; // @[el2_exu.scala 120:19] + wire i_alu_io_flush_lower_r; // @[el2_exu.scala 120:19] + wire i_alu_io_enable; // @[el2_exu.scala 120:19] + wire i_alu_io_valid_in; // @[el2_exu.scala 120:19] + wire i_alu_io_ap_land; // @[el2_exu.scala 120:19] + wire i_alu_io_ap_lor; // @[el2_exu.scala 120:19] + wire i_alu_io_ap_lxor; // @[el2_exu.scala 120:19] + wire i_alu_io_ap_sll; // @[el2_exu.scala 120:19] + wire i_alu_io_ap_srl; // @[el2_exu.scala 120:19] + wire i_alu_io_ap_sra; // @[el2_exu.scala 120:19] + wire i_alu_io_ap_beq; // @[el2_exu.scala 120:19] + wire i_alu_io_ap_bne; // @[el2_exu.scala 120:19] + wire i_alu_io_ap_blt; // @[el2_exu.scala 120:19] + wire i_alu_io_ap_bge; // @[el2_exu.scala 120:19] + wire i_alu_io_ap_add; // @[el2_exu.scala 120:19] + wire i_alu_io_ap_sub; // @[el2_exu.scala 120:19] + wire i_alu_io_ap_slt; // @[el2_exu.scala 120:19] + wire i_alu_io_ap_unsign; // @[el2_exu.scala 120:19] + wire i_alu_io_ap_jal; // @[el2_exu.scala 120:19] + wire i_alu_io_ap_predict_t; // @[el2_exu.scala 120:19] + wire i_alu_io_ap_predict_nt; // @[el2_exu.scala 120:19] + wire i_alu_io_ap_csr_write; // @[el2_exu.scala 120:19] + wire i_alu_io_ap_csr_imm; // @[el2_exu.scala 120:19] + wire i_alu_io_csr_ren_in; // @[el2_exu.scala 120:19] + wire [31:0] i_alu_io_a_in; // @[el2_exu.scala 120:19] + wire [31:0] i_alu_io_b_in; // @[el2_exu.scala 120:19] + wire [30:0] i_alu_io_pc_in; // @[el2_exu.scala 120:19] + wire i_alu_io_pp_in_boffset; // @[el2_exu.scala 120:19] + wire i_alu_io_pp_in_pc4; // @[el2_exu.scala 120:19] + wire [1:0] i_alu_io_pp_in_hist; // @[el2_exu.scala 120:19] + wire [11:0] i_alu_io_pp_in_toffset; // @[el2_exu.scala 120:19] + wire i_alu_io_pp_in_valid; // @[el2_exu.scala 120:19] + wire i_alu_io_pp_in_br_error; // @[el2_exu.scala 120:19] + wire i_alu_io_pp_in_br_start_error; // @[el2_exu.scala 120:19] + wire [30:0] i_alu_io_pp_in_prett; // @[el2_exu.scala 120:19] + wire i_alu_io_pp_in_pcall; // @[el2_exu.scala 120:19] + wire i_alu_io_pp_in_pret; // @[el2_exu.scala 120:19] + wire i_alu_io_pp_in_pja; // @[el2_exu.scala 120:19] + wire i_alu_io_pp_in_way; // @[el2_exu.scala 120:19] + wire [11:0] i_alu_io_brimm_in; // @[el2_exu.scala 120:19] + wire [31:0] i_alu_io_result_ff; // @[el2_exu.scala 120:19] + wire i_alu_io_flush_upper_out; // @[el2_exu.scala 120:19] + wire i_alu_io_flush_final_out; // @[el2_exu.scala 120:19] + wire [30:0] i_alu_io_flush_path_out; // @[el2_exu.scala 120:19] + wire [30:0] i_alu_io_pc_ff; // @[el2_exu.scala 120:19] + wire i_alu_io_pred_correct_out; // @[el2_exu.scala 120:19] + wire i_alu_io_predict_p_out_misp; // @[el2_exu.scala 120:19] + wire i_alu_io_predict_p_out_ataken; // @[el2_exu.scala 120:19] + wire i_alu_io_predict_p_out_boffset; // @[el2_exu.scala 120:19] + wire i_alu_io_predict_p_out_pc4; // @[el2_exu.scala 120:19] + wire [1:0] i_alu_io_predict_p_out_hist; // @[el2_exu.scala 120:19] + wire [11:0] i_alu_io_predict_p_out_toffset; // @[el2_exu.scala 120:19] + wire i_alu_io_predict_p_out_valid; // @[el2_exu.scala 120:19] + wire i_alu_io_predict_p_out_br_error; // @[el2_exu.scala 120:19] + wire i_alu_io_predict_p_out_br_start_error; // @[el2_exu.scala 120:19] + wire i_alu_io_predict_p_out_pcall; // @[el2_exu.scala 120:19] + wire i_alu_io_predict_p_out_pret; // @[el2_exu.scala 120:19] + wire i_alu_io_predict_p_out_pja; // @[el2_exu.scala 120:19] + wire i_alu_io_predict_p_out_way; // @[el2_exu.scala 120:19] + wire i_mul_clock; // @[el2_exu.scala 141:19] + wire i_mul_reset; // @[el2_exu.scala 141:19] + wire i_mul_io_scan_mode; // @[el2_exu.scala 141:19] + wire i_mul_io_mul_p_valid; // @[el2_exu.scala 141:19] + wire i_mul_io_mul_p_rs1_sign; // @[el2_exu.scala 141:19] + wire i_mul_io_mul_p_rs2_sign; // @[el2_exu.scala 141:19] + wire i_mul_io_mul_p_low; // @[el2_exu.scala 141:19] + wire [31:0] i_mul_io_rs1_in; // @[el2_exu.scala 141:19] + wire [31:0] i_mul_io_rs2_in; // @[el2_exu.scala 141:19] + wire [31:0] i_mul_io_result_x; // @[el2_exu.scala 141:19] + wire i_div_clock; // @[el2_exu.scala 148:19] + wire i_div_reset; // @[el2_exu.scala 148:19] + wire i_div_io_scan_mode; // @[el2_exu.scala 148:19] + wire i_div_io_dp_valid; // @[el2_exu.scala 148:19] + wire i_div_io_dp_unsign; // @[el2_exu.scala 148:19] + wire i_div_io_dp_rem; // @[el2_exu.scala 148:19] + wire [31:0] i_div_io_dividend; // @[el2_exu.scala 148:19] + wire [31:0] i_div_io_divisor; // @[el2_exu.scala 148:19] + wire i_div_io_cancel; // @[el2_exu.scala 148:19] + wire [31:0] i_div_io_out; // @[el2_exu.scala 148:19] + wire i_div_io_finish_dly; // @[el2_exu.scala 148:19] + wire [15:0] _T = {io_i0_predict_fghr_d,io_i0_predict_index_d}; // @[Cat.scala 29:58] + reg [31:0] i0_flush_path_x; // @[el2_lib.scala 514:16] + reg [31:0] _T_3; // @[el2_lib.scala 514:16] + reg i0_predict_p_x_misp; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_ataken; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_boffset; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_pc4; // @[el2_lib.scala 524:16] + reg [1:0] i0_predict_p_x_hist; // @[el2_lib.scala 524:16] + reg [11:0] i0_predict_p_x_toffset; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_valid; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_br_error; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_br_start_error; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_pcall; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_pret; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_pja; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_way; // @[el2_lib.scala 524:16] + reg [20:0] predpipe_x; // @[el2_lib.scala 514:16] + reg [20:0] predpipe_r; // @[el2_lib.scala 514:16] + reg [7:0] ghr_x; // @[el2_lib.scala 514:16] + reg i0_pred_correct_upper_x; // @[el2_lib.scala 514:16] + reg i0_flush_upper_x; // @[el2_lib.scala 514:16] + reg i0_taken_x; // @[el2_lib.scala 514:16] + reg i0_valid_x; // @[el2_lib.scala 514:16] + reg i0_pp_r_misp; // @[el2_lib.scala 524:16] + reg i0_pp_r_ataken; // @[el2_lib.scala 524:16] + reg i0_pp_r_boffset; // @[el2_lib.scala 524:16] + reg i0_pp_r_pc4; // @[el2_lib.scala 524:16] + reg [1:0] i0_pp_r_hist; // @[el2_lib.scala 524:16] + reg i0_pp_r_valid; // @[el2_lib.scala 524:16] + reg i0_pp_r_br_error; // @[el2_lib.scala 524:16] + reg i0_pp_r_br_start_error; // @[el2_lib.scala 524:16] + reg i0_pp_r_way; // @[el2_lib.scala 524:16] + reg [5:0] pred_temp1; // @[el2_lib.scala 514:16] + reg i0_pred_correct_upper_r; // @[el2_lib.scala 514:16] + reg [31:0] i0_flush_path_upper_r; // @[el2_lib.scala 514:16] + reg [24:0] pred_temp2; // @[el2_lib.scala 514:16] + wire [30:0] _T_23 = {pred_temp2,pred_temp1}; // @[Cat.scala 29:58] + wire _T_149 = ~io_dec_tlu_flush_lower_r; // @[el2_exu.scala 173:6] + wire i0_predict_p_d_valid = i_alu_io_predict_p_out_valid; // @[el2_exu.scala 22:46 el2_exu.scala 137:41] + wire _T_145 = i0_predict_p_d_valid & io_dec_i0_alu_decode_d; // @[el2_exu.scala 166:54] + wire i0_valid_d = _T_145 & _T_149; // @[el2_exu.scala 166:79] + wire _T_150 = _T_149 & i0_valid_d; // @[el2_exu.scala 173:32] + reg [7:0] ghr_d; // @[el2_lib.scala 514:16] + wire i0_predict_p_d_ataken = i_alu_io_predict_p_out_ataken; // @[el2_exu.scala 22:46 el2_exu.scala 137:41] + wire i0_taken_d = i0_predict_p_d_ataken & io_dec_i0_alu_decode_d; // @[el2_exu.scala 167:54] + wire [7:0] _T_153 = {ghr_d[6:0],i0_taken_d}; // @[Cat.scala 29:58] + wire [7:0] _T_159 = _T_150 ? _T_153 : 8'h0; // @[Mux.scala 27:72] + wire _T_155 = ~i0_valid_d; // @[el2_exu.scala 174:34] + wire _T_156 = _T_149 & _T_155; // @[el2_exu.scala 174:32] + wire [7:0] _T_160 = _T_156 ? ghr_d : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_162 = _T_159 | _T_160; // @[Mux.scala 27:72] + wire [7:0] _T_161 = io_dec_tlu_flush_lower_r ? ghr_x : 8'h0; // @[Mux.scala 27:72] + wire [7:0] ghr_d_ns = _T_162 | _T_161; // @[Mux.scala 27:72] + wire _T_39 = ghr_d_ns != ghr_d; // @[el2_exu.scala 68:39] + reg mul_valid_x; // @[el2_lib.scala 514:16] + wire _T_40 = io_mul_p_valid != mul_valid_x; // @[el2_exu.scala 68:70] + wire _T_41 = _T_39 | _T_40; // @[el2_exu.scala 68:50] + reg flush_lower_ff; // @[el2_lib.scala 514:16] + wire _T_42 = io_dec_tlu_flush_lower_r != flush_lower_ff; // @[el2_exu.scala 68:116] + wire i0_rs1_bypass_en_d = io_dec_i0_rs1_bypass_en_d[0] | io_dec_i0_rs1_bypass_en_d[1]; // @[el2_exu.scala 69:65] + wire i0_rs2_bypass_en_d = io_dec_i0_rs2_bypass_en_d[0] | io_dec_i0_rs2_bypass_en_d[1]; // @[el2_exu.scala 70:65] + wire [31:0] _T_52 = io_dec_i0_rs1_bypass_en_d[0] ? io_dec_i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_53 = io_dec_i0_rs1_bypass_en_d[1] ? io_exu_i0_result_x : 32'h0; // @[Mux.scala 27:72] + wire [31:0] i0_rs1_bypass_data_d = _T_52 | _T_53; // @[Mux.scala 27:72] + wire [31:0] _T_59 = io_dec_i0_rs2_bypass_en_d[0] ? io_dec_i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_60 = io_dec_i0_rs2_bypass_en_d[1] ? io_exu_i0_result_x : 32'h0; // @[Mux.scala 27:72] + wire [31:0] i0_rs2_bypass_data_d = _T_59 | _T_60; // @[Mux.scala 27:72] + wire _T_63 = ~i0_rs1_bypass_en_d; // @[el2_exu.scala 84:6] + wire _T_64 = _T_63 & io_dec_i0_select_pc_d; // @[el2_exu.scala 84:26] + wire [31:0] _T_66 = {io_dec_i0_pc_d,1'h0}; // @[Cat.scala 29:58] + wire _T_68 = _T_63 & io_dec_debug_wdata_rs1_d; // @[el2_exu.scala 85:26] + wire _T_71 = ~io_dec_debug_wdata_rs1_d; // @[el2_exu.scala 86:28] + wire _T_72 = _T_63 & _T_71; // @[el2_exu.scala 86:26] + wire _T_73 = _T_72 & io_dec_i0_rs1_en_d; // @[el2_exu.scala 86:54] + wire [31:0] _T_75 = i0_rs1_bypass_en_d ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_76 = _T_64 ? _T_66 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_77 = _T_68 ? io_dbg_cmd_wrdata : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_78 = _T_73 ? io_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_79 = _T_75 | _T_76; // @[Mux.scala 27:72] + wire [31:0] _T_80 = _T_79 | _T_77; // @[Mux.scala 27:72] + wire [31:0] i0_rs1_d = _T_80 | _T_78; // @[Mux.scala 27:72] + wire _T_82 = ~i0_rs2_bypass_en_d; // @[el2_exu.scala 90:6] + wire _T_83 = _T_82 & io_dec_i0_rs2_en_d; // @[el2_exu.scala 90:26] + wire [31:0] _T_88 = _T_83 ? io_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_89 = _T_82 ? io_dec_i0_immed_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_90 = i0_rs2_bypass_en_d ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_91 = _T_88 | _T_89; // @[Mux.scala 27:72] + wire _T_94 = ~io_dec_extint_stall; // @[el2_exu.scala 96:28] + wire _T_95 = _T_63 & _T_94; // @[el2_exu.scala 96:26] + wire _T_96 = _T_95 & io_dec_i0_rs1_en_d; // @[el2_exu.scala 96:49] + wire _T_99 = i0_rs1_bypass_en_d & _T_94; // @[el2_exu.scala 97:25] + wire [31:0] _T_102 = {io_dec_tlu_meihap,2'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_103 = _T_96 ? io_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_104 = _T_99 ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_105 = io_dec_extint_stall ? _T_102 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_106 = _T_103 | _T_104; // @[Mux.scala 27:72] + wire _T_111 = _T_82 & _T_94; // @[el2_exu.scala 102:26] + wire _T_112 = _T_111 & io_dec_i0_rs2_en_d; // @[el2_exu.scala 102:49] + wire _T_115 = i0_rs2_bypass_en_d & _T_94; // @[el2_exu.scala 103:25] + wire [31:0] _T_117 = _T_112 ? io_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_118 = _T_115 ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72] + wire _T_122 = _T_63 & io_dec_i0_rs1_en_d; // @[el2_exu.scala 107:26] + wire [31:0] _T_125 = _T_122 ? io_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72] + wire [7:0] _T_167 = {ghr_x[6:0],i0_taken_x}; // @[Cat.scala 29:58] + wire [20:0] final_predpipe_mp = i0_flush_upper_x ? predpipe_x : 21'h0; // @[el2_exu.scala 191:49] + wire _T_179 = i0_flush_upper_x & _T_149; // @[el2_exu.scala 193:67] + wire [31:0] i0_flush_path_d = {{1'd0}, i_alu_io_flush_path_out}; // @[el2_exu.scala 21:46 el2_exu.scala 136:41] + wire [31:0] _T_186 = io_dec_tlu_flush_lower_r ? {{1'd0}, io_dec_tlu_flush_path_r} : i0_flush_path_d; // @[el2_exu.scala 210:56] + wire [31:0] pred_correct_npc_r = {{1'd0}, _T_23}; // @[el2_exu.scala 26:46 el2_exu.scala 55:41] + wire [31:0] _T_188 = i0_pred_correct_upper_r ? pred_correct_npc_r : i0_flush_path_upper_r; // @[el2_exu.scala 211:56] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 518:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 518:23] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) + ); + rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) + ); + rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_12_io_l1clk), + .io_clk(rvclkhdr_12_io_clk), + .io_en(rvclkhdr_12_io_en), + .io_scan_mode(rvclkhdr_12_io_scan_mode) + ); + rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_13_io_l1clk), + .io_clk(rvclkhdr_13_io_clk), + .io_en(rvclkhdr_13_io_en), + .io_scan_mode(rvclkhdr_13_io_scan_mode) + ); + rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_14_io_l1clk), + .io_clk(rvclkhdr_14_io_clk), + .io_en(rvclkhdr_14_io_en), + .io_scan_mode(rvclkhdr_14_io_scan_mode) + ); + rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_15_io_l1clk), + .io_clk(rvclkhdr_15_io_clk), + .io_en(rvclkhdr_15_io_en), + .io_scan_mode(rvclkhdr_15_io_scan_mode) + ); + rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_16_io_l1clk), + .io_clk(rvclkhdr_16_io_clk), + .io_en(rvclkhdr_16_io_en), + .io_scan_mode(rvclkhdr_16_io_scan_mode) + ); + rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_17_io_l1clk), + .io_clk(rvclkhdr_17_io_clk), + .io_en(rvclkhdr_17_io_en), + .io_scan_mode(rvclkhdr_17_io_scan_mode) + ); + el2_exu_alu_ctl i_alu ( // @[el2_exu.scala 120:19] + .clock(i_alu_clock), + .reset(i_alu_reset), + .io_scan_mode(i_alu_io_scan_mode), + .io_flush_upper_x(i_alu_io_flush_upper_x), + .io_flush_lower_r(i_alu_io_flush_lower_r), + .io_enable(i_alu_io_enable), + .io_valid_in(i_alu_io_valid_in), + .io_ap_land(i_alu_io_ap_land), + .io_ap_lor(i_alu_io_ap_lor), + .io_ap_lxor(i_alu_io_ap_lxor), + .io_ap_sll(i_alu_io_ap_sll), + .io_ap_srl(i_alu_io_ap_srl), + .io_ap_sra(i_alu_io_ap_sra), + .io_ap_beq(i_alu_io_ap_beq), + .io_ap_bne(i_alu_io_ap_bne), + .io_ap_blt(i_alu_io_ap_blt), + .io_ap_bge(i_alu_io_ap_bge), + .io_ap_add(i_alu_io_ap_add), + .io_ap_sub(i_alu_io_ap_sub), + .io_ap_slt(i_alu_io_ap_slt), + .io_ap_unsign(i_alu_io_ap_unsign), + .io_ap_jal(i_alu_io_ap_jal), + .io_ap_predict_t(i_alu_io_ap_predict_t), + .io_ap_predict_nt(i_alu_io_ap_predict_nt), + .io_ap_csr_write(i_alu_io_ap_csr_write), + .io_ap_csr_imm(i_alu_io_ap_csr_imm), + .io_csr_ren_in(i_alu_io_csr_ren_in), + .io_a_in(i_alu_io_a_in), + .io_b_in(i_alu_io_b_in), + .io_pc_in(i_alu_io_pc_in), + .io_pp_in_boffset(i_alu_io_pp_in_boffset), + .io_pp_in_pc4(i_alu_io_pp_in_pc4), + .io_pp_in_hist(i_alu_io_pp_in_hist), + .io_pp_in_toffset(i_alu_io_pp_in_toffset), + .io_pp_in_valid(i_alu_io_pp_in_valid), + .io_pp_in_br_error(i_alu_io_pp_in_br_error), + .io_pp_in_br_start_error(i_alu_io_pp_in_br_start_error), + .io_pp_in_prett(i_alu_io_pp_in_prett), + .io_pp_in_pcall(i_alu_io_pp_in_pcall), + .io_pp_in_pret(i_alu_io_pp_in_pret), + .io_pp_in_pja(i_alu_io_pp_in_pja), + .io_pp_in_way(i_alu_io_pp_in_way), + .io_brimm_in(i_alu_io_brimm_in), + .io_result_ff(i_alu_io_result_ff), + .io_flush_upper_out(i_alu_io_flush_upper_out), + .io_flush_final_out(i_alu_io_flush_final_out), + .io_flush_path_out(i_alu_io_flush_path_out), + .io_pc_ff(i_alu_io_pc_ff), + .io_pred_correct_out(i_alu_io_pred_correct_out), + .io_predict_p_out_misp(i_alu_io_predict_p_out_misp), + .io_predict_p_out_ataken(i_alu_io_predict_p_out_ataken), + .io_predict_p_out_boffset(i_alu_io_predict_p_out_boffset), + .io_predict_p_out_pc4(i_alu_io_predict_p_out_pc4), + .io_predict_p_out_hist(i_alu_io_predict_p_out_hist), + .io_predict_p_out_toffset(i_alu_io_predict_p_out_toffset), + .io_predict_p_out_valid(i_alu_io_predict_p_out_valid), + .io_predict_p_out_br_error(i_alu_io_predict_p_out_br_error), + .io_predict_p_out_br_start_error(i_alu_io_predict_p_out_br_start_error), + .io_predict_p_out_pcall(i_alu_io_predict_p_out_pcall), + .io_predict_p_out_pret(i_alu_io_predict_p_out_pret), + .io_predict_p_out_pja(i_alu_io_predict_p_out_pja), + .io_predict_p_out_way(i_alu_io_predict_p_out_way) + ); + el2_exu_mul_ctl i_mul ( // @[el2_exu.scala 141:19] + .clock(i_mul_clock), + .reset(i_mul_reset), + .io_scan_mode(i_mul_io_scan_mode), + .io_mul_p_valid(i_mul_io_mul_p_valid), + .io_mul_p_rs1_sign(i_mul_io_mul_p_rs1_sign), + .io_mul_p_rs2_sign(i_mul_io_mul_p_rs2_sign), + .io_mul_p_low(i_mul_io_mul_p_low), + .io_rs1_in(i_mul_io_rs1_in), + .io_rs2_in(i_mul_io_rs2_in), + .io_result_x(i_mul_io_result_x) + ); + el2_exu_div_ctl i_div ( // @[el2_exu.scala 148:19] + .clock(i_div_clock), + .reset(i_div_reset), + .io_scan_mode(i_div_io_scan_mode), + .io_dp_valid(i_div_io_dp_valid), + .io_dp_unsign(i_div_io_dp_unsign), + .io_dp_rem(i_div_io_dp_rem), + .io_dividend(i_div_io_dividend), + .io_divisor(i_div_io_divisor), + .io_cancel(i_div_io_cancel), + .io_out(i_div_io_out), + .io_finish_dly(i_div_io_finish_dly) + ); + assign io_exu_lsu_rs1_d = _T_106 | _T_105; // @[el2_exu.scala 95:19] + assign io_exu_lsu_rs2_d = _T_117 | _T_118; // @[el2_exu.scala 101:19] + assign io_exu_flush_final = i_alu_io_flush_final_out; // @[el2_exu.scala 135:33] + assign io_exu_flush_path_final = _T_186[30:0]; // @[el2_exu.scala 210:50] + assign io_exu_i0_result_x = mul_valid_x ? i_mul_io_result_x : i_alu_io_result_ff; // @[el2_exu.scala 157:42] + assign io_exu_i0_pc_x = i_alu_io_pc_ff; // @[el2_exu.scala 139:41] + assign io_exu_csr_rs1_x = _T_3; // @[el2_exu.scala 41:41] + assign io_exu_npc_r = _T_188[30:0]; // @[el2_exu.scala 211:50] + assign io_exu_i0_br_hist_r = i0_pp_r_hist; // @[el2_exu.scala 184:50] + assign io_exu_i0_br_error_r = i0_pp_r_br_error; // @[el2_exu.scala 185:42] + assign io_exu_i0_br_start_error_r = i0_pp_r_br_start_error; // @[el2_exu.scala 187:36] + assign io_exu_i0_br_index_r = predpipe_r[12:5]; // @[el2_exu.scala 189:42] + assign io_exu_i0_br_valid_r = i0_pp_r_valid; // @[el2_exu.scala 181:36] + assign io_exu_i0_br_mp_r = i0_pp_r_misp; // @[el2_exu.scala 182:36] + assign io_exu_i0_br_middle_r = i0_pp_r_pc4 ^ i0_pp_r_boffset; // @[el2_exu.scala 186:36] + assign io_exu_i0_br_fghr_r = predpipe_r[20:13]; // @[el2_exu.scala 188:50] + assign io_exu_i0_br_way_r = i0_pp_r_way; // @[el2_exu.scala 183:36] + assign io_exu_mp_pkt_misp = i0_flush_upper_x & i0_predict_p_x_misp; // @[el2_exu.scala 197:36] + assign io_exu_mp_pkt_ataken = i0_flush_upper_x & i0_predict_p_x_ataken; // @[el2_exu.scala 201:36] + assign io_exu_mp_pkt_boffset = i0_flush_upper_x & i0_predict_p_x_boffset; // @[el2_exu.scala 202:36] + assign io_exu_mp_pkt_pc4 = i0_flush_upper_x & i0_predict_p_x_pc4; // @[el2_exu.scala 203:36] + assign io_exu_mp_pkt_hist = i0_flush_upper_x ? i0_predict_p_x_hist : 2'h0; // @[el2_exu.scala 204:50] + assign io_exu_mp_pkt_toffset = i0_flush_upper_x ? i0_predict_p_x_toffset : 12'h0; // @[el2_exu.scala 205:42] + assign io_exu_mp_pkt_valid = 1'h0; // @[el2_exu.scala 32:41] + assign io_exu_mp_pkt_br_error = 1'h0; // @[el2_exu.scala 31:41] + assign io_exu_mp_pkt_br_start_error = 1'h0; // @[el2_exu.scala 30:31] + assign io_exu_mp_pkt_prett = 31'h0; // @[el2_exu.scala 29:41] + assign io_exu_mp_pkt_pcall = i0_flush_upper_x & i0_predict_p_x_pcall; // @[el2_exu.scala 198:36] + assign io_exu_mp_pkt_pret = i0_flush_upper_x & i0_predict_p_x_pret; // @[el2_exu.scala 200:36] + assign io_exu_mp_pkt_pja = i0_flush_upper_x & i0_predict_p_x_pja; // @[el2_exu.scala 199:36] + assign io_exu_mp_pkt_way = i0_flush_upper_x & i0_predict_p_x_way; // @[el2_exu.scala 196:36] + assign io_exu_mp_eghr = final_predpipe_mp[20:13]; // @[el2_exu.scala 209:36] + assign io_exu_mp_fghr = _T_179 ? ghr_d : ghr_x; // @[el2_exu.scala 206:36] + assign io_exu_mp_index = final_predpipe_mp[12:5]; // @[el2_exu.scala 207:58] + assign io_exu_mp_btag = final_predpipe_mp[4:0]; // @[el2_exu.scala 208:58] + assign io_exu_pmu_i0_br_misp = i0_pp_r_misp; // @[el2_exu.scala 161:31] + assign io_exu_pmu_i0_br_ataken = i0_pp_r_ataken; // @[el2_exu.scala 162:31] + assign io_exu_pmu_i0_pc4 = i0_pp_r_pc4; // @[el2_exu.scala 163:31] + assign io_exu_div_result = i_div_io_out; // @[el2_exu.scala 155:33] + assign io_exu_div_wren = i_div_io_finish_dly; // @[el2_exu.scala 154:41] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = io_dec_data_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = io_dec_data_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 520:18] + assign rvclkhdr_2_io_en = io_dec_data_en[1]; // @[el2_lib.scala 521:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_3_io_en = io_dec_data_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_4_io_en = io_dec_data_en[0]; // @[el2_lib.scala 511:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_5_io_en = io_dec_ctl_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_6_io_en = io_dec_ctl_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_7_io_en = io_dec_ctl_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_8_io_en = io_dec_ctl_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_9_io_en = io_dec_ctl_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 520:18] + assign rvclkhdr_10_io_en = io_dec_ctl_en[0]; // @[el2_lib.scala 521:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] + assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_11_io_en = io_dec_ctl_en[0]; // @[el2_lib.scala 511:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_12_io_en = io_dec_ctl_en[0]; // @[el2_lib.scala 511:17] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_13_io_en = io_dec_data_en[0]; // @[el2_lib.scala 511:17] + assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_14_io_en = io_dec_data_en[0]; // @[el2_lib.scala 511:17] + assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_15_io_en = _T_41 | _T_42; // @[el2_lib.scala 511:17] + assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_16_io_en = _T_41 | _T_42; // @[el2_lib.scala 511:17] + assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_17_io_en = _T_41 | _T_42; // @[el2_lib.scala 511:17] + assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign i_alu_clock = clock; + assign i_alu_reset = reset; + assign i_alu_io_scan_mode = io_scan_mode; // @[el2_exu.scala 121:33] + assign i_alu_io_flush_upper_x = i0_flush_upper_x; // @[el2_exu.scala 125:33] + assign i_alu_io_flush_lower_r = io_dec_tlu_flush_lower_r; // @[el2_exu.scala 126:33] + assign i_alu_io_enable = io_dec_ctl_en[1]; // @[el2_exu.scala 122:41] + assign i_alu_io_valid_in = io_dec_i0_alu_decode_d; // @[el2_exu.scala 124:33] + assign i_alu_io_ap_land = io_i0_ap_land; // @[el2_exu.scala 131:41] + assign i_alu_io_ap_lor = io_i0_ap_lor; // @[el2_exu.scala 131:41] + assign i_alu_io_ap_lxor = io_i0_ap_lxor; // @[el2_exu.scala 131:41] + assign i_alu_io_ap_sll = io_i0_ap_sll; // @[el2_exu.scala 131:41] + assign i_alu_io_ap_srl = io_i0_ap_srl; // @[el2_exu.scala 131:41] + assign i_alu_io_ap_sra = io_i0_ap_sra; // @[el2_exu.scala 131:41] + assign i_alu_io_ap_beq = io_i0_ap_beq; // @[el2_exu.scala 131:41] + assign i_alu_io_ap_bne = io_i0_ap_bne; // @[el2_exu.scala 131:41] + assign i_alu_io_ap_blt = io_i0_ap_blt; // @[el2_exu.scala 131:41] + assign i_alu_io_ap_bge = io_i0_ap_bge; // @[el2_exu.scala 131:41] + assign i_alu_io_ap_add = io_i0_ap_add; // @[el2_exu.scala 131:41] + assign i_alu_io_ap_sub = io_i0_ap_sub; // @[el2_exu.scala 131:41] + assign i_alu_io_ap_slt = io_i0_ap_slt; // @[el2_exu.scala 131:41] + assign i_alu_io_ap_unsign = io_i0_ap_unsign; // @[el2_exu.scala 131:41] + assign i_alu_io_ap_jal = io_i0_ap_jal; // @[el2_exu.scala 131:41] + assign i_alu_io_ap_predict_t = io_i0_ap_predict_t; // @[el2_exu.scala 131:41] + assign i_alu_io_ap_predict_nt = io_i0_ap_predict_nt; // @[el2_exu.scala 131:41] + assign i_alu_io_ap_csr_write = io_i0_ap_csr_write; // @[el2_exu.scala 131:41] + assign i_alu_io_ap_csr_imm = io_i0_ap_csr_imm; // @[el2_exu.scala 131:41] + assign i_alu_io_csr_ren_in = io_dec_csr_ren_d; // @[el2_exu.scala 132:33] + assign i_alu_io_a_in = _T_80 | _T_78; // @[el2_exu.scala 127:33] + assign i_alu_io_b_in = _T_91 | _T_90; // @[el2_exu.scala 128:33] + assign i_alu_io_pc_in = io_dec_i0_pc_d; // @[el2_exu.scala 129:41] + assign i_alu_io_pp_in_boffset = io_dec_i0_pc_d[0]; // @[el2_exu.scala 123:41] + assign i_alu_io_pp_in_pc4 = io_dec_i0_predict_p_d_pc4; // @[el2_exu.scala 123:41] + assign i_alu_io_pp_in_hist = io_dec_i0_predict_p_d_hist; // @[el2_exu.scala 123:41] + assign i_alu_io_pp_in_toffset = io_dec_i0_predict_p_d_toffset; // @[el2_exu.scala 123:41] + assign i_alu_io_pp_in_valid = io_dec_i0_predict_p_d_valid; // @[el2_exu.scala 123:41] + assign i_alu_io_pp_in_br_error = io_dec_i0_predict_p_d_br_error; // @[el2_exu.scala 123:41] + assign i_alu_io_pp_in_br_start_error = io_dec_i0_predict_p_d_br_start_error; // @[el2_exu.scala 123:41] + assign i_alu_io_pp_in_prett = io_dec_i0_predict_p_d_prett; // @[el2_exu.scala 123:41] + assign i_alu_io_pp_in_pcall = io_dec_i0_predict_p_d_pcall; // @[el2_exu.scala 123:41] + assign i_alu_io_pp_in_pret = io_dec_i0_predict_p_d_pret; // @[el2_exu.scala 123:41] + assign i_alu_io_pp_in_pja = io_dec_i0_predict_p_d_pja; // @[el2_exu.scala 123:41] + assign i_alu_io_pp_in_way = io_dec_i0_predict_p_d_way; // @[el2_exu.scala 123:41] + assign i_alu_io_brimm_in = io_dec_i0_br_immed_d; // @[el2_exu.scala 130:33] + assign i_mul_clock = clock; + assign i_mul_reset = reset; + assign i_mul_io_scan_mode = io_scan_mode; // @[el2_exu.scala 142:33] + assign i_mul_io_mul_p_valid = io_mul_p_valid; // @[el2_exu.scala 143:41] + assign i_mul_io_mul_p_rs1_sign = io_mul_p_rs1_sign; // @[el2_exu.scala 143:41] + assign i_mul_io_mul_p_rs2_sign = io_mul_p_rs2_sign; // @[el2_exu.scala 143:41] + assign i_mul_io_mul_p_low = io_mul_p_low; // @[el2_exu.scala 143:41] + assign i_mul_io_rs1_in = _T_125 | _T_75; // @[el2_exu.scala 144:41] + assign i_mul_io_rs2_in = _T_91 | _T_90; // @[el2_exu.scala 145:41] + assign i_div_clock = clock; + assign i_div_reset = reset; + assign i_div_io_scan_mode = io_scan_mode; // @[el2_exu.scala 149:33] + assign i_div_io_dp_valid = io_div_p_valid; // @[el2_exu.scala 151:41] + assign i_div_io_dp_unsign = io_div_p_unsign; // @[el2_exu.scala 151:41] + assign i_div_io_dp_rem = io_div_p_rem; // @[el2_exu.scala 151:41] + assign i_div_io_dividend = _T_125 | _T_75; // @[el2_exu.scala 152:33] + assign i_div_io_divisor = _T_91 | _T_90; // @[el2_exu.scala 153:33] + assign i_div_io_cancel = io_dec_div_cancel; // @[el2_exu.scala 150:41] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + i0_flush_path_x = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + _T_3 = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + i0_predict_p_x_misp = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + i0_predict_p_x_ataken = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + i0_predict_p_x_boffset = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + i0_predict_p_x_pc4 = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + i0_predict_p_x_hist = _RAND_6[1:0]; + _RAND_7 = {1{`RANDOM}}; + i0_predict_p_x_toffset = _RAND_7[11:0]; + _RAND_8 = {1{`RANDOM}}; + i0_predict_p_x_valid = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + i0_predict_p_x_br_error = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + i0_predict_p_x_br_start_error = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + i0_predict_p_x_pcall = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + i0_predict_p_x_pret = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + i0_predict_p_x_pja = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + i0_predict_p_x_way = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + predpipe_x = _RAND_15[20:0]; + _RAND_16 = {1{`RANDOM}}; + predpipe_r = _RAND_16[20:0]; + _RAND_17 = {1{`RANDOM}}; + ghr_x = _RAND_17[7:0]; + _RAND_18 = {1{`RANDOM}}; + i0_pred_correct_upper_x = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + i0_flush_upper_x = _RAND_19[0:0]; + _RAND_20 = {1{`RANDOM}}; + i0_taken_x = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + i0_valid_x = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + i0_pp_r_misp = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + i0_pp_r_ataken = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + i0_pp_r_boffset = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + i0_pp_r_pc4 = _RAND_25[0:0]; + _RAND_26 = {1{`RANDOM}}; + i0_pp_r_hist = _RAND_26[1:0]; + _RAND_27 = {1{`RANDOM}}; + i0_pp_r_valid = _RAND_27[0:0]; + _RAND_28 = {1{`RANDOM}}; + i0_pp_r_br_error = _RAND_28[0:0]; + _RAND_29 = {1{`RANDOM}}; + i0_pp_r_br_start_error = _RAND_29[0:0]; + _RAND_30 = {1{`RANDOM}}; + i0_pp_r_way = _RAND_30[0:0]; + _RAND_31 = {1{`RANDOM}}; + pred_temp1 = _RAND_31[5:0]; + _RAND_32 = {1{`RANDOM}}; + i0_pred_correct_upper_r = _RAND_32[0:0]; + _RAND_33 = {1{`RANDOM}}; + i0_flush_path_upper_r = _RAND_33[31:0]; + _RAND_34 = {1{`RANDOM}}; + pred_temp2 = _RAND_34[24:0]; + _RAND_35 = {1{`RANDOM}}; + ghr_d = _RAND_35[7:0]; + _RAND_36 = {1{`RANDOM}}; + mul_valid_x = _RAND_36[0:0]; + _RAND_37 = {1{`RANDOM}}; + flush_lower_ff = _RAND_37[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + i0_flush_path_x = 32'h0; + end + if (reset) begin + _T_3 = 32'h0; + end + if (reset) begin + i0_predict_p_x_misp = 1'h0; + end + if (reset) begin + i0_predict_p_x_ataken = 1'h0; + end + if (reset) begin + i0_predict_p_x_boffset = 1'h0; + end + if (reset) begin + i0_predict_p_x_pc4 = 1'h0; + end + if (reset) begin + i0_predict_p_x_hist = 2'h0; + end + if (reset) begin + i0_predict_p_x_toffset = 12'h0; + end + if (reset) begin + i0_predict_p_x_valid = 1'h0; + end + if (reset) begin + i0_predict_p_x_br_error = 1'h0; + end + if (reset) begin + i0_predict_p_x_br_start_error = 1'h0; + end + if (reset) begin + i0_predict_p_x_pcall = 1'h0; + end + if (reset) begin + i0_predict_p_x_pret = 1'h0; + end + if (reset) begin + i0_predict_p_x_pja = 1'h0; + end + if (reset) begin + i0_predict_p_x_way = 1'h0; + end + if (reset) begin + predpipe_x = 21'h0; + end + if (reset) begin + predpipe_r = 21'h0; + end + if (reset) begin + ghr_x = 8'h0; + end + if (reset) begin + i0_pred_correct_upper_x = 1'h0; + end + if (reset) begin + i0_flush_upper_x = 1'h0; + end + if (reset) begin + i0_taken_x = 1'h0; + end + if (reset) begin + i0_valid_x = 1'h0; + end + if (reset) begin + i0_pp_r_misp = 1'h0; + end + if (reset) begin + i0_pp_r_ataken = 1'h0; + end + if (reset) begin + i0_pp_r_boffset = 1'h0; + end + if (reset) begin + i0_pp_r_pc4 = 1'h0; + end + if (reset) begin + i0_pp_r_hist = 2'h0; + end + if (reset) begin + i0_pp_r_valid = 1'h0; + end + if (reset) begin + i0_pp_r_br_error = 1'h0; + end + if (reset) begin + i0_pp_r_br_start_error = 1'h0; + end + if (reset) begin + i0_pp_r_way = 1'h0; + end + if (reset) begin + pred_temp1 = 6'h0; + end + if (reset) begin + i0_pred_correct_upper_r = 1'h0; + end + if (reset) begin + i0_flush_path_upper_r = 32'h0; + end + if (reset) begin + pred_temp2 = 25'h0; + end + if (reset) begin + ghr_d = 8'h0; + end + if (reset) begin + mul_valid_x = 1'h0; + end + if (reset) begin + flush_lower_ff = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + i0_flush_path_x <= 32'h0; + end else begin + i0_flush_path_x <= {{1'd0}, i_alu_io_flush_path_out}; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + _T_3 <= 32'h0; + end else if (io_dec_csr_ren_d) begin + _T_3 <= i0_rs1_d; + end else begin + _T_3 <= io_exu_csr_rs1_x; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_misp <= 1'h0; + end else begin + i0_predict_p_x_misp <= i_alu_io_predict_p_out_misp; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_ataken <= 1'h0; + end else begin + i0_predict_p_x_ataken <= i_alu_io_predict_p_out_ataken; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_boffset <= 1'h0; + end else begin + i0_predict_p_x_boffset <= i_alu_io_predict_p_out_boffset; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_pc4 <= 1'h0; + end else begin + i0_predict_p_x_pc4 <= i_alu_io_predict_p_out_pc4; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_hist <= 2'h0; + end else begin + i0_predict_p_x_hist <= i_alu_io_predict_p_out_hist; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_toffset <= 12'h0; + end else begin + i0_predict_p_x_toffset <= i_alu_io_predict_p_out_toffset; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_valid <= 1'h0; + end else begin + i0_predict_p_x_valid <= i_alu_io_predict_p_out_valid; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_br_error <= 1'h0; + end else begin + i0_predict_p_x_br_error <= i_alu_io_predict_p_out_br_error; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_br_start_error <= 1'h0; + end else begin + i0_predict_p_x_br_start_error <= i_alu_io_predict_p_out_br_start_error; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_pcall <= 1'h0; + end else begin + i0_predict_p_x_pcall <= i_alu_io_predict_p_out_pcall; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_pret <= 1'h0; + end else begin + i0_predict_p_x_pret <= i_alu_io_predict_p_out_pret; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_pja <= 1'h0; + end else begin + i0_predict_p_x_pja <= i_alu_io_predict_p_out_pja; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_way <= 1'h0; + end else begin + i0_predict_p_x_way <= i_alu_io_predict_p_out_way; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + predpipe_x <= 21'h0; + end else begin + predpipe_x <= {_T,io_i0_predict_btag_d}; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + predpipe_r <= 21'h0; + end else begin + predpipe_r <= predpipe_x; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + ghr_x <= 8'h0; + end else if (i0_valid_x) begin + ghr_x <= _T_167; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + i0_pred_correct_upper_x <= 1'h0; + end else begin + i0_pred_correct_upper_x <= i_alu_io_pred_correct_out; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + i0_flush_upper_x <= 1'h0; + end else begin + i0_flush_upper_x <= i_alu_io_flush_upper_out; + end + end + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin + if (reset) begin + i0_taken_x <= 1'h0; + end else begin + i0_taken_x <= i0_predict_p_d_ataken & io_dec_i0_alu_decode_d; + end + end + always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin + if (reset) begin + i0_valid_x <= 1'h0; + end else begin + i0_valid_x <= _T_145 & _T_149; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_misp <= 1'h0; + end else begin + i0_pp_r_misp <= i0_predict_p_x_misp; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_ataken <= 1'h0; + end else begin + i0_pp_r_ataken <= i0_predict_p_x_ataken; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_boffset <= 1'h0; + end else begin + i0_pp_r_boffset <= i0_predict_p_x_boffset; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_pc4 <= 1'h0; + end else begin + i0_pp_r_pc4 <= i0_predict_p_x_pc4; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_hist <= 2'h0; + end else begin + i0_pp_r_hist <= i0_predict_p_x_hist; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_valid <= 1'h0; + end else begin + i0_pp_r_valid <= i0_predict_p_x_valid; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_br_error <= 1'h0; + end else begin + i0_pp_r_br_error <= i0_predict_p_x_br_error; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_br_start_error <= 1'h0; + end else begin + i0_pp_r_br_start_error <= i0_predict_p_x_br_start_error; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_way <= 1'h0; + end else begin + i0_pp_r_way <= i0_predict_p_x_way; + end + end + always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin + if (reset) begin + pred_temp1 <= 6'h0; + end else begin + pred_temp1 <= io_pred_correct_npc_x[5:0]; + end + end + always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin + if (reset) begin + i0_pred_correct_upper_r <= 1'h0; + end else begin + i0_pred_correct_upper_r <= i0_pred_correct_upper_x; + end + end + always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin + if (reset) begin + i0_flush_path_upper_r <= 32'h0; + end else begin + i0_flush_path_upper_r <= i0_flush_path_x; + end + end + always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin + if (reset) begin + pred_temp2 <= 25'h0; + end else begin + pred_temp2 <= io_pred_correct_npc_x[30:6]; + end + end + always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin + if (reset) begin + ghr_d <= 8'h0; + end else begin + ghr_d <= _T_162 | _T_161; + end + end + always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin + if (reset) begin + mul_valid_x <= 1'h0; + end else begin + mul_valid_x <= io_mul_p_valid; + end + end + always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin + if (reset) begin + flush_lower_ff <= 1'h0; + end else begin + flush_lower_ff <= io_dec_tlu_flush_lower_r; + end + end +endmodule diff --git a/src/main/scala/el2_dma_ctrl.scala b/src/main/scala/el2_dma_ctrl.scala index b6477c72..0f2f392d 100644 --- a/src/main/scala/el2_dma_ctrl.scala +++ b/src/main/scala/el2_dma_ctrl.scala @@ -1,4 +1,3 @@ -package dma import chisel3._ import chisel3.util._ import scala.collection._ diff --git a/src/main/scala/el2_swerv.scala b/src/main/scala/el2_swerv.scala new file mode 100644 index 00000000..1ab72ab4 --- /dev/null +++ b/src/main/scala/el2_swerv.scala @@ -0,0 +1,662 @@ +import chisel3._ +import chisel3.util._ +import ifu._ +import dec._ +import exu._ +import lsu._ +import lib._ +import include._ +import dmi._ +import dbg._ + +class el2_swerv extends Module with RequireAsyncReset with el2_lib { + val io = IO (new Bundle{ + val dbg_rst_l = Input(Bool()) + val rst_vec = Input(UInt(31.W)) + val nmi_int = Input(Bool()) + val nmi_vec = Input(UInt(31.W)) + val core_rst_l = Output(Bool()) + val trace_rv_i_insn_ip = Output(UInt(32.W)) + val trace_rv_i_address_ip = Output(UInt(32.W)) + val trace_rv_i_valid_ip = Output(UInt(2.W)) + val trace_rv_i_exception_ip = Output(UInt(2.W)) + val trace_rv_i_ecause_ip = Output(UInt(5.W)) + val trace_rv_i_interrupt_ip = Output(UInt(2.W)) + val trace_rv_i_tval_ip = Output(UInt(32.W)) + val dccm_clk_override = Output(Bool()) + val icm_clk_override = Output(Bool()) + val dec_tlu_core_ecc_disable = Output(Bool()) + val i_cpu_halt_req = Input(Bool()) + val i_cpu_run_req = Input(Bool()) + val o_cpu_halt_ack = Output(Bool()) + val o_cpu_halt_status = Output(Bool()) + val o_cpu_run_ack = Output(Bool()) + val o_debug_mode_status = Output(Bool()) + val core_id = Input(UInt(28.W)) + val mpc_debug_halt_req = Input(Bool()) + val mpc_debug_run_req = Input(Bool()) + val mpc_reset_run_req = Input(Bool()) + val mpc_debug_halt_ack = Output(Bool()) + val mpc_debug_run_ack = Output(Bool()) + val debug_brkpt_status = Output(Bool()) + val dec_tlu_perfcnt0 = Output(Bool()) + val dec_tlu_perfcnt1 = Output(Bool()) + val dec_tlu_perfcnt2 = Output(Bool()) + val dec_tlu_perfcnt3 = Output(Bool()) + val dccm_wren = Output(Bool()) + val dccm_rden = Output(Bool()) + val dccm_wr_addr_lo = Output(UInt(DCCM_BITS.W)) + val dccm_wr_addr_hi = Output(UInt(DCCM_BITS.W)) + val dccm_rd_addr_lo = Output(UInt(DCCM_BITS.W)) + val dccm_rd_addr_hi = Output(UInt(DCCM_BITS.W)) + + val dccm_wr_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W)) + val dccm_wr_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W)) + val dccm_rd_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W)) + val dccm_rd_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W)) + + val iccm_rw_addr = Output(UInt(ICCM_BITS.W)) + val iccm_wren = Output(Bool()) + val iccm_rden = Output(Bool()) + val iccm_wr_size = Output(UInt(3.W)) + val iccm_wr_data = Output(UInt(78.W)) + val iccm_buf_correct_ecc = Output(Bool()) + val iccm_correction_state = Output(Bool()) + + val iccm_rd_data = Input(UInt(64.W)) + val iccm_rd_data_ecc = Input(UInt(78.W)) + + val ic_rw_addr = Output(UInt(31.W)) + val ic_tag_valid = Output(UInt(ICACHE_NUM_WAYS.W)) + val ic_wr_en = Output(UInt(ICACHE_NUM_WAYS.W)) + val ic_rd_en = Output(Bool()) + val ic_wr_data = Output(Vec(ICACHE_BANKS_WAY, UInt(71.W))) + val ic_rd_data = Input(UInt(64.W)) + val ic_debug_rd_data = Input(UInt(71.W)) + val ictag_debug_rd_data = Input(UInt(26.W)) + val ic_debug_wr_data = Output(UInt(71.W)) + + val ic_eccerr = Input(UInt(ICACHE_BANKS_WAY.W)) + val ic_parerr = Input(UInt(ICACHE_BANKS_WAY.W)) + val ic_premux_data = Output(UInt(64.W)) + val ic_sel_premux_data = Output(Bool()) + + val ic_debug_addr = Output(UInt((ICACHE_INDEX_HI-2).W)) + val ic_debug_rd_en = Output(Bool()) + val ic_debug_wr_en = Output(Bool()) + val ic_debug_tag_array = Output(Bool()) + val ic_debug_way = Output(UInt(ICACHE_NUM_WAYS.W)) + val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W)) + val ic_tag_perr = Input(Bool()) + + // AXI Signals + val lsu_axi_awvalid = Output(Bool()) + val lsu_axi_awready = Input(Bool()) + val lsu_axi_awid = Output(UInt(LSU_BUS_TAG.W)) + val lsu_axi_awaddr = Output(UInt(32.W)) + val lsu_axi_awregion = Output(UInt(4.W)) + val lsu_axi_awlen = Output(UInt(8.W)) + val lsu_axi_awsize = Output(UInt(3.W)) + val lsu_axi_awburst = Output(UInt(2.W)) + val lsu_axi_awlock = Output(Bool()) + val lsu_axi_awcache = Output(UInt(4.W)) + val lsu_axi_awprot = Output(UInt(3.W)) + val lsu_axi_awqos = Output(UInt(4.W)) + val lsu_axi_wvalid = Output(Bool()) + val lsu_axi_wready = Input(Bool()) + val lsu_axi_wdata = Output(UInt(64.W)) + val lsu_axi_wstrb = Output(UInt(8.W)) + val lsu_axi_wlast = Output(Bool()) + val lsu_axi_bvalid = Input(Bool()) + val lsu_axi_bready = Output(Bool()) + val lsu_axi_bresp = Input(UInt(2.W)) + val lsu_axi_bid = Input(UInt(LSU_BUS_TAG.W)) + + + val lsu_axi_arvalid = Output(Bool()) + val lsu_axi_arready = Input(Bool()) + val lsu_axi_arid = Output(UInt(LSU_BUS_TAG.W)) + val lsu_axi_araddr = Output(UInt(32.W)) + val lsu_axi_arregion = Output(UInt(4.W)) + val lsu_axi_arlen = Output(UInt(8.W)) + val lsu_axi_arsize = Output(UInt(3.W)) + val lsu_axi_arburst = Output(UInt(2.W)) + val lsu_axi_arlock = Output(Bool()) + val lsu_axi_arcache = Output(UInt(4.W)) + val lsu_axi_arprot = Output(UInt(3.W)) + val lsu_axi_arqos = Output(UInt(4.W)) + val lsu_axi_rvalid = Input(Bool()) + val lsu_axi_rready = Output(Bool()) + val lsu_axi_rid = Input(UInt(LSU_BUS_TAG.W)) + val lsu_axi_rdata = Input(UInt(64.W)) + val lsu_axi_rresp = Input(UInt(2.W)) + val lsu_axi_rlast = Input(Bool()) + + + // AXI IFU Signals + val ifu_axi_awvalid = Output(Bool()) + val ifu_axi_awready = Input(Bool()) + val ifu_axi_awid = Output(UInt(IFU_BUS_TAG.W)) + val ifu_axi_awaddr = Output(UInt(32.W)) + val ifu_axi_awregion = Output(UInt(4.W)) + val ifu_axi_awlen = Output(UInt(8.W)) + val ifu_axi_awsize = Output(UInt(3.W)) + val ifu_axi_awburst = Output(UInt(2.W)) + val ifu_axi_awlock = Output(Bool()) + val ifu_axi_awcache = Output(UInt(4.W)) + val ifu_axi_awprot = Output(UInt(3.W)) + val ifu_axi_awqos = Output(UInt(4.W)) + val ifu_axi_wvalid = Output(Bool()) + val ifu_axi_wready = Output(Bool()) + val ifu_axi_wdata = Input(UInt(64.W)) + val ifu_axi_wstrb = Output(UInt(8.W)) + val ifu_axi_wlast = Output(Bool()) + val ifu_axi_bvalid = Input(Bool()) + val ifu_axi_bready = Output(Bool()) + val ifu_axi_bresp = Input(UInt(2.W)) + val ifu_axi_bid = Input(UInt(IFU_BUS_TAG.W)) + val ifu_axi_arvalid = Output(Bool()) + val ifu_axi_arready = Output(Bool()) + val ifu_axi_arid = Output(UInt(IFU_BUS_TAG.W)) + val ifu_axi_araddr = Output(UInt(32.W)) + val ifu_axi_arregion = Output(UInt(4.W)) + val ifu_axi_arlen = Output(UInt(8.W)) + val ifu_axi_arsize = Output(UInt(3.W)) + val ifu_axi_arburst = Output(UInt(2.W)) + val ifu_axi_arlock = Output(Bool()) + val ifu_axi_arcache = Output(UInt(4.W)) + val ifu_axi_arprot = Output(UInt(3.W)) + val ifu_axi_arqos = Output(UInt(4.W)) + val ifu_axi_rvalid = Input(Bool()) + val ifu_axi_rready = Output(Bool()) + val ifu_axi_rid = Input(UInt(IFU_BUS_TAG.W)) + val ifu_axi_rdata = Input(UInt(64.W)) + val ifu_axi_rresp = Input(UInt(2.W)) + val ifu_axi_rlast = Input(Bool()) + + // SB AXI Signals + val sb_axi_awvalid = Output(Bool()) + val sb_axi_awready = Input(Bool()) + val sb_axi_awid = Output(UInt(SB_BUS_TAG.W)) + val sb_axi_awaddr = Output(UInt(32.W)) + val sb_axi_awregion = Output(UInt(4.W)) + val sb_axi_awlen = Output(UInt(8.W)) + val sb_axi_awsize = Output(UInt(3.W)) + val sb_axi_awburst = Output(UInt(2.W)) + val sb_axi_awlock = Output(Bool()) + val sb_axi_awcache = Output(UInt(4.W)) + val sb_axi_awprot = Output(UInt(3.W)) + val sb_axi_awqos = Output(UInt(4.W)) + val sb_axi_wvalid = Output(Bool()) + val sb_axi_wready = Input(Bool()) + val sb_axi_wdata = Output(UInt(64.W)) + val sb_axi_wstrb = Output(UInt(8.W)) + val sb_axi_wlast = Output(Bool()) + val sb_axi_bvalid = Input(Bool()) + val sb_axi_bready = Output(Bool()) + val sb_axi_bresp = Input(UInt(2.W)) + val sb_axi_bid = Input(UInt(SB_BUS_TAG.W)) + val sb_axi_arvalid = Output(Bool()) + val sb_axi_arready = Input(Bool()) + val sb_axi_arid = Output(UInt(SB_BUS_TAG.W)) + val sb_axi_araddr = Output(UInt(32.W)) + val sb_axi_arregion = Output(UInt(4.W)) + val sb_axi_arlen = Output(UInt(8.W)) + val sb_axi_arsize = Output(UInt(3.W)) + val sb_axi_arburst = Output(UInt(2.W)) + val sb_axi_arlock = Output(Bool()) + val sb_axi_arcache = Output(UInt(4.W)) + val sb_axi_arprot = Output(UInt(3.W)) + val sb_axi_arqos = Output(UInt(4.W)) + val sb_axi_rvalid = Input(Bool()) + val sb_axi_rready = Output(Bool()) + val sb_axi_rid = Input(UInt(SB_BUS_TAG.W)) + val sb_axi_rdata = Input(UInt(64.W)) + val sb_axi_rresp = Input(UInt(2.W)) + val sb_axi_rlast = Input(Bool()) + // DMA signals + val dma_axi_awvalid = Input(Bool()) + val dma_axi_awready = Output(Bool()) + val dma_axi_awid = Input(UInt(DMA_BUS_TAG.W)) + val dma_axi_awaddr = Input(UInt(32.W)) + val dma_axi_awsize = Input(UInt(3.W)) + val dma_axi_awprot = Input(UInt(3.W)) + val dma_axi_awlen = Input(UInt(8.W)) + val dma_axi_awburst = Input(UInt(2.W)) + val dma_axi_wvalid = Input(Bool()) + val dma_axi_wready = Output(Bool()) + val dma_axi_wdata = Input(UInt(64.W)) + val dma_axi_wstrb = Input(UInt(8.W)) + val dma_axi_wlast = Input(Bool()) + val dma_axi_bvalid = Output(Bool()) + val dma_axi_bready = Input(Bool()) + val dma_axi_bresp = Output(UInt(2.W)) + val dma_axi_bid = Output(UInt(DMA_BUS_TAG.W)) + + // AXI Read Channels + val dma_axi_arvalid = Input(Bool()) + val dma_axi_arready = Output(Bool()) + val dma_axi_arid = Input(UInt(DMA_BUS_TAG.W)) + + val dma_axi_araddr = Input(UInt(32.W)) + val dma_axi_arsize = Input(UInt(3.W)) + + val dma_axi_arprot = Input(UInt(3.W)) + val dma_axi_arlen = Input(UInt(8.W)) + val dma_axi_arburst = Input(UInt(2.W)) + val dma_axi_rvalid = Output(Bool()) + val dma_axi_rready = Input(Bool()) + + val dma_axi_rid = Output(UInt(DMA_BUS_TAG.W)) + val dma_axi_rdata = Output(UInt(64.W)) + val dma_axi_rresp = Output(UInt(2.W)) + val dma_axi_rlast = Output(Bool()) + + // AHB Lite Bus + val haddr = Output(UInt(32.W)) + val hburst = Output(UInt(3.W)) + val hmastlock = Output(Bool()) + val hprot = Output(UInt(4.W)) + val hsize = Output(UInt(3.W)) + val htrans = Output(UInt(2.W)) + val hwrite = Output(Bool()) + val hrdata = Input(UInt(64.W)) + val hready = Input(Bool()) + val hresp = Input(Bool()) + + // AHB Master + val lsu_haddr = Output(UInt(32.W)) + val lsu_hburst = Output(UInt(3.W)) + val lsu_hmastlock = Output(Bool()) + val lsu_hprot = Output(UInt(4.W)) + val lsu_hsize = Output(UInt(3.W)) + val lsu_htrans = Output(UInt(2.W)) + val lsu_hwrite = Output(Bool()) + val lsu_hwdata = Output(UInt(64.W)) + val lsu_hrdata = Input(UInt(64.W)) + val lsu_hready = Input(Bool()) + val lsu_hresp = Input(Bool()) + + // System Bus Debug Master + val sb_haddr = Output(UInt(32.W)) + val sb_hburst = Output(UInt(3.W)) + val sb_hmastlock = Output(Bool()) + val sb_hprot = Output(UInt(4.W)) + val sb_hsize = Output(UInt(3.W)) + val sb_htrans = Output(UInt(2.W)) + val sb_hwrite = Output(Bool()) + val sb_hwdata = Output(UInt(64.W)) + val sb_hrdata = Input(UInt(64.W)) + val sb_hready = Input(Bool()) + val sb_hresp = Input(Bool()) + + // DMA slave + val dma_hsel = Input(Bool()) + val dma_haddr = Input(UInt(32.W)) + val dma_hburst = Input(UInt(3.W)) + val dma_hmastlock = Input(Bool()) + val dma_hprot = Input(UInt(4.W)) + val dma_hsize = Input(UInt(3.W)) + val dma_htrans = Input(UInt(2.W)) + val dma_hwrite = Input(Bool()) + val dma_hwdata = Input(UInt(64.W)) + val dma_hreadyin = Input(Bool()) + val dma_hrdata = Output(UInt(64.W)) + val dma_hreadyout = Output(Bool()) + val dma_hresp = Output(Bool()) + val lsu_bus_clk_en = Input(Bool()) + val ifu_bus_clk_en = Input(Bool()) + val dbg_bus_clk_en = Input(Bool()) + val dma_bus_clk_en = Input(Bool()) + val dmi_reg_en = Input(Bool()) + val dmi_reg_addr = Input(UInt(7.W)) + val dmi_reg_wr_en = Input(Bool()) + val dmi_reg_wdata = Input(UInt(32.W)) + val dmi_reg_rdata = Output(UInt(32.W)) + val dmi_hard_reset = Input(Bool()) + val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W)) + val timer_int = Input(Bool()) + val soft_int = Input(Bool()) + val scan_mode = Input(Bool()) + }) + + + val ifu = Module(new el2_ifu) + val dec = Module(new el2_dec) + val dbg = Module(new el2_dbg) + val exu = Module(new el2_exu) + val lsu = Module(new el2_lsu) + val pic_ctl_inst = Module(new el2_pic_ctrl) + val dma_ctrl = Module(new el2_dma_ctrl) + val lsu_axi4_to_ahb = Module(new axi4_to_ahb) + val ifu_axi4_to_ahb = Module(new axi4_to_ahb) + val sb_axi4_to_ahb = Module(new axi4_to_ahb) + + val core_reset = (!(reset.asBool() & (dbg.io.dbg_core_rst_l.asBool() | io.scan_mode))).asAsyncReset() + val active_state = (!dec.io.dec_pause_state_cg | dec.io.dec_tlu_flush_lower_r) | dec.io.dec_tlu_misc_clk_override + val free_clk = rvclkhdr(clock, true.B, io.scan_mode) + val active_clk = rvclkhdr(clock, active_state, io.scan_mode) + val core_dbg_cmd_done = dma_ctrl.io.dma_dbg_cmd_done | dec.io.dec_dbg_cmd_done + val core_dbg_cmd_fail = dma_ctrl.io.dma_dbg_cmd_fail | dec.io.dec_dbg_cmd_fail + val core_dbg_rddata = Mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) + + // AHB to AXI-4 still remaining + + + // Lets start with IFU + ifu.reset := core_reset + ifu.io.free_clk := free_clk + ifu.io.active_clk := active_clk + ifu.io.dec_i0_decode_d := dec.io.dec_i0_decode_d + ifu.io.exu_flush_final := dec.io.exu_flush_final + ifu.io.dec_tlu_i0_commit_cmt := dec.io.dec_tlu_i0_commit_cmt + ifu.io.dec_tlu_flush_err_wb := dec.io.dec_tlu_flush_err_r + ifu.io.dec_tlu_flush_noredir_wb := dec.io.dec_tlu_flush_noredir_r + ifu.io.exu_flush_path_final := exu.io.exu_flush_path_final + ifu.io.dec_tlu_mrac_ff := dec.io.dec_tlu_mrac_ff + ifu.io.dec_tlu_fence_i_wb := dec.io.dec_tlu_fence_i_r + ifu.io.dec_tlu_flush_leak_one_wb := dec.io.dec_tlu_flush_leak_one_r + ifu.io.dec_tlu_bpred_disable := dec.io.dec_tlu_bpred_disable + ifu.io.dec_tlu_core_ecc_disable := dec.io.dec_tlu_core_ecc_disable + ifu.io.dec_tlu_force_halt := dec.io.dec_tlu_force_halt + ifu.io.ifu_axi_arready := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_arready) + ifu.io.ifu_axi_rvalid := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_rvalid) + ifu.io.ifu_axi_rid := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_rid) + ifu.io.ifu_axi_rdata := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_rdata) + ifu.io.ifu_axi_rresp := Mux(BUILD_AHB_LITE.B, 0.U, io.ifu_axi_rresp) + ifu.io.ifu_bus_clk_en := io.ifu_bus_clk_en + ifu.io.dma_iccm_req := dma_ctrl.io.dma_iccm_req + ifu.io.dma_mem_addr := dma_ctrl.io.dma_mem_addr + ifu.io.dma_mem_sz := dma_ctrl.io.dma_mem_sz + ifu.io.dma_mem_write := dma_ctrl.io.dma_mem_write + ifu.io.dma_mem_wdata := dma_ctrl.io.dma_mem_wdata + ifu.io.dma_mem_tag := dma_ctrl.io.dma_mem_tag + ifu.io.dma_iccm_stall_any := dma_ctrl.io.dma_iccm_stall_any + ifu.io.ic_rd_data := io.ic_rd_data + ifu.io.ic_debug_rd_data := io.ic_debug_rd_data + ifu.io.ictag_debug_rd_data := io.ictag_debug_rd_data + ifu.io.ic_eccerr := io.ic_eccerr + ifu.io.ic_parerr := io.ic_parerr + ifu.io.ic_rd_hit := io.ic_rd_hit + ifu.io.ic_tag_perr := io.ic_tag_perr + ifu.io.iccm_rd_data := io.iccm_rd_data + ifu.io.exu_mp_pkt <> exu.io.exu_mp_pkt + ifu.io.exu_mp_eghr := exu.io.exu_mp_eghr + ifu.io.exu_mp_fghr := exu.io.exu_mp_fghr + ifu.io.exu_mp_index := exu.io.exu_mp_index + ifu.io.exu_mp_btag := exu.io.exu_mp_btag + ifu.io.dec_tlu_br0_r_pkt <> dec.io.dec_tlu_br0_r_pkt + ifu.io.exu_i0_br_fghr_r := exu.io.exu_i0_br_fghr_r + ifu.io.exu_i0_br_index_r := exu.io.exu_i0_br_index_r + ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_tlu_flush_lower_r + ifu.io.dec_tlu_ic_diag_pkt <> dec.io.dec_tlu_ic_diag_pkt + + // Lets start with Dec + dec.reset := core_reset + dec.io.free_clk := free_clk + dec.io.active_clk := active_clk + dec.io.lsu_fastint_stall_any := lsu.io.lsu_fastint_stall_any + dec.io.rst_vec := io.rst_vec + dec.io.nmi_int := io.nmi_int + dec.io.nmi_vec := io.nmi_vec + dec.io.i_cpu_halt_req := io.i_cpu_halt_req + dec.io.i_cpu_run_req := io.i_cpu_run_req + dec.io.core_id := io.core_id + dec.io.mpc_debug_halt_req := io.mpc_debug_halt_req + dec.io.mpc_debug_run_req := io.mpc_debug_run_req + dec.io.mpc_reset_run_req := io.mpc_reset_run_req + dec.io.exu_pmu_i0_br_misp := exu.io.exu_pmu_i0_br_misp + dec.io.exu_pmu_i0_br_ataken := exu.io.exu_pmu_i0_br_ataken + dec.io.exu_pmu_i0_pc4 := exu.io.exu_pmu_i0_pc4 + dec.io.lsu_nonblock_load_valid_m := lsu.io.lsu_nonblock_load_valid_m + dec.io.lsu_nonblock_load_tag_m := lsu.io.lsu_nonblock_load_tag_m + dec.io.lsu_nonblock_load_inv_r := lsu.io.lsu_nonblock_load_inv_r + dec.io.lsu_nonblock_load_inv_tag_r := lsu.io.lsu_nonblock_load_inv_tag_r + dec.io.lsu_nonblock_load_data_valid := lsu.io.lsu_nonblock_load_data_valid + dec.io.lsu_nonblock_load_data_error := lsu.io.lsu_nonblock_load_data_error + dec.io.lsu_nonblock_load_data_tag := lsu.io.lsu_nonblock_load_data_tag + dec.io.lsu_nonblock_load_data := lsu.io.lsu_nonblock_load_data + dec.io.lsu_pmu_bus_trxn := lsu.io.lsu_pmu_bus_trxn + dec.io.lsu_pmu_bus_misaligned := lsu.io.lsu_pmu_bus_misaligned + dec.io.lsu_pmu_bus_error := lsu.io.lsu_pmu_bus_error + dec.io.lsu_pmu_bus_busy := lsu.io.lsu_pmu_bus_busy + dec.io.lsu_pmu_misaligned_m := lsu.io.lsu_pmu_misaligned_m + dec.io.lsu_pmu_load_external_m := lsu.io.lsu_pmu_load_external_m + dec.io.lsu_pmu_store_external_m := lsu.io.lsu_pmu_store_external_m + dec.io.dma_pmu_dccm_read := dma_ctrl.io.dma_pmu_dccm_read + dec.io.dma_pmu_dccm_write := dma_ctrl.io.dma_pmu_dccm_write + dec.io.dma_pmu_any_read := dma_ctrl.io.dma_pmu_any_read + dec.io.dma_pmu_any_write := dma_ctrl.io.dma_pmu_any_write + dec.io.lsu_fir_addr := lsu.io.lsu_fir_addr + dec.io.lsu_fir_error := lsu.io.lsu_fir_error + dec.io.ifu_pmu_instr_aligned := ifu.io.ifu_pmu_instr_aligned + dec.io.ifu_pmu_fetch_stall := ifu.io.ifu_pmu_fetch_stall + dec.io.ifu_pmu_ic_miss := ifu.io.ifu_pmu_ic_miss + dec.io.ifu_pmu_ic_hit := ifu.io.ifu_pmu_ic_hit + dec.io.ifu_pmu_bus_error := ifu.io.ifu_pmu_bus_error + dec.io.ifu_pmu_bus_busy := ifu.io.ifu_pmu_bus_busy + dec.io.ifu_pmu_bus_trxn := ifu.io.ifu_pmu_bus_trxn + dec.io.ifu_ic_error_start := ifu.io.ifu_ic_error_start + dec.io.ifu_iccm_rd_ecc_single_err := ifu.io.ifu_iccm_rd_ecc_single_err + dec.io.lsu_trigger_match_m := lsu.io.lsu_trigger_match_m + dec.io.dbg_cmd_valid := dbg.io.dbg_cmd_valid + dec.io.dbg_cmd_write := dbg.io.dbg_cmd_write + dec.io.dbg_cmd_type := dbg.io.dbg_cmd_type + dec.io.dbg_cmd_addr := dbg.io.dbg_cmd_addr + dec.io.dbg_cmd_wrdata := dbg.io.dbg_cmd_wrdata + dec.io.ifu_i0_icaf := ifu.io.ifu_i0_icaf + dec.io.ifu_i0_icaf_type := ifu.io.ifu_i0_icaf_type + dec.io.ifu_i0_icaf_f1 := ifu.io.ifu_i0_icaf_f1 + dec.io.ifu_i0_dbecc := ifu.io.ifu_i0_dbecc + dec.io.lsu_idle_any := lsu.io.lsu_idle_any + dec.io.i0_brp := ifu.io.i0_brp + dec.io.ifu_i0_bp_index := ifu.io.ifu_i0_bp_index + dec.io.ifu_i0_bp_fghr := ifu.io.ifu_i0_bp_fghr + dec.io.ifu_i0_bp_btag := ifu.io.ifu_i0_bp_btag + dec.io.lsu_error_pkt_r <> lsu.io.lsu_error_pkt_r + dec.io.lsu_single_ecc_error_incr := lsu.io.lsu_single_ecc_error_incr + dec.io.lsu_imprecise_error_load_any := lsu.io.lsu_imprecise_error_load_any + dec.io.lsu_imprecise_error_store_any := lsu.io.lsu_imprecise_error_store_any + dec.io.lsu_imprecise_error_addr_any := lsu.io.lsu_imprecise_error_addr_any + dec.io.exu_div_result := exu.io.exu_div_result + dec.io.exu_div_wren := exu.io.exu_div_wren + dec.io.exu_csr_rs1_x := exu.io.exu_csr_rs1_x + dec.io.lsu_result_m := lsu.io.lsu_result_m + dec.io.lsu_result_corr_r := lsu.io.lsu_result_corr_r + dec.io.lsu_load_stall_any := lsu.io.lsu_load_stall_any + dec.io.lsu_store_stall_any := lsu.io.lsu_store_stall_any + dec.io.dma_dccm_stall_any := dma_ctrl.io.dma_dccm_stall_any + dec.io.dma_iccm_stall_any := dma_ctrl.io.dma_iccm_stall_any + dec.io.iccm_dma_sb_error := ifu.io.iccm_dma_sb_error + dec.io.exu_flush_final := exu.io.exu_flush_final + dec.io.exu_npc_r := exu.io.exu_npc_r + dec.io.exu_i0_result_x := exu.io.exu_i0_result_x + dec.io.ifu_i0_valid := ifu.io.ifu_i0_valid + dec.io.ifu_i0_instr := ifu.io.ifu_i0_instr + dec.io.ifu_i0_pc := ifu.io.ifu_i0_pc + dec.io.ifu_i0_pc4 := ifu.io.ifu_i0_pc4 + dec.io.exu_i0_pc_x := exu.io.exu_i0_pc_x + dec.io.mexintpend := pic_ctl_inst.io.mexintpend + dec.io.soft_int := io.soft_int + dec.io.pic_claimid := pic_ctl_inst.io.claimid + dec.io.pic_pl := pic_ctl_inst.io.pl + dec.io.mhwakeup := pic_ctl_inst.io.mhwakeup + dec.io.ifu_ic_debug_rd_data := ifu.io.ifu_ic_debug_rd_data + dec.io.ifu_ic_debug_rd_data_valid := ifu.io.ifu_ic_debug_rd_data_valid + dec.io.dbg_halt_req := dbg.io.dbg_halt_req + dec.io.dbg_resume_req := dbg.io.dbg_resume_req + dec.io.ifu_miss_state_idle := ifu.io.ifu_miss_state_idle + dec.io.exu_i0_br_hist_r := exu.io.exu_i0_br_hist_r + dec.io.exu_i0_br_error_r := exu.io.exu_i0_br_error_r + dec.io.exu_i0_br_start_error_r := exu.io.exu_i0_br_start_error_r + dec.io.exu_i0_br_valid_r := exu.io.exu_i0_br_valid_r + dec.io.exu_i0_br_mp_r := exu.io.exu_i0_br_mp_r + dec.io.exu_i0_br_middle_r := exu.io.exu_i0_br_middle_r + dec.io.exu_i0_br_way_r := exu.io.exu_i0_br_way_r + dec.io.ifu_i0_cinst := ifu.io.ifu_i0_cinst + dec.io.scan_mode := io.scan_mode + + // EXU lets go + exu.reset := core_reset + exu.io.scan_mode := io.scan_mode + exu.io.dec_data_en := dec.io.dec_data_en + exu.io.dec_ctl_en := dec.io.dec_ctl_en + exu.io.dbg_cmd_wrdata := dbg.io.dbg_cmd_wrdata + exu.io.i0_ap := dec.io.i0_ap + exu.io.dec_debug_wdata_rs1_d := dec.io.dec_debug_wdata_rs1_d + exu.io.dec_i0_predict_p_d <> dec.io.dec_i0_predict_p_d + exu.io.i0_predict_fghr_d := dec.io.i0_predict_fghr_d + exu.io.i0_predict_index_d := dec.io.i0_predict_index_d + exu.io.i0_predict_btag_d := dec.io.i0_predict_btag_d + exu.io.dec_i0_rs1_en_d := dec.io.dec_i0_rs1_en_d + exu.io.dec_i0_rs2_en_d := dec.io.dec_i0_rs2_en_d + exu.io.gpr_i0_rs1_d := dec.io.gpr_i0_rs1_d + exu.io.gpr_i0_rs2_d := dec.io.gpr_i0_rs2_d + exu.io.dec_i0_immed_d := dec.io.dec_i0_immed_d + exu.io.dec_i0_rs1_bypass_data_d := dec.io.dec_i0_rs1_bypass_data_d + exu.io.dec_i0_rs2_bypass_data_d := dec.io.dec_i0_rs2_bypass_data_d + exu.io.dec_i0_br_immed_d := dec.io.dec_i0_br_immed_d + exu.io.dec_i0_alu_decode_d := dec.io.dec_i0_alu_decode_d + exu.io.dec_i0_select_pc_d := dec.io.dec_i0_select_pc_d + exu.io.dec_i0_pc_d := dec.io.dec_i0_pc_d + exu.io.dec_i0_rs1_bypass_en_d := dec.io.dec_i0_rs1_bypass_en_d + exu.io.dec_i0_rs2_bypass_en_d := dec.io.dec_i0_rs2_bypass_en_d + exu.io.dec_csr_ren_d := dec.io.dec_csr_ren_d + exu.io.mul_p <> dec.io.mul_p + exu.io.div_p <> dec.io.div_p + exu.io.dec_div_cancel := dec.io.dec_div_cancel + exu.io.pred_correct_npc_x := dec.io.pred_correct_npc_x + exu.io.dec_tlu_flush_lower_r := dec.io.dec_tlu_flush_lower_r + exu.io.dec_tlu_flush_path_r := dec.io.dec_tlu_flush_path_r + exu.io.dec_extint_stall := dec.io.dec_extint_stall + exu.io.dec_tlu_meihap := dec.io.dec_tlu_meihap + + + // LSU Lets go + lsu.reset := core_reset + lsu.io.clk_override := dec.io.dec_tlu_lsu_clk_override + lsu.io.dec_tlu_flush_lower_r := dec.io.dec_tlu_flush_lower_r + lsu.io.dec_tlu_i0_kill_writeb_r := dec.io.dec_tlu_i0_kill_writeb_r + lsu.io.dec_tlu_force_halt := dec.io.dec_tlu_force_halt + lsu.io.dec_tlu_external_ldfwd_disable := dec.io.dec_tlu_external_ldfwd_disable + lsu.io.dec_tlu_wb_coalescing_disable := dec.io.dec_tlu_wb_coalescing_disable + lsu.io.dec_tlu_sideeffect_posted_disable := dec.io.dec_tlu_sideeffect_posted_disable + lsu.io.dec_tlu_core_ecc_disable := dec.io.dec_tlu_core_ecc_disable + lsu.io.exu_lsu_rs1_d := exu.io.exu_lsu_rs1_d + lsu.io.exu_lsu_rs2_d := exu.io.exu_lsu_rs2_d + lsu.io.dec_lsu_offset_d := dec.io.dec_lsu_offset_d + lsu.io.lsu_p <> dec.io.lsu_p + lsu.io.dec_lsu_valid_raw_d := dec.io.dec_lsu_valid_raw_d + lsu.io.dec_tlu_mrac_ff := dec.io.dec_tlu_mrac_ff + lsu.io.trigger_pkt_any <> dec.io.trigger_pkt_any + lsu.io.dccm_rd_data_lo := io.dccm_rd_data_lo + lsu.io.dccm_rd_data_hi := io.dccm_rd_data_hi + lsu.io.lsu_axi_awready := io.lsu_axi_awready + lsu.io.lsu_axi_wready := io.lsu_axi_wready + lsu.io.lsu_axi_bvalid := io.lsu_axi_bvalid + lsu.io.lsu_axi_bresp := io.lsu_axi_bresp + lsu.io.lsu_axi_bid := io.lsu_axi_bid + lsu.io.lsu_axi_arready := io.lsu_axi_arready + lsu.io.lsu_axi_rvalid := io.lsu_axi_rvalid + lsu.io.lsu_axi_rid := io.lsu_axi_rid + lsu.io.lsu_axi_rdata := io.lsu_axi_rdata + lsu.io.lsu_axi_rresp := io.lsu_axi_rresp + lsu.io.lsu_axi_rlast := io.lsu_axi_rlast + lsu.io.lsu_bus_clk_en := io.lsu_bus_clk_en + lsu.io.dma_dccm_req := dma_ctrl.io.dma_dccm_req + lsu.io.dma_mem_tag := dma_ctrl.io.dma_mem_tag + lsu.io.dma_mem_addr := dma_ctrl.io.dma_mem_addr + lsu.io.dma_mem_sz := dma_ctrl.io.dma_mem_sz + lsu.io.dma_mem_write := dma_ctrl.io.dma_mem_write + lsu.io.dma_mem_wdata := dma_ctrl.io.dma_mem_wdata + lsu.io.scan_mode := io.scan_mode + lsu.io.free_clk := free_clk + + // Debug lets go + dbg.reset := core_reset + dbg.io.core_dbg_rddata := Mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) + dbg.io.core_dbg_cmd_done := dma_ctrl.io.dma_dbg_cmd_done | dec.io.dec_dbg_cmd_done + dbg.io.core_dbg_cmd_fail := dma_ctrl.io.dma_dbg_cmd_fail | dec.io.dec_dbg_cmd_fail + dbg.io.dma_dbg_ready := dma_ctrl.io.dma_dbg_ready + dbg.io.dec_tlu_debug_mode := dec.io.dec_tlu_debug_mode + dbg.io.dec_tlu_dbg_halted := dec.io.dec_tlu_dbg_halted + dbg.io.dec_tlu_mpc_halted_only := dec.io.dec_tlu_mpc_halted_only + dbg.io.dec_tlu_resume_ack := dec.io.dec_tlu_resume_ack + dbg.io.dmi_reg_en := io.dmi_reg_en + dbg.io.dmi_reg_addr := io.dmi_reg_addr + dbg.io.dmi_reg_wr_en := io.dmi_reg_wr_en + dbg.io.dmi_reg_wdata := io.dmi_reg_wdata + dbg.io.sb_axi_awready := io.sb_axi_awready + dbg.io.sb_axi_wready := io.sb_axi_wready + dbg.io.sb_axi_bvalid := io.sb_axi_bvalid + dbg.io.sb_axi_bresp := io.sb_axi_bresp + dbg.io.sb_axi_arready := io.sb_axi_arready + dbg.io.sb_axi_rvalid := io.sb_axi_rvalid + dbg.io.sb_axi_rdata := io.sb_axi_rdata + dbg.io.sb_axi_rresp := io.sb_axi_rresp + dbg.io.dbg_bus_clk_en := io.dbg_bus_clk_en + dbg.io.dbg_rst_l := io.dbg_rst_l + dbg.io.clk_override := dec.io.dec_tlu_misc_clk_override + dbg.io.scan_mode := io.scan_mode + + + // DMA Lets go + dma_ctrl.reset := core_reset + dma_ctrl.io.free_clk := free_clk + dma_ctrl.io.dma_bus_clk_en := io.dma_bus_clk_en + dma_ctrl.io.clk_override := dec.io.dec_tlu_misc_clk_override + dma_ctrl.io.scan_mode := io.scan_mode + dma_ctrl.io.dbg_cmd_addr := dbg.io.dbg_cmd_addr + dma_ctrl.io.dbg_cmd_wrdata := dbg.io.dbg_cmd_wrdata + dma_ctrl.io.dbg_cmd_valid := dbg.io.dbg_cmd_valid + dma_ctrl.io.dbg_cmd_write := dbg.io.dbg_cmd_write + dma_ctrl.io.dbg_cmd_type := dbg.io.dbg_cmd_type + dma_ctrl.io.dbg_cmd_size := dbg.io.dbg_cmd_size + dma_ctrl.io.dbg_dma_bubble := dbg.io.dbg_dma_bubble + dma_ctrl.io.dccm_dma_rvalid := lsu.io.dccm_dma_rvalid + dma_ctrl.io.dccm_dma_ecc_error := lsu.io.dccm_dma_ecc_error + dma_ctrl.io.dccm_dma_rtag := lsu.io.dccm_dma_rtag + dma_ctrl.io.dccm_dma_rdata := lsu.io.dccm_dma_rdata + dma_ctrl.io.iccm_dma_rvalid := ifu.io.iccm_dma_rvalid + dma_ctrl.io.iccm_dma_rtag := ifu.io.iccm_dma_rtag + dma_ctrl.io.iccm_dma_rdata := ifu.io.iccm_dma_rdata + dma_ctrl.io.dccm_ready := lsu.io.dccm_ready + dma_ctrl.io.iccm_ready := ifu.io.iccm_ready + dma_ctrl.io.dec_tlu_dma_qos_prty := dec.io.dec_tlu_dma_qos_prty + dma_ctrl.io.dma_axi_awvalid := io.dma_axi_awvalid + dma_ctrl.io.dma_axi_awid := io.dma_axi_awid + dma_ctrl.io.dma_axi_awaddr := io.dma_axi_awaddr + dma_ctrl.io.dma_axi_awsize := io.dma_axi_awsize + dma_ctrl.io.dma_axi_wvalid := io.dma_axi_wvalid + dma_ctrl.io.dma_axi_wdata := io.dma_axi_wdata + dma_ctrl.io.dma_axi_wstrb := io.dma_axi_wstrb + dma_ctrl.io.dma_axi_bready := io.dma_axi_bready + dma_ctrl.io.dma_axi_arvalid := io.dma_axi_arvalid + dma_ctrl.io.dma_axi_arid := io.dma_axi_arid + dma_ctrl.io.dma_axi_araddr := io.dma_axi_araddr + dma_ctrl.io.dma_axi_arsize := io.dma_axi_arsize + dma_ctrl.io.dma_axi_rready := io.dma_axi_rready + + + // PIC lets go + pic_ctl_inst.reset := core_reset + pic_ctl_inst.io.free_clk := free_clk + pic_ctl_inst.io.active_clk := active_clk + pic_ctl_inst.io.clk_override := dec.io.dec_tlu_pic_clk_override + pic_ctl_inst.io.extintsrc_req := io.extintsrc_req + pic_ctl_inst.io.picm_rdaddr := lsu.io.picm_rdaddr + pic_ctl_inst.io.picm_wraddr := lsu.io.picm_wraddr + pic_ctl_inst.io.picm_wr_data := lsu.io.picm_wr_data + pic_ctl_inst.io.picm_wren := lsu.io.picm_wren + pic_ctl_inst.io.picm_rden := lsu.io.picm_rden + pic_ctl_inst.io.picm_mken := lsu.io.picm_mken + pic_ctl_inst.io.meicurpl := dec.io.dec_tlu_meicurpl + pic_ctl_inst.io.meipt := dec.io.dec_tlu_meipt + + + + + + + +} diff --git a/src/main/scala/exu/el2_exu.scala b/src/main/scala/exu/el2_exu.scala index baa0e58e..e8834794 100644 --- a/src/main/scala/exu/el2_exu.scala +++ b/src/main/scala/exu/el2_exu.scala @@ -1,5 +1,295 @@ package exu +import chisel3._ +import scala.collection._ +import chisel3.util._ +import include._ +import lib._ -class el2_exu { +class el2_exu extends Module with el2_lib with RequireAsyncReset{ + val io=IO(new el2_exu_IO) + val PREDPIPESIZE = BTB_ADDR_HI - BTB_ADDR_LO + BHT_GHR_SIZE + BTB_BTAG_SIZE +1 + val ghr_x_ns = Wire(UInt(BHT_GHR_SIZE.W)) + val ghr_d_ns = Wire(UInt(BHT_GHR_SIZE.W)) + val ghr_d = Wire(UInt(BHT_GHR_SIZE.W)) + val i0_taken_d =Wire(UInt(1.W)) + val mul_valid_x =Wire(UInt(1.W)) + val i0_valid_d =Wire(UInt(1.W)) + val flush_lower_ff =Wire(UInt(1.W)) + val data_gate_en =Wire(UInt(1.W)) + val csr_rs1_in_d =Wire(UInt(32.W)) + val i0_predict_newp_d =Wire(new el2_predict_pkt_t) + val i0_flush_path_d =Wire(UInt(32.W)) + val i0_predict_p_d =Wire(new el2_predict_pkt_t) + val i0_pp_r =Wire(new el2_predict_pkt_t) + val i0_predict_p_x =Wire(new el2_predict_pkt_t) + val final_predict_mp =Wire(new el2_predict_pkt_t) + val pred_correct_npc_r =Wire(UInt(32.W)) + val i0_pred_correct_upper_d =Wire(UInt(1.W)) + val i0_flush_upper_d =Wire(UInt(1.W)) + io.exu_mp_pkt.prett :=0.U + io.exu_mp_pkt.br_start_error:=0.U + io.exu_mp_pkt.br_error :=0.U + io.exu_mp_pkt.valid :=0.U + val x_data_en = io.dec_data_en(1) + val r_data_en = io.dec_data_en(0) + val x_ctl_en = io.dec_ctl_en(1) + val r_ctl_en = io.dec_ctl_en(0) + val predpipe_d = Cat(io.i0_predict_fghr_d, io.i0_predict_index_d, io.i0_predict_btag_d) + + val i0_flush_path_x =rvdffe(i0_flush_path_d,x_data_en.asBool,clock,io.scan_mode) + io.exu_csr_rs1_x :=rvdffe(csr_rs1_in_d,x_data_en.asBool,clock,io.scan_mode) + i0_predict_p_x :=rvdffe(i0_predict_p_d,x_data_en.asBool,clock,io.scan_mode) + val predpipe_x =rvdffe(predpipe_d,x_data_en.asBool,clock,io.scan_mode) + val predpipe_r =rvdffe(predpipe_x ,r_data_en.asBool,clock,io.scan_mode) + val ghr_x =rvdffe(ghr_x_ns ,x_ctl_en.asBool,clock,io.scan_mode) + val i0_pred_correct_upper_x =rvdffe(i0_pred_correct_upper_d ,x_ctl_en.asBool,clock,io.scan_mode) + val i0_flush_upper_x =rvdffe(i0_flush_upper_d ,x_ctl_en.asBool,clock,io.scan_mode) + val i0_taken_x =rvdffe(i0_taken_d ,x_ctl_en.asBool,clock,io.scan_mode) + val i0_valid_x =rvdffe(i0_valid_d ,x_ctl_en.asBool,clock,io.scan_mode) + i0_pp_r :=rvdffe(i0_predict_p_x,r_ctl_en.asBool,clock,io.scan_mode) + val pred_temp1 =rvdffe(io.pred_correct_npc_x(5,0) ,r_ctl_en.asBool,clock,io.scan_mode) + val i0_pred_correct_upper_r =rvdffe(i0_pred_correct_upper_x ,r_ctl_en.asBool,clock,io.scan_mode) + val i0_flush_path_upper_r =rvdffe(i0_flush_path_x ,r_data_en.asBool,clock,io.scan_mode) + val pred_temp2 =rvdffe(io.pred_correct_npc_x(30,6) ,r_data_en.asBool,clock,io.scan_mode) + pred_correct_npc_r :=Cat(pred_temp2,pred_temp1) + + when (BHT_SIZE.asUInt===32.U || BHT_SIZE.asUInt===64.U){ + ghr_d :=RegEnable(ghr_d_ns,0.U,data_gate_en.asBool) + mul_valid_x :=RegEnable(io.mul_p.valid,0.U,data_gate_en.asBool) + flush_lower_ff :=RegEnable(io.dec_tlu_flush_lower_r,0.U,data_gate_en.asBool) + }.otherwise{ + ghr_d :=rvdffe(ghr_d_ns ,data_gate_en.asBool,clock,io.scan_mode) + mul_valid_x :=rvdffe(io.mul_p.valid ,data_gate_en.asBool,clock,io.scan_mode) + flush_lower_ff :=rvdffe(io.dec_tlu_flush_lower_r ,data_gate_en.asBool,clock,io.scan_mode) + } + + + data_gate_en := (ghr_d_ns =/= ghr_d) | ( io.mul_p.valid =/= mul_valid_x) | ( io.dec_tlu_flush_lower_r =/= flush_lower_ff) + val i0_rs1_bypass_en_d = io.dec_i0_rs1_bypass_en_d(0) | io.dec_i0_rs1_bypass_en_d(1) + val i0_rs2_bypass_en_d = io.dec_i0_rs2_bypass_en_d(0) | io.dec_i0_rs2_bypass_en_d(1) + + val i0_rs1_bypass_data_d = Mux1H(Seq( + io.dec_i0_rs1_bypass_en_d(0).asBool -> io.dec_i0_rs1_bypass_data_d, + io.dec_i0_rs1_bypass_en_d(1).asBool -> io.exu_i0_result_x + )) + + val i0_rs2_bypass_data_d = Mux1H(Seq( + io.dec_i0_rs2_bypass_en_d(0).asBool -> io.dec_i0_rs2_bypass_data_d, + io.dec_i0_rs2_bypass_en_d(1).asBool -> io.exu_i0_result_x + )) + + val i0_rs1_d = Mux1H(Seq( + i0_rs1_bypass_en_d.asBool -> i0_rs1_bypass_data_d, + (~i0_rs1_bypass_en_d & io.dec_i0_select_pc_d).asBool -> Cat(io.dec_i0_pc_d,0.U(1.W)), + (~i0_rs1_bypass_en_d & io.dec_debug_wdata_rs1_d).asBool -> io.dbg_cmd_wrdata, + (~i0_rs1_bypass_en_d & ~io.dec_debug_wdata_rs1_d & io.dec_i0_rs1_en_d).asBool -> io.gpr_i0_rs1_d + )) + + val i0_rs2_d=Mux1H(Seq( + (~i0_rs2_bypass_en_d & io.dec_i0_rs2_en_d).asBool -> io.gpr_i0_rs2_d, + (~i0_rs2_bypass_en_d).asBool -> io.dec_i0_immed_d, + (i0_rs2_bypass_en_d).asBool -> i0_rs2_bypass_data_d + )) + + io.exu_lsu_rs1_d:=Mux1H(Seq( + (~i0_rs1_bypass_en_d & ~io.dec_extint_stall & io.dec_i0_rs1_en_d).asBool -> io.gpr_i0_rs1_d, + (i0_rs1_bypass_en_d & ~io.dec_extint_stall).asBool -> i0_rs1_bypass_data_d, + (io.dec_extint_stall).asBool -> Cat(io.dec_tlu_meihap,0.U(2.W)) + )) + + io.exu_lsu_rs2_d:=Mux1H(Seq( + (~i0_rs2_bypass_en_d & ~io.dec_extint_stall & io.dec_i0_rs2_en_d).asBool -> io.gpr_i0_rs2_d, + (i0_rs2_bypass_en_d & ~io.dec_extint_stall).asBool -> i0_rs2_bypass_data_d + )) + + val muldiv_rs1_d=Mux1H(Seq( + (~i0_rs1_bypass_en_d & io.dec_i0_rs1_en_d).asBool -> io.gpr_i0_rs1_d, + (i0_rs1_bypass_en_d).asBool -> i0_rs1_bypass_data_d + )) + + val muldiv_rs2_d=Mux1H(Seq( + (~i0_rs2_bypass_en_d & io.dec_i0_rs2_en_d).asBool -> io.gpr_i0_rs2_d, + (~i0_rs2_bypass_en_d).asBool -> io.dec_i0_immed_d, + (i0_rs2_bypass_en_d).asBool -> i0_rs2_bypass_data_d + )) + + csr_rs1_in_d := Mux( io.dec_csr_ren_d.asBool, i0_rs1_d, io.exu_csr_rs1_x) + + + val i_alu=Module(new el2_exu_alu_ctl) + i_alu.io.scan_mode :=io.scan_mode + i_alu.io.enable :=x_ctl_en + i_alu.io.pp_in :=i0_predict_newp_d + i_alu.io.valid_in :=io.dec_i0_alu_decode_d + i_alu.io.flush_upper_x :=i0_flush_upper_x + i_alu.io.flush_lower_r :=io.dec_tlu_flush_lower_r + i_alu.io.a_in :=i0_rs1_d.asSInt + i_alu.io.b_in :=i0_rs2_d + i_alu.io.pc_in :=io.dec_i0_pc_d + i_alu.io.brimm_in :=io.dec_i0_br_immed_d + i_alu.io.ap :=io.i0_ap + i_alu.io.csr_ren_in :=io.dec_csr_ren_d + val alu_result_x =i_alu.io.result_ff + i0_flush_upper_d :=i_alu.io.flush_upper_out + io.exu_flush_final :=i_alu.io.flush_final_out + i0_flush_path_d :=i_alu.io.flush_path_out + i0_predict_p_d :=i_alu.io.predict_p_out + i0_pred_correct_upper_d :=i_alu.io.pred_correct_out + io.exu_i0_pc_x :=i_alu.io.pc_ff + + val i_mul=Module(new el2_exu_mul_ctl) + i_mul.io.scan_mode :=io.scan_mode + i_mul.io.mul_p :=io.mul_p + i_mul.io.rs1_in :=muldiv_rs1_d + i_mul.io.rs2_in :=muldiv_rs2_d + val mul_result_x =i_mul.io.result_x + + val i_div=Module(new el2_exu_div_ctl) + i_div.io.scan_mode :=io.scan_mode + i_div.io.cancel :=io.dec_div_cancel + i_div.io.dp :=io.div_p + i_div.io.dividend :=muldiv_rs1_d + i_div.io.divisor :=muldiv_rs2_d + io.exu_div_wren :=i_div.io.finish_dly + io.exu_div_result :=i_div.io.out + + io.exu_i0_result_x := Mux(mul_valid_x.asBool, mul_result_x, alu_result_x) + i0_predict_newp_d := io.dec_i0_predict_p_d + i0_predict_newp_d.boffset := io.dec_i0_pc_d(0) // from the start of inst + + io.exu_pmu_i0_br_misp := i0_pp_r.misp + io.exu_pmu_i0_br_ataken := i0_pp_r.ataken + io.exu_pmu_i0_pc4 := i0_pp_r.pc4 + + + i0_valid_d := i0_predict_p_d.valid & io.dec_i0_alu_decode_d & ~io.dec_tlu_flush_lower_r + i0_taken_d := (i0_predict_p_d.ataken & io.dec_i0_alu_decode_d) + + + + // maintain GHR at D + ghr_d_ns:=Mux1H(Seq( + (~io.dec_tlu_flush_lower_r & i0_valid_d).asBool -> Cat(ghr_d(BHT_GHR_SIZE-2,0),i0_taken_d), + (~io.dec_tlu_flush_lower_r & ~i0_valid_d).asBool -> ghr_d, + (io.dec_tlu_flush_lower_r).asBool -> ghr_x + )) + + // maintain GHR at X + ghr_x_ns:=Mux(i0_valid_x===1.U, Cat(ghr_x(BHT_GHR_SIZE-2,0),i0_taken_x), ghr_x ) + + io.exu_i0_br_valid_r := i0_pp_r.valid + io.exu_i0_br_mp_r := i0_pp_r.misp + io.exu_i0_br_way_r := i0_pp_r.way + io.exu_i0_br_hist_r := i0_pp_r.hist + io.exu_i0_br_error_r := i0_pp_r.br_error + io.exu_i0_br_middle_r := i0_pp_r.pc4 ^ i0_pp_r.boffset + io.exu_i0_br_start_error_r := i0_pp_r.br_start_error + io.exu_i0_br_fghr_r := predpipe_r(PREDPIPESIZE-1,BTB_ADDR_HI+BTB_BTAG_SIZE-BTB_ADDR_LO+1) + io.exu_i0_br_index_r := predpipe_r(BTB_ADDR_HI+BTB_BTAG_SIZE-BTB_ADDR_LO,BTB_BTAG_SIZE) + final_predict_mp := Mux(i0_flush_upper_x===1.U,i0_predict_p_x,0.U.asTypeOf(i0_predict_p_x)) + val final_predpipe_mp = Mux(i0_flush_upper_x===1.U,predpipe_x,0.U) + + val after_flush_eghr = Mux((i0_flush_upper_x===1.U & ~(io.dec_tlu_flush_lower_r===1.U)), ghr_d, ghr_x) + + + io.exu_mp_pkt.way := final_predict_mp.way + io.exu_mp_pkt.misp := final_predict_mp.misp + io.exu_mp_pkt.pcall := final_predict_mp.pcall + io.exu_mp_pkt.pja := final_predict_mp.pja + io.exu_mp_pkt.pret := final_predict_mp.pret + io.exu_mp_pkt.ataken := final_predict_mp.ataken + io.exu_mp_pkt.boffset := final_predict_mp.boffset + io.exu_mp_pkt.pc4 := final_predict_mp.pc4 + io.exu_mp_pkt.hist := final_predict_mp.hist(1,0) + io.exu_mp_pkt.toffset := final_predict_mp.toffset(11,0) + io.exu_mp_fghr := after_flush_eghr + io.exu_mp_index := final_predpipe_mp(PREDPIPESIZE-BHT_GHR_SIZE-1,BTB_BTAG_SIZE) + io.exu_mp_btag := final_predpipe_mp(BTB_BTAG_SIZE-1,0) + io.exu_mp_eghr := final_predpipe_mp(PREDPIPESIZE-1,BTB_ADDR_HI-BTB_ADDR_LO+BTB_BTAG_SIZE+1) // mp ghr for bht write + io.exu_flush_path_final := Mux(io.dec_tlu_flush_lower_r.asBool, io.dec_tlu_flush_path_r, i0_flush_path_d) + io.exu_npc_r := Mux(i0_pred_correct_upper_r===1.U, pred_correct_npc_r, i0_flush_path_upper_r) } +class el2_exu_IO extends Bundle with param{ + val scan_mode =Input(Bool()) // Scan control + + val dec_data_en =Input(UInt(2.W)) // Clock enable {x,r}, one cycle pulse + val dec_ctl_en =Input(UInt(2.W)) // Clock enable {x,r}, two cycle pulse + val dbg_cmd_wrdata =Input(UInt(32.W)) // Debug data to primary I0 RS1 + val i0_ap =Input(new el2_alu_pkt_t) // DEC alu {valid,predecodes} + + val dec_debug_wdata_rs1_d =Input(UInt(1.W)) // Debug select to primary I0 RS1 + val dec_i0_predict_p_d =Input(new el2_predict_pkt_t) // DEC branch predict packet + + val i0_predict_fghr_d =Input(UInt(BHT_GHR_SIZE.W)) // DEC predict fghr + val i0_predict_index_d =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // DEC predict index + val i0_predict_btag_d =Input(UInt(BTB_BTAG_SIZE.W)) // DEC predict branch tag + + val dec_i0_rs1_en_d =Input(UInt(1.W)) // Qualify GPR RS1 data + val dec_i0_rs2_en_d =Input(UInt(1.W)) // Qualify GPR RS2 data + val gpr_i0_rs1_d =Input(UInt(32.W)) // DEC data gpr + val gpr_i0_rs2_d =Input(UInt(32.W)) // DEC data gpr + val dec_i0_immed_d =Input(UInt(32.W)) // DEC data immediate + val dec_i0_rs1_bypass_data_d=Input(UInt(32.W)) // DEC bypass data + val dec_i0_rs2_bypass_data_d=Input(UInt(32.W)) // DEC bypass data + val dec_i0_br_immed_d =Input(UInt(12.W)) // Branch immediate + val dec_i0_alu_decode_d =Input(UInt(1.W)) // Valid to X-stage ALU + val dec_i0_select_pc_d =Input(UInt(1.W)) // PC select to RS1 + val dec_i0_pc_d =Input(UInt(31.W)) // Instruction PC + val dec_i0_rs1_bypass_en_d =Input(UInt(2.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data + val dec_i0_rs2_bypass_en_d =Input(UInt(2.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data + val dec_csr_ren_d =Input(UInt(1.W)) // Clear I0 RS1 primary + + val mul_p =Input(new el2_mul_pkt_t) // DEC {valid, operand signs, low, operand bypass} + val div_p =Input(new el2_div_pkt_t) // DEC {valid, unsigned, rem} + val dec_div_cancel =Input(UInt(1.W)) // Cancel the divide operation + + val pred_correct_npc_x =Input(UInt(31.W)) // DEC NPC for correctly predicted branch + + val dec_tlu_flush_lower_r =Input(UInt(1.W)) // Flush divide and secondary ALUs + val dec_tlu_flush_path_r =Input(UInt(31.W)) // Redirect target + + + val dec_extint_stall =Input(UInt(1.W)) // External stall mux select + val dec_tlu_meihap =Input(UInt(30.W)) // External stall mux data + + + val exu_lsu_rs1_d =Output(UInt(32.W)) // LSU operand + val exu_lsu_rs2_d =Output(UInt(32.W)) // LSU operand + + val exu_flush_final =Output(UInt(1.W)) // Pipe is being flushed this cycle + val exu_flush_path_final =Output(UInt(31.W)) // Target for the oldest flush source + + val exu_i0_result_x =Output(UInt(32.W)) // Primary ALU result to DEC + val exu_i0_pc_x =Output(UInt(31.W)) // Primary PC result to DEC + val exu_csr_rs1_x =Output(UInt(32.W)) // RS1 source for a CSR instruction + + val exu_npc_r =Output(UInt(31.W)) // Divide NPC + val exu_i0_br_hist_r =Output(UInt(2.W)) // to DEC I0 branch history + val exu_i0_br_error_r =Output(UInt(1.W)) // to DEC I0 branch error + val exu_i0_br_start_error_r =Output(UInt(1.W)) // to DEC I0 branch start error + val exu_i0_br_index_r =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // to DEC I0 branch index + val exu_i0_br_valid_r =Output(UInt(1.W)) // to DEC I0 branch valid + val exu_i0_br_mp_r =Output(UInt(1.W)) // to DEC I0 branch mispredict + val exu_i0_br_middle_r =Output(UInt(1.W)) // to DEC I0 branch middle + val exu_i0_br_fghr_r =Output(UInt(BHT_GHR_SIZE.W)) // to DEC I0 branch fghr + val exu_i0_br_way_r =Output(UInt(1.W)) // to DEC I0 branch way + val exu_mp_pkt =Output(new el2_predict_pkt_t) // Mispredict branch packet + val exu_mp_eghr =Output(UInt(BHT_GHR_SIZE.W)) // Mispredict global history + val exu_mp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // Mispredict fghr + val exu_mp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // Mispredict index + val exu_mp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // Mispredict btag + + + val exu_pmu_i0_br_misp =Output(UInt(1.W)) // to PMU - I0 E4 branch mispredict + val exu_pmu_i0_br_ataken =Output(UInt(1.W)) // to PMU - I0 E4 taken + val exu_pmu_i0_pc4 =Output(UInt(1.W)) // to PMU - I0 E4 PC + + + val exu_div_result =Output(UInt(32.W)) // Divide result + val exu_div_wren =Output(UInt(1.W)) // Divide write enable to GPR +} + +object exu_gen extends App{ + println(chisel3.Driver.emitVerilog(new el2_exu())) +} \ No newline at end of file diff --git a/src/main/scala/ifu/el2_ifu_mem_ctl.scala b/src/main/scala/ifu/el2_ifu_mem_ctl.scala index 26487551..f929f130 100644 --- a/src/main/scala/ifu/el2_ifu_mem_ctl.scala +++ b/src/main/scala/ifu/el2_ifu_mem_ctl.scala @@ -59,6 +59,8 @@ class mem_ctl_bundle extends Bundle with el2_lib{ val ifu_pmu_bus_error = Output(Bool()) val ifu_pmu_bus_busy = Output(Bool()) val ifu_pmu_bus_trxn = Output(Bool()) + + val ifu_axi_awvalid = Output(Bool()) val ifu_axi_awid = Output(UInt(IFU_BUS_TAG.W)) val ifu_axi_awaddr = Output(UInt(32.W)) diff --git a/src/main/scala/lsu/el2_lsu.scala b/src/main/scala/lsu/el2_lsu.scala index 464f487c..df44aa56 100644 --- a/src/main/scala/lsu/el2_lsu.scala +++ b/src/main/scala/lsu/el2_lsu.scala @@ -27,8 +27,8 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib { val dec_tlu_mrac_ff = Input(UInt(32.W)) //Outputs - // val lsu_result_m = Output(UInt(32.W)) - // val lsu_result_corr_r = Output(UInt(32.W)) + val lsu_result_m = Output(UInt(32.W)) + val lsu_result_corr_r = Output(UInt(32.W)) val lsu_load_stall_any = Output(Bool()) val lsu_store_stall_any = Output(Bool()) val lsu_fastint_stall_any = Output(Bool()) @@ -152,6 +152,8 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib { val lsu_raw_fwd_hi_r = WireInit(0.U(1.W)) val lsu_lsc_ctl = Module(new el2_lsu_lsc_ctl ) + io.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m + io.lsu_result_corr_r := lsu_lsc_ctl.io.lsu_result_corr_r val dccm_ctl = Module(new el2_lsu_dccm_ctl ) val stbuf = Module(new el2_lsu_stbuf ) val ecc = Module(new el2_lsu_ecc ) diff --git a/src/main/scala/lsu/el2_lsu_bus_buffer.scala b/src/main/scala/lsu/el2_lsu_bus_buffer.scala index 79298622..1d443200 100644 --- a/src/main/scala/lsu/el2_lsu_bus_buffer.scala +++ b/src/main/scala/lsu/el2_lsu_bus_buffer.scala @@ -40,7 +40,6 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib { val ldst_dual_m = Input(Bool()) val ldst_dual_r = Input(Bool()) val ldst_byteen_ext_m = Input(UInt(8.W)) - val lsu_axi_awready = Input(Bool()) val lsu_axi_wready = Input(Bool()) val lsu_axi_bvalid = Input(Bool()) val lsu_axi_bresp = Input(UInt(2.W)) @@ -77,7 +76,10 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib { val lsu_pmu_bus_misaligned = Output(Bool()) val lsu_pmu_bus_error = Output(Bool()) val lsu_pmu_bus_busy = Output(Bool()) + + // AXI Signals val lsu_axi_awvalid = Output(Bool()) + val lsu_axi_awready = Input(Bool()) val lsu_axi_awid = Output(UInt(LSU_BUS_TAG.W)) val lsu_axi_awaddr = Output(UInt(32.W)) val lsu_axi_awregion = Output(UInt(4.W)) diff --git a/target/scala-2.12/classes/dma/dma$.class b/target/scala-2.12/classes/dma$.class similarity index 57% rename from target/scala-2.12/classes/dma/dma$.class rename to target/scala-2.12/classes/dma$.class index b1b1a1bb..431b77b0 100644 Binary files a/target/scala-2.12/classes/dma/dma$.class and b/target/scala-2.12/classes/dma$.class differ diff --git a/target/scala-2.12/classes/dma$delayedInit$body.class b/target/scala-2.12/classes/dma$delayedInit$body.class new file mode 100644 index 00000000..812c0307 Binary files /dev/null and b/target/scala-2.12/classes/dma$delayedInit$body.class differ diff --git a/target/scala-2.12/classes/dma/dma.class b/target/scala-2.12/classes/dma.class similarity index 52% rename from target/scala-2.12/classes/dma/dma.class rename to target/scala-2.12/classes/dma.class index 47f0203c..d9d90c62 100644 Binary files a/target/scala-2.12/classes/dma/dma.class and b/target/scala-2.12/classes/dma.class differ diff --git a/target/scala-2.12/classes/dma/dma$delayedInit$body.class b/target/scala-2.12/classes/dma/dma$delayedInit$body.class deleted file mode 100644 index fb7cf7a0..00000000 Binary files a/target/scala-2.12/classes/dma/dma$delayedInit$body.class and /dev/null differ diff --git a/target/scala-2.12/classes/dma/el2_dma_ctrl$$anon$1.class b/target/scala-2.12/classes/dma/el2_dma_ctrl$$anon$1.class deleted file mode 100644 index d060ff4a..00000000 Binary files a/target/scala-2.12/classes/dma/el2_dma_ctrl$$anon$1.class and /dev/null differ diff --git a/target/scala-2.12/classes/el2_dma_ctrl$$anon$1.class b/target/scala-2.12/classes/el2_dma_ctrl$$anon$1.class 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differ diff --git a/target/scala-2.12/classes/exu/el2_exu.class b/target/scala-2.12/classes/exu/el2_exu.class index 783b5e0a..3a86c255 100644 Binary files a/target/scala-2.12/classes/exu/el2_exu.class and b/target/scala-2.12/classes/exu/el2_exu.class differ diff --git a/target/scala-2.12/classes/exu/el2_exu_IO.class b/target/scala-2.12/classes/exu/el2_exu_IO.class new file mode 100644 index 00000000..0c53d7f8 Binary files /dev/null and b/target/scala-2.12/classes/exu/el2_exu_IO.class differ diff --git a/target/scala-2.12/classes/exu/exu_gen$.class b/target/scala-2.12/classes/exu/exu_gen$.class new file mode 100644 index 00000000..3c1b8f41 Binary files /dev/null and b/target/scala-2.12/classes/exu/exu_gen$.class differ diff --git a/target/scala-2.12/classes/exu/exu_gen$delayedInit$body.class b/target/scala-2.12/classes/exu/exu_gen$delayedInit$body.class new file mode 100644 index 00000000..75a02a88 Binary files /dev/null and b/target/scala-2.12/classes/exu/exu_gen$delayedInit$body.class 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