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This commit is contained in:
waleed-lm 2020-12-18 18:05:45 +05:00
parent 12a696944d
commit db3d66663a
444 changed files with 190212 additions and 132043 deletions
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3
.idea/.gitignore vendored
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# Default ignored files
/shelf/
/workspace.xml

7
.idea/codeStyles/Project.xml
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<component name="ProjectCodeStyleConfiguration">
<code_scheme name="Project" version="173">
<ScalaCodeStyleSettings>
<option name="MULTILINE_STRING_CLOSING_QUOTES_ON_NEW_LINE" value="true" />
</ScalaCodeStyleSettings>
</code_scheme>
</component>

5
.idea/codeStyles/codeStyleConfig.xml
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<component name="ProjectCodeStyleConfiguration">
<state>
<option name="PREFERRED_PROJECT_CODE_STYLE" value="Default" />
</state>
</component>

8
.idea/compiler.xml
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<?xml version="1.0" encoding="UTF-8"?>
<project version="4">
<component name="CompilerConfiguration">
<bytecodeTargetLevel target="1.8">
<module name="Quasar" target="1.8" />
</bytecodeTargetLevel>
</component>
</project>

13
.idea/libraries/sbt__com_github_nscala_time_nscala_time_2_12_2_22_0_jar.xml
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<component name="libraryTable">
<library name="sbt: com.github.nscala-time:nscala-time_2.12:2.22.0:jar">
<CLASSES>
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13
.idea/libraries/sbt__com_github_scopt_scopt_2_12_3_7_1_jar.xml
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<component name="libraryTable">
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13
.idea/libraries/sbt__com_google_protobuf_protobuf_java_3_9_0_jar.xml
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13
.idea/libraries/sbt__com_lihaoyi_utest_2_12_0_6_6_jar.xml
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@ -1,13 +0,0 @@
<component name="libraryTable">
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13
.idea/libraries/sbt__com_thoughtworks_paranamer_paranamer_2_8_jar.xml
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@ -1,13 +0,0 @@
<component name="libraryTable">
<library name="sbt: com.thoughtworks.paranamer:paranamer:2.8:jar">
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13
.idea/libraries/sbt__edu_berkeley_cs_chisel3_2_12_3_3_1_jar.xml
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@ -1,13 +0,0 @@
<component name="libraryTable">
<library name="sbt: edu.berkeley.cs:chisel3_2.12:3.3.1:jar">
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13
.idea/libraries/sbt__edu_berkeley_cs_chisel3_core_2_12_3_3_1_jar.xml
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@ -1,13 +0,0 @@
<component name="libraryTable">
<library name="sbt: edu.berkeley.cs:chisel3-core_2.12:3.3.1:jar">
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13
.idea/libraries/sbt__edu_berkeley_cs_chisel3_macros_2_12_3_3_1_jar.xml
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@ -1,13 +0,0 @@
<component name="libraryTable">
<library name="sbt: edu.berkeley.cs:chisel3-macros_2.12:3.3.1:jar">
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<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar!/" />
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<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1-javadoc.jar!/" />
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13
.idea/libraries/sbt__edu_berkeley_cs_chisel_iotesters_2_12_1_4_1_jar.xml
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@ -1,13 +0,0 @@
<component name="libraryTable">
<library name="sbt: edu.berkeley.cs:chisel-iotesters_2.12:1.4.1:jar">
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</library>
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13
.idea/libraries/sbt__edu_berkeley_cs_chiseltest_2_12_0_2_1_jar.xml
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@ -1,13 +0,0 @@
<component name="libraryTable">
<library name="sbt: edu.berkeley.cs:chiseltest_2.12:0.2.1:jar">
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<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar!/" />
</CLASSES>
<JAVADOC>
<root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1-javadoc.jar!/" />
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</SOURCES>
</library>
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13
.idea/libraries/sbt__edu_berkeley_cs_firrtl_2_12_1_3_1_jar.xml
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@ -1,13 +0,0 @@
<component name="libraryTable">
<library name="sbt: edu.berkeley.cs:firrtl_2.12:1.3.1:jar">
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13
.idea/libraries/sbt__edu_berkeley_cs_firrtl_interpreter_2_12_1_3_1_jar.xml
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@ -1,13 +0,0 @@
<component name="libraryTable">
<library name="sbt: edu.berkeley.cs:firrtl-interpreter_2.12:1.3.1:jar">
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13
.idea/libraries/sbt__edu_berkeley_cs_treadle_2_12_1_2_1_jar.xml
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@ -1,13 +0,0 @@
<component name="libraryTable">
<library name="sbt: edu.berkeley.cs:treadle_2.12:1.2.1:jar">
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13
.idea/libraries/sbt__joda_time_joda_time_2_10_1_jar.xml
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@ -1,13 +0,0 @@
<component name="libraryTable">
<library name="sbt: joda-time:joda-time:2.10.1:jar">
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13
.idea/libraries/sbt__junit_junit_4_13_jar.xml
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@ -1,13 +0,0 @@
<component name="libraryTable">
<library name="sbt: junit:junit:4.13:jar">
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13
.idea/libraries/sbt__net_jcazevedo_moultingyaml_2_12_0_4_2_jar.xml
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@ -1,13 +0,0 @@
<component name="libraryTable">
<library name="sbt: net.jcazevedo:moultingyaml_2.12:0.4.2:jar">
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13
.idea/libraries/sbt__org_antlr_antlr4_runtime_4_7_1_jar.xml
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@ -1,13 +0,0 @@
<component name="libraryTable">
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13
.idea/libraries/sbt__org_apache_commons_commons_lang3_3_9_jar.xml
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@ -1,13 +0,0 @@
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13
.idea/libraries/sbt__org_apache_commons_commons_text_1_8_jar.xml
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@ -1,13 +0,0 @@
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13
.idea/libraries/sbt__org_fusesource_jansi_jansi_1_11_jar.xml
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@ -1,13 +0,0 @@
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13
.idea/libraries/sbt__org_hamcrest_hamcrest_core_1_3_jar.xml
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@ -1,13 +0,0 @@
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13
.idea/libraries/sbt__org_joda_joda_convert_2_2_0_jar.xml
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@ -1,13 +0,0 @@
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13
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<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/librarymanagement-ivy_2.12-1.3.1.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/lm-coursier-shaded_2.12-2.0.0-RC5-3.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/log4j-api-2.11.2.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/log4j-core-2.11.2.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/log4j-slf4j-impl-2.11.2.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/logic_2.12-1.3.8.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/main-settings_2.12-1.3.8.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/main_2.12-1.3.8.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/okhttp-3.14.2.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/okhttp-urlconnection-3.7.0.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/okio-1.17.2.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/protobuf-java-3.7.0.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/protocol_2.12-1.3.8.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/reactive-streams-1.0.2.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/run_2.12-1.3.8.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/sbinary_2.12-0.5.0.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/sbt-1.3.8.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/scala-parser-combinators_2.12-1.1.2.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/scala-reflect-2.12.10.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/scala-xml_2.12-1.2.0.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/scalacache-caffeine_2.12-0.20.0.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/scalacache-core_2.12-0.20.0.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/scalapb-runtime_2.12-0.6.0.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/scripted-plugin_2.12-1.3.8.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/scripted-sbt-redux_2.12-1.3.8.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/shaded-scalajson_2.12-1.0.0-M4.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/sjson-new-core_2.12-0.8.3.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/sjson-new-murmurhash_2.12-0.8.3.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/sjson-new-scalajson_2.12-0.8.2.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/slf4j-api-1.7.26.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/sourcecode_2.12-0.1.3.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/ssl-config-core_2.12-0.4.0.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/task-system_2.12-1.3.8.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/tasks_2.12-1.3.8.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/template-resolver-0.1.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/test-agent-1.3.8.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/test-interface-1.0.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/testing_2.12-1.3.8.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/util-cache_2.12-1.3.3.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/util-control_2.12-1.3.3.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/util-interface-1.3.3.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/util-logging_2.12-1.3.3.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/util-position_2.12-1.3.3.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/util-relation_2.12-1.3.3.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/util-scripted_2.12-1.3.3.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/util-tracking_2.12-1.3.3.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/zinc-apiinfo_2.12-1.3.4.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/zinc-classfile_2.12-1.3.4.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/zinc-classpath_2.12-1.3.4.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/zinc-compile-core_2.12-1.3.4.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/zinc-compile_2.12-1.3.4.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/zinc-core_2.12-1.3.4.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/zinc-lm-integration_2.12-1.3.8.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/zinc-persist_2.12-1.3.4.jar!/" />
<root url="jar://$USER_HOME$/.sbt/boot/scala-2.12.10/org.scala-sbt/sbt/1.3.8/zinc_2.12-1.3.4.jar!/" />
</CLASSES>
<JAVADOC />
<SOURCES />
</library>
</orderEntry>
</component>
<component name="SbtModule">
<option name="buildForURI" value="file:$MODULE_DIR$/../../" />
<option name="imports" value="_root_.sbt.Keys._, _root_.sbt.ScriptedPlugin.autoImport._, _root_.sbt._, _root_.sbt.nio.Keys._, _root_.sbt.plugins.IvyPlugin, _root_.sbt.plugins.JvmPlugin, _root_.sbt.plugins.CorePlugin, _root_.sbt.ScriptedPlugin, _root_.sbt.plugins.SbtPlugin, _root_.sbt.plugins.SemanticdbPlugin, _root_.sbt.plugins.JUnitXmlReportPlugin, _root_.sbt.plugins.Giter8TemplatePlugin, _root_.scala.xml.{TopScope=&gt;SUB:DOLLARscope}" />
</component>
</module>

49
.idea/modules/Quasar.iml
View File

@ -1,49 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<module external.linked.project.id="quasar [file:/home/waleedbinehsan/Desktop/Quasar/]" external.linked.project.path="$MODULE_DIR$/../.." external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" type="JAVA_MODULE" version="4">
<component name="NewModuleRootManager" LANGUAGE_LEVEL="JDK_1_8">
<output url="file://$MODULE_DIR$/../../target/scala-2.12/classes" />
<output-test url="file://$MODULE_DIR$/../../target/scala-2.12/test-classes" />
<exclude-output />
<content url="file://$MODULE_DIR$/../..">
<excludeFolder url="file://$MODULE_DIR$/../../target" />
</content>
<orderEntry type="inheritedJdk" />
<orderEntry type="sourceFolder" forTests="false" />
<orderEntry type="library" name="sbt: com.github.nscala-time:nscala-time_2.12:2.22.0:jar" level="project" />
<orderEntry type="library" name="sbt: com.github.scopt:scopt_2.12:3.7.1:jar" level="project" />
<orderEntry type="library" name="sbt: com.google.protobuf:protobuf-java:3.9.0:jar" level="project" />
<orderEntry type="library" name="sbt: com.lihaoyi:utest_2.12:0.6.6:jar" level="project" />
<orderEntry type="library" name="sbt: com.thoughtworks.paranamer:paranamer:2.8:jar" level="project" />
<orderEntry type="library" name="sbt: edu.berkeley.cs:chisel-iotesters_2.12:1.4.1:jar" level="project" />
<orderEntry type="library" name="sbt: edu.berkeley.cs:chisel3-core_2.12:3.3.1:jar" level="project" />
<orderEntry type="library" name="sbt: edu.berkeley.cs:chisel3-macros_2.12:3.3.1:jar" level="project" />
<orderEntry type="library" name="sbt: edu.berkeley.cs:chisel3_2.12:3.3.1:jar" level="project" />
<orderEntry type="library" name="sbt: edu.berkeley.cs:chiseltest_2.12:0.2.1:jar" level="project" />
<orderEntry type="library" name="sbt: edu.berkeley.cs:firrtl-interpreter_2.12:1.3.1:jar" level="project" />
<orderEntry type="library" name="sbt: edu.berkeley.cs:firrtl_2.12:1.3.1:jar" level="project" />
<orderEntry type="library" name="sbt: edu.berkeley.cs:treadle_2.12:1.2.1:jar" level="project" />
<orderEntry type="library" name="sbt: joda-time:joda-time:2.10.1:jar" level="project" />
<orderEntry type="library" name="sbt: junit:junit:4.13:jar" level="project" />
<orderEntry type="library" name="sbt: net.jcazevedo:moultingyaml_2.12:0.4.2:jar" level="project" />
<orderEntry type="library" name="sbt: org.antlr:antlr4-runtime:4.7.1:jar" level="project" />
<orderEntry type="library" name="sbt: org.apache.commons:commons-lang3:3.9:jar" level="project" />
<orderEntry type="library" name="sbt: org.apache.commons:commons-text:1.8:jar" level="project" />
<orderEntry type="library" name="sbt: org.fusesource.jansi:jansi:1.11:jar" level="project" />
<orderEntry type="library" name="sbt: org.hamcrest:hamcrest-core:1.3:jar" level="project" />
<orderEntry type="library" name="sbt: org.joda:joda-convert:2.2.0:jar" level="project" />
<orderEntry type="library" name="sbt: org.json4s:json4s-ast_2.12:3.6.8:jar" level="project" />
<orderEntry type="library" name="sbt: org.json4s:json4s-core_2.12:3.6.8:jar" level="project" />
<orderEntry type="library" name="sbt: org.json4s:json4s-native_2.12:3.6.8:jar" level="project" />
<orderEntry type="library" name="sbt: org.json4s:json4s-scalap_2.12:3.6.8:jar" level="project" />
<orderEntry type="library" name="sbt: org.portable-scala:portable-scala-reflect_2.12:0.1.0:jar" level="project" />
<orderEntry type="library" name="sbt: org.scala-lang.modules:scala-jline:2.12.1:jar" level="project" />
<orderEntry type="library" name="sbt: org.scala-lang.modules:scala-xml_2.12:1.2.0:jar" level="project" />
<orderEntry type="library" name="sbt: org.scala-lang:scala-library:2.12.10:jar" level="project" />
<orderEntry type="library" name="sbt: org.scala-lang:scala-reflect:2.12.10:jar" level="project" />
<orderEntry type="library" name="sbt: org.scala-sbt:test-interface:1.0:jar" level="project" />
<orderEntry type="library" name="sbt: org.scalacheck:scalacheck_2.12:1.14.3:jar" level="project" />
<orderEntry type="library" name="sbt: org.scalactic:scalactic_2.12:3.0.8:jar" level="project" />
<orderEntry type="library" name="sbt: org.scalatest:scalatest_2.12:3.0.8:jar" level="project" />
<orderEntry type="library" name="sbt: org.yaml:snakeyaml:1.26:jar" level="project" />
</component>
</module>

17
.idea/sbt.xml
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@ -1,17 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<project version="4">
<component name="ScalaSbtSettings">
<option name="linkedExternalProjectsSettings">
<SbtProjectSettings>
<option name="externalProjectPath" value="$PROJECT_DIR$" />
<option name="modules">
<set>
<option value="$PROJECT_DIR$" />
<option value="$PROJECT_DIR$/project" />
</set>
</option>
<option name="sbtVersion" value="1.3.8" />
</SbtProjectSettings>
</option>
</component>
</project>

14
.idea/scala_compiler.xml
View File

@ -1,14 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<project version="4">
<component name="ScalaCompilerConfiguration">
<profile name="sbt 1" modules="quasar_9951" />
<profile name="sbt 2" modules="Quasar">
<parameters>
<parameter value="-Xsource:2.11" />
</parameters>
<plugins>
<plugin path="$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar" />
</plugins>
</profile>
</component>
</project>

6
.idea/vcs.xml
View File

@ -1,6 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<project version="4">
<component name="VcsDirectoryMappings">
<mapping directory="" vcs="Git" />
</component>
</project>

57
build.sbt
View File

@ -1,57 +0,0 @@
// See README.md for license details.
def scalacOptionsVersion(scalaVersion: String): Seq[String] = {
Seq() ++ {
// If we're building with Scala > 2.11, enable the compile option
// switch to support our anonymous Bundle definitions:
// https://github.com/scala/bug/issues/10047
CrossVersion.partialVersion(scalaVersion) match {
case Some((2, scalaMajor: Long)) if scalaMajor < 12 => Seq()
case _ => Seq("-Xsource:2.11")
}
}
}
def javacOptionsVersion(scalaVersion: String): Seq[String] = {
Seq() ++ {
// Scala 2.12 requires Java 8. We continue to generate
// Java 7 compatible code for Scala 2.11
// for compatibility with old clients.
CrossVersion.partialVersion(scalaVersion) match {
case Some((2, scalaMajor: Long)) if scalaMajor < 12 =>
Seq("-source", "1.7", "-target", "1.7")
case _ =>
Seq("-source", "1.8", "-target", "1.8")
}
}
}
name := "Quasar"
organization := "https://www.lampromellon.com/"
version := "3.3.0"
scalaVersion := "2.12.10"
crossScalaVersions := Seq("2.12.10", "2.11.12")
resolvers ++= Seq(
Resolver.sonatypeRepo("snapshots"),
Resolver.sonatypeRepo("releases")
)
addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full)
// Provide a managed dependency on X if -DXVersion="" is supplied on the command line.
val defaultVersions = Seq(
"chisel-iotesters" -> "1.4.1+",
"chiseltest" -> "0.2.1+"
)
libraryDependencies ++= defaultVersions.map { case (dep, ver) =>
"edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", ver) }
scalacOptions ++= scalacOptionsVersion(scalaVersion.value)
javacOptions ++= javacOptionsVersion(scalaVersion.value)

0
config/README.md → configs/README.md
View File

2369
configs/swerv.config Executable file
View File

File diff suppressed because it is too large Load Diff

2371
configs/swerv.config~ Normal file
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File diff suppressed because it is too large Load Diff

57
configs/swerv_config_gen.py Normal file
View File

@ -0,0 +1,57 @@
#!/usr/bin/env python
from fusesoc.capi2.generator import Generator
import os
import shutil
import subprocess
import sys
import tempfile
if sys.version[0] == '2':
devnull = open(os.devnull, 'w')
else:
from subprocess import DEVNULL as devnull
class SwervConfigGenerator(Generator):
def run(self):
script_root = os.path.abspath(os.path.join(os.path.dirname(sys.argv[0]), '..'))
files = [
{"configs/snapshots/default/common_defines.vh" : {
"copyto" : "config/common_defines.vh",
"file_type" : "systemVerilogSource"}},
{"configs/snapshots/default/el2_pdef.vh" : {
"copyto" : "config/el2_pdef.vh",
"file_type" : "systemVerilogSource"}},
{"configs/snapshots/default/el2_param.vh" : {
"is_include_file" : True,
"file_type" : "systemVerilogSource"}},
{"configs/snapshots/default/pic_map_auto.h" : {
"is_include_file" : True,
"file_type" : "systemVerilogSource"}}]
tmp_dir = os.path.join(tempfile.mkdtemp(), 'core')
shutil.copytree(script_root, tmp_dir)
cwd = tmp_dir
env = os.environ.copy()
env['RV_ROOT'] = tmp_dir
args = ['configs/swerv.config'] + self.config.get('args', [])
rc = subprocess.call(args, cwd=cwd, env=env, stdout=devnull)
if rc:
exit(1)
filenames = []
for f in files:
for k in f:
filenames.append(k)
for f in filenames:
d = os.path.dirname(f)
if d and not os.path.exists(d):
os.makedirs(d)
shutil.copy2(os.path.join(cwd, f),f)
self.add_files(files)
g = SwervConfigGenerator()
g.run()
g.write()

2
design/.idea/.name
View File

@ -1 +1 @@
Quasar
chisel-module-template

10
design/.idea/codeStyles/Project.xml
View File

@ -2,16 +2,6 @@
<code_scheme name="Project" version="173">
<ScalaCodeStyleSettings>
<option name="MULTILINE_STRING_CLOSING_QUOTES_ON_NEW_LINE" value="true" />
<option name="REPLACE_CASE_ARROW_WITH_UNICODE_CHAR" value="true" />
<option name="REPLACE_MAP_ARROW_WITH_UNICODE_CHAR" value="true" />
<option name="REPLACE_FOR_GENERATOR_ARROW_WITH_UNICODE_CHAR" value="true" />
</ScalaCodeStyleSettings>
<codeStyleSettings language="Scala">
<indentOptions>
<option name="USE_TAB_CHARACTER" value="true" />
<option name="SMART_TABS" value="true" />
<option name="KEEP_INDENTS_ON_EMPTY_LINES" value="true" />
</indentOptions>
</codeStyleSettings>
</code_scheme>
</component>

1
design/.idea/compiler.xml
View File

@ -3,7 +3,6 @@
<component name="CompilerConfiguration">
<bytecodeTargetLevel target="1.8">
<module name="chisel-module-template" target="1.8" />
<module name="Quasar" target="1.8" />
</bytecodeTargetLevel>
</component>
</project>

303
design/.idea/misc.xml
View File

@ -4,71 +4,6 @@
<component name="SVCompilerDirectivesDefines">
<option name="define">
<map>
<entry key="EL2_LOCAL_RAM_TEST_IO">
<value>
<Define>
<option name="definitions">
<list>
<Body>
<option name="offset" value="668" />
<option name="replacementList" value="input logic WE, &#10;input logic ME, &#10;input logic CLK" />
<option name="source" value="mem_lib.sv" />
</Body>
</list>
</option>
</Define>
</value>
</entry>
<entry key="EL2_RAM">
<value>
<Define>
<option name="definitions">
<list>
<Body>
<option name="offset" value="788" />
<option name="parameters">
<list>
<Parameter>
<option name="name" value="depth" />
</Parameter>
<Parameter>
<option name="name" value="width" />
</Parameter>
</list>
</option>
<option name="replacementList" value="module ram_``depth``x``width( &#10; input logic [$clog2(depth)-1:0] ADR, &#10; input logic [(width-1):0] D, &#10; output logic [(width-1):0] Q, &#10; `EL2_LOCAL_RAM_TEST_IO &#10;); &#10;reg [(width-1):0] ram_core [(depth-1):0]; &#10; &#10;always @(posedge CLK) begin &#10; if (ME &amp;&amp; WE) ram_core[ADR] = D; &#10; if (ME &amp;&amp; ~WE) Q &lt;= ram_core[ADR]; &#10;end &#10; &#10;endmodule" />
<option name="source" value="mem_lib.sv" />
</Body>
</list>
</option>
</Define>
</value>
</entry>
<entry key="EL2_RAM_BE">
<value>
<Define>
<option name="definitions">
<list>
<Body>
<option name="offset" value="1437" />
<option name="parameters">
<list>
<Parameter>
<option name="name" value="depth" />
</Parameter>
<Parameter>
<option name="name" value="width" />
</Parameter>
</list>
</option>
<option name="replacementList" value="module ram_be_``depth``x``width( &#10; input logic [$clog2(depth)-1:0] ADR, &#10; input logic [(width-1):0] D, WEM, &#10; output logic [(width-1):0] Q, &#10; `EL2_LOCAL_RAM_TEST_IO &#10;); &#10;reg [(width-1):0] ram_core [(depth-1):0]; &#10; &#10;always @(posedge CLK) begin &#10; if (ME &amp;&amp; WE) ram_core[ADR] = D &amp; WEM | ~WEM &amp; ram_core[ADR];&#10; if (ME &amp;&amp; ~WE) Q &lt;= ram_core[ADR]; &#10;end &#10; &#10; &#10;endmodule" />
<option name="source" value="mem_lib.sv" />
</Body>
</list>
</option>
</Define>
</value>
</entry>
<entry key="RANDOM">
<value>
<Define>
@ -150,29 +85,9 @@
<option name="source" value="el2_ifu_mem_ctl.v" />
</Body>
<Body>
<option name="offset" value="44499" />
<option name="offset" value="149445" />
<option name="replacementList" value="$random" />
<option name="source" value="dbg.v" />
</Body>
<Body>
<option name="offset" value="9623" />
<option name="replacementList" value="$random" />
<option name="source" value="lsu.v" />
</Body>
<Body>
<option name="offset" value="55649" />
<option name="replacementList" value="$random" />
<option name="source" value="dma_ctrl.v" />
</Body>
<Body>
<option name="offset" value="151383" />
<option name="replacementList" value="$random" />
<option name="source" value="pic_ctrl.v" />
</Body>
<Body>
<option name="offset" value="198988" />
<option name="replacementList" value="$random" />
<option name="source" value="lsu_bus_buffer.v" />
<option name="source" value="dec.v" />
</Body>
</list>
</option>
@ -188,11 +103,7 @@
<option value="el2_exu_alu_ctl.v" />
<option value="el2_lsu.v" />
<option value="el2_ifu_mem_ctl.v" />
<option value="dbg.v" />
<option value="lsu.v" />
<option value="dma_ctrl.v" />
<option value="pic_ctrl.v" />
<option value="lsu_bus_buffer.v" />
<option value="dec.v" />
</set>
</option>
</Define>
@ -932,8 +843,8 @@
</InclusionDependency>
</list>
</option>
<option name="offset" value="44300" />
<option name="source" value="dbg.v" />
<option name="offset" value="149246" />
<option name="source" value="dec.v" />
</Body>
<Body>
<option name="inclusionDependencies">
@ -944,8 +855,8 @@
</InclusionDependency>
</list>
</option>
<option name="offset" value="44357" />
<option name="source" value="dbg.v" />
<option name="offset" value="149303" />
<option name="source" value="dec.v" />
</Body>
<Body>
<option name="inclusionDependencies">
@ -956,8 +867,8 @@
</InclusionDependency>
</list>
</option>
<option name="offset" value="44408" />
<option name="source" value="dbg.v" />
<option name="offset" value="149354" />
<option name="source" value="dec.v" />
</Body>
<Body>
<option name="inclusionDependencies">
@ -968,200 +879,8 @@
</InclusionDependency>
</list>
</option>
<option name="offset" value="44459" />
<option name="source" value="dbg.v" />
</Body>
<Body>
<option name="inclusionDependencies">
<list>
<InclusionDependency>
<option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
<option name="rule" value="DEFINED" />
</InclusionDependency>
</list>
</option>
<option name="offset" value="9424" />
<option name="source" value="lsu.v" />
</Body>
<Body>
<option name="inclusionDependencies">
<list>
<InclusionDependency>
<option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
<option name="rule" value="DEFINED" />
</InclusionDependency>
</list>
</option>
<option name="offset" value="9481" />
<option name="source" value="lsu.v" />
</Body>
<Body>
<option name="inclusionDependencies">
<list>
<InclusionDependency>
<option name="name" value="RANDOMIZE_REG_INIT" />
<option name="rule" value="DEFINED" />
</InclusionDependency>
</list>
</option>
<option name="offset" value="9532" />
<option name="source" value="lsu.v" />
</Body>
<Body>
<option name="inclusionDependencies">
<list>
<InclusionDependency>
<option name="name" value="RANDOMIZE_MEM_INIT" />
<option name="rule" value="DEFINED" />
</InclusionDependency>
</list>
</option>
<option name="offset" value="9583" />
<option name="source" value="lsu.v" />
</Body>
<Body>
<option name="inclusionDependencies">
<list>
<InclusionDependency>
<option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
<option name="rule" value="DEFINED" />
</InclusionDependency>
</list>
</option>
<option name="offset" value="55450" />
<option name="source" value="dma_ctrl.v" />
</Body>
<Body>
<option name="inclusionDependencies">
<list>
<InclusionDependency>
<option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
<option name="rule" value="DEFINED" />
</InclusionDependency>
</list>
</option>
<option name="offset" value="55507" />
<option name="source" value="dma_ctrl.v" />
</Body>
<Body>
<option name="inclusionDependencies">
<list>
<InclusionDependency>
<option name="name" value="RANDOMIZE_REG_INIT" />
<option name="rule" value="DEFINED" />
</InclusionDependency>
</list>
</option>
<option name="offset" value="55558" />
<option name="source" value="dma_ctrl.v" />
</Body>
<Body>
<option name="inclusionDependencies">
<list>
<InclusionDependency>
<option name="name" value="RANDOMIZE_MEM_INIT" />
<option name="rule" value="DEFINED" />
</InclusionDependency>
</list>
</option>
<option name="offset" value="55609" />
<option name="source" value="dma_ctrl.v" />
</Body>
<Body>
<option name="inclusionDependencies">
<list>
<InclusionDependency>
<option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
<option name="rule" value="DEFINED" />
</InclusionDependency>
</list>
</option>
<option name="offset" value="151184" />
<option name="source" value="pic_ctrl.v" />
</Body>
<Body>
<option name="inclusionDependencies">
<list>
<InclusionDependency>
<option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
<option name="rule" value="DEFINED" />
</InclusionDependency>
</list>
</option>
<option name="offset" value="151241" />
<option name="source" value="pic_ctrl.v" />
</Body>
<Body>
<option name="inclusionDependencies">
<list>
<InclusionDependency>
<option name="name" value="RANDOMIZE_REG_INIT" />
<option name="rule" value="DEFINED" />
</InclusionDependency>
</list>
</option>
<option name="offset" value="151292" />
<option name="source" value="pic_ctrl.v" />
</Body>
<Body>
<option name="inclusionDependencies">
<list>
<InclusionDependency>
<option name="name" value="RANDOMIZE_MEM_INIT" />
<option name="rule" value="DEFINED" />
</InclusionDependency>
</list>
</option>
<option name="offset" value="151343" />
<option name="source" value="pic_ctrl.v" />
</Body>
<Body>
<option name="inclusionDependencies">
<list>
<InclusionDependency>
<option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
<option name="rule" value="DEFINED" />
</InclusionDependency>
</list>
</option>
<option name="offset" value="198789" />
<option name="source" value="lsu_bus_buffer.v" />
</Body>
<Body>
<option name="inclusionDependencies">
<list>
<InclusionDependency>
<option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
<option name="rule" value="DEFINED" />
</InclusionDependency>
</list>
</option>
<option name="offset" value="198846" />
<option name="source" value="lsu_bus_buffer.v" />
</Body>
<Body>
<option name="inclusionDependencies">
<list>
<InclusionDependency>
<option name="name" value="RANDOMIZE_REG_INIT" />
<option name="rule" value="DEFINED" />
</InclusionDependency>
</list>
</option>
<option name="offset" value="198897" />
<option name="source" value="lsu_bus_buffer.v" />
</Body>
<Body>
<option name="inclusionDependencies">
<list>
<InclusionDependency>
<option name="name" value="RANDOMIZE_MEM_INIT" />
<option name="rule" value="DEFINED" />
</InclusionDependency>
</list>
</option>
<option name="offset" value="198948" />
<option name="source" value="lsu_bus_buffer.v" />
<option name="offset" value="149405" />
<option name="source" value="dec.v" />
</Body>
</list>
</option>

4
design/.idea/modules.xml
View File

@ -2,8 +2,8 @@
<project version="4">
<component name="ProjectModuleManager">
<modules>
<module fileurl="file://$PROJECT_DIR$/.idea/modules/Quasar.iml" filepath="$PROJECT_DIR$/.idea/modules/Quasar.iml" />
<module fileurl="file://$PROJECT_DIR$/.idea/modules/Quasar-build.iml" filepath="$PROJECT_DIR$/.idea/modules/Quasar-build.iml" />
<module fileurl="file://$PROJECT_DIR$/.idea/modules/chisel-module-template.iml" filepath="$PROJECT_DIR$/.idea/modules/chisel-module-template.iml" />
<module fileurl="file://$PROJECT_DIR$/.idea/modules/chisel-module-template-build.iml" filepath="$PROJECT_DIR$/.idea/modules/chisel-module-template-build.iml" />
</modules>
</component>
</project>

2
design/.idea/modules/Quasar-build.iml → design/.idea/modules/chisel-module-template-build.iml
View File

@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<module external.linked.project.id="Quasar-build" external.linked.project.path="$MODULE_DIR$/../../project" external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" sbt.imports="_root_.sbt.Keys._, _root_.sbt.ScriptedPlugin.autoImport._, _root_.sbt._, _root_.sbt.nio.Keys._, _root_.sbt.plugins.IvyPlugin, _root_.sbt.plugins.JvmPlugin, _root_.sbt.plugins.CorePlugin, _root_.sbt.ScriptedPlugin, _root_.sbt.plugins.SbtPlugin, _root_.sbt.plugins.SemanticdbPlugin, _root_.sbt.plugins.JUnitXmlReportPlugin, _root_.sbt.plugins.Giter8TemplatePlugin, _root_.scala.xml.{TopScope=&amp;gt;SUB:DOLLARscope}" sbt.resolvers="https://oss.sonatype.org/content/repositories/snapshots|maven|sonatype-snapshots, https://repo1.maven.org/maven2/|maven|public, https://oss.sonatype.org/content/repositories/releases|maven|sonatype-releases, file:/home/waleedbinehsan/.sbt/preloaded|maven|local-preloaded, /home/waleedbinehsan/.ivy2/cache|ivy|Local cache" type="SBT_MODULE" version="4">
<module external.linked.project.id="chisel-module-template-build" external.linked.project.path="$MODULE_DIR$/../../project" external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" sbt.imports="_root_.sbt.Keys._, _root_.sbt.ScriptedPlugin.autoImport._, _root_.sbt._, _root_.sbt.nio.Keys._, _root_.sbt.plugins.IvyPlugin, _root_.sbt.plugins.JvmPlugin, _root_.sbt.plugins.CorePlugin, _root_.sbt.ScriptedPlugin, _root_.sbt.plugins.SbtPlugin, _root_.sbt.plugins.SemanticdbPlugin, _root_.sbt.plugins.JUnitXmlReportPlugin, _root_.sbt.plugins.Giter8TemplatePlugin, _root_.scala.xml.{TopScope=&amp;gt;SUB:DOLLARscope}" sbt.resolvers="https://oss.sonatype.org/content/repositories/snapshots|maven|sonatype-snapshots, https://repo1.maven.org/maven2/|maven|public, https://oss.sonatype.org/content/repositories/releases|maven|sonatype-releases, file:/home/waleedbinehsan/.sbt/preloaded|maven|local-preloaded, /home/waleedbinehsan/.ivy2/cache|ivy|Local cache" type="SBT_MODULE" version="4">
<component name="NewModuleRootManager">
<output url="file://$MODULE_DIR$/../../project/target/idea-classes" />
<output-test url="file://$MODULE_DIR$/../../project/target/idea-test-classes" />

0
design/.idea/modules/Quasar.iml → design/.idea/modules/chisel-module-template.iml
View File

2
design/.idea/scala_compiler.xml
View File

@ -2,7 +2,7 @@
<project version="4">
<component name="ScalaCompilerConfiguration">
<profile name="sbt 1" modules="swerv-chislified-master_3681" />
<profile name="sbt 2" modules="Quasar,chisel-module-template">
<profile name="sbt 2" modules="chisel-module-template">
<parameters>
<parameter value="-Xsource:2.11" />
</parameters>

4
design/build.sbt
View File

@ -26,9 +26,7 @@ def javacOptionsVersion(scalaVersion: String): Seq[String] = {
}
}
name := "Quasar"
organization := "https://www.lampromellon.com/"
name := "chisel-module-template"
version := "3.3.0"

90
design/dmi_wrapper.sv
View File

@ -1,90 +0,0 @@
// SPDX-License-Identifier: Apache-2.0
// Copyright 2018 Western Digital Corporation or it's affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//------------------------------------------------------------------------------------
//
// Copyright Western Digital, 2018
// Owner : Anusha Narayanamoorthy
// Description:
// Wrapper module for JTAG_TAP and DMI synchronizer
//
//-------------------------------------------------------------------------------------
module dmi_wrapper(
// JTAG signals
input trst_n, // JTAG reset
input tck, // JTAG clock
input tms, // Test mode select
input tdi, // Test Data Input
output tdo, // Test Data Output
output tdoEnable, // Test Data Output enable
// Processor Signals
input core_rst_n, // Core reset
input core_clk, // Core clock
input [31:1] jtag_id, // JTAG ID
input [31:0] rd_data, // 32 bit Read data from Processor
output [31:0] reg_wr_data, // 32 bit Write data to Processor
output [6:0] reg_wr_addr, // 7 bit reg address to Processor
output reg_en, // 1 bit Read enable to Processor
output reg_wr_en, // 1 bit Write enable to Processor
output dmi_hard_reset
);
//Wire Declaration
wire rd_en;
wire wr_en;
wire dmireset;
//jtag_tap instantiation
rvjtag_tap i_jtag_tap(
.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
.tck(tck), // dedicated JTAG TCK pad signal
.tms(tms), // dedicated JTAG TMS pad signal
.tdi(tdi), // dedicated JTAG TDI pad signal
.tdo(tdo), // dedicated JTAG TDO pad signal
.tdoEnable(tdoEnable), // enable for TDO pad
.wr_data(reg_wr_data), // 32 bit Write data
.wr_addr(reg_wr_addr), // 7 bit Write address
.rd_en(rd_en), // 1 bit read enable
.wr_en(wr_en), // 1 bit Write enable
.rd_data(rd_data), // 32 bit Read data
.rd_status(2'b0),
.idle(3'h0), // no need to wait to sample data
.dmi_stat(2'b0), // no need to wait or error possible
.version(4'h1), // debug spec 0.13 compliant
.jtag_id(jtag_id),
.dmi_hard_reset(dmi_hard_reset),
.dmi_reset(dmireset)
);
// dmi_jtag_to_core_sync instantiation
dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
.wr_en(wr_en), // 1 bit Write enable
.rd_en(rd_en), // 1 bit Read enable
.rst_n(core_rst_n),
.clk(core_clk),
.reg_en(reg_en), // 1 bit Write interface bit
.reg_wr_en(reg_wr_en) // 1 bit Write enable
);
endmodule

3
design/firrtl_black_box_resource_files.f
View File

@ -1,3 +0,0 @@
/home/waleedbinehsan/Desktop/Quasar/design/gated_latch.v
/home/waleedbinehsan/Desktop/Quasar/design/dmi_wrapper.sv
/home/waleedbinehsan/Desktop/Quasar/design/mem.sv

14
design/gated_latch.v
View File

@ -1,14 +0,0 @@
module gated_latch
(
input wire SE, EN, CK,
output Q
);
reg en_ff;
wire enable;
assign enable = EN | SE;
always @(CK, enable) begin
if(!CK)
en_ff = enable;
end
assign Q = CK & en_ff;
endmodule

173
design/mem.sv
View File

@ -1,173 +0,0 @@
module mem #(
parameter ICACHE_BEAT_BITS,
parameter ICCM_BITS,
parameter ICACHE_NUM_WAYS,
parameter DCCM_BYTE_WIDTH,
parameter ICCM_BANK_INDEX_LO,
parameter ICACHE_BANK_BITS,
parameter DCCM_BITS,
parameter ICACHE_BEAT_ADDR_HI,
parameter ICCM_INDEX_BITS,
parameter ICCM_BANK_HI,
parameter ICACHE_BANKS_WAY,
parameter ICACHE_INDEX_HI,
parameter DCCM_NUM_BANKS,
parameter ICACHE_BANK_HI,
parameter ICACHE_BANK_LO,
parameter DCCM_ENABLE= 'b1,
parameter ICACHE_TAG_LO,
parameter ICACHE_DATA_INDEX_LO,
parameter ICCM_NUM_BANKS,
parameter ICACHE_ECC,
parameter ICACHE_ENABLE= 'b1,
parameter DCCM_BANK_BITS,
parameter ICCM_ENABLE= 'b1,
parameter ICCM_BANK_BITS,
parameter ICACHE_TAG_DEPTH,
parameter ICACHE_WAYPACK,
parameter DCCM_SIZE,
parameter DCCM_FDATA_WIDTH,
parameter ICACHE_TAG_INDEX_LO,
parameter ICACHE_DATA_DEPTH)
(
input logic clk,
input logic rst_l,
input logic dccm_clk_override,
input logic icm_clk_override,
input logic dec_tlu_core_ecc_disable,
//DCCM ports
input logic dccm_wren,
input logic dccm_rden,
input logic [DCCM_BITS-1:0] dccm_wr_addr_lo,
input logic [DCCM_BITS-1:0] dccm_wr_addr_hi,
input logic [DCCM_BITS-1:0] dccm_rd_addr_lo,
input logic [DCCM_BITS-1:0] dccm_rd_addr_hi,
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
//`ifdef DCCM_ENABLE
//`endif
//ICCM ports
input logic [ICCM_BITS-1:1] iccm_rw_addr,
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle
input logic iccm_wren,
input logic iccm_rden,
input logic [2:0] iccm_wr_size,
input logic [77:0] iccm_wr_data,
output logic [63:0] iccm_rd_data,
output logic [77:0] iccm_rd_data_ecc,
// Icache and Itag Ports
input logic [31:1] ic_rw_addr,
input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid,
input logic [ICACHE_NUM_WAYS-1:0] ic_wr_en,
input logic ic_rd_en,
input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
input logic ic_sel_premux_data, // Premux data sel
input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_1,
input logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
input logic ic_debug_rd_en, // Icache debug rd
input logic ic_debug_wr_en, // Icache debug wr
input logic ic_debug_tag_array, // Debug tag array
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank
output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit,
output logic ic_tag_perr, // Icache Tag parity error
input logic scan_mode
);
logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data;
assign ic_wr_data [0] = ic_wr_data_0;
assign ic_wr_data [1] = ic_wr_data_1;
// DCCM Instantiation
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
lsu_dccm_mem #(
.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
.DCCM_BITS(DCCM_BITS),
.DCCM_NUM_BANKS(DCCM_NUM_BANKS),
.DCCM_BANK_BITS(DCCM_BANK_BITS),
.DCCM_SIZE(DCCM_SIZE),
.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH)) dccm (
.clk_override(dccm_clk_override),
.*
);
end else begin: Gen_dccm_disable
assign dccm_rd_data_lo = '0;
assign dccm_rd_data_hi = '0;
end
if ( ICACHE_ENABLE ) begin: icache
ifu_ic_mem #(
.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
.ICACHE_BEAT_ADDR_HI(ICACHE_BEAT_ADDR_HI),
.ICACHE_BANKS_WAY(ICACHE_BANKS_WAY),
.ICACHE_INDEX_HI(ICACHE_INDEX_HI),
.ICACHE_BANK_HI(ICACHE_BANK_HI),
.ICACHE_BANK_LO(ICACHE_BANK_LO),
.ICACHE_TAG_LO(ICACHE_TAG_LO),
.ICACHE_DATA_INDEX_LO(ICACHE_DATA_INDEX_LO),
.ICACHE_ECC(ICACHE_ECC),
.ICACHE_TAG_DEPTH(ICACHE_TAG_DEPTH),
.ICACHE_WAYPACK(ICACHE_WAYPACK),
.ICACHE_TAG_INDEX_LO(ICACHE_TAG_INDEX_LO),
.ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH)) icm (
.clk_override(icm_clk_override),
.*
);
end
else begin
assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
assign ic_tag_perr = '0 ;
assign ic_rd_data = '0 ;
assign ic_tag_debug_rd_data = '0 ;
end // else: !if( ICACHE_ENABLE )
if (ICCM_ENABLE) begin : iccm
ifu_iccm_mem #(
.ICCM_BITS(ICCM_BITS),
.ICCM_BANK_INDEX_LO(ICCM_BANK_INDEX_LO),
.ICCM_INDEX_BITS(ICCM_INDEX_BITS),
.ICCM_BANK_HI(ICCM_BANK_HI),
.ICCM_NUM_BANKS(ICCM_NUM_BANKS),
.ICCM_BANK_BITS(ICCM_BANK_BITS)) iccm (.*,
.clk_override(icm_clk_override),
.iccm_rw_addr(iccm_rw_addr[ICCM_BITS-1:1]),
.iccm_rd_data(iccm_rd_data[63:0])
);
end
else begin
assign iccm_rd_data = '0 ;
assign iccm_rd_data_ecc = '0 ;
end
endmodule

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