Update el2_ifu_compress_ctl.scala
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682c9269c9
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@ -177,7 +177,7 @@ class RVCDecoder(x: UInt, xLen: Int) {
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def ret_q3 = q3
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def ret_q3 = q3
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}
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}
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class el2_ifu_compress( val XLen: Int, val usingCompressed: Boolean) extends Module {
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class el2_ifu_compress_ctl( val XLen: Int, val usingCompressed: Boolean) extends Module {
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val io = IO(new Bundle {
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val io = IO(new Bundle {
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val in = Input(UInt(32.W))
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val in = Input(UInt(32.W))
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val out = Output(new ExpandedInstruction)
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val out = Output(new ExpandedInstruction)
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@ -221,5 +221,5 @@ class el2_ifu_compress( val XLen: Int, val usingCompressed: Boolean) extends Mod
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}
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}
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object ifu_compress extends App {
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object ifu_compress extends App {
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println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress(64, true)))
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println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress_ctl(64, true)))
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}
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}
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