Delete swervolf_syscon.v
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Laraib Khan
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019-2020 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// $Id$
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//
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// Function: SweRVolf SoC-level controller
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// Comments:
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//
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//********************************************************************************
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module swervolf_syscon
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#(parameter [31:0] clk_freq_hz = 0)
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(input wire i_clk,
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input wire i_rst,
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input wire [63:0] i_gpio,
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output reg [63:0] o_gpio,
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output reg o_timer_irq,
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output wire o_sw_irq3,
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output wire o_sw_irq4,
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input wire i_ram_init_done,
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input wire i_ram_init_error,
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output reg [31:0] o_nmi_vec,
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output wire o_nmi_int,
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input wire [5:0] i_wb_adr,
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input wire [31:0] i_wb_dat,
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input wire [3:0] i_wb_sel,
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input wire i_wb_we,
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input wire i_wb_cyc,
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input wire i_wb_stb,
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output reg [31:0] o_wb_rdt,
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output reg o_wb_ack);
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reg [63:0] mtime;
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reg [63:0] mtimecmp;
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reg sw_irq3;
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reg sw_irq3_edge;
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reg sw_irq3_pol;
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reg sw_irq3_timer;
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reg sw_irq4;
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reg sw_irq4_edge;
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reg sw_irq4_pol;
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reg sw_irq4_timer;
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reg irq_timer_en;
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reg [31:0] irq_timer_cnt;
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reg nmi_int;
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reg nmi_int_r;
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`ifdef SIMPRINT
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reg [1023:0] signature_file;
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integer f = 0;
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initial begin
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if ($value$plusargs("signature=%s", signature_file)) begin
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$display("Writing signature to %0s", signature_file);
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f = $fopen(signature_file, "w");
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end
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end
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`endif
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`ifndef VERSION_DIRTY
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`define VERSION_DIRTY 1
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`endif
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`ifndef VERSION_MAJOR
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`define VERSION_MAJOR 255
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`endif
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`ifndef VERSION_MINOR
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`define VERSION_MINOR 255
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`endif
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`ifndef VERSION_REV
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`define VERSION_REV 255
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`endif
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`ifndef VERSION_SHA
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`define VERSION_SHA deadbeef
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`endif
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wire [31:0] version;
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assign version[31] = `VERSION_DIRTY;
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assign version[30:24] = `VERSION_REV;
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assign version[23:16] = `VERSION_MAJOR;
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assign version[15: 8] = `VERSION_MINOR;
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assign version[ 7: 0] = `VERSION_PATCH;
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assign o_sw_irq4 = sw_irq4^sw_irq4_pol;
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assign o_sw_irq3 = sw_irq3^sw_irq3_pol;
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assign o_nmi_int = nmi_int | nmi_int_r;
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wire reg_we = i_wb_cyc & i_wb_stb & i_wb_we & !o_wb_ack;
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//00 = ver
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//04 = sha
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//08 = simprint
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//09 = simexit
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//0A = RAM status
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//0B = sw_irq
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//10 = gpio
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//20 = timer/timecmp
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//40 = SPI
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always @(posedge i_clk) begin
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o_wb_ack <= i_wb_cyc & !o_wb_ack;
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if (sw_irq3_edge)
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sw_irq3 <= 1'b0;
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if (sw_irq4_edge)
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sw_irq4 <= 1'b0;
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if (irq_timer_en)
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irq_timer_cnt <= irq_timer_cnt - 1;
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nmi_int <= 1'b0;
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nmi_int_r <= nmi_int;
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if (irq_timer_cnt == 32'd1) begin
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irq_timer_en <= 1'b0;
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if (sw_irq3_timer)
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sw_irq3 <= 1'b1;
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if (sw_irq4_timer)
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sw_irq4 <= 1'b1;
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if (!(sw_irq3_timer | sw_irq4_timer))
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nmi_int <= 1'b1;
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end
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if (reg_we)
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case (i_wb_adr[5:2])
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2: begin //0x08-0x0B
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`ifdef SIMPRINT
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if (i_wb_sel[0]) begin
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if (|f) $fwrite(f, "%c", i_wb_dat[7:0]);
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$write("%c", i_wb_dat[7:0]);
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end
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if (i_wb_sel[1]) begin
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$display("\nFinito");
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$finish;
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end
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`endif
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if (i_wb_sel[3]) begin
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sw_irq4 <= i_wb_dat[31];
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sw_irq4_edge <= i_wb_dat[30];
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sw_irq4_pol <= i_wb_dat[29];
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sw_irq4_timer <= i_wb_dat[28];
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sw_irq3 <= i_wb_dat[27];
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sw_irq3_edge <= i_wb_dat[26];
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sw_irq3_pol <= i_wb_dat[25];
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sw_irq3_timer <= i_wb_dat[24];
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end
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end
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3: begin //0x0C-0x0F
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if (i_wb_sel[0]) o_nmi_vec[7:0] <= i_wb_dat[7:0];
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if (i_wb_sel[1]) o_nmi_vec[15:8] <= i_wb_dat[15:8];
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if (i_wb_sel[2]) o_nmi_vec[23:16] <= i_wb_dat[23:16];
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if (i_wb_sel[3]) o_nmi_vec[31:24] <= i_wb_dat[31:24];
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end
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4 : begin //0x10-0x13
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if (i_wb_sel[0]) o_gpio[7:0] <= i_wb_dat[7:0] ;
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if (i_wb_sel[1]) o_gpio[15:8] <= i_wb_dat[15:8] ;
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if (i_wb_sel[2]) o_gpio[23:16] <= i_wb_dat[23:16];
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if (i_wb_sel[3]) o_gpio[31:24] <= i_wb_dat[31:24];
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end
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5: begin //0x14-0x17
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if (i_wb_sel[0]) o_gpio[39:32] <= i_wb_dat[7:0];
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if (i_wb_sel[1]) o_gpio[47:40] <= i_wb_dat[15:8];
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if (i_wb_sel[2]) o_gpio[55:48] <= i_wb_dat[23:16];
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if (i_wb_sel[3]) o_gpio[63:56] <= i_wb_dat[31:24];
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end
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10 : begin //0x28-0x2B
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if (i_wb_sel[0]) mtimecmp[7:0] <= i_wb_dat[7:0];
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if (i_wb_sel[1]) mtimecmp[15:8] <= i_wb_dat[15:8];
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if (i_wb_sel[2]) mtimecmp[23:16] <= i_wb_dat[23:16];
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if (i_wb_sel[3]) mtimecmp[31:24] <= i_wb_dat[31:24];
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end
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11 : begin //0x2C-0x2F
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if (i_wb_sel[0]) mtimecmp[39:32] <= i_wb_dat[7:0];
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if (i_wb_sel[1]) mtimecmp[47:40] <= i_wb_dat[15:8];
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if (i_wb_sel[2]) mtimecmp[55:48] <= i_wb_dat[23:16];
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if (i_wb_sel[3]) mtimecmp[63:56] <= i_wb_dat[31:24];
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end
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12 : begin //0x30-3f
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if (i_wb_sel[0]) irq_timer_cnt[7:0] <= i_wb_dat[7:0] ;
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if (i_wb_sel[1]) irq_timer_cnt[15:8] <= i_wb_dat[15:8] ;
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if (i_wb_sel[2]) irq_timer_cnt[23:16] <= i_wb_dat[23:16];
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if (i_wb_sel[3]) irq_timer_cnt[31:24] <= i_wb_dat[31:24];
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end
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13 : begin
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if (i_wb_sel[0])
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irq_timer_en <= i_wb_dat[0];
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end
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endcase
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case (i_wb_adr[5:2])
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//0x00-0x03
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0 : o_wb_rdt <= version;
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//0x04-0x07
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1 : o_wb_rdt <= 32'h`VERSION_SHA;
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//0x08-0x0C
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2 : begin
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//0xB
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o_wb_rdt[31:28] <= {sw_irq4, sw_irq4_edge, sw_irq4_pol, sw_irq4_timer};
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o_wb_rdt[27:24] <= {sw_irq3, sw_irq3_edge, sw_irq3_pol, sw_irq3_timer};
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//0xA
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o_wb_rdt[23:18] <= 6'd0;
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o_wb_rdt[17:16] <= {i_ram_init_error, i_ram_init_done};
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//0x8-0x9
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o_wb_rdt[15:0] <= 16'd0;
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end
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//0xC-0xF
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3 : o_wb_rdt <= o_nmi_vec;
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//0x10-0x13
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4 : o_wb_rdt <= i_gpio[31:0];
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//0x14-0x17
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5 : o_wb_rdt <= i_gpio[63:32];
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//0x20-0x23
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8 : o_wb_rdt <= mtime[31:0];
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//0x24-0x27
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9 : o_wb_rdt <= mtime[63:32];
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//0x28-0x2B
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10 : o_wb_rdt <= mtimecmp[31:0];
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//0x2C-0x2F
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11 : o_wb_rdt <= mtimecmp[63:32];
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//0x30-0x33
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12 : o_wb_rdt <= irq_timer_cnt;
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//0x34-0x37
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13 : o_wb_rdt <= {31'd0, irq_timer_en};
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//0x3C
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15 : o_wb_rdt <= clk_freq_hz;
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endcase
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mtime <= mtime + 64'd1;
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o_timer_irq <= (mtime >= mtimecmp);
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if (i_rst) begin
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mtime <= 64'd0;
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mtimecmp <= 64'd0;
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o_wb_ack <= 1'b0;
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end
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end
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endmodule
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