Read fixed
This commit is contained in:
waleed-lm
parent
19afe9e5d3
commit
df273bc349
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@ -159,22 +159,42 @@ circuit el2_ifu_iccm_mem :
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infer mport _T_104 = _T_88[addr_bank[3]], clock @[el2_ifu_iccm_mem.scala 54:66]
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_T_104 <= iccm_bank_wr_data[3] @[el2_ifu_iccm_mem.scala 54:81]
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skip @[el2_ifu_iccm_mem.scala 54:54]
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read mport _T_105 = _T_85[addr_bank[0]], clock @[el2_ifu_iccm_mem.scala 56:80]
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reg _T_106 : UInt, clock @[el2_ifu_iccm_mem.scala 56:63]
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_T_106 <= _T_105 @[el2_ifu_iccm_mem.scala 56:63]
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iccm_bank_dout[0] <= _T_106 @[el2_ifu_iccm_mem.scala 56:53]
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read mport _T_107 = _T_86[addr_bank[1]], clock @[el2_ifu_iccm_mem.scala 56:80]
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reg _T_108 : UInt, clock @[el2_ifu_iccm_mem.scala 56:63]
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_T_108 <= _T_107 @[el2_ifu_iccm_mem.scala 56:63]
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iccm_bank_dout[1] <= _T_108 @[el2_ifu_iccm_mem.scala 56:53]
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read mport _T_109 = _T_87[addr_bank[2]], clock @[el2_ifu_iccm_mem.scala 56:80]
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reg _T_110 : UInt, clock @[el2_ifu_iccm_mem.scala 56:63]
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_T_110 <= _T_109 @[el2_ifu_iccm_mem.scala 56:63]
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iccm_bank_dout[2] <= _T_110 @[el2_ifu_iccm_mem.scala 56:53]
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read mport _T_111 = _T_88[addr_bank[3]], clock @[el2_ifu_iccm_mem.scala 56:80]
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reg _T_112 : UInt, clock @[el2_ifu_iccm_mem.scala 56:63]
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_T_112 <= _T_111 @[el2_ifu_iccm_mem.scala 56:63]
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iccm_bank_dout[3] <= _T_112 @[el2_ifu_iccm_mem.scala 56:53]
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wire _T_105 : UInt @[el2_ifu_iccm_mem.scala 56:72]
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_T_105 is invalid @[el2_ifu_iccm_mem.scala 56:72]
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when read_enable[0] : @[el2_ifu_iccm_mem.scala 56:72]
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_T_105 <= addr_bank[0] @[el2_ifu_iccm_mem.scala 56:72]
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node _T_106 = or(_T_105, UInt<12>("h00")) @[el2_ifu_iccm_mem.scala 56:72]
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node _T_107 = bits(_T_106, 11, 0) @[el2_ifu_iccm_mem.scala 56:72]
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read mport _T_108 = _T_85[_T_107], clock @[el2_ifu_iccm_mem.scala 56:72]
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skip @[el2_ifu_iccm_mem.scala 56:72]
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iccm_bank_dout[0] <= _T_108 @[el2_ifu_iccm_mem.scala 56:53]
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wire _T_109 : UInt @[el2_ifu_iccm_mem.scala 56:72]
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_T_109 is invalid @[el2_ifu_iccm_mem.scala 56:72]
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when read_enable[1] : @[el2_ifu_iccm_mem.scala 56:72]
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_T_109 <= addr_bank[1] @[el2_ifu_iccm_mem.scala 56:72]
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node _T_110 = or(_T_109, UInt<12>("h00")) @[el2_ifu_iccm_mem.scala 56:72]
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node _T_111 = bits(_T_110, 11, 0) @[el2_ifu_iccm_mem.scala 56:72]
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read mport _T_112 = _T_86[_T_111], clock @[el2_ifu_iccm_mem.scala 56:72]
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skip @[el2_ifu_iccm_mem.scala 56:72]
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iccm_bank_dout[1] <= _T_112 @[el2_ifu_iccm_mem.scala 56:53]
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wire _T_113 : UInt @[el2_ifu_iccm_mem.scala 56:72]
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_T_113 is invalid @[el2_ifu_iccm_mem.scala 56:72]
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when read_enable[2] : @[el2_ifu_iccm_mem.scala 56:72]
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_T_113 <= addr_bank[2] @[el2_ifu_iccm_mem.scala 56:72]
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node _T_114 = or(_T_113, UInt<12>("h00")) @[el2_ifu_iccm_mem.scala 56:72]
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node _T_115 = bits(_T_114, 11, 0) @[el2_ifu_iccm_mem.scala 56:72]
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read mport _T_116 = _T_87[_T_115], clock @[el2_ifu_iccm_mem.scala 56:72]
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skip @[el2_ifu_iccm_mem.scala 56:72]
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iccm_bank_dout[2] <= _T_116 @[el2_ifu_iccm_mem.scala 56:53]
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wire _T_117 : UInt @[el2_ifu_iccm_mem.scala 56:72]
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_T_117 is invalid @[el2_ifu_iccm_mem.scala 56:72]
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when read_enable[3] : @[el2_ifu_iccm_mem.scala 56:72]
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_T_117 <= addr_bank[3] @[el2_ifu_iccm_mem.scala 56:72]
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node _T_118 = or(_T_117, UInt<12>("h00")) @[el2_ifu_iccm_mem.scala 56:72]
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node _T_119 = bits(_T_118, 11, 0) @[el2_ifu_iccm_mem.scala 56:72]
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read mport _T_120 = _T_88[_T_119], clock @[el2_ifu_iccm_mem.scala 56:72]
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skip @[el2_ifu_iccm_mem.scala 56:72]
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iccm_bank_dout[3] <= _T_120 @[el2_ifu_iccm_mem.scala 56:53]
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io.iccm_bank_addr[0] <= addr_bank[0] @[el2_ifu_iccm_mem.scala 61:21]
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io.iccm_bank_addr[1] <= addr_bank[1] @[el2_ifu_iccm_mem.scala 61:21]
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io.iccm_bank_addr[2] <= addr_bank[2] @[el2_ifu_iccm_mem.scala 61:21]
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@ -184,132 +204,132 @@ circuit el2_ifu_iccm_mem :
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wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 67:31]
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redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 68:21]
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redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 68:21]
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node _T_113 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67]
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node _T_114 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90]
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node _T_115 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128]
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node _T_116 = eq(_T_114, _T_115) @[el2_ifu_iccm_mem.scala 70:105]
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node _T_117 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163]
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node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 70:169]
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node _T_119 = and(_T_116, _T_118) @[el2_ifu_iccm_mem.scala 70:145]
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node _T_120 = and(_T_113, _T_119) @[el2_ifu_iccm_mem.scala 70:71]
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node _T_121 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22]
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node _T_122 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60]
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node _T_123 = eq(_T_121, _T_122) @[el2_ifu_iccm_mem.scala 71:37]
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node _T_124 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93]
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node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 71:99]
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node _T_126 = and(_T_123, _T_125) @[el2_ifu_iccm_mem.scala 71:77]
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node _T_127 = or(_T_120, _T_126) @[el2_ifu_iccm_mem.scala 70:179]
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node _T_128 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67]
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node _T_129 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90]
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node _T_130 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128]
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node _T_131 = eq(_T_129, _T_130) @[el2_ifu_iccm_mem.scala 70:105]
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node _T_132 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163]
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node _T_133 = eq(_T_132, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 70:169]
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node _T_134 = and(_T_131, _T_133) @[el2_ifu_iccm_mem.scala 70:145]
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node _T_135 = and(_T_128, _T_134) @[el2_ifu_iccm_mem.scala 70:71]
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node _T_136 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22]
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node _T_137 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60]
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node _T_138 = eq(_T_136, _T_137) @[el2_ifu_iccm_mem.scala 71:37]
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node _T_139 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93]
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node _T_140 = eq(_T_139, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 71:99]
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node _T_141 = and(_T_138, _T_140) @[el2_ifu_iccm_mem.scala 71:77]
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node _T_142 = or(_T_135, _T_141) @[el2_ifu_iccm_mem.scala 70:179]
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node _T_143 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67]
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node _T_144 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90]
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node _T_145 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128]
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node _T_146 = eq(_T_144, _T_145) @[el2_ifu_iccm_mem.scala 70:105]
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node _T_147 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163]
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node _T_148 = eq(_T_147, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 70:169]
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node _T_149 = and(_T_146, _T_148) @[el2_ifu_iccm_mem.scala 70:145]
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node _T_150 = and(_T_143, _T_149) @[el2_ifu_iccm_mem.scala 70:71]
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node _T_151 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22]
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node _T_152 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60]
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node _T_153 = eq(_T_151, _T_152) @[el2_ifu_iccm_mem.scala 71:37]
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node _T_154 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93]
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node _T_155 = eq(_T_154, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 71:99]
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node _T_156 = and(_T_153, _T_155) @[el2_ifu_iccm_mem.scala 71:77]
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node _T_157 = or(_T_150, _T_156) @[el2_ifu_iccm_mem.scala 70:179]
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node _T_158 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67]
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node _T_159 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90]
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node _T_160 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128]
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node _T_161 = eq(_T_159, _T_160) @[el2_ifu_iccm_mem.scala 70:105]
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node _T_162 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163]
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node _T_163 = eq(_T_162, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 70:169]
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node _T_164 = and(_T_161, _T_163) @[el2_ifu_iccm_mem.scala 70:145]
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node _T_165 = and(_T_158, _T_164) @[el2_ifu_iccm_mem.scala 70:71]
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node _T_166 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22]
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node _T_167 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60]
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node _T_168 = eq(_T_166, _T_167) @[el2_ifu_iccm_mem.scala 71:37]
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node _T_169 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93]
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node _T_170 = eq(_T_169, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 71:99]
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node _T_171 = and(_T_168, _T_170) @[el2_ifu_iccm_mem.scala 71:77]
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node _T_172 = or(_T_165, _T_171) @[el2_ifu_iccm_mem.scala 70:179]
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node _T_173 = cat(_T_172, _T_157) @[Cat.scala 29:58]
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node _T_174 = cat(_T_173, _T_142) @[Cat.scala 29:58]
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node sel_red1 = cat(_T_174, _T_127) @[Cat.scala 29:58]
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node _T_175 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67]
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node _T_176 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90]
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node _T_177 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128]
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node _T_178 = eq(_T_176, _T_177) @[el2_ifu_iccm_mem.scala 72:105]
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node _T_179 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163]
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node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 72:169]
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node _T_181 = and(_T_178, _T_180) @[el2_ifu_iccm_mem.scala 72:145]
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node _T_182 = and(_T_175, _T_181) @[el2_ifu_iccm_mem.scala 72:71]
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node _T_183 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22]
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node _T_184 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60]
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node _T_185 = eq(_T_183, _T_184) @[el2_ifu_iccm_mem.scala 73:37]
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node _T_186 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93]
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node _T_187 = eq(_T_186, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 73:99]
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node _T_188 = and(_T_185, _T_187) @[el2_ifu_iccm_mem.scala 73:77]
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node _T_189 = or(_T_182, _T_188) @[el2_ifu_iccm_mem.scala 72:179]
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node _T_190 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67]
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node _T_191 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90]
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node _T_192 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128]
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node _T_193 = eq(_T_191, _T_192) @[el2_ifu_iccm_mem.scala 72:105]
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node _T_194 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163]
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node _T_195 = eq(_T_194, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 72:169]
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node _T_196 = and(_T_193, _T_195) @[el2_ifu_iccm_mem.scala 72:145]
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node _T_197 = and(_T_190, _T_196) @[el2_ifu_iccm_mem.scala 72:71]
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node _T_198 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22]
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node _T_199 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60]
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node _T_200 = eq(_T_198, _T_199) @[el2_ifu_iccm_mem.scala 73:37]
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node _T_201 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93]
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node _T_202 = eq(_T_201, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 73:99]
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node _T_203 = and(_T_200, _T_202) @[el2_ifu_iccm_mem.scala 73:77]
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node _T_204 = or(_T_197, _T_203) @[el2_ifu_iccm_mem.scala 72:179]
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node _T_205 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67]
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node _T_206 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90]
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node _T_207 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128]
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node _T_208 = eq(_T_206, _T_207) @[el2_ifu_iccm_mem.scala 72:105]
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node _T_209 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163]
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node _T_210 = eq(_T_209, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 72:169]
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node _T_211 = and(_T_208, _T_210) @[el2_ifu_iccm_mem.scala 72:145]
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node _T_212 = and(_T_205, _T_211) @[el2_ifu_iccm_mem.scala 72:71]
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node _T_213 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22]
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node _T_214 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60]
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node _T_215 = eq(_T_213, _T_214) @[el2_ifu_iccm_mem.scala 73:37]
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node _T_216 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93]
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node _T_217 = eq(_T_216, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 73:99]
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node _T_218 = and(_T_215, _T_217) @[el2_ifu_iccm_mem.scala 73:77]
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node _T_219 = or(_T_212, _T_218) @[el2_ifu_iccm_mem.scala 72:179]
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node _T_220 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67]
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node _T_221 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90]
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node _T_222 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128]
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node _T_223 = eq(_T_221, _T_222) @[el2_ifu_iccm_mem.scala 72:105]
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node _T_224 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163]
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node _T_225 = eq(_T_224, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 72:169]
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node _T_226 = and(_T_223, _T_225) @[el2_ifu_iccm_mem.scala 72:145]
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node _T_227 = and(_T_220, _T_226) @[el2_ifu_iccm_mem.scala 72:71]
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node _T_228 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22]
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node _T_229 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60]
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node _T_230 = eq(_T_228, _T_229) @[el2_ifu_iccm_mem.scala 73:37]
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node _T_231 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93]
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node _T_232 = eq(_T_231, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 73:99]
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node _T_233 = and(_T_230, _T_232) @[el2_ifu_iccm_mem.scala 73:77]
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node _T_234 = or(_T_227, _T_233) @[el2_ifu_iccm_mem.scala 72:179]
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node _T_235 = cat(_T_234, _T_219) @[Cat.scala 29:58]
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node _T_236 = cat(_T_235, _T_204) @[Cat.scala 29:58]
|
||||
node sel_red0 = cat(_T_236, _T_189) @[Cat.scala 29:58]
|
||||
node _T_121 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67]
|
||||
node _T_122 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90]
|
||||
node _T_123 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128]
|
||||
node _T_124 = eq(_T_122, _T_123) @[el2_ifu_iccm_mem.scala 70:105]
|
||||
node _T_125 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163]
|
||||
node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 70:169]
|
||||
node _T_127 = and(_T_124, _T_126) @[el2_ifu_iccm_mem.scala 70:145]
|
||||
node _T_128 = and(_T_121, _T_127) @[el2_ifu_iccm_mem.scala 70:71]
|
||||
node _T_129 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22]
|
||||
node _T_130 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60]
|
||||
node _T_131 = eq(_T_129, _T_130) @[el2_ifu_iccm_mem.scala 71:37]
|
||||
node _T_132 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93]
|
||||
node _T_133 = eq(_T_132, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 71:99]
|
||||
node _T_134 = and(_T_131, _T_133) @[el2_ifu_iccm_mem.scala 71:77]
|
||||
node _T_135 = or(_T_128, _T_134) @[el2_ifu_iccm_mem.scala 70:179]
|
||||
node _T_136 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67]
|
||||
node _T_137 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90]
|
||||
node _T_138 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128]
|
||||
node _T_139 = eq(_T_137, _T_138) @[el2_ifu_iccm_mem.scala 70:105]
|
||||
node _T_140 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163]
|
||||
node _T_141 = eq(_T_140, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 70:169]
|
||||
node _T_142 = and(_T_139, _T_141) @[el2_ifu_iccm_mem.scala 70:145]
|
||||
node _T_143 = and(_T_136, _T_142) @[el2_ifu_iccm_mem.scala 70:71]
|
||||
node _T_144 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22]
|
||||
node _T_145 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60]
|
||||
node _T_146 = eq(_T_144, _T_145) @[el2_ifu_iccm_mem.scala 71:37]
|
||||
node _T_147 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93]
|
||||
node _T_148 = eq(_T_147, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 71:99]
|
||||
node _T_149 = and(_T_146, _T_148) @[el2_ifu_iccm_mem.scala 71:77]
|
||||
node _T_150 = or(_T_143, _T_149) @[el2_ifu_iccm_mem.scala 70:179]
|
||||
node _T_151 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67]
|
||||
node _T_152 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90]
|
||||
node _T_153 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128]
|
||||
node _T_154 = eq(_T_152, _T_153) @[el2_ifu_iccm_mem.scala 70:105]
|
||||
node _T_155 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163]
|
||||
node _T_156 = eq(_T_155, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 70:169]
|
||||
node _T_157 = and(_T_154, _T_156) @[el2_ifu_iccm_mem.scala 70:145]
|
||||
node _T_158 = and(_T_151, _T_157) @[el2_ifu_iccm_mem.scala 70:71]
|
||||
node _T_159 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22]
|
||||
node _T_160 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60]
|
||||
node _T_161 = eq(_T_159, _T_160) @[el2_ifu_iccm_mem.scala 71:37]
|
||||
node _T_162 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93]
|
||||
node _T_163 = eq(_T_162, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 71:99]
|
||||
node _T_164 = and(_T_161, _T_163) @[el2_ifu_iccm_mem.scala 71:77]
|
||||
node _T_165 = or(_T_158, _T_164) @[el2_ifu_iccm_mem.scala 70:179]
|
||||
node _T_166 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67]
|
||||
node _T_167 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90]
|
||||
node _T_168 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128]
|
||||
node _T_169 = eq(_T_167, _T_168) @[el2_ifu_iccm_mem.scala 70:105]
|
||||
node _T_170 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163]
|
||||
node _T_171 = eq(_T_170, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 70:169]
|
||||
node _T_172 = and(_T_169, _T_171) @[el2_ifu_iccm_mem.scala 70:145]
|
||||
node _T_173 = and(_T_166, _T_172) @[el2_ifu_iccm_mem.scala 70:71]
|
||||
node _T_174 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22]
|
||||
node _T_175 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60]
|
||||
node _T_176 = eq(_T_174, _T_175) @[el2_ifu_iccm_mem.scala 71:37]
|
||||
node _T_177 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93]
|
||||
node _T_178 = eq(_T_177, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 71:99]
|
||||
node _T_179 = and(_T_176, _T_178) @[el2_ifu_iccm_mem.scala 71:77]
|
||||
node _T_180 = or(_T_173, _T_179) @[el2_ifu_iccm_mem.scala 70:179]
|
||||
node _T_181 = cat(_T_180, _T_165) @[Cat.scala 29:58]
|
||||
node _T_182 = cat(_T_181, _T_150) @[Cat.scala 29:58]
|
||||
node sel_red1 = cat(_T_182, _T_135) @[Cat.scala 29:58]
|
||||
node _T_183 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67]
|
||||
node _T_184 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90]
|
||||
node _T_185 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128]
|
||||
node _T_186 = eq(_T_184, _T_185) @[el2_ifu_iccm_mem.scala 72:105]
|
||||
node _T_187 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163]
|
||||
node _T_188 = eq(_T_187, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 72:169]
|
||||
node _T_189 = and(_T_186, _T_188) @[el2_ifu_iccm_mem.scala 72:145]
|
||||
node _T_190 = and(_T_183, _T_189) @[el2_ifu_iccm_mem.scala 72:71]
|
||||
node _T_191 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22]
|
||||
node _T_192 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60]
|
||||
node _T_193 = eq(_T_191, _T_192) @[el2_ifu_iccm_mem.scala 73:37]
|
||||
node _T_194 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93]
|
||||
node _T_195 = eq(_T_194, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 73:99]
|
||||
node _T_196 = and(_T_193, _T_195) @[el2_ifu_iccm_mem.scala 73:77]
|
||||
node _T_197 = or(_T_190, _T_196) @[el2_ifu_iccm_mem.scala 72:179]
|
||||
node _T_198 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67]
|
||||
node _T_199 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90]
|
||||
node _T_200 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128]
|
||||
node _T_201 = eq(_T_199, _T_200) @[el2_ifu_iccm_mem.scala 72:105]
|
||||
node _T_202 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163]
|
||||
node _T_203 = eq(_T_202, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 72:169]
|
||||
node _T_204 = and(_T_201, _T_203) @[el2_ifu_iccm_mem.scala 72:145]
|
||||
node _T_205 = and(_T_198, _T_204) @[el2_ifu_iccm_mem.scala 72:71]
|
||||
node _T_206 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22]
|
||||
node _T_207 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60]
|
||||
node _T_208 = eq(_T_206, _T_207) @[el2_ifu_iccm_mem.scala 73:37]
|
||||
node _T_209 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93]
|
||||
node _T_210 = eq(_T_209, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 73:99]
|
||||
node _T_211 = and(_T_208, _T_210) @[el2_ifu_iccm_mem.scala 73:77]
|
||||
node _T_212 = or(_T_205, _T_211) @[el2_ifu_iccm_mem.scala 72:179]
|
||||
node _T_213 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67]
|
||||
node _T_214 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90]
|
||||
node _T_215 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128]
|
||||
node _T_216 = eq(_T_214, _T_215) @[el2_ifu_iccm_mem.scala 72:105]
|
||||
node _T_217 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163]
|
||||
node _T_218 = eq(_T_217, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 72:169]
|
||||
node _T_219 = and(_T_216, _T_218) @[el2_ifu_iccm_mem.scala 72:145]
|
||||
node _T_220 = and(_T_213, _T_219) @[el2_ifu_iccm_mem.scala 72:71]
|
||||
node _T_221 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22]
|
||||
node _T_222 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60]
|
||||
node _T_223 = eq(_T_221, _T_222) @[el2_ifu_iccm_mem.scala 73:37]
|
||||
node _T_224 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93]
|
||||
node _T_225 = eq(_T_224, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 73:99]
|
||||
node _T_226 = and(_T_223, _T_225) @[el2_ifu_iccm_mem.scala 73:77]
|
||||
node _T_227 = or(_T_220, _T_226) @[el2_ifu_iccm_mem.scala 72:179]
|
||||
node _T_228 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67]
|
||||
node _T_229 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90]
|
||||
node _T_230 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128]
|
||||
node _T_231 = eq(_T_229, _T_230) @[el2_ifu_iccm_mem.scala 72:105]
|
||||
node _T_232 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163]
|
||||
node _T_233 = eq(_T_232, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 72:169]
|
||||
node _T_234 = and(_T_231, _T_233) @[el2_ifu_iccm_mem.scala 72:145]
|
||||
node _T_235 = and(_T_228, _T_234) @[el2_ifu_iccm_mem.scala 72:71]
|
||||
node _T_236 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22]
|
||||
node _T_237 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60]
|
||||
node _T_238 = eq(_T_236, _T_237) @[el2_ifu_iccm_mem.scala 73:37]
|
||||
node _T_239 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93]
|
||||
node _T_240 = eq(_T_239, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 73:99]
|
||||
node _T_241 = and(_T_238, _T_240) @[el2_ifu_iccm_mem.scala 73:77]
|
||||
node _T_242 = or(_T_235, _T_241) @[el2_ifu_iccm_mem.scala 72:179]
|
||||
node _T_243 = cat(_T_242, _T_227) @[Cat.scala 29:58]
|
||||
node _T_244 = cat(_T_243, _T_212) @[Cat.scala 29:58]
|
||||
node sel_red0 = cat(_T_244, _T_197) @[Cat.scala 29:58]
|
||||
reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 75:27]
|
||||
sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 75:27]
|
||||
reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 76:27]
|
||||
|
|
@ -317,268 +337,268 @@ circuit el2_ifu_iccm_mem :
|
|||
wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 77:28]
|
||||
redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 78:18]
|
||||
redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 78:18]
|
||||
node _T_237 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 80:47]
|
||||
node _T_238 = bits(_T_237, 0, 0) @[el2_ifu_iccm_mem.scala 80:51]
|
||||
node _T_239 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 81:47]
|
||||
node _T_240 = bits(_T_239, 0, 0) @[el2_ifu_iccm_mem.scala 81:51]
|
||||
node _T_241 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 82:47]
|
||||
node _T_242 = not(_T_241) @[el2_ifu_iccm_mem.scala 82:36]
|
||||
node _T_243 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 82:64]
|
||||
node _T_244 = not(_T_243) @[el2_ifu_iccm_mem.scala 82:53]
|
||||
node _T_245 = and(_T_242, _T_244) @[el2_ifu_iccm_mem.scala 82:51]
|
||||
node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_iccm_mem.scala 82:69]
|
||||
node _T_247 = mux(_T_238, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_248 = mux(_T_240, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_249 = mux(_T_246, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_250 = or(_T_247, _T_248) @[Mux.scala 27:72]
|
||||
node _T_251 = or(_T_250, _T_249) @[Mux.scala 27:72]
|
||||
node _T_245 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 80:47]
|
||||
node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_iccm_mem.scala 80:51]
|
||||
node _T_247 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 81:47]
|
||||
node _T_248 = bits(_T_247, 0, 0) @[el2_ifu_iccm_mem.scala 81:51]
|
||||
node _T_249 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 82:47]
|
||||
node _T_250 = not(_T_249) @[el2_ifu_iccm_mem.scala 82:36]
|
||||
node _T_251 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 82:64]
|
||||
node _T_252 = not(_T_251) @[el2_ifu_iccm_mem.scala 82:53]
|
||||
node _T_253 = and(_T_250, _T_252) @[el2_ifu_iccm_mem.scala 82:51]
|
||||
node _T_254 = bits(_T_253, 0, 0) @[el2_ifu_iccm_mem.scala 82:69]
|
||||
node _T_255 = mux(_T_246, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_256 = mux(_T_248, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_257 = mux(_T_254, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_258 = or(_T_255, _T_256) @[Mux.scala 27:72]
|
||||
node _T_259 = or(_T_258, _T_257) @[Mux.scala 27:72]
|
||||
wire iccm_bank_dout_fn_0 : UInt<39> @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_0 <= _T_251 @[Mux.scala 27:72]
|
||||
node _T_252 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 80:47]
|
||||
node _T_253 = bits(_T_252, 0, 0) @[el2_ifu_iccm_mem.scala 80:51]
|
||||
node _T_254 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 81:47]
|
||||
node _T_255 = bits(_T_254, 0, 0) @[el2_ifu_iccm_mem.scala 81:51]
|
||||
node _T_256 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 82:47]
|
||||
node _T_257 = not(_T_256) @[el2_ifu_iccm_mem.scala 82:36]
|
||||
node _T_258 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 82:64]
|
||||
node _T_259 = not(_T_258) @[el2_ifu_iccm_mem.scala 82:53]
|
||||
node _T_260 = and(_T_257, _T_259) @[el2_ifu_iccm_mem.scala 82:51]
|
||||
node _T_261 = bits(_T_260, 0, 0) @[el2_ifu_iccm_mem.scala 82:69]
|
||||
node _T_262 = mux(_T_253, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_263 = mux(_T_255, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_264 = mux(_T_261, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_265 = or(_T_262, _T_263) @[Mux.scala 27:72]
|
||||
node _T_266 = or(_T_265, _T_264) @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_0 <= _T_259 @[Mux.scala 27:72]
|
||||
node _T_260 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 80:47]
|
||||
node _T_261 = bits(_T_260, 0, 0) @[el2_ifu_iccm_mem.scala 80:51]
|
||||
node _T_262 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 81:47]
|
||||
node _T_263 = bits(_T_262, 0, 0) @[el2_ifu_iccm_mem.scala 81:51]
|
||||
node _T_264 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 82:47]
|
||||
node _T_265 = not(_T_264) @[el2_ifu_iccm_mem.scala 82:36]
|
||||
node _T_266 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 82:64]
|
||||
node _T_267 = not(_T_266) @[el2_ifu_iccm_mem.scala 82:53]
|
||||
node _T_268 = and(_T_265, _T_267) @[el2_ifu_iccm_mem.scala 82:51]
|
||||
node _T_269 = bits(_T_268, 0, 0) @[el2_ifu_iccm_mem.scala 82:69]
|
||||
node _T_270 = mux(_T_261, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_271 = mux(_T_263, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_272 = mux(_T_269, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_273 = or(_T_270, _T_271) @[Mux.scala 27:72]
|
||||
node _T_274 = or(_T_273, _T_272) @[Mux.scala 27:72]
|
||||
wire iccm_bank_dout_fn_1 : UInt<39> @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_1 <= _T_266 @[Mux.scala 27:72]
|
||||
node _T_267 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 80:47]
|
||||
node _T_268 = bits(_T_267, 0, 0) @[el2_ifu_iccm_mem.scala 80:51]
|
||||
node _T_269 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 81:47]
|
||||
node _T_270 = bits(_T_269, 0, 0) @[el2_ifu_iccm_mem.scala 81:51]
|
||||
node _T_271 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 82:47]
|
||||
node _T_272 = not(_T_271) @[el2_ifu_iccm_mem.scala 82:36]
|
||||
node _T_273 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 82:64]
|
||||
node _T_274 = not(_T_273) @[el2_ifu_iccm_mem.scala 82:53]
|
||||
node _T_275 = and(_T_272, _T_274) @[el2_ifu_iccm_mem.scala 82:51]
|
||||
node _T_276 = bits(_T_275, 0, 0) @[el2_ifu_iccm_mem.scala 82:69]
|
||||
node _T_277 = mux(_T_268, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_278 = mux(_T_270, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_279 = mux(_T_276, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_280 = or(_T_277, _T_278) @[Mux.scala 27:72]
|
||||
node _T_281 = or(_T_280, _T_279) @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_1 <= _T_274 @[Mux.scala 27:72]
|
||||
node _T_275 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 80:47]
|
||||
node _T_276 = bits(_T_275, 0, 0) @[el2_ifu_iccm_mem.scala 80:51]
|
||||
node _T_277 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 81:47]
|
||||
node _T_278 = bits(_T_277, 0, 0) @[el2_ifu_iccm_mem.scala 81:51]
|
||||
node _T_279 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 82:47]
|
||||
node _T_280 = not(_T_279) @[el2_ifu_iccm_mem.scala 82:36]
|
||||
node _T_281 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 82:64]
|
||||
node _T_282 = not(_T_281) @[el2_ifu_iccm_mem.scala 82:53]
|
||||
node _T_283 = and(_T_280, _T_282) @[el2_ifu_iccm_mem.scala 82:51]
|
||||
node _T_284 = bits(_T_283, 0, 0) @[el2_ifu_iccm_mem.scala 82:69]
|
||||
node _T_285 = mux(_T_276, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_286 = mux(_T_278, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_287 = mux(_T_284, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_288 = or(_T_285, _T_286) @[Mux.scala 27:72]
|
||||
node _T_289 = or(_T_288, _T_287) @[Mux.scala 27:72]
|
||||
wire iccm_bank_dout_fn_2 : UInt<39> @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_2 <= _T_281 @[Mux.scala 27:72]
|
||||
node _T_282 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 80:47]
|
||||
node _T_283 = bits(_T_282, 0, 0) @[el2_ifu_iccm_mem.scala 80:51]
|
||||
node _T_284 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 81:47]
|
||||
node _T_285 = bits(_T_284, 0, 0) @[el2_ifu_iccm_mem.scala 81:51]
|
||||
node _T_286 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 82:47]
|
||||
node _T_287 = not(_T_286) @[el2_ifu_iccm_mem.scala 82:36]
|
||||
node _T_288 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 82:64]
|
||||
node _T_289 = not(_T_288) @[el2_ifu_iccm_mem.scala 82:53]
|
||||
node _T_290 = and(_T_287, _T_289) @[el2_ifu_iccm_mem.scala 82:51]
|
||||
node _T_291 = bits(_T_290, 0, 0) @[el2_ifu_iccm_mem.scala 82:69]
|
||||
node _T_292 = mux(_T_283, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_293 = mux(_T_285, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_294 = mux(_T_291, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_295 = or(_T_292, _T_293) @[Mux.scala 27:72]
|
||||
node _T_296 = or(_T_295, _T_294) @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_2 <= _T_289 @[Mux.scala 27:72]
|
||||
node _T_290 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 80:47]
|
||||
node _T_291 = bits(_T_290, 0, 0) @[el2_ifu_iccm_mem.scala 80:51]
|
||||
node _T_292 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 81:47]
|
||||
node _T_293 = bits(_T_292, 0, 0) @[el2_ifu_iccm_mem.scala 81:51]
|
||||
node _T_294 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 82:47]
|
||||
node _T_295 = not(_T_294) @[el2_ifu_iccm_mem.scala 82:36]
|
||||
node _T_296 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 82:64]
|
||||
node _T_297 = not(_T_296) @[el2_ifu_iccm_mem.scala 82:53]
|
||||
node _T_298 = and(_T_295, _T_297) @[el2_ifu_iccm_mem.scala 82:51]
|
||||
node _T_299 = bits(_T_298, 0, 0) @[el2_ifu_iccm_mem.scala 82:69]
|
||||
node _T_300 = mux(_T_291, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_301 = mux(_T_293, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_302 = mux(_T_299, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_303 = or(_T_300, _T_301) @[Mux.scala 27:72]
|
||||
node _T_304 = or(_T_303, _T_302) @[Mux.scala 27:72]
|
||||
wire iccm_bank_dout_fn_3 : UInt<39> @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_3 <= _T_296 @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_3 <= _T_304 @[Mux.scala 27:72]
|
||||
wire redundant_lru : UInt<1>
|
||||
redundant_lru <= UInt<1>("h00")
|
||||
node _T_297 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 84:20]
|
||||
node r0_addr_en = and(_T_297, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 84:35]
|
||||
node _T_305 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 84:20]
|
||||
node r0_addr_en = and(_T_305, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 84:35]
|
||||
node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 85:35]
|
||||
node _T_298 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 86:63]
|
||||
node _T_299 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 86:78]
|
||||
node _T_300 = or(_T_298, _T_299) @[el2_ifu_iccm_mem.scala 86:67]
|
||||
node _T_301 = and(_T_300, io.iccm_rden) @[el2_ifu_iccm_mem.scala 86:83]
|
||||
node _T_302 = and(_T_301, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 86:98]
|
||||
node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_302) @[el2_ifu_iccm_mem.scala 86:50]
|
||||
node _T_303 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 87:55]
|
||||
node _T_304 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 87:84]
|
||||
node _T_305 = mux(_T_304, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 87:74]
|
||||
node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_303, _T_305) @[el2_ifu_iccm_mem.scala 87:29]
|
||||
reg _T_306 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when redundant_lru_en : @[Reg.scala 28:19]
|
||||
_T_306 <= redundant_lru_in @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_lru <= _T_306 @[el2_ifu_iccm_mem.scala 88:17]
|
||||
node _T_307 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 89:52]
|
||||
reg _T_308 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when r0_addr_en : @[Reg.scala 28:19]
|
||||
_T_308 <= _T_307 @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_address[0] <= _T_308 @[el2_ifu_iccm_mem.scala 89:24]
|
||||
node _T_309 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 90:52]
|
||||
node _T_310 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 90:85]
|
||||
reg _T_311 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_310 : @[Reg.scala 28:19]
|
||||
_T_311 <= _T_309 @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_address[1] <= _T_311 @[el2_ifu_iccm_mem.scala 90:24]
|
||||
node _T_312 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 91:57]
|
||||
reg _T_313 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_312 : @[Reg.scala 28:19]
|
||||
_T_313 <= UInt<1>("h01") @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_306 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 86:63]
|
||||
node _T_307 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 86:78]
|
||||
node _T_308 = or(_T_306, _T_307) @[el2_ifu_iccm_mem.scala 86:67]
|
||||
node _T_309 = and(_T_308, io.iccm_rden) @[el2_ifu_iccm_mem.scala 86:83]
|
||||
node _T_310 = and(_T_309, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 86:98]
|
||||
node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_310) @[el2_ifu_iccm_mem.scala 86:50]
|
||||
node _T_311 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 87:55]
|
||||
node _T_312 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 87:84]
|
||||
node _T_313 = mux(_T_312, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 87:74]
|
||||
node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_311, _T_313) @[el2_ifu_iccm_mem.scala 87:29]
|
||||
reg _T_314 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when redundant_lru_en : @[Reg.scala 28:19]
|
||||
_T_314 <= redundant_lru_in @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_lru <= _T_314 @[el2_ifu_iccm_mem.scala 88:17]
|
||||
node _T_315 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 89:52]
|
||||
reg _T_316 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when r0_addr_en : @[Reg.scala 28:19]
|
||||
_T_314 <= UInt<1>("h01") @[Reg.scala 28:23]
|
||||
_T_316 <= _T_315 @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_315 = cat(_T_313, _T_314) @[Cat.scala 29:58]
|
||||
redundant_valid <= _T_315 @[el2_ifu_iccm_mem.scala 91:19]
|
||||
node _T_316 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 93:45]
|
||||
node _T_317 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 93:85]
|
||||
node _T_318 = eq(_T_316, _T_317) @[el2_ifu_iccm_mem.scala 93:61]
|
||||
node _T_319 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 94:22]
|
||||
node _T_320 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 94:48]
|
||||
node _T_321 = and(_T_319, _T_320) @[el2_ifu_iccm_mem.scala 94:26]
|
||||
node _T_322 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 94:70]
|
||||
node _T_323 = eq(_T_322, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 94:75]
|
||||
node _T_324 = or(_T_321, _T_323) @[el2_ifu_iccm_mem.scala 94:52]
|
||||
node _T_325 = and(_T_318, _T_324) @[el2_ifu_iccm_mem.scala 93:102]
|
||||
node _T_326 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 94:101]
|
||||
node _T_327 = and(_T_325, _T_326) @[el2_ifu_iccm_mem.scala 94:84]
|
||||
node _T_328 = and(_T_327, io.iccm_wren) @[el2_ifu_iccm_mem.scala 94:105]
|
||||
node _T_329 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 95:6]
|
||||
node _T_330 = and(_T_329, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 95:21]
|
||||
node redundant_data0_en = or(_T_328, _T_330) @[el2_ifu_iccm_mem.scala 94:121]
|
||||
node _T_331 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 96:49]
|
||||
node _T_332 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 96:73]
|
||||
node _T_333 = and(_T_331, _T_332) @[el2_ifu_iccm_mem.scala 96:52]
|
||||
node _T_334 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 96:100]
|
||||
node _T_335 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 96:122]
|
||||
node _T_336 = eq(_T_335, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:127]
|
||||
node _T_337 = and(_T_334, _T_336) @[el2_ifu_iccm_mem.scala 96:104]
|
||||
node _T_338 = or(_T_333, _T_337) @[el2_ifu_iccm_mem.scala 96:78]
|
||||
node _T_339 = bits(_T_338, 0, 0) @[el2_ifu_iccm_mem.scala 96:137]
|
||||
node _T_340 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 97:20]
|
||||
node _T_341 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 97:44]
|
||||
node redundant_data0_in = mux(_T_339, _T_340, _T_341) @[el2_ifu_iccm_mem.scala 96:31]
|
||||
node _T_342 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 98:78]
|
||||
reg _T_343 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_342 : @[Reg.scala 28:19]
|
||||
_T_343 <= redundant_data0_in @[Reg.scala 28:23]
|
||||
redundant_address[0] <= _T_316 @[el2_ifu_iccm_mem.scala 89:24]
|
||||
node _T_317 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 90:52]
|
||||
node _T_318 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 90:85]
|
||||
reg _T_319 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_318 : @[Reg.scala 28:19]
|
||||
_T_319 <= _T_317 @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_data[0] <= _T_343 @[el2_ifu_iccm_mem.scala 98:21]
|
||||
node _T_344 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 100:45]
|
||||
node _T_345 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 100:85]
|
||||
node _T_346 = eq(_T_344, _T_345) @[el2_ifu_iccm_mem.scala 100:61]
|
||||
node _T_347 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 101:22]
|
||||
node _T_348 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 101:48]
|
||||
node _T_349 = and(_T_347, _T_348) @[el2_ifu_iccm_mem.scala 101:26]
|
||||
node _T_350 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 101:70]
|
||||
node _T_351 = eq(_T_350, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 101:75]
|
||||
node _T_352 = or(_T_349, _T_351) @[el2_ifu_iccm_mem.scala 101:52]
|
||||
node _T_353 = and(_T_346, _T_352) @[el2_ifu_iccm_mem.scala 100:102]
|
||||
node _T_354 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 101:101]
|
||||
node _T_355 = and(_T_353, _T_354) @[el2_ifu_iccm_mem.scala 101:84]
|
||||
node _T_356 = and(_T_355, io.iccm_wren) @[el2_ifu_iccm_mem.scala 101:105]
|
||||
node _T_357 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 102:6]
|
||||
node _T_358 = and(_T_357, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 102:21]
|
||||
node redundant_data1_en = or(_T_356, _T_358) @[el2_ifu_iccm_mem.scala 101:121]
|
||||
node _T_359 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 103:49]
|
||||
node _T_360 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 103:73]
|
||||
node _T_361 = and(_T_359, _T_360) @[el2_ifu_iccm_mem.scala 103:52]
|
||||
node _T_362 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 103:100]
|
||||
node _T_363 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 103:122]
|
||||
node _T_364 = eq(_T_363, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 103:127]
|
||||
node _T_365 = and(_T_362, _T_364) @[el2_ifu_iccm_mem.scala 103:104]
|
||||
node _T_366 = or(_T_361, _T_365) @[el2_ifu_iccm_mem.scala 103:78]
|
||||
node _T_367 = bits(_T_366, 0, 0) @[el2_ifu_iccm_mem.scala 103:137]
|
||||
node _T_368 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 104:20]
|
||||
node _T_369 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 104:44]
|
||||
node redundant_data1_in = mux(_T_367, _T_368, _T_369) @[el2_ifu_iccm_mem.scala 103:31]
|
||||
node _T_370 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 105:78]
|
||||
reg _T_371 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_370 : @[Reg.scala 28:19]
|
||||
_T_371 <= redundant_data1_in @[Reg.scala 28:23]
|
||||
redundant_address[1] <= _T_319 @[el2_ifu_iccm_mem.scala 90:24]
|
||||
node _T_320 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 91:57]
|
||||
reg _T_321 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_320 : @[Reg.scala 28:19]
|
||||
_T_321 <= UInt<1>("h01") @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_data[1] <= _T_371 @[el2_ifu_iccm_mem.scala 105:21]
|
||||
node _T_372 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 107:50]
|
||||
reg _T_322 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when r0_addr_en : @[Reg.scala 28:19]
|
||||
_T_322 <= UInt<1>("h01") @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_323 = cat(_T_321, _T_322) @[Cat.scala 29:58]
|
||||
redundant_valid <= _T_323 @[el2_ifu_iccm_mem.scala 91:19]
|
||||
node _T_324 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 93:45]
|
||||
node _T_325 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 93:85]
|
||||
node _T_326 = eq(_T_324, _T_325) @[el2_ifu_iccm_mem.scala 93:61]
|
||||
node _T_327 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 94:22]
|
||||
node _T_328 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 94:48]
|
||||
node _T_329 = and(_T_327, _T_328) @[el2_ifu_iccm_mem.scala 94:26]
|
||||
node _T_330 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 94:70]
|
||||
node _T_331 = eq(_T_330, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 94:75]
|
||||
node _T_332 = or(_T_329, _T_331) @[el2_ifu_iccm_mem.scala 94:52]
|
||||
node _T_333 = and(_T_326, _T_332) @[el2_ifu_iccm_mem.scala 93:102]
|
||||
node _T_334 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 94:101]
|
||||
node _T_335 = and(_T_333, _T_334) @[el2_ifu_iccm_mem.scala 94:84]
|
||||
node _T_336 = and(_T_335, io.iccm_wren) @[el2_ifu_iccm_mem.scala 94:105]
|
||||
node _T_337 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 95:6]
|
||||
node _T_338 = and(_T_337, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 95:21]
|
||||
node redundant_data0_en = or(_T_336, _T_338) @[el2_ifu_iccm_mem.scala 94:121]
|
||||
node _T_339 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 96:49]
|
||||
node _T_340 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 96:73]
|
||||
node _T_341 = and(_T_339, _T_340) @[el2_ifu_iccm_mem.scala 96:52]
|
||||
node _T_342 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 96:100]
|
||||
node _T_343 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 96:122]
|
||||
node _T_344 = eq(_T_343, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:127]
|
||||
node _T_345 = and(_T_342, _T_344) @[el2_ifu_iccm_mem.scala 96:104]
|
||||
node _T_346 = or(_T_341, _T_345) @[el2_ifu_iccm_mem.scala 96:78]
|
||||
node _T_347 = bits(_T_346, 0, 0) @[el2_ifu_iccm_mem.scala 96:137]
|
||||
node _T_348 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 97:20]
|
||||
node _T_349 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 97:44]
|
||||
node redundant_data0_in = mux(_T_347, _T_348, _T_349) @[el2_ifu_iccm_mem.scala 96:31]
|
||||
node _T_350 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 98:78]
|
||||
reg _T_351 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_350 : @[Reg.scala 28:19]
|
||||
_T_351 <= redundant_data0_in @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_data[0] <= _T_351 @[el2_ifu_iccm_mem.scala 98:21]
|
||||
node _T_352 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 100:45]
|
||||
node _T_353 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 100:85]
|
||||
node _T_354 = eq(_T_352, _T_353) @[el2_ifu_iccm_mem.scala 100:61]
|
||||
node _T_355 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 101:22]
|
||||
node _T_356 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 101:48]
|
||||
node _T_357 = and(_T_355, _T_356) @[el2_ifu_iccm_mem.scala 101:26]
|
||||
node _T_358 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 101:70]
|
||||
node _T_359 = eq(_T_358, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 101:75]
|
||||
node _T_360 = or(_T_357, _T_359) @[el2_ifu_iccm_mem.scala 101:52]
|
||||
node _T_361 = and(_T_354, _T_360) @[el2_ifu_iccm_mem.scala 100:102]
|
||||
node _T_362 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 101:101]
|
||||
node _T_363 = and(_T_361, _T_362) @[el2_ifu_iccm_mem.scala 101:84]
|
||||
node _T_364 = and(_T_363, io.iccm_wren) @[el2_ifu_iccm_mem.scala 101:105]
|
||||
node _T_365 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 102:6]
|
||||
node _T_366 = and(_T_365, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 102:21]
|
||||
node redundant_data1_en = or(_T_364, _T_366) @[el2_ifu_iccm_mem.scala 101:121]
|
||||
node _T_367 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 103:49]
|
||||
node _T_368 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 103:73]
|
||||
node _T_369 = and(_T_367, _T_368) @[el2_ifu_iccm_mem.scala 103:52]
|
||||
node _T_370 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 103:100]
|
||||
node _T_371 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 103:122]
|
||||
node _T_372 = eq(_T_371, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 103:127]
|
||||
node _T_373 = and(_T_370, _T_372) @[el2_ifu_iccm_mem.scala 103:104]
|
||||
node _T_374 = or(_T_369, _T_373) @[el2_ifu_iccm_mem.scala 103:78]
|
||||
node _T_375 = bits(_T_374, 0, 0) @[el2_ifu_iccm_mem.scala 103:137]
|
||||
node _T_376 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 104:20]
|
||||
node _T_377 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 104:44]
|
||||
node redundant_data1_in = mux(_T_375, _T_376, _T_377) @[el2_ifu_iccm_mem.scala 103:31]
|
||||
node _T_378 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 105:78]
|
||||
reg _T_379 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_378 : @[Reg.scala 28:19]
|
||||
_T_379 <= redundant_data1_in @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_data[1] <= _T_379 @[el2_ifu_iccm_mem.scala 105:21]
|
||||
node _T_380 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 107:50]
|
||||
reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 107:34]
|
||||
iccm_rd_addr_lo_q <= _T_372 @[el2_ifu_iccm_mem.scala 107:34]
|
||||
node _T_373 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 108:48]
|
||||
iccm_rd_addr_lo_q <= _T_380 @[el2_ifu_iccm_mem.scala 107:34]
|
||||
node _T_381 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 108:48]
|
||||
reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 108:34]
|
||||
iccm_rd_addr_hi_q <= _T_373 @[el2_ifu_iccm_mem.scala 108:34]
|
||||
node _T_374 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 110:86]
|
||||
node _T_375 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 110:115]
|
||||
node _T_376 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 110:86]
|
||||
node _T_377 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 110:115]
|
||||
node _T_378 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 110:86]
|
||||
node _T_379 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 110:115]
|
||||
node _T_380 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 110:86]
|
||||
node _T_381 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 110:115]
|
||||
node _T_382 = mux(_T_374, _T_375, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_383 = mux(_T_376, _T_377, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_384 = mux(_T_378, _T_379, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_385 = mux(_T_380, _T_381, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_386 = or(_T_382, _T_383) @[Mux.scala 27:72]
|
||||
node _T_387 = or(_T_386, _T_384) @[Mux.scala 27:72]
|
||||
node _T_388 = or(_T_387, _T_385) @[Mux.scala 27:72]
|
||||
wire _T_389 : UInt<32> @[Mux.scala 27:72]
|
||||
_T_389 <= _T_388 @[Mux.scala 27:72]
|
||||
node _T_390 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59]
|
||||
node _T_391 = eq(_T_390, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 111:77]
|
||||
node _T_392 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 111:106]
|
||||
node _T_393 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59]
|
||||
node _T_394 = eq(_T_393, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 111:77]
|
||||
node _T_395 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 111:106]
|
||||
node _T_396 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59]
|
||||
node _T_397 = eq(_T_396, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 111:77]
|
||||
node _T_398 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 111:106]
|
||||
node _T_399 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59]
|
||||
node _T_400 = eq(_T_399, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 111:77]
|
||||
node _T_401 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 111:106]
|
||||
node _T_402 = mux(_T_391, _T_392, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_403 = mux(_T_394, _T_395, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_404 = mux(_T_397, _T_398, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_405 = mux(_T_400, _T_401, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_406 = or(_T_402, _T_403) @[Mux.scala 27:72]
|
||||
node _T_407 = or(_T_406, _T_404) @[Mux.scala 27:72]
|
||||
node _T_408 = or(_T_407, _T_405) @[Mux.scala 27:72]
|
||||
wire _T_409 : UInt<32> @[Mux.scala 27:72]
|
||||
_T_409 <= _T_408 @[Mux.scala 27:72]
|
||||
node iccm_rd_data_pre = cat(_T_389, _T_409) @[Cat.scala 29:58]
|
||||
node _T_410 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 112:43]
|
||||
node _T_411 = bits(_T_410, 0, 0) @[el2_ifu_iccm_mem.scala 112:53]
|
||||
node _T_412 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_413 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 112:89]
|
||||
node _T_414 = cat(_T_412, _T_413) @[Cat.scala 29:58]
|
||||
node _T_415 = mux(_T_411, _T_414, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 112:25]
|
||||
io.iccm_rd_data <= _T_415 @[el2_ifu_iccm_mem.scala 112:19]
|
||||
node _T_416 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 113:85]
|
||||
node _T_417 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 113:85]
|
||||
node _T_418 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 113:85]
|
||||
node _T_419 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 113:85]
|
||||
node _T_420 = mux(_T_416, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_421 = mux(_T_417, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_422 = mux(_T_418, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_423 = mux(_T_419, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_424 = or(_T_420, _T_421) @[Mux.scala 27:72]
|
||||
node _T_425 = or(_T_424, _T_422) @[Mux.scala 27:72]
|
||||
node _T_426 = or(_T_425, _T_423) @[Mux.scala 27:72]
|
||||
wire _T_427 : UInt<39> @[Mux.scala 27:72]
|
||||
_T_427 <= _T_426 @[Mux.scala 27:72]
|
||||
node _T_428 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61]
|
||||
node _T_429 = eq(_T_428, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 114:79]
|
||||
node _T_430 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61]
|
||||
node _T_431 = eq(_T_430, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 114:79]
|
||||
node _T_432 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61]
|
||||
node _T_433 = eq(_T_432, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 114:79]
|
||||
node _T_434 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61]
|
||||
node _T_435 = eq(_T_434, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 114:79]
|
||||
node _T_436 = mux(_T_429, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_437 = mux(_T_431, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_438 = mux(_T_433, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_439 = mux(_T_435, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_440 = or(_T_436, _T_437) @[Mux.scala 27:72]
|
||||
node _T_441 = or(_T_440, _T_438) @[Mux.scala 27:72]
|
||||
node _T_442 = or(_T_441, _T_439) @[Mux.scala 27:72]
|
||||
wire _T_443 : UInt<39> @[Mux.scala 27:72]
|
||||
_T_443 <= _T_442 @[Mux.scala 27:72]
|
||||
node _T_444 = cat(_T_427, _T_443) @[Cat.scala 29:58]
|
||||
io.iccm_rd_data_ecc <= _T_444 @[el2_ifu_iccm_mem.scala 113:23]
|
||||
iccm_rd_addr_hi_q <= _T_381 @[el2_ifu_iccm_mem.scala 108:34]
|
||||
node _T_382 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 110:86]
|
||||
node _T_383 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 110:115]
|
||||
node _T_384 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 110:86]
|
||||
node _T_385 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 110:115]
|
||||
node _T_386 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 110:86]
|
||||
node _T_387 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 110:115]
|
||||
node _T_388 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 110:86]
|
||||
node _T_389 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 110:115]
|
||||
node _T_390 = mux(_T_382, _T_383, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_391 = mux(_T_384, _T_385, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_392 = mux(_T_386, _T_387, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_393 = mux(_T_388, _T_389, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_394 = or(_T_390, _T_391) @[Mux.scala 27:72]
|
||||
node _T_395 = or(_T_394, _T_392) @[Mux.scala 27:72]
|
||||
node _T_396 = or(_T_395, _T_393) @[Mux.scala 27:72]
|
||||
wire _T_397 : UInt<32> @[Mux.scala 27:72]
|
||||
_T_397 <= _T_396 @[Mux.scala 27:72]
|
||||
node _T_398 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59]
|
||||
node _T_399 = eq(_T_398, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 111:77]
|
||||
node _T_400 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 111:106]
|
||||
node _T_401 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59]
|
||||
node _T_402 = eq(_T_401, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 111:77]
|
||||
node _T_403 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 111:106]
|
||||
node _T_404 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59]
|
||||
node _T_405 = eq(_T_404, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 111:77]
|
||||
node _T_406 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 111:106]
|
||||
node _T_407 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59]
|
||||
node _T_408 = eq(_T_407, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 111:77]
|
||||
node _T_409 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 111:106]
|
||||
node _T_410 = mux(_T_399, _T_400, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_411 = mux(_T_402, _T_403, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_412 = mux(_T_405, _T_406, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_413 = mux(_T_408, _T_409, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_414 = or(_T_410, _T_411) @[Mux.scala 27:72]
|
||||
node _T_415 = or(_T_414, _T_412) @[Mux.scala 27:72]
|
||||
node _T_416 = or(_T_415, _T_413) @[Mux.scala 27:72]
|
||||
wire _T_417 : UInt<32> @[Mux.scala 27:72]
|
||||
_T_417 <= _T_416 @[Mux.scala 27:72]
|
||||
node iccm_rd_data_pre = cat(_T_397, _T_417) @[Cat.scala 29:58]
|
||||
node _T_418 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 112:43]
|
||||
node _T_419 = bits(_T_418, 0, 0) @[el2_ifu_iccm_mem.scala 112:53]
|
||||
node _T_420 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_421 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 112:89]
|
||||
node _T_422 = cat(_T_420, _T_421) @[Cat.scala 29:58]
|
||||
node _T_423 = mux(_T_419, _T_422, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 112:25]
|
||||
io.iccm_rd_data <= _T_423 @[el2_ifu_iccm_mem.scala 112:19]
|
||||
node _T_424 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 113:85]
|
||||
node _T_425 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 113:85]
|
||||
node _T_426 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 113:85]
|
||||
node _T_427 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 113:85]
|
||||
node _T_428 = mux(_T_424, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_429 = mux(_T_425, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_430 = mux(_T_426, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_431 = mux(_T_427, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_432 = or(_T_428, _T_429) @[Mux.scala 27:72]
|
||||
node _T_433 = or(_T_432, _T_430) @[Mux.scala 27:72]
|
||||
node _T_434 = or(_T_433, _T_431) @[Mux.scala 27:72]
|
||||
wire _T_435 : UInt<39> @[Mux.scala 27:72]
|
||||
_T_435 <= _T_434 @[Mux.scala 27:72]
|
||||
node _T_436 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61]
|
||||
node _T_437 = eq(_T_436, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 114:79]
|
||||
node _T_438 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61]
|
||||
node _T_439 = eq(_T_438, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 114:79]
|
||||
node _T_440 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61]
|
||||
node _T_441 = eq(_T_440, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 114:79]
|
||||
node _T_442 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61]
|
||||
node _T_443 = eq(_T_442, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 114:79]
|
||||
node _T_444 = mux(_T_437, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_445 = mux(_T_439, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_446 = mux(_T_441, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_447 = mux(_T_443, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_448 = or(_T_444, _T_445) @[Mux.scala 27:72]
|
||||
node _T_449 = or(_T_448, _T_446) @[Mux.scala 27:72]
|
||||
node _T_450 = or(_T_449, _T_447) @[Mux.scala 27:72]
|
||||
wire _T_451 : UInt<39> @[Mux.scala 27:72]
|
||||
_T_451 <= _T_450 @[Mux.scala 27:72]
|
||||
node _T_452 = cat(_T_435, _T_451) @[Cat.scala 29:58]
|
||||
io.iccm_rd_data_ecc <= _T_452 @[el2_ifu_iccm_mem.scala 113:23]
|
||||
|
||||
|
|
|
|||
|
|
@ -19,19 +19,19 @@ module el2_ifu_iccm_mem(
|
|||
);
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
reg [63:0] _RAND_0;
|
||||
reg [63:0] _RAND_2;
|
||||
reg [63:0] _RAND_4;
|
||||
reg [63:0] _RAND_3;
|
||||
reg [63:0] _RAND_6;
|
||||
reg [63:0] _RAND_9;
|
||||
`endif // RANDOMIZE_MEM_INIT
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
reg [31:0] _RAND_1;
|
||||
reg [31:0] _RAND_3;
|
||||
reg [31:0] _RAND_2;
|
||||
reg [31:0] _RAND_4;
|
||||
reg [31:0] _RAND_5;
|
||||
reg [31:0] _RAND_7;
|
||||
reg [63:0] _RAND_8;
|
||||
reg [63:0] _RAND_9;
|
||||
reg [63:0] _RAND_10;
|
||||
reg [63:0] _RAND_11;
|
||||
reg [31:0] _RAND_8;
|
||||
reg [31:0] _RAND_10;
|
||||
reg [31:0] _RAND_11;
|
||||
reg [31:0] _RAND_12;
|
||||
reg [31:0] _RAND_13;
|
||||
reg [31:0] _RAND_14;
|
||||
|
|
@ -45,41 +45,45 @@ module el2_ifu_iccm_mem(
|
|||
reg [31:0] _RAND_22;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
reg [38:0] _T_85 [0:4095]; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [38:0] _T_85__T_105_data; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [11:0] _T_85__T_105_addr; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [38:0] _T_85__T_108_data; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [11:0] _T_85__T_108_addr; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [38:0] _T_85__T_101_data; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [11:0] _T_85__T_101_addr; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire _T_85__T_101_mask; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire _T_85__T_101_en; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
reg [11:0] _T_85__T_105_addr_pipe_0;
|
||||
reg _T_85__T_108_en_pipe_0;
|
||||
reg [11:0] _T_85__T_108_addr_pipe_0;
|
||||
reg [38:0] _T_86 [0:4095]; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [38:0] _T_86__T_107_data; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [11:0] _T_86__T_107_addr; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [38:0] _T_86__T_112_data; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [11:0] _T_86__T_112_addr; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [38:0] _T_86__T_102_data; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [11:0] _T_86__T_102_addr; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire _T_86__T_102_mask; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire _T_86__T_102_en; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
reg [11:0] _T_86__T_107_addr_pipe_0;
|
||||
reg _T_86__T_112_en_pipe_0;
|
||||
reg [11:0] _T_86__T_112_addr_pipe_0;
|
||||
reg [38:0] _T_87 [0:4095]; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [38:0] _T_87__T_109_data; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [11:0] _T_87__T_109_addr; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [38:0] _T_87__T_116_data; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [11:0] _T_87__T_116_addr; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [38:0] _T_87__T_103_data; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [11:0] _T_87__T_103_addr; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire _T_87__T_103_mask; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire _T_87__T_103_en; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
reg [11:0] _T_87__T_109_addr_pipe_0;
|
||||
reg _T_87__T_116_en_pipe_0;
|
||||
reg [11:0] _T_87__T_116_addr_pipe_0;
|
||||
reg [38:0] _T_88 [0:4095]; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [38:0] _T_88__T_111_data; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [11:0] _T_88__T_111_addr; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [38:0] _T_88__T_120_data; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [11:0] _T_88__T_120_addr; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [38:0] _T_88__T_104_data; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire [11:0] _T_88__T_104_addr; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire _T_88__T_104_mask; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire _T_88__T_104_en; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
reg [11:0] _T_88__T_111_addr_pipe_0;
|
||||
reg _T_88__T_120_en_pipe_0;
|
||||
reg [11:0] _T_88__T_120_addr_pipe_0;
|
||||
wire _T_1 = io_iccm_wr_size[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 24:43]
|
||||
wire [1:0] addr_inc = _T_1 ? 2'h2 : 2'h1; // @[el2_ifu_iccm_mem.scala 24:21]
|
||||
wire [14:0] _GEN_27 = {{13'd0}, addr_inc}; // @[el2_ifu_iccm_mem.scala 25:54]
|
||||
wire [14:0] addr_bank_inc = io_iccm_rw_addr + _GEN_27; // @[el2_ifu_iccm_mem.scala 25:54]
|
||||
wire [14:0] _GEN_43 = {{13'd0}, addr_inc}; // @[el2_ifu_iccm_mem.scala 25:54]
|
||||
wire [14:0] addr_bank_inc = io_iccm_rw_addr + _GEN_43; // @[el2_ifu_iccm_mem.scala 25:54]
|
||||
wire [38:0] iccm_bank_wr_data_0 = io_iccm_wr_data[38:0]; // @[el2_ifu_iccm_mem.scala 29:50]
|
||||
wire [38:0] iccm_bank_wr_data_1 = io_iccm_wr_data[77:39]; // @[el2_ifu_iccm_mem.scala 30:54]
|
||||
wire _T_10 = io_iccm_rw_addr[2:1] == 2'h0; // @[el2_ifu_iccm_mem.scala 33:100]
|
||||
|
|
@ -118,185 +122,189 @@ module el2_ifu_iccm_mem(
|
|||
wire [11:0] _T_67 = _T_17 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 40:8]
|
||||
wire [11:0] _T_75 = _T_22 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 40:8]
|
||||
wire [11:0] _T_83 = _T_27 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 40:8]
|
||||
reg [38:0] iccm_bank_dout_0; // @[el2_ifu_iccm_mem.scala 56:63]
|
||||
reg [38:0] iccm_bank_dout_1; // @[el2_ifu_iccm_mem.scala 56:63]
|
||||
reg [38:0] iccm_bank_dout_2; // @[el2_ifu_iccm_mem.scala 56:63]
|
||||
reg [38:0] iccm_bank_dout_3; // @[el2_ifu_iccm_mem.scala 56:63]
|
||||
reg _T_313; // @[Reg.scala 27:20]
|
||||
reg _T_314; // @[Reg.scala 27:20]
|
||||
wire [1:0] redundant_valid = {_T_313,_T_314}; // @[Cat.scala 29:58]
|
||||
wire _T_93 = ~wren_bank_0; // @[el2_ifu_iccm_mem.scala 48:72]
|
||||
wire _T_95 = ~wren_bank_1; // @[el2_ifu_iccm_mem.scala 48:72]
|
||||
wire _T_97 = ~wren_bank_2; // @[el2_ifu_iccm_mem.scala 48:72]
|
||||
wire _T_99 = ~wren_bank_3; // @[el2_ifu_iccm_mem.scala 48:72]
|
||||
reg _T_321; // @[Reg.scala 27:20]
|
||||
reg _T_322; // @[Reg.scala 27:20]
|
||||
wire [1:0] redundant_valid = {_T_321,_T_322}; // @[Cat.scala 29:58]
|
||||
reg [13:0] redundant_address_1; // @[Reg.scala 27:20]
|
||||
wire _T_116 = io_iccm_rw_addr[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 70:105]
|
||||
wire _T_119 = _T_116 & _T_10; // @[el2_ifu_iccm_mem.scala 70:145]
|
||||
wire _T_120 = redundant_valid[1] & _T_119; // @[el2_ifu_iccm_mem.scala 70:71]
|
||||
wire _T_123 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 71:37]
|
||||
wire _T_126 = _T_123 & _T_12; // @[el2_ifu_iccm_mem.scala 71:77]
|
||||
wire _T_127 = _T_120 | _T_126; // @[el2_ifu_iccm_mem.scala 70:179]
|
||||
wire _T_134 = _T_116 & _T_15; // @[el2_ifu_iccm_mem.scala 70:145]
|
||||
wire _T_135 = redundant_valid[1] & _T_134; // @[el2_ifu_iccm_mem.scala 70:71]
|
||||
wire _T_141 = _T_123 & _T_17; // @[el2_ifu_iccm_mem.scala 71:77]
|
||||
wire _T_142 = _T_135 | _T_141; // @[el2_ifu_iccm_mem.scala 70:179]
|
||||
wire _T_149 = _T_116 & _T_20; // @[el2_ifu_iccm_mem.scala 70:145]
|
||||
wire _T_150 = redundant_valid[1] & _T_149; // @[el2_ifu_iccm_mem.scala 70:71]
|
||||
wire _T_156 = _T_123 & _T_22; // @[el2_ifu_iccm_mem.scala 71:77]
|
||||
wire _T_157 = _T_150 | _T_156; // @[el2_ifu_iccm_mem.scala 70:179]
|
||||
wire _T_164 = _T_116 & _T_25; // @[el2_ifu_iccm_mem.scala 70:145]
|
||||
wire _T_165 = redundant_valid[1] & _T_164; // @[el2_ifu_iccm_mem.scala 70:71]
|
||||
wire _T_171 = _T_123 & _T_27; // @[el2_ifu_iccm_mem.scala 71:77]
|
||||
wire _T_172 = _T_165 | _T_171; // @[el2_ifu_iccm_mem.scala 70:179]
|
||||
wire [3:0] sel_red1 = {_T_172,_T_157,_T_142,_T_127}; // @[Cat.scala 29:58]
|
||||
wire _T_124 = io_iccm_rw_addr[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 70:105]
|
||||
wire _T_127 = _T_124 & _T_10; // @[el2_ifu_iccm_mem.scala 70:145]
|
||||
wire _T_128 = redundant_valid[1] & _T_127; // @[el2_ifu_iccm_mem.scala 70:71]
|
||||
wire _T_131 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 71:37]
|
||||
wire _T_134 = _T_131 & _T_12; // @[el2_ifu_iccm_mem.scala 71:77]
|
||||
wire _T_135 = _T_128 | _T_134; // @[el2_ifu_iccm_mem.scala 70:179]
|
||||
wire _T_142 = _T_124 & _T_15; // @[el2_ifu_iccm_mem.scala 70:145]
|
||||
wire _T_143 = redundant_valid[1] & _T_142; // @[el2_ifu_iccm_mem.scala 70:71]
|
||||
wire _T_149 = _T_131 & _T_17; // @[el2_ifu_iccm_mem.scala 71:77]
|
||||
wire _T_150 = _T_143 | _T_149; // @[el2_ifu_iccm_mem.scala 70:179]
|
||||
wire _T_157 = _T_124 & _T_20; // @[el2_ifu_iccm_mem.scala 70:145]
|
||||
wire _T_158 = redundant_valid[1] & _T_157; // @[el2_ifu_iccm_mem.scala 70:71]
|
||||
wire _T_164 = _T_131 & _T_22; // @[el2_ifu_iccm_mem.scala 71:77]
|
||||
wire _T_165 = _T_158 | _T_164; // @[el2_ifu_iccm_mem.scala 70:179]
|
||||
wire _T_172 = _T_124 & _T_25; // @[el2_ifu_iccm_mem.scala 70:145]
|
||||
wire _T_173 = redundant_valid[1] & _T_172; // @[el2_ifu_iccm_mem.scala 70:71]
|
||||
wire _T_179 = _T_131 & _T_27; // @[el2_ifu_iccm_mem.scala 71:77]
|
||||
wire _T_180 = _T_173 | _T_179; // @[el2_ifu_iccm_mem.scala 70:179]
|
||||
wire [3:0] sel_red1 = {_T_180,_T_165,_T_150,_T_135}; // @[Cat.scala 29:58]
|
||||
reg [13:0] redundant_address_0; // @[Reg.scala 27:20]
|
||||
wire _T_178 = io_iccm_rw_addr[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 72:105]
|
||||
wire _T_181 = _T_178 & _T_10; // @[el2_ifu_iccm_mem.scala 72:145]
|
||||
wire _T_182 = redundant_valid[0] & _T_181; // @[el2_ifu_iccm_mem.scala 72:71]
|
||||
wire _T_185 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 73:37]
|
||||
wire _T_188 = _T_185 & _T_12; // @[el2_ifu_iccm_mem.scala 73:77]
|
||||
wire _T_189 = _T_182 | _T_188; // @[el2_ifu_iccm_mem.scala 72:179]
|
||||
wire _T_196 = _T_178 & _T_15; // @[el2_ifu_iccm_mem.scala 72:145]
|
||||
wire _T_197 = redundant_valid[0] & _T_196; // @[el2_ifu_iccm_mem.scala 72:71]
|
||||
wire _T_203 = _T_185 & _T_17; // @[el2_ifu_iccm_mem.scala 73:77]
|
||||
wire _T_204 = _T_197 | _T_203; // @[el2_ifu_iccm_mem.scala 72:179]
|
||||
wire _T_211 = _T_178 & _T_20; // @[el2_ifu_iccm_mem.scala 72:145]
|
||||
wire _T_212 = redundant_valid[0] & _T_211; // @[el2_ifu_iccm_mem.scala 72:71]
|
||||
wire _T_218 = _T_185 & _T_22; // @[el2_ifu_iccm_mem.scala 73:77]
|
||||
wire _T_219 = _T_212 | _T_218; // @[el2_ifu_iccm_mem.scala 72:179]
|
||||
wire _T_226 = _T_178 & _T_25; // @[el2_ifu_iccm_mem.scala 72:145]
|
||||
wire _T_227 = redundant_valid[0] & _T_226; // @[el2_ifu_iccm_mem.scala 72:71]
|
||||
wire _T_233 = _T_185 & _T_27; // @[el2_ifu_iccm_mem.scala 73:77]
|
||||
wire _T_234 = _T_227 | _T_233; // @[el2_ifu_iccm_mem.scala 72:179]
|
||||
wire [3:0] sel_red0 = {_T_234,_T_219,_T_204,_T_189}; // @[Cat.scala 29:58]
|
||||
wire _T_186 = io_iccm_rw_addr[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 72:105]
|
||||
wire _T_189 = _T_186 & _T_10; // @[el2_ifu_iccm_mem.scala 72:145]
|
||||
wire _T_190 = redundant_valid[0] & _T_189; // @[el2_ifu_iccm_mem.scala 72:71]
|
||||
wire _T_193 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 73:37]
|
||||
wire _T_196 = _T_193 & _T_12; // @[el2_ifu_iccm_mem.scala 73:77]
|
||||
wire _T_197 = _T_190 | _T_196; // @[el2_ifu_iccm_mem.scala 72:179]
|
||||
wire _T_204 = _T_186 & _T_15; // @[el2_ifu_iccm_mem.scala 72:145]
|
||||
wire _T_205 = redundant_valid[0] & _T_204; // @[el2_ifu_iccm_mem.scala 72:71]
|
||||
wire _T_211 = _T_193 & _T_17; // @[el2_ifu_iccm_mem.scala 73:77]
|
||||
wire _T_212 = _T_205 | _T_211; // @[el2_ifu_iccm_mem.scala 72:179]
|
||||
wire _T_219 = _T_186 & _T_20; // @[el2_ifu_iccm_mem.scala 72:145]
|
||||
wire _T_220 = redundant_valid[0] & _T_219; // @[el2_ifu_iccm_mem.scala 72:71]
|
||||
wire _T_226 = _T_193 & _T_22; // @[el2_ifu_iccm_mem.scala 73:77]
|
||||
wire _T_227 = _T_220 | _T_226; // @[el2_ifu_iccm_mem.scala 72:179]
|
||||
wire _T_234 = _T_186 & _T_25; // @[el2_ifu_iccm_mem.scala 72:145]
|
||||
wire _T_235 = redundant_valid[0] & _T_234; // @[el2_ifu_iccm_mem.scala 72:71]
|
||||
wire _T_241 = _T_193 & _T_27; // @[el2_ifu_iccm_mem.scala 73:77]
|
||||
wire _T_242 = _T_235 | _T_241; // @[el2_ifu_iccm_mem.scala 72:179]
|
||||
wire [3:0] sel_red0 = {_T_242,_T_227,_T_212,_T_197}; // @[Cat.scala 29:58]
|
||||
reg [3:0] sel_red0_q; // @[el2_ifu_iccm_mem.scala 75:27]
|
||||
reg [3:0] sel_red1_q; // @[el2_ifu_iccm_mem.scala 76:27]
|
||||
wire _T_242 = ~sel_red0_q[0]; // @[el2_ifu_iccm_mem.scala 82:36]
|
||||
wire _T_244 = ~sel_red1_q[0]; // @[el2_ifu_iccm_mem.scala 82:53]
|
||||
wire _T_245 = _T_242 & _T_244; // @[el2_ifu_iccm_mem.scala 82:51]
|
||||
wire _T_250 = ~sel_red0_q[0]; // @[el2_ifu_iccm_mem.scala 82:36]
|
||||
wire _T_252 = ~sel_red1_q[0]; // @[el2_ifu_iccm_mem.scala 82:53]
|
||||
wire _T_253 = _T_250 & _T_252; // @[el2_ifu_iccm_mem.scala 82:51]
|
||||
reg [38:0] redundant_data_1; // @[Reg.scala 27:20]
|
||||
wire [38:0] _T_247 = sel_red1_q[0] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_255 = sel_red1_q[0] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
reg [38:0] redundant_data_0; // @[Reg.scala 27:20]
|
||||
wire [38:0] _T_248 = sel_red0_q[0] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_249 = _T_245 ? iccm_bank_dout_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_250 = _T_247 | _T_248; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_0 = _T_250 | _T_249; // @[Mux.scala 27:72]
|
||||
wire _T_257 = ~sel_red0_q[1]; // @[el2_ifu_iccm_mem.scala 82:36]
|
||||
wire _T_259 = ~sel_red1_q[1]; // @[el2_ifu_iccm_mem.scala 82:53]
|
||||
wire _T_260 = _T_257 & _T_259; // @[el2_ifu_iccm_mem.scala 82:51]
|
||||
wire [38:0] _T_262 = sel_red1_q[1] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_263 = sel_red0_q[1] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_264 = _T_260 ? iccm_bank_dout_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_265 = _T_262 | _T_263; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_1 = _T_265 | _T_264; // @[Mux.scala 27:72]
|
||||
wire _T_272 = ~sel_red0_q[2]; // @[el2_ifu_iccm_mem.scala 82:36]
|
||||
wire _T_274 = ~sel_red1_q[2]; // @[el2_ifu_iccm_mem.scala 82:53]
|
||||
wire _T_275 = _T_272 & _T_274; // @[el2_ifu_iccm_mem.scala 82:51]
|
||||
wire [38:0] _T_277 = sel_red1_q[2] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_278 = sel_red0_q[2] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_279 = _T_275 ? iccm_bank_dout_2 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_280 = _T_277 | _T_278; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_2 = _T_280 | _T_279; // @[Mux.scala 27:72]
|
||||
wire _T_287 = ~sel_red0_q[3]; // @[el2_ifu_iccm_mem.scala 82:36]
|
||||
wire _T_289 = ~sel_red1_q[3]; // @[el2_ifu_iccm_mem.scala 82:53]
|
||||
wire _T_290 = _T_287 & _T_289; // @[el2_ifu_iccm_mem.scala 82:51]
|
||||
wire [38:0] _T_292 = sel_red1_q[3] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_293 = sel_red0_q[3] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_294 = _T_290 ? iccm_bank_dout_3 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_295 = _T_292 | _T_293; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_3 = _T_295 | _T_294; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_256 = sel_red0_q[0] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_0 = _T_85__T_108_data; // @[el2_ifu_iccm_mem.scala 50:28 el2_ifu_iccm_mem.scala 56:53]
|
||||
wire [38:0] _T_257 = _T_253 ? iccm_bank_dout_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_258 = _T_255 | _T_256; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_0 = _T_258 | _T_257; // @[Mux.scala 27:72]
|
||||
wire _T_265 = ~sel_red0_q[1]; // @[el2_ifu_iccm_mem.scala 82:36]
|
||||
wire _T_267 = ~sel_red1_q[1]; // @[el2_ifu_iccm_mem.scala 82:53]
|
||||
wire _T_268 = _T_265 & _T_267; // @[el2_ifu_iccm_mem.scala 82:51]
|
||||
wire [38:0] _T_270 = sel_red1_q[1] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_271 = sel_red0_q[1] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_1 = _T_86__T_112_data; // @[el2_ifu_iccm_mem.scala 50:28 el2_ifu_iccm_mem.scala 56:53]
|
||||
wire [38:0] _T_272 = _T_268 ? iccm_bank_dout_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_273 = _T_270 | _T_271; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_1 = _T_273 | _T_272; // @[Mux.scala 27:72]
|
||||
wire _T_280 = ~sel_red0_q[2]; // @[el2_ifu_iccm_mem.scala 82:36]
|
||||
wire _T_282 = ~sel_red1_q[2]; // @[el2_ifu_iccm_mem.scala 82:53]
|
||||
wire _T_283 = _T_280 & _T_282; // @[el2_ifu_iccm_mem.scala 82:51]
|
||||
wire [38:0] _T_285 = sel_red1_q[2] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_286 = sel_red0_q[2] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_2 = _T_87__T_116_data; // @[el2_ifu_iccm_mem.scala 50:28 el2_ifu_iccm_mem.scala 56:53]
|
||||
wire [38:0] _T_287 = _T_283 ? iccm_bank_dout_2 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_288 = _T_285 | _T_286; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_2 = _T_288 | _T_287; // @[Mux.scala 27:72]
|
||||
wire _T_295 = ~sel_red0_q[3]; // @[el2_ifu_iccm_mem.scala 82:36]
|
||||
wire _T_297 = ~sel_red1_q[3]; // @[el2_ifu_iccm_mem.scala 82:53]
|
||||
wire _T_298 = _T_295 & _T_297; // @[el2_ifu_iccm_mem.scala 82:51]
|
||||
wire [38:0] _T_300 = sel_red1_q[3] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_301 = sel_red0_q[3] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_3 = _T_88__T_120_data; // @[el2_ifu_iccm_mem.scala 50:28 el2_ifu_iccm_mem.scala 56:53]
|
||||
wire [38:0] _T_302 = _T_298 ? iccm_bank_dout_3 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_303 = _T_300 | _T_301; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_3 = _T_303 | _T_302; // @[Mux.scala 27:72]
|
||||
reg redundant_lru; // @[Reg.scala 27:20]
|
||||
wire _T_297 = ~redundant_lru; // @[el2_ifu_iccm_mem.scala 84:20]
|
||||
wire r0_addr_en = _T_297 & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 84:35]
|
||||
wire _T_305 = ~redundant_lru; // @[el2_ifu_iccm_mem.scala 84:20]
|
||||
wire r0_addr_en = _T_305 & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 84:35]
|
||||
wire r1_addr_en = redundant_lru & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 85:35]
|
||||
wire _T_298 = |sel_red0; // @[el2_ifu_iccm_mem.scala 86:63]
|
||||
wire _T_299 = |sel_red1; // @[el2_ifu_iccm_mem.scala 86:78]
|
||||
wire _T_300 = _T_298 | _T_299; // @[el2_ifu_iccm_mem.scala 86:67]
|
||||
wire _T_301 = _T_300 & io_iccm_rden; // @[el2_ifu_iccm_mem.scala 86:83]
|
||||
wire _T_302 = _T_301 & io_iccm_correction_state; // @[el2_ifu_iccm_mem.scala 86:98]
|
||||
wire redundant_lru_en = io_iccm_buf_correct_ecc | _T_302; // @[el2_ifu_iccm_mem.scala 86:50]
|
||||
wire _GEN_23 = r1_addr_en | _T_313; // @[Reg.scala 28:19]
|
||||
wire _GEN_24 = r0_addr_en | _T_314; // @[Reg.scala 28:19]
|
||||
wire _T_318 = io_iccm_rw_addr[14:2] == redundant_address_0[13:1]; // @[el2_ifu_iccm_mem.scala 93:61]
|
||||
wire _T_321 = io_iccm_rw_addr[1] & redundant_address_0[0]; // @[el2_ifu_iccm_mem.scala 94:26]
|
||||
wire _T_324 = _T_321 | _T_1; // @[el2_ifu_iccm_mem.scala 94:52]
|
||||
wire _T_325 = _T_318 & _T_324; // @[el2_ifu_iccm_mem.scala 93:102]
|
||||
wire _T_327 = _T_325 & redundant_valid[0]; // @[el2_ifu_iccm_mem.scala 94:84]
|
||||
wire _T_328 = _T_327 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 94:105]
|
||||
wire redundant_data0_en = _T_328 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 94:121]
|
||||
wire _T_337 = redundant_address_0[0] & _T_1; // @[el2_ifu_iccm_mem.scala 96:104]
|
||||
wire _T_338 = _T_321 | _T_337; // @[el2_ifu_iccm_mem.scala 96:78]
|
||||
wire _T_346 = io_iccm_rw_addr[14:2] == redundant_address_1[13:1]; // @[el2_ifu_iccm_mem.scala 100:61]
|
||||
wire _T_349 = io_iccm_rw_addr[1] & redundant_address_1[0]; // @[el2_ifu_iccm_mem.scala 101:26]
|
||||
wire _T_352 = _T_349 | _T_1; // @[el2_ifu_iccm_mem.scala 101:52]
|
||||
wire _T_353 = _T_346 & _T_352; // @[el2_ifu_iccm_mem.scala 100:102]
|
||||
wire _T_355 = _T_353 & redundant_valid[1]; // @[el2_ifu_iccm_mem.scala 101:84]
|
||||
wire _T_356 = _T_355 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 101:105]
|
||||
wire redundant_data1_en = _T_356 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 101:121]
|
||||
wire _T_365 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 103:104]
|
||||
wire _T_366 = _T_349 | _T_365; // @[el2_ifu_iccm_mem.scala 103:78]
|
||||
wire _T_306 = |sel_red0; // @[el2_ifu_iccm_mem.scala 86:63]
|
||||
wire _T_307 = |sel_red1; // @[el2_ifu_iccm_mem.scala 86:78]
|
||||
wire _T_308 = _T_306 | _T_307; // @[el2_ifu_iccm_mem.scala 86:67]
|
||||
wire _T_309 = _T_308 & io_iccm_rden; // @[el2_ifu_iccm_mem.scala 86:83]
|
||||
wire _T_310 = _T_309 & io_iccm_correction_state; // @[el2_ifu_iccm_mem.scala 86:98]
|
||||
wire redundant_lru_en = io_iccm_buf_correct_ecc | _T_310; // @[el2_ifu_iccm_mem.scala 86:50]
|
||||
wire _GEN_39 = r1_addr_en | _T_321; // @[Reg.scala 28:19]
|
||||
wire _GEN_40 = r0_addr_en | _T_322; // @[Reg.scala 28:19]
|
||||
wire _T_326 = io_iccm_rw_addr[14:2] == redundant_address_0[13:1]; // @[el2_ifu_iccm_mem.scala 93:61]
|
||||
wire _T_329 = io_iccm_rw_addr[1] & redundant_address_0[0]; // @[el2_ifu_iccm_mem.scala 94:26]
|
||||
wire _T_332 = _T_329 | _T_1; // @[el2_ifu_iccm_mem.scala 94:52]
|
||||
wire _T_333 = _T_326 & _T_332; // @[el2_ifu_iccm_mem.scala 93:102]
|
||||
wire _T_335 = _T_333 & redundant_valid[0]; // @[el2_ifu_iccm_mem.scala 94:84]
|
||||
wire _T_336 = _T_335 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 94:105]
|
||||
wire redundant_data0_en = _T_336 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 94:121]
|
||||
wire _T_345 = redundant_address_0[0] & _T_1; // @[el2_ifu_iccm_mem.scala 96:104]
|
||||
wire _T_346 = _T_329 | _T_345; // @[el2_ifu_iccm_mem.scala 96:78]
|
||||
wire _T_354 = io_iccm_rw_addr[14:2] == redundant_address_1[13:1]; // @[el2_ifu_iccm_mem.scala 100:61]
|
||||
wire _T_357 = io_iccm_rw_addr[1] & redundant_address_1[0]; // @[el2_ifu_iccm_mem.scala 101:26]
|
||||
wire _T_360 = _T_357 | _T_1; // @[el2_ifu_iccm_mem.scala 101:52]
|
||||
wire _T_361 = _T_354 & _T_360; // @[el2_ifu_iccm_mem.scala 100:102]
|
||||
wire _T_363 = _T_361 & redundant_valid[1]; // @[el2_ifu_iccm_mem.scala 101:84]
|
||||
wire _T_364 = _T_363 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 101:105]
|
||||
wire redundant_data1_en = _T_364 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 101:121]
|
||||
wire _T_373 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 103:104]
|
||||
wire _T_374 = _T_357 | _T_373; // @[el2_ifu_iccm_mem.scala 103:78]
|
||||
reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 107:34]
|
||||
reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 108:34]
|
||||
wire _T_374 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 110:86]
|
||||
wire _T_376 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 110:86]
|
||||
wire _T_378 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 110:86]
|
||||
wire _T_380 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 110:86]
|
||||
wire [31:0] _T_382 = _T_374 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_383 = _T_376 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_384 = _T_378 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_385 = _T_380 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_386 = _T_382 | _T_383; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_387 = _T_386 | _T_384; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_388 = _T_387 | _T_385; // @[Mux.scala 27:72]
|
||||
wire _T_391 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 111:77]
|
||||
wire _T_394 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 111:77]
|
||||
wire _T_397 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 111:77]
|
||||
wire _T_400 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 111:77]
|
||||
wire [31:0] _T_402 = _T_391 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_403 = _T_394 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_404 = _T_397 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_405 = _T_400 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_406 = _T_402 | _T_403; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_407 = _T_406 | _T_404; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_408 = _T_407 | _T_405; // @[Mux.scala 27:72]
|
||||
wire [63:0] iccm_rd_data_pre = {_T_388,_T_408}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_414 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58]
|
||||
wire [38:0] _T_420 = _T_374 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_421 = _T_376 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_422 = _T_378 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_423 = _T_380 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_424 = _T_420 | _T_421; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_425 = _T_424 | _T_422; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_426 = _T_425 | _T_423; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_436 = _T_391 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_437 = _T_394 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_438 = _T_397 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_439 = _T_400 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_440 = _T_436 | _T_437; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_441 = _T_440 | _T_438; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_442 = _T_441 | _T_439; // @[Mux.scala 27:72]
|
||||
assign _T_85__T_105_addr = _T_85__T_105_addr_pipe_0;
|
||||
assign _T_85__T_105_data = _T_85[_T_85__T_105_addr]; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
wire _T_382 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 110:86]
|
||||
wire _T_384 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 110:86]
|
||||
wire _T_386 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 110:86]
|
||||
wire _T_388 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 110:86]
|
||||
wire [31:0] _T_390 = _T_382 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_391 = _T_384 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_392 = _T_386 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_393 = _T_388 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_394 = _T_390 | _T_391; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_395 = _T_394 | _T_392; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_396 = _T_395 | _T_393; // @[Mux.scala 27:72]
|
||||
wire _T_399 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 111:77]
|
||||
wire _T_402 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 111:77]
|
||||
wire _T_405 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 111:77]
|
||||
wire _T_408 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 111:77]
|
||||
wire [31:0] _T_410 = _T_399 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_411 = _T_402 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_412 = _T_405 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_413 = _T_408 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_414 = _T_410 | _T_411; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_415 = _T_414 | _T_412; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_416 = _T_415 | _T_413; // @[Mux.scala 27:72]
|
||||
wire [63:0] iccm_rd_data_pre = {_T_396,_T_416}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_422 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58]
|
||||
wire [38:0] _T_428 = _T_382 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_429 = _T_384 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_430 = _T_386 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_431 = _T_388 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_432 = _T_428 | _T_429; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_433 = _T_432 | _T_430; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_434 = _T_433 | _T_431; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_444 = _T_399 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_445 = _T_402 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_446 = _T_405 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_447 = _T_408 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_448 = _T_444 | _T_445; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_449 = _T_448 | _T_446; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_450 = _T_449 | _T_447; // @[Mux.scala 27:72]
|
||||
assign _T_85__T_108_addr = _T_85__T_108_addr_pipe_0;
|
||||
assign _T_85__T_108_data = _T_85[_T_85__T_108_addr]; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
assign _T_85__T_101_data = io_iccm_wr_data[38:0];
|
||||
assign _T_85__T_101_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign _T_85__T_101_mask = 1'h1;
|
||||
assign _T_85__T_101_en = iccm_clken_0 & wren_bank_0;
|
||||
assign _T_86__T_107_addr = _T_86__T_107_addr_pipe_0;
|
||||
assign _T_86__T_107_data = _T_86[_T_86__T_107_addr]; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
assign _T_86__T_112_addr = _T_86__T_112_addr_pipe_0;
|
||||
assign _T_86__T_112_data = _T_86[_T_86__T_112_addr]; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
assign _T_86__T_102_data = io_iccm_wr_data[77:39];
|
||||
assign _T_86__T_102_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_67;
|
||||
assign _T_86__T_102_mask = 1'h1;
|
||||
assign _T_86__T_102_en = iccm_clken_1 & wren_bank_1;
|
||||
assign _T_87__T_109_addr = _T_87__T_109_addr_pipe_0;
|
||||
assign _T_87__T_109_data = _T_87[_T_87__T_109_addr]; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
assign _T_87__T_116_addr = _T_87__T_116_addr_pipe_0;
|
||||
assign _T_87__T_116_data = _T_87[_T_87__T_116_addr]; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
assign _T_87__T_103_data = io_iccm_wr_data[38:0];
|
||||
assign _T_87__T_103_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_75;
|
||||
assign _T_87__T_103_mask = 1'h1;
|
||||
assign _T_87__T_103_en = iccm_clken_2 & wren_bank_2;
|
||||
assign _T_88__T_111_addr = _T_88__T_111_addr_pipe_0;
|
||||
assign _T_88__T_111_data = _T_88[_T_88__T_111_addr]; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
assign _T_88__T_120_addr = _T_88__T_120_addr_pipe_0;
|
||||
assign _T_88__T_120_data = _T_88[_T_88__T_120_addr]; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
assign _T_88__T_104_data = io_iccm_wr_data[77:39];
|
||||
assign _T_88__T_104_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_83;
|
||||
assign _T_88__T_104_mask = 1'h1;
|
||||
assign _T_88__T_104_en = iccm_clken_3 & wren_bank_3;
|
||||
assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_414 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 112:19]
|
||||
assign io_iccm_rd_data_ecc = {_T_426,_T_442}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 113:23]
|
||||
assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_422 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 112:19]
|
||||
assign io_iccm_rd_data_ecc = {_T_434,_T_450}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 113:23]
|
||||
assign io_iccm_bank_addr_0 = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; // @[el2_ifu_iccm_mem.scala 61:21]
|
||||
assign io_iccm_bank_addr_1 = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_67; // @[el2_ifu_iccm_mem.scala 61:21]
|
||||
assign io_iccm_bank_addr_2 = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_75; // @[el2_ifu_iccm_mem.scala 61:21]
|
||||
|
|
@ -339,37 +347,37 @@ initial begin
|
|||
_RAND_0 = {2{`RANDOM}};
|
||||
for (initvar = 0; initvar < 4096; initvar = initvar+1)
|
||||
_T_85[initvar] = _RAND_0[38:0];
|
||||
_RAND_2 = {2{`RANDOM}};
|
||||
_RAND_3 = {2{`RANDOM}};
|
||||
for (initvar = 0; initvar < 4096; initvar = initvar+1)
|
||||
_T_86[initvar] = _RAND_2[38:0];
|
||||
_RAND_4 = {2{`RANDOM}};
|
||||
for (initvar = 0; initvar < 4096; initvar = initvar+1)
|
||||
_T_87[initvar] = _RAND_4[38:0];
|
||||
_T_86[initvar] = _RAND_3[38:0];
|
||||
_RAND_6 = {2{`RANDOM}};
|
||||
for (initvar = 0; initvar < 4096; initvar = initvar+1)
|
||||
_T_88[initvar] = _RAND_6[38:0];
|
||||
_T_87[initvar] = _RAND_6[38:0];
|
||||
_RAND_9 = {2{`RANDOM}};
|
||||
for (initvar = 0; initvar < 4096; initvar = initvar+1)
|
||||
_T_88[initvar] = _RAND_9[38:0];
|
||||
`endif // RANDOMIZE_MEM_INIT
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
_RAND_1 = {1{`RANDOM}};
|
||||
_T_85__T_105_addr_pipe_0 = _RAND_1[11:0];
|
||||
_RAND_3 = {1{`RANDOM}};
|
||||
_T_86__T_107_addr_pipe_0 = _RAND_3[11:0];
|
||||
_T_85__T_108_en_pipe_0 = _RAND_1[0:0];
|
||||
_RAND_2 = {1{`RANDOM}};
|
||||
_T_85__T_108_addr_pipe_0 = _RAND_2[11:0];
|
||||
_RAND_4 = {1{`RANDOM}};
|
||||
_T_86__T_112_en_pipe_0 = _RAND_4[0:0];
|
||||
_RAND_5 = {1{`RANDOM}};
|
||||
_T_87__T_109_addr_pipe_0 = _RAND_5[11:0];
|
||||
_T_86__T_112_addr_pipe_0 = _RAND_5[11:0];
|
||||
_RAND_7 = {1{`RANDOM}};
|
||||
_T_88__T_111_addr_pipe_0 = _RAND_7[11:0];
|
||||
_RAND_8 = {2{`RANDOM}};
|
||||
iccm_bank_dout_0 = _RAND_8[38:0];
|
||||
_RAND_9 = {2{`RANDOM}};
|
||||
iccm_bank_dout_1 = _RAND_9[38:0];
|
||||
_RAND_10 = {2{`RANDOM}};
|
||||
iccm_bank_dout_2 = _RAND_10[38:0];
|
||||
_RAND_11 = {2{`RANDOM}};
|
||||
iccm_bank_dout_3 = _RAND_11[38:0];
|
||||
_T_87__T_116_en_pipe_0 = _RAND_7[0:0];
|
||||
_RAND_8 = {1{`RANDOM}};
|
||||
_T_87__T_116_addr_pipe_0 = _RAND_8[11:0];
|
||||
_RAND_10 = {1{`RANDOM}};
|
||||
_T_88__T_120_en_pipe_0 = _RAND_10[0:0];
|
||||
_RAND_11 = {1{`RANDOM}};
|
||||
_T_88__T_120_addr_pipe_0 = _RAND_11[11:0];
|
||||
_RAND_12 = {1{`RANDOM}};
|
||||
_T_313 = _RAND_12[0:0];
|
||||
_T_321 = _RAND_12[0:0];
|
||||
_RAND_13 = {1{`RANDOM}};
|
||||
_T_314 = _RAND_13[0:0];
|
||||
_T_322 = _RAND_13[0:0];
|
||||
_RAND_14 = {1{`RANDOM}};
|
||||
redundant_address_1 = _RAND_14[13:0];
|
||||
_RAND_15 = {1{`RANDOM}};
|
||||
|
|
@ -399,56 +407,64 @@ end // initial
|
|||
if(_T_85__T_101_en & _T_85__T_101_mask) begin
|
||||
_T_85[_T_85__T_101_addr] <= _T_85__T_101_data; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
end
|
||||
_T_85__T_108_en_pipe_0 <= iccm_clken_0 & _T_93;
|
||||
if (iccm_clken_0 & _T_93) begin
|
||||
if (wren_bank_0) begin
|
||||
_T_85__T_105_addr_pipe_0 <= io_iccm_rw_addr[14:3];
|
||||
_T_85__T_108_addr_pipe_0 <= io_iccm_rw_addr[14:3];
|
||||
end else if (_T_12) begin
|
||||
_T_85__T_105_addr_pipe_0 <= addr_bank_inc[14:3];
|
||||
_T_85__T_108_addr_pipe_0 <= addr_bank_inc[14:3];
|
||||
end else begin
|
||||
_T_85__T_105_addr_pipe_0 <= io_iccm_rw_addr[14:3];
|
||||
_T_85__T_108_addr_pipe_0 <= io_iccm_rw_addr[14:3];
|
||||
end
|
||||
end
|
||||
if(_T_86__T_102_en & _T_86__T_102_mask) begin
|
||||
_T_86[_T_86__T_102_addr] <= _T_86__T_102_data; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
end
|
||||
_T_86__T_112_en_pipe_0 <= iccm_clken_1 & _T_95;
|
||||
if (iccm_clken_1 & _T_95) begin
|
||||
if (wren_bank_1) begin
|
||||
_T_86__T_107_addr_pipe_0 <= io_iccm_rw_addr[14:3];
|
||||
_T_86__T_112_addr_pipe_0 <= io_iccm_rw_addr[14:3];
|
||||
end else if (_T_17) begin
|
||||
_T_86__T_107_addr_pipe_0 <= addr_bank_inc[14:3];
|
||||
_T_86__T_112_addr_pipe_0 <= addr_bank_inc[14:3];
|
||||
end else begin
|
||||
_T_86__T_107_addr_pipe_0 <= io_iccm_rw_addr[14:3];
|
||||
_T_86__T_112_addr_pipe_0 <= io_iccm_rw_addr[14:3];
|
||||
end
|
||||
end
|
||||
if(_T_87__T_103_en & _T_87__T_103_mask) begin
|
||||
_T_87[_T_87__T_103_addr] <= _T_87__T_103_data; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
end
|
||||
_T_87__T_116_en_pipe_0 <= iccm_clken_2 & _T_97;
|
||||
if (iccm_clken_2 & _T_97) begin
|
||||
if (wren_bank_2) begin
|
||||
_T_87__T_109_addr_pipe_0 <= io_iccm_rw_addr[14:3];
|
||||
_T_87__T_116_addr_pipe_0 <= io_iccm_rw_addr[14:3];
|
||||
end else if (_T_22) begin
|
||||
_T_87__T_109_addr_pipe_0 <= addr_bank_inc[14:3];
|
||||
_T_87__T_116_addr_pipe_0 <= addr_bank_inc[14:3];
|
||||
end else begin
|
||||
_T_87__T_109_addr_pipe_0 <= io_iccm_rw_addr[14:3];
|
||||
_T_87__T_116_addr_pipe_0 <= io_iccm_rw_addr[14:3];
|
||||
end
|
||||
end
|
||||
if(_T_88__T_104_en & _T_88__T_104_mask) begin
|
||||
_T_88[_T_88__T_104_addr] <= _T_88__T_104_data; // @[el2_ifu_iccm_mem.scala 43:59]
|
||||
end
|
||||
_T_88__T_120_en_pipe_0 <= iccm_clken_3 & _T_99;
|
||||
if (iccm_clken_3 & _T_99) begin
|
||||
if (wren_bank_3) begin
|
||||
_T_88__T_111_addr_pipe_0 <= io_iccm_rw_addr[14:3];
|
||||
_T_88__T_120_addr_pipe_0 <= io_iccm_rw_addr[14:3];
|
||||
end else if (_T_27) begin
|
||||
_T_88__T_111_addr_pipe_0 <= addr_bank_inc[14:3];
|
||||
_T_88__T_120_addr_pipe_0 <= addr_bank_inc[14:3];
|
||||
end else begin
|
||||
_T_88__T_111_addr_pipe_0 <= io_iccm_rw_addr[14:3];
|
||||
_T_88__T_120_addr_pipe_0 <= io_iccm_rw_addr[14:3];
|
||||
end
|
||||
iccm_bank_dout_0 <= _T_85__T_105_data;
|
||||
iccm_bank_dout_1 <= _T_86__T_107_data;
|
||||
iccm_bank_dout_2 <= _T_87__T_109_data;
|
||||
iccm_bank_dout_3 <= _T_88__T_111_data;
|
||||
if (reset) begin
|
||||
_T_313 <= 1'h0;
|
||||
end else begin
|
||||
_T_313 <= _GEN_23;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_314 <= 1'h0;
|
||||
_T_321 <= 1'h0;
|
||||
end else begin
|
||||
_T_314 <= _GEN_24;
|
||||
_T_321 <= _GEN_39;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_322 <= 1'h0;
|
||||
end else begin
|
||||
_T_322 <= _GEN_40;
|
||||
end
|
||||
if (reset) begin
|
||||
redundant_address_1 <= 14'h0;
|
||||
|
|
@ -473,7 +489,7 @@ end // initial
|
|||
if (reset) begin
|
||||
redundant_data_1 <= 39'h0;
|
||||
end else if (redundant_data1_en) begin
|
||||
if (_T_366) begin
|
||||
if (_T_374) begin
|
||||
redundant_data_1 <= iccm_bank_wr_data_1;
|
||||
end else begin
|
||||
redundant_data_1 <= iccm_bank_wr_data_0;
|
||||
|
|
@ -482,7 +498,7 @@ end // initial
|
|||
if (reset) begin
|
||||
redundant_data_0 <= 39'h0;
|
||||
end else if (redundant_data0_en) begin
|
||||
if (_T_338) begin
|
||||
if (_T_346) begin
|
||||
redundant_data_0 <= iccm_bank_wr_data_1;
|
||||
end else begin
|
||||
redundant_data_0 <= iccm_bank_wr_data_0;
|
||||
|
|
@ -492,9 +508,9 @@ end // initial
|
|||
redundant_lru <= 1'h0;
|
||||
end else if (redundant_lru_en) begin
|
||||
if (io_iccm_buf_correct_ecc) begin
|
||||
redundant_lru <= _T_297;
|
||||
redundant_lru <= _T_305;
|
||||
end else begin
|
||||
redundant_lru <= _T_298;
|
||||
redundant_lru <= _T_306;
|
||||
end
|
||||
end
|
||||
if (reset) begin
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ class el2_ifu_iccm_mem extends Module with el2_lib {
|
|||
|
||||
for(i<-0 until ICCM_NUM_BANKS) when(write_vec(i)) {iccm_mem(i)(addr_bank(i)) := iccm_bank_wr_data(i)}
|
||||
|
||||
for(i<-0 until ICCM_NUM_BANKS) {iccm_bank_dout(i) := RegNext(iccm_mem(i).read(addr_bank(i)))}
|
||||
for(i<-0 until ICCM_NUM_BANKS) {iccm_bank_dout(i) := iccm_mem(i).read(addr_bank(i),read_enable(i))}
|
||||
//(0 until ICCM_NUM_BANKS).map(i=> )
|
||||
|
||||
// iccm_bank_dout(i) := RegNext(inter(i))
|
||||
|
|
|
|||
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Reference in New Issue