QUASAR added

dbg.anno.json

@@ -0,0 +1,59 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~dbg|dbg>io_dbg_resume_req",
+    "sources":[
+      "~dbg|dbg>io_dec_tlu_mpc_halted_only",
+      "~dbg|dbg>io_core_dbg_cmd_done",
+      "~dbg|dbg>io_dbg_dec_dma_dbg_ib_dbg_cmd_valid",
+      "~dbg|dbg>io_dbg_dma_dma_dbg_ready",
+      "~dbg|dbg>io_dbg_bus_clk_en",
+      "~dbg|dbg>io_sb_axi_r_valid",
+      "~dbg|dbg>io_sb_axi_r_ready",
+      "~dbg|dbg>io_sb_axi_b_valid",
+      "~dbg|dbg>io_sb_axi_b_ready",
+      "~dbg|dbg>reset",
+      "~dbg|dbg>io_sb_axi_ar_valid",
+      "~dbg|dbg>io_sb_axi_ar_ready",
+      "~dbg|dbg>io_sb_axi_aw_valid",
+      "~dbg|dbg>io_sb_axi_aw_ready",
+      "~dbg|dbg>io_sb_axi_w_valid",
+      "~dbg|dbg>io_sb_axi_w_ready"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~dbg|dbg>io_dbg_core_rst_l",
+    "sources":[
+      "~dbg|dbg>io_scan_mode"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~dbg|dbg>io_dbg_dec_dma_dbg_ib_dbg_cmd_valid",
+    "sources":[
+      "~dbg|dbg>io_dbg_dma_dma_dbg_ready"
+    ]
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxResourceAnno",
+    "target":"dbg.gated_latch",
+    "resourceId":"/vsrc/gated_latch.sv"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"dbg"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]

src/main/scala/pic_ctrl.scala

@@ -10,7 +10,7 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
   val io = IO (new Bundle {
     val scan_mode              = Input(Bool())
     val free_clk               = Input(Clock () )
-    val active_clk             = Input(Clock () )
+    val io_clk_override        = Input(Bool () )
     val clk_override           = Input(Bool () )
     val extintsrc_req          = Input(UInt (PIC_TOTAL_INT_PLUS1.W))
     val lsu_pic = Flipped(new lsu_pic())
@@ -101,9 +101,9 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
 
   withClock(pic_raddr_c1_clk) {picm_raddr_ff := RegNext(io.lsu_pic.picm_rdaddr,0.U)}
   withClock(pic_data_c1_clk)  {picm_waddr_ff := RegNext (io.lsu_pic.picm_wraddr,0.U)}
-  withClock(io.active_clk)    {picm_wren_ff := RegNext(io.lsu_pic.picm_wren,0.U)}
-  withClock(io.active_clk)    {picm_rden_ff := RegNext(io.lsu_pic.picm_rden,0.U)}
-  withClock(io.active_clk)    {picm_mken_ff := RegNext(io.lsu_pic.picm_mken,0.U)}
+  withClock(io.free_clk)    {picm_wren_ff := RegNext(io.lsu_pic.picm_wren,0.U)}
+  withClock(io.free_clk)    {picm_rden_ff := RegNext(io.lsu_pic.picm_rden,0.U)}
+  withClock(io.free_clk)    {picm_mken_ff := RegNext(io.lsu_pic.picm_mken,0.U)}
   withClock(pic_data_c1_clk)  {picm_wr_data_ff := RegNext(io.lsu_pic.picm_wr_data,0.U)}
 
   val temp_raddr_intenable_base_match =   ~(picm_raddr_ff ^ INTENABLE_BASE_ADDR.asUInt)
@@ -134,7 +134,7 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
   pic_data_c1_clk   := rvclkhdr(clock,pic_data_c1_clken,io.scan_mode)
   pic_pri_c1_clk    := rvclkhdr(clock,pic_pri_c1_clken.asBool,io.scan_mode)
   pic_int_c1_clk    := rvclkhdr(clock,pic_int_c1_clken.asBool,io.scan_mode)
-  gw_config_c1_clk  := rvclkhdr(clock,gw_config_c1_clken.asBool,io.scan_mode)
+  gw_config_c1_clk  := rvclkhdr(clock,(gw_config_c1_clken | io.io_clk_override).asBool,io.scan_mode)
 
   // ------ end clock gating section ------------------------
   val extintsrc_req_sync  = Cat(rvsyncss(io.extintsrc_req(PIC_TOTAL_INT_PLUS1-1,1),io.free_clk),io.extintsrc_req(0))

src/main/scala/quasar.scala

@@ -232,8 +232,8 @@ class quasar extends Module with RequireAsyncReset with lib {
   pic_ctrl_inst.clock := io.free_l2clk
   pic_ctrl_inst.reset := io.core_rst_l
   pic_ctrl_inst.io.free_clk := free_clk
-  pic_ctrl_inst.io.active_clk := active_clk
-  pic_ctrl_inst.io.clk_override := dec.io.dec_tlu_picio_clk_override
+  pic_ctrl_inst.io.io_clk_override := dec.io.dec_tlu_picio_clk_override
+  pic_ctrl_inst.io.clk_override := dec.io.dec_tlu_pic_clk_override
   pic_ctrl_inst.io.extintsrc_req := Cat(io.extintsrc_req,0.U)
   pic_ctrl_inst.io.lsu_pic <> lsu.io.lsu_pic
   pic_ctrl_inst.io.dec_pic <> dec.io.dec_pic