From 195b0904c31dd527cedda00329a62302c1f43099 Mon Sep 17 00:00:00 2001
From: Sarmad-paracha <67508400+Sarmad-paracha@users.noreply.github.com>
Date: Thu, 24 Sep 2020 11:02:59 +0500
Subject: [PATCH 1/3] Rename el2_ifu_compress.scala to
 el2_ifu_compress_ctl.scala

---
 .../ifu/{el2_ifu_compress.scala => el2_ifu_compress_ctl.scala}  | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
 rename src/main/scala/ifu/{el2_ifu_compress.scala => el2_ifu_compress_ctl.scala} (99%)

diff --git a/src/main/scala/ifu/el2_ifu_compress.scala b/src/main/scala/ifu/el2_ifu_compress_ctl.scala
similarity index 99%
rename from src/main/scala/ifu/el2_ifu_compress.scala
rename to src/main/scala/ifu/el2_ifu_compress_ctl.scala
index 70ad77d0..f15b3e1b 100644
--- a/src/main/scala/ifu/el2_ifu_compress.scala
+++ b/src/main/scala/ifu/el2_ifu_compress_ctl.scala
@@ -223,4 +223,4 @@ class el2_ifu_compress( val XLen: Int, val usingCompressed: Boolean) extends Mod
 
 object ifu_compress extends App {
   println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress(64, true)))
-}
\ No newline at end of file
+}

From 682c9269c9796aa72e78c688239d8d048ae0e2fd Mon Sep 17 00:00:00 2001
From: Sarmad-paracha <67508400+Sarmad-paracha@users.noreply.github.com>
Date: Thu, 24 Sep 2020 18:24:40 +0500
Subject: [PATCH 2/3] Update el2_ifu_compress_ctl.scala

---
 src/main/scala/ifu/el2_ifu_compress_ctl.scala | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/main/scala/ifu/el2_ifu_compress_ctl.scala b/src/main/scala/ifu/el2_ifu_compress_ctl.scala
index f15b3e1b..7471c9b3 100644
--- a/src/main/scala/ifu/el2_ifu_compress_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_compress_ctl.scala
@@ -2,7 +2,6 @@ package ifu
 
 import chisel3._
 import chisel3.util._
-import lib.ExpandedInstruction
 
 class ExpandedInstruction extends Bundle {
   val bits = UInt(32.W)

From dc471419161dcd70934a10e10820f4a98eec4737 Mon Sep 17 00:00:00 2001
From: Sarmad-paracha <67508400+Sarmad-paracha@users.noreply.github.com>
Date: Thu, 24 Sep 2020 18:28:06 +0500
Subject: [PATCH 3/3] Update el2_ifu_compress_ctl.scala

---
 src/main/scala/ifu/el2_ifu_compress_ctl.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/ifu/el2_ifu_compress_ctl.scala b/src/main/scala/ifu/el2_ifu_compress_ctl.scala
index 7471c9b3..e46ced94 100644
--- a/src/main/scala/ifu/el2_ifu_compress_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_compress_ctl.scala
@@ -177,7 +177,7 @@ class RVCDecoder(x: UInt, xLen: Int) {
   def ret_q3 = q3
 }
 
-class el2_ifu_compress( val XLen: Int, val usingCompressed: Boolean) extends Module  {
+class el2_ifu_compress_ctl( val XLen: Int, val usingCompressed: Boolean) extends Module  {
   val io = IO(new Bundle {
     val in = Input(UInt(32.W))
     val out = Output(new ExpandedInstruction)
@@ -221,5 +221,5 @@ class el2_ifu_compress( val XLen: Int, val usingCompressed: Boolean) extends Mod
 }
 
 object ifu_compress extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress(64, true)))
+  println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress_ctl(64, true)))
 }