From e24a5f750f6b8d22f701635e7960c9c807419c87 Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Mon, 14 Dec 2020 18:22:02 +0500 Subject: [PATCH] Bridge conf updated --- ahb_to_axi4.anno.json | 34 + ahb_to_axi4.fir | 618 ++--- ahb_to_axi4.v | 584 +++++ axi4_to_ahb.anno.json | 113 + axi4_to_ahb.fir | 1406 +++++++++++ axi4_to_ahb.v | 1139 +++++++++ quasar_wrapper.fir | 1376 +++++------ quasar_wrapper.v | 2672 +++++++-------------- src/main/scala/lib/ahb_to_axi4.scala | 2 +- src/main/scala/lib/axi4_to_ahb.scala | 2 +- src/main/scala/lib/param.scala | 4 +- src/main/scala/quasar.scala | 17 +- target/scala-2.12/classes/lib/param.class | Bin 23339 -> 23339 bytes target/scala-2.12/classes/quasar.class | Bin 146654 -> 154782 bytes 14 files changed, 5032 insertions(+), 2935 deletions(-) create mode 100644 ahb_to_axi4.anno.json create mode 100644 ahb_to_axi4.v create mode 100644 axi4_to_ahb.anno.json create mode 100644 axi4_to_ahb.fir create mode 100644 axi4_to_ahb.v diff --git a/ahb_to_axi4.anno.json b/ahb_to_axi4.anno.json new file mode 100644 index 00000000..e256d28b --- /dev/null +++ b/ahb_to_axi4.anno.json @@ -0,0 +1,34 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~ahb_to_axi4|ahb_to_axi4>io_ahb_sig_in_hready", + "sources":[ + "~ahb_to_axi4|ahb_to_axi4>io_ahb_sig_in_hresp", + "~ahb_to_axi4|ahb_to_axi4>io_axi_aw_valid", + "~ahb_to_axi4|ahb_to_axi4>io_axi_aw_ready", + "~ahb_to_axi4|ahb_to_axi4>io_axi_ar_valid", + "~ahb_to_axi4|ahb_to_axi4>io_axi_ar_ready" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"ahb_to_axi4.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"ahb_to_axi4" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/ahb_to_axi4.fir b/ahb_to_axi4.fir index a96f75ed..1ae07a04 100644 --- a/ahb_to_axi4.fir +++ b/ahb_to_axi4.fir @@ -147,87 +147,87 @@ circuit ahb_to_axi4 : module ahb_to_axi4 : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, hreadyout : UInt<1>, flip hsel : UInt<1>, flip hreadyin : UInt<1>}} + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}} - wire _T : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[ahb_to_axi4.scala 21:25] - _T.r.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 21:25] - _T.r.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 21:25] - _T.r.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 21:25] - _T.r.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 21:25] - _T.r.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 21:25] - _T.r.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 21:25] - _T.ar.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 21:25] - _T.ar.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 21:25] - _T.ar.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 21:25] - _T.ar.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 21:25] - _T.ar.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 21:25] - _T.ar.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 21:25] - _T.ar.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 21:25] - _T.ar.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 21:25] - _T.ar.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 21:25] - _T.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 21:25] - _T.ar.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 21:25] - _T.ar.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 21:25] - _T.b.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 21:25] - _T.b.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 21:25] - _T.b.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 21:25] - _T.b.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 21:25] - _T.w.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 21:25] - _T.w.bits.strb <= UInt<8>("h00") @[ahb_to_axi4.scala 21:25] - _T.w.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 21:25] - _T.w.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 21:25] - _T.w.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 21:25] - _T.aw.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 21:25] - _T.aw.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 21:25] - _T.aw.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 21:25] - _T.aw.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 21:25] - _T.aw.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 21:25] - _T.aw.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 21:25] - _T.aw.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 21:25] - _T.aw.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 21:25] - _T.aw.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 21:25] - _T.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 21:25] - _T.aw.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 21:25] - _T.aw.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 21:25] - _T.r.bits.last <= io.axi.r.bits.last @[ahb_to_axi4.scala 21:10] - _T.r.bits.resp <= io.axi.r.bits.resp @[ahb_to_axi4.scala 21:10] - _T.r.bits.data <= io.axi.r.bits.data @[ahb_to_axi4.scala 21:10] - _T.r.bits.id <= io.axi.r.bits.id @[ahb_to_axi4.scala 21:10] - _T.r.valid <= io.axi.r.valid @[ahb_to_axi4.scala 21:10] - io.axi.r.ready <= _T.r.ready @[ahb_to_axi4.scala 21:10] - io.axi.ar.bits.qos <= _T.ar.bits.qos @[ahb_to_axi4.scala 21:10] - io.axi.ar.bits.prot <= _T.ar.bits.prot @[ahb_to_axi4.scala 21:10] - io.axi.ar.bits.cache <= _T.ar.bits.cache @[ahb_to_axi4.scala 21:10] - io.axi.ar.bits.lock <= _T.ar.bits.lock @[ahb_to_axi4.scala 21:10] - io.axi.ar.bits.burst <= _T.ar.bits.burst @[ahb_to_axi4.scala 21:10] - io.axi.ar.bits.size <= _T.ar.bits.size @[ahb_to_axi4.scala 21:10] - io.axi.ar.bits.len <= _T.ar.bits.len @[ahb_to_axi4.scala 21:10] - io.axi.ar.bits.region <= _T.ar.bits.region @[ahb_to_axi4.scala 21:10] - io.axi.ar.bits.addr <= _T.ar.bits.addr @[ahb_to_axi4.scala 21:10] - io.axi.ar.bits.id <= _T.ar.bits.id @[ahb_to_axi4.scala 21:10] - io.axi.ar.valid <= _T.ar.valid @[ahb_to_axi4.scala 21:10] - _T.ar.ready <= io.axi.ar.ready @[ahb_to_axi4.scala 21:10] - _T.b.bits.id <= io.axi.b.bits.id @[ahb_to_axi4.scala 21:10] - _T.b.bits.resp <= io.axi.b.bits.resp @[ahb_to_axi4.scala 21:10] - _T.b.valid <= io.axi.b.valid @[ahb_to_axi4.scala 21:10] - io.axi.b.ready <= _T.b.ready @[ahb_to_axi4.scala 21:10] - io.axi.w.bits.last <= _T.w.bits.last @[ahb_to_axi4.scala 21:10] - io.axi.w.bits.strb <= _T.w.bits.strb @[ahb_to_axi4.scala 21:10] - io.axi.w.bits.data <= _T.w.bits.data @[ahb_to_axi4.scala 21:10] - io.axi.w.valid <= _T.w.valid @[ahb_to_axi4.scala 21:10] - _T.w.ready <= io.axi.w.ready @[ahb_to_axi4.scala 21:10] - io.axi.aw.bits.qos <= _T.aw.bits.qos @[ahb_to_axi4.scala 21:10] - io.axi.aw.bits.prot <= _T.aw.bits.prot @[ahb_to_axi4.scala 21:10] - io.axi.aw.bits.cache <= _T.aw.bits.cache @[ahb_to_axi4.scala 21:10] - io.axi.aw.bits.lock <= _T.aw.bits.lock @[ahb_to_axi4.scala 21:10] - io.axi.aw.bits.burst <= _T.aw.bits.burst @[ahb_to_axi4.scala 21:10] - io.axi.aw.bits.size <= _T.aw.bits.size @[ahb_to_axi4.scala 21:10] - io.axi.aw.bits.len <= _T.aw.bits.len @[ahb_to_axi4.scala 21:10] - io.axi.aw.bits.region <= _T.aw.bits.region @[ahb_to_axi4.scala 21:10] - io.axi.aw.bits.addr <= _T.aw.bits.addr @[ahb_to_axi4.scala 21:10] - io.axi.aw.bits.id <= _T.aw.bits.id @[ahb_to_axi4.scala 21:10] - io.axi.aw.valid <= _T.aw.valid @[ahb_to_axi4.scala 21:10] - _T.aw.ready <= io.axi.aw.ready @[ahb_to_axi4.scala 21:10] + wire _T : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[ahb_to_axi4.scala 20:25] + _T.r.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.b.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.b.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] + _T.b.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.b.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.bits.strb <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.bits.last <= io.axi.r.bits.last @[ahb_to_axi4.scala 20:10] + _T.r.bits.resp <= io.axi.r.bits.resp @[ahb_to_axi4.scala 20:10] + _T.r.bits.data <= io.axi.r.bits.data @[ahb_to_axi4.scala 20:10] + _T.r.bits.id <= io.axi.r.bits.id @[ahb_to_axi4.scala 20:10] + _T.r.valid <= io.axi.r.valid @[ahb_to_axi4.scala 20:10] + io.axi.r.ready <= _T.r.ready @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.qos <= _T.ar.bits.qos @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.prot <= _T.ar.bits.prot @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.cache <= _T.ar.bits.cache @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.lock <= _T.ar.bits.lock @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.burst <= _T.ar.bits.burst @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.size <= _T.ar.bits.size @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.len <= _T.ar.bits.len @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.region <= _T.ar.bits.region @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.addr <= _T.ar.bits.addr @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.id <= _T.ar.bits.id @[ahb_to_axi4.scala 20:10] + io.axi.ar.valid <= _T.ar.valid @[ahb_to_axi4.scala 20:10] + _T.ar.ready <= io.axi.ar.ready @[ahb_to_axi4.scala 20:10] + _T.b.bits.id <= io.axi.b.bits.id @[ahb_to_axi4.scala 20:10] + _T.b.bits.resp <= io.axi.b.bits.resp @[ahb_to_axi4.scala 20:10] + _T.b.valid <= io.axi.b.valid @[ahb_to_axi4.scala 20:10] + io.axi.b.ready <= _T.b.ready @[ahb_to_axi4.scala 20:10] + io.axi.w.bits.last <= _T.w.bits.last @[ahb_to_axi4.scala 20:10] + io.axi.w.bits.strb <= _T.w.bits.strb @[ahb_to_axi4.scala 20:10] + io.axi.w.bits.data <= _T.w.bits.data @[ahb_to_axi4.scala 20:10] + io.axi.w.valid <= _T.w.valid @[ahb_to_axi4.scala 20:10] + _T.w.ready <= io.axi.w.ready @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.qos <= _T.aw.bits.qos @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.prot <= _T.aw.bits.prot @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.cache <= _T.aw.bits.cache @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.lock <= _T.aw.bits.lock @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.burst <= _T.aw.bits.burst @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.size <= _T.aw.bits.size @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.len <= _T.aw.bits.len @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.region <= _T.aw.bits.region @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.addr <= _T.aw.bits.addr @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.id <= _T.aw.bits.id @[ahb_to_axi4.scala 20:10] + io.axi.aw.valid <= _T.aw.valid @[ahb_to_axi4.scala 20:10] + _T.aw.ready <= io.axi.aw.ready @[ahb_to_axi4.scala 20:10] wire master_wstrb : UInt<8> master_wstrb <= UInt<8>("h00") wire buf_state_en : UInt<1> @@ -262,9 +262,9 @@ circuit ahb_to_axi4 : ahb_bus_addr_clk_en <= UInt<1>("h00") wire buf_rdata_clk_en : UInt<1> buf_rdata_clk_en <= UInt<1>("h00") - wire ahb_clk : Clock @[ahb_to_axi4.scala 45:33] - wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 46:33] - wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 47:33] + wire ahb_clk : Clock @[ahb_to_axi4.scala 44:33] + wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 45:33] + wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 46:33] wire cmdbuf_wr_en : UInt<1> cmdbuf_wr_en <= UInt<1>("h00") wire cmdbuf_rst : UInt<1> @@ -283,7 +283,7 @@ circuit ahb_to_axi4 : cmdbuf_addr <= UInt<32>("h00") wire cmdbuf_wdata : UInt<64> cmdbuf_wdata <= UInt<64>("h00") - wire bus_clk : Clock @[ahb_to_axi4.scala 59:33] + wire bus_clk : Clock @[ahb_to_axi4.scala 58:33] node _T_1 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] node ahb_addr_in_dccm_region_nc = eq(_T_1, UInt<4>("h0f")) @[lib.scala 84:47] node _T_2 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14] @@ -300,260 +300,260 @@ circuit ahb_to_axi4 : buf_state <= UInt<2>("h00") wire buf_nxtstate : UInt<2> buf_nxtstate <= UInt<2>("h00") - buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 69:31] - buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 70:31] - buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 71:31] - buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 72:31] - cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 73:31] + buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 68:31] + buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 69:31] + buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 70:31] + buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 71:31] + cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 72:31] node _T_7 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30] when _T_7 : @[Conditional.scala 40:58] - node _T_8 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 77:26] - buf_nxtstate <= _T_8 @[ahb_to_axi4.scala 77:20] - node _T_9 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 78:57] - node _T_10 = and(ahb_hready, _T_9) @[ahb_to_axi4.scala 78:34] - node _T_11 = and(_T_10, io.ahb.hsel) @[ahb_to_axi4.scala 78:61] - buf_state_en <= _T_11 @[ahb_to_axi4.scala 78:20] + node _T_8 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 76:26] + buf_nxtstate <= _T_8 @[ahb_to_axi4.scala 76:20] + node _T_9 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 77:57] + node _T_10 = and(ahb_hready, _T_9) @[ahb_to_axi4.scala 77:34] + node _T_11 = and(_T_10, io.ahb.hsel) @[ahb_to_axi4.scala 77:61] + buf_state_en <= _T_11 @[ahb_to_axi4.scala 77:20] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_12 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30] when _T_12 : @[Conditional.scala 39:67] - node _T_13 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 81:72] - node _T_14 = eq(_T_13, UInt<1>("h00")) @[ahb_to_axi4.scala 81:79] - node _T_15 = or(io.ahb.sig.in.hresp, _T_14) @[ahb_to_axi4.scala 81:48] - node _T_16 = eq(io.ahb.hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 81:93] - node _T_17 = or(_T_15, _T_16) @[ahb_to_axi4.scala 81:91] - node _T_18 = bits(_T_17, 0, 0) @[ahb_to_axi4.scala 81:107] - node _T_19 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 81:124] - node _T_20 = mux(_T_18, UInt<2>("h00"), _T_19) @[ahb_to_axi4.scala 81:26] - buf_nxtstate <= _T_20 @[ahb_to_axi4.scala 81:20] - node _T_21 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 82:24] - node _T_22 = or(_T_21, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 82:37] - buf_state_en <= _T_22 @[ahb_to_axi4.scala 82:20] - node _T_23 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 83:23] - node _T_24 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 83:85] - node _T_25 = eq(_T_24, UInt<2>("h01")) @[ahb_to_axi4.scala 83:92] - node _T_26 = and(_T_25, io.ahb.hsel) @[ahb_to_axi4.scala 83:110] - node _T_27 = or(io.ahb.sig.in.hresp, _T_26) @[ahb_to_axi4.scala 83:60] - node _T_28 = eq(_T_27, UInt<1>("h00")) @[ahb_to_axi4.scala 83:38] - node _T_29 = and(_T_23, _T_28) @[ahb_to_axi4.scala 83:36] - cmdbuf_wr_en <= _T_29 @[ahb_to_axi4.scala 83:20] + node _T_13 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 80:72] + node _T_14 = eq(_T_13, UInt<1>("h00")) @[ahb_to_axi4.scala 80:79] + node _T_15 = or(io.ahb.sig.in.hresp, _T_14) @[ahb_to_axi4.scala 80:48] + node _T_16 = eq(io.ahb.hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 80:93] + node _T_17 = or(_T_15, _T_16) @[ahb_to_axi4.scala 80:91] + node _T_18 = bits(_T_17, 0, 0) @[ahb_to_axi4.scala 80:107] + node _T_19 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 80:124] + node _T_20 = mux(_T_18, UInt<2>("h00"), _T_19) @[ahb_to_axi4.scala 80:26] + buf_nxtstate <= _T_20 @[ahb_to_axi4.scala 80:20] + node _T_21 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 81:24] + node _T_22 = or(_T_21, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 81:37] + buf_state_en <= _T_22 @[ahb_to_axi4.scala 81:20] + node _T_23 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 82:23] + node _T_24 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 82:85] + node _T_25 = eq(_T_24, UInt<2>("h01")) @[ahb_to_axi4.scala 82:92] + node _T_26 = and(_T_25, io.ahb.hsel) @[ahb_to_axi4.scala 82:110] + node _T_27 = or(io.ahb.sig.in.hresp, _T_26) @[ahb_to_axi4.scala 82:60] + node _T_28 = eq(_T_27, UInt<1>("h00")) @[ahb_to_axi4.scala 82:38] + node _T_29 = and(_T_23, _T_28) @[ahb_to_axi4.scala 82:36] + cmdbuf_wr_en <= _T_29 @[ahb_to_axi4.scala 82:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_30 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30] when _T_30 : @[Conditional.scala 39:67] - node _T_31 = mux(io.ahb.sig.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 86:26] - buf_nxtstate <= _T_31 @[ahb_to_axi4.scala 86:20] - node _T_32 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 87:24] - node _T_33 = or(_T_32, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 87:37] - buf_state_en <= _T_33 @[ahb_to_axi4.scala 87:20] - node _T_34 = eq(io.ahb.sig.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 88:23] - node _T_35 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 88:46] - node _T_36 = and(_T_34, _T_35) @[ahb_to_axi4.scala 88:44] - cmdbuf_wr_en <= _T_36 @[ahb_to_axi4.scala 88:20] + node _T_31 = mux(io.ahb.sig.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 85:26] + buf_nxtstate <= _T_31 @[ahb_to_axi4.scala 85:20] + node _T_32 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 86:24] + node _T_33 = or(_T_32, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 86:37] + buf_state_en <= _T_33 @[ahb_to_axi4.scala 86:20] + node _T_34 = eq(io.ahb.sig.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 87:23] + node _T_35 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 87:46] + node _T_36 = and(_T_34, _T_35) @[ahb_to_axi4.scala 87:44] + cmdbuf_wr_en <= _T_36 @[ahb_to_axi4.scala 87:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_37 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30] when _T_37 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 91:20] - node _T_38 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 92:40] - node _T_39 = and(io.axi.r.valid, _T_38) @[ahb_to_axi4.scala 92:38] - buf_state_en <= _T_39 @[ahb_to_axi4.scala 92:20] - buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 93:20] - node _T_40 = bits(io.axi.r.bits.resp, 1, 0) @[ahb_to_axi4.scala 94:61] - node _T_41 = orr(_T_40) @[ahb_to_axi4.scala 94:68] - node _T_42 = and(buf_state_en, _T_41) @[ahb_to_axi4.scala 94:41] - buf_read_error_in <= _T_42 @[ahb_to_axi4.scala 94:25] + buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 90:20] + node _T_38 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 91:40] + node _T_39 = and(io.axi.r.valid, _T_38) @[ahb_to_axi4.scala 91:38] + buf_state_en <= _T_39 @[ahb_to_axi4.scala 91:20] + buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 92:20] + node _T_40 = bits(io.axi.r.bits.resp, 1, 0) @[ahb_to_axi4.scala 93:61] + node _T_41 = orr(_T_40) @[ahb_to_axi4.scala 93:68] + node _T_42 = and(buf_state_en, _T_41) @[ahb_to_axi4.scala 93:41] + buf_read_error_in <= _T_42 @[ahb_to_axi4.scala 93:25] skip @[Conditional.scala 39:67] - node _T_43 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 97:99] + node _T_43 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 96:99] reg _T_44 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_43 : @[Reg.scala 28:19] _T_44 <= buf_nxtstate @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_state <= _T_44 @[ahb_to_axi4.scala 97:31] - node _T_45 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 99:54] - node _T_46 = eq(_T_45, UInt<1>("h00")) @[ahb_to_axi4.scala 99:60] + buf_state <= _T_44 @[ahb_to_axi4.scala 96:31] + node _T_45 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 98:54] + node _T_46 = eq(_T_45, UInt<1>("h00")) @[ahb_to_axi4.scala 98:60] node _T_47 = bits(_T_46, 0, 0) @[Bitwise.scala 72:15] node _T_48 = mux(_T_47, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_49 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 99:92] - node _T_50 = dshl(UInt<1>("h01"), _T_49) @[ahb_to_axi4.scala 99:78] - node _T_51 = and(_T_48, _T_50) @[ahb_to_axi4.scala 99:70] - node _T_52 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 100:24] - node _T_53 = eq(_T_52, UInt<1>("h01")) @[ahb_to_axi4.scala 100:30] + node _T_49 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 98:92] + node _T_50 = dshl(UInt<1>("h01"), _T_49) @[ahb_to_axi4.scala 98:78] + node _T_51 = and(_T_48, _T_50) @[ahb_to_axi4.scala 98:70] + node _T_52 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 99:24] + node _T_53 = eq(_T_52, UInt<1>("h01")) @[ahb_to_axi4.scala 99:30] node _T_54 = bits(_T_53, 0, 0) @[Bitwise.scala 72:15] node _T_55 = mux(_T_54, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_56 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 100:62] - node _T_57 = dshl(UInt<2>("h03"), _T_56) @[ahb_to_axi4.scala 100:48] - node _T_58 = and(_T_55, _T_57) @[ahb_to_axi4.scala 100:40] - node _T_59 = or(_T_51, _T_58) @[ahb_to_axi4.scala 99:109] - node _T_60 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 101:24] - node _T_61 = eq(_T_60, UInt<2>("h02")) @[ahb_to_axi4.scala 101:30] + node _T_56 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 99:62] + node _T_57 = dshl(UInt<2>("h03"), _T_56) @[ahb_to_axi4.scala 99:48] + node _T_58 = and(_T_55, _T_57) @[ahb_to_axi4.scala 99:40] + node _T_59 = or(_T_51, _T_58) @[ahb_to_axi4.scala 98:109] + node _T_60 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 100:24] + node _T_61 = eq(_T_60, UInt<2>("h02")) @[ahb_to_axi4.scala 100:30] node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15] node _T_63 = mux(_T_62, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_64 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 101:62] - node _T_65 = dshl(UInt<4>("h0f"), _T_64) @[ahb_to_axi4.scala 101:48] - node _T_66 = and(_T_63, _T_65) @[ahb_to_axi4.scala 101:40] - node _T_67 = or(_T_59, _T_66) @[ahb_to_axi4.scala 100:79] - node _T_68 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 102:24] - node _T_69 = eq(_T_68, UInt<2>("h03")) @[ahb_to_axi4.scala 102:30] + node _T_64 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 100:62] + node _T_65 = dshl(UInt<4>("h0f"), _T_64) @[ahb_to_axi4.scala 100:48] + node _T_66 = and(_T_63, _T_65) @[ahb_to_axi4.scala 100:40] + node _T_67 = or(_T_59, _T_66) @[ahb_to_axi4.scala 99:79] + node _T_68 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 101:24] + node _T_69 = eq(_T_68, UInt<2>("h03")) @[ahb_to_axi4.scala 101:30] node _T_70 = bits(_T_69, 0, 0) @[Bitwise.scala 72:15] node _T_71 = mux(_T_70, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_72 = and(_T_71, UInt<8>("h0ff")) @[ahb_to_axi4.scala 102:40] - node _T_73 = or(_T_67, _T_72) @[ahb_to_axi4.scala 101:79] - master_wstrb <= _T_73 @[ahb_to_axi4.scala 99:31] - node _T_74 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 105:80] - node _T_75 = and(ahb_hresp_q, _T_74) @[ahb_to_axi4.scala 105:78] - node _T_76 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 105:98] - node _T_77 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 105:124] - node _T_78 = or(_T_76, _T_77) @[ahb_to_axi4.scala 105:111] - node _T_79 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 105:149] - node _T_80 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 105:168] - node _T_81 = or(_T_79, _T_80) @[ahb_to_axi4.scala 105:156] - node _T_82 = eq(_T_81, UInt<1>("h00")) @[ahb_to_axi4.scala 105:137] - node _T_83 = and(_T_78, _T_82) @[ahb_to_axi4.scala 105:135] - node _T_84 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 105:181] - node _T_85 = and(_T_83, _T_84) @[ahb_to_axi4.scala 105:179] - node _T_86 = mux(io.ahb.sig.in.hresp, _T_75, _T_85) @[ahb_to_axi4.scala 105:44] - io.ahb.sig.in.hready <= _T_86 @[ahb_to_axi4.scala 105:38] - node _T_87 = and(io.ahb.sig.in.hready, io.ahb.hreadyin) @[ahb_to_axi4.scala 106:55] - ahb_hready <= _T_87 @[ahb_to_axi4.scala 106:31] + node _T_72 = and(_T_71, UInt<8>("h0ff")) @[ahb_to_axi4.scala 101:40] + node _T_73 = or(_T_67, _T_72) @[ahb_to_axi4.scala 100:79] + master_wstrb <= _T_73 @[ahb_to_axi4.scala 98:31] + node _T_74 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 104:80] + node _T_75 = and(ahb_hresp_q, _T_74) @[ahb_to_axi4.scala 104:78] + node _T_76 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 104:98] + node _T_77 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 104:124] + node _T_78 = or(_T_76, _T_77) @[ahb_to_axi4.scala 104:111] + node _T_79 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 104:149] + node _T_80 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 104:168] + node _T_81 = or(_T_79, _T_80) @[ahb_to_axi4.scala 104:156] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[ahb_to_axi4.scala 104:137] + node _T_83 = and(_T_78, _T_82) @[ahb_to_axi4.scala 104:135] + node _T_84 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 104:181] + node _T_85 = and(_T_83, _T_84) @[ahb_to_axi4.scala 104:179] + node _T_86 = mux(io.ahb.sig.in.hresp, _T_75, _T_85) @[ahb_to_axi4.scala 104:44] + io.ahb.sig.in.hready <= _T_86 @[ahb_to_axi4.scala 104:38] + node _T_87 = and(io.ahb.sig.in.hready, io.ahb.hreadyin) @[ahb_to_axi4.scala 105:55] + ahb_hready <= _T_87 @[ahb_to_axi4.scala 105:31] node _T_88 = bits(io.ahb.hsel, 0, 0) @[Bitwise.scala 72:15] node _T_89 = mux(_T_88, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_90 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 107:77] - node _T_91 = and(_T_89, _T_90) @[ahb_to_axi4.scala 107:54] - ahb_htrans_in <= _T_91 @[ahb_to_axi4.scala 107:31] - node _T_92 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 108:50] - io.ahb.sig.in.hrdata <= _T_92 @[ahb_to_axi4.scala 108:38] - node _T_93 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 109:55] - node _T_94 = neq(_T_93, UInt<1>("h00")) @[ahb_to_axi4.scala 109:61] - node _T_95 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 109:83] - node _T_96 = and(_T_94, _T_95) @[ahb_to_axi4.scala 109:70] - node _T_97 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 110:26] - node _T_98 = eq(_T_97, UInt<1>("h00")) @[ahb_to_axi4.scala 110:7] - node _T_99 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 111:46] - node _T_100 = or(ahb_addr_in_iccm, _T_99) @[ahb_to_axi4.scala 111:26] - node _T_101 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 111:80] - node _T_102 = eq(_T_101, UInt<2>("h02")) @[ahb_to_axi4.scala 111:86] - node _T_103 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 111:109] - node _T_104 = eq(_T_103, UInt<2>("h03")) @[ahb_to_axi4.scala 111:115] - node _T_105 = or(_T_102, _T_104) @[ahb_to_axi4.scala 111:95] - node _T_106 = eq(_T_105, UInt<1>("h00")) @[ahb_to_axi4.scala 111:66] - node _T_107 = and(_T_100, _T_106) @[ahb_to_axi4.scala 111:64] - node _T_108 = or(_T_98, _T_107) @[ahb_to_axi4.scala 110:47] - node _T_109 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 112:20] - node _T_110 = eq(_T_109, UInt<1>("h01")) @[ahb_to_axi4.scala 112:26] - node _T_111 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 112:48] - node _T_112 = and(_T_110, _T_111) @[ahb_to_axi4.scala 112:35] - node _T_113 = or(_T_108, _T_112) @[ahb_to_axi4.scala 111:126] - node _T_114 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 113:20] - node _T_115 = eq(_T_114, UInt<2>("h02")) @[ahb_to_axi4.scala 113:26] - node _T_116 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 113:49] - node _T_117 = orr(_T_116) @[ahb_to_axi4.scala 113:56] - node _T_118 = and(_T_115, _T_117) @[ahb_to_axi4.scala 113:35] - node _T_119 = or(_T_113, _T_118) @[ahb_to_axi4.scala 112:55] - node _T_120 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 114:20] - node _T_121 = eq(_T_120, UInt<2>("h03")) @[ahb_to_axi4.scala 114:26] - node _T_122 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 114:49] - node _T_123 = orr(_T_122) @[ahb_to_axi4.scala 114:56] - node _T_124 = and(_T_121, _T_123) @[ahb_to_axi4.scala 114:35] - node _T_125 = or(_T_119, _T_124) @[ahb_to_axi4.scala 113:61] - node _T_126 = and(_T_96, _T_125) @[ahb_to_axi4.scala 109:94] - node _T_127 = or(_T_126, buf_read_error) @[ahb_to_axi4.scala 114:63] - node _T_128 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 116:20] - node _T_129 = and(ahb_hresp_q, _T_128) @[ahb_to_axi4.scala 116:18] - node _T_130 = or(_T_127, _T_129) @[ahb_to_axi4.scala 115:20] - io.ahb.sig.in.hresp <= _T_130 @[ahb_to_axi4.scala 109:38] - reg _T_131 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 119:66] - _T_131 <= io.axi.r.bits.data @[ahb_to_axi4.scala 119:66] - buf_rdata <= _T_131 @[ahb_to_axi4.scala 119:31] - reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 120:60] - _T_132 <= buf_read_error_in @[ahb_to_axi4.scala 120:60] - buf_read_error <= _T_132 @[ahb_to_axi4.scala 120:31] - reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 123:60] - _T_133 <= io.ahb.sig.in.hresp @[ahb_to_axi4.scala 123:60] - ahb_hresp_q <= _T_133 @[ahb_to_axi4.scala 123:31] - reg _T_134 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 124:60] - _T_134 <= ahb_hready @[ahb_to_axi4.scala 124:60] - ahb_hready_q <= _T_134 @[ahb_to_axi4.scala 124:31] - reg _T_135 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 125:60] - _T_135 <= ahb_htrans_in @[ahb_to_axi4.scala 125:60] - ahb_htrans_q <= _T_135 @[ahb_to_axi4.scala 125:31] - reg _T_136 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 126:65] - _T_136 <= io.ahb.sig.out.hsize @[ahb_to_axi4.scala 126:65] - ahb_hsize_q <= _T_136 @[ahb_to_axi4.scala 126:31] - reg _T_137 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 127:65] - _T_137 <= io.ahb.sig.out.hwrite @[ahb_to_axi4.scala 127:65] - ahb_hwrite_q <= _T_137 @[ahb_to_axi4.scala 127:31] - reg _T_138 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 128:65] - _T_138 <= io.ahb.sig.out.haddr @[ahb_to_axi4.scala 128:65] - ahb_haddr_q <= _T_138 @[ahb_to_axi4.scala 128:31] - node _T_139 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 131:85] - node _T_140 = and(ahb_hready, _T_139) @[ahb_to_axi4.scala 131:62] - node _T_141 = and(io.bus_clk_en, _T_140) @[ahb_to_axi4.scala 131:48] - ahb_bus_addr_clk_en <= _T_141 @[ahb_to_axi4.scala 131:31] - node _T_142 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 132:48] - buf_rdata_clk_en <= _T_142 @[ahb_to_axi4.scala 132:31] + node _T_90 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 106:77] + node _T_91 = and(_T_89, _T_90) @[ahb_to_axi4.scala 106:54] + ahb_htrans_in <= _T_91 @[ahb_to_axi4.scala 106:31] + node _T_92 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 107:50] + io.ahb.sig.in.hrdata <= _T_92 @[ahb_to_axi4.scala 107:38] + node _T_93 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 108:55] + node _T_94 = neq(_T_93, UInt<1>("h00")) @[ahb_to_axi4.scala 108:61] + node _T_95 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 108:83] + node _T_96 = and(_T_94, _T_95) @[ahb_to_axi4.scala 108:70] + node _T_97 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 109:26] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[ahb_to_axi4.scala 109:7] + node _T_99 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 110:46] + node _T_100 = or(ahb_addr_in_iccm, _T_99) @[ahb_to_axi4.scala 110:26] + node _T_101 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 110:80] + node _T_102 = eq(_T_101, UInt<2>("h02")) @[ahb_to_axi4.scala 110:86] + node _T_103 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 110:109] + node _T_104 = eq(_T_103, UInt<2>("h03")) @[ahb_to_axi4.scala 110:115] + node _T_105 = or(_T_102, _T_104) @[ahb_to_axi4.scala 110:95] + node _T_106 = eq(_T_105, UInt<1>("h00")) @[ahb_to_axi4.scala 110:66] + node _T_107 = and(_T_100, _T_106) @[ahb_to_axi4.scala 110:64] + node _T_108 = or(_T_98, _T_107) @[ahb_to_axi4.scala 109:47] + node _T_109 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 111:20] + node _T_110 = eq(_T_109, UInt<1>("h01")) @[ahb_to_axi4.scala 111:26] + node _T_111 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 111:48] + node _T_112 = and(_T_110, _T_111) @[ahb_to_axi4.scala 111:35] + node _T_113 = or(_T_108, _T_112) @[ahb_to_axi4.scala 110:126] + node _T_114 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 112:20] + node _T_115 = eq(_T_114, UInt<2>("h02")) @[ahb_to_axi4.scala 112:26] + node _T_116 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 112:49] + node _T_117 = orr(_T_116) @[ahb_to_axi4.scala 112:56] + node _T_118 = and(_T_115, _T_117) @[ahb_to_axi4.scala 112:35] + node _T_119 = or(_T_113, _T_118) @[ahb_to_axi4.scala 111:55] + node _T_120 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 113:20] + node _T_121 = eq(_T_120, UInt<2>("h03")) @[ahb_to_axi4.scala 113:26] + node _T_122 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 113:49] + node _T_123 = orr(_T_122) @[ahb_to_axi4.scala 113:56] + node _T_124 = and(_T_121, _T_123) @[ahb_to_axi4.scala 113:35] + node _T_125 = or(_T_119, _T_124) @[ahb_to_axi4.scala 112:61] + node _T_126 = and(_T_96, _T_125) @[ahb_to_axi4.scala 108:94] + node _T_127 = or(_T_126, buf_read_error) @[ahb_to_axi4.scala 113:63] + node _T_128 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 115:20] + node _T_129 = and(ahb_hresp_q, _T_128) @[ahb_to_axi4.scala 115:18] + node _T_130 = or(_T_127, _T_129) @[ahb_to_axi4.scala 114:20] + io.ahb.sig.in.hresp <= _T_130 @[ahb_to_axi4.scala 108:38] + reg _T_131 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 118:66] + _T_131 <= io.axi.r.bits.data @[ahb_to_axi4.scala 118:66] + buf_rdata <= _T_131 @[ahb_to_axi4.scala 118:31] + reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 119:60] + _T_132 <= buf_read_error_in @[ahb_to_axi4.scala 119:60] + buf_read_error <= _T_132 @[ahb_to_axi4.scala 119:31] + reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 122:60] + _T_133 <= io.ahb.sig.in.hresp @[ahb_to_axi4.scala 122:60] + ahb_hresp_q <= _T_133 @[ahb_to_axi4.scala 122:31] + reg _T_134 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 123:60] + _T_134 <= ahb_hready @[ahb_to_axi4.scala 123:60] + ahb_hready_q <= _T_134 @[ahb_to_axi4.scala 123:31] + reg _T_135 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 124:60] + _T_135 <= ahb_htrans_in @[ahb_to_axi4.scala 124:60] + ahb_htrans_q <= _T_135 @[ahb_to_axi4.scala 124:31] + reg _T_136 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 125:65] + _T_136 <= io.ahb.sig.out.hsize @[ahb_to_axi4.scala 125:65] + ahb_hsize_q <= _T_136 @[ahb_to_axi4.scala 125:31] + reg _T_137 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 126:65] + _T_137 <= io.ahb.sig.out.hwrite @[ahb_to_axi4.scala 126:65] + ahb_hwrite_q <= _T_137 @[ahb_to_axi4.scala 126:31] + reg _T_138 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 127:65] + _T_138 <= io.ahb.sig.out.haddr @[ahb_to_axi4.scala 127:65] + ahb_haddr_q <= _T_138 @[ahb_to_axi4.scala 127:31] + node _T_139 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 130:85] + node _T_140 = and(ahb_hready, _T_139) @[ahb_to_axi4.scala 130:62] + node _T_141 = and(io.bus_clk_en, _T_140) @[ahb_to_axi4.scala 130:48] + ahb_bus_addr_clk_en <= _T_141 @[ahb_to_axi4.scala 130:31] + node _T_142 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 131:48] + buf_rdata_clk_en <= _T_142 @[ahb_to_axi4.scala 131:31] inst rvclkhdr of rvclkhdr @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 344:17] rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 134:31] + ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 133:31] inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] rvclkhdr_1.io.en <= ahb_bus_addr_clk_en @[lib.scala 345:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 135:31] + ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 134:31] inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 343:22] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] rvclkhdr_2.io.en <= buf_rdata_clk_en @[lib.scala 345:16] rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 136:31] - node _T_143 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 138:53] - node _T_144 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 138:91] - node _T_145 = or(_T_143, _T_144) @[ahb_to_axi4.scala 138:72] - node _T_146 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 138:113] - node _T_147 = and(_T_145, _T_146) @[ahb_to_axi4.scala 138:111] - node _T_148 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 138:153] - node _T_149 = and(io.ahb.sig.in.hresp, _T_148) @[ahb_to_axi4.scala 138:151] - node _T_150 = or(_T_147, _T_149) @[ahb_to_axi4.scala 138:128] - cmdbuf_rst <= _T_150 @[ahb_to_axi4.scala 138:31] - node _T_151 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 139:67] - node _T_152 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 139:105] - node _T_153 = or(_T_151, _T_152) @[ahb_to_axi4.scala 139:86] - node _T_154 = eq(_T_153, UInt<1>("h00")) @[ahb_to_axi4.scala 139:48] - node _T_155 = and(cmdbuf_vld, _T_154) @[ahb_to_axi4.scala 139:46] - cmdbuf_full <= _T_155 @[ahb_to_axi4.scala 139:31] - node _T_156 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 141:86] - node _T_157 = mux(_T_156, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 141:66] - node _T_158 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 141:110] - node _T_159 = and(_T_157, _T_158) @[ahb_to_axi4.scala 141:108] - reg _T_160 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 141:61] - _T_160 <= _T_159 @[ahb_to_axi4.scala 141:61] - cmdbuf_vld <= _T_160 @[ahb_to_axi4.scala 141:31] - node _T_161 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 145:53] + buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 135:31] + node _T_143 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 137:53] + node _T_144 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 137:91] + node _T_145 = or(_T_143, _T_144) @[ahb_to_axi4.scala 137:72] + node _T_146 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 137:113] + node _T_147 = and(_T_145, _T_146) @[ahb_to_axi4.scala 137:111] + node _T_148 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 137:153] + node _T_149 = and(io.ahb.sig.in.hresp, _T_148) @[ahb_to_axi4.scala 137:151] + node _T_150 = or(_T_147, _T_149) @[ahb_to_axi4.scala 137:128] + cmdbuf_rst <= _T_150 @[ahb_to_axi4.scala 137:31] + node _T_151 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 138:67] + node _T_152 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 138:105] + node _T_153 = or(_T_151, _T_152) @[ahb_to_axi4.scala 138:86] + node _T_154 = eq(_T_153, UInt<1>("h00")) @[ahb_to_axi4.scala 138:48] + node _T_155 = and(cmdbuf_vld, _T_154) @[ahb_to_axi4.scala 138:46] + cmdbuf_full <= _T_155 @[ahb_to_axi4.scala 138:31] + node _T_156 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 140:86] + node _T_157 = mux(_T_156, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 140:66] + node _T_158 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 140:110] + node _T_159 = and(_T_157, _T_158) @[ahb_to_axi4.scala 140:108] + reg _T_160 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 140:61] + _T_160 <= _T_159 @[ahb_to_axi4.scala 140:61] + cmdbuf_vld <= _T_160 @[ahb_to_axi4.scala 140:31] + node _T_161 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 144:53] reg _T_162 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_161 : @[Reg.scala 28:19] _T_162 <= ahb_hwrite_q @[Reg.scala 28:23] skip @[Reg.scala 28:19] - cmdbuf_write <= _T_162 @[ahb_to_axi4.scala 144:31] - node _T_163 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 148:52] + cmdbuf_write <= _T_162 @[ahb_to_axi4.scala 143:31] + node _T_163 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 147:52] reg _T_164 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_163 : @[Reg.scala 28:19] _T_164 <= ahb_hsize_q @[Reg.scala 28:23] skip @[Reg.scala 28:19] - cmdbuf_size <= _T_164 @[ahb_to_axi4.scala 147:31] - node _T_165 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 151:53] + cmdbuf_size <= _T_164 @[ahb_to_axi4.scala 146:31] + node _T_165 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 150:53] reg _T_166 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_165 : @[Reg.scala 28:19] _T_166 <= master_wstrb @[Reg.scala 28:23] skip @[Reg.scala 28:19] - cmdbuf_wstrb <= _T_166 @[ahb_to_axi4.scala 150:31] - node _T_167 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 154:57] + cmdbuf_wstrb <= _T_166 @[ahb_to_axi4.scala 149:31] + node _T_167 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 153:57] inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -562,8 +562,8 @@ circuit ahb_to_axi4 : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_168 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_168 <= ahb_haddr_q @[lib.scala 374:16] - cmdbuf_addr <= _T_168 @[ahb_to_axi4.scala 154:15] - node _T_169 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 155:68] + cmdbuf_addr <= _T_168 @[ahb_to_axi4.scala 153:15] + node _T_169 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 154:68] inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -572,44 +572,44 @@ circuit ahb_to_axi4 : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_170 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_170 <= io.ahb.sig.out.hwdata @[lib.scala 374:16] - cmdbuf_wdata <= _T_170 @[ahb_to_axi4.scala 155:16] - node _T_171 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 158:42] - io.axi.aw.valid <= _T_171 @[ahb_to_axi4.scala 158:28] - io.axi.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 159:33] - io.axi.aw.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 160:33] - node _T_172 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 161:59] + cmdbuf_wdata <= _T_170 @[ahb_to_axi4.scala 154:16] + node _T_171 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 157:42] + io.axi.aw.valid <= _T_171 @[ahb_to_axi4.scala 157:28] + io.axi.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 158:33] + io.axi.aw.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 159:33] + node _T_172 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 160:59] node _T_173 = cat(UInt<1>("h00"), _T_172) @[Cat.scala 29:58] - io.axi.aw.bits.size <= _T_173 @[ahb_to_axi4.scala 161:33] + io.axi.aw.bits.size <= _T_173 @[ahb_to_axi4.scala 160:33] node _T_174 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - io.axi.aw.bits.prot <= _T_174 @[ahb_to_axi4.scala 162:33] + io.axi.aw.bits.prot <= _T_174 @[ahb_to_axi4.scala 161:33] node _T_175 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - io.axi.aw.bits.len <= _T_175 @[ahb_to_axi4.scala 163:33] - io.axi.aw.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 164:33] - node _T_176 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 166:42] - io.axi.w.valid <= _T_176 @[ahb_to_axi4.scala 166:28] - io.axi.w.bits.data <= cmdbuf_wdata @[ahb_to_axi4.scala 167:33] - io.axi.w.bits.strb <= cmdbuf_wstrb @[ahb_to_axi4.scala 168:33] - io.axi.w.bits.last <= UInt<1>("h01") @[ahb_to_axi4.scala 169:33] - io.axi.b.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 171:28] - node _T_177 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 173:44] - node _T_178 = and(cmdbuf_vld, _T_177) @[ahb_to_axi4.scala 173:42] - io.axi.ar.valid <= _T_178 @[ahb_to_axi4.scala 173:28] - io.axi.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 174:33] - io.axi.ar.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 175:33] - node _T_179 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 176:59] + io.axi.aw.bits.len <= _T_175 @[ahb_to_axi4.scala 162:33] + io.axi.aw.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 163:33] + node _T_176 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 165:42] + io.axi.w.valid <= _T_176 @[ahb_to_axi4.scala 165:28] + io.axi.w.bits.data <= cmdbuf_wdata @[ahb_to_axi4.scala 166:33] + io.axi.w.bits.strb <= cmdbuf_wstrb @[ahb_to_axi4.scala 167:33] + io.axi.w.bits.last <= UInt<1>("h01") @[ahb_to_axi4.scala 168:33] + io.axi.b.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 170:28] + node _T_177 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 172:44] + node _T_178 = and(cmdbuf_vld, _T_177) @[ahb_to_axi4.scala 172:42] + io.axi.ar.valid <= _T_178 @[ahb_to_axi4.scala 172:28] + io.axi.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 173:33] + io.axi.ar.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 174:33] + node _T_179 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 175:59] node _T_180 = cat(UInt<1>("h00"), _T_179) @[Cat.scala 29:58] - io.axi.ar.bits.size <= _T_180 @[ahb_to_axi4.scala 176:33] + io.axi.ar.bits.size <= _T_180 @[ahb_to_axi4.scala 175:33] node _T_181 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - io.axi.ar.bits.prot <= _T_181 @[ahb_to_axi4.scala 177:33] + io.axi.ar.bits.prot <= _T_181 @[ahb_to_axi4.scala 176:33] node _T_182 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - io.axi.ar.bits.len <= _T_182 @[ahb_to_axi4.scala 178:33] - io.axi.ar.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 179:33] - io.axi.r.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 181:28] + io.axi.ar.bits.len <= _T_182 @[ahb_to_axi4.scala 177:33] + io.axi.ar.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 178:33] + io.axi.r.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 180:28] inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 343:22] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset rvclkhdr_5.io.clk <= clock @[lib.scala 344:17] rvclkhdr_5.io.en <= io.bus_clk_en @[lib.scala 345:16] rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 182:27] + bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 181:27] diff --git a/ahb_to_axi4.v b/ahb_to_axi4.v new file mode 100644 index 00000000..b65746cd --- /dev/null +++ b/ahb_to_axi4.v @@ -0,0 +1,584 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[lib.scala 334:26] + wire clkhdr_CK; // @[lib.scala 334:26] + wire clkhdr_EN; // @[lib.scala 334:26] + wire clkhdr_SE; // @[lib.scala 334:26] + gated_latch clkhdr ( // @[lib.scala 334:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14] + assign clkhdr_CK = io_clk; // @[lib.scala 336:18] + assign clkhdr_EN = io_en; // @[lib.scala 337:18] + assign clkhdr_SE = io_scan_mode; // @[lib.scala 338:18] +endmodule +module ahb_to_axi4( + input clock, + input reset, + input io_scan_mode, + input io_bus_clk_en, + input io_clk_override, + input io_axi_aw_ready, + output io_axi_aw_valid, + output io_axi_aw_bits_id, + output [31:0] io_axi_aw_bits_addr, + output [3:0] io_axi_aw_bits_region, + output [7:0] io_axi_aw_bits_len, + output [2:0] io_axi_aw_bits_size, + output [1:0] io_axi_aw_bits_burst, + output io_axi_aw_bits_lock, + output [3:0] io_axi_aw_bits_cache, + output [2:0] io_axi_aw_bits_prot, + output [3:0] io_axi_aw_bits_qos, + input io_axi_w_ready, + output io_axi_w_valid, + output [63:0] io_axi_w_bits_data, + output [7:0] io_axi_w_bits_strb, + output io_axi_w_bits_last, + output io_axi_b_ready, + input io_axi_b_valid, + input [1:0] io_axi_b_bits_resp, + input io_axi_b_bits_id, + input io_axi_ar_ready, + output io_axi_ar_valid, + output io_axi_ar_bits_id, + output [31:0] io_axi_ar_bits_addr, + output [3:0] io_axi_ar_bits_region, + output [7:0] io_axi_ar_bits_len, + output [2:0] io_axi_ar_bits_size, + output [1:0] io_axi_ar_bits_burst, + output io_axi_ar_bits_lock, + output [3:0] io_axi_ar_bits_cache, + output [2:0] io_axi_ar_bits_prot, + output [3:0] io_axi_ar_bits_qos, + output io_axi_r_ready, + input io_axi_r_valid, + input io_axi_r_bits_id, + input [63:0] io_axi_r_bits_data, + input [1:0] io_axi_r_bits_resp, + input io_axi_r_bits_last, + output [63:0] io_ahb_sig_in_hrdata, + output io_ahb_sig_in_hready, + output io_ahb_sig_in_hresp, + input [31:0] io_ahb_sig_out_haddr, + input [2:0] io_ahb_sig_out_hburst, + input io_ahb_sig_out_hmastlock, + input [3:0] io_ahb_sig_out_hprot, + input [2:0] io_ahb_sig_out_hsize, + input [1:0] io_ahb_sig_out_htrans, + input io_ahb_sig_out_hwrite, + input [63:0] io_ahb_sig_out_hwdata, + input io_ahb_hsel, + input io_ahb_hreadyin +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [63:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [63:0] _RAND_14; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_2_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_2_io_en; // @[lib.scala 343:22] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_5_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_5_io_en; // @[lib.scala 343:22] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 343:22] + wire ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 45:33 ahb_to_axi4.scala 134:31] + reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 127:65] + wire ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[lib.scala 87:29] + wire ahb_addr_in_iccm = ahb_haddr_q[31:16] == 16'hee00; // @[lib.scala 87:29] + wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 44:33 ahb_to_axi4.scala 133:31] + reg [1:0] buf_state; // @[Reg.scala 27:20] + wire _T_7 = 2'h0 == buf_state; // @[Conditional.scala 37:30] + wire ahb_hready = io_ahb_sig_in_hready & io_ahb_hreadyin; // @[ahb_to_axi4.scala 105:55] + wire _T_10 = ahb_hready & io_ahb_sig_out_htrans[1]; // @[ahb_to_axi4.scala 77:34] + wire _T_11 = _T_10 & io_ahb_hsel; // @[ahb_to_axi4.scala 77:61] + wire _T_12 = 2'h1 == buf_state; // @[Conditional.scala 37:30] + wire _T_14 = io_ahb_sig_out_htrans == 2'h0; // @[ahb_to_axi4.scala 80:79] + wire _T_15 = io_ahb_sig_in_hresp | _T_14; // @[ahb_to_axi4.scala 80:48] + wire _T_16 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 80:93] + wire _T_17 = _T_15 | _T_16; // @[ahb_to_axi4.scala 80:91] + wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 58:33 ahb_to_axi4.scala 181:27] + reg cmdbuf_vld; // @[ahb_to_axi4.scala 140:61] + wire _T_151 = io_axi_aw_valid & io_axi_aw_ready; // @[ahb_to_axi4.scala 138:67] + wire _T_152 = io_axi_ar_valid & io_axi_ar_ready; // @[ahb_to_axi4.scala 138:105] + wire _T_153 = _T_151 | _T_152; // @[ahb_to_axi4.scala 138:86] + wire _T_154 = ~_T_153; // @[ahb_to_axi4.scala 138:48] + wire cmdbuf_full = cmdbuf_vld & _T_154; // @[ahb_to_axi4.scala 138:46] + wire _T_21 = ~cmdbuf_full; // @[ahb_to_axi4.scala 81:24] + wire _T_22 = _T_21 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 81:37] + wire _T_25 = io_ahb_sig_out_htrans == 2'h1; // @[ahb_to_axi4.scala 82:92] + wire _T_26 = _T_25 & io_ahb_hsel; // @[ahb_to_axi4.scala 82:110] + wire _T_27 = io_ahb_sig_in_hresp | _T_26; // @[ahb_to_axi4.scala 82:60] + wire _T_28 = ~_T_27; // @[ahb_to_axi4.scala 82:38] + wire _T_29 = _T_21 & _T_28; // @[ahb_to_axi4.scala 82:36] + wire _T_30 = 2'h2 == buf_state; // @[Conditional.scala 37:30] + wire _T_34 = ~io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 87:23] + wire _T_36 = _T_34 & _T_21; // @[ahb_to_axi4.scala 87:44] + wire _T_37 = 2'h3 == buf_state; // @[Conditional.scala 37:30] + reg cmdbuf_write; // @[Reg.scala 27:20] + wire _T_38 = ~cmdbuf_write; // @[ahb_to_axi4.scala 91:40] + wire _T_39 = io_axi_r_valid & _T_38; // @[ahb_to_axi4.scala 91:38] + wire _T_41 = |io_axi_r_bits_resp; // @[ahb_to_axi4.scala 93:68] + wire _GEN_1 = _T_37 & _T_39; // @[Conditional.scala 39:67] + wire _GEN_5 = _T_30 ? _T_22 : _GEN_1; // @[Conditional.scala 39:67] + wire _GEN_10 = _T_12 ? _T_22 : _GEN_5; // @[Conditional.scala 39:67] + wire buf_state_en = _T_7 ? _T_11 : _GEN_10; // @[Conditional.scala 40:58] + wire _T_42 = buf_state_en & _T_41; // @[ahb_to_axi4.scala 93:41] + wire _GEN_2 = _T_37 & buf_state_en; // @[Conditional.scala 39:67] + wire _GEN_3 = _T_37 & _T_42; // @[Conditional.scala 39:67] + wire _GEN_6 = _T_30 & _T_36; // @[Conditional.scala 39:67] + wire _GEN_7 = _T_30 ? 1'h0 : _GEN_2; // @[Conditional.scala 39:67] + wire _GEN_11 = _T_12 ? _T_29 : _GEN_6; // @[Conditional.scala 39:67] + wire _GEN_12 = _T_12 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] + wire cmdbuf_wr_en = _T_7 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58] + wire buf_rdata_en = _T_7 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58] + reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 125:65] + wire _T_46 = ahb_hsize_q == 3'h0; // @[ahb_to_axi4.scala 98:60] + wire [7:0] _T_48 = _T_46 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_50 = 8'h1 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 98:78] + wire [7:0] _T_51 = _T_48 & _T_50; // @[ahb_to_axi4.scala 98:70] + wire _T_53 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 99:30] + wire [7:0] _T_55 = _T_53 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [8:0] _T_57 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 99:48] + wire [8:0] _GEN_23 = {{1'd0}, _T_55}; // @[ahb_to_axi4.scala 99:40] + wire [8:0] _T_58 = _GEN_23 & _T_57; // @[ahb_to_axi4.scala 99:40] + wire [8:0] _GEN_24 = {{1'd0}, _T_51}; // @[ahb_to_axi4.scala 98:109] + wire [8:0] _T_59 = _GEN_24 | _T_58; // @[ahb_to_axi4.scala 98:109] + wire _T_61 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 100:30] + wire [7:0] _T_63 = _T_61 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [10:0] _T_65 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 100:48] + wire [10:0] _GEN_25 = {{3'd0}, _T_63}; // @[ahb_to_axi4.scala 100:40] + wire [10:0] _T_66 = _GEN_25 & _T_65; // @[ahb_to_axi4.scala 100:40] + wire [10:0] _GEN_26 = {{2'd0}, _T_59}; // @[ahb_to_axi4.scala 99:79] + wire [10:0] _T_67 = _GEN_26 | _T_66; // @[ahb_to_axi4.scala 99:79] + wire _T_69 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 101:30] + wire [7:0] _T_71 = _T_69 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [10:0] _GEN_27 = {{3'd0}, _T_71}; // @[ahb_to_axi4.scala 100:79] + wire [10:0] _T_73 = _T_67 | _GEN_27; // @[ahb_to_axi4.scala 100:79] + reg ahb_hready_q; // @[ahb_to_axi4.scala 123:60] + wire _T_74 = ~ahb_hready_q; // @[ahb_to_axi4.scala 104:80] + reg ahb_hresp_q; // @[ahb_to_axi4.scala 122:60] + wire _T_75 = ahb_hresp_q & _T_74; // @[ahb_to_axi4.scala 104:78] + wire _T_77 = buf_state == 2'h0; // @[ahb_to_axi4.scala 104:124] + wire _T_78 = _T_21 | _T_77; // @[ahb_to_axi4.scala 104:111] + wire _T_79 = buf_state == 2'h2; // @[ahb_to_axi4.scala 104:149] + wire _T_80 = buf_state == 2'h3; // @[ahb_to_axi4.scala 104:168] + wire _T_81 = _T_79 | _T_80; // @[ahb_to_axi4.scala 104:156] + wire _T_82 = ~_T_81; // @[ahb_to_axi4.scala 104:137] + wire _T_83 = _T_78 & _T_82; // @[ahb_to_axi4.scala 104:135] + reg buf_read_error; // @[ahb_to_axi4.scala 119:60] + wire _T_84 = ~buf_read_error; // @[ahb_to_axi4.scala 104:181] + wire _T_85 = _T_83 & _T_84; // @[ahb_to_axi4.scala 104:179] + wire [1:0] _T_89 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire buf_rdata_clk = rvclkhdr_2_io_l1clk; // @[ahb_to_axi4.scala 46:33 ahb_to_axi4.scala 135:31] + reg [63:0] buf_rdata; // @[ahb_to_axi4.scala 118:66] + reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 124:60] + wire _T_94 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 108:61] + wire _T_95 = buf_state != 2'h0; // @[ahb_to_axi4.scala 108:83] + wire _T_96 = _T_94 & _T_95; // @[ahb_to_axi4.scala 108:70] + wire _T_97 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 109:26] + wire _T_98 = ~_T_97; // @[ahb_to_axi4.scala 109:7] + reg ahb_hwrite_q; // @[ahb_to_axi4.scala 126:65] + wire _T_99 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 110:46] + wire _T_100 = ahb_addr_in_iccm | _T_99; // @[ahb_to_axi4.scala 110:26] + wire _T_102 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 110:86] + wire _T_104 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 110:115] + wire _T_105 = _T_102 | _T_104; // @[ahb_to_axi4.scala 110:95] + wire _T_106 = ~_T_105; // @[ahb_to_axi4.scala 110:66] + wire _T_107 = _T_100 & _T_106; // @[ahb_to_axi4.scala 110:64] + wire _T_108 = _T_98 | _T_107; // @[ahb_to_axi4.scala 109:47] + wire _T_112 = _T_53 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 111:35] + wire _T_113 = _T_108 | _T_112; // @[ahb_to_axi4.scala 110:126] + wire _T_117 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 112:56] + wire _T_118 = _T_61 & _T_117; // @[ahb_to_axi4.scala 112:35] + wire _T_119 = _T_113 | _T_118; // @[ahb_to_axi4.scala 111:55] + wire _T_123 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 113:56] + wire _T_124 = _T_69 & _T_123; // @[ahb_to_axi4.scala 113:35] + wire _T_125 = _T_119 | _T_124; // @[ahb_to_axi4.scala 112:61] + wire _T_126 = _T_96 & _T_125; // @[ahb_to_axi4.scala 108:94] + wire _T_127 = _T_126 | buf_read_error; // @[ahb_to_axi4.scala 113:63] + wire _T_146 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 137:113] + wire _T_147 = _T_153 & _T_146; // @[ahb_to_axi4.scala 137:111] + wire _T_149 = io_ahb_sig_in_hresp & _T_38; // @[ahb_to_axi4.scala 137:151] + wire cmdbuf_rst = _T_147 | _T_149; // @[ahb_to_axi4.scala 137:128] + wire _T_157 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 140:66] + wire _T_158 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 140:110] + reg [2:0] _T_164; // @[Reg.scala 27:20] + reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20] + wire [7:0] master_wstrb = _T_73[7:0]; // @[ahb_to_axi4.scala 98:31] + reg [31:0] cmdbuf_addr; // @[lib.scala 374:16] + reg [63:0] cmdbuf_wdata; // @[lib.scala 374:16] + wire [1:0] cmdbuf_size = _T_164[1:0]; // @[ahb_to_axi4.scala 146:31] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + assign io_axi_aw_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 157:28] + assign io_axi_aw_bits_id = 1'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 158:33] + assign io_axi_aw_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 159:33] + assign io_axi_aw_bits_region = 4'h0; // @[ahb_to_axi4.scala 20:10] + assign io_axi_aw_bits_len = 8'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 162:33] + assign io_axi_aw_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 160:33] + assign io_axi_aw_bits_burst = 2'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 163:33] + assign io_axi_aw_bits_lock = 1'h0; // @[ahb_to_axi4.scala 20:10] + assign io_axi_aw_bits_cache = 4'h0; // @[ahb_to_axi4.scala 20:10] + assign io_axi_aw_bits_prot = 3'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 161:33] + assign io_axi_aw_bits_qos = 4'h0; // @[ahb_to_axi4.scala 20:10] + assign io_axi_w_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 165:28] + assign io_axi_w_bits_data = cmdbuf_wdata; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 166:33] + assign io_axi_w_bits_strb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 167:33] + assign io_axi_w_bits_last = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 168:33] + assign io_axi_b_ready = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 170:28] + assign io_axi_ar_valid = cmdbuf_vld & _T_38; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 172:28] + assign io_axi_ar_bits_id = 1'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 173:33] + assign io_axi_ar_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 174:33] + assign io_axi_ar_bits_region = 4'h0; // @[ahb_to_axi4.scala 20:10] + assign io_axi_ar_bits_len = 8'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 177:33] + assign io_axi_ar_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 175:33] + assign io_axi_ar_bits_burst = 2'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 178:33] + assign io_axi_ar_bits_lock = 1'h0; // @[ahb_to_axi4.scala 20:10] + assign io_axi_ar_bits_cache = 4'h0; // @[ahb_to_axi4.scala 20:10] + assign io_axi_ar_bits_prot = 3'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 176:33] + assign io_axi_ar_bits_qos = 4'h0; // @[ahb_to_axi4.scala 20:10] + assign io_axi_r_ready = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 180:28] + assign io_ahb_sig_in_hrdata = buf_rdata; // @[ahb_to_axi4.scala 107:38] + assign io_ahb_sig_in_hready = io_ahb_sig_in_hresp ? _T_75 : _T_85; // @[ahb_to_axi4.scala 104:38] + assign io_ahb_sig_in_hresp = _T_127 | _T_75; // @[ahb_to_axi4.scala 108:38] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = io_bus_clk_en & _T_10; // @[lib.scala 345:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_2_io_en = io_bus_clk_en & buf_rdata_en; // @[lib.scala 345:16] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_3_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = _T_7 ? 1'h0 : _GEN_11; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = _T_7 ? 1'h0 : _GEN_11; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_5_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + ahb_haddr_q = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + buf_state = _RAND_1[1:0]; + _RAND_2 = {1{`RANDOM}}; + cmdbuf_vld = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + cmdbuf_write = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + ahb_hsize_q = _RAND_4[2:0]; + _RAND_5 = {1{`RANDOM}}; + ahb_hready_q = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + ahb_hresp_q = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + buf_read_error = _RAND_7[0:0]; + _RAND_8 = {2{`RANDOM}}; + buf_rdata = _RAND_8[63:0]; + _RAND_9 = {1{`RANDOM}}; + ahb_htrans_q = _RAND_9[1:0]; + _RAND_10 = {1{`RANDOM}}; + ahb_hwrite_q = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + _T_164 = _RAND_11[2:0]; + _RAND_12 = {1{`RANDOM}}; + cmdbuf_wstrb = _RAND_12[7:0]; + _RAND_13 = {1{`RANDOM}}; + cmdbuf_addr = _RAND_13[31:0]; + _RAND_14 = {2{`RANDOM}}; + cmdbuf_wdata = _RAND_14[63:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + ahb_haddr_q = 32'h0; + end + if (reset) begin + buf_state = 2'h0; + end + if (reset) begin + cmdbuf_vld = 1'h0; + end + if (reset) begin + cmdbuf_write = 1'h0; + end + if (reset) begin + ahb_hsize_q = 3'h0; + end + if (reset) begin + ahb_hready_q = 1'h0; + end + if (reset) begin + ahb_hresp_q = 1'h0; + end + if (reset) begin + buf_read_error = 1'h0; + end + if (reset) begin + buf_rdata = 64'h0; + end + if (reset) begin + ahb_htrans_q = 2'h0; + end + if (reset) begin + ahb_hwrite_q = 1'h0; + end + if (reset) begin + _T_164 = 3'h0; + end + if (reset) begin + cmdbuf_wstrb = 8'h0; + end + if (reset) begin + cmdbuf_addr = 32'h0; + end + if (reset) begin + cmdbuf_wdata = 64'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge ahb_addr_clk or posedge reset) begin + if (reset) begin + ahb_haddr_q <= 32'h0; + end else begin + ahb_haddr_q <= io_ahb_sig_out_haddr; + end + end + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + buf_state <= 2'h0; + end else if (buf_state_en) begin + if (_T_7) begin + if (io_ahb_sig_out_hwrite) begin + buf_state <= 2'h1; + end else begin + buf_state <= 2'h2; + end + end else if (_T_12) begin + if (_T_17) begin + buf_state <= 2'h0; + end else if (io_ahb_sig_out_hwrite) begin + buf_state <= 2'h1; + end else begin + buf_state <= 2'h2; + end + end else if (_T_30) begin + if (io_ahb_sig_in_hresp) begin + buf_state <= 2'h0; + end else begin + buf_state <= 2'h3; + end + end else begin + buf_state <= 2'h0; + end + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + cmdbuf_vld <= 1'h0; + end else begin + cmdbuf_vld <= _T_157 & _T_158; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + cmdbuf_write <= 1'h0; + end else if (cmdbuf_wr_en) begin + cmdbuf_write <= ahb_hwrite_q; + end + end + always @(posedge ahb_addr_clk or posedge reset) begin + if (reset) begin + ahb_hsize_q <= 3'h0; + end else begin + ahb_hsize_q <= io_ahb_sig_out_hsize; + end + end + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + ahb_hready_q <= 1'h0; + end else begin + ahb_hready_q <= io_ahb_sig_in_hready & io_ahb_hreadyin; + end + end + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + ahb_hresp_q <= 1'h0; + end else begin + ahb_hresp_q <= io_ahb_sig_in_hresp; + end + end + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + buf_read_error <= 1'h0; + end else if (_T_7) begin + buf_read_error <= 1'h0; + end else if (_T_12) begin + buf_read_error <= 1'h0; + end else if (_T_30) begin + buf_read_error <= 1'h0; + end else begin + buf_read_error <= _GEN_3; + end + end + always @(posedge buf_rdata_clk or posedge reset) begin + if (reset) begin + buf_rdata <= 64'h0; + end else begin + buf_rdata <= io_axi_r_bits_data; + end + end + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + ahb_htrans_q <= 2'h0; + end else begin + ahb_htrans_q <= _T_89 & io_ahb_sig_out_htrans; + end + end + always @(posedge ahb_addr_clk or posedge reset) begin + if (reset) begin + ahb_hwrite_q <= 1'h0; + end else begin + ahb_hwrite_q <= io_ahb_sig_out_hwrite; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + _T_164 <= 3'h0; + end else if (cmdbuf_wr_en) begin + _T_164 <= ahb_hsize_q; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + cmdbuf_wstrb <= 8'h0; + end else if (cmdbuf_wr_en) begin + cmdbuf_wstrb <= master_wstrb; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + cmdbuf_addr <= 32'h0; + end else begin + cmdbuf_addr <= ahb_haddr_q; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + cmdbuf_wdata <= 64'h0; + end else begin + cmdbuf_wdata <= io_ahb_sig_out_hwdata; + end + end +endmodule diff --git a/axi4_to_ahb.anno.json b/axi4_to_ahb.anno.json new file mode 100644 index 00000000..d41890d1 --- /dev/null +++ b/axi4_to_ahb.anno.json @@ -0,0 +1,113 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_w_ready", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hprot", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_prot" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_aw_ready", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_haddr", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_addr", + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_b_valid", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hsize", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_size", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hwrite", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_htrans", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_r_valid", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_ready", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"axi4_to_ahb.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"axi4_to_ahb" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/axi4_to_ahb.fir b/axi4_to_ahb.fir new file mode 100644 index 00000000..6f56dc26 --- /dev/null +++ b/axi4_to_ahb.fir @@ -0,0 +1,1406 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit axi4_to_ahb : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module axi4_to_ahb : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} + + wire buf_rst : UInt<1> + buf_rst <= UInt<1>("h00") + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 28:11] + io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 29:21] + wire buf_state_en : UInt<1> + buf_state_en <= UInt<1>("h00") + wire ahbm_clk : Clock @[axi4_to_ahb.scala 31:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 32:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 33:27] + wire buf_state : UInt<3> + buf_state <= UInt<3>("h00") + wire buf_nxtstate : UInt<3> + buf_nxtstate <= UInt<3>("h00") + node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 37:70] + node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 37:50] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 37:108] + node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] + node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 37:98] + reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 37:45] + _T_6 <= _T_5 @[axi4_to_ahb.scala 37:45] + buf_state <= _T_6 @[axi4_to_ahb.scala 37:13] + wire slave_valid : UInt<1> + slave_valid <= UInt<1>("h00") + wire slave_ready : UInt<1> + slave_ready <= UInt<1>("h00") + wire slave_tag : UInt<1> + slave_tag <= UInt<1>("h00") + wire slave_rdata : UInt<64> + slave_rdata <= UInt<64>("h00") + wire slave_opc : UInt<4> + slave_opc <= UInt<4>("h00") + wire wrbuf_en : UInt<1> + wrbuf_en <= UInt<1>("h00") + wire wrbuf_data_en : UInt<1> + wrbuf_data_en <= UInt<1>("h00") + wire wrbuf_cmd_sent : UInt<1> + wrbuf_cmd_sent <= UInt<1>("h00") + wire wrbuf_rst : UInt<1> + wrbuf_rst <= UInt<1>("h00") + wire wrbuf_vld : UInt<1> + wrbuf_vld <= UInt<1>("h00") + wire wrbuf_data_vld : UInt<1> + wrbuf_data_vld <= UInt<1>("h00") + wire wrbuf_tag : UInt<1> + wrbuf_tag <= UInt<1>("h00") + wire wrbuf_size : UInt<3> + wrbuf_size <= UInt<3>("h00") + wire wrbuf_addr : UInt<32> + wrbuf_addr <= UInt<32>("h00") + wire wrbuf_data : UInt<64> + wrbuf_data <= UInt<64>("h00") + wire wrbuf_byteen : UInt<8> + wrbuf_byteen <= UInt<8>("h00") + wire bus_write_clk_en : UInt<1> + bus_write_clk_en <= UInt<1>("h00") + wire bus_clk : Clock @[axi4_to_ahb.scala 57:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 58:27] + wire master_valid : UInt<1> + master_valid <= UInt<1>("h00") + wire master_ready : UInt<1> + master_ready <= UInt<1>("h00") + wire master_tag : UInt<1> + master_tag <= UInt<1>("h00") + wire master_addr : UInt<32> + master_addr <= UInt<32>("h00") + wire master_wdata : UInt<64> + master_wdata <= UInt<64>("h00") + wire master_size : UInt<3> + master_size <= UInt<3>("h00") + wire master_opc : UInt<3> + master_opc <= UInt<3>("h00") + wire master_byteen : UInt<8> + master_byteen <= UInt<8>("h00") + wire buf_addr : UInt<32> + buf_addr <= UInt<32>("h00") + wire buf_size : UInt<2> + buf_size <= UInt<2>("h00") + wire buf_write : UInt<1> + buf_write <= UInt<1>("h00") + wire buf_byteen : UInt<8> + buf_byteen <= UInt<8>("h00") + wire buf_aligned : UInt<1> + buf_aligned <= UInt<1>("h00") + wire buf_data : UInt<64> + buf_data <= UInt<64>("h00") + wire buf_tag : UInt<1> + buf_tag <= UInt<1>("h00") + wire buf_tag_in : UInt<1> + buf_tag_in <= UInt<1>("h00") + wire buf_addr_in : UInt<32> + buf_addr_in <= UInt<32>("h00") + wire buf_byteen_in : UInt<8> + buf_byteen_in <= UInt<8>("h00") + wire buf_data_in : UInt<64> + buf_data_in <= UInt<64>("h00") + wire buf_write_in : UInt<1> + buf_write_in <= UInt<1>("h00") + wire buf_aligned_in : UInt<1> + buf_aligned_in <= UInt<1>("h00") + wire buf_size_in : UInt<3> + buf_size_in <= UInt<3>("h00") + wire buf_wr_en : UInt<1> + buf_wr_en <= UInt<1>("h00") + wire buf_data_wr_en : UInt<1> + buf_data_wr_en <= UInt<1>("h00") + wire slvbuf_error_en : UInt<1> + slvbuf_error_en <= UInt<1>("h00") + wire wr_cmd_vld : UInt<1> + wr_cmd_vld <= UInt<1>("h00") + wire cmd_done_rst : UInt<1> + cmd_done_rst <= UInt<1>("h00") + wire cmd_done : UInt<1> + cmd_done <= UInt<1>("h00") + wire cmd_doneQ : UInt<1> + cmd_doneQ <= UInt<1>("h00") + wire trxn_done : UInt<1> + trxn_done <= UInt<1>("h00") + wire buf_cmd_byte_ptr : UInt<3> + buf_cmd_byte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptrQ : UInt<3> + buf_cmd_byte_ptrQ <= UInt<3>("h00") + wire buf_cmd_nxtbyte_ptr : UInt<3> + buf_cmd_nxtbyte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptr_en : UInt<1> + buf_cmd_byte_ptr_en <= UInt<1>("h00") + wire found : UInt<1> + found <= UInt<1>("h00") + wire slave_valid_pre : UInt<1> + slave_valid_pre <= UInt<1>("h00") + wire ahb_hready_q : UInt<1> + ahb_hready_q <= UInt<1>("h00") + wire ahb_hresp_q : UInt<1> + ahb_hresp_q <= UInt<1>("h00") + wire ahb_htrans_q : UInt<2> + ahb_htrans_q <= UInt<2>("h00") + wire ahb_hwrite_q : UInt<1> + ahb_hwrite_q <= UInt<1>("h00") + wire ahb_hrdata_q : UInt<64> + ahb_hrdata_q <= UInt<64>("h00") + wire slvbuf_write : UInt<1> + slvbuf_write <= UInt<1>("h00") + wire slvbuf_error : UInt<1> + slvbuf_error <= UInt<1>("h00") + wire slvbuf_tag : UInt<1> + slvbuf_tag <= UInt<1>("h00") + wire slvbuf_error_in : UInt<1> + slvbuf_error_in <= UInt<1>("h00") + wire slvbuf_wr_en : UInt<1> + slvbuf_wr_en <= UInt<1>("h00") + wire bypass_en : UInt<1> + bypass_en <= UInt<1>("h00") + wire rd_bypass_idle : UInt<1> + rd_bypass_idle <= UInt<1>("h00") + wire last_addr_en : UInt<1> + last_addr_en <= UInt<1>("h00") + wire last_bus_addr : UInt<32> + last_bus_addr <= UInt<32>("h00") + wire buf_clken : UInt<1> + buf_clken <= UInt<1>("h00") + wire slvbuf_clken : UInt<1> + slvbuf_clken <= UInt<1>("h00") + wire ahbm_addr_clken : UInt<1> + ahbm_addr_clken <= UInt<1>("h00") + wire ahbm_data_clken : UInt<1> + ahbm_data_clken <= UInt<1>("h00") + wire buf_clk : Clock @[axi4_to_ahb.scala 125:21] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 146:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 146:14] + node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 147:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 147:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 148:38] + node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 148:51] + node _T_11 = bits(io.axi.ar.bits.id, 0, 0) @[axi4_to_ahb.scala 148:82] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 148:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 148:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 149:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 149:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 149:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 150:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 150:53] + node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 150:81] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 150:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 150:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 151:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 151:53] + node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 151:80] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 151:21] + master_size <= _T_22 @[axi4_to_ahb.scala 151:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 152:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 152:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 153:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 153:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 156:33] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 156:58] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 156:47] + io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 156:18] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 157:38] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 157:65] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 157:55] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 157:28] + io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 157:22] + node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 158:32] + io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 158:20] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 160:33] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 160:59] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 160:66] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 160:47] + io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 160:18] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 161:38] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 161:65] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 161:55] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 161:28] + io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 161:22] + node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 162:32] + io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 162:20] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 163:36] + io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 163:22] + node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 164:33] + slave_ready <= _T_43 @[axi4_to_ahb.scala 164:15] + node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 167:57] + node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 167:94] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 167:76] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 167:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 167:20] + inst rvclkhdr of rvclkhdr @[lib.scala 343:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 169:11] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 170:59] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 343:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 170:17] + node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] + when _T_49 : @[Conditional.scala 40:58] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 174:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 175:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 175:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 175:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 176:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 176:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 176:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 177:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 177:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 178:17] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 179:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 179:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 179:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 180:27] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 182:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 182:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 142:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 142:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 143:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 143:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 143:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 143:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 143:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 143:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 143:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 143:48] + node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] + node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] + node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] + node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] + node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] + node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] + node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 182:124] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 182:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 182:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 183:17] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 184:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 184:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 184:22] + node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] + node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 185:49] + io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 185:25] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] + when _T_101 : @[Conditional.scala 39:67] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 189:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 189:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 189:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 189:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 189:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 189:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 190:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 190:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 190:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 190:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 190:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 190:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 191:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 191:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 191:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 192:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 193:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 193:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 193:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 193:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 193:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 193:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 193:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 193:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 193:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 193:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 193:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 193:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 193:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 194:17] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 195:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 195:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 196:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 196:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 196:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 196:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 196:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 197:48] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 197:62] + node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] + node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 197:36] + io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 197:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] + when _T_136 : @[Conditional.scala 39:67] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 201:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 201:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 201:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 201:70] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 201:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 201:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 201:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 202:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 202:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 202:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 202:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 202:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 203:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 203:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 203:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 203:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 203:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 203:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 203:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 203:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 203:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 204:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 204:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 205:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 206:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 207:23] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 208:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 208:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 208:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 209:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 209:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 209:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 210:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 210:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 210:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 210:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 210:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 211:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 211:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 211:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 211:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 211:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 212:63] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 212:78] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 212:47] + node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] + node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 212:36] + io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 212:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 213:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] + when _T_175 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 217:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 218:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 218:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 218:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 218:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 218:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 218:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 219:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 220:20] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 221:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 221:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 222:51] + node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] + node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 222:41] + io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 222:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] + when _T_186 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 226:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 227:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 227:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 228:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 229:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 230:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 231:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] + when _T_188 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 235:20] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 236:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 236:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 236:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 236:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 236:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 237:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 238:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 239:20] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 240:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 240:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 240:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 142:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 142:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 143:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 143:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 143:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 143:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 143:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 143:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 143:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 143:48] + node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] + node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] + node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] + node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] + node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] + node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] + node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 240:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 240:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 241:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 241:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 241:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 241:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 142:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 142:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 143:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 143:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 143:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 143:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 143:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 143:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 143:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 143:48] + node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] + node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] + node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] + node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] + node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] + node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] + node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 241:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 241:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 241:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 241:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 241:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 241:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 242:47] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 242:36] + node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] + node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 242:61] + io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 242:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] + when _T_281 : @[Conditional.scala 39:67] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 246:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 246:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 246:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 247:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 247:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 247:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 247:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 248:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 248:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 248:80] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 248:111] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 248:117] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 248:132] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 248:99] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 248:65] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 248:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 248:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 249:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 250:23] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 251:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 251:39] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 251:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 252:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 252:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 252:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 252:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 252:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 253:22] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 254:65] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 254:71] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 254:50] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 255:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 255:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 255:101] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 142:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 142:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 143:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 143:48] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 143:48] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 143:48] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 143:48] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 143:48] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 143:48] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 143:48] + node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] + node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] + node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] + node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] + node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] + node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] + node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 255:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 255:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 255:116] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 255:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 254:80] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 254:34] + cmd_done <= _T_348 @[axi4_to_ahb.scala 254:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 256:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 256:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 256:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 256:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 257:48] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 257:37] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 257:61] + node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] + node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 257:75] + io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 257:25] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 258:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 258:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 258:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 259:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 259:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 259:69] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 259:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 259:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 260:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 260:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 261:79] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 142:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 142:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 143:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 143:48] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 143:48] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 143:48] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 143:48] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 143:48] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 143:48] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 143:48] + node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] + node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] + node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] + node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] + node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] + node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] + node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 261:141] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 261:157] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 142:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 142:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 143:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 143:48] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 143:48] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 143:48] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 143:48] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 143:48] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 143:48] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 143:48] + node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] + node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] + node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] + node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] + node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] + node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] + node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 261:97] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 261:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 261:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] + when _T_440 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 264:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 265:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 266:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 267:23] + skip @[Conditional.scala 39:67] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 271:16] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 272:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 272:73] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 272:80] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 272:60] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 272:100] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:132] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 134:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 134:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 134:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 134:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 134:106] + node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] + node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 134:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 135:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 135:42] + node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] + node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 135:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 134:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 136:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 136:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 136:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 136:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 136:56] + node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] + node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 136:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 135:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 137:35] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 137:42] + node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] + node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 137:15] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 136:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 138:33] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 138:40] + node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] + node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 138:13] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 272:152] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 272:43] + node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 272:15] + node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 273:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 273:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 274:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 274:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 275:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 275:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 275:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 275:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 275:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 276:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 276:58] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 276:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 276:84] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 276:91] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 276:71] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 276:111] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 276:142] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 128:42] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 128:49] + node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] + node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 128:25] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 129:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 129:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 129:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 129:55] + node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] + node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 129:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 128:64] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 130:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 130:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 130:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 130:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 130:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 130:123] + node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] + node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 130:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 129:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 276:161] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 276:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 276:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 277:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 277:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 278:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 277:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 278:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 278:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 278:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 278:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 279:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 279:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 279:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 279:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 279:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 279:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 279:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 279:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 279:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 280:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 279:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 280:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 280:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 280:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 280:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 279:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 278:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 277:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 282:43] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 282:62] + node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 282:87] + node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] + node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 282:108] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 282:133] + node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] + node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 282:26] + io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 282:20] + node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 283:43] + node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] + node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 283:94] + node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 283:81] + node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] + node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] + node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 283:148] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 283:138] + node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] + node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 283:26] + io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 283:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 285:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 286:24] + node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 287:57] + node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 287:37] + node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] + io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 287:20] + node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 288:44] + node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 288:59] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 288:66] + node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 288:27] + io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 288:21] + node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 289:32] + io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 289:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 291:15] + node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 292:43] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 292:23] + node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] + node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 292:88] + node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] + slave_opc <= _T_600 @[axi4_to_ahb.scala 292:13] + node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 293:41] + node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 293:66] + node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] + node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 293:91] + node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 293:110] + node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 293:131] + node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 293:79] + node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 293:21] + slave_rdata <= _T_608 @[axi4_to_ahb.scala 293:15] + node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 294:26] + slave_tag <= _T_609 @[axi4_to_ahb.scala 294:13] + node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 296:37] + node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 296:44] + node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 296:56] + node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 296:75] + last_addr_en <= _T_613 @[axi4_to_ahb.scala 296:16] + node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 298:31] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 298:49] + wrbuf_en <= _T_615 @[axi4_to_ahb.scala 298:12] + node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 299:35] + node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 299:52] + wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 299:17] + node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 300:34] + node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 300:62] + node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 300:69] + node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 300:49] + wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 300:18] + node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 301:33] + node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 301:31] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 301:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 303:36] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 303:34] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 303:22] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 303:53] + io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 303:19] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 304:40] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 304:38] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 304:21] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 304:57] + io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 304:18] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 305:34] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 305:22] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 305:52] + io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 305:19] + io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 306:22] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 308:71] + node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 308:55] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 308:91] + node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 308:89] + reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 308:51] + _T_639 <= _T_638 @[axi4_to_ahb.scala 308:51] + wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 308:21] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 309:76] + node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 309:55] + node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 309:102] + node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 309:100] + reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 309:51] + _T_644 <= _T_643 @[axi4_to_ahb.scala 309:51] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 309:21] + node _T_645 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 310:71] + node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 310:105] + reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_646 : @[Reg.scala 28:19] + _T_647 <= _T_645 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 310:21] + node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 311:73] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 311:101] + reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_649 : @[Reg.scala 28:19] + _T_650 <= _T_648 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_size <= _T_650 @[axi4_to_ahb.scala 311:21] + node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 312:61] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 368:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] + wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 312:21] + node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 313:65] + inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] + wrbuf_data <= _T_654 @[axi4_to_ahb.scala 313:21] + node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 314:72] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 314:105] + reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_656 : @[Reg.scala 28:19] + _T_657 <= _T_655 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 314:21] + node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 315:71] + node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 315:104] + reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_659 : @[Reg.scala 28:19] + _T_660 <= _T_658 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + last_bus_addr <= _T_660 @[axi4_to_ahb.scala 315:21] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] + reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_661 : @[Reg.scala 28:19] + _T_662 <= buf_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_write <= _T_662 @[axi4_to_ahb.scala 316:21] + node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 317:64] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] + reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_664 : @[Reg.scala 28:19] + _T_665 <= _T_663 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_tag <= _T_665 @[axi4_to_ahb.scala 317:21] + node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 318:42] + node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 318:61] + node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 318:78] + inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 368:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_669 <= _T_666 @[lib.scala 374:16] + buf_addr <= _T_669 @[axi4_to_ahb.scala 318:21] + node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 319:65] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 319:94] + reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_671 : @[Reg.scala 28:19] + _T_672 <= _T_670 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_size <= _T_672 @[axi4_to_ahb.scala 319:21] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 320:91] + reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_673 : @[Reg.scala 28:19] + _T_674 <= buf_aligned_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_aligned <= _T_674 @[axi4_to_ahb.scala 320:21] + node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 321:67] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 321:96] + reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_676 : @[Reg.scala 28:19] + _T_677 <= _T_675 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen <= _T_677 @[axi4_to_ahb.scala 321:21] + node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 322:42] + node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 322:66] + node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 322:89] + inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 368:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_681 <= _T_678 @[lib.scala 374:16] + buf_data <= _T_681 @[axi4_to_ahb.scala 322:21] + node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 323:89] + reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_682 : @[Reg.scala 28:19] + _T_683 <= buf_write @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_write <= _T_683 @[axi4_to_ahb.scala 323:21] + node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 324:61] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 324:99] + reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_685 : @[Reg.scala 28:19] + _T_686 <= _T_684 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 324:21] + node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 325:99] + reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_687 : @[Reg.scala 28:19] + _T_688 <= slvbuf_error_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_error <= _T_688 @[axi4_to_ahb.scala 325:21] + node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 326:72] + node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 326:56] + node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 326:92] + node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 326:90] + reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 326:52] + _T_693 <= _T_692 @[axi4_to_ahb.scala 326:52] + cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 326:21] + node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 327:71] + node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 327:110] + reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_695 : @[Reg.scala 28:19] + _T_696 <= _T_694 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 327:21] + reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 328:52] + _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 328:52] + ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 328:21] + node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 329:70] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 329:52] + _T_699 <= _T_698 @[axi4_to_ahb.scala 329:52] + ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 329:21] + reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 330:57] + _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 330:57] + ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 330:21] + reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 331:52] + _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 331:52] + ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 331:21] + node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 332:74] + reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 332:57] + _T_703 <= _T_702 @[axi4_to_ahb.scala 332:57] + ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 332:21] + node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 334:43] + node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 334:58] + node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 334:30] + buf_clken <= _T_706 @[axi4_to_ahb.scala 334:13] + node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 335:76] + node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 335:57] + node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 335:81] + node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 335:36] + ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 335:19] + node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 336:50] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 336:60] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 336:36] + ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 336:19] + inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 343:22] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 339:12] + inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 343:22] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 340:12] + inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 343:22] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 341:17] + inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 343:22] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 342:17] + diff --git a/axi4_to_ahb.v b/axi4_to_ahb.v new file mode 100644 index 00000000..2c3bf777 --- /dev/null +++ b/axi4_to_ahb.v @@ -0,0 +1,1139 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[lib.scala 334:26] + wire clkhdr_CK; // @[lib.scala 334:26] + wire clkhdr_EN; // @[lib.scala 334:26] + wire clkhdr_SE; // @[lib.scala 334:26] + gated_latch clkhdr ( // @[lib.scala 334:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14] + assign clkhdr_CK = io_clk; // @[lib.scala 336:18] + assign clkhdr_EN = io_en; // @[lib.scala 337:18] + assign clkhdr_SE = io_scan_mode; // @[lib.scala 338:18] +endmodule +module axi4_to_ahb( + input clock, + input reset, + input io_scan_mode, + input io_bus_clk_en, + input io_clk_override, + output io_axi_aw_ready, + input io_axi_aw_valid, + input io_axi_aw_bits_id, + input [31:0] io_axi_aw_bits_addr, + input [3:0] io_axi_aw_bits_region, + input [7:0] io_axi_aw_bits_len, + input [2:0] io_axi_aw_bits_size, + input [1:0] io_axi_aw_bits_burst, + input io_axi_aw_bits_lock, + input [3:0] io_axi_aw_bits_cache, + input [2:0] io_axi_aw_bits_prot, + input [3:0] io_axi_aw_bits_qos, + output io_axi_w_ready, + input io_axi_w_valid, + input [63:0] io_axi_w_bits_data, + input [7:0] io_axi_w_bits_strb, + input io_axi_w_bits_last, + input io_axi_b_ready, + output io_axi_b_valid, + output [1:0] io_axi_b_bits_resp, + output io_axi_b_bits_id, + output io_axi_ar_ready, + input io_axi_ar_valid, + input io_axi_ar_bits_id, + input [31:0] io_axi_ar_bits_addr, + input [3:0] io_axi_ar_bits_region, + input [7:0] io_axi_ar_bits_len, + input [2:0] io_axi_ar_bits_size, + input [1:0] io_axi_ar_bits_burst, + input io_axi_ar_bits_lock, + input [3:0] io_axi_ar_bits_cache, + input [2:0] io_axi_ar_bits_prot, + input [3:0] io_axi_ar_bits_qos, + input io_axi_r_ready, + output io_axi_r_valid, + output io_axi_r_bits_id, + output [63:0] io_axi_r_bits_data, + output [1:0] io_axi_r_bits_resp, + output io_axi_r_bits_last, + input [63:0] io_ahb_in_hrdata, + input io_ahb_in_hready, + input io_ahb_in_hresp, + output [31:0] io_ahb_out_haddr, + output [2:0] io_ahb_out_hburst, + output io_ahb_out_hmastlock, + output [3:0] io_ahb_out_hprot, + output [2:0] io_ahb_out_hsize, + output [1:0] io_ahb_out_htrans, + output io_ahb_out_hwrite, + output [63:0] io_ahb_out_hwdata +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [63:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [63:0] _RAND_17; + reg [63:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_en; // @[lib.scala 368:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_6_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_6_io_en; // @[lib.scala 343:22] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_7_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_7_io_en; // @[lib.scala 343:22] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_8_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_8_io_en; // @[lib.scala 343:22] + wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_9_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_9_io_en; // @[lib.scala 343:22] + wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] + wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 31:22 axi4_to_ahb.scala 340:12] + reg [2:0] buf_state; // @[axi4_to_ahb.scala 37:45] + wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] + wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 57:21 axi4_to_ahb.scala 169:11] + reg wrbuf_vld; // @[axi4_to_ahb.scala 308:51] + reg wrbuf_data_vld; // @[axi4_to_ahb.scala 309:51] + wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 146:27] + wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 147:30] + wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] + reg ahb_hready_q; // @[axi4_to_ahb.scala 328:52] + reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 329:52] + wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 190:58] + wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 190:36] + wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 32:27 axi4_to_ahb.scala 341:17] + reg ahb_hwrite_q; // @[axi4_to_ahb.scala 330:57] + wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 190:72] + wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 190:70] + wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] + reg ahb_hresp_q; // @[axi4_to_ahb.scala 331:52] + wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 204:37] + wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] + wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] + wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] + wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 236:33] + wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 236:48] + wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] + wire _GEN_15 = _T_281 & _T_192; // @[Conditional.scala 39:67] + wire _GEN_19 = _T_188 ? _T_192 : _GEN_15; // @[Conditional.scala 39:67] + wire _GEN_40 = _T_186 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_175 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] + wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] + wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] + wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] + reg cmd_doneQ; // @[axi4_to_ahb.scala 326:52] + wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 246:34] + wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 246:50] + wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] + wire slave_ready = io_axi_b_ready & io_axi_r_ready; // @[axi4_to_ahb.scala 164:33] + wire _GEN_1 = _T_440 & slave_ready; // @[Conditional.scala 39:67] + wire _GEN_3 = _T_281 ? _T_283 : _GEN_1; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] + wire _GEN_35 = _T_186 ? _T_156 : _GEN_20; // @[Conditional.scala 39:67] + wire _GEN_51 = _T_175 ? _T_111 : _GEN_35; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_136 ? _T_156 : _GEN_51; // @[Conditional.scala 39:67] + wire _GEN_83 = _T_101 ? _T_111 : _GEN_69; // @[Conditional.scala 39:67] + wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] + wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 149:20] + wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 149:14] + wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 175:41] + wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] + wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] + wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_175 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] + wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] + wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] + wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 176:26] + wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 189:61] + wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 189:41] + wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 189:26] + wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 193:174] + wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 193:88] + wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 201:39] + wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 201:37] + wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 201:70] + wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 201:55] + wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 201:53] + wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 247:36] + wire _T_286 = _T_285 & slave_ready; // @[axi4_to_ahb.scala 247:51] + wire _GEN_4 = _T_281 & _T_286; // @[Conditional.scala 39:67] + wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] + wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_136 ? _T_143 : _GEN_62; // @[Conditional.scala 39:67] + wire _GEN_86 = _T_101 ? _T_125 : _GEN_66; // @[Conditional.scala 39:67] + wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] + wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 203:82] + wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 203:97] + wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 203:67] + wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 203:26] + wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 248:42] + wire _T_288 = ahb_hresp_q | _T_287; // @[axi4_to_ahb.scala 248:40] + wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 248:99] + wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 248:65] + wire [2:0] _T_295 = _T_288 ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 248:26] + wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] + wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] + wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] + wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] + wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67] + wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] + wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] + reg wrbuf_tag; // @[Reg.scala 27:20] + reg [31:0] wrbuf_addr; // @[lib.scala 374:16] + wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 150:21] + reg [2:0] wrbuf_size; // @[Reg.scala 27:20] + wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 151:21] + reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] + reg [63:0] wrbuf_data; // @[lib.scala 374:16] + wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 258:55] + wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 258:39] + wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67] + wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] + wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] + wire _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] + wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] + wire _T_25 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 156:33] + wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 125:21 axi4_to_ahb.scala 339:12] + reg slvbuf_write; // @[Reg.scala 27:20] + wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 292:23] + reg slvbuf_error; // @[Reg.scala 27:20] + wire [1:0] _T_598 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 292:88] + wire [3:0] slave_opc = {_T_596,_T_599}; // @[Cat.scala 29:58] + wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 157:55] + reg slvbuf_tag; // @[Reg.scala 27:20] + wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 160:66] + reg [31:0] last_bus_addr; // @[Reg.scala 27:20] + wire [63:0] _T_603 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] + wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 293:91] + reg [63:0] buf_data; // @[lib.scala 374:16] + wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 33:27 axi4_to_ahb.scala 342:17] + reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 332:57] + wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 293:79] + wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 167:57] + wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 167:94] + wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 167:76] + wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 179:54] + wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 179:38] + wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16] + wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16] + wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16] + wire [2:0] _T_90 = wrbuf_byteen[3] ? 3'h3 : _T_89; // @[Mux.scala 98:16] + wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16] + wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16] + wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16] + wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 182:30] + wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 184:51] + wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 195:33] + wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 210:64] + wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 210:48] + wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 210:79] + wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 256:33] + wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 256:48] + wire _GEN_12 = _T_281 & _T_351; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] + wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_65 = _T_175 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] + wire _GEN_75 = _T_136 ? _T_164 : _GEN_65; // @[Conditional.scala 39:67] + wire _GEN_88 = _T_101 ? _T_126 : _GEN_75; // @[Conditional.scala 39:67] + wire bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] + wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 185:49] + wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 191:34] + wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 191:32] + reg [31:0] buf_addr; // @[lib.scala 374:16] + wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 196:30] + wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 197:48] + wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 197:62] + wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 197:36] + wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 212:63] + wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 212:78] + wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 212:47] + wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 212:36] + wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 222:41] + reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] + reg [7:0] buf_byteen; // @[Reg.scala 27:20] + wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 142:52] + wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 143:62] + wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 143:48] + wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 143:62] + wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 143:48] + wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 143:62] + wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 143:48] + wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 143:62] + wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 143:48] + wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 143:62] + wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 143:48] + wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 143:62] + wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 143:48] + wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 143:62] + wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 143:48] + wire [2:0] _T_224 = _T_219 ? 3'h6 : 3'h7; // @[Mux.scala 98:16] + wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16] + wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16] + wire [2:0] _T_227 = _T_210 ? 3'h3 : _T_226; // @[Mux.scala 98:16] + wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16] + wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16] + wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16] + wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 240:30] + wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 241:65] + reg buf_aligned; // @[Reg.scala 27:20] + wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 241:44] + wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 241:92] + wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 241:163] + wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 241:79] + wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 241:29] + wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 255:38] + wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 254:80] + wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 254:34] + wire _GEN_11 = _T_281 & _T_348; // @[Conditional.scala 39:67] + wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] + wire _GEN_61 = _T_175 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_136 ? _T_113 : _GEN_61; // @[Conditional.scala 39:67] + wire _GEN_84 = _T_101 ? _T_113 : _GEN_74; // @[Conditional.scala 39:67] + wire cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] + wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 242:47] + wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 242:36] + wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 242:61] + wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 252:62] + wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 252:33] + wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 257:61] + wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 257:75] + wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 260:40] + wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 261:30] + wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] + wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67] + wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] + wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] + wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_175 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] + wire _GEN_67 = _T_136 ? _T_152 : _GEN_64; // @[Conditional.scala 39:67] + wire _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] + wire buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] + wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] + wire [1:0] _GEN_13 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67] + wire _GEN_16 = _T_281 & _T_364; // @[Conditional.scala 39:67] + wire [2:0] _GEN_17 = _T_281 ? _T_439 : 3'h0; // @[Conditional.scala 39:67] + wire _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] + wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] + wire [2:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67] + wire [1:0] _GEN_25 = _T_188 ? _T_280 : _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_28 = _T_188 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] + wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] + wire _GEN_36 = _T_186 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_186 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] + wire _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] + wire _GEN_41 = _T_186 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] + wire [2:0] _GEN_42 = _T_186 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67] + wire [1:0] _GEN_44 = _T_186 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] + wire [2:0] _GEN_54 = _T_175 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67] + wire [1:0] _GEN_55 = _T_175 ? _T_185 : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] + wire _GEN_58 = _T_175 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] + wire _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_72 = _T_136 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] + wire [2:0] _GEN_76 = _T_136 ? _T_130 : _GEN_54; // @[Conditional.scala 39:67] + wire [1:0] _GEN_77 = _T_136 ? _T_174 : _GEN_55; // @[Conditional.scala 39:67] + wire _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] + wire [2:0] _GEN_89 = _T_101 ? _T_130 : _GEN_76; // @[Conditional.scala 39:67] + wire [1:0] _GEN_90 = _T_101 ? _T_135 : _GEN_77; // @[Conditional.scala 39:67] + wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] + wire _GEN_93 = _T_101 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] + wire _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] + wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] + wire buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58] + wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58] + wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] + wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] + wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 278:24] + wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 277:48] + wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 278:54] + wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 278:33] + wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 278:93] + wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 278:72] + wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 279:25] + wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 279:62] + wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 279:97] + wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 279:74] + wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 279:132] + wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 279:109] + wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 279:168] + wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 279:145] + wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 280:28] + wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 279:181] + wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 280:63] + wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 280:40] + wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 280:99] + wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 280:76] + wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 279:38] + wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 278:106] + wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 272:60] + wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 135:15] + wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 136:56] + wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 136:15] + wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 135:63] + wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 137:15] + wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 136:96] + wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 272:43] + wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 275:33] + wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 276:38] + wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 276:71] + wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 129:55] + wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 129:16] + wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 128:64] + wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 130:60] + wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 130:89] + wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 130:123] + wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 130:21] + wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 129:93] + wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 276:21] + wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 276:15] + wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 283:81] + wire [2:0] _T_580 = {1'h0,_T_579}; // @[Cat.scala 29:58] + wire [1:0] _T_582 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + reg [1:0] buf_size; // @[Reg.scala 27:20] + wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 283:138] + wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58] + wire _T_588 = ~io_axi_ar_bits_prot[2]; // @[axi4_to_ahb.scala 287:37] + wire [1:0] _T_589 = {1'h1,_T_588}; // @[Cat.scala 29:58] + reg buf_write; // @[Reg.scala 27:20] + wire _T_611 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 296:44] + wire _T_612 = _T_611 & io_ahb_in_hready; // @[axi4_to_ahb.scala 296:56] + wire last_addr_en = _T_612 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 296:75] + wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 298:49] + wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 299:52] + wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 300:49] + wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 301:33] + wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 301:31] + wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 303:36] + wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 303:34] + wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 303:22] + wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 304:38] + wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 304:21] + wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 305:22] + wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 308:55] + wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 308:91] + wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 309:55] + reg buf_tag; // @[Reg.scala 27:20] + wire _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 326:92] + wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 334:43] + wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 334:58] + wire _T_708 = io_ahb_in_hready & io_ahb_out_htrans[1]; // @[axi4_to_ahb.scala 335:57] + wire _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 335:81] + wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 336:50] + wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 336:60] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 303:19] + assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 304:18] + assign io_axi_b_valid = _T_25 & slave_opc[3]; // @[axi4_to_ahb.scala 156:18] + assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 157:22] + assign io_axi_b_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 158:20] + assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 305:19] + assign io_axi_r_valid = _T_25 & _T_35; // @[axi4_to_ahb.scala 160:18] + assign io_axi_r_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 162:20] + assign io_axi_r_bits_data = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 163:22] + assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 161:22] + assign io_axi_r_bits_last = 1'h1; // @[axi4_to_ahb.scala 306:22] + assign io_ahb_out_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 282:20] + assign io_ahb_out_hburst = 3'h0; // @[axi4_to_ahb.scala 285:21] + assign io_ahb_out_hmastlock = 1'h0; // @[axi4_to_ahb.scala 286:24] + assign io_ahb_out_hprot = {{2'd0}, _T_589}; // @[axi4_to_ahb.scala 287:20] + assign io_ahb_out_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 283:20] + assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 29:21 axi4_to_ahb.scala 185:25 axi4_to_ahb.scala 197:25 axi4_to_ahb.scala 212:25 axi4_to_ahb.scala 222:25 axi4_to_ahb.scala 242:25 axi4_to_ahb.scala 257:25] + assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 288:21] + assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 289:21] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = io_bus_clk_en & _T_46; // @[lib.scala 345:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_2_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = _T_44 & master_ready; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = _T_45 & master_ready; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = buf_wr_en & io_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_6_io_en = io_bus_clk_en & _T_705; // @[lib.scala 345:16] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_7_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_8_io_en = io_bus_clk_en & _T_709; // @[lib.scala 345:16] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_9_io_en = io_bus_clk_en & _T_712; // @[lib.scala 345:16] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + buf_state = _RAND_0[2:0]; + _RAND_1 = {1{`RANDOM}}; + wrbuf_vld = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + wrbuf_data_vld = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + ahb_hready_q = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + ahb_htrans_q = _RAND_4[1:0]; + _RAND_5 = {1{`RANDOM}}; + ahb_hwrite_q = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + ahb_hresp_q = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + cmd_doneQ = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + wrbuf_tag = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + wrbuf_addr = _RAND_9[31:0]; + _RAND_10 = {1{`RANDOM}}; + wrbuf_size = _RAND_10[2:0]; + _RAND_11 = {1{`RANDOM}}; + wrbuf_byteen = _RAND_11[7:0]; + _RAND_12 = {2{`RANDOM}}; + wrbuf_data = _RAND_12[63:0]; + _RAND_13 = {1{`RANDOM}}; + slvbuf_write = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + slvbuf_error = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + slvbuf_tag = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + last_bus_addr = _RAND_16[31:0]; + _RAND_17 = {2{`RANDOM}}; + buf_data = _RAND_17[63:0]; + _RAND_18 = {2{`RANDOM}}; + ahb_hrdata_q = _RAND_18[63:0]; + _RAND_19 = {1{`RANDOM}}; + buf_addr = _RAND_19[31:0]; + _RAND_20 = {1{`RANDOM}}; + buf_cmd_byte_ptrQ = _RAND_20[2:0]; + _RAND_21 = {1{`RANDOM}}; + buf_byteen = _RAND_21[7:0]; + _RAND_22 = {1{`RANDOM}}; + buf_aligned = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + buf_size = _RAND_23[1:0]; + _RAND_24 = {1{`RANDOM}}; + buf_write = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + buf_tag = _RAND_25[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + buf_state = 3'h0; + end + if (reset) begin + wrbuf_vld = 1'h0; + end + if (reset) begin + wrbuf_data_vld = 1'h0; + end + if (reset) begin + ahb_hready_q = 1'h0; + end + if (reset) begin + ahb_htrans_q = 2'h0; + end + if (reset) begin + ahb_hwrite_q = 1'h0; + end + if (reset) begin + ahb_hresp_q = 1'h0; + end + if (reset) begin + cmd_doneQ = 1'h0; + end + if (reset) begin + wrbuf_tag = 1'h0; + end + if (reset) begin + wrbuf_addr = 32'h0; + end + if (reset) begin + wrbuf_size = 3'h0; + end + if (reset) begin + wrbuf_byteen = 8'h0; + end + if (reset) begin + wrbuf_data = 64'h0; + end + if (reset) begin + slvbuf_write = 1'h0; + end + if (reset) begin + slvbuf_error = 1'h0; + end + if (reset) begin + slvbuf_tag = 1'h0; + end + if (reset) begin + last_bus_addr = 32'h0; + end + if (reset) begin + buf_data = 64'h0; + end + if (reset) begin + ahb_hrdata_q = 64'h0; + end + if (reset) begin + buf_addr = 32'h0; + end + if (reset) begin + buf_cmd_byte_ptrQ = 3'h0; + end + if (reset) begin + buf_byteen = 8'h0; + end + if (reset) begin + buf_aligned = 1'h0; + end + if (reset) begin + buf_size = 2'h0; + end + if (reset) begin + buf_write = 1'h0; + end + if (reset) begin + buf_tag = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + buf_state <= 3'h0; + end else if (buf_state_en) begin + if (_T_49) begin + if (buf_write_in) begin + buf_state <= 3'h2; + end else begin + buf_state <= 3'h1; + end + end else if (_T_101) begin + if (_T_104) begin + buf_state <= 3'h6; + end else begin + buf_state <= 3'h3; + end + end else if (_T_136) begin + if (ahb_hresp_q) begin + buf_state <= 3'h7; + end else if (_T_152) begin + buf_state <= 3'h6; + end else begin + buf_state <= 3'h3; + end + end else if (_T_175) begin + buf_state <= 3'h3; + end else if (_T_186) begin + buf_state <= 3'h5; + end else if (_T_188) begin + buf_state <= 3'h4; + end else if (_T_281) begin + if (_T_288) begin + buf_state <= 3'h5; + end else if (master_valid) begin + if (_T_51) begin + buf_state <= 3'h2; + end else begin + buf_state <= 3'h1; + end + end else begin + buf_state <= 3'h0; + end + end else begin + buf_state <= 3'h0; + end + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_vld <= 1'h0; + end else begin + wrbuf_vld <= _T_636 & _T_637; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_data_vld <= 1'h0; + end else begin + wrbuf_data_vld <= _T_641 & _T_637; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + ahb_hready_q <= 1'h0; + end else begin + ahb_hready_q <= io_ahb_in_hready; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + ahb_htrans_q <= 2'h0; + end else begin + ahb_htrans_q <= io_ahb_out_htrans; + end + end + always @(posedge ahbm_addr_clk or posedge reset) begin + if (reset) begin + ahb_hwrite_q <= 1'h0; + end else begin + ahb_hwrite_q <= io_ahb_out_hwrite; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + ahb_hresp_q <= 1'h0; + end else begin + ahb_hresp_q <= io_ahb_in_hresp; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + cmd_doneQ <= 1'h0; + end else begin + cmd_doneQ <= _T_276 & _T_691; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_tag <= 1'h0; + end else if (wrbuf_en) begin + wrbuf_tag <= io_axi_aw_bits_id; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + wrbuf_addr <= 32'h0; + end else begin + wrbuf_addr <= io_axi_aw_bits_addr; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_size <= 3'h0; + end else if (wrbuf_en) begin + wrbuf_size <= io_axi_aw_bits_size; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_byteen <= 8'h0; + end else if (wrbuf_data_en) begin + wrbuf_byteen <= io_axi_w_bits_strb; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + wrbuf_data <= 64'h0; + end else begin + wrbuf_data <= io_axi_w_bits_data; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + slvbuf_write <= 1'h0; + end else if (slvbuf_wr_en) begin + slvbuf_write <= buf_write; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + slvbuf_error <= 1'h0; + end else if (slvbuf_error_en) begin + if (_T_49) begin + slvbuf_error <= 1'h0; + end else if (_T_101) begin + slvbuf_error <= 1'h0; + end else if (_T_136) begin + slvbuf_error <= ahb_hresp_q; + end else if (_T_175) begin + slvbuf_error <= 1'h0; + end else if (_T_186) begin + slvbuf_error <= ahb_hresp_q; + end else if (_T_188) begin + slvbuf_error <= 1'h0; + end else begin + slvbuf_error <= _GEN_6; + end + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + slvbuf_tag <= 1'h0; + end else if (slvbuf_wr_en) begin + slvbuf_tag <= buf_tag; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + last_bus_addr <= 32'h0; + end else if (last_addr_en) begin + last_bus_addr <= io_ahb_out_haddr; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + buf_data <= 64'h0; + end else if (_T_489) begin + buf_data <= ahb_hrdata_q; + end else begin + buf_data <= wrbuf_data; + end + end + always @(posedge ahbm_data_clk or posedge reset) begin + if (reset) begin + ahb_hrdata_q <= 64'h0; + end else begin + ahb_hrdata_q <= io_ahb_in_hrdata; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr <= 32'h0; + end else begin + buf_addr <= {master_addr[31:3],_T_485}; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (buf_cmd_byte_ptr_en) begin + if (_T_49) begin + if (buf_write_in) begin + if (wrbuf_byteen[0]) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (wrbuf_byteen[1]) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (wrbuf_byteen[2]) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (wrbuf_byteen[3]) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (wrbuf_byteen[4]) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (wrbuf_byteen[5]) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (wrbuf_byteen[6]) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end else begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end + end else if (_T_101) begin + if (bypass_en) begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end else begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end + end else if (_T_136) begin + if (bypass_en) begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end else begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end + end else if (_T_175) begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end else if (_T_186) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_188) begin + if (trxn_done) begin + if (_T_201) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_204) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (_T_207) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (_T_210) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (_T_213) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (_T_216) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (_T_219) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end + end else if (_T_281) begin + if (bypass_en) begin + if (wrbuf_byteen[0]) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (wrbuf_byteen[1]) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (wrbuf_byteen[2]) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (wrbuf_byteen[3]) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (wrbuf_byteen[4]) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (wrbuf_byteen[5]) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (wrbuf_byteen[6]) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end else if (trxn_done) begin + if (_T_201) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_204) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (_T_207) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (_T_210) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (_T_213) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (_T_216) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (_T_219) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end + end else begin + buf_cmd_byte_ptrQ <= 3'h0; + end + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_byteen <= 8'h0; + end else if (buf_wr_en) begin + buf_byteen <= wrbuf_byteen; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_aligned <= 1'h0; + end else if (buf_wr_en) begin + buf_aligned <= buf_aligned_in; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_size <= 2'h0; + end else if (buf_wr_en) begin + buf_size <= buf_size_in[1:0]; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_write <= 1'h0; + end else if (buf_wr_en) begin + if (_T_49) begin + buf_write <= _T_51; + end else if (_T_101) begin + buf_write <= 1'h0; + end else if (_T_136) begin + buf_write <= 1'h0; + end else if (_T_175) begin + buf_write <= 1'h0; + end else if (_T_186) begin + buf_write <= 1'h0; + end else if (_T_188) begin + buf_write <= 1'h0; + end else begin + buf_write <= _GEN_8; + end + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_tag <= 1'h0; + end else if (buf_wr_en) begin + if (wr_cmd_vld) begin + buf_tag <= wrbuf_tag; + end else begin + buf_tag <= io_axi_ar_bits_id; + end + end + end +endmodule diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir index e44fa672..4c78863d 100644 --- a/quasar_wrapper.fir +++ b/quasar_wrapper.fir @@ -95900,7 +95900,7 @@ circuit quasar_wrapper : node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[lsu_bus_buffer.scala 174:32] node _T_749 = or(_T_747, _T_748) @[lsu_bus_buffer.scala 173:103] io.ld_fwddata_buf_hi <= _T_749 @[lsu_bus_buffer.scala 170:24] - node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 176:77] + node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h01")) @[lsu_bus_buffer.scala 176:77] node _T_750 = mux(io.lsu_pkt_r.bits.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_751 = mux(io.lsu_pkt_r.bits.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_752 = mux(io.lsu_pkt_r.bits.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -97157,7 +97157,7 @@ circuit quasar_wrapper : node _T_1751 = and(_T_1723, _T_1750) @[lsu_bus_buffer.scala 339:67] node _T_1752 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 340:81] node _T_1753 = and(_T_1751, _T_1752) @[lsu_bus_buffer.scala 340:79] - node _T_1754 = eq(UInt<1>("h01"), UInt<1>("h00")) @[lsu_bus_buffer.scala 340:107] + node _T_1754 = eq(UInt<1>("h00"), UInt<1>("h00")) @[lsu_bus_buffer.scala 340:107] node _T_1755 = and(_T_1753, _T_1754) @[lsu_bus_buffer.scala 340:105] node _T_1756 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 56:118] node _T_1757 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 56:129] @@ -99196,7 +99196,7 @@ circuit quasar_wrapper : node _T_3589 = eq(UInt<3>("h03"), buf_state[0]) @[Conditional.scala 37:30] when _T_3589 : @[Conditional.scala 39:67] node _T_3590 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 465:67] - node _T_3591 = and(UInt<1>("h01"), bus_rsp_write_error) @[lsu_bus_buffer.scala 465:94] + node _T_3591 = and(UInt<1>("h00"), bus_rsp_write_error) @[lsu_bus_buffer.scala 465:94] node _T_3592 = eq(_T_3591, UInt<1>("h00")) @[lsu_bus_buffer.scala 465:73] node _T_3593 = and(_T_3590, _T_3592) @[lsu_bus_buffer.scala 465:71] node _T_3594 = or(io.dec_tlu_force_halt, _T_3593) @[lsu_bus_buffer.scala 465:55] @@ -99274,7 +99274,7 @@ circuit quasar_wrapper : node _T_3660 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 476:66] node _T_3661 = and(_T_3659, _T_3660) @[lsu_bus_buffer.scala 476:46] node _T_3662 = or(_T_3657, _T_3661) @[lsu_bus_buffer.scala 475:143] - node _T_3663 = and(bus_rsp_write_error, UInt<1>("h01")) @[lsu_bus_buffer.scala 477:32] + node _T_3663 = and(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 477:32] node _T_3664 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 477:74] node _T_3665 = and(_T_3663, _T_3664) @[lsu_bus_buffer.scala 477:53] node _T_3666 = or(_T_3662, _T_3665) @[lsu_bus_buffer.scala 476:88] @@ -99472,7 +99472,7 @@ circuit quasar_wrapper : node _T_3782 = eq(UInt<3>("h03"), buf_state[1]) @[Conditional.scala 37:30] when _T_3782 : @[Conditional.scala 39:67] node _T_3783 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 465:67] - node _T_3784 = and(UInt<1>("h01"), bus_rsp_write_error) @[lsu_bus_buffer.scala 465:94] + node _T_3784 = and(UInt<1>("h00"), bus_rsp_write_error) @[lsu_bus_buffer.scala 465:94] node _T_3785 = eq(_T_3784, UInt<1>("h00")) @[lsu_bus_buffer.scala 465:73] node _T_3786 = and(_T_3783, _T_3785) @[lsu_bus_buffer.scala 465:71] node _T_3787 = or(io.dec_tlu_force_halt, _T_3786) @[lsu_bus_buffer.scala 465:55] @@ -99550,7 +99550,7 @@ circuit quasar_wrapper : node _T_3853 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 476:66] node _T_3854 = and(_T_3852, _T_3853) @[lsu_bus_buffer.scala 476:46] node _T_3855 = or(_T_3850, _T_3854) @[lsu_bus_buffer.scala 475:143] - node _T_3856 = and(bus_rsp_write_error, UInt<1>("h01")) @[lsu_bus_buffer.scala 477:32] + node _T_3856 = and(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 477:32] node _T_3857 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 477:74] node _T_3858 = and(_T_3856, _T_3857) @[lsu_bus_buffer.scala 477:53] node _T_3859 = or(_T_3855, _T_3858) @[lsu_bus_buffer.scala 476:88] @@ -99748,7 +99748,7 @@ circuit quasar_wrapper : node _T_3975 = eq(UInt<3>("h03"), buf_state[2]) @[Conditional.scala 37:30] when _T_3975 : @[Conditional.scala 39:67] node _T_3976 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 465:67] - node _T_3977 = and(UInt<1>("h01"), bus_rsp_write_error) @[lsu_bus_buffer.scala 465:94] + node _T_3977 = and(UInt<1>("h00"), bus_rsp_write_error) @[lsu_bus_buffer.scala 465:94] node _T_3978 = eq(_T_3977, UInt<1>("h00")) @[lsu_bus_buffer.scala 465:73] node _T_3979 = and(_T_3976, _T_3978) @[lsu_bus_buffer.scala 465:71] node _T_3980 = or(io.dec_tlu_force_halt, _T_3979) @[lsu_bus_buffer.scala 465:55] @@ -99826,7 +99826,7 @@ circuit quasar_wrapper : node _T_4046 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 476:66] node _T_4047 = and(_T_4045, _T_4046) @[lsu_bus_buffer.scala 476:46] node _T_4048 = or(_T_4043, _T_4047) @[lsu_bus_buffer.scala 475:143] - node _T_4049 = and(bus_rsp_write_error, UInt<1>("h01")) @[lsu_bus_buffer.scala 477:32] + node _T_4049 = and(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 477:32] node _T_4050 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 477:74] node _T_4051 = and(_T_4049, _T_4050) @[lsu_bus_buffer.scala 477:53] node _T_4052 = or(_T_4048, _T_4051) @[lsu_bus_buffer.scala 476:88] @@ -100024,7 +100024,7 @@ circuit quasar_wrapper : node _T_4168 = eq(UInt<3>("h03"), buf_state[3]) @[Conditional.scala 37:30] when _T_4168 : @[Conditional.scala 39:67] node _T_4169 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 465:67] - node _T_4170 = and(UInt<1>("h01"), bus_rsp_write_error) @[lsu_bus_buffer.scala 465:94] + node _T_4170 = and(UInt<1>("h00"), bus_rsp_write_error) @[lsu_bus_buffer.scala 465:94] node _T_4171 = eq(_T_4170, UInt<1>("h00")) @[lsu_bus_buffer.scala 465:73] node _T_4172 = and(_T_4169, _T_4171) @[lsu_bus_buffer.scala 465:71] node _T_4173 = or(io.dec_tlu_force_halt, _T_4172) @[lsu_bus_buffer.scala 465:55] @@ -100102,7 +100102,7 @@ circuit quasar_wrapper : node _T_4239 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 476:66] node _T_4240 = and(_T_4238, _T_4239) @[lsu_bus_buffer.scala 476:46] node _T_4241 = or(_T_4236, _T_4240) @[lsu_bus_buffer.scala 475:143] - node _T_4242 = and(bus_rsp_write_error, UInt<1>("h01")) @[lsu_bus_buffer.scala 477:32] + node _T_4242 = and(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 477:32] node _T_4243 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 477:74] node _T_4244 = and(_T_4242, _T_4243) @[lsu_bus_buffer.scala 477:53] node _T_4245 = or(_T_4241, _T_4244) @[lsu_bus_buffer.scala 476:88] @@ -100617,19 +100617,19 @@ circuit quasar_wrapper : io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= WrPtr0_r @[lsu_bus_buffer.scala 533:47] node _T_4522 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 534:80] node _T_4523 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 534:127] - node _T_4524 = and(UInt<1>("h01"), _T_4523) @[lsu_bus_buffer.scala 534:116] + node _T_4524 = and(UInt<1>("h00"), _T_4523) @[lsu_bus_buffer.scala 534:116] node _T_4525 = eq(_T_4524, UInt<1>("h00")) @[lsu_bus_buffer.scala 534:95] node _T_4526 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 534:80] node _T_4527 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 534:127] - node _T_4528 = and(UInt<1>("h01"), _T_4527) @[lsu_bus_buffer.scala 534:116] + node _T_4528 = and(UInt<1>("h00"), _T_4527) @[lsu_bus_buffer.scala 534:116] node _T_4529 = eq(_T_4528, UInt<1>("h00")) @[lsu_bus_buffer.scala 534:95] node _T_4530 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 534:80] node _T_4531 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 534:127] - node _T_4532 = and(UInt<1>("h01"), _T_4531) @[lsu_bus_buffer.scala 534:116] + node _T_4532 = and(UInt<1>("h00"), _T_4531) @[lsu_bus_buffer.scala 534:116] node _T_4533 = eq(_T_4532, UInt<1>("h00")) @[lsu_bus_buffer.scala 534:95] node _T_4534 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 534:80] node _T_4535 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 534:127] - node _T_4536 = and(UInt<1>("h01"), _T_4535) @[lsu_bus_buffer.scala 534:116] + node _T_4536 = and(UInt<1>("h00"), _T_4535) @[lsu_bus_buffer.scala 534:116] node _T_4537 = eq(_T_4536, UInt<1>("h00")) @[lsu_bus_buffer.scala 534:95] node _T_4538 = mux(_T_4522, _T_4525, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4539 = mux(_T_4526, _T_4529, UInt<1>("h00")) @[Mux.scala 27:72] @@ -100917,7 +100917,7 @@ circuit quasar_wrapper : node _T_4799 = or(_T_4796, _T_4798) @[lsu_bus_buffer.scala 551:157] bus_sideeffect_pend <= _T_4799 @[lsu_bus_buffer.scala 551:23] node _T_4800 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:71] - node _T_4801 = and(UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 553:25] + node _T_4801 = and(UInt<1>("h00"), obuf_valid) @[lsu_bus_buffer.scala 553:25] node _T_4802 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 553:50] node _T_4803 = bits(buf_addr[0], 31, 3) @[lsu_bus_buffer.scala 553:70] node _T_4804 = eq(_T_4802, _T_4803) @[lsu_bus_buffer.scala 553:56] @@ -100929,7 +100929,7 @@ circuit quasar_wrapper : node _T_4810 = eq(_T_4809, UInt<1>("h00")) @[lsu_bus_buffer.scala 553:80] node _T_4811 = and(_T_4805, _T_4810) @[lsu_bus_buffer.scala 553:78] node _T_4812 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:71] - node _T_4813 = and(UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 553:25] + node _T_4813 = and(UInt<1>("h00"), obuf_valid) @[lsu_bus_buffer.scala 553:25] node _T_4814 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 553:50] node _T_4815 = bits(buf_addr[1], 31, 3) @[lsu_bus_buffer.scala 553:70] node _T_4816 = eq(_T_4814, _T_4815) @[lsu_bus_buffer.scala 553:56] @@ -100941,7 +100941,7 @@ circuit quasar_wrapper : node _T_4822 = eq(_T_4821, UInt<1>("h00")) @[lsu_bus_buffer.scala 553:80] node _T_4823 = and(_T_4817, _T_4822) @[lsu_bus_buffer.scala 553:78] node _T_4824 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:71] - node _T_4825 = and(UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 553:25] + node _T_4825 = and(UInt<1>("h00"), obuf_valid) @[lsu_bus_buffer.scala 553:25] node _T_4826 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 553:50] node _T_4827 = bits(buf_addr[2], 31, 3) @[lsu_bus_buffer.scala 553:70] node _T_4828 = eq(_T_4826, _T_4827) @[lsu_bus_buffer.scala 553:56] @@ -100953,7 +100953,7 @@ circuit quasar_wrapper : node _T_4834 = eq(_T_4833, UInt<1>("h00")) @[lsu_bus_buffer.scala 553:80] node _T_4835 = and(_T_4829, _T_4834) @[lsu_bus_buffer.scala 553:78] node _T_4836 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:71] - node _T_4837 = and(UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 553:25] + node _T_4837 = and(UInt<1>("h00"), obuf_valid) @[lsu_bus_buffer.scala 553:25] node _T_4838 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 553:50] node _T_4839 = bits(buf_addr[3], 31, 3) @[lsu_bus_buffer.scala 553:70] node _T_4840 = eq(_T_4838, _T_4839) @[lsu_bus_buffer.scala 553:56] @@ -114385,804 +114385,548 @@ circuit quasar_wrapper : io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 238:11] io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 238:11] io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 238:11] - when UInt<1>("h00") : @[quasar.scala 241:26] - inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 242:32] - axi4_to_ahb.clock <= clock - axi4_to_ahb.reset <= reset - inst axi4_to_ahb_1 of axi4_to_ahb_1 @[quasar.scala 243:33] - axi4_to_ahb_1.clock <= clock - axi4_to_ahb_1.reset <= reset - inst axi4_to_ahb_2 of axi4_to_ahb_2 @[quasar.scala 244:33] - axi4_to_ahb_2.clock <= clock - axi4_to_ahb_2.reset <= reset - inst ahb_to_axi4 of ahb_to_axi4 @[quasar.scala 245:33] - ahb_to_axi4.clock <= clock - ahb_to_axi4.reset <= reset - axi4_to_ahb_2.io.scan_mode <= io.scan_mode @[quasar.scala 247:34] - axi4_to_ahb_2.io.bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 248:35] - axi4_to_ahb_2.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 249:37] - lsu.io.axi.r.bits.last <= axi4_to_ahb_2.io.axi.r.bits.last @[quasar.scala 250:28] - lsu.io.axi.r.bits.resp <= axi4_to_ahb_2.io.axi.r.bits.resp @[quasar.scala 250:28] - lsu.io.axi.r.bits.data <= axi4_to_ahb_2.io.axi.r.bits.data @[quasar.scala 250:28] - lsu.io.axi.r.bits.id <= axi4_to_ahb_2.io.axi.r.bits.id @[quasar.scala 250:28] - lsu.io.axi.r.valid <= axi4_to_ahb_2.io.axi.r.valid @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 250:28] - lsu.io.axi.ar.ready <= axi4_to_ahb_2.io.axi.ar.ready @[quasar.scala 250:28] - lsu.io.axi.b.bits.id <= axi4_to_ahb_2.io.axi.b.bits.id @[quasar.scala 250:28] - lsu.io.axi.b.bits.resp <= axi4_to_ahb_2.io.axi.b.bits.resp @[quasar.scala 250:28] - lsu.io.axi.b.valid <= axi4_to_ahb_2.io.axi.b.valid @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 250:28] - lsu.io.axi.w.ready <= axi4_to_ahb_2.io.axi.w.ready @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 250:28] - axi4_to_ahb_2.io.axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 250:28] - lsu.io.axi.aw.ready <= axi4_to_ahb_2.io.axi.aw.ready @[quasar.scala 250:28] - io.lsu_ahb.out.hwdata <= axi4_to_ahb_2.io.ahb.out.hwdata @[quasar.scala 251:28] - io.lsu_ahb.out.hwrite <= axi4_to_ahb_2.io.ahb.out.hwrite @[quasar.scala 251:28] - io.lsu_ahb.out.htrans <= axi4_to_ahb_2.io.ahb.out.htrans @[quasar.scala 251:28] - io.lsu_ahb.out.hsize <= axi4_to_ahb_2.io.ahb.out.hsize @[quasar.scala 251:28] - io.lsu_ahb.out.hprot <= axi4_to_ahb_2.io.ahb.out.hprot @[quasar.scala 251:28] - io.lsu_ahb.out.hmastlock <= axi4_to_ahb_2.io.ahb.out.hmastlock @[quasar.scala 251:28] - io.lsu_ahb.out.hburst <= axi4_to_ahb_2.io.ahb.out.hburst @[quasar.scala 251:28] - io.lsu_ahb.out.haddr <= axi4_to_ahb_2.io.ahb.out.haddr @[quasar.scala 251:28] - axi4_to_ahb_2.io.ahb.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 251:28] - axi4_to_ahb_2.io.ahb.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 251:28] - axi4_to_ahb_2.io.ahb.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 251:28] - axi4_to_ahb_1.io.scan_mode <= io.scan_mode @[quasar.scala 254:34] - axi4_to_ahb_1.io.bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 255:35] - axi4_to_ahb_1.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 256:37] - ifu.io.ifu.r.bits.last <= axi4_to_ahb_1.io.axi.r.bits.last @[quasar.scala 257:28] - ifu.io.ifu.r.bits.resp <= axi4_to_ahb_1.io.axi.r.bits.resp @[quasar.scala 257:28] - ifu.io.ifu.r.bits.data <= axi4_to_ahb_1.io.axi.r.bits.data @[quasar.scala 257:28] - ifu.io.ifu.r.bits.id <= axi4_to_ahb_1.io.axi.r.bits.id @[quasar.scala 257:28] - ifu.io.ifu.r.valid <= axi4_to_ahb_1.io.axi.r.valid @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 257:28] - ifu.io.ifu.ar.ready <= axi4_to_ahb_1.io.axi.ar.ready @[quasar.scala 257:28] - ifu.io.ifu.b.bits.id <= axi4_to_ahb_1.io.axi.b.bits.id @[quasar.scala 257:28] - ifu.io.ifu.b.bits.resp <= axi4_to_ahb_1.io.axi.b.bits.resp @[quasar.scala 257:28] - ifu.io.ifu.b.valid <= axi4_to_ahb_1.io.axi.b.valid @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 257:28] - ifu.io.ifu.w.ready <= axi4_to_ahb_1.io.axi.w.ready @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 257:28] - axi4_to_ahb_1.io.axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 257:28] - ifu.io.ifu.aw.ready <= axi4_to_ahb_1.io.axi.aw.ready @[quasar.scala 257:28] - io.ifu_ahb.out.hwdata <= axi4_to_ahb_1.io.ahb.out.hwdata @[quasar.scala 258:28] - io.ifu_ahb.out.hwrite <= axi4_to_ahb_1.io.ahb.out.hwrite @[quasar.scala 258:28] - io.ifu_ahb.out.htrans <= axi4_to_ahb_1.io.ahb.out.htrans @[quasar.scala 258:28] - io.ifu_ahb.out.hsize <= axi4_to_ahb_1.io.ahb.out.hsize @[quasar.scala 258:28] - io.ifu_ahb.out.hprot <= axi4_to_ahb_1.io.ahb.out.hprot @[quasar.scala 258:28] - io.ifu_ahb.out.hmastlock <= axi4_to_ahb_1.io.ahb.out.hmastlock @[quasar.scala 258:28] - io.ifu_ahb.out.hburst <= axi4_to_ahb_1.io.ahb.out.hburst @[quasar.scala 258:28] - io.ifu_ahb.out.haddr <= axi4_to_ahb_1.io.ahb.out.haddr @[quasar.scala 258:28] - axi4_to_ahb_1.io.ahb.in.hresp <= io.ifu_ahb.in.hresp @[quasar.scala 258:28] - axi4_to_ahb_1.io.ahb.in.hready <= io.ifu_ahb.in.hready @[quasar.scala 258:28] - axi4_to_ahb_1.io.ahb.in.hrdata <= io.ifu_ahb.in.hrdata @[quasar.scala 258:28] - axi4_to_ahb.io.scan_mode <= io.scan_mode @[quasar.scala 260:33] - axi4_to_ahb.io.bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 261:34] - axi4_to_ahb.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 262:36] - dbg.io.sb_axi.r.bits.last <= axi4_to_ahb.io.axi.r.bits.last @[quasar.scala 263:27] - dbg.io.sb_axi.r.bits.resp <= axi4_to_ahb.io.axi.r.bits.resp @[quasar.scala 263:27] - dbg.io.sb_axi.r.bits.data <= axi4_to_ahb.io.axi.r.bits.data @[quasar.scala 263:27] - dbg.io.sb_axi.r.bits.id <= axi4_to_ahb.io.axi.r.bits.id @[quasar.scala 263:27] - dbg.io.sb_axi.r.valid <= axi4_to_ahb.io.axi.r.valid @[quasar.scala 263:27] - axi4_to_ahb.io.axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 263:27] - axi4_to_ahb.io.axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 263:27] - dbg.io.sb_axi.ar.ready <= axi4_to_ahb.io.axi.ar.ready @[quasar.scala 263:27] - dbg.io.sb_axi.b.bits.id <= axi4_to_ahb.io.axi.b.bits.id @[quasar.scala 263:27] - dbg.io.sb_axi.b.bits.resp <= axi4_to_ahb.io.axi.b.bits.resp @[quasar.scala 263:27] - dbg.io.sb_axi.b.valid <= axi4_to_ahb.io.axi.b.valid @[quasar.scala 263:27] - axi4_to_ahb.io.axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 263:27] - axi4_to_ahb.io.axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 263:27] - axi4_to_ahb.io.axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 263:27] - axi4_to_ahb.io.axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 263:27] - axi4_to_ahb.io.axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 263:27] - dbg.io.sb_axi.w.ready <= axi4_to_ahb.io.axi.w.ready @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 263:27] - axi4_to_ahb.io.axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 263:27] - dbg.io.sb_axi.aw.ready <= axi4_to_ahb.io.axi.aw.ready @[quasar.scala 263:27] - io.sb_ahb.out.hwdata <= axi4_to_ahb.io.ahb.out.hwdata @[quasar.scala 264:27] - io.sb_ahb.out.hwrite <= axi4_to_ahb.io.ahb.out.hwrite @[quasar.scala 264:27] - io.sb_ahb.out.htrans <= axi4_to_ahb.io.ahb.out.htrans @[quasar.scala 264:27] - io.sb_ahb.out.hsize <= axi4_to_ahb.io.ahb.out.hsize @[quasar.scala 264:27] - io.sb_ahb.out.hprot <= axi4_to_ahb.io.ahb.out.hprot @[quasar.scala 264:27] - io.sb_ahb.out.hmastlock <= axi4_to_ahb.io.ahb.out.hmastlock @[quasar.scala 264:27] - io.sb_ahb.out.hburst <= axi4_to_ahb.io.ahb.out.hburst @[quasar.scala 264:27] - io.sb_ahb.out.haddr <= axi4_to_ahb.io.ahb.out.haddr @[quasar.scala 264:27] - axi4_to_ahb.io.ahb.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 264:27] - axi4_to_ahb.io.ahb.in.hready <= io.sb_ahb.in.hready @[quasar.scala 264:27] - axi4_to_ahb.io.ahb.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 264:27] - ahb_to_axi4.io.scan_mode <= io.scan_mode @[quasar.scala 266:34] - ahb_to_axi4.io.bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 267:35] - ahb_to_axi4.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 268:37] - ahb_to_axi4.io.axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 269:28] - ahb_to_axi4.io.axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 269:28] - ahb_to_axi4.io.axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 269:28] - ahb_to_axi4.io.axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 269:28] - ahb_to_axi4.io.axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.r.ready <= ahb_to_axi4.io.axi.r.ready @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.qos <= ahb_to_axi4.io.axi.ar.bits.qos @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.prot <= ahb_to_axi4.io.axi.ar.bits.prot @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.cache <= ahb_to_axi4.io.axi.ar.bits.cache @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.lock <= ahb_to_axi4.io.axi.ar.bits.lock @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.burst <= ahb_to_axi4.io.axi.ar.bits.burst @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.size <= ahb_to_axi4.io.axi.ar.bits.size @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.len <= ahb_to_axi4.io.axi.ar.bits.len @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.region <= ahb_to_axi4.io.axi.ar.bits.region @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.addr <= ahb_to_axi4.io.axi.ar.bits.addr @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.bits.id <= ahb_to_axi4.io.axi.ar.bits.id @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.ar.valid <= ahb_to_axi4.io.axi.ar.valid @[quasar.scala 269:28] - ahb_to_axi4.io.axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 269:28] - ahb_to_axi4.io.axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 269:28] - ahb_to_axi4.io.axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 269:28] - ahb_to_axi4.io.axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.b.ready <= ahb_to_axi4.io.axi.b.ready @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.w.bits.last <= ahb_to_axi4.io.axi.w.bits.last @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.w.bits.strb <= ahb_to_axi4.io.axi.w.bits.strb @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.w.bits.data <= ahb_to_axi4.io.axi.w.bits.data @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.w.valid <= ahb_to_axi4.io.axi.w.valid @[quasar.scala 269:28] - ahb_to_axi4.io.axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.qos <= ahb_to_axi4.io.axi.aw.bits.qos @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.prot <= ahb_to_axi4.io.axi.aw.bits.prot @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.cache <= ahb_to_axi4.io.axi.aw.bits.cache @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.lock <= ahb_to_axi4.io.axi.aw.bits.lock @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.burst <= ahb_to_axi4.io.axi.aw.bits.burst @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.size <= ahb_to_axi4.io.axi.aw.bits.size @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.len <= ahb_to_axi4.io.axi.aw.bits.len @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.region <= ahb_to_axi4.io.axi.aw.bits.region @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.addr <= ahb_to_axi4.io.axi.aw.bits.addr @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.bits.id <= ahb_to_axi4.io.axi.aw.bits.id @[quasar.scala 269:28] - dma_ctrl.io.dma_axi.aw.valid <= ahb_to_axi4.io.axi.aw.valid @[quasar.scala 269:28] - ahb_to_axi4.io.axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 269:28] - ahb_to_axi4.io.ahb.hreadyin <= io.dma_ahb.hreadyin @[quasar.scala 270:28] - ahb_to_axi4.io.ahb.hsel <= io.dma_ahb.hsel @[quasar.scala 270:28] - ahb_to_axi4.io.ahb.sig.out.hwdata <= io.dma_ahb.sig.out.hwdata @[quasar.scala 270:28] - ahb_to_axi4.io.ahb.sig.out.hwrite <= io.dma_ahb.sig.out.hwrite @[quasar.scala 270:28] - ahb_to_axi4.io.ahb.sig.out.htrans <= io.dma_ahb.sig.out.htrans @[quasar.scala 270:28] - ahb_to_axi4.io.ahb.sig.out.hsize <= io.dma_ahb.sig.out.hsize @[quasar.scala 270:28] - ahb_to_axi4.io.ahb.sig.out.hprot <= io.dma_ahb.sig.out.hprot @[quasar.scala 270:28] - ahb_to_axi4.io.ahb.sig.out.hmastlock <= io.dma_ahb.sig.out.hmastlock @[quasar.scala 270:28] - ahb_to_axi4.io.ahb.sig.out.hburst <= io.dma_ahb.sig.out.hburst @[quasar.scala 270:28] - ahb_to_axi4.io.ahb.sig.out.haddr <= io.dma_ahb.sig.out.haddr @[quasar.scala 270:28] - io.dma_ahb.sig.in.hresp <= ahb_to_axi4.io.ahb.sig.in.hresp @[quasar.scala 270:28] - io.dma_ahb.sig.in.hready <= ahb_to_axi4.io.ahb.sig.in.hready @[quasar.scala 270:28] - io.dma_ahb.sig.in.hrdata <= ahb_to_axi4.io.ahb.sig.in.hrdata @[quasar.scala 270:28] - wire _T_12 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 272:31] - _T_12.r.bits.last <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.r.bits.resp <= UInt<2>("h00") @[quasar.scala 272:31] - _T_12.r.bits.data <= UInt<64>("h00") @[quasar.scala 272:31] - _T_12.r.bits.id <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.r.valid <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.r.ready <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.size <= UInt<3>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.len <= UInt<8>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.region <= UInt<4>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 272:31] - _T_12.ar.bits.id <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.ar.valid <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.ar.ready <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.b.bits.id <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.b.bits.resp <= UInt<2>("h00") @[quasar.scala 272:31] - _T_12.b.valid <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.b.ready <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.w.bits.last <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.w.bits.strb <= UInt<8>("h00") @[quasar.scala 272:31] - _T_12.w.bits.data <= UInt<64>("h00") @[quasar.scala 272:31] - _T_12.w.valid <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.w.ready <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.size <= UInt<3>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.len <= UInt<8>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.region <= UInt<4>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 272:31] - _T_12.aw.bits.id <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.aw.valid <= UInt<1>("h00") @[quasar.scala 272:31] - _T_12.aw.ready <= UInt<1>("h00") @[quasar.scala 272:31] - io.dma_axi.r.bits.last <= _T_12.r.bits.last @[quasar.scala 272:16] - io.dma_axi.r.bits.resp <= _T_12.r.bits.resp @[quasar.scala 272:16] - io.dma_axi.r.bits.data <= _T_12.r.bits.data @[quasar.scala 272:16] - io.dma_axi.r.bits.id <= _T_12.r.bits.id @[quasar.scala 272:16] - io.dma_axi.r.valid <= _T_12.r.valid @[quasar.scala 272:16] - _T_12.r.ready <= io.dma_axi.r.ready @[quasar.scala 272:16] - _T_12.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 272:16] - _T_12.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 272:16] - _T_12.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 272:16] - _T_12.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 272:16] - _T_12.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 272:16] - _T_12.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 272:16] - _T_12.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 272:16] - _T_12.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 272:16] - _T_12.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 272:16] - _T_12.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 272:16] - _T_12.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 272:16] - io.dma_axi.ar.ready <= _T_12.ar.ready @[quasar.scala 272:16] - io.dma_axi.b.bits.id <= _T_12.b.bits.id @[quasar.scala 272:16] - io.dma_axi.b.bits.resp <= _T_12.b.bits.resp @[quasar.scala 272:16] - io.dma_axi.b.valid <= _T_12.b.valid @[quasar.scala 272:16] - _T_12.b.ready <= io.dma_axi.b.ready @[quasar.scala 272:16] - _T_12.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 272:16] - _T_12.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 272:16] - _T_12.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 272:16] - _T_12.w.valid <= io.dma_axi.w.valid @[quasar.scala 272:16] - io.dma_axi.w.ready <= _T_12.w.ready @[quasar.scala 272:16] - _T_12.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 272:16] - _T_12.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 272:16] - _T_12.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 272:16] - _T_12.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 272:16] - _T_12.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 272:16] - _T_12.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 272:16] - _T_12.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 272:16] - _T_12.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 272:16] - _T_12.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 272:16] - _T_12.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 272:16] - _T_12.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 272:16] - io.dma_axi.aw.ready <= _T_12.aw.ready @[quasar.scala 272:16] - wire _T_13 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 273:36] - _T_13.r.bits.last <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.r.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36] - _T_13.r.bits.data <= UInt<64>("h00") @[quasar.scala 273:36] - _T_13.r.bits.id <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.r.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.r.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.size <= UInt<3>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.len <= UInt<8>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.region <= UInt<4>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36] - _T_13.ar.bits.id <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.ar.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.ar.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.b.bits.id <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.b.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36] - _T_13.b.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.b.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.w.bits.last <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.w.bits.strb <= UInt<8>("h00") @[quasar.scala 273:36] - _T_13.w.bits.data <= UInt<64>("h00") @[quasar.scala 273:36] - _T_13.w.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.w.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.size <= UInt<3>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.len <= UInt<8>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.region <= UInt<4>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36] - _T_13.aw.bits.id <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.aw.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.aw.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_13.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 273:21] - _T_13.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 273:21] - _T_13.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 273:21] - _T_13.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 273:21] - _T_13.r.valid <= io.sb_axi.r.valid @[quasar.scala 273:21] - io.sb_axi.r.ready <= _T_13.r.ready @[quasar.scala 273:21] - io.sb_axi.ar.bits.qos <= _T_13.ar.bits.qos @[quasar.scala 273:21] - io.sb_axi.ar.bits.prot <= _T_13.ar.bits.prot @[quasar.scala 273:21] - io.sb_axi.ar.bits.cache <= _T_13.ar.bits.cache @[quasar.scala 273:21] - io.sb_axi.ar.bits.lock <= _T_13.ar.bits.lock @[quasar.scala 273:21] - io.sb_axi.ar.bits.burst <= _T_13.ar.bits.burst @[quasar.scala 273:21] - io.sb_axi.ar.bits.size <= _T_13.ar.bits.size @[quasar.scala 273:21] - io.sb_axi.ar.bits.len <= _T_13.ar.bits.len @[quasar.scala 273:21] - io.sb_axi.ar.bits.region <= _T_13.ar.bits.region @[quasar.scala 273:21] - io.sb_axi.ar.bits.addr <= _T_13.ar.bits.addr @[quasar.scala 273:21] - io.sb_axi.ar.bits.id <= _T_13.ar.bits.id @[quasar.scala 273:21] - io.sb_axi.ar.valid <= _T_13.ar.valid @[quasar.scala 273:21] - _T_13.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 273:21] - _T_13.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 273:21] - _T_13.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 273:21] - _T_13.b.valid <= io.sb_axi.b.valid @[quasar.scala 273:21] - io.sb_axi.b.ready <= _T_13.b.ready @[quasar.scala 273:21] - io.sb_axi.w.bits.last <= _T_13.w.bits.last @[quasar.scala 273:21] - io.sb_axi.w.bits.strb <= _T_13.w.bits.strb @[quasar.scala 273:21] - io.sb_axi.w.bits.data <= _T_13.w.bits.data @[quasar.scala 273:21] - io.sb_axi.w.valid <= _T_13.w.valid @[quasar.scala 273:21] - _T_13.w.ready <= io.sb_axi.w.ready @[quasar.scala 273:21] - io.sb_axi.aw.bits.qos <= _T_13.aw.bits.qos @[quasar.scala 273:21] - io.sb_axi.aw.bits.prot <= _T_13.aw.bits.prot @[quasar.scala 273:21] - io.sb_axi.aw.bits.cache <= _T_13.aw.bits.cache @[quasar.scala 273:21] - io.sb_axi.aw.bits.lock <= _T_13.aw.bits.lock @[quasar.scala 273:21] - io.sb_axi.aw.bits.burst <= _T_13.aw.bits.burst @[quasar.scala 273:21] - io.sb_axi.aw.bits.size <= _T_13.aw.bits.size @[quasar.scala 273:21] - io.sb_axi.aw.bits.len <= _T_13.aw.bits.len @[quasar.scala 273:21] - io.sb_axi.aw.bits.region <= _T_13.aw.bits.region @[quasar.scala 273:21] - io.sb_axi.aw.bits.addr <= _T_13.aw.bits.addr @[quasar.scala 273:21] - io.sb_axi.aw.bits.id <= _T_13.aw.bits.id @[quasar.scala 273:21] - io.sb_axi.aw.valid <= _T_13.aw.valid @[quasar.scala 273:21] - _T_13.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 273:21] - wire _T_14 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 274:40] - _T_14.r.bits.last <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.r.bits.resp <= UInt<2>("h00") @[quasar.scala 274:40] - _T_14.r.bits.data <= UInt<64>("h00") @[quasar.scala 274:40] - _T_14.r.bits.id <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.r.valid <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.r.ready <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.size <= UInt<3>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.len <= UInt<8>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.region <= UInt<4>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 274:40] - _T_14.ar.bits.id <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.ar.valid <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.ar.ready <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.b.bits.id <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.b.bits.resp <= UInt<2>("h00") @[quasar.scala 274:40] - _T_14.b.valid <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.b.ready <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.w.bits.last <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.w.bits.strb <= UInt<8>("h00") @[quasar.scala 274:40] - _T_14.w.bits.data <= UInt<64>("h00") @[quasar.scala 274:40] - _T_14.w.valid <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.w.ready <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.size <= UInt<3>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.len <= UInt<8>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.region <= UInt<4>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 274:40] - _T_14.aw.bits.id <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.aw.valid <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.aw.ready <= UInt<1>("h00") @[quasar.scala 274:40] - _T_14.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 274:25] - _T_14.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 274:25] - _T_14.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 274:25] - _T_14.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 274:25] - _T_14.r.valid <= io.ifu_axi.r.valid @[quasar.scala 274:25] - io.ifu_axi.r.ready <= _T_14.r.ready @[quasar.scala 274:25] - io.ifu_axi.ar.bits.qos <= _T_14.ar.bits.qos @[quasar.scala 274:25] - io.ifu_axi.ar.bits.prot <= _T_14.ar.bits.prot @[quasar.scala 274:25] - io.ifu_axi.ar.bits.cache <= _T_14.ar.bits.cache @[quasar.scala 274:25] - io.ifu_axi.ar.bits.lock <= _T_14.ar.bits.lock @[quasar.scala 274:25] - io.ifu_axi.ar.bits.burst <= _T_14.ar.bits.burst @[quasar.scala 274:25] - io.ifu_axi.ar.bits.size <= _T_14.ar.bits.size @[quasar.scala 274:25] - io.ifu_axi.ar.bits.len <= _T_14.ar.bits.len @[quasar.scala 274:25] - io.ifu_axi.ar.bits.region <= _T_14.ar.bits.region @[quasar.scala 274:25] - io.ifu_axi.ar.bits.addr <= _T_14.ar.bits.addr @[quasar.scala 274:25] - io.ifu_axi.ar.bits.id <= _T_14.ar.bits.id @[quasar.scala 274:25] - io.ifu_axi.ar.valid <= _T_14.ar.valid @[quasar.scala 274:25] - _T_14.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 274:25] - _T_14.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 274:25] - _T_14.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 274:25] - _T_14.b.valid <= io.ifu_axi.b.valid @[quasar.scala 274:25] - io.ifu_axi.b.ready <= _T_14.b.ready @[quasar.scala 274:25] - io.ifu_axi.w.bits.last <= _T_14.w.bits.last @[quasar.scala 274:25] - io.ifu_axi.w.bits.strb <= _T_14.w.bits.strb @[quasar.scala 274:25] - io.ifu_axi.w.bits.data <= _T_14.w.bits.data @[quasar.scala 274:25] - io.ifu_axi.w.valid <= _T_14.w.valid @[quasar.scala 274:25] - _T_14.w.ready <= io.ifu_axi.w.ready @[quasar.scala 274:25] - io.ifu_axi.aw.bits.qos <= _T_14.aw.bits.qos @[quasar.scala 274:25] - io.ifu_axi.aw.bits.prot <= _T_14.aw.bits.prot @[quasar.scala 274:25] - io.ifu_axi.aw.bits.cache <= _T_14.aw.bits.cache @[quasar.scala 274:25] - io.ifu_axi.aw.bits.lock <= _T_14.aw.bits.lock @[quasar.scala 274:25] - io.ifu_axi.aw.bits.burst <= _T_14.aw.bits.burst @[quasar.scala 274:25] - io.ifu_axi.aw.bits.size <= _T_14.aw.bits.size @[quasar.scala 274:25] - io.ifu_axi.aw.bits.len <= _T_14.aw.bits.len @[quasar.scala 274:25] - io.ifu_axi.aw.bits.region <= _T_14.aw.bits.region @[quasar.scala 274:25] - io.ifu_axi.aw.bits.addr <= _T_14.aw.bits.addr @[quasar.scala 274:25] - io.ifu_axi.aw.bits.id <= _T_14.aw.bits.id @[quasar.scala 274:25] - io.ifu_axi.aw.valid <= _T_14.aw.valid @[quasar.scala 274:25] - _T_14.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 274:25] - wire _T_15 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 275:40] - _T_15.r.bits.last <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.r.bits.resp <= UInt<2>("h00") @[quasar.scala 275:40] - _T_15.r.bits.data <= UInt<64>("h00") @[quasar.scala 275:40] - _T_15.r.bits.id <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.r.valid <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.r.ready <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.size <= UInt<3>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.len <= UInt<8>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.region <= UInt<4>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 275:40] - _T_15.ar.bits.id <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.ar.valid <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.ar.ready <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.b.bits.id <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.b.bits.resp <= UInt<2>("h00") @[quasar.scala 275:40] - _T_15.b.valid <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.b.ready <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.w.bits.last <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.w.bits.strb <= UInt<8>("h00") @[quasar.scala 275:40] - _T_15.w.bits.data <= UInt<64>("h00") @[quasar.scala 275:40] - _T_15.w.valid <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.w.ready <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.size <= UInt<3>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.len <= UInt<8>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.region <= UInt<4>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 275:40] - _T_15.aw.bits.id <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.aw.valid <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.aw.ready <= UInt<1>("h00") @[quasar.scala 275:40] - _T_15.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 275:25] - _T_15.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 275:25] - _T_15.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 275:25] - _T_15.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 275:25] - _T_15.r.valid <= io.lsu_axi.r.valid @[quasar.scala 275:25] - io.lsu_axi.r.ready <= _T_15.r.ready @[quasar.scala 275:25] - io.lsu_axi.ar.bits.qos <= _T_15.ar.bits.qos @[quasar.scala 275:25] - io.lsu_axi.ar.bits.prot <= _T_15.ar.bits.prot @[quasar.scala 275:25] - io.lsu_axi.ar.bits.cache <= _T_15.ar.bits.cache @[quasar.scala 275:25] - io.lsu_axi.ar.bits.lock <= _T_15.ar.bits.lock @[quasar.scala 275:25] - io.lsu_axi.ar.bits.burst <= _T_15.ar.bits.burst @[quasar.scala 275:25] - io.lsu_axi.ar.bits.size <= _T_15.ar.bits.size @[quasar.scala 275:25] - io.lsu_axi.ar.bits.len <= _T_15.ar.bits.len @[quasar.scala 275:25] - io.lsu_axi.ar.bits.region <= _T_15.ar.bits.region @[quasar.scala 275:25] - io.lsu_axi.ar.bits.addr <= _T_15.ar.bits.addr @[quasar.scala 275:25] - io.lsu_axi.ar.bits.id <= _T_15.ar.bits.id @[quasar.scala 275:25] - io.lsu_axi.ar.valid <= _T_15.ar.valid @[quasar.scala 275:25] - _T_15.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 275:25] - _T_15.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 275:25] - _T_15.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 275:25] - _T_15.b.valid <= io.lsu_axi.b.valid @[quasar.scala 275:25] - io.lsu_axi.b.ready <= _T_15.b.ready @[quasar.scala 275:25] - io.lsu_axi.w.bits.last <= _T_15.w.bits.last @[quasar.scala 275:25] - io.lsu_axi.w.bits.strb <= _T_15.w.bits.strb @[quasar.scala 275:25] - io.lsu_axi.w.bits.data <= _T_15.w.bits.data @[quasar.scala 275:25] - io.lsu_axi.w.valid <= _T_15.w.valid @[quasar.scala 275:25] - _T_15.w.ready <= io.lsu_axi.w.ready @[quasar.scala 275:25] - io.lsu_axi.aw.bits.qos <= _T_15.aw.bits.qos @[quasar.scala 275:25] - io.lsu_axi.aw.bits.prot <= _T_15.aw.bits.prot @[quasar.scala 275:25] - io.lsu_axi.aw.bits.cache <= _T_15.aw.bits.cache @[quasar.scala 275:25] - io.lsu_axi.aw.bits.lock <= _T_15.aw.bits.lock @[quasar.scala 275:25] - io.lsu_axi.aw.bits.burst <= _T_15.aw.bits.burst @[quasar.scala 275:25] - io.lsu_axi.aw.bits.size <= _T_15.aw.bits.size @[quasar.scala 275:25] - io.lsu_axi.aw.bits.len <= _T_15.aw.bits.len @[quasar.scala 275:25] - io.lsu_axi.aw.bits.region <= _T_15.aw.bits.region @[quasar.scala 275:25] - io.lsu_axi.aw.bits.addr <= _T_15.aw.bits.addr @[quasar.scala 275:25] - io.lsu_axi.aw.bits.id <= _T_15.aw.bits.id @[quasar.scala 275:25] - io.lsu_axi.aw.valid <= _T_15.aw.valid @[quasar.scala 275:25] - _T_15.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 275:25] - skip @[quasar.scala 241:26] - else : @[quasar.scala 277:15] - wire _T_16 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 278:33] - _T_16.out.hwdata <= UInt<64>("h00") @[quasar.scala 278:33] - _T_16.out.hwrite <= UInt<1>("h00") @[quasar.scala 278:33] - _T_16.out.htrans <= UInt<2>("h00") @[quasar.scala 278:33] - _T_16.out.hsize <= UInt<3>("h00") @[quasar.scala 278:33] - _T_16.out.hprot <= UInt<4>("h00") @[quasar.scala 278:33] - _T_16.out.hmastlock <= UInt<1>("h00") @[quasar.scala 278:33] - _T_16.out.hburst <= UInt<3>("h00") @[quasar.scala 278:33] - _T_16.out.haddr <= UInt<32>("h00") @[quasar.scala 278:33] - _T_16.in.hresp <= UInt<1>("h00") @[quasar.scala 278:33] - _T_16.in.hready <= UInt<1>("h00") @[quasar.scala 278:33] - _T_16.in.hrdata <= UInt<64>("h00") @[quasar.scala 278:33] - io.lsu_ahb.out.hwdata <= _T_16.out.hwdata @[quasar.scala 278:18] - io.lsu_ahb.out.hwrite <= _T_16.out.hwrite @[quasar.scala 278:18] - io.lsu_ahb.out.htrans <= _T_16.out.htrans @[quasar.scala 278:18] - io.lsu_ahb.out.hsize <= _T_16.out.hsize @[quasar.scala 278:18] - io.lsu_ahb.out.hprot <= _T_16.out.hprot @[quasar.scala 278:18] - io.lsu_ahb.out.hmastlock <= _T_16.out.hmastlock @[quasar.scala 278:18] - io.lsu_ahb.out.hburst <= _T_16.out.hburst @[quasar.scala 278:18] - io.lsu_ahb.out.haddr <= _T_16.out.haddr @[quasar.scala 278:18] - _T_16.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 278:18] - _T_16.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 278:18] - _T_16.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 278:18] - wire _T_17 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 279:33] - _T_17.out.hwdata <= UInt<64>("h00") @[quasar.scala 279:33] - _T_17.out.hwrite <= UInt<1>("h00") @[quasar.scala 279:33] - _T_17.out.htrans <= UInt<2>("h00") @[quasar.scala 279:33] - _T_17.out.hsize <= UInt<3>("h00") @[quasar.scala 279:33] - _T_17.out.hprot <= UInt<4>("h00") @[quasar.scala 279:33] - _T_17.out.hmastlock <= UInt<1>("h00") @[quasar.scala 279:33] - _T_17.out.hburst <= UInt<3>("h00") @[quasar.scala 279:33] - _T_17.out.haddr <= UInt<32>("h00") @[quasar.scala 279:33] - _T_17.in.hresp <= UInt<1>("h00") @[quasar.scala 279:33] - _T_17.in.hready <= UInt<1>("h00") @[quasar.scala 279:33] - _T_17.in.hrdata <= UInt<64>("h00") @[quasar.scala 279:33] - io.ifu_ahb.out.hwdata <= _T_17.out.hwdata @[quasar.scala 279:18] - io.ifu_ahb.out.hwrite <= _T_17.out.hwrite @[quasar.scala 279:18] - io.ifu_ahb.out.htrans <= _T_17.out.htrans @[quasar.scala 279:18] - io.ifu_ahb.out.hsize <= _T_17.out.hsize @[quasar.scala 279:18] - io.ifu_ahb.out.hprot <= _T_17.out.hprot @[quasar.scala 279:18] - io.ifu_ahb.out.hmastlock <= _T_17.out.hmastlock @[quasar.scala 279:18] - io.ifu_ahb.out.hburst <= _T_17.out.hburst @[quasar.scala 279:18] - io.ifu_ahb.out.haddr <= _T_17.out.haddr @[quasar.scala 279:18] - _T_17.in.hresp <= io.ifu_ahb.in.hresp @[quasar.scala 279:18] - _T_17.in.hready <= io.ifu_ahb.in.hready @[quasar.scala 279:18] - _T_17.in.hrdata <= io.ifu_ahb.in.hrdata @[quasar.scala 279:18] - wire _T_18 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 280:32] - _T_18.out.hwdata <= UInt<64>("h00") @[quasar.scala 280:32] - _T_18.out.hwrite <= UInt<1>("h00") @[quasar.scala 280:32] - _T_18.out.htrans <= UInt<2>("h00") @[quasar.scala 280:32] - _T_18.out.hsize <= UInt<3>("h00") @[quasar.scala 280:32] - _T_18.out.hprot <= UInt<4>("h00") @[quasar.scala 280:32] - _T_18.out.hmastlock <= UInt<1>("h00") @[quasar.scala 280:32] - _T_18.out.hburst <= UInt<3>("h00") @[quasar.scala 280:32] - _T_18.out.haddr <= UInt<32>("h00") @[quasar.scala 280:32] - _T_18.in.hresp <= UInt<1>("h00") @[quasar.scala 280:32] - _T_18.in.hready <= UInt<1>("h00") @[quasar.scala 280:32] - _T_18.in.hrdata <= UInt<64>("h00") @[quasar.scala 280:32] - io.sb_ahb.out.hwdata <= _T_18.out.hwdata @[quasar.scala 280:17] - io.sb_ahb.out.hwrite <= _T_18.out.hwrite @[quasar.scala 280:17] - io.sb_ahb.out.htrans <= _T_18.out.htrans @[quasar.scala 280:17] - io.sb_ahb.out.hsize <= _T_18.out.hsize @[quasar.scala 280:17] - io.sb_ahb.out.hprot <= _T_18.out.hprot @[quasar.scala 280:17] - io.sb_ahb.out.hmastlock <= _T_18.out.hmastlock @[quasar.scala 280:17] - io.sb_ahb.out.hburst <= _T_18.out.hburst @[quasar.scala 280:17] - io.sb_ahb.out.haddr <= _T_18.out.haddr @[quasar.scala 280:17] - _T_18.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 280:17] - _T_18.in.hready <= io.sb_ahb.in.hready @[quasar.scala 280:17] - _T_18.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 280:17] - wire _T_19 : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>} @[quasar.scala 281:33] - _T_19.hreadyin <= UInt<1>("h00") @[quasar.scala 281:33] - _T_19.hsel <= UInt<1>("h00") @[quasar.scala 281:33] - _T_19.sig.out.hwdata <= UInt<64>("h00") @[quasar.scala 281:33] - _T_19.sig.out.hwrite <= UInt<1>("h00") @[quasar.scala 281:33] - _T_19.sig.out.htrans <= UInt<2>("h00") @[quasar.scala 281:33] - _T_19.sig.out.hsize <= UInt<3>("h00") @[quasar.scala 281:33] - _T_19.sig.out.hprot <= UInt<4>("h00") @[quasar.scala 281:33] - _T_19.sig.out.hmastlock <= UInt<1>("h00") @[quasar.scala 281:33] - _T_19.sig.out.hburst <= UInt<3>("h00") @[quasar.scala 281:33] - _T_19.sig.out.haddr <= UInt<32>("h00") @[quasar.scala 281:33] - _T_19.sig.in.hresp <= UInt<1>("h00") @[quasar.scala 281:33] - _T_19.sig.in.hready <= UInt<1>("h00") @[quasar.scala 281:33] - _T_19.sig.in.hrdata <= UInt<64>("h00") @[quasar.scala 281:33] - _T_19.hreadyin <= io.dma_ahb.hreadyin @[quasar.scala 281:18] - _T_19.hsel <= io.dma_ahb.hsel @[quasar.scala 281:18] - _T_19.sig.out.hwdata <= io.dma_ahb.sig.out.hwdata @[quasar.scala 281:18] - _T_19.sig.out.hwrite <= io.dma_ahb.sig.out.hwrite @[quasar.scala 281:18] - _T_19.sig.out.htrans <= io.dma_ahb.sig.out.htrans @[quasar.scala 281:18] - _T_19.sig.out.hsize <= io.dma_ahb.sig.out.hsize @[quasar.scala 281:18] - _T_19.sig.out.hprot <= io.dma_ahb.sig.out.hprot @[quasar.scala 281:18] - _T_19.sig.out.hmastlock <= io.dma_ahb.sig.out.hmastlock @[quasar.scala 281:18] - _T_19.sig.out.hburst <= io.dma_ahb.sig.out.hburst @[quasar.scala 281:18] - _T_19.sig.out.haddr <= io.dma_ahb.sig.out.haddr @[quasar.scala 281:18] - io.dma_ahb.sig.in.hresp <= _T_19.sig.in.hresp @[quasar.scala 281:18] - io.dma_ahb.sig.in.hready <= _T_19.sig.in.hready @[quasar.scala 281:18] - io.dma_ahb.sig.in.hrdata <= _T_19.sig.in.hrdata @[quasar.scala 281:18] - io.dma_axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 282:27] - io.dma_axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 282:27] - io.dma_axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 282:27] - io.dma_axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 282:27] - io.dma_axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 282:27] - io.dma_axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 282:27] - io.dma_axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 282:27] - io.dma_axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 282:27] - io.dma_axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar.scala 282:27] - io.dma_axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 282:27] - io.dma_axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 282:27] - dbg.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 283:27] - dbg.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 283:27] - dbg.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 283:27] - dbg.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 283:27] - dbg.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar.scala 283:27] - io.sb_axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 283:27] - io.sb_axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 283:27] - io.sb_axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 283:27] - io.sb_axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 283:27] - io.sb_axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 283:27] - io.sb_axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 283:27] - io.sb_axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 283:27] - io.sb_axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 283:27] - io.sb_axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 283:27] - io.sb_axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 283:27] - io.sb_axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 283:27] - io.sb_axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 283:27] - dbg.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 283:27] - dbg.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 283:27] - dbg.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 283:27] - dbg.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar.scala 283:27] - io.sb_axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 283:27] - io.sb_axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 283:27] - io.sb_axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 283:27] - io.sb_axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 283:27] - io.sb_axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 283:27] - dbg.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar.scala 283:27] - io.sb_axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 283:27] - io.sb_axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 283:27] - io.sb_axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 283:27] - io.sb_axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 283:27] - io.sb_axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 283:27] - io.sb_axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 283:27] - io.sb_axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 283:27] - io.sb_axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 283:27] - io.sb_axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 283:27] - io.sb_axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 283:27] - io.sb_axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 283:27] - dbg.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 283:27] - ifu.io.ifu.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 284:27] - ifu.io.ifu.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 284:27] - ifu.io.ifu.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 284:27] - ifu.io.ifu.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 284:27] - ifu.io.ifu.r.valid <= io.ifu_axi.r.valid @[quasar.scala 284:27] - io.ifu_axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 284:27] - io.ifu_axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 284:27] - io.ifu_axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 284:27] - io.ifu_axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 284:27] - io.ifu_axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 284:27] - io.ifu_axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 284:27] - io.ifu_axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 284:27] - io.ifu_axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 284:27] - io.ifu_axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 284:27] - io.ifu_axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 284:27] - io.ifu_axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 284:27] - io.ifu_axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 284:27] - ifu.io.ifu.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 284:27] - ifu.io.ifu.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 284:27] - ifu.io.ifu.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 284:27] - ifu.io.ifu.b.valid <= io.ifu_axi.b.valid @[quasar.scala 284:27] - io.ifu_axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 284:27] - io.ifu_axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 284:27] - io.ifu_axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 284:27] - io.ifu_axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 284:27] - io.ifu_axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 284:27] - ifu.io.ifu.w.ready <= io.ifu_axi.w.ready @[quasar.scala 284:27] - io.ifu_axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 284:27] - io.ifu_axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 284:27] - io.ifu_axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 284:27] - io.ifu_axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 284:27] - io.ifu_axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 284:27] - io.ifu_axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 284:27] - io.ifu_axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 284:27] - io.ifu_axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 284:27] - io.ifu_axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 284:27] - io.ifu_axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 284:27] - io.ifu_axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 284:27] - ifu.io.ifu.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 284:27] - lsu.io.axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 285:27] - lsu.io.axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 285:27] - lsu.io.axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 285:27] - lsu.io.axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 285:27] - lsu.io.axi.r.valid <= io.lsu_axi.r.valid @[quasar.scala 285:27] - io.lsu_axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 285:27] - io.lsu_axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 285:27] - io.lsu_axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 285:27] - io.lsu_axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 285:27] - io.lsu_axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 285:27] - io.lsu_axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 285:27] - io.lsu_axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 285:27] - io.lsu_axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 285:27] - io.lsu_axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 285:27] - io.lsu_axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 285:27] - io.lsu_axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 285:27] - io.lsu_axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 285:27] - lsu.io.axi.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 285:27] - lsu.io.axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 285:27] - lsu.io.axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 285:27] - lsu.io.axi.b.valid <= io.lsu_axi.b.valid @[quasar.scala 285:27] - io.lsu_axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 285:27] - io.lsu_axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 285:27] - io.lsu_axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 285:27] - io.lsu_axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 285:27] - io.lsu_axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 285:27] - lsu.io.axi.w.ready <= io.lsu_axi.w.ready @[quasar.scala 285:27] - io.lsu_axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 285:27] - io.lsu_axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 285:27] - io.lsu_axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 285:27] - io.lsu_axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 285:27] - io.lsu_axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 285:27] - io.lsu_axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 285:27] - io.lsu_axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 285:27] - io.lsu_axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 285:27] - io.lsu_axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 285:27] - io.lsu_axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 285:27] - io.lsu_axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 285:27] - lsu.io.axi.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 285:27] - skip @[quasar.scala 277:15] + inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 242:32] + axi4_to_ahb.clock <= clock + axi4_to_ahb.reset <= reset + inst axi4_to_ahb_1 of axi4_to_ahb_1 @[quasar.scala 243:33] + axi4_to_ahb_1.clock <= clock + axi4_to_ahb_1.reset <= reset + inst axi4_to_ahb_2 of axi4_to_ahb_2 @[quasar.scala 244:33] + axi4_to_ahb_2.clock <= clock + axi4_to_ahb_2.reset <= reset + inst ahb_to_axi4 of ahb_to_axi4 @[quasar.scala 245:33] + ahb_to_axi4.clock <= clock + ahb_to_axi4.reset <= reset + axi4_to_ahb_2.io.scan_mode <= io.scan_mode @[quasar.scala 247:34] + axi4_to_ahb_2.io.bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 248:35] + axi4_to_ahb_2.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 249:37] + lsu.io.axi.r.bits.last <= axi4_to_ahb_2.io.axi.r.bits.last @[quasar.scala 250:28] + lsu.io.axi.r.bits.resp <= axi4_to_ahb_2.io.axi.r.bits.resp @[quasar.scala 250:28] + lsu.io.axi.r.bits.data <= axi4_to_ahb_2.io.axi.r.bits.data @[quasar.scala 250:28] + lsu.io.axi.r.bits.id <= axi4_to_ahb_2.io.axi.r.bits.id @[quasar.scala 250:28] + lsu.io.axi.r.valid <= axi4_to_ahb_2.io.axi.r.valid @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 250:28] + lsu.io.axi.ar.ready <= axi4_to_ahb_2.io.axi.ar.ready @[quasar.scala 250:28] + lsu.io.axi.b.bits.id <= axi4_to_ahb_2.io.axi.b.bits.id @[quasar.scala 250:28] + lsu.io.axi.b.bits.resp <= axi4_to_ahb_2.io.axi.b.bits.resp @[quasar.scala 250:28] + lsu.io.axi.b.valid <= axi4_to_ahb_2.io.axi.b.valid @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 250:28] + lsu.io.axi.w.ready <= axi4_to_ahb_2.io.axi.w.ready @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 250:28] + lsu.io.axi.aw.ready <= axi4_to_ahb_2.io.axi.aw.ready @[quasar.scala 250:28] + io.lsu_ahb.out.hwdata <= axi4_to_ahb_2.io.ahb.out.hwdata @[quasar.scala 251:28] + io.lsu_ahb.out.hwrite <= axi4_to_ahb_2.io.ahb.out.hwrite @[quasar.scala 251:28] + io.lsu_ahb.out.htrans <= axi4_to_ahb_2.io.ahb.out.htrans @[quasar.scala 251:28] + io.lsu_ahb.out.hsize <= axi4_to_ahb_2.io.ahb.out.hsize @[quasar.scala 251:28] + io.lsu_ahb.out.hprot <= axi4_to_ahb_2.io.ahb.out.hprot @[quasar.scala 251:28] + io.lsu_ahb.out.hmastlock <= axi4_to_ahb_2.io.ahb.out.hmastlock @[quasar.scala 251:28] + io.lsu_ahb.out.hburst <= axi4_to_ahb_2.io.ahb.out.hburst @[quasar.scala 251:28] + io.lsu_ahb.out.haddr <= axi4_to_ahb_2.io.ahb.out.haddr @[quasar.scala 251:28] + axi4_to_ahb_2.io.ahb.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 251:28] + axi4_to_ahb_2.io.ahb.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 251:28] + axi4_to_ahb_2.io.ahb.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 251:28] + axi4_to_ahb_1.io.scan_mode <= io.scan_mode @[quasar.scala 254:34] + axi4_to_ahb_1.io.bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 255:35] + axi4_to_ahb_1.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 256:37] + ifu.io.ifu.r.bits.last <= axi4_to_ahb_1.io.axi.r.bits.last @[quasar.scala 257:28] + ifu.io.ifu.r.bits.resp <= axi4_to_ahb_1.io.axi.r.bits.resp @[quasar.scala 257:28] + ifu.io.ifu.r.bits.data <= axi4_to_ahb_1.io.axi.r.bits.data @[quasar.scala 257:28] + ifu.io.ifu.r.bits.id <= axi4_to_ahb_1.io.axi.r.bits.id @[quasar.scala 257:28] + ifu.io.ifu.r.valid <= axi4_to_ahb_1.io.axi.r.valid @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 257:28] + ifu.io.ifu.ar.ready <= axi4_to_ahb_1.io.axi.ar.ready @[quasar.scala 257:28] + ifu.io.ifu.b.bits.id <= axi4_to_ahb_1.io.axi.b.bits.id @[quasar.scala 257:28] + ifu.io.ifu.b.bits.resp <= axi4_to_ahb_1.io.axi.b.bits.resp @[quasar.scala 257:28] + ifu.io.ifu.b.valid <= axi4_to_ahb_1.io.axi.b.valid @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 257:28] + ifu.io.ifu.w.ready <= axi4_to_ahb_1.io.axi.w.ready @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 257:28] + ifu.io.ifu.aw.ready <= axi4_to_ahb_1.io.axi.aw.ready @[quasar.scala 257:28] + io.ifu_ahb.out.hwdata <= axi4_to_ahb_1.io.ahb.out.hwdata @[quasar.scala 258:28] + io.ifu_ahb.out.hwrite <= axi4_to_ahb_1.io.ahb.out.hwrite @[quasar.scala 258:28] + io.ifu_ahb.out.htrans <= axi4_to_ahb_1.io.ahb.out.htrans @[quasar.scala 258:28] + io.ifu_ahb.out.hsize <= axi4_to_ahb_1.io.ahb.out.hsize @[quasar.scala 258:28] + io.ifu_ahb.out.hprot <= axi4_to_ahb_1.io.ahb.out.hprot @[quasar.scala 258:28] + io.ifu_ahb.out.hmastlock <= axi4_to_ahb_1.io.ahb.out.hmastlock @[quasar.scala 258:28] + io.ifu_ahb.out.hburst <= axi4_to_ahb_1.io.ahb.out.hburst @[quasar.scala 258:28] + io.ifu_ahb.out.haddr <= axi4_to_ahb_1.io.ahb.out.haddr @[quasar.scala 258:28] + axi4_to_ahb_1.io.ahb.in.hresp <= io.ifu_ahb.in.hresp @[quasar.scala 258:28] + axi4_to_ahb_1.io.ahb.in.hready <= io.ifu_ahb.in.hready @[quasar.scala 258:28] + axi4_to_ahb_1.io.ahb.in.hrdata <= io.ifu_ahb.in.hrdata @[quasar.scala 258:28] + axi4_to_ahb.io.scan_mode <= io.scan_mode @[quasar.scala 260:33] + axi4_to_ahb.io.bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 261:34] + axi4_to_ahb.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 262:36] + dbg.io.sb_axi.r.bits.last <= axi4_to_ahb.io.axi.r.bits.last @[quasar.scala 263:27] + dbg.io.sb_axi.r.bits.resp <= axi4_to_ahb.io.axi.r.bits.resp @[quasar.scala 263:27] + dbg.io.sb_axi.r.bits.data <= axi4_to_ahb.io.axi.r.bits.data @[quasar.scala 263:27] + dbg.io.sb_axi.r.bits.id <= axi4_to_ahb.io.axi.r.bits.id @[quasar.scala 263:27] + dbg.io.sb_axi.r.valid <= axi4_to_ahb.io.axi.r.valid @[quasar.scala 263:27] + axi4_to_ahb.io.axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 263:27] + dbg.io.sb_axi.ar.ready <= axi4_to_ahb.io.axi.ar.ready @[quasar.scala 263:27] + dbg.io.sb_axi.b.bits.id <= axi4_to_ahb.io.axi.b.bits.id @[quasar.scala 263:27] + dbg.io.sb_axi.b.bits.resp <= axi4_to_ahb.io.axi.b.bits.resp @[quasar.scala 263:27] + dbg.io.sb_axi.b.valid <= axi4_to_ahb.io.axi.b.valid @[quasar.scala 263:27] + axi4_to_ahb.io.axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 263:27] + axi4_to_ahb.io.axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 263:27] + axi4_to_ahb.io.axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 263:27] + axi4_to_ahb.io.axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 263:27] + axi4_to_ahb.io.axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 263:27] + dbg.io.sb_axi.w.ready <= axi4_to_ahb.io.axi.w.ready @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 263:27] + dbg.io.sb_axi.aw.ready <= axi4_to_ahb.io.axi.aw.ready @[quasar.scala 263:27] + io.sb_ahb.out.hwdata <= axi4_to_ahb.io.ahb.out.hwdata @[quasar.scala 264:27] + io.sb_ahb.out.hwrite <= axi4_to_ahb.io.ahb.out.hwrite @[quasar.scala 264:27] + io.sb_ahb.out.htrans <= axi4_to_ahb.io.ahb.out.htrans @[quasar.scala 264:27] + io.sb_ahb.out.hsize <= axi4_to_ahb.io.ahb.out.hsize @[quasar.scala 264:27] + io.sb_ahb.out.hprot <= axi4_to_ahb.io.ahb.out.hprot @[quasar.scala 264:27] + io.sb_ahb.out.hmastlock <= axi4_to_ahb.io.ahb.out.hmastlock @[quasar.scala 264:27] + io.sb_ahb.out.hburst <= axi4_to_ahb.io.ahb.out.hburst @[quasar.scala 264:27] + io.sb_ahb.out.haddr <= axi4_to_ahb.io.ahb.out.haddr @[quasar.scala 264:27] + axi4_to_ahb.io.ahb.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 264:27] + axi4_to_ahb.io.ahb.in.hready <= io.sb_ahb.in.hready @[quasar.scala 264:27] + axi4_to_ahb.io.ahb.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 264:27] + ahb_to_axi4.io.scan_mode <= io.scan_mode @[quasar.scala 266:34] + ahb_to_axi4.io.bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 267:35] + ahb_to_axi4.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 268:37] + ahb_to_axi4.io.axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 269:28] + ahb_to_axi4.io.axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 269:28] + ahb_to_axi4.io.axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 269:28] + ahb_to_axi4.io.axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 269:28] + ahb_to_axi4.io.axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.r.ready <= ahb_to_axi4.io.axi.r.ready @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.qos <= ahb_to_axi4.io.axi.ar.bits.qos @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.prot <= ahb_to_axi4.io.axi.ar.bits.prot @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.cache <= ahb_to_axi4.io.axi.ar.bits.cache @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.lock <= ahb_to_axi4.io.axi.ar.bits.lock @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.burst <= ahb_to_axi4.io.axi.ar.bits.burst @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.size <= ahb_to_axi4.io.axi.ar.bits.size @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.len <= ahb_to_axi4.io.axi.ar.bits.len @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.region <= ahb_to_axi4.io.axi.ar.bits.region @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.addr <= ahb_to_axi4.io.axi.ar.bits.addr @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.id <= ahb_to_axi4.io.axi.ar.bits.id @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.valid <= ahb_to_axi4.io.axi.ar.valid @[quasar.scala 269:28] + ahb_to_axi4.io.axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 269:28] + ahb_to_axi4.io.axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 269:28] + ahb_to_axi4.io.axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 269:28] + ahb_to_axi4.io.axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.b.ready <= ahb_to_axi4.io.axi.b.ready @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.w.bits.last <= ahb_to_axi4.io.axi.w.bits.last @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.w.bits.strb <= ahb_to_axi4.io.axi.w.bits.strb @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.w.bits.data <= ahb_to_axi4.io.axi.w.bits.data @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.w.valid <= ahb_to_axi4.io.axi.w.valid @[quasar.scala 269:28] + ahb_to_axi4.io.axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.qos <= ahb_to_axi4.io.axi.aw.bits.qos @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.prot <= ahb_to_axi4.io.axi.aw.bits.prot @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.cache <= ahb_to_axi4.io.axi.aw.bits.cache @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.lock <= ahb_to_axi4.io.axi.aw.bits.lock @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.burst <= ahb_to_axi4.io.axi.aw.bits.burst @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.size <= ahb_to_axi4.io.axi.aw.bits.size @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.len <= ahb_to_axi4.io.axi.aw.bits.len @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.region <= ahb_to_axi4.io.axi.aw.bits.region @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.addr <= ahb_to_axi4.io.axi.aw.bits.addr @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.id <= ahb_to_axi4.io.axi.aw.bits.id @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.valid <= ahb_to_axi4.io.axi.aw.valid @[quasar.scala 269:28] + ahb_to_axi4.io.axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 269:28] + ahb_to_axi4.io.ahb.hreadyin <= io.dma_ahb.hreadyin @[quasar.scala 270:28] + ahb_to_axi4.io.ahb.hsel <= io.dma_ahb.hsel @[quasar.scala 270:28] + ahb_to_axi4.io.ahb.sig.out.hwdata <= io.dma_ahb.sig.out.hwdata @[quasar.scala 270:28] + ahb_to_axi4.io.ahb.sig.out.hwrite <= io.dma_ahb.sig.out.hwrite @[quasar.scala 270:28] + ahb_to_axi4.io.ahb.sig.out.htrans <= io.dma_ahb.sig.out.htrans @[quasar.scala 270:28] + ahb_to_axi4.io.ahb.sig.out.hsize <= io.dma_ahb.sig.out.hsize @[quasar.scala 270:28] + ahb_to_axi4.io.ahb.sig.out.hprot <= io.dma_ahb.sig.out.hprot @[quasar.scala 270:28] + ahb_to_axi4.io.ahb.sig.out.hmastlock <= io.dma_ahb.sig.out.hmastlock @[quasar.scala 270:28] + ahb_to_axi4.io.ahb.sig.out.hburst <= io.dma_ahb.sig.out.hburst @[quasar.scala 270:28] + ahb_to_axi4.io.ahb.sig.out.haddr <= io.dma_ahb.sig.out.haddr @[quasar.scala 270:28] + io.dma_ahb.sig.in.hresp <= ahb_to_axi4.io.ahb.sig.in.hresp @[quasar.scala 270:28] + io.dma_ahb.sig.in.hready <= ahb_to_axi4.io.ahb.sig.in.hready @[quasar.scala 270:28] + io.dma_ahb.sig.in.hrdata <= ahb_to_axi4.io.ahb.sig.in.hrdata @[quasar.scala 270:28] + wire _T_12 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 272:31] + _T_12.r.bits.last <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.r.bits.resp <= UInt<2>("h00") @[quasar.scala 272:31] + _T_12.r.bits.data <= UInt<64>("h00") @[quasar.scala 272:31] + _T_12.r.bits.id <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.r.valid <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.r.ready <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.size <= UInt<3>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.len <= UInt<8>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.region <= UInt<4>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.id <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.ar.valid <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.ar.ready <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.b.bits.id <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.b.bits.resp <= UInt<2>("h00") @[quasar.scala 272:31] + _T_12.b.valid <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.b.ready <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.w.bits.last <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.w.bits.strb <= UInt<8>("h00") @[quasar.scala 272:31] + _T_12.w.bits.data <= UInt<64>("h00") @[quasar.scala 272:31] + _T_12.w.valid <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.w.ready <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.size <= UInt<3>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.len <= UInt<8>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.region <= UInt<4>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.id <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.aw.valid <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.aw.ready <= UInt<1>("h00") @[quasar.scala 272:31] + io.dma_axi.r.bits.last <= _T_12.r.bits.last @[quasar.scala 272:16] + io.dma_axi.r.bits.resp <= _T_12.r.bits.resp @[quasar.scala 272:16] + io.dma_axi.r.bits.data <= _T_12.r.bits.data @[quasar.scala 272:16] + io.dma_axi.r.bits.id <= _T_12.r.bits.id @[quasar.scala 272:16] + io.dma_axi.r.valid <= _T_12.r.valid @[quasar.scala 272:16] + _T_12.r.ready <= io.dma_axi.r.ready @[quasar.scala 272:16] + _T_12.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 272:16] + _T_12.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 272:16] + _T_12.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 272:16] + _T_12.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 272:16] + _T_12.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 272:16] + _T_12.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 272:16] + _T_12.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 272:16] + _T_12.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 272:16] + _T_12.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 272:16] + _T_12.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 272:16] + _T_12.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 272:16] + io.dma_axi.ar.ready <= _T_12.ar.ready @[quasar.scala 272:16] + io.dma_axi.b.bits.id <= _T_12.b.bits.id @[quasar.scala 272:16] + io.dma_axi.b.bits.resp <= _T_12.b.bits.resp @[quasar.scala 272:16] + io.dma_axi.b.valid <= _T_12.b.valid @[quasar.scala 272:16] + _T_12.b.ready <= io.dma_axi.b.ready @[quasar.scala 272:16] + _T_12.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 272:16] + _T_12.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 272:16] + _T_12.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 272:16] + _T_12.w.valid <= io.dma_axi.w.valid @[quasar.scala 272:16] + io.dma_axi.w.ready <= _T_12.w.ready @[quasar.scala 272:16] + _T_12.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 272:16] + _T_12.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 272:16] + _T_12.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 272:16] + _T_12.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 272:16] + _T_12.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 272:16] + _T_12.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 272:16] + _T_12.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 272:16] + _T_12.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 272:16] + _T_12.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 272:16] + _T_12.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 272:16] + _T_12.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 272:16] + io.dma_axi.aw.ready <= _T_12.aw.ready @[quasar.scala 272:16] + wire _T_13 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 273:36] + _T_13.r.bits.last <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.r.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36] + _T_13.r.bits.data <= UInt<64>("h00") @[quasar.scala 273:36] + _T_13.r.bits.id <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.r.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.r.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.size <= UInt<3>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.len <= UInt<8>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.region <= UInt<4>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.id <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.ar.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.ar.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.b.bits.id <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.b.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36] + _T_13.b.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.b.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.w.bits.last <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.w.bits.strb <= UInt<8>("h00") @[quasar.scala 273:36] + _T_13.w.bits.data <= UInt<64>("h00") @[quasar.scala 273:36] + _T_13.w.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.w.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.size <= UInt<3>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.len <= UInt<8>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.region <= UInt<4>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.id <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.aw.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.aw.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 273:21] + _T_13.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 273:21] + _T_13.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 273:21] + _T_13.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 273:21] + _T_13.r.valid <= io.sb_axi.r.valid @[quasar.scala 273:21] + io.sb_axi.r.ready <= _T_13.r.ready @[quasar.scala 273:21] + io.sb_axi.ar.bits.qos <= _T_13.ar.bits.qos @[quasar.scala 273:21] + io.sb_axi.ar.bits.prot <= _T_13.ar.bits.prot @[quasar.scala 273:21] + io.sb_axi.ar.bits.cache <= _T_13.ar.bits.cache @[quasar.scala 273:21] + io.sb_axi.ar.bits.lock <= _T_13.ar.bits.lock @[quasar.scala 273:21] + io.sb_axi.ar.bits.burst <= _T_13.ar.bits.burst @[quasar.scala 273:21] + io.sb_axi.ar.bits.size <= _T_13.ar.bits.size @[quasar.scala 273:21] + io.sb_axi.ar.bits.len <= _T_13.ar.bits.len @[quasar.scala 273:21] + io.sb_axi.ar.bits.region <= _T_13.ar.bits.region @[quasar.scala 273:21] + io.sb_axi.ar.bits.addr <= _T_13.ar.bits.addr @[quasar.scala 273:21] + io.sb_axi.ar.bits.id <= _T_13.ar.bits.id @[quasar.scala 273:21] + io.sb_axi.ar.valid <= _T_13.ar.valid @[quasar.scala 273:21] + _T_13.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 273:21] + _T_13.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 273:21] + _T_13.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 273:21] + _T_13.b.valid <= io.sb_axi.b.valid @[quasar.scala 273:21] + io.sb_axi.b.ready <= _T_13.b.ready @[quasar.scala 273:21] + io.sb_axi.w.bits.last <= _T_13.w.bits.last @[quasar.scala 273:21] + io.sb_axi.w.bits.strb <= _T_13.w.bits.strb @[quasar.scala 273:21] + io.sb_axi.w.bits.data <= _T_13.w.bits.data @[quasar.scala 273:21] + io.sb_axi.w.valid <= _T_13.w.valid @[quasar.scala 273:21] + _T_13.w.ready <= io.sb_axi.w.ready @[quasar.scala 273:21] + io.sb_axi.aw.bits.qos <= _T_13.aw.bits.qos @[quasar.scala 273:21] + io.sb_axi.aw.bits.prot <= _T_13.aw.bits.prot @[quasar.scala 273:21] + io.sb_axi.aw.bits.cache <= _T_13.aw.bits.cache @[quasar.scala 273:21] + io.sb_axi.aw.bits.lock <= _T_13.aw.bits.lock @[quasar.scala 273:21] + io.sb_axi.aw.bits.burst <= _T_13.aw.bits.burst @[quasar.scala 273:21] + io.sb_axi.aw.bits.size <= _T_13.aw.bits.size @[quasar.scala 273:21] + io.sb_axi.aw.bits.len <= _T_13.aw.bits.len @[quasar.scala 273:21] + io.sb_axi.aw.bits.region <= _T_13.aw.bits.region @[quasar.scala 273:21] + io.sb_axi.aw.bits.addr <= _T_13.aw.bits.addr @[quasar.scala 273:21] + io.sb_axi.aw.bits.id <= _T_13.aw.bits.id @[quasar.scala 273:21] + io.sb_axi.aw.valid <= _T_13.aw.valid @[quasar.scala 273:21] + _T_13.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 273:21] + wire _T_14 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 274:40] + _T_14.r.bits.last <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.r.bits.resp <= UInt<2>("h00") @[quasar.scala 274:40] + _T_14.r.bits.data <= UInt<64>("h00") @[quasar.scala 274:40] + _T_14.r.bits.id <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.r.valid <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.r.ready <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.size <= UInt<3>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.len <= UInt<8>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.region <= UInt<4>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.id <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.ar.valid <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.ar.ready <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.b.bits.id <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.b.bits.resp <= UInt<2>("h00") @[quasar.scala 274:40] + _T_14.b.valid <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.b.ready <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.w.bits.last <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.w.bits.strb <= UInt<8>("h00") @[quasar.scala 274:40] + _T_14.w.bits.data <= UInt<64>("h00") @[quasar.scala 274:40] + _T_14.w.valid <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.w.ready <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.size <= UInt<3>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.len <= UInt<8>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.region <= UInt<4>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.id <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.aw.valid <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.aw.ready <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 274:25] + _T_14.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 274:25] + _T_14.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 274:25] + _T_14.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 274:25] + _T_14.r.valid <= io.ifu_axi.r.valid @[quasar.scala 274:25] + io.ifu_axi.r.ready <= _T_14.r.ready @[quasar.scala 274:25] + io.ifu_axi.ar.bits.qos <= _T_14.ar.bits.qos @[quasar.scala 274:25] + io.ifu_axi.ar.bits.prot <= _T_14.ar.bits.prot @[quasar.scala 274:25] + io.ifu_axi.ar.bits.cache <= _T_14.ar.bits.cache @[quasar.scala 274:25] + io.ifu_axi.ar.bits.lock <= _T_14.ar.bits.lock @[quasar.scala 274:25] + io.ifu_axi.ar.bits.burst <= _T_14.ar.bits.burst @[quasar.scala 274:25] + io.ifu_axi.ar.bits.size <= _T_14.ar.bits.size @[quasar.scala 274:25] + io.ifu_axi.ar.bits.len <= _T_14.ar.bits.len @[quasar.scala 274:25] + io.ifu_axi.ar.bits.region <= _T_14.ar.bits.region @[quasar.scala 274:25] + io.ifu_axi.ar.bits.addr <= _T_14.ar.bits.addr @[quasar.scala 274:25] + io.ifu_axi.ar.bits.id <= _T_14.ar.bits.id @[quasar.scala 274:25] + io.ifu_axi.ar.valid <= _T_14.ar.valid @[quasar.scala 274:25] + _T_14.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 274:25] + _T_14.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 274:25] + _T_14.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 274:25] + _T_14.b.valid <= io.ifu_axi.b.valid @[quasar.scala 274:25] + io.ifu_axi.b.ready <= _T_14.b.ready @[quasar.scala 274:25] + io.ifu_axi.w.bits.last <= _T_14.w.bits.last @[quasar.scala 274:25] + io.ifu_axi.w.bits.strb <= _T_14.w.bits.strb @[quasar.scala 274:25] + io.ifu_axi.w.bits.data <= _T_14.w.bits.data @[quasar.scala 274:25] + io.ifu_axi.w.valid <= _T_14.w.valid @[quasar.scala 274:25] + _T_14.w.ready <= io.ifu_axi.w.ready @[quasar.scala 274:25] + io.ifu_axi.aw.bits.qos <= _T_14.aw.bits.qos @[quasar.scala 274:25] + io.ifu_axi.aw.bits.prot <= _T_14.aw.bits.prot @[quasar.scala 274:25] + io.ifu_axi.aw.bits.cache <= _T_14.aw.bits.cache @[quasar.scala 274:25] + io.ifu_axi.aw.bits.lock <= _T_14.aw.bits.lock @[quasar.scala 274:25] + io.ifu_axi.aw.bits.burst <= _T_14.aw.bits.burst @[quasar.scala 274:25] + io.ifu_axi.aw.bits.size <= _T_14.aw.bits.size @[quasar.scala 274:25] + io.ifu_axi.aw.bits.len <= _T_14.aw.bits.len @[quasar.scala 274:25] + io.ifu_axi.aw.bits.region <= _T_14.aw.bits.region @[quasar.scala 274:25] + io.ifu_axi.aw.bits.addr <= _T_14.aw.bits.addr @[quasar.scala 274:25] + io.ifu_axi.aw.bits.id <= _T_14.aw.bits.id @[quasar.scala 274:25] + io.ifu_axi.aw.valid <= _T_14.aw.valid @[quasar.scala 274:25] + _T_14.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 274:25] + wire _T_15 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 275:40] + _T_15.r.bits.last <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.r.bits.resp <= UInt<2>("h00") @[quasar.scala 275:40] + _T_15.r.bits.data <= UInt<64>("h00") @[quasar.scala 275:40] + _T_15.r.bits.id <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.r.valid <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.r.ready <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.size <= UInt<3>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.len <= UInt<8>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.region <= UInt<4>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.id <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.ar.valid <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.ar.ready <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.b.bits.id <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.b.bits.resp <= UInt<2>("h00") @[quasar.scala 275:40] + _T_15.b.valid <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.b.ready <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.w.bits.last <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.w.bits.strb <= UInt<8>("h00") @[quasar.scala 275:40] + _T_15.w.bits.data <= UInt<64>("h00") @[quasar.scala 275:40] + _T_15.w.valid <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.w.ready <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.size <= UInt<3>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.len <= UInt<8>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.region <= UInt<4>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.id <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.aw.valid <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.aw.ready <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 275:25] + _T_15.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 275:25] + _T_15.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 275:25] + _T_15.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 275:25] + _T_15.r.valid <= io.lsu_axi.r.valid @[quasar.scala 275:25] + io.lsu_axi.r.ready <= _T_15.r.ready @[quasar.scala 275:25] + io.lsu_axi.ar.bits.qos <= _T_15.ar.bits.qos @[quasar.scala 275:25] + io.lsu_axi.ar.bits.prot <= _T_15.ar.bits.prot @[quasar.scala 275:25] + io.lsu_axi.ar.bits.cache <= _T_15.ar.bits.cache @[quasar.scala 275:25] + io.lsu_axi.ar.bits.lock <= _T_15.ar.bits.lock @[quasar.scala 275:25] + io.lsu_axi.ar.bits.burst <= _T_15.ar.bits.burst @[quasar.scala 275:25] + io.lsu_axi.ar.bits.size <= _T_15.ar.bits.size @[quasar.scala 275:25] + io.lsu_axi.ar.bits.len <= _T_15.ar.bits.len @[quasar.scala 275:25] + io.lsu_axi.ar.bits.region <= _T_15.ar.bits.region @[quasar.scala 275:25] + io.lsu_axi.ar.bits.addr <= _T_15.ar.bits.addr @[quasar.scala 275:25] + io.lsu_axi.ar.bits.id <= _T_15.ar.bits.id @[quasar.scala 275:25] + io.lsu_axi.ar.valid <= _T_15.ar.valid @[quasar.scala 275:25] + _T_15.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 275:25] + _T_15.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 275:25] + _T_15.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 275:25] + _T_15.b.valid <= io.lsu_axi.b.valid @[quasar.scala 275:25] + io.lsu_axi.b.ready <= _T_15.b.ready @[quasar.scala 275:25] + io.lsu_axi.w.bits.last <= _T_15.w.bits.last @[quasar.scala 275:25] + io.lsu_axi.w.bits.strb <= _T_15.w.bits.strb @[quasar.scala 275:25] + io.lsu_axi.w.bits.data <= _T_15.w.bits.data @[quasar.scala 275:25] + io.lsu_axi.w.valid <= _T_15.w.valid @[quasar.scala 275:25] + _T_15.w.ready <= io.lsu_axi.w.ready @[quasar.scala 275:25] + io.lsu_axi.aw.bits.qos <= _T_15.aw.bits.qos @[quasar.scala 275:25] + io.lsu_axi.aw.bits.prot <= _T_15.aw.bits.prot @[quasar.scala 275:25] + io.lsu_axi.aw.bits.cache <= _T_15.aw.bits.cache @[quasar.scala 275:25] + io.lsu_axi.aw.bits.lock <= _T_15.aw.bits.lock @[quasar.scala 275:25] + io.lsu_axi.aw.bits.burst <= _T_15.aw.bits.burst @[quasar.scala 275:25] + io.lsu_axi.aw.bits.size <= _T_15.aw.bits.size @[quasar.scala 275:25] + io.lsu_axi.aw.bits.len <= _T_15.aw.bits.len @[quasar.scala 275:25] + io.lsu_axi.aw.bits.region <= _T_15.aw.bits.region @[quasar.scala 275:25] + io.lsu_axi.aw.bits.addr <= _T_15.aw.bits.addr @[quasar.scala 275:25] + io.lsu_axi.aw.bits.id <= _T_15.aw.bits.id @[quasar.scala 275:25] + io.lsu_axi.aw.valid <= _T_15.aw.valid @[quasar.scala 275:25] + _T_15.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 275:25] io.dmi_reg_rdata <= UInt<1>("h00") @[quasar.scala 287:20] module quasar_wrapper : diff --git a/quasar_wrapper.v b/quasar_wrapper.v index 83b0c187..1b4055c2 100644 --- a/quasar_wrapper.v +++ b/quasar_wrapper.v @@ -56,8 +56,6 @@ module ifu_mem_ctl( input io_ifu_axi_ar_ready, output io_ifu_axi_ar_valid, output [2:0] io_ifu_axi_ar_bits_id, - output [31:0] io_ifu_axi_ar_bits_addr, - output [3:0] io_ifu_axi_ar_bits_region, output io_ifu_axi_r_ready, input io_ifu_axi_r_valid, input [2:0] io_ifu_axi_r_bits_id, @@ -283,8 +281,8 @@ module ifu_mem_ctl( reg [31:0] _RAND_160; reg [31:0] _RAND_161; reg [31:0] _RAND_162; - reg [31:0] _RAND_163; - reg [63:0] _RAND_164; + reg [63:0] _RAND_163; + reg [31:0] _RAND_164; reg [31:0] _RAND_165; reg [31:0] _RAND_166; reg [31:0] _RAND_167; @@ -561,8 +559,8 @@ module ifu_mem_ctl( reg [31:0] _RAND_438; reg [31:0] _RAND_439; reg [31:0] _RAND_440; - reg [31:0] _RAND_441; - reg [95:0] _RAND_442; + reg [95:0] _RAND_441; + reg [31:0] _RAND_442; reg [31:0] _RAND_443; reg [31:0] _RAND_444; reg [31:0] _RAND_445; @@ -571,14 +569,14 @@ module ifu_mem_ctl( reg [31:0] _RAND_448; reg [31:0] _RAND_449; reg [31:0] _RAND_450; - reg [31:0] _RAND_451; - reg [63:0] _RAND_452; + reg [63:0] _RAND_451; + reg [31:0] _RAND_452; reg [31:0] _RAND_453; reg [31:0] _RAND_454; reg [31:0] _RAND_455; reg [31:0] _RAND_456; - reg [31:0] _RAND_457; - reg [63:0] _RAND_458; + reg [63:0] _RAND_457; + reg [31:0] _RAND_458; reg [31:0] _RAND_459; reg [31:0] _RAND_460; reg [31:0] _RAND_461; @@ -592,7 +590,6 @@ module ifu_mem_ctl( reg [31:0] _RAND_469; reg [31:0] _RAND_470; reg [31:0] _RAND_471; - reg [31:0] _RAND_472; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] wire rvclkhdr_io_clk; // @[lib.scala 343:22] @@ -1918,7 +1915,6 @@ module ifu_mem_ctl( wire _T_299 = reset_all_tags | reset_ic_ff; // @[ifu_mem_ctl.scala 211:72] wire reset_ic_in = _T_298 & _T_299; // @[ifu_mem_ctl.scala 211:53] reg fetch_uncacheable_ff; // @[ifu_mem_ctl.scala 213:62] - reg [25:0] miss_addr; // @[ifu_mem_ctl.scala 222:48] wire _T_309 = io_ifu_bus_clk_en | ic_act_miss_f; // @[ifu_mem_ctl.scala 221:57] wire _T_315 = _T_2283 & flush_final_f; // @[ifu_mem_ctl.scala 226:87] wire _T_316 = ~_T_315; // @[ifu_mem_ctl.scala 226:55] @@ -1929,7 +1925,6 @@ module ifu_mem_ctl( wire _T_318 = ~stream_miss_f; // @[ifu_mem_ctl.scala 226:106] reg ifc_region_acc_fault_f; // @[ifu_mem_ctl.scala 232:68] reg [2:0] bus_rd_addr_count; // @[ifu_mem_ctl.scala 540:55] - wire [28:0] ifu_ic_req_addr_f = {miss_addr,bus_rd_addr_count}; // @[Cat.scala 29:58] wire _T_325 = _T_239 | _T_2268; // @[ifu_mem_ctl.scala 234:55] wire _T_328 = _T_325 & _T_56; // @[ifu_mem_ctl.scala 234:82] wire _T_2289 = ~ifu_bus_rid_ff[0]; // @[ifu_mem_ctl.scala 378:55] @@ -3415,8 +3410,6 @@ module ifu_mem_ctl( wire _T_2603 = ~bus_cmd_sent; // @[ifu_mem_ctl.scala 474:61] wire _T_2604 = _T_2591 & _T_2603; // @[ifu_mem_ctl.scala 474:59] wire [2:0] _T_2608 = ifu_bus_cmd_valid ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_2610 = {miss_addr,bus_rd_addr_count,3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2612 = ifu_bus_cmd_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] reg ifu_bus_arready_unq_ff; // @[ifu_mem_ctl.scala 509:57] reg ifu_bus_arvalid_ff; // @[ifu_mem_ctl.scala 511:53] wire ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 523:51] @@ -5661,8 +5654,6 @@ module ifu_mem_ctl( assign io_dec_mem_ctrl_ifu_miss_state_idle = miss_state == 3'h0; // @[ifu_mem_ctl.scala 235:39] assign io_ifu_axi_ar_valid = ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 497:23] assign io_ifu_axi_ar_bits_id = bus_rd_addr_count & _T_2608; // @[ifu_mem_ctl.scala 498:25] - assign io_ifu_axi_ar_bits_addr = _T_2610 & _T_2612; // @[ifu_mem_ctl.scala 499:27] - assign io_ifu_axi_ar_bits_region = ifu_ic_req_addr_f[28:25]; // @[ifu_mem_ctl.scala 502:29] assign io_ifu_axi_r_ready = 1'h1; // @[ifu_mem_ctl.scala 504:22] assign io_iccm_rw_addr = _T_3110 ? io_dma_mem_ctl_dma_mem_addr[15:1] : _T_3117; // @[ifu_mem_ctl.scala 599:19] assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2497; // @[ifu_mem_ctl.scala 395:27] @@ -6339,631 +6330,629 @@ initial begin _RAND_159 = {1{`RANDOM}}; fetch_uncacheable_ff = _RAND_159[0:0]; _RAND_160 = {1{`RANDOM}}; - miss_addr = _RAND_160[25:0]; + ifc_region_acc_fault_f = _RAND_160[0:0]; _RAND_161 = {1{`RANDOM}}; - ifc_region_acc_fault_f = _RAND_161[0:0]; + bus_rd_addr_count = _RAND_161[2:0]; _RAND_162 = {1{`RANDOM}}; - bus_rd_addr_count = _RAND_162[2:0]; - _RAND_163 = {1{`RANDOM}}; - ic_act_miss_f_delayed = _RAND_163[0:0]; - _RAND_164 = {2{`RANDOM}}; - ifu_bus_rdata_ff = _RAND_164[63:0]; + ic_act_miss_f_delayed = _RAND_162[0:0]; + _RAND_163 = {2{`RANDOM}}; + ifu_bus_rdata_ff = _RAND_163[63:0]; + _RAND_164 = {1{`RANDOM}}; + ic_miss_buff_data_0 = _RAND_164[31:0]; _RAND_165 = {1{`RANDOM}}; - ic_miss_buff_data_0 = _RAND_165[31:0]; + ic_miss_buff_data_1 = _RAND_165[31:0]; _RAND_166 = {1{`RANDOM}}; - ic_miss_buff_data_1 = _RAND_166[31:0]; + ic_miss_buff_data_2 = _RAND_166[31:0]; _RAND_167 = {1{`RANDOM}}; - ic_miss_buff_data_2 = _RAND_167[31:0]; + ic_miss_buff_data_3 = _RAND_167[31:0]; _RAND_168 = {1{`RANDOM}}; - ic_miss_buff_data_3 = _RAND_168[31:0]; + ic_miss_buff_data_4 = _RAND_168[31:0]; _RAND_169 = {1{`RANDOM}}; - ic_miss_buff_data_4 = _RAND_169[31:0]; + ic_miss_buff_data_5 = _RAND_169[31:0]; _RAND_170 = {1{`RANDOM}}; - ic_miss_buff_data_5 = _RAND_170[31:0]; + ic_miss_buff_data_6 = _RAND_170[31:0]; _RAND_171 = {1{`RANDOM}}; - ic_miss_buff_data_6 = _RAND_171[31:0]; + ic_miss_buff_data_7 = _RAND_171[31:0]; _RAND_172 = {1{`RANDOM}}; - ic_miss_buff_data_7 = _RAND_172[31:0]; + ic_miss_buff_data_8 = _RAND_172[31:0]; _RAND_173 = {1{`RANDOM}}; - ic_miss_buff_data_8 = _RAND_173[31:0]; + ic_miss_buff_data_9 = _RAND_173[31:0]; _RAND_174 = {1{`RANDOM}}; - ic_miss_buff_data_9 = _RAND_174[31:0]; + ic_miss_buff_data_10 = _RAND_174[31:0]; _RAND_175 = {1{`RANDOM}}; - ic_miss_buff_data_10 = _RAND_175[31:0]; + ic_miss_buff_data_11 = _RAND_175[31:0]; _RAND_176 = {1{`RANDOM}}; - ic_miss_buff_data_11 = _RAND_176[31:0]; + ic_miss_buff_data_12 = _RAND_176[31:0]; _RAND_177 = {1{`RANDOM}}; - ic_miss_buff_data_12 = _RAND_177[31:0]; + ic_miss_buff_data_13 = _RAND_177[31:0]; _RAND_178 = {1{`RANDOM}}; - ic_miss_buff_data_13 = _RAND_178[31:0]; + ic_miss_buff_data_14 = _RAND_178[31:0]; _RAND_179 = {1{`RANDOM}}; - ic_miss_buff_data_14 = _RAND_179[31:0]; + ic_miss_buff_data_15 = _RAND_179[31:0]; _RAND_180 = {1{`RANDOM}}; - ic_miss_buff_data_15 = _RAND_180[31:0]; + ic_crit_wd_rdy_new_ff = _RAND_180[0:0]; _RAND_181 = {1{`RANDOM}}; - ic_crit_wd_rdy_new_ff = _RAND_181[0:0]; + ic_miss_buff_data_error = _RAND_181[7:0]; _RAND_182 = {1{`RANDOM}}; - ic_miss_buff_data_error = _RAND_182[7:0]; + ic_debug_ict_array_sel_ff = _RAND_182[0:0]; _RAND_183 = {1{`RANDOM}}; - ic_debug_ict_array_sel_ff = _RAND_183[0:0]; + ic_tag_valid_out_1_0 = _RAND_183[0:0]; _RAND_184 = {1{`RANDOM}}; - ic_tag_valid_out_1_0 = _RAND_184[0:0]; + ic_tag_valid_out_1_1 = _RAND_184[0:0]; _RAND_185 = {1{`RANDOM}}; - ic_tag_valid_out_1_1 = _RAND_185[0:0]; + ic_tag_valid_out_1_2 = _RAND_185[0:0]; _RAND_186 = {1{`RANDOM}}; - ic_tag_valid_out_1_2 = _RAND_186[0:0]; + ic_tag_valid_out_1_3 = _RAND_186[0:0]; _RAND_187 = {1{`RANDOM}}; - ic_tag_valid_out_1_3 = _RAND_187[0:0]; + ic_tag_valid_out_1_4 = _RAND_187[0:0]; _RAND_188 = {1{`RANDOM}}; - ic_tag_valid_out_1_4 = _RAND_188[0:0]; + ic_tag_valid_out_1_5 = _RAND_188[0:0]; _RAND_189 = {1{`RANDOM}}; - ic_tag_valid_out_1_5 = _RAND_189[0:0]; + ic_tag_valid_out_1_6 = _RAND_189[0:0]; _RAND_190 = {1{`RANDOM}}; - ic_tag_valid_out_1_6 = _RAND_190[0:0]; + ic_tag_valid_out_1_7 = _RAND_190[0:0]; _RAND_191 = {1{`RANDOM}}; - ic_tag_valid_out_1_7 = _RAND_191[0:0]; + ic_tag_valid_out_1_8 = _RAND_191[0:0]; _RAND_192 = {1{`RANDOM}}; - ic_tag_valid_out_1_8 = _RAND_192[0:0]; + ic_tag_valid_out_1_9 = _RAND_192[0:0]; _RAND_193 = {1{`RANDOM}}; - ic_tag_valid_out_1_9 = _RAND_193[0:0]; + ic_tag_valid_out_1_10 = _RAND_193[0:0]; _RAND_194 = {1{`RANDOM}}; - ic_tag_valid_out_1_10 = _RAND_194[0:0]; + ic_tag_valid_out_1_11 = _RAND_194[0:0]; _RAND_195 = {1{`RANDOM}}; - ic_tag_valid_out_1_11 = _RAND_195[0:0]; + ic_tag_valid_out_1_12 = _RAND_195[0:0]; _RAND_196 = {1{`RANDOM}}; - ic_tag_valid_out_1_12 = _RAND_196[0:0]; + ic_tag_valid_out_1_13 = _RAND_196[0:0]; _RAND_197 = {1{`RANDOM}}; - ic_tag_valid_out_1_13 = _RAND_197[0:0]; + ic_tag_valid_out_1_14 = _RAND_197[0:0]; _RAND_198 = {1{`RANDOM}}; - ic_tag_valid_out_1_14 = _RAND_198[0:0]; + ic_tag_valid_out_1_15 = _RAND_198[0:0]; _RAND_199 = {1{`RANDOM}}; - ic_tag_valid_out_1_15 = _RAND_199[0:0]; + ic_tag_valid_out_1_16 = _RAND_199[0:0]; _RAND_200 = {1{`RANDOM}}; - ic_tag_valid_out_1_16 = _RAND_200[0:0]; + ic_tag_valid_out_1_17 = _RAND_200[0:0]; _RAND_201 = {1{`RANDOM}}; - ic_tag_valid_out_1_17 = _RAND_201[0:0]; + ic_tag_valid_out_1_18 = _RAND_201[0:0]; _RAND_202 = {1{`RANDOM}}; - ic_tag_valid_out_1_18 = _RAND_202[0:0]; + ic_tag_valid_out_1_19 = _RAND_202[0:0]; _RAND_203 = {1{`RANDOM}}; - ic_tag_valid_out_1_19 = _RAND_203[0:0]; + ic_tag_valid_out_1_20 = _RAND_203[0:0]; _RAND_204 = {1{`RANDOM}}; - ic_tag_valid_out_1_20 = _RAND_204[0:0]; + ic_tag_valid_out_1_21 = _RAND_204[0:0]; _RAND_205 = {1{`RANDOM}}; - ic_tag_valid_out_1_21 = _RAND_205[0:0]; + ic_tag_valid_out_1_22 = _RAND_205[0:0]; _RAND_206 = {1{`RANDOM}}; - ic_tag_valid_out_1_22 = _RAND_206[0:0]; + ic_tag_valid_out_1_23 = _RAND_206[0:0]; _RAND_207 = {1{`RANDOM}}; - ic_tag_valid_out_1_23 = _RAND_207[0:0]; + ic_tag_valid_out_1_24 = _RAND_207[0:0]; _RAND_208 = {1{`RANDOM}}; - ic_tag_valid_out_1_24 = _RAND_208[0:0]; + ic_tag_valid_out_1_25 = _RAND_208[0:0]; _RAND_209 = {1{`RANDOM}}; - ic_tag_valid_out_1_25 = _RAND_209[0:0]; + ic_tag_valid_out_1_26 = _RAND_209[0:0]; _RAND_210 = {1{`RANDOM}}; - ic_tag_valid_out_1_26 = _RAND_210[0:0]; + ic_tag_valid_out_1_27 = _RAND_210[0:0]; _RAND_211 = {1{`RANDOM}}; - ic_tag_valid_out_1_27 = _RAND_211[0:0]; + ic_tag_valid_out_1_28 = _RAND_211[0:0]; _RAND_212 = {1{`RANDOM}}; - ic_tag_valid_out_1_28 = _RAND_212[0:0]; + ic_tag_valid_out_1_29 = _RAND_212[0:0]; _RAND_213 = {1{`RANDOM}}; - ic_tag_valid_out_1_29 = _RAND_213[0:0]; + ic_tag_valid_out_1_30 = _RAND_213[0:0]; _RAND_214 = {1{`RANDOM}}; - ic_tag_valid_out_1_30 = _RAND_214[0:0]; + ic_tag_valid_out_1_31 = _RAND_214[0:0]; _RAND_215 = {1{`RANDOM}}; - ic_tag_valid_out_1_31 = _RAND_215[0:0]; + ic_tag_valid_out_1_32 = _RAND_215[0:0]; _RAND_216 = {1{`RANDOM}}; - ic_tag_valid_out_1_32 = _RAND_216[0:0]; + ic_tag_valid_out_1_33 = _RAND_216[0:0]; _RAND_217 = {1{`RANDOM}}; - ic_tag_valid_out_1_33 = _RAND_217[0:0]; + ic_tag_valid_out_1_34 = _RAND_217[0:0]; _RAND_218 = {1{`RANDOM}}; - ic_tag_valid_out_1_34 = _RAND_218[0:0]; + ic_tag_valid_out_1_35 = _RAND_218[0:0]; _RAND_219 = {1{`RANDOM}}; - ic_tag_valid_out_1_35 = _RAND_219[0:0]; + ic_tag_valid_out_1_36 = _RAND_219[0:0]; _RAND_220 = {1{`RANDOM}}; - ic_tag_valid_out_1_36 = _RAND_220[0:0]; + ic_tag_valid_out_1_37 = _RAND_220[0:0]; _RAND_221 = {1{`RANDOM}}; - ic_tag_valid_out_1_37 = _RAND_221[0:0]; + ic_tag_valid_out_1_38 = _RAND_221[0:0]; _RAND_222 = {1{`RANDOM}}; - ic_tag_valid_out_1_38 = _RAND_222[0:0]; + ic_tag_valid_out_1_39 = _RAND_222[0:0]; _RAND_223 = {1{`RANDOM}}; - ic_tag_valid_out_1_39 = _RAND_223[0:0]; + ic_tag_valid_out_1_40 = _RAND_223[0:0]; _RAND_224 = {1{`RANDOM}}; - ic_tag_valid_out_1_40 = _RAND_224[0:0]; + ic_tag_valid_out_1_41 = _RAND_224[0:0]; _RAND_225 = {1{`RANDOM}}; - ic_tag_valid_out_1_41 = _RAND_225[0:0]; + ic_tag_valid_out_1_42 = _RAND_225[0:0]; _RAND_226 = {1{`RANDOM}}; - ic_tag_valid_out_1_42 = _RAND_226[0:0]; + ic_tag_valid_out_1_43 = _RAND_226[0:0]; _RAND_227 = {1{`RANDOM}}; - ic_tag_valid_out_1_43 = _RAND_227[0:0]; + ic_tag_valid_out_1_44 = _RAND_227[0:0]; _RAND_228 = {1{`RANDOM}}; - ic_tag_valid_out_1_44 = _RAND_228[0:0]; + ic_tag_valid_out_1_45 = _RAND_228[0:0]; _RAND_229 = {1{`RANDOM}}; - ic_tag_valid_out_1_45 = _RAND_229[0:0]; + ic_tag_valid_out_1_46 = _RAND_229[0:0]; _RAND_230 = {1{`RANDOM}}; - ic_tag_valid_out_1_46 = _RAND_230[0:0]; + ic_tag_valid_out_1_47 = _RAND_230[0:0]; _RAND_231 = {1{`RANDOM}}; - ic_tag_valid_out_1_47 = _RAND_231[0:0]; + ic_tag_valid_out_1_48 = _RAND_231[0:0]; _RAND_232 = {1{`RANDOM}}; - ic_tag_valid_out_1_48 = _RAND_232[0:0]; + ic_tag_valid_out_1_49 = _RAND_232[0:0]; _RAND_233 = {1{`RANDOM}}; - ic_tag_valid_out_1_49 = _RAND_233[0:0]; + ic_tag_valid_out_1_50 = _RAND_233[0:0]; _RAND_234 = {1{`RANDOM}}; - ic_tag_valid_out_1_50 = _RAND_234[0:0]; + ic_tag_valid_out_1_51 = _RAND_234[0:0]; _RAND_235 = {1{`RANDOM}}; - ic_tag_valid_out_1_51 = _RAND_235[0:0]; + ic_tag_valid_out_1_52 = _RAND_235[0:0]; _RAND_236 = {1{`RANDOM}}; - ic_tag_valid_out_1_52 = _RAND_236[0:0]; + ic_tag_valid_out_1_53 = _RAND_236[0:0]; _RAND_237 = {1{`RANDOM}}; - ic_tag_valid_out_1_53 = _RAND_237[0:0]; + ic_tag_valid_out_1_54 = _RAND_237[0:0]; _RAND_238 = {1{`RANDOM}}; - ic_tag_valid_out_1_54 = _RAND_238[0:0]; + ic_tag_valid_out_1_55 = _RAND_238[0:0]; _RAND_239 = {1{`RANDOM}}; - ic_tag_valid_out_1_55 = _RAND_239[0:0]; + ic_tag_valid_out_1_56 = _RAND_239[0:0]; _RAND_240 = {1{`RANDOM}}; - ic_tag_valid_out_1_56 = _RAND_240[0:0]; + ic_tag_valid_out_1_57 = _RAND_240[0:0]; _RAND_241 = {1{`RANDOM}}; - ic_tag_valid_out_1_57 = _RAND_241[0:0]; + ic_tag_valid_out_1_58 = _RAND_241[0:0]; _RAND_242 = {1{`RANDOM}}; - ic_tag_valid_out_1_58 = _RAND_242[0:0]; + ic_tag_valid_out_1_59 = _RAND_242[0:0]; _RAND_243 = {1{`RANDOM}}; - ic_tag_valid_out_1_59 = _RAND_243[0:0]; + ic_tag_valid_out_1_60 = _RAND_243[0:0]; _RAND_244 = {1{`RANDOM}}; - ic_tag_valid_out_1_60 = _RAND_244[0:0]; + ic_tag_valid_out_1_61 = _RAND_244[0:0]; _RAND_245 = {1{`RANDOM}}; - ic_tag_valid_out_1_61 = _RAND_245[0:0]; + ic_tag_valid_out_1_62 = _RAND_245[0:0]; _RAND_246 = {1{`RANDOM}}; - ic_tag_valid_out_1_62 = _RAND_246[0:0]; + ic_tag_valid_out_1_63 = _RAND_246[0:0]; _RAND_247 = {1{`RANDOM}}; - ic_tag_valid_out_1_63 = _RAND_247[0:0]; + ic_tag_valid_out_1_64 = _RAND_247[0:0]; _RAND_248 = {1{`RANDOM}}; - ic_tag_valid_out_1_64 = _RAND_248[0:0]; + ic_tag_valid_out_1_65 = _RAND_248[0:0]; _RAND_249 = {1{`RANDOM}}; - ic_tag_valid_out_1_65 = _RAND_249[0:0]; + ic_tag_valid_out_1_66 = _RAND_249[0:0]; _RAND_250 = {1{`RANDOM}}; - ic_tag_valid_out_1_66 = _RAND_250[0:0]; + ic_tag_valid_out_1_67 = _RAND_250[0:0]; _RAND_251 = {1{`RANDOM}}; - ic_tag_valid_out_1_67 = _RAND_251[0:0]; + ic_tag_valid_out_1_68 = _RAND_251[0:0]; _RAND_252 = {1{`RANDOM}}; - ic_tag_valid_out_1_68 = _RAND_252[0:0]; + ic_tag_valid_out_1_69 = _RAND_252[0:0]; _RAND_253 = {1{`RANDOM}}; - ic_tag_valid_out_1_69 = _RAND_253[0:0]; + ic_tag_valid_out_1_70 = _RAND_253[0:0]; _RAND_254 = {1{`RANDOM}}; - ic_tag_valid_out_1_70 = _RAND_254[0:0]; + ic_tag_valid_out_1_71 = _RAND_254[0:0]; _RAND_255 = {1{`RANDOM}}; - ic_tag_valid_out_1_71 = _RAND_255[0:0]; + ic_tag_valid_out_1_72 = _RAND_255[0:0]; _RAND_256 = {1{`RANDOM}}; - ic_tag_valid_out_1_72 = _RAND_256[0:0]; + ic_tag_valid_out_1_73 = _RAND_256[0:0]; _RAND_257 = {1{`RANDOM}}; - ic_tag_valid_out_1_73 = _RAND_257[0:0]; + ic_tag_valid_out_1_74 = _RAND_257[0:0]; _RAND_258 = {1{`RANDOM}}; - ic_tag_valid_out_1_74 = _RAND_258[0:0]; + ic_tag_valid_out_1_75 = _RAND_258[0:0]; _RAND_259 = {1{`RANDOM}}; - ic_tag_valid_out_1_75 = _RAND_259[0:0]; + ic_tag_valid_out_1_76 = _RAND_259[0:0]; _RAND_260 = {1{`RANDOM}}; - ic_tag_valid_out_1_76 = _RAND_260[0:0]; + ic_tag_valid_out_1_77 = _RAND_260[0:0]; _RAND_261 = {1{`RANDOM}}; - ic_tag_valid_out_1_77 = _RAND_261[0:0]; + ic_tag_valid_out_1_78 = _RAND_261[0:0]; _RAND_262 = {1{`RANDOM}}; - ic_tag_valid_out_1_78 = _RAND_262[0:0]; + ic_tag_valid_out_1_79 = _RAND_262[0:0]; _RAND_263 = {1{`RANDOM}}; - ic_tag_valid_out_1_79 = _RAND_263[0:0]; + ic_tag_valid_out_1_80 = _RAND_263[0:0]; _RAND_264 = {1{`RANDOM}}; - ic_tag_valid_out_1_80 = _RAND_264[0:0]; + ic_tag_valid_out_1_81 = _RAND_264[0:0]; _RAND_265 = {1{`RANDOM}}; - ic_tag_valid_out_1_81 = _RAND_265[0:0]; + ic_tag_valid_out_1_82 = _RAND_265[0:0]; _RAND_266 = {1{`RANDOM}}; - ic_tag_valid_out_1_82 = _RAND_266[0:0]; + ic_tag_valid_out_1_83 = _RAND_266[0:0]; _RAND_267 = {1{`RANDOM}}; - ic_tag_valid_out_1_83 = _RAND_267[0:0]; + ic_tag_valid_out_1_84 = _RAND_267[0:0]; _RAND_268 = {1{`RANDOM}}; - ic_tag_valid_out_1_84 = _RAND_268[0:0]; + ic_tag_valid_out_1_85 = _RAND_268[0:0]; _RAND_269 = {1{`RANDOM}}; - ic_tag_valid_out_1_85 = _RAND_269[0:0]; + ic_tag_valid_out_1_86 = _RAND_269[0:0]; _RAND_270 = {1{`RANDOM}}; - ic_tag_valid_out_1_86 = _RAND_270[0:0]; + ic_tag_valid_out_1_87 = _RAND_270[0:0]; _RAND_271 = {1{`RANDOM}}; - ic_tag_valid_out_1_87 = _RAND_271[0:0]; + ic_tag_valid_out_1_88 = _RAND_271[0:0]; _RAND_272 = {1{`RANDOM}}; - ic_tag_valid_out_1_88 = _RAND_272[0:0]; + ic_tag_valid_out_1_89 = _RAND_272[0:0]; _RAND_273 = {1{`RANDOM}}; - ic_tag_valid_out_1_89 = _RAND_273[0:0]; + ic_tag_valid_out_1_90 = _RAND_273[0:0]; _RAND_274 = {1{`RANDOM}}; - ic_tag_valid_out_1_90 = _RAND_274[0:0]; + ic_tag_valid_out_1_91 = _RAND_274[0:0]; _RAND_275 = {1{`RANDOM}}; - ic_tag_valid_out_1_91 = _RAND_275[0:0]; + ic_tag_valid_out_1_92 = _RAND_275[0:0]; _RAND_276 = {1{`RANDOM}}; - ic_tag_valid_out_1_92 = _RAND_276[0:0]; + ic_tag_valid_out_1_93 = _RAND_276[0:0]; _RAND_277 = {1{`RANDOM}}; - ic_tag_valid_out_1_93 = _RAND_277[0:0]; + ic_tag_valid_out_1_94 = _RAND_277[0:0]; _RAND_278 = {1{`RANDOM}}; - ic_tag_valid_out_1_94 = _RAND_278[0:0]; + ic_tag_valid_out_1_95 = _RAND_278[0:0]; _RAND_279 = {1{`RANDOM}}; - ic_tag_valid_out_1_95 = _RAND_279[0:0]; + ic_tag_valid_out_1_96 = _RAND_279[0:0]; _RAND_280 = {1{`RANDOM}}; - ic_tag_valid_out_1_96 = _RAND_280[0:0]; + ic_tag_valid_out_1_97 = _RAND_280[0:0]; _RAND_281 = {1{`RANDOM}}; - ic_tag_valid_out_1_97 = _RAND_281[0:0]; + ic_tag_valid_out_1_98 = _RAND_281[0:0]; _RAND_282 = {1{`RANDOM}}; - ic_tag_valid_out_1_98 = _RAND_282[0:0]; + ic_tag_valid_out_1_99 = _RAND_282[0:0]; _RAND_283 = {1{`RANDOM}}; - ic_tag_valid_out_1_99 = _RAND_283[0:0]; + ic_tag_valid_out_1_100 = _RAND_283[0:0]; _RAND_284 = {1{`RANDOM}}; - ic_tag_valid_out_1_100 = _RAND_284[0:0]; + ic_tag_valid_out_1_101 = _RAND_284[0:0]; _RAND_285 = {1{`RANDOM}}; - ic_tag_valid_out_1_101 = _RAND_285[0:0]; + ic_tag_valid_out_1_102 = _RAND_285[0:0]; _RAND_286 = {1{`RANDOM}}; - ic_tag_valid_out_1_102 = _RAND_286[0:0]; + ic_tag_valid_out_1_103 = _RAND_286[0:0]; _RAND_287 = {1{`RANDOM}}; - ic_tag_valid_out_1_103 = _RAND_287[0:0]; + ic_tag_valid_out_1_104 = _RAND_287[0:0]; _RAND_288 = {1{`RANDOM}}; - ic_tag_valid_out_1_104 = _RAND_288[0:0]; + ic_tag_valid_out_1_105 = _RAND_288[0:0]; _RAND_289 = {1{`RANDOM}}; - ic_tag_valid_out_1_105 = _RAND_289[0:0]; + ic_tag_valid_out_1_106 = _RAND_289[0:0]; _RAND_290 = {1{`RANDOM}}; - ic_tag_valid_out_1_106 = _RAND_290[0:0]; + ic_tag_valid_out_1_107 = _RAND_290[0:0]; _RAND_291 = {1{`RANDOM}}; - ic_tag_valid_out_1_107 = _RAND_291[0:0]; + ic_tag_valid_out_1_108 = _RAND_291[0:0]; _RAND_292 = {1{`RANDOM}}; - ic_tag_valid_out_1_108 = _RAND_292[0:0]; + ic_tag_valid_out_1_109 = _RAND_292[0:0]; _RAND_293 = {1{`RANDOM}}; - ic_tag_valid_out_1_109 = _RAND_293[0:0]; + ic_tag_valid_out_1_110 = _RAND_293[0:0]; _RAND_294 = {1{`RANDOM}}; - ic_tag_valid_out_1_110 = _RAND_294[0:0]; + ic_tag_valid_out_1_111 = _RAND_294[0:0]; _RAND_295 = {1{`RANDOM}}; - ic_tag_valid_out_1_111 = _RAND_295[0:0]; + ic_tag_valid_out_1_112 = _RAND_295[0:0]; _RAND_296 = {1{`RANDOM}}; - ic_tag_valid_out_1_112 = _RAND_296[0:0]; + ic_tag_valid_out_1_113 = _RAND_296[0:0]; _RAND_297 = {1{`RANDOM}}; - ic_tag_valid_out_1_113 = _RAND_297[0:0]; + ic_tag_valid_out_1_114 = _RAND_297[0:0]; _RAND_298 = {1{`RANDOM}}; - ic_tag_valid_out_1_114 = _RAND_298[0:0]; + ic_tag_valid_out_1_115 = _RAND_298[0:0]; _RAND_299 = {1{`RANDOM}}; - ic_tag_valid_out_1_115 = _RAND_299[0:0]; + ic_tag_valid_out_1_116 = _RAND_299[0:0]; _RAND_300 = {1{`RANDOM}}; - ic_tag_valid_out_1_116 = _RAND_300[0:0]; + ic_tag_valid_out_1_117 = _RAND_300[0:0]; _RAND_301 = {1{`RANDOM}}; - ic_tag_valid_out_1_117 = _RAND_301[0:0]; + ic_tag_valid_out_1_118 = _RAND_301[0:0]; _RAND_302 = {1{`RANDOM}}; - ic_tag_valid_out_1_118 = _RAND_302[0:0]; + ic_tag_valid_out_1_119 = _RAND_302[0:0]; _RAND_303 = {1{`RANDOM}}; - ic_tag_valid_out_1_119 = _RAND_303[0:0]; + ic_tag_valid_out_1_120 = _RAND_303[0:0]; _RAND_304 = {1{`RANDOM}}; - ic_tag_valid_out_1_120 = _RAND_304[0:0]; + ic_tag_valid_out_1_121 = _RAND_304[0:0]; _RAND_305 = {1{`RANDOM}}; - ic_tag_valid_out_1_121 = _RAND_305[0:0]; + ic_tag_valid_out_1_122 = _RAND_305[0:0]; _RAND_306 = {1{`RANDOM}}; - ic_tag_valid_out_1_122 = _RAND_306[0:0]; + ic_tag_valid_out_1_123 = _RAND_306[0:0]; _RAND_307 = {1{`RANDOM}}; - ic_tag_valid_out_1_123 = _RAND_307[0:0]; + ic_tag_valid_out_1_124 = _RAND_307[0:0]; _RAND_308 = {1{`RANDOM}}; - ic_tag_valid_out_1_124 = _RAND_308[0:0]; + ic_tag_valid_out_1_125 = _RAND_308[0:0]; _RAND_309 = {1{`RANDOM}}; - ic_tag_valid_out_1_125 = _RAND_309[0:0]; + ic_tag_valid_out_1_126 = _RAND_309[0:0]; _RAND_310 = {1{`RANDOM}}; - ic_tag_valid_out_1_126 = _RAND_310[0:0]; + ic_tag_valid_out_1_127 = _RAND_310[0:0]; _RAND_311 = {1{`RANDOM}}; - ic_tag_valid_out_1_127 = _RAND_311[0:0]; + ic_tag_valid_out_0_0 = _RAND_311[0:0]; _RAND_312 = {1{`RANDOM}}; - ic_tag_valid_out_0_0 = _RAND_312[0:0]; + ic_tag_valid_out_0_1 = _RAND_312[0:0]; _RAND_313 = {1{`RANDOM}}; - ic_tag_valid_out_0_1 = _RAND_313[0:0]; + ic_tag_valid_out_0_2 = _RAND_313[0:0]; _RAND_314 = {1{`RANDOM}}; - ic_tag_valid_out_0_2 = _RAND_314[0:0]; + ic_tag_valid_out_0_3 = _RAND_314[0:0]; _RAND_315 = {1{`RANDOM}}; - ic_tag_valid_out_0_3 = _RAND_315[0:0]; + ic_tag_valid_out_0_4 = _RAND_315[0:0]; _RAND_316 = {1{`RANDOM}}; - ic_tag_valid_out_0_4 = _RAND_316[0:0]; + ic_tag_valid_out_0_5 = _RAND_316[0:0]; _RAND_317 = {1{`RANDOM}}; - ic_tag_valid_out_0_5 = _RAND_317[0:0]; + ic_tag_valid_out_0_6 = _RAND_317[0:0]; _RAND_318 = {1{`RANDOM}}; - ic_tag_valid_out_0_6 = _RAND_318[0:0]; + ic_tag_valid_out_0_7 = _RAND_318[0:0]; _RAND_319 = {1{`RANDOM}}; - ic_tag_valid_out_0_7 = _RAND_319[0:0]; + ic_tag_valid_out_0_8 = _RAND_319[0:0]; _RAND_320 = {1{`RANDOM}}; - ic_tag_valid_out_0_8 = _RAND_320[0:0]; + ic_tag_valid_out_0_9 = _RAND_320[0:0]; _RAND_321 = {1{`RANDOM}}; - ic_tag_valid_out_0_9 = _RAND_321[0:0]; + ic_tag_valid_out_0_10 = _RAND_321[0:0]; _RAND_322 = {1{`RANDOM}}; - ic_tag_valid_out_0_10 = _RAND_322[0:0]; + ic_tag_valid_out_0_11 = _RAND_322[0:0]; _RAND_323 = {1{`RANDOM}}; - ic_tag_valid_out_0_11 = _RAND_323[0:0]; + ic_tag_valid_out_0_12 = _RAND_323[0:0]; _RAND_324 = {1{`RANDOM}}; - ic_tag_valid_out_0_12 = _RAND_324[0:0]; + ic_tag_valid_out_0_13 = _RAND_324[0:0]; _RAND_325 = {1{`RANDOM}}; - ic_tag_valid_out_0_13 = _RAND_325[0:0]; + ic_tag_valid_out_0_14 = _RAND_325[0:0]; _RAND_326 = {1{`RANDOM}}; - ic_tag_valid_out_0_14 = _RAND_326[0:0]; + ic_tag_valid_out_0_15 = _RAND_326[0:0]; _RAND_327 = {1{`RANDOM}}; - ic_tag_valid_out_0_15 = _RAND_327[0:0]; + ic_tag_valid_out_0_16 = _RAND_327[0:0]; _RAND_328 = {1{`RANDOM}}; - ic_tag_valid_out_0_16 = _RAND_328[0:0]; + ic_tag_valid_out_0_17 = _RAND_328[0:0]; _RAND_329 = {1{`RANDOM}}; - ic_tag_valid_out_0_17 = _RAND_329[0:0]; + ic_tag_valid_out_0_18 = _RAND_329[0:0]; _RAND_330 = {1{`RANDOM}}; - ic_tag_valid_out_0_18 = _RAND_330[0:0]; + ic_tag_valid_out_0_19 = _RAND_330[0:0]; _RAND_331 = {1{`RANDOM}}; - ic_tag_valid_out_0_19 = _RAND_331[0:0]; + ic_tag_valid_out_0_20 = _RAND_331[0:0]; _RAND_332 = {1{`RANDOM}}; - ic_tag_valid_out_0_20 = _RAND_332[0:0]; + ic_tag_valid_out_0_21 = _RAND_332[0:0]; _RAND_333 = {1{`RANDOM}}; - ic_tag_valid_out_0_21 = _RAND_333[0:0]; + ic_tag_valid_out_0_22 = _RAND_333[0:0]; _RAND_334 = {1{`RANDOM}}; - ic_tag_valid_out_0_22 = _RAND_334[0:0]; + ic_tag_valid_out_0_23 = _RAND_334[0:0]; _RAND_335 = {1{`RANDOM}}; - ic_tag_valid_out_0_23 = _RAND_335[0:0]; + ic_tag_valid_out_0_24 = _RAND_335[0:0]; _RAND_336 = {1{`RANDOM}}; - ic_tag_valid_out_0_24 = _RAND_336[0:0]; + ic_tag_valid_out_0_25 = _RAND_336[0:0]; _RAND_337 = {1{`RANDOM}}; - ic_tag_valid_out_0_25 = _RAND_337[0:0]; + ic_tag_valid_out_0_26 = _RAND_337[0:0]; _RAND_338 = {1{`RANDOM}}; - ic_tag_valid_out_0_26 = _RAND_338[0:0]; + ic_tag_valid_out_0_27 = _RAND_338[0:0]; _RAND_339 = {1{`RANDOM}}; - ic_tag_valid_out_0_27 = _RAND_339[0:0]; + ic_tag_valid_out_0_28 = _RAND_339[0:0]; _RAND_340 = {1{`RANDOM}}; - ic_tag_valid_out_0_28 = _RAND_340[0:0]; + ic_tag_valid_out_0_29 = _RAND_340[0:0]; _RAND_341 = {1{`RANDOM}}; - ic_tag_valid_out_0_29 = _RAND_341[0:0]; + ic_tag_valid_out_0_30 = _RAND_341[0:0]; _RAND_342 = {1{`RANDOM}}; - ic_tag_valid_out_0_30 = _RAND_342[0:0]; + ic_tag_valid_out_0_31 = _RAND_342[0:0]; _RAND_343 = {1{`RANDOM}}; - ic_tag_valid_out_0_31 = _RAND_343[0:0]; + ic_tag_valid_out_0_32 = _RAND_343[0:0]; _RAND_344 = {1{`RANDOM}}; - ic_tag_valid_out_0_32 = _RAND_344[0:0]; + ic_tag_valid_out_0_33 = _RAND_344[0:0]; _RAND_345 = {1{`RANDOM}}; - ic_tag_valid_out_0_33 = _RAND_345[0:0]; + ic_tag_valid_out_0_34 = _RAND_345[0:0]; _RAND_346 = {1{`RANDOM}}; - ic_tag_valid_out_0_34 = _RAND_346[0:0]; + ic_tag_valid_out_0_35 = _RAND_346[0:0]; _RAND_347 = {1{`RANDOM}}; - ic_tag_valid_out_0_35 = _RAND_347[0:0]; + ic_tag_valid_out_0_36 = _RAND_347[0:0]; _RAND_348 = {1{`RANDOM}}; - ic_tag_valid_out_0_36 = _RAND_348[0:0]; + ic_tag_valid_out_0_37 = _RAND_348[0:0]; _RAND_349 = {1{`RANDOM}}; - ic_tag_valid_out_0_37 = _RAND_349[0:0]; + ic_tag_valid_out_0_38 = _RAND_349[0:0]; _RAND_350 = {1{`RANDOM}}; - ic_tag_valid_out_0_38 = _RAND_350[0:0]; + ic_tag_valid_out_0_39 = _RAND_350[0:0]; _RAND_351 = {1{`RANDOM}}; - ic_tag_valid_out_0_39 = _RAND_351[0:0]; + ic_tag_valid_out_0_40 = _RAND_351[0:0]; _RAND_352 = {1{`RANDOM}}; - ic_tag_valid_out_0_40 = _RAND_352[0:0]; + ic_tag_valid_out_0_41 = _RAND_352[0:0]; _RAND_353 = {1{`RANDOM}}; - ic_tag_valid_out_0_41 = _RAND_353[0:0]; + ic_tag_valid_out_0_42 = _RAND_353[0:0]; _RAND_354 = {1{`RANDOM}}; - ic_tag_valid_out_0_42 = _RAND_354[0:0]; + ic_tag_valid_out_0_43 = _RAND_354[0:0]; _RAND_355 = {1{`RANDOM}}; - ic_tag_valid_out_0_43 = _RAND_355[0:0]; + ic_tag_valid_out_0_44 = _RAND_355[0:0]; _RAND_356 = {1{`RANDOM}}; - ic_tag_valid_out_0_44 = _RAND_356[0:0]; + ic_tag_valid_out_0_45 = _RAND_356[0:0]; _RAND_357 = {1{`RANDOM}}; - ic_tag_valid_out_0_45 = _RAND_357[0:0]; + ic_tag_valid_out_0_46 = _RAND_357[0:0]; _RAND_358 = {1{`RANDOM}}; - ic_tag_valid_out_0_46 = _RAND_358[0:0]; + ic_tag_valid_out_0_47 = _RAND_358[0:0]; _RAND_359 = {1{`RANDOM}}; - ic_tag_valid_out_0_47 = _RAND_359[0:0]; + ic_tag_valid_out_0_48 = _RAND_359[0:0]; _RAND_360 = {1{`RANDOM}}; - ic_tag_valid_out_0_48 = _RAND_360[0:0]; + ic_tag_valid_out_0_49 = _RAND_360[0:0]; _RAND_361 = {1{`RANDOM}}; - ic_tag_valid_out_0_49 = _RAND_361[0:0]; + ic_tag_valid_out_0_50 = _RAND_361[0:0]; _RAND_362 = {1{`RANDOM}}; - ic_tag_valid_out_0_50 = _RAND_362[0:0]; + ic_tag_valid_out_0_51 = _RAND_362[0:0]; _RAND_363 = {1{`RANDOM}}; - ic_tag_valid_out_0_51 = _RAND_363[0:0]; + ic_tag_valid_out_0_52 = _RAND_363[0:0]; _RAND_364 = {1{`RANDOM}}; - ic_tag_valid_out_0_52 = _RAND_364[0:0]; + ic_tag_valid_out_0_53 = _RAND_364[0:0]; _RAND_365 = {1{`RANDOM}}; - ic_tag_valid_out_0_53 = _RAND_365[0:0]; + ic_tag_valid_out_0_54 = _RAND_365[0:0]; _RAND_366 = {1{`RANDOM}}; - ic_tag_valid_out_0_54 = _RAND_366[0:0]; + ic_tag_valid_out_0_55 = _RAND_366[0:0]; _RAND_367 = {1{`RANDOM}}; - ic_tag_valid_out_0_55 = _RAND_367[0:0]; + ic_tag_valid_out_0_56 = _RAND_367[0:0]; _RAND_368 = {1{`RANDOM}}; - ic_tag_valid_out_0_56 = _RAND_368[0:0]; + ic_tag_valid_out_0_57 = _RAND_368[0:0]; _RAND_369 = {1{`RANDOM}}; - ic_tag_valid_out_0_57 = _RAND_369[0:0]; + ic_tag_valid_out_0_58 = _RAND_369[0:0]; _RAND_370 = {1{`RANDOM}}; - ic_tag_valid_out_0_58 = _RAND_370[0:0]; + ic_tag_valid_out_0_59 = _RAND_370[0:0]; _RAND_371 = {1{`RANDOM}}; - ic_tag_valid_out_0_59 = _RAND_371[0:0]; + ic_tag_valid_out_0_60 = _RAND_371[0:0]; _RAND_372 = {1{`RANDOM}}; - ic_tag_valid_out_0_60 = _RAND_372[0:0]; + ic_tag_valid_out_0_61 = _RAND_372[0:0]; _RAND_373 = {1{`RANDOM}}; - ic_tag_valid_out_0_61 = _RAND_373[0:0]; + ic_tag_valid_out_0_62 = _RAND_373[0:0]; _RAND_374 = {1{`RANDOM}}; - ic_tag_valid_out_0_62 = _RAND_374[0:0]; + ic_tag_valid_out_0_63 = _RAND_374[0:0]; _RAND_375 = {1{`RANDOM}}; - ic_tag_valid_out_0_63 = _RAND_375[0:0]; + ic_tag_valid_out_0_64 = _RAND_375[0:0]; _RAND_376 = {1{`RANDOM}}; - ic_tag_valid_out_0_64 = _RAND_376[0:0]; + ic_tag_valid_out_0_65 = _RAND_376[0:0]; _RAND_377 = {1{`RANDOM}}; - ic_tag_valid_out_0_65 = _RAND_377[0:0]; + ic_tag_valid_out_0_66 = _RAND_377[0:0]; _RAND_378 = {1{`RANDOM}}; - ic_tag_valid_out_0_66 = _RAND_378[0:0]; + ic_tag_valid_out_0_67 = _RAND_378[0:0]; _RAND_379 = {1{`RANDOM}}; - ic_tag_valid_out_0_67 = _RAND_379[0:0]; + ic_tag_valid_out_0_68 = _RAND_379[0:0]; _RAND_380 = {1{`RANDOM}}; - ic_tag_valid_out_0_68 = _RAND_380[0:0]; + ic_tag_valid_out_0_69 = _RAND_380[0:0]; _RAND_381 = {1{`RANDOM}}; - ic_tag_valid_out_0_69 = _RAND_381[0:0]; + ic_tag_valid_out_0_70 = _RAND_381[0:0]; _RAND_382 = {1{`RANDOM}}; - ic_tag_valid_out_0_70 = _RAND_382[0:0]; + ic_tag_valid_out_0_71 = _RAND_382[0:0]; _RAND_383 = {1{`RANDOM}}; - ic_tag_valid_out_0_71 = _RAND_383[0:0]; + ic_tag_valid_out_0_72 = _RAND_383[0:0]; _RAND_384 = {1{`RANDOM}}; - ic_tag_valid_out_0_72 = _RAND_384[0:0]; + ic_tag_valid_out_0_73 = _RAND_384[0:0]; _RAND_385 = {1{`RANDOM}}; - ic_tag_valid_out_0_73 = _RAND_385[0:0]; + ic_tag_valid_out_0_74 = _RAND_385[0:0]; _RAND_386 = {1{`RANDOM}}; - ic_tag_valid_out_0_74 = _RAND_386[0:0]; + ic_tag_valid_out_0_75 = _RAND_386[0:0]; _RAND_387 = {1{`RANDOM}}; - ic_tag_valid_out_0_75 = _RAND_387[0:0]; + ic_tag_valid_out_0_76 = _RAND_387[0:0]; _RAND_388 = {1{`RANDOM}}; - ic_tag_valid_out_0_76 = _RAND_388[0:0]; + ic_tag_valid_out_0_77 = _RAND_388[0:0]; _RAND_389 = {1{`RANDOM}}; - ic_tag_valid_out_0_77 = _RAND_389[0:0]; + ic_tag_valid_out_0_78 = _RAND_389[0:0]; _RAND_390 = {1{`RANDOM}}; - ic_tag_valid_out_0_78 = _RAND_390[0:0]; + ic_tag_valid_out_0_79 = _RAND_390[0:0]; _RAND_391 = {1{`RANDOM}}; - ic_tag_valid_out_0_79 = _RAND_391[0:0]; + ic_tag_valid_out_0_80 = _RAND_391[0:0]; _RAND_392 = {1{`RANDOM}}; - ic_tag_valid_out_0_80 = _RAND_392[0:0]; + ic_tag_valid_out_0_81 = _RAND_392[0:0]; _RAND_393 = {1{`RANDOM}}; - ic_tag_valid_out_0_81 = _RAND_393[0:0]; + ic_tag_valid_out_0_82 = _RAND_393[0:0]; _RAND_394 = {1{`RANDOM}}; - ic_tag_valid_out_0_82 = _RAND_394[0:0]; + ic_tag_valid_out_0_83 = _RAND_394[0:0]; _RAND_395 = {1{`RANDOM}}; - ic_tag_valid_out_0_83 = _RAND_395[0:0]; + ic_tag_valid_out_0_84 = _RAND_395[0:0]; _RAND_396 = {1{`RANDOM}}; - ic_tag_valid_out_0_84 = _RAND_396[0:0]; + ic_tag_valid_out_0_85 = _RAND_396[0:0]; _RAND_397 = {1{`RANDOM}}; - ic_tag_valid_out_0_85 = _RAND_397[0:0]; + ic_tag_valid_out_0_86 = _RAND_397[0:0]; _RAND_398 = {1{`RANDOM}}; - ic_tag_valid_out_0_86 = _RAND_398[0:0]; + ic_tag_valid_out_0_87 = _RAND_398[0:0]; _RAND_399 = {1{`RANDOM}}; - ic_tag_valid_out_0_87 = _RAND_399[0:0]; + ic_tag_valid_out_0_88 = _RAND_399[0:0]; _RAND_400 = {1{`RANDOM}}; - ic_tag_valid_out_0_88 = _RAND_400[0:0]; + ic_tag_valid_out_0_89 = _RAND_400[0:0]; _RAND_401 = {1{`RANDOM}}; - ic_tag_valid_out_0_89 = _RAND_401[0:0]; + ic_tag_valid_out_0_90 = _RAND_401[0:0]; _RAND_402 = {1{`RANDOM}}; - ic_tag_valid_out_0_90 = _RAND_402[0:0]; + ic_tag_valid_out_0_91 = _RAND_402[0:0]; _RAND_403 = {1{`RANDOM}}; - ic_tag_valid_out_0_91 = _RAND_403[0:0]; + ic_tag_valid_out_0_92 = _RAND_403[0:0]; _RAND_404 = {1{`RANDOM}}; - ic_tag_valid_out_0_92 = _RAND_404[0:0]; + ic_tag_valid_out_0_93 = _RAND_404[0:0]; _RAND_405 = {1{`RANDOM}}; - ic_tag_valid_out_0_93 = _RAND_405[0:0]; + ic_tag_valid_out_0_94 = _RAND_405[0:0]; _RAND_406 = {1{`RANDOM}}; - ic_tag_valid_out_0_94 = _RAND_406[0:0]; + ic_tag_valid_out_0_95 = _RAND_406[0:0]; _RAND_407 = {1{`RANDOM}}; - ic_tag_valid_out_0_95 = _RAND_407[0:0]; + ic_tag_valid_out_0_96 = _RAND_407[0:0]; _RAND_408 = {1{`RANDOM}}; - ic_tag_valid_out_0_96 = _RAND_408[0:0]; + ic_tag_valid_out_0_97 = _RAND_408[0:0]; _RAND_409 = {1{`RANDOM}}; - ic_tag_valid_out_0_97 = _RAND_409[0:0]; + ic_tag_valid_out_0_98 = _RAND_409[0:0]; _RAND_410 = {1{`RANDOM}}; - ic_tag_valid_out_0_98 = _RAND_410[0:0]; + ic_tag_valid_out_0_99 = _RAND_410[0:0]; _RAND_411 = {1{`RANDOM}}; - ic_tag_valid_out_0_99 = _RAND_411[0:0]; + ic_tag_valid_out_0_100 = _RAND_411[0:0]; _RAND_412 = {1{`RANDOM}}; - ic_tag_valid_out_0_100 = _RAND_412[0:0]; + ic_tag_valid_out_0_101 = _RAND_412[0:0]; _RAND_413 = {1{`RANDOM}}; - ic_tag_valid_out_0_101 = _RAND_413[0:0]; + ic_tag_valid_out_0_102 = _RAND_413[0:0]; _RAND_414 = {1{`RANDOM}}; - ic_tag_valid_out_0_102 = _RAND_414[0:0]; + ic_tag_valid_out_0_103 = _RAND_414[0:0]; _RAND_415 = {1{`RANDOM}}; - ic_tag_valid_out_0_103 = _RAND_415[0:0]; + ic_tag_valid_out_0_104 = _RAND_415[0:0]; _RAND_416 = {1{`RANDOM}}; - ic_tag_valid_out_0_104 = _RAND_416[0:0]; + ic_tag_valid_out_0_105 = _RAND_416[0:0]; _RAND_417 = {1{`RANDOM}}; - ic_tag_valid_out_0_105 = _RAND_417[0:0]; + ic_tag_valid_out_0_106 = _RAND_417[0:0]; _RAND_418 = {1{`RANDOM}}; - ic_tag_valid_out_0_106 = _RAND_418[0:0]; + ic_tag_valid_out_0_107 = _RAND_418[0:0]; _RAND_419 = {1{`RANDOM}}; - ic_tag_valid_out_0_107 = _RAND_419[0:0]; + ic_tag_valid_out_0_108 = _RAND_419[0:0]; _RAND_420 = {1{`RANDOM}}; - ic_tag_valid_out_0_108 = _RAND_420[0:0]; + ic_tag_valid_out_0_109 = _RAND_420[0:0]; _RAND_421 = {1{`RANDOM}}; - ic_tag_valid_out_0_109 = _RAND_421[0:0]; + ic_tag_valid_out_0_110 = _RAND_421[0:0]; _RAND_422 = {1{`RANDOM}}; - ic_tag_valid_out_0_110 = _RAND_422[0:0]; + ic_tag_valid_out_0_111 = _RAND_422[0:0]; _RAND_423 = {1{`RANDOM}}; - ic_tag_valid_out_0_111 = _RAND_423[0:0]; + ic_tag_valid_out_0_112 = _RAND_423[0:0]; _RAND_424 = {1{`RANDOM}}; - ic_tag_valid_out_0_112 = _RAND_424[0:0]; + ic_tag_valid_out_0_113 = _RAND_424[0:0]; _RAND_425 = {1{`RANDOM}}; - ic_tag_valid_out_0_113 = _RAND_425[0:0]; + ic_tag_valid_out_0_114 = _RAND_425[0:0]; _RAND_426 = {1{`RANDOM}}; - ic_tag_valid_out_0_114 = _RAND_426[0:0]; + ic_tag_valid_out_0_115 = _RAND_426[0:0]; _RAND_427 = {1{`RANDOM}}; - ic_tag_valid_out_0_115 = _RAND_427[0:0]; + ic_tag_valid_out_0_116 = _RAND_427[0:0]; _RAND_428 = {1{`RANDOM}}; - ic_tag_valid_out_0_116 = _RAND_428[0:0]; + ic_tag_valid_out_0_117 = _RAND_428[0:0]; _RAND_429 = {1{`RANDOM}}; - ic_tag_valid_out_0_117 = _RAND_429[0:0]; + ic_tag_valid_out_0_118 = _RAND_429[0:0]; _RAND_430 = {1{`RANDOM}}; - ic_tag_valid_out_0_118 = _RAND_430[0:0]; + ic_tag_valid_out_0_119 = _RAND_430[0:0]; _RAND_431 = {1{`RANDOM}}; - ic_tag_valid_out_0_119 = _RAND_431[0:0]; + ic_tag_valid_out_0_120 = _RAND_431[0:0]; _RAND_432 = {1{`RANDOM}}; - ic_tag_valid_out_0_120 = _RAND_432[0:0]; + ic_tag_valid_out_0_121 = _RAND_432[0:0]; _RAND_433 = {1{`RANDOM}}; - ic_tag_valid_out_0_121 = _RAND_433[0:0]; + ic_tag_valid_out_0_122 = _RAND_433[0:0]; _RAND_434 = {1{`RANDOM}}; - ic_tag_valid_out_0_122 = _RAND_434[0:0]; + ic_tag_valid_out_0_123 = _RAND_434[0:0]; _RAND_435 = {1{`RANDOM}}; - ic_tag_valid_out_0_123 = _RAND_435[0:0]; + ic_tag_valid_out_0_124 = _RAND_435[0:0]; _RAND_436 = {1{`RANDOM}}; - ic_tag_valid_out_0_124 = _RAND_436[0:0]; + ic_tag_valid_out_0_125 = _RAND_436[0:0]; _RAND_437 = {1{`RANDOM}}; - ic_tag_valid_out_0_125 = _RAND_437[0:0]; + ic_tag_valid_out_0_126 = _RAND_437[0:0]; _RAND_438 = {1{`RANDOM}}; - ic_tag_valid_out_0_126 = _RAND_438[0:0]; + ic_tag_valid_out_0_127 = _RAND_438[0:0]; _RAND_439 = {1{`RANDOM}}; - ic_tag_valid_out_0_127 = _RAND_439[0:0]; + ic_debug_way_ff = _RAND_439[1:0]; _RAND_440 = {1{`RANDOM}}; - ic_debug_way_ff = _RAND_440[1:0]; - _RAND_441 = {1{`RANDOM}}; - ic_debug_rd_en_ff = _RAND_441[0:0]; - _RAND_442 = {3{`RANDOM}}; - _T_1212 = _RAND_442[70:0]; + ic_debug_rd_en_ff = _RAND_440[0:0]; + _RAND_441 = {3{`RANDOM}}; + _T_1212 = _RAND_441[70:0]; + _RAND_442 = {1{`RANDOM}}; + ifc_region_acc_fault_memory_f = _RAND_442[0:0]; _RAND_443 = {1{`RANDOM}}; - ifc_region_acc_fault_memory_f = _RAND_443[0:0]; + perr_ic_index_ff = _RAND_443[6:0]; _RAND_444 = {1{`RANDOM}}; - perr_ic_index_ff = _RAND_444[6:0]; + dma_sb_err_state_ff = _RAND_444[0:0]; _RAND_445 = {1{`RANDOM}}; - dma_sb_err_state_ff = _RAND_445[0:0]; + bus_cmd_req_hold = _RAND_445[0:0]; _RAND_446 = {1{`RANDOM}}; - bus_cmd_req_hold = _RAND_446[0:0]; + ifu_bus_cmd_valid = _RAND_446[0:0]; _RAND_447 = {1{`RANDOM}}; - ifu_bus_cmd_valid = _RAND_447[0:0]; + bus_cmd_beat_count = _RAND_447[2:0]; _RAND_448 = {1{`RANDOM}}; - bus_cmd_beat_count = _RAND_448[2:0]; + ifu_bus_arready_unq_ff = _RAND_448[0:0]; _RAND_449 = {1{`RANDOM}}; - ifu_bus_arready_unq_ff = _RAND_449[0:0]; + ifu_bus_arvalid_ff = _RAND_449[0:0]; _RAND_450 = {1{`RANDOM}}; - ifu_bus_arvalid_ff = _RAND_450[0:0]; - _RAND_451 = {1{`RANDOM}}; - ifc_dma_access_ok_prev = _RAND_451[0:0]; - _RAND_452 = {2{`RANDOM}}; - iccm_ecc_corr_data_ff = _RAND_452[38:0]; + ifc_dma_access_ok_prev = _RAND_450[0:0]; + _RAND_451 = {2{`RANDOM}}; + iccm_ecc_corr_data_ff = _RAND_451[38:0]; + _RAND_452 = {1{`RANDOM}}; + dma_mem_addr_ff = _RAND_452[1:0]; _RAND_453 = {1{`RANDOM}}; - dma_mem_addr_ff = _RAND_453[1:0]; + dma_mem_tag_ff = _RAND_453[2:0]; _RAND_454 = {1{`RANDOM}}; - dma_mem_tag_ff = _RAND_454[2:0]; + iccm_dma_rtag_temp = _RAND_454[2:0]; _RAND_455 = {1{`RANDOM}}; - iccm_dma_rtag_temp = _RAND_455[2:0]; + iccm_dma_rvalid_temp = _RAND_455[0:0]; _RAND_456 = {1{`RANDOM}}; - iccm_dma_rvalid_temp = _RAND_456[0:0]; - _RAND_457 = {1{`RANDOM}}; - iccm_dma_ecc_error = _RAND_457[0:0]; - _RAND_458 = {2{`RANDOM}}; - iccm_dma_rdata_temp = _RAND_458[63:0]; + iccm_dma_ecc_error = _RAND_456[0:0]; + _RAND_457 = {2{`RANDOM}}; + iccm_dma_rdata_temp = _RAND_457[63:0]; + _RAND_458 = {1{`RANDOM}}; + iccm_ecc_corr_index_ff = _RAND_458[13:0]; _RAND_459 = {1{`RANDOM}}; - iccm_ecc_corr_index_ff = _RAND_459[13:0]; + iccm_rd_ecc_single_err_ff = _RAND_459[0:0]; _RAND_460 = {1{`RANDOM}}; - iccm_rd_ecc_single_err_ff = _RAND_460[0:0]; + iccm_rw_addr_f = _RAND_460[13:0]; _RAND_461 = {1{`RANDOM}}; - iccm_rw_addr_f = _RAND_461[13:0]; + ifu_status_wr_addr_ff = _RAND_461[6:0]; _RAND_462 = {1{`RANDOM}}; - ifu_status_wr_addr_ff = _RAND_462[6:0]; + way_status_wr_en_ff = _RAND_462[0:0]; _RAND_463 = {1{`RANDOM}}; - way_status_wr_en_ff = _RAND_463[0:0]; + way_status_new_ff = _RAND_463[0:0]; _RAND_464 = {1{`RANDOM}}; - way_status_new_ff = _RAND_464[0:0]; + ifu_tag_wren_ff = _RAND_464[1:0]; _RAND_465 = {1{`RANDOM}}; - ifu_tag_wren_ff = _RAND_465[1:0]; + ic_valid_ff = _RAND_465[0:0]; _RAND_466 = {1{`RANDOM}}; - ic_valid_ff = _RAND_466[0:0]; + _T_9799 = _RAND_466[0:0]; _RAND_467 = {1{`RANDOM}}; - _T_9799 = _RAND_467[0:0]; + _T_9800 = _RAND_467[0:0]; _RAND_468 = {1{`RANDOM}}; - _T_9800 = _RAND_468[0:0]; + _T_9801 = _RAND_468[0:0]; _RAND_469 = {1{`RANDOM}}; - _T_9801 = _RAND_469[0:0]; + _T_9805 = _RAND_469[0:0]; _RAND_470 = {1{`RANDOM}}; - _T_9805 = _RAND_470[0:0]; + _T_9806 = _RAND_470[0:0]; _RAND_471 = {1{`RANDOM}}; - _T_9806 = _RAND_471[0:0]; - _RAND_472 = {1{`RANDOM}}; - _T_9826 = _RAND_472[0:0]; + _T_9826 = _RAND_471[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin flush_final_f = 1'h0; @@ -7445,9 +7434,6 @@ initial begin if (reset) begin fetch_uncacheable_ff = 1'h0; end - if (reset) begin - miss_addr = 26'h0; - end if (reset) begin ifc_region_acc_fault_f = 1'h0; end @@ -9650,15 +9636,6 @@ end // initial fetch_uncacheable_ff <= io_ifc_fetch_uncacheable_bf; end end - always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin - if (reset) begin - miss_addr <= 26'h0; - end else if (_T_231) begin - miss_addr <= imb_ff[30:5]; - end else if (scnd_miss_req_q) begin - miss_addr <= imb_scnd_ff[30:5]; - end - end always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin if (reset) begin ifc_region_acc_fault_f <= 1'h0; @@ -44532,8 +44509,6 @@ module ifu( input io_ifu_ar_ready, output io_ifu_ar_valid, output [2:0] io_ifu_ar_bits_id, - output [31:0] io_ifu_ar_bits_addr, - output [3:0] io_ifu_ar_bits_region, input io_ifu_r_valid, input [2:0] io_ifu_r_bits_id, input [63:0] io_ifu_r_bits_data, @@ -44591,8 +44566,6 @@ module ifu( wire mem_ctl_io_ifu_axi_ar_ready; // @[ifu.scala 34:23] wire mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 34:23] wire [2:0] mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 34:23] - wire [31:0] mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 34:23] - wire [3:0] mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 34:23] wire mem_ctl_io_ifu_axi_r_ready; // @[ifu.scala 34:23] wire mem_ctl_io_ifu_axi_r_valid; // @[ifu.scala 34:23] wire [2:0] mem_ctl_io_ifu_axi_r_bits_id; // @[ifu.scala 34:23] @@ -44807,8 +44780,6 @@ module ifu( .io_ifu_axi_ar_ready(mem_ctl_io_ifu_axi_ar_ready), .io_ifu_axi_ar_valid(mem_ctl_io_ifu_axi_ar_valid), .io_ifu_axi_ar_bits_id(mem_ctl_io_ifu_axi_ar_bits_id), - .io_ifu_axi_ar_bits_addr(mem_ctl_io_ifu_axi_ar_bits_addr), - .io_ifu_axi_ar_bits_region(mem_ctl_io_ifu_axi_ar_bits_region), .io_ifu_axi_r_ready(mem_ctl_io_ifu_axi_r_ready), .io_ifu_axi_r_valid(mem_ctl_io_ifu_axi_r_valid), .io_ifu_axi_r_bits_id(mem_ctl_io_ifu_axi_r_bits_id), @@ -45048,8 +45019,6 @@ module ifu( assign io_ic_sel_premux_data = mem_ctl_io_ic_sel_premux_data; // @[ifu.scala 106:17] assign io_ifu_ar_valid = mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 103:22] assign io_ifu_ar_bits_id = mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 103:22] - assign io_ifu_ar_bits_addr = mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 103:22] - assign io_ifu_ar_bits_region = mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 103:22] assign io_iccm_dma_ecc_error = mem_ctl_io_iccm_dma_ecc_error; // @[ifu.scala 113:25] assign io_iccm_dma_rvalid = mem_ctl_io_iccm_dma_rvalid; // @[ifu.scala 114:22] assign io_iccm_dma_rdata = mem_ctl_io_iccm_dma_rdata; // @[ifu.scala 115:21] @@ -50547,7 +50516,6 @@ module csr_tlu( input io_lsu_imprecise_error_load_any, input io_lsu_imprecise_error_store_any, output [31:0] io_dec_tlu_mrac_ff, - output io_dec_tlu_wb_coalescing_disable, output io_dec_tlu_bpred_disable, output io_dec_tlu_sideeffect_posted_disable, output io_dec_tlu_core_ecc_disable, @@ -52662,7 +52630,6 @@ module csr_tlu( assign io_dec_tlu_meicurpl = meicurpl; // @[dec_tlu_ctl.scala 1970:22] assign io_dec_tlu_meihap = {meivt,meihap}; // @[dec_tlu_ctl.scala 1956:20] assign io_dec_tlu_mrac_ff = mrac; // @[dec_tlu_ctl.scala 1807:21] - assign io_dec_tlu_wb_coalescing_disable = mfdc[2]; // @[dec_tlu_ctl.scala 1767:39] assign io_dec_tlu_bpred_disable = mfdc[3]; // @[dec_tlu_ctl.scala 1766:39] assign io_dec_tlu_sideeffect_posted_disable = mfdc[6]; // @[dec_tlu_ctl.scala 1765:39] assign io_dec_tlu_core_ecc_disable = mfdc[8]; // @[dec_tlu_ctl.scala 1764:39] @@ -54421,7 +54388,6 @@ module dec_tlu_ctl( input io_tlu_busbuff_lsu_pmu_bus_error, input io_tlu_busbuff_lsu_pmu_bus_busy, output io_tlu_busbuff_dec_tlu_external_ldfwd_disable, - output io_tlu_busbuff_dec_tlu_wb_coalescing_disable, output io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, input io_tlu_busbuff_lsu_imprecise_error_load_any, input io_tlu_busbuff_lsu_imprecise_error_store_any, @@ -54656,7 +54622,6 @@ module dec_tlu_ctl( wire csr_io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 818:15] wire csr_io_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 818:15] wire [31:0] csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 818:15] - wire csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 818:15] wire csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 818:15] wire csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 818:15] wire csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 818:15] @@ -55745,7 +55710,6 @@ module dec_tlu_ctl( .io_lsu_imprecise_error_load_any(csr_io_lsu_imprecise_error_load_any), .io_lsu_imprecise_error_store_any(csr_io_lsu_imprecise_error_store_any), .io_dec_tlu_mrac_ff(csr_io_dec_tlu_mrac_ff), - .io_dec_tlu_wb_coalescing_disable(csr_io_dec_tlu_wb_coalescing_disable), .io_dec_tlu_bpred_disable(csr_io_dec_tlu_bpred_disable), .io_dec_tlu_sideeffect_posted_disable(csr_io_dec_tlu_sideeffect_posted_disable), .io_dec_tlu_core_ecc_disable(csr_io_dec_tlu_core_ecc_disable), @@ -56072,7 +56036,6 @@ module dec_tlu_ctl( assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid = csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 882:52] assign io_tlu_mem_dec_tlu_core_ecc_disable = csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 905:48] assign io_tlu_busbuff_dec_tlu_external_ldfwd_disable = csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 906:52] - assign io_tlu_busbuff_dec_tlu_wb_coalescing_disable = csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 902:52] assign io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 904:52] assign io_dec_pic_dec_tlu_meicurpl = csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 876:52] assign io_dec_pic_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 878:52] @@ -58084,7 +58047,6 @@ module dec( input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error, input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy, output io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable, - output io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable, output io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable, input io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any, input io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any, @@ -58533,7 +58495,6 @@ module dec( wire tlu_io_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 120:19] - wire tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec.scala 120:19] wire tlu_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec.scala 120:19] @@ -58990,7 +58951,6 @@ module dec( .io_tlu_busbuff_lsu_pmu_bus_error(tlu_io_tlu_busbuff_lsu_pmu_bus_error), .io_tlu_busbuff_lsu_pmu_bus_busy(tlu_io_tlu_busbuff_lsu_pmu_bus_busy), .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), - .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_tlu_busbuff_lsu_imprecise_error_load_any(tlu_io_tlu_busbuff_lsu_imprecise_error_load_any), .io_tlu_busbuff_lsu_imprecise_error_store_any(tlu_io_tlu_busbuff_lsu_imprecise_error_store_any), @@ -59177,7 +59137,6 @@ module dec( assign io_dec_exu_gpr_exu_gpr_i0_rs1_d = gpr_io_gpr_exu_gpr_i0_rs1_d; // @[dec.scala 201:22] assign io_dec_exu_gpr_exu_gpr_i0_rs2_d = gpr_io_gpr_exu_gpr_i0_rs2_d; // @[dec.scala 201:22] assign io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 222:26] - assign io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 222:26] assign io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 222:26] assign io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = tlu_io_tlu_dma_dec_tlu_dma_qos_prty; // @[dec.scala 206:18] assign io_dec_pic_dec_tlu_meicurpl = tlu_io_dec_pic_dec_tlu_meicurpl; // @[dec.scala 224:14] @@ -59425,21 +59384,14 @@ module dbg( input [31:0] io_dmi_reg_wdata, input io_sb_axi_aw_ready, output io_sb_axi_aw_valid, - output [31:0] io_sb_axi_aw_bits_addr, - output [3:0] io_sb_axi_aw_bits_region, - output [2:0] io_sb_axi_aw_bits_size, input io_sb_axi_w_ready, output io_sb_axi_w_valid, output [63:0] io_sb_axi_w_bits_data, - output [7:0] io_sb_axi_w_bits_strb, output io_sb_axi_b_ready, input io_sb_axi_b_valid, input [1:0] io_sb_axi_b_bits_resp, input io_sb_axi_ar_ready, output io_sb_axi_ar_valid, - output [31:0] io_sb_axi_ar_bits_addr, - output [3:0] io_sb_axi_ar_bits_region, - output [2:0] io_sb_axi_ar_bits_size, output io_sb_axi_r_ready, input io_sb_axi_r_valid, input [63:0] io_sb_axi_r_bits_data, @@ -59903,25 +59855,6 @@ module dbg( wire [63:0] _T_599 = _T_57 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] wire [63:0] _T_602 = {sbdata1_reg,sbdata0_reg}; // @[Cat.scala 29:58] wire [63:0] _T_603 = _T_599 & _T_602; // @[dbg.scala 427:119] - wire [7:0] _T_608 = _T_62 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [14:0] _T_610 = 15'h1 << sbaddress0_reg[2:0]; // @[dbg.scala 429:82] - wire [14:0] _GEN_115 = {{7'd0}, _T_608}; // @[dbg.scala 429:67] - wire [14:0] _T_611 = _GEN_115 & _T_610; // @[dbg.scala 429:67] - wire [7:0] _T_615 = _T_47 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_617 = {sbaddress0_reg[2:1],1'h0}; // @[Cat.scala 29:58] - wire [14:0] _T_618 = 15'h3 << _T_617; // @[dbg.scala 430:59] - wire [14:0] _GEN_116 = {{7'd0}, _T_615}; // @[dbg.scala 430:44] - wire [14:0] _T_619 = _GEN_116 & _T_618; // @[dbg.scala 430:44] - wire [14:0] _T_620 = _T_611 | _T_619; // @[dbg.scala 429:107] - wire [7:0] _T_624 = _T_51 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_626 = {sbaddress0_reg[2],2'h0}; // @[Cat.scala 29:58] - wire [14:0] _T_627 = 15'hf << _T_626; // @[dbg.scala 431:59] - wire [14:0] _GEN_117 = {{7'd0}, _T_624}; // @[dbg.scala 431:44] - wire [14:0] _T_628 = _GEN_117 & _T_627; // @[dbg.scala 431:44] - wire [14:0] _T_629 = _T_620 | _T_628; // @[dbg.scala 430:97] - wire [7:0] _T_633 = _T_57 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [14:0] _GEN_118 = {{7'd0}, _T_633}; // @[dbg.scala 431:100] - wire [14:0] _T_635 = _T_629 | _GEN_118; // @[dbg.scala 431:100] wire [3:0] _GEN_119 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 448:99] wire [6:0] _T_646 = 4'h8 * _GEN_119; // @[dbg.scala 448:99] wire [63:0] _T_647 = io_sb_axi_r_bits_data >> _T_646; // @[dbg.scala 448:92] @@ -59993,17 +59926,10 @@ module dbg( assign io_dbg_halt_req = _T_300 ? _T_316 : _GEN_35; // @[dbg.scala 268:19 dbg.scala 274:23 dbg.scala 279:23 dbg.scala 290:23 dbg.scala 295:23 dbg.scala 300:23 dbg.scala 307:23 dbg.scala 312:23] assign io_dbg_resume_req = _T_300 ? 1'h0 : _GEN_38; // @[dbg.scala 269:21 dbg.scala 289:25] assign io_sb_axi_aw_valid = _T_560 | _T_561; // @[dbg.scala 414:22] - assign io_sb_axi_aw_bits_addr = sbaddress0_reg; // @[dbg.scala 415:26] - assign io_sb_axi_aw_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 420:28] - assign io_sb_axi_aw_bits_size = sbcs_reg[19:17]; // @[dbg.scala 417:26] assign io_sb_axi_w_valid = _T_560 | _T_567; // @[dbg.scala 425:21] assign io_sb_axi_w_bits_data = _T_595 | _T_603; // @[dbg.scala 426:25] - assign io_sb_axi_w_bits_strb = _T_635[7:0]; // @[dbg.scala 429:25] assign io_sb_axi_b_ready = 1'h1; // @[dbg.scala 446:21] assign io_sb_axi_ar_valid = sb_state == 4'h3; // @[dbg.scala 435:22] - assign io_sb_axi_ar_bits_addr = sbaddress0_reg; // @[dbg.scala 436:26] - assign io_sb_axi_ar_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 441:28] - assign io_sb_axi_ar_bits_size = sbcs_reg[19:17]; // @[dbg.scala 438:26] assign io_sb_axi_r_ready = 1'h1; // @[dbg.scala 447:21] assign io_dbg_dec_dbg_ib_dbg_cmd_valid = _T_482 & io_dbg_dma_io_dma_dbg_ready; // @[dbg.scala 333:35] assign io_dbg_dec_dbg_ib_dbg_cmd_write = command_reg[16]; // @[dbg.scala 334:35] @@ -68150,7 +68076,6 @@ module lsu_bus_buffer( output io_tlu_busbuff_lsu_pmu_bus_error, output io_tlu_busbuff_lsu_pmu_bus_busy, input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, - input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, output io_tlu_busbuff_lsu_imprecise_error_load_any, output io_tlu_busbuff_lsu_imprecise_error_store_any, @@ -68199,25 +68124,15 @@ module lsu_bus_buffer( input io_lsu_axi_aw_ready, output io_lsu_axi_aw_valid, output [2:0] io_lsu_axi_aw_bits_id, - output [31:0] io_lsu_axi_aw_bits_addr, - output [3:0] io_lsu_axi_aw_bits_region, - output [2:0] io_lsu_axi_aw_bits_size, - output [3:0] io_lsu_axi_aw_bits_cache, input io_lsu_axi_w_ready, output io_lsu_axi_w_valid, output [63:0] io_lsu_axi_w_bits_data, - output [7:0] io_lsu_axi_w_bits_strb, output io_lsu_axi_b_ready, input io_lsu_axi_b_valid, - input [1:0] io_lsu_axi_b_bits_resp, input [2:0] io_lsu_axi_b_bits_id, input io_lsu_axi_ar_ready, output io_lsu_axi_ar_valid, output [2:0] io_lsu_axi_ar_bits_id, - output [31:0] io_lsu_axi_ar_bits_addr, - output [3:0] io_lsu_axi_ar_bits_region, - output [2:0] io_lsu_axi_ar_bits_size, - output [3:0] io_lsu_axi_ar_bits_cache, output io_lsu_axi_r_ready, input io_lsu_axi_r_valid, input [2:0] io_lsu_axi_r_bits_id, @@ -68311,11 +68226,11 @@ module lsu_bus_buffer( reg [31:0] _RAND_73; reg [31:0] _RAND_74; reg [31:0] _RAND_75; - reg [31:0] _RAND_76; + reg [63:0] _RAND_76; reg [31:0] _RAND_77; reg [31:0] _RAND_78; reg [31:0] _RAND_79; - reg [63:0] _RAND_80; + reg [31:0] _RAND_80; reg [31:0] _RAND_81; reg [31:0] _RAND_82; reg [31:0] _RAND_83; @@ -68338,10 +68253,6 @@ module lsu_bus_buffer( reg [31:0] _RAND_100; reg [31:0] _RAND_101; reg [31:0] _RAND_102; - reg [31:0] _RAND_103; - reg [31:0] _RAND_104; - reg [31:0] _RAND_105; - reg [31:0] _RAND_106; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] wire rvclkhdr_io_clk; // @[lib.scala 368:23] @@ -69015,74 +68926,26 @@ module lsu_bus_buffer( wire _T_854 = ~ibuf_byp; // @[lsu_bus_buffer.scala 206:56] wire ibuf_wr_en = _T_853 & _T_854; // @[lsu_bus_buffer.scala 206:54] wire _T_855 = ~ibuf_wr_en; // @[lsu_bus_buffer.scala 208:36] - reg [2:0] ibuf_timer; // @[lsu_bus_buffer.scala 251:55] - wire _T_864 = ibuf_timer == 3'h7; // @[lsu_bus_buffer.scala 214:62] - wire _T_865 = ibuf_wr_en | _T_864; // @[lsu_bus_buffer.scala 214:48] - wire _T_929 = _T_853 & io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 233:54] - wire _T_930 = _T_929 & ibuf_valid; // @[lsu_bus_buffer.scala 233:80] - wire _T_931 = _T_930 & ibuf_write; // @[lsu_bus_buffer.scala 233:93] - wire _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 233:129] - wire _T_935 = _T_931 & _T_934; // @[lsu_bus_buffer.scala 233:106] - wire _T_936 = ~io_is_sideeffects_r; // @[lsu_bus_buffer.scala 233:152] - wire _T_937 = _T_935 & _T_936; // @[lsu_bus_buffer.scala 233:150] - wire _T_938 = ~io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 233:175] - wire ibuf_merge_en = _T_937 & _T_938; // @[lsu_bus_buffer.scala 233:173] - wire ibuf_merge_in = ~io_ldst_dual_r; // @[lsu_bus_buffer.scala 234:20] - wire _T_866 = ibuf_merge_en & ibuf_merge_in; // @[lsu_bus_buffer.scala 214:98] - wire _T_867 = ~_T_866; // @[lsu_bus_buffer.scala 214:82] - wire _T_868 = _T_865 & _T_867; // @[lsu_bus_buffer.scala 214:80] - wire _T_869 = _T_868 | ibuf_byp; // @[lsu_bus_buffer.scala 215:5] wire _T_857 = ~io_lsu_busreq_r; // @[lsu_bus_buffer.scala 209:44] wire _T_858 = io_lsu_busreq_m & _T_857; // @[lsu_bus_buffer.scala 209:42] wire _T_859 = _T_858 & ibuf_valid; // @[lsu_bus_buffer.scala 209:61] wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[lsu_bus_buffer.scala 209:120] wire _T_863 = io_lsu_pkt_m_bits_load | _T_862; // @[lsu_bus_buffer.scala 209:100] wire ibuf_force_drain = _T_859 & _T_863; // @[lsu_bus_buffer.scala 209:74] - wire _T_870 = _T_869 | ibuf_force_drain; // @[lsu_bus_buffer.scala 215:16] reg ibuf_sideeffect; // @[Reg.scala 27:20] - wire _T_871 = _T_870 | ibuf_sideeffect; // @[lsu_bus_buffer.scala 215:35] - wire _T_872 = ~ibuf_write; // @[lsu_bus_buffer.scala 215:55] - wire _T_873 = _T_871 | _T_872; // @[lsu_bus_buffer.scala 215:53] - wire _T_874 = _T_873 | io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 215:67] - wire ibuf_drain_vld = ibuf_valid & _T_874; // @[lsu_bus_buffer.scala 214:32] - wire _T_856 = ibuf_drain_vld & _T_855; // @[lsu_bus_buffer.scala 208:34] + wire _T_856 = ibuf_valid & _T_855; // @[lsu_bus_buffer.scala 208:34] wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 208:49] reg [1:0] WrPtr1_r; // @[lsu_bus_buffer.scala 615:49] reg [1:0] WrPtr0_r; // @[lsu_bus_buffer.scala 614:49] reg [1:0] ibuf_tag; // @[Reg.scala 27:20] wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_bits_word,io_lsu_pkt_r_bits_half}; // @[Cat.scala 29:58] - wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[lsu_bus_buffer.scala 224:77] - wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 229:8] wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[lsu_bus_buffer.scala 230:8] - wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[lsu_bus_buffer.scala 228:46] - wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 229:8] wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[lsu_bus_buffer.scala 230:8] - wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[lsu_bus_buffer.scala 228:46] - wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 229:8] wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[lsu_bus_buffer.scala 230:8] - wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[lsu_bus_buffer.scala 228:46] - wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 229:8] wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[lsu_bus_buffer.scala 230:8] - wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[lsu_bus_buffer.scala 228:46] - wire [23:0] _T_922 = {_T_920,_T_911,_T_902}; // @[Cat.scala 29:58] - wire _T_923 = ibuf_timer < 3'h7; // @[lsu_bus_buffer.scala 231:59] - wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[lsu_bus_buffer.scala 231:93] - wire _T_941 = ~ibuf_merge_in; // @[lsu_bus_buffer.scala 235:65] - wire _T_942 = ibuf_merge_en & _T_941; // @[lsu_bus_buffer.scala 235:63] - wire _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[lsu_bus_buffer.scala 235:96] - wire _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[lsu_bus_buffer.scala 235:48] - wire _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[lsu_bus_buffer.scala 235:96] - wire _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[lsu_bus_buffer.scala 235:48] - wire _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[lsu_bus_buffer.scala 235:96] - wire _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[lsu_bus_buffer.scala 235:48] - wire _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[lsu_bus_buffer.scala 235:96] - wire _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[lsu_bus_buffer.scala 235:48] - wire [3:0] ibuf_byteen_out = {_T_968,_T_961,_T_954,_T_947}; // @[Cat.scala 29:58] - wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 236:45] - wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 236:45] - wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 236:45] - wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 236:45] - wire [31:0] ibuf_data_out = {_T_1002,_T_994,_T_986,_T_978}; // @[Cat.scala 29:58] + wire [23:0] _T_922 = {_T_919,_T_910,_T_901}; // @[Cat.scala 29:58] + wire [3:0] ibuf_byteen_out = {ibuf_byteen[3],ibuf_byteen[2],ibuf_byteen[1],ibuf_byteen[0]}; // @[Cat.scala 29:58] + wire [31:0] ibuf_data_out = {ibuf_data[31:24],ibuf_data[23:16],ibuf_data[15:8],ibuf_data[7:0]}; // @[Cat.scala 29:58] wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[lsu_bus_buffer.scala 238:58] wire _T_1006 = ~ibuf_rst; // @[lsu_bus_buffer.scala 238:93] reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20] @@ -69091,24 +68954,10 @@ module lsu_bus_buffer( reg ibuf_nomerge; // @[Reg.scala 27:20] reg ibuf_unsign; // @[Reg.scala 27:20] reg [1:0] ibuf_sz; // @[Reg.scala 27:20] - wire _T_4446 = buf_write[3] & _T_2621; // @[lsu_bus_buffer.scala 521:64] wire _T_4447 = ~buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 521:91] - wire _T_4448 = _T_4446 & _T_4447; // @[lsu_bus_buffer.scala 521:89] - wire _T_4441 = buf_write[2] & _T_2616; // @[lsu_bus_buffer.scala 521:64] wire _T_4442 = ~buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 521:91] - wire _T_4443 = _T_4441 & _T_4442; // @[lsu_bus_buffer.scala 521:89] - wire [1:0] _T_4449 = _T_4448 + _T_4443; // @[lsu_bus_buffer.scala 521:142] - wire _T_4436 = buf_write[1] & _T_2611; // @[lsu_bus_buffer.scala 521:64] wire _T_4437 = ~buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 521:91] - wire _T_4438 = _T_4436 & _T_4437; // @[lsu_bus_buffer.scala 521:89] - wire [1:0] _GEN_362 = {{1'd0}, _T_4438}; // @[lsu_bus_buffer.scala 521:142] - wire [2:0] _T_4450 = _T_4449 + _GEN_362; // @[lsu_bus_buffer.scala 521:142] - wire _T_4431 = buf_write[0] & _T_2606; // @[lsu_bus_buffer.scala 521:64] wire _T_4432 = ~buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 521:91] - wire _T_4433 = _T_4431 & _T_4432; // @[lsu_bus_buffer.scala 521:89] - wire [2:0] _GEN_363 = {{2'd0}, _T_4433}; // @[lsu_bus_buffer.scala 521:142] - wire [3:0] buf_numvld_wrcmd_any = _T_4450 + _GEN_363; // @[lsu_bus_buffer.scala 521:142] - wire _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[lsu_bus_buffer.scala 261:43] wire _T_4463 = _T_2621 & _T_4447; // @[lsu_bus_buffer.scala 522:73] wire _T_4460 = _T_2616 & _T_4442; // @[lsu_bus_buffer.scala 522:73] wire [1:0] _T_4464 = _T_4463 + _T_4460; // @[lsu_bus_buffer.scala 522:126] @@ -69119,11 +68968,6 @@ module lsu_bus_buffer( wire [2:0] _GEN_365 = {{2'd0}, _T_4454}; // @[lsu_bus_buffer.scala 522:126] wire [3:0] buf_numvld_cmd_any = _T_4465 + _GEN_365; // @[lsu_bus_buffer.scala 522:126] wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[lsu_bus_buffer.scala 261:72] - wire _T_1018 = _T_1016 & _T_1017; // @[lsu_bus_buffer.scala 261:51] - reg [2:0] obuf_wr_timer; // @[lsu_bus_buffer.scala 360:54] - wire _T_1019 = obuf_wr_timer != 3'h7; // @[lsu_bus_buffer.scala 261:97] - wire _T_1020 = _T_1018 & _T_1019; // @[lsu_bus_buffer.scala 261:80] - wire _T_1022 = _T_1020 & _T_938; // @[lsu_bus_buffer.scala 261:114] wire _T_1979 = |buf_age_3; // @[lsu_bus_buffer.scala 377:58] wire _T_1980 = ~_T_1979; // @[lsu_bus_buffer.scala 377:45] wire _T_1982 = _T_1980 & _T_2621; // @[lsu_bus_buffer.scala 377:63] @@ -69158,18 +69002,9 @@ module lsu_bus_buffer( wire _T_1025 = CmdPtr0 == 2'h2; // @[lsu_bus_buffer.scala 262:114] wire _T_1026 = CmdPtr0 == 2'h3; // @[lsu_bus_buffer.scala 262:114] reg buf_nomerge_0; // @[Reg.scala 27:20] - wire _T_1027 = _T_1023 & buf_nomerge_0; // @[Mux.scala 27:72] reg buf_nomerge_1; // @[Reg.scala 27:20] - wire _T_1028 = _T_1024 & buf_nomerge_1; // @[Mux.scala 27:72] reg buf_nomerge_2; // @[Reg.scala 27:20] - wire _T_1029 = _T_1025 & buf_nomerge_2; // @[Mux.scala 27:72] reg buf_nomerge_3; // @[Reg.scala 27:20] - wire _T_1030 = _T_1026 & buf_nomerge_3; // @[Mux.scala 27:72] - wire _T_1031 = _T_1027 | _T_1028; // @[Mux.scala 27:72] - wire _T_1032 = _T_1031 | _T_1029; // @[Mux.scala 27:72] - wire _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72] - wire _T_1035 = ~_T_1033; // @[lsu_bus_buffer.scala 262:31] - wire _T_1036 = _T_1022 & _T_1035; // @[lsu_bus_buffer.scala 262:29] reg _T_4330; // @[Reg.scala 27:20] reg _T_4327; // @[Reg.scala 27:20] reg _T_4324; // @[Reg.scala 27:20] @@ -69183,7 +69018,6 @@ module lsu_bus_buffer( wire _T_1050 = _T_1049 | _T_1047; // @[Mux.scala 27:72] wire _T_1051 = _T_1050 | _T_1048; // @[Mux.scala 27:72] wire _T_1053 = ~_T_1051; // @[lsu_bus_buffer.scala 263:5] - wire _T_1054 = _T_1036 & _T_1053; // @[lsu_bus_buffer.scala 262:140] wire _T_1065 = _T_858 & _T_852; // @[lsu_bus_buffer.scala 265:58] wire _T_1067 = _T_1065 & _T_1017; // @[lsu_bus_buffer.scala 265:72] wire [29:0] _T_1077 = _T_1023 ? buf_addr_0[31:2] : 30'h0; // @[Mux.scala 27:72] @@ -69195,12 +69029,6 @@ module lsu_bus_buffer( wire [29:0] _T_1083 = _T_1082 | _T_1080; // @[Mux.scala 27:72] wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[lsu_bus_buffer.scala 265:123] wire obuf_force_wr_en = _T_1067 & _T_1085; // @[lsu_bus_buffer.scala 265:101] - wire _T_1055 = ~obuf_force_wr_en; // @[lsu_bus_buffer.scala 263:119] - wire obuf_wr_wait = _T_1054 & _T_1055; // @[lsu_bus_buffer.scala 263:117] - wire _T_1056 = |buf_numvld_cmd_any; // @[lsu_bus_buffer.scala 264:75] - wire _T_1057 = obuf_wr_timer < 3'h7; // @[lsu_bus_buffer.scala 264:95] - wire _T_1058 = _T_1056 & _T_1057; // @[lsu_bus_buffer.scala 264:79] - wire [2:0] _T_1060 = obuf_wr_timer + 3'h1; // @[lsu_bus_buffer.scala 264:123] wire _T_4482 = buf_state_3 == 3'h1; // @[lsu_bus_buffer.scala 523:63] wire _T_4486 = _T_4482 | _T_4463; // @[lsu_bus_buffer.scala 523:74] wire _T_4477 = buf_state_2 == 3'h1; // @[lsu_bus_buffer.scala 523:63] @@ -69357,47 +69185,8 @@ module lsu_bus_buffer( reg obuf_nosend; // @[Reg.scala 27:20] wire _T_1233 = _T_1232 | obuf_nosend; // @[lsu_bus_buffer.scala 286:60] wire _T_1234 = _T_1230 & _T_1233; // @[lsu_bus_buffer.scala 286:29] - wire _T_1235 = ~obuf_wr_wait; // @[lsu_bus_buffer.scala 286:77] - wire _T_1236 = _T_1234 & _T_1235; // @[lsu_bus_buffer.scala 286:75] reg [31:0] obuf_addr; // @[lib.scala 374:16] - wire _T_4804 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[lsu_bus_buffer.scala 553:56] - wire _T_4805 = obuf_valid & _T_4804; // @[lsu_bus_buffer.scala 553:38] - wire _T_4807 = obuf_tag1 == 2'h0; // @[lsu_bus_buffer.scala 553:126] - wire _T_4808 = obuf_merge & _T_4807; // @[lsu_bus_buffer.scala 553:114] - wire _T_4809 = _T_3562 | _T_4808; // @[lsu_bus_buffer.scala 553:100] - wire _T_4810 = ~_T_4809; // @[lsu_bus_buffer.scala 553:80] - wire _T_4811 = _T_4805 & _T_4810; // @[lsu_bus_buffer.scala 553:78] - wire _T_4848 = _T_4778 & _T_4811; // @[Mux.scala 27:72] - wire _T_4816 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[lsu_bus_buffer.scala 553:56] - wire _T_4817 = obuf_valid & _T_4816; // @[lsu_bus_buffer.scala 553:38] - wire _T_4819 = obuf_tag1 == 2'h1; // @[lsu_bus_buffer.scala 553:126] - wire _T_4820 = obuf_merge & _T_4819; // @[lsu_bus_buffer.scala 553:114] - wire _T_4821 = _T_3755 | _T_4820; // @[lsu_bus_buffer.scala 553:100] - wire _T_4822 = ~_T_4821; // @[lsu_bus_buffer.scala 553:80] - wire _T_4823 = _T_4817 & _T_4822; // @[lsu_bus_buffer.scala 553:78] - wire _T_4849 = _T_4782 & _T_4823; // @[Mux.scala 27:72] - wire _T_4852 = _T_4848 | _T_4849; // @[Mux.scala 27:72] - wire _T_4828 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[lsu_bus_buffer.scala 553:56] - wire _T_4829 = obuf_valid & _T_4828; // @[lsu_bus_buffer.scala 553:38] - wire _T_4831 = obuf_tag1 == 2'h2; // @[lsu_bus_buffer.scala 553:126] - wire _T_4832 = obuf_merge & _T_4831; // @[lsu_bus_buffer.scala 553:114] - wire _T_4833 = _T_3948 | _T_4832; // @[lsu_bus_buffer.scala 553:100] - wire _T_4834 = ~_T_4833; // @[lsu_bus_buffer.scala 553:80] - wire _T_4835 = _T_4829 & _T_4834; // @[lsu_bus_buffer.scala 553:78] - wire _T_4850 = _T_4786 & _T_4835; // @[Mux.scala 27:72] - wire _T_4853 = _T_4852 | _T_4850; // @[Mux.scala 27:72] - wire _T_4840 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[lsu_bus_buffer.scala 553:56] - wire _T_4841 = obuf_valid & _T_4840; // @[lsu_bus_buffer.scala 553:38] - wire _T_4843 = obuf_tag1 == 2'h3; // @[lsu_bus_buffer.scala 553:126] - wire _T_4844 = obuf_merge & _T_4843; // @[lsu_bus_buffer.scala 553:114] - wire _T_4845 = _T_4141 | _T_4844; // @[lsu_bus_buffer.scala 553:100] - wire _T_4846 = ~_T_4845; // @[lsu_bus_buffer.scala 553:80] - wire _T_4847 = _T_4841 & _T_4846; // @[lsu_bus_buffer.scala 553:78] - wire _T_4851 = _T_4790 & _T_4847; // @[Mux.scala 27:72] - wire bus_addr_match_pending = _T_4853 | _T_4851; // @[Mux.scala 27:72] - wire _T_1239 = ~bus_addr_match_pending; // @[lsu_bus_buffer.scala 286:118] - wire _T_1240 = _T_1236 & _T_1239; // @[lsu_bus_buffer.scala 286:116] - wire obuf_wr_en = _T_1240 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 286:142] + wire obuf_wr_en = _T_1234 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 286:142] wire _T_1242 = obuf_valid & obuf_nosend; // @[lsu_bus_buffer.scala 288:47] wire bus_wcmd_sent = io_lsu_axi_aw_valid & io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 556:40] wire _T_4863 = obuf_cmd_done | bus_wcmd_sent; // @[lsu_bus_buffer.scala 558:35] @@ -69484,20 +69273,6 @@ module lsu_bus_buffer( wire _T_1332 = bus_cmd_sent & _T_1343; // @[lsu_bus_buffer.scala 316:20] wire _T_1333 = ~io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 316:37] wire _T_1334 = _T_1332 & _T_1333; // @[lsu_bus_buffer.scala 316:35] - wire [7:0] _T_1358 = {ldst_byteen_lo_r,4'h0}; // @[Cat.scala 29:58] - wire [7:0] _T_1359 = {4'h0,ldst_byteen_lo_r}; // @[Cat.scala 29:58] - wire [7:0] _T_1360 = io_lsu_addr_r[2] ? _T_1358 : _T_1359; // @[lsu_bus_buffer.scala 323:46] - wire [3:0] _T_1379 = _T_1023 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_1380 = _T_1024 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_1381 = _T_1025 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_1382 = _T_1026 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_1383 = _T_1379 | _T_1380; // @[Mux.scala 27:72] - wire [3:0] _T_1384 = _T_1383 | _T_1381; // @[Mux.scala 27:72] - wire [3:0] _T_1385 = _T_1384 | _T_1382; // @[Mux.scala 27:72] - wire [7:0] _T_1387 = {_T_1385,4'h0}; // @[Cat.scala 29:58] - wire [7:0] _T_1400 = {4'h0,_T_1385}; // @[Cat.scala 29:58] - wire [7:0] _T_1401 = _T_1289[2] ? _T_1387 : _T_1400; // @[lsu_bus_buffer.scala 324:8] - wire [7:0] obuf_byteen0_in = ibuf_buf_byp ? _T_1360 : _T_1401; // @[lsu_bus_buffer.scala 323:28] wire [7:0] _T_1403 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58] wire [7:0] _T_1404 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58] wire [7:0] _T_1405 = io_end_addr_r[2] ? _T_1403 : _T_1404; // @[lsu_bus_buffer.scala 325:46] @@ -69587,22 +69362,13 @@ module lsu_bus_buffer( wire _T_1837 = _T_1836 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 342:35] wire obuf_merge_en = _T_1835 | _T_1837; // @[lsu_bus_buffer.scala 341:253] wire _T_1539 = obuf_merge_en & obuf_byteen1_in[0]; // @[lsu_bus_buffer.scala 332:80] - wire _T_1540 = obuf_byteen0_in[0] | _T_1539; // @[lsu_bus_buffer.scala 332:63] wire _T_1543 = obuf_merge_en & obuf_byteen1_in[1]; // @[lsu_bus_buffer.scala 332:80] - wire _T_1544 = obuf_byteen0_in[1] | _T_1543; // @[lsu_bus_buffer.scala 332:63] wire _T_1547 = obuf_merge_en & obuf_byteen1_in[2]; // @[lsu_bus_buffer.scala 332:80] - wire _T_1548 = obuf_byteen0_in[2] | _T_1547; // @[lsu_bus_buffer.scala 332:63] wire _T_1551 = obuf_merge_en & obuf_byteen1_in[3]; // @[lsu_bus_buffer.scala 332:80] - wire _T_1552 = obuf_byteen0_in[3] | _T_1551; // @[lsu_bus_buffer.scala 332:63] wire _T_1555 = obuf_merge_en & obuf_byteen1_in[4]; // @[lsu_bus_buffer.scala 332:80] - wire _T_1556 = obuf_byteen0_in[4] | _T_1555; // @[lsu_bus_buffer.scala 332:63] wire _T_1559 = obuf_merge_en & obuf_byteen1_in[5]; // @[lsu_bus_buffer.scala 332:80] - wire _T_1560 = obuf_byteen0_in[5] | _T_1559; // @[lsu_bus_buffer.scala 332:63] wire _T_1563 = obuf_merge_en & obuf_byteen1_in[6]; // @[lsu_bus_buffer.scala 332:80] - wire _T_1564 = obuf_byteen0_in[6] | _T_1563; // @[lsu_bus_buffer.scala 332:63] wire _T_1567 = obuf_merge_en & obuf_byteen1_in[7]; // @[lsu_bus_buffer.scala 332:80] - wire _T_1568 = obuf_byteen0_in[7] | _T_1567; // @[lsu_bus_buffer.scala 332:63] - wire [7:0] obuf_byteen_in = {_T_1568,_T_1564,_T_1560,_T_1556,_T_1552,_T_1548,_T_1544,_T_1540}; // @[Cat.scala 29:58] wire [7:0] _T_1579 = _T_1539 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[lsu_bus_buffer.scala 333:44] wire [7:0] _T_1584 = _T_1543 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[lsu_bus_buffer.scala 333:44] wire [7:0] _T_1589 = _T_1547 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[lsu_bus_buffer.scala 333:44] @@ -69614,8 +69380,6 @@ module lsu_bus_buffer( wire [55:0] _T_1620 = {_T_1614,_T_1609,_T_1604,_T_1599,_T_1594,_T_1589,_T_1584}; // @[Cat.scala 29:58] wire _T_1839 = obuf_wr_en | obuf_valid; // @[lsu_bus_buffer.scala 345:58] wire _T_1840 = ~obuf_rst; // @[lsu_bus_buffer.scala 345:93] - reg [1:0] obuf_sz; // @[Reg.scala 27:20] - reg [7:0] obuf_byteen; // @[Reg.scala 27:20] reg [63:0] obuf_data; // @[lib.scala 374:16] wire _T_1853 = buf_state_0 == 3'h0; // @[lsu_bus_buffer.scala 363:65] wire _T_1854 = ibuf_tag == 2'h0; // @[lsu_bus_buffer.scala 364:30] @@ -69652,6 +69416,7 @@ module lsu_bus_buffer( wire _T_1885 = _T_1875 & _T_1884; // @[lsu_bus_buffer.scala 363:76] wire _T_1886 = buf_state_3 == 3'h0; // @[lsu_bus_buffer.scala 363:65] wire _T_1887 = ibuf_tag == 2'h3; // @[lsu_bus_buffer.scala 364:30] + wire _T_1888 = ibuf_valid & _T_1887; // @[lsu_bus_buffer.scala 364:19] wire _T_1889 = WrPtr0_r == 2'h3; // @[lsu_bus_buffer.scala 365:18] wire _T_1890 = WrPtr1_r == 2'h3; // @[lsu_bus_buffer.scala 365:57] wire [1:0] _T_1898 = _T_1885 ? 2'h2 : 2'h3; // @[Mux.scala 98:16] @@ -69727,17 +69492,15 @@ module lsu_bus_buffer( wire _T_2125 = _T_2123 | _T_2104[7]; // @[lsu_bus_buffer.scala 385:104] wire [2:0] _T_2127 = {_T_2111,_T_2118,_T_2125}; // @[Cat.scala 29:58] wire _T_3532 = ibuf_byp | io_ldst_dual_r; // @[lsu_bus_buffer.scala 443:77] - wire _T_3533 = ~ibuf_merge_en; // @[lsu_bus_buffer.scala 443:97] - wire _T_3534 = _T_3532 & _T_3533; // @[lsu_bus_buffer.scala 443:95] wire _T_3535 = 2'h0 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117] - wire _T_3536 = _T_3534 & _T_3535; // @[lsu_bus_buffer.scala 443:112] + wire _T_3536 = _T_3532 & _T_3535; // @[lsu_bus_buffer.scala 443:112] wire _T_3537 = ibuf_byp & io_ldst_dual_r; // @[lsu_bus_buffer.scala 443:144] wire _T_3538 = 2'h0 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166] wire _T_3539 = _T_3537 & _T_3538; // @[lsu_bus_buffer.scala 443:161] wire _T_3540 = _T_3536 | _T_3539; // @[lsu_bus_buffer.scala 443:132] wire _T_3541 = _T_853 & _T_3540; // @[lsu_bus_buffer.scala 443:63] wire _T_3542 = 2'h0 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206] - wire _T_3543 = ibuf_drain_vld & _T_3542; // @[lsu_bus_buffer.scala 443:201] + wire _T_3543 = ibuf_valid & _T_3542; // @[lsu_bus_buffer.scala 443:201] wire _T_3544 = _T_3541 | _T_3543; // @[lsu_bus_buffer.scala 443:183] wire _T_3554 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 450:46] wire _T_3589 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30] @@ -69805,7 +69568,7 @@ module lsu_bus_buffer( wire _GEN_64 = _T_3551 ? _T_3554 : _GEN_54; // @[Conditional.scala 39:67] wire buf_state_en_0 = _T_3528 ? _T_3544 : _GEN_64; // @[Conditional.scala 40:58] wire _T_2129 = _T_1853 & buf_state_en_0; // @[lsu_bus_buffer.scala 405:94] - wire _T_2135 = ibuf_drain_vld & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 407:23] + wire _T_2135 = ibuf_valid & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 407:23] wire _T_2137 = _T_2135 & _T_3532; // @[lsu_bus_buffer.scala 407:41] wire _T_2139 = _T_2137 & _T_1856; // @[lsu_bus_buffer.scala 407:71] wire _T_2141 = _T_2139 & _T_1854; // @[lsu_bus_buffer.scala 407:92] @@ -69837,13 +69600,13 @@ module lsu_bus_buffer( wire _T_2227 = _T_2225 | buf_age_0[3]; // @[lsu_bus_buffer.scala 408:97] wire [2:0] _T_2229 = {_T_2227,_T_2202,_T_2177}; // @[Cat.scala 29:58] wire _T_3728 = 2'h1 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117] - wire _T_3729 = _T_3534 & _T_3728; // @[lsu_bus_buffer.scala 443:112] + wire _T_3729 = _T_3532 & _T_3728; // @[lsu_bus_buffer.scala 443:112] wire _T_3731 = 2'h1 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166] wire _T_3732 = _T_3537 & _T_3731; // @[lsu_bus_buffer.scala 443:161] wire _T_3733 = _T_3729 | _T_3732; // @[lsu_bus_buffer.scala 443:132] wire _T_3734 = _T_853 & _T_3733; // @[lsu_bus_buffer.scala 443:63] wire _T_3735 = 2'h1 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206] - wire _T_3736 = ibuf_drain_vld & _T_3735; // @[lsu_bus_buffer.scala 443:201] + wire _T_3736 = ibuf_valid & _T_3735; // @[lsu_bus_buffer.scala 443:201] wire _T_3737 = _T_3734 | _T_3736; // @[lsu_bus_buffer.scala 443:183] wire _T_3782 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30] wire _T_3827 = io_lsu_axi_b_bits_id == 3'h1; // @[lsu_bus_buffer.scala 468:73] @@ -69927,13 +69690,13 @@ module lsu_bus_buffer( wire _T_2329 = _T_2327 | buf_age_1[3]; // @[lsu_bus_buffer.scala 408:97] wire [2:0] _T_2331 = {_T_2329,_T_2304,_T_2279}; // @[Cat.scala 29:58] wire _T_3921 = 2'h2 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117] - wire _T_3922 = _T_3534 & _T_3921; // @[lsu_bus_buffer.scala 443:112] + wire _T_3922 = _T_3532 & _T_3921; // @[lsu_bus_buffer.scala 443:112] wire _T_3924 = 2'h2 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166] wire _T_3925 = _T_3537 & _T_3924; // @[lsu_bus_buffer.scala 443:161] wire _T_3926 = _T_3922 | _T_3925; // @[lsu_bus_buffer.scala 443:132] wire _T_3927 = _T_853 & _T_3926; // @[lsu_bus_buffer.scala 443:63] wire _T_3928 = 2'h2 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206] - wire _T_3929 = ibuf_drain_vld & _T_3928; // @[lsu_bus_buffer.scala 443:201] + wire _T_3929 = ibuf_valid & _T_3928; // @[lsu_bus_buffer.scala 443:201] wire _T_3930 = _T_3927 | _T_3929; // @[lsu_bus_buffer.scala 443:183] wire _T_3975 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30] wire _T_4020 = io_lsu_axi_b_bits_id == 3'h2; // @[lsu_bus_buffer.scala 468:73] @@ -70017,13 +69780,13 @@ module lsu_bus_buffer( wire _T_2431 = _T_2429 | buf_age_2[3]; // @[lsu_bus_buffer.scala 408:97] wire [2:0] _T_2433 = {_T_2431,_T_2406,_T_2381}; // @[Cat.scala 29:58] wire _T_4114 = 2'h3 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117] - wire _T_4115 = _T_3534 & _T_4114; // @[lsu_bus_buffer.scala 443:112] + wire _T_4115 = _T_3532 & _T_4114; // @[lsu_bus_buffer.scala 443:112] wire _T_4117 = 2'h3 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166] wire _T_4118 = _T_3537 & _T_4117; // @[lsu_bus_buffer.scala 443:161] wire _T_4119 = _T_4115 | _T_4118; // @[lsu_bus_buffer.scala 443:132] wire _T_4120 = _T_853 & _T_4119; // @[lsu_bus_buffer.scala 443:63] wire _T_4121 = 2'h3 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206] - wire _T_4122 = ibuf_drain_vld & _T_4121; // @[lsu_bus_buffer.scala 443:201] + wire _T_4122 = ibuf_valid & _T_4121; // @[lsu_bus_buffer.scala 443:201] wire _T_4123 = _T_4120 | _T_4122; // @[lsu_bus_buffer.scala 443:183] wire _T_4168 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30] wire _T_4213 = io_lsu_axi_b_bits_id == 3'h3; // @[lsu_bus_buffer.scala 468:73] @@ -70218,11 +69981,7 @@ module lsu_bus_buffer( wire _T_3213 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[lsu_bus_buffer.scala 419:88] wire _T_3216 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[lsu_bus_buffer.scala 419:88] wire [2:0] _T_3218 = {_T_3216,_T_3213,_T_3210}; // @[Cat.scala 29:58] - wire _T_3329 = ibuf_drain_vld & _T_1854; // @[lsu_bus_buffer.scala 425:63] - wire _T_3331 = ibuf_drain_vld & _T_1865; // @[lsu_bus_buffer.scala 425:63] - wire _T_3333 = ibuf_drain_vld & _T_1876; // @[lsu_bus_buffer.scala 425:63] - wire _T_3335 = ibuf_drain_vld & _T_1887; // @[lsu_bus_buffer.scala 425:63] - wire [3:0] ibuf_drainvec_vld = {_T_3335,_T_3333,_T_3331,_T_3329}; // @[Cat.scala 29:58] + wire [3:0] ibuf_drainvec_vld = {_T_1888,_T_1877,_T_1866,_T_1855}; // @[Cat.scala 29:58] wire _T_3343 = _T_3537 & _T_1857; // @[lsu_bus_buffer.scala 427:35] wire _T_3352 = _T_3537 & _T_1868; // @[lsu_bus_buffer.scala 427:35] wire _T_3361 = _T_3537 & _T_1879; // @[lsu_bus_buffer.scala 427:35] @@ -70277,18 +70036,12 @@ module lsu_bus_buffer( wire _T_3659 = bus_rsp_read_error & buf_ldfwd[0]; // @[lsu_bus_buffer.scala 476:31] wire _T_3661 = _T_3659 & _T_3638; // @[lsu_bus_buffer.scala 476:46] wire _T_3662 = _T_3657 | _T_3661; // @[lsu_bus_buffer.scala 475:143] - wire _T_4870 = io_lsu_axi_b_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 563:66] - wire bus_rsp_write_error = bus_rsp_write & _T_4870; // @[lsu_bus_buffer.scala 563:40] - wire _T_3665 = bus_rsp_write_error & _T_3634; // @[lsu_bus_buffer.scala 477:53] - wire _T_3666 = _T_3662 | _T_3665; // @[lsu_bus_buffer.scala 476:88] - wire _T_3667 = _T_3568 & _T_3666; // @[lsu_bus_buffer.scala 475:68] + wire _T_3667 = _T_3568 & _T_3662; // @[lsu_bus_buffer.scala 475:68] wire _GEN_46 = _T_3589 & _T_3667; // @[Conditional.scala 39:67] wire _GEN_59 = _T_3555 ? _T_3582 : _GEN_46; // @[Conditional.scala 39:67] wire _GEN_71 = _T_3551 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] wire buf_error_en_0 = _T_3528 ? 1'h0 : _GEN_71; // @[Conditional.scala 40:58] - wire _T_3592 = ~bus_rsp_write_error; // @[lsu_bus_buffer.scala 465:73] - wire _T_3593 = buf_write[0] & _T_3592; // @[lsu_bus_buffer.scala 465:71] - wire _T_3594 = io_dec_tlu_force_halt | _T_3593; // @[lsu_bus_buffer.scala 465:55] + wire _T_3594 = io_dec_tlu_force_halt | buf_write[0]; // @[lsu_bus_buffer.scala 465:55] wire _T_3596 = ~buf_samedw_0; // @[lsu_bus_buffer.scala 466:30] wire _T_3597 = buf_dual_0 & _T_3596; // @[lsu_bus_buffer.scala 466:28] wire _T_3600 = _T_3597 & _T_3643; // @[lsu_bus_buffer.scala 466:45] @@ -70350,15 +70103,12 @@ module lsu_bus_buffer( wire _T_3852 = bus_rsp_read_error & buf_ldfwd[1]; // @[lsu_bus_buffer.scala 476:31] wire _T_3854 = _T_3852 & _T_3831; // @[lsu_bus_buffer.scala 476:46] wire _T_3855 = _T_3850 | _T_3854; // @[lsu_bus_buffer.scala 475:143] - wire _T_3858 = bus_rsp_write_error & _T_3827; // @[lsu_bus_buffer.scala 477:53] - wire _T_3859 = _T_3855 | _T_3858; // @[lsu_bus_buffer.scala 476:88] - wire _T_3860 = _T_3761 & _T_3859; // @[lsu_bus_buffer.scala 475:68] + wire _T_3860 = _T_3761 & _T_3855; // @[lsu_bus_buffer.scala 475:68] wire _GEN_122 = _T_3782 & _T_3860; // @[Conditional.scala 39:67] wire _GEN_135 = _T_3748 ? _T_3775 : _GEN_122; // @[Conditional.scala 39:67] wire _GEN_147 = _T_3744 ? 1'h0 : _GEN_135; // @[Conditional.scala 39:67] wire buf_error_en_1 = _T_3721 ? 1'h0 : _GEN_147; // @[Conditional.scala 40:58] - wire _T_3786 = buf_write[1] & _T_3592; // @[lsu_bus_buffer.scala 465:71] - wire _T_3787 = io_dec_tlu_force_halt | _T_3786; // @[lsu_bus_buffer.scala 465:55] + wire _T_3787 = io_dec_tlu_force_halt | buf_write[1]; // @[lsu_bus_buffer.scala 465:55] wire _T_3789 = ~buf_samedw_1; // @[lsu_bus_buffer.scala 466:30] wire _T_3790 = buf_dual_1 & _T_3789; // @[lsu_bus_buffer.scala 466:28] wire _T_3793 = _T_3790 & _T_3836; // @[lsu_bus_buffer.scala 466:45] @@ -70417,15 +70167,12 @@ module lsu_bus_buffer( wire _T_4045 = bus_rsp_read_error & buf_ldfwd[2]; // @[lsu_bus_buffer.scala 476:31] wire _T_4047 = _T_4045 & _T_4024; // @[lsu_bus_buffer.scala 476:46] wire _T_4048 = _T_4043 | _T_4047; // @[lsu_bus_buffer.scala 475:143] - wire _T_4051 = bus_rsp_write_error & _T_4020; // @[lsu_bus_buffer.scala 477:53] - wire _T_4052 = _T_4048 | _T_4051; // @[lsu_bus_buffer.scala 476:88] - wire _T_4053 = _T_3954 & _T_4052; // @[lsu_bus_buffer.scala 475:68] + wire _T_4053 = _T_3954 & _T_4048; // @[lsu_bus_buffer.scala 475:68] wire _GEN_198 = _T_3975 & _T_4053; // @[Conditional.scala 39:67] wire _GEN_211 = _T_3941 ? _T_3968 : _GEN_198; // @[Conditional.scala 39:67] wire _GEN_223 = _T_3937 ? 1'h0 : _GEN_211; // @[Conditional.scala 39:67] wire buf_error_en_2 = _T_3914 ? 1'h0 : _GEN_223; // @[Conditional.scala 40:58] - wire _T_3979 = buf_write[2] & _T_3592; // @[lsu_bus_buffer.scala 465:71] - wire _T_3980 = io_dec_tlu_force_halt | _T_3979; // @[lsu_bus_buffer.scala 465:55] + wire _T_3980 = io_dec_tlu_force_halt | buf_write[2]; // @[lsu_bus_buffer.scala 465:55] wire _T_3982 = ~buf_samedw_2; // @[lsu_bus_buffer.scala 466:30] wire _T_3983 = buf_dual_2 & _T_3982; // @[lsu_bus_buffer.scala 466:28] wire _T_3986 = _T_3983 & _T_4029; // @[lsu_bus_buffer.scala 466:45] @@ -70484,15 +70231,12 @@ module lsu_bus_buffer( wire _T_4238 = bus_rsp_read_error & buf_ldfwd[3]; // @[lsu_bus_buffer.scala 476:31] wire _T_4240 = _T_4238 & _T_4217; // @[lsu_bus_buffer.scala 476:46] wire _T_4241 = _T_4236 | _T_4240; // @[lsu_bus_buffer.scala 475:143] - wire _T_4244 = bus_rsp_write_error & _T_4213; // @[lsu_bus_buffer.scala 477:53] - wire _T_4245 = _T_4241 | _T_4244; // @[lsu_bus_buffer.scala 476:88] - wire _T_4246 = _T_4147 & _T_4245; // @[lsu_bus_buffer.scala 475:68] + wire _T_4246 = _T_4147 & _T_4241; // @[lsu_bus_buffer.scala 475:68] wire _GEN_274 = _T_4168 & _T_4246; // @[Conditional.scala 39:67] wire _GEN_287 = _T_4134 ? _T_4161 : _GEN_274; // @[Conditional.scala 39:67] wire _GEN_299 = _T_4130 ? 1'h0 : _GEN_287; // @[Conditional.scala 39:67] wire buf_error_en_3 = _T_4107 ? 1'h0 : _GEN_299; // @[Conditional.scala 40:58] - wire _T_4172 = buf_write[3] & _T_3592; // @[lsu_bus_buffer.scala 465:71] - wire _T_4173 = io_dec_tlu_force_halt | _T_4172; // @[lsu_bus_buffer.scala 465:55] + wire _T_4173 = io_dec_tlu_force_halt | buf_write[3]; // @[lsu_bus_buffer.scala 465:55] wire _T_4175 = ~buf_samedw_3; // @[lsu_bus_buffer.scala 466:30] wire _T_4176 = buf_dual_3 & _T_4175; // @[lsu_bus_buffer.scala 466:28] wire _T_4179 = _T_4176 & _T_4222; // @[lsu_bus_buffer.scala 466:45] @@ -70591,13 +70335,9 @@ module lsu_bus_buffer( wire _T_4518 = ~io_ld_full_hit_m; // @[lsu_bus_buffer.scala 529:129] wire _T_4520 = ~io_lsu_commit_r; // @[lsu_bus_buffer.scala 532:74] reg lsu_nonblock_load_valid_r; // @[lsu_bus_buffer.scala 617:66] - wire _T_4538 = _T_2799 & _T_3643; // @[Mux.scala 27:72] - wire _T_4539 = _T_2821 & _T_3836; // @[Mux.scala 27:72] - wire _T_4540 = _T_2843 & _T_4029; // @[Mux.scala 27:72] - wire _T_4541 = _T_2865 & _T_4222; // @[Mux.scala 27:72] - wire _T_4542 = _T_4538 | _T_4539; // @[Mux.scala 27:72] - wire _T_4543 = _T_4542 | _T_4540; // @[Mux.scala 27:72] - wire lsu_nonblock_load_data_ready = _T_4543 | _T_4541; // @[Mux.scala 27:72] + wire _T_4542 = _T_2799 | _T_2821; // @[Mux.scala 27:72] + wire _T_4543 = _T_4542 | _T_2843; // @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready = _T_4543 | _T_2865; // @[Mux.scala 27:72] wire _T_4549 = buf_error[0] & _T_3643; // @[lsu_bus_buffer.scala 535:121] wire _T_4554 = buf_error[1] & _T_3836; // @[lsu_bus_buffer.scala 535:121] wire _T_4559 = buf_error[2] & _T_4029; // @[lsu_bus_buffer.scala 535:121] @@ -70608,22 +70348,26 @@ module lsu_bus_buffer( wire _T_4568 = _T_2865 & _T_4564; // @[Mux.scala 27:72] wire _T_4569 = _T_4565 | _T_4566; // @[Mux.scala 27:72] wire _T_4570 = _T_4569 | _T_4567; // @[Mux.scala 27:72] + wire _T_4576 = _T_2799 & _T_3643; // @[lsu_bus_buffer.scala 536:103] wire _T_4577 = ~buf_dual_0; // @[lsu_bus_buffer.scala 536:122] wire _T_4578 = ~buf_dualhi_0; // @[lsu_bus_buffer.scala 536:137] wire _T_4579 = _T_4577 | _T_4578; // @[lsu_bus_buffer.scala 536:135] - wire _T_4580 = _T_4538 & _T_4579; // @[lsu_bus_buffer.scala 536:119] + wire _T_4580 = _T_4576 & _T_4579; // @[lsu_bus_buffer.scala 536:119] + wire _T_4584 = _T_2821 & _T_3836; // @[lsu_bus_buffer.scala 536:103] wire _T_4585 = ~buf_dual_1; // @[lsu_bus_buffer.scala 536:122] wire _T_4586 = ~buf_dualhi_1; // @[lsu_bus_buffer.scala 536:137] wire _T_4587 = _T_4585 | _T_4586; // @[lsu_bus_buffer.scala 536:135] - wire _T_4588 = _T_4539 & _T_4587; // @[lsu_bus_buffer.scala 536:119] + wire _T_4588 = _T_4584 & _T_4587; // @[lsu_bus_buffer.scala 536:119] + wire _T_4592 = _T_2843 & _T_4029; // @[lsu_bus_buffer.scala 536:103] wire _T_4593 = ~buf_dual_2; // @[lsu_bus_buffer.scala 536:122] wire _T_4594 = ~buf_dualhi_2; // @[lsu_bus_buffer.scala 536:137] wire _T_4595 = _T_4593 | _T_4594; // @[lsu_bus_buffer.scala 536:135] - wire _T_4596 = _T_4540 & _T_4595; // @[lsu_bus_buffer.scala 536:119] + wire _T_4596 = _T_4592 & _T_4595; // @[lsu_bus_buffer.scala 536:119] + wire _T_4600 = _T_2865 & _T_4222; // @[lsu_bus_buffer.scala 536:103] wire _T_4601 = ~buf_dual_3; // @[lsu_bus_buffer.scala 536:122] wire _T_4602 = ~buf_dualhi_3; // @[lsu_bus_buffer.scala 536:137] wire _T_4603 = _T_4601 | _T_4602; // @[lsu_bus_buffer.scala 536:135] - wire _T_4604 = _T_4541 & _T_4603; // @[lsu_bus_buffer.scala 536:119] + wire _T_4604 = _T_4600 & _T_4603; // @[lsu_bus_buffer.scala 536:119] wire [1:0] _T_4607 = _T_4596 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_4608 = _T_4604 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _GEN_391 = {{1'd0}, _T_4588}; // @[Mux.scala 27:72] @@ -70635,10 +70379,10 @@ module lsu_bus_buffer( wire [31:0] _T_4649 = _T_4645 | _T_4646; // @[Mux.scala 27:72] wire [31:0] _T_4650 = _T_4649 | _T_4647; // @[Mux.scala 27:72] wire [31:0] lsu_nonblock_load_data_lo = _T_4650 | _T_4648; // @[Mux.scala 27:72] - wire _T_4657 = _T_4538 & _T_3641; // @[lsu_bus_buffer.scala 538:105] - wire _T_4663 = _T_4539 & _T_3834; // @[lsu_bus_buffer.scala 538:105] - wire _T_4669 = _T_4540 & _T_4027; // @[lsu_bus_buffer.scala 538:105] - wire _T_4675 = _T_4541 & _T_4220; // @[lsu_bus_buffer.scala 538:105] + wire _T_4657 = _T_4576 & _T_3641; // @[lsu_bus_buffer.scala 538:105] + wire _T_4663 = _T_4584 & _T_3834; // @[lsu_bus_buffer.scala 538:105] + wire _T_4669 = _T_4592 & _T_4027; // @[lsu_bus_buffer.scala 538:105] + wire _T_4675 = _T_4600 & _T_4220; // @[lsu_bus_buffer.scala 538:105] wire [31:0] _T_4676 = _T_4657 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_4677 = _T_4663 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_4678 = _T_4669 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] @@ -70703,14 +70447,8 @@ module lsu_bus_buffer( wire [63:0] _T_4776 = _GEN_393 | _T_4772; // @[Mux.scala 27:72] wire _T_4874 = obuf_valid & obuf_write; // @[lsu_bus_buffer.scala 568:37] wire _T_4875 = ~obuf_cmd_done; // @[lsu_bus_buffer.scala 568:52] - wire _T_4876 = _T_4874 & _T_4875; // @[lsu_bus_buffer.scala 568:50] - wire [31:0] _T_4880 = {obuf_addr[31:3],3'h0}; // @[Cat.scala 29:58] - wire [2:0] _T_4882 = {1'h0,obuf_sz}; // @[Cat.scala 29:58] wire _T_4887 = ~obuf_data_done; // @[lsu_bus_buffer.scala 580:51] - wire _T_4888 = _T_4874 & _T_4887; // @[lsu_bus_buffer.scala 580:49] - wire [7:0] _T_4892 = obuf_write ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire _T_4895 = obuf_valid & _T_1343; // @[lsu_bus_buffer.scala 585:37] - wire _T_4897 = _T_4895 & _T_1349; // @[lsu_bus_buffer.scala 585:51] wire _T_4909 = io_lsu_bus_clk_en_q & buf_error[0]; // @[lsu_bus_buffer.scala 598:126] wire _T_4911 = _T_4909 & buf_write[0]; // @[lsu_bus_buffer.scala 598:141] wire _T_4914 = io_lsu_bus_clk_en_q & buf_error[1]; // @[lsu_bus_buffer.scala 598:126] @@ -70842,22 +70580,13 @@ module lsu_bus_buffer( assign io_dctl_busbuff_lsu_nonblock_load_data_error = _T_4570 | _T_4568; // @[lsu_bus_buffer.scala 535:48] assign io_dctl_busbuff_lsu_nonblock_load_data_tag = _T_4610 | _T_4608; // @[lsu_bus_buffer.scala 536:46] assign io_dctl_busbuff_lsu_nonblock_load_data = _T_4776[31:0]; // @[lsu_bus_buffer.scala 546:42] - assign io_lsu_axi_aw_valid = _T_4876 & _T_1239; // @[lsu_bus_buffer.scala 568:23] + assign io_lsu_axi_aw_valid = _T_4874 & _T_4875; // @[lsu_bus_buffer.scala 568:23] assign io_lsu_axi_aw_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 569:25] - assign io_lsu_axi_aw_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 570:27] - assign io_lsu_axi_aw_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 574:29] - assign io_lsu_axi_aw_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 571:27] - assign io_lsu_axi_aw_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 573:28] - assign io_lsu_axi_w_valid = _T_4888 & _T_1239; // @[lsu_bus_buffer.scala 580:22] + assign io_lsu_axi_w_valid = _T_4874 & _T_4887; // @[lsu_bus_buffer.scala 580:22] assign io_lsu_axi_w_bits_data = obuf_data; // @[lsu_bus_buffer.scala 582:26] - assign io_lsu_axi_w_bits_strb = obuf_byteen & _T_4892; // @[lsu_bus_buffer.scala 581:26] assign io_lsu_axi_b_ready = 1'h1; // @[lsu_bus_buffer.scala 596:22] - assign io_lsu_axi_ar_valid = _T_4897 & _T_1239; // @[lsu_bus_buffer.scala 585:23] + assign io_lsu_axi_ar_valid = _T_4895 & _T_1349; // @[lsu_bus_buffer.scala 585:23] assign io_lsu_axi_ar_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 586:25] - assign io_lsu_axi_ar_bits_addr = obuf_sideeffect ? obuf_addr : _T_4880; // @[lsu_bus_buffer.scala 587:27] - assign io_lsu_axi_ar_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 591:29] - assign io_lsu_axi_ar_bits_size = obuf_sideeffect ? _T_4882 : 3'h3; // @[lsu_bus_buffer.scala 588:27] - assign io_lsu_axi_ar_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 590:28] assign io_lsu_axi_r_ready = 1'h1; // @[lsu_bus_buffer.scala 597:22] assign io_lsu_busreq_r = _T_4987; // @[lsu_bus_buffer.scala 616:19] assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[lsu_bus_buffer.scala 525:30] @@ -70874,10 +70603,10 @@ module lsu_bus_buffer( assign rvclkhdr_1_io_en = _T_853 & _T_854; // @[lib.scala 371:17] assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_2_io_en = _T_1240 & io_lsu_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_2_io_en = _T_1234 & io_lsu_bus_clk_en; // @[lib.scala 371:17] assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_3_io_en = _T_1240 & io_lsu_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_3_io_en = _T_1234 & io_lsu_bus_clk_en; // @[lib.scala 371:17] assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_4_io_en = _T_3528 & buf_state_en_0; // @[lib.scala 371:17] @@ -71007,151 +70736,143 @@ initial begin _RAND_33 = {1{`RANDOM}}; ibuf_data = _RAND_33[31:0]; _RAND_34 = {1{`RANDOM}}; - ibuf_timer = _RAND_34[2:0]; + ibuf_sideeffect = _RAND_34[0:0]; _RAND_35 = {1{`RANDOM}}; - ibuf_sideeffect = _RAND_35[0:0]; + WrPtr1_r = _RAND_35[1:0]; _RAND_36 = {1{`RANDOM}}; - WrPtr1_r = _RAND_36[1:0]; + WrPtr0_r = _RAND_36[1:0]; _RAND_37 = {1{`RANDOM}}; - WrPtr0_r = _RAND_37[1:0]; + ibuf_tag = _RAND_37[1:0]; _RAND_38 = {1{`RANDOM}}; - ibuf_tag = _RAND_38[1:0]; + ibuf_dualtag = _RAND_38[1:0]; _RAND_39 = {1{`RANDOM}}; - ibuf_dualtag = _RAND_39[1:0]; + ibuf_dual = _RAND_39[0:0]; _RAND_40 = {1{`RANDOM}}; - ibuf_dual = _RAND_40[0:0]; + ibuf_samedw = _RAND_40[0:0]; _RAND_41 = {1{`RANDOM}}; - ibuf_samedw = _RAND_41[0:0]; + ibuf_nomerge = _RAND_41[0:0]; _RAND_42 = {1{`RANDOM}}; - ibuf_nomerge = _RAND_42[0:0]; + ibuf_unsign = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; - ibuf_unsign = _RAND_43[0:0]; + ibuf_sz = _RAND_43[1:0]; _RAND_44 = {1{`RANDOM}}; - ibuf_sz = _RAND_44[1:0]; + buf_nomerge_0 = _RAND_44[0:0]; _RAND_45 = {1{`RANDOM}}; - obuf_wr_timer = _RAND_45[2:0]; + buf_nomerge_1 = _RAND_45[0:0]; _RAND_46 = {1{`RANDOM}}; - buf_nomerge_0 = _RAND_46[0:0]; + buf_nomerge_2 = _RAND_46[0:0]; _RAND_47 = {1{`RANDOM}}; - buf_nomerge_1 = _RAND_47[0:0]; + buf_nomerge_3 = _RAND_47[0:0]; _RAND_48 = {1{`RANDOM}}; - buf_nomerge_2 = _RAND_48[0:0]; + _T_4330 = _RAND_48[0:0]; _RAND_49 = {1{`RANDOM}}; - buf_nomerge_3 = _RAND_49[0:0]; + _T_4327 = _RAND_49[0:0]; _RAND_50 = {1{`RANDOM}}; - _T_4330 = _RAND_50[0:0]; + _T_4324 = _RAND_50[0:0]; _RAND_51 = {1{`RANDOM}}; - _T_4327 = _RAND_51[0:0]; + _T_4321 = _RAND_51[0:0]; _RAND_52 = {1{`RANDOM}}; - _T_4324 = _RAND_52[0:0]; + obuf_sideeffect = _RAND_52[0:0]; _RAND_53 = {1{`RANDOM}}; - _T_4321 = _RAND_53[0:0]; + buf_dual_3 = _RAND_53[0:0]; _RAND_54 = {1{`RANDOM}}; - obuf_sideeffect = _RAND_54[0:0]; + buf_dual_2 = _RAND_54[0:0]; _RAND_55 = {1{`RANDOM}}; - buf_dual_3 = _RAND_55[0:0]; + buf_dual_1 = _RAND_55[0:0]; _RAND_56 = {1{`RANDOM}}; - buf_dual_2 = _RAND_56[0:0]; + buf_dual_0 = _RAND_56[0:0]; _RAND_57 = {1{`RANDOM}}; - buf_dual_1 = _RAND_57[0:0]; + buf_samedw_3 = _RAND_57[0:0]; _RAND_58 = {1{`RANDOM}}; - buf_dual_0 = _RAND_58[0:0]; + buf_samedw_2 = _RAND_58[0:0]; _RAND_59 = {1{`RANDOM}}; - buf_samedw_3 = _RAND_59[0:0]; + buf_samedw_1 = _RAND_59[0:0]; _RAND_60 = {1{`RANDOM}}; - buf_samedw_2 = _RAND_60[0:0]; + buf_samedw_0 = _RAND_60[0:0]; _RAND_61 = {1{`RANDOM}}; - buf_samedw_1 = _RAND_61[0:0]; + obuf_write = _RAND_61[0:0]; _RAND_62 = {1{`RANDOM}}; - buf_samedw_0 = _RAND_62[0:0]; + obuf_cmd_done = _RAND_62[0:0]; _RAND_63 = {1{`RANDOM}}; - obuf_write = _RAND_63[0:0]; + obuf_data_done = _RAND_63[0:0]; _RAND_64 = {1{`RANDOM}}; - obuf_cmd_done = _RAND_64[0:0]; + obuf_nosend = _RAND_64[0:0]; _RAND_65 = {1{`RANDOM}}; - obuf_data_done = _RAND_65[0:0]; + obuf_addr = _RAND_65[31:0]; _RAND_66 = {1{`RANDOM}}; - obuf_nosend = _RAND_66[0:0]; + buf_sz_0 = _RAND_66[1:0]; _RAND_67 = {1{`RANDOM}}; - obuf_addr = _RAND_67[31:0]; + buf_sz_1 = _RAND_67[1:0]; _RAND_68 = {1{`RANDOM}}; - buf_sz_0 = _RAND_68[1:0]; + buf_sz_2 = _RAND_68[1:0]; _RAND_69 = {1{`RANDOM}}; - buf_sz_1 = _RAND_69[1:0]; + buf_sz_3 = _RAND_69[1:0]; _RAND_70 = {1{`RANDOM}}; - buf_sz_2 = _RAND_70[1:0]; + obuf_rdrsp_pend = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - buf_sz_3 = _RAND_71[1:0]; + obuf_rdrsp_tag = _RAND_71[2:0]; _RAND_72 = {1{`RANDOM}}; - obuf_rdrsp_pend = _RAND_72[0:0]; + buf_dualhi_3 = _RAND_72[0:0]; _RAND_73 = {1{`RANDOM}}; - obuf_rdrsp_tag = _RAND_73[2:0]; + buf_dualhi_2 = _RAND_73[0:0]; _RAND_74 = {1{`RANDOM}}; - buf_dualhi_3 = _RAND_74[0:0]; + buf_dualhi_1 = _RAND_74[0:0]; _RAND_75 = {1{`RANDOM}}; - buf_dualhi_2 = _RAND_75[0:0]; - _RAND_76 = {1{`RANDOM}}; - buf_dualhi_1 = _RAND_76[0:0]; + buf_dualhi_0 = _RAND_75[0:0]; + _RAND_76 = {2{`RANDOM}}; + obuf_data = _RAND_76[63:0]; _RAND_77 = {1{`RANDOM}}; - buf_dualhi_0 = _RAND_77[0:0]; + buf_rspageQ_0 = _RAND_77[3:0]; _RAND_78 = {1{`RANDOM}}; - obuf_sz = _RAND_78[1:0]; + buf_rspageQ_1 = _RAND_78[3:0]; _RAND_79 = {1{`RANDOM}}; - obuf_byteen = _RAND_79[7:0]; - _RAND_80 = {2{`RANDOM}}; - obuf_data = _RAND_80[63:0]; + buf_rspageQ_2 = _RAND_79[3:0]; + _RAND_80 = {1{`RANDOM}}; + buf_rspageQ_3 = _RAND_80[3:0]; _RAND_81 = {1{`RANDOM}}; - buf_rspageQ_0 = _RAND_81[3:0]; + _T_4307 = _RAND_81[0:0]; _RAND_82 = {1{`RANDOM}}; - buf_rspageQ_1 = _RAND_82[3:0]; + _T_4305 = _RAND_82[0:0]; _RAND_83 = {1{`RANDOM}}; - buf_rspageQ_2 = _RAND_83[3:0]; + _T_4303 = _RAND_83[0:0]; _RAND_84 = {1{`RANDOM}}; - buf_rspageQ_3 = _RAND_84[3:0]; + _T_4301 = _RAND_84[0:0]; _RAND_85 = {1{`RANDOM}}; - _T_4307 = _RAND_85[0:0]; + buf_ldfwdtag_0 = _RAND_85[1:0]; _RAND_86 = {1{`RANDOM}}; - _T_4305 = _RAND_86[0:0]; + buf_dualtag_0 = _RAND_86[1:0]; _RAND_87 = {1{`RANDOM}}; - _T_4303 = _RAND_87[0:0]; + buf_ldfwdtag_3 = _RAND_87[1:0]; _RAND_88 = {1{`RANDOM}}; - _T_4301 = _RAND_88[0:0]; + buf_ldfwdtag_2 = _RAND_88[1:0]; _RAND_89 = {1{`RANDOM}}; - buf_ldfwdtag_0 = _RAND_89[1:0]; + buf_ldfwdtag_1 = _RAND_89[1:0]; _RAND_90 = {1{`RANDOM}}; - buf_dualtag_0 = _RAND_90[1:0]; + buf_dualtag_1 = _RAND_90[1:0]; _RAND_91 = {1{`RANDOM}}; - buf_ldfwdtag_3 = _RAND_91[1:0]; + buf_dualtag_2 = _RAND_91[1:0]; _RAND_92 = {1{`RANDOM}}; - buf_ldfwdtag_2 = _RAND_92[1:0]; + buf_dualtag_3 = _RAND_92[1:0]; _RAND_93 = {1{`RANDOM}}; - buf_ldfwdtag_1 = _RAND_93[1:0]; + _T_4336 = _RAND_93[0:0]; _RAND_94 = {1{`RANDOM}}; - buf_dualtag_1 = _RAND_94[1:0]; + _T_4339 = _RAND_94[0:0]; _RAND_95 = {1{`RANDOM}}; - buf_dualtag_2 = _RAND_95[1:0]; + _T_4342 = _RAND_95[0:0]; _RAND_96 = {1{`RANDOM}}; - buf_dualtag_3 = _RAND_96[1:0]; + _T_4345 = _RAND_96[0:0]; _RAND_97 = {1{`RANDOM}}; - _T_4336 = _RAND_97[0:0]; + _T_4411 = _RAND_97[0:0]; _RAND_98 = {1{`RANDOM}}; - _T_4339 = _RAND_98[0:0]; + _T_4406 = _RAND_98[0:0]; _RAND_99 = {1{`RANDOM}}; - _T_4342 = _RAND_99[0:0]; + _T_4401 = _RAND_99[0:0]; _RAND_100 = {1{`RANDOM}}; - _T_4345 = _RAND_100[0:0]; + _T_4396 = _RAND_100[0:0]; _RAND_101 = {1{`RANDOM}}; - _T_4411 = _RAND_101[0:0]; + lsu_nonblock_load_valid_r = _RAND_101[0:0]; _RAND_102 = {1{`RANDOM}}; - _T_4406 = _RAND_102[0:0]; - _RAND_103 = {1{`RANDOM}}; - _T_4401 = _RAND_103[0:0]; - _RAND_104 = {1{`RANDOM}}; - _T_4396 = _RAND_104[0:0]; - _RAND_105 = {1{`RANDOM}}; - lsu_nonblock_load_valid_r = _RAND_105[0:0]; - _RAND_106 = {1{`RANDOM}}; - _T_4987 = _RAND_106[0:0]; + _T_4987 = _RAND_102[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin buf_addr_0 = 32'h0; @@ -71255,9 +70976,6 @@ initial begin if (reset) begin ibuf_data = 32'h0; end - if (reset) begin - ibuf_timer = 3'h0; - end if (reset) begin ibuf_sideeffect = 1'h0; end @@ -71288,9 +71006,6 @@ initial begin if (reset) begin ibuf_sz = 2'h0; end - if (reset) begin - obuf_wr_timer = 3'h0; - end if (reset) begin buf_nomerge_0 = 1'h0; end @@ -71387,12 +71102,6 @@ initial begin if (reset) begin buf_dualhi_0 = 1'h0; end - if (reset) begin - obuf_sz = 2'h0; - end - if (reset) begin - obuf_byteen = 8'h0; - end if (reset) begin obuf_data = 64'h0; end @@ -71863,7 +71572,7 @@ end // initial if (reset) begin obuf_wr_enQ <= 1'h0; end else begin - obuf_wr_enQ <= _T_1240 & io_lsu_bus_clk_en; + obuf_wr_enQ <= _T_1234 & io_lsu_bus_clk_en; end end always @(posedge rvclkhdr_io_l1clk or posedge reset) begin @@ -71893,9 +71602,7 @@ end // initial if (reset) begin ibuf_byteen <= 4'h0; end else if (ibuf_wr_en) begin - if (_T_866) begin - ibuf_byteen <= _T_881; - end else if (io_ldst_dual_r) begin + if (io_ldst_dual_r) begin ibuf_byteen <= ldst_byteen_hi_r; end else begin ibuf_byteen <= ldst_byteen_lo_r; @@ -72059,16 +71766,7 @@ end // initial if (reset) begin ibuf_data <= 32'h0; end else begin - ibuf_data <= {_T_922,_T_893}; - end - end - always @(posedge io_lsu_free_c2_clk or posedge reset) begin - if (reset) begin - ibuf_timer <= 3'h0; - end else if (ibuf_wr_en) begin - ibuf_timer <= 3'h0; - end else if (_T_923) begin - ibuf_timer <= _T_926; + ibuf_data <= {_T_922,_T_892}; end end always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin @@ -72108,12 +71806,10 @@ end // initial if (reset) begin ibuf_tag <= 2'h0; end else if (ibuf_wr_en) begin - if (!(_T_866)) begin - if (io_ldst_dual_r) begin - ibuf_tag <= WrPtr1_r; - end else begin - ibuf_tag <= WrPtr0_r; - end + if (io_ldst_dual_r) begin + ibuf_tag <= WrPtr1_r; + end else begin + ibuf_tag <= WrPtr0_r; end end end @@ -72159,15 +71855,6 @@ end // initial ibuf_sz <= ibuf_sz_in; end end - always @(posedge io_lsu_busm_clk or posedge reset) begin - if (reset) begin - obuf_wr_timer <= 3'h0; - end else if (obuf_wr_en) begin - obuf_wr_timer <= 3'h0; - end else if (_T_1058) begin - obuf_wr_timer <= _T_1060; - end - end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_nomerge_0 <= 1'h0; @@ -72418,24 +72105,6 @@ end // initial buf_dualhi_0 <= buf_dualhi_in[0]; end end - always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin - if (reset) begin - obuf_sz <= 2'h0; - end else if (obuf_wr_en) begin - if (ibuf_buf_byp) begin - obuf_sz <= ibuf_sz_in; - end else begin - obuf_sz <= _T_1302; - end - end - end - always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin - if (reset) begin - obuf_byteen <= 8'h0; - end else if (obuf_wr_en) begin - obuf_byteen <= obuf_byteen_in; - end - end always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin if (reset) begin obuf_data <= 64'h0; @@ -72715,7 +72384,6 @@ module lsu_bus_intf( output io_tlu_busbuff_lsu_pmu_bus_error, output io_tlu_busbuff_lsu_pmu_bus_busy, input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, - input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, output io_tlu_busbuff_lsu_imprecise_error_load_any, output io_tlu_busbuff_lsu_imprecise_error_store_any, @@ -72732,24 +72400,14 @@ module lsu_bus_intf( input io_axi_aw_ready, output io_axi_aw_valid, output [2:0] io_axi_aw_bits_id, - output [31:0] io_axi_aw_bits_addr, - output [3:0] io_axi_aw_bits_region, - output [2:0] io_axi_aw_bits_size, - output [3:0] io_axi_aw_bits_cache, input io_axi_w_ready, output io_axi_w_valid, output [63:0] io_axi_w_bits_data, - output [7:0] io_axi_w_bits_strb, input io_axi_b_valid, - input [1:0] io_axi_b_bits_resp, input [2:0] io_axi_b_bits_id, input io_axi_ar_ready, output io_axi_ar_valid, output [2:0] io_axi_ar_bits_id, - output [31:0] io_axi_ar_bits_addr, - output [3:0] io_axi_ar_bits_region, - output [2:0] io_axi_ar_bits_size, - output [3:0] io_axi_ar_bits_cache, input io_axi_r_valid, input [2:0] io_axi_r_bits_id, input [63:0] io_axi_r_bits_data, @@ -72810,7 +72468,6 @@ module lsu_bus_intf( wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 101:39] - wire bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 101:39] @@ -72859,25 +72516,15 @@ module lsu_bus_intf( wire bus_buffer_io_lsu_axi_aw_ready; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 101:39] wire [2:0] bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 101:39] - wire [31:0] bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 101:39] - wire [3:0] bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 101:39] - wire [2:0] bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 101:39] - wire [3:0] bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_lsu_axi_w_ready; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 101:39] wire [63:0] bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 101:39] - wire [7:0] bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_lsu_axi_b_ready; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_lsu_axi_b_valid; // @[lsu_bus_intf.scala 101:39] - wire [1:0] bus_buffer_io_lsu_axi_b_bits_resp; // @[lsu_bus_intf.scala 101:39] wire [2:0] bus_buffer_io_lsu_axi_b_bits_id; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_lsu_axi_ar_ready; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 101:39] wire [2:0] bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 101:39] - wire [31:0] bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 101:39] - wire [3:0] bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 101:39] - wire [2:0] bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 101:39] - wire [3:0] bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_lsu_axi_r_ready; // @[lsu_bus_intf.scala 101:39] wire bus_buffer_io_lsu_axi_r_valid; // @[lsu_bus_intf.scala 101:39] wire [2:0] bus_buffer_io_lsu_axi_r_bits_id; // @[lsu_bus_intf.scala 101:39] @@ -73083,7 +72730,6 @@ module lsu_bus_intf( .io_tlu_busbuff_lsu_pmu_bus_error(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error), .io_tlu_busbuff_lsu_pmu_bus_busy(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy), .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), - .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any), .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any), @@ -73132,25 +72778,15 @@ module lsu_bus_intf( .io_lsu_axi_aw_ready(bus_buffer_io_lsu_axi_aw_ready), .io_lsu_axi_aw_valid(bus_buffer_io_lsu_axi_aw_valid), .io_lsu_axi_aw_bits_id(bus_buffer_io_lsu_axi_aw_bits_id), - .io_lsu_axi_aw_bits_addr(bus_buffer_io_lsu_axi_aw_bits_addr), - .io_lsu_axi_aw_bits_region(bus_buffer_io_lsu_axi_aw_bits_region), - .io_lsu_axi_aw_bits_size(bus_buffer_io_lsu_axi_aw_bits_size), - .io_lsu_axi_aw_bits_cache(bus_buffer_io_lsu_axi_aw_bits_cache), .io_lsu_axi_w_ready(bus_buffer_io_lsu_axi_w_ready), .io_lsu_axi_w_valid(bus_buffer_io_lsu_axi_w_valid), .io_lsu_axi_w_bits_data(bus_buffer_io_lsu_axi_w_bits_data), - .io_lsu_axi_w_bits_strb(bus_buffer_io_lsu_axi_w_bits_strb), .io_lsu_axi_b_ready(bus_buffer_io_lsu_axi_b_ready), .io_lsu_axi_b_valid(bus_buffer_io_lsu_axi_b_valid), - .io_lsu_axi_b_bits_resp(bus_buffer_io_lsu_axi_b_bits_resp), .io_lsu_axi_b_bits_id(bus_buffer_io_lsu_axi_b_bits_id), .io_lsu_axi_ar_ready(bus_buffer_io_lsu_axi_ar_ready), .io_lsu_axi_ar_valid(bus_buffer_io_lsu_axi_ar_valid), .io_lsu_axi_ar_bits_id(bus_buffer_io_lsu_axi_ar_bits_id), - .io_lsu_axi_ar_bits_addr(bus_buffer_io_lsu_axi_ar_bits_addr), - .io_lsu_axi_ar_bits_region(bus_buffer_io_lsu_axi_ar_bits_region), - .io_lsu_axi_ar_bits_size(bus_buffer_io_lsu_axi_ar_bits_size), - .io_lsu_axi_ar_bits_cache(bus_buffer_io_lsu_axi_ar_bits_cache), .io_lsu_axi_r_ready(bus_buffer_io_lsu_axi_r_ready), .io_lsu_axi_r_valid(bus_buffer_io_lsu_axi_r_valid), .io_lsu_axi_r_bits_id(bus_buffer_io_lsu_axi_r_bits_id), @@ -73176,19 +72812,10 @@ module lsu_bus_intf( assign io_tlu_busbuff_lsu_imprecise_error_addr_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 104:18] assign io_axi_aw_valid = bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 130:43] assign io_axi_aw_bits_id = bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 130:43] - assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 130:43] - assign io_axi_aw_bits_region = bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 130:43] - assign io_axi_aw_bits_size = bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 130:43] - assign io_axi_aw_bits_cache = bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 130:43] assign io_axi_w_valid = bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 130:43] assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 130:43] - assign io_axi_w_bits_strb = bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 130:43] assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 130:43] assign io_axi_ar_bits_id = bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 130:43] - assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 130:43] - assign io_axi_ar_bits_region = bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 130:43] - assign io_axi_ar_bits_size = bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 130:43] - assign io_axi_ar_bits_cache = bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 130:43] assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 133:38] assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 134:38] assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 135:38] @@ -73206,7 +72833,6 @@ module lsu_bus_intf( assign bus_buffer_reset = reset; assign bus_buffer_io_scan_mode = io_scan_mode; // @[lsu_bus_intf.scala 103:29] assign bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 104:18] - assign bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 104:18] assign bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 104:18] assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 106:51] assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 107:51] @@ -73244,7 +72870,6 @@ module lsu_bus_intf( assign bus_buffer_io_lsu_axi_aw_ready = io_axi_aw_ready; // @[lsu_bus_intf.scala 130:43] assign bus_buffer_io_lsu_axi_w_ready = io_axi_w_ready; // @[lsu_bus_intf.scala 130:43] assign bus_buffer_io_lsu_axi_b_valid = io_axi_b_valid; // @[lsu_bus_intf.scala 130:43] - assign bus_buffer_io_lsu_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu_bus_intf.scala 130:43] assign bus_buffer_io_lsu_axi_b_bits_id = io_axi_b_bits_id; // @[lsu_bus_intf.scala 130:43] assign bus_buffer_io_lsu_axi_ar_ready = io_axi_ar_ready; // @[lsu_bus_intf.scala 130:43] assign bus_buffer_io_lsu_axi_r_valid = io_axi_r_valid; // @[lsu_bus_intf.scala 130:43] @@ -73387,7 +73012,6 @@ module lsu( output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error, output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy, input io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable, - input io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable, input io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable, output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any, output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any, @@ -73415,24 +73039,14 @@ module lsu( input io_axi_aw_ready, output io_axi_aw_valid, output [2:0] io_axi_aw_bits_id, - output [31:0] io_axi_aw_bits_addr, - output [3:0] io_axi_aw_bits_region, - output [2:0] io_axi_aw_bits_size, - output [3:0] io_axi_aw_bits_cache, input io_axi_w_ready, output io_axi_w_valid, output [63:0] io_axi_w_bits_data, - output [7:0] io_axi_w_bits_strb, input io_axi_b_valid, - input [1:0] io_axi_b_bits_resp, input [2:0] io_axi_b_bits_id, input io_axi_ar_ready, output io_axi_ar_valid, output [2:0] io_axi_ar_bits_id, - output [31:0] io_axi_ar_bits_addr, - output [3:0] io_axi_ar_bits_region, - output [2:0] io_axi_ar_bits_size, - output [3:0] io_axi_ar_bits_cache, input io_axi_r_valid, input [2:0] io_axi_r_bits_id, input [63:0] io_axi_r_bits_data, @@ -73857,7 +73471,6 @@ module lsu( wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 68:30] - wire bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 68:30] @@ -73874,24 +73487,14 @@ module lsu( wire bus_intf_io_axi_aw_ready; // @[lsu.scala 68:30] wire bus_intf_io_axi_aw_valid; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_aw_bits_id; // @[lsu.scala 68:30] - wire [31:0] bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 68:30] - wire [3:0] bus_intf_io_axi_aw_bits_region; // @[lsu.scala 68:30] - wire [2:0] bus_intf_io_axi_aw_bits_size; // @[lsu.scala 68:30] - wire [3:0] bus_intf_io_axi_aw_bits_cache; // @[lsu.scala 68:30] wire bus_intf_io_axi_w_ready; // @[lsu.scala 68:30] wire bus_intf_io_axi_w_valid; // @[lsu.scala 68:30] wire [63:0] bus_intf_io_axi_w_bits_data; // @[lsu.scala 68:30] - wire [7:0] bus_intf_io_axi_w_bits_strb; // @[lsu.scala 68:30] wire bus_intf_io_axi_b_valid; // @[lsu.scala 68:30] - wire [1:0] bus_intf_io_axi_b_bits_resp; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_b_bits_id; // @[lsu.scala 68:30] wire bus_intf_io_axi_ar_ready; // @[lsu.scala 68:30] wire bus_intf_io_axi_ar_valid; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_ar_bits_id; // @[lsu.scala 68:30] - wire [31:0] bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 68:30] - wire [3:0] bus_intf_io_axi_ar_bits_region; // @[lsu.scala 68:30] - wire [2:0] bus_intf_io_axi_ar_bits_size; // @[lsu.scala 68:30] - wire [3:0] bus_intf_io_axi_ar_bits_cache; // @[lsu.scala 68:30] wire bus_intf_io_axi_r_valid; // @[lsu.scala 68:30] wire [2:0] bus_intf_io_axi_r_bits_id; // @[lsu.scala 68:30] wire [63:0] bus_intf_io_axi_r_bits_data; // @[lsu.scala 68:30] @@ -74342,7 +73945,6 @@ module lsu( .io_tlu_busbuff_lsu_pmu_bus_error(bus_intf_io_tlu_busbuff_lsu_pmu_bus_error), .io_tlu_busbuff_lsu_pmu_bus_busy(bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy), .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), - .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any), .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any), @@ -74359,24 +73961,14 @@ module lsu( .io_axi_aw_ready(bus_intf_io_axi_aw_ready), .io_axi_aw_valid(bus_intf_io_axi_aw_valid), .io_axi_aw_bits_id(bus_intf_io_axi_aw_bits_id), - .io_axi_aw_bits_addr(bus_intf_io_axi_aw_bits_addr), - .io_axi_aw_bits_region(bus_intf_io_axi_aw_bits_region), - .io_axi_aw_bits_size(bus_intf_io_axi_aw_bits_size), - .io_axi_aw_bits_cache(bus_intf_io_axi_aw_bits_cache), .io_axi_w_ready(bus_intf_io_axi_w_ready), .io_axi_w_valid(bus_intf_io_axi_w_valid), .io_axi_w_bits_data(bus_intf_io_axi_w_bits_data), - .io_axi_w_bits_strb(bus_intf_io_axi_w_bits_strb), .io_axi_b_valid(bus_intf_io_axi_b_valid), - .io_axi_b_bits_resp(bus_intf_io_axi_b_bits_resp), .io_axi_b_bits_id(bus_intf_io_axi_b_bits_id), .io_axi_ar_ready(bus_intf_io_axi_ar_ready), .io_axi_ar_valid(bus_intf_io_axi_ar_valid), .io_axi_ar_bits_id(bus_intf_io_axi_ar_bits_id), - .io_axi_ar_bits_addr(bus_intf_io_axi_ar_bits_addr), - .io_axi_ar_bits_region(bus_intf_io_axi_ar_bits_region), - .io_axi_ar_bits_size(bus_intf_io_axi_ar_bits_size), - .io_axi_ar_bits_cache(bus_intf_io_axi_ar_bits_cache), .io_axi_r_valid(bus_intf_io_axi_r_valid), .io_axi_r_bits_id(bus_intf_io_axi_r_bits_id), .io_axi_r_bits_data(bus_intf_io_axi_r_bits_data), @@ -74460,19 +74052,10 @@ module lsu( assign io_lsu_tlu_lsu_pmu_store_external_m = _T_50 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 106:39] assign io_axi_aw_valid = bus_intf_io_axi_aw_valid; // @[lsu.scala 314:49] assign io_axi_aw_bits_id = bus_intf_io_axi_aw_bits_id; // @[lsu.scala 314:49] - assign io_axi_aw_bits_addr = bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 314:49] - assign io_axi_aw_bits_region = bus_intf_io_axi_aw_bits_region; // @[lsu.scala 314:49] - assign io_axi_aw_bits_size = bus_intf_io_axi_aw_bits_size; // @[lsu.scala 314:49] - assign io_axi_aw_bits_cache = bus_intf_io_axi_aw_bits_cache; // @[lsu.scala 314:49] assign io_axi_w_valid = bus_intf_io_axi_w_valid; // @[lsu.scala 314:49] assign io_axi_w_bits_data = bus_intf_io_axi_w_bits_data; // @[lsu.scala 314:49] - assign io_axi_w_bits_strb = bus_intf_io_axi_w_bits_strb; // @[lsu.scala 314:49] assign io_axi_ar_valid = bus_intf_io_axi_ar_valid; // @[lsu.scala 314:49] assign io_axi_ar_bits_id = bus_intf_io_axi_ar_bits_id; // @[lsu.scala 314:49] - assign io_axi_ar_bits_addr = bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 314:49] - assign io_axi_ar_bits_region = bus_intf_io_axi_ar_bits_region; // @[lsu.scala 314:49] - assign io_axi_ar_bits_size = bus_intf_io_axi_ar_bits_size; // @[lsu.scala 314:49] - assign io_axi_ar_bits_cache = bus_intf_io_axi_ar_bits_cache; // @[lsu.scala 314:49] assign io_lsu_result_m = lsu_lsc_ctl_io_lsu_result_m; // @[lsu.scala 61:19] assign io_lsu_result_corr_r = lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 62:24] assign io_lsu_load_stall_any = bus_intf_io_lsu_bus_buffer_full_any | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 75:25] @@ -74707,7 +74290,6 @@ module lsu( assign bus_intf_reset = reset; assign bus_intf_io_scan_mode = io_scan_mode; // @[lsu.scala 285:49] assign bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 286:26] - assign bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 286:26] assign bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 286:26] assign bus_intf_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 287:49] assign bus_intf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 288:49] @@ -74721,7 +74303,6 @@ module lsu( assign bus_intf_io_axi_aw_ready = io_axi_aw_ready; // @[lsu.scala 314:49] assign bus_intf_io_axi_w_ready = io_axi_w_ready; // @[lsu.scala 314:49] assign bus_intf_io_axi_b_valid = io_axi_b_valid; // @[lsu.scala 314:49] - assign bus_intf_io_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu.scala 314:49] assign bus_intf_io_axi_b_bits_id = io_axi_b_bits_id; // @[lsu.scala 314:49] assign bus_intf_io_axi_ar_ready = io_axi_ar_ready; // @[lsu.scala 314:49] assign bus_intf_io_axi_r_valid = io_axi_r_valid; // @[lsu.scala 314:49] @@ -78491,28 +78072,10 @@ module dma_ctrl( input [2:0] io_iccm_dma_rtag, input [63:0] io_iccm_dma_rdata, input io_iccm_ready, - output io_dma_axi_aw_ready, - input io_dma_axi_aw_valid, - input io_dma_axi_aw_bits_id, - input [31:0] io_dma_axi_aw_bits_addr, - input [2:0] io_dma_axi_aw_bits_size, - output io_dma_axi_w_ready, - input io_dma_axi_w_valid, - input [63:0] io_dma_axi_w_bits_data, - input [7:0] io_dma_axi_w_bits_strb, - input io_dma_axi_b_ready, output io_dma_axi_b_valid, - output [1:0] io_dma_axi_b_bits_resp, - output io_dma_axi_b_bits_id, output io_dma_axi_ar_ready, input io_dma_axi_ar_valid, - input io_dma_axi_ar_bits_id, - input [31:0] io_dma_axi_ar_bits_addr, - input [2:0] io_dma_axi_ar_bits_size, - input io_dma_axi_r_ready, output io_dma_axi_r_valid, - output io_dma_axi_r_bits_id, - output [63:0] io_dma_axi_r_bits_data, output [1:0] io_dma_axi_r_bits_resp, output io_lsu_dma_dma_lsc_ctl_dma_dccm_req, output [31:0] io_lsu_dma_dma_lsc_ctl_dma_mem_addr, @@ -78585,36 +78148,20 @@ module dma_ctrl( reg [31:0] _RAND_46; reg [31:0] _RAND_47; reg [31:0] _RAND_48; - reg [63:0] _RAND_49; + reg [31:0] _RAND_49; reg [31:0] _RAND_50; reg [31:0] _RAND_51; reg [31:0] _RAND_52; reg [31:0] _RAND_53; reg [31:0] _RAND_54; reg [31:0] _RAND_55; - reg [31:0] _RAND_56; - reg [31:0] _RAND_57; - reg [31:0] _RAND_58; - reg [31:0] _RAND_59; - reg [31:0] _RAND_60; + reg [63:0] _RAND_56; + reg [63:0] _RAND_57; + reg [63:0] _RAND_58; + reg [63:0] _RAND_59; + reg [63:0] _RAND_60; reg [31:0] _RAND_61; reg [31:0] _RAND_62; - reg [31:0] _RAND_63; - reg [31:0] _RAND_64; - reg [63:0] _RAND_65; - reg [63:0] _RAND_66; - reg [63:0] _RAND_67; - reg [63:0] _RAND_68; - reg [63:0] _RAND_69; - reg [31:0] _RAND_70; - reg [31:0] _RAND_71; - reg [31:0] _RAND_72; - reg [31:0] _RAND_73; - reg [31:0] _RAND_74; - reg [31:0] _RAND_75; - reg [31:0] _RAND_76; - reg [31:0] _RAND_77; - reg [31:0] _RAND_78; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] wire rvclkhdr_io_clk; // @[lib.scala 368:23] @@ -78695,33 +78242,19 @@ module dma_ctrl( wire dma_mem_addr_in_pic = dma_mem_addr_int[31:15] == 17'h1e018; // @[lib.scala 361:39] wire dma_mem_addr_in_iccm = dma_mem_addr_int[31:16] == 16'hee00; // @[lib.scala 361:39] wire dma_bus_clk = dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 170:25 dma_ctrl.scala 405:28] - reg wrbuf_vld; // @[dma_ctrl.scala 415:59] - reg wrbuf_data_vld; // @[dma_ctrl.scala 417:59] - wire _T_1260 = wrbuf_vld & wrbuf_data_vld; // @[dma_ctrl.scala 473:43] reg rdbuf_vld; // @[dma_ctrl.scala 441:47] - wire _T_1261 = _T_1260 & rdbuf_vld; // @[dma_ctrl.scala 473:60] - reg axi_mstr_priority; // @[Reg.scala 27:20] - wire axi_mstr_sel = _T_1261 ? axi_mstr_priority : _T_1260; // @[dma_ctrl.scala 473:31] - reg [31:0] wrbuf_addr; // @[lib.scala 374:16] - reg [31:0] rdbuf_addr; // @[lib.scala 374:16] - wire [31:0] bus_cmd_addr = axi_mstr_sel ? wrbuf_addr : rdbuf_addr; // @[dma_ctrl.scala 463:43] wire [2:0] _GEN_90 = {{2'd0}, io_dbg_dma_dbg_ib_dbg_cmd_addr[2]}; // @[dma_ctrl.scala 195:91] wire [3:0] _T_17 = 3'h4 * _GEN_90; // @[dma_ctrl.scala 195:91] wire [18:0] _T_18 = 19'hf << _T_17; // @[dma_ctrl.scala 195:83] - reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] - wire [18:0] _T_20 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_18 : {{11'd0}, wrbuf_byteen}; // @[dma_ctrl.scala 195:34] + wire [18:0] _T_20 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_18 : 19'h0; // @[dma_ctrl.scala 195:34] wire [2:0] _T_23 = {1'h0,io_dbg_cmd_size}; // @[Cat.scala 29:58] - reg [2:0] wrbuf_sz; // @[Reg.scala 27:20] - reg [2:0] rdbuf_sz; // @[Reg.scala 27:20] - wire [2:0] bus_cmd_sz = axi_mstr_sel ? wrbuf_sz : rdbuf_sz; // @[dma_ctrl.scala 464:45] - wire [2:0] fifo_sz_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_23 : bus_cmd_sz; // @[dma_ctrl.scala 197:33] - wire fifo_write_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? io_dbg_dma_dbg_ib_dbg_cmd_write : axi_mstr_sel; // @[dma_ctrl.scala 199:33] - wire bus_cmd_valid = _T_1260 | rdbuf_vld; // @[dma_ctrl.scala 459:69] + wire [2:0] fifo_sz_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_23 : 3'h0; // @[dma_ctrl.scala 197:33] + wire fifo_write_in = io_dbg_dma_dbg_ib_dbg_cmd_valid & io_dbg_dma_dbg_ib_dbg_cmd_write; // @[dma_ctrl.scala 199:33] reg fifo_full; // @[dma_ctrl.scala 373:12] reg dbg_dma_bubble_bus; // @[dma_ctrl.scala 377:12] wire _T_989 = fifo_full | dbg_dma_bubble_bus; // @[dma_ctrl.scala 299:39] wire dma_fifo_ready = ~_T_989; // @[dma_ctrl.scala 299:27] - wire axi_mstr_prty_en = bus_cmd_valid & dma_fifo_ready; // @[dma_ctrl.scala 460:54] + wire axi_mstr_prty_en = rdbuf_vld & dma_fifo_ready; // @[dma_ctrl.scala 460:54] wire _T_28 = axi_mstr_prty_en & io_dma_bus_clk_en; // @[dma_ctrl.scala 206:80] wire _T_31 = io_dbg_dma_dbg_ib_dbg_cmd_valid & io_dbg_dma_dbg_ib_dbg_cmd_type[1]; // @[dma_ctrl.scala 206:136] wire _T_32 = _T_28 | _T_31; // @[dma_ctrl.scala 206:101] @@ -79011,9 +78544,7 @@ module dma_ctrl( wire _T_399 = fifo_done_en[4] | fifo_done[4]; // @[dma_ctrl.scala 218:75] wire _T_400 = _T_399 & io_dma_bus_clk_en; // @[dma_ctrl.scala 218:91] wire [4:0] fifo_done_bus_en = {_T_400,_T_396,_T_392,_T_388,_T_384}; // @[Cat.scala 29:58] - wire _T_1285 = io_dma_axi_b_valid & io_dma_axi_b_ready; // @[dma_ctrl.scala 502:61] - wire _T_1286 = io_dma_axi_r_valid & io_dma_axi_r_ready; // @[dma_ctrl.scala 502:105] - wire bus_rsp_sent = _T_1285 | _T_1286; // @[dma_ctrl.scala 502:83] + wire bus_rsp_sent = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 502:83] wire _T_406 = bus_rsp_sent & io_dma_bus_clk_en; // @[dma_ctrl.scala 220:99] wire _T_407 = _T_406 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 220:120] reg [2:0] RspPtr; // @[Reg.scala 27:20] @@ -79031,8 +78562,7 @@ module dma_ctrl( wire _T_491 = fifo_error_en[0] & _T_269; // @[dma_ctrl.scala 224:77] wire [63:0] _T_493 = {32'h0,fifo_addr_0}; // @[Cat.scala 29:58] wire [63:0] _T_498 = {io_dbg_dma_dbg_dctl_dbg_cmd_wrdata,io_dbg_dma_dbg_dctl_dbg_cmd_wrdata}; // @[Cat.scala 29:58] - reg [63:0] wrbuf_data; // @[lib.scala 374:16] - wire [63:0] _T_500 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_498 : wrbuf_data; // @[dma_ctrl.scala 224:347] + wire [63:0] _T_500 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_498 : 64'h0; // @[dma_ctrl.scala 224:347] wire _T_506 = fifo_error_en[1] & _T_276; // @[dma_ctrl.scala 224:77] wire [63:0] _T_508 = {32'h0,fifo_addr_1}; // @[Cat.scala 29:58] wire _T_521 = fifo_error_en[2] & _T_283; // @[dma_ctrl.scala 224:77] @@ -79095,14 +78625,6 @@ module dma_ctrl( reg [63:0] fifo_data_2; // @[lib.scala 374:16] reg [63:0] fifo_data_3; // @[lib.scala 374:16] reg [63:0] fifo_data_4; // @[lib.scala 374:16] - reg fifo_tag_0; // @[Reg.scala 27:20] - reg wrbuf_tag; // @[Reg.scala 27:20] - reg rdbuf_tag; // @[Reg.scala 27:20] - wire bus_cmd_tag = axi_mstr_sel ? wrbuf_tag : rdbuf_tag; // @[dma_ctrl.scala 467:43] - reg fifo_tag_1; // @[Reg.scala 27:20] - reg fifo_tag_2; // @[Reg.scala 27:20] - reg fifo_tag_3; // @[Reg.scala 27:20] - reg fifo_tag_4; // @[Reg.scala 27:20] wire _T_931 = WrPtr == 3'h4; // @[dma_ctrl.scala 260:30] wire [2:0] _T_934 = WrPtr + 3'h1; // @[dma_ctrl.scala 260:76] wire _T_936 = RdPtr == 3'h4; // @[dma_ctrl.scala 262:30] @@ -79167,38 +78689,20 @@ module dma_ctrl( wire [63:0] _GEN_76 = 3'h2 == RdPtr ? fifo_data_2 : _GEN_75; // @[dma_ctrl.scala 361:40] wire [63:0] _GEN_77 = 3'h3 == RdPtr ? fifo_data_3 : _GEN_76; // @[dma_ctrl.scala 361:40] reg dma_dbg_cmd_done_q; // @[dma_ctrl.scala 381:12] - wire _T_1212 = bus_cmd_valid & io_dma_bus_clk_en; // @[dma_ctrl.scala 386:44] + wire _T_1212 = rdbuf_vld & io_dma_bus_clk_en; // @[dma_ctrl.scala 386:44] wire _T_1213 = _T_1212 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 386:65] - wire bus_rsp_valid = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 501:60] - wire _T_1214 = bus_cmd_valid | bus_rsp_valid; // @[dma_ctrl.scala 387:44] + wire _T_1214 = rdbuf_vld | bus_rsp_sent; // @[dma_ctrl.scala 387:44] wire _T_1215 = _T_1214 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 387:60] wire _T_1216 = _T_1215 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 387:94] wire _T_1217 = _T_1216 | dma_dbg_cmd_done_q; // @[dma_ctrl.scala 387:116] wire _T_1219 = _T_1217 | _T_1143; // @[dma_ctrl.scala 387:137] - wire wrbuf_en = io_dma_axi_aw_valid & io_dma_axi_aw_ready; // @[dma_ctrl.scala 409:47] - wire wrbuf_data_en = io_dma_axi_w_valid & io_dma_axi_w_ready; // @[dma_ctrl.scala 410:46] - wire wrbuf_cmd_sent = axi_mstr_prty_en & axi_mstr_sel; // @[dma_ctrl.scala 411:40] - wire _T_1221 = ~wrbuf_en; // @[dma_ctrl.scala 412:51] - wire wrbuf_rst = wrbuf_cmd_sent & _T_1221; // @[dma_ctrl.scala 412:49] - wire _T_1223 = ~wrbuf_data_en; // @[dma_ctrl.scala 413:51] - wire wrbuf_data_rst = wrbuf_cmd_sent & _T_1223; // @[dma_ctrl.scala 413:49] - wire _T_1224 = wrbuf_en | wrbuf_vld; // @[dma_ctrl.scala 415:63] - wire _T_1225 = ~wrbuf_rst; // @[dma_ctrl.scala 415:92] - wire _T_1228 = wrbuf_data_en | wrbuf_data_vld; // @[dma_ctrl.scala 417:63] - wire _T_1229 = ~wrbuf_data_rst; // @[dma_ctrl.scala 417:102] wire rdbuf_en = io_dma_axi_ar_valid & io_dma_axi_ar_ready; // @[dma_ctrl.scala 437:59] - wire _T_1234 = ~axi_mstr_sel; // @[dma_ctrl.scala 438:44] - wire rdbuf_cmd_sent = axi_mstr_prty_en & _T_1234; // @[dma_ctrl.scala 438:42] wire _T_1236 = ~rdbuf_en; // @[dma_ctrl.scala 439:63] - wire rdbuf_rst = rdbuf_cmd_sent & _T_1236; // @[dma_ctrl.scala 439:61] + wire rdbuf_rst = axi_mstr_prty_en & _T_1236; // @[dma_ctrl.scala 439:61] wire _T_1237 = rdbuf_en | rdbuf_vld; // @[dma_ctrl.scala 441:51] wire _T_1238 = ~rdbuf_rst; // @[dma_ctrl.scala 441:80] - wire _T_1242 = ~wrbuf_cmd_sent; // @[dma_ctrl.scala 453:44] - wire _T_1243 = wrbuf_vld & _T_1242; // @[dma_ctrl.scala 453:42] - wire _T_1246 = wrbuf_data_vld & _T_1242; // @[dma_ctrl.scala 454:47] - wire _T_1248 = ~rdbuf_cmd_sent; // @[dma_ctrl.scala 455:44] + wire _T_1248 = ~axi_mstr_prty_en; // @[dma_ctrl.scala 455:44] wire _T_1249 = rdbuf_vld & _T_1248; // @[dma_ctrl.scala 455:42] - wire axi_mstr_prty_in = ~axi_mstr_priority; // @[dma_ctrl.scala 474:27] wire _T_1271 = ~_T_1108[0]; // @[dma_ctrl.scala 481:50] wire _T_1272 = _T_1106[0] & _T_1271; // @[dma_ctrl.scala 481:48] wire [4:0] _T_1273 = fifo_done_bus >> RspPtr; // @[dma_ctrl.scala 481:83] @@ -79206,9 +78710,6 @@ module dma_ctrl( wire [4:0] _T_1275 = fifo_write >> RspPtr; // @[dma_ctrl.scala 483:39] wire axi_rsp_write = _T_1275[0]; // @[dma_ctrl.scala 483:39] wire [1:0] _T_1278 = _GEN_57[1] ? 2'h3 : 2'h0; // @[dma_ctrl.scala 484:64] - wire _GEN_86 = 3'h1 == RspPtr ? fifo_tag_1 : fifo_tag_0; // @[dma_ctrl.scala 492:33] - wire _GEN_87 = 3'h2 == RspPtr ? fifo_tag_2 : _GEN_86; // @[dma_ctrl.scala 492:33] - wire _GEN_88 = 3'h3 == RspPtr ? fifo_tag_3 : _GEN_87; // @[dma_ctrl.scala 492:33] wire _T_1281 = ~axi_rsp_write; // @[dma_ctrl.scala 494:46] rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), @@ -79317,15 +78818,9 @@ module dma_ctrl( assign io_dec_dma_tlu_dma_dma_pmu_any_write = _T_165 & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 368:42] assign io_dec_dma_tlu_dma_dma_dccm_stall_any = _T_1137 & _T_1138; // @[dma_ctrl.scala 332:41] assign io_dec_dma_tlu_dma_dma_iccm_stall_any = io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[dma_ctrl.scala 334:41] - assign io_dma_axi_aw_ready = ~_T_1243; // @[dma_ctrl.scala 453:27] - assign io_dma_axi_w_ready = ~_T_1246; // @[dma_ctrl.scala 454:27] assign io_dma_axi_b_valid = axi_rsp_valid & axi_rsp_write; // @[dma_ctrl.scala 490:27] - assign io_dma_axi_b_bits_resp = _GEN_57[0] ? 2'h2 : _T_1278; // @[dma_ctrl.scala 491:41] - assign io_dma_axi_b_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 492:33] assign io_dma_axi_ar_ready = ~_T_1249; // @[dma_ctrl.scala 455:27] assign io_dma_axi_r_valid = axi_rsp_valid & _T_1281; // @[dma_ctrl.scala 494:27] - assign io_dma_axi_r_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 498:37] - assign io_dma_axi_r_bits_data = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 496:43] assign io_dma_axi_r_bits_resp = _GEN_57[0] ? 2'h2 : _T_1278; // @[dma_ctrl.scala 495:41] assign io_lsu_dma_dma_lsc_ctl_dma_dccm_req = _T_1137 & io_lsu_dma_dccm_ready; // @[dma_ctrl.scala 352:40] assign io_lsu_dma_dma_lsc_ctl_dma_mem_addr = _T_1184 ? _T_1188 : dma_mem_addr_int; // @[dma_ctrl.scala 357:40] @@ -79382,10 +78877,10 @@ module dma_ctrl( assign dma_bus_cgc_io_en = io_dma_bus_clk_en; // @[dma_ctrl.scala 402:28] assign dma_bus_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 403:28] assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_10_io_en = wrbuf_en & io_dma_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_10_io_en = 1'h0; // @[lib.scala 371:17] assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_11_io_en = wrbuf_data_en & io_dma_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_11_io_en = 1'h0; // @[lib.scala 371:17] assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_12_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_12_io_en = rdbuf_en & io_dma_bus_clk_en; // @[lib.scala 371:17] @@ -79438,151 +78933,119 @@ initial begin _RAND_5 = {1{`RANDOM}}; fifo_addr_0 = _RAND_5[31:0]; _RAND_6 = {1{`RANDOM}}; - wrbuf_vld = _RAND_6[0:0]; + rdbuf_vld = _RAND_6[0:0]; _RAND_7 = {1{`RANDOM}}; - wrbuf_data_vld = _RAND_7[0:0]; + fifo_full = _RAND_7[0:0]; _RAND_8 = {1{`RANDOM}}; - rdbuf_vld = _RAND_8[0:0]; + dbg_dma_bubble_bus = _RAND_8[0:0]; _RAND_9 = {1{`RANDOM}}; - axi_mstr_priority = _RAND_9[0:0]; + WrPtr = _RAND_9[2:0]; _RAND_10 = {1{`RANDOM}}; - wrbuf_addr = _RAND_10[31:0]; + _T_598 = _RAND_10[0:0]; _RAND_11 = {1{`RANDOM}}; - rdbuf_addr = _RAND_11[31:0]; + _T_591 = _RAND_11[0:0]; _RAND_12 = {1{`RANDOM}}; - wrbuf_byteen = _RAND_12[7:0]; + _T_584 = _RAND_12[0:0]; _RAND_13 = {1{`RANDOM}}; - wrbuf_sz = _RAND_13[2:0]; + _T_577 = _RAND_13[0:0]; _RAND_14 = {1{`RANDOM}}; - rdbuf_sz = _RAND_14[2:0]; + _T_570 = _RAND_14[0:0]; _RAND_15 = {1{`RANDOM}}; - fifo_full = _RAND_15[0:0]; + _T_760 = _RAND_15[0:0]; _RAND_16 = {1{`RANDOM}}; - dbg_dma_bubble_bus = _RAND_16[0:0]; + _T_753 = _RAND_16[0:0]; _RAND_17 = {1{`RANDOM}}; - WrPtr = _RAND_17[2:0]; + _T_746 = _RAND_17[0:0]; _RAND_18 = {1{`RANDOM}}; - _T_598 = _RAND_18[0:0]; + _T_739 = _RAND_18[0:0]; _RAND_19 = {1{`RANDOM}}; - _T_591 = _RAND_19[0:0]; + _T_732 = _RAND_19[0:0]; _RAND_20 = {1{`RANDOM}}; - _T_584 = _RAND_20[0:0]; + _T_886 = _RAND_20[0:0]; _RAND_21 = {1{`RANDOM}}; - _T_577 = _RAND_21[0:0]; + _T_884 = _RAND_21[0:0]; _RAND_22 = {1{`RANDOM}}; - _T_570 = _RAND_22[0:0]; + _T_882 = _RAND_22[0:0]; _RAND_23 = {1{`RANDOM}}; - _T_760 = _RAND_23[0:0]; + _T_880 = _RAND_23[0:0]; _RAND_24 = {1{`RANDOM}}; - _T_753 = _RAND_24[0:0]; + _T_878 = _RAND_24[0:0]; _RAND_25 = {1{`RANDOM}}; - _T_746 = _RAND_25[0:0]; + fifo_sz_4 = _RAND_25[2:0]; _RAND_26 = {1{`RANDOM}}; - _T_739 = _RAND_26[0:0]; + fifo_sz_3 = _RAND_26[2:0]; _RAND_27 = {1{`RANDOM}}; - _T_732 = _RAND_27[0:0]; + fifo_sz_2 = _RAND_27[2:0]; _RAND_28 = {1{`RANDOM}}; - _T_886 = _RAND_28[0:0]; + fifo_sz_1 = _RAND_28[2:0]; _RAND_29 = {1{`RANDOM}}; - _T_884 = _RAND_29[0:0]; + fifo_sz_0 = _RAND_29[2:0]; _RAND_30 = {1{`RANDOM}}; - _T_882 = _RAND_30[0:0]; + fifo_byteen_4 = _RAND_30[7:0]; _RAND_31 = {1{`RANDOM}}; - _T_880 = _RAND_31[0:0]; + fifo_byteen_3 = _RAND_31[7:0]; _RAND_32 = {1{`RANDOM}}; - _T_878 = _RAND_32[0:0]; + fifo_byteen_2 = _RAND_32[7:0]; _RAND_33 = {1{`RANDOM}}; - fifo_sz_4 = _RAND_33[2:0]; + fifo_byteen_1 = _RAND_33[7:0]; _RAND_34 = {1{`RANDOM}}; - fifo_sz_3 = _RAND_34[2:0]; + fifo_byteen_0 = _RAND_34[7:0]; _RAND_35 = {1{`RANDOM}}; - fifo_sz_2 = _RAND_35[2:0]; + fifo_error_0 = _RAND_35[1:0]; _RAND_36 = {1{`RANDOM}}; - fifo_sz_1 = _RAND_36[2:0]; + fifo_error_1 = _RAND_36[1:0]; _RAND_37 = {1{`RANDOM}}; - fifo_sz_0 = _RAND_37[2:0]; + fifo_error_2 = _RAND_37[1:0]; _RAND_38 = {1{`RANDOM}}; - fifo_byteen_4 = _RAND_38[7:0]; + fifo_error_3 = _RAND_38[1:0]; _RAND_39 = {1{`RANDOM}}; - fifo_byteen_3 = _RAND_39[7:0]; + fifo_error_4 = _RAND_39[1:0]; _RAND_40 = {1{`RANDOM}}; - fifo_byteen_2 = _RAND_40[7:0]; + RspPtr = _RAND_40[2:0]; _RAND_41 = {1{`RANDOM}}; - fifo_byteen_1 = _RAND_41[7:0]; + _T_721 = _RAND_41[0:0]; _RAND_42 = {1{`RANDOM}}; - fifo_byteen_0 = _RAND_42[7:0]; + _T_714 = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; - fifo_error_0 = _RAND_43[1:0]; + _T_707 = _RAND_43[0:0]; _RAND_44 = {1{`RANDOM}}; - fifo_error_1 = _RAND_44[1:0]; + _T_700 = _RAND_44[0:0]; _RAND_45 = {1{`RANDOM}}; - fifo_error_2 = _RAND_45[1:0]; + _T_693 = _RAND_45[0:0]; _RAND_46 = {1{`RANDOM}}; - fifo_error_3 = _RAND_46[1:0]; + _T_799 = _RAND_46[0:0]; _RAND_47 = {1{`RANDOM}}; - fifo_error_4 = _RAND_47[1:0]; + _T_792 = _RAND_47[0:0]; _RAND_48 = {1{`RANDOM}}; - RspPtr = _RAND_48[2:0]; - _RAND_49 = {2{`RANDOM}}; - wrbuf_data = _RAND_49[63:0]; + _T_785 = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + _T_778 = _RAND_49[0:0]; _RAND_50 = {1{`RANDOM}}; - _T_721 = _RAND_50[0:0]; + _T_771 = _RAND_50[0:0]; _RAND_51 = {1{`RANDOM}}; - _T_714 = _RAND_51[0:0]; + _T_850 = _RAND_51[0:0]; _RAND_52 = {1{`RANDOM}}; - _T_707 = _RAND_52[0:0]; + _T_852 = _RAND_52[0:0]; _RAND_53 = {1{`RANDOM}}; - _T_700 = _RAND_53[0:0]; + _T_854 = _RAND_53[0:0]; _RAND_54 = {1{`RANDOM}}; - _T_693 = _RAND_54[0:0]; + _T_856 = _RAND_54[0:0]; _RAND_55 = {1{`RANDOM}}; - _T_799 = _RAND_55[0:0]; - _RAND_56 = {1{`RANDOM}}; - _T_792 = _RAND_56[0:0]; - _RAND_57 = {1{`RANDOM}}; - _T_785 = _RAND_57[0:0]; - _RAND_58 = {1{`RANDOM}}; - _T_778 = _RAND_58[0:0]; - _RAND_59 = {1{`RANDOM}}; - _T_771 = _RAND_59[0:0]; - _RAND_60 = {1{`RANDOM}}; - _T_850 = _RAND_60[0:0]; + _T_858 = _RAND_55[0:0]; + _RAND_56 = {2{`RANDOM}}; + fifo_data_0 = _RAND_56[63:0]; + _RAND_57 = {2{`RANDOM}}; + fifo_data_1 = _RAND_57[63:0]; + _RAND_58 = {2{`RANDOM}}; + fifo_data_2 = _RAND_58[63:0]; + _RAND_59 = {2{`RANDOM}}; + fifo_data_3 = _RAND_59[63:0]; + _RAND_60 = {2{`RANDOM}}; + fifo_data_4 = _RAND_60[63:0]; _RAND_61 = {1{`RANDOM}}; - _T_852 = _RAND_61[0:0]; + dma_nack_count = _RAND_61[2:0]; _RAND_62 = {1{`RANDOM}}; - _T_854 = _RAND_62[0:0]; - _RAND_63 = {1{`RANDOM}}; - _T_856 = _RAND_63[0:0]; - _RAND_64 = {1{`RANDOM}}; - _T_858 = _RAND_64[0:0]; - _RAND_65 = {2{`RANDOM}}; - fifo_data_0 = _RAND_65[63:0]; - _RAND_66 = {2{`RANDOM}}; - fifo_data_1 = _RAND_66[63:0]; - _RAND_67 = {2{`RANDOM}}; - fifo_data_2 = _RAND_67[63:0]; - _RAND_68 = {2{`RANDOM}}; - fifo_data_3 = _RAND_68[63:0]; - _RAND_69 = {2{`RANDOM}}; - fifo_data_4 = _RAND_69[63:0]; - _RAND_70 = {1{`RANDOM}}; - fifo_tag_0 = _RAND_70[0:0]; - _RAND_71 = {1{`RANDOM}}; - wrbuf_tag = _RAND_71[0:0]; - _RAND_72 = {1{`RANDOM}}; - rdbuf_tag = _RAND_72[0:0]; - _RAND_73 = {1{`RANDOM}}; - fifo_tag_1 = _RAND_73[0:0]; - _RAND_74 = {1{`RANDOM}}; - fifo_tag_2 = _RAND_74[0:0]; - _RAND_75 = {1{`RANDOM}}; - fifo_tag_3 = _RAND_75[0:0]; - _RAND_76 = {1{`RANDOM}}; - fifo_tag_4 = _RAND_76[0:0]; - _RAND_77 = {1{`RANDOM}}; - dma_nack_count = _RAND_77[2:0]; - _RAND_78 = {1{`RANDOM}}; - dma_dbg_cmd_done_q = _RAND_78[0:0]; + dma_dbg_cmd_done_q = _RAND_62[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin RdPtr = 3'h0; @@ -79602,33 +79065,9 @@ initial begin if (reset) begin fifo_addr_0 = 32'h0; end - if (reset) begin - wrbuf_vld = 1'h0; - end - if (reset) begin - wrbuf_data_vld = 1'h0; - end if (reset) begin rdbuf_vld = 1'h0; end - if (reset) begin - axi_mstr_priority = 1'h0; - end - if (reset) begin - wrbuf_addr = 32'h0; - end - if (reset) begin - rdbuf_addr = 32'h0; - end - if (reset) begin - wrbuf_byteen = 8'h0; - end - if (reset) begin - wrbuf_sz = 3'h0; - end - if (reset) begin - rdbuf_sz = 3'h0; - end if (reset) begin fifo_full = 1'h0; end @@ -79731,9 +79170,6 @@ initial begin if (reset) begin RspPtr = 3'h0; end - if (reset) begin - wrbuf_data = 64'h0; - end if (reset) begin _T_721 = 1'h0; end @@ -79794,27 +79230,6 @@ initial begin if (reset) begin fifo_data_4 = 64'h0; end - if (reset) begin - fifo_tag_0 = 1'h0; - end - if (reset) begin - wrbuf_tag = 1'h0; - end - if (reset) begin - rdbuf_tag = 1'h0; - end - if (reset) begin - fifo_tag_1 = 1'h0; - end - if (reset) begin - fifo_tag_2 = 1'h0; - end - if (reset) begin - fifo_tag_3 = 1'h0; - end - if (reset) begin - fifo_tag_4 = 1'h0; - end if (reset) begin dma_nack_count = 3'h0; end @@ -79843,10 +79258,8 @@ end // initial fifo_addr_4 <= 32'h0; end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_addr_4 <= io_dbg_dma_dbg_ib_dbg_cmd_addr; - end else if (axi_mstr_sel) begin - fifo_addr_4 <= wrbuf_addr; end else begin - fifo_addr_4 <= rdbuf_addr; + fifo_addr_4 <= 32'h0; end end always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin @@ -79854,10 +79267,8 @@ end // initial fifo_addr_3 <= 32'h0; end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_addr_3 <= io_dbg_dma_dbg_ib_dbg_cmd_addr; - end else if (axi_mstr_sel) begin - fifo_addr_3 <= wrbuf_addr; end else begin - fifo_addr_3 <= rdbuf_addr; + fifo_addr_3 <= 32'h0; end end always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin @@ -79865,10 +79276,8 @@ end // initial fifo_addr_2 <= 32'h0; end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_addr_2 <= io_dbg_dma_dbg_ib_dbg_cmd_addr; - end else if (axi_mstr_sel) begin - fifo_addr_2 <= wrbuf_addr; end else begin - fifo_addr_2 <= rdbuf_addr; + fifo_addr_2 <= 32'h0; end end always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin @@ -79876,10 +79285,8 @@ end // initial fifo_addr_1 <= 32'h0; end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_addr_1 <= io_dbg_dma_dbg_ib_dbg_cmd_addr; - end else if (axi_mstr_sel) begin - fifo_addr_1 <= wrbuf_addr; end else begin - fifo_addr_1 <= rdbuf_addr; + fifo_addr_1 <= 32'h0; end end always @(posedge rvclkhdr_io_l1clk or posedge reset) begin @@ -79888,21 +79295,7 @@ end // initial end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_addr_0 <= io_dbg_dma_dbg_ib_dbg_cmd_addr; end else begin - fifo_addr_0 <= bus_cmd_addr; - end - end - always @(posedge dma_bus_clk or posedge reset) begin - if (reset) begin - wrbuf_vld <= 1'h0; - end else begin - wrbuf_vld <= _T_1224 & _T_1225; - end - end - always @(posedge dma_bus_clk or posedge reset) begin - if (reset) begin - wrbuf_data_vld <= 1'h0; - end else begin - wrbuf_data_vld <= _T_1228 & _T_1229; + fifo_addr_0 <= 32'h0; end end always @(posedge dma_bus_clk or posedge reset) begin @@ -79912,48 +79305,6 @@ end // initial rdbuf_vld <= _T_1237 & _T_1238; end end - always @(posedge dma_bus_clk or posedge reset) begin - if (reset) begin - axi_mstr_priority <= 1'h0; - end else if (axi_mstr_prty_en) begin - axi_mstr_priority <= axi_mstr_prty_in; - end - end - always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin - if (reset) begin - wrbuf_addr <= 32'h0; - end else begin - wrbuf_addr <= io_dma_axi_aw_bits_addr; - end - end - always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin - if (reset) begin - rdbuf_addr <= 32'h0; - end else begin - rdbuf_addr <= io_dma_axi_ar_bits_addr; - end - end - always @(posedge dma_bus_clk or posedge reset) begin - if (reset) begin - wrbuf_byteen <= 8'h0; - end else if (wrbuf_data_en) begin - wrbuf_byteen <= io_dma_axi_w_bits_strb; - end - end - always @(posedge dma_bus_clk or posedge reset) begin - if (reset) begin - wrbuf_sz <= 3'h0; - end else if (wrbuf_en) begin - wrbuf_sz <= io_dma_axi_aw_bits_size; - end - end - always @(posedge dma_bus_clk or posedge reset) begin - if (reset) begin - rdbuf_sz <= 3'h0; - end else if (rdbuf_en) begin - rdbuf_sz <= io_dma_axi_ar_bits_size; - end - end always @(posedge dma_bus_clk or posedge reset) begin if (reset) begin fifo_full <= 1'h0; @@ -80090,10 +79441,8 @@ end // initial end else if (fifo_cmd_en[4]) begin if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_sz_4 <= _T_23; - end else if (axi_mstr_sel) begin - fifo_sz_4 <= wrbuf_sz; end else begin - fifo_sz_4 <= rdbuf_sz; + fifo_sz_4 <= 3'h0; end end end @@ -80103,10 +79452,8 @@ end // initial end else if (fifo_cmd_en[3]) begin if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_sz_3 <= _T_23; - end else if (axi_mstr_sel) begin - fifo_sz_3 <= wrbuf_sz; end else begin - fifo_sz_3 <= rdbuf_sz; + fifo_sz_3 <= 3'h0; end end end @@ -80116,10 +79463,8 @@ end // initial end else if (fifo_cmd_en[2]) begin if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_sz_2 <= _T_23; - end else if (axi_mstr_sel) begin - fifo_sz_2 <= wrbuf_sz; end else begin - fifo_sz_2 <= rdbuf_sz; + fifo_sz_2 <= 3'h0; end end end @@ -80129,10 +79474,8 @@ end // initial end else if (fifo_cmd_en[1]) begin if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_sz_1 <= _T_23; - end else if (axi_mstr_sel) begin - fifo_sz_1 <= wrbuf_sz; end else begin - fifo_sz_1 <= rdbuf_sz; + fifo_sz_1 <= 3'h0; end end end @@ -80224,13 +79567,6 @@ end // initial end end end - always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin - if (reset) begin - wrbuf_data <= 64'h0; - end else begin - wrbuf_data <= io_dma_axi_w_bits_data; - end - end always @(posedge dma_free_clk or posedge reset) begin if (reset) begin _T_721 <= 1'h0; @@ -80305,52 +79641,28 @@ end // initial if (reset) begin _T_850 <= 1'h0; end else if (fifo_cmd_en[0]) begin - if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin - _T_850 <= io_dbg_dma_dbg_ib_dbg_cmd_write; - end else if (_T_1261) begin - _T_850 <= axi_mstr_priority; - end else begin - _T_850 <= _T_1260; - end + _T_850 <= fifo_write_in; end end always @(posedge dma_buffer_c1_clk or posedge reset) begin if (reset) begin _T_852 <= 1'h0; end else if (fifo_cmd_en[1]) begin - if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin - _T_852 <= io_dbg_dma_dbg_ib_dbg_cmd_write; - end else if (_T_1261) begin - _T_852 <= axi_mstr_priority; - end else begin - _T_852 <= _T_1260; - end + _T_852 <= fifo_write_in; end end always @(posedge dma_buffer_c1_clk or posedge reset) begin if (reset) begin _T_854 <= 1'h0; end else if (fifo_cmd_en[2]) begin - if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin - _T_854 <= io_dbg_dma_dbg_ib_dbg_cmd_write; - end else if (_T_1261) begin - _T_854 <= axi_mstr_priority; - end else begin - _T_854 <= _T_1260; - end + _T_854 <= fifo_write_in; end end always @(posedge dma_buffer_c1_clk or posedge reset) begin if (reset) begin _T_856 <= 1'h0; end else if (fifo_cmd_en[3]) begin - if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin - _T_856 <= io_dbg_dma_dbg_ib_dbg_cmd_write; - end else if (_T_1261) begin - _T_856 <= axi_mstr_priority; - end else begin - _T_856 <= _T_1260; - end + _T_856 <= fifo_write_in; end end always @(posedge dma_buffer_c1_clk or posedge reset) begin @@ -80372,7 +79684,7 @@ end // initial end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_data_0 <= _T_498; end else begin - fifo_data_0 <= wrbuf_data; + fifo_data_0 <= 64'h0; end end always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin @@ -80387,7 +79699,7 @@ end // initial end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_data_1 <= _T_498; end else begin - fifo_data_1 <= wrbuf_data; + fifo_data_1 <= 64'h0; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin @@ -80402,7 +79714,7 @@ end // initial end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_data_2 <= _T_498; end else begin - fifo_data_2 <= wrbuf_data; + fifo_data_2 <= 64'h0; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin @@ -80417,7 +79729,7 @@ end // initial end else if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin fifo_data_3 <= _T_498; end else begin - fifo_data_3 <= wrbuf_data; + fifo_data_3 <= 64'h0; end end always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin @@ -80433,71 +79745,6 @@ end // initial fifo_data_4 <= _T_500; end end - always @(posedge dma_buffer_c1_clk or posedge reset) begin - if (reset) begin - fifo_tag_0 <= 1'h0; - end else if (fifo_cmd_en[0]) begin - if (axi_mstr_sel) begin - fifo_tag_0 <= wrbuf_tag; - end else begin - fifo_tag_0 <= rdbuf_tag; - end - end - end - always @(posedge dma_bus_clk or posedge reset) begin - if (reset) begin - wrbuf_tag <= 1'h0; - end else if (wrbuf_en) begin - wrbuf_tag <= io_dma_axi_aw_bits_id; - end - end - always @(posedge dma_bus_clk or posedge reset) begin - if (reset) begin - rdbuf_tag <= 1'h0; - end else if (rdbuf_en) begin - rdbuf_tag <= io_dma_axi_ar_bits_id; - end - end - always @(posedge dma_buffer_c1_clk or posedge reset) begin - if (reset) begin - fifo_tag_1 <= 1'h0; - end else if (fifo_cmd_en[1]) begin - if (axi_mstr_sel) begin - fifo_tag_1 <= wrbuf_tag; - end else begin - fifo_tag_1 <= rdbuf_tag; - end - end - end - always @(posedge dma_buffer_c1_clk or posedge reset) begin - if (reset) begin - fifo_tag_2 <= 1'h0; - end else if (fifo_cmd_en[2]) begin - if (axi_mstr_sel) begin - fifo_tag_2 <= wrbuf_tag; - end else begin - fifo_tag_2 <= rdbuf_tag; - end - end - end - always @(posedge dma_buffer_c1_clk or posedge reset) begin - if (reset) begin - fifo_tag_3 <= 1'h0; - end else if (fifo_cmd_en[3]) begin - if (axi_mstr_sel) begin - fifo_tag_3 <= wrbuf_tag; - end else begin - fifo_tag_3 <= rdbuf_tag; - end - end - end - always @(posedge dma_buffer_c1_clk or posedge reset) begin - if (reset) begin - fifo_tag_4 <= 1'h0; - end else if (fifo_cmd_en[4]) begin - fifo_tag_4 <= bus_cmd_tag; - end - end always @(posedge dma_free_clk or posedge reset) begin if (reset) begin dma_nack_count <= 3'h0; @@ -80520,22 +79767,40 @@ end // initial end endmodule module axi4_to_ahb( - input clock, - input reset, - input io_scan_mode, - input io_bus_clk_en, - input io_clk_override, - output io_axi_aw_ready, - input io_axi_aw_valid, - output io_axi_w_ready, - input io_axi_w_valid, - input io_axi_b_ready, - input io_axi_ar_valid + input clock, + input reset, + input io_scan_mode, + input io_bus_clk_en, + input io_clk_override, + output io_axi_aw_ready, + input io_axi_aw_valid, + input io_axi_aw_bits_id, + output io_axi_w_ready, + input io_axi_w_valid, + input [63:0] io_axi_w_bits_data, + input io_axi_b_ready, + output io_axi_b_valid, + output [1:0] io_axi_b_bits_resp, + output io_axi_b_bits_id, + output io_axi_ar_ready, + input io_axi_ar_valid, + input io_axi_ar_bits_id, + output io_axi_r_valid, + output io_axi_r_bits_id, + output [63:0] io_axi_r_bits_data, + output [1:0] io_axi_r_bits_resp ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; reg [31:0] _RAND_1; reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [63:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [63:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] wire rvclkhdr_io_clk; // @[lib.scala 343:22] @@ -80636,6 +79901,27 @@ module axi4_to_ahb( wire [2:0] _GEN_68 = _T_136 ? _T_154 : _GEN_50; // @[Conditional.scala 39:67] wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] + reg wrbuf_tag; // @[Reg.scala 27:20] + reg [63:0] wrbuf_data; // @[lib.scala 374:16] + wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 258:55] + wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 258:39] + wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67] + wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] + wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] + wire _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_136 ? buf_state_en : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] + wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] + wire _T_25 = slave_valid_pre & io_axi_b_ready; // @[axi4_to_ahb.scala 156:33] + wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 125:21 axi4_to_ahb.scala 339:12] + reg slvbuf_write; // @[Reg.scala 27:20] + wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 292:23] + wire [3:0] slave_opc = {_T_596,2'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 157:55] + reg slvbuf_tag; // @[Reg.scala 27:20] + wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 160:66] + wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 293:91] + reg [63:0] buf_data; // @[lib.scala 374:16] wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 167:57] wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 167:94] wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 167:76] @@ -80664,6 +79950,8 @@ module axi4_to_ahb( wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] + wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 275:33] + reg buf_write; // @[Reg.scala 27:20] wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 298:49] wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 299:52] wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 300:49] @@ -80674,9 +79962,11 @@ module axi4_to_ahb( wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 303:22] wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 304:38] wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 304:21] + wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 305:22] wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 308:55] wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 308:91] wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 309:55] + reg buf_tag; // @[Reg.scala 27:20] wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 334:43] wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 334:58] wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 336:50] @@ -80743,6 +80033,14 @@ module axi4_to_ahb( ); assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 303:19] assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 304:18] + assign io_axi_b_valid = _T_25 & slave_opc[3]; // @[axi4_to_ahb.scala 156:18] + assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 157:22] + assign io_axi_b_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 158:20] + assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 305:19] + assign io_axi_r_valid = _T_25 & _T_35; // @[axi4_to_ahb.scala 160:18] + assign io_axi_r_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 162:20] + assign io_axi_r_bits_data = _T_604 ? buf_data : 64'h0; // @[axi4_to_ahb.scala 163:22] + assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 161:22] assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] @@ -80814,6 +80112,20 @@ initial begin wrbuf_vld = _RAND_1[0:0]; _RAND_2 = {1{`RANDOM}}; wrbuf_data_vld = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + wrbuf_tag = _RAND_3[0:0]; + _RAND_4 = {2{`RANDOM}}; + wrbuf_data = _RAND_4[63:0]; + _RAND_5 = {1{`RANDOM}}; + slvbuf_write = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + slvbuf_tag = _RAND_6[0:0]; + _RAND_7 = {2{`RANDOM}}; + buf_data = _RAND_7[63:0]; + _RAND_8 = {1{`RANDOM}}; + buf_write = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + buf_tag = _RAND_9[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin buf_state = 3'h0; @@ -80824,6 +80136,27 @@ initial begin if (reset) begin wrbuf_data_vld = 1'h0; end + if (reset) begin + wrbuf_tag = 1'h0; + end + if (reset) begin + wrbuf_data = 64'h0; + end + if (reset) begin + slvbuf_write = 1'h0; + end + if (reset) begin + slvbuf_tag = 1'h0; + end + if (reset) begin + buf_data = 64'h0; + end + if (reset) begin + buf_write = 1'h0; + end + if (reset) begin + buf_tag = 1'h0; + end `endif // RANDOMIZE end // initial `ifdef FIRRTL_AFTER_INITIAL @@ -80889,13 +80222,81 @@ end // initial wrbuf_data_vld <= _T_641 & _T_637; end end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_tag <= 1'h0; + end else if (wrbuf_en) begin + wrbuf_tag <= io_axi_aw_bits_id; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + wrbuf_data <= 64'h0; + end else begin + wrbuf_data <= io_axi_w_bits_data; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + slvbuf_write <= 1'h0; + end else if (slvbuf_wr_en) begin + slvbuf_write <= buf_write; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + slvbuf_tag <= 1'h0; + end else if (slvbuf_wr_en) begin + slvbuf_tag <= buf_tag; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + buf_data <= 64'h0; + end else if (_T_489) begin + buf_data <= 64'h0; + end else begin + buf_data <= wrbuf_data; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_write <= 1'h0; + end else if (buf_wr_en) begin + if (_T_49) begin + buf_write <= _T_51; + end else if (_T_101) begin + buf_write <= 1'h0; + end else if (_T_136) begin + buf_write <= 1'h0; + end else if (_T_175) begin + buf_write <= 1'h0; + end else if (_T_186) begin + buf_write <= 1'h0; + end else if (_T_188) begin + buf_write <= 1'h0; + end else begin + buf_write <= _GEN_8; + end + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_tag <= 1'h0; + end else if (buf_wr_en) begin + if (wr_cmd_vld) begin + buf_tag <= wrbuf_tag; + end else begin + buf_tag <= io_axi_ar_bits_id; + end + end + end endmodule module ahb_to_axi4( input clock, input reset, input io_scan_mode, input io_bus_clk_en, - input io_axi_aw_ready, output io_axi_aw_valid, input io_axi_ar_ready, output io_axi_ar_valid, @@ -80939,9 +80340,8 @@ module ahb_to_axi4( wire _T_12 = 2'h1 == buf_state; // @[Conditional.scala 37:30] wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 58:33 ahb_to_axi4.scala 181:27] reg cmdbuf_vld; // @[ahb_to_axi4.scala 140:61] - wire _T_151 = io_axi_aw_valid & io_axi_aw_ready; // @[ahb_to_axi4.scala 138:67] wire _T_152 = io_axi_ar_valid & io_axi_ar_ready; // @[ahb_to_axi4.scala 138:105] - wire _T_153 = _T_151 | _T_152; // @[ahb_to_axi4.scala 138:86] + wire _T_153 = io_axi_aw_valid | _T_152; // @[ahb_to_axi4.scala 138:86] wire _T_154 = ~_T_153; // @[ahb_to_axi4.scala 138:48] wire cmdbuf_full = cmdbuf_vld & _T_154; // @[ahb_to_axi4.scala 138:46] wire _T_21 = ~cmdbuf_full; // @[ahb_to_axi4.scala 81:24] @@ -81141,82 +80541,6 @@ endmodule module quasar( input clock, input reset, - input io_lsu_axi_aw_ready, - output io_lsu_axi_aw_valid, - output [2:0] io_lsu_axi_aw_bits_id, - output [31:0] io_lsu_axi_aw_bits_addr, - output [3:0] io_lsu_axi_aw_bits_region, - output [2:0] io_lsu_axi_aw_bits_size, - output [3:0] io_lsu_axi_aw_bits_cache, - input io_lsu_axi_w_ready, - output io_lsu_axi_w_valid, - output [63:0] io_lsu_axi_w_bits_data, - output [7:0] io_lsu_axi_w_bits_strb, - input io_lsu_axi_b_valid, - input [1:0] io_lsu_axi_b_bits_resp, - input [2:0] io_lsu_axi_b_bits_id, - input io_lsu_axi_ar_ready, - output io_lsu_axi_ar_valid, - output [2:0] io_lsu_axi_ar_bits_id, - output [31:0] io_lsu_axi_ar_bits_addr, - output [3:0] io_lsu_axi_ar_bits_region, - output [2:0] io_lsu_axi_ar_bits_size, - output [3:0] io_lsu_axi_ar_bits_cache, - input io_lsu_axi_r_valid, - input [2:0] io_lsu_axi_r_bits_id, - input [63:0] io_lsu_axi_r_bits_data, - input [1:0] io_lsu_axi_r_bits_resp, - input io_ifu_axi_ar_ready, - output io_ifu_axi_ar_valid, - output [2:0] io_ifu_axi_ar_bits_id, - output [31:0] io_ifu_axi_ar_bits_addr, - output [3:0] io_ifu_axi_ar_bits_region, - input io_ifu_axi_r_valid, - input [2:0] io_ifu_axi_r_bits_id, - input [63:0] io_ifu_axi_r_bits_data, - input [1:0] io_ifu_axi_r_bits_resp, - input io_sb_axi_aw_ready, - output io_sb_axi_aw_valid, - output [31:0] io_sb_axi_aw_bits_addr, - output [3:0] io_sb_axi_aw_bits_region, - output [2:0] io_sb_axi_aw_bits_size, - input io_sb_axi_w_ready, - output io_sb_axi_w_valid, - output [63:0] io_sb_axi_w_bits_data, - output [7:0] io_sb_axi_w_bits_strb, - input io_sb_axi_b_valid, - input [1:0] io_sb_axi_b_bits_resp, - input io_sb_axi_ar_ready, - output io_sb_axi_ar_valid, - output [31:0] io_sb_axi_ar_bits_addr, - output [3:0] io_sb_axi_ar_bits_region, - output [2:0] io_sb_axi_ar_bits_size, - input io_sb_axi_r_valid, - input [63:0] io_sb_axi_r_bits_data, - input [1:0] io_sb_axi_r_bits_resp, - output io_dma_axi_aw_ready, - input io_dma_axi_aw_valid, - input io_dma_axi_aw_bits_id, - input [31:0] io_dma_axi_aw_bits_addr, - input [2:0] io_dma_axi_aw_bits_size, - output io_dma_axi_w_ready, - input io_dma_axi_w_valid, - input [63:0] io_dma_axi_w_bits_data, - input [7:0] io_dma_axi_w_bits_strb, - input io_dma_axi_b_ready, - output io_dma_axi_b_valid, - output [1:0] io_dma_axi_b_bits_resp, - output io_dma_axi_b_bits_id, - output io_dma_axi_ar_ready, - input io_dma_axi_ar_valid, - input io_dma_axi_ar_bits_id, - input [31:0] io_dma_axi_ar_bits_addr, - input [2:0] io_dma_axi_ar_bits_size, - input io_dma_axi_r_ready, - output io_dma_axi_r_valid, - output io_dma_axi_r_bits_id, - output [63:0] io_dma_axi_r_bits_data, - output [1:0] io_dma_axi_r_bits_resp, input io_dbg_rst_l, input [30:0] io_rst_vec, input io_nmi_int, @@ -81407,8 +80731,6 @@ module quasar( wire ifu_io_ifu_ar_ready; // @[quasar.scala 72:19] wire ifu_io_ifu_ar_valid; // @[quasar.scala 72:19] wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 72:19] - wire [31:0] ifu_io_ifu_ar_bits_addr; // @[quasar.scala 72:19] - wire [3:0] ifu_io_ifu_ar_bits_region; // @[quasar.scala 72:19] wire ifu_io_ifu_r_valid; // @[quasar.scala 72:19] wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 72:19] wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 72:19] @@ -81667,7 +80989,6 @@ module quasar( wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 73:19] wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 73:19] wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 73:19] - wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 73:19] wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 73:19] wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 73:19] wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 73:19] @@ -81720,21 +81041,14 @@ module quasar( wire [31:0] dbg_io_dmi_reg_wdata; // @[quasar.scala 74:19] wire dbg_io_sb_axi_aw_ready; // @[quasar.scala 74:19] wire dbg_io_sb_axi_aw_valid; // @[quasar.scala 74:19] - wire [31:0] dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 74:19] - wire [3:0] dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 74:19] - wire [2:0] dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 74:19] wire dbg_io_sb_axi_w_ready; // @[quasar.scala 74:19] wire dbg_io_sb_axi_w_valid; // @[quasar.scala 74:19] wire [63:0] dbg_io_sb_axi_w_bits_data; // @[quasar.scala 74:19] - wire [7:0] dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 74:19] wire dbg_io_sb_axi_b_ready; // @[quasar.scala 74:19] wire dbg_io_sb_axi_b_valid; // @[quasar.scala 74:19] wire [1:0] dbg_io_sb_axi_b_bits_resp; // @[quasar.scala 74:19] wire dbg_io_sb_axi_ar_ready; // @[quasar.scala 74:19] wire dbg_io_sb_axi_ar_valid; // @[quasar.scala 74:19] - wire [31:0] dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 74:19] - wire [3:0] dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 74:19] - wire [2:0] dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 74:19] wire dbg_io_sb_axi_r_ready; // @[quasar.scala 74:19] wire dbg_io_sb_axi_r_valid; // @[quasar.scala 74:19] wire [63:0] dbg_io_sb_axi_r_bits_data; // @[quasar.scala 74:19] @@ -81888,7 +81202,6 @@ module quasar( wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 76:19] wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 76:19] wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 76:19] - wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 76:19] wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 76:19] wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 76:19] wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 76:19] @@ -81916,24 +81229,14 @@ module quasar( wire lsu_io_axi_aw_ready; // @[quasar.scala 76:19] wire lsu_io_axi_aw_valid; // @[quasar.scala 76:19] wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 76:19] - wire [31:0] lsu_io_axi_aw_bits_addr; // @[quasar.scala 76:19] - wire [3:0] lsu_io_axi_aw_bits_region; // @[quasar.scala 76:19] - wire [2:0] lsu_io_axi_aw_bits_size; // @[quasar.scala 76:19] - wire [3:0] lsu_io_axi_aw_bits_cache; // @[quasar.scala 76:19] wire lsu_io_axi_w_ready; // @[quasar.scala 76:19] wire lsu_io_axi_w_valid; // @[quasar.scala 76:19] wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 76:19] - wire [7:0] lsu_io_axi_w_bits_strb; // @[quasar.scala 76:19] wire lsu_io_axi_b_valid; // @[quasar.scala 76:19] - wire [1:0] lsu_io_axi_b_bits_resp; // @[quasar.scala 76:19] wire [2:0] lsu_io_axi_b_bits_id; // @[quasar.scala 76:19] wire lsu_io_axi_ar_ready; // @[quasar.scala 76:19] wire lsu_io_axi_ar_valid; // @[quasar.scala 76:19] wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 76:19] - wire [31:0] lsu_io_axi_ar_bits_addr; // @[quasar.scala 76:19] - wire [3:0] lsu_io_axi_ar_bits_region; // @[quasar.scala 76:19] - wire [2:0] lsu_io_axi_ar_bits_size; // @[quasar.scala 76:19] - wire [3:0] lsu_io_axi_ar_bits_cache; // @[quasar.scala 76:19] wire lsu_io_axi_r_valid; // @[quasar.scala 76:19] wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 76:19] wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 76:19] @@ -82045,28 +81348,10 @@ module quasar( wire [2:0] dma_ctrl_io_iccm_dma_rtag; // @[quasar.scala 78:24] wire [63:0] dma_ctrl_io_iccm_dma_rdata; // @[quasar.scala 78:24] wire dma_ctrl_io_iccm_ready; // @[quasar.scala 78:24] - wire dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 78:24] - wire dma_ctrl_io_dma_axi_aw_valid; // @[quasar.scala 78:24] - wire dma_ctrl_io_dma_axi_aw_bits_id; // @[quasar.scala 78:24] - wire [31:0] dma_ctrl_io_dma_axi_aw_bits_addr; // @[quasar.scala 78:24] - wire [2:0] dma_ctrl_io_dma_axi_aw_bits_size; // @[quasar.scala 78:24] - wire dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 78:24] - wire dma_ctrl_io_dma_axi_w_valid; // @[quasar.scala 78:24] - wire [63:0] dma_ctrl_io_dma_axi_w_bits_data; // @[quasar.scala 78:24] - wire [7:0] dma_ctrl_io_dma_axi_w_bits_strb; // @[quasar.scala 78:24] - wire dma_ctrl_io_dma_axi_b_ready; // @[quasar.scala 78:24] wire dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 78:24] - wire [1:0] dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 78:24] - wire dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 78:24] wire dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 78:24] wire dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 78:24] - wire dma_ctrl_io_dma_axi_ar_bits_id; // @[quasar.scala 78:24] - wire [31:0] dma_ctrl_io_dma_axi_ar_bits_addr; // @[quasar.scala 78:24] - wire [2:0] dma_ctrl_io_dma_axi_ar_bits_size; // @[quasar.scala 78:24] - wire dma_ctrl_io_dma_axi_r_ready; // @[quasar.scala 78:24] wire dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 78:24] - wire dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 78:24] - wire [63:0] dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 78:24] wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 78:24] wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 78:24] wire [31:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 78:24] @@ -82103,10 +81388,21 @@ module quasar( wire axi4_to_ahb_io_clk_override; // @[quasar.scala 242:32] wire axi4_to_ahb_io_axi_aw_ready; // @[quasar.scala 242:32] wire axi4_to_ahb_io_axi_aw_valid; // @[quasar.scala 242:32] + wire axi4_to_ahb_io_axi_aw_bits_id; // @[quasar.scala 242:32] wire axi4_to_ahb_io_axi_w_ready; // @[quasar.scala 242:32] wire axi4_to_ahb_io_axi_w_valid; // @[quasar.scala 242:32] + wire [63:0] axi4_to_ahb_io_axi_w_bits_data; // @[quasar.scala 242:32] wire axi4_to_ahb_io_axi_b_ready; // @[quasar.scala 242:32] + wire axi4_to_ahb_io_axi_b_valid; // @[quasar.scala 242:32] + wire [1:0] axi4_to_ahb_io_axi_b_bits_resp; // @[quasar.scala 242:32] + wire axi4_to_ahb_io_axi_b_bits_id; // @[quasar.scala 242:32] + wire axi4_to_ahb_io_axi_ar_ready; // @[quasar.scala 242:32] wire axi4_to_ahb_io_axi_ar_valid; // @[quasar.scala 242:32] + wire axi4_to_ahb_io_axi_ar_bits_id; // @[quasar.scala 242:32] + wire axi4_to_ahb_io_axi_r_valid; // @[quasar.scala 242:32] + wire axi4_to_ahb_io_axi_r_bits_id; // @[quasar.scala 242:32] + wire [63:0] axi4_to_ahb_io_axi_r_bits_data; // @[quasar.scala 242:32] + wire [1:0] axi4_to_ahb_io_axi_r_bits_resp; // @[quasar.scala 242:32] wire axi4_to_ahb_1_clock; // @[quasar.scala 243:33] wire axi4_to_ahb_1_reset; // @[quasar.scala 243:33] wire axi4_to_ahb_1_io_scan_mode; // @[quasar.scala 243:33] @@ -82114,10 +81410,21 @@ module quasar( wire axi4_to_ahb_1_io_clk_override; // @[quasar.scala 243:33] wire axi4_to_ahb_1_io_axi_aw_ready; // @[quasar.scala 243:33] wire axi4_to_ahb_1_io_axi_aw_valid; // @[quasar.scala 243:33] + wire axi4_to_ahb_1_io_axi_aw_bits_id; // @[quasar.scala 243:33] wire axi4_to_ahb_1_io_axi_w_ready; // @[quasar.scala 243:33] wire axi4_to_ahb_1_io_axi_w_valid; // @[quasar.scala 243:33] + wire [63:0] axi4_to_ahb_1_io_axi_w_bits_data; // @[quasar.scala 243:33] wire axi4_to_ahb_1_io_axi_b_ready; // @[quasar.scala 243:33] + wire axi4_to_ahb_1_io_axi_b_valid; // @[quasar.scala 243:33] + wire [1:0] axi4_to_ahb_1_io_axi_b_bits_resp; // @[quasar.scala 243:33] + wire axi4_to_ahb_1_io_axi_b_bits_id; // @[quasar.scala 243:33] + wire axi4_to_ahb_1_io_axi_ar_ready; // @[quasar.scala 243:33] wire axi4_to_ahb_1_io_axi_ar_valid; // @[quasar.scala 243:33] + wire axi4_to_ahb_1_io_axi_ar_bits_id; // @[quasar.scala 243:33] + wire axi4_to_ahb_1_io_axi_r_valid; // @[quasar.scala 243:33] + wire axi4_to_ahb_1_io_axi_r_bits_id; // @[quasar.scala 243:33] + wire [63:0] axi4_to_ahb_1_io_axi_r_bits_data; // @[quasar.scala 243:33] + wire [1:0] axi4_to_ahb_1_io_axi_r_bits_resp; // @[quasar.scala 243:33] wire axi4_to_ahb_2_clock; // @[quasar.scala 244:33] wire axi4_to_ahb_2_reset; // @[quasar.scala 244:33] wire axi4_to_ahb_2_io_scan_mode; // @[quasar.scala 244:33] @@ -82125,15 +81432,25 @@ module quasar( wire axi4_to_ahb_2_io_clk_override; // @[quasar.scala 244:33] wire axi4_to_ahb_2_io_axi_aw_ready; // @[quasar.scala 244:33] wire axi4_to_ahb_2_io_axi_aw_valid; // @[quasar.scala 244:33] + wire axi4_to_ahb_2_io_axi_aw_bits_id; // @[quasar.scala 244:33] wire axi4_to_ahb_2_io_axi_w_ready; // @[quasar.scala 244:33] wire axi4_to_ahb_2_io_axi_w_valid; // @[quasar.scala 244:33] + wire [63:0] axi4_to_ahb_2_io_axi_w_bits_data; // @[quasar.scala 244:33] wire axi4_to_ahb_2_io_axi_b_ready; // @[quasar.scala 244:33] + wire axi4_to_ahb_2_io_axi_b_valid; // @[quasar.scala 244:33] + wire [1:0] axi4_to_ahb_2_io_axi_b_bits_resp; // @[quasar.scala 244:33] + wire axi4_to_ahb_2_io_axi_b_bits_id; // @[quasar.scala 244:33] + wire axi4_to_ahb_2_io_axi_ar_ready; // @[quasar.scala 244:33] wire axi4_to_ahb_2_io_axi_ar_valid; // @[quasar.scala 244:33] + wire axi4_to_ahb_2_io_axi_ar_bits_id; // @[quasar.scala 244:33] + wire axi4_to_ahb_2_io_axi_r_valid; // @[quasar.scala 244:33] + wire axi4_to_ahb_2_io_axi_r_bits_id; // @[quasar.scala 244:33] + wire [63:0] axi4_to_ahb_2_io_axi_r_bits_data; // @[quasar.scala 244:33] + wire [1:0] axi4_to_ahb_2_io_axi_r_bits_resp; // @[quasar.scala 244:33] wire ahb_to_axi4_clock; // @[quasar.scala 245:33] wire ahb_to_axi4_reset; // @[quasar.scala 245:33] wire ahb_to_axi4_io_scan_mode; // @[quasar.scala 245:33] wire ahb_to_axi4_io_bus_clk_en; // @[quasar.scala 245:33] - wire ahb_to_axi4_io_axi_aw_ready; // @[quasar.scala 245:33] wire ahb_to_axi4_io_axi_aw_valid; // @[quasar.scala 245:33] wire ahb_to_axi4_io_axi_ar_ready; // @[quasar.scala 245:33] wire ahb_to_axi4_io_axi_ar_valid; // @[quasar.scala 245:33] @@ -82251,8 +81568,6 @@ module quasar( .io_ifu_ar_ready(ifu_io_ifu_ar_ready), .io_ifu_ar_valid(ifu_io_ifu_ar_valid), .io_ifu_ar_bits_id(ifu_io_ifu_ar_bits_id), - .io_ifu_ar_bits_addr(ifu_io_ifu_ar_bits_addr), - .io_ifu_ar_bits_region(ifu_io_ifu_ar_bits_region), .io_ifu_r_valid(ifu_io_ifu_r_valid), .io_ifu_r_bits_id(ifu_io_ifu_r_bits_id), .io_ifu_r_bits_data(ifu_io_ifu_r_bits_data), @@ -82513,7 +81828,6 @@ module quasar( .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error), .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy), .io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable), - .io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any(dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any(dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any), @@ -82568,21 +81882,14 @@ module quasar( .io_dmi_reg_wdata(dbg_io_dmi_reg_wdata), .io_sb_axi_aw_ready(dbg_io_sb_axi_aw_ready), .io_sb_axi_aw_valid(dbg_io_sb_axi_aw_valid), - .io_sb_axi_aw_bits_addr(dbg_io_sb_axi_aw_bits_addr), - .io_sb_axi_aw_bits_region(dbg_io_sb_axi_aw_bits_region), - .io_sb_axi_aw_bits_size(dbg_io_sb_axi_aw_bits_size), .io_sb_axi_w_ready(dbg_io_sb_axi_w_ready), .io_sb_axi_w_valid(dbg_io_sb_axi_w_valid), .io_sb_axi_w_bits_data(dbg_io_sb_axi_w_bits_data), - .io_sb_axi_w_bits_strb(dbg_io_sb_axi_w_bits_strb), .io_sb_axi_b_ready(dbg_io_sb_axi_b_ready), .io_sb_axi_b_valid(dbg_io_sb_axi_b_valid), .io_sb_axi_b_bits_resp(dbg_io_sb_axi_b_bits_resp), .io_sb_axi_ar_ready(dbg_io_sb_axi_ar_ready), .io_sb_axi_ar_valid(dbg_io_sb_axi_ar_valid), - .io_sb_axi_ar_bits_addr(dbg_io_sb_axi_ar_bits_addr), - .io_sb_axi_ar_bits_region(dbg_io_sb_axi_ar_bits_region), - .io_sb_axi_ar_bits_size(dbg_io_sb_axi_ar_bits_size), .io_sb_axi_r_ready(dbg_io_sb_axi_r_ready), .io_sb_axi_r_valid(dbg_io_sb_axi_r_valid), .io_sb_axi_r_bits_data(dbg_io_sb_axi_r_bits_data), @@ -82740,7 +82047,6 @@ module quasar( .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error), .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy), .io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable), - .io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any(lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any(lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any), @@ -82768,24 +82074,14 @@ module quasar( .io_axi_aw_ready(lsu_io_axi_aw_ready), .io_axi_aw_valid(lsu_io_axi_aw_valid), .io_axi_aw_bits_id(lsu_io_axi_aw_bits_id), - .io_axi_aw_bits_addr(lsu_io_axi_aw_bits_addr), - .io_axi_aw_bits_region(lsu_io_axi_aw_bits_region), - .io_axi_aw_bits_size(lsu_io_axi_aw_bits_size), - .io_axi_aw_bits_cache(lsu_io_axi_aw_bits_cache), .io_axi_w_ready(lsu_io_axi_w_ready), .io_axi_w_valid(lsu_io_axi_w_valid), .io_axi_w_bits_data(lsu_io_axi_w_bits_data), - .io_axi_w_bits_strb(lsu_io_axi_w_bits_strb), .io_axi_b_valid(lsu_io_axi_b_valid), - .io_axi_b_bits_resp(lsu_io_axi_b_bits_resp), .io_axi_b_bits_id(lsu_io_axi_b_bits_id), .io_axi_ar_ready(lsu_io_axi_ar_ready), .io_axi_ar_valid(lsu_io_axi_ar_valid), .io_axi_ar_bits_id(lsu_io_axi_ar_bits_id), - .io_axi_ar_bits_addr(lsu_io_axi_ar_bits_addr), - .io_axi_ar_bits_region(lsu_io_axi_ar_bits_region), - .io_axi_ar_bits_size(lsu_io_axi_ar_bits_size), - .io_axi_ar_bits_cache(lsu_io_axi_ar_bits_cache), .io_axi_r_valid(lsu_io_axi_r_valid), .io_axi_r_bits_id(lsu_io_axi_r_bits_id), .io_axi_r_bits_data(lsu_io_axi_r_bits_data), @@ -82901,28 +82197,10 @@ module quasar( .io_iccm_dma_rtag(dma_ctrl_io_iccm_dma_rtag), .io_iccm_dma_rdata(dma_ctrl_io_iccm_dma_rdata), .io_iccm_ready(dma_ctrl_io_iccm_ready), - .io_dma_axi_aw_ready(dma_ctrl_io_dma_axi_aw_ready), - .io_dma_axi_aw_valid(dma_ctrl_io_dma_axi_aw_valid), - .io_dma_axi_aw_bits_id(dma_ctrl_io_dma_axi_aw_bits_id), - .io_dma_axi_aw_bits_addr(dma_ctrl_io_dma_axi_aw_bits_addr), - .io_dma_axi_aw_bits_size(dma_ctrl_io_dma_axi_aw_bits_size), - .io_dma_axi_w_ready(dma_ctrl_io_dma_axi_w_ready), - .io_dma_axi_w_valid(dma_ctrl_io_dma_axi_w_valid), - .io_dma_axi_w_bits_data(dma_ctrl_io_dma_axi_w_bits_data), - .io_dma_axi_w_bits_strb(dma_ctrl_io_dma_axi_w_bits_strb), - .io_dma_axi_b_ready(dma_ctrl_io_dma_axi_b_ready), .io_dma_axi_b_valid(dma_ctrl_io_dma_axi_b_valid), - .io_dma_axi_b_bits_resp(dma_ctrl_io_dma_axi_b_bits_resp), - .io_dma_axi_b_bits_id(dma_ctrl_io_dma_axi_b_bits_id), .io_dma_axi_ar_ready(dma_ctrl_io_dma_axi_ar_ready), .io_dma_axi_ar_valid(dma_ctrl_io_dma_axi_ar_valid), - .io_dma_axi_ar_bits_id(dma_ctrl_io_dma_axi_ar_bits_id), - .io_dma_axi_ar_bits_addr(dma_ctrl_io_dma_axi_ar_bits_addr), - .io_dma_axi_ar_bits_size(dma_ctrl_io_dma_axi_ar_bits_size), - .io_dma_axi_r_ready(dma_ctrl_io_dma_axi_r_ready), .io_dma_axi_r_valid(dma_ctrl_io_dma_axi_r_valid), - .io_dma_axi_r_bits_id(dma_ctrl_io_dma_axi_r_bits_id), - .io_dma_axi_r_bits_data(dma_ctrl_io_dma_axi_r_bits_data), .io_dma_axi_r_bits_resp(dma_ctrl_io_dma_axi_r_bits_resp), .io_lsu_dma_dma_lsc_ctl_dma_dccm_req(dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req), .io_lsu_dma_dma_lsc_ctl_dma_mem_addr(dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr), @@ -82965,10 +82243,21 @@ module quasar( .io_clk_override(axi4_to_ahb_io_clk_override), .io_axi_aw_ready(axi4_to_ahb_io_axi_aw_ready), .io_axi_aw_valid(axi4_to_ahb_io_axi_aw_valid), + .io_axi_aw_bits_id(axi4_to_ahb_io_axi_aw_bits_id), .io_axi_w_ready(axi4_to_ahb_io_axi_w_ready), .io_axi_w_valid(axi4_to_ahb_io_axi_w_valid), + .io_axi_w_bits_data(axi4_to_ahb_io_axi_w_bits_data), .io_axi_b_ready(axi4_to_ahb_io_axi_b_ready), - .io_axi_ar_valid(axi4_to_ahb_io_axi_ar_valid) + .io_axi_b_valid(axi4_to_ahb_io_axi_b_valid), + .io_axi_b_bits_resp(axi4_to_ahb_io_axi_b_bits_resp), + .io_axi_b_bits_id(axi4_to_ahb_io_axi_b_bits_id), + .io_axi_ar_ready(axi4_to_ahb_io_axi_ar_ready), + .io_axi_ar_valid(axi4_to_ahb_io_axi_ar_valid), + .io_axi_ar_bits_id(axi4_to_ahb_io_axi_ar_bits_id), + .io_axi_r_valid(axi4_to_ahb_io_axi_r_valid), + .io_axi_r_bits_id(axi4_to_ahb_io_axi_r_bits_id), + .io_axi_r_bits_data(axi4_to_ahb_io_axi_r_bits_data), + .io_axi_r_bits_resp(axi4_to_ahb_io_axi_r_bits_resp) ); axi4_to_ahb axi4_to_ahb_1 ( // @[quasar.scala 243:33] .clock(axi4_to_ahb_1_clock), @@ -82978,10 +82267,21 @@ module quasar( .io_clk_override(axi4_to_ahb_1_io_clk_override), .io_axi_aw_ready(axi4_to_ahb_1_io_axi_aw_ready), .io_axi_aw_valid(axi4_to_ahb_1_io_axi_aw_valid), + .io_axi_aw_bits_id(axi4_to_ahb_1_io_axi_aw_bits_id), .io_axi_w_ready(axi4_to_ahb_1_io_axi_w_ready), .io_axi_w_valid(axi4_to_ahb_1_io_axi_w_valid), + .io_axi_w_bits_data(axi4_to_ahb_1_io_axi_w_bits_data), .io_axi_b_ready(axi4_to_ahb_1_io_axi_b_ready), - .io_axi_ar_valid(axi4_to_ahb_1_io_axi_ar_valid) + .io_axi_b_valid(axi4_to_ahb_1_io_axi_b_valid), + .io_axi_b_bits_resp(axi4_to_ahb_1_io_axi_b_bits_resp), + .io_axi_b_bits_id(axi4_to_ahb_1_io_axi_b_bits_id), + .io_axi_ar_ready(axi4_to_ahb_1_io_axi_ar_ready), + .io_axi_ar_valid(axi4_to_ahb_1_io_axi_ar_valid), + .io_axi_ar_bits_id(axi4_to_ahb_1_io_axi_ar_bits_id), + .io_axi_r_valid(axi4_to_ahb_1_io_axi_r_valid), + .io_axi_r_bits_id(axi4_to_ahb_1_io_axi_r_bits_id), + .io_axi_r_bits_data(axi4_to_ahb_1_io_axi_r_bits_data), + .io_axi_r_bits_resp(axi4_to_ahb_1_io_axi_r_bits_resp) ); axi4_to_ahb axi4_to_ahb_2 ( // @[quasar.scala 244:33] .clock(axi4_to_ahb_2_clock), @@ -82991,17 +82291,27 @@ module quasar( .io_clk_override(axi4_to_ahb_2_io_clk_override), .io_axi_aw_ready(axi4_to_ahb_2_io_axi_aw_ready), .io_axi_aw_valid(axi4_to_ahb_2_io_axi_aw_valid), + .io_axi_aw_bits_id(axi4_to_ahb_2_io_axi_aw_bits_id), .io_axi_w_ready(axi4_to_ahb_2_io_axi_w_ready), .io_axi_w_valid(axi4_to_ahb_2_io_axi_w_valid), + .io_axi_w_bits_data(axi4_to_ahb_2_io_axi_w_bits_data), .io_axi_b_ready(axi4_to_ahb_2_io_axi_b_ready), - .io_axi_ar_valid(axi4_to_ahb_2_io_axi_ar_valid) + .io_axi_b_valid(axi4_to_ahb_2_io_axi_b_valid), + .io_axi_b_bits_resp(axi4_to_ahb_2_io_axi_b_bits_resp), + .io_axi_b_bits_id(axi4_to_ahb_2_io_axi_b_bits_id), + .io_axi_ar_ready(axi4_to_ahb_2_io_axi_ar_ready), + .io_axi_ar_valid(axi4_to_ahb_2_io_axi_ar_valid), + .io_axi_ar_bits_id(axi4_to_ahb_2_io_axi_ar_bits_id), + .io_axi_r_valid(axi4_to_ahb_2_io_axi_r_valid), + .io_axi_r_bits_id(axi4_to_ahb_2_io_axi_r_bits_id), + .io_axi_r_bits_data(axi4_to_ahb_2_io_axi_r_bits_data), + .io_axi_r_bits_resp(axi4_to_ahb_2_io_axi_r_bits_resp) ); ahb_to_axi4 ahb_to_axi4 ( // @[quasar.scala 245:33] .clock(ahb_to_axi4_clock), .reset(ahb_to_axi4_reset), .io_scan_mode(ahb_to_axi4_io_scan_mode), .io_bus_clk_en(ahb_to_axi4_io_bus_clk_en), - .io_axi_aw_ready(ahb_to_axi4_io_axi_aw_ready), .io_axi_aw_valid(ahb_to_axi4_io_axi_aw_valid), .io_axi_ar_ready(ahb_to_axi4_io_axi_ar_ready), .io_axi_ar_valid(ahb_to_axi4_io_axi_ar_valid), @@ -83009,46 +82319,6 @@ module quasar( .io_axi_r_bits_resp(ahb_to_axi4_io_axi_r_bits_resp), .io_ahb_sig_in_hresp(ahb_to_axi4_io_ahb_sig_in_hresp) ); - assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 275:25 quasar.scala 285:27] - assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 275:25 quasar.scala 285:27] - assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 275:25 quasar.scala 285:27] - assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 275:25 quasar.scala 285:27] - assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 275:25 quasar.scala 285:27] - assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 275:25 quasar.scala 285:27] - assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 275:25 quasar.scala 285:27] - assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 275:25 quasar.scala 285:27] - assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 275:25 quasar.scala 285:27] - assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 275:25 quasar.scala 285:27] - assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 275:25 quasar.scala 285:27] - assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 275:25 quasar.scala 285:27] - assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 275:25 quasar.scala 285:27] - assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 275:25 quasar.scala 285:27] - assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 275:25 quasar.scala 285:27] - assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 274:25 quasar.scala 284:27] - assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 274:25 quasar.scala 284:27] - assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 274:25 quasar.scala 284:27] - assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 274:25 quasar.scala 284:27] - assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 273:21 quasar.scala 283:27] - assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 273:21 quasar.scala 283:27] - assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 273:21 quasar.scala 283:27] - assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 273:21 quasar.scala 283:27] - assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 273:21 quasar.scala 283:27] - assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 273:21 quasar.scala 283:27] - assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 273:21 quasar.scala 283:27] - assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 273:21 quasar.scala 283:27] - assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 273:21 quasar.scala 283:27] - assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 273:21 quasar.scala 283:27] - assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 273:21 quasar.scala 283:27] - assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 272:16 quasar.scala 282:27] - assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 272:16 quasar.scala 282:27] - assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 272:16 quasar.scala 282:27] - assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 272:16 quasar.scala 282:27] - assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 272:16 quasar.scala 282:27] - assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 272:16 quasar.scala 282:27] - assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 272:16 quasar.scala 282:27] - assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 272:16 quasar.scala 282:27] - assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 272:16 quasar.scala 282:27] - assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 272:16 quasar.scala 282:27] assign io_core_rst_l = reset & _T_2; // @[quasar.scala 80:17] assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 220:19] assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 220:19] @@ -83150,11 +82420,11 @@ module quasar( assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 101:13] assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 101:13] assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 101:13] - assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 257:28 quasar.scala 284:27] - assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 257:28 quasar.scala 284:27] - assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 257:28 quasar.scala 284:27] - assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 257:28 quasar.scala 284:27] - assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 257:28 quasar.scala 284:27] + assign ifu_io_ifu_ar_ready = axi4_to_ahb_1_io_axi_ar_ready; // @[quasar.scala 257:28] + assign ifu_io_ifu_r_valid = axi4_to_ahb_1_io_axi_r_valid; // @[quasar.scala 257:28] + assign ifu_io_ifu_r_bits_id = {{2'd0}, axi4_to_ahb_1_io_axi_r_bits_id}; // @[quasar.scala 257:28] + assign ifu_io_ifu_r_bits_data = axi4_to_ahb_1_io_axi_r_bits_data; // @[quasar.scala 257:28] + assign ifu_io_ifu_r_bits_resp = axi4_to_ahb_1_io_axi_r_bits_resp; // @[quasar.scala 257:28] assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 99:25] assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 100:18] assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 100:18] @@ -83296,14 +82566,14 @@ module quasar( assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 186:23] assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 187:24] assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 188:24] - assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 263:27 quasar.scala 283:27] - assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 263:27 quasar.scala 283:27] - assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 263:27 quasar.scala 283:27] - assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 263:27 quasar.scala 283:27] - assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 263:27 quasar.scala 283:27] - assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 263:27 quasar.scala 283:27] - assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 263:27 quasar.scala 283:27] - assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 263:27 quasar.scala 283:27] + assign dbg_io_sb_axi_aw_ready = axi4_to_ahb_io_axi_aw_ready; // @[quasar.scala 263:27] + assign dbg_io_sb_axi_w_ready = axi4_to_ahb_io_axi_w_ready; // @[quasar.scala 263:27] + assign dbg_io_sb_axi_b_valid = axi4_to_ahb_io_axi_b_valid; // @[quasar.scala 263:27] + assign dbg_io_sb_axi_b_bits_resp = axi4_to_ahb_io_axi_b_bits_resp; // @[quasar.scala 263:27] + assign dbg_io_sb_axi_ar_ready = axi4_to_ahb_io_axi_ar_ready; // @[quasar.scala 263:27] + assign dbg_io_sb_axi_r_valid = axi4_to_ahb_io_axi_r_valid; // @[quasar.scala 263:27] + assign dbg_io_sb_axi_r_bits_data = axi4_to_ahb_io_axi_r_bits_data; // @[quasar.scala 263:27] + assign dbg_io_sb_axi_r_bits_resp = axi4_to_ahb_io_axi_r_bits_resp; // @[quasar.scala 263:27] assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 202:26] assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 189:25] assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 190:20] @@ -83391,20 +82661,18 @@ module quasar( assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 164:18] assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 164:18] assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 123:18] - assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 123:18] assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 123:18] assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 238:11] assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 238:11] - assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 250:28 quasar.scala 285:27] - assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 250:28 quasar.scala 285:27] - assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 250:28 quasar.scala 285:27] - assign lsu_io_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar.scala 250:28 quasar.scala 285:27] - assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 250:28 quasar.scala 285:27] - assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 250:28 quasar.scala 285:27] - assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 250:28 quasar.scala 285:27] - assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 250:28 quasar.scala 285:27] - assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 250:28 quasar.scala 285:27] - assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 250:28 quasar.scala 285:27] + assign lsu_io_axi_aw_ready = axi4_to_ahb_2_io_axi_aw_ready; // @[quasar.scala 250:28] + assign lsu_io_axi_w_ready = axi4_to_ahb_2_io_axi_w_ready; // @[quasar.scala 250:28] + assign lsu_io_axi_b_valid = axi4_to_ahb_2_io_axi_b_valid; // @[quasar.scala 250:28] + assign lsu_io_axi_b_bits_id = {{2'd0}, axi4_to_ahb_2_io_axi_b_bits_id}; // @[quasar.scala 250:28] + assign lsu_io_axi_ar_ready = axi4_to_ahb_2_io_axi_ar_ready; // @[quasar.scala 250:28] + assign lsu_io_axi_r_valid = axi4_to_ahb_2_io_axi_r_valid; // @[quasar.scala 250:28] + assign lsu_io_axi_r_bits_id = {{2'd0}, axi4_to_ahb_2_io_axi_r_bits_id}; // @[quasar.scala 250:28] + assign lsu_io_axi_r_bits_data = axi4_to_ahb_2_io_axi_r_bits_data; // @[quasar.scala 250:28] + assign lsu_io_axi_r_bits_resp = axi4_to_ahb_2_io_axi_r_bits_resp; // @[quasar.scala 250:28] assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 160:32] assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 161:35] assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 162:29] @@ -83479,19 +82747,7 @@ module quasar( assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 205:29] assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 206:30] assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 207:26] - assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 269:28 quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 269:28 quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 269:28 quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 269:28 quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 269:28 quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 269:28 quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 269:28 quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 269:28 quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 269:28 quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 269:28 quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 269:28 quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 269:28 quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 269:28 quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_ar_valid = ahb_to_axi4_io_axi_ar_valid; // @[quasar.scala 269:28] assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 172:18] assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 172:18] assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 172:18] @@ -83509,32 +82765,40 @@ module quasar( assign axi4_to_ahb_io_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 261:34] assign axi4_to_ahb_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 262:36] assign axi4_to_ahb_io_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 263:27] + assign axi4_to_ahb_io_axi_aw_bits_id = 1'h0; // @[quasar.scala 263:27] assign axi4_to_ahb_io_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 263:27] + assign axi4_to_ahb_io_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 263:27] assign axi4_to_ahb_io_axi_b_ready = 1'h1; // @[quasar.scala 263:27] assign axi4_to_ahb_io_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 263:27] + assign axi4_to_ahb_io_axi_ar_bits_id = 1'h0; // @[quasar.scala 263:27] assign axi4_to_ahb_1_clock = clock; assign axi4_to_ahb_1_reset = reset; assign axi4_to_ahb_1_io_scan_mode = io_scan_mode; // @[quasar.scala 254:34] assign axi4_to_ahb_1_io_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 255:35] assign axi4_to_ahb_1_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 256:37] assign axi4_to_ahb_1_io_axi_aw_valid = 1'h0; // @[quasar.scala 257:28] + assign axi4_to_ahb_1_io_axi_aw_bits_id = 1'h0; // @[quasar.scala 257:28] assign axi4_to_ahb_1_io_axi_w_valid = 1'h0; // @[quasar.scala 257:28] + assign axi4_to_ahb_1_io_axi_w_bits_data = 64'h0; // @[quasar.scala 257:28] assign axi4_to_ahb_1_io_axi_b_ready = 1'h0; // @[quasar.scala 257:28] assign axi4_to_ahb_1_io_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 257:28] + assign axi4_to_ahb_1_io_axi_ar_bits_id = ifu_io_ifu_ar_bits_id[0]; // @[quasar.scala 257:28] assign axi4_to_ahb_2_clock = clock; assign axi4_to_ahb_2_reset = reset; assign axi4_to_ahb_2_io_scan_mode = io_scan_mode; // @[quasar.scala 247:34] assign axi4_to_ahb_2_io_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 248:35] assign axi4_to_ahb_2_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 249:37] assign axi4_to_ahb_2_io_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 250:28] + assign axi4_to_ahb_2_io_axi_aw_bits_id = lsu_io_axi_aw_bits_id[0]; // @[quasar.scala 250:28] assign axi4_to_ahb_2_io_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 250:28] + assign axi4_to_ahb_2_io_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 250:28] assign axi4_to_ahb_2_io_axi_b_ready = 1'h1; // @[quasar.scala 250:28] assign axi4_to_ahb_2_io_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 250:28] + assign axi4_to_ahb_2_io_axi_ar_bits_id = lsu_io_axi_ar_bits_id[0]; // @[quasar.scala 250:28] assign ahb_to_axi4_clock = clock; assign ahb_to_axi4_reset = reset; assign ahb_to_axi4_io_scan_mode = io_scan_mode; // @[quasar.scala 266:34] assign ahb_to_axi4_io_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 267:35] - assign ahb_to_axi4_io_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 269:28] assign ahb_to_axi4_io_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 269:28] assign ahb_to_axi4_io_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 269:28] assign ahb_to_axi4_io_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 269:28] @@ -83805,82 +83069,6 @@ module quasar_wrapper( wire dmi_wrapper_dmi_hard_reset; // @[quasar_wrapper.scala 64:27] wire core_clock; // @[quasar_wrapper.scala 65:20] wire core_reset; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 65:20] - wire [3:0] core_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 65:20] - wire [3:0] core_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_axi_w_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 65:20] - wire [7:0] core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_axi_b_valid; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20] - wire [3:0] core_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 65:20] - wire [3:0] core_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 65:20] - wire core_io_lsu_axi_r_valid; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 65:20] - wire core_io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20] - wire [3:0] core_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 65:20] - wire core_io_ifu_axi_r_valid; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_axi_aw_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 65:20] - wire [3:0] core_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_axi_w_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 65:20] - wire [7:0] core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_axi_b_valid; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_axi_ar_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20] - wire [3:0] core_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 65:20] - wire core_io_sb_axi_r_valid; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_aw_valid; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_w_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_w_valid; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 65:20] - wire [7:0] core_io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_b_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_b_valid; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_ar_valid; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 65:20] - wire [31:0] core_io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 65:20] - wire [2:0] core_io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_r_ready; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_r_valid; // @[quasar_wrapper.scala 65:20] - wire core_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 65:20] - wire [63:0] core_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 65:20] - wire [1:0] core_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 65:20] wire core_io_dbg_rst_l; // @[quasar_wrapper.scala 65:20] wire [30:0] core_io_rst_vec; // @[quasar_wrapper.scala 65:20] wire core_io_nmi_int; // @[quasar_wrapper.scala 65:20] @@ -84032,82 +83220,6 @@ module quasar_wrapper( quasar core ( // @[quasar_wrapper.scala 65:20] .clock(core_clock), .reset(core_reset), - .io_lsu_axi_aw_ready(core_io_lsu_axi_aw_ready), - .io_lsu_axi_aw_valid(core_io_lsu_axi_aw_valid), - .io_lsu_axi_aw_bits_id(core_io_lsu_axi_aw_bits_id), - .io_lsu_axi_aw_bits_addr(core_io_lsu_axi_aw_bits_addr), - .io_lsu_axi_aw_bits_region(core_io_lsu_axi_aw_bits_region), - .io_lsu_axi_aw_bits_size(core_io_lsu_axi_aw_bits_size), - .io_lsu_axi_aw_bits_cache(core_io_lsu_axi_aw_bits_cache), - .io_lsu_axi_w_ready(core_io_lsu_axi_w_ready), - .io_lsu_axi_w_valid(core_io_lsu_axi_w_valid), - .io_lsu_axi_w_bits_data(core_io_lsu_axi_w_bits_data), - .io_lsu_axi_w_bits_strb(core_io_lsu_axi_w_bits_strb), - .io_lsu_axi_b_valid(core_io_lsu_axi_b_valid), - .io_lsu_axi_b_bits_resp(core_io_lsu_axi_b_bits_resp), - .io_lsu_axi_b_bits_id(core_io_lsu_axi_b_bits_id), - .io_lsu_axi_ar_ready(core_io_lsu_axi_ar_ready), - .io_lsu_axi_ar_valid(core_io_lsu_axi_ar_valid), - .io_lsu_axi_ar_bits_id(core_io_lsu_axi_ar_bits_id), - .io_lsu_axi_ar_bits_addr(core_io_lsu_axi_ar_bits_addr), - .io_lsu_axi_ar_bits_region(core_io_lsu_axi_ar_bits_region), - .io_lsu_axi_ar_bits_size(core_io_lsu_axi_ar_bits_size), - .io_lsu_axi_ar_bits_cache(core_io_lsu_axi_ar_bits_cache), - .io_lsu_axi_r_valid(core_io_lsu_axi_r_valid), - .io_lsu_axi_r_bits_id(core_io_lsu_axi_r_bits_id), - .io_lsu_axi_r_bits_data(core_io_lsu_axi_r_bits_data), - .io_lsu_axi_r_bits_resp(core_io_lsu_axi_r_bits_resp), - .io_ifu_axi_ar_ready(core_io_ifu_axi_ar_ready), - .io_ifu_axi_ar_valid(core_io_ifu_axi_ar_valid), - .io_ifu_axi_ar_bits_id(core_io_ifu_axi_ar_bits_id), - .io_ifu_axi_ar_bits_addr(core_io_ifu_axi_ar_bits_addr), - .io_ifu_axi_ar_bits_region(core_io_ifu_axi_ar_bits_region), - .io_ifu_axi_r_valid(core_io_ifu_axi_r_valid), - .io_ifu_axi_r_bits_id(core_io_ifu_axi_r_bits_id), - .io_ifu_axi_r_bits_data(core_io_ifu_axi_r_bits_data), - .io_ifu_axi_r_bits_resp(core_io_ifu_axi_r_bits_resp), - .io_sb_axi_aw_ready(core_io_sb_axi_aw_ready), - .io_sb_axi_aw_valid(core_io_sb_axi_aw_valid), - .io_sb_axi_aw_bits_addr(core_io_sb_axi_aw_bits_addr), - .io_sb_axi_aw_bits_region(core_io_sb_axi_aw_bits_region), - .io_sb_axi_aw_bits_size(core_io_sb_axi_aw_bits_size), - .io_sb_axi_w_ready(core_io_sb_axi_w_ready), - .io_sb_axi_w_valid(core_io_sb_axi_w_valid), - .io_sb_axi_w_bits_data(core_io_sb_axi_w_bits_data), - .io_sb_axi_w_bits_strb(core_io_sb_axi_w_bits_strb), - .io_sb_axi_b_valid(core_io_sb_axi_b_valid), - .io_sb_axi_b_bits_resp(core_io_sb_axi_b_bits_resp), - .io_sb_axi_ar_ready(core_io_sb_axi_ar_ready), - .io_sb_axi_ar_valid(core_io_sb_axi_ar_valid), - .io_sb_axi_ar_bits_addr(core_io_sb_axi_ar_bits_addr), - .io_sb_axi_ar_bits_region(core_io_sb_axi_ar_bits_region), - .io_sb_axi_ar_bits_size(core_io_sb_axi_ar_bits_size), - .io_sb_axi_r_valid(core_io_sb_axi_r_valid), - .io_sb_axi_r_bits_data(core_io_sb_axi_r_bits_data), - .io_sb_axi_r_bits_resp(core_io_sb_axi_r_bits_resp), - .io_dma_axi_aw_ready(core_io_dma_axi_aw_ready), - .io_dma_axi_aw_valid(core_io_dma_axi_aw_valid), - .io_dma_axi_aw_bits_id(core_io_dma_axi_aw_bits_id), - .io_dma_axi_aw_bits_addr(core_io_dma_axi_aw_bits_addr), - .io_dma_axi_aw_bits_size(core_io_dma_axi_aw_bits_size), - .io_dma_axi_w_ready(core_io_dma_axi_w_ready), - .io_dma_axi_w_valid(core_io_dma_axi_w_valid), - .io_dma_axi_w_bits_data(core_io_dma_axi_w_bits_data), - .io_dma_axi_w_bits_strb(core_io_dma_axi_w_bits_strb), - .io_dma_axi_b_ready(core_io_dma_axi_b_ready), - .io_dma_axi_b_valid(core_io_dma_axi_b_valid), - .io_dma_axi_b_bits_resp(core_io_dma_axi_b_bits_resp), - .io_dma_axi_b_bits_id(core_io_dma_axi_b_bits_id), - .io_dma_axi_ar_ready(core_io_dma_axi_ar_ready), - .io_dma_axi_ar_valid(core_io_dma_axi_ar_valid), - .io_dma_axi_ar_bits_id(core_io_dma_axi_ar_bits_id), - .io_dma_axi_ar_bits_addr(core_io_dma_axi_ar_bits_addr), - .io_dma_axi_ar_bits_size(core_io_dma_axi_ar_bits_size), - .io_dma_axi_r_ready(core_io_dma_axi_r_ready), - .io_dma_axi_r_valid(core_io_dma_axi_r_valid), - .io_dma_axi_r_bits_id(core_io_dma_axi_r_bits_id), - .io_dma_axi_r_bits_data(core_io_dma_axi_r_bits_data), - .io_dma_axi_r_bits_resp(core_io_dma_axi_r_bits_resp), .io_dbg_rst_l(core_io_dbg_rst_l), .io_rst_vec(core_io_rst_vec), .io_nmi_int(core_io_nmi_int), @@ -84192,34 +83304,34 @@ module quasar_wrapper( .io_soft_int(core_io_soft_int), .io_scan_mode(core_io_scan_mode) ); - assign io_lsu_brg_aw_valid = core_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_id = core_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_addr = core_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_region = core_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_valid = 1'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 104:21] assign io_lsu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_size = core_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 104:21] assign io_lsu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_aw_bits_cache = core_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 104:21] assign io_lsu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 104:21] assign io_lsu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_w_valid = core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_w_bits_data = core_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_w_bits_strb = core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_valid = core_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_id = core_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_addr = core_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_region = core_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_w_valid = 1'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_w_bits_data = 64'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_w_bits_last = 1'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_b_ready = 1'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_valid = 1'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_id = 3'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_addr = 32'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_region = 4'h0; // @[quasar_wrapper.scala 104:21] assign io_lsu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_size = core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_size = 3'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_burst = 2'h0; // @[quasar_wrapper.scala 104:21] assign io_lsu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_ar_bits_cache = core_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 104:21] assign io_lsu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 104:21] assign io_lsu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 104:21] - assign io_lsu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_r_ready = 1'h0; // @[quasar_wrapper.scala 104:21] assign io_ifu_brg_aw_valid = 1'h0; // @[quasar_wrapper.scala 105:21] assign io_ifu_brg_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 105:21] assign io_ifu_brg_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 105:21] @@ -84236,57 +83348,57 @@ module quasar_wrapper( assign io_ifu_brg_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 105:21] assign io_ifu_brg_w_bits_last = 1'h0; // @[quasar_wrapper.scala 105:21] assign io_ifu_brg_b_ready = 1'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_valid = core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_id = core_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_addr = core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_region = core_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_valid = 1'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_id = 3'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_addr = 32'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_region = 4'h0; // @[quasar_wrapper.scala 105:21] assign io_ifu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_size = 3'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_burst = 2'h0; // @[quasar_wrapper.scala 105:21] assign io_ifu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 105:21] assign io_ifu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 105:21] assign io_ifu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 105:21] - assign io_ifu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 105:21] - assign io_sb_brg_aw_valid = core_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 106:21] + assign io_ifu_brg_r_ready = 1'h0; // @[quasar_wrapper.scala 105:21] + assign io_sb_brg_aw_valid = 1'h0; // @[quasar_wrapper.scala 106:21] assign io_sb_brg_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_addr = core_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_region = core_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 106:21] assign io_sb_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_size = core_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 106:21] assign io_sb_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 106:21] assign io_sb_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 106:21] assign io_sb_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_w_valid = core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_w_bits_data = core_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_w_bits_strb = core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_valid = core_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_w_valid = 1'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_w_bits_data = 64'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_w_bits_last = 1'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_b_ready = 1'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_valid = 1'h0; // @[quasar_wrapper.scala 106:21] assign io_sb_brg_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_addr = core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_region = core_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_addr = 32'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_region = 4'h0; // @[quasar_wrapper.scala 106:21] assign io_sb_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_size = core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_size = 3'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_burst = 2'h0; // @[quasar_wrapper.scala 106:21] assign io_sb_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 106:21] assign io_sb_brg_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 106:21] assign io_sb_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 106:21] assign io_sb_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 106:21] - assign io_sb_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 106:21] - assign io_dma_brg_aw_ready = core_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_w_ready = core_io_dma_axi_w_ready; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_b_valid = core_io_dma_axi_b_valid; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_b_bits_resp = core_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_b_bits_id = core_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_ar_ready = core_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_r_valid = core_io_dma_axi_r_valid; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_r_bits_id = core_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_r_bits_data = core_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_r_bits_resp = core_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 107:21] - assign io_dma_brg_r_bits_last = 1'h1; // @[quasar_wrapper.scala 107:21] + assign io_sb_brg_r_ready = 1'h0; // @[quasar_wrapper.scala 106:21] + assign io_dma_brg_aw_ready = 1'h0; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_w_ready = 1'h0; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_b_valid = 1'h0; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_b_bits_resp = 2'h0; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_b_bits_id = 1'h0; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_ar_ready = 1'h0; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_r_valid = 1'h0; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_r_bits_id = 1'h0; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_r_bits_data = 64'h0; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_r_bits_resp = 2'h0; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_r_bits_last = 1'h0; // @[quasar_wrapper.scala 107:21] assign io_dec_tlu_perfcnt0 = core_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 159:23] assign io_dec_tlu_perfcnt1 = core_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 160:23] assign io_dec_tlu_perfcnt2 = core_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 161:23] @@ -84351,42 +83463,6 @@ module quasar_wrapper( assign dmi_wrapper_rd_data = 32'h0; // @[quasar_wrapper.scala 73:26] assign core_clock = clock; assign core_reset = reset; - assign core_io_lsu_axi_aw_ready = io_lsu_brg_aw_ready; // @[quasar_wrapper.scala 104:21] - assign core_io_lsu_axi_w_ready = io_lsu_brg_w_ready; // @[quasar_wrapper.scala 104:21] - assign core_io_lsu_axi_b_valid = io_lsu_brg_b_valid; // @[quasar_wrapper.scala 104:21] - assign core_io_lsu_axi_b_bits_resp = io_lsu_brg_b_bits_resp; // @[quasar_wrapper.scala 104:21] - assign core_io_lsu_axi_b_bits_id = io_lsu_brg_b_bits_id; // @[quasar_wrapper.scala 104:21] - assign core_io_lsu_axi_ar_ready = io_lsu_brg_ar_ready; // @[quasar_wrapper.scala 104:21] - assign core_io_lsu_axi_r_valid = io_lsu_brg_r_valid; // @[quasar_wrapper.scala 104:21] - assign core_io_lsu_axi_r_bits_id = io_lsu_brg_r_bits_id; // @[quasar_wrapper.scala 104:21] - assign core_io_lsu_axi_r_bits_data = io_lsu_brg_r_bits_data; // @[quasar_wrapper.scala 104:21] - assign core_io_lsu_axi_r_bits_resp = io_lsu_brg_r_bits_resp; // @[quasar_wrapper.scala 104:21] - assign core_io_ifu_axi_ar_ready = io_ifu_brg_ar_ready; // @[quasar_wrapper.scala 105:21] - assign core_io_ifu_axi_r_valid = io_ifu_brg_r_valid; // @[quasar_wrapper.scala 105:21] - assign core_io_ifu_axi_r_bits_id = io_ifu_brg_r_bits_id; // @[quasar_wrapper.scala 105:21] - assign core_io_ifu_axi_r_bits_data = io_ifu_brg_r_bits_data; // @[quasar_wrapper.scala 105:21] - assign core_io_ifu_axi_r_bits_resp = io_ifu_brg_r_bits_resp; // @[quasar_wrapper.scala 105:21] - assign core_io_sb_axi_aw_ready = io_sb_brg_aw_ready; // @[quasar_wrapper.scala 106:21] - assign core_io_sb_axi_w_ready = io_sb_brg_w_ready; // @[quasar_wrapper.scala 106:21] - assign core_io_sb_axi_b_valid = io_sb_brg_b_valid; // @[quasar_wrapper.scala 106:21] - assign core_io_sb_axi_b_bits_resp = io_sb_brg_b_bits_resp; // @[quasar_wrapper.scala 106:21] - assign core_io_sb_axi_ar_ready = io_sb_brg_ar_ready; // @[quasar_wrapper.scala 106:21] - assign core_io_sb_axi_r_valid = io_sb_brg_r_valid; // @[quasar_wrapper.scala 106:21] - assign core_io_sb_axi_r_bits_data = io_sb_brg_r_bits_data; // @[quasar_wrapper.scala 106:21] - assign core_io_sb_axi_r_bits_resp = io_sb_brg_r_bits_resp; // @[quasar_wrapper.scala 106:21] - assign core_io_dma_axi_aw_valid = io_dma_brg_aw_valid; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_aw_bits_id = io_dma_brg_aw_bits_id; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_aw_bits_addr = io_dma_brg_aw_bits_addr; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_aw_bits_size = io_dma_brg_aw_bits_size; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_w_valid = io_dma_brg_w_valid; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_w_bits_data = io_dma_brg_w_bits_data; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_w_bits_strb = io_dma_brg_w_bits_strb; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_b_ready = io_dma_brg_b_ready; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_ar_valid = io_dma_brg_ar_valid; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_ar_bits_id = io_dma_brg_ar_bits_id; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_ar_bits_addr = io_dma_brg_ar_bits_addr; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_ar_bits_size = io_dma_brg_ar_bits_size; // @[quasar_wrapper.scala 107:21] - assign core_io_dma_axi_r_ready = io_dma_brg_r_ready; // @[quasar_wrapper.scala 107:21] assign core_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 93:21 quasar_wrapper.scala 121:21] assign core_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 122:19] assign core_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 123:19] diff --git a/src/main/scala/lib/ahb_to_axi4.scala b/src/main/scala/lib/ahb_to_axi4.scala index 60bf09d4..8d13dcd3 100644 --- a/src/main/scala/lib/ahb_to_axi4.scala +++ b/src/main/scala/lib/ahb_to_axi4.scala @@ -179,4 +179,4 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { // AXI Read Response Channel - Always ready as AHB reads are blocking and the the buffer is available for the read coming back always. io.axi.r.ready := true.B bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode) -} +} \ No newline at end of file diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala index 3422f2b1..834ccf43 100644 --- a/src/main/scala/lib/axi4_to_ahb.scala +++ b/src/main/scala/lib/axi4_to_ahb.scala @@ -340,4 +340,4 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { ahbm_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode) ahbm_addr_clk := rvclkhdr(clock, ahbm_addr_clken, io.scan_mode) ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode) -} \ No newline at end of file +} diff --git a/src/main/scala/lib/param.scala b/src/main/scala/lib/param.scala index 0917162d..3ee9d0f3 100644 --- a/src/main/scala/lib/param.scala +++ b/src/main/scala/lib/param.scala @@ -21,9 +21,9 @@ trait param { val BTB_INDEX3_HI = 0x19 val BTB_INDEX3_LO = 0x12 val BTB_SIZE = 0x200 - val BUILD_AHB_LITE = 0x0 + val BUILD_AHB_LITE = 0x1 val BUILD_AXI4 = 0x1 - val BUILD_AXI_NATIVE = 0x1 + val BUILD_AXI_NATIVE = 0x0 val BUS_PRTY_DEFAULT = 0x3 val DATA_ACCESS_ADDR0 = 0x00000000 val DATA_ACCESS_ADDR1 = 0xC0000000 diff --git a/src/main/scala/quasar.scala b/src/main/scala/quasar.scala index 407cf6d9..cc69f776 100644 --- a/src/main/scala/quasar.scala +++ b/src/main/scala/quasar.scala @@ -238,7 +238,7 @@ class quasar extends Module with RequireAsyncReset with lib { io.dccm <> lsu.io.dccm - when(BUILD_AHB_LITE.B) { + if(BUILD_AHB_LITE) { val sb_axi4_to_ahb = Module(new axi4_to_ahb()) val ifu_axi4_to_ahb = Module(new axi4_to_ahb()) val lsu_axi4_to_ahb = Module(new axi4_to_ahb()) @@ -269,12 +269,12 @@ class quasar extends Module with RequireAsyncReset with lib { dma_ahb_to_axi4.io.axi <> dma_ctrl.io.dma_axi dma_ahb_to_axi4.io.ahb <> io.dma_ahb - io.dma_axi <> 0.U.asTypeOf(io.dma_axi) - io.sb_axi <> 0.U.asTypeOf(io.dma_axi) - io.ifu_axi <> 0.U.asTypeOf(io.dma_axi) - io.lsu_axi <> 0.U.asTypeOf(io.dma_axi) + io.dma_axi <> 0.U.asTypeOf(io.dma_axi) + io.sb_axi <> 0.U.asTypeOf(io.sb_axi) + io.ifu_axi <> 0.U.asTypeOf(io.ifu_axi) + io.lsu_axi <> 0.U.asTypeOf(io.lsu_axi) } - .otherwise{ + else{ io.lsu_ahb <> 0.U.asTypeOf(io.lsu_ahb) io.ifu_ahb <> 0.U.asTypeOf(io.ifu_ahb) io.sb_ahb <> 0.U.asTypeOf(io.sb_ahb) @@ -286,5 +286,6 @@ class quasar extends Module with RequireAsyncReset with lib { } io.dmi_reg_rdata := 0.U } - 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