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Quasar 2.0 Final

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Laraib Khan 2021-04-09 10:34:47 +05:00 committed by GitHub
parent 08e44d5b94
commit e478679b75
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1 changed files with 1 additions and 15 deletions
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14
design/src/main/scala/ifu/ifu_aln_ctl.scala
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@ -14,22 +14,8 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
val ic_access_fault_type_f = Input(UInt(2.W)) // Type of access fault occured val ic_access_fault_type_f = Input(UInt(2.W)) // Type of access fault occured
val dec_i0_decode_d = Input(Bool()) val dec_i0_decode_d = Input(Bool())
val dec_aln = new dec_aln() val dec_aln = new dec_aln()
// val ifu_i0_valid = Output(Bool())
// val ifu_i0_icaf = Output(Bool())
// val ifu_i0_icaf_type = Output(UInt(2.W))
// val ifu_i0_icaf_second = Output(Bool())
// val ifu_i0_dbecc = Output(Bool())
// val ifu_i0_instr = Output(UInt(32.W))
// val ifu_i0_pc = Output(UInt(31.W))
// val ifu_i0_pc4 = Output(Bool())
val ifu_bp_fa_index_f = Vec(2, Input(UInt(log2Ceil(BTB_SIZE).W))) val ifu_bp_fa_index_f = Vec(2, Input(UInt(log2Ceil(BTB_SIZE).W)))
// val i0_brp = Output(Valid(new br_pkt_t()))
// val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
// val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W))
// val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
val ifu_i0_fa_index = Output(UInt(log2Ceil(BTB_SIZE).W)) val ifu_i0_fa_index = Output(UInt(log2Ceil(BTB_SIZE).W))
// val ifu_pmu_instr_aligned = Output(Bool())
// val ifu_i0_cinst = Output(UInt(16.W))
val ifu_bp_fghr_f = Input(UInt(BHT_GHR_SIZE.W)) // Data coming from the branch predictor to put in the FP val ifu_bp_fghr_f = Input(UInt(BHT_GHR_SIZE.W)) // Data coming from the branch predictor to put in the FP
val ifu_bp_btb_target_f = Input(UInt(31.W)) // Target for the instruction enqueue in the FP val ifu_bp_btb_target_f = Input(UInt(31.W)) // Target for the instruction enqueue in the FP
val ifu_bp_poffset_f = Input(UInt(12.W)) // Offset to the current PC for branch val ifu_bp_poffset_f = Input(UInt(12.W)) // Offset to the current PC for branch