dec update
This commit is contained in:
Laraib Khan
parent
23069873a9
commit
e4ec02558c
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@ -66869,14 +66869,14 @@ circuit el2_swerv_wrapper :
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i0_rs2_depth_d <= UInt<1>("h00")
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wire cam_wen : UInt<4>
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cam_wen <= UInt<1>("h00")
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wire cam : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 147:17]
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wire cam : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[el2_dec_decode_ctl.scala 147:17]
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wire cam_write : UInt<1>
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cam_write <= UInt<1>("h00")
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wire cam_inv_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 149:29]
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wire cam_data_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 150:30]
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wire nonblock_load_write : UInt<1>[4] @[el2_dec_decode_ctl.scala 151:31]
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wire cam_raw : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 152:20]
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wire cam_in : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 153:20]
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wire cam_raw : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[el2_dec_decode_ctl.scala 152:20]
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wire cam_in : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[el2_dec_decode_ctl.scala 153:20]
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wire i0_dp : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 155:18]
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wire i0_dp_raw : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 156:22]
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wire i0_rs1bypass : UInt<3>
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@ -67295,26 +67295,26 @@ circuit el2_swerv_wrapper :
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nonblock_load_valid_m_delay <= io.lsu_nonblock_load_valid_m @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.i0load) @[el2_dec_decode_ctl.scala 319:56]
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node _T_91 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].tag) @[el2_dec_decode_ctl.scala 321:66]
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node _T_91 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 321:66]
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node _T_92 = and(io.lsu_nonblock_load_inv_r, _T_91) @[el2_dec_decode_ctl.scala 321:45]
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node _T_93 = and(_T_92, cam[0].valid) @[el2_dec_decode_ctl.scala 321:82]
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node _T_93 = and(_T_92, cam[0].valid) @[el2_dec_decode_ctl.scala 321:87]
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cam_inv_reset_val[0] <= _T_93 @[el2_dec_decode_ctl.scala 321:26]
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node _T_94 = eq(io.lsu_nonblock_load_data_tag, cam[0].tag) @[el2_dec_decode_ctl.scala 322:67]
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node _T_94 = eq(io.lsu_nonblock_load_data_tag, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 322:67]
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node _T_95 = and(cam_data_reset, _T_94) @[el2_dec_decode_ctl.scala 322:45]
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node _T_96 = and(_T_95, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 322:83]
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node _T_96 = and(_T_95, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 322:88]
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cam_data_reset_val[0] <= _T_96 @[el2_dec_decode_ctl.scala 322:27]
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wire _T_97 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28]
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_T_97.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28]
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_T_97.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28]
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_T_97.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
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wire _T_97 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28]
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_T_97.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28]
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_T_97.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28]
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_T_97.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
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_T_97.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
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cam_in[0].rd <= _T_97.rd @[el2_dec_decode_ctl.scala 323:14]
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cam_in[0].tag <= _T_97.tag @[el2_dec_decode_ctl.scala 323:14]
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cam_in[0].wb <= _T_97.wb @[el2_dec_decode_ctl.scala 323:14]
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cam_in[0].bits.rd <= _T_97.bits.rd @[el2_dec_decode_ctl.scala 323:14]
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cam_in[0].bits.tag <= _T_97.bits.tag @[el2_dec_decode_ctl.scala 323:14]
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cam_in[0].bits.wb <= _T_97.bits.wb @[el2_dec_decode_ctl.scala 323:14]
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cam_in[0].valid <= _T_97.valid @[el2_dec_decode_ctl.scala 323:14]
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cam[0].rd <= cam_raw[0].rd @[el2_dec_decode_ctl.scala 324:11]
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cam[0].tag <= cam_raw[0].tag @[el2_dec_decode_ctl.scala 324:11]
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cam[0].wb <= cam_raw[0].wb @[el2_dec_decode_ctl.scala 324:11]
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cam[0].bits.rd <= cam_raw[0].bits.rd @[el2_dec_decode_ctl.scala 324:11]
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cam[0].bits.tag <= cam_raw[0].bits.tag @[el2_dec_decode_ctl.scala 324:11]
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cam[0].bits.wb <= cam_raw[0].bits.wb @[el2_dec_decode_ctl.scala 324:11]
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cam[0].valid <= cam_raw[0].valid @[el2_dec_decode_ctl.scala 324:11]
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node _T_98 = bits(cam_data_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 326:32]
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when _T_98 : @[el2_dec_decode_ctl.scala 326:39]
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@ -67324,75 +67324,75 @@ circuit el2_swerv_wrapper :
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node _T_100 = bits(_T_99, 0, 0) @[el2_dec_decode_ctl.scala 329:21]
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when _T_100 : @[el2_dec_decode_ctl.scala 329:28]
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cam_in[0].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27]
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cam_in[0].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27]
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cam_in[0].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27]
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cam_in[0].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27]
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cam_in[0].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32]
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cam_in[0].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32]
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cam_in[0].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32]
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skip @[el2_dec_decode_ctl.scala 329:28]
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else : @[el2_dec_decode_ctl.scala 334:116]
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else : @[el2_dec_decode_ctl.scala 334:126]
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node _T_101 = bits(cam_inv_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 334:37]
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node _T_102 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57]
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node _T_103 = eq(r_d_in.i0rd, cam[0].rd) @[el2_dec_decode_ctl.scala 334:80]
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node _T_103 = eq(r_d_in.i0rd, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 334:80]
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node _T_104 = and(_T_102, _T_103) @[el2_dec_decode_ctl.scala 334:64]
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node _T_105 = bits(cam[0].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108]
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node _T_106 = and(_T_104, _T_105) @[el2_dec_decode_ctl.scala 334:95]
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node _T_105 = bits(cam[0].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:118]
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node _T_106 = and(_T_104, _T_105) @[el2_dec_decode_ctl.scala 334:100]
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node _T_107 = or(_T_101, _T_106) @[el2_dec_decode_ctl.scala 334:44]
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when _T_107 : @[el2_dec_decode_ctl.scala 334:116]
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when _T_107 : @[el2_dec_decode_ctl.scala 334:126]
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cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23]
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skip @[el2_dec_decode_ctl.scala 334:116]
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skip @[el2_dec_decode_ctl.scala 334:126]
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else : @[el2_dec_decode_ctl.scala 336:16]
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cam_in[0].rd <= cam[0].rd @[el2_dec_decode_ctl.scala 337:22]
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cam_in[0].tag <= cam[0].tag @[el2_dec_decode_ctl.scala 337:22]
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cam_in[0].wb <= cam[0].wb @[el2_dec_decode_ctl.scala 337:22]
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cam_in[0].bits.rd <= cam[0].bits.rd @[el2_dec_decode_ctl.scala 337:22]
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cam_in[0].bits.tag <= cam[0].bits.tag @[el2_dec_decode_ctl.scala 337:22]
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cam_in[0].bits.wb <= cam[0].bits.wb @[el2_dec_decode_ctl.scala 337:22]
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cam_in[0].valid <= cam[0].valid @[el2_dec_decode_ctl.scala 337:22]
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skip @[el2_dec_decode_ctl.scala 336:16]
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node _T_108 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37]
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node _T_109 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].tag) @[el2_dec_decode_ctl.scala 339:79]
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node _T_109 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 339:79]
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node _T_110 = and(_T_108, _T_109) @[el2_dec_decode_ctl.scala 339:44]
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node _T_111 = eq(cam[0].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110]
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node _T_112 = and(_T_110, _T_111) @[el2_dec_decode_ctl.scala 339:95]
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when _T_112 : @[el2_dec_decode_ctl.scala 339:117]
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cam_in[0].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20]
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skip @[el2_dec_decode_ctl.scala 339:117]
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node _T_111 = eq(cam[0].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115]
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node _T_112 = and(_T_110, _T_111) @[el2_dec_decode_ctl.scala 339:100]
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when _T_112 : @[el2_dec_decode_ctl.scala 339:122]
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cam_in[0].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25]
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skip @[el2_dec_decode_ctl.scala 339:122]
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when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32]
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cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23]
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skip @[el2_dec_decode_ctl.scala 343:32]
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wire _T_113 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70]
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_T_113.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70]
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_T_113.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70]
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_T_113.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
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wire _T_113 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70]
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_T_113.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70]
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_T_113.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70]
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_T_113.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
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_T_113.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
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reg _T_114 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_113)) @[el2_dec_decode_ctl.scala 347:47]
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_T_114.rd <= cam_in[0].rd @[el2_dec_decode_ctl.scala 347:47]
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_T_114.tag <= cam_in[0].tag @[el2_dec_decode_ctl.scala 347:47]
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_T_114.wb <= cam_in[0].wb @[el2_dec_decode_ctl.scala 347:47]
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reg _T_114 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_113)) @[el2_dec_decode_ctl.scala 347:47]
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_T_114.bits.rd <= cam_in[0].bits.rd @[el2_dec_decode_ctl.scala 347:47]
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_T_114.bits.tag <= cam_in[0].bits.tag @[el2_dec_decode_ctl.scala 347:47]
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_T_114.bits.wb <= cam_in[0].bits.wb @[el2_dec_decode_ctl.scala 347:47]
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_T_114.valid <= cam_in[0].valid @[el2_dec_decode_ctl.scala 347:47]
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cam_raw[0].rd <= _T_114.rd @[el2_dec_decode_ctl.scala 347:15]
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cam_raw[0].tag <= _T_114.tag @[el2_dec_decode_ctl.scala 347:15]
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cam_raw[0].wb <= _T_114.wb @[el2_dec_decode_ctl.scala 347:15]
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cam_raw[0].bits.rd <= _T_114.bits.rd @[el2_dec_decode_ctl.scala 347:15]
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cam_raw[0].bits.tag <= _T_114.bits.tag @[el2_dec_decode_ctl.scala 347:15]
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cam_raw[0].bits.wb <= _T_114.bits.wb @[el2_dec_decode_ctl.scala 347:15]
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cam_raw[0].valid <= _T_114.valid @[el2_dec_decode_ctl.scala 347:15]
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node _T_115 = eq(io.lsu_nonblock_load_data_tag, cam_raw[0].tag) @[el2_dec_decode_ctl.scala 348:46]
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node _T_116 = and(_T_115, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 348:66]
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node _T_115 = eq(io.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[el2_dec_decode_ctl.scala 348:46]
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node _T_116 = and(_T_115, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 348:71]
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nonblock_load_write[0] <= _T_116 @[el2_dec_decode_ctl.scala 348:28]
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node _T_117 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].tag) @[el2_dec_decode_ctl.scala 321:66]
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node _T_117 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 321:66]
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node _T_118 = and(io.lsu_nonblock_load_inv_r, _T_117) @[el2_dec_decode_ctl.scala 321:45]
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node _T_119 = and(_T_118, cam[1].valid) @[el2_dec_decode_ctl.scala 321:82]
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node _T_119 = and(_T_118, cam[1].valid) @[el2_dec_decode_ctl.scala 321:87]
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cam_inv_reset_val[1] <= _T_119 @[el2_dec_decode_ctl.scala 321:26]
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node _T_120 = eq(io.lsu_nonblock_load_data_tag, cam[1].tag) @[el2_dec_decode_ctl.scala 322:67]
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node _T_120 = eq(io.lsu_nonblock_load_data_tag, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 322:67]
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node _T_121 = and(cam_data_reset, _T_120) @[el2_dec_decode_ctl.scala 322:45]
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node _T_122 = and(_T_121, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 322:83]
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node _T_122 = and(_T_121, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 322:88]
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cam_data_reset_val[1] <= _T_122 @[el2_dec_decode_ctl.scala 322:27]
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wire _T_123 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28]
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_T_123.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28]
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_T_123.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28]
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_T_123.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
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wire _T_123 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28]
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_T_123.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28]
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_T_123.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28]
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_T_123.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
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_T_123.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
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cam_in[1].rd <= _T_123.rd @[el2_dec_decode_ctl.scala 323:14]
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cam_in[1].tag <= _T_123.tag @[el2_dec_decode_ctl.scala 323:14]
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cam_in[1].wb <= _T_123.wb @[el2_dec_decode_ctl.scala 323:14]
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cam_in[1].bits.rd <= _T_123.bits.rd @[el2_dec_decode_ctl.scala 323:14]
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cam_in[1].bits.tag <= _T_123.bits.tag @[el2_dec_decode_ctl.scala 323:14]
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cam_in[1].bits.wb <= _T_123.bits.wb @[el2_dec_decode_ctl.scala 323:14]
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cam_in[1].valid <= _T_123.valid @[el2_dec_decode_ctl.scala 323:14]
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cam[1].rd <= cam_raw[1].rd @[el2_dec_decode_ctl.scala 324:11]
|
||||
cam[1].tag <= cam_raw[1].tag @[el2_dec_decode_ctl.scala 324:11]
|
||||
cam[1].wb <= cam_raw[1].wb @[el2_dec_decode_ctl.scala 324:11]
|
||||
cam[1].bits.rd <= cam_raw[1].bits.rd @[el2_dec_decode_ctl.scala 324:11]
|
||||
cam[1].bits.tag <= cam_raw[1].bits.tag @[el2_dec_decode_ctl.scala 324:11]
|
||||
cam[1].bits.wb <= cam_raw[1].bits.wb @[el2_dec_decode_ctl.scala 324:11]
|
||||
cam[1].valid <= cam_raw[1].valid @[el2_dec_decode_ctl.scala 324:11]
|
||||
node _T_124 = bits(cam_data_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 326:32]
|
||||
when _T_124 : @[el2_dec_decode_ctl.scala 326:39]
|
||||
|
|
@ -67402,75 +67402,75 @@ circuit el2_swerv_wrapper :
|
|||
node _T_126 = bits(_T_125, 0, 0) @[el2_dec_decode_ctl.scala 329:21]
|
||||
when _T_126 : @[el2_dec_decode_ctl.scala 329:28]
|
||||
cam_in[1].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27]
|
||||
cam_in[1].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27]
|
||||
cam_in[1].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27]
|
||||
cam_in[1].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27]
|
||||
cam_in[1].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32]
|
||||
cam_in[1].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32]
|
||||
cam_in[1].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32]
|
||||
skip @[el2_dec_decode_ctl.scala 329:28]
|
||||
else : @[el2_dec_decode_ctl.scala 334:116]
|
||||
else : @[el2_dec_decode_ctl.scala 334:126]
|
||||
node _T_127 = bits(cam_inv_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 334:37]
|
||||
node _T_128 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57]
|
||||
node _T_129 = eq(r_d_in.i0rd, cam[1].rd) @[el2_dec_decode_ctl.scala 334:80]
|
||||
node _T_129 = eq(r_d_in.i0rd, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 334:80]
|
||||
node _T_130 = and(_T_128, _T_129) @[el2_dec_decode_ctl.scala 334:64]
|
||||
node _T_131 = bits(cam[1].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108]
|
||||
node _T_132 = and(_T_130, _T_131) @[el2_dec_decode_ctl.scala 334:95]
|
||||
node _T_131 = bits(cam[1].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:118]
|
||||
node _T_132 = and(_T_130, _T_131) @[el2_dec_decode_ctl.scala 334:100]
|
||||
node _T_133 = or(_T_127, _T_132) @[el2_dec_decode_ctl.scala 334:44]
|
||||
when _T_133 : @[el2_dec_decode_ctl.scala 334:116]
|
||||
when _T_133 : @[el2_dec_decode_ctl.scala 334:126]
|
||||
cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23]
|
||||
skip @[el2_dec_decode_ctl.scala 334:116]
|
||||
skip @[el2_dec_decode_ctl.scala 334:126]
|
||||
else : @[el2_dec_decode_ctl.scala 336:16]
|
||||
cam_in[1].rd <= cam[1].rd @[el2_dec_decode_ctl.scala 337:22]
|
||||
cam_in[1].tag <= cam[1].tag @[el2_dec_decode_ctl.scala 337:22]
|
||||
cam_in[1].wb <= cam[1].wb @[el2_dec_decode_ctl.scala 337:22]
|
||||
cam_in[1].bits.rd <= cam[1].bits.rd @[el2_dec_decode_ctl.scala 337:22]
|
||||
cam_in[1].bits.tag <= cam[1].bits.tag @[el2_dec_decode_ctl.scala 337:22]
|
||||
cam_in[1].bits.wb <= cam[1].bits.wb @[el2_dec_decode_ctl.scala 337:22]
|
||||
cam_in[1].valid <= cam[1].valid @[el2_dec_decode_ctl.scala 337:22]
|
||||
skip @[el2_dec_decode_ctl.scala 336:16]
|
||||
node _T_134 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37]
|
||||
node _T_135 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].tag) @[el2_dec_decode_ctl.scala 339:79]
|
||||
node _T_135 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 339:79]
|
||||
node _T_136 = and(_T_134, _T_135) @[el2_dec_decode_ctl.scala 339:44]
|
||||
node _T_137 = eq(cam[1].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110]
|
||||
node _T_138 = and(_T_136, _T_137) @[el2_dec_decode_ctl.scala 339:95]
|
||||
when _T_138 : @[el2_dec_decode_ctl.scala 339:117]
|
||||
cam_in[1].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20]
|
||||
skip @[el2_dec_decode_ctl.scala 339:117]
|
||||
node _T_137 = eq(cam[1].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115]
|
||||
node _T_138 = and(_T_136, _T_137) @[el2_dec_decode_ctl.scala 339:100]
|
||||
when _T_138 : @[el2_dec_decode_ctl.scala 339:122]
|
||||
cam_in[1].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25]
|
||||
skip @[el2_dec_decode_ctl.scala 339:122]
|
||||
when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32]
|
||||
cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23]
|
||||
skip @[el2_dec_decode_ctl.scala 343:32]
|
||||
wire _T_139 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_139.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_139.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_139.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
wire _T_139 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_139.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_139.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_139.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_139.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
reg _T_140 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_139)) @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_140.rd <= cam_in[1].rd @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_140.tag <= cam_in[1].tag @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_140.wb <= cam_in[1].wb @[el2_dec_decode_ctl.scala 347:47]
|
||||
reg _T_140 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_139)) @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_140.bits.rd <= cam_in[1].bits.rd @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_140.bits.tag <= cam_in[1].bits.tag @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_140.bits.wb <= cam_in[1].bits.wb @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_140.valid <= cam_in[1].valid @[el2_dec_decode_ctl.scala 347:47]
|
||||
cam_raw[1].rd <= _T_140.rd @[el2_dec_decode_ctl.scala 347:15]
|
||||
cam_raw[1].tag <= _T_140.tag @[el2_dec_decode_ctl.scala 347:15]
|
||||
cam_raw[1].wb <= _T_140.wb @[el2_dec_decode_ctl.scala 347:15]
|
||||
cam_raw[1].bits.rd <= _T_140.bits.rd @[el2_dec_decode_ctl.scala 347:15]
|
||||
cam_raw[1].bits.tag <= _T_140.bits.tag @[el2_dec_decode_ctl.scala 347:15]
|
||||
cam_raw[1].bits.wb <= _T_140.bits.wb @[el2_dec_decode_ctl.scala 347:15]
|
||||
cam_raw[1].valid <= _T_140.valid @[el2_dec_decode_ctl.scala 347:15]
|
||||
node _T_141 = eq(io.lsu_nonblock_load_data_tag, cam_raw[1].tag) @[el2_dec_decode_ctl.scala 348:46]
|
||||
node _T_142 = and(_T_141, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 348:66]
|
||||
node _T_141 = eq(io.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[el2_dec_decode_ctl.scala 348:46]
|
||||
node _T_142 = and(_T_141, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 348:71]
|
||||
nonblock_load_write[1] <= _T_142 @[el2_dec_decode_ctl.scala 348:28]
|
||||
node _T_143 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].tag) @[el2_dec_decode_ctl.scala 321:66]
|
||||
node _T_143 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 321:66]
|
||||
node _T_144 = and(io.lsu_nonblock_load_inv_r, _T_143) @[el2_dec_decode_ctl.scala 321:45]
|
||||
node _T_145 = and(_T_144, cam[2].valid) @[el2_dec_decode_ctl.scala 321:82]
|
||||
node _T_145 = and(_T_144, cam[2].valid) @[el2_dec_decode_ctl.scala 321:87]
|
||||
cam_inv_reset_val[2] <= _T_145 @[el2_dec_decode_ctl.scala 321:26]
|
||||
node _T_146 = eq(io.lsu_nonblock_load_data_tag, cam[2].tag) @[el2_dec_decode_ctl.scala 322:67]
|
||||
node _T_146 = eq(io.lsu_nonblock_load_data_tag, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 322:67]
|
||||
node _T_147 = and(cam_data_reset, _T_146) @[el2_dec_decode_ctl.scala 322:45]
|
||||
node _T_148 = and(_T_147, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 322:83]
|
||||
node _T_148 = and(_T_147, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 322:88]
|
||||
cam_data_reset_val[2] <= _T_148 @[el2_dec_decode_ctl.scala 322:27]
|
||||
wire _T_149 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28]
|
||||
_T_149.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28]
|
||||
_T_149.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28]
|
||||
_T_149.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
|
||||
wire _T_149 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28]
|
||||
_T_149.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28]
|
||||
_T_149.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28]
|
||||
_T_149.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
|
||||
_T_149.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
|
||||
cam_in[2].rd <= _T_149.rd @[el2_dec_decode_ctl.scala 323:14]
|
||||
cam_in[2].tag <= _T_149.tag @[el2_dec_decode_ctl.scala 323:14]
|
||||
cam_in[2].wb <= _T_149.wb @[el2_dec_decode_ctl.scala 323:14]
|
||||
cam_in[2].bits.rd <= _T_149.bits.rd @[el2_dec_decode_ctl.scala 323:14]
|
||||
cam_in[2].bits.tag <= _T_149.bits.tag @[el2_dec_decode_ctl.scala 323:14]
|
||||
cam_in[2].bits.wb <= _T_149.bits.wb @[el2_dec_decode_ctl.scala 323:14]
|
||||
cam_in[2].valid <= _T_149.valid @[el2_dec_decode_ctl.scala 323:14]
|
||||
cam[2].rd <= cam_raw[2].rd @[el2_dec_decode_ctl.scala 324:11]
|
||||
cam[2].tag <= cam_raw[2].tag @[el2_dec_decode_ctl.scala 324:11]
|
||||
cam[2].wb <= cam_raw[2].wb @[el2_dec_decode_ctl.scala 324:11]
|
||||
cam[2].bits.rd <= cam_raw[2].bits.rd @[el2_dec_decode_ctl.scala 324:11]
|
||||
cam[2].bits.tag <= cam_raw[2].bits.tag @[el2_dec_decode_ctl.scala 324:11]
|
||||
cam[2].bits.wb <= cam_raw[2].bits.wb @[el2_dec_decode_ctl.scala 324:11]
|
||||
cam[2].valid <= cam_raw[2].valid @[el2_dec_decode_ctl.scala 324:11]
|
||||
node _T_150 = bits(cam_data_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 326:32]
|
||||
when _T_150 : @[el2_dec_decode_ctl.scala 326:39]
|
||||
|
|
@ -67480,75 +67480,75 @@ circuit el2_swerv_wrapper :
|
|||
node _T_152 = bits(_T_151, 0, 0) @[el2_dec_decode_ctl.scala 329:21]
|
||||
when _T_152 : @[el2_dec_decode_ctl.scala 329:28]
|
||||
cam_in[2].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27]
|
||||
cam_in[2].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27]
|
||||
cam_in[2].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27]
|
||||
cam_in[2].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27]
|
||||
cam_in[2].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32]
|
||||
cam_in[2].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32]
|
||||
cam_in[2].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32]
|
||||
skip @[el2_dec_decode_ctl.scala 329:28]
|
||||
else : @[el2_dec_decode_ctl.scala 334:116]
|
||||
else : @[el2_dec_decode_ctl.scala 334:126]
|
||||
node _T_153 = bits(cam_inv_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 334:37]
|
||||
node _T_154 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57]
|
||||
node _T_155 = eq(r_d_in.i0rd, cam[2].rd) @[el2_dec_decode_ctl.scala 334:80]
|
||||
node _T_155 = eq(r_d_in.i0rd, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 334:80]
|
||||
node _T_156 = and(_T_154, _T_155) @[el2_dec_decode_ctl.scala 334:64]
|
||||
node _T_157 = bits(cam[2].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108]
|
||||
node _T_158 = and(_T_156, _T_157) @[el2_dec_decode_ctl.scala 334:95]
|
||||
node _T_157 = bits(cam[2].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:118]
|
||||
node _T_158 = and(_T_156, _T_157) @[el2_dec_decode_ctl.scala 334:100]
|
||||
node _T_159 = or(_T_153, _T_158) @[el2_dec_decode_ctl.scala 334:44]
|
||||
when _T_159 : @[el2_dec_decode_ctl.scala 334:116]
|
||||
when _T_159 : @[el2_dec_decode_ctl.scala 334:126]
|
||||
cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23]
|
||||
skip @[el2_dec_decode_ctl.scala 334:116]
|
||||
skip @[el2_dec_decode_ctl.scala 334:126]
|
||||
else : @[el2_dec_decode_ctl.scala 336:16]
|
||||
cam_in[2].rd <= cam[2].rd @[el2_dec_decode_ctl.scala 337:22]
|
||||
cam_in[2].tag <= cam[2].tag @[el2_dec_decode_ctl.scala 337:22]
|
||||
cam_in[2].wb <= cam[2].wb @[el2_dec_decode_ctl.scala 337:22]
|
||||
cam_in[2].bits.rd <= cam[2].bits.rd @[el2_dec_decode_ctl.scala 337:22]
|
||||
cam_in[2].bits.tag <= cam[2].bits.tag @[el2_dec_decode_ctl.scala 337:22]
|
||||
cam_in[2].bits.wb <= cam[2].bits.wb @[el2_dec_decode_ctl.scala 337:22]
|
||||
cam_in[2].valid <= cam[2].valid @[el2_dec_decode_ctl.scala 337:22]
|
||||
skip @[el2_dec_decode_ctl.scala 336:16]
|
||||
node _T_160 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37]
|
||||
node _T_161 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].tag) @[el2_dec_decode_ctl.scala 339:79]
|
||||
node _T_161 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 339:79]
|
||||
node _T_162 = and(_T_160, _T_161) @[el2_dec_decode_ctl.scala 339:44]
|
||||
node _T_163 = eq(cam[2].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110]
|
||||
node _T_164 = and(_T_162, _T_163) @[el2_dec_decode_ctl.scala 339:95]
|
||||
when _T_164 : @[el2_dec_decode_ctl.scala 339:117]
|
||||
cam_in[2].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20]
|
||||
skip @[el2_dec_decode_ctl.scala 339:117]
|
||||
node _T_163 = eq(cam[2].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115]
|
||||
node _T_164 = and(_T_162, _T_163) @[el2_dec_decode_ctl.scala 339:100]
|
||||
when _T_164 : @[el2_dec_decode_ctl.scala 339:122]
|
||||
cam_in[2].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25]
|
||||
skip @[el2_dec_decode_ctl.scala 339:122]
|
||||
when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32]
|
||||
cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23]
|
||||
skip @[el2_dec_decode_ctl.scala 343:32]
|
||||
wire _T_165 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_165.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_165.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_165.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
wire _T_165 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_165.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_165.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_165.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_165.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
reg _T_166 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_165)) @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_166.rd <= cam_in[2].rd @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_166.tag <= cam_in[2].tag @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_166.wb <= cam_in[2].wb @[el2_dec_decode_ctl.scala 347:47]
|
||||
reg _T_166 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_165)) @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_166.bits.rd <= cam_in[2].bits.rd @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_166.bits.tag <= cam_in[2].bits.tag @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_166.bits.wb <= cam_in[2].bits.wb @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_166.valid <= cam_in[2].valid @[el2_dec_decode_ctl.scala 347:47]
|
||||
cam_raw[2].rd <= _T_166.rd @[el2_dec_decode_ctl.scala 347:15]
|
||||
cam_raw[2].tag <= _T_166.tag @[el2_dec_decode_ctl.scala 347:15]
|
||||
cam_raw[2].wb <= _T_166.wb @[el2_dec_decode_ctl.scala 347:15]
|
||||
cam_raw[2].bits.rd <= _T_166.bits.rd @[el2_dec_decode_ctl.scala 347:15]
|
||||
cam_raw[2].bits.tag <= _T_166.bits.tag @[el2_dec_decode_ctl.scala 347:15]
|
||||
cam_raw[2].bits.wb <= _T_166.bits.wb @[el2_dec_decode_ctl.scala 347:15]
|
||||
cam_raw[2].valid <= _T_166.valid @[el2_dec_decode_ctl.scala 347:15]
|
||||
node _T_167 = eq(io.lsu_nonblock_load_data_tag, cam_raw[2].tag) @[el2_dec_decode_ctl.scala 348:46]
|
||||
node _T_168 = and(_T_167, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 348:66]
|
||||
node _T_167 = eq(io.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[el2_dec_decode_ctl.scala 348:46]
|
||||
node _T_168 = and(_T_167, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 348:71]
|
||||
nonblock_load_write[2] <= _T_168 @[el2_dec_decode_ctl.scala 348:28]
|
||||
node _T_169 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].tag) @[el2_dec_decode_ctl.scala 321:66]
|
||||
node _T_169 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 321:66]
|
||||
node _T_170 = and(io.lsu_nonblock_load_inv_r, _T_169) @[el2_dec_decode_ctl.scala 321:45]
|
||||
node _T_171 = and(_T_170, cam[3].valid) @[el2_dec_decode_ctl.scala 321:82]
|
||||
node _T_171 = and(_T_170, cam[3].valid) @[el2_dec_decode_ctl.scala 321:87]
|
||||
cam_inv_reset_val[3] <= _T_171 @[el2_dec_decode_ctl.scala 321:26]
|
||||
node _T_172 = eq(io.lsu_nonblock_load_data_tag, cam[3].tag) @[el2_dec_decode_ctl.scala 322:67]
|
||||
node _T_172 = eq(io.lsu_nonblock_load_data_tag, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 322:67]
|
||||
node _T_173 = and(cam_data_reset, _T_172) @[el2_dec_decode_ctl.scala 322:45]
|
||||
node _T_174 = and(_T_173, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 322:83]
|
||||
node _T_174 = and(_T_173, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 322:88]
|
||||
cam_data_reset_val[3] <= _T_174 @[el2_dec_decode_ctl.scala 322:27]
|
||||
wire _T_175 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28]
|
||||
_T_175.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28]
|
||||
_T_175.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28]
|
||||
_T_175.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
|
||||
wire _T_175 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28]
|
||||
_T_175.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28]
|
||||
_T_175.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28]
|
||||
_T_175.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
|
||||
_T_175.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28]
|
||||
cam_in[3].rd <= _T_175.rd @[el2_dec_decode_ctl.scala 323:14]
|
||||
cam_in[3].tag <= _T_175.tag @[el2_dec_decode_ctl.scala 323:14]
|
||||
cam_in[3].wb <= _T_175.wb @[el2_dec_decode_ctl.scala 323:14]
|
||||
cam_in[3].bits.rd <= _T_175.bits.rd @[el2_dec_decode_ctl.scala 323:14]
|
||||
cam_in[3].bits.tag <= _T_175.bits.tag @[el2_dec_decode_ctl.scala 323:14]
|
||||
cam_in[3].bits.wb <= _T_175.bits.wb @[el2_dec_decode_ctl.scala 323:14]
|
||||
cam_in[3].valid <= _T_175.valid @[el2_dec_decode_ctl.scala 323:14]
|
||||
cam[3].rd <= cam_raw[3].rd @[el2_dec_decode_ctl.scala 324:11]
|
||||
cam[3].tag <= cam_raw[3].tag @[el2_dec_decode_ctl.scala 324:11]
|
||||
cam[3].wb <= cam_raw[3].wb @[el2_dec_decode_ctl.scala 324:11]
|
||||
cam[3].bits.rd <= cam_raw[3].bits.rd @[el2_dec_decode_ctl.scala 324:11]
|
||||
cam[3].bits.tag <= cam_raw[3].bits.tag @[el2_dec_decode_ctl.scala 324:11]
|
||||
cam[3].bits.wb <= cam_raw[3].bits.wb @[el2_dec_decode_ctl.scala 324:11]
|
||||
cam[3].valid <= cam_raw[3].valid @[el2_dec_decode_ctl.scala 324:11]
|
||||
node _T_176 = bits(cam_data_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 326:32]
|
||||
when _T_176 : @[el2_dec_decode_ctl.scala 326:39]
|
||||
|
|
@ -67558,54 +67558,54 @@ circuit el2_swerv_wrapper :
|
|||
node _T_178 = bits(_T_177, 0, 0) @[el2_dec_decode_ctl.scala 329:21]
|
||||
when _T_178 : @[el2_dec_decode_ctl.scala 329:28]
|
||||
cam_in[3].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27]
|
||||
cam_in[3].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27]
|
||||
cam_in[3].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27]
|
||||
cam_in[3].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27]
|
||||
cam_in[3].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32]
|
||||
cam_in[3].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32]
|
||||
cam_in[3].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32]
|
||||
skip @[el2_dec_decode_ctl.scala 329:28]
|
||||
else : @[el2_dec_decode_ctl.scala 334:116]
|
||||
else : @[el2_dec_decode_ctl.scala 334:126]
|
||||
node _T_179 = bits(cam_inv_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 334:37]
|
||||
node _T_180 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57]
|
||||
node _T_181 = eq(r_d_in.i0rd, cam[3].rd) @[el2_dec_decode_ctl.scala 334:80]
|
||||
node _T_181 = eq(r_d_in.i0rd, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 334:80]
|
||||
node _T_182 = and(_T_180, _T_181) @[el2_dec_decode_ctl.scala 334:64]
|
||||
node _T_183 = bits(cam[3].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108]
|
||||
node _T_184 = and(_T_182, _T_183) @[el2_dec_decode_ctl.scala 334:95]
|
||||
node _T_183 = bits(cam[3].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:118]
|
||||
node _T_184 = and(_T_182, _T_183) @[el2_dec_decode_ctl.scala 334:100]
|
||||
node _T_185 = or(_T_179, _T_184) @[el2_dec_decode_ctl.scala 334:44]
|
||||
when _T_185 : @[el2_dec_decode_ctl.scala 334:116]
|
||||
when _T_185 : @[el2_dec_decode_ctl.scala 334:126]
|
||||
cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23]
|
||||
skip @[el2_dec_decode_ctl.scala 334:116]
|
||||
skip @[el2_dec_decode_ctl.scala 334:126]
|
||||
else : @[el2_dec_decode_ctl.scala 336:16]
|
||||
cam_in[3].rd <= cam[3].rd @[el2_dec_decode_ctl.scala 337:22]
|
||||
cam_in[3].tag <= cam[3].tag @[el2_dec_decode_ctl.scala 337:22]
|
||||
cam_in[3].wb <= cam[3].wb @[el2_dec_decode_ctl.scala 337:22]
|
||||
cam_in[3].bits.rd <= cam[3].bits.rd @[el2_dec_decode_ctl.scala 337:22]
|
||||
cam_in[3].bits.tag <= cam[3].bits.tag @[el2_dec_decode_ctl.scala 337:22]
|
||||
cam_in[3].bits.wb <= cam[3].bits.wb @[el2_dec_decode_ctl.scala 337:22]
|
||||
cam_in[3].valid <= cam[3].valid @[el2_dec_decode_ctl.scala 337:22]
|
||||
skip @[el2_dec_decode_ctl.scala 336:16]
|
||||
node _T_186 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37]
|
||||
node _T_187 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].tag) @[el2_dec_decode_ctl.scala 339:79]
|
||||
node _T_187 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 339:79]
|
||||
node _T_188 = and(_T_186, _T_187) @[el2_dec_decode_ctl.scala 339:44]
|
||||
node _T_189 = eq(cam[3].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110]
|
||||
node _T_190 = and(_T_188, _T_189) @[el2_dec_decode_ctl.scala 339:95]
|
||||
when _T_190 : @[el2_dec_decode_ctl.scala 339:117]
|
||||
cam_in[3].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20]
|
||||
skip @[el2_dec_decode_ctl.scala 339:117]
|
||||
node _T_189 = eq(cam[3].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115]
|
||||
node _T_190 = and(_T_188, _T_189) @[el2_dec_decode_ctl.scala 339:100]
|
||||
when _T_190 : @[el2_dec_decode_ctl.scala 339:122]
|
||||
cam_in[3].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25]
|
||||
skip @[el2_dec_decode_ctl.scala 339:122]
|
||||
when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32]
|
||||
cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23]
|
||||
skip @[el2_dec_decode_ctl.scala 343:32]
|
||||
wire _T_191 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_191.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_191.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_191.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
wire _T_191 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_191.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_191.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_191.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
_T_191.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70]
|
||||
reg _T_192 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_191)) @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_192.rd <= cam_in[3].rd @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_192.tag <= cam_in[3].tag @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_192.wb <= cam_in[3].wb @[el2_dec_decode_ctl.scala 347:47]
|
||||
reg _T_192 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_191)) @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_192.bits.rd <= cam_in[3].bits.rd @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_192.bits.tag <= cam_in[3].bits.tag @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_192.bits.wb <= cam_in[3].bits.wb @[el2_dec_decode_ctl.scala 347:47]
|
||||
_T_192.valid <= cam_in[3].valid @[el2_dec_decode_ctl.scala 347:47]
|
||||
cam_raw[3].rd <= _T_192.rd @[el2_dec_decode_ctl.scala 347:15]
|
||||
cam_raw[3].tag <= _T_192.tag @[el2_dec_decode_ctl.scala 347:15]
|
||||
cam_raw[3].wb <= _T_192.wb @[el2_dec_decode_ctl.scala 347:15]
|
||||
cam_raw[3].bits.rd <= _T_192.bits.rd @[el2_dec_decode_ctl.scala 347:15]
|
||||
cam_raw[3].bits.tag <= _T_192.bits.tag @[el2_dec_decode_ctl.scala 347:15]
|
||||
cam_raw[3].bits.wb <= _T_192.bits.wb @[el2_dec_decode_ctl.scala 347:15]
|
||||
cam_raw[3].valid <= _T_192.valid @[el2_dec_decode_ctl.scala 347:15]
|
||||
node _T_193 = eq(io.lsu_nonblock_load_data_tag, cam_raw[3].tag) @[el2_dec_decode_ctl.scala 348:46]
|
||||
node _T_194 = and(_T_193, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 348:66]
|
||||
node _T_193 = eq(io.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[el2_dec_decode_ctl.scala 348:46]
|
||||
node _T_194 = and(_T_193, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 348:71]
|
||||
nonblock_load_write[3] <= _T_194 @[el2_dec_decode_ctl.scala 348:28]
|
||||
io.dec_nonblock_load_waddr <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:29]
|
||||
node _T_195 = eq(r_d_in.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 353:44]
|
||||
|
|
@ -67628,40 +67628,40 @@ circuit el2_swerv_wrapper :
|
|||
i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[el2_dec_decode_ctl.scala 357:26]
|
||||
node _T_209 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_210 = mux(_T_209, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_211 = and(_T_210, cam[0].rd) @[el2_dec_decode_ctl.scala 359:88]
|
||||
node _T_212 = and(io.dec_i0_rs1_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:121]
|
||||
node _T_213 = eq(cam[0].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149]
|
||||
node _T_214 = and(_T_212, _T_213) @[el2_dec_decode_ctl.scala 359:136]
|
||||
node _T_215 = and(io.dec_i0_rs2_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:182]
|
||||
node _T_216 = eq(cam[0].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210]
|
||||
node _T_217 = and(_T_215, _T_216) @[el2_dec_decode_ctl.scala 359:197]
|
||||
node _T_211 = and(_T_210, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 359:88]
|
||||
node _T_212 = and(io.dec_i0_rs1_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:126]
|
||||
node _T_213 = eq(cam[0].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159]
|
||||
node _T_214 = and(_T_212, _T_213) @[el2_dec_decode_ctl.scala 359:141]
|
||||
node _T_215 = and(io.dec_i0_rs2_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:192]
|
||||
node _T_216 = eq(cam[0].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225]
|
||||
node _T_217 = and(_T_215, _T_216) @[el2_dec_decode_ctl.scala 359:207]
|
||||
node _T_218 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_219 = mux(_T_218, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_220 = and(_T_219, cam[1].rd) @[el2_dec_decode_ctl.scala 359:88]
|
||||
node _T_221 = and(io.dec_i0_rs1_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:121]
|
||||
node _T_222 = eq(cam[1].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149]
|
||||
node _T_223 = and(_T_221, _T_222) @[el2_dec_decode_ctl.scala 359:136]
|
||||
node _T_224 = and(io.dec_i0_rs2_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:182]
|
||||
node _T_225 = eq(cam[1].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210]
|
||||
node _T_226 = and(_T_224, _T_225) @[el2_dec_decode_ctl.scala 359:197]
|
||||
node _T_220 = and(_T_219, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 359:88]
|
||||
node _T_221 = and(io.dec_i0_rs1_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:126]
|
||||
node _T_222 = eq(cam[1].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159]
|
||||
node _T_223 = and(_T_221, _T_222) @[el2_dec_decode_ctl.scala 359:141]
|
||||
node _T_224 = and(io.dec_i0_rs2_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:192]
|
||||
node _T_225 = eq(cam[1].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225]
|
||||
node _T_226 = and(_T_224, _T_225) @[el2_dec_decode_ctl.scala 359:207]
|
||||
node _T_227 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_228 = mux(_T_227, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_229 = and(_T_228, cam[2].rd) @[el2_dec_decode_ctl.scala 359:88]
|
||||
node _T_230 = and(io.dec_i0_rs1_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:121]
|
||||
node _T_231 = eq(cam[2].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149]
|
||||
node _T_232 = and(_T_230, _T_231) @[el2_dec_decode_ctl.scala 359:136]
|
||||
node _T_233 = and(io.dec_i0_rs2_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:182]
|
||||
node _T_234 = eq(cam[2].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210]
|
||||
node _T_235 = and(_T_233, _T_234) @[el2_dec_decode_ctl.scala 359:197]
|
||||
node _T_229 = and(_T_228, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 359:88]
|
||||
node _T_230 = and(io.dec_i0_rs1_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:126]
|
||||
node _T_231 = eq(cam[2].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159]
|
||||
node _T_232 = and(_T_230, _T_231) @[el2_dec_decode_ctl.scala 359:141]
|
||||
node _T_233 = and(io.dec_i0_rs2_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:192]
|
||||
node _T_234 = eq(cam[2].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225]
|
||||
node _T_235 = and(_T_233, _T_234) @[el2_dec_decode_ctl.scala 359:207]
|
||||
node _T_236 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_237 = mux(_T_236, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_238 = and(_T_237, cam[3].rd) @[el2_dec_decode_ctl.scala 359:88]
|
||||
node _T_239 = and(io.dec_i0_rs1_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:121]
|
||||
node _T_240 = eq(cam[3].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149]
|
||||
node _T_241 = and(_T_239, _T_240) @[el2_dec_decode_ctl.scala 359:136]
|
||||
node _T_242 = and(io.dec_i0_rs2_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:182]
|
||||
node _T_243 = eq(cam[3].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210]
|
||||
node _T_244 = and(_T_242, _T_243) @[el2_dec_decode_ctl.scala 359:197]
|
||||
node _T_238 = and(_T_237, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 359:88]
|
||||
node _T_239 = and(io.dec_i0_rs1_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:126]
|
||||
node _T_240 = eq(cam[3].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159]
|
||||
node _T_241 = and(_T_239, _T_240) @[el2_dec_decode_ctl.scala 359:141]
|
||||
node _T_242 = and(io.dec_i0_rs2_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:192]
|
||||
node _T_243 = eq(cam[3].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225]
|
||||
node _T_244 = and(_T_242, _T_243) @[el2_dec_decode_ctl.scala 359:207]
|
||||
node _T_245 = or(_T_211, _T_220) @[el2_dec_decode_ctl.scala 360:69]
|
||||
node _T_246 = or(_T_245, _T_229) @[el2_dec_decode_ctl.scala 360:69]
|
||||
node waddr = or(_T_246, _T_238) @[el2_dec_decode_ctl.scala 360:69]
|
||||
|
|
|
|||
|
|
@ -46518,38 +46518,38 @@ module el2_dec_decode_ctl(
|
|||
wire _T_48 = ~_T_47; // @[el2_dec_decode_ctl.scala 276:26]
|
||||
wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 278:20]
|
||||
wire cam_data_reset = io_lsu_nonblock_load_data_valid | io_lsu_nonblock_load_data_error; // @[el2_dec_decode_ctl.scala 311:63]
|
||||
reg [2:0] cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
reg [2:0] cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire [2:0] _GEN_123 = {{1'd0}, io_lsu_nonblock_load_data_tag}; // @[el2_dec_decode_ctl.scala 322:67]
|
||||
wire _T_94 = _GEN_123 == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 322:67]
|
||||
wire _T_94 = _GEN_123 == cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 322:67]
|
||||
wire _T_95 = cam_data_reset & _T_94; // @[el2_dec_decode_ctl.scala 322:45]
|
||||
reg cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire cam_data_reset_val_0 = _T_95 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 322:83]
|
||||
wire cam_data_reset_val_0 = _T_95 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 322:88]
|
||||
wire cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 326:39]
|
||||
wire _T_51 = ~cam_0_valid; // @[el2_dec_decode_ctl.scala 303:78]
|
||||
reg [2:0] cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_120 = _GEN_123 == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 322:67]
|
||||
reg [2:0] cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_120 = _GEN_123 == cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 322:67]
|
||||
wire _T_121 = cam_data_reset & _T_120; // @[el2_dec_decode_ctl.scala 322:45]
|
||||
reg cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire cam_data_reset_val_1 = _T_121 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 322:83]
|
||||
wire cam_data_reset_val_1 = _T_121 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 322:88]
|
||||
wire cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 326:39]
|
||||
wire _T_54 = ~cam_1_valid; // @[el2_dec_decode_ctl.scala 303:78]
|
||||
wire _T_57 = cam_0_valid & _T_54; // @[el2_dec_decode_ctl.scala 303:126]
|
||||
wire [1:0] _T_59 = {io_lsu_nonblock_load_valid_m, 1'h0}; // @[el2_dec_decode_ctl.scala 303:158]
|
||||
reg [2:0] cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_146 = _GEN_123 == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 322:67]
|
||||
reg [2:0] cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_146 = _GEN_123 == cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 322:67]
|
||||
wire _T_147 = cam_data_reset & _T_146; // @[el2_dec_decode_ctl.scala 322:45]
|
||||
reg cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire cam_data_reset_val_2 = _T_147 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 322:83]
|
||||
wire cam_data_reset_val_2 = _T_147 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 322:88]
|
||||
wire cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 326:39]
|
||||
wire _T_60 = ~cam_2_valid; // @[el2_dec_decode_ctl.scala 303:78]
|
||||
wire _T_63 = cam_0_valid & cam_1_valid; // @[el2_dec_decode_ctl.scala 303:126]
|
||||
wire _T_66 = _T_63 & _T_60; // @[el2_dec_decode_ctl.scala 303:126]
|
||||
wire [2:0] _T_68 = {io_lsu_nonblock_load_valid_m, 2'h0}; // @[el2_dec_decode_ctl.scala 303:158]
|
||||
reg [2:0] cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_172 = _GEN_123 == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 322:67]
|
||||
reg [2:0] cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_172 = _GEN_123 == cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 322:67]
|
||||
wire _T_173 = cam_data_reset & _T_172; // @[el2_dec_decode_ctl.scala 322:45]
|
||||
reg cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire cam_data_reset_val_3 = _T_173 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 322:83]
|
||||
wire cam_data_reset_val_3 = _T_173 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 322:88]
|
||||
wire cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 326:39]
|
||||
wire _T_69 = ~cam_3_valid; // @[el2_dec_decode_ctl.scala 303:78]
|
||||
wire _T_75 = _T_63 & cam_2_valid; // @[el2_dec_decode_ctl.scala 303:126]
|
||||
|
|
@ -46576,76 +46576,76 @@ module el2_dec_decode_ctl(
|
|||
reg r_d_i0load; // @[el2_lib.scala 524:16]
|
||||
wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_i0load; // @[el2_dec_decode_ctl.scala 319:56]
|
||||
wire [2:0] _GEN_130 = {{1'd0}, io_lsu_nonblock_load_inv_tag_r}; // @[el2_dec_decode_ctl.scala 321:66]
|
||||
wire _T_91 = _GEN_130 == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 321:66]
|
||||
wire _T_91 = _GEN_130 == cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 321:66]
|
||||
wire _T_92 = io_lsu_nonblock_load_inv_r & _T_91; // @[el2_dec_decode_ctl.scala 321:45]
|
||||
wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[el2_dec_decode_ctl.scala 321:82]
|
||||
wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[el2_dec_decode_ctl.scala 321:87]
|
||||
reg r_d_i0v; // @[el2_lib.scala 524:16]
|
||||
wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 687:41]
|
||||
wire r_d_in_i0v = r_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 687:39]
|
||||
wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 695:42]
|
||||
wire i0_wen_r = r_d_in_i0v & _T_754; // @[el2_dec_decode_ctl.scala 695:40]
|
||||
reg [4:0] r_d_i0rd; // @[el2_lib.scala 524:16]
|
||||
reg [4:0] cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_103 = r_d_i0rd == cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 334:80]
|
||||
reg [4:0] cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_103 = r_d_i0rd == cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 334:80]
|
||||
wire _T_104 = i0_wen_r & _T_103; // @[el2_dec_decode_ctl.scala 334:64]
|
||||
reg cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_106 = _T_104 & cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 334:95]
|
||||
reg cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_106 = _T_104 & cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:100]
|
||||
wire _T_107 = cam_inv_reset_val_0 | _T_106; // @[el2_dec_decode_ctl.scala 334:44]
|
||||
wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 334:116]
|
||||
wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 334:116]
|
||||
wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 334:126]
|
||||
wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:126]
|
||||
wire _GEN_56 = cam_wen[0] | _GEN_52; // @[el2_dec_decode_ctl.scala 329:28]
|
||||
wire _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[el2_dec_decode_ctl.scala 329:28]
|
||||
wire _T_110 = nonblock_load_valid_m_delay & _T_91; // @[el2_dec_decode_ctl.scala 339:44]
|
||||
wire _T_112 = _T_110 & cam_0_valid; // @[el2_dec_decode_ctl.scala 339:95]
|
||||
wire nonblock_load_write_0 = _T_94 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 348:66]
|
||||
wire _T_117 = _GEN_130 == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 321:66]
|
||||
wire _T_112 = _T_110 & cam_0_valid; // @[el2_dec_decode_ctl.scala 339:100]
|
||||
wire nonblock_load_write_0 = _T_94 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 348:71]
|
||||
wire _T_117 = _GEN_130 == cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 321:66]
|
||||
wire _T_118 = io_lsu_nonblock_load_inv_r & _T_117; // @[el2_dec_decode_ctl.scala 321:45]
|
||||
wire cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[el2_dec_decode_ctl.scala 321:82]
|
||||
reg [4:0] cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_129 = r_d_i0rd == cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 334:80]
|
||||
wire cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[el2_dec_decode_ctl.scala 321:87]
|
||||
reg [4:0] cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_129 = r_d_i0rd == cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 334:80]
|
||||
wire _T_130 = i0_wen_r & _T_129; // @[el2_dec_decode_ctl.scala 334:64]
|
||||
reg cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_132 = _T_130 & cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 334:95]
|
||||
reg cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_132 = _T_130 & cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:100]
|
||||
wire _T_133 = cam_inv_reset_val_1 | _T_132; // @[el2_dec_decode_ctl.scala 334:44]
|
||||
wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 334:116]
|
||||
wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 334:116]
|
||||
wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 334:126]
|
||||
wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:126]
|
||||
wire _GEN_67 = cam_wen[1] | _GEN_63; // @[el2_dec_decode_ctl.scala 329:28]
|
||||
wire _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[el2_dec_decode_ctl.scala 329:28]
|
||||
wire _T_136 = nonblock_load_valid_m_delay & _T_117; // @[el2_dec_decode_ctl.scala 339:44]
|
||||
wire _T_138 = _T_136 & cam_1_valid; // @[el2_dec_decode_ctl.scala 339:95]
|
||||
wire nonblock_load_write_1 = _T_120 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 348:66]
|
||||
wire _T_143 = _GEN_130 == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 321:66]
|
||||
wire _T_138 = _T_136 & cam_1_valid; // @[el2_dec_decode_ctl.scala 339:100]
|
||||
wire nonblock_load_write_1 = _T_120 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 348:71]
|
||||
wire _T_143 = _GEN_130 == cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 321:66]
|
||||
wire _T_144 = io_lsu_nonblock_load_inv_r & _T_143; // @[el2_dec_decode_ctl.scala 321:45]
|
||||
wire cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[el2_dec_decode_ctl.scala 321:82]
|
||||
reg [4:0] cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_155 = r_d_i0rd == cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 334:80]
|
||||
wire cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[el2_dec_decode_ctl.scala 321:87]
|
||||
reg [4:0] cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_155 = r_d_i0rd == cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 334:80]
|
||||
wire _T_156 = i0_wen_r & _T_155; // @[el2_dec_decode_ctl.scala 334:64]
|
||||
reg cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_158 = _T_156 & cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 334:95]
|
||||
reg cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_158 = _T_156 & cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:100]
|
||||
wire _T_159 = cam_inv_reset_val_2 | _T_158; // @[el2_dec_decode_ctl.scala 334:44]
|
||||
wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 334:116]
|
||||
wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 334:116]
|
||||
wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 334:126]
|
||||
wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:126]
|
||||
wire _GEN_78 = cam_wen[2] | _GEN_74; // @[el2_dec_decode_ctl.scala 329:28]
|
||||
wire _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[el2_dec_decode_ctl.scala 329:28]
|
||||
wire _T_162 = nonblock_load_valid_m_delay & _T_143; // @[el2_dec_decode_ctl.scala 339:44]
|
||||
wire _T_164 = _T_162 & cam_2_valid; // @[el2_dec_decode_ctl.scala 339:95]
|
||||
wire nonblock_load_write_2 = _T_146 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 348:66]
|
||||
wire _T_169 = _GEN_130 == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 321:66]
|
||||
wire _T_164 = _T_162 & cam_2_valid; // @[el2_dec_decode_ctl.scala 339:100]
|
||||
wire nonblock_load_write_2 = _T_146 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 348:71]
|
||||
wire _T_169 = _GEN_130 == cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 321:66]
|
||||
wire _T_170 = io_lsu_nonblock_load_inv_r & _T_169; // @[el2_dec_decode_ctl.scala 321:45]
|
||||
wire cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[el2_dec_decode_ctl.scala 321:82]
|
||||
reg [4:0] cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_181 = r_d_i0rd == cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 334:80]
|
||||
wire cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[el2_dec_decode_ctl.scala 321:87]
|
||||
reg [4:0] cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_181 = r_d_i0rd == cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 334:80]
|
||||
wire _T_182 = i0_wen_r & _T_181; // @[el2_dec_decode_ctl.scala 334:64]
|
||||
reg cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_184 = _T_182 & cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 334:95]
|
||||
reg cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 347:47]
|
||||
wire _T_184 = _T_182 & cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:100]
|
||||
wire _T_185 = cam_inv_reset_val_3 | _T_184; // @[el2_dec_decode_ctl.scala 334:44]
|
||||
wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 334:116]
|
||||
wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 334:116]
|
||||
wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 334:126]
|
||||
wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:126]
|
||||
wire _GEN_89 = cam_wen[3] | _GEN_85; // @[el2_dec_decode_ctl.scala 329:28]
|
||||
wire _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[el2_dec_decode_ctl.scala 329:28]
|
||||
wire _T_188 = nonblock_load_valid_m_delay & _T_169; // @[el2_dec_decode_ctl.scala 339:44]
|
||||
wire _T_190 = _T_188 & cam_3_valid; // @[el2_dec_decode_ctl.scala 339:95]
|
||||
wire nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 348:66]
|
||||
wire _T_190 = _T_188 & cam_3_valid; // @[el2_dec_decode_ctl.scala 339:100]
|
||||
wire nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 348:71]
|
||||
wire _T_195 = r_d_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 353:44]
|
||||
wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[el2_dec_decode_ctl.scala 353:76]
|
||||
wire _T_196 = nonblock_load_write_0 | nonblock_load_write_1; // @[el2_dec_decode_ctl.scala 354:95]
|
||||
|
|
@ -46662,37 +46662,37 @@ module el2_dec_decode_ctl(
|
|||
wire _T_208 = _T_207 & io_dec_i0_rs2_en_d; // @[el2_dec_decode_ctl.scala 355:180]
|
||||
wire i0_nonblock_boundary_stall = _T_205 | _T_208; // @[el2_dec_decode_ctl.scala 355:118]
|
||||
wire [4:0] _T_210 = nonblock_load_write_0 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
|
||||
wire [4:0] _T_211 = _T_210 & cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 359:88]
|
||||
wire _T_212 = io_dec_i0_rs1_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:121]
|
||||
wire _T_213 = cam_raw_0_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149]
|
||||
wire _T_214 = _T_212 & _T_213; // @[el2_dec_decode_ctl.scala 359:136]
|
||||
wire _T_215 = io_dec_i0_rs2_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:182]
|
||||
wire _T_216 = cam_raw_0_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210]
|
||||
wire _T_217 = _T_215 & _T_216; // @[el2_dec_decode_ctl.scala 359:197]
|
||||
wire [4:0] _T_211 = _T_210 & cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 359:88]
|
||||
wire _T_212 = io_dec_i0_rs1_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:126]
|
||||
wire _T_213 = cam_raw_0_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159]
|
||||
wire _T_214 = _T_212 & _T_213; // @[el2_dec_decode_ctl.scala 359:141]
|
||||
wire _T_215 = io_dec_i0_rs2_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:192]
|
||||
wire _T_216 = cam_raw_0_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225]
|
||||
wire _T_217 = _T_215 & _T_216; // @[el2_dec_decode_ctl.scala 359:207]
|
||||
wire [4:0] _T_219 = nonblock_load_write_1 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
|
||||
wire [4:0] _T_220 = _T_219 & cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 359:88]
|
||||
wire _T_221 = io_dec_i0_rs1_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:121]
|
||||
wire _T_222 = cam_raw_1_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149]
|
||||
wire _T_223 = _T_221 & _T_222; // @[el2_dec_decode_ctl.scala 359:136]
|
||||
wire _T_224 = io_dec_i0_rs2_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:182]
|
||||
wire _T_225 = cam_raw_1_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210]
|
||||
wire _T_226 = _T_224 & _T_225; // @[el2_dec_decode_ctl.scala 359:197]
|
||||
wire [4:0] _T_220 = _T_219 & cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 359:88]
|
||||
wire _T_221 = io_dec_i0_rs1_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:126]
|
||||
wire _T_222 = cam_raw_1_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159]
|
||||
wire _T_223 = _T_221 & _T_222; // @[el2_dec_decode_ctl.scala 359:141]
|
||||
wire _T_224 = io_dec_i0_rs2_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:192]
|
||||
wire _T_225 = cam_raw_1_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225]
|
||||
wire _T_226 = _T_224 & _T_225; // @[el2_dec_decode_ctl.scala 359:207]
|
||||
wire [4:0] _T_228 = nonblock_load_write_2 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
|
||||
wire [4:0] _T_229 = _T_228 & cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 359:88]
|
||||
wire _T_230 = io_dec_i0_rs1_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:121]
|
||||
wire _T_231 = cam_raw_2_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149]
|
||||
wire _T_232 = _T_230 & _T_231; // @[el2_dec_decode_ctl.scala 359:136]
|
||||
wire _T_233 = io_dec_i0_rs2_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:182]
|
||||
wire _T_234 = cam_raw_2_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210]
|
||||
wire _T_235 = _T_233 & _T_234; // @[el2_dec_decode_ctl.scala 359:197]
|
||||
wire [4:0] _T_229 = _T_228 & cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 359:88]
|
||||
wire _T_230 = io_dec_i0_rs1_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:126]
|
||||
wire _T_231 = cam_raw_2_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159]
|
||||
wire _T_232 = _T_230 & _T_231; // @[el2_dec_decode_ctl.scala 359:141]
|
||||
wire _T_233 = io_dec_i0_rs2_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:192]
|
||||
wire _T_234 = cam_raw_2_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225]
|
||||
wire _T_235 = _T_233 & _T_234; // @[el2_dec_decode_ctl.scala 359:207]
|
||||
wire [4:0] _T_237 = nonblock_load_write_3 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
|
||||
wire [4:0] _T_238 = _T_237 & cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 359:88]
|
||||
wire _T_239 = io_dec_i0_rs1_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:121]
|
||||
wire _T_240 = cam_raw_3_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149]
|
||||
wire _T_241 = _T_239 & _T_240; // @[el2_dec_decode_ctl.scala 359:136]
|
||||
wire _T_242 = io_dec_i0_rs2_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:182]
|
||||
wire _T_243 = cam_raw_3_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210]
|
||||
wire _T_244 = _T_242 & _T_243; // @[el2_dec_decode_ctl.scala 359:197]
|
||||
wire [4:0] _T_238 = _T_237 & cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 359:88]
|
||||
wire _T_239 = io_dec_i0_rs1_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:126]
|
||||
wire _T_240 = cam_raw_3_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159]
|
||||
wire _T_241 = _T_239 & _T_240; // @[el2_dec_decode_ctl.scala 359:141]
|
||||
wire _T_242 = io_dec_i0_rs2_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:192]
|
||||
wire _T_243 = cam_raw_3_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225]
|
||||
wire _T_244 = _T_242 & _T_243; // @[el2_dec_decode_ctl.scala 359:207]
|
||||
wire [4:0] _T_245 = _T_211 | _T_220; // @[el2_dec_decode_ctl.scala 360:69]
|
||||
wire [4:0] _T_246 = _T_245 | _T_229; // @[el2_dec_decode_ctl.scala 360:69]
|
||||
wire _T_247 = _T_214 | _T_223; // @[el2_dec_decode_ctl.scala 360:102]
|
||||
|
|
@ -47441,19 +47441,19 @@ initial begin
|
|||
_RAND_9 = {1{`RANDOM}};
|
||||
illegal_lockout = _RAND_9[0:0];
|
||||
_RAND_10 = {1{`RANDOM}};
|
||||
cam_raw_0_tag = _RAND_10[2:0];
|
||||
cam_raw_0_bits_tag = _RAND_10[2:0];
|
||||
_RAND_11 = {1{`RANDOM}};
|
||||
cam_raw_0_valid = _RAND_11[0:0];
|
||||
_RAND_12 = {1{`RANDOM}};
|
||||
cam_raw_1_tag = _RAND_12[2:0];
|
||||
cam_raw_1_bits_tag = _RAND_12[2:0];
|
||||
_RAND_13 = {1{`RANDOM}};
|
||||
cam_raw_1_valid = _RAND_13[0:0];
|
||||
_RAND_14 = {1{`RANDOM}};
|
||||
cam_raw_2_tag = _RAND_14[2:0];
|
||||
cam_raw_2_bits_tag = _RAND_14[2:0];
|
||||
_RAND_15 = {1{`RANDOM}};
|
||||
cam_raw_2_valid = _RAND_15[0:0];
|
||||
_RAND_16 = {1{`RANDOM}};
|
||||
cam_raw_3_tag = _RAND_16[2:0];
|
||||
cam_raw_3_bits_tag = _RAND_16[2:0];
|
||||
_RAND_17 = {1{`RANDOM}};
|
||||
cam_raw_3_valid = _RAND_17[0:0];
|
||||
_RAND_18 = {1{`RANDOM}};
|
||||
|
|
@ -47471,21 +47471,21 @@ initial begin
|
|||
_RAND_24 = {1{`RANDOM}};
|
||||
r_d_i0rd = _RAND_24[4:0];
|
||||
_RAND_25 = {1{`RANDOM}};
|
||||
cam_raw_0_rd = _RAND_25[4:0];
|
||||
cam_raw_0_bits_rd = _RAND_25[4:0];
|
||||
_RAND_26 = {1{`RANDOM}};
|
||||
cam_raw_0_wb = _RAND_26[0:0];
|
||||
cam_raw_0_bits_wb = _RAND_26[0:0];
|
||||
_RAND_27 = {1{`RANDOM}};
|
||||
cam_raw_1_rd = _RAND_27[4:0];
|
||||
cam_raw_1_bits_rd = _RAND_27[4:0];
|
||||
_RAND_28 = {1{`RANDOM}};
|
||||
cam_raw_1_wb = _RAND_28[0:0];
|
||||
cam_raw_1_bits_wb = _RAND_28[0:0];
|
||||
_RAND_29 = {1{`RANDOM}};
|
||||
cam_raw_2_rd = _RAND_29[4:0];
|
||||
cam_raw_2_bits_rd = _RAND_29[4:0];
|
||||
_RAND_30 = {1{`RANDOM}};
|
||||
cam_raw_2_wb = _RAND_30[0:0];
|
||||
cam_raw_2_bits_wb = _RAND_30[0:0];
|
||||
_RAND_31 = {1{`RANDOM}};
|
||||
cam_raw_3_rd = _RAND_31[4:0];
|
||||
cam_raw_3_bits_rd = _RAND_31[4:0];
|
||||
_RAND_32 = {1{`RANDOM}};
|
||||
cam_raw_3_wb = _RAND_32[0:0];
|
||||
cam_raw_3_bits_wb = _RAND_32[0:0];
|
||||
_RAND_33 = {1{`RANDOM}};
|
||||
lsu_idle = _RAND_33[0:0];
|
||||
_RAND_34 = {1{`RANDOM}};
|
||||
|
|
@ -47634,25 +47634,25 @@ initial begin
|
|||
illegal_lockout = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cam_raw_0_tag = 3'h0;
|
||||
cam_raw_0_bits_tag = 3'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cam_raw_0_valid = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cam_raw_1_tag = 3'h0;
|
||||
cam_raw_1_bits_tag = 3'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cam_raw_1_valid = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cam_raw_2_tag = 3'h0;
|
||||
cam_raw_2_bits_tag = 3'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cam_raw_2_valid = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cam_raw_3_tag = 3'h0;
|
||||
cam_raw_3_bits_tag = 3'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cam_raw_3_valid = 1'h0;
|
||||
|
|
@ -47679,28 +47679,28 @@ initial begin
|
|||
r_d_i0rd = 5'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cam_raw_0_rd = 5'h0;
|
||||
cam_raw_0_bits_rd = 5'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cam_raw_0_wb = 1'h0;
|
||||
cam_raw_0_bits_wb = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cam_raw_1_rd = 5'h0;
|
||||
cam_raw_1_bits_rd = 5'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cam_raw_1_wb = 1'h0;
|
||||
cam_raw_1_bits_wb = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cam_raw_2_rd = 5'h0;
|
||||
cam_raw_2_bits_rd = 5'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cam_raw_2_wb = 1'h0;
|
||||
cam_raw_2_bits_wb = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cam_raw_3_rd = 5'h0;
|
||||
cam_raw_3_bits_rd = 5'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
cam_raw_3_wb = 1'h0;
|
||||
cam_raw_3_bits_wb = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
lsu_idle = 1'h0;
|
||||
|
|
@ -47960,11 +47960,11 @@ end // initial
|
|||
end
|
||||
always @(posedge io_free_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
cam_raw_0_tag <= 3'h0;
|
||||
cam_raw_0_bits_tag <= 3'h0;
|
||||
end else if (cam_wen[0]) begin
|
||||
cam_raw_0_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m};
|
||||
cam_raw_0_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m};
|
||||
end else if (_T_107) begin
|
||||
cam_raw_0_tag <= 3'h0;
|
||||
cam_raw_0_bits_tag <= 3'h0;
|
||||
end
|
||||
end
|
||||
always @(posedge io_free_clk or posedge reset) begin
|
||||
|
|
@ -47978,11 +47978,11 @@ end // initial
|
|||
end
|
||||
always @(posedge io_free_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
cam_raw_1_tag <= 3'h0;
|
||||
cam_raw_1_bits_tag <= 3'h0;
|
||||
end else if (cam_wen[1]) begin
|
||||
cam_raw_1_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m};
|
||||
cam_raw_1_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m};
|
||||
end else if (_T_133) begin
|
||||
cam_raw_1_tag <= 3'h0;
|
||||
cam_raw_1_bits_tag <= 3'h0;
|
||||
end
|
||||
end
|
||||
always @(posedge io_free_clk or posedge reset) begin
|
||||
|
|
@ -47996,11 +47996,11 @@ end // initial
|
|||
end
|
||||
always @(posedge io_free_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
cam_raw_2_tag <= 3'h0;
|
||||
cam_raw_2_bits_tag <= 3'h0;
|
||||
end else if (cam_wen[2]) begin
|
||||
cam_raw_2_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m};
|
||||
cam_raw_2_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m};
|
||||
end else if (_T_159) begin
|
||||
cam_raw_2_tag <= 3'h0;
|
||||
cam_raw_2_bits_tag <= 3'h0;
|
||||
end
|
||||
end
|
||||
always @(posedge io_free_clk or posedge reset) begin
|
||||
|
|
@ -48014,11 +48014,11 @@ end // initial
|
|||
end
|
||||
always @(posedge io_free_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
cam_raw_3_tag <= 3'h0;
|
||||
cam_raw_3_bits_tag <= 3'h0;
|
||||
end else if (cam_wen[3]) begin
|
||||
cam_raw_3_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m};
|
||||
cam_raw_3_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m};
|
||||
end else if (_T_185) begin
|
||||
cam_raw_3_tag <= 3'h0;
|
||||
cam_raw_3_bits_tag <= 3'h0;
|
||||
end
|
||||
end
|
||||
always @(posedge io_free_clk or posedge reset) begin
|
||||
|
|
@ -48081,82 +48081,82 @@ end // initial
|
|||
end
|
||||
always @(posedge io_free_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
cam_raw_0_rd <= 5'h0;
|
||||
cam_raw_0_bits_rd <= 5'h0;
|
||||
end else if (cam_wen[0]) begin
|
||||
if (x_d_i0load) begin
|
||||
cam_raw_0_rd <= x_d_i0rd;
|
||||
cam_raw_0_bits_rd <= x_d_i0rd;
|
||||
end else begin
|
||||
cam_raw_0_rd <= 5'h0;
|
||||
cam_raw_0_bits_rd <= 5'h0;
|
||||
end
|
||||
end else if (_T_107) begin
|
||||
cam_raw_0_rd <= 5'h0;
|
||||
cam_raw_0_bits_rd <= 5'h0;
|
||||
end
|
||||
end
|
||||
always @(posedge io_free_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
cam_raw_0_wb <= 1'h0;
|
||||
cam_raw_0_bits_wb <= 1'h0;
|
||||
end else begin
|
||||
cam_raw_0_wb <= _T_112 | _GEN_57;
|
||||
cam_raw_0_bits_wb <= _T_112 | _GEN_57;
|
||||
end
|
||||
end
|
||||
always @(posedge io_free_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
cam_raw_1_rd <= 5'h0;
|
||||
cam_raw_1_bits_rd <= 5'h0;
|
||||
end else if (cam_wen[1]) begin
|
||||
if (x_d_i0load) begin
|
||||
cam_raw_1_rd <= x_d_i0rd;
|
||||
cam_raw_1_bits_rd <= x_d_i0rd;
|
||||
end else begin
|
||||
cam_raw_1_rd <= 5'h0;
|
||||
cam_raw_1_bits_rd <= 5'h0;
|
||||
end
|
||||
end else if (_T_133) begin
|
||||
cam_raw_1_rd <= 5'h0;
|
||||
cam_raw_1_bits_rd <= 5'h0;
|
||||
end
|
||||
end
|
||||
always @(posedge io_free_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
cam_raw_1_wb <= 1'h0;
|
||||
cam_raw_1_bits_wb <= 1'h0;
|
||||
end else begin
|
||||
cam_raw_1_wb <= _T_138 | _GEN_68;
|
||||
cam_raw_1_bits_wb <= _T_138 | _GEN_68;
|
||||
end
|
||||
end
|
||||
always @(posedge io_free_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
cam_raw_2_rd <= 5'h0;
|
||||
cam_raw_2_bits_rd <= 5'h0;
|
||||
end else if (cam_wen[2]) begin
|
||||
if (x_d_i0load) begin
|
||||
cam_raw_2_rd <= x_d_i0rd;
|
||||
cam_raw_2_bits_rd <= x_d_i0rd;
|
||||
end else begin
|
||||
cam_raw_2_rd <= 5'h0;
|
||||
cam_raw_2_bits_rd <= 5'h0;
|
||||
end
|
||||
end else if (_T_159) begin
|
||||
cam_raw_2_rd <= 5'h0;
|
||||
cam_raw_2_bits_rd <= 5'h0;
|
||||
end
|
||||
end
|
||||
always @(posedge io_free_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
cam_raw_2_wb <= 1'h0;
|
||||
cam_raw_2_bits_wb <= 1'h0;
|
||||
end else begin
|
||||
cam_raw_2_wb <= _T_164 | _GEN_79;
|
||||
cam_raw_2_bits_wb <= _T_164 | _GEN_79;
|
||||
end
|
||||
end
|
||||
always @(posedge io_free_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
cam_raw_3_rd <= 5'h0;
|
||||
cam_raw_3_bits_rd <= 5'h0;
|
||||
end else if (cam_wen[3]) begin
|
||||
if (x_d_i0load) begin
|
||||
cam_raw_3_rd <= x_d_i0rd;
|
||||
cam_raw_3_bits_rd <= x_d_i0rd;
|
||||
end else begin
|
||||
cam_raw_3_rd <= 5'h0;
|
||||
cam_raw_3_bits_rd <= 5'h0;
|
||||
end
|
||||
end else if (_T_185) begin
|
||||
cam_raw_3_rd <= 5'h0;
|
||||
cam_raw_3_bits_rd <= 5'h0;
|
||||
end
|
||||
end
|
||||
always @(posedge io_free_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
cam_raw_3_wb <= 1'h0;
|
||||
cam_raw_3_bits_wb <= 1'h0;
|
||||
end else begin
|
||||
cam_raw_3_wb <= _T_190 | _GEN_90;
|
||||
cam_raw_3_bits_wb <= _T_190 | _GEN_90;
|
||||
end
|
||||
end
|
||||
always @(posedge io_active_clk or posedge reset) begin
|
||||
|
|
|
|||
|
|
@ -144,13 +144,13 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
val i0_rs1_depth_d = WireInit(UInt(2.W),0.U)
|
||||
val i0_rs2_depth_d = WireInit(UInt(2.W),0.U)
|
||||
val cam_wen=WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U)
|
||||
val cam = Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t))
|
||||
val cam = Wire(Vec(LSU_NUM_NBLOAD,Valid(new el2_load_cam_pkt_t)))
|
||||
val cam_write=WireInit(UInt(1.W), 0.U)
|
||||
val cam_inv_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
||||
val cam_data_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
||||
val nonblock_load_write=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
||||
val cam_raw =Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t))
|
||||
val cam_in =Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t))
|
||||
val cam_raw =Wire(Vec(LSU_NUM_NBLOAD,Valid(new el2_load_cam_pkt_t)))
|
||||
val cam_in =Wire(Vec(LSU_NUM_NBLOAD,Valid(new el2_load_cam_pkt_t)))
|
||||
//val i0_temp = Wire(new el2_inst_pkt_t)
|
||||
val i0_dp= Wire(new el2_dec_pkt_t)
|
||||
val i0_dp_raw= Wire(new el2_dec_pkt_t)
|
||||
|
|
@ -318,8 +318,8 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
val nonblock_load_valid_m_delay=withClock(io.active_clk){RegEnable(io.lsu_nonblock_load_valid_m,0.U, i0_r_ctl_en.asBool)}
|
||||
val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.i0load
|
||||
for(i <- 0 until LSU_NUM_NBLOAD){
|
||||
cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).tag) & cam(i).valid
|
||||
cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).tag) & cam_raw(i).valid
|
||||
cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).bits.tag) & cam(i).valid
|
||||
cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).bits.tag) & cam_raw(i).valid
|
||||
cam_in(i):=0.U.asTypeOf(cam(0))
|
||||
cam(i):=cam_raw(i)
|
||||
|
||||
|
|
@ -328,16 +328,16 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
}
|
||||
when(cam_wen(i).asBool){
|
||||
cam_in(i).valid := 1.U(1.W)
|
||||
cam_in(i).wb := 0.U(1.W)
|
||||
cam_in(i).tag := cam_write_tag
|
||||
cam_in(i).rd := nonblock_load_rd
|
||||
}.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.i0rd === cam(i).rd) && cam(i).wb.asBool)){
|
||||
cam_in(i).bits.wb := 0.U(1.W)
|
||||
cam_in(i).bits.tag := cam_write_tag
|
||||
cam_in(i).bits.rd := nonblock_load_rd
|
||||
}.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.i0rd === cam(i).bits.rd) && cam(i).bits.wb.asBool)){
|
||||
cam_in(i).valid := 0.U
|
||||
}.otherwise{
|
||||
cam_in(i) := cam(i)
|
||||
}
|
||||
when(nonblock_load_valid_m_delay===1.U && (io.lsu_nonblock_load_inv_tag_r === cam(i).tag) && cam(i).valid===1.U){
|
||||
cam_in(i).wb := 1.U
|
||||
when(nonblock_load_valid_m_delay===1.U && (io.lsu_nonblock_load_inv_tag_r === cam(i).bits.tag) && cam(i).valid===1.U){
|
||||
cam_in(i).bits.wb := 1.U
|
||||
}
|
||||
// force debug halt forces cam valids to 0; highest priority
|
||||
when(io.dec_tlu_force_halt){
|
||||
|
|
@ -345,7 +345,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
}
|
||||
|
||||
cam_raw(i):=withClock(io.free_clk){RegNext(cam_in(i),0.U.asTypeOf(cam(0)))}
|
||||
nonblock_load_write(i) := (load_data_tag === cam_raw(i).tag) & cam_raw(i).valid
|
||||
nonblock_load_write(i) := (load_data_tag === cam_raw(i).bits.tag) & cam_raw(i).valid
|
||||
}
|
||||
|
||||
io.dec_nonblock_load_waddr:=0.U(5.W)
|
||||
|
|
@ -356,7 +356,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
|
||||
i0_nonblock_load_stall := i0_nonblock_boundary_stall
|
||||
|
||||
val cal_temp= for(i <-0 until LSU_NUM_NBLOAD) yield ((Fill(5,nonblock_load_write(i)) & cam(i).rd), io.dec_i0_rs1_en_d & cam(i).valid & (cam(i).rd === i0r.rs1), io.dec_i0_rs2_en_d & cam(i).valid & (cam(i).rd === i0r.rs2))
|
||||
val cal_temp= for(i <-0 until LSU_NUM_NBLOAD) yield ((Fill(5,nonblock_load_write(i)) & cam(i).bits.rd), io.dec_i0_rs1_en_d & cam(i).valid & (cam(i).bits.rd === i0r.rs1), io.dec_i0_rs2_en_d & cam(i).valid & (cam(i).bits.rd === i0r.rs2))
|
||||
val (waddr, ld_stall_1, ld_stall_2) = (cal_temp.map(_._1).reduce(_|_) , cal_temp.map(_._2).reduce(_|_), cal_temp.map(_._3).reduce(_|_) )
|
||||
io.dec_nonblock_load_waddr:=waddr
|
||||
i0_nonblock_load_stall:=ld_stall_1 | ld_stall_2 | i0_nonblock_boundary_stall
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ object el2_inst_pkt_t extends Enumeration{
|
|||
}
|
||||
|
||||
class el2_load_cam_pkt_t extends Bundle {
|
||||
val valid = UInt(1.W)
|
||||
//val valid = UInt(1.W)
|
||||
val wb = UInt(1.W)
|
||||
val tag = UInt(3.W)
|
||||
val rd = UInt(5.W)
|
||||
|
|
|
|||
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Reference in New Issue