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axi to ahb update

This commit is contained in:
​Laraib Khan 2020-12-01 11:44:51 +05:00
parent 6a0fe72da2
commit e6054811cd
4 changed files with 101 additions and 98 deletions
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81
axi4_to_ahb.fir
View File

@ -507,6 +507,7 @@ circuit axi4_to_ahb :
buf_nxtstate <= _T_51 @[axi4_to_ahb.scala 249:20]
node _T_52 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 250:36]
buf_state_en <= _T_52 @[axi4_to_ahb.scala 250:20]
buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 251:17]
node _T_53 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 252:54]
node _T_54 = and(buf_state_en, _T_53) @[axi4_to_ahb.scala 252:38]
buf_data_wr_en <= _T_54 @[axi4_to_ahb.scala 252:22]
@ -592,6 +593,7 @@ circuit axi4_to_ahb :
node _T_122 = eq(_T_121, UInt<3>("h06")) @[axi4_to_ahb.scala 266:174]
node _T_123 = and(_T_116, _T_122) @[axi4_to_ahb.scala 266:88]
master_ready <= _T_123 @[axi4_to_ahb.scala 266:20]
buf_wr_en <= master_ready @[axi4_to_ahb.scala 267:17]
node _T_124 = and(master_ready, master_valid) @[axi4_to_ahb.scala 268:33]
bypass_en <= _T_124 @[axi4_to_ahb.scala 268:17]
node _T_125 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 269:47]
@ -617,48 +619,49 @@ circuit axi4_to_ahb :
node _T_140 = eq(_T_139, UInt<1>("h00")) @[axi4_to_ahb.scala 274:55]
node _T_141 = and(_T_136, _T_140) @[axi4_to_ahb.scala 274:53]
master_ready <= _T_141 @[axi4_to_ahb.scala 274:20]
node _T_142 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 276:45]
node _T_143 = and(master_valid, master_ready) @[axi4_to_ahb.scala 276:82]
node _T_144 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 276:110]
node _T_145 = eq(_T_144, UInt<1>("h00")) @[axi4_to_ahb.scala 276:117]
node _T_146 = and(_T_143, _T_145) @[axi4_to_ahb.scala 276:97]
node _T_147 = bits(_T_146, 0, 0) @[axi4_to_ahb.scala 276:138]
node _T_148 = mux(_T_147, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 276:67]
node _T_149 = mux(_T_142, UInt<3>("h07"), _T_148) @[axi4_to_ahb.scala 276:26]
buf_nxtstate <= _T_149 @[axi4_to_ahb.scala 276:20]
node _T_150 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 277:37]
buf_state_en <= _T_150 @[axi4_to_ahb.scala 277:20]
node _T_142 = and(master_valid, master_ready) @[axi4_to_ahb.scala 275:34]
node _T_143 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 275:62]
node _T_144 = eq(_T_143, UInt<1>("h00")) @[axi4_to_ahb.scala 275:69]
node _T_145 = and(_T_142, _T_144) @[axi4_to_ahb.scala 275:49]
buf_wr_en <= _T_145 @[axi4_to_ahb.scala 275:17]
node _T_146 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 276:45]
node _T_147 = and(master_valid, master_ready) @[axi4_to_ahb.scala 276:82]
node _T_148 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 276:110]
node _T_149 = eq(_T_148, UInt<1>("h00")) @[axi4_to_ahb.scala 276:117]
node _T_150 = and(_T_147, _T_149) @[axi4_to_ahb.scala 276:97]
node _T_151 = bits(_T_150, 0, 0) @[axi4_to_ahb.scala 276:138]
node _T_152 = mux(_T_151, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 276:67]
node _T_153 = mux(_T_146, UInt<3>("h07"), _T_152) @[axi4_to_ahb.scala 276:26]
buf_nxtstate <= _T_153 @[axi4_to_ahb.scala 276:20]
node _T_154 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 277:37]
buf_state_en <= _T_154 @[axi4_to_ahb.scala 277:20]
buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 278:22]
slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 279:23]
slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 280:23]
node _T_151 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 281:41]
node _T_152 = and(buf_state_en, _T_151) @[axi4_to_ahb.scala 281:39]
slave_valid_pre <= _T_152 @[axi4_to_ahb.scala 281:23]
node _T_153 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 282:34]
node _T_154 = and(buf_state_en, _T_153) @[axi4_to_ahb.scala 282:32]
cmd_done <= _T_154 @[axi4_to_ahb.scala 282:16]
node _T_155 = and(master_ready, master_valid) @[axi4_to_ahb.scala 283:33]
node _T_156 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 283:64]
node _T_157 = and(_T_155, _T_156) @[axi4_to_ahb.scala 283:48]
node _T_158 = and(_T_157, buf_state_en) @[axi4_to_ahb.scala 283:79]
bypass_en <= _T_158 @[axi4_to_ahb.scala 283:17]
node _T_159 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 284:47]
node _T_160 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 284:62]
node _T_161 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 284:78]
node _T_162 = mux(_T_159, _T_160, _T_161) @[axi4_to_ahb.scala 284:30]
buf_cmd_byte_ptr <= _T_162 @[axi4_to_ahb.scala 284:24]
node _T_163 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 285:59]
node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 285:74]
node _T_165 = eq(_T_164, UInt<1>("h00")) @[axi4_to_ahb.scala 285:43]
node _T_166 = bits(_T_165, 0, 0) @[Bitwise.scala 72:15]
node _T_167 = mux(_T_166, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_168 = and(UInt<2>("h02"), _T_167) @[axi4_to_ahb.scala 285:32]
io.ahb_htrans <= _T_168 @[axi4_to_ahb.scala 285:21]
node _T_169 = and(master_valid, master_ready) @[axi4_to_ahb.scala 286:37]
node _T_170 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 286:65]
node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 286:72]
node _T_172 = and(_T_169, _T_171) @[axi4_to_ahb.scala 286:52]
slvbuf_wr_en <= _T_172 @[axi4_to_ahb.scala 286:20]
node _T_155 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 281:41]
node _T_156 = and(buf_state_en, _T_155) @[axi4_to_ahb.scala 281:39]
slave_valid_pre <= _T_156 @[axi4_to_ahb.scala 281:23]
node _T_157 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 282:34]
node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 282:32]
cmd_done <= _T_158 @[axi4_to_ahb.scala 282:16]
node _T_159 = and(master_ready, master_valid) @[axi4_to_ahb.scala 283:33]
node _T_160 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 283:64]
node _T_161 = and(_T_159, _T_160) @[axi4_to_ahb.scala 283:48]
node _T_162 = and(_T_161, buf_state_en) @[axi4_to_ahb.scala 283:79]
bypass_en <= _T_162 @[axi4_to_ahb.scala 283:17]
node _T_163 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 284:47]
node _T_164 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 284:62]
node _T_165 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 284:78]
node _T_166 = mux(_T_163, _T_164, _T_165) @[axi4_to_ahb.scala 284:30]
buf_cmd_byte_ptr <= _T_166 @[axi4_to_ahb.scala 284:24]
node _T_167 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 285:59]
node _T_168 = and(_T_167, buf_state_en) @[axi4_to_ahb.scala 285:74]
node _T_169 = eq(_T_168, UInt<1>("h00")) @[axi4_to_ahb.scala 285:43]
node _T_170 = bits(_T_169, 0, 0) @[Bitwise.scala 72:15]
node _T_171 = mux(_T_170, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_172 = and(UInt<2>("h02"), _T_171) @[axi4_to_ahb.scala 285:32]
io.ahb_htrans <= _T_172 @[axi4_to_ahb.scala 285:21]
slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 286:20]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_173 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30]

110
axi4_to_ahb.v
View File

@ -151,7 +151,7 @@ module axi4_to_ahb(
wire _T_109 = _T_107 & _T_108; // @[axi4_to_ahb.scala 263:70]
wire _T_134 = 3'h6 == buf_state; // @[Conditional.scala 37:30]
reg ahb_hresp_q; // @[axi4_to_ahb.scala 454:12]
wire _T_150 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 277:37]
wire _T_154 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 277:37]
wire _T_173 = 3'h7 == buf_state; // @[Conditional.scala 37:30]
wire _T_184 = 3'h3 == buf_state; // @[Conditional.scala 37:30]
wire _T_186 = 3'h2 == buf_state; // @[Conditional.scala 37:30]
@ -162,9 +162,9 @@ module axi4_to_ahb(
wire _GEN_19 = _T_186 ? _T_190 : _GEN_15; // @[Conditional.scala 39:67]
wire _GEN_40 = _T_184 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67]
wire _GEN_59 = _T_173 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67]
wire _GEN_78 = _T_134 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67]
wire _GEN_94 = _T_99 ? 1'h0 : _GEN_78; // @[Conditional.scala 39:67]
wire trxn_done = _T_47 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58]
wire _GEN_79 = _T_134 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67]
wire _GEN_95 = _T_99 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67]
wire trxn_done = _T_47 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58]
reg cmd_doneQ; // @[axi4_to_ahb.scala 436:12]
wire _T_280 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 319:34]
wire _T_281 = _T_280 | ahb_hresp_q; // @[axi4_to_ahb.scala 319:50]
@ -173,10 +173,10 @@ module axi4_to_ahb(
wire _GEN_1 = _T_442 & slave_ready; // @[Conditional.scala 39:67]
wire _GEN_3 = _T_279 ? _T_281 : _GEN_1; // @[Conditional.scala 39:67]
wire _GEN_20 = _T_186 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67]
wire _GEN_35 = _T_184 ? _T_150 : _GEN_20; // @[Conditional.scala 39:67]
wire _GEN_35 = _T_184 ? _T_154 : _GEN_20; // @[Conditional.scala 39:67]
wire _GEN_51 = _T_173 ? _T_109 : _GEN_35; // @[Conditional.scala 39:67]
wire _GEN_68 = _T_134 ? _T_150 : _GEN_51; // @[Conditional.scala 39:67]
wire _GEN_83 = _T_99 ? _T_109 : _GEN_68; // @[Conditional.scala 39:67]
wire _GEN_69 = _T_134 ? _T_154 : _GEN_51; // @[Conditional.scala 39:67]
wire _GEN_83 = _T_99 ? _T_109 : _GEN_69; // @[Conditional.scala 39:67]
wire buf_state_en = _T_47 ? master_valid : _GEN_83; // @[Conditional.scala 40:58]
wire [1:0] _T_12 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 203:20]
wire [2:0] master_opc = {{1'd0}, _T_12}; // @[axi4_to_ahb.scala 203:14]
@ -185,9 +185,9 @@ module axi4_to_ahb(
wire _GEN_29 = _T_186 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67]
wire _GEN_46 = _T_184 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67]
wire _GEN_63 = _T_173 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67]
wire _GEN_80 = _T_134 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67]
wire _GEN_96 = _T_99 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67]
wire buf_write_in = _T_47 ? _T_49 : _GEN_96; // @[Conditional.scala 40:58]
wire _GEN_81 = _T_134 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67]
wire _GEN_97 = _T_99 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67]
wire buf_write_in = _T_47 ? _T_49 : _GEN_97; // @[Conditional.scala 40:58]
wire [2:0] _T_51 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 249:26]
wire _T_101 = master_opc == 3'h0; // @[axi4_to_ahb.scala 262:61]
wire _T_102 = master_valid & _T_101; // @[axi4_to_ahb.scala 262:41]
@ -208,21 +208,21 @@ module axi4_to_ahb(
wire _GEN_66 = _T_134 ? _T_141 : _GEN_62; // @[Conditional.scala 39:67]
wire _GEN_86 = _T_99 ? _T_123 : _GEN_66; // @[Conditional.scala 39:67]
wire master_ready = _T_47 | _GEN_86; // @[Conditional.scala 40:58]
wire _T_143 = master_valid & master_ready; // @[axi4_to_ahb.scala 276:82]
wire _T_146 = _T_143 & _T_101; // @[axi4_to_ahb.scala 276:97]
wire [2:0] _T_148 = _T_146 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 276:67]
wire [2:0] _T_149 = ahb_hresp_q ? 3'h7 : _T_148; // @[axi4_to_ahb.scala 276:26]
wire _T_147 = master_valid & master_ready; // @[axi4_to_ahb.scala 276:82]
wire _T_150 = _T_147 & _T_101; // @[axi4_to_ahb.scala 276:97]
wire [2:0] _T_152 = _T_150 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 276:67]
wire [2:0] _T_153 = ahb_hresp_q ? 3'h7 : _T_152; // @[axi4_to_ahb.scala 276:26]
wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 321:42]
wire _T_288 = ahb_hresp_q | _T_287; // @[axi4_to_ahb.scala 321:40]
wire [2:0] _T_294 = _T_49 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 321:119]
wire [2:0] _T_295 = _T_143 ? _T_294 : 3'h0; // @[axi4_to_ahb.scala 321:75]
wire [2:0] _T_295 = _T_147 ? _T_294 : 3'h0; // @[axi4_to_ahb.scala 321:75]
wire [2:0] _T_296 = _T_288 ? 3'h5 : _T_295; // @[axi4_to_ahb.scala 321:26]
wire [2:0] _GEN_5 = _T_279 ? _T_296 : 3'h0; // @[Conditional.scala 39:67]
wire [2:0] _GEN_18 = _T_186 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67]
wire [2:0] _GEN_34 = _T_184 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67]
wire [2:0] _GEN_50 = _T_173 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67]
wire [2:0] _GEN_67 = _T_134 ? _T_149 : _GEN_50; // @[Conditional.scala 39:67]
wire [2:0] _GEN_82 = _T_99 ? _T_104 : _GEN_67; // @[Conditional.scala 39:67]
wire [2:0] _GEN_68 = _T_134 ? _T_153 : _GEN_50; // @[Conditional.scala 39:67]
wire [2:0] _GEN_82 = _T_99 ? _T_104 : _GEN_68; // @[Conditional.scala 39:67]
wire [2:0] buf_nxtstate = _T_47 ? _T_51 : _GEN_82; // @[Conditional.scala 40:58]
wire [2:0] _T_1 = buf_state_en ? buf_nxtstate : buf_state; // @[axi4_to_ahb.scala 69:16]
reg wrbuf_tag; // @[Reg.scala 27:20]
@ -232,16 +232,16 @@ module axi4_to_ahb(
wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 205:21]
reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20]
reg [63:0] wrbuf_data; // @[el2_lib.scala 514:16]
wire _T_152 = buf_state_en & _T_135; // @[axi4_to_ahb.scala 281:39]
wire _T_156 = buf_state_en & _T_135; // @[axi4_to_ahb.scala 281:39]
wire _T_359 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 330:55]
wire _T_360 = buf_state_en & _T_359; // @[axi4_to_ahb.scala 330:39]
wire _GEN_14 = _T_279 ? _T_360 : _T_442; // @[Conditional.scala 39:67]
wire _GEN_33 = _T_186 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67]
wire _GEN_49 = _T_184 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67]
wire _GEN_52 = _T_173 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67]
wire _GEN_72 = _T_134 ? _T_152 : _GEN_52; // @[Conditional.scala 39:67]
wire _GEN_93 = _T_99 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67]
wire slave_valid_pre = _T_47 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58]
wire _GEN_73 = _T_134 ? _T_156 : _GEN_52; // @[Conditional.scala 39:67]
wire _GEN_94 = _T_99 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67]
wire slave_valid_pre = _T_47 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58]
wire _T_23 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 210:32]
wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 158:21 axi4_to_ahb.scala 465:12]
reg slvbuf_write; // @[Reg.scala 27:20]
@ -276,18 +276,18 @@ module axi4_to_ahb(
wire [2:0] _T_93 = buf_write_in ? _T_91 : master_addr[2:0]; // @[axi4_to_ahb.scala 255:30]
wire _T_94 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 257:51]
wire _T_124 = master_ready & master_valid; // @[axi4_to_ahb.scala 268:33]
wire _T_156 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 283:64]
wire _T_157 = _T_124 & _T_156; // @[axi4_to_ahb.scala 283:48]
wire _T_158 = _T_157 & buf_state_en; // @[axi4_to_ahb.scala 283:79]
wire _T_160 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 283:64]
wire _T_161 = _T_124 & _T_160; // @[axi4_to_ahb.scala 283:48]
wire _T_162 = _T_161 & buf_state_en; // @[axi4_to_ahb.scala 283:79]
wire _T_350 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 328:33]
wire _T_352 = _T_350 & _T_53; // @[axi4_to_ahb.scala 328:48]
wire _GEN_12 = _T_279 & _T_352; // @[Conditional.scala 39:67]
wire _GEN_32 = _T_186 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67]
wire _GEN_48 = _T_184 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67]
wire _GEN_65 = _T_173 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67]
wire _GEN_74 = _T_134 ? _T_158 : _GEN_65; // @[Conditional.scala 39:67]
wire _GEN_87 = _T_99 ? _T_124 : _GEN_74; // @[Conditional.scala 39:67]
wire bypass_en = _T_47 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58]
wire _GEN_75 = _T_134 ? _T_162 : _GEN_65; // @[Conditional.scala 39:67]
wire _GEN_88 = _T_99 ? _T_124 : _GEN_75; // @[Conditional.scala 39:67]
wire bypass_en = _T_47 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58]
wire [1:0] _T_97 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_98 = _T_97 & 2'h2; // @[axi4_to_ahb.scala 258:45]
wire _T_110 = ~master_valid; // @[axi4_to_ahb.scala 264:34]
@ -298,11 +298,11 @@ module axi4_to_ahb(
wire _T_130 = _T_129 | bypass_en; // @[axi4_to_ahb.scala 270:58]
wire [1:0] _T_132 = _T_130 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_133 = 2'h2 & _T_132; // @[axi4_to_ahb.scala 270:32]
wire _T_163 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 285:59]
wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 285:74]
wire _T_165 = ~_T_164; // @[axi4_to_ahb.scala 285:43]
wire [1:0] _T_167 = _T_165 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_168 = 2'h2 & _T_167; // @[axi4_to_ahb.scala 285:32]
wire _T_167 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 285:59]
wire _T_168 = _T_167 & buf_state_en; // @[axi4_to_ahb.scala 285:74]
wire _T_169 = ~_T_168; // @[axi4_to_ahb.scala 285:43]
wire [1:0] _T_171 = _T_169 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_172 = 2'h2 & _T_171; // @[axi4_to_ahb.scala 285:32]
wire [1:0] _T_182 = _T_129 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_183 = 2'h2 & _T_182; // @[axi4_to_ahb.scala 295:37]
reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20]
@ -345,8 +345,8 @@ module axi4_to_ahb(
wire _GEN_24 = _T_186 ? _T_273 : _GEN_11; // @[Conditional.scala 39:67]
wire _GEN_43 = _T_184 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67]
wire _GEN_61 = _T_173 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67]
wire _GEN_73 = _T_134 ? _T_111 : _GEN_61; // @[Conditional.scala 39:67]
wire _GEN_84 = _T_99 ? _T_111 : _GEN_73; // @[Conditional.scala 39:67]
wire _GEN_74 = _T_134 ? _T_111 : _GEN_61; // @[Conditional.scala 39:67]
wire _GEN_84 = _T_99 ? _T_111 : _GEN_74; // @[Conditional.scala 39:67]
wire cmd_done = _T_47 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58]
wire _T_274 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 315:43]
wire _T_275 = ~_T_274; // @[axi4_to_ahb.scala 315:32]
@ -365,9 +365,9 @@ module axi4_to_ahb(
wire _GEN_30 = _T_186 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67]
wire _GEN_47 = _T_184 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67]
wire _GEN_64 = _T_173 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67]
wire _GEN_81 = _T_134 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67]
wire _GEN_97 = _T_99 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67]
wire buf_wr_en = _T_47 ? 1'h0 : _GEN_97; // @[Conditional.scala 40:58]
wire _GEN_67 = _T_134 ? _T_150 : _GEN_64; // @[Conditional.scala 39:67]
wire _GEN_87 = _T_99 ? master_ready : _GEN_67; // @[Conditional.scala 39:67]
wire buf_wr_en = _T_47 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58]
wire _GEN_10 = _T_279 & buf_wr_en; // @[Conditional.scala 39:67]
wire [1:0] _GEN_13 = _T_279 ? _T_358 : 2'h0; // @[Conditional.scala 39:67]
wire _GEN_16 = _T_279 & _T_365; // @[Conditional.scala 39:67]
@ -390,23 +390,23 @@ module axi4_to_ahb(
wire _GEN_56 = _T_173 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67]
wire _GEN_58 = _T_173 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67]
wire _GEN_60 = _T_173 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67]
wire _GEN_69 = _T_134 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67]
wire _GEN_71 = _T_134 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67]
wire [2:0] _GEN_75 = _T_134 ? _T_128 : _GEN_54; // @[Conditional.scala 39:67]
wire [1:0] _GEN_76 = _T_134 ? _T_168 : _GEN_55; // @[Conditional.scala 39:67]
wire _GEN_77 = _T_134 ? _T_146 : _GEN_53; // @[Conditional.scala 39:67]
wire _GEN_79 = _T_134 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67]
wire _GEN_85 = _T_99 ? buf_state_en : _GEN_77; // @[Conditional.scala 39:67]
wire [2:0] _GEN_88 = _T_99 ? _T_128 : _GEN_75; // @[Conditional.scala 39:67]
wire [1:0] _GEN_89 = _T_99 ? _T_133 : _GEN_76; // @[Conditional.scala 39:67]
wire _GEN_90 = _T_99 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67]
wire _GEN_92 = _T_99 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67]
wire _GEN_95 = _T_99 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67]
wire buf_data_wr_en = _T_47 ? _T_54 : _GEN_90; // @[Conditional.scala 40:58]
wire buf_cmd_byte_ptr_en = _T_47 ? buf_state_en : _GEN_95; // @[Conditional.scala 40:58]
wire [2:0] buf_cmd_byte_ptr = _T_47 ? _T_93 : _GEN_88; // @[Conditional.scala 40:58]
wire _GEN_70 = _T_134 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67]
wire _GEN_72 = _T_134 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67]
wire [2:0] _GEN_76 = _T_134 ? _T_128 : _GEN_54; // @[Conditional.scala 39:67]
wire [1:0] _GEN_77 = _T_134 ? _T_172 : _GEN_55; // @[Conditional.scala 39:67]
wire _GEN_78 = _T_134 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67]
wire _GEN_80 = _T_134 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67]
wire _GEN_85 = _T_99 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67]
wire [2:0] _GEN_89 = _T_99 ? _T_128 : _GEN_76; // @[Conditional.scala 39:67]
wire [1:0] _GEN_90 = _T_99 ? _T_133 : _GEN_77; // @[Conditional.scala 39:67]
wire _GEN_91 = _T_99 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67]
wire _GEN_93 = _T_99 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67]
wire _GEN_96 = _T_99 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67]
wire buf_data_wr_en = _T_47 ? _T_54 : _GEN_91; // @[Conditional.scala 40:58]
wire buf_cmd_byte_ptr_en = _T_47 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58]
wire [2:0] buf_cmd_byte_ptr = _T_47 ? _T_93 : _GEN_89; // @[Conditional.scala 40:58]
wire slvbuf_wr_en = _T_47 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58]
wire slvbuf_error_en = _T_47 ? 1'h0 : _GEN_92; // @[Conditional.scala 40:58]
wire slvbuf_error_en = _T_47 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58]
wire _T_534 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 353:24]
wire _T_535 = _T_101 | _T_534; // @[axi4_to_ahb.scala 352:51]
wire _T_537 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 353:57]
@ -453,7 +453,7 @@ module axi4_to_ahb(
wire last_addr_en = _T_611 & io_ahb_hwrite; // @[axi4_to_ahb.scala 371:68]
wire wrbuf_en = _T_42 & master_ready; // @[axi4_to_ahb.scala 373:47]
wire wrbuf_data_en = _T_43 & master_ready; // @[axi4_to_ahb.scala 374:50]
wire wrbuf_cmd_sent = _T_143 & _T_49; // @[axi4_to_ahb.scala 375:49]
wire wrbuf_cmd_sent = _T_147 & _T_49; // @[axi4_to_ahb.scala 375:49]
wire _T_621 = ~wrbuf_en; // @[axi4_to_ahb.scala 376:33]
wire wrbuf_rst = wrbuf_cmd_sent & _T_621; // @[axi4_to_ahb.scala 376:31]
wire _T_623 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 378:35]
@ -549,7 +549,7 @@ module axi4_to_ahb(
assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 361:20]
assign io_ahb_hprot = {{2'd0}, _T_588}; // @[axi4_to_ahb.scala 362:16]
assign io_ahb_hsize = bypass_en ? _T_579 : _T_584; // @[axi4_to_ahb.scala 358:16]
assign io_ahb_htrans = _T_47 ? _T_98 : _GEN_89; // @[axi4_to_ahb.scala 227:17 axi4_to_ahb.scala 258:21 axi4_to_ahb.scala 270:21 axi4_to_ahb.scala 285:21 axi4_to_ahb.scala 295:21 axi4_to_ahb.scala 315:21 axi4_to_ahb.scala 329:21]
assign io_ahb_htrans = _T_47 ? _T_98 : _GEN_90; // @[axi4_to_ahb.scala 227:17 axi4_to_ahb.scala 258:21 axi4_to_ahb.scala 270:21 axi4_to_ahb.scala 285:21 axi4_to_ahb.scala 295:21 axi4_to_ahb.scala 315:21 axi4_to_ahb.scala 329:21]
assign io_ahb_hwrite = bypass_en ? _T_49 : buf_write; // @[axi4_to_ahb.scala 363:17]
assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 364:17]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]

8
src/main/scala/lib/axi4_to_ahb.scala
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@ -248,7 +248,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
buf_write_in := (master_opc(2, 1) === "b01".U)
buf_nxtstate := Mux(buf_write_in.asBool(), cmd_wr, cmd_rd)
buf_state_en := master_valid & 1.U
// buf_wr_en := buf_state_en
buf_wr_en := buf_state_en
buf_data_wr_en := buf_state_en & (buf_nxtstate === cmd_wr)
buf_cmd_byte_ptr_en := buf_state_en
// ---------------------FROM FUNCTION CHECK LATER
@ -264,7 +264,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
cmd_done := buf_state_en & !master_valid
slvbuf_wr_en := buf_state_en
master_ready := (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q) & (Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd) === stream_rd) ////////////TBD////////
// buf_wr_en := master_ready
buf_wr_en := master_ready
bypass_en := master_ready & master_valid
buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0))
io.ahb_htrans := "b10".U & (Fill(2, (!buf_state_en | bypass_en)))
@ -272,7 +272,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
is(stream_rd) {
master_ready := (ahb_hready_q & !ahb_hresp_q) & !(master_valid & master_opc(2, 1) === "b01".U)
// buf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // update the fifo if we are streaming the read commands
buf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // update the fifo if we are streaming the read commands
buf_nxtstate := Mux(ahb_hresp_q.asBool(), stream_err_rd, Mux((master_valid & master_ready & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd)) // assuming that the master accpets the slave response right away.
buf_state_en := (ahb_hready_q | ahb_hresp_q)
buf_data_wr_en := buf_state_en
@ -283,7 +283,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
bypass_en := master_ready & master_valid & (buf_nxtstate === stream_rd) & buf_state_en
buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0))
io.ahb_htrans := "b10".U & Fill(2, (!((buf_nxtstate =/= stream_rd) & buf_state_en)))
slvbuf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // shifting the contents from the buf to slv_buf for streaming cases
slvbuf_wr_en := buf_wr_en// shifting the contents from the buf to slv_buf for streaming cases
}
is(stream_err_rd) {

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target/scala-2.12/classes/lib/axi4_to_ahb.class
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