Delete rvjtag_tap.scala
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laraibkhan-lm
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@ -1,122 +0,0 @@
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package dmi
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import chisel3._
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import chisel3.util._
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import include._
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import lib._
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class rvjtag_tap extends Module with el2_lib with RequireAsyncReset {
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val io = IO(new Bundle{
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val trst = Input(AsyncReset())
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val tck = Input(Clock())
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val tms = Input(Bool())
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val tdi = Input(Bool())
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val dmi_reset = Output(Bool())
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val dmi_hard_reset = Output(Bool())
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val rd_status = Input(UInt(2.W))
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val dmi_stat = Input(UInt(2.W))
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val idle = Input(UInt(3.W))
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val version = Input(UInt(4.W))
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val jtag_id = Input(UInt(31.W))
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val rd_data = Input(UInt(32.W))
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val tdo = Output(Bool())
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val tdoEnable = Output(Bool())
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val wr_en = Output(Bool())
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val rd_en = Output(Bool())
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val wr_data = Output(UInt(32.W))
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val wr_addr = Output(UInt(AWIDTH.W))
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})
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val AWIDTH = 7
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val USER_DR_LENGTH = AWIDTH + 34
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val nsr = WireInit(0.U(USER_DR_LENGTH.W))
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val sr = withClockAndReset (io.tck,io.trst) {RegNext(nsr,0.U)}
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val dr = WireInit(0.U(USER_DR_LENGTH.W))
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///////////////////////////////////////////////////////
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// Tap controller
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///////////////////////////////////////////////////////
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val test_logic_reset_state :: run_test_idle_state :: select_dr_scan_state :: capture_dr_state :: shift_dr_state :: exit1_dr_state :: pause_dr_state :: exit2_dr_state :: update_dr_state :: select_ir_scan_state :: capture_ir_state :: shift_ir_state :: exit1_ir_state :: pause_ir_state :: exit2_ir_state :: update_ir_state :: Nil = Enum(16)
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val nstate = WireInit(test_logic_reset_state)
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val state = withClockAndReset(io.tck,io.trst) {RegNext(nstate,test_logic_reset_state)}
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val ir = WireInit(0.U(5.W))
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val jtag_reset = WireInit(Bool(),false.B)
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val shift_dr = WireInit(UInt(1.W),init = 0.U)
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val pause_dr = WireInit(UInt(1.W),init = 0.U)
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val update_dr = WireInit(Bool(),false.B)
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val capture_dr = WireInit(UInt(1.W),init = 0.U)
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val shift_ir = WireInit(UInt(1.W),init = 0.U)
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val pause_ir = WireInit(UInt(1.W),init = 0.U)
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val update_ir = WireInit(Bool(),false.B)
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val capture_ir = WireInit(UInt(1.W),init = 0.U)
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val dr_en = WireInit(UInt(2.W),init = 0.U)
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val devid_sel = WireInit(Bool(),false.B)
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val abits = AWIDTH.U(6.W)
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switch (state) {
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is(test_logic_reset_state) {nstate := Mux(io.tms, test_logic_reset_state, run_test_idle_state)
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jtag_reset := 1.U }
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is(run_test_idle_state) {nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state) }
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is(select_dr_scan_state) {nstate := Mux(io.tms,select_ir_scan_state,capture_dr_state) }
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is(capture_dr_state) {nstate := Mux(io.tms,exit1_dr_state,shift_dr_state)
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capture_dr := 1.U }
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is(shift_dr_state) {nstate := Mux(io.tms,exit1_dr_state,shift_dr_state)
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shift_dr := 1.U }
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is(exit1_dr_state) {nstate := Mux(io.tms,update_dr_state,pause_dr_state) }
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is(pause_dr_state) {nstate := Mux(io.tms,exit2_dr_state,pause_dr_state)
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pause_dr := 1.U }
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is(exit2_dr_state) {nstate := Mux(io.tms,update_dr_state,shift_dr_state) }
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is(update_dr_state) {nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state)
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update_dr := 1.U }
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is(select_ir_scan_state) {nstate := Mux(io.tms,test_logic_reset_state,capture_ir_state) }
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is(capture_ir_state) {nstate := Mux(io.tms,exit1_ir_state,shift_ir_state)
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capture_ir := 1.U }
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is(shift_ir_state) {nstate := Mux(io.tms,exit1_ir_state,shift_ir_state)
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shift_ir := 1.U }
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is(exit1_ir_state) {nstate := Mux(io.tms,update_ir_state,pause_ir_state) }
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is(pause_ir_state) {nstate := Mux(io.tms,exit2_ir_state,pause_ir_state)
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pause_ir := 1.U }
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is(exit2_ir_state) {nstate := Mux(io.tms,update_ir_state,shift_ir_state) }
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is(update_ir_state) {nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state)
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update_ir := 1.U }
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}
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io.tdoEnable := shift_dr | shift_ir
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///////////////////////////////////////////////////////
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// IR register
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//////////////////////////////////////////////////////
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ir := withClockAndReset(io.tck,io.trst) {RegNext(Mux(jtag_reset,1.U,Mux(update_ir,Mux((sr(4,0)===0.U).asBool,"h1f".U,sr(4,0)),0.U)),1.U)}
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devid_sel := ir==="b00001".U(5.W)
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dr_en := Cat(ir===17.U,ir===16.U)
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///////////////////////////////////////////////////////
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// Shift register
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///////////////////////////////////////////////////////
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when(shift_dr===1.U){
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when(dr_en(1)===true.B){nsr :=Cat(io.tdi, sr(USER_DR_LENGTH-1,1))}
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.elsewhen(dr_en(0)===1.U || devid_sel===true.B){nsr := Cat(Fill(USER_DR_LENGTH-32,0.U) , io.tdi, sr(31,1))}
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.otherwise{nsr := Cat(Fill(USER_DR_LENGTH-1,0.U),io.tdi)} // bypass
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}
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.elsewhen(capture_dr ===1.U){
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when(dr_en(0)){nsr := Cat(Fill(USER_DR_LENGTH-15,0.U) ,io.idle, io.dmi_stat,abits,io.version)}
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.elsewhen(dr_en(1)){nsr := Cat(Fill(AWIDTH,0.U),io.rd_data,io.rd_status)}
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.elsewhen(devid_sel){nsr := Cat(Fill(USER_DR_LENGTH-32,0.U),io.jtag_id,1.U)}
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}
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.elsewhen(shift_ir===1.U){nsr := Cat(Fill(USER_DR_LENGTH-5,0.U),io.tdi,sr(4,1))}
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.elsewhen(capture_ir===1.U){nsr := Cat(Fill(USER_DR_LENGTH-1,0.U),1.U)}
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// TDO retiming
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withClock(io.tck) {io.tdo:=RegNext(sr(0),0.U)}
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// DMI CS register
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withClockAndReset (io.tck,io.trst) {io.dmi_hard_reset := RegNext(Mux(update_dr & dr_en(0).asBool(),sr(17),0.U),0.U)}
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withClockAndReset (io.tck,io.trst) {io.dmi_reset := RegNext(Mux(update_dr & dr_en(0).asBool(),sr(16),0.U),0.U)}
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// DR register
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withClockAndReset (io.tck,io.trst) {dr := RegNext(Mux(update_dr & dr_en(1).asBool(),sr,Cat(dr(USER_DR_LENGTH-1,2),0.U(2.W))),0.U)}
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io.rd_en := dr(0)
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io.wr_en := dr(1)
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io.wr_data := dr(33,2)
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io.wr_addr := dr(40,34)
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}
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object tapmain extends App{
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println("Generate Verilog")
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println((new chisel3.stage.ChiselStage).emitVerilog(new rvjtag_tap()))
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}
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