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IFC bits rectified

This commit is contained in:
waleed-lm 2020-10-01 11:41:24 +05:00
parent ceaa73e344
commit e7810dad72
16 changed files with 485 additions and 435 deletions
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47
EL2_IC_DATA.anno.json
View File

@ -1,7 +1,7 @@
[ [
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_DATA|EL2_IC_DATA>io_test", "sink":"~EL2_IC_DATA|EL2_IC_DATA>io_test_port_1_1",
"sources":[ "sources":[
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_wr_en", "~EL2_IC_DATA|EL2_IC_DATA>io_ic_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way", "~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way",
@ -14,6 +14,51 @@
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_en" "~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_en"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_DATA|EL2_IC_DATA>io_test_port_0_0",
"sources":[
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way",
"~EL2_IC_DATA|EL2_IC_DATA>io_clk_override",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rw_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_tag_array",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_DATA|EL2_IC_DATA>io_test_port_0_1",
"sources":[
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way",
"~EL2_IC_DATA|EL2_IC_DATA>io_clk_override",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rw_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_tag_array",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_DATA|EL2_IC_DATA>io_test_port_1_0",
"sources":[
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way",
"~EL2_IC_DATA|EL2_IC_DATA>io_clk_override",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_wr_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rw_addr",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_tag_array",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_en",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_en"
]
},
{ {
"class":"firrtl.EmitCircuitAnnotation", "class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter" "emitter":"firrtl.VerilogEmitter"

171
EL2_IC_DATA.fir
View File

@ -3,7 +3,7 @@ circuit EL2_IC_DATA :
module EL2_IC_DATA : module EL2_IC_DATA :
input clock : Clock input clock : Clock
input reset : UInt<1> input reset : UInt<1>
output io : {flip clk_override : UInt<1>, flip ic_rw_addr : UInt<12>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, flip ic_debug_wr_data : UInt<71>, ic_debug_rd_data : UInt<71>, ic_parerr : UInt<2>, ic_eccerr : UInt<2>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_rd_hit : UInt<2>, flip scan_mode : UInt<1>, flip test_in : UInt<71>, test : UInt} output io : {flip clk_override : UInt<1>, flip ic_rw_addr : UInt<12>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, flip ic_debug_wr_data : UInt<71>, ic_debug_rd_data : UInt<71>, ic_parerr : UInt<2>, ic_eccerr : UInt<2>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_rd_hit : UInt<2>, flip scan_mode : UInt<1>, flip test_in : UInt<71>, test : UInt, test_port : UInt<71>[2][2]}
io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 194:17] io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 194:17]
io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 195:23] io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 195:23]
@ -181,85 +181,94 @@ circuit EL2_IC_DATA :
node _T_133 = bits(ic_rw_addr_ff, 4, 2) @[el2_ifu_ic_mem.scala 238:43] node _T_133 = bits(ic_rw_addr_ff, 4, 2) @[el2_ifu_ic_mem.scala 238:43]
node _T_134 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_134 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node ic_cacheline_wrap_ff = eq(_T_133, _T_134) @[el2_ifu_ic_mem.scala 238:84] node ic_cacheline_wrap_ff = eq(_T_133, _T_134) @[el2_ifu_ic_mem.scala 238:84]
wire wb_out : UInt<71>[2][2] @[el2_ifu_ic_mem.scala 242:20]
cmem data_mem : UInt<71>[2][2][512] @[el2_ifu_ic_mem.scala 243:21] cmem data_mem : UInt<71>[2][2][512] @[el2_ifu_ic_mem.scala 243:21]
node _T_135 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 245:73] wb_out[0][0] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 245:18]
node _T_136 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 246:83] node _T_135 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 246:73]
node _T_137 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 247:26] node _T_136 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 247:83]
node _T_138 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 247:52] node _T_137 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 248:26]
node _T_139 = and(_T_137, _T_138) @[el2_ifu_ic_mem.scala 247:30] node _T_138 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 248:52]
node _T_140 = bits(_T_139, 0, 0) @[el2_ifu_ic_mem.scala 247:57] node _T_139 = and(_T_137, _T_138) @[el2_ifu_ic_mem.scala 248:30]
when _T_140 : @[el2_ifu_ic_mem.scala 247:64] node _T_140 = bits(_T_139, 0, 0) @[el2_ifu_ic_mem.scala 248:57]
infer mport _T_141 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 248:15] when _T_140 : @[el2_ifu_ic_mem.scala 248:64]
_T_141[0][0] <= io.test_in @[el2_ifu_ic_mem.scala 248:44] infer mport _T_141 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 249:15]
skip @[el2_ifu_ic_mem.scala 247:64] _T_141[0][0] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
else : @[el2_ifu_ic_mem.scala 249:69] skip @[el2_ifu_ic_mem.scala 248:64]
node _T_142 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 249:33] else : @[el2_ifu_ic_mem.scala 250:69]
node _T_143 = eq(_T_142, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 249:17] node _T_142 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 250:33]
node _T_144 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 249:57] node _T_143 = eq(_T_142, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
node _T_145 = and(_T_143, _T_144) @[el2_ifu_ic_mem.scala 249:36] node _T_144 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 250:57]
node _T_146 = bits(_T_145, 0, 0) @[el2_ifu_ic_mem.scala 249:62] node _T_145 = and(_T_143, _T_144) @[el2_ifu_ic_mem.scala 250:36]
when _T_146 : @[el2_ifu_ic_mem.scala 249:69] node _T_146 = bits(_T_145, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
infer mport _T_147 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 250:26] when _T_146 : @[el2_ifu_ic_mem.scala 250:69]
io.test <= _T_147[0][0] @[el2_ifu_ic_mem.scala 250:15] infer mport _T_147 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 251:31]
skip @[el2_ifu_ic_mem.scala 249:69] wb_out[0][0] <= _T_147[0][0] @[el2_ifu_ic_mem.scala 251:20]
node _T_148 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 245:73] skip @[el2_ifu_ic_mem.scala 250:69]
node _T_149 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 246:83] wb_out[0][1] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 245:18]
node _T_150 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 247:26] node _T_148 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 246:73]
node _T_151 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 247:52] node _T_149 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 247:83]
node _T_152 = and(_T_150, _T_151) @[el2_ifu_ic_mem.scala 247:30] node _T_150 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 248:26]
node _T_153 = bits(_T_152, 0, 0) @[el2_ifu_ic_mem.scala 247:57] node _T_151 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 248:52]
when _T_153 : @[el2_ifu_ic_mem.scala 247:64] node _T_152 = and(_T_150, _T_151) @[el2_ifu_ic_mem.scala 248:30]
infer mport _T_154 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 248:15] node _T_153 = bits(_T_152, 0, 0) @[el2_ifu_ic_mem.scala 248:57]
_T_154[1][0] <= io.test_in @[el2_ifu_ic_mem.scala 248:44] when _T_153 : @[el2_ifu_ic_mem.scala 248:64]
skip @[el2_ifu_ic_mem.scala 247:64] infer mport _T_154 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 249:15]
else : @[el2_ifu_ic_mem.scala 249:69] _T_154[1][0] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
node _T_155 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 249:33] skip @[el2_ifu_ic_mem.scala 248:64]
node _T_156 = eq(_T_155, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 249:17] else : @[el2_ifu_ic_mem.scala 250:69]
node _T_157 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 249:57] node _T_155 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 250:33]
node _T_158 = and(_T_156, _T_157) @[el2_ifu_ic_mem.scala 249:36] node _T_156 = eq(_T_155, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
node _T_159 = bits(_T_158, 0, 0) @[el2_ifu_ic_mem.scala 249:62] node _T_157 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 250:57]
when _T_159 : @[el2_ifu_ic_mem.scala 249:69] node _T_158 = and(_T_156, _T_157) @[el2_ifu_ic_mem.scala 250:36]
infer mport _T_160 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 250:26] node _T_159 = bits(_T_158, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
io.test <= _T_160[1][0] @[el2_ifu_ic_mem.scala 250:15] when _T_159 : @[el2_ifu_ic_mem.scala 250:69]
skip @[el2_ifu_ic_mem.scala 249:69] infer mport _T_160 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 251:31]
node _T_161 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 245:73] wb_out[0][1] <= _T_160[1][0] @[el2_ifu_ic_mem.scala 251:20]
node _T_162 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 246:83] skip @[el2_ifu_ic_mem.scala 250:69]
node _T_163 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 247:26] wb_out[1][0] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 245:18]
node _T_164 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 247:52] node _T_161 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 246:73]
node _T_165 = and(_T_163, _T_164) @[el2_ifu_ic_mem.scala 247:30] node _T_162 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 247:83]
node _T_166 = bits(_T_165, 0, 0) @[el2_ifu_ic_mem.scala 247:57] node _T_163 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 248:26]
when _T_166 : @[el2_ifu_ic_mem.scala 247:64] node _T_164 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 248:52]
infer mport _T_167 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 248:15] node _T_165 = and(_T_163, _T_164) @[el2_ifu_ic_mem.scala 248:30]
_T_167[0][1] <= io.test_in @[el2_ifu_ic_mem.scala 248:44] node _T_166 = bits(_T_165, 0, 0) @[el2_ifu_ic_mem.scala 248:57]
skip @[el2_ifu_ic_mem.scala 247:64] when _T_166 : @[el2_ifu_ic_mem.scala 248:64]
else : @[el2_ifu_ic_mem.scala 249:69] infer mport _T_167 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 249:15]
node _T_168 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 249:33] _T_167[0][1] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
node _T_169 = eq(_T_168, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 249:17] skip @[el2_ifu_ic_mem.scala 248:64]
node _T_170 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 249:57] else : @[el2_ifu_ic_mem.scala 250:69]
node _T_171 = and(_T_169, _T_170) @[el2_ifu_ic_mem.scala 249:36] node _T_168 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 250:33]
node _T_172 = bits(_T_171, 0, 0) @[el2_ifu_ic_mem.scala 249:62] node _T_169 = eq(_T_168, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
when _T_172 : @[el2_ifu_ic_mem.scala 249:69] node _T_170 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 250:57]
infer mport _T_173 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 250:26] node _T_171 = and(_T_169, _T_170) @[el2_ifu_ic_mem.scala 250:36]
io.test <= _T_173[0][1] @[el2_ifu_ic_mem.scala 250:15] node _T_172 = bits(_T_171, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
skip @[el2_ifu_ic_mem.scala 249:69] when _T_172 : @[el2_ifu_ic_mem.scala 250:69]
node _T_174 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 245:73] infer mport _T_173 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 251:31]
node _T_175 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 246:83] wb_out[1][0] <= _T_173[0][1] @[el2_ifu_ic_mem.scala 251:20]
node _T_176 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 247:26] skip @[el2_ifu_ic_mem.scala 250:69]
node _T_177 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 247:52] wb_out[1][1] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 245:18]
node _T_178 = and(_T_176, _T_177) @[el2_ifu_ic_mem.scala 247:30] node _T_174 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 246:73]
node _T_179 = bits(_T_178, 0, 0) @[el2_ifu_ic_mem.scala 247:57] node _T_175 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 247:83]
when _T_179 : @[el2_ifu_ic_mem.scala 247:64] node _T_176 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 248:26]
infer mport _T_180 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 248:15] node _T_177 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 248:52]
_T_180[1][1] <= io.test_in @[el2_ifu_ic_mem.scala 248:44] node _T_178 = and(_T_176, _T_177) @[el2_ifu_ic_mem.scala 248:30]
skip @[el2_ifu_ic_mem.scala 247:64] node _T_179 = bits(_T_178, 0, 0) @[el2_ifu_ic_mem.scala 248:57]
else : @[el2_ifu_ic_mem.scala 249:69] when _T_179 : @[el2_ifu_ic_mem.scala 248:64]
node _T_181 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 249:33] infer mport _T_180 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 249:15]
node _T_182 = eq(_T_181, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 249:17] _T_180[1][1] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
node _T_183 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 249:57] skip @[el2_ifu_ic_mem.scala 248:64]
node _T_184 = and(_T_182, _T_183) @[el2_ifu_ic_mem.scala 249:36] else : @[el2_ifu_ic_mem.scala 250:69]
node _T_185 = bits(_T_184, 0, 0) @[el2_ifu_ic_mem.scala 249:62] node _T_181 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 250:33]
when _T_185 : @[el2_ifu_ic_mem.scala 249:69] node _T_182 = eq(_T_181, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
infer mport _T_186 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 250:26] node _T_183 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 250:57]
io.test <= _T_186[1][1] @[el2_ifu_ic_mem.scala 250:15] node _T_184 = and(_T_182, _T_183) @[el2_ifu_ic_mem.scala 250:36]
skip @[el2_ifu_ic_mem.scala 249:69] node _T_185 = bits(_T_184, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
when _T_185 : @[el2_ifu_ic_mem.scala 250:69]
infer mport _T_186 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 251:31]
wb_out[1][1] <= _T_186[1][1] @[el2_ifu_ic_mem.scala 251:20]
skip @[el2_ifu_ic_mem.scala 250:69]
io.test_port[0][0] <= wb_out[0][0] @[el2_ifu_ic_mem.scala 254:16]
io.test_port[0][1] <= wb_out[0][1] @[el2_ifu_ic_mem.scala 254:16]
io.test_port[1][0] <= wb_out[1][0] @[el2_ifu_ic_mem.scala 254:16]
io.test_port[1][1] <= wb_out[1][1] @[el2_ifu_ic_mem.scala 254:16]

47
EL2_IC_DATA.v
View File

@ -22,7 +22,11 @@ module EL2_IC_DATA(
input [1:0] io_ic_rd_hit, input [1:0] io_ic_rd_hit,
input io_scan_mode, input io_scan_mode,
input [70:0] io_test_in, input [70:0] io_test_in,
output [70:0] io_test output io_test,
output [70:0] io_test_port_0_0,
output [70:0] io_test_port_0_1,
output [70:0] io_test_port_1_0,
output [70:0] io_test_port_1_1
); );
`ifdef RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_MEM_INIT
reg [95:0] _RAND_0; reg [95:0] _RAND_0;
@ -174,25 +178,22 @@ module EL2_IC_DATA(
wire ic_rw_addr_wrap = _T_121 & _T_114; // @[el2_ifu_ic_mem.scala 224:108] wire ic_rw_addr_wrap = _T_121 & _T_114; // @[el2_ifu_ic_mem.scala 224:108]
wire _T_124 = ~ic_rw_addr_wrap; // @[el2_ifu_ic_mem.scala 226:40] wire _T_124 = ~ic_rw_addr_wrap; // @[el2_ifu_ic_mem.scala 226:40]
wire [8:0] _T_129 = {ic_rw_addr_q[11:5],ic_rw_addr_q_inc[4:3]}; // @[Cat.scala 29:58] wire [8:0] _T_129 = {ic_rw_addr_q[11:5],ic_rw_addr_q_inc[4:3]}; // @[Cat.scala 29:58]
wire _T_139 = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 247:30] wire _T_139 = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 248:30]
wire _T_143 = ~ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 249:17] wire _T_143 = ~ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 250:17]
wire _T_145 = _T_143 & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 249:36] wire _T_145 = _T_143 & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 250:36]
wire [70:0] _GEN_3 = _T_145 ? data_mem_0_0__T_147_data : 71'h0; // @[el2_ifu_ic_mem.scala 249:69] wire [70:0] _GEN_3 = _T_145 ? data_mem_0_0__T_147_data : 71'h0; // @[el2_ifu_ic_mem.scala 250:69]
wire [70:0] _GEN_13 = _T_139 ? 71'h0 : _GEN_3; // @[el2_ifu_ic_mem.scala 247:64] wire _T_152 = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 248:30]
wire _T_152 = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 247:30] wire _T_156 = ~ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 250:17]
wire _T_156 = ~ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 249:17] wire _T_158 = _T_156 & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 250:36]
wire _T_158 = _T_156 & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 249:36] wire [70:0] _GEN_17 = _T_158 ? data_mem_1_0__T_160_data : 71'h0; // @[el2_ifu_ic_mem.scala 250:69]
wire [70:0] _GEN_17 = _T_158 ? data_mem_1_0__T_160_data : _GEN_13; // @[el2_ifu_ic_mem.scala 249:69] wire _T_165 = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 248:30]
wire [70:0] _GEN_27 = _T_152 ? _GEN_13 : _GEN_17; // @[el2_ifu_ic_mem.scala 247:64] wire _T_169 = ~ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 250:17]
wire _T_165 = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 247:30] wire _T_171 = _T_169 & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 250:36]
wire _T_169 = ~ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 249:17] wire [70:0] _GEN_31 = _T_171 ? data_mem_0_1__T_173_data : 71'h0; // @[el2_ifu_ic_mem.scala 250:69]
wire _T_171 = _T_169 & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 249:36] wire _T_178 = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 248:30]
wire [70:0] _GEN_31 = _T_171 ? data_mem_0_1__T_173_data : _GEN_27; // @[el2_ifu_ic_mem.scala 249:69] wire _T_182 = ~ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 250:17]
wire [70:0] _GEN_41 = _T_165 ? _GEN_27 : _GEN_31; // @[el2_ifu_ic_mem.scala 247:64] wire _T_184 = _T_182 & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 250:36]
wire _T_178 = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 247:30] wire [70:0] _GEN_45 = _T_184 ? data_mem_1_1__T_186_data : 71'h0; // @[el2_ifu_ic_mem.scala 250:69]
wire _T_182 = ~ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 249:17]
wire _T_184 = _T_182 & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 249:36]
wire [70:0] _GEN_45 = _T_184 ? data_mem_1_1__T_186_data : _GEN_41; // @[el2_ifu_ic_mem.scala 249:69]
assign data_mem_0_0__T_147_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129; assign data_mem_0_0__T_147_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
assign data_mem_0_0__T_147_data = data_mem_0_0[data_mem_0_0__T_147_addr]; // @[el2_ifu_ic_mem.scala 243:21] assign data_mem_0_0__T_147_data = data_mem_0_0[data_mem_0_0__T_147_addr]; // @[el2_ifu_ic_mem.scala 243:21]
assign data_mem_0_0__T_160_addr = ic_rw_addr_q[11:3]; assign data_mem_0_0__T_160_addr = ic_rw_addr_q[11:3];
@ -293,7 +294,11 @@ module EL2_IC_DATA(
assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 195:23] assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 195:23]
assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 196:16] assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 196:16]
assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 197:16] assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 197:16]
assign io_test = _T_178 ? _GEN_41 : _GEN_45; // @[el2_ifu_ic_mem.scala 198:11 el2_ifu_ic_mem.scala 250:15 el2_ifu_ic_mem.scala 250:15 el2_ifu_ic_mem.scala 250:15 el2_ifu_ic_mem.scala 250:15] assign io_test = 1'h0; // @[el2_ifu_ic_mem.scala 198:11]
assign io_test_port_0_0 = _T_139 ? 71'h0 : _GEN_3; // @[el2_ifu_ic_mem.scala 254:16]
assign io_test_port_0_1 = _T_152 ? 71'h0 : _GEN_17; // @[el2_ifu_ic_mem.scala 254:16]
assign io_test_port_1_0 = _T_165 ? 71'h0 : _GEN_31; // @[el2_ifu_ic_mem.scala 254:16]
assign io_test_port_1_1 = _T_178 ? 71'h0 : _GEN_45; // @[el2_ifu_ic_mem.scala 254:16]
`ifdef RANDOMIZE_GARBAGE_ASSIGN `ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE `define RANDOMIZE
`endif `endif

7
el2_ifu_ifc_ctl.anno.json
View File

@ -103,13 +103,6 @@
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f" "~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_req_f"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_test",
"sources":[
"~el2_ifu_ifc_ctl|el2_ifu_ifc_ctl>io_ifc_fetch_addr_f"
]
},
{ {
"class":"firrtl.EmitCircuitAnnotation", "class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter" "emitter":"firrtl.VerilogEmitter"

375
el2_ifu_ifc_ctl.fir
View File

@ -3,7 +3,7 @@ circuit el2_ifu_ifc_ctl :
module el2_ifu_ifc_ctl : module el2_ifu_ifc_ctl :
input clock : Clock input clock : Clock
input reset : AsyncReset input reset : AsyncReset
output io : {flip free_clk : Clock, flip active_clk : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>, test : UInt<1>} output io : {flip free_clk : Clock, flip active_clk : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>}
wire fetch_addr_bf : UInt<31> wire fetch_addr_bf : UInt<31>
fetch_addr_bf <= UInt<1>("h00") fetch_addr_bf <= UInt<1>("h00")
@ -47,31 +47,31 @@ circuit el2_ifu_ifc_ctl :
state <= UInt<1>("h00") state <= UInt<1>("h00")
wire dma_iccm_stall_any_f : UInt<1> wire dma_iccm_stall_any_f : UInt<1>
dma_iccm_stall_any_f <= UInt<1>("h00") dma_iccm_stall_any_f <= UInt<1>("h00")
node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 63:36] node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 62:36]
reg _T : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 64:58] reg _T : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 63:58]
_T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctl.scala 64:58] _T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctl.scala 63:58]
dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctl.scala 64:24] dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctl.scala 63:24]
reg _T_1 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 66:44] reg _T_1 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 65:44]
_T_1 <= miss_f @[el2_ifu_ifc_ctl.scala 66:44] _T_1 <= miss_f @[el2_ifu_ifc_ctl.scala 65:44]
miss_a <= _T_1 @[el2_ifu_ifc_ctl.scala 66:10] miss_a <= _T_1 @[el2_ifu_ifc_ctl.scala 65:10]
node _T_2 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 68:26] node _T_2 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:26]
node _T_3 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 68:49] node _T_3 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:49]
node _T_4 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 68:71] node _T_4 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:71]
node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctl.scala 68:69] node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctl.scala 67:69]
node sel_last_addr_bf = and(_T_2, _T_5) @[el2_ifu_ifc_ctl.scala 68:46] node sel_last_addr_bf = and(_T_2, _T_5) @[el2_ifu_ifc_ctl.scala 67:46]
node _T_6 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 69:26] node _T_6 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 68:26]
node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 69:46] node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 68:46]
node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctl.scala 69:67] node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctl.scala 68:67]
node sel_btb_addr_bf = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 69:92] node sel_btb_addr_bf = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 68:92]
node _T_9 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 70:26] node _T_9 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 69:26]
node _T_10 = and(_T_9, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 70:46] node _T_10 = and(_T_9, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 69:46]
node _T_11 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 70:69] node _T_11 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 69:69]
node _T_12 = and(_T_10, _T_11) @[el2_ifu_ifc_ctl.scala 70:67] node _T_12 = and(_T_10, _T_11) @[el2_ifu_ifc_ctl.scala 69:67]
node sel_next_addr_bf = and(_T_12, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 70:92] node sel_next_addr_bf = and(_T_12, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 69:92]
node _T_13 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctl.scala 73:56] node _T_13 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctl.scala 72:56]
node _T_14 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 74:22] node _T_14 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 73:22]
node _T_15 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 75:21] node _T_15 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 74:21]
node _T_16 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 76:22] node _T_16 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 75:22]
node _T_17 = mux(_T_13, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72] node _T_17 = mux(_T_13, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_18 = mux(_T_14, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_18 = mux(_T_14, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_19 = mux(_T_15, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_19 = mux(_T_15, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
@ -81,122 +81,121 @@ circuit el2_ifu_ifc_ctl :
node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72] node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72]
wire _T_24 : UInt<31> @[Mux.scala 27:72] wire _T_24 : UInt<31> @[Mux.scala 27:72]
_T_24 <= _T_23 @[Mux.scala 27:72] _T_24 <= _T_23 @[Mux.scala 27:72]
io.ifc_fetch_addr_bf <= _T_24 @[el2_ifu_ifc_ctl.scala 73:24] io.ifc_fetch_addr_bf <= _T_24 @[el2_ifu_ifc_ctl.scala 72:24]
node _T_25 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctl.scala 78:42] node _T_25 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctl.scala 77:42]
node _T_26 = add(_T_25, UInt<1>("h01")) @[el2_ifu_ifc_ctl.scala 78:48] node _T_26 = add(_T_25, UInt<1>("h01")) @[el2_ifu_ifc_ctl.scala 77:48]
node address_upper = tail(_T_26, 1) @[el2_ifu_ifc_ctl.scala 78:48] node address_upper = tail(_T_26, 1) @[el2_ifu_ifc_ctl.scala 77:48]
node _T_27 = bits(address_upper, 4, 4) @[el2_ifu_ifc_ctl.scala 79:39] node _T_27 = bits(address_upper, 4, 4) @[el2_ifu_ifc_ctl.scala 78:39]
node _T_28 = bits(io.ifc_fetch_addr_f, 5, 5) @[el2_ifu_ifc_ctl.scala 79:84] node _T_28 = bits(io.ifc_fetch_addr_f, 5, 5) @[el2_ifu_ifc_ctl.scala 78:84]
node _T_29 = xor(_T_27, _T_28) @[el2_ifu_ifc_ctl.scala 79:63] node _T_29 = xor(_T_27, _T_28) @[el2_ifu_ifc_ctl.scala 78:63]
node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 79:24] node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 78:24]
node _T_31 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctl.scala 79:130] node _T_31 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctl.scala 78:130]
node _T_32 = and(_T_30, _T_31) @[el2_ifu_ifc_ctl.scala 79:109] node _T_32 = and(_T_30, _T_31) @[el2_ifu_ifc_ctl.scala 78:109]
fetch_addr_next_0 <= _T_32 @[el2_ifu_ifc_ctl.scala 79:21] fetch_addr_next_0 <= _T_32 @[el2_ifu_ifc_ctl.scala 78:21]
io.test <= fetch_addr_next_0 @[el2_ifu_ifc_ctl.scala 80:11]
node _T_33 = cat(address_upper, fetch_addr_next_0) @[Cat.scala 29:58] node _T_33 = cat(address_upper, fetch_addr_next_0) @[Cat.scala 29:58]
fetch_addr_next <= _T_33 @[el2_ifu_ifc_ctl.scala 81:19] fetch_addr_next <= _T_33 @[el2_ifu_ifc_ctl.scala 80:19]
node _T_34 = not(idle) @[el2_ifu_ifc_ctl.scala 83:30] node _T_34 = not(idle) @[el2_ifu_ifc_ctl.scala 82:30]
io.ifc_fetch_req_bf_raw <= _T_34 @[el2_ifu_ifc_ctl.scala 83:27] io.ifc_fetch_req_bf_raw <= _T_34 @[el2_ifu_ifc_ctl.scala 82:27]
node _T_35 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 85:91] node _T_35 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 84:91]
node _T_36 = eq(_T_35, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:70] node _T_36 = eq(_T_35, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:70]
node _T_37 = and(fb_full_f_ns, _T_36) @[el2_ifu_ifc_ctl.scala 85:68] node _T_37 = and(fb_full_f_ns, _T_36) @[el2_ifu_ifc_ctl.scala 84:68]
node _T_38 = eq(_T_37, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:53] node _T_38 = eq(_T_37, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:53]
node _T_39 = and(io.ifc_fetch_req_bf_raw, _T_38) @[el2_ifu_ifc_ctl.scala 85:51] node _T_39 = and(io.ifc_fetch_req_bf_raw, _T_38) @[el2_ifu_ifc_ctl.scala 84:51]
node _T_40 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 86:5] node _T_40 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:5]
node _T_41 = and(_T_39, _T_40) @[el2_ifu_ifc_ctl.scala 85:114] node _T_41 = and(_T_39, _T_40) @[el2_ifu_ifc_ctl.scala 84:114]
node _T_42 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 86:18] node _T_42 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:18]
node _T_43 = and(_T_41, _T_42) @[el2_ifu_ifc_ctl.scala 86:16] node _T_43 = and(_T_41, _T_42) @[el2_ifu_ifc_ctl.scala 85:16]
node _T_44 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 86:39] node _T_44 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:39]
node _T_45 = and(_T_43, _T_44) @[el2_ifu_ifc_ctl.scala 86:37] node _T_45 = and(_T_43, _T_44) @[el2_ifu_ifc_ctl.scala 85:37]
io.ifc_fetch_req_bf <= _T_45 @[el2_ifu_ifc_ctl.scala 85:23] io.ifc_fetch_req_bf <= _T_45 @[el2_ifu_ifc_ctl.scala 84:23]
node _T_46 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 88:37] node _T_46 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 87:37]
fetch_bf_en <= _T_46 @[el2_ifu_ifc_ctl.scala 88:15] fetch_bf_en <= _T_46 @[el2_ifu_ifc_ctl.scala 87:15]
node _T_47 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 90:34] node _T_47 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:34]
node _T_48 = and(io.ifc_fetch_req_f, _T_47) @[el2_ifu_ifc_ctl.scala 90:32] node _T_48 = and(io.ifc_fetch_req_f, _T_47) @[el2_ifu_ifc_ctl.scala 89:32]
node _T_49 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 90:49] node _T_49 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:49]
node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctl.scala 90:47] node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctl.scala 89:47]
miss_f <= _T_50 @[el2_ifu_ifc_ctl.scala 90:10] miss_f <= _T_50 @[el2_ifu_ifc_ctl.scala 89:10]
node _T_51 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 92:39] node _T_51 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 91:39]
node _T_52 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 92:63] node _T_52 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:63]
node _T_53 = and(_T_51, _T_52) @[el2_ifu_ifc_ctl.scala 92:61] node _T_53 = and(_T_51, _T_52) @[el2_ifu_ifc_ctl.scala 91:61]
node _T_54 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 92:76] node _T_54 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:76]
node _T_55 = and(_T_53, _T_54) @[el2_ifu_ifc_ctl.scala 92:74] node _T_55 = and(_T_53, _T_54) @[el2_ifu_ifc_ctl.scala 91:74]
node _T_56 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 92:86] node _T_56 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:86]
node _T_57 = and(_T_55, _T_56) @[el2_ifu_ifc_ctl.scala 92:84] node _T_57 = and(_T_55, _T_56) @[el2_ifu_ifc_ctl.scala 91:84]
mb_empty_mod <= _T_57 @[el2_ifu_ifc_ctl.scala 92:16] mb_empty_mod <= _T_57 @[el2_ifu_ifc_ctl.scala 91:16]
node _T_58 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctl.scala 94:35] node _T_58 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctl.scala 93:35]
goto_idle <= _T_58 @[el2_ifu_ifc_ctl.scala 94:13] goto_idle <= _T_58 @[el2_ifu_ifc_ctl.scala 93:13]
node _T_59 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 96:38] node _T_59 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 95:38]
node _T_60 = and(io.exu_flush_final, _T_59) @[el2_ifu_ifc_ctl.scala 96:36] node _T_60 = and(io.exu_flush_final, _T_59) @[el2_ifu_ifc_ctl.scala 95:36]
node _T_61 = and(_T_60, idle) @[el2_ifu_ifc_ctl.scala 96:67] node _T_61 = and(_T_60, idle) @[el2_ifu_ifc_ctl.scala 95:67]
leave_idle <= _T_61 @[el2_ifu_ifc_ctl.scala 96:14] leave_idle <= _T_61 @[el2_ifu_ifc_ctl.scala 95:14]
node _T_62 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 98:29] node _T_62 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 97:29]
node _T_63 = eq(_T_62, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:23] node _T_63 = eq(_T_62, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:23]
node _T_64 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 98:40] node _T_64 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 97:40]
node _T_65 = and(_T_63, _T_64) @[el2_ifu_ifc_ctl.scala 98:33] node _T_65 = and(_T_63, _T_64) @[el2_ifu_ifc_ctl.scala 97:33]
node _T_66 = and(_T_65, miss_f) @[el2_ifu_ifc_ctl.scala 98:44] node _T_66 = and(_T_65, miss_f) @[el2_ifu_ifc_ctl.scala 97:44]
node _T_67 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:55] node _T_67 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:55]
node _T_68 = and(_T_66, _T_67) @[el2_ifu_ifc_ctl.scala 98:53] node _T_68 = and(_T_66, _T_67) @[el2_ifu_ifc_ctl.scala 97:53]
node _T_69 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 99:11] node _T_69 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 98:11]
node _T_70 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 99:17] node _T_70 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:17]
node _T_71 = and(_T_69, _T_70) @[el2_ifu_ifc_ctl.scala 99:15] node _T_71 = and(_T_69, _T_70) @[el2_ifu_ifc_ctl.scala 98:15]
node _T_72 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 99:33] node _T_72 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:33]
node _T_73 = and(_T_71, _T_72) @[el2_ifu_ifc_ctl.scala 99:31] node _T_73 = and(_T_71, _T_72) @[el2_ifu_ifc_ctl.scala 98:31]
node next_state_1 = or(_T_68, _T_73) @[el2_ifu_ifc_ctl.scala 98:67] node next_state_1 = or(_T_68, _T_73) @[el2_ifu_ifc_ctl.scala 97:67]
node _T_74 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 101:23] node _T_74 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:23]
node _T_75 = and(_T_74, leave_idle) @[el2_ifu_ifc_ctl.scala 101:34] node _T_75 = and(_T_74, leave_idle) @[el2_ifu_ifc_ctl.scala 100:34]
node _T_76 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 101:56] node _T_76 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 100:56]
node _T_77 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 101:62] node _T_77 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:62]
node _T_78 = and(_T_76, _T_77) @[el2_ifu_ifc_ctl.scala 101:60] node _T_78 = and(_T_76, _T_77) @[el2_ifu_ifc_ctl.scala 100:60]
node next_state_0 = or(_T_75, _T_78) @[el2_ifu_ifc_ctl.scala 101:48] node next_state_0 = or(_T_75, _T_78) @[el2_ifu_ifc_ctl.scala 100:48]
node _T_79 = cat(next_state_1, next_state_0) @[Cat.scala 29:58] node _T_79 = cat(next_state_1, next_state_0) @[Cat.scala 29:58]
reg _T_80 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 103:19] reg _T_80 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 102:19]
_T_80 <= _T_79 @[el2_ifu_ifc_ctl.scala 103:19] _T_80 <= _T_79 @[el2_ifu_ifc_ctl.scala 102:19]
state <= _T_80 @[el2_ifu_ifc_ctl.scala 103:9] state <= _T_80 @[el2_ifu_ifc_ctl.scala 102:9]
flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctl.scala 105:12] flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctl.scala 104:12]
node _T_81 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 107:38] node _T_81 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:38]
node _T_82 = and(io.ifu_fb_consume1, _T_81) @[el2_ifu_ifc_ctl.scala 107:36] node _T_82 = and(io.ifu_fb_consume1, _T_81) @[el2_ifu_ifc_ctl.scala 106:36]
node _T_83 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 107:61] node _T_83 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:61]
node _T_84 = or(_T_83, miss_f) @[el2_ifu_ifc_ctl.scala 107:81] node _T_84 = or(_T_83, miss_f) @[el2_ifu_ifc_ctl.scala 106:81]
node _T_85 = and(_T_82, _T_84) @[el2_ifu_ifc_ctl.scala 107:58] node _T_85 = and(_T_82, _T_84) @[el2_ifu_ifc_ctl.scala 106:58]
node _T_86 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 108:25] node _T_86 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 107:25]
node _T_87 = or(_T_85, _T_86) @[el2_ifu_ifc_ctl.scala 107:92] node _T_87 = or(_T_85, _T_86) @[el2_ifu_ifc_ctl.scala 106:92]
fb_right <= _T_87 @[el2_ifu_ifc_ctl.scala 107:12] fb_right <= _T_87 @[el2_ifu_ifc_ctl.scala 106:12]
node _T_88 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 110:39] node _T_88 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 109:39]
node _T_89 = or(_T_88, miss_f) @[el2_ifu_ifc_ctl.scala 110:59] node _T_89 = or(_T_88, miss_f) @[el2_ifu_ifc_ctl.scala 109:59]
node _T_90 = and(io.ifu_fb_consume2, _T_89) @[el2_ifu_ifc_ctl.scala 110:36] node _T_90 = and(io.ifu_fb_consume2, _T_89) @[el2_ifu_ifc_ctl.scala 109:36]
fb_right2 <= _T_90 @[el2_ifu_ifc_ctl.scala 110:13] fb_right2 <= _T_90 @[el2_ifu_ifc_ctl.scala 109:13]
node _T_91 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctl.scala 111:56] node _T_91 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctl.scala 110:56]
node _T_92 = eq(_T_91, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 111:35] node _T_92 = eq(_T_91, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:35]
node _T_93 = and(io.ifc_fetch_req_f, _T_92) @[el2_ifu_ifc_ctl.scala 111:33] node _T_93 = and(io.ifc_fetch_req_f, _T_92) @[el2_ifu_ifc_ctl.scala 110:33]
node _T_94 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 111:80] node _T_94 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:80]
node _T_95 = and(_T_93, _T_94) @[el2_ifu_ifc_ctl.scala 111:78] node _T_95 = and(_T_93, _T_94) @[el2_ifu_ifc_ctl.scala 110:78]
fb_left <= _T_95 @[el2_ifu_ifc_ctl.scala 111:11] fb_left <= _T_95 @[el2_ifu_ifc_ctl.scala 110:11]
node _T_96 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctl.scala 113:37] node _T_96 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctl.scala 112:37]
node _T_97 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 114:6] node _T_97 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 113:6]
node _T_98 = and(_T_97, fb_right) @[el2_ifu_ifc_ctl.scala 114:16] node _T_98 = and(_T_97, fb_right) @[el2_ifu_ifc_ctl.scala 113:16]
node _T_99 = bits(_T_98, 0, 0) @[el2_ifu_ifc_ctl.scala 114:28] node _T_99 = bits(_T_98, 0, 0) @[el2_ifu_ifc_ctl.scala 113:28]
node _T_100 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctl.scala 114:62] node _T_100 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctl.scala 113:62]
node _T_101 = cat(UInt<1>("h00"), _T_100) @[Cat.scala 29:58] node _T_101 = cat(UInt<1>("h00"), _T_100) @[Cat.scala 29:58]
node _T_102 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 115:6] node _T_102 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 114:6]
node _T_103 = and(_T_102, fb_right2) @[el2_ifu_ifc_ctl.scala 115:16] node _T_103 = and(_T_102, fb_right2) @[el2_ifu_ifc_ctl.scala 114:16]
node _T_104 = bits(_T_103, 0, 0) @[el2_ifu_ifc_ctl.scala 115:29] node _T_104 = bits(_T_103, 0, 0) @[el2_ifu_ifc_ctl.scala 114:29]
node _T_105 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctl.scala 115:63] node _T_105 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctl.scala 114:63]
node _T_106 = cat(UInt<2>("h00"), _T_105) @[Cat.scala 29:58] node _T_106 = cat(UInt<2>("h00"), _T_105) @[Cat.scala 29:58]
node _T_107 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:6] node _T_107 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 115:6]
node _T_108 = and(_T_107, fb_left) @[el2_ifu_ifc_ctl.scala 116:16] node _T_108 = and(_T_107, fb_left) @[el2_ifu_ifc_ctl.scala 115:16]
node _T_109 = bits(_T_108, 0, 0) @[el2_ifu_ifc_ctl.scala 116:27] node _T_109 = bits(_T_108, 0, 0) @[el2_ifu_ifc_ctl.scala 115:27]
node _T_110 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctl.scala 116:51] node _T_110 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctl.scala 115:51]
node _T_111 = cat(_T_110, UInt<1>("h00")) @[Cat.scala 29:58] node _T_111 = cat(_T_110, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_112 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 117:6] node _T_112 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:6]
node _T_113 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 117:18] node _T_113 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:18]
node _T_114 = and(_T_112, _T_113) @[el2_ifu_ifc_ctl.scala 117:16] node _T_114 = and(_T_112, _T_113) @[el2_ifu_ifc_ctl.scala 116:16]
node _T_115 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 117:30] node _T_115 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:30]
node _T_116 = and(_T_114, _T_115) @[el2_ifu_ifc_ctl.scala 117:28] node _T_116 = and(_T_114, _T_115) @[el2_ifu_ifc_ctl.scala 116:28]
node _T_117 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 117:43] node _T_117 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:43]
node _T_118 = and(_T_116, _T_117) @[el2_ifu_ifc_ctl.scala 117:41] node _T_118 = and(_T_116, _T_117) @[el2_ifu_ifc_ctl.scala 116:41]
node _T_119 = bits(_T_118, 0, 0) @[el2_ifu_ifc_ctl.scala 117:53] node _T_119 = bits(_T_118, 0, 0) @[el2_ifu_ifc_ctl.scala 116:53]
node _T_120 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctl.scala 117:73] node _T_120 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctl.scala 116:73]
node _T_121 = mux(_T_96, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_121 = mux(_T_96, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_122 = mux(_T_99, _T_101, UInt<1>("h00")) @[Mux.scala 27:72] node _T_122 = mux(_T_99, _T_101, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_123 = mux(_T_104, _T_106, UInt<1>("h00")) @[Mux.scala 27:72] node _T_123 = mux(_T_104, _T_106, UInt<1>("h00")) @[Mux.scala 27:72]
@ -208,65 +207,65 @@ circuit el2_ifu_ifc_ctl :
node _T_129 = or(_T_128, _T_125) @[Mux.scala 27:72] node _T_129 = or(_T_128, _T_125) @[Mux.scala 27:72]
wire _T_130 : UInt<4> @[Mux.scala 27:72] wire _T_130 : UInt<4> @[Mux.scala 27:72]
_T_130 <= _T_129 @[Mux.scala 27:72] _T_130 <= _T_129 @[Mux.scala 27:72]
fb_write_ns <= _T_130 @[el2_ifu_ifc_ctl.scala 113:15] fb_write_ns <= _T_130 @[el2_ifu_ifc_ctl.scala 112:15]
node _T_131 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 120:38] node _T_131 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 119:38]
reg _T_132 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 120:26] reg _T_132 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 119:26]
_T_132 <= _T_131 @[el2_ifu_ifc_ctl.scala 120:26] _T_132 <= _T_131 @[el2_ifu_ifc_ctl.scala 119:26]
fb_full_f_ns <= _T_132 @[el2_ifu_ifc_ctl.scala 120:16] fb_full_f_ns <= _T_132 @[el2_ifu_ifc_ctl.scala 119:16]
node _T_133 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctl.scala 122:17] node _T_133 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctl.scala 121:17]
idle <= _T_133 @[el2_ifu_ifc_ctl.scala 122:8] idle <= _T_133 @[el2_ifu_ifc_ctl.scala 121:8]
node _T_134 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctl.scala 123:16] node _T_134 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctl.scala 122:16]
wfm <= _T_134 @[el2_ifu_ifc_ctl.scala 123:7] wfm <= _T_134 @[el2_ifu_ifc_ctl.scala 122:7]
node _T_135 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 125:30] node _T_135 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 124:30]
fb_full_f_ns <= _T_135 @[el2_ifu_ifc_ctl.scala 125:16] fb_full_f_ns <= _T_135 @[el2_ifu_ifc_ctl.scala 124:16]
reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 126:26] reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 125:26]
fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctl.scala 126:26] fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctl.scala 125:26]
reg _T_136 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 127:24] reg _T_136 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 126:24]
_T_136 <= fb_write_ns @[el2_ifu_ifc_ctl.scala 127:24] _T_136 <= fb_write_ns @[el2_ifu_ifc_ctl.scala 126:24]
fb_write_f <= _T_136 @[el2_ifu_ifc_ctl.scala 127:14] fb_write_f <= _T_136 @[el2_ifu_ifc_ctl.scala 126:14]
node _T_137 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 130:40] node _T_137 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 129:40]
node _T_138 = or(_T_137, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 130:61] node _T_138 = or(_T_137, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 129:61]
node _T_139 = eq(_T_138, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 130:19] node _T_139 = eq(_T_138, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 129:19]
node _T_140 = and(fb_full_f, _T_139) @[el2_ifu_ifc_ctl.scala 130:17] node _T_140 = and(fb_full_f, _T_139) @[el2_ifu_ifc_ctl.scala 129:17]
node _T_141 = or(_T_140, dma_stall) @[el2_ifu_ifc_ctl.scala 130:84] node _T_141 = or(_T_140, dma_stall) @[el2_ifu_ifc_ctl.scala 129:84]
node _T_142 = and(io.ifc_fetch_req_bf_raw, _T_141) @[el2_ifu_ifc_ctl.scala 129:60] node _T_142 = and(io.ifc_fetch_req_bf_raw, _T_141) @[el2_ifu_ifc_ctl.scala 128:60]
node _T_143 = or(wfm, _T_142) @[el2_ifu_ifc_ctl.scala 129:33] node _T_143 = or(wfm, _T_142) @[el2_ifu_ifc_ctl.scala 128:33]
io.ifu_pmu_fetch_stall <= _T_143 @[el2_ifu_ifc_ctl.scala 129:26] io.ifu_pmu_fetch_stall <= _T_143 @[el2_ifu_ifc_ctl.scala 128:26]
node _T_144 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] node _T_144 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_145 = bits(_T_144, 31, 28) @[el2_lib.scala 211:25] node _T_145 = bits(_T_144, 31, 28) @[el2_lib.scala 211:25]
node iccm_acc_in_region_bf = eq(_T_145, UInt<4>("h0e")) @[el2_lib.scala 211:47] node iccm_acc_in_region_bf = eq(_T_145, UInt<4>("h0e")) @[el2_lib.scala 211:47]
node _T_146 = bits(_T_144, 31, 16) @[el2_lib.scala 214:14] node _T_146 = bits(_T_144, 31, 16) @[el2_lib.scala 214:14]
node iccm_acc_in_range_bf = eq(_T_146, UInt<16>("h0ee00")) @[el2_lib.scala 214:29] node iccm_acc_in_range_bf = eq(_T_146, UInt<16>("h0ee00")) @[el2_lib.scala 214:29]
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctl.scala 135:25] io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctl.scala 134:25]
node _T_147 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 136:30] node _T_147 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:30]
node _T_148 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 137:39] node _T_148 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 136:39]
node _T_149 = eq(_T_148, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:18] node _T_149 = eq(_T_148, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 136:18]
node _T_150 = and(fb_full_f, _T_149) @[el2_ifu_ifc_ctl.scala 137:16] node _T_150 = and(fb_full_f, _T_149) @[el2_ifu_ifc_ctl.scala 136:16]
node _T_151 = or(_T_147, _T_150) @[el2_ifu_ifc_ctl.scala 136:53] node _T_151 = or(_T_147, _T_150) @[el2_ifu_ifc_ctl.scala 135:53]
node _T_152 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 138:13] node _T_152 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:13]
node _T_153 = and(wfm, _T_152) @[el2_ifu_ifc_ctl.scala 138:11] node _T_153 = and(wfm, _T_152) @[el2_ifu_ifc_ctl.scala 137:11]
node _T_154 = or(_T_151, _T_153) @[el2_ifu_ifc_ctl.scala 137:62] node _T_154 = or(_T_151, _T_153) @[el2_ifu_ifc_ctl.scala 136:62]
node _T_155 = or(_T_154, idle) @[el2_ifu_ifc_ctl.scala 138:35] node _T_155 = or(_T_154, idle) @[el2_ifu_ifc_ctl.scala 137:35]
node _T_156 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 138:46] node _T_156 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:46]
node _T_157 = and(_T_155, _T_156) @[el2_ifu_ifc_ctl.scala 138:44] node _T_157 = and(_T_155, _T_156) @[el2_ifu_ifc_ctl.scala 137:44]
node _T_158 = or(_T_157, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 138:67] node _T_158 = or(_T_157, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 137:67]
io.ifc_dma_access_ok <= _T_158 @[el2_ifu_ifc_ctl.scala 136:24] io.ifc_dma_access_ok <= _T_158 @[el2_ifu_ifc_ctl.scala 135:24]
node _T_159 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 140:33] node _T_159 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 139:33]
node _T_160 = and(_T_159, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctl.scala 140:55] node _T_160 = and(_T_159, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctl.scala 139:55]
io.ifc_region_acc_fault_bf <= _T_160 @[el2_ifu_ifc_ctl.scala 140:30] io.ifc_region_acc_fault_bf <= _T_160 @[el2_ifu_ifc_ctl.scala 139:30]
node _T_161 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctl.scala 141:78] node _T_161 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctl.scala 140:78]
node _T_162 = cat(_T_161, UInt<1>("h00")) @[Cat.scala 29:58] node _T_162 = cat(_T_161, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_163 = dshr(io.dec_tlu_mrac_ff, _T_162) @[el2_ifu_ifc_ctl.scala 141:53] node _T_163 = dshr(io.dec_tlu_mrac_ff, _T_162) @[el2_ifu_ifc_ctl.scala 140:53]
node _T_164 = bits(_T_163, 0, 0) @[el2_ifu_ifc_ctl.scala 141:53] node _T_164 = bits(_T_163, 0, 0) @[el2_ifu_ifc_ctl.scala 140:53]
node _T_165 = not(_T_164) @[el2_ifu_ifc_ctl.scala 141:34] node _T_165 = not(_T_164) @[el2_ifu_ifc_ctl.scala 140:34]
io.ifc_fetch_uncacheable_bf <= _T_165 @[el2_ifu_ifc_ctl.scala 141:31] io.ifc_fetch_uncacheable_bf <= _T_165 @[el2_ifu_ifc_ctl.scala 140:31]
reg _T_166 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 143:32] reg _T_166 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 142:32]
_T_166 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 143:32] _T_166 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 142:32]
io.ifc_fetch_req_f <= _T_166 @[el2_ifu_ifc_ctl.scala 143:22] io.ifc_fetch_req_f <= _T_166 @[el2_ifu_ifc_ctl.scala 142:22]
node _T_167 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 145:88] node _T_167 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 144:88]
reg _T_168 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_168 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_167 : @[Reg.scala 28:19] when _T_167 : @[Reg.scala 28:19]
_T_168 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23] _T_168 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
io.ifc_fetch_addr_f <= _T_168 @[el2_ifu_ifc_ctl.scala 145:23] io.ifc_fetch_addr_f <= _T_168 @[el2_ifu_ifc_ctl.scala 144:23]

212
el2_ifu_ifc_ctl.v
View File

@ -26,8 +26,7 @@ module el2_ifu_ifc_ctl(
output io_ifc_fetch_req_bf_raw, output io_ifc_fetch_req_bf_raw,
output io_ifc_iccm_access_bf, output io_ifc_iccm_access_bf,
output io_ifc_region_acc_fault_bf, output io_ifc_region_acc_fault_bf,
output io_ifc_dma_access_ok, output io_ifc_dma_access_ok
output io_test
); );
`ifdef RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0; reg [31:0] _RAND_0;
@ -38,135 +37,134 @@ module el2_ifu_ifc_ctl(
reg [31:0] _RAND_5; reg [31:0] _RAND_5;
reg [31:0] _RAND_6; reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE_REG_INIT
reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 64:58] reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 63:58]
wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 63:36] wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 62:36]
reg miss_a; // @[el2_ifu_ifc_ctl.scala 66:44] reg miss_a; // @[el2_ifu_ifc_ctl.scala 65:44]
wire _T_2 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 68:26] wire _T_2 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 67:26]
wire _T_3 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 68:49] wire _T_3 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 67:49]
wire _T_4 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 68:71] wire _T_4 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 67:71]
wire _T_5 = _T_3 | _T_4; // @[el2_ifu_ifc_ctl.scala 68:69] wire _T_5 = _T_3 | _T_4; // @[el2_ifu_ifc_ctl.scala 67:69]
wire sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctl.scala 68:46] wire sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctl.scala 67:46]
wire _T_7 = _T_2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 69:46] wire _T_7 = _T_2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 68:46]
wire _T_8 = _T_7 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 69:67] wire _T_8 = _T_7 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 68:67]
wire sel_btb_addr_bf = _T_8 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 69:92] wire sel_btb_addr_bf = _T_8 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 68:92]
wire _T_11 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 70:69] wire _T_11 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctl.scala 69:69]
wire _T_12 = _T_7 & _T_11; // @[el2_ifu_ifc_ctl.scala 70:67] wire _T_12 = _T_7 & _T_11; // @[el2_ifu_ifc_ctl.scala 69:67]
wire sel_next_addr_bf = _T_12 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 70:92] wire sel_next_addr_bf = _T_12 & io_ic_hit_f; // @[el2_ifu_ifc_ctl.scala 69:92]
wire [30:0] _T_17 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_17 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctl.scala 78:48] wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctl.scala 77:48]
wire _T_29 = address_upper[4] ^ io_ifc_fetch_addr_f[5]; // @[el2_ifu_ifc_ctl.scala 79:63] wire _T_29 = address_upper[4] ^ io_ifc_fetch_addr_f[5]; // @[el2_ifu_ifc_ctl.scala 78:63]
wire _T_30 = ~_T_29; // @[el2_ifu_ifc_ctl.scala 79:24] wire _T_30 = ~_T_29; // @[el2_ifu_ifc_ctl.scala 78:24]
wire fetch_addr_next_0 = _T_30 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctl.scala 79:109] wire fetch_addr_next_0 = _T_30 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctl.scala 78:109]
wire [30:0] fetch_addr_next = {address_upper,fetch_addr_next_0}; // @[Cat.scala 29:58] wire [30:0] fetch_addr_next = {address_upper,fetch_addr_next_0}; // @[Cat.scala 29:58]
wire [30:0] _T_20 = sel_next_addr_bf ? fetch_addr_next : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_20 = sel_next_addr_bf ? fetch_addr_next : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72] wire [30:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72]
wire [30:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72] wire [30:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72]
reg [1:0] state; // @[el2_ifu_ifc_ctl.scala 103:19] reg [1:0] state; // @[el2_ifu_ifc_ctl.scala 102:19]
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctl.scala 122:17] wire idle = state == 2'h0; // @[el2_ifu_ifc_ctl.scala 121:17]
wire _T_35 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctl.scala 85:91] wire _T_35 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctl.scala 84:91]
wire _T_36 = ~_T_35; // @[el2_ifu_ifc_ctl.scala 85:70] wire _T_36 = ~_T_35; // @[el2_ifu_ifc_ctl.scala 84:70]
wire [3:0] _T_121 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_121 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
wire _T_81 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 107:38] wire _T_81 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 106:38]
wire _T_82 = io_ifu_fb_consume1 & _T_81; // @[el2_ifu_ifc_ctl.scala 107:36] wire _T_82 = io_ifu_fb_consume1 & _T_81; // @[el2_ifu_ifc_ctl.scala 106:36]
wire _T_48 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctl.scala 90:32] wire _T_48 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctl.scala 89:32]
wire miss_f = _T_48 & _T_2; // @[el2_ifu_ifc_ctl.scala 90:47] wire miss_f = _T_48 & _T_2; // @[el2_ifu_ifc_ctl.scala 89:47]
wire _T_84 = _T_3 | miss_f; // @[el2_ifu_ifc_ctl.scala 107:81] wire _T_84 = _T_3 | miss_f; // @[el2_ifu_ifc_ctl.scala 106:81]
wire _T_85 = _T_82 & _T_84; // @[el2_ifu_ifc_ctl.scala 107:58] wire _T_85 = _T_82 & _T_84; // @[el2_ifu_ifc_ctl.scala 106:58]
wire _T_86 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 108:25] wire _T_86 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 107:25]
wire fb_right = _T_85 | _T_86; // @[el2_ifu_ifc_ctl.scala 107:92] wire fb_right = _T_85 | _T_86; // @[el2_ifu_ifc_ctl.scala 106:92]
wire _T_98 = _T_2 & fb_right; // @[el2_ifu_ifc_ctl.scala 114:16] wire _T_98 = _T_2 & fb_right; // @[el2_ifu_ifc_ctl.scala 113:16]
reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctl.scala 127:24] reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctl.scala 126:24]
wire [3:0] _T_101 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58] wire [3:0] _T_101 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
wire [3:0] _T_122 = _T_98 ? _T_101 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_122 = _T_98 ? _T_101 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_126 = _T_121 | _T_122; // @[Mux.scala 27:72] wire [3:0] _T_126 = _T_121 | _T_122; // @[Mux.scala 27:72]
wire fb_right2 = io_ifu_fb_consume2 & _T_84; // @[el2_ifu_ifc_ctl.scala 110:36] wire fb_right2 = io_ifu_fb_consume2 & _T_84; // @[el2_ifu_ifc_ctl.scala 109:36]
wire _T_103 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctl.scala 115:16] wire _T_103 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctl.scala 114:16]
wire [3:0] _T_106 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58] wire [3:0] _T_106 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
wire [3:0] _T_123 = _T_103 ? _T_106 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_123 = _T_103 ? _T_106 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_127 = _T_126 | _T_123; // @[Mux.scala 27:72] wire [3:0] _T_127 = _T_126 | _T_123; // @[Mux.scala 27:72]
wire _T_91 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 111:56] wire _T_91 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 110:56]
wire _T_92 = ~_T_91; // @[el2_ifu_ifc_ctl.scala 111:35] wire _T_92 = ~_T_91; // @[el2_ifu_ifc_ctl.scala 110:35]
wire _T_93 = io_ifc_fetch_req_f & _T_92; // @[el2_ifu_ifc_ctl.scala 111:33] wire _T_93 = io_ifc_fetch_req_f & _T_92; // @[el2_ifu_ifc_ctl.scala 110:33]
wire _T_94 = ~miss_f; // @[el2_ifu_ifc_ctl.scala 111:80] wire _T_94 = ~miss_f; // @[el2_ifu_ifc_ctl.scala 110:80]
wire fb_left = _T_93 & _T_94; // @[el2_ifu_ifc_ctl.scala 111:78] wire fb_left = _T_93 & _T_94; // @[el2_ifu_ifc_ctl.scala 110:78]
wire _T_108 = _T_2 & fb_left; // @[el2_ifu_ifc_ctl.scala 116:16] wire _T_108 = _T_2 & fb_left; // @[el2_ifu_ifc_ctl.scala 115:16]
wire [3:0] _T_111 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58] wire [3:0] _T_111 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
wire [3:0] _T_124 = _T_108 ? _T_111 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_124 = _T_108 ? _T_111 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_128 = _T_127 | _T_124; // @[Mux.scala 27:72] wire [3:0] _T_128 = _T_127 | _T_124; // @[Mux.scala 27:72]
wire _T_113 = ~fb_right; // @[el2_ifu_ifc_ctl.scala 117:18] wire _T_113 = ~fb_right; // @[el2_ifu_ifc_ctl.scala 116:18]
wire _T_114 = _T_2 & _T_113; // @[el2_ifu_ifc_ctl.scala 117:16] wire _T_114 = _T_2 & _T_113; // @[el2_ifu_ifc_ctl.scala 116:16]
wire _T_115 = ~fb_right2; // @[el2_ifu_ifc_ctl.scala 117:30] wire _T_115 = ~fb_right2; // @[el2_ifu_ifc_ctl.scala 116:30]
wire _T_116 = _T_114 & _T_115; // @[el2_ifu_ifc_ctl.scala 117:28] wire _T_116 = _T_114 & _T_115; // @[el2_ifu_ifc_ctl.scala 116:28]
wire _T_117 = ~fb_left; // @[el2_ifu_ifc_ctl.scala 117:43] wire _T_117 = ~fb_left; // @[el2_ifu_ifc_ctl.scala 116:43]
wire _T_118 = _T_116 & _T_117; // @[el2_ifu_ifc_ctl.scala 117:41] wire _T_118 = _T_116 & _T_117; // @[el2_ifu_ifc_ctl.scala 116:41]
wire [3:0] _T_125 = _T_118 ? fb_write_f : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_125 = _T_118 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
wire [3:0] fb_write_ns = _T_128 | _T_125; // @[Mux.scala 27:72] wire [3:0] fb_write_ns = _T_128 | _T_125; // @[Mux.scala 27:72]
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctl.scala 125:30] wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctl.scala 124:30]
wire _T_37 = fb_full_f_ns & _T_36; // @[el2_ifu_ifc_ctl.scala 85:68] wire _T_37 = fb_full_f_ns & _T_36; // @[el2_ifu_ifc_ctl.scala 84:68]
wire _T_38 = ~_T_37; // @[el2_ifu_ifc_ctl.scala 85:53] wire _T_38 = ~_T_37; // @[el2_ifu_ifc_ctl.scala 84:53]
wire _T_39 = io_ifc_fetch_req_bf_raw & _T_38; // @[el2_ifu_ifc_ctl.scala 85:51] wire _T_39 = io_ifc_fetch_req_bf_raw & _T_38; // @[el2_ifu_ifc_ctl.scala 84:51]
wire _T_40 = ~dma_stall; // @[el2_ifu_ifc_ctl.scala 86:5] wire _T_40 = ~dma_stall; // @[el2_ifu_ifc_ctl.scala 85:5]
wire _T_41 = _T_39 & _T_40; // @[el2_ifu_ifc_ctl.scala 85:114] wire _T_41 = _T_39 & _T_40; // @[el2_ifu_ifc_ctl.scala 84:114]
wire _T_42 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctl.scala 86:18] wire _T_42 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctl.scala 85:18]
wire _T_43 = _T_41 & _T_42; // @[el2_ifu_ifc_ctl.scala 86:16] wire _T_43 = _T_41 & _T_42; // @[el2_ifu_ifc_ctl.scala 85:16]
wire _T_44 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 86:39] wire _T_44 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 85:39]
wire fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 88:37] wire fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 87:37]
wire _T_51 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 92:39] wire _T_51 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 91:39]
wire _T_53 = _T_51 & _T_40; // @[el2_ifu_ifc_ctl.scala 92:61] wire _T_53 = _T_51 & _T_40; // @[el2_ifu_ifc_ctl.scala 91:61]
wire _T_55 = _T_53 & _T_94; // @[el2_ifu_ifc_ctl.scala 92:74] wire _T_55 = _T_53 & _T_94; // @[el2_ifu_ifc_ctl.scala 91:74]
wire _T_56 = ~miss_a; // @[el2_ifu_ifc_ctl.scala 92:86] wire _T_56 = ~miss_a; // @[el2_ifu_ifc_ctl.scala 91:86]
wire mb_empty_mod = _T_55 & _T_56; // @[el2_ifu_ifc_ctl.scala 92:84] wire mb_empty_mod = _T_55 & _T_56; // @[el2_ifu_ifc_ctl.scala 91:84]
wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 94:35] wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 93:35]
wire _T_60 = io_exu_flush_final & _T_44; // @[el2_ifu_ifc_ctl.scala 96:36] wire _T_60 = io_exu_flush_final & _T_44; // @[el2_ifu_ifc_ctl.scala 95:36]
wire leave_idle = _T_60 & idle; // @[el2_ifu_ifc_ctl.scala 96:67] wire leave_idle = _T_60 & idle; // @[el2_ifu_ifc_ctl.scala 95:67]
wire _T_63 = ~state[1]; // @[el2_ifu_ifc_ctl.scala 98:23] wire _T_63 = ~state[1]; // @[el2_ifu_ifc_ctl.scala 97:23]
wire _T_65 = _T_63 & state[0]; // @[el2_ifu_ifc_ctl.scala 98:33] wire _T_65 = _T_63 & state[0]; // @[el2_ifu_ifc_ctl.scala 97:33]
wire _T_66 = _T_65 & miss_f; // @[el2_ifu_ifc_ctl.scala 98:44] wire _T_66 = _T_65 & miss_f; // @[el2_ifu_ifc_ctl.scala 97:44]
wire _T_67 = ~goto_idle; // @[el2_ifu_ifc_ctl.scala 98:55] wire _T_67 = ~goto_idle; // @[el2_ifu_ifc_ctl.scala 97:55]
wire _T_68 = _T_66 & _T_67; // @[el2_ifu_ifc_ctl.scala 98:53] wire _T_68 = _T_66 & _T_67; // @[el2_ifu_ifc_ctl.scala 97:53]
wire _T_70 = ~mb_empty_mod; // @[el2_ifu_ifc_ctl.scala 99:17] wire _T_70 = ~mb_empty_mod; // @[el2_ifu_ifc_ctl.scala 98:17]
wire _T_71 = state[1] & _T_70; // @[el2_ifu_ifc_ctl.scala 99:15] wire _T_71 = state[1] & _T_70; // @[el2_ifu_ifc_ctl.scala 98:15]
wire _T_73 = _T_71 & _T_67; // @[el2_ifu_ifc_ctl.scala 99:31] wire _T_73 = _T_71 & _T_67; // @[el2_ifu_ifc_ctl.scala 98:31]
wire next_state_1 = _T_68 | _T_73; // @[el2_ifu_ifc_ctl.scala 98:67] wire next_state_1 = _T_68 | _T_73; // @[el2_ifu_ifc_ctl.scala 97:67]
wire _T_75 = _T_67 & leave_idle; // @[el2_ifu_ifc_ctl.scala 101:34] wire _T_75 = _T_67 & leave_idle; // @[el2_ifu_ifc_ctl.scala 100:34]
wire _T_78 = state[0] & _T_67; // @[el2_ifu_ifc_ctl.scala 101:60] wire _T_78 = state[0] & _T_67; // @[el2_ifu_ifc_ctl.scala 100:60]
wire next_state_0 = _T_75 | _T_78; // @[el2_ifu_ifc_ctl.scala 101:48] wire next_state_0 = _T_75 | _T_78; // @[el2_ifu_ifc_ctl.scala 100:48]
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctl.scala 123:16] wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctl.scala 122:16]
reg fb_full_f; // @[el2_ifu_ifc_ctl.scala 126:26] reg fb_full_f; // @[el2_ifu_ifc_ctl.scala 125:26]
wire _T_138 = _T_35 | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 130:61] wire _T_138 = _T_35 | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 129:61]
wire _T_139 = ~_T_138; // @[el2_ifu_ifc_ctl.scala 130:19] wire _T_139 = ~_T_138; // @[el2_ifu_ifc_ctl.scala 129:19]
wire _T_140 = fb_full_f & _T_139; // @[el2_ifu_ifc_ctl.scala 130:17] wire _T_140 = fb_full_f & _T_139; // @[el2_ifu_ifc_ctl.scala 129:17]
wire _T_141 = _T_140 | dma_stall; // @[el2_ifu_ifc_ctl.scala 130:84] wire _T_141 = _T_140 | dma_stall; // @[el2_ifu_ifc_ctl.scala 129:84]
wire _T_142 = io_ifc_fetch_req_bf_raw & _T_141; // @[el2_ifu_ifc_ctl.scala 129:60] wire _T_142 = io_ifc_fetch_req_bf_raw & _T_141; // @[el2_ifu_ifc_ctl.scala 128:60]
wire [31:0] _T_144 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58] wire [31:0] _T_144 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
wire iccm_acc_in_region_bf = _T_144[31:28] == 4'he; // @[el2_lib.scala 211:47] wire iccm_acc_in_region_bf = _T_144[31:28] == 4'he; // @[el2_lib.scala 211:47]
wire iccm_acc_in_range_bf = _T_144[31:16] == 16'hee00; // @[el2_lib.scala 214:29] wire iccm_acc_in_range_bf = _T_144[31:16] == 16'hee00; // @[el2_lib.scala 214:29]
wire _T_147 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 136:30] wire _T_147 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 135:30]
wire _T_150 = fb_full_f & _T_36; // @[el2_ifu_ifc_ctl.scala 137:16] wire _T_150 = fb_full_f & _T_36; // @[el2_ifu_ifc_ctl.scala 136:16]
wire _T_151 = _T_147 | _T_150; // @[el2_ifu_ifc_ctl.scala 136:53] wire _T_151 = _T_147 | _T_150; // @[el2_ifu_ifc_ctl.scala 135:53]
wire _T_152 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctl.scala 138:13] wire _T_152 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctl.scala 137:13]
wire _T_153 = wfm & _T_152; // @[el2_ifu_ifc_ctl.scala 138:11] wire _T_153 = wfm & _T_152; // @[el2_ifu_ifc_ctl.scala 137:11]
wire _T_154 = _T_151 | _T_153; // @[el2_ifu_ifc_ctl.scala 137:62] wire _T_154 = _T_151 | _T_153; // @[el2_ifu_ifc_ctl.scala 136:62]
wire _T_155 = _T_154 | idle; // @[el2_ifu_ifc_ctl.scala 138:35] wire _T_155 = _T_154 | idle; // @[el2_ifu_ifc_ctl.scala 137:35]
wire _T_157 = _T_155 & _T_2; // @[el2_ifu_ifc_ctl.scala 138:44] wire _T_157 = _T_155 & _T_2; // @[el2_ifu_ifc_ctl.scala 137:44]
wire _T_159 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctl.scala 140:33] wire _T_159 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctl.scala 139:33]
wire [4:0] _T_162 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58] wire [4:0] _T_162 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_163 = io_dec_tlu_mrac_ff >> _T_162; // @[el2_ifu_ifc_ctl.scala 141:53] wire [31:0] _T_163 = io_dec_tlu_mrac_ff >> _T_162; // @[el2_ifu_ifc_ctl.scala 140:53]
reg _T_166; // @[el2_ifu_ifc_ctl.scala 143:32] reg _T_166; // @[el2_ifu_ifc_ctl.scala 142:32]
reg [30:0] _T_168; // @[Reg.scala 27:20] reg [30:0] _T_168; // @[Reg.scala 27:20]
assign io_ifc_fetch_addr_f = _T_168; // @[el2_ifu_ifc_ctl.scala 145:23] assign io_ifc_fetch_addr_f = _T_168; // @[el2_ifu_ifc_ctl.scala 144:23]
assign io_ifc_fetch_addr_bf = _T_22 | _T_20; // @[el2_ifu_ifc_ctl.scala 73:24] assign io_ifc_fetch_addr_bf = _T_22 | _T_20; // @[el2_ifu_ifc_ctl.scala 72:24]
assign io_ifc_fetch_req_f = _T_166; // @[el2_ifu_ifc_ctl.scala 143:22] assign io_ifc_fetch_req_f = _T_166; // @[el2_ifu_ifc_ctl.scala 142:22]
assign io_ifu_pmu_fetch_stall = wfm | _T_142; // @[el2_ifu_ifc_ctl.scala 129:26] assign io_ifu_pmu_fetch_stall = wfm | _T_142; // @[el2_ifu_ifc_ctl.scala 128:26]
assign io_ifc_fetch_uncacheable_bf = ~_T_163[0]; // @[el2_ifu_ifc_ctl.scala 141:31] assign io_ifc_fetch_uncacheable_bf = ~_T_163[0]; // @[el2_ifu_ifc_ctl.scala 140:31]
assign io_ifc_fetch_req_bf = _T_43 & _T_44; // @[el2_ifu_ifc_ctl.scala 85:23] assign io_ifc_fetch_req_bf = _T_43 & _T_44; // @[el2_ifu_ifc_ctl.scala 84:23]
assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctl.scala 83:27] assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctl.scala 82:27]
assign io_ifc_iccm_access_bf = _T_144[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 135:25] assign io_ifc_iccm_access_bf = _T_144[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 134:25]
assign io_ifc_region_acc_fault_bf = _T_159 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 140:30] assign io_ifc_region_acc_fault_bf = _T_159 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 139:30]
assign io_ifc_dma_access_ok = _T_157 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 136:24] assign io_ifc_dma_access_ok = _T_157 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 135:24]
assign io_test = _T_30 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctl.scala 80:11]
`ifdef RANDOMIZE_GARBAGE_ASSIGN `ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE `define RANDOMIZE
`endif `endif

6
src/main/scala/ifu/el2_ifu_ic_mem.scala
View File

@ -188,7 +188,7 @@ class EL2_IC_DATA extends Module with el2_lib {
val scan_mode = Input(UInt(1.W)) val scan_mode = Input(UInt(1.W))
val test_in = Input(UInt(71.W)) val test_in = Input(UInt(71.W))
val test = Output(UInt()) val test = Output(UInt())
// val test_port = Output(Vec(ICACHE_BANKS_WAY, Vec(ICACHE_NUM_WAYS, UInt(71.W)))) val test_port = Output(Vec(ICACHE_BANKS_WAY, Vec(ICACHE_NUM_WAYS, UInt(71.W))))
}) })
io.ic_rd_data := 0.U io.ic_rd_data := 0.U
@ -242,14 +242,16 @@ class EL2_IC_DATA extends Module with el2_lib {
val wb_out = Wire(Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W)))) val wb_out = Wire(Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W))))
val data_mem = Mem(ICACHE_DATA_DEPTH, Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W)))) val data_mem = Mem(ICACHE_DATA_DEPTH, Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W))))
for(i<-0 until ICACHE_NUM_WAYS; k<-0 until ICACHE_BANKS_WAY){ for(i<-0 until ICACHE_NUM_WAYS; k<-0 until ICACHE_BANKS_WAY){
wb_out(i)(k) := 0.U
val WE = if(ICACHE_WAYPACK) ic_b_sb_wren(k).orR else ic_b_sb_wren(k)(i) val WE = if(ICACHE_WAYPACK) ic_b_sb_wren(k).orR else ic_b_sb_wren(k)(i)
val ME = if(ICACHE_WAYPACK) ic_bank_way_clken(k).orR else ic_bank_way_clken(k)(i) val ME = if(ICACHE_WAYPACK) ic_bank_way_clken(k).orR else ic_bank_way_clken(k)(i)
when((ic_b_sb_wren(k)(i) & ic_bank_way_clken(k)(i)).asBool){ when((ic_b_sb_wren(k)(i) & ic_bank_way_clken(k)(i)).asBool){
data_mem(ic_rw_addr_bank_q(k))(k)(i) := io.test_in data_mem(ic_rw_addr_bank_q(k))(k)(i) := io.test_in
}.elsewhen((!ic_b_sb_wren(k)(i)&ic_bank_way_clken(k)(i)).asBool){ }.elsewhen((!ic_b_sb_wren(k)(i)&ic_bank_way_clken(k)(i)).asBool){
wb_out := data_mem(ic_rw_addr_bank_q(k))(k)(i) wb_out(i)(k) := data_mem(ic_rw_addr_bank_q(k))(k)(i)
} }
} }
io.test_port := wb_out
// val ic_bank_way_clken = new Array[UInt](ICACHE_NUM_WAYS) // val ic_bank_way_clken = new Array[UInt](ICACHE_NUM_WAYS)
// ic_bank_way_clken(0) = (repl(ICACHE_NUM_WAYS,ic_b_rden(0)) | io.clk_override | ic_b_sb_wren(0)) // ic_bank_way_clken(0) = (repl(ICACHE_NUM_WAYS,ic_b_rden(0)) | io.clk_override | ic_b_sb_wren(0))

55
src/main/scala/ifu/el2_ifu_ifc_ctl.scala
View File

@ -5,35 +5,34 @@ import chisel3.util._
class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset { class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
val io = IO(new Bundle{ val io = IO(new Bundle{
val free_clk = Input(Clock()) val free_clk = Input(Clock())
val active_clk = Input(Bool()) val active_clk = Input(Bool())
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val ic_hit_f = Input(Bool()) val ic_hit_f = Input(Bool())
val ifu_ic_mb_empty = Input(Bool()) val ifu_ic_mb_empty = Input(Bool())
val ifu_fb_consume1 = Input(Bool()) val ifu_fb_consume1 = Input(Bool())
val ifu_fb_consume2 = Input(Bool()) val ifu_fb_consume2 = Input(Bool())
val dec_tlu_flush_noredir_wb = Input(Bool()) val dec_tlu_flush_noredir_wb = Input(Bool())
val exu_flush_final = Input(Bool()) val exu_flush_final = Input(Bool())
val exu_flush_path_final = Input(UInt(31.W)) val exu_flush_path_final = Input(UInt(31.W))
val ifu_bp_hit_taken_f = Input(Bool()) val ifu_bp_hit_taken_f = Input(Bool())
val ifu_bp_btb_target_f = Input(UInt(31.W)) val ifu_bp_btb_target_f = Input(UInt(31.W))
val ic_dma_active = Input(Bool()) val ic_dma_active = Input(Bool())
val ic_write_stall = Input(Bool()) val ic_write_stall = Input(Bool())
val dma_iccm_stall_any = Input(Bool()) val dma_iccm_stall_any = Input(Bool())
val dec_tlu_mrac_ff = Input(UInt(32.W)) val dec_tlu_mrac_ff = Input(UInt(32.W))
val ifc_fetch_addr_f = Output(UInt(31.W)) val ifc_fetch_addr_f = Output(UInt(31.W))
val ifc_fetch_addr_bf = Output(UInt(31.W)) val ifc_fetch_addr_bf = Output(UInt(31.W))
val ifc_fetch_req_f = Output(Bool()) val ifc_fetch_req_f = Output(Bool())
val ifu_pmu_fetch_stall = Output(Bool()) val ifu_pmu_fetch_stall = Output(Bool())
val ifc_fetch_uncacheable_bf = Output(Bool()) val ifc_fetch_uncacheable_bf = Output(Bool())
val ifc_fetch_req_bf = Output(Bool()) val ifc_fetch_req_bf = Output(Bool())
val ifc_fetch_req_bf_raw = Output(Bool()) val ifc_fetch_req_bf_raw = Output(Bool())
val ifc_iccm_access_bf = Output(Bool()) val ifc_iccm_access_bf = Output(Bool())
val ifc_region_acc_fault_bf = Output(Bool()) val ifc_region_acc_fault_bf = Output(Bool())
val ifc_dma_access_ok = Output(Bool()) val ifc_dma_access_ok = Output(Bool())
val test = Output(Bool())
}) })
val fetch_addr_bf = WireInit(UInt(31.W), init = 0.U) val fetch_addr_bf = WireInit(UInt(31.W), init = 0.U)
@ -77,7 +76,7 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
val address_upper = io.ifc_fetch_addr_f(30,1)+1.U val address_upper = io.ifc_fetch_addr_f(30,1)+1.U
fetch_addr_next_0 := !(address_upper(ICACHE_TAG_INDEX_LO-2) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO-1)) & io.ifc_fetch_addr_f(0) fetch_addr_next_0 := !(address_upper(ICACHE_TAG_INDEX_LO-2) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO-1)) & io.ifc_fetch_addr_f(0)
io.test := fetch_addr_next_0
fetch_addr_next := Cat(address_upper, fetch_addr_next_0) fetch_addr_next := Cat(address_upper, fetch_addr_next_0)
io.ifc_fetch_req_bf_raw := ~idle io.ifc_fetch_req_bf_raw := ~idle

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target/scala-2.12/classes/ifu/EL2_IC_DATA$$anon$3.class
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target/scala-2.12/classes/ifu/EL2_IC_DATA.class
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target/scala-2.12/classes/ifu/ifu_ic$.class
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