axi to ahb update
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@ -168,7 +168,6 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
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("b01".U & (Fill(2, ((byteen(7, 0) === "hc0".U) | (byteen(7, 0) === "h30".U) | (byteen(7, 0) === "h0c".U) | (byteen(7, 0) === "h03".U)))))
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("b01".U & (Fill(2, ((byteen(7, 0) === "hc0".U) | (byteen(7, 0) === "h30".U) | (byteen(7, 0) === "h0c".U) | (byteen(7, 0) === "h03".U)))))
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size
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size
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}
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}
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def get_write_addr(byteen_e: UInt) = {
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def get_write_addr(byteen_e: UInt) = {
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val byteen_e = WireInit(0.U(8.W))
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val byteen_e = WireInit(0.U(8.W))
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val addr = ("h0".U & (Fill(3, ((byteen_e(7, 0) === "hff".U) | (byteen_e(7, 0) === "h0f".U) | (byteen_e(7, 0) === "h03".U))))) |
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val addr = ("h0".U & (Fill(3, ((byteen_e(7, 0) === "hff".U) | (byteen_e(7, 0) === "h0f".U) | (byteen_e(7, 0) === "h03".U))))) |
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