From e9c21910d83dc3c5514ab43123c63d37289d68e8 Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Thu, 8 Oct 2020 14:29:53 +0500 Subject: [PATCH] RegEnable added --- el2_ifu_iccm_mem.fir | 802 +++++++++--------- el2_ifu_iccm_mem.v | 496 +++++------ src/main/scala/ifu/el2_ifu_iccm_mem.scala | 2 +- .../classes/ifu/el2_ifu_iccm_mem.class | Bin 93821 -> 93706 bytes 4 files changed, 648 insertions(+), 652 deletions(-) diff --git a/el2_ifu_iccm_mem.fir b/el2_ifu_iccm_mem.fir index a0587504..05505e07 100644 --- a/el2_ifu_iccm_mem.fir +++ b/el2_ifu_iccm_mem.fir @@ -159,42 +159,30 @@ circuit el2_ifu_iccm_mem : infer mport _T_104 = _T_88[addr_bank[3]], clock @[el2_ifu_iccm_mem.scala 54:66] _T_104 <= iccm_bank_wr_data[3] @[el2_ifu_iccm_mem.scala 54:81] skip @[el2_ifu_iccm_mem.scala 54:54] - wire _T_105 : UInt @[el2_ifu_iccm_mem.scala 56:72] - _T_105 is invalid @[el2_ifu_iccm_mem.scala 56:72] - when read_enable[0] : @[el2_ifu_iccm_mem.scala 56:72] - _T_105 <= addr_bank[0] @[el2_ifu_iccm_mem.scala 56:72] - node _T_106 = or(_T_105, UInt<12>("h00")) @[el2_ifu_iccm_mem.scala 56:72] - node _T_107 = bits(_T_106, 11, 0) @[el2_ifu_iccm_mem.scala 56:72] - read mport _T_108 = _T_85[_T_107], clock @[el2_ifu_iccm_mem.scala 56:72] - skip @[el2_ifu_iccm_mem.scala 56:72] - iccm_bank_dout[0] <= _T_108 @[el2_ifu_iccm_mem.scala 56:53] - wire _T_109 : UInt @[el2_ifu_iccm_mem.scala 56:72] - _T_109 is invalid @[el2_ifu_iccm_mem.scala 56:72] - when read_enable[1] : @[el2_ifu_iccm_mem.scala 56:72] - _T_109 <= addr_bank[1] @[el2_ifu_iccm_mem.scala 56:72] - node _T_110 = or(_T_109, UInt<12>("h00")) @[el2_ifu_iccm_mem.scala 56:72] - node _T_111 = bits(_T_110, 11, 0) @[el2_ifu_iccm_mem.scala 56:72] - read mport _T_112 = _T_86[_T_111], clock @[el2_ifu_iccm_mem.scala 56:72] - skip @[el2_ifu_iccm_mem.scala 56:72] - iccm_bank_dout[1] <= _T_112 @[el2_ifu_iccm_mem.scala 56:53] - wire _T_113 : UInt @[el2_ifu_iccm_mem.scala 56:72] - _T_113 is invalid @[el2_ifu_iccm_mem.scala 56:72] - when read_enable[2] : @[el2_ifu_iccm_mem.scala 56:72] - _T_113 <= addr_bank[2] @[el2_ifu_iccm_mem.scala 56:72] - node _T_114 = or(_T_113, UInt<12>("h00")) @[el2_ifu_iccm_mem.scala 56:72] - node _T_115 = bits(_T_114, 11, 0) @[el2_ifu_iccm_mem.scala 56:72] - read mport _T_116 = _T_87[_T_115], clock @[el2_ifu_iccm_mem.scala 56:72] - skip @[el2_ifu_iccm_mem.scala 56:72] - iccm_bank_dout[2] <= _T_116 @[el2_ifu_iccm_mem.scala 56:53] - wire _T_117 : UInt @[el2_ifu_iccm_mem.scala 56:72] - _T_117 is invalid @[el2_ifu_iccm_mem.scala 56:72] - when read_enable[3] : @[el2_ifu_iccm_mem.scala 56:72] - _T_117 <= addr_bank[3] @[el2_ifu_iccm_mem.scala 56:72] - node _T_118 = or(_T_117, UInt<12>("h00")) @[el2_ifu_iccm_mem.scala 56:72] - node _T_119 = bits(_T_118, 11, 0) @[el2_ifu_iccm_mem.scala 56:72] - read mport _T_120 = _T_88[_T_119], clock @[el2_ifu_iccm_mem.scala 56:72] - skip @[el2_ifu_iccm_mem.scala 56:72] - iccm_bank_dout[3] <= _T_120 @[el2_ifu_iccm_mem.scala 56:53] + infer mport _T_105 = _T_85[addr_bank[0]], clock @[el2_ifu_iccm_mem.scala 56:77] + reg _T_106 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when read_enable[0] : @[Reg.scala 28:19] + _T_106 <= _T_105 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + iccm_bank_dout[0] <= _T_106 @[el2_ifu_iccm_mem.scala 56:53] + infer mport _T_107 = _T_86[addr_bank[1]], clock @[el2_ifu_iccm_mem.scala 56:77] + reg _T_108 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when read_enable[1] : @[Reg.scala 28:19] + _T_108 <= _T_107 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + iccm_bank_dout[1] <= _T_108 @[el2_ifu_iccm_mem.scala 56:53] + infer mport _T_109 = _T_87[addr_bank[2]], clock @[el2_ifu_iccm_mem.scala 56:77] + reg _T_110 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when read_enable[2] : @[Reg.scala 28:19] + _T_110 <= _T_109 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + iccm_bank_dout[2] <= _T_110 @[el2_ifu_iccm_mem.scala 56:53] + infer mport _T_111 = _T_88[addr_bank[3]], clock @[el2_ifu_iccm_mem.scala 56:77] + reg _T_112 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when read_enable[3] : @[Reg.scala 28:19] + _T_112 <= _T_111 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + iccm_bank_dout[3] <= _T_112 @[el2_ifu_iccm_mem.scala 56:53] io.iccm_bank_addr[0] <= addr_bank[0] @[el2_ifu_iccm_mem.scala 61:21] io.iccm_bank_addr[1] <= addr_bank[1] @[el2_ifu_iccm_mem.scala 61:21] io.iccm_bank_addr[2] <= addr_bank[2] @[el2_ifu_iccm_mem.scala 61:21] @@ -204,132 +192,132 @@ circuit el2_ifu_iccm_mem : wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 67:31] redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 68:21] redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 68:21] - node _T_121 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67] - node _T_122 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90] - node _T_123 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128] - node _T_124 = eq(_T_122, _T_123) @[el2_ifu_iccm_mem.scala 70:105] - node _T_125 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163] - node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 70:169] - node _T_127 = and(_T_124, _T_126) @[el2_ifu_iccm_mem.scala 70:145] - node _T_128 = and(_T_121, _T_127) @[el2_ifu_iccm_mem.scala 70:71] - node _T_129 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22] - node _T_130 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60] - node _T_131 = eq(_T_129, _T_130) @[el2_ifu_iccm_mem.scala 71:37] - node _T_132 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93] - node _T_133 = eq(_T_132, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 71:99] - node _T_134 = and(_T_131, _T_133) @[el2_ifu_iccm_mem.scala 71:77] - node _T_135 = or(_T_128, _T_134) @[el2_ifu_iccm_mem.scala 70:179] - node _T_136 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67] - node _T_137 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90] - node _T_138 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128] - node _T_139 = eq(_T_137, _T_138) @[el2_ifu_iccm_mem.scala 70:105] - node _T_140 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163] - node _T_141 = eq(_T_140, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 70:169] - node _T_142 = and(_T_139, _T_141) @[el2_ifu_iccm_mem.scala 70:145] - node _T_143 = and(_T_136, _T_142) @[el2_ifu_iccm_mem.scala 70:71] - node _T_144 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22] - node _T_145 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60] - node _T_146 = eq(_T_144, _T_145) @[el2_ifu_iccm_mem.scala 71:37] - node _T_147 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93] - node _T_148 = eq(_T_147, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 71:99] - node _T_149 = and(_T_146, _T_148) @[el2_ifu_iccm_mem.scala 71:77] - node _T_150 = or(_T_143, _T_149) @[el2_ifu_iccm_mem.scala 70:179] - node _T_151 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67] - node _T_152 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90] - node _T_153 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128] - node _T_154 = eq(_T_152, _T_153) @[el2_ifu_iccm_mem.scala 70:105] - node _T_155 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163] - node _T_156 = eq(_T_155, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 70:169] - node _T_157 = and(_T_154, _T_156) @[el2_ifu_iccm_mem.scala 70:145] - node _T_158 = and(_T_151, _T_157) @[el2_ifu_iccm_mem.scala 70:71] - node _T_159 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22] - node _T_160 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60] - node _T_161 = eq(_T_159, _T_160) @[el2_ifu_iccm_mem.scala 71:37] - node _T_162 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93] - node _T_163 = eq(_T_162, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 71:99] - node _T_164 = and(_T_161, _T_163) @[el2_ifu_iccm_mem.scala 71:77] - node _T_165 = or(_T_158, _T_164) @[el2_ifu_iccm_mem.scala 70:179] - node _T_166 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67] - node _T_167 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90] - node _T_168 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128] - node _T_169 = eq(_T_167, _T_168) @[el2_ifu_iccm_mem.scala 70:105] - node _T_170 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163] - node _T_171 = eq(_T_170, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 70:169] - node _T_172 = and(_T_169, _T_171) @[el2_ifu_iccm_mem.scala 70:145] - node _T_173 = and(_T_166, _T_172) @[el2_ifu_iccm_mem.scala 70:71] - node _T_174 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22] - node _T_175 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60] - node _T_176 = eq(_T_174, _T_175) @[el2_ifu_iccm_mem.scala 71:37] - node _T_177 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93] - node _T_178 = eq(_T_177, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 71:99] - node _T_179 = and(_T_176, _T_178) @[el2_ifu_iccm_mem.scala 71:77] - node _T_180 = or(_T_173, _T_179) @[el2_ifu_iccm_mem.scala 70:179] - node _T_181 = cat(_T_180, _T_165) @[Cat.scala 29:58] - node _T_182 = cat(_T_181, _T_150) @[Cat.scala 29:58] - node sel_red1 = cat(_T_182, _T_135) @[Cat.scala 29:58] - node _T_183 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67] - node _T_184 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90] - node _T_185 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128] - node _T_186 = eq(_T_184, _T_185) @[el2_ifu_iccm_mem.scala 72:105] - node _T_187 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163] - node _T_188 = eq(_T_187, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 72:169] - node _T_189 = and(_T_186, _T_188) @[el2_ifu_iccm_mem.scala 72:145] - node _T_190 = and(_T_183, _T_189) @[el2_ifu_iccm_mem.scala 72:71] - node _T_191 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22] - node _T_192 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60] - node _T_193 = eq(_T_191, _T_192) @[el2_ifu_iccm_mem.scala 73:37] - node _T_194 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93] - node _T_195 = eq(_T_194, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 73:99] - node _T_196 = and(_T_193, _T_195) @[el2_ifu_iccm_mem.scala 73:77] - node _T_197 = or(_T_190, _T_196) @[el2_ifu_iccm_mem.scala 72:179] - node _T_198 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67] - node _T_199 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90] - node _T_200 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128] - node _T_201 = eq(_T_199, _T_200) @[el2_ifu_iccm_mem.scala 72:105] - node _T_202 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163] - node _T_203 = eq(_T_202, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 72:169] - node _T_204 = and(_T_201, _T_203) @[el2_ifu_iccm_mem.scala 72:145] - node _T_205 = and(_T_198, _T_204) @[el2_ifu_iccm_mem.scala 72:71] - node _T_206 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22] - node _T_207 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60] - node _T_208 = eq(_T_206, _T_207) @[el2_ifu_iccm_mem.scala 73:37] - node _T_209 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93] - node _T_210 = eq(_T_209, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 73:99] - node _T_211 = and(_T_208, _T_210) @[el2_ifu_iccm_mem.scala 73:77] - node _T_212 = or(_T_205, _T_211) @[el2_ifu_iccm_mem.scala 72:179] - node _T_213 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67] - node _T_214 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90] - node _T_215 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128] - node _T_216 = eq(_T_214, _T_215) @[el2_ifu_iccm_mem.scala 72:105] - node _T_217 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163] - node _T_218 = eq(_T_217, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 72:169] - node _T_219 = and(_T_216, _T_218) @[el2_ifu_iccm_mem.scala 72:145] - node _T_220 = and(_T_213, _T_219) @[el2_ifu_iccm_mem.scala 72:71] - node _T_221 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22] - node _T_222 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60] - node _T_223 = eq(_T_221, _T_222) @[el2_ifu_iccm_mem.scala 73:37] - node _T_224 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93] - node _T_225 = eq(_T_224, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 73:99] - node _T_226 = and(_T_223, _T_225) @[el2_ifu_iccm_mem.scala 73:77] - node _T_227 = or(_T_220, _T_226) @[el2_ifu_iccm_mem.scala 72:179] - node _T_228 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67] - node _T_229 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90] - node _T_230 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128] - node _T_231 = eq(_T_229, _T_230) @[el2_ifu_iccm_mem.scala 72:105] - node _T_232 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163] - node _T_233 = eq(_T_232, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 72:169] - node _T_234 = and(_T_231, _T_233) @[el2_ifu_iccm_mem.scala 72:145] - node _T_235 = and(_T_228, _T_234) @[el2_ifu_iccm_mem.scala 72:71] - node _T_236 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22] - node _T_237 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60] - node _T_238 = eq(_T_236, _T_237) @[el2_ifu_iccm_mem.scala 73:37] - node _T_239 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93] - node _T_240 = eq(_T_239, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 73:99] - node _T_241 = and(_T_238, _T_240) @[el2_ifu_iccm_mem.scala 73:77] - node _T_242 = or(_T_235, _T_241) @[el2_ifu_iccm_mem.scala 72:179] - node _T_243 = cat(_T_242, _T_227) @[Cat.scala 29:58] - node _T_244 = cat(_T_243, _T_212) @[Cat.scala 29:58] - node sel_red0 = cat(_T_244, _T_197) @[Cat.scala 29:58] + node _T_113 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67] + node _T_114 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90] + node _T_115 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128] + node _T_116 = eq(_T_114, _T_115) @[el2_ifu_iccm_mem.scala 70:105] + node _T_117 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 70:169] + node _T_119 = and(_T_116, _T_118) @[el2_ifu_iccm_mem.scala 70:145] + node _T_120 = and(_T_113, _T_119) @[el2_ifu_iccm_mem.scala 70:71] + node _T_121 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22] + node _T_122 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60] + node _T_123 = eq(_T_121, _T_122) @[el2_ifu_iccm_mem.scala 71:37] + node _T_124 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93] + node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 71:99] + node _T_126 = and(_T_123, _T_125) @[el2_ifu_iccm_mem.scala 71:77] + node _T_127 = or(_T_120, _T_126) @[el2_ifu_iccm_mem.scala 70:179] + node _T_128 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67] + node _T_129 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90] + node _T_130 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128] + node _T_131 = eq(_T_129, _T_130) @[el2_ifu_iccm_mem.scala 70:105] + node _T_132 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163] + node _T_133 = eq(_T_132, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 70:169] + node _T_134 = and(_T_131, _T_133) @[el2_ifu_iccm_mem.scala 70:145] + node _T_135 = and(_T_128, _T_134) @[el2_ifu_iccm_mem.scala 70:71] + node _T_136 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22] + node _T_137 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60] + node _T_138 = eq(_T_136, _T_137) @[el2_ifu_iccm_mem.scala 71:37] + node _T_139 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 71:99] + node _T_141 = and(_T_138, _T_140) @[el2_ifu_iccm_mem.scala 71:77] + node _T_142 = or(_T_135, _T_141) @[el2_ifu_iccm_mem.scala 70:179] + node _T_143 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67] + node _T_144 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90] + node _T_145 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128] + node _T_146 = eq(_T_144, _T_145) @[el2_ifu_iccm_mem.scala 70:105] + node _T_147 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163] + node _T_148 = eq(_T_147, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 70:169] + node _T_149 = and(_T_146, _T_148) @[el2_ifu_iccm_mem.scala 70:145] + node _T_150 = and(_T_143, _T_149) @[el2_ifu_iccm_mem.scala 70:71] + node _T_151 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22] + node _T_152 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60] + node _T_153 = eq(_T_151, _T_152) @[el2_ifu_iccm_mem.scala 71:37] + node _T_154 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93] + node _T_155 = eq(_T_154, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 71:99] + node _T_156 = and(_T_153, _T_155) @[el2_ifu_iccm_mem.scala 71:77] + node _T_157 = or(_T_150, _T_156) @[el2_ifu_iccm_mem.scala 70:179] + node _T_158 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67] + node _T_159 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90] + node _T_160 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128] + node _T_161 = eq(_T_159, _T_160) @[el2_ifu_iccm_mem.scala 70:105] + node _T_162 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163] + node _T_163 = eq(_T_162, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 70:169] + node _T_164 = and(_T_161, _T_163) @[el2_ifu_iccm_mem.scala 70:145] + node _T_165 = and(_T_158, _T_164) @[el2_ifu_iccm_mem.scala 70:71] + node _T_166 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22] + node _T_167 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60] + node _T_168 = eq(_T_166, _T_167) @[el2_ifu_iccm_mem.scala 71:37] + node _T_169 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93] + node _T_170 = eq(_T_169, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 71:99] + node _T_171 = and(_T_168, _T_170) @[el2_ifu_iccm_mem.scala 71:77] + node _T_172 = or(_T_165, _T_171) @[el2_ifu_iccm_mem.scala 70:179] + node _T_173 = cat(_T_172, _T_157) @[Cat.scala 29:58] + node _T_174 = cat(_T_173, _T_142) @[Cat.scala 29:58] + node sel_red1 = cat(_T_174, _T_127) @[Cat.scala 29:58] + node _T_175 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67] + node _T_176 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90] + node _T_177 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128] + node _T_178 = eq(_T_176, _T_177) @[el2_ifu_iccm_mem.scala 72:105] + node _T_179 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163] + node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 72:169] + node _T_181 = and(_T_178, _T_180) @[el2_ifu_iccm_mem.scala 72:145] + node _T_182 = and(_T_175, _T_181) @[el2_ifu_iccm_mem.scala 72:71] + node _T_183 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22] + node _T_184 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60] + node _T_185 = eq(_T_183, _T_184) @[el2_ifu_iccm_mem.scala 73:37] + node _T_186 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93] + node _T_187 = eq(_T_186, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 73:99] + node _T_188 = and(_T_185, _T_187) @[el2_ifu_iccm_mem.scala 73:77] + node _T_189 = or(_T_182, _T_188) @[el2_ifu_iccm_mem.scala 72:179] + node _T_190 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67] + node _T_191 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90] + node _T_192 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128] + node _T_193 = eq(_T_191, _T_192) @[el2_ifu_iccm_mem.scala 72:105] + node _T_194 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163] + node _T_195 = eq(_T_194, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 72:169] + node _T_196 = and(_T_193, _T_195) @[el2_ifu_iccm_mem.scala 72:145] + node _T_197 = and(_T_190, _T_196) @[el2_ifu_iccm_mem.scala 72:71] + node _T_198 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22] + node _T_199 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60] + node _T_200 = eq(_T_198, _T_199) @[el2_ifu_iccm_mem.scala 73:37] + node _T_201 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93] + node _T_202 = eq(_T_201, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 73:99] + node _T_203 = and(_T_200, _T_202) @[el2_ifu_iccm_mem.scala 73:77] + node _T_204 = or(_T_197, _T_203) @[el2_ifu_iccm_mem.scala 72:179] + node _T_205 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67] + node _T_206 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90] + node _T_207 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128] + node _T_208 = eq(_T_206, _T_207) @[el2_ifu_iccm_mem.scala 72:105] + node _T_209 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163] + node _T_210 = eq(_T_209, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 72:169] + node _T_211 = and(_T_208, _T_210) @[el2_ifu_iccm_mem.scala 72:145] + node _T_212 = and(_T_205, _T_211) @[el2_ifu_iccm_mem.scala 72:71] + node _T_213 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22] + node _T_214 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60] + node _T_215 = eq(_T_213, _T_214) @[el2_ifu_iccm_mem.scala 73:37] + node _T_216 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93] + node _T_217 = eq(_T_216, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 73:99] + node _T_218 = and(_T_215, _T_217) @[el2_ifu_iccm_mem.scala 73:77] + node _T_219 = or(_T_212, _T_218) @[el2_ifu_iccm_mem.scala 72:179] + node _T_220 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67] + node _T_221 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90] + node _T_222 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128] + node _T_223 = eq(_T_221, _T_222) @[el2_ifu_iccm_mem.scala 72:105] + node _T_224 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163] + node _T_225 = eq(_T_224, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 72:169] + node _T_226 = and(_T_223, _T_225) @[el2_ifu_iccm_mem.scala 72:145] + node _T_227 = and(_T_220, _T_226) @[el2_ifu_iccm_mem.scala 72:71] + node _T_228 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22] + node _T_229 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60] + node _T_230 = eq(_T_228, _T_229) @[el2_ifu_iccm_mem.scala 73:37] + node _T_231 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93] + node _T_232 = eq(_T_231, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 73:99] + node _T_233 = and(_T_230, _T_232) @[el2_ifu_iccm_mem.scala 73:77] + node _T_234 = or(_T_227, _T_233) @[el2_ifu_iccm_mem.scala 72:179] + node _T_235 = cat(_T_234, _T_219) @[Cat.scala 29:58] + node _T_236 = cat(_T_235, _T_204) @[Cat.scala 29:58] + node sel_red0 = cat(_T_236, _T_189) @[Cat.scala 29:58] reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 75:27] sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 75:27] reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 76:27] @@ -337,268 +325,268 @@ circuit el2_ifu_iccm_mem : wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 77:28] redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 78:18] redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 78:18] - node _T_245 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 80:47] - node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_iccm_mem.scala 80:51] - node _T_247 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 81:47] - node _T_248 = bits(_T_247, 0, 0) @[el2_ifu_iccm_mem.scala 81:51] - node _T_249 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 82:47] - node _T_250 = not(_T_249) @[el2_ifu_iccm_mem.scala 82:36] - node _T_251 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 82:64] - node _T_252 = not(_T_251) @[el2_ifu_iccm_mem.scala 82:53] - node _T_253 = and(_T_250, _T_252) @[el2_ifu_iccm_mem.scala 82:51] - node _T_254 = bits(_T_253, 0, 0) @[el2_ifu_iccm_mem.scala 82:69] - node _T_255 = mux(_T_246, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_256 = mux(_T_248, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_257 = mux(_T_254, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_258 = or(_T_255, _T_256) @[Mux.scala 27:72] - node _T_259 = or(_T_258, _T_257) @[Mux.scala 27:72] + node _T_237 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 80:47] + node _T_238 = bits(_T_237, 0, 0) @[el2_ifu_iccm_mem.scala 80:51] + node _T_239 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 81:47] + node _T_240 = bits(_T_239, 0, 0) @[el2_ifu_iccm_mem.scala 81:51] + node _T_241 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 82:47] + node _T_242 = not(_T_241) @[el2_ifu_iccm_mem.scala 82:36] + node _T_243 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 82:64] + node _T_244 = not(_T_243) @[el2_ifu_iccm_mem.scala 82:53] + node _T_245 = and(_T_242, _T_244) @[el2_ifu_iccm_mem.scala 82:51] + node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_iccm_mem.scala 82:69] + node _T_247 = mux(_T_238, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_248 = mux(_T_240, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_249 = mux(_T_246, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_250 = or(_T_247, _T_248) @[Mux.scala 27:72] + node _T_251 = or(_T_250, _T_249) @[Mux.scala 27:72] wire iccm_bank_dout_fn_0 : UInt<39> @[Mux.scala 27:72] - iccm_bank_dout_fn_0 <= _T_259 @[Mux.scala 27:72] - node _T_260 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 80:47] - node _T_261 = bits(_T_260, 0, 0) @[el2_ifu_iccm_mem.scala 80:51] - node _T_262 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 81:47] - node _T_263 = bits(_T_262, 0, 0) @[el2_ifu_iccm_mem.scala 81:51] - node _T_264 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 82:47] - node _T_265 = not(_T_264) @[el2_ifu_iccm_mem.scala 82:36] - node _T_266 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 82:64] - node _T_267 = not(_T_266) @[el2_ifu_iccm_mem.scala 82:53] - node _T_268 = and(_T_265, _T_267) @[el2_ifu_iccm_mem.scala 82:51] - node _T_269 = bits(_T_268, 0, 0) @[el2_ifu_iccm_mem.scala 82:69] - node _T_270 = mux(_T_261, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_271 = mux(_T_263, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_272 = mux(_T_269, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_273 = or(_T_270, _T_271) @[Mux.scala 27:72] - node _T_274 = or(_T_273, _T_272) @[Mux.scala 27:72] + iccm_bank_dout_fn_0 <= _T_251 @[Mux.scala 27:72] + node _T_252 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 80:47] + node _T_253 = bits(_T_252, 0, 0) @[el2_ifu_iccm_mem.scala 80:51] + node _T_254 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 81:47] + node _T_255 = bits(_T_254, 0, 0) @[el2_ifu_iccm_mem.scala 81:51] + node _T_256 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 82:47] + node _T_257 = not(_T_256) @[el2_ifu_iccm_mem.scala 82:36] + node _T_258 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 82:64] + node _T_259 = not(_T_258) @[el2_ifu_iccm_mem.scala 82:53] + node _T_260 = and(_T_257, _T_259) @[el2_ifu_iccm_mem.scala 82:51] + node _T_261 = bits(_T_260, 0, 0) @[el2_ifu_iccm_mem.scala 82:69] + node _T_262 = mux(_T_253, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_263 = mux(_T_255, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_264 = mux(_T_261, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_265 = or(_T_262, _T_263) @[Mux.scala 27:72] + node _T_266 = or(_T_265, _T_264) @[Mux.scala 27:72] wire iccm_bank_dout_fn_1 : UInt<39> @[Mux.scala 27:72] - iccm_bank_dout_fn_1 <= _T_274 @[Mux.scala 27:72] - node _T_275 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 80:47] - node _T_276 = bits(_T_275, 0, 0) @[el2_ifu_iccm_mem.scala 80:51] - node _T_277 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 81:47] - node _T_278 = bits(_T_277, 0, 0) @[el2_ifu_iccm_mem.scala 81:51] - node _T_279 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 82:47] - node _T_280 = not(_T_279) @[el2_ifu_iccm_mem.scala 82:36] - node _T_281 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 82:64] - node _T_282 = not(_T_281) @[el2_ifu_iccm_mem.scala 82:53] - node _T_283 = and(_T_280, _T_282) @[el2_ifu_iccm_mem.scala 82:51] - node _T_284 = bits(_T_283, 0, 0) @[el2_ifu_iccm_mem.scala 82:69] - node _T_285 = mux(_T_276, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_286 = mux(_T_278, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_287 = mux(_T_284, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_288 = or(_T_285, _T_286) @[Mux.scala 27:72] - node _T_289 = or(_T_288, _T_287) @[Mux.scala 27:72] + iccm_bank_dout_fn_1 <= _T_266 @[Mux.scala 27:72] + node _T_267 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 80:47] + node _T_268 = bits(_T_267, 0, 0) @[el2_ifu_iccm_mem.scala 80:51] + node _T_269 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 81:47] + node _T_270 = bits(_T_269, 0, 0) @[el2_ifu_iccm_mem.scala 81:51] + node _T_271 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 82:47] + node _T_272 = not(_T_271) @[el2_ifu_iccm_mem.scala 82:36] + node _T_273 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 82:64] + node _T_274 = not(_T_273) @[el2_ifu_iccm_mem.scala 82:53] + node _T_275 = and(_T_272, _T_274) @[el2_ifu_iccm_mem.scala 82:51] + node _T_276 = bits(_T_275, 0, 0) @[el2_ifu_iccm_mem.scala 82:69] + node _T_277 = mux(_T_268, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_278 = mux(_T_270, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_279 = mux(_T_276, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_280 = or(_T_277, _T_278) @[Mux.scala 27:72] + node _T_281 = or(_T_280, _T_279) @[Mux.scala 27:72] wire iccm_bank_dout_fn_2 : UInt<39> @[Mux.scala 27:72] - iccm_bank_dout_fn_2 <= _T_289 @[Mux.scala 27:72] - node _T_290 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 80:47] - node _T_291 = bits(_T_290, 0, 0) @[el2_ifu_iccm_mem.scala 80:51] - node _T_292 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 81:47] - node _T_293 = bits(_T_292, 0, 0) @[el2_ifu_iccm_mem.scala 81:51] - node _T_294 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 82:47] - node _T_295 = not(_T_294) @[el2_ifu_iccm_mem.scala 82:36] - node _T_296 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 82:64] - node _T_297 = not(_T_296) @[el2_ifu_iccm_mem.scala 82:53] - node _T_298 = and(_T_295, _T_297) @[el2_ifu_iccm_mem.scala 82:51] - node _T_299 = bits(_T_298, 0, 0) @[el2_ifu_iccm_mem.scala 82:69] - node _T_300 = mux(_T_291, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_301 = mux(_T_293, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_302 = mux(_T_299, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_303 = or(_T_300, _T_301) @[Mux.scala 27:72] - node _T_304 = or(_T_303, _T_302) @[Mux.scala 27:72] + iccm_bank_dout_fn_2 <= _T_281 @[Mux.scala 27:72] + node _T_282 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 80:47] + node _T_283 = bits(_T_282, 0, 0) @[el2_ifu_iccm_mem.scala 80:51] + node _T_284 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 81:47] + node _T_285 = bits(_T_284, 0, 0) @[el2_ifu_iccm_mem.scala 81:51] + node _T_286 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 82:47] + node _T_287 = not(_T_286) @[el2_ifu_iccm_mem.scala 82:36] + node _T_288 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 82:64] + node _T_289 = not(_T_288) @[el2_ifu_iccm_mem.scala 82:53] + node _T_290 = and(_T_287, _T_289) @[el2_ifu_iccm_mem.scala 82:51] + node _T_291 = bits(_T_290, 0, 0) @[el2_ifu_iccm_mem.scala 82:69] + node _T_292 = mux(_T_283, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_293 = mux(_T_285, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_294 = mux(_T_291, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_295 = or(_T_292, _T_293) @[Mux.scala 27:72] + node _T_296 = or(_T_295, _T_294) @[Mux.scala 27:72] wire iccm_bank_dout_fn_3 : UInt<39> @[Mux.scala 27:72] - iccm_bank_dout_fn_3 <= _T_304 @[Mux.scala 27:72] + iccm_bank_dout_fn_3 <= _T_296 @[Mux.scala 27:72] wire redundant_lru : UInt<1> redundant_lru <= UInt<1>("h00") - node _T_305 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 84:20] - node r0_addr_en = and(_T_305, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 84:35] + node _T_297 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 84:20] + node r0_addr_en = and(_T_297, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 84:35] node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 85:35] - node _T_306 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 86:63] - node _T_307 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 86:78] - node _T_308 = or(_T_306, _T_307) @[el2_ifu_iccm_mem.scala 86:67] - node _T_309 = and(_T_308, io.iccm_rden) @[el2_ifu_iccm_mem.scala 86:83] - node _T_310 = and(_T_309, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 86:98] - node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_310) @[el2_ifu_iccm_mem.scala 86:50] - node _T_311 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 87:55] - node _T_312 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 87:84] - node _T_313 = mux(_T_312, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 87:74] - node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_311, _T_313) @[el2_ifu_iccm_mem.scala 87:29] - reg _T_314 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_298 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 86:63] + node _T_299 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 86:78] + node _T_300 = or(_T_298, _T_299) @[el2_ifu_iccm_mem.scala 86:67] + node _T_301 = and(_T_300, io.iccm_rden) @[el2_ifu_iccm_mem.scala 86:83] + node _T_302 = and(_T_301, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 86:98] + node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_302) @[el2_ifu_iccm_mem.scala 86:50] + node _T_303 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 87:55] + node _T_304 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 87:84] + node _T_305 = mux(_T_304, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 87:74] + node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_303, _T_305) @[el2_ifu_iccm_mem.scala 87:29] + reg _T_306 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when redundant_lru_en : @[Reg.scala 28:19] - _T_314 <= redundant_lru_in @[Reg.scala 28:23] + _T_306 <= redundant_lru_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - redundant_lru <= _T_314 @[el2_ifu_iccm_mem.scala 88:17] - node _T_315 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 89:52] - reg _T_316 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + redundant_lru <= _T_306 @[el2_ifu_iccm_mem.scala 88:17] + node _T_307 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 89:52] + reg _T_308 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when r0_addr_en : @[Reg.scala 28:19] - _T_316 <= _T_315 @[Reg.scala 28:23] + _T_308 <= _T_307 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - redundant_address[0] <= _T_316 @[el2_ifu_iccm_mem.scala 89:24] - node _T_317 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 90:52] - node _T_318 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 90:85] - reg _T_319 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_318 : @[Reg.scala 28:19] - _T_319 <= _T_317 @[Reg.scala 28:23] + redundant_address[0] <= _T_308 @[el2_ifu_iccm_mem.scala 89:24] + node _T_309 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 90:52] + node _T_310 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 90:85] + reg _T_311 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_310 : @[Reg.scala 28:19] + _T_311 <= _T_309 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - redundant_address[1] <= _T_319 @[el2_ifu_iccm_mem.scala 90:24] - node _T_320 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 91:57] - reg _T_321 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_320 : @[Reg.scala 28:19] - _T_321 <= UInt<1>("h01") @[Reg.scala 28:23] + redundant_address[1] <= _T_311 @[el2_ifu_iccm_mem.scala 90:24] + node _T_312 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 91:57] + reg _T_313 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_312 : @[Reg.scala 28:19] + _T_313 <= UInt<1>("h01") @[Reg.scala 28:23] skip @[Reg.scala 28:19] - reg _T_322 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_314 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when r0_addr_en : @[Reg.scala 28:19] - _T_322 <= UInt<1>("h01") @[Reg.scala 28:23] + _T_314 <= UInt<1>("h01") @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_323 = cat(_T_321, _T_322) @[Cat.scala 29:58] - redundant_valid <= _T_323 @[el2_ifu_iccm_mem.scala 91:19] - node _T_324 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 93:45] - node _T_325 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 93:85] - node _T_326 = eq(_T_324, _T_325) @[el2_ifu_iccm_mem.scala 93:61] - node _T_327 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 94:22] - node _T_328 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 94:48] - node _T_329 = and(_T_327, _T_328) @[el2_ifu_iccm_mem.scala 94:26] - node _T_330 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 94:70] - node _T_331 = eq(_T_330, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 94:75] - node _T_332 = or(_T_329, _T_331) @[el2_ifu_iccm_mem.scala 94:52] - node _T_333 = and(_T_326, _T_332) @[el2_ifu_iccm_mem.scala 93:102] - node _T_334 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 94:101] - node _T_335 = and(_T_333, _T_334) @[el2_ifu_iccm_mem.scala 94:84] - node _T_336 = and(_T_335, io.iccm_wren) @[el2_ifu_iccm_mem.scala 94:105] - node _T_337 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 95:6] - node _T_338 = and(_T_337, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 95:21] - node redundant_data0_en = or(_T_336, _T_338) @[el2_ifu_iccm_mem.scala 94:121] - node _T_339 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 96:49] - node _T_340 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 96:73] - node _T_341 = and(_T_339, _T_340) @[el2_ifu_iccm_mem.scala 96:52] - node _T_342 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 96:100] - node _T_343 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 96:122] - node _T_344 = eq(_T_343, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:127] - node _T_345 = and(_T_342, _T_344) @[el2_ifu_iccm_mem.scala 96:104] - node _T_346 = or(_T_341, _T_345) @[el2_ifu_iccm_mem.scala 96:78] - node _T_347 = bits(_T_346, 0, 0) @[el2_ifu_iccm_mem.scala 96:137] - node _T_348 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 97:20] - node _T_349 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 97:44] - node redundant_data0_in = mux(_T_347, _T_348, _T_349) @[el2_ifu_iccm_mem.scala 96:31] - node _T_350 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 98:78] - reg _T_351 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_350 : @[Reg.scala 28:19] - _T_351 <= redundant_data0_in @[Reg.scala 28:23] + node _T_315 = cat(_T_313, _T_314) @[Cat.scala 29:58] + redundant_valid <= _T_315 @[el2_ifu_iccm_mem.scala 91:19] + node _T_316 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 93:45] + node _T_317 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 93:85] + node _T_318 = eq(_T_316, _T_317) @[el2_ifu_iccm_mem.scala 93:61] + node _T_319 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 94:22] + node _T_320 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 94:48] + node _T_321 = and(_T_319, _T_320) @[el2_ifu_iccm_mem.scala 94:26] + node _T_322 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 94:70] + node _T_323 = eq(_T_322, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 94:75] + node _T_324 = or(_T_321, _T_323) @[el2_ifu_iccm_mem.scala 94:52] + node _T_325 = and(_T_318, _T_324) @[el2_ifu_iccm_mem.scala 93:102] + node _T_326 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 94:101] + node _T_327 = and(_T_325, _T_326) @[el2_ifu_iccm_mem.scala 94:84] + node _T_328 = and(_T_327, io.iccm_wren) @[el2_ifu_iccm_mem.scala 94:105] + node _T_329 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 95:6] + node _T_330 = and(_T_329, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 95:21] + node redundant_data0_en = or(_T_328, _T_330) @[el2_ifu_iccm_mem.scala 94:121] + node _T_331 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 96:49] + node _T_332 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 96:73] + node _T_333 = and(_T_331, _T_332) @[el2_ifu_iccm_mem.scala 96:52] + node _T_334 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 96:100] + node _T_335 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 96:122] + node _T_336 = eq(_T_335, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:127] + node _T_337 = and(_T_334, _T_336) @[el2_ifu_iccm_mem.scala 96:104] + node _T_338 = or(_T_333, _T_337) @[el2_ifu_iccm_mem.scala 96:78] + node _T_339 = bits(_T_338, 0, 0) @[el2_ifu_iccm_mem.scala 96:137] + node _T_340 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 97:20] + node _T_341 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 97:44] + node redundant_data0_in = mux(_T_339, _T_340, _T_341) @[el2_ifu_iccm_mem.scala 96:31] + node _T_342 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 98:78] + reg _T_343 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_342 : @[Reg.scala 28:19] + _T_343 <= redundant_data0_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - redundant_data[0] <= _T_351 @[el2_ifu_iccm_mem.scala 98:21] - node _T_352 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 100:45] - node _T_353 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 100:85] - node _T_354 = eq(_T_352, _T_353) @[el2_ifu_iccm_mem.scala 100:61] - node _T_355 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 101:22] - node _T_356 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 101:48] - node _T_357 = and(_T_355, _T_356) @[el2_ifu_iccm_mem.scala 101:26] - node _T_358 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 101:70] - node _T_359 = eq(_T_358, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 101:75] - node _T_360 = or(_T_357, _T_359) @[el2_ifu_iccm_mem.scala 101:52] - node _T_361 = and(_T_354, _T_360) @[el2_ifu_iccm_mem.scala 100:102] - node _T_362 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 101:101] - node _T_363 = and(_T_361, _T_362) @[el2_ifu_iccm_mem.scala 101:84] - node _T_364 = and(_T_363, io.iccm_wren) @[el2_ifu_iccm_mem.scala 101:105] - node _T_365 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 102:6] - node _T_366 = and(_T_365, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 102:21] - node redundant_data1_en = or(_T_364, _T_366) @[el2_ifu_iccm_mem.scala 101:121] - node _T_367 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 103:49] - node _T_368 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 103:73] - node _T_369 = and(_T_367, _T_368) @[el2_ifu_iccm_mem.scala 103:52] - node _T_370 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 103:100] - node _T_371 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 103:122] - node _T_372 = eq(_T_371, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 103:127] - node _T_373 = and(_T_370, _T_372) @[el2_ifu_iccm_mem.scala 103:104] - node _T_374 = or(_T_369, _T_373) @[el2_ifu_iccm_mem.scala 103:78] - node _T_375 = bits(_T_374, 0, 0) @[el2_ifu_iccm_mem.scala 103:137] - node _T_376 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 104:20] - node _T_377 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 104:44] - node redundant_data1_in = mux(_T_375, _T_376, _T_377) @[el2_ifu_iccm_mem.scala 103:31] - node _T_378 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 105:78] - reg _T_379 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_378 : @[Reg.scala 28:19] - _T_379 <= redundant_data1_in @[Reg.scala 28:23] + redundant_data[0] <= _T_343 @[el2_ifu_iccm_mem.scala 98:21] + node _T_344 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 100:45] + node _T_345 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 100:85] + node _T_346 = eq(_T_344, _T_345) @[el2_ifu_iccm_mem.scala 100:61] + node _T_347 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 101:22] + node _T_348 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 101:48] + node _T_349 = and(_T_347, _T_348) @[el2_ifu_iccm_mem.scala 101:26] + node _T_350 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 101:70] + node _T_351 = eq(_T_350, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 101:75] + node _T_352 = or(_T_349, _T_351) @[el2_ifu_iccm_mem.scala 101:52] + node _T_353 = and(_T_346, _T_352) @[el2_ifu_iccm_mem.scala 100:102] + node _T_354 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 101:101] + node _T_355 = and(_T_353, _T_354) @[el2_ifu_iccm_mem.scala 101:84] + node _T_356 = and(_T_355, io.iccm_wren) @[el2_ifu_iccm_mem.scala 101:105] + node _T_357 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 102:6] + node _T_358 = and(_T_357, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 102:21] + node redundant_data1_en = or(_T_356, _T_358) @[el2_ifu_iccm_mem.scala 101:121] + node _T_359 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 103:49] + node _T_360 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 103:73] + node _T_361 = and(_T_359, _T_360) @[el2_ifu_iccm_mem.scala 103:52] + node _T_362 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 103:100] + node _T_363 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 103:122] + node _T_364 = eq(_T_363, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 103:127] + node _T_365 = and(_T_362, _T_364) @[el2_ifu_iccm_mem.scala 103:104] + node _T_366 = or(_T_361, _T_365) @[el2_ifu_iccm_mem.scala 103:78] + node _T_367 = bits(_T_366, 0, 0) @[el2_ifu_iccm_mem.scala 103:137] + node _T_368 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 104:20] + node _T_369 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 104:44] + node redundant_data1_in = mux(_T_367, _T_368, _T_369) @[el2_ifu_iccm_mem.scala 103:31] + node _T_370 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 105:78] + reg _T_371 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_370 : @[Reg.scala 28:19] + _T_371 <= redundant_data1_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - redundant_data[1] <= _T_379 @[el2_ifu_iccm_mem.scala 105:21] - node _T_380 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 107:50] + redundant_data[1] <= _T_371 @[el2_ifu_iccm_mem.scala 105:21] + node _T_372 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 107:50] reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 107:34] - iccm_rd_addr_lo_q <= _T_380 @[el2_ifu_iccm_mem.scala 107:34] - node _T_381 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 108:48] + iccm_rd_addr_lo_q <= _T_372 @[el2_ifu_iccm_mem.scala 107:34] + node _T_373 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 108:48] reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 108:34] - iccm_rd_addr_hi_q <= _T_381 @[el2_ifu_iccm_mem.scala 108:34] - node _T_382 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 110:86] - node _T_383 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 110:115] - node _T_384 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 110:86] - node _T_385 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 110:115] - node _T_386 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 110:86] - node _T_387 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 110:115] - node _T_388 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 110:86] - node _T_389 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 110:115] - node _T_390 = mux(_T_382, _T_383, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_391 = mux(_T_384, _T_385, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_392 = mux(_T_386, _T_387, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_393 = mux(_T_388, _T_389, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_394 = or(_T_390, _T_391) @[Mux.scala 27:72] - node _T_395 = or(_T_394, _T_392) @[Mux.scala 27:72] - node _T_396 = or(_T_395, _T_393) @[Mux.scala 27:72] - wire _T_397 : UInt<32> @[Mux.scala 27:72] - _T_397 <= _T_396 @[Mux.scala 27:72] - node _T_398 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59] - node _T_399 = eq(_T_398, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 111:77] - node _T_400 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 111:106] - node _T_401 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59] - node _T_402 = eq(_T_401, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 111:77] - node _T_403 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 111:106] - node _T_404 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59] - node _T_405 = eq(_T_404, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 111:77] - node _T_406 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 111:106] - node _T_407 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59] - node _T_408 = eq(_T_407, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 111:77] - node _T_409 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 111:106] - node _T_410 = mux(_T_399, _T_400, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_411 = mux(_T_402, _T_403, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_412 = mux(_T_405, _T_406, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_413 = mux(_T_408, _T_409, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_414 = or(_T_410, _T_411) @[Mux.scala 27:72] - node _T_415 = or(_T_414, _T_412) @[Mux.scala 27:72] - node _T_416 = or(_T_415, _T_413) @[Mux.scala 27:72] - wire _T_417 : UInt<32> @[Mux.scala 27:72] - _T_417 <= _T_416 @[Mux.scala 27:72] - node iccm_rd_data_pre = cat(_T_397, _T_417) @[Cat.scala 29:58] - node _T_418 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 112:43] - node _T_419 = bits(_T_418, 0, 0) @[el2_ifu_iccm_mem.scala 112:53] - node _T_420 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] - node _T_421 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 112:89] - node _T_422 = cat(_T_420, _T_421) @[Cat.scala 29:58] - node _T_423 = mux(_T_419, _T_422, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 112:25] - io.iccm_rd_data <= _T_423 @[el2_ifu_iccm_mem.scala 112:19] - node _T_424 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 113:85] - node _T_425 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 113:85] - node _T_426 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 113:85] - node _T_427 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 113:85] - node _T_428 = mux(_T_424, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_429 = mux(_T_425, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_430 = mux(_T_426, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_431 = mux(_T_427, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_432 = or(_T_428, _T_429) @[Mux.scala 27:72] - node _T_433 = or(_T_432, _T_430) @[Mux.scala 27:72] - node _T_434 = or(_T_433, _T_431) @[Mux.scala 27:72] - wire _T_435 : UInt<39> @[Mux.scala 27:72] - _T_435 <= _T_434 @[Mux.scala 27:72] - node _T_436 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61] - node _T_437 = eq(_T_436, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 114:79] - node _T_438 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61] - node _T_439 = eq(_T_438, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 114:79] - node _T_440 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61] - node _T_441 = eq(_T_440, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 114:79] - node _T_442 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61] - node _T_443 = eq(_T_442, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 114:79] - node _T_444 = mux(_T_437, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_445 = mux(_T_439, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_446 = mux(_T_441, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_447 = mux(_T_443, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_448 = or(_T_444, _T_445) @[Mux.scala 27:72] - node _T_449 = or(_T_448, _T_446) @[Mux.scala 27:72] - node _T_450 = or(_T_449, _T_447) @[Mux.scala 27:72] - wire _T_451 : UInt<39> @[Mux.scala 27:72] - _T_451 <= _T_450 @[Mux.scala 27:72] - node _T_452 = cat(_T_435, _T_451) @[Cat.scala 29:58] - io.iccm_rd_data_ecc <= _T_452 @[el2_ifu_iccm_mem.scala 113:23] + iccm_rd_addr_hi_q <= _T_373 @[el2_ifu_iccm_mem.scala 108:34] + node _T_374 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 110:86] + node _T_375 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 110:115] + node _T_376 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 110:86] + node _T_377 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 110:115] + node _T_378 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 110:86] + node _T_379 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 110:115] + node _T_380 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 110:86] + node _T_381 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 110:115] + node _T_382 = mux(_T_374, _T_375, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_383 = mux(_T_376, _T_377, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_384 = mux(_T_378, _T_379, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_385 = mux(_T_380, _T_381, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_386 = or(_T_382, _T_383) @[Mux.scala 27:72] + node _T_387 = or(_T_386, _T_384) @[Mux.scala 27:72] + node _T_388 = or(_T_387, _T_385) @[Mux.scala 27:72] + wire _T_389 : UInt<32> @[Mux.scala 27:72] + _T_389 <= _T_388 @[Mux.scala 27:72] + node _T_390 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59] + node _T_391 = eq(_T_390, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 111:77] + node _T_392 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 111:106] + node _T_393 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59] + node _T_394 = eq(_T_393, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 111:77] + node _T_395 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 111:106] + node _T_396 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59] + node _T_397 = eq(_T_396, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 111:77] + node _T_398 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 111:106] + node _T_399 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59] + node _T_400 = eq(_T_399, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 111:77] + node _T_401 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 111:106] + node _T_402 = mux(_T_391, _T_392, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_403 = mux(_T_394, _T_395, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_404 = mux(_T_397, _T_398, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_405 = mux(_T_400, _T_401, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_406 = or(_T_402, _T_403) @[Mux.scala 27:72] + node _T_407 = or(_T_406, _T_404) @[Mux.scala 27:72] + node _T_408 = or(_T_407, _T_405) @[Mux.scala 27:72] + wire _T_409 : UInt<32> @[Mux.scala 27:72] + _T_409 <= _T_408 @[Mux.scala 27:72] + node iccm_rd_data_pre = cat(_T_389, _T_409) @[Cat.scala 29:58] + node _T_410 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 112:43] + node _T_411 = bits(_T_410, 0, 0) @[el2_ifu_iccm_mem.scala 112:53] + node _T_412 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_413 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 112:89] + node _T_414 = cat(_T_412, _T_413) @[Cat.scala 29:58] + node _T_415 = mux(_T_411, _T_414, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 112:25] + io.iccm_rd_data <= _T_415 @[el2_ifu_iccm_mem.scala 112:19] + node _T_416 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 113:85] + node _T_417 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 113:85] + node _T_418 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 113:85] + node _T_419 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 113:85] + node _T_420 = mux(_T_416, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_421 = mux(_T_417, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_422 = mux(_T_418, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_423 = mux(_T_419, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_424 = or(_T_420, _T_421) @[Mux.scala 27:72] + node _T_425 = or(_T_424, _T_422) @[Mux.scala 27:72] + node _T_426 = or(_T_425, _T_423) @[Mux.scala 27:72] + wire _T_427 : UInt<39> @[Mux.scala 27:72] + _T_427 <= _T_426 @[Mux.scala 27:72] + node _T_428 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61] + node _T_429 = eq(_T_428, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 114:79] + node _T_430 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61] + node _T_431 = eq(_T_430, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 114:79] + node _T_432 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61] + node _T_433 = eq(_T_432, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 114:79] + node _T_434 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61] + node _T_435 = eq(_T_434, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 114:79] + node _T_436 = mux(_T_429, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_437 = mux(_T_431, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_438 = mux(_T_433, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_439 = mux(_T_435, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_440 = or(_T_436, _T_437) @[Mux.scala 27:72] + node _T_441 = or(_T_440, _T_438) @[Mux.scala 27:72] + node _T_442 = or(_T_441, _T_439) @[Mux.scala 27:72] + wire _T_443 : UInt<39> @[Mux.scala 27:72] + _T_443 <= _T_442 @[Mux.scala 27:72] + node _T_444 = cat(_T_427, _T_443) @[Cat.scala 29:58] + io.iccm_rd_data_ecc <= _T_444 @[el2_ifu_iccm_mem.scala 113:23] diff --git a/el2_ifu_iccm_mem.v b/el2_ifu_iccm_mem.v index 2913a3a3..6d7464bb 100644 --- a/el2_ifu_iccm_mem.v +++ b/el2_ifu_iccm_mem.v @@ -19,19 +19,19 @@ module el2_ifu_iccm_mem( ); `ifdef RANDOMIZE_MEM_INIT reg [63:0] _RAND_0; - reg [63:0] _RAND_3; + reg [63:0] _RAND_2; + reg [63:0] _RAND_4; reg [63:0] _RAND_6; - reg [63:0] _RAND_9; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_1; - reg [31:0] _RAND_2; - reg [31:0] _RAND_4; + reg [31:0] _RAND_3; reg [31:0] _RAND_5; reg [31:0] _RAND_7; - reg [31:0] _RAND_8; - reg [31:0] _RAND_10; - reg [31:0] _RAND_11; + reg [63:0] _RAND_8; + reg [63:0] _RAND_9; + reg [63:0] _RAND_10; + reg [63:0] _RAND_11; reg [31:0] _RAND_12; reg [31:0] _RAND_13; reg [31:0] _RAND_14; @@ -45,45 +45,41 @@ module el2_ifu_iccm_mem( reg [31:0] _RAND_22; `endif // RANDOMIZE_REG_INIT reg [38:0] _T_85 [0:4095]; // @[el2_ifu_iccm_mem.scala 43:59] - wire [38:0] _T_85__T_108_data; // @[el2_ifu_iccm_mem.scala 43:59] - wire [11:0] _T_85__T_108_addr; // @[el2_ifu_iccm_mem.scala 43:59] + wire [38:0] _T_85__T_105_data; // @[el2_ifu_iccm_mem.scala 43:59] + wire [11:0] _T_85__T_105_addr; // @[el2_ifu_iccm_mem.scala 43:59] wire [38:0] _T_85__T_101_data; // @[el2_ifu_iccm_mem.scala 43:59] wire [11:0] _T_85__T_101_addr; // @[el2_ifu_iccm_mem.scala 43:59] wire _T_85__T_101_mask; // @[el2_ifu_iccm_mem.scala 43:59] wire _T_85__T_101_en; // @[el2_ifu_iccm_mem.scala 43:59] - reg _T_85__T_108_en_pipe_0; - reg [11:0] _T_85__T_108_addr_pipe_0; + reg [11:0] _T_85__T_105_addr_pipe_0; reg [38:0] _T_86 [0:4095]; // @[el2_ifu_iccm_mem.scala 43:59] - wire [38:0] _T_86__T_112_data; // @[el2_ifu_iccm_mem.scala 43:59] - wire [11:0] _T_86__T_112_addr; // @[el2_ifu_iccm_mem.scala 43:59] + wire [38:0] _T_86__T_107_data; // @[el2_ifu_iccm_mem.scala 43:59] + wire [11:0] _T_86__T_107_addr; // @[el2_ifu_iccm_mem.scala 43:59] wire [38:0] _T_86__T_102_data; // @[el2_ifu_iccm_mem.scala 43:59] wire [11:0] _T_86__T_102_addr; // @[el2_ifu_iccm_mem.scala 43:59] wire _T_86__T_102_mask; // @[el2_ifu_iccm_mem.scala 43:59] wire _T_86__T_102_en; // @[el2_ifu_iccm_mem.scala 43:59] - reg _T_86__T_112_en_pipe_0; - reg [11:0] _T_86__T_112_addr_pipe_0; + reg [11:0] _T_86__T_107_addr_pipe_0; reg [38:0] _T_87 [0:4095]; // @[el2_ifu_iccm_mem.scala 43:59] - wire [38:0] _T_87__T_116_data; // @[el2_ifu_iccm_mem.scala 43:59] - wire [11:0] _T_87__T_116_addr; // @[el2_ifu_iccm_mem.scala 43:59] + wire [38:0] _T_87__T_109_data; // @[el2_ifu_iccm_mem.scala 43:59] + wire [11:0] _T_87__T_109_addr; // @[el2_ifu_iccm_mem.scala 43:59] wire [38:0] _T_87__T_103_data; // @[el2_ifu_iccm_mem.scala 43:59] wire [11:0] _T_87__T_103_addr; // @[el2_ifu_iccm_mem.scala 43:59] wire _T_87__T_103_mask; // @[el2_ifu_iccm_mem.scala 43:59] wire _T_87__T_103_en; // @[el2_ifu_iccm_mem.scala 43:59] - reg _T_87__T_116_en_pipe_0; - reg [11:0] _T_87__T_116_addr_pipe_0; + reg [11:0] _T_87__T_109_addr_pipe_0; reg [38:0] _T_88 [0:4095]; // @[el2_ifu_iccm_mem.scala 43:59] - wire [38:0] _T_88__T_120_data; // @[el2_ifu_iccm_mem.scala 43:59] - wire [11:0] _T_88__T_120_addr; // @[el2_ifu_iccm_mem.scala 43:59] + wire [38:0] _T_88__T_111_data; // @[el2_ifu_iccm_mem.scala 43:59] + wire [11:0] _T_88__T_111_addr; // @[el2_ifu_iccm_mem.scala 43:59] wire [38:0] _T_88__T_104_data; // @[el2_ifu_iccm_mem.scala 43:59] wire [11:0] _T_88__T_104_addr; // @[el2_ifu_iccm_mem.scala 43:59] wire _T_88__T_104_mask; // @[el2_ifu_iccm_mem.scala 43:59] wire _T_88__T_104_en; // @[el2_ifu_iccm_mem.scala 43:59] - reg _T_88__T_120_en_pipe_0; - reg [11:0] _T_88__T_120_addr_pipe_0; + reg [11:0] _T_88__T_111_addr_pipe_0; wire _T_1 = io_iccm_wr_size[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 24:43] wire [1:0] addr_inc = _T_1 ? 2'h2 : 2'h1; // @[el2_ifu_iccm_mem.scala 24:21] - wire [14:0] _GEN_43 = {{13'd0}, addr_inc}; // @[el2_ifu_iccm_mem.scala 25:54] - wire [14:0] addr_bank_inc = io_iccm_rw_addr + _GEN_43; // @[el2_ifu_iccm_mem.scala 25:54] + wire [14:0] _GEN_31 = {{13'd0}, addr_inc}; // @[el2_ifu_iccm_mem.scala 25:54] + wire [14:0] addr_bank_inc = io_iccm_rw_addr + _GEN_31; // @[el2_ifu_iccm_mem.scala 25:54] wire [38:0] iccm_bank_wr_data_0 = io_iccm_wr_data[38:0]; // @[el2_ifu_iccm_mem.scala 29:50] wire [38:0] iccm_bank_wr_data_1 = io_iccm_wr_data[77:39]; // @[el2_ifu_iccm_mem.scala 30:54] wire _T_10 = io_iccm_rw_addr[2:1] == 2'h0; // @[el2_ifu_iccm_mem.scala 33:100] @@ -123,188 +119,192 @@ module el2_ifu_iccm_mem( wire [11:0] _T_75 = _T_22 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 40:8] wire [11:0] _T_83 = _T_27 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 40:8] wire _T_93 = ~wren_bank_0; // @[el2_ifu_iccm_mem.scala 48:72] + wire read_enable_0 = iccm_clken_0 & _T_93; // @[el2_ifu_iccm_mem.scala 48:70] wire _T_95 = ~wren_bank_1; // @[el2_ifu_iccm_mem.scala 48:72] + wire read_enable_1 = iccm_clken_1 & _T_95; // @[el2_ifu_iccm_mem.scala 48:70] wire _T_97 = ~wren_bank_2; // @[el2_ifu_iccm_mem.scala 48:72] + wire read_enable_2 = iccm_clken_2 & _T_97; // @[el2_ifu_iccm_mem.scala 48:70] wire _T_99 = ~wren_bank_3; // @[el2_ifu_iccm_mem.scala 48:72] - reg _T_321; // @[Reg.scala 27:20] - reg _T_322; // @[Reg.scala 27:20] - wire [1:0] redundant_valid = {_T_321,_T_322}; // @[Cat.scala 29:58] + wire read_enable_3 = iccm_clken_3 & _T_99; // @[el2_ifu_iccm_mem.scala 48:70] + reg [38:0] iccm_bank_dout_0; // @[Reg.scala 27:20] + reg [38:0] iccm_bank_dout_1; // @[Reg.scala 27:20] + reg [38:0] iccm_bank_dout_2; // @[Reg.scala 27:20] + reg [38:0] iccm_bank_dout_3; // @[Reg.scala 27:20] + reg _T_313; // @[Reg.scala 27:20] + reg _T_314; // @[Reg.scala 27:20] + wire [1:0] redundant_valid = {_T_313,_T_314}; // @[Cat.scala 29:58] reg [13:0] redundant_address_1; // @[Reg.scala 27:20] - wire _T_124 = io_iccm_rw_addr[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 70:105] - wire _T_127 = _T_124 & _T_10; // @[el2_ifu_iccm_mem.scala 70:145] - wire _T_128 = redundant_valid[1] & _T_127; // @[el2_ifu_iccm_mem.scala 70:71] - wire _T_131 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 71:37] - wire _T_134 = _T_131 & _T_12; // @[el2_ifu_iccm_mem.scala 71:77] - wire _T_135 = _T_128 | _T_134; // @[el2_ifu_iccm_mem.scala 70:179] - wire _T_142 = _T_124 & _T_15; // @[el2_ifu_iccm_mem.scala 70:145] - wire _T_143 = redundant_valid[1] & _T_142; // @[el2_ifu_iccm_mem.scala 70:71] - wire _T_149 = _T_131 & _T_17; // @[el2_ifu_iccm_mem.scala 71:77] - wire _T_150 = _T_143 | _T_149; // @[el2_ifu_iccm_mem.scala 70:179] - wire _T_157 = _T_124 & _T_20; // @[el2_ifu_iccm_mem.scala 70:145] - wire _T_158 = redundant_valid[1] & _T_157; // @[el2_ifu_iccm_mem.scala 70:71] - wire _T_164 = _T_131 & _T_22; // @[el2_ifu_iccm_mem.scala 71:77] - wire _T_165 = _T_158 | _T_164; // @[el2_ifu_iccm_mem.scala 70:179] - wire _T_172 = _T_124 & _T_25; // @[el2_ifu_iccm_mem.scala 70:145] - wire _T_173 = redundant_valid[1] & _T_172; // @[el2_ifu_iccm_mem.scala 70:71] - wire _T_179 = _T_131 & _T_27; // @[el2_ifu_iccm_mem.scala 71:77] - wire _T_180 = _T_173 | _T_179; // @[el2_ifu_iccm_mem.scala 70:179] - wire [3:0] sel_red1 = {_T_180,_T_165,_T_150,_T_135}; // @[Cat.scala 29:58] + wire _T_116 = io_iccm_rw_addr[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 70:105] + wire _T_119 = _T_116 & _T_10; // @[el2_ifu_iccm_mem.scala 70:145] + wire _T_120 = redundant_valid[1] & _T_119; // @[el2_ifu_iccm_mem.scala 70:71] + wire _T_123 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 71:37] + wire _T_126 = _T_123 & _T_12; // @[el2_ifu_iccm_mem.scala 71:77] + wire _T_127 = _T_120 | _T_126; // @[el2_ifu_iccm_mem.scala 70:179] + wire _T_134 = _T_116 & _T_15; // @[el2_ifu_iccm_mem.scala 70:145] + wire _T_135 = redundant_valid[1] & _T_134; // @[el2_ifu_iccm_mem.scala 70:71] + wire _T_141 = _T_123 & _T_17; // @[el2_ifu_iccm_mem.scala 71:77] + wire _T_142 = _T_135 | _T_141; // @[el2_ifu_iccm_mem.scala 70:179] + wire _T_149 = _T_116 & _T_20; // @[el2_ifu_iccm_mem.scala 70:145] + wire _T_150 = redundant_valid[1] & _T_149; // @[el2_ifu_iccm_mem.scala 70:71] + wire _T_156 = _T_123 & _T_22; // @[el2_ifu_iccm_mem.scala 71:77] + wire _T_157 = _T_150 | _T_156; // @[el2_ifu_iccm_mem.scala 70:179] + wire _T_164 = _T_116 & _T_25; // @[el2_ifu_iccm_mem.scala 70:145] + wire _T_165 = redundant_valid[1] & _T_164; // @[el2_ifu_iccm_mem.scala 70:71] + wire _T_171 = _T_123 & _T_27; // @[el2_ifu_iccm_mem.scala 71:77] + wire _T_172 = _T_165 | _T_171; // @[el2_ifu_iccm_mem.scala 70:179] + wire [3:0] sel_red1 = {_T_172,_T_157,_T_142,_T_127}; // @[Cat.scala 29:58] reg [13:0] redundant_address_0; // @[Reg.scala 27:20] - wire _T_186 = io_iccm_rw_addr[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 72:105] - wire _T_189 = _T_186 & _T_10; // @[el2_ifu_iccm_mem.scala 72:145] - wire _T_190 = redundant_valid[0] & _T_189; // @[el2_ifu_iccm_mem.scala 72:71] - wire _T_193 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 73:37] - wire _T_196 = _T_193 & _T_12; // @[el2_ifu_iccm_mem.scala 73:77] - wire _T_197 = _T_190 | _T_196; // @[el2_ifu_iccm_mem.scala 72:179] - wire _T_204 = _T_186 & _T_15; // @[el2_ifu_iccm_mem.scala 72:145] - wire _T_205 = redundant_valid[0] & _T_204; // @[el2_ifu_iccm_mem.scala 72:71] - wire _T_211 = _T_193 & _T_17; // @[el2_ifu_iccm_mem.scala 73:77] - wire _T_212 = _T_205 | _T_211; // @[el2_ifu_iccm_mem.scala 72:179] - wire _T_219 = _T_186 & _T_20; // @[el2_ifu_iccm_mem.scala 72:145] - wire _T_220 = redundant_valid[0] & _T_219; // @[el2_ifu_iccm_mem.scala 72:71] - wire _T_226 = _T_193 & _T_22; // @[el2_ifu_iccm_mem.scala 73:77] - wire _T_227 = _T_220 | _T_226; // @[el2_ifu_iccm_mem.scala 72:179] - wire _T_234 = _T_186 & _T_25; // @[el2_ifu_iccm_mem.scala 72:145] - wire _T_235 = redundant_valid[0] & _T_234; // @[el2_ifu_iccm_mem.scala 72:71] - wire _T_241 = _T_193 & _T_27; // @[el2_ifu_iccm_mem.scala 73:77] - wire _T_242 = _T_235 | _T_241; // @[el2_ifu_iccm_mem.scala 72:179] - wire [3:0] sel_red0 = {_T_242,_T_227,_T_212,_T_197}; // @[Cat.scala 29:58] + wire _T_178 = io_iccm_rw_addr[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 72:105] + wire _T_181 = _T_178 & _T_10; // @[el2_ifu_iccm_mem.scala 72:145] + wire _T_182 = redundant_valid[0] & _T_181; // @[el2_ifu_iccm_mem.scala 72:71] + wire _T_185 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 73:37] + wire _T_188 = _T_185 & _T_12; // @[el2_ifu_iccm_mem.scala 73:77] + wire _T_189 = _T_182 | _T_188; // @[el2_ifu_iccm_mem.scala 72:179] + wire _T_196 = _T_178 & _T_15; // @[el2_ifu_iccm_mem.scala 72:145] + wire _T_197 = redundant_valid[0] & _T_196; // @[el2_ifu_iccm_mem.scala 72:71] + wire _T_203 = _T_185 & _T_17; // @[el2_ifu_iccm_mem.scala 73:77] + wire _T_204 = _T_197 | _T_203; // @[el2_ifu_iccm_mem.scala 72:179] + wire _T_211 = _T_178 & _T_20; // @[el2_ifu_iccm_mem.scala 72:145] + wire _T_212 = redundant_valid[0] & _T_211; // @[el2_ifu_iccm_mem.scala 72:71] + wire _T_218 = _T_185 & _T_22; // @[el2_ifu_iccm_mem.scala 73:77] + wire _T_219 = _T_212 | _T_218; // @[el2_ifu_iccm_mem.scala 72:179] + wire _T_226 = _T_178 & _T_25; // @[el2_ifu_iccm_mem.scala 72:145] + wire _T_227 = redundant_valid[0] & _T_226; // @[el2_ifu_iccm_mem.scala 72:71] + wire _T_233 = _T_185 & _T_27; // @[el2_ifu_iccm_mem.scala 73:77] + wire _T_234 = _T_227 | _T_233; // @[el2_ifu_iccm_mem.scala 72:179] + wire [3:0] sel_red0 = {_T_234,_T_219,_T_204,_T_189}; // @[Cat.scala 29:58] reg [3:0] sel_red0_q; // @[el2_ifu_iccm_mem.scala 75:27] reg [3:0] sel_red1_q; // @[el2_ifu_iccm_mem.scala 76:27] - wire _T_250 = ~sel_red0_q[0]; // @[el2_ifu_iccm_mem.scala 82:36] - wire _T_252 = ~sel_red1_q[0]; // @[el2_ifu_iccm_mem.scala 82:53] - wire _T_253 = _T_250 & _T_252; // @[el2_ifu_iccm_mem.scala 82:51] + wire _T_242 = ~sel_red0_q[0]; // @[el2_ifu_iccm_mem.scala 82:36] + wire _T_244 = ~sel_red1_q[0]; // @[el2_ifu_iccm_mem.scala 82:53] + wire _T_245 = _T_242 & _T_244; // @[el2_ifu_iccm_mem.scala 82:51] reg [38:0] redundant_data_1; // @[Reg.scala 27:20] - wire [38:0] _T_255 = sel_red1_q[0] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_247 = sel_red1_q[0] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] reg [38:0] redundant_data_0; // @[Reg.scala 27:20] - wire [38:0] _T_256 = sel_red0_q[0] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_0 = _T_85__T_108_data; // @[el2_ifu_iccm_mem.scala 50:28 el2_ifu_iccm_mem.scala 56:53] - wire [38:0] _T_257 = _T_253 ? iccm_bank_dout_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_258 = _T_255 | _T_256; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_fn_0 = _T_258 | _T_257; // @[Mux.scala 27:72] - wire _T_265 = ~sel_red0_q[1]; // @[el2_ifu_iccm_mem.scala 82:36] - wire _T_267 = ~sel_red1_q[1]; // @[el2_ifu_iccm_mem.scala 82:53] - wire _T_268 = _T_265 & _T_267; // @[el2_ifu_iccm_mem.scala 82:51] - wire [38:0] _T_270 = sel_red1_q[1] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_271 = sel_red0_q[1] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_1 = _T_86__T_112_data; // @[el2_ifu_iccm_mem.scala 50:28 el2_ifu_iccm_mem.scala 56:53] - wire [38:0] _T_272 = _T_268 ? iccm_bank_dout_1 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_273 = _T_270 | _T_271; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_fn_1 = _T_273 | _T_272; // @[Mux.scala 27:72] - wire _T_280 = ~sel_red0_q[2]; // @[el2_ifu_iccm_mem.scala 82:36] - wire _T_282 = ~sel_red1_q[2]; // @[el2_ifu_iccm_mem.scala 82:53] - wire _T_283 = _T_280 & _T_282; // @[el2_ifu_iccm_mem.scala 82:51] - wire [38:0] _T_285 = sel_red1_q[2] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_286 = sel_red0_q[2] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_2 = _T_87__T_116_data; // @[el2_ifu_iccm_mem.scala 50:28 el2_ifu_iccm_mem.scala 56:53] - wire [38:0] _T_287 = _T_283 ? iccm_bank_dout_2 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_288 = _T_285 | _T_286; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_fn_2 = _T_288 | _T_287; // @[Mux.scala 27:72] - wire _T_295 = ~sel_red0_q[3]; // @[el2_ifu_iccm_mem.scala 82:36] - wire _T_297 = ~sel_red1_q[3]; // @[el2_ifu_iccm_mem.scala 82:53] - wire _T_298 = _T_295 & _T_297; // @[el2_ifu_iccm_mem.scala 82:51] - wire [38:0] _T_300 = sel_red1_q[3] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_301 = sel_red0_q[3] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_3 = _T_88__T_120_data; // @[el2_ifu_iccm_mem.scala 50:28 el2_ifu_iccm_mem.scala 56:53] - wire [38:0] _T_302 = _T_298 ? iccm_bank_dout_3 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_303 = _T_300 | _T_301; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_fn_3 = _T_303 | _T_302; // @[Mux.scala 27:72] + wire [38:0] _T_248 = sel_red0_q[0] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_249 = _T_245 ? iccm_bank_dout_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_250 = _T_247 | _T_248; // @[Mux.scala 27:72] + wire [38:0] iccm_bank_dout_fn_0 = _T_250 | _T_249; // @[Mux.scala 27:72] + wire _T_257 = ~sel_red0_q[1]; // @[el2_ifu_iccm_mem.scala 82:36] + wire _T_259 = ~sel_red1_q[1]; // @[el2_ifu_iccm_mem.scala 82:53] + wire _T_260 = _T_257 & _T_259; // @[el2_ifu_iccm_mem.scala 82:51] + wire [38:0] _T_262 = sel_red1_q[1] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_263 = sel_red0_q[1] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_264 = _T_260 ? iccm_bank_dout_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_265 = _T_262 | _T_263; // @[Mux.scala 27:72] + wire [38:0] iccm_bank_dout_fn_1 = _T_265 | _T_264; // @[Mux.scala 27:72] + wire _T_272 = ~sel_red0_q[2]; // @[el2_ifu_iccm_mem.scala 82:36] + wire _T_274 = ~sel_red1_q[2]; // @[el2_ifu_iccm_mem.scala 82:53] + wire _T_275 = _T_272 & _T_274; // @[el2_ifu_iccm_mem.scala 82:51] + wire [38:0] _T_277 = sel_red1_q[2] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_278 = sel_red0_q[2] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_279 = _T_275 ? iccm_bank_dout_2 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_280 = _T_277 | _T_278; // @[Mux.scala 27:72] + wire [38:0] iccm_bank_dout_fn_2 = _T_280 | _T_279; // @[Mux.scala 27:72] + wire _T_287 = ~sel_red0_q[3]; // @[el2_ifu_iccm_mem.scala 82:36] + wire _T_289 = ~sel_red1_q[3]; // @[el2_ifu_iccm_mem.scala 82:53] + wire _T_290 = _T_287 & _T_289; // @[el2_ifu_iccm_mem.scala 82:51] + wire [38:0] _T_292 = sel_red1_q[3] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_293 = sel_red0_q[3] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_294 = _T_290 ? iccm_bank_dout_3 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_295 = _T_292 | _T_293; // @[Mux.scala 27:72] + wire [38:0] iccm_bank_dout_fn_3 = _T_295 | _T_294; // @[Mux.scala 27:72] reg redundant_lru; // @[Reg.scala 27:20] - wire _T_305 = ~redundant_lru; // @[el2_ifu_iccm_mem.scala 84:20] - wire r0_addr_en = _T_305 & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 84:35] + wire _T_297 = ~redundant_lru; // @[el2_ifu_iccm_mem.scala 84:20] + wire r0_addr_en = _T_297 & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 84:35] wire r1_addr_en = redundant_lru & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 85:35] - wire _T_306 = |sel_red0; // @[el2_ifu_iccm_mem.scala 86:63] - wire _T_307 = |sel_red1; // @[el2_ifu_iccm_mem.scala 86:78] - wire _T_308 = _T_306 | _T_307; // @[el2_ifu_iccm_mem.scala 86:67] - wire _T_309 = _T_308 & io_iccm_rden; // @[el2_ifu_iccm_mem.scala 86:83] - wire _T_310 = _T_309 & io_iccm_correction_state; // @[el2_ifu_iccm_mem.scala 86:98] - wire redundant_lru_en = io_iccm_buf_correct_ecc | _T_310; // @[el2_ifu_iccm_mem.scala 86:50] - wire _GEN_39 = r1_addr_en | _T_321; // @[Reg.scala 28:19] - wire _GEN_40 = r0_addr_en | _T_322; // @[Reg.scala 28:19] - wire _T_326 = io_iccm_rw_addr[14:2] == redundant_address_0[13:1]; // @[el2_ifu_iccm_mem.scala 93:61] - wire _T_329 = io_iccm_rw_addr[1] & redundant_address_0[0]; // @[el2_ifu_iccm_mem.scala 94:26] - wire _T_332 = _T_329 | _T_1; // @[el2_ifu_iccm_mem.scala 94:52] - wire _T_333 = _T_326 & _T_332; // @[el2_ifu_iccm_mem.scala 93:102] - wire _T_335 = _T_333 & redundant_valid[0]; // @[el2_ifu_iccm_mem.scala 94:84] - wire _T_336 = _T_335 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 94:105] - wire redundant_data0_en = _T_336 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 94:121] - wire _T_345 = redundant_address_0[0] & _T_1; // @[el2_ifu_iccm_mem.scala 96:104] - wire _T_346 = _T_329 | _T_345; // @[el2_ifu_iccm_mem.scala 96:78] - wire _T_354 = io_iccm_rw_addr[14:2] == redundant_address_1[13:1]; // @[el2_ifu_iccm_mem.scala 100:61] - wire _T_357 = io_iccm_rw_addr[1] & redundant_address_1[0]; // @[el2_ifu_iccm_mem.scala 101:26] - wire _T_360 = _T_357 | _T_1; // @[el2_ifu_iccm_mem.scala 101:52] - wire _T_361 = _T_354 & _T_360; // @[el2_ifu_iccm_mem.scala 100:102] - wire _T_363 = _T_361 & redundant_valid[1]; // @[el2_ifu_iccm_mem.scala 101:84] - wire _T_364 = _T_363 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 101:105] - wire redundant_data1_en = _T_364 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 101:121] - wire _T_373 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 103:104] - wire _T_374 = _T_357 | _T_373; // @[el2_ifu_iccm_mem.scala 103:78] + wire _T_298 = |sel_red0; // @[el2_ifu_iccm_mem.scala 86:63] + wire _T_299 = |sel_red1; // @[el2_ifu_iccm_mem.scala 86:78] + wire _T_300 = _T_298 | _T_299; // @[el2_ifu_iccm_mem.scala 86:67] + wire _T_301 = _T_300 & io_iccm_rden; // @[el2_ifu_iccm_mem.scala 86:83] + wire _T_302 = _T_301 & io_iccm_correction_state; // @[el2_ifu_iccm_mem.scala 86:98] + wire redundant_lru_en = io_iccm_buf_correct_ecc | _T_302; // @[el2_ifu_iccm_mem.scala 86:50] + wire _GEN_27 = r1_addr_en | _T_313; // @[Reg.scala 28:19] + wire _GEN_28 = r0_addr_en | _T_314; // @[Reg.scala 28:19] + wire _T_318 = io_iccm_rw_addr[14:2] == redundant_address_0[13:1]; // @[el2_ifu_iccm_mem.scala 93:61] + wire _T_321 = io_iccm_rw_addr[1] & redundant_address_0[0]; // @[el2_ifu_iccm_mem.scala 94:26] + wire _T_324 = _T_321 | _T_1; // @[el2_ifu_iccm_mem.scala 94:52] + wire _T_325 = _T_318 & _T_324; // @[el2_ifu_iccm_mem.scala 93:102] + wire _T_327 = _T_325 & redundant_valid[0]; // @[el2_ifu_iccm_mem.scala 94:84] + wire _T_328 = _T_327 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 94:105] + wire redundant_data0_en = _T_328 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 94:121] + wire _T_337 = redundant_address_0[0] & _T_1; // @[el2_ifu_iccm_mem.scala 96:104] + wire _T_338 = _T_321 | _T_337; // @[el2_ifu_iccm_mem.scala 96:78] + wire _T_346 = io_iccm_rw_addr[14:2] == redundant_address_1[13:1]; // @[el2_ifu_iccm_mem.scala 100:61] + wire _T_349 = io_iccm_rw_addr[1] & redundant_address_1[0]; // @[el2_ifu_iccm_mem.scala 101:26] + wire _T_352 = _T_349 | _T_1; // @[el2_ifu_iccm_mem.scala 101:52] + wire _T_353 = _T_346 & _T_352; // @[el2_ifu_iccm_mem.scala 100:102] + wire _T_355 = _T_353 & redundant_valid[1]; // @[el2_ifu_iccm_mem.scala 101:84] + wire _T_356 = _T_355 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 101:105] + wire redundant_data1_en = _T_356 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 101:121] + wire _T_365 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 103:104] + wire _T_366 = _T_349 | _T_365; // @[el2_ifu_iccm_mem.scala 103:78] reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 107:34] reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 108:34] - wire _T_382 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 110:86] - wire _T_384 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 110:86] - wire _T_386 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 110:86] - wire _T_388 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 110:86] - wire [31:0] _T_390 = _T_382 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_391 = _T_384 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_392 = _T_386 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_393 = _T_388 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_394 = _T_390 | _T_391; // @[Mux.scala 27:72] - wire [31:0] _T_395 = _T_394 | _T_392; // @[Mux.scala 27:72] - wire [31:0] _T_396 = _T_395 | _T_393; // @[Mux.scala 27:72] - wire _T_399 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 111:77] - wire _T_402 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 111:77] - wire _T_405 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 111:77] - wire _T_408 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 111:77] - wire [31:0] _T_410 = _T_399 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_411 = _T_402 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_412 = _T_405 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_413 = _T_408 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_414 = _T_410 | _T_411; // @[Mux.scala 27:72] - wire [31:0] _T_415 = _T_414 | _T_412; // @[Mux.scala 27:72] - wire [31:0] _T_416 = _T_415 | _T_413; // @[Mux.scala 27:72] - wire [63:0] iccm_rd_data_pre = {_T_396,_T_416}; // @[Cat.scala 29:58] - wire [63:0] _T_422 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58] - wire [38:0] _T_428 = _T_382 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_429 = _T_384 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_430 = _T_386 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_431 = _T_388 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_432 = _T_428 | _T_429; // @[Mux.scala 27:72] - wire [38:0] _T_433 = _T_432 | _T_430; // @[Mux.scala 27:72] - wire [38:0] _T_434 = _T_433 | _T_431; // @[Mux.scala 27:72] - wire [38:0] _T_444 = _T_399 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_445 = _T_402 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_446 = _T_405 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_447 = _T_408 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_448 = _T_444 | _T_445; // @[Mux.scala 27:72] - wire [38:0] _T_449 = _T_448 | _T_446; // @[Mux.scala 27:72] - wire [38:0] _T_450 = _T_449 | _T_447; // @[Mux.scala 27:72] - assign _T_85__T_108_addr = _T_85__T_108_addr_pipe_0; - assign _T_85__T_108_data = _T_85[_T_85__T_108_addr]; // @[el2_ifu_iccm_mem.scala 43:59] + wire _T_374 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 110:86] + wire _T_376 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 110:86] + wire _T_378 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 110:86] + wire _T_380 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 110:86] + wire [31:0] _T_382 = _T_374 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_383 = _T_376 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_384 = _T_378 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_385 = _T_380 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_386 = _T_382 | _T_383; // @[Mux.scala 27:72] + wire [31:0] _T_387 = _T_386 | _T_384; // @[Mux.scala 27:72] + wire [31:0] _T_388 = _T_387 | _T_385; // @[Mux.scala 27:72] + wire _T_391 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 111:77] + wire _T_394 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 111:77] + wire _T_397 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 111:77] + wire _T_400 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 111:77] + wire [31:0] _T_402 = _T_391 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_403 = _T_394 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_404 = _T_397 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_405 = _T_400 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_406 = _T_402 | _T_403; // @[Mux.scala 27:72] + wire [31:0] _T_407 = _T_406 | _T_404; // @[Mux.scala 27:72] + wire [31:0] _T_408 = _T_407 | _T_405; // @[Mux.scala 27:72] + wire [63:0] iccm_rd_data_pre = {_T_388,_T_408}; // @[Cat.scala 29:58] + wire [63:0] _T_414 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58] + wire [38:0] _T_420 = _T_374 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_421 = _T_376 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_422 = _T_378 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_423 = _T_380 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_424 = _T_420 | _T_421; // @[Mux.scala 27:72] + wire [38:0] _T_425 = _T_424 | _T_422; // @[Mux.scala 27:72] + wire [38:0] _T_426 = _T_425 | _T_423; // @[Mux.scala 27:72] + wire [38:0] _T_436 = _T_391 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_437 = _T_394 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_438 = _T_397 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_439 = _T_400 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_440 = _T_436 | _T_437; // @[Mux.scala 27:72] + wire [38:0] _T_441 = _T_440 | _T_438; // @[Mux.scala 27:72] + wire [38:0] _T_442 = _T_441 | _T_439; // @[Mux.scala 27:72] + assign _T_85__T_105_addr = _T_85__T_105_addr_pipe_0; + assign _T_85__T_105_data = _T_85[_T_85__T_105_addr]; // @[el2_ifu_iccm_mem.scala 43:59] assign _T_85__T_101_data = io_iccm_wr_data[38:0]; assign _T_85__T_101_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; assign _T_85__T_101_mask = 1'h1; assign _T_85__T_101_en = iccm_clken_0 & wren_bank_0; - assign _T_86__T_112_addr = _T_86__T_112_addr_pipe_0; - assign _T_86__T_112_data = _T_86[_T_86__T_112_addr]; // @[el2_ifu_iccm_mem.scala 43:59] + assign _T_86__T_107_addr = _T_86__T_107_addr_pipe_0; + assign _T_86__T_107_data = _T_86[_T_86__T_107_addr]; // @[el2_ifu_iccm_mem.scala 43:59] assign _T_86__T_102_data = io_iccm_wr_data[77:39]; assign _T_86__T_102_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_67; assign _T_86__T_102_mask = 1'h1; assign _T_86__T_102_en = iccm_clken_1 & wren_bank_1; - assign _T_87__T_116_addr = _T_87__T_116_addr_pipe_0; - assign _T_87__T_116_data = _T_87[_T_87__T_116_addr]; // @[el2_ifu_iccm_mem.scala 43:59] + assign _T_87__T_109_addr = _T_87__T_109_addr_pipe_0; + assign _T_87__T_109_data = _T_87[_T_87__T_109_addr]; // @[el2_ifu_iccm_mem.scala 43:59] assign _T_87__T_103_data = io_iccm_wr_data[38:0]; assign _T_87__T_103_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_75; assign _T_87__T_103_mask = 1'h1; assign _T_87__T_103_en = iccm_clken_2 & wren_bank_2; - assign _T_88__T_120_addr = _T_88__T_120_addr_pipe_0; - assign _T_88__T_120_data = _T_88[_T_88__T_120_addr]; // @[el2_ifu_iccm_mem.scala 43:59] + assign _T_88__T_111_addr = _T_88__T_111_addr_pipe_0; + assign _T_88__T_111_data = _T_88[_T_88__T_111_addr]; // @[el2_ifu_iccm_mem.scala 43:59] assign _T_88__T_104_data = io_iccm_wr_data[77:39]; assign _T_88__T_104_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_83; assign _T_88__T_104_mask = 1'h1; assign _T_88__T_104_en = iccm_clken_3 & wren_bank_3; - assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_422 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 112:19] - assign io_iccm_rd_data_ecc = {_T_434,_T_450}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 113:23] + assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_414 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 112:19] + assign io_iccm_rd_data_ecc = {_T_426,_T_442}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 113:23] assign io_iccm_bank_addr_0 = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; // @[el2_ifu_iccm_mem.scala 61:21] assign io_iccm_bank_addr_1 = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_67; // @[el2_ifu_iccm_mem.scala 61:21] assign io_iccm_bank_addr_2 = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_75; // @[el2_ifu_iccm_mem.scala 61:21] @@ -347,37 +347,37 @@ initial begin _RAND_0 = {2{`RANDOM}}; for (initvar = 0; initvar < 4096; initvar = initvar+1) _T_85[initvar] = _RAND_0[38:0]; - _RAND_3 = {2{`RANDOM}}; + _RAND_2 = {2{`RANDOM}}; for (initvar = 0; initvar < 4096; initvar = initvar+1) - _T_86[initvar] = _RAND_3[38:0]; + _T_86[initvar] = _RAND_2[38:0]; + _RAND_4 = {2{`RANDOM}}; + for (initvar = 0; initvar < 4096; initvar = initvar+1) + _T_87[initvar] = _RAND_4[38:0]; _RAND_6 = {2{`RANDOM}}; for (initvar = 0; initvar < 4096; initvar = initvar+1) - _T_87[initvar] = _RAND_6[38:0]; - _RAND_9 = {2{`RANDOM}}; - for (initvar = 0; initvar < 4096; initvar = initvar+1) - _T_88[initvar] = _RAND_9[38:0]; + _T_88[initvar] = _RAND_6[38:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT _RAND_1 = {1{`RANDOM}}; - _T_85__T_108_en_pipe_0 = _RAND_1[0:0]; - _RAND_2 = {1{`RANDOM}}; - _T_85__T_108_addr_pipe_0 = _RAND_2[11:0]; - _RAND_4 = {1{`RANDOM}}; - _T_86__T_112_en_pipe_0 = _RAND_4[0:0]; + _T_85__T_105_addr_pipe_0 = _RAND_1[11:0]; + _RAND_3 = {1{`RANDOM}}; + _T_86__T_107_addr_pipe_0 = _RAND_3[11:0]; _RAND_5 = {1{`RANDOM}}; - _T_86__T_112_addr_pipe_0 = _RAND_5[11:0]; + _T_87__T_109_addr_pipe_0 = _RAND_5[11:0]; _RAND_7 = {1{`RANDOM}}; - _T_87__T_116_en_pipe_0 = _RAND_7[0:0]; - _RAND_8 = {1{`RANDOM}}; - _T_87__T_116_addr_pipe_0 = _RAND_8[11:0]; - _RAND_10 = {1{`RANDOM}}; - _T_88__T_120_en_pipe_0 = _RAND_10[0:0]; - _RAND_11 = {1{`RANDOM}}; - _T_88__T_120_addr_pipe_0 = _RAND_11[11:0]; + _T_88__T_111_addr_pipe_0 = _RAND_7[11:0]; + _RAND_8 = {2{`RANDOM}}; + iccm_bank_dout_0 = _RAND_8[38:0]; + _RAND_9 = {2{`RANDOM}}; + iccm_bank_dout_1 = _RAND_9[38:0]; + _RAND_10 = {2{`RANDOM}}; + iccm_bank_dout_2 = _RAND_10[38:0]; + _RAND_11 = {2{`RANDOM}}; + iccm_bank_dout_3 = _RAND_11[38:0]; _RAND_12 = {1{`RANDOM}}; - _T_321 = _RAND_12[0:0]; + _T_313 = _RAND_12[0:0]; _RAND_13 = {1{`RANDOM}}; - _T_322 = _RAND_13[0:0]; + _T_314 = _RAND_13[0:0]; _RAND_14 = {1{`RANDOM}}; redundant_address_1 = _RAND_14[13:0]; _RAND_15 = {1{`RANDOM}}; @@ -407,64 +407,72 @@ end // initial if(_T_85__T_101_en & _T_85__T_101_mask) begin _T_85[_T_85__T_101_addr] <= _T_85__T_101_data; // @[el2_ifu_iccm_mem.scala 43:59] end - _T_85__T_108_en_pipe_0 <= iccm_clken_0 & _T_93; - if (iccm_clken_0 & _T_93) begin - if (wren_bank_0) begin - _T_85__T_108_addr_pipe_0 <= io_iccm_rw_addr[14:3]; - end else if (_T_12) begin - _T_85__T_108_addr_pipe_0 <= addr_bank_inc[14:3]; - end else begin - _T_85__T_108_addr_pipe_0 <= io_iccm_rw_addr[14:3]; - end + if (wren_bank_0) begin + _T_85__T_105_addr_pipe_0 <= io_iccm_rw_addr[14:3]; + end else if (_T_12) begin + _T_85__T_105_addr_pipe_0 <= addr_bank_inc[14:3]; + end else begin + _T_85__T_105_addr_pipe_0 <= io_iccm_rw_addr[14:3]; end if(_T_86__T_102_en & _T_86__T_102_mask) begin _T_86[_T_86__T_102_addr] <= _T_86__T_102_data; // @[el2_ifu_iccm_mem.scala 43:59] end - _T_86__T_112_en_pipe_0 <= iccm_clken_1 & _T_95; - if (iccm_clken_1 & _T_95) begin - if (wren_bank_1) begin - _T_86__T_112_addr_pipe_0 <= io_iccm_rw_addr[14:3]; - end else if (_T_17) begin - _T_86__T_112_addr_pipe_0 <= addr_bank_inc[14:3]; - end else begin - _T_86__T_112_addr_pipe_0 <= io_iccm_rw_addr[14:3]; - end + if (wren_bank_1) begin + _T_86__T_107_addr_pipe_0 <= io_iccm_rw_addr[14:3]; + end else if (_T_17) begin + _T_86__T_107_addr_pipe_0 <= addr_bank_inc[14:3]; + end else begin + _T_86__T_107_addr_pipe_0 <= io_iccm_rw_addr[14:3]; end if(_T_87__T_103_en & _T_87__T_103_mask) begin _T_87[_T_87__T_103_addr] <= _T_87__T_103_data; // @[el2_ifu_iccm_mem.scala 43:59] end - _T_87__T_116_en_pipe_0 <= iccm_clken_2 & _T_97; - if (iccm_clken_2 & _T_97) begin - if (wren_bank_2) begin - _T_87__T_116_addr_pipe_0 <= io_iccm_rw_addr[14:3]; - end else if (_T_22) begin - _T_87__T_116_addr_pipe_0 <= addr_bank_inc[14:3]; - end else begin - _T_87__T_116_addr_pipe_0 <= io_iccm_rw_addr[14:3]; - end + if (wren_bank_2) begin + _T_87__T_109_addr_pipe_0 <= io_iccm_rw_addr[14:3]; + end else if (_T_22) begin + _T_87__T_109_addr_pipe_0 <= addr_bank_inc[14:3]; + end else begin + _T_87__T_109_addr_pipe_0 <= io_iccm_rw_addr[14:3]; end if(_T_88__T_104_en & _T_88__T_104_mask) begin _T_88[_T_88__T_104_addr] <= _T_88__T_104_data; // @[el2_ifu_iccm_mem.scala 43:59] end - _T_88__T_120_en_pipe_0 <= iccm_clken_3 & _T_99; - if (iccm_clken_3 & _T_99) begin - if (wren_bank_3) begin - _T_88__T_120_addr_pipe_0 <= io_iccm_rw_addr[14:3]; - end else if (_T_27) begin - _T_88__T_120_addr_pipe_0 <= addr_bank_inc[14:3]; - end else begin - _T_88__T_120_addr_pipe_0 <= io_iccm_rw_addr[14:3]; - end + if (wren_bank_3) begin + _T_88__T_111_addr_pipe_0 <= io_iccm_rw_addr[14:3]; + end else if (_T_27) begin + _T_88__T_111_addr_pipe_0 <= addr_bank_inc[14:3]; + end else begin + _T_88__T_111_addr_pipe_0 <= io_iccm_rw_addr[14:3]; end if (reset) begin - _T_321 <= 1'h0; - end else begin - _T_321 <= _GEN_39; + iccm_bank_dout_0 <= 39'h0; + end else if (read_enable_0) begin + iccm_bank_dout_0 <= _T_85__T_105_data; end if (reset) begin - _T_322 <= 1'h0; + iccm_bank_dout_1 <= 39'h0; + end else if (read_enable_1) begin + iccm_bank_dout_1 <= _T_86__T_107_data; + end + if (reset) begin + iccm_bank_dout_2 <= 39'h0; + end else if (read_enable_2) begin + iccm_bank_dout_2 <= _T_87__T_109_data; + end + if (reset) begin + iccm_bank_dout_3 <= 39'h0; + end else if (read_enable_3) begin + iccm_bank_dout_3 <= _T_88__T_111_data; + end + if (reset) begin + _T_313 <= 1'h0; end else begin - _T_322 <= _GEN_40; + _T_313 <= _GEN_27; + end + if (reset) begin + _T_314 <= 1'h0; + end else begin + _T_314 <= _GEN_28; end if (reset) begin redundant_address_1 <= 14'h0; @@ -489,7 +497,7 @@ end // initial if (reset) begin redundant_data_1 <= 39'h0; end else if (redundant_data1_en) begin - if (_T_374) begin + if (_T_366) begin redundant_data_1 <= iccm_bank_wr_data_1; end else begin redundant_data_1 <= iccm_bank_wr_data_0; @@ -498,7 +506,7 @@ end // initial if (reset) begin redundant_data_0 <= 39'h0; end else if (redundant_data0_en) begin - if (_T_346) begin + if (_T_338) begin redundant_data_0 <= iccm_bank_wr_data_1; end else begin redundant_data_0 <= iccm_bank_wr_data_0; @@ -508,9 +516,9 @@ end // initial redundant_lru <= 1'h0; end else if (redundant_lru_en) begin if (io_iccm_buf_correct_ecc) begin - redundant_lru <= _T_305; + redundant_lru <= _T_297; end else begin - redundant_lru <= _T_306; + redundant_lru <= _T_298; end end if (reset) begin diff --git a/src/main/scala/ifu/el2_ifu_iccm_mem.scala b/src/main/scala/ifu/el2_ifu_iccm_mem.scala index f55f4fe7..a7a6e7b7 100644 --- a/src/main/scala/ifu/el2_ifu_iccm_mem.scala +++ b/src/main/scala/ifu/el2_ifu_iccm_mem.scala @@ -53,7 +53,7 @@ class el2_ifu_iccm_mem extends Module with el2_lib { for(i<-0 until ICCM_NUM_BANKS) when(write_vec(i)) {iccm_mem(i)(addr_bank(i)) := iccm_bank_wr_data(i)} - for(i<-0 until ICCM_NUM_BANKS) {iccm_bank_dout(i) := iccm_mem(i).read(addr_bank(i),read_enable(i))} + for(i<-0 until ICCM_NUM_BANKS) {iccm_bank_dout(i) := RegEnable(iccm_mem(i)(addr_bank(i)),0.U,read_enable(i))} //(0 until ICCM_NUM_BANKS).map(i=> ) // iccm_bank_dout(i) := RegNext(inter(i)) diff --git a/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem.class b/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem.class index 0ec4520a4c2c2b0619a314723df39ecb38af9412..356896ae7e8ea0827f6aa52f4d2894cd8a140832 100644 GIT binary patch literal 93706 zcmd2^2YejG)t|lF-P4^`)=6?ZS7gggu9Dmh1{GVDEmyfWS(eVSY!zFQ8wk@Op?5+H z9YW{^ixzt5kWfPpA%%og2ni(w`2KHZcW?J@?!5SbeEwNe-oE$d&6_uGW_D)hp84v& z2N`1%1HVyN&!$Z~#z&irYZ2Er)z`PwwnSS3Oi|dt`pr!p(dLrzO|6~L_SU-Q@zv4B zy81oy+ZuK>M+3~Su*~MBjhq;9fN2Wr9nWc8M}1v$ox%oH^Thb}=%(gqedqWZ0@pM( zw$^p-XphcNn6`0GXS72JU9T(Jq(;RzbheUTzBs?HqWSieZ_ke?<-R;EKg+K+DvDlJ z7tw%WLi#+rsVtbN;7=rrMXHlP?b}9XfRvrD6U`}j#;dvfxFO+jU&67o;W*jQFNhxjUkwUB?PpSO>He5o>| zZW!^+$x#6xZNbX{A0gm9QQsK?PVKq9r`?{5MSD&`duHj>p6iB`<}B_NtKUeUs9%mY zOy~8OMD-X=eCv9k9^+#5*pq43V=S*n{s7dYk=LUQ^%!Nu>ao_WN6_CP#PnNi>vwKUu2orFuAa)!ep5;gA3kwK+sa7| zm6N-ck6S$@(;vw!%I`mMXF!R7c-YGP;Nn^HRA2Sb={coamIi$N3v=qWEKve`s=9Xd z7<5R;Uz)kSE;4CLWABD3BmBOa5&AS`{Ho&S@`D z%TbzF1biih!Td3$zLuI$b-uE4tUtR~!-&SdQ?|^~i%LiKpSq>#$RW9PeS`i|UsF#0 z62)ILb4+esB;>CeG_f>)wNI%G)s@a!SJGHBeawn+{ig0XT8reg4nWt;uU;{vv@oQN z8Zf-nH)Q9!+=dldJVkk)R0y>V7THN zvaPnbVteVp66*hp$CYYZDtk2VY92Iw)4CzkO0)Zs-8J>eFX#Fip1r!HEoWfSocUzu z>x|MNYl<7z?9JQVwz4Q%HFr#|GC1g8ys0|Bw6@S6TsAM-19rS8w{Y9euXl~c+ zv5^@Ysb49)+-ZH4SyuffM9Y^LyT+_8Zou=P&yuTrdPDj2uH~%*N;c&T3yu=-;Itu1 z1~0FARZ-iDy_uC+{igTUw5a0uP4W$>t1imV&seHu6)kUBr3A}!3r4{1+A8&`oUDE& z9fuF^oRU?g^x*Km#T(a+>*~E=ZLx2lR!}*A-Gut`>1%h5=|8ohR2!Ac>l-o}Th~n3 z9o;*$PuBXP4K2L~^eGkk8a_5MwVCu`tS;J7zPDs$OC-max31^P`D;0!73HO+ee-(- zg9UZrw*J9jq{8p_P1e@sqFr0pEHCIgKQd)gubg02L0z`5S5{YLkF_NYO~bny7x;a? zncAqLwpB$f<-_xHa;i%EX``y5u%kWmatACQyH3e$n>(hlmCLW@<(qnR$)o4U8DR=IoVwo zuYajlD(qr1`iJiGtu8IfDXK0V?=RnypI?_93Tj8^6=nEzKl;Jg!9i`Yo~2GG_xU!> z&nw!v?69`Vxug4Jtsb#y4cdq68+>|HDWSHx)s^E{PuMlD$Cx4c`2%u-`NpcUwN!5l zuIAPGr*A6H?OHy6ZBhNI-bQKJx{{4mdq+2pixjua^M&fne$r?D+Q}QLW{#ONzSLsxN@4W&-^i!t$iWi>?3<; zS1H+!@_GMq*QaD-lOAUuxm_!=*H36%w>&2&r)N<2*9Z5gwMt%1j{z%$J$21)SvzCL z;r%)T!%72?d(7q@tBcy2_STOWzusNmf_2c}sGN*Ot`BMl#fX+2$@Oq}Z_vZO>W}9A zbHlvpMp4s zv32jfM%azBJ-9yVj)pyyh8*?a{kTZTCxH*|>{I7#|6KUNNMu6|7IsZo{gXUDWQmqP?a^57)WhYO2|r*|#+2Pd8TO!Y{3vw4vS?Qih80Vopn6 zvWG5x;kpvvP@AvtYjtzS1TfVtwx-9kc5iELs&DEnZ)@4s)Er&7t+T1EwWGkDEpM*t z=m@Y(%!E_Z1z48C@+8Cx>t#`HtE=By*BC7*YinyR2(Ylivf~~FST3g2{JDf~SygK% z=z0N#C$S2Mqc2z5X$+M$V&3Jcm{vu zVbi84kVY#k(7uyr6xLTPcowxs8={*EO55Apc9nK?w2@lJDa>#_4X_DVOF2*!=4)z$ zI;$j+tgYQt=Uhh5%DaGKigQ>x>X?b;>$Un-_>5*P}f;kyE6*H zESnH*3%Y^M{GoP+bDfFj!Cmdq)>`7Duo31uuD-3A)^V`(@l7o)J38w&Hb=)-wKha| zM;mIQ+d(zO8)mFLvep??UQUACr2Gb3h7f;_rir%Vfn8}Rhd;pj6${Zdc0FqLwAL?) z)-}wJwt)F?>4TUQ&RWB=g~pO-$d)*>9sFyft)vAsOiccUwjG`5ov;BkU|nlx?asR9 zrUq0o1|j*Q9UYJ!i|ty#i(*NbMaYCssNEjR6j7!}j0d%?OK((e?Ix(_8@Ga8|Ew7M z=Jp*ZyM00}*EMN9W_w%*^t34UH0&aUUSP^@P!mA8F%Zc=f#W3rC74Ar%p%ylrGoYb zAxm=`=}DNA1>4+2urO~Tz<96N){a)oswiDrT04K%{MzcO1+%D%qKhuwv8_2e5tg&k z1vs=i=2jMN+=9L^L@wD)FEeh*X?RGe(Ujk{C>2NH} zUU8V*8v!q~Y|hf!(u#^DwR2EHELXh{^szZPkK` zSu42^CK?A6@j7raGfxG@^2Kq_i)-D_OX8lF@aGv+tdO8b*|MtYirUgSWiW=NsB6ds ztgM;{egmeyco5&)jg z7U@+>XVtE#s-PYwAiNDsh+r_Qyxc;`l0%+OlP{Er$>i`I_1)bXdd6ki}CO9Ji(xT^g=x zc4^I0blj!0mMmGeXld<|Srt`FW|gByWL1@ymd}}0TTDuVY+*C+&{+>Bh#Zv*K)pD} ziD7Ea$*87wMJZ&;v(RRhI^3R(NKm0Miyzmk>HT_|#2hBn>nz&Y1R)a@%@(Vm)nvKm zLwBQ@K*5*lXqb@d1+_JBvzCy&6(J}zm2F}W2-Tx@H6aTZRHL>QNlp2JirQ-EKZYP2 znk7li($b~yRHEt@6?tN_=9bzB6sx$^a0DeqSd9Wv7L}II;{dnqqe>QlYKY>kY>aDA z0D1pFb%0>$P2@xkdFAm;(3w`wu^m<}SP5MSV%y?5s<3!vF05YUxz&fNW-o({n>KA_ zOq;f{+@^D?7Qm+Ce0e;Kd`~=#d`~>AL;@q<6OTu}Cmu$=Cmu$=+zE^M@sHIOAxU9+qho(_`%q+)hsWlX!VvfOTZP>$?$K^bwxI@=Af zJw1VIFews)13q6+1!lZ90dc8SS3X<4nAIdb- zLKPu1Cp59NYW}PxwbipK!G9KpB24r*HH$TSfry~vu_GOGX#UD%#wZ8G+B_8anAG}r z7l5kgNGFmx84oKu-dcz$eEW{p&Zd^=_?pi49rf66tZOc>Yi_Q=@-Cocz$a{MYwPUj zY_HpKqbQ){CW;v!tSXInJ&L#OyAsU_eHLkTIFAtk67*}8&PLt5Ro zZOwZWR)9($sCFRER>HZADLHtNv#F`I!BFxPmALg(SpPV3+L2wdqjf1XRS-~m!{X;J ztXNh(tAO4Rq`*ZfeU(U1>7(?+SjHDt=Ie$GWdO#8ZFTK+Em6EAB1LrY=33)uRME_a zGDsOrf*k^fA6r?8*JjEPG*V-T+pJ5sdk`e;gk&6I%ivURp0ovY0fV@S3q=W$N?IJ+lB0y3? z5VHmGPA5Y__j9oThQ$I&2@5o{`?XNCzCJ@~iem#Tiw%+zHe?u<6YOX@5>1WwQZ7k= zVX;6`!U87XB0%0EKvF^gD{#DYq_=b#%FZ|@z_FMhDPaQR=*b1&xMNdoeOr4w-f7ix z9UK+M3YZovsYMmXSrp|>0!k*9T^wgol(z_^7F8T)QIxj`q!v{Svk~vZ&6?rOb!|sy zT_@V-hwkbTs>MrcY{jr2XZujzB9NL^F)YPJ5HlirB+&=#!bK1>nPREQ6vvqiq< zCQ}R>aFq}<4|*gK2`%j+h#5h#)CfxAjDYf{NR&)0p(M@-C~px+ji4mX2qO z{YLy@dq^V!Oy(Sq`b5mJVgEEIo)E>3b{CtHjiG#?{F#LK3&x~)UbUOrnj6f6v`*nTyueWYE=d335QFc^ zi3;Re>}(iF{wYX4c2v1>bGun(ScA36%+1H0OHhDL<A1oX)SPY?xX{l6^lD(mP zuKb4-^99XncSd(&%NMK1rp`TB>(pcSIl#B;sQ93O^G(0JMAQPq$2cpWf?B(tH_~=w zPCN(%Dp!+F1M~Ks8{475C~By;ZQ9fk?ZkT%8wlK>U>?F;uYG4bP9a212@e@LH=#p` zwKKQCVsw+42SADKMf1H?TVp)OcMIuVsd%NC!IS)Lrb^|an-~XY54m422fQ7@SsbyS&s|~i5HIq(O8mvV;0jyP|)*7r$ zq}Cg3n@DXi*mjZHXs~uc+hDK`0o!D-P669&upI)n#b7%{s@Y(>M5@(byG3f7!S;w$ zyTOhWsZN6(B~m*L)+PAuHrUZ3b)>=eid2`ujuCi!4R)+Z9c!@TMCy2h9WPQR8tep- zI@w?+iqsDbc9KY)YOs?<>U4vhB2s4>><6NZvkmq`kvi94r;61120KlpE;QKbBK0GK zogq?}80<`uy3Al_iPVn`cDCSrrNPb-sjCfku1H;Lu=7OfdV`%WQa>@+1tRrRgIy?6 zHyi9Ck-F7jKN6|i4R*0e?K9XVB6XL+E)}V6gIy+4_ZaMQA}xi%wSiD)Pn}Q zQluU>*i|C+sKKrlsh=C{8j*U!VAqP&QwFJ@|CBvQXJ*v%sKy1{M{sW%OFt4O_Vu-ioH*9N;?q<&+tJ4EWY2HPi6zc<*O zBK5w(?h>g#8En6h>dyx27OB4)>~8V&?*_X^q&_s*y(0BbgWV@m|1#M9BK3*EekN!? zGuQ(H_8)^iC{q75*h3=qmBAk7DL*sVBO>K9*rOt)8tgI7#jhLe=K_{tu*XFzWUwbh z$}rfIBGtoSPYH^!!JZbWT!TF$p7u1@vm({oV9$wEUxPg_QrM7yYn*GaU$9@IXZr^l z>;>^;u)$swseFUIBvL~S_OeI~GuSI4HNs%8iqt5B{Ys=p8|*ca8f&oEMQXgk-VmuG zgS{zIB?fy-q$U~cZIPN{uy;gin!$c8QgHF_iqv5S`;AB)Zm{=6s?=b=6{&KA{Z6E2 z8SM8WRcWw4h!jSa_eE-+!Tu;x^9}YVky>c54@3$c@XsOz5BL|6T4u1niqr~&{Y|7+ z8SL*OwZ>ro5UF(r`%t864fc^p)fw!cB2{m&k3}kKuz!hEqrv_yQcVW?M5MMF>{F3y zG1zA!)n>5IMQXdj{v%Qy2Kz#!b{OoxBDKq4Uy9TogMB4ZM;YvEkviH?m`ELCVB$~X ztp7Me@rl$4*e#&}gKtR1Mlyc*O&p99BSuQ3>V*P{kBTx*v6F5BaafWfW2ft^acVUU zX+u+>(?+d89-IU#h9Rv4oy0p}O)aF9H6^6@nij}}0-}A?PspAUEmnciNw~!y3{1_G z9~+_bf}YTbEDIR9=Oq=Ll0k+C)`z2J5 z_DiT9?UztJ+ApDcv|mE?XupJN>Q&~q#JO4PP_0nvAu>Cs7h!aKN}$L_=eQ%d2SAJ+ z@)U?kg|iRr3Ow1k>o~_NkYrvp{&?>J z8zFYkSn!e!x8h8(dHz_S$;K<|=y6qrz>!U#EF3zPCa|Q96g$K$kj6>OEXmnsK_IJ! zc}%yMA9)sNvc@;j?32&}Q)Y8cOl#(FAUtd8Aah(!exhCYyPN|E$xm4eA!V-9V(K`2 zec-xVXR-xm3R!vA2QH7>o+E@sEXC@GGjLp`B`$oE=5yv-#|yq4_Gi^(#dmyDC<9F!E^}wfaTif)DOrm zHmgmcLC2}~0~SqZ*d4Z$!g>kQZ8|C1nvg9EOVJ(86Z1k!IUbE;?(t6E%od(y408Qg zSni6*{5wBi92-I9O$>HUt4@k!8Uybka&rbJAycf#r22>(!jeiKv%RE(9cYxZKNk>9 zq>h|Ri}Iu;#>`XdE9~zJ1UG3znmDNkC&$+af|b-g#($*X9W})q)OjqQULK^FgT|w# zn1jZnrkI1qqo$aH#-pZ~gT|w#SVK8c54eU(L{71WN<>bvhDt;>^(*yZ4qFg1r&vQJ za!#>^N<>bvhDtKb9_^Pc8#*W-FfrcHq&LjxL~CTGx(m!)EQSkMf(B0_sud80tt8{Ahd!ZS_pp zNTx0USoL_wXrYUa98gchF&(hyA8(<8Fus^9=BI1w$?7Q~ z^(6HNhT_N9btv~#=qZLKzDNwHr$de6^FDq^G9F=u^Ak4nD@JE&Cdg3FRL=@2lhw0L z$?A4=;7l8x^oen_wLim9&sEP0sa@*%IM-%Xj!ZG2Ug&_7HFb6b)F0sxnD8RzwM7B- z5_l%lvzRdY-cP+Os9vgGj>AC~%O>lR*p9Xx?e)>7)=h2WYk0D{sTD?WMFtCylnx=y zFZZhGd=8B0>X3S+dJPU*HnoTgwdga);ZA~7O1VzGJ_M0&@FY?dqzkAw!kJj&C%MEc zpx%U2Mz(iPg2gp*OHjR8y%kMN)vE7Q*kp&JNU}sMTYymp zcX83Fuf?$=jl4J6d=6F+7{kxh2SV!o>Vt+dMRcf#afBTXW30n^4(JFlz-Zfd)HQ=n zDK^uHd)i*ezSfF-(TJqJ$gYs^%gS^i($fyb(361rtf3q(o;{BfExzgG34RGrU@6wR z0WF}u2!Cs{wZPnpUJj}+sjuLEGpCobFzjp6%sbcMp$DqJ3W4G^)Nz@izM&2cu>tCv z5DnIW<`MrDwm#NKym{@y54MqP20|(7+v+L1KP>sq!M>K_H{PtXs(`{4F~Sea<15y$MozGAGP$WSUoOa8;a zg-qP1e*`jo*uhyKRxq{UX~ey3lj7gc@teuOgUwLKkSabyb9$Pa1=Rn58MS=OlUrUN zW7K~$)i2a9G2aqwzc!R=E}Dj;F6byi9K`N%7Spm)J{oHHAl|TSasH0o1py5ozsGL! zA`sc2hMP!(S|)lqd6*7rD}^nJ8PK=XTw0da0}e*ZHgNYbX;{m_nJ?aJv^<;x6RBQ? zvQ#|nqp%}mLbxr+?Rea|w8iD@47FQ}grJvx(DhVP*N7E-5yi~_v0Lvr{Z*z;rFvlv zVBfFkxQq_^A4*@-SWV)5#M@z5P%F@|GRPCggH!mM$6Kx-ppAs7m;g@4%iAzZ-OcaHv?{d=VD!WWn&!G-ydP}} zYEcdPTc$omJ-I1c*S3V!<$m<300r>8xuSR0MBAI{nwyT~OCGHaM-5{>+`QAHx~^qo zLmj@ouiI2t-`Uo_C!lRdUFw?YVhanVu#=rrUXv6Eo8vDxb>1oBGqhFeZc<(s_#912^J5(1 zGuMKa`sD>3+xUeZ(r*ee5(?hd4KAe9spIF`MVTDnmX6hq%S9nr!tJp>Ik2&2m|PqH ztEp{2kg#m=I9qm_71jI15G>}TcoW63-#NmBe*kA_6~3dhsd@a8XyYt?aVV@1>&A#} zg>g^0J)R!aPSei7iw(i-EZ0X_Znxyl@$oX|-b4q3xaWkx@Z5NDF|fIo$-H~R6WIR7 zx~kOU%$d{U)eD~*YCoby!?(C#;dLX&c?tQrOAQPRd_HkGUhxP$U18wZ!dC>xEOJOlREf0-?lVG|7TK6Io6(duZ9w};lPzAHezE!x1T z(b4YG_S5*^t+0u);gntr4+VKsN!RTEfTY~f2ZV)wc1)i@fnn7 z%fMfk!iB^^V5$9MT`>NA4!u*;{u^Sd_9c8C_WH1Pz(rgE?Q8U%0(zTUfSw`V=JF@> zE>~A{U#8AnG%uWF&|1A4C0Smzfi)pcu*vq*&vrA4Ih0}yY}#Cw3=(@@$444?N*;;Pa6ig#ZH+nRTDe3z3@;jZ+4 zdVdTnI&Lz{vi$OjrgmJBrVnz?899u)q<%)~nzUyqw3&o1qvMTuL?7kS*tcAgXk!#LIs_GrfeJ)-ux4*dn(8-W z*oErG!2_B7JpLiq;e?<*UWa{$P0(v?6<)$_`=K9SAEz9e<3_ar~wMD$U&eCUx^a{N) ztX}UN)f{g&3+fu`wsq3y-BXivW0`NaEL}{k^tt*x>b2F-5AH1+;#{EE@8n%1VI9t3 zRFVQMy;;-oB5t0GbD63yK?^20?3jXLKQI6rT8a(C#IZt(%x!9UP+z8Ffos&)wU+I` za5Nh~VUc9#6qiI`Jy$=z+<}T_T&1rLfyo+7EL!Nc$ZAV~SXB}wlJauCTCra7>Ff0M z)S9)qL8OM0?cdGL6(W&>k(E?;v9&n*>QCNH*ufuP-q)O<4U_fSPkz zKrc14Ljpe!;9^-^lu40#aCi(9mvD zJ|RILhMDNr^;kt%dEo6DFVk|Tg3NiF2^`|oR2Xw3| zV~Y*zw_Xa0ENvV5vqELhL6YZlS(qI6&xLR=0Q6!m%c0_JFOAnp3$U1jmwv_Rr7bY` z(!UDouj;Siu#1>bzY#+ADx885*|+1(eOgSIUkgiq7bX8Dm*tYJil1fLgi{@owRDW~ zccL1<2jw4fSst}~;-&yiH^dD2PeIh{1M~@Xc?hY$;H-?0?r(;2q;OllUwC?|=B|1p#wh}3@#|9 z0iU6q&7THvZ$XWK>4tKifZ^VPWr89^FP^ZGb)k5WWhfVmR5tB!U1}(oiEOT+Tp?0e z*jz1Ay$$6$k?LzGKM|>ZhH{fg4KS2jMQRYv_lVLC!I>W+%Me4kLp;SbUw4Vra6`FU zq(&ObeIiw8C=ZC#7(;njq{bP_Vq&-{LbhT{HX~3W z3YdigX6LeA=vc}xMfIxCbF9e*e+4wVsTn`C7MKUmY&+W61L{+O`N2SSU;zwP`Bez1 zML1g}^ar*t3AUK9_OZ1l*7PxHmJ4ZCK$?}gtT*o;ZseFx2&@svYk|Bjm-QiJU(rPC zofs0nA}o)@8!{w(MU$-@6277-Rt^bY(Nrskgs%v1#{?Y`KDw=y=P2Q$TUkX82_Id# zDso8p=+ab?L&8TlqKX{JLU){s9LYi#n2H?9LKl^a9LYjgkBS`0LidV_9LYkLhVmRG zd~`Xe$dN2`^QXv>EOf1>$dN2`XQ#-KEOa5K$dN2`+os5oEOeEo$dN2`Po~I`EOZH` z$dN2`ttHPUK%(AxK(T*kJruIMp(}~cI){Skum$p^WEA3vg)mfDhxIS=0C~#fiCx-eY-^>cY zcjrn5CiU;)@hyh>sYu;sXbVK@4ntckQg<5KMy;MY=zc>xU%P-(cN^M;+C`MQ*U;`4 zsrwD>N%8anLwicV9x}9#w0{!bBZl^=NIhm~{}HLj4ebk&dXnDlHbgtjowcagKf_zA zDb6aI`&QQeTeLx-$p&4V_i}4epjO0+2n3#0*m)B6-}VNaWM9uEal&q#5(+#Y3OpD1 z1^WCiu}9F%HxnJA8-W)C&*ZYcftT>Q&;Dg~yfrE3civ^ybmCVd=htmpN-sz0%@vO2 zE!fer5%=;7NNzO_R5mZieT$SgfnibcMb;hu9aukCwPJD1&py(1{vmP74=xg1BQQ() zsfFcD{3`v@*48%Mv5eQsKn!Da7eBKgcmkANLq9rD)!GbMXul0>1rCAuET8$9%FqjN z#ZWFCr^e1BoUz{A~csL}?V;m9YF%Agx7{`NojKje^#?fFN<6tn4aV(g}I26od90}$z z4g~WUm)6^C<03U4;~F&{;}SI< zZ!_cVW{m68IK0Eml@feq)@fcU4@fa7P@fg>k@feq(@fcU3@fa7O z@fg>j@feq&@%U_$&pBp{>(4m+JTu1CXFQLK&v=Y$&v<;18UM(PFE-;#%=l6>##Lt= z9~YhR7}uQf_zE+=(u}V%=Gvm+A_&;X+g&E_TFpiH)!g!1;!g&0(i0OJT$}5T)`zTf(WkEW+ zj~U6Uc-n<=$B%gIeF}a%r+Rc@x6*6=m?xMv=JtI`|H3?F;OK58zgrp6t&E;Ox^PUl zGJeIF+d<$D{0dlMTVqd=GHRK827!)&2urVx`G*xK}H7Au&IM3`=sDsj!Td29VQ1em=g_F!) zg<5bhnksN7FisFk)*t5OMtBVXU6P-|?V)}|5)r<=Z0q2{tKXh>JsW` zTd2LMgu>R!cPi8}mr%#rLLHY%DD3Tgr$Q}v33Y-k)QPEt!k&^>p$=-2=N9T@Tc}e~ z35D$~uR@)AFgE2D>NH!Z(^CnBoi?vR9h9N3a5dkVwoqrK5(*o9UWGa+Kefsw)H$|L z=cW=0JB;6{P^(=+oo@?uK`NoJyZN08waz8fMYd2sN+lFFTEA1F*1Lqd#1`t(R6=39 z*Q-zmH6Xi%y4)7($Ek$E&a+pc4rXuYO z;lRZADAaAXP`9TN3gY!}OE!59#p&m~q6b@Z^73!dz=Vq6tp0tH}DwR+;|Mfiz z^^7glv#Er_u`{ni9h6ONb!qB(Tc}^85(cvz-;i#Ecp$_W( z)OMFpFWW-Bl3XZ7c~$w9Dby@%f6>-jps@d#dz80n)6D1CBMaEvfug*l{2I?GMZ2H0 zhZay?$N2;w-y;k901g8X##i|7D!(yH7!O23)e7%X{vhXX2n4}joE=f#1C#faKblOY zV@Hnm9;PZJc;VZj@ubm})g%ZA|5`2ECT70^^ zfW*e*1z3#-wqO}ZB6OylXQEoTL6BN}8BU>L8URoUhA#`7#kJ;pl zz>=6|6pkJ<_8#A$R0U_)1!wsBnk|yyi%{i=gRdV>7x}FM`=YQ2{`&C(2g}=MsJys@ z_VFD;#hLAc4Ar5)H_X)DT2p%=sspKSteovcuH%qhi;!=GS&I-afNBx)jRcGo8S;%n z%2MQTUU-fQk}wGXv@j4zka6<570HG0RJURuP6cqwh-;rIa;CyCob6-PEW@r@hNzj< zK8||8f@&om^e*2td1*;JDBI|pjz%JTj=ABxe23l)K%$#>F@Y8j^UXAgapaEMbhz*? z-w{t@u(;b-K}ixuoU!mTB{N~%5Ddd+>ngrkzS$Cna|FYAU^wR+GOYH^Hx14)K0-$?OB-W}r^aASQsSlF zh_^_ImwO}L>RTbPp;g|9Tcjng@kZP#C0^%^xJ^o2>y3Dul(^0t@pdV3y*J`^skWou zh&!YuH+m!Pl$PA&jd+K&Jh;^U>nCwU`2 zK}vjzH{uhe#6R>#e3F#-G;hQwONr0$Mtq8t_$+V4Kag73Io^nWC?!768}X@9;tRYH zpC%=~$Q$wLQsRrf5uYI?zSJA>nNs4*y%C=!CBDKN@!3)%xyl>yIa18@v&pFD1Uw8}S8F;+wn?UnnKM#T)TOQsUdZ5&uX^e1|vUi>1VOdLzC>O1$42 z@ugDYyS))#CMCYt8}a4RUUk1W;vY*(e!v^?6;k4dyb)h1C4R&k@l{gd$Gj0=EhT>3 z8}T(#;wQZkUn?bk+8gn8QsQU55nnGglIOh<-ykjdm)?kfA|-y&8}W@&;+MS<|5Qr+ zsyE`Bq{OdzBfeQm{DwE;TcpHqc_Y46O8kyD;@hOe?|LJ?T}u3(H{v^_#J}@KyiZE} z2XDl8N{RpIjrcAp@dw_B_e;CvU%U}_ONsyHjreY<*#GcGe2W%nkQf+_kjraj+$zOOQeo#vMr8nY-q{Lr)BYs#$>{q-IKO!aedn0~S zO00P!eoWR>{(v{)pG!*)dLzcKjU>J_^=En`#!oFsh_k#A;};tw#M$16pOPvp#~bm} zQsO*s#P~e~iP*io5#!oU32`59#Lr2IBi@LgmlF5)M*Iu^09$My-(b-S@A412MY?+t zw>!gLkd}Oiw~}9!5)bi4{F0Qoz#H+)QsUv>h+mNskMu_Ts+73U8}YBC#ACb>za}Lf z=Z*MvDe(kv#BWH6i@g!QDJ7ohjrc7o@nmnrZ%c`%dLw>EN<7^g@vo)C-Zo6xyHetr z-b((Bl=uj5#P3Oo%e)c)R!Usqjrey`;@RGae=jATG=qm+1o zH{w4@i5Gbz{y<9XaSQp+Qeux=$bXR%d)z|)tCV=9w>tk#O1#<|@!zGyYrPTwLrT2f z8}Wxy;tk%2Kavt}^hW$oDRF~0;*X`oo4gVKOG>=i8}YxT#9O=(e!%j@L5=N#`W6Z-h|a+c?%!SV(<%L~$A`4c(Ii_&0uqnzc%X|VjMoaLoyu)Imm z^71rT-YjQ%MH(z`k(>He-dQHN;9KP^uStXDZE}{^rNQ!cIm;W;V0nj}<&9~u+$U#w zQyMJql(W1g4VHJwS>Bcg%l&eeccj6xTh8*%G+5p(XSqKOmiNe6-kk=^d*v+eO@rlq za!+)>ca{mm+5K`UAMnmH!4v&V&hnu&SUwnEK;#mM^Bk@(DT1m(yVRq@3le zX|Q}s&hoW1SUxRh`9>NnpOLeCD-D*<%2~dX2FvH6&r<;Q8Td`-^s-)XRXUC#2;G+4eNZ}HE)vrI6eH|0`(;hkkdi@zmj`DGd`-JIjO?|C5|$pEOv0AZHm#gXN#) zEc>Uy@-P0s+PnDTrZT;7@P7Xw?<{c}lY1BcZ*nOQ@y;@#dHybEIV261|B$mRNQ32v za+br>VEK`p<;XNx{!`AfFb$R;%UO;|gXO>EEXSq6^51fn6VhP$iJWC|8Z1ARvz(X) z%g^L2C#S*kb2-bYX|Vi{oaOX1SbiaAnZ_Mc{{PBZ&P+qfFXb$cNQ329a+YOju>4xi zvf|)b;@(c#6=43^X|Pn}Ea#-b(kEv*Hw~74Im_xaSgLZC3({bz$yqK+gQYHKnZ{vB zH6Ul1#$ib{L(Vdd!;)%H&T?fMx(vx#u1yGrh)FJUV{ATbw*bVW0xOJBz-X>#GDy>e!{nEozR;NszDpBl=cu5MA zGMNU&&XP(pGoH!#q)ZM4lS(NQerL4v?&%3Bnaq(gDT|k+I4Kh{wkoN)SHv?ZOJoA# zxl##c#}k()5T&U-L+E};#YND_5lg1rNndNB@jO}8&5o6N?aXJJTFmvl)OMn zyda*qT1vc7s<=h*#Pbu09g15d?N~MOOco|(vKZA^BCW=Ud)D+ne#k%cUi+jVBhr{1{KXLR#|rcw+Gjjq$`Qr6q5OCl)_27f-xO zTJpwtV)654@x-g8B{#$qi(hAoCtf2hc~d;G_-&wg;%CVn6DzB?r=IYXOV}P^Ojs+ zRnj8yI{;MV7%Fn-e&3vLr^s+b-KFjpL!xpg3o#v%e^A)1?$!El?p9Ags%`$5ZuN)v zsHctbKcJq`t)6oO3oaPjtzPiZ!|Fv3s~3ld`}e6ozF)m^Ri1iPcwo5rZuQ!3^(POj zKLvQ7dRw=8C(rKhR_~2r9Re)t;X`J5>ISpK>1ssfWj+#7?LsrBYZ1*+?ELTuN4bN- zlRcC>C|uwy_YO2_HXFq9)h>2CJC9w6So~naQl@^*@{wUaC7_-JGf=y}#;g%m>!xPc}z{{@H;H>81V8ymzeb|zGw&vf-s^)dX4M-MhY{W+TmoC{fo z`Z!=3I~MXi0T})2$p`8l^H+vGP>-Zv8RDCFL7%!O90nka_Iy%(O0=hMFw3O&RGJ*E z_>80#pLpXY$=_yrL$^C#Qs1KasCw;dI>^A~PAhrxFK%57%^Z0B#nc9bT|c92S9 zJAZfB4)+Bv+xgIo?fmnb*v`=K;^gYQSK6pU!}ZBYoNYQZoT{nhMm99OCpmMukqymZ zrzNLx3$!IU;``s9?TEFSWji0+w(~FBcK&VK&L`e&=Tpmelq{CPoz>Y;^5^~URlo8v z?qM`$XB=IsAUr39TEM~_fHYqc^KPQLEk`il*KD=BTgJQjxSl5# zsr36rtC_C(x%MjA08QoEW9)3JmmwwZWtwJ^RDL<2R-=&3az?5#Gq_^wIHSG`vVB=N^1!+nyI$-BzP@TlY@rrVc_ zI5IplIpJ@q>ekSu^-bk|k}%(voH=}uJ+&Db&Pa-=^~Yq$fjc6_bcEwtGocaT31Di^ zglI-Gn=NB2)h?w>sZo~OrrJy+$jTI^s?v-^3kFm&*ss~A9>$dn2gyYi?M2o|(}Vx2 z*a&tp8>u|bM%c5Jm9YB(-0o+=?gx_HE6Z7iHi*22asGs~J8YkJ1O|rih;FUCTdVBW<~r0q zIy@tJ6V0!Qe;YZP*Gc^F)f!7ywkDaZ3oH-EcEiJwtQ8P#k?qu+J@+|>RO3_hToscB z_pgnK*G5993R|d(WI`>rg}TZVswJsVP79ro!tH8H9nwz-&rYh-MCrx*Dj|J~EqzNe z>6h8k9|47uO5y*smE;OBWW=jxvZK8Wo4KJakDCbtfSIti%C@a@Ox3Id^CA6<5pr+q z?z5A_Wl1Zltp_g1Hjrdi-<`~7FJ|A>>f)`-DeXF2+I7jK-Kf=@uO`=-(vI4vZ7%G8 zpLQf;6rI3WtYlj4SS6pFN>8Kgl1C+Lgi~xi-Ha6=HNtLG^@n0SIy05ZriSOIRvCJ# zUrhhO=4`WByS4MIicAepid95S_~>t{qrrFE71^DvBIj!tm@1rvYS7P2X2t}FS5gJ% zE!O;*oFg+&LLx)vbD?&T;HGAYg_M6PDsi!M?K3-Ep1l5-ImYB4ryP^rELSIGsoo0# zuEf$9or4eOdV_QAJv)aTn}XKSr)P(ok|WYc92-!tPClS&F1d5qHOYC(=kgHv#^f~4 zxic`&Nsjq}t7?@g5K%SEWoRDYl)WQsdM&F86K7#kxzbH>Z}Z} zOO7s|UR8Qs8C9m}wW>>(Iqc5lQaIPemEqQ;h}!kEwkcs{*f{B8e`R0d9hvo>Wd+S@ z@GHL7D-_v#7BQc>%fo!e&nG|jgguw9LS`$Euu9+W*=&CgR>}K3Eq!KT5_1Ee#1vx^ z^AkRa!B4_!H_{}A{TY*(pNdJ0f2!qokV-O%xk>rN^gHtzY68C#*{9u62&+^dP%m2L zA6@gXc4xPCcei$5ycZG@iSaUmAJ?1=VvyqockB0K@x##?3j;tt>3+FSa(aO|UVYL7 zo_*4s@PT|1oV?s8&GGD$=6Lr>4|()SDEu4yB+z*DNx<~zljelKxlgJ(pifGw^D3`C zsp^~gq^fW3ld8P>q$;mI30n8)ldAsz`lLDVNmcMkbKsMzTt4Yx+b2C@`y_fbEPT>q z-hI-~58fvUiAdV`wJ-<(T z3EotHKzn7Cf1mam(ioNB=(x@l%(lmK#OT3o0gzs<2cVDzW#j9*diZ`U1Q)Nr|EIk=phi;dosI6;e zu_Qd}fQ`TxAfy&+@chfe+TXgh53v%9jiTZu#UgByEM|XaOSpA$%k|}1<2F)B#_f-^ zf12a=9p=l2qwNOxm-Ov(Yj}B5xz%@t@qA*v5V$xz*f}t_hC7ne-iwOHYNccG;%8z@ zQ}n~5t=h1olhx)^yEgBcwYkNv&F7f-zM#2Q3vDUhm8kL=W?L#JeSq4xg;Tu!mesy3 z)|TuRyY{yvtNnlM+8=K&Vi(x8m$&8i@UrCX;jWFOake|eTVRW~Aeney*y8Oo8)vUA zo}_Ww!-pl8P2M=|;f2Xb4p^ObM|Jkv)!8ep4pY=^K67h)%Iho_lW8_^8>YLo*L%12 zRpC9lia)&&`_)6RU#$nb^{j{0llH4aXlYqJn)Y_}?9uktZjiQ^&Hd#2V=H#+B|-0S z9%^R4BPAZR0Sz8GV{IOp;uUamE`9h5>lhdDX1h)7DuY*EL~}6HBf2fp#j3L#_YDtE zu4h{3f-r8svu}8GauVkN8;tD-U}IwRq-(Uops-EucRgO_t5** zVTGj7>48XqtF%uf;7~(GBqOEnP~A}QX9>jU?zBMSHFL-y&z zKsF-bC9h=*{lg<-wxAcrz(XD2u@9@q?pH_e(~D8OzgwS7EVbrteR|=2dKqKg`W%$y zd?+5(Ft$%$*{!eb);Bz?ez9L2PrBK=UoDcNN8`~;q-a~>(IzESlr)RK-VOFkZL4C# z!~Go<2Rj%FEzAasD`WN5VBGiVH#x0Pzr|u(;i|~( z5GAo&bh}9JxmUkmVGrvM+^0Xm*uDBQw7ZLH$h*`plhMBHq@9a$Ux)3Hi;L6PJXZ&J zix*XGqQ8@fUM)di;8w82#OBLQY`(bLQVII7vSqi zFNXlVBfVn+#M$49@RX!NV0V#DIk*~YMR;jaeEoBD0-EITLu8hJa8zVPcy3bS_>K7$ z;en}f_p9r9T{LWb1(aC#L(cEmxLO&`0UvV!(CWzJ(kgx*k)g@@MEa1%0$QYxLt}j- zeTBwi$1$AS5UauylgfsZ7`AJKC;^8ktHOO_qNop%DA1NIN+c5Dq68xmhba9b{Zfgt z+Pf&&Vzax^>J&?=fZ>pNb%M+nSdGjKJ9r7L$Im98ayX+Jv6sX@MuE^Gh=OvfIxguMisv|gez}AH~ zCFh8GX>sa`CdGEWdRw2uF{(mc`H_6Cu3nLRhq{JDh6r`V4dm-nZL@%(YZ_4-){~1V zrV&FULwV_aB10Xe7eorArProdkGftEu1|Fm6NA$RdvF>S8O8;OM20y87#m5!{~y)TNjMllO&MM@RU(sKDSz>}6Eu^f8gx>!`TT8|uPik_zf_%NzJC zUG5Lf7cU!O4)5BNhCse+fFJ5Gs*Nf1sA0##K25XHxtPODfY)(sgug2b42w8lmW_*y zizyC*;Khz}B!aKb>wO|@W?ejGM+d3h{$+HqfdxTh{^68xuORgxlE~@ zT_x&uc@75ye7*QNuHT$3V`c>=KRNeB^5MI&w979l07)cwE=W)#zd5nh}}7HBb_n;n2XLkwaq|2)jqF%?BR2 z4vQSdnNErv=3qKAGSk7-^@QqW9>GZC`V&5!bzXeVJ%iZT=FA_2H9>I4Z0_Dy(g659*#ZaoXpp_EM zkq|l7w)@p)J{c&DlyZH}jg&g{Sr#d?^?5&kIir2}t8DhC#Z z!?70V4lK4ShE;w|_;7k^uWh%5S0$fq{Wi98CsG$#Bq(Z>7vu;zndd%ywwnwenm3?IP zY1wBY{wy2}8){d0Px#dE8ERL~`kc0$cC{;aL+f5*PsJ>&=u1LSg=*T$4 zZINRmC#YThmiKGyw?*yhe|`VE``@Q_4R~t68w1|9&Xo3=!z#XJhvHxd{;T5CUGb^q zVN5k)7QB*wDpSF92i$u0HI8z|!|9wV|4s%U*nGt@;;5XIvS&h~GrsnH!a@>Ki<}GP z`+ylqa4b9$Fcl6L*8Cc15$lnHo0H>#@B~--Na$-;&B6!Z>g4PN*HRI?n&o<6?PTv2 zU)TT+35#>Zb68K01vv}*CNyyc?q8*fS@OZq;xIP8M>~xh z%JHnCx z^=u_o8Z8q{- zmf9)#cfp%(3b8)36{FARtnfRigR>sr6@P9*vCoaG*_iLBBF@Tumt{B`M@(1}iaIO%eU|BL)*Wo} z_gGtJjlb`5-OY?~dFuCEacAZK7iGK0_v!zG+B-GyzbfB36j}3xL;pv*aO&fKDMP}1 zW9I)*Ax@?IujOzWib>G3-LjE0AKlJuwkq>Yr>6lx3Rv;y)1%nfcpE+WdnS-vV7mGY>4k2Hq@`O z0{>_>+O?{FK);CFDuigvvTb;R)OzH zXXAU)+1f{}Qu~U{)^Syr?!(_$R;5ozd>EUjH?wN}QZ`@z6I&1%!WIUqSWVz)wlwfH zTb8ksEf2oLR)n5mD??whRhd6vtBph18sl}g-gtwp%esKA@9{6TE_)zbpZz$i4VSa^ z;WoA*cQvca^Ro?k#cX5Vxh$G@9&6~ikVSjl${KpT#-hECVVin?$)bHmvBpSGwmI?u z;=i({e${MizhAQE{^M9{|3=o<|8m4vvTXw%W!nc1VeJD~B5q^+mQUYZ_(JMXyiDGJ z4|#pK8E`FjQnABX~`DX##w39t<1LBJXT z3#cyxwi&RH`T$@}fCU4O1GWV)BXApFTLH_=7z9`|U_CN20BZp(E29IjR=~m;>i}y5 zEIUYe+W^ZA65e*ea)NDuwFA~OxC*ci!19700@evw@8Fw&?EtJ-<`BSk0@gRv0Bjdv zeKKzWY&T&2GA{yb4`31FW5A9CY=H3&U`GMgKkGKYx&RxLbunN^12(WnEns^AJETVy zV8;M9IQvY%js5S!)E|?B4ESAy8t^0uwgmvfSnB3 z$egu+odVd1+)luL09aw}dcb}N*r?p60Xr42F}ZgFb{b%#^Qa!D12!&?>Tw2OV|z9M zb|zpGde#7T7GUFhMF2Y+u;N~Rz|H}zsP`Pe&IN2@?_$8t1FWR?6M&r$*yP@~19kym zlloKwb|GL>`xF6o5nxmLjsfgPfKBh)8?cK3n-&=d*d>4+8tDtzrGU+doB-HmfX$4w z0CqWGhxOY6*pC4_qTf=$t^n-t{`UcPC17R!uLbNXz)A7th&whnEL!9G8^yUGbcq_iK6J ze6oH@k{0Za=j^<$$^++X^lMGd#qeZw*HT6yH;sGZ89Ogp%HRg!zGz9mL*JJ~$b{=s z#1-(Ko9x-7oPQQCrMMs7Gv{9?tNw%WjGZ?gNUQ(5q(VL%&r4k7?p4UZp#k(;Y5#pR zp0o2?^8>ejpdu;fpT~1{e#h;B^YWyepNQw|`~=$r=QT+=KNZi}`8D(bIfnvI2c9u6 z3ePk9LZI-z0KRY|z6=BZn+R9qyKe&*JZG~YF1Ertwn3qw&AZCFkL%J+l#+rI1G7xhCWlDVdpdSDt&>z$f7|C zd;n{Zz?$M<#H+=@i}KqYdE#?a91X!vl)z5aPq$?_o#Y0u^Wu2jp#Q|i`H3m#{sh=V z`lI?|Hr`_<-Y+D0FG=v;OTeqr-%o@EjtG=lWgx|M7O0fKR!Ly%ov^?QtPfgkFIr^* zwB7`bZim)R)K5kIZ_xLnHowqc(%;kHN12s@Re|+^U&9?g4Y&M=hWk_$9WF*uaY3)5 zV|Y|F+TR_GddMZ+ZuN&r1j(QsdZ53=trXl&!5tLrqu@>o?xJ8nvFfJaZpz+6!MzmRN5TCR{EVJHK&b~Qc!+|BDR_i} zM=5xWP<~FS$0>M%f+s0>iXJ>o!84S7mV)Ofc%Fh^`0;BBFHq`53SOe%WeQ%Q;8hBK zMZs$nyiUOz6ue2nTNJ!a!8;WEnu2#J_zeZ`QSe&|en-LYDfj~g?^Ezc3jRdF2Ne97 zg1=DkR|@_{!QUzP2L&He@DT<7q~K!;{)Iq!mm2inl>LN)Pbv6}g3l@V4+URP@LvkP zq~I$GzDA%h3KR-_1lvdf{R$GJAE**ParKe%N2dH6S3N23Q|fOB82u;^qhE&MzW{}$ zHnQ{!OpJc~h|zCxF#0tQMn9~O{ zT@>u6pqqlbDY%D%dnve&xZF>vpHc7t1rJj25CsoY@CXHuQt%id|C~~fQ}6@@Pg3w4 z1y51%GzHI4@GJ$-Q}7E4eo4U#6ud~mOT_AB3SOb?s}%f-g4ZZ`oq{+1ucP~k3^I%Z zIR1N|=b0{Bb=aRo?Xs>N>M%y@QW0GuMMUhuh!|sxF-Am0L_|bH)S+5i z|94q+Xe(oF&*!;({2tG9e!TDH`PzMFdXEoS!bdD)#gR{@&-j9`_-5lfeps$T>OPCp zXF2)2X8MU=_zfZREIppZ!t)=jV*`Kj55m%U6XMM+x16_3|FK;(tZ1uN=TZ z3|CsvD1?bZ`YdF+TI4DOo9esV=OZM1>Lc=XlGJJaq);OYRiS7(t=yI9F5n_A;W8$0 z1(TS4({R}rZIyt%wi7nSimCg;{hJx5gy|>p5Q5-;W=L5C0^k* zPT(}o;4IGJP4~9`WYjAt9ZTb#Xik?-rc<4kO_xT}p-4y4(MZGfZc2yUQd;QPOs-M!trx%1)!^7&`Y%)Wi^&6_uG-qf9Y z>Wh2sXN*k={9a+bo44$o6m2Q4LtNL~(9l}f8f^_QMPY**wl;T0TS_K1w{=B3+Ui>- zRY#lZ8}=@0Z`|1u4KTmLGFzHAb7I5+rYWp%Jg14B4fQSc3L8?*6O%fkTUw$GU6X1E zT+`gtR^PR=BRX4Q+UC7o(M~0Ft*&TOn-t%Oc}jlyvi$yv=G$AoBR`^)`|`B>EWg^M zD0)?WL<{ryp7=54tP@xzRZO4aAsw-oZ-rzoWa4F zL1mc|s;^Ln=Z{b{b!4!9h?e2+=O=yb&B+fo2bIlA$UieC+23A`NngHVnpUXFH@W2_M?$9l6IL4T)^YaQe& z>Q8d*2>8lN>tc3xESGBse&66SH_046(yre%SLanTG_a2 z5xppfHTTOe=lU9zy|$!1XK>N{ zMP%n2jMCxjiW}GM%iGhwx+q$;V0^AJH0WQpr8>W~uFxM`u`t>TcDy&YH`#fce_7S^ z)-}^N&0RTVcgva?ozcF7D%)3=G*%9uSs%9YnaA^));efb=fYkE{o4l3*wnP#sGKwa z_Uq3d&Ha&HpVPLcxb29Iz4x?in0m}YvR8%6zhjaTu;kxVr5E(if_;W^c>a6*MI!%b zZuh(ik=dK6T`4@@nf;ZyR{17J%a-ad`jY%^N0m_g%cc*f&@!s9dyRazpv7^}ELpoY7dSjm_od4H->s z>n87s?isKurgmT67)33Cg z?5>-azf>y~b}VN|czfl7as9H^j^45k^~3cIKE0}xQ2T=F%1LV{?_Stz{P6tzK{>&EV@=t5 zDz^n!^XmPxwv^{~uUxdgs9{ZCqqJ;8$>yqk9=V8v`tlW#?PNr z>a?2?yC)8ro$o(9XLZ)v+3i(&S7m$u!#1xORnSk-W^Jij*;NUB?mS|xQ8{s7Nxpxs z15dQO>FpboylCHoRZ9kyY~HZEyD!<-!o`C!Mk-p@!s6~xlLnL&`$tArXRV*yxiHsI z9q^(UTm@XW@QaR^XB2JTP||wDg7KAEizauJYRify4VbQp*p0J3xIXHSg*}vp9OdBcxJbw+fsg9ySMRLCAWK#{~D2<1&iSTlj zZzzc#HLIZCqCvB{|C_LA@|F!~PZIdH4SK{`Zt{Dm*QwA)P_)+t1-r*bN}|zy4ZGV= z-y=s3nmz&cQziV|rZscAsorx%ea(s

x00T(d8;e`(C0Zm!COUs^YHQ-d$0j1c|B z{MPKBX;V5nPc4UgyU+1}FJ(A-tt-nzZHCAwsLS95z?XMy{% zyrsUgGr%%25>8DQU|9;wlMpMck43q?zTv3)rf5M~dwWYkfQ1#79rr50axtXl?1b~So7(p3X3P%iTLNsL!ou-TM{zBo zZIo5bja^#2{oxnT+$B%72J6x6r1w-poxSiZtWZmZu_KdGg@tqIeUUF}CjCoPJ0 zZEbIyU*Fc)674LgZf`$o=k@>_0SQv02G~f2=>i|Ra?EH7I(9X*9JRHv1DY74u%P{j z3UZ@0ZrKtA(l~_$I(G2~h4mK`o~0ep#^{!U(vFVy-KCwK?WER;3NxH<18g$pQVtY_ z`I_6I&T32RWjm=@m?mY^H#T5)B9VHO@@aY_X-rZ5xSl?A& zw<`+5ESnH@3%bG1=fms=&UFsn2X}Ww+v3L+2yF& z+t#o=THm-R+6v~Qq%UGpI7ab1(vW46b2KyQm;Z^JH9=mn_dZ)#b?ykH`T3b?|@|}Rb(%g<7wq2NH}K5>}b8v!q~Y<_KBX+_2Iy7|Z<_EfzD`SEwlmzS=otC+jAc0LMEkjnW$F0Gkg zR|K)v!e?2)nyR%>PzF7UWM)}ynUlHoB$(5alX(_lm(`Y5*3DZ|U4bIl&w^WTdZt&! zbybTi=C0;Km}neO#LK|R%xB6d_FNqIzPQf)z9jB_34fnK*$N4Im940%uBa=WUj}2S zMOi~8V0G0L7?1r>x45*nY9-zSR8zNfc`Ye$Ug?VJT9_TTr_%EBxivLhH)zZWFlaUb zRxE*)NMMj8fp)3{HcbMXjxNk8-`vHeWz};bp#%yUB~VByfkI9R6p~7ykW~VOv=S)f zb(M8dY0biTeG)8Qp9G87C&A+NNw9c*5-eVy1dG=v!609+it_SBb!DZC7uJh*yy0R7XEQb&h&oy;bXt0L$Ko(DVaNL?Y zG-f+={B@bIZ{pvZ~5U%jeInD<&mDwy^o^&{;1hh#Zv* zK&?2(iD7Ea$*87oRVif3v(V<2I^3R(NKm0Miyzmk>HT_}#2hBn>&)6&1tAj^)fOwD zRb{#6OLwK2K*5*FXqb@d#dS4svzCy&79l7!m2F}W2*sm%H6cqDSEIBRNlp3Uin?m( zKZYP2nk7k1ZD}n$l___B@!6*@%kiKygmsQuTO%->yu#d z`Xm_1SG}aPqONvH-HMvIbxW&P)IgR%b4F*M`v*1s)4)2?@cuAeGd5X!2LW-qT<#om7Ys#zfkVOw=rI40}co>`U zXU>hkf;+BTwPbk(JO`(uPR|PO9nZ*x7*n#`>1>`j(a&Oz#3p27JQi z_V%vMu8#Wc3Om~=L5h_H=U^Xfo7q?UlQ4JD*xhLoUUWa|o+ zhP3+a+gtW3tN?{RSm{8Vt%P$KQ*yA7v!%JM(NOXfmALg**uXe)+L2wpv#l1IDhMcj zVeyNWRII3;TRLlNlno%QSS;n(pgES_7hn;wHjwRhEkx63@Ia&QRq9P zZJpSHE^TPQEWDXd;HNqH$C0MwItJTo&_f|C6H{e{RXQ1of;vk6RXC4VCXjX}Lc`GI z*7nBo`i8Ah82|A2s!6bMw3C3K0s4UC`IFm=(>zG~$3Sj*0}32!Vk?G+c1nmxGjpU8 zvEjRero}|tG8E+JB*t5l7^y^JIC)`i9lQB_KSMdvO%DW<9;rln$S*RdwWSONZq%7M z-kQYHa-!#OV&l=oMk+BY^eG1B>~-zCq8%O0jnNEck((X}COuM#^fTPpcr>w*O2nS& z#>S(GjZ_}hqG(8#-$mz}tRH%|2&AS}3`=nl#EghuN%R4`a1q2zrdVn+#c?J> z&z4A1lPQJ`xN?Y@2fdPrgqn5{#EhU=Y6K;5MnKP|NR&*>p(M@-=-DEW8bL{%5zw%tkk)ibTusxnMIf!|lDL|tXNy2u(saWzfP7J;;;r^MAXJzE6Qnw}C@)AVc+NNajZTusxnMS!H*5#8RRu%TnB?42&Y zcQe-gh^70@_`~*)Mg$nlk00aQBAA_;+)!RsUdv><@;Y+t!huk1tyRl*XEAgO(B?^b zX*K#$dvap$o~(@neZBi9X3jKKahJ}TB$;v;$~(&Ms5rl;fj>^YZtmJ#*M-fOt@WK- zu~j_At-J(X`nF^LG$)=A*^YB(o05&8yr=w`g!l{kq#$Vg96Ss{qhn~3k)CQtb7Ve z?Rwut+mSi(AP}frO+F3GJ9cgEfCi%|q29h_OJ}qT>n1i3xIw`@gt1=7t`3|+h?)`( z8?zvxL5aCDx4>dFlQ{=LiS0%6y;WOd{E6=t(psrl(#+sVzM830m7{-i%7fa#l8R&N zaP~o@Gkm$eJk)@%H%62lyISizkHUe9*7~jnw2oORO~ox|g5jvd3qC|_RqOOb6@jfz zXC@FBb7rT&Hd~2x+V8k(;<7Y+1AT+2D1&(=VIYfb*hCg`M~{v5MJ8P97!Rt0s_(9u#`wQC9x)XOAMFBnO{SYq|U(LI_ZmnzOa z?7T#IDX&8_J{fbvH^n!V3OUVSb!=0R`Ft2_`Nxc{GT3I;K+mX%3~QfXVG(qX4zrIP zJ(_K>MiwQ4BhXt|1O+We?`^<&vz=X0S^)*)m4>g>R~7;uHllQKC;*#r32eoA0E2B| zO~e!%c5t5@=wxa5ssuA^nT3=O!lTnAr>rM$WVz6oZXmZ&R;?toJr<2oTRd+bVu zt#iY^#$KPe=SxMi4pRuJ)G<|14%;fUzRY0FB2{CsZ6dXTD{!sBj$$pOlhp=m6>k7* z6RGtEYZs}F2HP%Dn+&!?q&6F@L(n!FtW&_Y7_3Xcwi;}wfNe9_E|F?6*lv+(GuR%H z+HSDDBGqBAqeZIAV8@8mE`xOoetQgdtVkVguze!cZLs46-admJFH*-F>;#cI(O@Tv z)OQSal1QCmuS}|XCsNlM><1$C6N8;E zQa2dv0+G7WU>Azi%?7(jq;56X#Ui!eU_TV8I}CP-Nc9-(QjxmLU_TPF++(mG3)s&L zc9}@sZ?MZn>Oq5DAyN+;>`IaPxxuaysmBaDT7@rI6rN$>jdmsgZ)IL zer2%hMe5fEyFsL0FxXE;>Lr8SC{nK&>?VzL`mezr5UDQ=_8?FBnZX_sDWAa}7Ae(Wk8m!2-C#c#undDe zDpDbXJtk6y!5$Z>UIu$YP=pQkq)6o&>?!fKx50iPQhg2fv`F^YIjH`uR5YJ|a_7paj3dqJc|8|+1q8f&nZL~5MDUKXhd275)M zCK>Eikt#CSYa&%*u-8Rus=?k6sp$rLQ>11Z>^C9>7yp(>9d5ASiqsJXdt0PR4fc*m zl^g7LA~n}wzZa=WgZ)9I(6hWNQVR|CN0C}&us?~^5`(=bQt*I(7AbhZzlhWdgZ)*c zRvGMlky>N0zlqd3gZ*8kHW=&!k*YJ;KSZkDVE+`U27`SlQc;8bOQf0%_K`?68|-6| zI?7<5h*Yb=J{75UgZ*2ib{OnGBGqZI&qQjc!Tu{!yAAfaNbNP)7b10x!M+r!V-1Cg z)Nuv|{?yOkG!8p-lq(rJ-B9M5mDB~16=_U|ICdo2( zy3XpS)>4-?A_Y2a)C%OGNw8uV(n8Qlyn~k1LP}XuLW(bGflMeM+DH9_>?zS=1sIov zTl~Sm)J*xY5jrpE3C${UG7&j9I$h|28y!0IfJSE#J)v3Lq*V_s$22FkIM;zjks%*F z#hb9e!#PKRGg?*)7LIxRF%_o!RHVQhBjL%1lg(~Trh4Z( z%{%IJfm(PFy_yGuz6!FbTW_3A?RrBt_3I7U)UY>XQ^($rO)YyvHuZe4il#$ElfBg* zp?b7mLiK3BgzC|L3Du+h5~@f0B~*|0OQ@z^WqwPXo3#$r3Z)K{**PtQ(eWvPBI}*w zj^G{yF?PsPASM;gKCmnBWc{w=9IrrLKh*=;_l$cqP zv(17)Rt)o)ZZSXdEYM_?Z=%^Jp#`SQ=A4+;$l+jk*3d!bxSae%z3{c1g9yn_SqmX$ zuG3=bIDCEZvRh}e1!f9adDG+vmIbP8q-aXOQAJbnpoI7~FEcokF|~TGs1%hh`dfiE zR$@#hE63?@fh%h_Cax%oRqrxmHxc<+a=|V|RdU}zN6ZhJF=5ilbAc#pKW4^s2>YP< z+UL{{$}TplO`$=@srG|rO=s90wv)no3Da#lDe9V#EelK09L*E+LP|Lv^<(b-PF~Fx zo@ESj{a9G;g2?pJ|40S`|&V0YSQw&xr-cG{@BxA-(uiU`-hcQWB#q#C)qLP-ea>{oW9e9js8+wZ2 z+A_`+d1EuJQlzk%HeaN$nN}q2RQZ6v%P2CHGURAlVPtq^F~ky|NX*pXW$VAzpcEnwJ@TO(lD zky|TZ*pXW&VAzpcFH+c%+aOZdk=rOzIGE)$;^jE_)X@m7m#D*VqC}x2rosY^;jIXL+%Yg=)9r!W+5|C7^bN*m!!|i(lZgWoKJKTXZ)aTNyA$ zev}jkHgH_EKpZ!vFEGZ%_*x$!RpHj3hI+byrnbHV--gZI(-7r1F9p1uT z4%%v&u$6#%9Gz0BiWyJ^E*_z;hbD{kkLXH4LP8G2gh{4o`1ZB0>b!WvY4N) zsi&x?hSZbQ(+tIruj`QS_n@a3n)o6ypne}}6rcC;Lz3|bvz?!?nO`wFb2CAPdZv0- zNSUUdZAwW^?Z$YR-ST@u^bzO$nt+T6CKeNqiiRyVi72rkQD z0g}=or1|Au6`jw45nUNlFITU^LCfY=aiJD{<~YhpkV+}nsMm%d(siChs)BR@^?EoH zOZ+64cm>p-;*^o?-IHK(jocJeZ&Yta6;rVqx)e6e;i!@jO0M}rh25&&76PyRI0bBp z=SB>uccAVY+w074L6?uIs z4#*aum%&|Jbn0ta>_{VTO*WrH6$HlcGxffZdaruFp-dMI>OmY~hr^iQu%3fD0(3Ci zj-B-_pi_#?G~(X27qYLlB40E*sV}k%B>b{6ONjKOLoxIwp#H*8ju7vj!HE{%Eb;`u zgeR~RYu$hrP@jXpwb@!=Zbi=r)nBVG;C?fwm$ESIYtqa+*WjTCt1pE>@iNM|!cbpT zM}*iQ^)-kF>p=C0{|eg}t0Z2%cIJm#Nj3wa6!i`D&5(Mbio;3MNd}+#TY7}?1W1t0 z^>F_V890&6;_H&(ck1s$>eK2U%uMTBw;Spo1?*4I55D{0_JCNKVx|$t?7_Zbtf0tH zDnw2G-N1!R+^7EoWcaXyvp}q1Xv5Qp``9MMzn|kblYs}Dt&S&Ee2VJyG&T#U{{b_q z`IslSygvG<|7NP6sh?xKCD?vxDAimv4M$zjP=q*$-Tf?vWu?3~)bK&PVcFuMoqGxb z8a{rH-Q-0evOx_ukp{I)v~uz=om5u}TN*Q*xy=c( zz8VfUk4WkA_-&DJc*C?(I6SQks$Ye!+0n<^6}_doqob>3l1ZUeXmdkss5VbwlVbKG zM~?3Vm27Q(2+~z4Y>VSNtFPI>92Jk=zeigbLcLczJ=1P{1H-Q(B(HKLZ~hu4A$@JX z(-FIWkUFzoXt_Jv>O1z5>uqZ?wB^*+F4St`jTDZ|-%L#B3Ks#Dx~&-AEl*;g0d1|z zp?}StirwVahqQGX<~VbNcy-jN+#fF^ocP3p_ui|vM%&8UF-qOT@5;0awHsix#6}wC zx?sE=Z3${o4f?KxUN`t0 zOG@*jAL1j|g4TwW1)baZg&xvx3egh^-qsB+q|+Ib7T8&t9N?CY*G|YqCYZwQwLUqp zv1XfG9004TZ9kAOZSgo-cA6EH`#T|6%*pX4ieta?g$bXARSA*8B#{P3)N~cr5_3)N zw&d>U(iT^=EbaT+8Pu}QjF%HVnrnW{Wq}K@9gTHIsmCERr^lKL9}{XnpxMILI8))e zA&+?hIkyW9^ay+)aWU3*gpMyUaB(GvVXi91GbGa2JDw4R)GpI5$M93T0v}iv;bSG8 z&pnXv6~QBmCnO}Q#H0il86nKEta4{pbIYXidR)@1VUn6>J0=^>ozqW)+6~%`crR($ z0S!}8V>j+JS{~hkn}zE!mp*Ka1kq|?j%7pZI^R{G-X3k_)M#P1YM7Q@qU~4Ml$f#7 zx`EZa94zPxU`c0sM+g!hkSJj?`XFV4sHwXQWs^wVL&}3*gz}K^6=9$vo{&gT=6Yu8u1j1LC6jsDejnq~)p_@rGBz<3a5) z?FnEAN9EQ5h@YatkMtcUe>$lBLVE^PB~Zjiq5%!l#sMakx$5G$9hwt97i5#PUt@7n zG_4oN^s=#d62mjJm-(8AhVMz1i01GbmSYQAo7;AF7Bs={;6ttgbceVA32vKLYpl;Q z=N*YN5zAoA?^zA)4eiYkWWm&Lk&xxL=u2Y*5SVf!#)9wA2;^z)cYNtfrVrRl0=P2T zR@+gJJ99dzTSd9EwLgTQuy^snTmo_x-9rwvfQH!~zQ<0A;IK^L4#D=%AyngEa4DAC zKpZy&AH?H{+$^QA4MG)vH`r1!T>D2#-k7AV7Zm@3@@yISIw@R890Zm+FxCX)7jkGZ zP5U&&RPEpJdD!H`qyaZ@1+>r5b_!@2w*W0eEaUPww1}&Hu6>cI{a5=EDRl?FT+}hN zi6rUr`Ffr153%98ibh$5p{V1_d9Kq~;}b_rLF-diks6>M+W+4)V5K7~Km`|ADBt?2zRHL@E2s^$*djizG` z7#l2d7&S?KP*5MJ<7?yCl+K#$VC|XDb@ZV@7SV^{nX2qDvvE{%Q7If*((R-;2u0cNIsMRTx*ZOfY*wxZjG>I&h3%$6DdlIw7MP#>pH zphe)eF46yV;G=QO466)%l0F$7kPhn)(}jL5G2ewIG74*;5)Tr)oPIfdr9a!yOY|ur zC zkBz90x?HA_+6LRbg>&&SMzUFuG=QWr7k+)Qp=rYEn*iFH%L4l0hBi!qjsmD9mt~N_ z+UwTvBURLE1awSmW9!xynCo~)P~Wbjsm2Cajx~#zFkM0zOeytUxhzQXXJV*;pO4tt zg5ik5>fsKB9XK>=S=iU(5%s6`%CLTFF3Tk00;c;g^zR7=ak`*ImDGt5(0}Nf9=p3P_fy&iVs~VhhV)Bx%o*LaJtJ1zsePe2gt$z< zoGSDRsQ${ZemN!>Sg(vXZ}NfHsP2 z88!3+ik_+8q4&tTP{-_GNm~Ob@8aEELc5W*qy(g}evhGDr+iF;{tSZN7gj!&Rar3~ zRXv!?vh{~Bq^6%SX@Kh*Y1NSBxr#B-NXW#{AJKoFso$+XD$zEk!IriS{c)kPCm_j_ zxhzbM`#~Yx(*Qk_%W^1t+e0ZDBlvr_$?^k&SiO2^NG6wG~5s) z4oIbz5s4G>X7giVJAsEA>k{+ z_Mvz}!dEoIdP2figqfIlhlGzVjO9<1@X^Jv;t2^K-TEq?knqvHt>Os@A6?2So=6tD zW>q|qEOdvecp_Qou2k_vve50P;)!ITt4+ld$wK#*@+V68=zdc1M6%H3qvDBVp_@g; z6Ujo?hKeVWh3*6uPb3Rn_$i)97P`$-JdrGPRi}6&S?C^4@kFxF&6@m)5?Q#_F@ zbUmhcB3bC}OYuaq(8ZSGiDaQ$E5#GZLRV6XCz6Hkn-ot-3=np1&3Mb&_e49Fi_78z z0Sr$S9bINwhT+)O=HVi&3YO}xI%P(Kl= z+YN28NF6Y=Wg>N_p>5V0sDa*XXlHBZQ0iVoJ6Ai8Qui6!og(#sp*qPcZuZ2?9b1)8k; z$B{F)CIxCmEQ>(kmkK*i!v5>t1C(qnx+G565L7~e=R$#B1%8b-|2%dpTKImZLv$nX zV&K_a)<5tP79Q;%cgOloIlp!mN%4U9>e`#A=JFa=g z0yhxD=xW6;JqVrvW!KQ}9#plpKo;8a!>olvAU?}yKBh9X0^D+xODDRqd6`Rxw|R`C z+dRf0Y^DTWLE6V=;XRH>+s}vN83(29XL^t0()KgG$DwK0GmcK%&xDVo&-QZ#o^ia{ zex8SC9CCI&XV9`82eJ!ZVujE^?sW6T)0wQ+ph)y8Ao)W+lE%=gEe@d;*pq8a0U zHjane*?5e**?5eb*?5e5*?5dw*?5dQ*?5c_*?5fm*m#WF*m#V)*m#Va*m#V4*m!)l z$>$t1#tm#7ex4cQ_BH;DyVrP(o7Z@Jp&4If#uuCM56$=zGsbOe93OYB@fbI)@%S<` zzTAwjFykxD8277jJlw9vW8AIAW8AF9W8AC8W8A97W8A66W8A35W8A04W89|3W89_2 zW89?1W89<0<6F)6HZ#TzY8-yM8RPae{*1fRc#NCVczmY`zsrp8HsgED_+B%{ZD|}I zcct+dH>L6T0W*Hkj2|-Nhs_xGqj5akj>co$jmBf#jK*W!i^gNzipFEyiN<5xh{j{w zhsI;vhQ?#ug~nstfyU!sna|IeF>XKO@aN4KH=prm+KUo+#^ z%@{YGaeUl!#$()a#^bll__t>Kwi&-;#<<&z9^(!(9)DoQ|1e|RUdG`cnlWxJ9wom=8Qr6dTQsh4e2+3|)%aUM;19fp zFq0{tv)q6Z3@FnAuLGc?7h`O2;0=Vsz*)l&8c$Y=0L^5>aXPvLeHU_5G-V1-Hob{7 z4wY&w454rW`x_N%h)bv$woo%u357G*UWGdBP&AeA66$bUs5z;G!r^bPLY1a3RGBSQ zc`BiBj@heF^A1I*5iU(t+Ct4wB@~WSdll-CH02g*fi2X+R6^k}wO64QABv_5T$);9 z3$-+rP&gXxRj5PK)M%Gb%Wa`*QVE3<+25#8V_ZV5u!UNgN+_KD`bLGC=MrkQE!3J+ zLgDb)w6pnm-i$c}gLTyeZ6ppHR6)JitE}^eW zQ(J7InoH^>Ybzlr2bx3|{jZ3I=Y@yCgB@}iTzfqyq zx`g_HE!6p`gu?FTH!9QymrxhlLS2+fC~UNTqe5+T3H3u;s7q1_h3#IiLLE|v>=x=r zwopG#B@}j^y$W?m({{H|m)k;JkxD3Rf_oL}kX%BYtNO08g}OSGP}q<6D%2slgiS7? zuC;}_E|pL?8sJr^L$WEiP}kc+-H=KsoKo;A)FCaJ)w?uxqb<};sf5CTiEmM;TWq0j zO(hi0X?PXtkZh{arK$b4P`9TN3P(o1QK6zPp$^zW^`sICr&qiRbx4Np7V0irsJl}M zg@ZI+g*qhX=@#l zN+_Ik@+#CJ*_2zTpW8w`no1}fy7DU2Avw>jE=@gd3-v@Qp>Y1|TNLUkTc}^85(>x8 zyb5(lHg%LsQ_t8!J)24>92WB`)FG`;ZFdRvD_f}NQVE5lW?qFlr1hyCE}@>cg?b^m zP>S-R@{%dkTx@^Q)>@!&;P|_gH)zw$=h!0)*xZ4lys7*K?ry0>hS4SN;Uq6l?$PPh76|&Of4buRCaxi>Z*fgd+=VjOx)({5^hYpUYclr9r^C-mDG>~kg z3;MEguz*w_^o7w#sA7V?9OR}7!}j&!Wy3}1u_M;v?uaJtBEW!N8?MesL(XE;<|KO^MXCDe~^7-eVH4<4ut z1-_A{_ST!)3sD(JeG}wtr*IvI>{5h$qs>x;cm`C8kZ%lNq{xtOEK-&tNAb*aRFH&8 z0HB3|K!Qw^m#s)Hgr~9<`*13NTSi>{OqVkihT*Iqt7I8=$udOAtom`30~S;#@t}A3 zX3BF*;z8MF-z-!T*>lVd-{Cv#MgS7syo(96c(`wlNsJ?R+@`~YcleHc9G%6Tz6wf` zFyf4bpDCFM{f1x|HfvY$&GpTbFq|(KE(F8*Uy)(8Z;@$mjt=60Z{}^%@+H(W&UDy^ z>U@h$TjmEn6yFlxQnS8etOp+O9p;@idPo;bwpCgg%RN;FYnBq%dL!N@C0^-`_$c2h zi4CpsM%*gRd7U@nHYxE2Z^Z3V;yQ1{+oi zVsFG}NQp1;Mtr7}_($G|&yo^f=8gDlsgYdajrbfX@m1c4&y^Bi+y;tQq3w|FDINJ@O0H{y$>#J77R{-KokfH&exq{Mf6BfeBh ze785^A4yx)z21m_EY0~oZ^V~Li68Jre7ThPA#cQ2NQocuMtr4|_)%}fS4oK<_eOlR zl=w++#MelPf8mYzTB(sd;QsRGjBfeWo{Gm7Ed!)o4c_Y48O8kj8 z;-5*i{cmr?_epd9%p39jQsU3O5kDX${?Z%qgEC^j;*IzrDY4%h@xxML%^UF}va0e2 zyb=Fgnsd+_F@EqQanaPD>5Uk__8=k7@r&!r-iY6j63_5P{HBz6mN(+xNQu2|n6kH|#B;pm{97sUk=}^k zmJ*kFBYsCpT;YxQcT(bc-iUuMC7$n%_zzOz1>T6?l@eEbBmSe5c(FI)KS_y~dLw>M zO6+k9`Oi{fk6XxpkrI2{LjJ3ic(u1Ozb_?T>y7wtQsVXAi2p7n-sp|^11a$)Z^ZwQ z5^wfK{7)%yqc`FYrNmpj5&ug{yww}=M^fT#-iSYz61R9G{zOXL=8gDMDe-o1#Q&BO zcX%WIkCeE}8}VmS;$7Z||0^Zl~@( z|M%oluJg_^{!EzvbUDinX|VjhoMl}aEYFa$tWSgGnR1p5X|Oy?UgJ^kEE8({Y`K(8 z-dQHp_&IVZo4vD4kn&u)lt+1InIPqPa+a-Wu>66XWqTSd&zG~@kp{~P%k6Tnca{lu`9nF&W71%GiJaxJX|TLhuFK=RvrK3`Ka#UNAq|#4 zma{x54VIV5S)QB*%gf~~Pfdg66>^r}O@rl?a+as3!SX6O%QMnod9|G7S!uAmM&5eP z@y;@#jbAHgd0rYUuamPpKMj^Yk+Zxo4VKr-Szeq5%Nyh@FG+*tPvtCslm^QiLpror-VIm^4#V0n++6W!~bWkPp$ zuUyLeyt7R3L_d?Wd>{>$_sLm4lm^TDkeua{X|Q}) z&hi&&uzW;r>d$y*nPBQamrMCe?<^Bc{ZTo~=h9&Ln4IPFX|Q};&ho`HSUw?V`EnX8 zpOmwFH4T|l?Kb-%UNcp z!SWCC>dEoWGNF3jm9xxCgXJIP1@GgXWkQYrNzSrg8Z6(Fvy7y{^3QUX1Jhvn7yn=F zU3_sbfPaX0mbi_{y^H_8T*_hISteA^-{dTZr@`{?a+U>Yu>3&Ia#R{D{~>2N zCJmPVl(Q^MgXM>EmgCc4`7b%kiD|I>NX~L{8Z1ASvn)=7W?EdL{CIV%m8pUGLKamSSZzjBsy(vb3VIm;u{VEKidWmy_5zm&7AICPe{w^Mcn zn15axEEPG+`Dw89$yqK)gQZ{2vN{cxs+{HGG+1hKmP^xMsmocWaad9f$XTXwSW?Z9 zvrOZ#q#Bg7T%Cq4LvogD(_on?XSqHNmWG_=#xz)F$yshngJmx{%gt%9%$BokOoL@u z&T>l{EOX>6x2C}|SI%-<8Z7hVEL+lG*;~%CEe)1^E2&8T<}*Lwp}@-KEQ>sv{)CBjbt1F9pUEPnQypjwcqs=oe2s zLmgu-$vEy5R>#E?4@?wW+<>i)MNwv}<0VWc#WNAVJnWLdWHJFv=13(;xaE0xN=c58 zN>UOpiTDxSWRe^yWimCMiTKgmWK2q>#YwnddQ{5dl&Lc$ik%%VNnuhZGojeIQc32- zGntf>$zfnpDP_X%jCS5VJvk+l`BElj@sboLWkSYQB{lbocqV0uOhCLqD#5&X;_^gd zhq*75O2DtXcIra>s;=^*XT0`TNON8r zPb_|WGoE;*H0Sm4#NwA9se zc&#+&#&}}!>rC;)>!dkvi6<7n4HQqjUP`<*o>=@cO+4`iDe<;=;ufieZIlwX#1pqA z5{FAMh-ghP&mOfso>=^li(BkmU#YLmB#z=IC+No(h83=5%-r!X9;>HgIc?dJg8+l)GNY+!^L;1SNEttc~HFp;Qi_?J?icJ z@j#DycMNM7u&kF4nE9!j%p7N_5tZlpP(-ye&77r0G)K0J!lNDe4hc{5knfOifivIR zP^sB$2+LQy*@^5tb^&7XgAKJz{gUP5f%%kxdNRyF?fw$K#$f||0rlR1dd8QmjcFEA z3^Cvan#lYYAVS=b2D9yK2)EcdPWM8fNAV_$oCjv z^s6WDse8>|8G27Wnto-7Z{7uc>fUe|fH3OwarFsNpT40ilj>7xcGTiil3INFLG@`u zvDN-;a|1qrTFkzV0GvOiuC^vUppT&C$te-jQdM!@i%K z<}H^%MVy;MZIaPH|qyG8p~#}!)<%2AbaW;Gas_2x!it+x=lqGTB7|t z4P?hJh=`Ft*-k&$&Y!vMsIZ;CaN9W?w)0nRJELJc?+e>enl0NwDv9m<&0#y-7r1Qa z124Ao&#z)TBf`s)tMhJYrH%+UBqwp!>4Cb!pFFW(U|?+5y?EZf~{7& zl`^G9S!tVU3-utYQ<$nsBN8nbP|0AwWS@BGS27$V7h1FzT0KoK{;Oi6*~M&(@+cc^ zk5*R0?gw$Zp9{MmOm?rVWEt8J@*2vKEMFTcyoN7mwFRV-w1r_-TVQ8lv_fO-b+FLk z1NUn*y4$af@2yP$VDhOw+LRt`Mvr#*e(gwf4B^o|T6vFF*`qCRsC`^`cJeA(R1?1% zIgXb}{P5K}OIEfnnXHQ~56AYv!;!2N5N)aL)SNB%X@^vkQnXwZg9i7njfrI=AykDe zR7EnOmf1pGVG7lnR4Au~PEO%=wOWVtlf(0p>NHV$v0f#lZ?&awO(y*cTlyoRP*N%U zpSGG@A-ars)l75LmtiwEw3TrqVE`}^*4Egzb&jc;4PZWeU@=1OZQX5lTDUA}LA8y* z1=%K&%xb&S_~^xKyIOs`bvdQoU`x9pnY5d=26Jh0gDLIU{o2;Tf%j-fGe*%#jKy-M z*^ZU-DXH`{*3NlsvPwAB*3+e!0a7JwMNz*?MNQBb0H>R^Y(87S@f&biLKaCveQxyaE6|1f1A>}I((DNFTk2yiK;!e|V<`_>zsbM1LK z?D!P4j{2DwZcdI!J#VZ7{c-XRRCCFl!>&rsQ$BWwz}F|IagLRNc}{Z7_gqD*Oo51^ zVeCTvzEk$faNp!K7*C|od1d&pT%~CXv#a;~!V^pms}-c6*Q36YqtD zM52F;;Kwwlff(f4Pw0nT&BYx0jZFZ^C*3LcNlq^?->Xl$+p|xaA3m5*f{&H^r1_qG z(tPhe>0XaM37LOop9C6@J_(o}ebW5!SNBO(2lYuwbzbGwCslnlpH%hLeNvTIpH$`5 zCqe5TeNxr`U!OD|KB)>mX+C^XmCGmn%=St5**@uh+b2EX-6uVG=srnEWcnoSA=@WC z?C?ndhqZ^fPkQ95jJg&dY}EC0%ftDWupIKGzP$a~ll!%2;Z61Xv|p|9@7JD38olz1 z10DVT((t6@Je1w7TuQbWa52di?`pboPD-UXP>kHjhlP zkpNd|UL@d9Lq;Sc zrUvvMm^eFi5lN|w!XCYkqjQL)SOeE12h`Dp`}HCF^?ZhTBEar^a&$ll+hV}VZ}p|$kr(+cm==P=fzS0FFvOYv$6WBc{m9({F>zWzb= zvjgfR(#^gDYLOJZJ|4Y9inb*lZE8Y6NwfIt+h{LhTLl{x9_T2TUEWbnW7b7^r^|}8 zO_Y`taG$pBfI3@-)MlxqlklLUJrFsz(J?87RqEXb)Hx`RMR|gYa&n4+15qBCpb5u1 zzNLcVu;Xw@tjdeSgB+R>Dkzhc?z>dF@5|ntEy_*iAB+UK`JWpJI?O*52?_H*9u|cP z3Rp57&fAsgO!V{N`(EtPFBVp-*_8;Wx%g<&m4)*iLjM>;nFA`>BH29#f3%Y!TA9tm zqAU+PE!;MQ^6*dxL!pIvU~y@zyzsu$?$NJvTA_Zu#kRs#kQ*UNVzb!qBE92o{Z55F zsNa2${xD;A>yOcHE{ZW~vomO{C&$FwAr`x{p&ZRIWw=Q=7!uH4@_Ny+EbSjMEk+oS&}v4l0Q z8W$$C0)9&Wv!lt@hI=FDBqR1(?(j1sncU+48p(86yb&>k#nT}m7eg{XIYafm1L|rn z0cV^Q$>NOv7Rhoj?iJ}}Gj{Gft>AVoXRLp4KwT@kr|d{JXZp`bwu5On61JJ*$P(F) z-Sw>uACXjI9YZc1*5g24oC4W}Se_J7eV3O%Cz8WO{Unm(5H&ZF8xz&VuqHV}I(gSV zD=(7A8U8zx=U~`7(mM&m%_$hVa!zqH@7)9H`a)}n)F;x13-DQ_k3)dIk-jkj;_Po# zczRMHu$xGy8eEmNDqNcsU;hY=fCf4I(3s^P90gewUXYYHej|QWcyMam1L{UzmH;d4 z3HV~o4^L`O!0rH6hjYNk>;SZS^0+jM-%n(yvVM_%q_IFS($Ar>{*nGdW3l5G&TWV_ z;VDUF!^sQVHA0k3hbU{p{bQo250EI(mMuyo65*m`MIsJS21Ev=5@oG-QL-I1u{On& zDiC(ayf#7R^RZ$M?a8Vd<#lGVE<7`-ns_GI9D__^={-41QXzU1dv&45>JryEryHnR zUZDdc*yTip=0*lOv^Xd-C|--2LmeB!6Ou|Q_VUPP?7cjvEo?}kNwNjob8Sd9Qxscy zgCm2v?7bs{9kLIJ42j9^%z9&rmFGYo%hDmWb0)BnpIec;@qlv{urWL!xlV+?8yXqP zX3I>WSB!NsJaUJ=_RNE|I=o&`Uh4tiOiebcv$OxYMz{m(k z?gfzoY3_9?=A*6!!i}j;UZQi_WOq&@BO|#0gCipy0*s1`a#)L_y=)2>B`s1?>)sTu zNH6XOq|z-kKcIxyZXIoP1EFI@`{s9QNI$EVY-o2F6Clat-81#yT`m7{N>X%LDf( z0QD)xz~p_Q)^QQO78Mu~i7iHD&Ke(yEl0(D&QKp7pHxtnTi(P+>2iN)F1&1pIlOKU z8UiC-9lY~fhRrGTsJ-OqRW~~)a~KKmGERu_wX(q2h;y-QVq{`WaS#LxJIakj z4yLXT@wR&Hxtb2%b8VrXi_C#fcLTFsJ=ft5lWk6+M_13)9M^O4&b;2Wpt(`l{3 zV&5WRzYR_RyR%Qm77{V?9>I4Z0+r4cL3793F`<2wa@TJIu%5%yKYPb3TTE_Eg zci^_b!+}TD?u<~zz>Fb?>oT@ybgJFKP;g)n&%t%UmS8*LH-hg6KTx|fdu0yI9FF+n z%o{RqQoD_}j1Pa4>AB-Qm6A?}g7$ zyK^??wC8lF-MO1`cjR^%xi9xRpdc!(X+Gjqi_>vulgB|#)n?) z${7!*bE^Ei7<^Fk1z}2p zR|;-Ujt9dNTw&eCy;po;12`ls&K1vRy**~+%-^yg?TLaAhB{|~fdX^1cODG^rj|3oIITy(#jGKb--2o}IsJ{fEz z>&u#P!`v;bzj8N=;2WTUzH`|i-_0!F_aYnady|dutE|93j*ar4$VU4wWrhCh*f{?~ zY?A*oHd&p@im}=;O}&iGQ18ZVc>iT(+ALPCoz5z>N7+2>G5r05Rcc?bc{;A<(tY@w zz^e3Fh!1BA^%hpGU&0pYe`1RR!`YHR6{`sx%W4B(vK1Mt*~;Lr*{aY}Y<1{!wkGp5 zw$?a|tutO>8;w`lhOG11#$Nwo8?pzpjoFW~x^Ow$7;a~qa@Vr@JU`o%SIjo&oy($m z=ds4#OIWne&8)G{%PiXWIJTwl=PcT9ENhDNW?LioA^t0C9#GAW8t_ZjGH@bm8`#9! z2mT20k9!n*av|qWF+k!AFZ3fh~Zk ztQG4)O@R5?Gk|RcOlNnp{6I5cn(_i*+W^Z@?g#8Bzyj*?fVBV?Qttz-6|i97QNY>& zGXl2&)(%)^#t^`^1J)}e1F#){Wo2{%)&W>JV*_BFfMo{>uM4o;AmQx{!4e#)p9I z18k7-CSb<_HZbcJz>WuONY=%GodDS2UUh(-2-vV*Re+rY*wE}V0s9VM!?X7Qb~0f3 zVFR#J04vD;7_d_T8xcMOu+sn=72XZlcL5uj(*fA`02`CD905+j_GhpWeHo12VVCMlgsZRv39{^U| z#}C-~fED$f57-5OP3c<<*oAy*o=NffL#LE^#0=k zyA-fl{rdv;Bfw@xCIa?jzz&P_2kbJyW=Bo}>~g^7L|Os60XYH3)oeF z9Wn48z^(?YY~a;^T?1I@pf>=!7O;vzj{$ZaVCD2BpSXQC9MR|Ll~}NN7483U*e%^_ z5iA^cSKy|*0=KxoRb?Q51Fyxms`fQs4A*=GaLb-~kA=FInU|948?(@vKD=FuMTRoh2c6rdou}L}K6)&^%J}nQNPt;FJQiJ!zbDs9qYVb1s za+7m0JQ>}!lu^h{<7e@Vofj=-aD#APw4~pp-<(9q`{Q|uE8jg=+2ct$KN!zh+z0QO z^J~e9|8P8G=Zy!_;=h$t$e+ja5*N376*6#SpfrhMAB*Sg{MP*7b`_YPl=BnuoSols zd*Hk_Dd(r+IXgeW_Q1I=Dd&WX<(ywbACz+_@J!%YI63l@d1hM(6y6hfnK6=>q2tH* zVYnVNlNq?sIhzG>u|*!P1rEYr=3zJ$WD&#z5D!8;81YcV!w?VW^f|16jbfvLH5S8y zLS!)>G5w^+Bv!#0%(DXhWiSX09uSfx6>*buH{rT+(@YC=us36*EA}0ouZ=Qu0Tb@y?cs| z4nfgy7mT9AH!3Qwj#j9fS2Wy6sp#n96uP}i(czO74Y$)MbitlN&R@}RftErSl`Ayl zP&8busp#l##XSRTt8W%#%@k~-;3(fJ##$-WMnO9T+bP&VK?l9*SDL9LQvkCbe3eKhAJPLk5!TA(iK*5C+)G27f7g6eB3VukzB@|pr!HU}&*<%al)9gS2Pk-uf`=%0n1V+L<>!=ol!C`7c$|VK z=*5#1JVlScpx|i=o}u7bKYl&oSCo2=f?recJOwXM@FE2-QSdSauTbzR1+P)?It6b~ z@FoSnq2MhFeoMjI6ud*h?bU_}wo5$rPMI!KoCShTnYme~(h9Q}BHX&Y<8-3eKXpXH)7N zN}Wro^C)x4VNUDIpRW6?`Yb$(~_^Bw29%X9DD+&>=SF{a#V8Z(x&n8OpyW5MoI(=$BB z3%tZDymrYO(_1X!9p2mcfRC1+AZ=g7=!<-O`E2@vulNSx@**`}#KFsV{J>BA!fyyk zmp>3|?s?_1WcrJLjh+dv$&?|UTjg%6Ky8(j?Gf0XZSA4eDvesjOso889mEQ(#3~41 zR;kJ=E?HM&4Tdm`5eO01wGjKO@_cm^>oC^n0izHi3aPV@}fxZ zZ4zdR%S!VtcPG H%Od^*od(S<