diff --git a/axi4_to_ahb.anno.json b/axi4_to_ahb.anno.json index 0e21bc50..c31d62c4 100644 --- a/axi4_to_ahb.anno.json +++ b/axi4_to_ahb.anno.json @@ -21,9 +21,7 @@ "class":"firrtl.transforms.CombinationalPath", "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_wready", "sources":[ - "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid", - "~axi4_to_ahb|axi4_to_ahb>io_axi_bready", - "~axi4_to_ahb|axi4_to_ahb>io_axi_rready" + "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid" ] }, { @@ -35,6 +33,13 @@ "~axi4_to_ahb|axi4_to_ahb>io_axi_rready" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_awready", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_haddr", @@ -55,24 +60,6 @@ "~axi4_to_ahb|axi4_to_ahb>io_axi_rready" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_awready", - "sources":[ - "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid", - "~axi4_to_ahb|axi4_to_ahb>io_axi_bready", - "~axi4_to_ahb|axi4_to_ahb>io_axi_rready" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_arready", - "sources":[ - "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid", - "~axi4_to_ahb|axi4_to_ahb>io_axi_bready", - "~axi4_to_ahb|axi4_to_ahb>io_axi_rready" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_rvalid", diff --git a/axi4_to_ahb.fir b/axi4_to_ahb.fir index f8058c43..68a58808 100644 --- a/axi4_to_ahb.fir +++ b/axi4_to_ahb.fir @@ -247,7 +247,8 @@ circuit axi4_to_ahb : wire buf_state : UInt<3> buf_state <= UInt<3>("h00") - reg buf_nxtstate : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[axi4_to_ahb.scala 62:29] + wire buf_nxtstate : UInt<3> + buf_nxtstate <= UInt<3>("h00") wire slave_valid : UInt<1> slave_valid <= UInt<1>("h00") wire slave_ready : UInt<1> @@ -400,93 +401,64 @@ circuit axi4_to_ahb : wire ahbm_clk : Clock @[axi4_to_ahb.scala 152:22] wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 153:27] wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 154:27] - node _T = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 182:30] - node _T_1 = and(_T, master_ready) @[axi4_to_ahb.scala 182:47] - wrbuf_en <= _T_1 @[axi4_to_ahb.scala 182:12] - node _T_2 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 183:34] - node _T_3 = and(_T_2, master_ready) @[axi4_to_ahb.scala 183:50] - wrbuf_data_en <= _T_3 @[axi4_to_ahb.scala 183:17] - node _T_4 = and(master_valid, master_ready) @[axi4_to_ahb.scala 184:34] - node _T_5 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 184:62] - node _T_6 = eq(_T_5, UInt<1>("h01")) @[axi4_to_ahb.scala 184:69] - node _T_7 = and(_T_4, _T_6) @[axi4_to_ahb.scala 184:49] - wrbuf_cmd_sent <= _T_7 @[axi4_to_ahb.scala 184:18] - node _T_8 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 185:33] - node _T_9 = and(wrbuf_cmd_sent, _T_8) @[axi4_to_ahb.scala 185:31] - wrbuf_rst <= _T_9 @[axi4_to_ahb.scala 185:13] - node _T_10 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 187:35] - node _T_11 = and(wrbuf_vld, _T_10) @[axi4_to_ahb.scala 187:33] - node _T_12 = eq(_T_11, UInt<1>("h00")) @[axi4_to_ahb.scala 187:21] - node _T_13 = and(_T_12, master_ready) @[axi4_to_ahb.scala 187:52] - io.axi_awready <= _T_13 @[axi4_to_ahb.scala 187:18] - node _T_14 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 188:39] - node _T_15 = and(wrbuf_data_vld, _T_14) @[axi4_to_ahb.scala 188:37] - node _T_16 = eq(_T_15, UInt<1>("h00")) @[axi4_to_ahb.scala 188:20] - node _T_17 = and(_T_16, master_ready) @[axi4_to_ahb.scala 188:56] - io.axi_wready <= _T_17 @[axi4_to_ahb.scala 188:17] - node _T_18 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 189:33] - node _T_19 = eq(_T_18, UInt<1>("h00")) @[axi4_to_ahb.scala 189:21] - node _T_20 = and(_T_19, master_ready) @[axi4_to_ahb.scala 189:51] - io.axi_arready <= _T_20 @[axi4_to_ahb.scala 189:18] - io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 190:16] - node _T_21 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 192:27] - wr_cmd_vld <= _T_21 @[axi4_to_ahb.scala 192:14] - node _T_22 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 193:30] - master_valid <= _T_22 @[axi4_to_ahb.scala 193:16] - node _T_23 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 194:38] - node _T_24 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 194:51] - node _T_25 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 194:76] - node _T_26 = mux(_T_23, _T_24, _T_25) @[axi4_to_ahb.scala 194:20] - master_tag <= _T_26 @[axi4_to_ahb.scala 194:14] - node _T_27 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 195:38] - node _T_28 = mux(_T_27, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 195:20] - master_opc <= _T_28 @[axi4_to_ahb.scala 195:14] - node _T_29 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 196:39] - node _T_30 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 196:53] - node _T_31 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 196:75] - node _T_32 = mux(_T_29, _T_30, _T_31) @[axi4_to_ahb.scala 196:21] - master_addr <= _T_32 @[axi4_to_ahb.scala 196:15] - node _T_33 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 197:39] - node _T_34 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 197:53] - node _T_35 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 197:74] - node _T_36 = mux(_T_33, _T_34, _T_35) @[axi4_to_ahb.scala 197:21] - master_size <= _T_36 @[axi4_to_ahb.scala 197:15] - node _T_37 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 198:32] - master_byteen <= _T_37 @[axi4_to_ahb.scala 198:17] - node _T_38 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 199:29] - master_wdata <= _T_38 @[axi4_to_ahb.scala 199:16] - node _T_39 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 202:32] - node _T_40 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 202:57] - node _T_41 = and(_T_39, _T_40) @[axi4_to_ahb.scala 202:46] - io.axi_bvalid <= _T_41 @[axi4_to_ahb.scala 202:17] - node _T_42 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 203:32] - node _T_43 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 203:59] - node _T_44 = mux(_T_43, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 203:49] - node _T_45 = mux(_T_42, UInt<2>("h02"), _T_44) @[axi4_to_ahb.scala 203:22] - io.axi_bresp <= _T_45 @[axi4_to_ahb.scala 203:16] - node _T_46 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 204:26] - io.axi_bid <= _T_46 @[axi4_to_ahb.scala 204:14] - node _T_47 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 206:32] - node _T_48 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 206:58] - node _T_49 = eq(_T_48, UInt<1>("h00")) @[axi4_to_ahb.scala 206:65] - node _T_50 = and(_T_47, _T_49) @[axi4_to_ahb.scala 206:46] - io.axi_rvalid <= _T_50 @[axi4_to_ahb.scala 206:17] - node _T_51 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 207:32] - node _T_52 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 207:59] - node _T_53 = mux(_T_52, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 207:49] - node _T_54 = mux(_T_51, UInt<2>("h02"), _T_53) @[axi4_to_ahb.scala 207:22] - io.axi_rresp <= _T_54 @[axi4_to_ahb.scala 207:16] - node _T_55 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 208:26] - io.axi_rid <= _T_55 @[axi4_to_ahb.scala 208:14] - node _T_56 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 209:30] - io.axi_rdata <= _T_56 @[axi4_to_ahb.scala 209:16] - node _T_57 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 210:32] - slave_ready <= _T_57 @[axi4_to_ahb.scala 210:15] - node _T_58 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 213:56] - node _T_59 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 213:91] - node _T_60 = or(_T_58, _T_59) @[axi4_to_ahb.scala 213:74] - node _T_61 = and(io.bus_clk_en, _T_60) @[axi4_to_ahb.scala 213:37] - bus_write_clk_en <= _T_61 @[axi4_to_ahb.scala 213:20] + node _T = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 192:27] + wr_cmd_vld <= _T @[axi4_to_ahb.scala 192:14] + node _T_1 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 193:30] + master_valid <= _T_1 @[axi4_to_ahb.scala 193:16] + node _T_2 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 194:38] + node _T_3 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 194:51] + node _T_4 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 194:76] + node _T_5 = mux(_T_2, _T_3, _T_4) @[axi4_to_ahb.scala 194:20] + master_tag <= _T_5 @[axi4_to_ahb.scala 194:14] + node _T_6 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 195:38] + node _T_7 = mux(_T_6, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 195:20] + master_opc <= _T_7 @[axi4_to_ahb.scala 195:14] + node _T_8 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 196:39] + node _T_9 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 196:53] + node _T_10 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 196:75] + node _T_11 = mux(_T_8, _T_9, _T_10) @[axi4_to_ahb.scala 196:21] + master_addr <= _T_11 @[axi4_to_ahb.scala 196:15] + node _T_12 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 197:39] + node _T_13 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 197:53] + node _T_14 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 197:74] + node _T_15 = mux(_T_12, _T_13, _T_14) @[axi4_to_ahb.scala 197:21] + master_size <= _T_15 @[axi4_to_ahb.scala 197:15] + node _T_16 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 198:32] + master_byteen <= _T_16 @[axi4_to_ahb.scala 198:17] + node _T_17 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 199:29] + master_wdata <= _T_17 @[axi4_to_ahb.scala 199:16] + node _T_18 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 202:32] + node _T_19 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 202:57] + node _T_20 = and(_T_18, _T_19) @[axi4_to_ahb.scala 202:46] + io.axi_bvalid <= _T_20 @[axi4_to_ahb.scala 202:17] + node _T_21 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 203:32] + node _T_22 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 203:59] + node _T_23 = mux(_T_22, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 203:49] + node _T_24 = mux(_T_21, UInt<2>("h02"), _T_23) @[axi4_to_ahb.scala 203:22] + io.axi_bresp <= _T_24 @[axi4_to_ahb.scala 203:16] + node _T_25 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 204:26] + io.axi_bid <= _T_25 @[axi4_to_ahb.scala 204:14] + node _T_26 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 206:32] + node _T_27 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 206:58] + node _T_28 = eq(_T_27, UInt<1>("h00")) @[axi4_to_ahb.scala 206:65] + node _T_29 = and(_T_26, _T_28) @[axi4_to_ahb.scala 206:46] + io.axi_rvalid <= _T_29 @[axi4_to_ahb.scala 206:17] + node _T_30 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 207:32] + node _T_31 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 207:59] + node _T_32 = mux(_T_31, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 207:49] + node _T_33 = mux(_T_30, UInt<2>("h02"), _T_32) @[axi4_to_ahb.scala 207:22] + io.axi_rresp <= _T_33 @[axi4_to_ahb.scala 207:16] + node _T_34 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 208:26] + io.axi_rid <= _T_34 @[axi4_to_ahb.scala 208:14] + node _T_35 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 209:30] + io.axi_rdata <= _T_35 @[axi4_to_ahb.scala 209:16] + node _T_36 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 210:32] + slave_ready <= _T_36 @[axi4_to_ahb.scala 210:15] + node _T_37 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 213:56] + node _T_38 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 213:91] + node _T_39 = or(_T_37, _T_38) @[axi4_to_ahb.scala 213:74] + node _T_40 = and(io.bus_clk_en, _T_39) @[axi4_to_ahb.scala 213:37] + bus_write_clk_en <= _T_40 @[axi4_to_ahb.scala 213:20] inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -494,719 +466,754 @@ circuit axi4_to_ahb : rvclkhdr.io.en <= io.bus_clk_en @[el2_lib.scala 485:16] rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 215:11] - node _T_62 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 216:59] + node _T_41 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 216:59] inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_1.io.en <= _T_62 @[el2_lib.scala 485:16] + rvclkhdr_1.io.en <= _T_41 @[el2_lib.scala 485:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 216:17] io.ahb_htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 219:17] - master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 220:16] buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 221:16] - node _T_63 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_63 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 224:20] - node _T_64 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 225:34] - node _T_65 = eq(_T_64, UInt<1>("h01")) @[axi4_to_ahb.scala 225:41] - buf_write_in <= _T_65 @[axi4_to_ahb.scala 225:20] - node _T_66 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 226:46] - node _T_67 = mux(_T_66, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 226:26] - buf_nxtstate <= _T_67 @[axi4_to_ahb.scala 226:20] - node _T_68 = and(master_valid, master_ready) @[axi4_to_ahb.scala 227:36] - buf_state_en <= _T_68 @[axi4_to_ahb.scala 227:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 228:17] - node _T_69 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 229:54] - node _T_70 = and(buf_state_en, _T_69) @[axi4_to_ahb.scala 229:38] - buf_data_wr_en <= _T_70 @[axi4_to_ahb.scala 229:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 230:27] - node _T_71 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 232:50] - node _T_72 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 232:92] - node _T_73 = add(UInt<1>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 176:52] - node _T_74 = tail(_T_73, 1) @[axi4_to_ahb.scala 176:52] - node _T_75 = mux(UInt<1>("h00"), _T_74, UInt<1>("h00")) @[axi4_to_ahb.scala 176:24] - node _T_76 = bits(_T_72, 0, 0) @[axi4_to_ahb.scala 177:44] - node _T_77 = geq(UInt<1>("h00"), _T_75) @[axi4_to_ahb.scala 177:62] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 222:18] + buf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 223:18] + buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 224:18] + slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 225:21] + slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 226:21] + buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 227:18] + cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 228:18] + trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 229:18] + buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 230:23] + buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 231:20] + slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 232:21] + slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 233:19] + bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 234:20] + rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 235:18] + node _T_42 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] + when _T_42 : @[Conditional.scala 40:58] + node _T_43 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 240:34] + node _T_44 = eq(_T_43, UInt<1>("h01")) @[axi4_to_ahb.scala 240:41] + buf_write_in <= _T_44 @[axi4_to_ahb.scala 240:20] + node _T_45 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 241:49] + node _T_46 = mux(_T_45, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 241:29] + node _T_47 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 242:36] + buf_state_en <= _T_47 @[axi4_to_ahb.scala 242:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 243:17] + node _T_48 = eq(_T_46, UInt<3>("h02")) @[axi4_to_ahb.scala 244:54] + node _T_49 = and(buf_state_en, _T_48) @[axi4_to_ahb.scala 244:38] + buf_data_wr_en <= _T_49 @[axi4_to_ahb.scala 244:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 245:27] + node _T_50 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 247:50] + node _T_51 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 247:92] + node _T_52 = add(UInt<1>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 176:52] + node _T_53 = tail(_T_52, 1) @[axi4_to_ahb.scala 176:52] + node _T_54 = mux(UInt<1>("h00"), _T_53, UInt<1>("h00")) @[axi4_to_ahb.scala 176:24] + node _T_55 = bits(_T_51, 0, 0) @[axi4_to_ahb.scala 177:44] + node _T_56 = geq(UInt<1>("h00"), _T_54) @[axi4_to_ahb.scala 177:62] + node _T_57 = and(_T_55, _T_56) @[axi4_to_ahb.scala 177:48] + node _T_58 = bits(_T_51, 1, 1) @[axi4_to_ahb.scala 177:44] + node _T_59 = geq(UInt<1>("h01"), _T_54) @[axi4_to_ahb.scala 177:62] + node _T_60 = and(_T_58, _T_59) @[axi4_to_ahb.scala 177:48] + node _T_61 = bits(_T_51, 2, 2) @[axi4_to_ahb.scala 177:44] + node _T_62 = geq(UInt<2>("h02"), _T_54) @[axi4_to_ahb.scala 177:62] + node _T_63 = and(_T_61, _T_62) @[axi4_to_ahb.scala 177:48] + node _T_64 = bits(_T_51, 3, 3) @[axi4_to_ahb.scala 177:44] + node _T_65 = geq(UInt<2>("h03"), _T_54) @[axi4_to_ahb.scala 177:62] + node _T_66 = and(_T_64, _T_65) @[axi4_to_ahb.scala 177:48] + node _T_67 = bits(_T_51, 4, 4) @[axi4_to_ahb.scala 177:44] + node _T_68 = geq(UInt<3>("h04"), _T_54) @[axi4_to_ahb.scala 177:62] + node _T_69 = and(_T_67, _T_68) @[axi4_to_ahb.scala 177:48] + node _T_70 = bits(_T_51, 5, 5) @[axi4_to_ahb.scala 177:44] + node _T_71 = geq(UInt<3>("h05"), _T_54) @[axi4_to_ahb.scala 177:62] + node _T_72 = and(_T_70, _T_71) @[axi4_to_ahb.scala 177:48] + node _T_73 = bits(_T_51, 6, 6) @[axi4_to_ahb.scala 177:44] + node _T_74 = geq(UInt<3>("h06"), _T_54) @[axi4_to_ahb.scala 177:62] + node _T_75 = and(_T_73, _T_74) @[axi4_to_ahb.scala 177:48] + node _T_76 = bits(_T_51, 7, 7) @[axi4_to_ahb.scala 177:44] + node _T_77 = geq(UInt<3>("h07"), _T_54) @[axi4_to_ahb.scala 177:62] node _T_78 = and(_T_76, _T_77) @[axi4_to_ahb.scala 177:48] - node _T_79 = bits(_T_72, 1, 1) @[axi4_to_ahb.scala 177:44] - node _T_80 = geq(UInt<1>("h01"), _T_75) @[axi4_to_ahb.scala 177:62] - node _T_81 = and(_T_79, _T_80) @[axi4_to_ahb.scala 177:48] - node _T_82 = bits(_T_72, 2, 2) @[axi4_to_ahb.scala 177:44] - node _T_83 = geq(UInt<2>("h02"), _T_75) @[axi4_to_ahb.scala 177:62] - node _T_84 = and(_T_82, _T_83) @[axi4_to_ahb.scala 177:48] - node _T_85 = bits(_T_72, 3, 3) @[axi4_to_ahb.scala 177:44] - node _T_86 = geq(UInt<2>("h03"), _T_75) @[axi4_to_ahb.scala 177:62] - node _T_87 = and(_T_85, _T_86) @[axi4_to_ahb.scala 177:48] - node _T_88 = bits(_T_72, 4, 4) @[axi4_to_ahb.scala 177:44] - node _T_89 = geq(UInt<3>("h04"), _T_75) @[axi4_to_ahb.scala 177:62] - node _T_90 = and(_T_88, _T_89) @[axi4_to_ahb.scala 177:48] - node _T_91 = bits(_T_72, 5, 5) @[axi4_to_ahb.scala 177:44] - node _T_92 = geq(UInt<3>("h05"), _T_75) @[axi4_to_ahb.scala 177:62] - node _T_93 = and(_T_91, _T_92) @[axi4_to_ahb.scala 177:48] - node _T_94 = bits(_T_72, 6, 6) @[axi4_to_ahb.scala 177:44] - node _T_95 = geq(UInt<3>("h06"), _T_75) @[axi4_to_ahb.scala 177:62] - node _T_96 = and(_T_94, _T_95) @[axi4_to_ahb.scala 177:48] - node _T_97 = bits(_T_72, 7, 7) @[axi4_to_ahb.scala 177:44] - node _T_98 = geq(UInt<3>("h07"), _T_75) @[axi4_to_ahb.scala 177:62] - node _T_99 = and(_T_97, _T_98) @[axi4_to_ahb.scala 177:48] - node _T_100 = mux(_T_99, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_101 = mux(_T_96, UInt<3>("h06"), _T_100) @[Mux.scala 98:16] - node _T_102 = mux(_T_93, UInt<3>("h05"), _T_101) @[Mux.scala 98:16] - node _T_103 = mux(_T_90, UInt<3>("h04"), _T_102) @[Mux.scala 98:16] - node _T_104 = mux(_T_87, UInt<2>("h03"), _T_103) @[Mux.scala 98:16] - node _T_105 = mux(_T_84, UInt<2>("h02"), _T_104) @[Mux.scala 98:16] - node _T_106 = mux(_T_81, UInt<1>("h01"), _T_105) @[Mux.scala 98:16] - node _T_107 = mux(_T_78, UInt<1>("h00"), _T_106) @[Mux.scala 98:16] - node _T_108 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 232:141] - node _T_109 = mux(_T_71, _T_107, _T_108) @[axi4_to_ahb.scala 232:30] - buf_cmd_byte_ptr <= _T_109 @[axi4_to_ahb.scala 232:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 233:17] - node _T_110 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 234:51] - node _T_111 = and(bypass_en, _T_110) @[axi4_to_ahb.scala 234:35] - rd_bypass_idle <= _T_111 @[axi4_to_ahb.scala 234:22] - node _T_112 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] - node _T_113 = mux(_T_112, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_114 = and(_T_113, UInt<2>("h02")) @[axi4_to_ahb.scala 235:45] - io.ahb_htrans <= _T_114 @[axi4_to_ahb.scala 235:21] + node _T_79 = mux(_T_78, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_80 = mux(_T_75, UInt<3>("h06"), _T_79) @[Mux.scala 98:16] + node _T_81 = mux(_T_72, UInt<3>("h05"), _T_80) @[Mux.scala 98:16] + node _T_82 = mux(_T_69, UInt<3>("h04"), _T_81) @[Mux.scala 98:16] + node _T_83 = mux(_T_66, UInt<2>("h03"), _T_82) @[Mux.scala 98:16] + node _T_84 = mux(_T_63, UInt<2>("h02"), _T_83) @[Mux.scala 98:16] + node _T_85 = mux(_T_60, UInt<1>("h01"), _T_84) @[Mux.scala 98:16] + node _T_86 = mux(_T_57, UInt<1>("h00"), _T_85) @[Mux.scala 98:16] + node _T_87 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 247:141] + node _T_88 = mux(_T_50, _T_86, _T_87) @[axi4_to_ahb.scala 247:30] + buf_cmd_byte_ptr <= _T_88 @[axi4_to_ahb.scala 247:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 248:17] + node _T_89 = eq(_T_46, UInt<3>("h01")) @[axi4_to_ahb.scala 249:51] + node _T_90 = and(bypass_en, _T_89) @[axi4_to_ahb.scala 249:35] + rd_bypass_idle <= _T_90 @[axi4_to_ahb.scala 249:22] + node _T_91 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] + node _T_92 = mux(_T_91, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_93 = and(_T_92, UInt<2>("h02")) @[axi4_to_ahb.scala 250:45] + io.ahb_htrans <= _T_93 @[axi4_to_ahb.scala 250:21] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] - node _T_115 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_115 : @[Conditional.scala 39:67] - node _T_116 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 239:54] - node _T_117 = eq(_T_116, UInt<1>("h00")) @[axi4_to_ahb.scala 239:61] - node _T_118 = and(master_valid, _T_117) @[axi4_to_ahb.scala 239:41] - node _T_119 = bits(_T_118, 0, 0) @[axi4_to_ahb.scala 239:82] - node _T_120 = mux(_T_119, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 239:26] - buf_nxtstate <= _T_120 @[axi4_to_ahb.scala 239:20] - node _T_121 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 240:51] - node _T_122 = neq(_T_121, UInt<1>("h00")) @[axi4_to_ahb.scala 240:58] - node _T_123 = and(ahb_hready_q, _T_122) @[axi4_to_ahb.scala 240:36] - node _T_124 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 240:72] - node _T_125 = and(_T_123, _T_124) @[axi4_to_ahb.scala 240:70] - buf_state_en <= _T_125 @[axi4_to_ahb.scala 240:20] - node _T_126 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 241:34] - node _T_127 = and(buf_state_en, _T_126) @[axi4_to_ahb.scala 241:32] - cmd_done <= _T_127 @[axi4_to_ahb.scala 241:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 242:20] - node _T_128 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 243:52] - node _T_129 = neq(_T_128, UInt<1>("h00")) @[axi4_to_ahb.scala 243:59] - node _T_130 = and(ahb_hready_q, _T_129) @[axi4_to_ahb.scala 243:37] - node _T_131 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 243:73] - node _T_132 = and(_T_130, _T_131) @[axi4_to_ahb.scala 243:71] - node _T_133 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 243:104] - node _T_134 = and(_T_132, _T_133) @[axi4_to_ahb.scala 243:88] - master_ready <= _T_134 @[axi4_to_ahb.scala 243:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 244:17] - node _T_135 = and(master_ready, master_valid) @[axi4_to_ahb.scala 245:33] - bypass_en <= _T_135 @[axi4_to_ahb.scala 245:17] - node _T_136 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 246:47] - node _T_137 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 246:62] - node _T_138 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 246:78] - node _T_139 = mux(_T_136, _T_137, _T_138) @[axi4_to_ahb.scala 246:30] - buf_cmd_byte_ptr <= _T_139 @[axi4_to_ahb.scala 246:24] - node _T_140 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 247:44] - node _T_141 = or(_T_140, bypass_en) @[axi4_to_ahb.scala 247:58] - node _T_142 = bits(_T_141, 0, 0) @[Bitwise.scala 72:15] - node _T_143 = mux(_T_142, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_144 = and(UInt<2>("h02"), _T_143) @[axi4_to_ahb.scala 247:32] - io.ahb_htrans <= _T_144 @[axi4_to_ahb.scala 247:21] + node _T_94 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] + when _T_94 : @[Conditional.scala 39:67] + node _T_95 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 254:56] + node _T_96 = eq(_T_95, UInt<1>("h00")) @[axi4_to_ahb.scala 254:63] + node _T_97 = and(master_valid, _T_96) @[axi4_to_ahb.scala 254:43] + node _T_98 = bits(_T_97, 0, 0) @[axi4_to_ahb.scala 254:84] + node _T_99 = mux(_T_98, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 254:28] + node _T_100 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 255:51] + node _T_101 = neq(_T_100, UInt<1>("h00")) @[axi4_to_ahb.scala 255:58] + node _T_102 = and(ahb_hready_q, _T_101) @[axi4_to_ahb.scala 255:36] + node _T_103 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 255:72] + node _T_104 = and(_T_102, _T_103) @[axi4_to_ahb.scala 255:70] + buf_state_en <= _T_104 @[axi4_to_ahb.scala 255:20] + node _T_105 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 256:34] + node _T_106 = and(buf_state_en, _T_105) @[axi4_to_ahb.scala 256:32] + cmd_done <= _T_106 @[axi4_to_ahb.scala 256:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 257:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 258:55] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 258:62] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 258:40] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 258:76] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 258:74] + node _T_112 = eq(_T_99, UInt<3>("h06")) @[axi4_to_ahb.scala 258:107] + node _T_113 = and(_T_111, _T_112) @[axi4_to_ahb.scala 258:91] + buf_wr_en <= _T_113 @[axi4_to_ahb.scala 259:17] + node _T_114 = and(_T_113, master_valid) @[axi4_to_ahb.scala 260:33] + bypass_en <= _T_114 @[axi4_to_ahb.scala 260:17] + node _T_115 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 261:47] + node _T_116 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 261:62] + node _T_117 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 261:78] + node _T_118 = mux(_T_115, _T_116, _T_117) @[axi4_to_ahb.scala 261:30] + buf_cmd_byte_ptr <= _T_118 @[axi4_to_ahb.scala 261:24] + node _T_119 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 262:44] + node _T_120 = or(_T_119, bypass_en) @[axi4_to_ahb.scala 262:58] + node _T_121 = bits(_T_120, 0, 0) @[Bitwise.scala 72:15] + node _T_122 = mux(_T_121, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_123 = and(UInt<2>("h02"), _T_122) @[axi4_to_ahb.scala 262:32] + io.ahb_htrans <= _T_123 @[axi4_to_ahb.scala 262:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_145 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] - when _T_145 : @[Conditional.scala 39:67] - node _T_146 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 251:39] - node _T_147 = and(ahb_hready_q, _T_146) @[axi4_to_ahb.scala 251:37] - node _T_148 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 251:82] - node _T_149 = eq(_T_148, UInt<1>("h01")) @[axi4_to_ahb.scala 251:89] - node _T_150 = and(master_valid, _T_149) @[axi4_to_ahb.scala 251:70] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 251:55] - node _T_152 = and(_T_147, _T_151) @[axi4_to_ahb.scala 251:53] - master_ready <= _T_152 @[axi4_to_ahb.scala 251:20] - node _T_153 = and(master_valid, master_ready) @[axi4_to_ahb.scala 252:34] - node _T_154 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 252:62] - node _T_155 = eq(_T_154, UInt<1>("h00")) @[axi4_to_ahb.scala 252:69] - node _T_156 = and(_T_153, _T_155) @[axi4_to_ahb.scala 252:49] - buf_wr_en <= _T_156 @[axi4_to_ahb.scala 252:17] - node _T_157 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 253:45] - node _T_158 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 253:84] - node _T_159 = mux(_T_158, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 253:67] - node _T_160 = mux(_T_157, UInt<3>("h07"), _T_159) @[axi4_to_ahb.scala 253:26] - buf_nxtstate <= _T_160 @[axi4_to_ahb.scala 253:20] - node _T_161 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 254:37] - buf_state_en <= _T_161 @[axi4_to_ahb.scala 254:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 255:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 256:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 257:23] - node _T_162 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 258:41] - node _T_163 = and(buf_state_en, _T_162) @[axi4_to_ahb.scala 258:39] - slave_valid_pre <= _T_163 @[axi4_to_ahb.scala 258:23] - node _T_164 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 259:34] - node _T_165 = and(buf_state_en, _T_164) @[axi4_to_ahb.scala 259:32] - cmd_done <= _T_165 @[axi4_to_ahb.scala 259:16] - node _T_166 = and(master_ready, master_valid) @[axi4_to_ahb.scala 260:33] - node _T_167 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 260:64] - node _T_168 = and(_T_166, _T_167) @[axi4_to_ahb.scala 260:48] - node _T_169 = and(_T_168, buf_state_en) @[axi4_to_ahb.scala 260:79] - bypass_en <= _T_169 @[axi4_to_ahb.scala 260:17] - node _T_170 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 261:47] - node _T_171 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 261:62] - node _T_172 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 261:78] - node _T_173 = mux(_T_170, _T_171, _T_172) @[axi4_to_ahb.scala 261:30] - buf_cmd_byte_ptr <= _T_173 @[axi4_to_ahb.scala 261:24] - node _T_174 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 262:59] - node _T_175 = and(_T_174, buf_state_en) @[axi4_to_ahb.scala 262:74] - node _T_176 = eq(_T_175, UInt<1>("h00")) @[axi4_to_ahb.scala 262:43] - node _T_177 = bits(_T_176, 0, 0) @[Bitwise.scala 72:15] - node _T_178 = mux(_T_177, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_179 = and(UInt<2>("h02"), _T_178) @[axi4_to_ahb.scala 262:32] - io.ahb_htrans <= _T_179 @[axi4_to_ahb.scala 262:21] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 263:20] + node _T_124 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] + when _T_124 : @[Conditional.scala 39:67] + node _T_125 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 266:41] + node _T_126 = and(ahb_hready_q, _T_125) @[axi4_to_ahb.scala 266:39] + node _T_127 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 266:84] + node _T_128 = eq(_T_127, UInt<1>("h01")) @[axi4_to_ahb.scala 266:91] + node _T_129 = and(master_valid, _T_128) @[axi4_to_ahb.scala 266:72] + node _T_130 = eq(_T_129, UInt<1>("h00")) @[axi4_to_ahb.scala 266:57] + node _T_131 = and(_T_126, _T_130) @[axi4_to_ahb.scala 266:55] + node _T_132 = and(master_valid, _T_131) @[axi4_to_ahb.scala 267:34] + node _T_133 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 267:62] + node _T_134 = eq(_T_133, UInt<1>("h00")) @[axi4_to_ahb.scala 267:69] + node _T_135 = and(_T_132, _T_134) @[axi4_to_ahb.scala 267:49] + buf_wr_en <= _T_135 @[axi4_to_ahb.scala 267:17] + node _T_136 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 268:47] + node _T_137 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 268:86] + node _T_138 = mux(_T_137, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 268:69] + node _T_139 = mux(_T_136, UInt<3>("h07"), _T_138) @[axi4_to_ahb.scala 268:28] + node _T_140 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 269:37] + buf_state_en <= _T_140 @[axi4_to_ahb.scala 269:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 270:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 271:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 272:23] + node _T_141 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 273:41] + node _T_142 = and(buf_state_en, _T_141) @[axi4_to_ahb.scala 273:39] + slave_valid_pre <= _T_142 @[axi4_to_ahb.scala 273:23] + node _T_143 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 274:34] + node _T_144 = and(buf_state_en, _T_143) @[axi4_to_ahb.scala 274:32] + cmd_done <= _T_144 @[axi4_to_ahb.scala 274:16] + node _T_145 = and(_T_131, master_valid) @[axi4_to_ahb.scala 275:33] + node _T_146 = eq(_T_139, UInt<3>("h06")) @[axi4_to_ahb.scala 275:64] + node _T_147 = and(_T_145, _T_146) @[axi4_to_ahb.scala 275:48] + node _T_148 = and(_T_147, buf_state_en) @[axi4_to_ahb.scala 275:79] + bypass_en <= _T_148 @[axi4_to_ahb.scala 275:17] + node _T_149 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:47] + node _T_150 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 276:62] + node _T_151 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 276:78] + node _T_152 = mux(_T_149, _T_150, _T_151) @[axi4_to_ahb.scala 276:30] + buf_cmd_byte_ptr <= _T_152 @[axi4_to_ahb.scala 276:24] + node _T_153 = neq(_T_139, UInt<3>("h06")) @[axi4_to_ahb.scala 277:59] + node _T_154 = and(_T_153, buf_state_en) @[axi4_to_ahb.scala 277:74] + node _T_155 = eq(_T_154, UInt<1>("h00")) @[axi4_to_ahb.scala 277:43] + node _T_156 = bits(_T_155, 0, 0) @[Bitwise.scala 72:15] + node _T_157 = mux(_T_156, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_158 = and(UInt<2>("h02"), _T_157) @[axi4_to_ahb.scala 277:32] + io.ahb_htrans <= _T_158 @[axi4_to_ahb.scala 277:21] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 278:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_180 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] - when _T_180 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 267:20] - node _T_181 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 268:51] - node _T_182 = neq(_T_181, UInt<1>("h00")) @[axi4_to_ahb.scala 268:58] - node _T_183 = and(ahb_hready_q, _T_182) @[axi4_to_ahb.scala 268:36] - node _T_184 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 268:72] - node _T_185 = and(_T_183, _T_184) @[axi4_to_ahb.scala 268:70] - buf_state_en <= _T_185 @[axi4_to_ahb.scala 268:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 269:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 270:20] - node _T_186 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 271:35] - buf_cmd_byte_ptr <= _T_186 @[axi4_to_ahb.scala 271:24] - node _T_187 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 272:47] - node _T_188 = bits(_T_187, 0, 0) @[Bitwise.scala 72:15] - node _T_189 = mux(_T_188, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_190 = and(UInt<2>("h02"), _T_189) @[axi4_to_ahb.scala 272:37] - io.ahb_htrans <= _T_190 @[axi4_to_ahb.scala 272:21] + node _T_159 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] + when _T_159 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 282:20] + node _T_160 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 283:51] + node _T_161 = neq(_T_160, UInt<1>("h00")) @[axi4_to_ahb.scala 283:58] + node _T_162 = and(ahb_hready_q, _T_161) @[axi4_to_ahb.scala 283:36] + node _T_163 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 283:72] + node _T_164 = and(_T_162, _T_163) @[axi4_to_ahb.scala 283:70] + buf_state_en <= _T_164 @[axi4_to_ahb.scala 283:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 284:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 285:20] + node _T_165 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 286:35] + buf_cmd_byte_ptr <= _T_165 @[axi4_to_ahb.scala 286:24] + node _T_166 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 287:47] + node _T_167 = bits(_T_166, 0, 0) @[Bitwise.scala 72:15] + node _T_168 = mux(_T_167, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_169 = and(UInt<2>("h02"), _T_168) @[axi4_to_ahb.scala 287:37] + io.ahb_htrans <= _T_169 @[axi4_to_ahb.scala 287:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_191 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_191 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 276:20] - node _T_192 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 277:37] - buf_state_en <= _T_192 @[axi4_to_ahb.scala 277:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 278:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 279:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 280:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 281:20] + node _T_170 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] + when _T_170 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 291:20] + node _T_171 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 292:37] + buf_state_en <= _T_171 @[axi4_to_ahb.scala 292:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 293:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 294:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 295:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 296:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_193 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_193 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 285:20] - node _T_194 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 286:33] - node _T_195 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 286:63] - node _T_196 = neq(_T_195, UInt<1>("h00")) @[axi4_to_ahb.scala 286:70] - node _T_197 = and(_T_194, _T_196) @[axi4_to_ahb.scala 286:48] - trxn_done <= _T_197 @[axi4_to_ahb.scala 286:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 287:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 288:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 289:20] - node _T_198 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 290:47] - node _T_199 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 290:85] - node _T_200 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 290:103] - node _T_201 = add(_T_199, UInt<1>("h01")) @[axi4_to_ahb.scala 176:52] - node _T_202 = tail(_T_201, 1) @[axi4_to_ahb.scala 176:52] - node _T_203 = mux(UInt<1>("h01"), _T_202, _T_199) @[axi4_to_ahb.scala 176:24] - node _T_204 = bits(_T_200, 0, 0) @[axi4_to_ahb.scala 177:44] - node _T_205 = geq(UInt<1>("h00"), _T_203) @[axi4_to_ahb.scala 177:62] + node _T_172 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] + when _T_172 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 300:20] + node _T_173 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 301:33] + node _T_174 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 301:63] + node _T_175 = neq(_T_174, UInt<1>("h00")) @[axi4_to_ahb.scala 301:70] + node _T_176 = and(_T_173, _T_175) @[axi4_to_ahb.scala 301:48] + trxn_done <= _T_176 @[axi4_to_ahb.scala 301:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 302:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 303:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 304:20] + node _T_177 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 305:47] + node _T_178 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 305:85] + node _T_179 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 305:103] + node _T_180 = add(_T_178, UInt<1>("h01")) @[axi4_to_ahb.scala 176:52] + node _T_181 = tail(_T_180, 1) @[axi4_to_ahb.scala 176:52] + node _T_182 = mux(UInt<1>("h01"), _T_181, _T_178) @[axi4_to_ahb.scala 176:24] + node _T_183 = bits(_T_179, 0, 0) @[axi4_to_ahb.scala 177:44] + node _T_184 = geq(UInt<1>("h00"), _T_182) @[axi4_to_ahb.scala 177:62] + node _T_185 = and(_T_183, _T_184) @[axi4_to_ahb.scala 177:48] + node _T_186 = bits(_T_179, 1, 1) @[axi4_to_ahb.scala 177:44] + node _T_187 = geq(UInt<1>("h01"), _T_182) @[axi4_to_ahb.scala 177:62] + node _T_188 = and(_T_186, _T_187) @[axi4_to_ahb.scala 177:48] + node _T_189 = bits(_T_179, 2, 2) @[axi4_to_ahb.scala 177:44] + node _T_190 = geq(UInt<2>("h02"), _T_182) @[axi4_to_ahb.scala 177:62] + node _T_191 = and(_T_189, _T_190) @[axi4_to_ahb.scala 177:48] + node _T_192 = bits(_T_179, 3, 3) @[axi4_to_ahb.scala 177:44] + node _T_193 = geq(UInt<2>("h03"), _T_182) @[axi4_to_ahb.scala 177:62] + node _T_194 = and(_T_192, _T_193) @[axi4_to_ahb.scala 177:48] + node _T_195 = bits(_T_179, 4, 4) @[axi4_to_ahb.scala 177:44] + node _T_196 = geq(UInt<3>("h04"), _T_182) @[axi4_to_ahb.scala 177:62] + node _T_197 = and(_T_195, _T_196) @[axi4_to_ahb.scala 177:48] + node _T_198 = bits(_T_179, 5, 5) @[axi4_to_ahb.scala 177:44] + node _T_199 = geq(UInt<3>("h05"), _T_182) @[axi4_to_ahb.scala 177:62] + node _T_200 = and(_T_198, _T_199) @[axi4_to_ahb.scala 177:48] + node _T_201 = bits(_T_179, 6, 6) @[axi4_to_ahb.scala 177:44] + node _T_202 = geq(UInt<3>("h06"), _T_182) @[axi4_to_ahb.scala 177:62] + node _T_203 = and(_T_201, _T_202) @[axi4_to_ahb.scala 177:48] + node _T_204 = bits(_T_179, 7, 7) @[axi4_to_ahb.scala 177:44] + node _T_205 = geq(UInt<3>("h07"), _T_182) @[axi4_to_ahb.scala 177:62] node _T_206 = and(_T_204, _T_205) @[axi4_to_ahb.scala 177:48] - node _T_207 = bits(_T_200, 1, 1) @[axi4_to_ahb.scala 177:44] - node _T_208 = geq(UInt<1>("h01"), _T_203) @[axi4_to_ahb.scala 177:62] - node _T_209 = and(_T_207, _T_208) @[axi4_to_ahb.scala 177:48] - node _T_210 = bits(_T_200, 2, 2) @[axi4_to_ahb.scala 177:44] - node _T_211 = geq(UInt<2>("h02"), _T_203) @[axi4_to_ahb.scala 177:62] - node _T_212 = and(_T_210, _T_211) @[axi4_to_ahb.scala 177:48] - node _T_213 = bits(_T_200, 3, 3) @[axi4_to_ahb.scala 177:44] - node _T_214 = geq(UInt<2>("h03"), _T_203) @[axi4_to_ahb.scala 177:62] - node _T_215 = and(_T_213, _T_214) @[axi4_to_ahb.scala 177:48] - node _T_216 = bits(_T_200, 4, 4) @[axi4_to_ahb.scala 177:44] - node _T_217 = geq(UInt<3>("h04"), _T_203) @[axi4_to_ahb.scala 177:62] - node _T_218 = and(_T_216, _T_217) @[axi4_to_ahb.scala 177:48] - node _T_219 = bits(_T_200, 5, 5) @[axi4_to_ahb.scala 177:44] - node _T_220 = geq(UInt<3>("h05"), _T_203) @[axi4_to_ahb.scala 177:62] - node _T_221 = and(_T_219, _T_220) @[axi4_to_ahb.scala 177:48] - node _T_222 = bits(_T_200, 6, 6) @[axi4_to_ahb.scala 177:44] - node _T_223 = geq(UInt<3>("h06"), _T_203) @[axi4_to_ahb.scala 177:62] - node _T_224 = and(_T_222, _T_223) @[axi4_to_ahb.scala 177:48] - node _T_225 = bits(_T_200, 7, 7) @[axi4_to_ahb.scala 177:44] - node _T_226 = geq(UInt<3>("h07"), _T_203) @[axi4_to_ahb.scala 177:62] - node _T_227 = and(_T_225, _T_226) @[axi4_to_ahb.scala 177:48] - node _T_228 = mux(_T_227, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_229 = mux(_T_224, UInt<3>("h06"), _T_228) @[Mux.scala 98:16] - node _T_230 = mux(_T_221, UInt<3>("h05"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_218, UInt<3>("h04"), _T_230) @[Mux.scala 98:16] - node _T_232 = mux(_T_215, UInt<2>("h03"), _T_231) @[Mux.scala 98:16] - node _T_233 = mux(_T_212, UInt<2>("h02"), _T_232) @[Mux.scala 98:16] - node _T_234 = mux(_T_209, UInt<1>("h01"), _T_233) @[Mux.scala 98:16] - node _T_235 = mux(_T_206, UInt<1>("h00"), _T_234) @[Mux.scala 98:16] - node _T_236 = mux(_T_198, _T_235, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 290:30] - buf_cmd_byte_ptr <= _T_236 @[axi4_to_ahb.scala 290:24] - node _T_237 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 291:65] - node _T_238 = or(buf_aligned, _T_237) @[axi4_to_ahb.scala 291:44] - node _T_239 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 291:127] - node _T_240 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 291:145] - node _T_241 = add(_T_239, UInt<1>("h01")) @[axi4_to_ahb.scala 176:52] - node _T_242 = tail(_T_241, 1) @[axi4_to_ahb.scala 176:52] - node _T_243 = mux(UInt<1>("h01"), _T_242, _T_239) @[axi4_to_ahb.scala 176:24] - node _T_244 = bits(_T_240, 0, 0) @[axi4_to_ahb.scala 177:44] - node _T_245 = geq(UInt<1>("h00"), _T_243) @[axi4_to_ahb.scala 177:62] + node _T_207 = mux(_T_206, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_208 = mux(_T_203, UInt<3>("h06"), _T_207) @[Mux.scala 98:16] + node _T_209 = mux(_T_200, UInt<3>("h05"), _T_208) @[Mux.scala 98:16] + node _T_210 = mux(_T_197, UInt<3>("h04"), _T_209) @[Mux.scala 98:16] + node _T_211 = mux(_T_194, UInt<2>("h03"), _T_210) @[Mux.scala 98:16] + node _T_212 = mux(_T_191, UInt<2>("h02"), _T_211) @[Mux.scala 98:16] + node _T_213 = mux(_T_188, UInt<1>("h01"), _T_212) @[Mux.scala 98:16] + node _T_214 = mux(_T_185, UInt<1>("h00"), _T_213) @[Mux.scala 98:16] + node _T_215 = mux(_T_177, _T_214, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 305:30] + buf_cmd_byte_ptr <= _T_215 @[axi4_to_ahb.scala 305:24] + node _T_216 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 306:65] + node _T_217 = or(buf_aligned, _T_216) @[axi4_to_ahb.scala 306:44] + node _T_218 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 306:127] + node _T_219 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 306:145] + node _T_220 = add(_T_218, UInt<1>("h01")) @[axi4_to_ahb.scala 176:52] + node _T_221 = tail(_T_220, 1) @[axi4_to_ahb.scala 176:52] + node _T_222 = mux(UInt<1>("h01"), _T_221, _T_218) @[axi4_to_ahb.scala 176:24] + node _T_223 = bits(_T_219, 0, 0) @[axi4_to_ahb.scala 177:44] + node _T_224 = geq(UInt<1>("h00"), _T_222) @[axi4_to_ahb.scala 177:62] + node _T_225 = and(_T_223, _T_224) @[axi4_to_ahb.scala 177:48] + node _T_226 = bits(_T_219, 1, 1) @[axi4_to_ahb.scala 177:44] + node _T_227 = geq(UInt<1>("h01"), _T_222) @[axi4_to_ahb.scala 177:62] + node _T_228 = and(_T_226, _T_227) @[axi4_to_ahb.scala 177:48] + node _T_229 = bits(_T_219, 2, 2) @[axi4_to_ahb.scala 177:44] + node _T_230 = geq(UInt<2>("h02"), _T_222) @[axi4_to_ahb.scala 177:62] + node _T_231 = and(_T_229, _T_230) @[axi4_to_ahb.scala 177:48] + node _T_232 = bits(_T_219, 3, 3) @[axi4_to_ahb.scala 177:44] + node _T_233 = geq(UInt<2>("h03"), _T_222) @[axi4_to_ahb.scala 177:62] + node _T_234 = and(_T_232, _T_233) @[axi4_to_ahb.scala 177:48] + node _T_235 = bits(_T_219, 4, 4) @[axi4_to_ahb.scala 177:44] + node _T_236 = geq(UInt<3>("h04"), _T_222) @[axi4_to_ahb.scala 177:62] + node _T_237 = and(_T_235, _T_236) @[axi4_to_ahb.scala 177:48] + node _T_238 = bits(_T_219, 5, 5) @[axi4_to_ahb.scala 177:44] + node _T_239 = geq(UInt<3>("h05"), _T_222) @[axi4_to_ahb.scala 177:62] + node _T_240 = and(_T_238, _T_239) @[axi4_to_ahb.scala 177:48] + node _T_241 = bits(_T_219, 6, 6) @[axi4_to_ahb.scala 177:44] + node _T_242 = geq(UInt<3>("h06"), _T_222) @[axi4_to_ahb.scala 177:62] + node _T_243 = and(_T_241, _T_242) @[axi4_to_ahb.scala 177:48] + node _T_244 = bits(_T_219, 7, 7) @[axi4_to_ahb.scala 177:44] + node _T_245 = geq(UInt<3>("h07"), _T_222) @[axi4_to_ahb.scala 177:62] node _T_246 = and(_T_244, _T_245) @[axi4_to_ahb.scala 177:48] - node _T_247 = bits(_T_240, 1, 1) @[axi4_to_ahb.scala 177:44] - node _T_248 = geq(UInt<1>("h01"), _T_243) @[axi4_to_ahb.scala 177:62] - node _T_249 = and(_T_247, _T_248) @[axi4_to_ahb.scala 177:48] - node _T_250 = bits(_T_240, 2, 2) @[axi4_to_ahb.scala 177:44] - node _T_251 = geq(UInt<2>("h02"), _T_243) @[axi4_to_ahb.scala 177:62] - node _T_252 = and(_T_250, _T_251) @[axi4_to_ahb.scala 177:48] - node _T_253 = bits(_T_240, 3, 3) @[axi4_to_ahb.scala 177:44] - node _T_254 = geq(UInt<2>("h03"), _T_243) @[axi4_to_ahb.scala 177:62] - node _T_255 = and(_T_253, _T_254) @[axi4_to_ahb.scala 177:48] - node _T_256 = bits(_T_240, 4, 4) @[axi4_to_ahb.scala 177:44] - node _T_257 = geq(UInt<3>("h04"), _T_243) @[axi4_to_ahb.scala 177:62] - node _T_258 = and(_T_256, _T_257) @[axi4_to_ahb.scala 177:48] - node _T_259 = bits(_T_240, 5, 5) @[axi4_to_ahb.scala 177:44] - node _T_260 = geq(UInt<3>("h05"), _T_243) @[axi4_to_ahb.scala 177:62] - node _T_261 = and(_T_259, _T_260) @[axi4_to_ahb.scala 177:48] - node _T_262 = bits(_T_240, 6, 6) @[axi4_to_ahb.scala 177:44] - node _T_263 = geq(UInt<3>("h06"), _T_243) @[axi4_to_ahb.scala 177:62] - node _T_264 = and(_T_262, _T_263) @[axi4_to_ahb.scala 177:48] - node _T_265 = bits(_T_240, 7, 7) @[axi4_to_ahb.scala 177:44] - node _T_266 = geq(UInt<3>("h07"), _T_243) @[axi4_to_ahb.scala 177:62] - node _T_267 = and(_T_265, _T_266) @[axi4_to_ahb.scala 177:48] - node _T_268 = mux(_T_267, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_269 = mux(_T_264, UInt<3>("h06"), _T_268) @[Mux.scala 98:16] - node _T_270 = mux(_T_261, UInt<3>("h05"), _T_269) @[Mux.scala 98:16] - node _T_271 = mux(_T_258, UInt<3>("h04"), _T_270) @[Mux.scala 98:16] - node _T_272 = mux(_T_255, UInt<2>("h03"), _T_271) @[Mux.scala 98:16] - node _T_273 = mux(_T_252, UInt<2>("h02"), _T_272) @[Mux.scala 98:16] - node _T_274 = mux(_T_249, UInt<1>("h01"), _T_273) @[Mux.scala 98:16] - node _T_275 = mux(_T_246, UInt<1>("h00"), _T_274) @[Mux.scala 98:16] - node _T_276 = dshr(buf_byteen, _T_275) @[axi4_to_ahb.scala 291:92] - node _T_277 = bits(_T_276, 0, 0) @[axi4_to_ahb.scala 291:92] - node _T_278 = eq(_T_277, UInt<1>("h00")) @[axi4_to_ahb.scala 291:163] - node _T_279 = or(_T_238, _T_278) @[axi4_to_ahb.scala 291:79] - node _T_280 = and(trxn_done, _T_279) @[axi4_to_ahb.scala 291:29] - cmd_done <= _T_280 @[axi4_to_ahb.scala 291:16] - node _T_281 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 292:43] - node _T_282 = eq(_T_281, UInt<1>("h00")) @[axi4_to_ahb.scala 292:32] - node _T_283 = bits(_T_282, 0, 0) @[Bitwise.scala 72:15] - node _T_284 = mux(_T_283, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_285 = and(_T_284, UInt<2>("h02")) @[axi4_to_ahb.scala 292:57] - io.ahb_htrans <= _T_285 @[axi4_to_ahb.scala 292:21] + node _T_247 = mux(_T_246, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_248 = mux(_T_243, UInt<3>("h06"), _T_247) @[Mux.scala 98:16] + node _T_249 = mux(_T_240, UInt<3>("h05"), _T_248) @[Mux.scala 98:16] + node _T_250 = mux(_T_237, UInt<3>("h04"), _T_249) @[Mux.scala 98:16] + node _T_251 = mux(_T_234, UInt<2>("h03"), _T_250) @[Mux.scala 98:16] + node _T_252 = mux(_T_231, UInt<2>("h02"), _T_251) @[Mux.scala 98:16] + node _T_253 = mux(_T_228, UInt<1>("h01"), _T_252) @[Mux.scala 98:16] + node _T_254 = mux(_T_225, UInt<1>("h00"), _T_253) @[Mux.scala 98:16] + node _T_255 = dshr(buf_byteen, _T_254) @[axi4_to_ahb.scala 306:92] + node _T_256 = bits(_T_255, 0, 0) @[axi4_to_ahb.scala 306:92] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[axi4_to_ahb.scala 306:163] + node _T_258 = or(_T_217, _T_257) @[axi4_to_ahb.scala 306:79] + node _T_259 = and(trxn_done, _T_258) @[axi4_to_ahb.scala 306:29] + cmd_done <= _T_259 @[axi4_to_ahb.scala 306:16] + node _T_260 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 307:43] + node _T_261 = eq(_T_260, UInt<1>("h00")) @[axi4_to_ahb.scala 307:32] + node _T_262 = bits(_T_261, 0, 0) @[Bitwise.scala 72:15] + node _T_263 = mux(_T_262, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_264 = and(_T_263, UInt<2>("h02")) @[axi4_to_ahb.scala 307:57] + io.ahb_htrans <= _T_264 @[axi4_to_ahb.scala 307:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_286 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] - when _T_286 : @[Conditional.scala 39:67] - node _T_287 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 296:34] - node _T_288 = or(_T_287, ahb_hresp_q) @[axi4_to_ahb.scala 296:50] - buf_state_en <= _T_288 @[axi4_to_ahb.scala 296:20] - node _T_289 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 297:35] - node _T_290 = or(_T_289, ahb_hresp_q) @[axi4_to_ahb.scala 297:51] - node _T_291 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 297:68] - node _T_292 = and(_T_290, _T_291) @[axi4_to_ahb.scala 297:66] - node _T_293 = and(_T_292, slave_ready) @[axi4_to_ahb.scala 297:81] - master_ready <= _T_293 @[axi4_to_ahb.scala 297:20] - node _T_294 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 298:42] - node _T_295 = or(ahb_hresp_q, _T_294) @[axi4_to_ahb.scala 298:40] - node _T_296 = bits(_T_295, 0, 0) @[axi4_to_ahb.scala 298:62] - node _T_297 = and(master_valid, master_ready) @[axi4_to_ahb.scala 298:90] - node _T_298 = bits(_T_297, 0, 0) @[axi4_to_ahb.scala 298:112] - node _T_299 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 298:131] - node _T_300 = eq(_T_299, UInt<1>("h01")) @[axi4_to_ahb.scala 298:138] - node _T_301 = mux(_T_300, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 298:119] - node _T_302 = mux(_T_298, _T_301, UInt<3>("h00")) @[axi4_to_ahb.scala 298:75] - node _T_303 = mux(_T_296, UInt<3>("h05"), _T_302) @[axi4_to_ahb.scala 298:26] - buf_nxtstate <= _T_303 @[axi4_to_ahb.scala 298:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 299:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 300:23] - node _T_304 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 301:34] - node _T_305 = eq(_T_304, UInt<1>("h01")) @[axi4_to_ahb.scala 301:41] - buf_write_in <= _T_305 @[axi4_to_ahb.scala 301:20] - node _T_306 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 302:50] - node _T_307 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 302:78] - node _T_308 = or(_T_306, _T_307) @[axi4_to_ahb.scala 302:62] - node _T_309 = and(buf_state_en, _T_308) @[axi4_to_ahb.scala 302:33] - buf_wr_en <= _T_309 @[axi4_to_ahb.scala 302:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 303:22] - node _T_310 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 304:63] - node _T_311 = neq(_T_310, UInt<1>("h00")) @[axi4_to_ahb.scala 304:70] - node _T_312 = and(ahb_hready_q, _T_311) @[axi4_to_ahb.scala 304:48] - node _T_313 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 304:104] - node _T_314 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 304:166] - node _T_315 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 304:184] - node _T_316 = add(_T_314, UInt<1>("h01")) @[axi4_to_ahb.scala 176:52] - node _T_317 = tail(_T_316, 1) @[axi4_to_ahb.scala 176:52] - node _T_318 = mux(UInt<1>("h01"), _T_317, _T_314) @[axi4_to_ahb.scala 176:24] - node _T_319 = bits(_T_315, 0, 0) @[axi4_to_ahb.scala 177:44] - node _T_320 = geq(UInt<1>("h00"), _T_318) @[axi4_to_ahb.scala 177:62] + node _T_265 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] + when _T_265 : @[Conditional.scala 39:67] + node _T_266 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 311:34] + node _T_267 = or(_T_266, ahb_hresp_q) @[axi4_to_ahb.scala 311:50] + buf_state_en <= _T_267 @[axi4_to_ahb.scala 311:20] + node _T_268 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 312:37] + node _T_269 = or(_T_268, ahb_hresp_q) @[axi4_to_ahb.scala 312:53] + node _T_270 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 312:70] + node _T_271 = and(_T_269, _T_270) @[axi4_to_ahb.scala 312:68] + node _T_272 = and(_T_271, slave_ready) @[axi4_to_ahb.scala 312:83] + node _T_273 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 313:42] + node _T_274 = or(ahb_hresp_q, _T_273) @[axi4_to_ahb.scala 313:40] + node _T_275 = bits(_T_274, 0, 0) @[axi4_to_ahb.scala 313:62] + node _T_276 = and(master_valid, _T_272) @[axi4_to_ahb.scala 313:90] + node _T_277 = bits(_T_276, 0, 0) @[axi4_to_ahb.scala 313:112] + node _T_278 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 313:131] + node _T_279 = eq(_T_278, UInt<1>("h01")) @[axi4_to_ahb.scala 313:138] + node _T_280 = mux(_T_279, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 313:119] + node _T_281 = mux(_T_277, _T_280, UInt<3>("h00")) @[axi4_to_ahb.scala 313:75] + node _T_282 = mux(_T_275, UInt<3>("h05"), _T_281) @[axi4_to_ahb.scala 313:26] + buf_nxtstate <= _T_282 @[axi4_to_ahb.scala 313:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 314:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 315:23] + node _T_283 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 316:34] + node _T_284 = eq(_T_283, UInt<1>("h01")) @[axi4_to_ahb.scala 316:41] + buf_write_in <= _T_284 @[axi4_to_ahb.scala 316:20] + node _T_285 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 317:50] + node _T_286 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 317:78] + node _T_287 = or(_T_285, _T_286) @[axi4_to_ahb.scala 317:62] + node _T_288 = and(buf_state_en, _T_287) @[axi4_to_ahb.scala 317:33] + buf_wr_en <= _T_288 @[axi4_to_ahb.scala 317:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 318:22] + node _T_289 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 319:63] + node _T_290 = neq(_T_289, UInt<1>("h00")) @[axi4_to_ahb.scala 319:70] + node _T_291 = and(ahb_hready_q, _T_290) @[axi4_to_ahb.scala 319:48] + node _T_292 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 319:104] + node _T_293 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 319:166] + node _T_294 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 319:184] + node _T_295 = add(_T_293, UInt<1>("h01")) @[axi4_to_ahb.scala 176:52] + node _T_296 = tail(_T_295, 1) @[axi4_to_ahb.scala 176:52] + node _T_297 = mux(UInt<1>("h01"), _T_296, _T_293) @[axi4_to_ahb.scala 176:24] + node _T_298 = bits(_T_294, 0, 0) @[axi4_to_ahb.scala 177:44] + node _T_299 = geq(UInt<1>("h00"), _T_297) @[axi4_to_ahb.scala 177:62] + node _T_300 = and(_T_298, _T_299) @[axi4_to_ahb.scala 177:48] + node _T_301 = bits(_T_294, 1, 1) @[axi4_to_ahb.scala 177:44] + node _T_302 = geq(UInt<1>("h01"), _T_297) @[axi4_to_ahb.scala 177:62] + node _T_303 = and(_T_301, _T_302) @[axi4_to_ahb.scala 177:48] + node _T_304 = bits(_T_294, 2, 2) @[axi4_to_ahb.scala 177:44] + node _T_305 = geq(UInt<2>("h02"), _T_297) @[axi4_to_ahb.scala 177:62] + node _T_306 = and(_T_304, _T_305) @[axi4_to_ahb.scala 177:48] + node _T_307 = bits(_T_294, 3, 3) @[axi4_to_ahb.scala 177:44] + node _T_308 = geq(UInt<2>("h03"), _T_297) @[axi4_to_ahb.scala 177:62] + node _T_309 = and(_T_307, _T_308) @[axi4_to_ahb.scala 177:48] + node _T_310 = bits(_T_294, 4, 4) @[axi4_to_ahb.scala 177:44] + node _T_311 = geq(UInt<3>("h04"), _T_297) @[axi4_to_ahb.scala 177:62] + node _T_312 = and(_T_310, _T_311) @[axi4_to_ahb.scala 177:48] + node _T_313 = bits(_T_294, 5, 5) @[axi4_to_ahb.scala 177:44] + node _T_314 = geq(UInt<3>("h05"), _T_297) @[axi4_to_ahb.scala 177:62] + node _T_315 = and(_T_313, _T_314) @[axi4_to_ahb.scala 177:48] + node _T_316 = bits(_T_294, 6, 6) @[axi4_to_ahb.scala 177:44] + node _T_317 = geq(UInt<3>("h06"), _T_297) @[axi4_to_ahb.scala 177:62] + node _T_318 = and(_T_316, _T_317) @[axi4_to_ahb.scala 177:48] + node _T_319 = bits(_T_294, 7, 7) @[axi4_to_ahb.scala 177:44] + node _T_320 = geq(UInt<3>("h07"), _T_297) @[axi4_to_ahb.scala 177:62] node _T_321 = and(_T_319, _T_320) @[axi4_to_ahb.scala 177:48] - node _T_322 = bits(_T_315, 1, 1) @[axi4_to_ahb.scala 177:44] - node _T_323 = geq(UInt<1>("h01"), _T_318) @[axi4_to_ahb.scala 177:62] - node _T_324 = and(_T_322, _T_323) @[axi4_to_ahb.scala 177:48] - node _T_325 = bits(_T_315, 2, 2) @[axi4_to_ahb.scala 177:44] - node _T_326 = geq(UInt<2>("h02"), _T_318) @[axi4_to_ahb.scala 177:62] - node _T_327 = and(_T_325, _T_326) @[axi4_to_ahb.scala 177:48] - node _T_328 = bits(_T_315, 3, 3) @[axi4_to_ahb.scala 177:44] - node _T_329 = geq(UInt<2>("h03"), _T_318) @[axi4_to_ahb.scala 177:62] - node _T_330 = and(_T_328, _T_329) @[axi4_to_ahb.scala 177:48] - node _T_331 = bits(_T_315, 4, 4) @[axi4_to_ahb.scala 177:44] - node _T_332 = geq(UInt<3>("h04"), _T_318) @[axi4_to_ahb.scala 177:62] - node _T_333 = and(_T_331, _T_332) @[axi4_to_ahb.scala 177:48] - node _T_334 = bits(_T_315, 5, 5) @[axi4_to_ahb.scala 177:44] - node _T_335 = geq(UInt<3>("h05"), _T_318) @[axi4_to_ahb.scala 177:62] - node _T_336 = and(_T_334, _T_335) @[axi4_to_ahb.scala 177:48] - node _T_337 = bits(_T_315, 6, 6) @[axi4_to_ahb.scala 177:44] - node _T_338 = geq(UInt<3>("h06"), _T_318) @[axi4_to_ahb.scala 177:62] - node _T_339 = and(_T_337, _T_338) @[axi4_to_ahb.scala 177:48] - node _T_340 = bits(_T_315, 7, 7) @[axi4_to_ahb.scala 177:44] - node _T_341 = geq(UInt<3>("h07"), _T_318) @[axi4_to_ahb.scala 177:62] - node _T_342 = and(_T_340, _T_341) @[axi4_to_ahb.scala 177:48] - node _T_343 = mux(_T_342, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_344 = mux(_T_339, UInt<3>("h06"), _T_343) @[Mux.scala 98:16] - node _T_345 = mux(_T_336, UInt<3>("h05"), _T_344) @[Mux.scala 98:16] - node _T_346 = mux(_T_333, UInt<3>("h04"), _T_345) @[Mux.scala 98:16] - node _T_347 = mux(_T_330, UInt<2>("h03"), _T_346) @[Mux.scala 98:16] - node _T_348 = mux(_T_327, UInt<2>("h02"), _T_347) @[Mux.scala 98:16] - node _T_349 = mux(_T_324, UInt<1>("h01"), _T_348) @[Mux.scala 98:16] - node _T_350 = mux(_T_321, UInt<1>("h00"), _T_349) @[Mux.scala 98:16] - node _T_351 = dshr(buf_byteen, _T_350) @[axi4_to_ahb.scala 304:131] - node _T_352 = bits(_T_351, 0, 0) @[axi4_to_ahb.scala 304:131] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 304:202] - node _T_354 = or(_T_313, _T_353) @[axi4_to_ahb.scala 304:118] - node _T_355 = and(_T_312, _T_354) @[axi4_to_ahb.scala 304:82] - node _T_356 = or(ahb_hresp_q, _T_355) @[axi4_to_ahb.scala 304:32] - cmd_done <= _T_356 @[axi4_to_ahb.scala 304:16] - node _T_357 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 305:33] - node _T_358 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 305:64] - node _T_359 = and(_T_357, _T_358) @[axi4_to_ahb.scala 305:48] - bypass_en <= _T_359 @[axi4_to_ahb.scala 305:17] - node _T_360 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 306:44] - node _T_361 = eq(_T_360, UInt<1>("h00")) @[axi4_to_ahb.scala 306:33] - node _T_362 = or(_T_361, bypass_en) @[axi4_to_ahb.scala 306:57] - node _T_363 = bits(_T_362, 0, 0) @[Bitwise.scala 72:15] - node _T_364 = mux(_T_363, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_365 = and(_T_364, UInt<2>("h02")) @[axi4_to_ahb.scala 306:71] - io.ahb_htrans <= _T_365 @[axi4_to_ahb.scala 306:21] - node _T_366 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 307:55] - node _T_367 = and(buf_state_en, _T_366) @[axi4_to_ahb.scala 307:39] - slave_valid_pre <= _T_367 @[axi4_to_ahb.scala 307:23] - node _T_368 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 308:33] - node _T_369 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 308:63] - node _T_370 = neq(_T_369, UInt<1>("h00")) @[axi4_to_ahb.scala 308:70] - node _T_371 = and(_T_368, _T_370) @[axi4_to_ahb.scala 308:48] - trxn_done <= _T_371 @[axi4_to_ahb.scala 308:17] - node _T_372 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 309:40] - buf_cmd_byte_ptr_en <= _T_372 @[axi4_to_ahb.scala 309:27] - node _T_373 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_374 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 312:85] - node _T_375 = add(_T_373, UInt<1>("h01")) @[axi4_to_ahb.scala 176:52] - node _T_376 = tail(_T_375, 1) @[axi4_to_ahb.scala 176:52] - node _T_377 = mux(UInt<1>("h00"), _T_376, _T_373) @[axi4_to_ahb.scala 176:24] - node _T_378 = bits(_T_374, 0, 0) @[axi4_to_ahb.scala 177:44] - node _T_379 = geq(UInt<1>("h00"), _T_377) @[axi4_to_ahb.scala 177:62] + node _T_322 = mux(_T_321, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_323 = mux(_T_318, UInt<3>("h06"), _T_322) @[Mux.scala 98:16] + node _T_324 = mux(_T_315, UInt<3>("h05"), _T_323) @[Mux.scala 98:16] + node _T_325 = mux(_T_312, UInt<3>("h04"), _T_324) @[Mux.scala 98:16] + node _T_326 = mux(_T_309, UInt<2>("h03"), _T_325) @[Mux.scala 98:16] + node _T_327 = mux(_T_306, UInt<2>("h02"), _T_326) @[Mux.scala 98:16] + node _T_328 = mux(_T_303, UInt<1>("h01"), _T_327) @[Mux.scala 98:16] + node _T_329 = mux(_T_300, UInt<1>("h00"), _T_328) @[Mux.scala 98:16] + node _T_330 = dshr(buf_byteen, _T_329) @[axi4_to_ahb.scala 319:131] + node _T_331 = bits(_T_330, 0, 0) @[axi4_to_ahb.scala 319:131] + node _T_332 = eq(_T_331, UInt<1>("h00")) @[axi4_to_ahb.scala 319:202] + node _T_333 = or(_T_292, _T_332) @[axi4_to_ahb.scala 319:118] + node _T_334 = and(_T_291, _T_333) @[axi4_to_ahb.scala 319:82] + node _T_335 = or(ahb_hresp_q, _T_334) @[axi4_to_ahb.scala 319:32] + cmd_done <= _T_335 @[axi4_to_ahb.scala 319:16] + node _T_336 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 320:33] + node _T_337 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 320:64] + node _T_338 = and(_T_336, _T_337) @[axi4_to_ahb.scala 320:48] + bypass_en <= _T_338 @[axi4_to_ahb.scala 320:17] + node _T_339 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 321:44] + node _T_340 = eq(_T_339, UInt<1>("h00")) @[axi4_to_ahb.scala 321:33] + node _T_341 = or(_T_340, bypass_en) @[axi4_to_ahb.scala 321:57] + node _T_342 = bits(_T_341, 0, 0) @[Bitwise.scala 72:15] + node _T_343 = mux(_T_342, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_344 = and(_T_343, UInt<2>("h02")) @[axi4_to_ahb.scala 321:71] + io.ahb_htrans <= _T_344 @[axi4_to_ahb.scala 321:21] + node _T_345 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 322:55] + node _T_346 = and(buf_state_en, _T_345) @[axi4_to_ahb.scala 322:39] + slave_valid_pre <= _T_346 @[axi4_to_ahb.scala 322:23] + node _T_347 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 323:33] + node _T_348 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 323:63] + node _T_349 = neq(_T_348, UInt<1>("h00")) @[axi4_to_ahb.scala 323:70] + node _T_350 = and(_T_347, _T_349) @[axi4_to_ahb.scala 323:48] + trxn_done <= _T_350 @[axi4_to_ahb.scala 323:17] + node _T_351 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 324:40] + buf_cmd_byte_ptr_en <= _T_351 @[axi4_to_ahb.scala 324:27] + node _T_352 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_353 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 327:85] + node _T_354 = add(_T_352, UInt<1>("h01")) @[axi4_to_ahb.scala 176:52] + node _T_355 = tail(_T_354, 1) @[axi4_to_ahb.scala 176:52] + node _T_356 = mux(UInt<1>("h00"), _T_355, _T_352) @[axi4_to_ahb.scala 176:24] + node _T_357 = bits(_T_353, 0, 0) @[axi4_to_ahb.scala 177:44] + node _T_358 = geq(UInt<1>("h00"), _T_356) @[axi4_to_ahb.scala 177:62] + node _T_359 = and(_T_357, _T_358) @[axi4_to_ahb.scala 177:48] + node _T_360 = bits(_T_353, 1, 1) @[axi4_to_ahb.scala 177:44] + node _T_361 = geq(UInt<1>("h01"), _T_356) @[axi4_to_ahb.scala 177:62] + node _T_362 = and(_T_360, _T_361) @[axi4_to_ahb.scala 177:48] + node _T_363 = bits(_T_353, 2, 2) @[axi4_to_ahb.scala 177:44] + node _T_364 = geq(UInt<2>("h02"), _T_356) @[axi4_to_ahb.scala 177:62] + node _T_365 = and(_T_363, _T_364) @[axi4_to_ahb.scala 177:48] + node _T_366 = bits(_T_353, 3, 3) @[axi4_to_ahb.scala 177:44] + node _T_367 = geq(UInt<2>("h03"), _T_356) @[axi4_to_ahb.scala 177:62] + node _T_368 = and(_T_366, _T_367) @[axi4_to_ahb.scala 177:48] + node _T_369 = bits(_T_353, 4, 4) @[axi4_to_ahb.scala 177:44] + node _T_370 = geq(UInt<3>("h04"), _T_356) @[axi4_to_ahb.scala 177:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 177:48] + node _T_372 = bits(_T_353, 5, 5) @[axi4_to_ahb.scala 177:44] + node _T_373 = geq(UInt<3>("h05"), _T_356) @[axi4_to_ahb.scala 177:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 177:48] + node _T_375 = bits(_T_353, 6, 6) @[axi4_to_ahb.scala 177:44] + node _T_376 = geq(UInt<3>("h06"), _T_356) @[axi4_to_ahb.scala 177:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 177:48] + node _T_378 = bits(_T_353, 7, 7) @[axi4_to_ahb.scala 177:44] + node _T_379 = geq(UInt<3>("h07"), _T_356) @[axi4_to_ahb.scala 177:62] node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 177:48] - node _T_381 = bits(_T_374, 1, 1) @[axi4_to_ahb.scala 177:44] - node _T_382 = geq(UInt<1>("h01"), _T_377) @[axi4_to_ahb.scala 177:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 177:48] - node _T_384 = bits(_T_374, 2, 2) @[axi4_to_ahb.scala 177:44] - node _T_385 = geq(UInt<2>("h02"), _T_377) @[axi4_to_ahb.scala 177:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 177:48] - node _T_387 = bits(_T_374, 3, 3) @[axi4_to_ahb.scala 177:44] - node _T_388 = geq(UInt<2>("h03"), _T_377) @[axi4_to_ahb.scala 177:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 177:48] - node _T_390 = bits(_T_374, 4, 4) @[axi4_to_ahb.scala 177:44] - node _T_391 = geq(UInt<3>("h04"), _T_377) @[axi4_to_ahb.scala 177:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 177:48] - node _T_393 = bits(_T_374, 5, 5) @[axi4_to_ahb.scala 177:44] - node _T_394 = geq(UInt<3>("h05"), _T_377) @[axi4_to_ahb.scala 177:62] - node _T_395 = and(_T_393, _T_394) @[axi4_to_ahb.scala 177:48] - node _T_396 = bits(_T_374, 6, 6) @[axi4_to_ahb.scala 177:44] - node _T_397 = geq(UInt<3>("h06"), _T_377) @[axi4_to_ahb.scala 177:62] - node _T_398 = and(_T_396, _T_397) @[axi4_to_ahb.scala 177:48] - node _T_399 = bits(_T_374, 7, 7) @[axi4_to_ahb.scala 177:44] - node _T_400 = geq(UInt<3>("h07"), _T_377) @[axi4_to_ahb.scala 177:62] - node _T_401 = and(_T_399, _T_400) @[axi4_to_ahb.scala 177:48] - node _T_402 = mux(_T_401, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_403 = mux(_T_398, UInt<3>("h06"), _T_402) @[Mux.scala 98:16] - node _T_404 = mux(_T_395, UInt<3>("h05"), _T_403) @[Mux.scala 98:16] - node _T_405 = mux(_T_392, UInt<3>("h04"), _T_404) @[Mux.scala 98:16] - node _T_406 = mux(_T_389, UInt<2>("h03"), _T_405) @[Mux.scala 98:16] - node _T_407 = mux(_T_386, UInt<2>("h02"), _T_406) @[Mux.scala 98:16] - node _T_408 = mux(_T_383, UInt<1>("h01"), _T_407) @[Mux.scala 98:16] - node _T_409 = mux(_T_380, UInt<1>("h00"), _T_408) @[Mux.scala 98:16] - node _T_410 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 312:151] - node _T_411 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 312:169] - node _T_412 = add(_T_410, UInt<1>("h01")) @[axi4_to_ahb.scala 176:52] - node _T_413 = tail(_T_412, 1) @[axi4_to_ahb.scala 176:52] - node _T_414 = mux(UInt<1>("h01"), _T_413, _T_410) @[axi4_to_ahb.scala 176:24] - node _T_415 = bits(_T_411, 0, 0) @[axi4_to_ahb.scala 177:44] - node _T_416 = geq(UInt<1>("h00"), _T_414) @[axi4_to_ahb.scala 177:62] + node _T_381 = mux(_T_380, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_382 = mux(_T_377, UInt<3>("h06"), _T_381) @[Mux.scala 98:16] + node _T_383 = mux(_T_374, UInt<3>("h05"), _T_382) @[Mux.scala 98:16] + node _T_384 = mux(_T_371, UInt<3>("h04"), _T_383) @[Mux.scala 98:16] + node _T_385 = mux(_T_368, UInt<2>("h03"), _T_384) @[Mux.scala 98:16] + node _T_386 = mux(_T_365, UInt<2>("h02"), _T_385) @[Mux.scala 98:16] + node _T_387 = mux(_T_362, UInt<1>("h01"), _T_386) @[Mux.scala 98:16] + node _T_388 = mux(_T_359, UInt<1>("h00"), _T_387) @[Mux.scala 98:16] + node _T_389 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 327:151] + node _T_390 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 327:169] + node _T_391 = add(_T_389, UInt<1>("h01")) @[axi4_to_ahb.scala 176:52] + node _T_392 = tail(_T_391, 1) @[axi4_to_ahb.scala 176:52] + node _T_393 = mux(UInt<1>("h01"), _T_392, _T_389) @[axi4_to_ahb.scala 176:24] + node _T_394 = bits(_T_390, 0, 0) @[axi4_to_ahb.scala 177:44] + node _T_395 = geq(UInt<1>("h00"), _T_393) @[axi4_to_ahb.scala 177:62] + node _T_396 = and(_T_394, _T_395) @[axi4_to_ahb.scala 177:48] + node _T_397 = bits(_T_390, 1, 1) @[axi4_to_ahb.scala 177:44] + node _T_398 = geq(UInt<1>("h01"), _T_393) @[axi4_to_ahb.scala 177:62] + node _T_399 = and(_T_397, _T_398) @[axi4_to_ahb.scala 177:48] + node _T_400 = bits(_T_390, 2, 2) @[axi4_to_ahb.scala 177:44] + node _T_401 = geq(UInt<2>("h02"), _T_393) @[axi4_to_ahb.scala 177:62] + node _T_402 = and(_T_400, _T_401) @[axi4_to_ahb.scala 177:48] + node _T_403 = bits(_T_390, 3, 3) @[axi4_to_ahb.scala 177:44] + node _T_404 = geq(UInt<2>("h03"), _T_393) @[axi4_to_ahb.scala 177:62] + node _T_405 = and(_T_403, _T_404) @[axi4_to_ahb.scala 177:48] + node _T_406 = bits(_T_390, 4, 4) @[axi4_to_ahb.scala 177:44] + node _T_407 = geq(UInt<3>("h04"), _T_393) @[axi4_to_ahb.scala 177:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 177:48] + node _T_409 = bits(_T_390, 5, 5) @[axi4_to_ahb.scala 177:44] + node _T_410 = geq(UInt<3>("h05"), _T_393) @[axi4_to_ahb.scala 177:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 177:48] + node _T_412 = bits(_T_390, 6, 6) @[axi4_to_ahb.scala 177:44] + node _T_413 = geq(UInt<3>("h06"), _T_393) @[axi4_to_ahb.scala 177:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 177:48] + node _T_415 = bits(_T_390, 7, 7) @[axi4_to_ahb.scala 177:44] + node _T_416 = geq(UInt<3>("h07"), _T_393) @[axi4_to_ahb.scala 177:62] node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 177:48] - node _T_418 = bits(_T_411, 1, 1) @[axi4_to_ahb.scala 177:44] - node _T_419 = geq(UInt<1>("h01"), _T_414) @[axi4_to_ahb.scala 177:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 177:48] - node _T_421 = bits(_T_411, 2, 2) @[axi4_to_ahb.scala 177:44] - node _T_422 = geq(UInt<2>("h02"), _T_414) @[axi4_to_ahb.scala 177:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 177:48] - node _T_424 = bits(_T_411, 3, 3) @[axi4_to_ahb.scala 177:44] - node _T_425 = geq(UInt<2>("h03"), _T_414) @[axi4_to_ahb.scala 177:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 177:48] - node _T_427 = bits(_T_411, 4, 4) @[axi4_to_ahb.scala 177:44] - node _T_428 = geq(UInt<3>("h04"), _T_414) @[axi4_to_ahb.scala 177:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 177:48] - node _T_430 = bits(_T_411, 5, 5) @[axi4_to_ahb.scala 177:44] - node _T_431 = geq(UInt<3>("h05"), _T_414) @[axi4_to_ahb.scala 177:62] - node _T_432 = and(_T_430, _T_431) @[axi4_to_ahb.scala 177:48] - node _T_433 = bits(_T_411, 6, 6) @[axi4_to_ahb.scala 177:44] - node _T_434 = geq(UInt<3>("h06"), _T_414) @[axi4_to_ahb.scala 177:62] - node _T_435 = and(_T_433, _T_434) @[axi4_to_ahb.scala 177:48] - node _T_436 = bits(_T_411, 7, 7) @[axi4_to_ahb.scala 177:44] - node _T_437 = geq(UInt<3>("h07"), _T_414) @[axi4_to_ahb.scala 177:62] - node _T_438 = and(_T_436, _T_437) @[axi4_to_ahb.scala 177:48] - node _T_439 = mux(_T_438, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_440 = mux(_T_435, UInt<3>("h06"), _T_439) @[Mux.scala 98:16] - node _T_441 = mux(_T_432, UInt<3>("h05"), _T_440) @[Mux.scala 98:16] - node _T_442 = mux(_T_429, UInt<3>("h04"), _T_441) @[Mux.scala 98:16] - node _T_443 = mux(_T_426, UInt<2>("h03"), _T_442) @[Mux.scala 98:16] - node _T_444 = mux(_T_423, UInt<2>("h02"), _T_443) @[Mux.scala 98:16] - node _T_445 = mux(_T_420, UInt<1>("h01"), _T_444) @[Mux.scala 98:16] - node _T_446 = mux(_T_417, UInt<1>("h00"), _T_445) @[Mux.scala 98:16] - node _T_447 = mux(trxn_done, _T_446, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 312:106] - node _T_448 = mux(bypass_en, _T_409, _T_447) @[axi4_to_ahb.scala 312:30] - buf_cmd_byte_ptr <= _T_448 @[axi4_to_ahb.scala 312:24] + node _T_418 = mux(_T_417, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_419 = mux(_T_414, UInt<3>("h06"), _T_418) @[Mux.scala 98:16] + node _T_420 = mux(_T_411, UInt<3>("h05"), _T_419) @[Mux.scala 98:16] + node _T_421 = mux(_T_408, UInt<3>("h04"), _T_420) @[Mux.scala 98:16] + node _T_422 = mux(_T_405, UInt<2>("h03"), _T_421) @[Mux.scala 98:16] + node _T_423 = mux(_T_402, UInt<2>("h02"), _T_422) @[Mux.scala 98:16] + node _T_424 = mux(_T_399, UInt<1>("h01"), _T_423) @[Mux.scala 98:16] + node _T_425 = mux(_T_396, UInt<1>("h00"), _T_424) @[Mux.scala 98:16] + node _T_426 = mux(trxn_done, _T_425, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 327:106] + node _T_427 = mux(bypass_en, _T_388, _T_426) @[axi4_to_ahb.scala 327:30] + buf_cmd_byte_ptr <= _T_427 @[axi4_to_ahb.scala 327:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_449 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] - when _T_449 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 315:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 316:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 317:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 318:23] + node _T_428 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] + when _T_428 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 330:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 331:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 332:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 333:23] skip @[Conditional.scala 39:67] - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 322:11] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 323:16] - node _T_450 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 324:68] - node _T_451 = eq(_T_450, UInt<1>("h01")) @[axi4_to_ahb.scala 324:75] - node _T_452 = and(buf_aligned_in, _T_451) @[axi4_to_ahb.scala 324:55] - node _T_453 = bits(_T_452, 0, 0) @[axi4_to_ahb.scala 324:95] - node _T_454 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 324:127] - wire _T_455 : UInt<8> - _T_455 <= UInt<8>("h00") - node _T_456 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 168:44] - node _T_457 = eq(_T_456, UInt<8>("h0ff")) @[axi4_to_ahb.scala 168:51] - node _T_458 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 168:75] - node _T_459 = eq(_T_458, UInt<4>("h0f")) @[axi4_to_ahb.scala 168:82] - node _T_460 = or(_T_457, _T_459) @[axi4_to_ahb.scala 168:64] - node _T_461 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 168:106] - node _T_462 = eq(_T_461, UInt<2>("h03")) @[axi4_to_ahb.scala 168:113] - node _T_463 = or(_T_460, _T_462) @[axi4_to_ahb.scala 168:95] - node _T_464 = bits(_T_463, 0, 0) @[Bitwise.scala 72:15] - node _T_465 = mux(_T_464, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_466 = and(UInt<1>("h00"), _T_465) @[axi4_to_ahb.scala 168:24] - node _T_467 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 169:35] - node _T_468 = eq(_T_467, UInt<4>("h0c")) @[axi4_to_ahb.scala 169:42] - node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] - node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_471 = and(UInt<2>("h02"), _T_470) @[axi4_to_ahb.scala 169:15] - node _T_472 = or(_T_466, _T_471) @[axi4_to_ahb.scala 168:128] - node _T_473 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 170:36] - node _T_474 = eq(_T_473, UInt<8>("h0f0")) @[axi4_to_ahb.scala 170:43] - node _T_475 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 170:67] - node _T_476 = eq(_T_475, UInt<2>("h03")) @[axi4_to_ahb.scala 170:74] - node _T_477 = or(_T_474, _T_476) @[axi4_to_ahb.scala 170:56] - node _T_478 = bits(_T_477, 0, 0) @[Bitwise.scala 72:15] - node _T_479 = mux(_T_478, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_480 = and(UInt<3>("h04"), _T_479) @[axi4_to_ahb.scala 170:15] - node _T_481 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 171:37] - node _T_482 = eq(_T_481, UInt<8>("h0c0")) @[axi4_to_ahb.scala 171:44] - node _T_483 = bits(_T_482, 0, 0) @[Bitwise.scala 72:15] - node _T_484 = mux(_T_483, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_485 = and(UInt<3>("h06"), _T_484) @[axi4_to_ahb.scala 171:17] - node _T_486 = or(_T_480, _T_485) @[axi4_to_ahb.scala 170:90] - node _T_487 = or(_T_472, _T_486) @[axi4_to_ahb.scala 169:58] - node _T_488 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 324:147] - node _T_489 = mux(_T_453, _T_487, _T_488) @[axi4_to_ahb.scala 324:38] - node _T_490 = cat(master_addr, _T_489) @[Cat.scala 29:58] - buf_addr_in <= _T_490 @[axi4_to_ahb.scala 324:15] - node _T_491 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 325:27] - buf_tag_in <= _T_491 @[axi4_to_ahb.scala 325:14] - node _T_492 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 326:32] - buf_byteen_in <= _T_492 @[axi4_to_ahb.scala 326:17] - node _T_493 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 327:33] - node _T_494 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 327:59] - node _T_495 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 327:80] - node _T_496 = mux(_T_493, _T_494, _T_495) @[axi4_to_ahb.scala 327:21] - buf_data_in <= _T_496 @[axi4_to_ahb.scala 327:15] - node _T_497 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 328:52] - node _T_498 = eq(_T_497, UInt<2>("h03")) @[axi4_to_ahb.scala 328:59] - node _T_499 = and(buf_aligned_in, _T_498) @[axi4_to_ahb.scala 328:38] - node _T_500 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 328:85] - node _T_501 = eq(_T_500, UInt<1>("h01")) @[axi4_to_ahb.scala 328:92] - node _T_502 = and(_T_499, _T_501) @[axi4_to_ahb.scala 328:72] - node _T_503 = bits(_T_502, 0, 0) @[axi4_to_ahb.scala 328:112] - node _T_504 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 328:144] - wire _T_505 : UInt<8> - _T_505 <= UInt<8>("h00") - node _T_506 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 160:43] - node _T_507 = eq(_T_506, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:50] - node _T_508 = bits(_T_507, 0, 0) @[Bitwise.scala 72:15] - node _T_509 = mux(_T_508, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_510 = and(UInt<2>("h03"), _T_509) @[axi4_to_ahb.scala 160:25] - node _T_511 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 161:34] - node _T_512 = eq(_T_511, UInt<8>("h0f0")) @[axi4_to_ahb.scala 161:41] - node _T_513 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 161:63] - node _T_514 = eq(_T_513, UInt<4>("h0f")) @[axi4_to_ahb.scala 161:70] - node _T_515 = or(_T_512, _T_514) @[axi4_to_ahb.scala 161:54] - node _T_516 = bits(_T_515, 0, 0) @[Bitwise.scala 72:15] - node _T_517 = mux(_T_516, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_518 = and(UInt<2>("h02"), _T_517) @[axi4_to_ahb.scala 161:16] - node _T_519 = or(_T_510, _T_518) @[axi4_to_ahb.scala 160:65] - node _T_520 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 162:34] - node _T_521 = eq(_T_520, UInt<8>("h0c0")) @[axi4_to_ahb.scala 162:41] - node _T_522 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 162:63] - node _T_523 = eq(_T_522, UInt<6>("h030")) @[axi4_to_ahb.scala 162:70] - node _T_524 = or(_T_521, _T_523) @[axi4_to_ahb.scala 162:54] - node _T_525 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 162:92] - node _T_526 = eq(_T_525, UInt<4>("h0c")) @[axi4_to_ahb.scala 162:99] - node _T_527 = or(_T_524, _T_526) @[axi4_to_ahb.scala 162:83] - node _T_528 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 162:121] - node _T_529 = eq(_T_528, UInt<2>("h03")) @[axi4_to_ahb.scala 162:128] - node _T_530 = or(_T_527, _T_529) @[axi4_to_ahb.scala 162:112] - node _T_531 = bits(_T_530, 0, 0) @[Bitwise.scala 72:15] - node _T_532 = mux(_T_531, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_533 = and(UInt<1>("h01"), _T_532) @[axi4_to_ahb.scala 162:16] - node _T_534 = or(_T_519, _T_533) @[axi4_to_ahb.scala 161:86] - node _T_535 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 328:164] - node _T_536 = mux(_T_503, _T_534, _T_535) @[axi4_to_ahb.scala 328:21] - buf_size_in <= _T_536 @[axi4_to_ahb.scala 328:15] - node _T_537 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 329:32] - node _T_538 = eq(_T_537, UInt<1>("h00")) @[axi4_to_ahb.scala 329:39] - node _T_539 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 330:17] - node _T_540 = eq(_T_539, UInt<1>("h00")) @[axi4_to_ahb.scala 330:24] - node _T_541 = or(_T_538, _T_540) @[axi4_to_ahb.scala 329:51] - node _T_542 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 330:50] - node _T_543 = eq(_T_542, UInt<1>("h01")) @[axi4_to_ahb.scala 330:57] - node _T_544 = or(_T_541, _T_543) @[axi4_to_ahb.scala 330:36] - node _T_545 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 330:84] - node _T_546 = eq(_T_545, UInt<2>("h02")) @[axi4_to_ahb.scala 330:91] - node _T_547 = or(_T_544, _T_546) @[axi4_to_ahb.scala 330:70] - node _T_548 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 331:18] - node _T_549 = eq(_T_548, UInt<2>("h03")) @[axi4_to_ahb.scala 331:25] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 331:55] - node _T_551 = eq(_T_550, UInt<2>("h03")) @[axi4_to_ahb.scala 331:62] - node _T_552 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 331:90] - node _T_553 = eq(_T_552, UInt<4>("h0c")) @[axi4_to_ahb.scala 331:97] - node _T_554 = or(_T_551, _T_553) @[axi4_to_ahb.scala 331:74] - node _T_555 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 331:125] - node _T_556 = eq(_T_555, UInt<6>("h030")) @[axi4_to_ahb.scala 331:132] - node _T_557 = or(_T_554, _T_556) @[axi4_to_ahb.scala 331:109] - node _T_558 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 331:161] - node _T_559 = eq(_T_558, UInt<8>("h0c0")) @[axi4_to_ahb.scala 331:168] - node _T_560 = or(_T_557, _T_559) @[axi4_to_ahb.scala 331:145] - node _T_561 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 332:21] - node _T_562 = eq(_T_561, UInt<4>("h0f")) @[axi4_to_ahb.scala 332:28] - node _T_563 = or(_T_560, _T_562) @[axi4_to_ahb.scala 331:181] - node _T_564 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 332:56] - node _T_565 = eq(_T_564, UInt<8>("h0f0")) @[axi4_to_ahb.scala 332:63] - node _T_566 = or(_T_563, _T_565) @[axi4_to_ahb.scala 332:40] - node _T_567 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 332:92] - node _T_568 = eq(_T_567, UInt<8>("h0ff")) @[axi4_to_ahb.scala 332:99] - node _T_569 = or(_T_566, _T_568) @[axi4_to_ahb.scala 332:76] - node _T_570 = and(_T_549, _T_569) @[axi4_to_ahb.scala 331:38] - node _T_571 = or(_T_547, _T_570) @[axi4_to_ahb.scala 330:104] - buf_aligned_in <= _T_571 @[axi4_to_ahb.scala 329:18] - node _T_572 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 334:39] - node _T_573 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 334:58] - node _T_574 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 334:83] - node _T_575 = cat(_T_573, _T_574) @[Cat.scala 29:58] - node _T_576 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 334:104] - node _T_577 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 334:129] - node _T_578 = cat(_T_576, _T_577) @[Cat.scala 29:58] - node _T_579 = mux(_T_572, _T_575, _T_578) @[axi4_to_ahb.scala 334:22] - io.ahb_haddr <= _T_579 @[axi4_to_ahb.scala 334:16] - node _T_580 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 335:39] - node _T_581 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 337:11] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 338:16] + node _T_429 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 339:68] + node _T_430 = eq(_T_429, UInt<1>("h01")) @[axi4_to_ahb.scala 339:75] + node _T_431 = and(buf_aligned_in, _T_430) @[axi4_to_ahb.scala 339:55] + node _T_432 = bits(_T_431, 0, 0) @[axi4_to_ahb.scala 339:95] + node _T_433 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 339:127] + wire _T_434 : UInt<8> + _T_434 <= UInt<8>("h00") + node _T_435 = bits(_T_434, 7, 0) @[axi4_to_ahb.scala 168:44] + node _T_436 = eq(_T_435, UInt<8>("h0ff")) @[axi4_to_ahb.scala 168:51] + node _T_437 = bits(_T_434, 7, 0) @[axi4_to_ahb.scala 168:75] + node _T_438 = eq(_T_437, UInt<4>("h0f")) @[axi4_to_ahb.scala 168:82] + node _T_439 = or(_T_436, _T_438) @[axi4_to_ahb.scala 168:64] + node _T_440 = bits(_T_434, 7, 0) @[axi4_to_ahb.scala 168:106] + node _T_441 = eq(_T_440, UInt<2>("h03")) @[axi4_to_ahb.scala 168:113] + node _T_442 = or(_T_439, _T_441) @[axi4_to_ahb.scala 168:95] + node _T_443 = bits(_T_442, 0, 0) @[Bitwise.scala 72:15] + node _T_444 = mux(_T_443, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_445 = and(UInt<1>("h00"), _T_444) @[axi4_to_ahb.scala 168:24] + node _T_446 = bits(_T_434, 7, 0) @[axi4_to_ahb.scala 169:35] + node _T_447 = eq(_T_446, UInt<4>("h0c")) @[axi4_to_ahb.scala 169:42] + node _T_448 = bits(_T_447, 0, 0) @[Bitwise.scala 72:15] + node _T_449 = mux(_T_448, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_450 = and(UInt<2>("h02"), _T_449) @[axi4_to_ahb.scala 169:15] + node _T_451 = or(_T_445, _T_450) @[axi4_to_ahb.scala 168:128] + node _T_452 = bits(_T_434, 7, 0) @[axi4_to_ahb.scala 170:36] + node _T_453 = eq(_T_452, UInt<8>("h0f0")) @[axi4_to_ahb.scala 170:43] + node _T_454 = bits(_T_434, 7, 0) @[axi4_to_ahb.scala 170:67] + node _T_455 = eq(_T_454, UInt<2>("h03")) @[axi4_to_ahb.scala 170:74] + node _T_456 = or(_T_453, _T_455) @[axi4_to_ahb.scala 170:56] + node _T_457 = bits(_T_456, 0, 0) @[Bitwise.scala 72:15] + node _T_458 = mux(_T_457, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_459 = and(UInt<3>("h04"), _T_458) @[axi4_to_ahb.scala 170:15] + node _T_460 = bits(_T_434, 7, 0) @[axi4_to_ahb.scala 171:37] + node _T_461 = eq(_T_460, UInt<8>("h0c0")) @[axi4_to_ahb.scala 171:44] + node _T_462 = bits(_T_461, 0, 0) @[Bitwise.scala 72:15] + node _T_463 = mux(_T_462, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_464 = and(UInt<3>("h06"), _T_463) @[axi4_to_ahb.scala 171:17] + node _T_465 = or(_T_459, _T_464) @[axi4_to_ahb.scala 170:90] + node _T_466 = or(_T_451, _T_465) @[axi4_to_ahb.scala 169:58] + node _T_467 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 339:147] + node _T_468 = mux(_T_432, _T_466, _T_467) @[axi4_to_ahb.scala 339:38] + node _T_469 = cat(master_addr, _T_468) @[Cat.scala 29:58] + buf_addr_in <= _T_469 @[axi4_to_ahb.scala 339:15] + node _T_470 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 340:27] + buf_tag_in <= _T_470 @[axi4_to_ahb.scala 340:14] + node _T_471 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 341:32] + buf_byteen_in <= _T_471 @[axi4_to_ahb.scala 341:17] + node _T_472 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 342:33] + node _T_473 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 342:59] + node _T_474 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 342:80] + node _T_475 = mux(_T_472, _T_473, _T_474) @[axi4_to_ahb.scala 342:21] + buf_data_in <= _T_475 @[axi4_to_ahb.scala 342:15] + node _T_476 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 343:52] + node _T_477 = eq(_T_476, UInt<2>("h03")) @[axi4_to_ahb.scala 343:59] + node _T_478 = and(buf_aligned_in, _T_477) @[axi4_to_ahb.scala 343:38] + node _T_479 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 343:85] + node _T_480 = eq(_T_479, UInt<1>("h01")) @[axi4_to_ahb.scala 343:92] + node _T_481 = and(_T_478, _T_480) @[axi4_to_ahb.scala 343:72] + node _T_482 = bits(_T_481, 0, 0) @[axi4_to_ahb.scala 343:112] + node _T_483 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:144] + wire _T_484 : UInt<8> + _T_484 <= UInt<8>("h00") + node _T_485 = bits(_T_484, 7, 0) @[axi4_to_ahb.scala 160:43] + node _T_486 = eq(_T_485, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:50] + node _T_487 = bits(_T_486, 0, 0) @[Bitwise.scala 72:15] + node _T_488 = mux(_T_487, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_489 = and(UInt<2>("h03"), _T_488) @[axi4_to_ahb.scala 160:25] + node _T_490 = bits(_T_484, 7, 0) @[axi4_to_ahb.scala 161:34] + node _T_491 = eq(_T_490, UInt<8>("h0f0")) @[axi4_to_ahb.scala 161:41] + node _T_492 = bits(_T_484, 7, 0) @[axi4_to_ahb.scala 161:63] + node _T_493 = eq(_T_492, UInt<4>("h0f")) @[axi4_to_ahb.scala 161:70] + node _T_494 = or(_T_491, _T_493) @[axi4_to_ahb.scala 161:54] + node _T_495 = bits(_T_494, 0, 0) @[Bitwise.scala 72:15] + node _T_496 = mux(_T_495, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_497 = and(UInt<2>("h02"), _T_496) @[axi4_to_ahb.scala 161:16] + node _T_498 = or(_T_489, _T_497) @[axi4_to_ahb.scala 160:65] + node _T_499 = bits(_T_484, 7, 0) @[axi4_to_ahb.scala 162:34] + node _T_500 = eq(_T_499, UInt<8>("h0c0")) @[axi4_to_ahb.scala 162:41] + node _T_501 = bits(_T_484, 7, 0) @[axi4_to_ahb.scala 162:63] + node _T_502 = eq(_T_501, UInt<6>("h030")) @[axi4_to_ahb.scala 162:70] + node _T_503 = or(_T_500, _T_502) @[axi4_to_ahb.scala 162:54] + node _T_504 = bits(_T_484, 7, 0) @[axi4_to_ahb.scala 162:92] + node _T_505 = eq(_T_504, UInt<4>("h0c")) @[axi4_to_ahb.scala 162:99] + node _T_506 = or(_T_503, _T_505) @[axi4_to_ahb.scala 162:83] + node _T_507 = bits(_T_484, 7, 0) @[axi4_to_ahb.scala 162:121] + node _T_508 = eq(_T_507, UInt<2>("h03")) @[axi4_to_ahb.scala 162:128] + node _T_509 = or(_T_506, _T_508) @[axi4_to_ahb.scala 162:112] + node _T_510 = bits(_T_509, 0, 0) @[Bitwise.scala 72:15] + node _T_511 = mux(_T_510, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_512 = and(UInt<1>("h01"), _T_511) @[axi4_to_ahb.scala 162:16] + node _T_513 = or(_T_498, _T_512) @[axi4_to_ahb.scala 161:86] + node _T_514 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 343:164] + node _T_515 = mux(_T_482, _T_513, _T_514) @[axi4_to_ahb.scala 343:21] + buf_size_in <= _T_515 @[axi4_to_ahb.scala 343:15] + node _T_516 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 344:32] + node _T_517 = eq(_T_516, UInt<1>("h00")) @[axi4_to_ahb.scala 344:39] + node _T_518 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 345:17] + node _T_519 = eq(_T_518, UInt<1>("h00")) @[axi4_to_ahb.scala 345:24] + node _T_520 = or(_T_517, _T_519) @[axi4_to_ahb.scala 344:51] + node _T_521 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 345:50] + node _T_522 = eq(_T_521, UInt<1>("h01")) @[axi4_to_ahb.scala 345:57] + node _T_523 = or(_T_520, _T_522) @[axi4_to_ahb.scala 345:36] + node _T_524 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 345:84] + node _T_525 = eq(_T_524, UInt<2>("h02")) @[axi4_to_ahb.scala 345:91] + node _T_526 = or(_T_523, _T_525) @[axi4_to_ahb.scala 345:70] + node _T_527 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:18] + node _T_528 = eq(_T_527, UInt<2>("h03")) @[axi4_to_ahb.scala 346:25] + node _T_529 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 346:55] + node _T_530 = eq(_T_529, UInt<2>("h03")) @[axi4_to_ahb.scala 346:62] + node _T_531 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 346:90] + node _T_532 = eq(_T_531, UInt<4>("h0c")) @[axi4_to_ahb.scala 346:97] + node _T_533 = or(_T_530, _T_532) @[axi4_to_ahb.scala 346:74] + node _T_534 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 346:125] + node _T_535 = eq(_T_534, UInt<6>("h030")) @[axi4_to_ahb.scala 346:132] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 346:109] + node _T_537 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 346:161] + node _T_538 = eq(_T_537, UInt<8>("h0c0")) @[axi4_to_ahb.scala 346:168] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 346:145] + node _T_540 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 347:21] + node _T_541 = eq(_T_540, UInt<4>("h0f")) @[axi4_to_ahb.scala 347:28] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 346:181] + node _T_543 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 347:56] + node _T_544 = eq(_T_543, UInt<8>("h0f0")) @[axi4_to_ahb.scala 347:63] + node _T_545 = or(_T_542, _T_544) @[axi4_to_ahb.scala 347:40] + node _T_546 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 347:92] + node _T_547 = eq(_T_546, UInt<8>("h0ff")) @[axi4_to_ahb.scala 347:99] + node _T_548 = or(_T_545, _T_547) @[axi4_to_ahb.scala 347:76] + node _T_549 = and(_T_528, _T_548) @[axi4_to_ahb.scala 346:38] + node _T_550 = or(_T_526, _T_549) @[axi4_to_ahb.scala 345:104] + buf_aligned_in <= _T_550 @[axi4_to_ahb.scala 344:18] + node _T_551 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 349:39] + node _T_552 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 349:58] + node _T_553 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 349:83] + node _T_554 = cat(_T_552, _T_553) @[Cat.scala 29:58] + node _T_555 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 349:104] + node _T_556 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 349:129] + node _T_557 = cat(_T_555, _T_556) @[Cat.scala 29:58] + node _T_558 = mux(_T_551, _T_554, _T_557) @[axi4_to_ahb.scala 349:22] + io.ahb_haddr <= _T_558 @[axi4_to_ahb.scala 349:16] + node _T_559 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 350:39] + node _T_560 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] + node _T_561 = mux(_T_560, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_562 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 350:93] + node _T_563 = and(_T_561, _T_562) @[axi4_to_ahb.scala 350:80] + node _T_564 = cat(UInt<1>("h00"), _T_563) @[Cat.scala 29:58] + node _T_565 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] + node _T_566 = mux(_T_565, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_567 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 350:148] + node _T_568 = and(_T_566, _T_567) @[axi4_to_ahb.scala 350:138] + node _T_569 = cat(UInt<1>("h00"), _T_568) @[Cat.scala 29:58] + node _T_570 = mux(_T_559, _T_564, _T_569) @[axi4_to_ahb.scala 350:22] + io.ahb_hsize <= _T_570 @[axi4_to_ahb.scala 350:16] + io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 352:17] + io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 353:20] + node _T_571 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 354:47] + node _T_572 = not(_T_571) @[axi4_to_ahb.scala 354:33] + node _T_573 = cat(UInt<1>("h01"), _T_572) @[Cat.scala 29:58] + io.ahb_hprot <= _T_573 @[axi4_to_ahb.scala 354:16] + node _T_574 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 355:40] + node _T_575 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 355:55] + node _T_576 = eq(_T_575, UInt<1>("h01")) @[axi4_to_ahb.scala 355:62] + node _T_577 = mux(_T_574, _T_576, buf_write) @[axi4_to_ahb.scala 355:23] + io.ahb_hwrite <= _T_577 @[axi4_to_ahb.scala 355:17] + node _T_578 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 356:28] + io.ahb_hwdata <= _T_578 @[axi4_to_ahb.scala 356:17] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 358:15] + node _T_579 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 359:43] + node _T_580 = mux(_T_579, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 359:23] + node _T_581 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 335:93] - node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 335:80] - node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] - node _T_586 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_587 = mux(_T_586, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_588 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 335:148] - node _T_589 = and(_T_587, _T_588) @[axi4_to_ahb.scala 335:138] - node _T_590 = cat(UInt<1>("h00"), _T_589) @[Cat.scala 29:58] - node _T_591 = mux(_T_580, _T_585, _T_590) @[axi4_to_ahb.scala 335:22] - io.ahb_hsize <= _T_591 @[axi4_to_ahb.scala 335:16] - io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 337:17] - io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 338:20] - node _T_592 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 339:47] - node _T_593 = not(_T_592) @[axi4_to_ahb.scala 339:33] - node _T_594 = cat(UInt<1>("h01"), _T_593) @[Cat.scala 29:58] - io.ahb_hprot <= _T_594 @[axi4_to_ahb.scala 339:16] - node _T_595 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 340:40] - node _T_596 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 340:55] - node _T_597 = eq(_T_596, UInt<1>("h01")) @[axi4_to_ahb.scala 340:62] - node _T_598 = mux(_T_595, _T_597, buf_write) @[axi4_to_ahb.scala 340:23] - io.ahb_hwrite <= _T_598 @[axi4_to_ahb.scala 340:17] - node _T_599 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 341:28] - io.ahb_hwdata <= _T_599 @[axi4_to_ahb.scala 341:17] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 343:15] - node _T_600 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 344:43] - node _T_601 = mux(_T_600, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 344:23] - node _T_602 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_603 = mux(_T_602, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_604 = and(_T_603, UInt<2>("h02")) @[axi4_to_ahb.scala 344:88] - node _T_605 = cat(_T_601, _T_604) @[Cat.scala 29:58] - slave_opc <= _T_605 @[axi4_to_ahb.scala 344:13] - node _T_606 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 345:41] - node _T_607 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 345:66] - node _T_608 = cat(_T_607, _T_607) @[Cat.scala 29:58] - node _T_609 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 345:91] - node _T_610 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 345:110] - node _T_611 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 345:131] - node _T_612 = mux(_T_609, _T_610, _T_611) @[axi4_to_ahb.scala 345:79] - node _T_613 = mux(_T_606, _T_608, _T_612) @[axi4_to_ahb.scala 345:21] - slave_rdata <= _T_613 @[axi4_to_ahb.scala 345:15] - node _T_614 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 346:26] - slave_tag <= _T_614 @[axi4_to_ahb.scala 346:13] - node _T_615 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 348:33] - node _T_616 = neq(_T_615, UInt<1>("h00")) @[axi4_to_ahb.scala 348:40] - node _T_617 = and(_T_616, io.ahb_hready) @[axi4_to_ahb.scala 348:52] - node _T_618 = and(_T_617, io.ahb_hwrite) @[axi4_to_ahb.scala 348:68] - last_addr_en <= _T_618 @[axi4_to_ahb.scala 348:16] - node _T_619 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 351:68] - node _T_620 = mux(_T_619, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 351:52] - node _T_621 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 351:88] - node _T_622 = and(_T_620, _T_621) @[axi4_to_ahb.scala 351:86] - reg _T_623 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 351:48] - _T_623 <= _T_622 @[axi4_to_ahb.scala 351:48] - wrbuf_vld <= _T_623 @[axi4_to_ahb.scala 351:18] - node _T_624 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 352:73] - node _T_625 = mux(_T_624, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 352:52] - node _T_626 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 352:99] - node _T_627 = and(_T_625, _T_626) @[axi4_to_ahb.scala 352:97] - reg _T_628 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 352:48] - _T_628 <= _T_627 @[axi4_to_ahb.scala 352:48] - wrbuf_data_vld <= _T_628 @[axi4_to_ahb.scala 352:18] - node _T_629 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 354:57] - node _T_630 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 354:91] + node _T_583 = and(_T_582, UInt<2>("h02")) @[axi4_to_ahb.scala 359:88] + node _T_584 = cat(_T_580, _T_583) @[Cat.scala 29:58] + slave_opc <= _T_584 @[axi4_to_ahb.scala 359:13] + node _T_585 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 360:41] + node _T_586 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 360:66] + node _T_587 = cat(_T_586, _T_586) @[Cat.scala 29:58] + node _T_588 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 360:91] + node _T_589 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 360:110] + node _T_590 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 360:131] + node _T_591 = mux(_T_588, _T_589, _T_590) @[axi4_to_ahb.scala 360:79] + node _T_592 = mux(_T_585, _T_587, _T_591) @[axi4_to_ahb.scala 360:21] + slave_rdata <= _T_592 @[axi4_to_ahb.scala 360:15] + node _T_593 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 361:26] + slave_tag <= _T_593 @[axi4_to_ahb.scala 361:13] + node _T_594 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 363:33] + node _T_595 = neq(_T_594, UInt<1>("h00")) @[axi4_to_ahb.scala 363:40] + node _T_596 = and(_T_595, io.ahb_hready) @[axi4_to_ahb.scala 363:52] + node _T_597 = and(_T_596, io.ahb_hwrite) @[axi4_to_ahb.scala 363:68] + last_addr_en <= _T_597 @[axi4_to_ahb.scala 363:16] + node _T_598 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 365:30] + node _T_599 = and(_T_598, master_ready) @[axi4_to_ahb.scala 365:47] + wrbuf_en <= _T_599 @[axi4_to_ahb.scala 365:12] + node _T_600 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 366:34] + node _T_601 = and(_T_600, master_ready) @[axi4_to_ahb.scala 366:50] + wrbuf_data_en <= _T_601 @[axi4_to_ahb.scala 366:17] + node _T_602 = and(master_valid, master_ready) @[axi4_to_ahb.scala 367:34] + node _T_603 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 367:62] + node _T_604 = eq(_T_603, UInt<1>("h01")) @[axi4_to_ahb.scala 367:69] + node _T_605 = and(_T_602, _T_604) @[axi4_to_ahb.scala 367:49] + wrbuf_cmd_sent <= _T_605 @[axi4_to_ahb.scala 367:18] + node _T_606 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 368:33] + node _T_607 = and(wrbuf_cmd_sent, _T_606) @[axi4_to_ahb.scala 368:31] + wrbuf_rst <= _T_607 @[axi4_to_ahb.scala 368:13] + node _T_608 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 370:35] + node _T_609 = and(wrbuf_vld, _T_608) @[axi4_to_ahb.scala 370:33] + node _T_610 = eq(_T_609, UInt<1>("h00")) @[axi4_to_ahb.scala 370:21] + node _T_611 = and(_T_610, master_ready) @[axi4_to_ahb.scala 370:52] + io.axi_awready <= _T_611 @[axi4_to_ahb.scala 370:18] + node _T_612 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 371:39] + node _T_613 = and(wrbuf_data_vld, _T_612) @[axi4_to_ahb.scala 371:37] + node _T_614 = eq(_T_613, UInt<1>("h00")) @[axi4_to_ahb.scala 371:20] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 371:56] + io.axi_wready <= _T_615 @[axi4_to_ahb.scala 371:17] + node _T_616 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 372:33] + node _T_617 = eq(_T_616, UInt<1>("h00")) @[axi4_to_ahb.scala 372:21] + node _T_618 = and(_T_617, master_ready) @[axi4_to_ahb.scala 372:51] + io.axi_arready <= _T_618 @[axi4_to_ahb.scala 372:18] + io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 373:16] + node _T_619 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 376:68] + node _T_620 = mux(_T_619, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 376:52] + node _T_621 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 376:88] + node _T_622 = and(_T_620, _T_621) @[axi4_to_ahb.scala 376:86] + reg _T_623 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 376:48] + _T_623 <= _T_622 @[axi4_to_ahb.scala 376:48] + wrbuf_vld <= _T_623 @[axi4_to_ahb.scala 376:18] + node _T_624 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 377:73] + node _T_625 = mux(_T_624, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 377:52] + node _T_626 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 377:99] + node _T_627 = and(_T_625, _T_626) @[axi4_to_ahb.scala 377:97] + reg _T_628 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 377:48] + _T_628 <= _T_627 @[axi4_to_ahb.scala 377:48] + wrbuf_data_vld <= _T_628 @[axi4_to_ahb.scala 377:18] + node _T_629 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 379:57] + node _T_630 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 379:91] reg _T_631 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_630 : @[Reg.scala 28:19] _T_631 <= _T_629 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_tag <= _T_631 @[axi4_to_ahb.scala 354:13] - node _T_632 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 355:60] - node _T_633 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 355:88] + wrbuf_tag <= _T_631 @[axi4_to_ahb.scala 379:13] + node _T_632 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 380:60] + node _T_633 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 380:88] reg _T_634 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_633 : @[Reg.scala 28:19] _T_634 <= _T_632 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_size <= _T_634 @[axi4_to_ahb.scala 355:14] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 357:48] + wrbuf_size <= _T_634 @[axi4_to_ahb.scala 380:14] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 382:48] inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -1215,8 +1222,8 @@ circuit axi4_to_ahb : rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_636 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_636 <= io.axi_awaddr @[el2_lib.scala 514:16] - wrbuf_addr <= _T_636 @[axi4_to_ahb.scala 357:14] - node _T_637 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 358:52] + wrbuf_addr <= _T_636 @[axi4_to_ahb.scala 382:14] + node _T_637 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 383:52] inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -1225,44 +1232,44 @@ circuit axi4_to_ahb : rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_638 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_638 <= io.axi_wdata @[el2_lib.scala 514:16] - wrbuf_data <= _T_638 @[axi4_to_ahb.scala 358:14] - node _T_639 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 361:27] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 361:60] + wrbuf_data <= _T_638 @[axi4_to_ahb.scala 383:14] + node _T_639 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 386:27] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 386:60] reg _T_641 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_640 : @[Reg.scala 28:19] _T_641 <= _T_639 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_641 @[axi4_to_ahb.scala 360:16] - node _T_642 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 364:27] - node _T_643 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 364:60] + wrbuf_byteen <= _T_641 @[axi4_to_ahb.scala 385:16] + node _T_642 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 389:27] + node _T_643 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 389:60] reg _T_644 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_643 : @[Reg.scala 28:19] _T_644 <= _T_642 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - last_bus_addr <= _T_644 @[axi4_to_ahb.scala 363:17] - node _T_645 = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 368:36] - node _T_646 = mux(_T_645, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 368:16] - node _T_647 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 368:65] - node _T_648 = and(_T_646, _T_647) @[axi4_to_ahb.scala 368:63] - reg _T_649 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 368:12] - _T_649 <= _T_648 @[axi4_to_ahb.scala 368:12] - buf_state <= _T_649 @[axi4_to_ahb.scala 367:13] - node _T_650 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 372:50] + last_bus_addr <= _T_644 @[axi4_to_ahb.scala 388:17] + node _T_645 = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 393:36] + node _T_646 = mux(_T_645, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 393:16] + node _T_647 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 393:65] + node _T_648 = and(_T_646, _T_647) @[axi4_to_ahb.scala 393:63] + reg _T_649 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 393:12] + _T_649 <= _T_648 @[axi4_to_ahb.scala 393:12] + buf_state <= _T_649 @[axi4_to_ahb.scala 392:13] + node _T_650 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 397:50] reg _T_651 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_650 : @[Reg.scala 28:19] _T_651 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write <= _T_651 @[axi4_to_ahb.scala 371:13] - node _T_652 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 375:25] - node _T_653 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 375:60] + buf_write <= _T_651 @[axi4_to_ahb.scala 396:13] + node _T_652 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 400:25] + node _T_653 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 400:60] reg _T_654 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_653 : @[Reg.scala 28:19] _T_654 <= _T_652 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_tag <= _T_654 @[axi4_to_ahb.scala 374:11] - node _T_655 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 378:33] - node _T_656 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 378:52] - node _T_657 = bits(_T_656, 0, 0) @[axi4_to_ahb.scala 378:69] + buf_tag <= _T_654 @[axi4_to_ahb.scala 399:11] + node _T_655 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 403:33] + node _T_656 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 403:52] + node _T_657 = bits(_T_656, 0, 0) @[axi4_to_ahb.scala 403:69] inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -1271,30 +1278,30 @@ circuit axi4_to_ahb : rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_658 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_658 <= _T_655 @[el2_lib.scala 514:16] - buf_addr <= _T_658 @[axi4_to_ahb.scala 378:12] - node _T_659 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 381:26] - node _T_660 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 381:55] + buf_addr <= _T_658 @[axi4_to_ahb.scala 403:12] + node _T_659 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 406:26] + node _T_660 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 406:55] reg _T_661 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_660 : @[Reg.scala 28:19] _T_661 <= _T_659 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_size <= _T_661 @[axi4_to_ahb.scala 380:12] - node _T_662 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 384:52] + buf_size <= _T_661 @[axi4_to_ahb.scala 405:12] + node _T_662 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 409:52] reg _T_663 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_662 : @[Reg.scala 28:19] _T_663 <= buf_aligned_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_aligned <= _T_663 @[axi4_to_ahb.scala 383:15] - node _T_664 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 387:28] - node _T_665 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 387:57] + buf_aligned <= _T_663 @[axi4_to_ahb.scala 408:15] + node _T_664 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 412:28] + node _T_665 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 412:57] reg _T_666 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_665 : @[Reg.scala 28:19] _T_666 <= _T_664 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen <= _T_666 @[axi4_to_ahb.scala 386:14] - node _T_667 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 390:33] - node _T_668 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 390:57] - node _T_669 = bits(_T_668, 0, 0) @[axi4_to_ahb.scala 390:80] + buf_byteen <= _T_666 @[axi4_to_ahb.scala 411:14] + node _T_667 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 415:33] + node _T_668 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 415:57] + node _T_669 = bits(_T_668, 0, 0) @[axi4_to_ahb.scala 415:80] inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -1303,96 +1310,96 @@ circuit axi4_to_ahb : rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_670 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_670 <= _T_667 @[el2_lib.scala 514:16] - buf_data <= _T_670 @[axi4_to_ahb.scala 390:12] - node _T_671 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 393:50] + buf_data <= _T_670 @[axi4_to_ahb.scala 415:12] + node _T_671 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 418:50] reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_671 : @[Reg.scala 28:19] _T_672 <= buf_write @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_write <= _T_672 @[axi4_to_ahb.scala 392:16] - node _T_673 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 396:22] - node _T_674 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 396:60] + slvbuf_write <= _T_672 @[axi4_to_ahb.scala 417:16] + node _T_673 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 421:22] + node _T_674 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 421:60] reg _T_675 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_674 : @[Reg.scala 28:19] _T_675 <= _T_673 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_tag <= _T_675 @[axi4_to_ahb.scala 395:14] - node _T_676 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 399:59] + slvbuf_tag <= _T_675 @[axi4_to_ahb.scala 420:14] + node _T_676 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 424:59] reg _T_677 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_676 : @[Reg.scala 28:19] _T_677 <= slvbuf_error_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_error <= _T_677 @[axi4_to_ahb.scala 398:16] - node _T_678 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 403:32] - node _T_679 = mux(_T_678, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 403:16] - node _T_680 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 403:52] - node _T_681 = and(_T_679, _T_680) @[axi4_to_ahb.scala 403:50] - reg _T_682 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 403:12] - _T_682 <= _T_681 @[axi4_to_ahb.scala 403:12] - cmd_doneQ <= _T_682 @[axi4_to_ahb.scala 402:13] - node _T_683 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 407:31] - node _T_684 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 407:70] + slvbuf_error <= _T_677 @[axi4_to_ahb.scala 423:16] + node _T_678 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 428:32] + node _T_679 = mux(_T_678, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 428:16] + node _T_680 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 428:52] + node _T_681 = and(_T_679, _T_680) @[axi4_to_ahb.scala 428:50] + reg _T_682 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 428:12] + _T_682 <= _T_681 @[axi4_to_ahb.scala 428:12] + cmd_doneQ <= _T_682 @[axi4_to_ahb.scala 427:13] + node _T_683 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 432:31] + node _T_684 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 432:70] reg _T_685 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_684 : @[Reg.scala 28:19] _T_685 <= _T_683 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_685 @[axi4_to_ahb.scala 406:21] - reg _T_686 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 412:12] - _T_686 <= io.ahb_hready @[axi4_to_ahb.scala 412:12] - ahb_hready_q <= _T_686 @[axi4_to_ahb.scala 411:16] - node _T_687 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 415:26] - reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 415:12] - _T_688 <= _T_687 @[axi4_to_ahb.scala 415:12] - ahb_htrans_q <= _T_688 @[axi4_to_ahb.scala 414:16] - reg _T_689 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 418:12] - _T_689 <= io.ahb_hwrite @[axi4_to_ahb.scala 418:12] - ahb_hwrite_q <= _T_689 @[axi4_to_ahb.scala 417:16] - reg _T_690 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 421:12] - _T_690 <= io.ahb_hresp @[axi4_to_ahb.scala 421:12] - ahb_hresp_q <= _T_690 @[axi4_to_ahb.scala 420:15] - node _T_691 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 424:26] - reg _T_692 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 424:12] - _T_692 <= _T_691 @[axi4_to_ahb.scala 424:12] - ahb_hrdata_q <= _T_692 @[axi4_to_ahb.scala 423:16] - node _T_693 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 427:43] - node _T_694 = or(_T_693, io.clk_override) @[axi4_to_ahb.scala 427:58] - node _T_695 = and(io.bus_clk_en, _T_694) @[axi4_to_ahb.scala 427:30] - buf_clken <= _T_695 @[axi4_to_ahb.scala 427:13] - node _T_696 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 428:69] - node _T_697 = and(io.ahb_hready, _T_696) @[axi4_to_ahb.scala 428:54] - node _T_698 = or(_T_697, io.clk_override) @[axi4_to_ahb.scala 428:74] - node _T_699 = and(io.bus_clk_en, _T_698) @[axi4_to_ahb.scala 428:36] - ahbm_addr_clken <= _T_699 @[axi4_to_ahb.scala 428:19] - node _T_700 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 429:50] - node _T_701 = or(_T_700, io.clk_override) @[axi4_to_ahb.scala 429:60] - node _T_702 = and(io.bus_clk_en, _T_701) @[axi4_to_ahb.scala 429:36] - ahbm_data_clken <= _T_702 @[axi4_to_ahb.scala 429:19] + buf_cmd_byte_ptrQ <= _T_685 @[axi4_to_ahb.scala 431:21] + reg _T_686 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 437:12] + _T_686 <= io.ahb_hready @[axi4_to_ahb.scala 437:12] + ahb_hready_q <= _T_686 @[axi4_to_ahb.scala 436:16] + node _T_687 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 440:26] + reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 440:12] + _T_688 <= _T_687 @[axi4_to_ahb.scala 440:12] + ahb_htrans_q <= _T_688 @[axi4_to_ahb.scala 439:16] + reg _T_689 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 443:12] + _T_689 <= io.ahb_hwrite @[axi4_to_ahb.scala 443:12] + ahb_hwrite_q <= _T_689 @[axi4_to_ahb.scala 442:16] + reg _T_690 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 446:12] + _T_690 <= io.ahb_hresp @[axi4_to_ahb.scala 446:12] + ahb_hresp_q <= _T_690 @[axi4_to_ahb.scala 445:15] + node _T_691 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 449:26] + reg _T_692 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 449:12] + _T_692 <= _T_691 @[axi4_to_ahb.scala 449:12] + ahb_hrdata_q <= _T_692 @[axi4_to_ahb.scala 448:16] + node _T_693 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 452:43] + node _T_694 = or(_T_693, io.clk_override) @[axi4_to_ahb.scala 452:58] + node _T_695 = and(io.bus_clk_en, _T_694) @[axi4_to_ahb.scala 452:30] + buf_clken <= _T_695 @[axi4_to_ahb.scala 452:13] + node _T_696 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 453:69] + node _T_697 = and(io.ahb_hready, _T_696) @[axi4_to_ahb.scala 453:54] + node _T_698 = or(_T_697, io.clk_override) @[axi4_to_ahb.scala 453:74] + node _T_699 = and(io.bus_clk_en, _T_698) @[axi4_to_ahb.scala 453:36] + ahbm_addr_clken <= _T_699 @[axi4_to_ahb.scala 453:19] + node _T_700 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 454:50] + node _T_701 = or(_T_700, io.clk_override) @[axi4_to_ahb.scala 454:60] + node _T_702 = and(io.bus_clk_en, _T_701) @[axi4_to_ahb.scala 454:36] + ahbm_data_clken <= _T_702 @[axi4_to_ahb.scala 454:19] inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 483:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_6.io.en <= buf_clken @[el2_lib.scala 485:16] rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 432:12] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 457:12] inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 483:22] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_7.io.en <= io.bus_clk_en @[el2_lib.scala 485:16] rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 433:12] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 458:12] inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 483:22] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_8.io.en <= ahbm_addr_clken @[el2_lib.scala 485:16] rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 434:17] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 459:17] inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 483:22] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_9.io.en <= ahbm_data_clken @[el2_lib.scala 485:16] rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 435:17] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 460:17] diff --git a/axi4_to_ahb.v b/axi4_to_ahb.v index 2ab3dfac..92e36f7b 100644 --- a/axi4_to_ahb.v +++ b/axi4_to_ahb.v @@ -65,7 +65,7 @@ module axi4_to_ahb( output [63:0] io_ahb_hwdata ); `ifdef RANDOMIZE_REG_INIT - reg [31:0] _RAND_0; + reg [63:0] _RAND_0; reg [31:0] _RAND_1; reg [31:0] _RAND_2; reg [31:0] _RAND_3; @@ -75,23 +75,13 @@ module axi4_to_ahb( reg [31:0] _RAND_7; reg [31:0] _RAND_8; reg [31:0] _RAND_9; - reg [31:0] _RAND_10; - reg [31:0] _RAND_11; + reg [63:0] _RAND_10; + reg [63:0] _RAND_11; reg [31:0] _RAND_12; - reg [63:0] _RAND_13; + reg [31:0] _RAND_13; reg [31:0] _RAND_14; reg [31:0] _RAND_15; reg [31:0] _RAND_16; - reg [31:0] _RAND_17; - reg [63:0] _RAND_18; - reg [63:0] _RAND_19; - reg [31:0] _RAND_20; - reg [31:0] _RAND_21; - reg [31:0] _RAND_22; - reg [31:0] _RAND_23; - reg [31:0] _RAND_24; - reg [31:0] _RAND_25; - reg [31:0] _RAND_26; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] @@ -133,334 +123,220 @@ module axi4_to_ahb( wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22] wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22] wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22] - reg [2:0] buf_nxtstate; // @[axi4_to_ahb.scala 62:29] - wire _T = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 182:30] - wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 152:22 axi4_to_ahb.scala 433:12] - reg [2:0] buf_state; // @[axi4_to_ahb.scala 368:12] - wire _T_63 = 3'h0 == buf_state; // @[Conditional.scala 37:30] - wire _T_115 = 3'h1 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hready_q; // @[axi4_to_ahb.scala 412:12] - reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 415:12] - wire _T_129 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 243:59] - wire _T_130 = ahb_hready_q & _T_129; // @[axi4_to_ahb.scala 243:37] - wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 153:27 axi4_to_ahb.scala 434:17] - reg ahb_hwrite_q; // @[axi4_to_ahb.scala 418:12] - wire _T_131 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 243:73] - wire _T_132 = _T_130 & _T_131; // @[axi4_to_ahb.scala 243:71] - wire _T_133 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 243:104] - wire _T_134 = _T_132 & _T_133; // @[axi4_to_ahb.scala 243:88] - wire _T_145 = 3'h6 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hresp_q; // @[axi4_to_ahb.scala 421:12] - wire _T_146 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 251:39] - wire _T_147 = ahb_hready_q & _T_146; // @[axi4_to_ahb.scala 251:37] - wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 82:21 axi4_to_ahb.scala 215:11] - reg wrbuf_vld; // @[axi4_to_ahb.scala 351:48] - reg wrbuf_data_vld; // @[axi4_to_ahb.scala 352:48] - wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 192:27] - wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 193:30] - wire [1:0] _T_28 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 195:20] - wire [2:0] master_opc = {{1'd0}, _T_28}; // @[axi4_to_ahb.scala 195:14] - wire _T_149 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 251:89] - wire _T_150 = master_valid & _T_149; // @[axi4_to_ahb.scala 251:70] - wire _T_151 = ~_T_150; // @[axi4_to_ahb.scala 251:55] - wire _T_152 = _T_147 & _T_151; // @[axi4_to_ahb.scala 251:53] - wire _T_180 = 3'h7 == buf_state; // @[Conditional.scala 37:30] - wire _T_191 = 3'h3 == buf_state; // @[Conditional.scala 37:30] - wire _T_193 = 3'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_286 = 3'h4 == buf_state; // @[Conditional.scala 37:30] - reg cmd_doneQ; // @[axi4_to_ahb.scala 403:12] - wire _T_289 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 297:35] - wire _T_290 = _T_289 | ahb_hresp_q; // @[axi4_to_ahb.scala 297:51] - wire _T_292 = _T_290 & _T_146; // @[axi4_to_ahb.scala 297:66] - wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 210:32] - wire _T_293 = _T_292 & slave_ready; // @[axi4_to_ahb.scala 297:81] - wire _GEN_4 = _T_286 & _T_293; // @[Conditional.scala 39:67] - wire _GEN_26 = _T_193 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] - wire _GEN_45 = _T_191 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] - wire _GEN_62 = _T_180 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] - wire _GEN_66 = _T_145 ? _T_152 : _GEN_62; // @[Conditional.scala 39:67] - wire _GEN_86 = _T_115 ? _T_134 : _GEN_66; // @[Conditional.scala 39:67] - wire master_ready = _T_63 | _GEN_86; // @[Conditional.scala 40:58] - wire wrbuf_en = _T & master_ready; // @[axi4_to_ahb.scala 182:47] - wire _T_2 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 183:34] - wire wrbuf_data_en = _T_2 & master_ready; // @[axi4_to_ahb.scala 183:50] - wire _T_4 = master_valid & master_ready; // @[axi4_to_ahb.scala 184:34] - wire wrbuf_cmd_sent = _T_4 & _T_149; // @[axi4_to_ahb.scala 184:49] - wire _T_8 = ~wrbuf_en; // @[axi4_to_ahb.scala 185:33] - wire wrbuf_rst = wrbuf_cmd_sent & _T_8; // @[axi4_to_ahb.scala 185:31] - wire _T_10 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 187:35] - wire _T_11 = wrbuf_vld & _T_10; // @[axi4_to_ahb.scala 187:33] - wire _T_12 = ~_T_11; // @[axi4_to_ahb.scala 187:21] - wire _T_15 = wrbuf_data_vld & _T_10; // @[axi4_to_ahb.scala 188:37] - wire _T_16 = ~_T_15; // @[axi4_to_ahb.scala 188:20] - wire _T_19 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 189:21] - reg wrbuf_tag; // @[Reg.scala 27:20] - reg [31:0] wrbuf_addr; // @[el2_lib.scala 514:16] - wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_araddr; // @[axi4_to_ahb.scala 196:21] - reg [2:0] wrbuf_size; // @[Reg.scala 27:20] - wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 197:21] - reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] reg [63:0] wrbuf_data; // @[el2_lib.scala 514:16] - wire _T_161 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 254:37] - wire _T_194 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 286:33] - wire _T_197 = _T_194 & _T_129; // @[axi4_to_ahb.scala 286:48] - wire _GEN_15 = _T_286 & _T_197; // @[Conditional.scala 39:67] - wire _GEN_19 = _T_193 ? _T_197 : _GEN_15; // @[Conditional.scala 39:67] - wire _GEN_40 = _T_191 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67] - wire _GEN_59 = _T_180 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] - wire _GEN_79 = _T_145 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] - wire _GEN_95 = _T_115 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] - wire trxn_done = _T_63 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] - wire _T_449 = 3'h5 == buf_state; // @[Conditional.scala 37:30] - wire _GEN_1 = _T_449 & slave_ready; // @[Conditional.scala 39:67] - wire _GEN_3 = _T_286 ? _T_290 : _GEN_1; // @[Conditional.scala 39:67] - wire _GEN_20 = _T_193 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] - wire _GEN_35 = _T_191 ? _T_161 : _GEN_20; // @[Conditional.scala 39:67] - wire _GEN_51 = _T_180 ? _T_132 : _GEN_35; // @[Conditional.scala 39:67] - wire _GEN_69 = _T_145 ? _T_161 : _GEN_51; // @[Conditional.scala 39:67] - wire _GEN_83 = _T_115 ? _T_132 : _GEN_69; // @[Conditional.scala 39:67] - wire buf_state_en = _T_63 ? _T_4 : _GEN_83; // @[Conditional.scala 40:58] - wire _T_163 = buf_state_en & _T_146; // @[axi4_to_ahb.scala 258:39] - wire _T_366 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 307:55] - wire _T_367 = buf_state_en & _T_366; // @[axi4_to_ahb.scala 307:39] - wire _GEN_14 = _T_286 ? _T_367 : _T_449; // @[Conditional.scala 39:67] - wire _GEN_33 = _T_193 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] - wire _GEN_49 = _T_191 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] - wire _GEN_52 = _T_180 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] - wire _GEN_73 = _T_145 ? _T_163 : _GEN_52; // @[Conditional.scala 39:67] - wire _GEN_94 = _T_115 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] - wire slave_valid_pre = _T_63 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] - wire _T_39 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 202:32] - wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 150:21 axi4_to_ahb.scala 432:12] - reg slvbuf_write; // @[Reg.scala 27:20] - wire [1:0] _T_601 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 344:23] + wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 152:22 axi4_to_ahb.scala 458:12] + reg [2:0] buf_state; // @[axi4_to_ahb.scala 393:12] + wire _T_42 = 3'h0 == buf_state; // @[Conditional.scala 37:30] + wire _T_94 = 3'h1 == buf_state; // @[Conditional.scala 37:30] + wire _T_124 = 3'h6 == buf_state; // @[Conditional.scala 37:30] + reg ahb_hready_q; // @[axi4_to_ahb.scala 437:12] + reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 440:12] + wire _T_101 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 255:58] + wire _T_102 = ahb_hready_q & _T_101; // @[axi4_to_ahb.scala 255:36] + wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 153:27 axi4_to_ahb.scala 459:17] + reg ahb_hwrite_q; // @[axi4_to_ahb.scala 443:12] + wire _T_103 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 255:72] + wire _T_104 = _T_102 & _T_103; // @[axi4_to_ahb.scala 255:70] + reg ahb_hresp_q; // @[axi4_to_ahb.scala 446:12] + wire _T_140 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 269:37] + wire _T_159 = 3'h7 == buf_state; // @[Conditional.scala 37:30] + wire _T_170 = 3'h3 == buf_state; // @[Conditional.scala 37:30] + wire _T_172 = 3'h2 == buf_state; // @[Conditional.scala 37:30] + wire _T_173 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 301:33] + wire _T_176 = _T_173 & _T_101; // @[axi4_to_ahb.scala 301:48] + wire _T_265 = 3'h4 == buf_state; // @[Conditional.scala 37:30] + wire _GEN_14 = _T_265 & _T_176; // @[Conditional.scala 39:67] + wire _GEN_18 = _T_172 ? _T_176 : _GEN_14; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_170 ? 1'h0 : _GEN_18; // @[Conditional.scala 39:67] + wire _GEN_56 = _T_159 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_124 ? 1'h0 : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_89 = _T_94 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67] + wire trxn_done = _T_42 ? 1'h0 : _GEN_89; // @[Conditional.scala 40:58] + reg cmd_doneQ; // @[axi4_to_ahb.scala 428:12] + wire _T_266 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 311:34] + wire _T_267 = _T_266 | ahb_hresp_q; // @[axi4_to_ahb.scala 311:50] + wire _T_428 = 3'h5 == buf_state; // @[Conditional.scala 37:30] + wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 210:32] + wire _GEN_1 = _T_428 & slave_ready; // @[Conditional.scala 39:67] + wire _GEN_3 = _T_265 ? _T_267 : _GEN_1; // @[Conditional.scala 39:67] + wire _GEN_19 = _T_172 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] + wire _GEN_33 = _T_170 ? _T_140 : _GEN_19; // @[Conditional.scala 39:67] + wire _GEN_48 = _T_159 ? _T_104 : _GEN_33; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_124 ? _T_140 : _GEN_48; // @[Conditional.scala 39:67] + wire _GEN_77 = _T_94 ? _T_104 : _GEN_63; // @[Conditional.scala 39:67] + wire buf_state_en = _T_42 ? io_axi_arvalid : _GEN_77; // @[Conditional.scala 40:58] + wire _T_141 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 273:41] + wire _T_142 = buf_state_en & _T_141; // @[axi4_to_ahb.scala 273:39] + wire _T_273 = ~slave_ready; // @[axi4_to_ahb.scala 313:42] + wire _T_274 = ahb_hresp_q | _T_273; // @[axi4_to_ahb.scala 313:40] + wire _T_271 = _T_267 & _T_141; // @[axi4_to_ahb.scala 312:68] + wire _T_272 = _T_271 & slave_ready; // @[axi4_to_ahb.scala 312:83] + wire _T_276 = io_axi_arvalid & _T_272; // @[axi4_to_ahb.scala 313:90] + wire [2:0] _T_281 = _T_276 ? 3'h1 : 3'h0; // @[axi4_to_ahb.scala 313:75] + wire [2:0] _T_282 = _T_274 ? 3'h5 : _T_281; // @[axi4_to_ahb.scala 313:26] + wire [2:0] _GEN_4 = _T_265 ? _T_282 : 3'h0; // @[Conditional.scala 39:67] + wire [2:0] _GEN_17 = _T_172 ? 3'h4 : _GEN_4; // @[Conditional.scala 39:67] + wire [2:0] _GEN_32 = _T_170 ? 3'h5 : _GEN_17; // @[Conditional.scala 39:67] + wire [2:0] _GEN_47 = _T_159 ? 3'h3 : _GEN_32; // @[Conditional.scala 39:67] + wire [2:0] _GEN_73 = _T_124 ? 3'h0 : _GEN_47; // @[Conditional.scala 39:67] + wire [2:0] _GEN_88 = _T_94 ? 3'h0 : _GEN_73; // @[Conditional.scala 39:67] + wire [2:0] buf_nxtstate = _T_42 ? 3'h0 : _GEN_88; // @[Conditional.scala 40:58] + wire _T_345 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 322:55] + wire _T_346 = buf_state_en & _T_345; // @[axi4_to_ahb.scala 322:39] + wire _GEN_13 = _T_265 ? _T_346 : _T_428; // @[Conditional.scala 39:67] + wire _GEN_31 = _T_172 ? 1'h0 : _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_46 = _T_170 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_49 = _T_159 ? buf_state_en : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_67 = _T_124 ? _T_142 : _GEN_49; // @[Conditional.scala 39:67] + wire _GEN_87 = _T_94 ? 1'h0 : _GEN_67; // @[Conditional.scala 39:67] + wire slave_valid_pre = _T_42 ? 1'h0 : _GEN_87; // @[Conditional.scala 40:58] + wire _T_18 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 202:32] + wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 150:21 axi4_to_ahb.scala 457:12] reg slvbuf_error; // @[Reg.scala 27:20] - wire [1:0] _T_603 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_604 = _T_603 & 2'h2; // @[axi4_to_ahb.scala 344:88] - wire [3:0] slave_opc = {_T_601,_T_604}; // @[Cat.scala 29:58] - wire [1:0] _T_44 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 203:49] + wire [1:0] _T_582 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_583 = _T_582 & 2'h2; // @[axi4_to_ahb.scala 359:88] + wire [3:0] slave_opc = {2'h0,_T_583}; // @[Cat.scala 29:58] + wire [1:0] _T_23 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 203:49] reg slvbuf_tag; // @[Reg.scala 27:20] - wire _T_49 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 206:65] + wire _T_28 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 206:65] reg [31:0] last_bus_addr; // @[Reg.scala 27:20] - wire [63:0] _T_608 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] - wire _T_609 = buf_state == 3'h5; // @[axi4_to_ahb.scala 345:91] + wire [63:0] _T_587 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] + wire _T_588 = buf_state == 3'h5; // @[axi4_to_ahb.scala 360:91] reg [63:0] buf_data; // @[el2_lib.scala 514:16] - wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 154:27 axi4_to_ahb.scala 435:17] - reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 424:12] - wire [63:0] _T_612 = _T_609 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 345:79] - wire _T_60 = _T | _T_2; // @[axi4_to_ahb.scala 213:74] - wire _GEN_8 = _T_286 & _T_149; // @[Conditional.scala 39:67] - wire _GEN_29 = _T_193 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] - wire _GEN_46 = _T_191 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] - wire _GEN_63 = _T_180 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] - wire _GEN_81 = _T_145 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] - wire _GEN_97 = _T_115 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] - wire buf_write_in = _T_63 ? _T_149 : _GEN_97; // @[Conditional.scala 40:58] - wire _T_69 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 229:54] - wire _T_70 = buf_state_en & _T_69; // @[axi4_to_ahb.scala 229:38] - wire [2:0] _T_100 = wrbuf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16] - wire [2:0] _T_101 = wrbuf_byteen[6] ? 3'h6 : _T_100; // @[Mux.scala 98:16] - wire [2:0] _T_102 = wrbuf_byteen[5] ? 3'h5 : _T_101; // @[Mux.scala 98:16] - wire [2:0] _T_103 = wrbuf_byteen[4] ? 3'h4 : _T_102; // @[Mux.scala 98:16] - wire [2:0] _T_104 = wrbuf_byteen[3] ? 3'h3 : _T_103; // @[Mux.scala 98:16] - wire [2:0] _T_105 = wrbuf_byteen[2] ? 3'h2 : _T_104; // @[Mux.scala 98:16] - wire [2:0] _T_106 = wrbuf_byteen[1] ? 3'h1 : _T_105; // @[Mux.scala 98:16] - wire [2:0] _T_107 = wrbuf_byteen[0] ? 3'h0 : _T_106; // @[Mux.scala 98:16] - wire [2:0] _T_109 = buf_write_in ? _T_107 : master_addr[2:0]; // @[axi4_to_ahb.scala 232:30] - wire _T_110 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 234:51] - wire _T_135 = master_ready & master_valid; // @[axi4_to_ahb.scala 245:33] - wire _T_168 = _T_135 & _T_133; // @[axi4_to_ahb.scala 260:48] - wire _T_169 = _T_168 & buf_state_en; // @[axi4_to_ahb.scala 260:79] - wire _T_357 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 305:33] - wire _T_359 = _T_357 & _T_69; // @[axi4_to_ahb.scala 305:48] - wire _GEN_12 = _T_286 & _T_359; // @[Conditional.scala 39:67] - wire _GEN_32 = _T_193 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] - wire _GEN_48 = _T_191 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] - wire _GEN_65 = _T_180 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] - wire _GEN_75 = _T_145 ? _T_169 : _GEN_65; // @[Conditional.scala 39:67] - wire _GEN_88 = _T_115 ? _T_135 : _GEN_75; // @[Conditional.scala 39:67] - wire bypass_en = _T_63 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] - wire [1:0] _T_113 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_114 = _T_113 & 2'h2; // @[axi4_to_ahb.scala 235:45] - wire _T_117 = master_opc == 3'h0; // @[axi4_to_ahb.scala 239:61] - wire _T_118 = master_valid & _T_117; // @[axi4_to_ahb.scala 239:41] - wire _T_126 = ~master_valid; // @[axi4_to_ahb.scala 241:34] - wire _T_127 = buf_state_en & _T_126; // @[axi4_to_ahb.scala 241:32] + wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 154:27 axi4_to_ahb.scala 460:17] + reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 449:12] + wire [63:0] _T_591 = _T_588 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 360:79] + wire _T_37 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 213:56] + wire _T_38 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 213:91] + wire _T_39 = _T_37 | _T_38; // @[axi4_to_ahb.scala 213:74] + wire [2:0] _T_99 = io_axi_arvalid ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 254:28] + wire _T_112 = _T_99 == 3'h6; // @[axi4_to_ahb.scala 258:107] + wire _T_113 = _T_104 & _T_112; // @[axi4_to_ahb.scala 258:91] + wire _T_114 = _T_113 & io_axi_arvalid; // @[axi4_to_ahb.scala 260:33] + wire _T_126 = ahb_hready_q & _T_141; // @[axi4_to_ahb.scala 266:39] + wire _T_145 = _T_126 & io_axi_arvalid; // @[axi4_to_ahb.scala 275:33] + wire _T_132 = io_axi_arvalid & _T_126; // @[axi4_to_ahb.scala 267:34] + wire _T_285 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 317:50] + wire _T_286 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 317:78] + wire _T_287 = _T_285 | _T_286; // @[axi4_to_ahb.scala 317:62] + wire _T_288 = buf_state_en & _T_287; // @[axi4_to_ahb.scala 317:33] + wire _GEN_8 = _T_265 & _T_288; // @[Conditional.scala 39:67] + wire _GEN_28 = _T_172 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] + wire _GEN_44 = _T_170 ? 1'h0 : _GEN_28; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_159 ? 1'h0 : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_124 ? _T_132 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_80 = _T_94 ? _T_113 : _GEN_62; // @[Conditional.scala 39:67] + wire buf_wr_en = _T_42 ? buf_state_en : _GEN_80; // @[Conditional.scala 40:58] + wire [2:0] _T_138 = buf_wr_en ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 268:69] + wire [2:0] _T_139 = ahb_hresp_q ? 3'h7 : _T_138; // @[axi4_to_ahb.scala 268:28] + wire _T_146 = _T_139 == 3'h6; // @[axi4_to_ahb.scala 275:64] + wire _T_147 = _T_145 & _T_146; // @[axi4_to_ahb.scala 275:48] + wire _T_148 = _T_147 & buf_state_en; // @[axi4_to_ahb.scala 275:79] + wire _GEN_69 = _T_124 & _T_148; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_94 ? _T_114 : _GEN_69; // @[Conditional.scala 39:67] + wire bypass_en = _T_42 ? buf_state_en : _GEN_81; // @[Conditional.scala 40:58] + wire [1:0] _T_92 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_93 = _T_92 & 2'h2; // @[axi4_to_ahb.scala 250:45] + wire _T_105 = ~io_axi_arvalid; // @[axi4_to_ahb.scala 256:34] + wire _T_106 = buf_state_en & _T_105; // @[axi4_to_ahb.scala 256:32] reg [31:0] buf_addr; // @[el2_lib.scala 514:16] - wire [2:0] _T_139 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 246:30] - wire _T_140 = ~buf_state_en; // @[axi4_to_ahb.scala 247:44] - wire _T_141 = _T_140 | bypass_en; // @[axi4_to_ahb.scala 247:58] - wire [1:0] _T_143 = _T_141 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_144 = 2'h2 & _T_143; // @[axi4_to_ahb.scala 247:32] - wire _T_156 = _T_4 & _T_117; // @[axi4_to_ahb.scala 252:49] - wire _T_308 = _T_69 | _T_110; // @[axi4_to_ahb.scala 302:62] - wire _T_309 = buf_state_en & _T_308; // @[axi4_to_ahb.scala 302:33] - wire _GEN_9 = _T_286 & _T_309; // @[Conditional.scala 39:67] - wire _GEN_30 = _T_193 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] - wire _GEN_47 = _T_191 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] - wire _GEN_64 = _T_180 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] - wire _GEN_67 = _T_145 ? _T_156 : _GEN_64; // @[Conditional.scala 39:67] - wire _GEN_87 = _T_115 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] - wire buf_wr_en = _T_63 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] - wire _T_174 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 262:59] - wire _T_175 = _T_174 & buf_state_en; // @[axi4_to_ahb.scala 262:74] - wire _T_176 = ~_T_175; // @[axi4_to_ahb.scala 262:43] - wire [1:0] _T_178 = _T_176 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_179 = 2'h2 & _T_178; // @[axi4_to_ahb.scala 262:32] - wire [1:0] _T_189 = _T_140 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_190 = 2'h2 & _T_189; // @[axi4_to_ahb.scala 272:37] + wire [2:0] _T_118 = bypass_en ? io_axi_araddr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 261:30] + wire _T_119 = ~buf_state_en; // @[axi4_to_ahb.scala 262:44] + wire _T_120 = _T_119 | bypass_en; // @[axi4_to_ahb.scala 262:58] + wire [1:0] _T_122 = _T_120 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_123 = 2'h2 & _T_122; // @[axi4_to_ahb.scala 262:32] + wire _T_153 = _T_139 != 3'h6; // @[axi4_to_ahb.scala 277:59] + wire _T_154 = _T_153 & buf_state_en; // @[axi4_to_ahb.scala 277:74] + wire _T_155 = ~_T_154; // @[axi4_to_ahb.scala 277:43] + wire [1:0] _T_157 = _T_155 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_158 = 2'h2 & _T_157; // @[axi4_to_ahb.scala 277:32] + wire [1:0] _T_168 = _T_119 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_169 = 2'h2 & _T_168; // @[axi4_to_ahb.scala 287:37] reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] - reg [7:0] buf_byteen; // @[Reg.scala 27:20] - wire [2:0] _T_202 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 176:52] - wire _T_205 = 3'h0 >= _T_202; // @[axi4_to_ahb.scala 177:62] - wire _T_206 = buf_byteen[0] & _T_205; // @[axi4_to_ahb.scala 177:48] - wire _T_208 = 3'h1 >= _T_202; // @[axi4_to_ahb.scala 177:62] - wire _T_209 = buf_byteen[1] & _T_208; // @[axi4_to_ahb.scala 177:48] - wire _T_211 = 3'h2 >= _T_202; // @[axi4_to_ahb.scala 177:62] - wire _T_212 = buf_byteen[2] & _T_211; // @[axi4_to_ahb.scala 177:48] - wire _T_214 = 3'h3 >= _T_202; // @[axi4_to_ahb.scala 177:62] - wire _T_215 = buf_byteen[3] & _T_214; // @[axi4_to_ahb.scala 177:48] - wire _T_217 = 3'h4 >= _T_202; // @[axi4_to_ahb.scala 177:62] - wire _T_218 = buf_byteen[4] & _T_217; // @[axi4_to_ahb.scala 177:48] - wire _T_220 = 3'h5 >= _T_202; // @[axi4_to_ahb.scala 177:62] - wire _T_221 = buf_byteen[5] & _T_220; // @[axi4_to_ahb.scala 177:48] - wire _T_223 = 3'h6 >= _T_202; // @[axi4_to_ahb.scala 177:62] - wire _T_224 = buf_byteen[6] & _T_223; // @[axi4_to_ahb.scala 177:48] - wire [2:0] _T_228 = buf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16] - wire [2:0] _T_229 = _T_224 ? 3'h6 : _T_228; // @[Mux.scala 98:16] - wire [2:0] _T_230 = _T_221 ? 3'h5 : _T_229; // @[Mux.scala 98:16] - wire [2:0] _T_231 = _T_218 ? 3'h4 : _T_230; // @[Mux.scala 98:16] - wire [2:0] _T_232 = _T_215 ? 3'h3 : _T_231; // @[Mux.scala 98:16] - wire [2:0] _T_233 = _T_212 ? 3'h2 : _T_232; // @[Mux.scala 98:16] - wire [2:0] _T_234 = _T_209 ? 3'h1 : _T_233; // @[Mux.scala 98:16] - wire [2:0] _T_235 = _T_206 ? 3'h0 : _T_234; // @[Mux.scala 98:16] - wire [2:0] _T_236 = trxn_done ? _T_235 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 290:30] - wire _T_237 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 291:65] + wire [2:0] _T_215 = trxn_done ? 3'h0 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 305:30] reg buf_aligned; // @[Reg.scala 27:20] - wire _T_238 = buf_aligned | _T_237; // @[axi4_to_ahb.scala 291:44] - wire [7:0] _T_276 = buf_byteen >> _T_235; // @[axi4_to_ahb.scala 291:92] - wire _T_278 = ~_T_276[0]; // @[axi4_to_ahb.scala 291:163] - wire _T_279 = _T_238 | _T_278; // @[axi4_to_ahb.scala 291:79] - wire _T_280 = trxn_done & _T_279; // @[axi4_to_ahb.scala 291:29] - wire _T_354 = _T_237 | _T_278; // @[axi4_to_ahb.scala 304:118] - wire _T_355 = _T_130 & _T_354; // @[axi4_to_ahb.scala 304:82] - wire _T_356 = ahb_hresp_q | _T_355; // @[axi4_to_ahb.scala 304:32] - wire _GEN_11 = _T_286 & _T_356; // @[Conditional.scala 39:67] - wire _GEN_24 = _T_193 ? _T_280 : _GEN_11; // @[Conditional.scala 39:67] - wire _GEN_43 = _T_191 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] - wire _GEN_61 = _T_180 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] - wire _GEN_74 = _T_145 ? _T_127 : _GEN_61; // @[Conditional.scala 39:67] - wire _GEN_84 = _T_115 ? _T_127 : _GEN_74; // @[Conditional.scala 39:67] - wire cmd_done = _T_63 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] - wire _T_281 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 292:43] - wire _T_282 = ~_T_281; // @[axi4_to_ahb.scala 292:32] - wire [1:0] _T_284 = _T_282 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_285 = _T_284 & 2'h2; // @[axi4_to_ahb.scala 292:57] - wire _T_294 = ~slave_ready; // @[axi4_to_ahb.scala 298:42] - wire _T_295 = ahb_hresp_q | _T_294; // @[axi4_to_ahb.scala 298:40] - wire _T_362 = _T_282 | bypass_en; // @[axi4_to_ahb.scala 306:57] - wire [1:0] _T_364 = _T_362 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_365 = _T_364 & 2'h2; // @[axi4_to_ahb.scala 306:71] - wire _T_372 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 309:40] - wire [2:0] _T_448 = bypass_en ? _T_107 : _T_236; // @[axi4_to_ahb.scala 312:30] - wire _GEN_6 = _T_286 & ahb_hresp_q; // @[Conditional.scala 39:67] - wire _GEN_7 = _T_286 ? buf_state_en : _T_449; // @[Conditional.scala 39:67] - wire _GEN_10 = _T_286 & buf_wr_en; // @[Conditional.scala 39:67] - wire [1:0] _GEN_13 = _T_286 ? _T_365 : 2'h0; // @[Conditional.scala 39:67] - wire _GEN_16 = _T_286 & _T_372; // @[Conditional.scala 39:67] - wire [2:0] _GEN_17 = _T_286 ? _T_448 : 3'h0; // @[Conditional.scala 39:67] - wire _GEN_21 = _T_193 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] - wire _GEN_22 = _T_193 & buf_state_en; // @[Conditional.scala 39:67] - wire [2:0] _GEN_23 = _T_193 ? _T_236 : _GEN_17; // @[Conditional.scala 39:67] - wire [1:0] _GEN_25 = _T_193 ? _T_285 : _GEN_13; // @[Conditional.scala 39:67] - wire _GEN_28 = _T_193 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] - wire _GEN_31 = _T_193 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] - wire _GEN_36 = _T_191 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] - wire _GEN_38 = _T_191 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] - wire _GEN_39 = _T_191 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] - wire _GEN_41 = _T_191 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] - wire [2:0] _GEN_42 = _T_191 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67] - wire [1:0] _GEN_44 = _T_191 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] - wire _GEN_53 = _T_180 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] - wire [2:0] _GEN_54 = _T_180 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67] - wire [1:0] _GEN_55 = _T_180 ? _T_190 : _GEN_44; // @[Conditional.scala 39:67] - wire _GEN_56 = _T_180 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] - wire _GEN_58 = _T_180 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] - wire _GEN_60 = _T_180 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] - wire _GEN_70 = _T_145 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] - wire _GEN_72 = _T_145 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] - wire [2:0] _GEN_76 = _T_145 ? _T_139 : _GEN_54; // @[Conditional.scala 39:67] - wire [1:0] _GEN_77 = _T_145 ? _T_179 : _GEN_55; // @[Conditional.scala 39:67] - wire _GEN_78 = _T_145 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] - wire _GEN_80 = _T_145 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] - wire _GEN_85 = _T_115 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] - wire [2:0] _GEN_89 = _T_115 ? _T_139 : _GEN_76; // @[Conditional.scala 39:67] - wire [1:0] _GEN_90 = _T_115 ? _T_144 : _GEN_77; // @[Conditional.scala 39:67] - wire _GEN_91 = _T_115 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] - wire _GEN_93 = _T_115 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] - wire _GEN_96 = _T_115 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] - wire buf_data_wr_en = _T_63 ? _T_70 : _GEN_91; // @[Conditional.scala 40:58] - wire buf_cmd_byte_ptr_en = _T_63 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58] - wire [2:0] buf_cmd_byte_ptr = _T_63 ? _T_109 : _GEN_89; // @[Conditional.scala 40:58] - wire slvbuf_wr_en = _T_63 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] - wire slvbuf_error_en = _T_63 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] - wire _T_540 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 330:24] - wire _T_541 = _T_117 | _T_540; // @[axi4_to_ahb.scala 329:51] - wire _T_543 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 330:57] - wire _T_544 = _T_541 | _T_543; // @[axi4_to_ahb.scala 330:36] - wire _T_546 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 330:91] - wire _T_547 = _T_544 | _T_546; // @[axi4_to_ahb.scala 330:70] - wire _T_549 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 331:25] - wire _T_551 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 331:62] - wire _T_553 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 331:97] - wire _T_554 = _T_551 | _T_553; // @[axi4_to_ahb.scala 331:74] - wire _T_556 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 331:132] - wire _T_557 = _T_554 | _T_556; // @[axi4_to_ahb.scala 331:109] - wire _T_559 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 331:168] - wire _T_560 = _T_557 | _T_559; // @[axi4_to_ahb.scala 331:145] - wire _T_562 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 332:28] - wire _T_563 = _T_560 | _T_562; // @[axi4_to_ahb.scala 331:181] - wire _T_565 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 332:63] - wire _T_566 = _T_563 | _T_565; // @[axi4_to_ahb.scala 332:40] - wire _T_568 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 332:99] - wire _T_569 = _T_566 | _T_568; // @[axi4_to_ahb.scala 332:76] - wire _T_570 = _T_549 & _T_569; // @[axi4_to_ahb.scala 331:38] - wire buf_aligned_in = _T_547 | _T_570; // @[axi4_to_ahb.scala 330:104] - wire _T_452 = buf_aligned_in & _T_149; // @[axi4_to_ahb.scala 324:55] - wire [2:0] _T_489 = _T_452 ? 3'h0 : master_addr[2:0]; // @[axi4_to_ahb.scala 324:38] - wire [34:0] _T_490 = {master_addr,_T_489}; // @[Cat.scala 29:58] - wire _T_493 = buf_state == 3'h3; // @[axi4_to_ahb.scala 327:33] - wire _T_499 = buf_aligned_in & _T_549; // @[axi4_to_ahb.scala 328:38] - wire _T_502 = _T_499 & _T_149; // @[axi4_to_ahb.scala 328:72] - wire [1:0] _T_536 = _T_502 ? 2'h0 : master_size[1:0]; // @[axi4_to_ahb.scala 328:21] - wire [31:0] _T_575 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [31:0] _T_578 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [1:0] _T_582 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [2:0] buf_size_in = {{1'd0}, _T_536}; // @[axi4_to_ahb.scala 328:15] - wire [1:0] _T_584 = _T_582 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 335:80] - wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58] - wire [1:0] _T_587 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_335 = ahb_hresp_q | _T_102; // @[axi4_to_ahb.scala 319:32] + wire _GEN_10 = _T_265 & _T_335; // @[Conditional.scala 39:67] + wire _GEN_23 = _T_172 ? trxn_done : _GEN_10; // @[Conditional.scala 39:67] + wire _GEN_41 = _T_170 ? 1'h0 : _GEN_23; // @[Conditional.scala 39:67] + wire _GEN_58 = _T_159 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] + wire _GEN_68 = _T_124 ? _T_106 : _GEN_58; // @[Conditional.scala 39:67] + wire _GEN_78 = _T_94 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] + wire cmd_done = _T_42 ? 1'h0 : _GEN_78; // @[Conditional.scala 40:58] + wire _T_260 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 307:43] + wire _T_261 = ~_T_260; // @[axi4_to_ahb.scala 307:32] + wire [1:0] _T_263 = _T_261 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_264 = _T_263 & 2'h2; // @[axi4_to_ahb.scala 307:57] + wire _T_341 = _T_261 | bypass_en; // @[axi4_to_ahb.scala 321:57] + wire [1:0] _T_343 = _T_341 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_344 = _T_343 & 2'h2; // @[axi4_to_ahb.scala 321:71] + wire _T_351 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 324:40] + wire [2:0] _T_427 = bypass_en ? 3'h0 : _T_215; // @[axi4_to_ahb.scala 327:30] + wire _GEN_5 = _T_265 & ahb_hresp_q; // @[Conditional.scala 39:67] + wire _GEN_6 = _T_265 ? buf_state_en : _T_428; // @[Conditional.scala 39:67] + wire _GEN_9 = _T_265 & buf_wr_en; // @[Conditional.scala 39:67] + wire [1:0] _GEN_12 = _T_265 ? _T_344 : 2'h0; // @[Conditional.scala 39:67] + wire _GEN_15 = _T_265 & _T_351; // @[Conditional.scala 39:67] + wire [2:0] _GEN_16 = _T_265 ? _T_427 : 3'h0; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_172 ? buf_state_en : _GEN_15; // @[Conditional.scala 39:67] + wire _GEN_21 = _T_172 & buf_state_en; // @[Conditional.scala 39:67] + wire [2:0] _GEN_22 = _T_172 ? _T_215 : _GEN_16; // @[Conditional.scala 39:67] + wire [1:0] _GEN_24 = _T_172 ? _T_264 : _GEN_12; // @[Conditional.scala 39:67] + wire _GEN_26 = _T_172 ? 1'h0 : _GEN_6; // @[Conditional.scala 39:67] + wire _GEN_29 = _T_172 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] + wire _GEN_34 = _T_170 ? buf_state_en : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_36 = _T_170 ? buf_state_en : _GEN_26; // @[Conditional.scala 39:67] + wire _GEN_37 = _T_170 ? buf_state_en : _GEN_21; // @[Conditional.scala 39:67] + wire _GEN_39 = _T_170 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67] + wire [2:0] _GEN_40 = _T_170 ? 3'h0 : _GEN_22; // @[Conditional.scala 39:67] + wire [1:0] _GEN_42 = _T_170 ? 2'h0 : _GEN_24; // @[Conditional.scala 39:67] + wire _GEN_50 = _T_159 ? buf_state_en : _GEN_37; // @[Conditional.scala 39:67] + wire [2:0] _GEN_51 = _T_159 ? buf_addr[2:0] : _GEN_40; // @[Conditional.scala 39:67] + wire [1:0] _GEN_52 = _T_159 ? _T_169 : _GEN_42; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_159 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67] + wire _GEN_55 = _T_159 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] + wire _GEN_57 = _T_159 ? 1'h0 : _GEN_39; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_124 ? buf_state_en : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_124 ? buf_state_en : _GEN_55; // @[Conditional.scala 39:67] + wire [2:0] _GEN_70 = _T_124 ? _T_118 : _GEN_51; // @[Conditional.scala 39:67] + wire [1:0] _GEN_71 = _T_124 ? _T_158 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_72 = _T_124 ? buf_wr_en : _GEN_50; // @[Conditional.scala 39:67] + wire _GEN_75 = _T_124 ? 1'h0 : _GEN_57; // @[Conditional.scala 39:67] + wire _GEN_79 = _T_94 ? buf_state_en : _GEN_72; // @[Conditional.scala 39:67] + wire [2:0] _GEN_82 = _T_94 ? _T_118 : _GEN_70; // @[Conditional.scala 39:67] + wire [1:0] _GEN_83 = _T_94 ? _T_123 : _GEN_71; // @[Conditional.scala 39:67] + wire _GEN_84 = _T_94 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67] + wire _GEN_86 = _T_94 ? 1'h0 : _GEN_66; // @[Conditional.scala 39:67] + wire _GEN_90 = _T_94 ? 1'h0 : _GEN_75; // @[Conditional.scala 39:67] + wire buf_data_wr_en = _T_42 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] + wire buf_cmd_byte_ptr_en = _T_42 ? buf_state_en : _GEN_90; // @[Conditional.scala 40:58] + wire [2:0] buf_cmd_byte_ptr = _T_42 ? io_axi_araddr[2:0] : _GEN_82; // @[Conditional.scala 40:58] + wire slvbuf_wr_en = _T_42 ? 1'h0 : _GEN_79; // @[Conditional.scala 40:58] + wire slvbuf_error_en = _T_42 ? 1'h0 : _GEN_86; // @[Conditional.scala 40:58] + wire [34:0] _T_469 = {io_axi_araddr,io_axi_araddr[2:0]}; // @[Cat.scala 29:58] + wire _T_472 = buf_state == 3'h3; // @[axi4_to_ahb.scala 342:33] + wire [31:0] _T_554 = {io_axi_araddr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [31:0] _T_557 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [2:0] buf_size_in = {{1'd0}, io_axi_arsize[1:0]}; // @[axi4_to_ahb.scala 343:15] + wire [2:0] _T_564 = {1'h0,buf_size_in[1:0]}; // @[Cat.scala 29:58] + wire [1:0] _T_566 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] reg [1:0] buf_size; // @[Reg.scala 27:20] - wire [1:0] _T_589 = _T_587 & buf_size; // @[axi4_to_ahb.scala 335:138] - wire [2:0] _T_590 = {1'h0,_T_589}; // @[Cat.scala 29:58] - wire _T_593 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 339:33] - wire [1:0] _T_594 = {1'h1,_T_593}; // @[Cat.scala 29:58] - reg buf_write; // @[Reg.scala 27:20] - wire _T_616 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 348:40] - wire _T_617 = _T_616 & io_ahb_hready; // @[axi4_to_ahb.scala 348:52] - wire last_addr_en = _T_617 & io_ahb_hwrite; // @[axi4_to_ahb.scala 348:68] - wire _T_620 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 351:52] - wire _T_621 = ~wrbuf_rst; // @[axi4_to_ahb.scala 351:88] - wire _T_625 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 352:52] - wire [2:0] _T_646 = buf_state_en ? buf_nxtstate : buf_state; // @[axi4_to_ahb.scala 368:16] + wire [1:0] _T_568 = _T_566 & buf_size; // @[axi4_to_ahb.scala 350:138] + wire [2:0] _T_569 = {1'h0,_T_568}; // @[Cat.scala 29:58] + wire _T_572 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 354:33] + wire [1:0] _T_573 = {1'h1,_T_572}; // @[Cat.scala 29:58] + wire _T_595 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 363:40] + wire _T_596 = _T_595 & io_ahb_hready; // @[axi4_to_ahb.scala 363:52] + wire last_addr_en = _T_596 & io_ahb_hwrite; // @[axi4_to_ahb.scala 363:68] + wire [2:0] _T_646 = buf_state_en ? buf_nxtstate : buf_state; // @[axi4_to_ahb.scala 393:16] reg buf_tag; // @[Reg.scala 27:20] - wire _T_680 = ~slave_valid_pre; // @[axi4_to_ahb.scala 403:52] - wire _T_693 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 427:43] - wire _T_694 = _T_693 | io_clk_override; // @[axi4_to_ahb.scala 427:58] - wire _T_697 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 428:54] - wire _T_698 = _T_697 | io_clk_override; // @[axi4_to_ahb.scala 428:74] - wire _T_700 = buf_state != 3'h0; // @[axi4_to_ahb.scala 429:50] - wire _T_701 = _T_700 | io_clk_override; // @[axi4_to_ahb.scala 429:60] + wire _T_680 = ~slave_valid_pre; // @[axi4_to_ahb.scala 428:52] + wire _T_693 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 452:43] + wire _T_694 = _T_693 | io_clk_override; // @[axi4_to_ahb.scala 452:58] + wire _T_697 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 453:54] + wire _T_698 = _T_697 | io_clk_override; // @[axi4_to_ahb.scala 453:74] + wire _T_700 = buf_state != 3'h0; // @[axi4_to_ahb.scala 454:50] + wire _T_701 = _T_700 | io_clk_override; // @[axi4_to_ahb.scala 454:60] rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -521,36 +397,36 @@ module axi4_to_ahb( .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - assign io_axi_awready = _T_12 & master_ready; // @[axi4_to_ahb.scala 187:18] - assign io_axi_wready = _T_16 & master_ready; // @[axi4_to_ahb.scala 188:17] - assign io_axi_bvalid = _T_39 & slave_opc[3]; // @[axi4_to_ahb.scala 202:17] - assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_44; // @[axi4_to_ahb.scala 203:16] + assign io_axi_awready = 1'h0; // @[axi4_to_ahb.scala 370:18] + assign io_axi_wready = 1'h0; // @[axi4_to_ahb.scala 371:17] + assign io_axi_bvalid = _T_18 & slave_opc[3]; // @[axi4_to_ahb.scala 202:17] + assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_23; // @[axi4_to_ahb.scala 203:16] assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 204:14] - assign io_axi_arready = _T_19 & master_ready; // @[axi4_to_ahb.scala 189:18] - assign io_axi_rvalid = _T_39 & _T_49; // @[axi4_to_ahb.scala 206:17] + assign io_axi_arready = 1'h0; // @[axi4_to_ahb.scala 372:18] + assign io_axi_rvalid = _T_18 & _T_28; // @[axi4_to_ahb.scala 206:17] assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 208:14] - assign io_axi_rdata = slvbuf_error ? _T_608 : _T_612; // @[axi4_to_ahb.scala 209:16] - assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_44; // @[axi4_to_ahb.scala 207:16] - assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 190:16] - assign io_ahb_haddr = bypass_en ? _T_575 : _T_578; // @[axi4_to_ahb.scala 334:16] - assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 337:17] - assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 338:20] - assign io_ahb_hprot = {{2'd0}, _T_594}; // @[axi4_to_ahb.scala 339:16] - assign io_ahb_hsize = bypass_en ? _T_585 : _T_590; // @[axi4_to_ahb.scala 335:16] - assign io_ahb_htrans = _T_63 ? _T_114 : _GEN_90; // @[axi4_to_ahb.scala 219:17 axi4_to_ahb.scala 235:21 axi4_to_ahb.scala 247:21 axi4_to_ahb.scala 262:21 axi4_to_ahb.scala 272:21 axi4_to_ahb.scala 292:21 axi4_to_ahb.scala 306:21] - assign io_ahb_hwrite = bypass_en ? _T_149 : buf_write; // @[axi4_to_ahb.scala 340:17] - assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 341:17] + assign io_axi_rdata = slvbuf_error ? _T_587 : _T_591; // @[axi4_to_ahb.scala 209:16] + assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_23; // @[axi4_to_ahb.scala 207:16] + assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 373:16] + assign io_ahb_haddr = bypass_en ? _T_554 : _T_557; // @[axi4_to_ahb.scala 349:16] + assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 352:17] + assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 353:20] + assign io_ahb_hprot = {{2'd0}, _T_573}; // @[axi4_to_ahb.scala 354:16] + assign io_ahb_hsize = bypass_en ? _T_564 : _T_569; // @[axi4_to_ahb.scala 350:16] + assign io_ahb_htrans = _T_42 ? _T_93 : _GEN_83; // @[axi4_to_ahb.scala 219:17 axi4_to_ahb.scala 250:21 axi4_to_ahb.scala 262:21 axi4_to_ahb.scala 277:21 axi4_to_ahb.scala 287:21 axi4_to_ahb.scala 307:21 axi4_to_ahb.scala 321:21] + assign io_ahb_hwrite = 1'h0; // @[axi4_to_ahb.scala 355:17] + assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 356:17] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_1_io_en = io_bus_clk_en & _T_60; // @[el2_lib.scala 485:16] + assign rvclkhdr_1_io_en = io_bus_clk_en & _T_39; // @[el2_lib.scala 485:16] assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_2_io_en = _T & master_ready; // @[el2_lib.scala 511:17] + assign rvclkhdr_2_io_en = 1'h0; // @[el2_lib.scala 511:17] assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_3_io_en = _T_2 & master_ready; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_en = 1'h0; // @[el2_lib.scala 511:17] assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] assign rvclkhdr_4_io_en = buf_wr_en & io_bus_clk_en; // @[el2_lib.scala 511:17] @@ -605,8 +481,8 @@ initial begin `endif `endif `ifdef RANDOMIZE_REG_INIT - _RAND_0 = {1{`RANDOM}}; - buf_nxtstate = _RAND_0[2:0]; + _RAND_0 = {2{`RANDOM}}; + wrbuf_data = _RAND_0[63:0]; _RAND_1 = {1{`RANDOM}}; buf_state = _RAND_1[2:0]; _RAND_2 = {1{`RANDOM}}; @@ -618,50 +494,30 @@ initial begin _RAND_5 = {1{`RANDOM}}; ahb_hresp_q = _RAND_5[0:0]; _RAND_6 = {1{`RANDOM}}; - wrbuf_vld = _RAND_6[0:0]; + cmd_doneQ = _RAND_6[0:0]; _RAND_7 = {1{`RANDOM}}; - wrbuf_data_vld = _RAND_7[0:0]; + slvbuf_error = _RAND_7[0:0]; _RAND_8 = {1{`RANDOM}}; - cmd_doneQ = _RAND_8[0:0]; + slvbuf_tag = _RAND_8[0:0]; _RAND_9 = {1{`RANDOM}}; - wrbuf_tag = _RAND_9[0:0]; - _RAND_10 = {1{`RANDOM}}; - wrbuf_addr = _RAND_10[31:0]; - _RAND_11 = {1{`RANDOM}}; - wrbuf_size = _RAND_11[2:0]; + last_bus_addr = _RAND_9[31:0]; + _RAND_10 = {2{`RANDOM}}; + buf_data = _RAND_10[63:0]; + _RAND_11 = {2{`RANDOM}}; + ahb_hrdata_q = _RAND_11[63:0]; _RAND_12 = {1{`RANDOM}}; - wrbuf_byteen = _RAND_12[7:0]; - _RAND_13 = {2{`RANDOM}}; - wrbuf_data = _RAND_13[63:0]; + buf_addr = _RAND_12[31:0]; + _RAND_13 = {1{`RANDOM}}; + buf_cmd_byte_ptrQ = _RAND_13[2:0]; _RAND_14 = {1{`RANDOM}}; - slvbuf_write = _RAND_14[0:0]; + buf_aligned = _RAND_14[0:0]; _RAND_15 = {1{`RANDOM}}; - slvbuf_error = _RAND_15[0:0]; + buf_size = _RAND_15[1:0]; _RAND_16 = {1{`RANDOM}}; - slvbuf_tag = _RAND_16[0:0]; - _RAND_17 = {1{`RANDOM}}; - last_bus_addr = _RAND_17[31:0]; - _RAND_18 = {2{`RANDOM}}; - buf_data = _RAND_18[63:0]; - _RAND_19 = {2{`RANDOM}}; - ahb_hrdata_q = _RAND_19[63:0]; - _RAND_20 = {1{`RANDOM}}; - buf_addr = _RAND_20[31:0]; - _RAND_21 = {1{`RANDOM}}; - buf_cmd_byte_ptrQ = _RAND_21[2:0]; - _RAND_22 = {1{`RANDOM}}; - buf_byteen = _RAND_22[7:0]; - _RAND_23 = {1{`RANDOM}}; - buf_aligned = _RAND_23[0:0]; - _RAND_24 = {1{`RANDOM}}; - buf_size = _RAND_24[1:0]; - _RAND_25 = {1{`RANDOM}}; - buf_write = _RAND_25[0:0]; - _RAND_26 = {1{`RANDOM}}; - buf_tag = _RAND_26[0:0]; + buf_tag = _RAND_16[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin - buf_nxtstate = 3'h0; + wrbuf_data = 64'h0; end if (reset) begin buf_state = 3'h0; @@ -678,33 +534,9 @@ initial begin if (reset) begin ahb_hresp_q = 1'h0; end - if (reset) begin - wrbuf_vld = 1'h0; - end - if (reset) begin - wrbuf_data_vld = 1'h0; - end if (reset) begin cmd_doneQ = 1'h0; end - if (reset) begin - wrbuf_tag = 1'h0; - end - if (reset) begin - wrbuf_addr = 32'h0; - end - if (reset) begin - wrbuf_size = 3'h0; - end - if (reset) begin - wrbuf_byteen = 8'h0; - end - if (reset) begin - wrbuf_data = 64'h0; - end - if (reset) begin - slvbuf_write = 1'h0; - end if (reset) begin slvbuf_error = 1'h0; end @@ -726,18 +558,12 @@ initial begin if (reset) begin buf_cmd_byte_ptrQ = 3'h0; end - if (reset) begin - buf_byteen = 8'h0; - end if (reset) begin buf_aligned = 1'h0; end if (reset) begin buf_size = 2'h0; end - if (reset) begin - buf_write = 1'h0; - end if (reset) begin buf_tag = 1'h0; end @@ -747,49 +573,11 @@ end // initial `FIRRTL_AFTER_INITIAL `endif `endif // SYNTHESIS - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin if (reset) begin - buf_nxtstate <= 3'h0; - end else if (_T_63) begin - if (buf_write_in) begin - buf_nxtstate <= 3'h2; - end else begin - buf_nxtstate <= 3'h1; - end - end else if (_T_115) begin - if (_T_118) begin - buf_nxtstate <= 3'h6; - end else begin - buf_nxtstate <= 3'h3; - end - end else if (_T_145) begin - if (ahb_hresp_q) begin - buf_nxtstate <= 3'h7; - end else if (buf_wr_en) begin - buf_nxtstate <= 3'h6; - end else begin - buf_nxtstate <= 3'h3; - end - end else if (_T_180) begin - buf_nxtstate <= 3'h3; - end else if (_T_191) begin - buf_nxtstate <= 3'h5; - end else if (_T_193) begin - buf_nxtstate <= 3'h4; - end else if (_T_286) begin - if (_T_295) begin - buf_nxtstate <= 3'h5; - end else if (_T_4) begin - if (_T_149) begin - buf_nxtstate <= 3'h2; - end else begin - buf_nxtstate <= 3'h1; - end - end else begin - buf_nxtstate <= 3'h0; - end - end else if (_T_449) begin - buf_nxtstate <= 3'h0; + wrbuf_data <= 64'h0; + end else begin + wrbuf_data <= io_axi_wdata; end end always @(posedge ahbm_clk or posedge reset) begin @@ -827,87 +615,31 @@ end // initial ahb_hresp_q <= io_ahb_hresp; end end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_vld <= 1'h0; - end else begin - wrbuf_vld <= _T_620 & _T_621; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_data_vld <= 1'h0; - end else begin - wrbuf_data_vld <= _T_625 & _T_621; - end - end always @(posedge ahbm_clk or posedge reset) begin if (reset) begin cmd_doneQ <= 1'h0; end else begin - cmd_doneQ <= _T_281 & _T_680; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_tag <= 1'h0; - end else if (wrbuf_en) begin - wrbuf_tag <= io_axi_awid; - end - end - always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin - if (reset) begin - wrbuf_addr <= 32'h0; - end else begin - wrbuf_addr <= io_axi_awaddr; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_size <= 3'h0; - end else if (wrbuf_en) begin - wrbuf_size <= io_axi_awsize; - end - end - always @(posedge bus_clk or posedge reset) begin - if (reset) begin - wrbuf_byteen <= 8'h0; - end else if (wrbuf_data_en) begin - wrbuf_byteen <= io_axi_wstrb; - end - end - always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin - if (reset) begin - wrbuf_data <= 64'h0; - end else begin - wrbuf_data <= io_axi_wdata; - end - end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - slvbuf_write <= 1'h0; - end else if (slvbuf_wr_en) begin - slvbuf_write <= buf_write; + cmd_doneQ <= _T_260 & _T_680; end end always @(posedge ahbm_clk or posedge reset) begin if (reset) begin slvbuf_error <= 1'h0; end else if (slvbuf_error_en) begin - if (_T_63) begin + if (_T_42) begin slvbuf_error <= 1'h0; - end else if (_T_115) begin + end else if (_T_94) begin slvbuf_error <= 1'h0; - end else if (_T_145) begin + end else if (_T_124) begin slvbuf_error <= ahb_hresp_q; - end else if (_T_180) begin + end else if (_T_159) begin slvbuf_error <= 1'h0; - end else if (_T_191) begin + end else if (_T_170) begin slvbuf_error <= ahb_hresp_q; - end else if (_T_193) begin + end else if (_T_172) begin slvbuf_error <= 1'h0; end else begin - slvbuf_error <= _GEN_6; + slvbuf_error <= _GEN_5; end end end @@ -928,7 +660,7 @@ end // initial always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin buf_data <= 64'h0; - end else if (_T_493) begin + end else if (_T_472) begin buf_data <= ahb_hrdata_q; end else begin buf_data <= wrbuf_data; @@ -945,134 +677,51 @@ end // initial if (reset) begin buf_addr <= 32'h0; end else begin - buf_addr <= _T_490[31:0]; + buf_addr <= _T_469[31:0]; end end always @(posedge ahbm_clk or posedge reset) begin if (reset) begin buf_cmd_byte_ptrQ <= 3'h0; end else if (buf_cmd_byte_ptr_en) begin - if (_T_63) begin - if (buf_write_in) begin - if (wrbuf_byteen[0]) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (wrbuf_byteen[1]) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (wrbuf_byteen[2]) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (wrbuf_byteen[3]) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (wrbuf_byteen[4]) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (wrbuf_byteen[5]) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (wrbuf_byteen[6]) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else if (wrbuf_byteen[7]) begin - buf_cmd_byte_ptrQ <= 3'h7; - end else begin - buf_cmd_byte_ptrQ <= 3'h0; - end - end else begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; - end - end else if (_T_115) begin + if (_T_42) begin + buf_cmd_byte_ptrQ <= io_axi_araddr[2:0]; + end else if (_T_94) begin if (bypass_en) begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; + buf_cmd_byte_ptrQ <= io_axi_araddr[2:0]; end else begin buf_cmd_byte_ptrQ <= buf_addr[2:0]; end - end else if (_T_145) begin + end else if (_T_124) begin if (bypass_en) begin - buf_cmd_byte_ptrQ <= master_addr[2:0]; + buf_cmd_byte_ptrQ <= io_axi_araddr[2:0]; end else begin buf_cmd_byte_ptrQ <= buf_addr[2:0]; end - end else if (_T_180) begin + end else if (_T_159) begin buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end else if (_T_191) begin + end else if (_T_170) begin buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_193) begin + end else if (_T_172) begin if (trxn_done) begin - if (_T_206) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_209) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_212) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_215) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_218) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_221) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_224) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else if (buf_byteen[7]) begin - buf_cmd_byte_ptrQ <= 3'h7; - end else begin - buf_cmd_byte_ptrQ <= 3'h0; - end + buf_cmd_byte_ptrQ <= 3'h0; end - end else if (_T_286) begin + end else if (_T_265) begin if (bypass_en) begin - if (wrbuf_byteen[0]) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (wrbuf_byteen[1]) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (wrbuf_byteen[2]) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (wrbuf_byteen[3]) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (wrbuf_byteen[4]) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (wrbuf_byteen[5]) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (wrbuf_byteen[6]) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else if (wrbuf_byteen[7]) begin - buf_cmd_byte_ptrQ <= 3'h7; - end else begin - buf_cmd_byte_ptrQ <= 3'h0; - end + buf_cmd_byte_ptrQ <= 3'h0; end else if (trxn_done) begin - if (_T_206) begin - buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_209) begin - buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_212) begin - buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_215) begin - buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_218) begin - buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_221) begin - buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_224) begin - buf_cmd_byte_ptrQ <= 3'h6; - end else if (buf_byteen[7]) begin - buf_cmd_byte_ptrQ <= 3'h7; - end else begin - buf_cmd_byte_ptrQ <= 3'h0; - end + buf_cmd_byte_ptrQ <= 3'h0; end end else begin buf_cmd_byte_ptrQ <= 3'h0; end end end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_byteen <= 8'h0; - end else if (buf_wr_en) begin - buf_byteen <= wrbuf_byteen; - end - end always @(posedge buf_clk or posedge reset) begin if (reset) begin buf_aligned <= 1'h0; - end else if (buf_wr_en) begin - buf_aligned <= buf_aligned_in; + end else begin + buf_aligned <= buf_wr_en | buf_aligned; end end always @(posedge buf_clk or posedge reset) begin @@ -1082,36 +731,11 @@ end // initial buf_size <= buf_size_in[1:0]; end end - always @(posedge buf_clk or posedge reset) begin - if (reset) begin - buf_write <= 1'h0; - end else if (buf_wr_en) begin - if (_T_63) begin - buf_write <= _T_149; - end else if (_T_115) begin - buf_write <= 1'h0; - end else if (_T_145) begin - buf_write <= 1'h0; - end else if (_T_180) begin - buf_write <= 1'h0; - end else if (_T_191) begin - buf_write <= 1'h0; - end else if (_T_193) begin - buf_write <= 1'h0; - end else begin - buf_write <= _GEN_8; - end - end - end always @(posedge buf_clk or posedge reset) begin if (reset) begin buf_tag <= 1'h0; end else if (buf_wr_en) begin - if (wr_cmd_vld) begin - buf_tag <= wrbuf_tag; - end else begin - buf_tag <= io_axi_arid; - end + buf_tag <= io_axi_arid; end end endmodule diff --git a/rvjtag_tap.fir b/rvjtag_tap.fir index 4a31b428..33e0bd16 100644 --- a/rvjtag_tap.fir +++ b/rvjtag_tap.fir @@ -3,21 +3,20 @@ circuit rvjtag_tap : module rvjtag_tap : input clock : Clock input reset : AsyncReset - output io : {flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, flip rd_data : UInt<32>, flip rd_status : UInt<2>, flip idle : UInt<3>, flip dmi_stat : UInt<2>, flip jtag_id : UInt<32>, flip version : UInt<4>, tdo : UInt<1>, tdoEnable : UInt<1>, wr_data : UInt<32>, wr_addr : UInt<7>, wr_en : UInt<1>, rd_en : UInt<1>, dmi_reset : UInt<1>, dmi_hard_reset : UInt<1>} + output io : {flip trst : AsyncReset, flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, dmi_reset : UInt<1>, dmi_hard_reset : UInt<1>, flip rd_status : UInt<2>, flip dmi_stat : UInt<2>, flip idle : UInt<3>, flip version : UInt<4>, flip jtag_id : UInt<31>, flip rd_data : UInt<32>, tdo : UInt<1>, tdoEnable : UInt<1>, wr_en : UInt<1>, rd_en : UInt<1>, wr_data : UInt<32>, wr_addr : UInt<0>} - io.tdo <= UInt<1>("h00") @[rvjtag_tap.scala 38:21] - io.tdoEnable <= UInt<1>("h00") @[rvjtag_tap.scala 39:21] - io.wr_data <= UInt<1>("h00") @[rvjtag_tap.scala 40:21] - io.wr_addr <= UInt<1>("h00") @[rvjtag_tap.scala 41:21] - io.wr_en <= UInt<1>("h00") @[rvjtag_tap.scala 42:21] - io.rd_en <= UInt<1>("h00") @[rvjtag_tap.scala 43:21] - io.dmi_reset <= UInt<1>("h00") @[rvjtag_tap.scala 44:21] - io.dmi_hard_reset <= UInt<1>("h00") @[rvjtag_tap.scala 45:21] - reg sr : UInt<41>, clock with : (reset => (reset, UInt<1>("h00"))) @[rvjtag_tap.scala 48:20] - reg nsr : UInt<41>, clock with : (reset => (reset, UInt<1>("h00"))) @[rvjtag_tap.scala 49:20] - reg dr : UInt<41>, clock with : (reset => (reset, UInt<1>("h00"))) @[rvjtag_tap.scala 50:20] + wire nsr : UInt<41> + nsr <= UInt<41>("h00") + reg sr : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 32:55] + sr <= nsr @[rvjtag_tap.scala 32:55] + wire dr : UInt<41> + dr <= UInt<41>("h00") + wire nstate : UInt<4> + nstate <= UInt<4>("h00") + reg state : UInt, io.tck with : (reset => (io.trst, UInt<4>("h00"))) @[rvjtag_tap.scala 39:57] + state <= nstate @[rvjtag_tap.scala 39:57] wire ir : UInt<5> - ir <= UInt<1>("h00") + ir <= UInt<5>("h00") wire jtag_reset : UInt<1> jtag_reset <= UInt<1>("h00") wire shift_dr : UInt<1> @@ -40,182 +39,234 @@ circuit rvjtag_tap : dr_en <= UInt<1>("h00") wire devid_sel : UInt<1> devid_sel <= UInt<1>("h00") - reg state : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[rvjtag_tap.scala 75:27] - reg nstate : UInt, clock with : (reset => (reset, UInt<4>("h00"))) @[rvjtag_tap.scala 76:27] - nstate <= state @[rvjtag_tap.scala 76:27] node _T = eq(UInt<4>("h00"), state) @[Conditional.scala 37:30] when _T : @[Conditional.scala 40:58] - node _T_1 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 80:21] - when _T_1 : @[rvjtag_tap.scala 80:32] - nstate <= UInt<4>("h00") @[rvjtag_tap.scala 80:41] - skip @[rvjtag_tap.scala 80:32] - else : @[rvjtag_tap.scala 81:20] - nstate <= UInt<4>("h01") @[rvjtag_tap.scala 81:29] - skip @[rvjtag_tap.scala 81:20] + node _T_1 = mux(io.tms, UInt<4>("h00"), UInt<4>("h01")) @[rvjtag_tap.scala 55:46] + nstate <= _T_1 @[rvjtag_tap.scala 55:40] + jtag_reset <= UInt<1>("h01") @[rvjtag_tap.scala 56:18] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_2 = eq(UInt<4>("h01"), state) @[Conditional.scala 37:30] when _T_2 : @[Conditional.scala 39:67] - node _T_3 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 84:21] - when _T_3 : @[rvjtag_tap.scala 84:32] - nstate <= UInt<4>("h02") @[rvjtag_tap.scala 84:40] - skip @[rvjtag_tap.scala 84:32] - else : @[rvjtag_tap.scala 85:20] - nstate <= UInt<4>("h01") @[rvjtag_tap.scala 85:28] - skip @[rvjtag_tap.scala 85:20] + node _T_3 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 57:47] + nstate <= _T_3 @[rvjtag_tap.scala 57:41] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_4 = eq(UInt<4>("h02"), state) @[Conditional.scala 37:30] when _T_4 : @[Conditional.scala 39:67] - node _T_5 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 88:21] - when _T_5 : @[rvjtag_tap.scala 88:32] - nstate <= UInt<4>("h09") @[rvjtag_tap.scala 88:40] - skip @[rvjtag_tap.scala 88:32] - else : @[rvjtag_tap.scala 89:20] - nstate <= UInt<4>("h03") @[rvjtag_tap.scala 89:28] - skip @[rvjtag_tap.scala 89:20] + node _T_5 = mux(io.tms, UInt<4>("h09"), UInt<4>("h03")) @[rvjtag_tap.scala 58:47] + nstate <= _T_5 @[rvjtag_tap.scala 58:41] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_6 = eq(UInt<4>("h03"), state) @[Conditional.scala 37:30] when _T_6 : @[Conditional.scala 39:67] - node _T_7 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 92:21] - when _T_7 : @[rvjtag_tap.scala 92:32] - nstate <= UInt<4>("h05") @[rvjtag_tap.scala 92:40] - skip @[rvjtag_tap.scala 92:32] - else : @[rvjtag_tap.scala 93:20] - nstate <= UInt<4>("h04") @[rvjtag_tap.scala 93:28] - skip @[rvjtag_tap.scala 93:20] + node _T_7 = mux(io.tms, UInt<4>("h05"), UInt<4>("h04")) @[rvjtag_tap.scala 59:47] + nstate <= _T_7 @[rvjtag_tap.scala 59:41] + capture_dr <= UInt<1>("h01") @[rvjtag_tap.scala 60:18] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_8 = eq(UInt<4>("h04"), state) @[Conditional.scala 37:30] when _T_8 : @[Conditional.scala 39:67] - node _T_9 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 96:21] - when _T_9 : @[rvjtag_tap.scala 96:32] - nstate <= UInt<4>("h05") @[rvjtag_tap.scala 96:40] - skip @[rvjtag_tap.scala 96:32] - else : @[rvjtag_tap.scala 97:20] - nstate <= UInt<4>("h04") @[rvjtag_tap.scala 97:28] - skip @[rvjtag_tap.scala 97:20] + node _T_9 = mux(io.tms, UInt<4>("h05"), UInt<4>("h04")) @[rvjtag_tap.scala 61:47] + nstate <= _T_9 @[rvjtag_tap.scala 61:41] + shift_dr <= UInt<1>("h01") @[rvjtag_tap.scala 62:16] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_10 = eq(UInt<4>("h05"), state) @[Conditional.scala 37:30] when _T_10 : @[Conditional.scala 39:67] - node _T_11 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 100:21] - when _T_11 : @[rvjtag_tap.scala 100:32] - nstate <= UInt<4>("h08") @[rvjtag_tap.scala 100:40] - skip @[rvjtag_tap.scala 100:32] - else : @[rvjtag_tap.scala 101:20] - nstate <= UInt<4>("h06") @[rvjtag_tap.scala 101:28] - skip @[rvjtag_tap.scala 101:20] + node _T_11 = mux(io.tms, UInt<4>("h08"), UInt<4>("h06")) @[rvjtag_tap.scala 63:47] + nstate <= _T_11 @[rvjtag_tap.scala 63:41] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_12 = eq(UInt<4>("h06"), state) @[Conditional.scala 37:30] when _T_12 : @[Conditional.scala 39:67] - node _T_13 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 104:18] - when _T_13 : @[rvjtag_tap.scala 104:29] - nstate <= UInt<4>("h07") @[rvjtag_tap.scala 104:37] - skip @[rvjtag_tap.scala 104:29] - else : @[rvjtag_tap.scala 105:20] - nstate <= UInt<4>("h06") @[rvjtag_tap.scala 105:28] - skip @[rvjtag_tap.scala 105:20] + node _T_13 = mux(io.tms, UInt<4>("h07"), UInt<4>("h06")) @[rvjtag_tap.scala 64:47] + nstate <= _T_13 @[rvjtag_tap.scala 64:41] + pause_dr <= UInt<1>("h01") @[rvjtag_tap.scala 65:16] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_14 = eq(UInt<4>("h07"), state) @[Conditional.scala 37:30] when _T_14 : @[Conditional.scala 39:67] - node _T_15 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 108:18] - when _T_15 : @[rvjtag_tap.scala 108:29] - nstate <= UInt<4>("h08") @[rvjtag_tap.scala 108:37] - skip @[rvjtag_tap.scala 108:29] - else : @[rvjtag_tap.scala 109:20] - nstate <= UInt<4>("h04") @[rvjtag_tap.scala 109:28] - skip @[rvjtag_tap.scala 109:20] + node _T_15 = mux(io.tms, UInt<4>("h08"), UInt<4>("h04")) @[rvjtag_tap.scala 66:47] + nstate <= _T_15 @[rvjtag_tap.scala 66:41] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_16 = eq(UInt<4>("h08"), state) @[Conditional.scala 37:30] when _T_16 : @[Conditional.scala 39:67] - node _T_17 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 112:18] - when _T_17 : @[rvjtag_tap.scala 112:29] - nstate <= UInt<4>("h02") @[rvjtag_tap.scala 112:37] - skip @[rvjtag_tap.scala 112:29] - else : @[rvjtag_tap.scala 113:20] - nstate <= UInt<4>("h01") @[rvjtag_tap.scala 113:28] - skip @[rvjtag_tap.scala 113:20] + node _T_17 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 67:47] + nstate <= _T_17 @[rvjtag_tap.scala 67:41] + update_dr <= UInt<1>("h01") @[rvjtag_tap.scala 68:17] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_18 = eq(UInt<4>("h09"), state) @[Conditional.scala 37:30] when _T_18 : @[Conditional.scala 39:67] - node _T_19 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 116:18] - when _T_19 : @[rvjtag_tap.scala 116:29] - nstate <= UInt<4>("h09") @[rvjtag_tap.scala 116:37] - skip @[rvjtag_tap.scala 116:29] - else : @[rvjtag_tap.scala 117:20] - nstate <= UInt<4>("h0a") @[rvjtag_tap.scala 117:28] - skip @[rvjtag_tap.scala 117:20] + node _T_19 = mux(io.tms, UInt<4>("h00"), UInt<4>("h0a")) @[rvjtag_tap.scala 69:47] + nstate <= _T_19 @[rvjtag_tap.scala 69:41] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_20 = eq(UInt<4>("h0a"), state) @[Conditional.scala 37:30] when _T_20 : @[Conditional.scala 39:67] - node _T_21 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 120:18] - when _T_21 : @[rvjtag_tap.scala 120:29] - nstate <= UInt<4>("h0c") @[rvjtag_tap.scala 120:37] - skip @[rvjtag_tap.scala 120:29] - else : @[rvjtag_tap.scala 121:20] - nstate <= UInt<4>("h0b") @[rvjtag_tap.scala 121:28] - skip @[rvjtag_tap.scala 121:20] + node _T_21 = mux(io.tms, UInt<4>("h0c"), UInt<4>("h0b")) @[rvjtag_tap.scala 70:47] + nstate <= _T_21 @[rvjtag_tap.scala 70:41] + capture_ir <= UInt<1>("h01") @[rvjtag_tap.scala 71:18] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_22 = eq(UInt<4>("h0b"), state) @[Conditional.scala 37:30] when _T_22 : @[Conditional.scala 39:67] - node _T_23 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 124:18] - when _T_23 : @[rvjtag_tap.scala 124:29] - nstate <= UInt<4>("h0c") @[rvjtag_tap.scala 124:37] - skip @[rvjtag_tap.scala 124:29] - else : @[rvjtag_tap.scala 125:20] - nstate <= UInt<4>("h0b") @[rvjtag_tap.scala 125:28] - skip @[rvjtag_tap.scala 125:20] + node _T_23 = mux(io.tms, UInt<4>("h0c"), UInt<4>("h0b")) @[rvjtag_tap.scala 72:47] + nstate <= _T_23 @[rvjtag_tap.scala 72:41] + shift_ir <= UInt<1>("h01") @[rvjtag_tap.scala 73:16] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_24 = eq(UInt<4>("h0c"), state) @[Conditional.scala 37:30] when _T_24 : @[Conditional.scala 39:67] - node _T_25 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 128:18] - when _T_25 : @[rvjtag_tap.scala 128:29] - nstate <= UInt<4>("h0f") @[rvjtag_tap.scala 128:37] - skip @[rvjtag_tap.scala 128:29] - else : @[rvjtag_tap.scala 129:20] - nstate <= UInt<4>("h0d") @[rvjtag_tap.scala 129:28] - skip @[rvjtag_tap.scala 129:20] + node _T_25 = mux(io.tms, UInt<4>("h0f"), UInt<4>("h0d")) @[rvjtag_tap.scala 74:47] + nstate <= _T_25 @[rvjtag_tap.scala 74:41] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_26 = eq(UInt<4>("h0d"), state) @[Conditional.scala 37:30] when _T_26 : @[Conditional.scala 39:67] - node _T_27 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 132:18] - when _T_27 : @[rvjtag_tap.scala 132:29] - nstate <= UInt<4>("h0e") @[rvjtag_tap.scala 132:37] - skip @[rvjtag_tap.scala 132:29] - else : @[rvjtag_tap.scala 133:20] - nstate <= UInt<4>("h0d") @[rvjtag_tap.scala 133:28] - skip @[rvjtag_tap.scala 133:20] + node _T_27 = mux(io.tms, UInt<4>("h0e"), UInt<4>("h0d")) @[rvjtag_tap.scala 75:47] + nstate <= _T_27 @[rvjtag_tap.scala 75:41] + pause_ir <= UInt<1>("h01") @[rvjtag_tap.scala 76:16] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_28 = eq(UInt<4>("h0e"), state) @[Conditional.scala 37:30] when _T_28 : @[Conditional.scala 39:67] - node _T_29 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 136:18] - when _T_29 : @[rvjtag_tap.scala 136:29] - nstate <= UInt<4>("h0f") @[rvjtag_tap.scala 136:37] - skip @[rvjtag_tap.scala 136:29] - else : @[rvjtag_tap.scala 137:20] - nstate <= UInt<4>("h0b") @[rvjtag_tap.scala 137:28] - skip @[rvjtag_tap.scala 137:20] + node _T_29 = mux(io.tms, UInt<4>("h0f"), UInt<4>("h0b")) @[rvjtag_tap.scala 77:47] + nstate <= _T_29 @[rvjtag_tap.scala 77:41] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_30 = eq(UInt<4>("h0f"), state) @[Conditional.scala 37:30] when _T_30 : @[Conditional.scala 39:67] - node _T_31 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 140:18] - when _T_31 : @[rvjtag_tap.scala 140:29] - nstate <= UInt<4>("h02") @[rvjtag_tap.scala 140:37] - skip @[rvjtag_tap.scala 140:29] - else : @[rvjtag_tap.scala 141:20] - nstate <= UInt<4>("h01") @[rvjtag_tap.scala 141:28] - skip @[rvjtag_tap.scala 141:20] + node _T_31 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 78:47] + nstate <= _T_31 @[rvjtag_tap.scala 78:41] + update_ir <= UInt<1>("h01") @[rvjtag_tap.scala 79:17] skip @[Conditional.scala 39:67] + node _T_32 = or(shift_dr, shift_ir) @[rvjtag_tap.scala 81:28] + io.tdoEnable <= _T_32 @[rvjtag_tap.scala 81:16] + node _T_33 = bits(sr, 4, 0) @[rvjtag_tap.scala 85:93] + node _T_34 = eq(_T_33, UInt<1>("h00")) @[rvjtag_tap.scala 85:98] + node _T_35 = bits(_T_34, 0, 0) @[rvjtag_tap.scala 85:106] + node _T_36 = bits(sr, 4, 0) @[rvjtag_tap.scala 85:123] + node _T_37 = mux(_T_35, UInt<5>("h01f"), _T_36) @[rvjtag_tap.scala 85:89] + node _T_38 = mux(update_ir, _T_37, UInt<1>("h00")) @[rvjtag_tap.scala 85:75] + node _T_39 = mux(jtag_reset, UInt<1>("h01"), _T_38) @[rvjtag_tap.scala 85:56] + reg _T_40 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h01"))) @[rvjtag_tap.scala 85:52] + _T_40 <= _T_39 @[rvjtag_tap.scala 85:52] + ir <= _T_40 @[rvjtag_tap.scala 85:6] + node _T_41 = eq(ir, UInt<5>("h01")) @[rvjtag_tap.scala 86:18] + devid_sel <= _T_41 @[rvjtag_tap.scala 86:13] + node _T_42 = eq(ir, UInt<5>("h011")) @[rvjtag_tap.scala 87:22] + node _T_43 = eq(ir, UInt<5>("h010")) @[rvjtag_tap.scala 87:32] + node _T_44 = cat(_T_42, _T_43) @[Cat.scala 29:58] + dr_en <= _T_44 @[rvjtag_tap.scala 87:13] + node _T_45 = eq(shift_dr, UInt<1>("h01")) @[rvjtag_tap.scala 92:16] + when _T_45 : @[rvjtag_tap.scala 92:23] + node _T_46 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 93:15] + node _T_47 = eq(_T_46, UInt<1>("h01")) @[rvjtag_tap.scala 93:18] + when _T_47 : @[rvjtag_tap.scala 93:28] + node _T_48 = bits(sr, 40, 1) @[rvjtag_tap.scala 93:49] + node _T_49 = cat(io.tdi, _T_48) @[Cat.scala 29:58] + nsr <= _T_49 @[rvjtag_tap.scala 93:33] + skip @[rvjtag_tap.scala 93:28] + else : @[rvjtag_tap.scala 94:54] + node _T_50 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 94:22] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[rvjtag_tap.scala 94:25] + node _T_52 = eq(devid_sel, UInt<1>("h01")) @[rvjtag_tap.scala 94:44] + node _T_53 = or(_T_51, _T_52) @[rvjtag_tap.scala 94:32] + when _T_53 : @[rvjtag_tap.scala 94:54] + node _T_54 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12] + node _T_55 = bits(sr, 31, 1) @[rvjtag_tap.scala 94:106] + node _T_56 = cat(_T_54, io.tdi) @[Cat.scala 29:58] + node _T_57 = cat(_T_56, _T_55) @[Cat.scala 29:58] + nsr <= _T_57 @[rvjtag_tap.scala 94:59] + skip @[rvjtag_tap.scala 94:54] + else : @[rvjtag_tap.scala 95:17] + node _T_58 = mux(UInt<1>("h00"), UInt<40>("h0ffffffffff"), UInt<40>("h00")) @[Bitwise.scala 72:12] + node _T_59 = cat(_T_58, io.tdi) @[Cat.scala 29:58] + nsr <= _T_59 @[rvjtag_tap.scala 95:22] + skip @[rvjtag_tap.scala 95:17] + skip @[rvjtag_tap.scala 92:23] + else : @[rvjtag_tap.scala 97:33] + node _T_60 = eq(capture_dr, UInt<1>("h01")) @[rvjtag_tap.scala 97:26] + when _T_60 : @[rvjtag_tap.scala 97:33] + node _T_61 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 98:17] + when _T_61 : @[rvjtag_tap.scala 98:21] + node _T_62 = mux(UInt<1>("h00"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12] + node _T_63 = cat(UInt<6>("h07"), io.version) @[Cat.scala 29:58] + node _T_64 = cat(_T_62, io.idle) @[Cat.scala 29:58] + node _T_65 = cat(_T_64, io.dmi_stat) @[Cat.scala 29:58] + node _T_66 = cat(_T_65, _T_63) @[Cat.scala 29:58] + nsr <= _T_66 @[rvjtag_tap.scala 98:26] + skip @[rvjtag_tap.scala 98:21] + else : @[rvjtag_tap.scala 99:28] + node _T_67 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 99:24] + when _T_67 : @[rvjtag_tap.scala 99:28] + node _T_68 = mux(UInt<1>("h00"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12] + node _T_69 = cat(_T_68, io.rd_data) @[Cat.scala 29:58] + node _T_70 = cat(_T_69, io.rd_status) @[Cat.scala 29:58] + nsr <= _T_70 @[rvjtag_tap.scala 99:33] + skip @[rvjtag_tap.scala 99:28] + else : @[rvjtag_tap.scala 100:29] + when devid_sel : @[rvjtag_tap.scala 100:29] + node _T_71 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12] + node _T_72 = cat(_T_71, io.jtag_id) @[Cat.scala 29:58] + node _T_73 = cat(_T_72, UInt<1>("h01")) @[Cat.scala 29:58] + nsr <= _T_73 @[rvjtag_tap.scala 100:34] + skip @[rvjtag_tap.scala 100:29] + skip @[rvjtag_tap.scala 97:33] + else : @[rvjtag_tap.scala 102:30] + node _T_74 = eq(shift_ir, UInt<1>("h01")) @[rvjtag_tap.scala 102:23] + when _T_74 : @[rvjtag_tap.scala 102:30] + node _T_75 = mux(UInt<1>("h00"), UInt<36>("h0fffffffff"), UInt<36>("h00")) @[Bitwise.scala 72:12] + node _T_76 = bits(sr, 4, 1) @[rvjtag_tap.scala 102:78] + node _T_77 = cat(_T_75, io.tdi) @[Cat.scala 29:58] + node _T_78 = cat(_T_77, _T_76) @[Cat.scala 29:58] + nsr <= _T_78 @[rvjtag_tap.scala 102:35] + skip @[rvjtag_tap.scala 102:30] + else : @[rvjtag_tap.scala 103:32] + node _T_79 = eq(capture_ir, UInt<1>("h01")) @[rvjtag_tap.scala 103:25] + when _T_79 : @[rvjtag_tap.scala 103:32] + node _T_80 = mux(UInt<1>("h00"), UInt<40>("h0ffffffffff"), UInt<40>("h00")) @[Bitwise.scala 72:12] + node _T_81 = cat(_T_80, UInt<1>("h01")) @[Cat.scala 29:58] + nsr <= _T_81 @[rvjtag_tap.scala 103:37] + skip @[rvjtag_tap.scala 103:32] + node _T_82 = bits(sr, 0, 0) @[rvjtag_tap.scala 106:40] + reg _T_83 : UInt<1>, io.tck with : (reset => (reset, UInt<1>("h00"))) @[rvjtag_tap.scala 106:37] + _T_83 <= _T_82 @[rvjtag_tap.scala 106:37] + io.tdo <= _T_83 @[rvjtag_tap.scala 106:28] + node _T_84 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 108:89] + node _T_85 = bits(_T_84, 0, 0) @[rvjtag_tap.scala 108:99] + node _T_86 = and(update_dr, _T_85) @[rvjtag_tap.scala 108:82] + node _T_87 = bits(sr, 17, 17) @[rvjtag_tap.scala 108:104] + node _T_88 = mux(_T_86, _T_87, UInt<1>("h00")) @[rvjtag_tap.scala 108:71] + reg _T_89 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 108:67] + _T_89 <= _T_88 @[rvjtag_tap.scala 108:67] + io.dmi_hard_reset <= _T_89 @[rvjtag_tap.scala 108:57] + node _T_90 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 109:84] + node _T_91 = bits(_T_90, 0, 0) @[rvjtag_tap.scala 109:94] + node _T_92 = and(update_dr, _T_91) @[rvjtag_tap.scala 109:77] + node _T_93 = bits(sr, 16, 16) @[rvjtag_tap.scala 109:99] + node _T_94 = mux(_T_92, _T_93, UInt<1>("h00")) @[rvjtag_tap.scala 109:66] + reg _T_95 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 109:62] + _T_95 <= _T_94 @[rvjtag_tap.scala 109:62] + io.dmi_reset <= _T_95 @[rvjtag_tap.scala 109:52] + node _T_96 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 111:74] + node _T_97 = bits(_T_96, 0, 0) @[rvjtag_tap.scala 111:84] + node _T_98 = and(update_dr, _T_97) @[rvjtag_tap.scala 111:67] + node _T_99 = bits(dr, 40, 2) @[rvjtag_tap.scala 111:96] + node _T_100 = cat(_T_99, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_101 = mux(_T_98, sr, _T_100) @[rvjtag_tap.scala 111:56] + reg _T_102 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 111:52] + _T_102 <= _T_101 @[rvjtag_tap.scala 111:52] + dr <= _T_102 @[rvjtag_tap.scala 111:42] + node _T_103 = bits(dr, 0, 0) @[rvjtag_tap.scala 113:19] + io.rd_en <= _T_103 @[rvjtag_tap.scala 113:14] + node _T_104 = bits(dr, 1, 1) @[rvjtag_tap.scala 114:19] + io.wr_en <= _T_104 @[rvjtag_tap.scala 114:14] + node _T_105 = bits(dr, 33, 2) @[rvjtag_tap.scala 115:19] + io.wr_data <= _T_105 @[rvjtag_tap.scala 115:14] + node _T_106 = bits(dr, 40, 34) @[rvjtag_tap.scala 116:19] + io.wr_addr <= _T_106 @[rvjtag_tap.scala 116:14] diff --git a/rvjtag_tap.v b/rvjtag_tap.v index 0da18247..bd77dc8d 100644 --- a/rvjtag_tap.v +++ b/rvjtag_tap.v @@ -1,30 +1,382 @@ module rvjtag_tap( input clock, input reset, + input io_trst, input io_tck, input io_tms, input io_tdi, - input [31:0] io_rd_data, + output io_dmi_reset, + output io_dmi_hard_reset, input [1:0] io_rd_status, - input [2:0] io_idle, input [1:0] io_dmi_stat, - input [31:0] io_jtag_id, + input [2:0] io_idle, input [3:0] io_version, + input [30:0] io_jtag_id, + input [31:0] io_rd_data, output io_tdo, output io_tdoEnable, - output [31:0] io_wr_data, - output [6:0] io_wr_addr, output io_wr_en, output io_rd_en, - output io_dmi_reset, - output io_dmi_hard_reset + output [31:0] io_wr_data ); - assign io_tdo = 1'h0; // @[rvjtag_tap.scala 38:21] - assign io_tdoEnable = 1'h0; // @[rvjtag_tap.scala 39:21] - assign io_wr_data = 32'h0; // @[rvjtag_tap.scala 40:21] - assign io_wr_addr = 7'h0; // @[rvjtag_tap.scala 41:21] - assign io_wr_en = 1'h0; // @[rvjtag_tap.scala 42:21] - assign io_rd_en = 1'h0; // @[rvjtag_tap.scala 43:21] - assign io_dmi_reset = 1'h0; // @[rvjtag_tap.scala 44:21] - assign io_dmi_hard_reset = 1'h0; // @[rvjtag_tap.scala 45:21] +`ifdef RANDOMIZE_REG_INIT + reg [63:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [63:0] _RAND_6; +`endif // RANDOMIZE_REG_INIT + reg [40:0] sr; // @[rvjtag_tap.scala 32:55] + reg [3:0] state; // @[rvjtag_tap.scala 39:57] + wire jtag_reset = 4'h0 == state; // @[Conditional.scala 37:30] + wire _T_2 = 4'h1 == state; // @[Conditional.scala 37:30] + wire _T_4 = 4'h2 == state; // @[Conditional.scala 37:30] + wire _T_6 = 4'h3 == state; // @[Conditional.scala 37:30] + wire _T_8 = 4'h4 == state; // @[Conditional.scala 37:30] + wire _T_10 = 4'h5 == state; // @[Conditional.scala 37:30] + wire _T_12 = 4'h6 == state; // @[Conditional.scala 37:30] + wire _T_14 = 4'h7 == state; // @[Conditional.scala 37:30] + wire _T_16 = 4'h8 == state; // @[Conditional.scala 37:30] + wire _T_18 = 4'h9 == state; // @[Conditional.scala 37:30] + wire _T_20 = 4'ha == state; // @[Conditional.scala 37:30] + wire _T_22 = 4'hb == state; // @[Conditional.scala 37:30] + wire _T_24 = 4'hc == state; // @[Conditional.scala 37:30] + wire _T_26 = 4'hd == state; // @[Conditional.scala 37:30] + wire _T_28 = 4'he == state; // @[Conditional.scala 37:30] + wire _T_30 = 4'hf == state; // @[Conditional.scala 37:30] + wire _GEN_3 = _T_28 ? 1'h0 : _T_30; // @[Conditional.scala 39:67] + wire _GEN_6 = _T_26 ? 1'h0 : _GEN_3; // @[Conditional.scala 39:67] + wire _GEN_9 = _T_24 ? 1'h0 : _GEN_6; // @[Conditional.scala 39:67] + wire _GEN_13 = _T_22 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] + wire _GEN_16 = _T_20 ? 1'h0 : _T_22; // @[Conditional.scala 39:67] + wire _GEN_18 = _T_20 ? 1'h0 : _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_18 ? 1'h0 : _T_20; // @[Conditional.scala 39:67] + wire _GEN_21 = _T_18 ? 1'h0 : _GEN_16; // @[Conditional.scala 39:67] + wire _GEN_23 = _T_18 ? 1'h0 : _GEN_18; // @[Conditional.scala 39:67] + wire _GEN_26 = _T_16 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67] + wire _GEN_27 = _T_16 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] + wire _GEN_29 = _T_16 ? 1'h0 : _GEN_23; // @[Conditional.scala 39:67] + wire _GEN_31 = _T_14 ? 1'h0 : _T_16; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_14 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] + wire _GEN_33 = _T_14 ? 1'h0 : _GEN_27; // @[Conditional.scala 39:67] + wire _GEN_35 = _T_14 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_12 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_39 = _T_12 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_40 = _T_12 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] + wire _GEN_42 = _T_12 ? 1'h0 : _GEN_35; // @[Conditional.scala 39:67] + wire _GEN_45 = _T_10 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] + wire _GEN_46 = _T_10 ? 1'h0 : _GEN_39; // @[Conditional.scala 39:67] + wire _GEN_47 = _T_10 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] + wire _GEN_49 = _T_10 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_8 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] + wire _GEN_54 = _T_8 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_55 = _T_8 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] + wire _GEN_57 = _T_8 ? 1'h0 : _GEN_49; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_6 ? 1'h0 : _T_8; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_6 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_6 ? 1'h0 : _GEN_54; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_6 ? 1'h0 : _GEN_55; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_6 ? 1'h0 : _GEN_57; // @[Conditional.scala 39:67] + wire _GEN_68 = _T_4 ? 1'h0 : _T_6; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_4 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_71 = _T_4 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67] + wire _GEN_72 = _T_4 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_4 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67] + wire _GEN_75 = _T_4 ? 1'h0 : _GEN_66; // @[Conditional.scala 39:67] + wire _GEN_77 = _T_2 ? 1'h0 : _GEN_68; // @[Conditional.scala 39:67] + wire _GEN_78 = _T_2 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67] + wire _GEN_80 = _T_2 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_2 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] + wire _GEN_82 = _T_2 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] + wire _GEN_84 = _T_2 ? 1'h0 : _GEN_75; // @[Conditional.scala 39:67] + wire capture_dr = jtag_reset ? 1'h0 : _GEN_77; // @[Conditional.scala 40:58] + wire shift_dr = jtag_reset ? 1'h0 : _GEN_78; // @[Conditional.scala 40:58] + wire update_dr = jtag_reset ? 1'h0 : _GEN_80; // @[Conditional.scala 40:58] + wire capture_ir = jtag_reset ? 1'h0 : _GEN_81; // @[Conditional.scala 40:58] + wire shift_ir = jtag_reset ? 1'h0 : _GEN_82; // @[Conditional.scala 40:58] + wire update_ir = jtag_reset ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] + wire _T_34 = sr[4:0] == 5'h0; // @[rvjtag_tap.scala 85:98] + reg [4:0] ir; // @[rvjtag_tap.scala 85:52] + wire devid_sel = ir == 5'h1; // @[rvjtag_tap.scala 86:18] + wire _T_42 = ir == 5'h11; // @[rvjtag_tap.scala 87:22] + wire _T_43 = ir == 5'h10; // @[rvjtag_tap.scala 87:32] + wire [1:0] dr_en = {_T_42,_T_43}; // @[Cat.scala 29:58] + wire [40:0] _T_49 = {io_tdi,sr[40:1]}; // @[Cat.scala 29:58] + wire _T_53 = dr_en[0] | devid_sel; // @[rvjtag_tap.scala 94:32] + wire [40:0] _T_57 = {9'h0,io_tdi,sr[31:1]}; // @[Cat.scala 29:58] + wire [40:0] _T_59 = {40'h0,io_tdi}; // @[Cat.scala 29:58] + wire [40:0] _T_66 = {26'h0,io_idle,io_dmi_stat,6'h7,io_version}; // @[Cat.scala 29:58] + wire [40:0] _T_70 = {7'h0,io_rd_data,io_rd_status}; // @[Cat.scala 29:58] + wire [40:0] _T_73 = {9'h0,io_jtag_id,1'h1}; // @[Cat.scala 29:58] + wire [40:0] _T_78 = {36'h0,io_tdi,sr[4:1]}; // @[Cat.scala 29:58] + reg _T_83; // @[rvjtag_tap.scala 106:37] + wire _T_86 = update_dr & dr_en[0]; // @[rvjtag_tap.scala 108:82] + reg _T_89; // @[rvjtag_tap.scala 108:67] + reg _T_95; // @[rvjtag_tap.scala 109:62] + wire _T_98 = update_dr & dr_en[1]; // @[rvjtag_tap.scala 111:67] + reg [40:0] dr; // @[rvjtag_tap.scala 111:52] + wire [40:0] _T_100 = {dr[40:2],2'h0}; // @[Cat.scala 29:58] + assign io_dmi_reset = _T_95; // @[rvjtag_tap.scala 109:52] + assign io_dmi_hard_reset = _T_89; // @[rvjtag_tap.scala 108:57] + assign io_tdo = _T_83; // @[rvjtag_tap.scala 106:28] + assign io_tdoEnable = shift_dr | shift_ir; // @[rvjtag_tap.scala 81:16] + assign io_wr_en = dr[1]; // @[rvjtag_tap.scala 114:14] + assign io_rd_en = dr[0]; // @[rvjtag_tap.scala 113:14] + assign io_wr_data = dr[33:2]; // @[rvjtag_tap.scala 115:14] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {2{`RANDOM}}; + sr = _RAND_0[40:0]; + _RAND_1 = {1{`RANDOM}}; + state = _RAND_1[3:0]; + _RAND_2 = {1{`RANDOM}}; + ir = _RAND_2[4:0]; + _RAND_3 = {1{`RANDOM}}; + _T_83 = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + _T_89 = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + _T_95 = _RAND_5[0:0]; + _RAND_6 = {2{`RANDOM}}; + dr = _RAND_6[40:0]; +`endif // RANDOMIZE_REG_INIT + if (io_trst) begin + sr = 41'h0; + end + if (io_trst) begin + state = 4'h0; + end + if (io_trst) begin + ir = 5'h1; + end + if (reset) begin + _T_83 = 1'h0; + end + if (io_trst) begin + _T_89 = 1'h0; + end + if (io_trst) begin + _T_95 = 1'h0; + end + if (io_trst) begin + dr = 41'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_tck or posedge io_trst) begin + if (io_trst) begin + sr <= 41'h0; + end else if (shift_dr) begin + if (dr_en[1]) begin + sr <= _T_49; + end else if (_T_53) begin + sr <= _T_57; + end else begin + sr <= _T_59; + end + end else if (capture_dr) begin + if (dr_en[0]) begin + sr <= _T_66; + end else if (dr_en[1]) begin + sr <= _T_70; + end else if (devid_sel) begin + sr <= _T_73; + end else begin + sr <= 41'h0; + end + end else if (shift_ir) begin + sr <= _T_78; + end else if (capture_ir) begin + sr <= 41'h1; + end else begin + sr <= 41'h0; + end + end + always @(posedge io_tck or posedge io_trst) begin + if (io_trst) begin + state <= 4'h0; + end else if (jtag_reset) begin + if (io_tms) begin + state <= 4'h0; + end else begin + state <= 4'h1; + end + end else if (_T_2) begin + if (io_tms) begin + state <= 4'h2; + end else begin + state <= 4'h1; + end + end else if (_T_4) begin + if (io_tms) begin + state <= 4'h9; + end else begin + state <= 4'h3; + end + end else if (_T_6) begin + if (io_tms) begin + state <= 4'h5; + end else begin + state <= 4'h4; + end + end else if (_T_8) begin + if (io_tms) begin + state <= 4'h5; + end else begin + state <= 4'h4; + end + end else if (_T_10) begin + if (io_tms) begin + state <= 4'h8; + end else begin + state <= 4'h6; + end + end else if (_T_12) begin + if (io_tms) begin + state <= 4'h7; + end else begin + state <= 4'h6; + end + end else if (_T_14) begin + if (io_tms) begin + state <= 4'h8; + end else begin + state <= 4'h4; + end + end else if (_T_16) begin + if (io_tms) begin + state <= 4'h2; + end else begin + state <= 4'h1; + end + end else if (_T_18) begin + if (io_tms) begin + state <= 4'h0; + end else begin + state <= 4'ha; + end + end else if (_T_20) begin + if (io_tms) begin + state <= 4'hc; + end else begin + state <= 4'hb; + end + end else if (_T_22) begin + if (io_tms) begin + state <= 4'hc; + end else begin + state <= 4'hb; + end + end else if (_T_24) begin + if (io_tms) begin + state <= 4'hf; + end else begin + state <= 4'hd; + end + end else if (_T_26) begin + if (io_tms) begin + state <= 4'he; + end else begin + state <= 4'hd; + end + end else if (_T_28) begin + if (io_tms) begin + state <= 4'hf; + end else begin + state <= 4'hb; + end + end else if (_T_30) begin + if (io_tms) begin + state <= 4'h2; + end else begin + state <= 4'h1; + end + end else begin + state <= 4'h0; + end + end + always @(posedge io_tck or posedge io_trst) begin + if (io_trst) begin + ir <= 5'h1; + end else if (jtag_reset) begin + ir <= 5'h1; + end else if (update_ir) begin + if (_T_34) begin + ir <= 5'h1f; + end else begin + ir <= sr[4:0]; + end + end else begin + ir <= 5'h0; + end + end + always @(posedge io_tck or posedge reset) begin + if (reset) begin + _T_83 <= 1'h0; + end else begin + _T_83 <= sr[0]; + end + end + always @(posedge io_tck or posedge io_trst) begin + if (io_trst) begin + _T_89 <= 1'h0; + end else begin + _T_89 <= _T_86 & sr[17]; + end + end + always @(posedge io_tck or posedge io_trst) begin + if (io_trst) begin + _T_95 <= 1'h0; + end else begin + _T_95 <= _T_86 & sr[16]; + end + end + always @(posedge io_tck or posedge io_trst) begin + if (io_trst) begin + dr <= 41'h0; + end else if (_T_98) begin + dr <= sr; + end else begin + dr <= _T_100; + end + end endmodule diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala index 5fb3b7f8..d79b6599 100644 --- a/src/main/scala/lib/axi4_to_ahb.scala +++ b/src/main/scala/lib/axi4_to_ahb.scala @@ -57,9 +57,9 @@ class axi4_to_ahb_IO extends Bundle with Config { class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config { val io = IO(new axi4_to_ahb_IO) - val idle :: cmd_rd :: cmd_wr :: data_rd :: data_wr :: done :: stream_rd :: stream_err_rd :: nil = Enum(8) + val idle :: cmd_rd :: cmd_wr :: data_rd :: data_wr :: done :: stream_rd :: stream_err_rd :: Nil = Enum(8) val buf_state = WireInit(idle) - val buf_nxtstate = RegInit(idle) + val buf_nxtstate = WireInit(idle) //logic signals val slave_valid = WireInit(Bool(), init = false.B) val slave_ready = WireInit(Bool(), init = false.B) @@ -178,16 +178,16 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config MuxCase(0.U, temp) } - // Write buffer - wrbuf_en := io.axi_awvalid & io.axi_awready & master_ready - wrbuf_data_en := io.axi_wvalid & io.axi_wready & master_ready - wrbuf_cmd_sent := master_valid & master_ready & (master_opc(2, 1) === "b01".U) - wrbuf_rst := wrbuf_cmd_sent & !wrbuf_en - - io.axi_awready := !(wrbuf_vld & !wrbuf_cmd_sent) & master_ready - io.axi_wready := !(wrbuf_data_vld & !wrbuf_cmd_sent) & master_ready - io.axi_arready := !(wrbuf_vld & wrbuf_data_vld) & master_ready - io.axi_rlast := true.B +// // Write buffer +// wrbuf_en := io.axi_awvalid & io.axi_awready & master_ready +// wrbuf_data_en := io.axi_wvalid & io.axi_wready & master_ready +// wrbuf_cmd_sent := master_valid & master_ready & (master_opc(2, 1) === "b01".U) +// wrbuf_rst := wrbuf_cmd_sent & !wrbuf_en +// +// io.axi_awready := !(wrbuf_vld & !wrbuf_cmd_sent) & master_ready +// io.axi_wready := !(wrbuf_data_vld & !wrbuf_cmd_sent) & master_ready +// io.axi_arready := !(wrbuf_vld & wrbuf_data_vld) & master_ready +// io.axi_rlast := true.B wr_cmd_vld := wrbuf_vld & wrbuf_data_vld master_valid := wr_cmd_vld | io.axi_arvalid @@ -217,13 +217,28 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config //State machine io.ahb_htrans := 0.U - master_ready := 0.U - buf_state_en := 0.U + //master_ready := 0.U + buf_state_en := false.B + buf_nxtstate := idle + buf_wr_en := 0.U + buf_data_wr_en := 0.U + slvbuf_error_in := 0.U + slvbuf_error_en := 0.U + buf_write_in := 0.U + cmd_done := 0.U + trxn_done := 0.U + buf_cmd_byte_ptr_en := 0.U + buf_cmd_byte_ptr := 0.U + slave_valid_pre := 0.U + slvbuf_wr_en := 0.U + bypass_en := 0.U + rd_bypass_idle := 0.U + switch(buf_state) { is(idle) { - master_ready := 1.U + val master_ready = 1.U buf_write_in := (master_opc(2, 1) === "b01".U) - buf_nxtstate := Mux(buf_write_in.asBool(), cmd_wr, cmd_rd) + val buf_nxtstate = Mux(buf_write_in.asBool(), cmd_wr, cmd_rd) buf_state_en := master_valid & master_ready buf_wr_en := buf_state_en buf_data_wr_en := buf_state_en & (buf_nxtstate === cmd_wr) @@ -236,11 +251,11 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config } is(cmd_rd) { - buf_nxtstate := Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd) + val buf_nxtstate = Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd) buf_state_en := ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q cmd_done := buf_state_en & !master_valid slvbuf_wr_en := buf_state_en - master_ready := (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q) & (buf_nxtstate === stream_rd) ////////////TBD//////// + val master_ready = (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q) & (buf_nxtstate === stream_rd) ////////////TBD//////// buf_wr_en := master_ready bypass_en := master_ready & master_valid buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0)) @@ -248,9 +263,9 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config } is(stream_rd) { - master_ready := (ahb_hready_q & !ahb_hresp_q) & !(master_valid & master_opc(2, 1) === "b01".U) + val master_ready = (ahb_hready_q & !ahb_hresp_q) & !(master_valid & master_opc(2, 1) === "b01".U) buf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // update the fifo if we are streaming the read commands - buf_nxtstate := Mux(ahb_hresp_q.asBool(), stream_err_rd, Mux(buf_wr_en.asBool(), stream_rd, data_rd)) // assuming that the master accpets the slave response right away. + val buf_nxtstate = Mux(ahb_hresp_q.asBool(), stream_err_rd, Mux(buf_wr_en.asBool(), stream_rd, data_rd)) // assuming that the master accpets the slave response right away. buf_state_en := (ahb_hready_q | ahb_hresp_q) buf_data_wr_en := buf_state_en slvbuf_error_in := ahb_hresp_q @@ -294,7 +309,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config is(data_wr) { buf_state_en := (cmd_doneQ & ahb_hready_q) | ahb_hresp_q - master_ready := ((cmd_doneQ & ahb_hready_q) | ahb_hresp_q) & !ahb_hresp_q & slave_ready //////////TBD///////// // Ready to accept new command if current command done and no error + val master_ready = ((cmd_doneQ & ahb_hready_q) | ahb_hresp_q) & !ahb_hresp_q & slave_ready //////////TBD///////// // Ready to accept new command if current command done and no error buf_nxtstate := Mux((ahb_hresp_q | !slave_ready).asBool(), done, Mux((master_valid & master_ready).asBool(), Mux((master_opc(2, 1) === "b01".U), cmd_wr, cmd_rd), idle)) slvbuf_error_in := ahb_hresp_q slvbuf_error_en := buf_state_en @@ -346,6 +361,16 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config slave_tag := slvbuf_tag(TAG - 1, 0) last_addr_en := (io.ahb_htrans(1, 0) =/= "b0".U) & io.ahb_hready & io.ahb_hwrite + // Write buffer + wrbuf_en := io.axi_awvalid & io.axi_awready & master_ready + wrbuf_data_en := io.axi_wvalid & io.axi_wready & master_ready + wrbuf_cmd_sent := master_valid & master_ready & (master_opc(2, 1) === "b01".U) + wrbuf_rst := wrbuf_cmd_sent & !wrbuf_en + + io.axi_awready := !(wrbuf_vld & !wrbuf_cmd_sent) & master_ready + io.axi_wready := !(wrbuf_data_vld & !wrbuf_cmd_sent) & master_ready + io.axi_arready := !(wrbuf_vld & wrbuf_data_vld) & master_ready + io.axi_rlast := true.B //rvdffsc wrbuf_vld := withClock(bus_clk) {RegNext(Mux(wrbuf_en.asBool(),1.U,wrbuf_vld) & !wrbuf_rst, 0.U)} diff --git a/target/scala-2.12/classes/lib/AXImain$.class b/target/scala-2.12/classes/lib/AXImain$.class index 70a88c06..d90994ae 100644 Binary files a/target/scala-2.12/classes/lib/AXImain$.class and b/target/scala-2.12/classes/lib/AXImain$.class differ diff --git a/target/scala-2.12/classes/lib/AXImain$delayedInit$body.class b/target/scala-2.12/classes/lib/AXImain$delayedInit$body.class index 6d36c39e..cd63c081 100644 Binary files a/target/scala-2.12/classes/lib/AXImain$delayedInit$body.class and b/target/scala-2.12/classes/lib/AXImain$delayedInit$body.class differ diff --git a/target/scala-2.12/classes/lib/axi4_to_ahb.class b/target/scala-2.12/classes/lib/axi4_to_ahb.class index fc101b35..da9bd322 100644 Binary files a/target/scala-2.12/classes/lib/axi4_to_ahb.class and b/target/scala-2.12/classes/lib/axi4_to_ahb.class differ