IMC DONE
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el2_ifu_mem_ctl.fir
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el2_ifu_mem_ctl.fir
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el2_ifu_mem_ctl.v
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el2_ifu_mem_ctl.v
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@ -659,7 +659,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
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val iccm_dma_rdata_temp = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(iccm_dma_rdata_in, 0.U)} else 0.U
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val iccm_dma_rdata_temp = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(iccm_dma_rdata_in, 0.U)} else 0.U
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io.iccm_dma_rdata := iccm_dma_rdata_temp
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io.iccm_dma_rdata := iccm_dma_rdata_temp
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val iccm_ecc_corr_index_ff = WireInit(UInt((ICCM_BITS-2).W), 0.U)
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val iccm_ecc_corr_index_ff = WireInit(UInt((ICCM_BITS-2).W), 0.U)
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io.iccm_rw_addr := Mux(ifc_dma_access_q_ok & io.dma_iccm_req & !iccm_correct_ecc, io.dma_mem_addr,
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io.iccm_rw_addr := Mux(ifc_dma_access_q_ok & io.dma_iccm_req & !iccm_correct_ecc, io.dma_mem_addr(ICCM_BITS-1,1),
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Mux(!(ifc_dma_access_q_ok & io.dma_iccm_req) & iccm_correct_ecc, Cat(iccm_ecc_corr_index_ff, 0.U), io.ifc_fetch_addr_bf(ICCM_BITS-2,0)))
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Mux(!(ifc_dma_access_q_ok & io.dma_iccm_req) & iccm_correct_ecc, Cat(iccm_ecc_corr_index_ff, 0.U), io.ifc_fetch_addr_bf(ICCM_BITS-2,0)))
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val ic_fetch_val_int_f = Cat(0.U(2.W), io.ic_fetch_val_f)
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val ic_fetch_val_int_f = Cat(0.U(2.W), io.ic_fetch_val_f)
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val ic_fetch_val_shift_right = ic_fetch_val_int_f << ifu_fetch_addr_int_f(0)
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val ic_fetch_val_shift_right = ic_fetch_val_int_f << ifu_fetch_addr_int_f(0)
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