IMC DONE

2020-10-29 15:02:33 +05:00 · 2020-10-29 15:02:33 +05:00 · eb0a5636fc
parent 88e8921788
commit eb0a5636fc
4 changed files with 12625 additions and 12625 deletions
--- a/el2_ifu_mem_ctl.fir
+++ b/el2_ifu_mem_ctl.fir
--- a/el2_ifu_mem_ctl.v
+++ b/el2_ifu_mem_ctl.v
--- a/src/main/scala/ifu/el2_ifu_mem_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_mem_ctl.scala
@ -659,7 +659,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
  val iccm_dma_rdata_temp = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(iccm_dma_rdata_in, 0.U)} else 0.U
  io.iccm_dma_rdata := iccm_dma_rdata_temp
  val iccm_ecc_corr_index_ff = WireInit(UInt((ICCM_BITS-2).W), 0.U)
-  io.iccm_rw_addr := Mux(ifc_dma_access_q_ok & io.dma_iccm_req  & !iccm_correct_ecc, io.dma_mem_addr,
+  io.iccm_rw_addr := Mux(ifc_dma_access_q_ok & io.dma_iccm_req  & !iccm_correct_ecc, io.dma_mem_addr(ICCM_BITS-1,1),
    Mux(!(ifc_dma_access_q_ok & io.dma_iccm_req) & iccm_correct_ecc, Cat(iccm_ecc_corr_index_ff, 0.U), io.ifc_fetch_addr_bf(ICCM_BITS-2,0)))
  val ic_fetch_val_int_f = Cat(0.U(2.W), io.ic_fetch_val_f)
  val ic_fetch_val_shift_right = ic_fetch_val_int_f << ifu_fetch_addr_int_f(0)
--- a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class
+++ b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class