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Regression so far

This commit is contained in:
waleed-lm 2020-12-16 13:02:50 +05:00
parent 02ed0fdee3
commit ebafe1e2b0
1 changed files with 2 additions and 1 deletions
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3
src/main/scala/include/bundle.scala
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@ -34,6 +34,7 @@ class tlu_dma extends Bundle{
class dec_bp extends Bundle{ class dec_bp extends Bundle{
val dec_tlu_br0_r_pkt = Flipped(Valid(new br_tlu_pkt_t)) val dec_tlu_br0_r_pkt = Flipped(Valid(new br_tlu_pkt_t))
// val dec_tlu_flush_lower_wb = Input(Bool())
val dec_tlu_flush_leak_one_wb = Input(Bool()) val dec_tlu_flush_leak_one_wb = Input(Bool())
val dec_tlu_bpred_disable = Input(Bool()) val dec_tlu_bpred_disable = Input(Bool())
} }
@ -339,7 +340,7 @@ class tlu_exu extends Bundle with lib{
val exu_i0_br_hist_r =Output(UInt(2.W)) // to DEC I0 branch history val exu_i0_br_hist_r =Output(UInt(2.W)) // to DEC I0 branch history
val exu_i0_br_error_r =Output(UInt(1.W)) // to DEC I0 branch error val exu_i0_br_error_r =Output(UInt(1.W)) // to DEC I0 branch error
val exu_i0_br_start_error_r =Output(UInt(1.W)) // to DEC I0 branch start error val exu_i0_br_start_error_r =Output(UInt(1.W)) // to DEC I0 branch start error
// val exu_i0_br_index_r =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // to DEC I0 branch index val exu_i0_br_index_r =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // to DEC I0 branch index
val exu_i0_br_valid_r =Output(UInt(1.W)) // to DEC I0 branch valid val exu_i0_br_valid_r =Output(UInt(1.W)) // to DEC I0 branch valid
val exu_i0_br_mp_r =Output(UInt(1.W)) // to DEC I0 branch mispredict val exu_i0_br_mp_r =Output(UInt(1.W)) // to DEC I0 branch mispredict
val exu_i0_br_middle_r =Output(UInt(1.W)) // to DEC I0 branch middle val exu_i0_br_middle_r =Output(UInt(1.W)) // to DEC I0 branch middle