From edb9e98a90dd0d98fd2b21daec9ea10d6cc8bf1b Mon Sep 17 00:00:00 2001 From: Laraib Khan <73219142+laraibkhan-lm@users.noreply.github.com> Date: Fri, 9 Apr 2021 09:40:20 +0500 Subject: [PATCH] Update quasar_wrapper.scala --- design/src/main/scala/quasar_wrapper.scala | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/design/src/main/scala/quasar_wrapper.scala b/design/src/main/scala/quasar_wrapper.scala index e8ddb172..5f28b837 100644 --- a/design/src/main/scala/quasar_wrapper.scala +++ b/design/src/main/scala/quasar_wrapper.scala @@ -64,7 +64,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset { val scan_mode = Input(Bool()) }) - // val core_rst_l = core.io.core_rst_l + val mem = Module(new quasar.mem()) val dmi_wrapper = Module(new dmi_wrapper()) val core = Module(new quasar()) @@ -81,7 +81,6 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset { core.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr core.io.dmi_reg_en := dmi_wrapper.io.reg_en core.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en - // core.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset io.jtag_tdo := dmi_wrapper.io.tdo // Memory signals @@ -171,4 +170,4 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset { } object QUASAR_Wrp extends App { println((new chisel3.stage.ChiselStage).emitVerilog(new quasar_wrapper())) -} \ No newline at end of file +}