From ef2f0bbbb2486a5969add5297c073820799fcc53 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Fri, 22 Jan 2021 14:59:02 +0500 Subject: [PATCH] vwayhit corrected --- ifu_bp_ctl.anno.json | 111 +- ifu_bp_ctl.fir | 3351 ++++++++--------- ifu_bp_ctl.v | 1425 +++---- src/main/scala/ifu/ifu_bp_ctl.scala | 119 +- src/main/scala/lib/param.scala | 1 - .../classes/ifu/bp$delayedInit$body.class | Bin 701 -> 0 bytes .../classes/ifu/{bp$.class => bp_MAIN$.class} | Bin 3836 -> 3861 bytes .../ifu/bp_MAIN$delayedInit$body.class | Bin 0 -> 731 bytes .../classes/ifu/{bp.class => bp_MAIN.class} | Bin 749 -> 775 bytes .../scala-2.12/classes/ifu/ifu_bp_ctl.class | Bin 215967 -> 197917 bytes 10 files changed, 2286 insertions(+), 2721 deletions(-) delete mode 100644 target/scala-2.12/classes/ifu/bp$delayedInit$body.class rename target/scala-2.12/classes/ifu/{bp$.class => bp_MAIN$.class} (63%) create mode 100644 target/scala-2.12/classes/ifu/bp_MAIN$delayedInit$body.class rename target/scala-2.12/classes/ifu/{bp.class => bp_MAIN.class} (50%) diff --git a/ifu_bp_ctl.anno.json b/ifu_bp_ctl.anno.json index 4a7fcf2d..0abc24c8 100644 --- a/ifu_bp_ctl.anno.json +++ b/ifu_bp_ctl.anno.json @@ -1,4 +1,13 @@ [ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f", + "sources":[ + "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable", + "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f", + "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hist1_f", @@ -6,6 +15,13 @@ "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_valid_f", + "sources":[ + "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_inst_mask_f", @@ -13,13 +29,7 @@ "~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f", "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable", "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f", - "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error", - "~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r" + "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f" ] }, { @@ -29,6 +39,13 @@ "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_poffset_f", + "sources":[ + "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_btb_target_f", @@ -36,56 +53,7 @@ "~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f", "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable", "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f", - "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error", - "~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_pc4_f", - "sources":[ - "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f", - "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error", - "~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_valid_f", - "sources":[ - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable", - "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f", - "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error", - "~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_ret_f", - "sources":[ - "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f", - "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error", - "~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r" + "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f" ] }, { @@ -105,35 +73,6 @@ "~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_poffset_f", - "sources":[ - "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f", - "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error", - "~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f", - "sources":[ - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable", - "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f", - "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error", - "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error", - "~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r" - ] - }, { "class":"firrtl.EmitCircuitAnnotation", "emitter":"firrtl.VerilogEmitter" diff --git a/ifu_bp_ctl.fir b/ifu_bp_ctl.fir index 4473ab17..cd8f864b 100644 --- a/ifu_bp_ctl.fir +++ b/ifu_bp_ctl.fir @@ -1680,32 +1680,32 @@ circuit ifu_bp_ctl : rets_out[5] <= UInt<1>("h00") @[ifu_bp_ctl.scala 371:12] rets_out[6] <= UInt<1>("h00") @[ifu_bp_ctl.scala 371:12] rets_out[7] <= UInt<1>("h00") @[ifu_bp_ctl.scala 371:12] - node _T_433 = eq(btb_rd_call_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 373:55] - node _T_434 = and(btb_rd_ret_f, _T_433) @[ifu_bp_ctl.scala 373:53] - node _T_435 = bits(rets_out[0], 0, 0) @[ifu_bp_ctl.scala 373:83] - node _T_436 = and(_T_434, _T_435) @[ifu_bp_ctl.scala 373:70] - node _T_437 = and(_T_436, io.ifu_bp_hit_taken_f) @[ifu_bp_ctl.scala 373:87] + node _T_433 = eq(btb_rd_call_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 375:56] + node _T_434 = and(btb_rd_ret_f, _T_433) @[ifu_bp_ctl.scala 375:54] + node _T_435 = bits(rets_out[0], 0, 0) @[ifu_bp_ctl.scala 375:84] + node _T_436 = and(_T_434, _T_435) @[ifu_bp_ctl.scala 375:71] + node _T_437 = and(_T_436, io.ifu_bp_hit_taken_f) @[ifu_bp_ctl.scala 375:88] node _T_438 = bits(_T_437, 0, 0) @[Bitwise.scala 72:15] node _T_439 = mux(_T_438, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] - node _T_440 = bits(rets_out[0], 31, 1) @[ifu_bp_ctl.scala 373:126] - node _T_441 = and(_T_439, _T_440) @[ifu_bp_ctl.scala 373:113] - node _T_442 = eq(btb_rd_ret_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 374:15] - node _T_443 = eq(btb_rd_call_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 374:31] - node _T_444 = and(_T_442, _T_443) @[ifu_bp_ctl.scala 374:29] - node _T_445 = bits(rets_out[0], 0, 0) @[ifu_bp_ctl.scala 374:59] - node _T_446 = and(_T_444, _T_445) @[ifu_bp_ctl.scala 374:46] - node _T_447 = and(_T_446, io.ifu_bp_hit_taken_f) @[ifu_bp_ctl.scala 374:63] + node _T_440 = bits(rets_out[0], 31, 1) @[ifu_bp_ctl.scala 375:127] + node _T_441 = and(_T_439, _T_440) @[ifu_bp_ctl.scala 375:114] + node _T_442 = eq(btb_rd_ret_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 376:15] + node _T_443 = eq(btb_rd_call_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 376:31] + node _T_444 = and(_T_442, _T_443) @[ifu_bp_ctl.scala 376:29] + node _T_445 = bits(rets_out[0], 0, 0) @[ifu_bp_ctl.scala 376:59] + node _T_446 = and(_T_444, _T_445) @[ifu_bp_ctl.scala 376:46] + node _T_447 = and(_T_446, io.ifu_bp_hit_taken_f) @[ifu_bp_ctl.scala 376:63] node _T_448 = bits(_T_447, 0, 0) @[Bitwise.scala 72:15] node _T_449 = mux(_T_448, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] - node _T_450 = bits(bp_btb_target_adder_f, 31, 1) @[ifu_bp_ctl.scala 374:112] - node _T_451 = and(_T_449, _T_450) @[ifu_bp_ctl.scala 374:89] - node _T_452 = or(_T_441, _T_451) @[ifu_bp_ctl.scala 373:134] - io.ifu_bp_btb_target_f <= _T_452 @[ifu_bp_ctl.scala 373:26] - node _T_453 = bits(adder_pc_in_f, 29, 0) @[ifu_bp_ctl.scala 377:56] + node _T_450 = bits(bp_btb_target_adder_f, 31, 1) @[ifu_bp_ctl.scala 376:112] + node _T_451 = and(_T_449, _T_450) @[ifu_bp_ctl.scala 376:89] + node _T_452 = or(_T_441, _T_451) @[ifu_bp_ctl.scala 375:135] + io.ifu_bp_btb_target_f <= _T_452 @[ifu_bp_ctl.scala 375:27] + node _T_453 = bits(adder_pc_in_f, 29, 0) @[ifu_bp_ctl.scala 379:56] node _T_454 = cat(_T_453, bp_total_branch_offset_f) @[Cat.scala 29:58] node _T_455 = cat(_T_454, UInt<1>("h00")) @[Cat.scala 29:58] node _T_456 = mux(UInt<1>("h00"), UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 72:12] - node _T_457 = not(btb_rd_pc4_f) @[ifu_bp_ctl.scala 377:113] + node _T_457 = not(btb_rd_pc4_f) @[ifu_bp_ctl.scala 379:113] node _T_458 = cat(_T_456, _T_457) @[Cat.scala 29:58] node _T_459 = cat(_T_458, UInt<1>("h00")) @[Cat.scala 29:58] node _T_460 = bits(_T_455, 12, 1) @[lib.scala 68:24] @@ -1741,74 +1741,74 @@ circuit ifu_bp_ctl : node _T_489 = bits(_T_462, 11, 0) @[lib.scala 74:94] node _T_490 = cat(_T_488, _T_489) @[Cat.scala 29:58] node bp_rs_call_target_f = cat(_T_490, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_491 = eq(btb_rd_ret_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 379:33] - node _T_492 = and(btb_rd_call_f, _T_491) @[ifu_bp_ctl.scala 379:31] - node rs_push = and(_T_492, io.ifu_bp_hit_taken_f) @[ifu_bp_ctl.scala 379:47] - node _T_493 = eq(btb_rd_call_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 380:31] - node _T_494 = and(btb_rd_ret_f, _T_493) @[ifu_bp_ctl.scala 380:29] - node rs_pop = and(_T_494, io.ifu_bp_hit_taken_f) @[ifu_bp_ctl.scala 380:46] - node _T_495 = eq(rs_push, UInt<1>("h00")) @[ifu_bp_ctl.scala 381:17] - node _T_496 = eq(rs_pop, UInt<1>("h00")) @[ifu_bp_ctl.scala 381:28] - node rs_hold = and(_T_495, _T_496) @[ifu_bp_ctl.scala 381:26] - node rsenable_0 = eq(rs_hold, UInt<1>("h00")) @[ifu_bp_ctl.scala 383:60] - node rsenable_1 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 383:119] - node rsenable_2 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 383:119] - node rsenable_3 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 383:119] - node rsenable_4 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 383:119] - node rsenable_5 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 383:119] - node rsenable_6 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 383:119] - node _T_497 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 386:23] - node _T_498 = bits(bp_rs_call_target_f, 31, 1) @[ifu_bp_ctl.scala 386:56] + node _T_491 = eq(btb_rd_ret_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 381:33] + node _T_492 = and(btb_rd_call_f, _T_491) @[ifu_bp_ctl.scala 381:31] + node rs_push = and(_T_492, io.ifu_bp_hit_taken_f) @[ifu_bp_ctl.scala 381:47] + node _T_493 = eq(btb_rd_call_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 382:31] + node _T_494 = and(btb_rd_ret_f, _T_493) @[ifu_bp_ctl.scala 382:29] + node rs_pop = and(_T_494, io.ifu_bp_hit_taken_f) @[ifu_bp_ctl.scala 382:46] + node _T_495 = eq(rs_push, UInt<1>("h00")) @[ifu_bp_ctl.scala 383:17] + node _T_496 = eq(rs_pop, UInt<1>("h00")) @[ifu_bp_ctl.scala 383:28] + node rs_hold = and(_T_495, _T_496) @[ifu_bp_ctl.scala 383:26] + node rsenable_0 = eq(rs_hold, UInt<1>("h00")) @[ifu_bp_ctl.scala 385:60] + node rsenable_1 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 385:119] + node rsenable_2 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 385:119] + node rsenable_3 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 385:119] + node rsenable_4 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 385:119] + node rsenable_5 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 385:119] + node rsenable_6 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 385:119] + node _T_497 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 388:23] + node _T_498 = bits(bp_rs_call_target_f, 31, 1) @[ifu_bp_ctl.scala 388:56] node _T_499 = cat(_T_498, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_500 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 387:22] + node _T_500 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 389:22] node _T_501 = mux(_T_497, _T_499, UInt<1>("h00")) @[Mux.scala 27:72] node _T_502 = mux(_T_500, rets_out[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_503 = or(_T_501, _T_502) @[Mux.scala 27:72] wire rets_in_0 : UInt<32> @[Mux.scala 27:72] rets_in_0 <= _T_503 @[Mux.scala 27:72] - node _T_504 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 389:28] - node _T_505 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 390:27] + node _T_504 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 391:28] + node _T_505 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 392:27] node _T_506 = mux(_T_504, rets_out[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_507 = mux(_T_505, rets_out[2], UInt<1>("h00")) @[Mux.scala 27:72] node _T_508 = or(_T_506, _T_507) @[Mux.scala 27:72] wire rets_in_1 : UInt<32> @[Mux.scala 27:72] rets_in_1 <= _T_508 @[Mux.scala 27:72] - node _T_509 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 389:28] - node _T_510 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 390:27] + node _T_509 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 391:28] + node _T_510 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 392:27] node _T_511 = mux(_T_509, rets_out[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_512 = mux(_T_510, rets_out[3], UInt<1>("h00")) @[Mux.scala 27:72] node _T_513 = or(_T_511, _T_512) @[Mux.scala 27:72] wire rets_in_2 : UInt<32> @[Mux.scala 27:72] rets_in_2 <= _T_513 @[Mux.scala 27:72] - node _T_514 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 389:28] - node _T_515 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 390:27] + node _T_514 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 391:28] + node _T_515 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 392:27] node _T_516 = mux(_T_514, rets_out[2], UInt<1>("h00")) @[Mux.scala 27:72] node _T_517 = mux(_T_515, rets_out[4], UInt<1>("h00")) @[Mux.scala 27:72] node _T_518 = or(_T_516, _T_517) @[Mux.scala 27:72] wire rets_in_3 : UInt<32> @[Mux.scala 27:72] rets_in_3 <= _T_518 @[Mux.scala 27:72] - node _T_519 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 389:28] - node _T_520 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 390:27] + node _T_519 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 391:28] + node _T_520 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 392:27] node _T_521 = mux(_T_519, rets_out[3], UInt<1>("h00")) @[Mux.scala 27:72] node _T_522 = mux(_T_520, rets_out[5], UInt<1>("h00")) @[Mux.scala 27:72] node _T_523 = or(_T_521, _T_522) @[Mux.scala 27:72] wire rets_in_4 : UInt<32> @[Mux.scala 27:72] rets_in_4 <= _T_523 @[Mux.scala 27:72] - node _T_524 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 389:28] - node _T_525 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 390:27] + node _T_524 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 391:28] + node _T_525 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 392:27] node _T_526 = mux(_T_524, rets_out[4], UInt<1>("h00")) @[Mux.scala 27:72] node _T_527 = mux(_T_525, rets_out[6], UInt<1>("h00")) @[Mux.scala 27:72] node _T_528 = or(_T_526, _T_527) @[Mux.scala 27:72] wire rets_in_5 : UInt<32> @[Mux.scala 27:72] rets_in_5 <= _T_528 @[Mux.scala 27:72] - node _T_529 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 389:28] - node _T_530 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 390:27] + node _T_529 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 391:28] + node _T_530 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 392:27] node _T_531 = mux(_T_529, rets_out[5], UInt<1>("h00")) @[Mux.scala 27:72] node _T_532 = mux(_T_530, rets_out[7], UInt<1>("h00")) @[Mux.scala 27:72] node _T_533 = or(_T_531, _T_532) @[Mux.scala 27:72] wire rets_in_6 : UInt<32> @[Mux.scala 27:72] rets_in_6 <= _T_533 @[Mux.scala 27:72] - node _T_534 = bits(rsenable_0, 0, 0) @[ifu_bp_ctl.scala 393:78] + node _T_534 = bits(rsenable_0, 0, 0) @[ifu_bp_ctl.scala 395:78] inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 399:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -1819,7 +1819,7 @@ circuit ifu_bp_ctl : when _T_534 : @[Reg.scala 28:19] _T_535 <= rets_in_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_536 = bits(rsenable_1, 0, 0) @[ifu_bp_ctl.scala 393:78] + node _T_536 = bits(rsenable_1, 0, 0) @[ifu_bp_ctl.scala 395:78] inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 399:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -1830,7 +1830,7 @@ circuit ifu_bp_ctl : when _T_536 : @[Reg.scala 28:19] _T_537 <= rets_in_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_538 = bits(rsenable_2, 0, 0) @[ifu_bp_ctl.scala 393:78] + node _T_538 = bits(rsenable_2, 0, 0) @[ifu_bp_ctl.scala 395:78] inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 399:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -1841,7 +1841,7 @@ circuit ifu_bp_ctl : when _T_538 : @[Reg.scala 28:19] _T_539 <= rets_in_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_540 = bits(rsenable_3, 0, 0) @[ifu_bp_ctl.scala 393:78] + node _T_540 = bits(rsenable_3, 0, 0) @[ifu_bp_ctl.scala 395:78] inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 399:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -1852,7 +1852,7 @@ circuit ifu_bp_ctl : when _T_540 : @[Reg.scala 28:19] _T_541 <= rets_in_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_542 = bits(rsenable_4, 0, 0) @[ifu_bp_ctl.scala 393:78] + node _T_542 = bits(rsenable_4, 0, 0) @[ifu_bp_ctl.scala 395:78] inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 399:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -1863,7 +1863,7 @@ circuit ifu_bp_ctl : when _T_542 : @[Reg.scala 28:19] _T_543 <= rets_in_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_544 = bits(rsenable_5, 0, 0) @[ifu_bp_ctl.scala 393:78] + node _T_544 = bits(rsenable_5, 0, 0) @[ifu_bp_ctl.scala 395:78] inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 399:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -1874,7 +1874,7 @@ circuit ifu_bp_ctl : when _T_544 : @[Reg.scala 28:19] _T_545 <= rets_in_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_546 = bits(rsenable_6, 0, 0) @[ifu_bp_ctl.scala 393:78] + node _T_546 = bits(rsenable_6, 0, 0) @[ifu_bp_ctl.scala 395:78] inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 399:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset @@ -1885,7 +1885,7 @@ circuit ifu_bp_ctl : when _T_546 : @[Reg.scala 28:19] _T_547 <= rets_in_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_548 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 393:78] + node _T_548 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 395:78] inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 399:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset @@ -1896,44 +1896,44 @@ circuit ifu_bp_ctl : when _T_548 : @[Reg.scala 28:19] _T_549 <= rets_out[6] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - rets_out[0] <= _T_535 @[ifu_bp_ctl.scala 393:12] - rets_out[1] <= _T_537 @[ifu_bp_ctl.scala 393:12] - rets_out[2] <= _T_539 @[ifu_bp_ctl.scala 393:12] - rets_out[3] <= _T_541 @[ifu_bp_ctl.scala 393:12] - rets_out[4] <= _T_543 @[ifu_bp_ctl.scala 393:12] - rets_out[5] <= _T_545 @[ifu_bp_ctl.scala 393:12] - rets_out[6] <= _T_547 @[ifu_bp_ctl.scala 393:12] - rets_out[7] <= _T_549 @[ifu_bp_ctl.scala 393:12] - node _T_550 = eq(dec_tlu_error_wb, UInt<1>("h00")) @[ifu_bp_ctl.scala 395:35] - node btb_valid = and(exu_mp_valid, _T_550) @[ifu_bp_ctl.scala 395:32] - node _T_551 = or(io.exu_bp.exu_mp_pkt.bits.pcall, io.exu_bp.exu_mp_pkt.bits.pja) @[ifu_bp_ctl.scala 409:89] - node _T_552 = or(io.exu_bp.exu_mp_pkt.bits.pret, io.exu_bp.exu_mp_pkt.bits.pja) @[ifu_bp_ctl.scala 409:113] + rets_out[0] <= _T_535 @[ifu_bp_ctl.scala 395:12] + rets_out[1] <= _T_537 @[ifu_bp_ctl.scala 395:12] + rets_out[2] <= _T_539 @[ifu_bp_ctl.scala 395:12] + rets_out[3] <= _T_541 @[ifu_bp_ctl.scala 395:12] + rets_out[4] <= _T_543 @[ifu_bp_ctl.scala 395:12] + rets_out[5] <= _T_545 @[ifu_bp_ctl.scala 395:12] + rets_out[6] <= _T_547 @[ifu_bp_ctl.scala 395:12] + rets_out[7] <= _T_549 @[ifu_bp_ctl.scala 395:12] + node _T_550 = eq(dec_tlu_error_wb, UInt<1>("h00")) @[ifu_bp_ctl.scala 397:35] + node btb_valid = and(exu_mp_valid, _T_550) @[ifu_bp_ctl.scala 397:32] + node _T_551 = or(io.exu_bp.exu_mp_pkt.bits.pcall, io.exu_bp.exu_mp_pkt.bits.pja) @[ifu_bp_ctl.scala 411:89] + node _T_552 = or(io.exu_bp.exu_mp_pkt.bits.pret, io.exu_bp.exu_mp_pkt.bits.pja) @[ifu_bp_ctl.scala 411:113] node _T_553 = cat(_T_551, _T_552) @[Cat.scala 29:58] node _T_554 = cat(_T_553, btb_valid) @[Cat.scala 29:58] node _T_555 = cat(io.exu_bp.exu_mp_pkt.bits.pc4, io.exu_bp.exu_mp_pkt.bits.boffset) @[Cat.scala 29:58] node _T_556 = cat(io.exu_bp.exu_mp_btag, io.exu_bp.exu_mp_pkt.bits.toffset) @[Cat.scala 29:58] node _T_557 = cat(_T_556, _T_555) @[Cat.scala 29:58] node btb_wr_data = cat(_T_557, _T_554) @[Cat.scala 29:58] - node _T_558 = and(exu_mp_valid, io.exu_bp.exu_mp_pkt.bits.ataken) @[ifu_bp_ctl.scala 410:41] - node _T_559 = eq(io.exu_bp.exu_mp_pkt.valid, UInt<1>("h00")) @[ifu_bp_ctl.scala 410:59] - node exu_mp_valid_write = and(_T_558, _T_559) @[ifu_bp_ctl.scala 410:57] - node middle_of_bank = xor(io.exu_bp.exu_mp_pkt.bits.pc4, io.exu_bp.exu_mp_pkt.bits.boffset) @[ifu_bp_ctl.scala 411:35] - node _T_560 = eq(io.exu_bp.exu_mp_pkt.bits.pcall, UInt<1>("h00")) @[ifu_bp_ctl.scala 414:43] - node _T_561 = and(exu_mp_valid, _T_560) @[ifu_bp_ctl.scala 414:41] - node _T_562 = eq(io.exu_bp.exu_mp_pkt.bits.pret, UInt<1>("h00")) @[ifu_bp_ctl.scala 414:58] - node _T_563 = and(_T_561, _T_562) @[ifu_bp_ctl.scala 414:56] - node _T_564 = eq(io.exu_bp.exu_mp_pkt.bits.pja, UInt<1>("h00")) @[ifu_bp_ctl.scala 414:72] - node _T_565 = and(_T_563, _T_564) @[ifu_bp_ctl.scala 414:70] + node _T_558 = and(exu_mp_valid, io.exu_bp.exu_mp_pkt.bits.ataken) @[ifu_bp_ctl.scala 412:41] + node _T_559 = eq(io.exu_bp.exu_mp_pkt.valid, UInt<1>("h00")) @[ifu_bp_ctl.scala 412:59] + node exu_mp_valid_write = and(_T_558, _T_559) @[ifu_bp_ctl.scala 412:57] + node middle_of_bank = xor(io.exu_bp.exu_mp_pkt.bits.pc4, io.exu_bp.exu_mp_pkt.bits.boffset) @[ifu_bp_ctl.scala 413:35] + node _T_560 = eq(io.exu_bp.exu_mp_pkt.bits.pcall, UInt<1>("h00")) @[ifu_bp_ctl.scala 416:43] + node _T_561 = and(exu_mp_valid, _T_560) @[ifu_bp_ctl.scala 416:41] + node _T_562 = eq(io.exu_bp.exu_mp_pkt.bits.pret, UInt<1>("h00")) @[ifu_bp_ctl.scala 416:58] + node _T_563 = and(_T_561, _T_562) @[ifu_bp_ctl.scala 416:56] + node _T_564 = eq(io.exu_bp.exu_mp_pkt.bits.pja, UInt<1>("h00")) @[ifu_bp_ctl.scala 416:72] + node _T_565 = and(_T_563, _T_564) @[ifu_bp_ctl.scala 416:70] node _T_566 = bits(_T_565, 0, 0) @[Bitwise.scala 72:15] node _T_567 = mux(_T_566, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_568 = not(middle_of_bank) @[ifu_bp_ctl.scala 414:106] + node _T_568 = not(middle_of_bank) @[ifu_bp_ctl.scala 416:106] node _T_569 = cat(middle_of_bank, _T_568) @[Cat.scala 29:58] - node bht_wr_en0 = and(_T_567, _T_569) @[ifu_bp_ctl.scala 414:84] + node bht_wr_en0 = and(_T_567, _T_569) @[ifu_bp_ctl.scala 416:84] node _T_570 = bits(io.dec_bp.dec_tlu_br0_r_pkt.valid, 0, 0) @[Bitwise.scala 72:15] node _T_571 = mux(_T_570, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_572 = not(io.dec_bp.dec_tlu_br0_r_pkt.bits.middle) @[ifu_bp_ctl.scala 415:75] + node _T_572 = not(io.dec_bp.dec_tlu_br0_r_pkt.bits.middle) @[ifu_bp_ctl.scala 417:75] node _T_573 = cat(io.dec_bp.dec_tlu_br0_r_pkt.bits.middle, _T_572) @[Cat.scala 29:58] - node bht_wr_en2 = and(_T_571, _T_573) @[ifu_bp_ctl.scala 415:46] + node bht_wr_en2 = and(_T_571, _T_573) @[ifu_bp_ctl.scala 417:46] node _T_574 = cat(io.exu_bp.exu_mp_index, UInt<2>("h00")) @[Cat.scala 29:58] node _T_575 = bits(_T_574, 9, 2) @[lib.scala 56:16] node _T_576 = bits(io.exu_bp.exu_mp_eghr, 7, 0) @[lib.scala 56:40] @@ -1950,501 +1950,502 @@ circuit ifu_bp_ctl : node _T_584 = bits(_T_583, 9, 2) @[lib.scala 56:16] node _T_585 = bits(fghr, 7, 0) @[lib.scala 56:40] node bht_rd_addr_hashed_p1_f = xor(_T_584, _T_585) @[lib.scala 56:35] - node _T_586 = eq(io.exu_bp.exu_mp_pkt.bits.way, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:26] - node _T_587 = and(_T_586, exu_mp_valid_write) @[ifu_bp_ctl.scala 434:39] - node _T_588 = eq(dec_tlu_error_wb, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:63] - node _T_589 = and(_T_587, _T_588) @[ifu_bp_ctl.scala 434:60] - node _T_590 = eq(dec_tlu_way_wb, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:87] - node _T_591 = and(_T_590, dec_tlu_error_wb) @[ifu_bp_ctl.scala 434:104] - node btb_wr_en_way0 = or(_T_589, _T_591) @[ifu_bp_ctl.scala 434:83] - node _T_592 = and(io.exu_bp.exu_mp_pkt.bits.way, exu_mp_valid_write) @[ifu_bp_ctl.scala 435:36] - node _T_593 = eq(dec_tlu_error_wb, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:60] - node _T_594 = and(_T_592, _T_593) @[ifu_bp_ctl.scala 435:57] - node _T_595 = and(dec_tlu_way_wb, dec_tlu_error_wb) @[ifu_bp_ctl.scala 435:98] - node btb_wr_en_way1 = or(_T_594, _T_595) @[ifu_bp_ctl.scala 435:80] - node _T_596 = bits(dec_tlu_error_wb, 0, 0) @[ifu_bp_ctl.scala 438:42] - node btb_wr_addr = mux(_T_596, btb_error_addr_wb, io.exu_bp.exu_mp_index) @[ifu_bp_ctl.scala 438:24] - node _T_597 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 440:43] - node _T_598 = bits(_T_597, 0, 0) @[Bitwise.scala 72:15] - node _T_599 = mux(_T_598, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_600 = bits(wayhit_f, 1, 0) @[ifu_bp_ctl.scala 440:58] - node _T_601 = and(_T_599, _T_600) @[ifu_bp_ctl.scala 440:48] - node _T_602 = bits(io.ifc_fetch_addr_f, 1, 1) @[ifu_bp_ctl.scala 440:95] - node _T_603 = bits(_T_602, 0, 0) @[Bitwise.scala 72:15] - node _T_604 = mux(_T_603, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_605 = bits(wayhit_p1_f, 0, 0) @[ifu_bp_ctl.scala 440:117] - node _T_606 = bits(wayhit_f, 1, 1) @[ifu_bp_ctl.scala 440:129] - node _T_607 = cat(_T_605, _T_606) @[Cat.scala 29:58] - node _T_608 = and(_T_604, _T_607) @[ifu_bp_ctl.scala 440:100] + node _T_586 = eq(io.exu_bp.exu_mp_pkt.bits.way, UInt<1>("h00")) @[ifu_bp_ctl.scala 436:26] + node _T_587 = and(_T_586, exu_mp_valid_write) @[ifu_bp_ctl.scala 436:39] + node _T_588 = eq(dec_tlu_error_wb, UInt<1>("h00")) @[ifu_bp_ctl.scala 436:63] + node _T_589 = and(_T_587, _T_588) @[ifu_bp_ctl.scala 436:60] + node _T_590 = eq(dec_tlu_way_wb, UInt<1>("h00")) @[ifu_bp_ctl.scala 436:87] + node _T_591 = and(_T_590, dec_tlu_error_wb) @[ifu_bp_ctl.scala 436:104] + node btb_wr_en_way0 = or(_T_589, _T_591) @[ifu_bp_ctl.scala 436:83] + node _T_592 = and(io.exu_bp.exu_mp_pkt.bits.way, exu_mp_valid_write) @[ifu_bp_ctl.scala 437:36] + node _T_593 = eq(dec_tlu_error_wb, UInt<1>("h00")) @[ifu_bp_ctl.scala 437:60] + node _T_594 = and(_T_592, _T_593) @[ifu_bp_ctl.scala 437:57] + node _T_595 = and(dec_tlu_way_wb, dec_tlu_error_wb) @[ifu_bp_ctl.scala 437:98] + node btb_wr_en_way1 = or(_T_594, _T_595) @[ifu_bp_ctl.scala 437:80] + node _T_596 = bits(dec_tlu_error_wb, 0, 0) @[ifu_bp_ctl.scala 440:42] + node btb_wr_addr = mux(_T_596, btb_error_addr_wb, io.exu_bp.exu_mp_index) @[ifu_bp_ctl.scala 440:24] + node _T_597 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 442:49] + node _T_598 = bits(_T_597, 0, 0) @[ifu_bp_ctl.scala 442:53] + node _T_599 = eq(_T_598, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:29] + node _T_600 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 443:24] + node _T_601 = bits(_T_600, 0, 0) @[ifu_bp_ctl.scala 443:28] + node _T_602 = bits(wayhit_p1_f, 0, 0) @[ifu_bp_ctl.scala 443:51] + node _T_603 = bits(wayhit_f, 1, 1) @[ifu_bp_ctl.scala 443:64] + node _T_604 = cat(_T_602, _T_603) @[Cat.scala 29:58] + node _T_605 = mux(_T_599, wayhit_f, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_606 = mux(_T_601, _T_604, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_607 = or(_T_605, _T_606) @[Mux.scala 27:72] + wire _T_608 : UInt<2> @[Mux.scala 27:72] + _T_608 <= _T_607 @[Mux.scala 27:72] node _T_609 = cat(eoc_mask, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_610 = and(_T_608, _T_609) @[ifu_bp_ctl.scala 440:135] - node _T_611 = or(_T_601, _T_610) @[ifu_bp_ctl.scala 440:65] - vwayhit_f <= _T_611 @[ifu_bp_ctl.scala 440:13] - node _T_612 = eq(btb_wr_addr, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:98] - node _T_613 = and(_T_612, btb_wr_en_way0) @[ifu_bp_ctl.scala 442:107] - node _T_614 = bits(_T_613, 0, 0) @[ifu_bp_ctl.scala 442:125] + node vwayhit_f_1 = and(_T_608, _T_609) @[ifu_bp_ctl.scala 443:71] + node _T_610 = eq(btb_wr_addr, UInt<1>("h00")) @[ifu_bp_ctl.scala 448:98] + node _T_611 = and(_T_610, btb_wr_en_way0) @[ifu_bp_ctl.scala 448:107] + node _T_612 = bits(_T_611, 0, 0) @[ifu_bp_ctl.scala 448:125] inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 399:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_9.io.en <= _T_614 @[lib.scala 402:17] + rvclkhdr_9.io.en <= _T_612 @[lib.scala 402:17] rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way0_out_0 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_614 : @[Reg.scala 28:19] + when _T_612 : @[Reg.scala 28:19] btb_bank0_rd_data_way0_out_0 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_615 = eq(btb_wr_addr, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:98] - node _T_616 = and(_T_615, btb_wr_en_way0) @[ifu_bp_ctl.scala 442:107] - node _T_617 = bits(_T_616, 0, 0) @[ifu_bp_ctl.scala 442:125] + node _T_613 = eq(btb_wr_addr, UInt<1>("h01")) @[ifu_bp_ctl.scala 448:98] + node _T_614 = and(_T_613, btb_wr_en_way0) @[ifu_bp_ctl.scala 448:107] + node _T_615 = bits(_T_614, 0, 0) @[ifu_bp_ctl.scala 448:125] inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 399:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset rvclkhdr_10.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_10.io.en <= _T_617 @[lib.scala 402:17] + rvclkhdr_10.io.en <= _T_615 @[lib.scala 402:17] rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way0_out_1 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_617 : @[Reg.scala 28:19] + when _T_615 : @[Reg.scala 28:19] btb_bank0_rd_data_way0_out_1 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_618 = eq(btb_wr_addr, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:98] - node _T_619 = and(_T_618, btb_wr_en_way0) @[ifu_bp_ctl.scala 442:107] - node _T_620 = bits(_T_619, 0, 0) @[ifu_bp_ctl.scala 442:125] + node _T_616 = eq(btb_wr_addr, UInt<2>("h02")) @[ifu_bp_ctl.scala 448:98] + node _T_617 = and(_T_616, btb_wr_en_way0) @[ifu_bp_ctl.scala 448:107] + node _T_618 = bits(_T_617, 0, 0) @[ifu_bp_ctl.scala 448:125] inst rvclkhdr_11 of rvclkhdr_11 @[lib.scala 399:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset rvclkhdr_11.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_11.io.en <= _T_620 @[lib.scala 402:17] + rvclkhdr_11.io.en <= _T_618 @[lib.scala 402:17] rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way0_out_2 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_620 : @[Reg.scala 28:19] + when _T_618 : @[Reg.scala 28:19] btb_bank0_rd_data_way0_out_2 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_621 = eq(btb_wr_addr, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:98] - node _T_622 = and(_T_621, btb_wr_en_way0) @[ifu_bp_ctl.scala 442:107] - node _T_623 = bits(_T_622, 0, 0) @[ifu_bp_ctl.scala 442:125] + node _T_619 = eq(btb_wr_addr, UInt<2>("h03")) @[ifu_bp_ctl.scala 448:98] + node _T_620 = and(_T_619, btb_wr_en_way0) @[ifu_bp_ctl.scala 448:107] + node _T_621 = bits(_T_620, 0, 0) @[ifu_bp_ctl.scala 448:125] inst rvclkhdr_12 of rvclkhdr_12 @[lib.scala 399:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset rvclkhdr_12.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_12.io.en <= _T_623 @[lib.scala 402:17] + rvclkhdr_12.io.en <= _T_621 @[lib.scala 402:17] rvclkhdr_12.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way0_out_3 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_623 : @[Reg.scala 28:19] + when _T_621 : @[Reg.scala 28:19] btb_bank0_rd_data_way0_out_3 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_624 = eq(btb_wr_addr, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:98] - node _T_625 = and(_T_624, btb_wr_en_way0) @[ifu_bp_ctl.scala 442:107] - node _T_626 = bits(_T_625, 0, 0) @[ifu_bp_ctl.scala 442:125] + node _T_622 = eq(btb_wr_addr, UInt<3>("h04")) @[ifu_bp_ctl.scala 448:98] + node _T_623 = and(_T_622, btb_wr_en_way0) @[ifu_bp_ctl.scala 448:107] + node _T_624 = bits(_T_623, 0, 0) @[ifu_bp_ctl.scala 448:125] inst rvclkhdr_13 of rvclkhdr_13 @[lib.scala 399:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset rvclkhdr_13.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_13.io.en <= _T_626 @[lib.scala 402:17] + rvclkhdr_13.io.en <= _T_624 @[lib.scala 402:17] rvclkhdr_13.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way0_out_4 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_626 : @[Reg.scala 28:19] + when _T_624 : @[Reg.scala 28:19] btb_bank0_rd_data_way0_out_4 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_627 = eq(btb_wr_addr, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:98] - node _T_628 = and(_T_627, btb_wr_en_way0) @[ifu_bp_ctl.scala 442:107] - node _T_629 = bits(_T_628, 0, 0) @[ifu_bp_ctl.scala 442:125] + node _T_625 = eq(btb_wr_addr, UInt<3>("h05")) @[ifu_bp_ctl.scala 448:98] + node _T_626 = and(_T_625, btb_wr_en_way0) @[ifu_bp_ctl.scala 448:107] + node _T_627 = bits(_T_626, 0, 0) @[ifu_bp_ctl.scala 448:125] inst rvclkhdr_14 of rvclkhdr_14 @[lib.scala 399:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset rvclkhdr_14.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_14.io.en <= _T_629 @[lib.scala 402:17] + rvclkhdr_14.io.en <= _T_627 @[lib.scala 402:17] rvclkhdr_14.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way0_out_5 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_629 : @[Reg.scala 28:19] + when _T_627 : @[Reg.scala 28:19] btb_bank0_rd_data_way0_out_5 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_630 = eq(btb_wr_addr, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:98] - node _T_631 = and(_T_630, btb_wr_en_way0) @[ifu_bp_ctl.scala 442:107] - node _T_632 = bits(_T_631, 0, 0) @[ifu_bp_ctl.scala 442:125] + node _T_628 = eq(btb_wr_addr, UInt<3>("h06")) @[ifu_bp_ctl.scala 448:98] + node _T_629 = and(_T_628, btb_wr_en_way0) @[ifu_bp_ctl.scala 448:107] + node _T_630 = bits(_T_629, 0, 0) @[ifu_bp_ctl.scala 448:125] inst rvclkhdr_15 of rvclkhdr_15 @[lib.scala 399:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset rvclkhdr_15.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_15.io.en <= _T_632 @[lib.scala 402:17] + rvclkhdr_15.io.en <= _T_630 @[lib.scala 402:17] rvclkhdr_15.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way0_out_6 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_632 : @[Reg.scala 28:19] + when _T_630 : @[Reg.scala 28:19] btb_bank0_rd_data_way0_out_6 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_633 = eq(btb_wr_addr, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:98] - node _T_634 = and(_T_633, btb_wr_en_way0) @[ifu_bp_ctl.scala 442:107] - node _T_635 = bits(_T_634, 0, 0) @[ifu_bp_ctl.scala 442:125] + node _T_631 = eq(btb_wr_addr, UInt<3>("h07")) @[ifu_bp_ctl.scala 448:98] + node _T_632 = and(_T_631, btb_wr_en_way0) @[ifu_bp_ctl.scala 448:107] + node _T_633 = bits(_T_632, 0, 0) @[ifu_bp_ctl.scala 448:125] inst rvclkhdr_16 of rvclkhdr_16 @[lib.scala 399:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset rvclkhdr_16.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_16.io.en <= _T_635 @[lib.scala 402:17] + rvclkhdr_16.io.en <= _T_633 @[lib.scala 402:17] rvclkhdr_16.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way0_out_7 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_635 : @[Reg.scala 28:19] + when _T_633 : @[Reg.scala 28:19] btb_bank0_rd_data_way0_out_7 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_636 = eq(btb_wr_addr, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:98] - node _T_637 = and(_T_636, btb_wr_en_way0) @[ifu_bp_ctl.scala 442:107] - node _T_638 = bits(_T_637, 0, 0) @[ifu_bp_ctl.scala 442:125] + node _T_634 = eq(btb_wr_addr, UInt<4>("h08")) @[ifu_bp_ctl.scala 448:98] + node _T_635 = and(_T_634, btb_wr_en_way0) @[ifu_bp_ctl.scala 448:107] + node _T_636 = bits(_T_635, 0, 0) @[ifu_bp_ctl.scala 448:125] inst rvclkhdr_17 of rvclkhdr_17 @[lib.scala 399:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset rvclkhdr_17.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_17.io.en <= _T_638 @[lib.scala 402:17] + rvclkhdr_17.io.en <= _T_636 @[lib.scala 402:17] rvclkhdr_17.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way0_out_8 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_638 : @[Reg.scala 28:19] + when _T_636 : @[Reg.scala 28:19] btb_bank0_rd_data_way0_out_8 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_639 = eq(btb_wr_addr, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:98] - node _T_640 = and(_T_639, btb_wr_en_way0) @[ifu_bp_ctl.scala 442:107] - node _T_641 = bits(_T_640, 0, 0) @[ifu_bp_ctl.scala 442:125] + node _T_637 = eq(btb_wr_addr, UInt<4>("h09")) @[ifu_bp_ctl.scala 448:98] + node _T_638 = and(_T_637, btb_wr_en_way0) @[ifu_bp_ctl.scala 448:107] + node _T_639 = bits(_T_638, 0, 0) @[ifu_bp_ctl.scala 448:125] inst rvclkhdr_18 of rvclkhdr_18 @[lib.scala 399:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset rvclkhdr_18.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_18.io.en <= _T_641 @[lib.scala 402:17] + rvclkhdr_18.io.en <= _T_639 @[lib.scala 402:17] rvclkhdr_18.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way0_out_9 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_641 : @[Reg.scala 28:19] + when _T_639 : @[Reg.scala 28:19] btb_bank0_rd_data_way0_out_9 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_642 = eq(btb_wr_addr, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:98] - node _T_643 = and(_T_642, btb_wr_en_way0) @[ifu_bp_ctl.scala 442:107] - node _T_644 = bits(_T_643, 0, 0) @[ifu_bp_ctl.scala 442:125] + node _T_640 = eq(btb_wr_addr, UInt<4>("h0a")) @[ifu_bp_ctl.scala 448:98] + node _T_641 = and(_T_640, btb_wr_en_way0) @[ifu_bp_ctl.scala 448:107] + node _T_642 = bits(_T_641, 0, 0) @[ifu_bp_ctl.scala 448:125] inst rvclkhdr_19 of rvclkhdr_19 @[lib.scala 399:23] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset rvclkhdr_19.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_19.io.en <= _T_644 @[lib.scala 402:17] + rvclkhdr_19.io.en <= _T_642 @[lib.scala 402:17] rvclkhdr_19.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way0_out_10 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_644 : @[Reg.scala 28:19] + when _T_642 : @[Reg.scala 28:19] btb_bank0_rd_data_way0_out_10 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_645 = eq(btb_wr_addr, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:98] - node _T_646 = and(_T_645, btb_wr_en_way0) @[ifu_bp_ctl.scala 442:107] - node _T_647 = bits(_T_646, 0, 0) @[ifu_bp_ctl.scala 442:125] + node _T_643 = eq(btb_wr_addr, UInt<4>("h0b")) @[ifu_bp_ctl.scala 448:98] + node _T_644 = and(_T_643, btb_wr_en_way0) @[ifu_bp_ctl.scala 448:107] + node _T_645 = bits(_T_644, 0, 0) @[ifu_bp_ctl.scala 448:125] inst rvclkhdr_20 of rvclkhdr_20 @[lib.scala 399:23] rvclkhdr_20.clock <= clock rvclkhdr_20.reset <= reset rvclkhdr_20.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_20.io.en <= _T_647 @[lib.scala 402:17] + rvclkhdr_20.io.en <= _T_645 @[lib.scala 402:17] rvclkhdr_20.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way0_out_11 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_647 : @[Reg.scala 28:19] + when _T_645 : @[Reg.scala 28:19] btb_bank0_rd_data_way0_out_11 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_648 = eq(btb_wr_addr, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:98] - node _T_649 = and(_T_648, btb_wr_en_way0) @[ifu_bp_ctl.scala 442:107] - node _T_650 = bits(_T_649, 0, 0) @[ifu_bp_ctl.scala 442:125] + node _T_646 = eq(btb_wr_addr, UInt<4>("h0c")) @[ifu_bp_ctl.scala 448:98] + node _T_647 = and(_T_646, btb_wr_en_way0) @[ifu_bp_ctl.scala 448:107] + node _T_648 = bits(_T_647, 0, 0) @[ifu_bp_ctl.scala 448:125] inst rvclkhdr_21 of rvclkhdr_21 @[lib.scala 399:23] rvclkhdr_21.clock <= clock rvclkhdr_21.reset <= reset rvclkhdr_21.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_21.io.en <= _T_650 @[lib.scala 402:17] + rvclkhdr_21.io.en <= _T_648 @[lib.scala 402:17] rvclkhdr_21.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way0_out_12 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_650 : @[Reg.scala 28:19] + when _T_648 : @[Reg.scala 28:19] btb_bank0_rd_data_way0_out_12 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_651 = eq(btb_wr_addr, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:98] - node _T_652 = and(_T_651, btb_wr_en_way0) @[ifu_bp_ctl.scala 442:107] - node _T_653 = bits(_T_652, 0, 0) @[ifu_bp_ctl.scala 442:125] + node _T_649 = eq(btb_wr_addr, UInt<4>("h0d")) @[ifu_bp_ctl.scala 448:98] + node _T_650 = and(_T_649, btb_wr_en_way0) @[ifu_bp_ctl.scala 448:107] + node _T_651 = bits(_T_650, 0, 0) @[ifu_bp_ctl.scala 448:125] inst rvclkhdr_22 of rvclkhdr_22 @[lib.scala 399:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset rvclkhdr_22.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_22.io.en <= _T_653 @[lib.scala 402:17] + rvclkhdr_22.io.en <= _T_651 @[lib.scala 402:17] rvclkhdr_22.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way0_out_13 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_653 : @[Reg.scala 28:19] + when _T_651 : @[Reg.scala 28:19] btb_bank0_rd_data_way0_out_13 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_654 = eq(btb_wr_addr, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:98] - node _T_655 = and(_T_654, btb_wr_en_way0) @[ifu_bp_ctl.scala 442:107] - node _T_656 = bits(_T_655, 0, 0) @[ifu_bp_ctl.scala 442:125] + node _T_652 = eq(btb_wr_addr, UInt<4>("h0e")) @[ifu_bp_ctl.scala 448:98] + node _T_653 = and(_T_652, btb_wr_en_way0) @[ifu_bp_ctl.scala 448:107] + node _T_654 = bits(_T_653, 0, 0) @[ifu_bp_ctl.scala 448:125] inst rvclkhdr_23 of rvclkhdr_23 @[lib.scala 399:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset rvclkhdr_23.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_23.io.en <= _T_656 @[lib.scala 402:17] + rvclkhdr_23.io.en <= _T_654 @[lib.scala 402:17] rvclkhdr_23.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way0_out_14 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_656 : @[Reg.scala 28:19] + when _T_654 : @[Reg.scala 28:19] btb_bank0_rd_data_way0_out_14 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_657 = eq(btb_wr_addr, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:98] - node _T_658 = and(_T_657, btb_wr_en_way0) @[ifu_bp_ctl.scala 442:107] - node _T_659 = bits(_T_658, 0, 0) @[ifu_bp_ctl.scala 442:125] + node _T_655 = eq(btb_wr_addr, UInt<4>("h0f")) @[ifu_bp_ctl.scala 448:98] + node _T_656 = and(_T_655, btb_wr_en_way0) @[ifu_bp_ctl.scala 448:107] + node _T_657 = bits(_T_656, 0, 0) @[ifu_bp_ctl.scala 448:125] inst rvclkhdr_24 of rvclkhdr_24 @[lib.scala 399:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset rvclkhdr_24.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_24.io.en <= _T_659 @[lib.scala 402:17] + rvclkhdr_24.io.en <= _T_657 @[lib.scala 402:17] rvclkhdr_24.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way0_out_15 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_659 : @[Reg.scala 28:19] + when _T_657 : @[Reg.scala 28:19] btb_bank0_rd_data_way0_out_15 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_660 = eq(btb_wr_addr, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:98] - node _T_661 = and(_T_660, btb_wr_en_way1) @[ifu_bp_ctl.scala 443:107] - node _T_662 = bits(_T_661, 0, 0) @[ifu_bp_ctl.scala 443:125] + node _T_658 = eq(btb_wr_addr, UInt<1>("h00")) @[ifu_bp_ctl.scala 449:98] + node _T_659 = and(_T_658, btb_wr_en_way1) @[ifu_bp_ctl.scala 449:107] + node _T_660 = bits(_T_659, 0, 0) @[ifu_bp_ctl.scala 449:125] inst rvclkhdr_25 of rvclkhdr_25 @[lib.scala 399:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset rvclkhdr_25.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_25.io.en <= _T_662 @[lib.scala 402:17] + rvclkhdr_25.io.en <= _T_660 @[lib.scala 402:17] rvclkhdr_25.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way1_out_0 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_662 : @[Reg.scala 28:19] + when _T_660 : @[Reg.scala 28:19] btb_bank0_rd_data_way1_out_0 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_663 = eq(btb_wr_addr, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:98] - node _T_664 = and(_T_663, btb_wr_en_way1) @[ifu_bp_ctl.scala 443:107] - node _T_665 = bits(_T_664, 0, 0) @[ifu_bp_ctl.scala 443:125] + node _T_661 = eq(btb_wr_addr, UInt<1>("h01")) @[ifu_bp_ctl.scala 449:98] + node _T_662 = and(_T_661, btb_wr_en_way1) @[ifu_bp_ctl.scala 449:107] + node _T_663 = bits(_T_662, 0, 0) @[ifu_bp_ctl.scala 449:125] inst rvclkhdr_26 of rvclkhdr_26 @[lib.scala 399:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset rvclkhdr_26.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_26.io.en <= _T_665 @[lib.scala 402:17] + rvclkhdr_26.io.en <= _T_663 @[lib.scala 402:17] rvclkhdr_26.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way1_out_1 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_665 : @[Reg.scala 28:19] + when _T_663 : @[Reg.scala 28:19] btb_bank0_rd_data_way1_out_1 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_666 = eq(btb_wr_addr, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:98] - node _T_667 = and(_T_666, btb_wr_en_way1) @[ifu_bp_ctl.scala 443:107] - node _T_668 = bits(_T_667, 0, 0) @[ifu_bp_ctl.scala 443:125] + node _T_664 = eq(btb_wr_addr, UInt<2>("h02")) @[ifu_bp_ctl.scala 449:98] + node _T_665 = and(_T_664, btb_wr_en_way1) @[ifu_bp_ctl.scala 449:107] + node _T_666 = bits(_T_665, 0, 0) @[ifu_bp_ctl.scala 449:125] inst rvclkhdr_27 of rvclkhdr_27 @[lib.scala 399:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset rvclkhdr_27.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_27.io.en <= _T_668 @[lib.scala 402:17] + rvclkhdr_27.io.en <= _T_666 @[lib.scala 402:17] rvclkhdr_27.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way1_out_2 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_668 : @[Reg.scala 28:19] + when _T_666 : @[Reg.scala 28:19] btb_bank0_rd_data_way1_out_2 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_669 = eq(btb_wr_addr, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:98] - node _T_670 = and(_T_669, btb_wr_en_way1) @[ifu_bp_ctl.scala 443:107] - node _T_671 = bits(_T_670, 0, 0) @[ifu_bp_ctl.scala 443:125] + node _T_667 = eq(btb_wr_addr, UInt<2>("h03")) @[ifu_bp_ctl.scala 449:98] + node _T_668 = and(_T_667, btb_wr_en_way1) @[ifu_bp_ctl.scala 449:107] + node _T_669 = bits(_T_668, 0, 0) @[ifu_bp_ctl.scala 449:125] inst rvclkhdr_28 of rvclkhdr_28 @[lib.scala 399:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset rvclkhdr_28.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_28.io.en <= _T_671 @[lib.scala 402:17] + rvclkhdr_28.io.en <= _T_669 @[lib.scala 402:17] rvclkhdr_28.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way1_out_3 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_671 : @[Reg.scala 28:19] + when _T_669 : @[Reg.scala 28:19] btb_bank0_rd_data_way1_out_3 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_672 = eq(btb_wr_addr, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:98] - node _T_673 = and(_T_672, btb_wr_en_way1) @[ifu_bp_ctl.scala 443:107] - node _T_674 = bits(_T_673, 0, 0) @[ifu_bp_ctl.scala 443:125] + node _T_670 = eq(btb_wr_addr, UInt<3>("h04")) @[ifu_bp_ctl.scala 449:98] + node _T_671 = and(_T_670, btb_wr_en_way1) @[ifu_bp_ctl.scala 449:107] + node _T_672 = bits(_T_671, 0, 0) @[ifu_bp_ctl.scala 449:125] inst rvclkhdr_29 of rvclkhdr_29 @[lib.scala 399:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset rvclkhdr_29.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_29.io.en <= _T_674 @[lib.scala 402:17] + rvclkhdr_29.io.en <= _T_672 @[lib.scala 402:17] rvclkhdr_29.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way1_out_4 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_674 : @[Reg.scala 28:19] + when _T_672 : @[Reg.scala 28:19] btb_bank0_rd_data_way1_out_4 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_675 = eq(btb_wr_addr, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:98] - node _T_676 = and(_T_675, btb_wr_en_way1) @[ifu_bp_ctl.scala 443:107] - node _T_677 = bits(_T_676, 0, 0) @[ifu_bp_ctl.scala 443:125] + node _T_673 = eq(btb_wr_addr, UInt<3>("h05")) @[ifu_bp_ctl.scala 449:98] + node _T_674 = and(_T_673, btb_wr_en_way1) @[ifu_bp_ctl.scala 449:107] + node _T_675 = bits(_T_674, 0, 0) @[ifu_bp_ctl.scala 449:125] inst rvclkhdr_30 of rvclkhdr_30 @[lib.scala 399:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset rvclkhdr_30.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_30.io.en <= _T_677 @[lib.scala 402:17] + rvclkhdr_30.io.en <= _T_675 @[lib.scala 402:17] rvclkhdr_30.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way1_out_5 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_677 : @[Reg.scala 28:19] + when _T_675 : @[Reg.scala 28:19] btb_bank0_rd_data_way1_out_5 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_678 = eq(btb_wr_addr, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:98] - node _T_679 = and(_T_678, btb_wr_en_way1) @[ifu_bp_ctl.scala 443:107] - node _T_680 = bits(_T_679, 0, 0) @[ifu_bp_ctl.scala 443:125] + node _T_676 = eq(btb_wr_addr, UInt<3>("h06")) @[ifu_bp_ctl.scala 449:98] + node _T_677 = and(_T_676, btb_wr_en_way1) @[ifu_bp_ctl.scala 449:107] + node _T_678 = bits(_T_677, 0, 0) @[ifu_bp_ctl.scala 449:125] inst rvclkhdr_31 of rvclkhdr_31 @[lib.scala 399:23] rvclkhdr_31.clock <= clock rvclkhdr_31.reset <= reset rvclkhdr_31.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_31.io.en <= _T_680 @[lib.scala 402:17] + rvclkhdr_31.io.en <= _T_678 @[lib.scala 402:17] rvclkhdr_31.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way1_out_6 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_680 : @[Reg.scala 28:19] + when _T_678 : @[Reg.scala 28:19] btb_bank0_rd_data_way1_out_6 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_681 = eq(btb_wr_addr, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:98] - node _T_682 = and(_T_681, btb_wr_en_way1) @[ifu_bp_ctl.scala 443:107] - node _T_683 = bits(_T_682, 0, 0) @[ifu_bp_ctl.scala 443:125] + node _T_679 = eq(btb_wr_addr, UInt<3>("h07")) @[ifu_bp_ctl.scala 449:98] + node _T_680 = and(_T_679, btb_wr_en_way1) @[ifu_bp_ctl.scala 449:107] + node _T_681 = bits(_T_680, 0, 0) @[ifu_bp_ctl.scala 449:125] inst rvclkhdr_32 of rvclkhdr_32 @[lib.scala 399:23] rvclkhdr_32.clock <= clock rvclkhdr_32.reset <= reset rvclkhdr_32.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_32.io.en <= _T_683 @[lib.scala 402:17] + rvclkhdr_32.io.en <= _T_681 @[lib.scala 402:17] rvclkhdr_32.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way1_out_7 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_683 : @[Reg.scala 28:19] + when _T_681 : @[Reg.scala 28:19] btb_bank0_rd_data_way1_out_7 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_684 = eq(btb_wr_addr, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:98] - node _T_685 = and(_T_684, btb_wr_en_way1) @[ifu_bp_ctl.scala 443:107] - node _T_686 = bits(_T_685, 0, 0) @[ifu_bp_ctl.scala 443:125] + node _T_682 = eq(btb_wr_addr, UInt<4>("h08")) @[ifu_bp_ctl.scala 449:98] + node _T_683 = and(_T_682, btb_wr_en_way1) @[ifu_bp_ctl.scala 449:107] + node _T_684 = bits(_T_683, 0, 0) @[ifu_bp_ctl.scala 449:125] inst rvclkhdr_33 of rvclkhdr_33 @[lib.scala 399:23] rvclkhdr_33.clock <= clock rvclkhdr_33.reset <= reset rvclkhdr_33.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_33.io.en <= _T_686 @[lib.scala 402:17] + rvclkhdr_33.io.en <= _T_684 @[lib.scala 402:17] rvclkhdr_33.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way1_out_8 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_686 : @[Reg.scala 28:19] + when _T_684 : @[Reg.scala 28:19] btb_bank0_rd_data_way1_out_8 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_687 = eq(btb_wr_addr, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:98] - node _T_688 = and(_T_687, btb_wr_en_way1) @[ifu_bp_ctl.scala 443:107] - node _T_689 = bits(_T_688, 0, 0) @[ifu_bp_ctl.scala 443:125] + node _T_685 = eq(btb_wr_addr, UInt<4>("h09")) @[ifu_bp_ctl.scala 449:98] + node _T_686 = and(_T_685, btb_wr_en_way1) @[ifu_bp_ctl.scala 449:107] + node _T_687 = bits(_T_686, 0, 0) @[ifu_bp_ctl.scala 449:125] inst rvclkhdr_34 of rvclkhdr_34 @[lib.scala 399:23] rvclkhdr_34.clock <= clock rvclkhdr_34.reset <= reset rvclkhdr_34.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_34.io.en <= _T_689 @[lib.scala 402:17] + rvclkhdr_34.io.en <= _T_687 @[lib.scala 402:17] rvclkhdr_34.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way1_out_9 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_689 : @[Reg.scala 28:19] + when _T_687 : @[Reg.scala 28:19] btb_bank0_rd_data_way1_out_9 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_690 = eq(btb_wr_addr, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:98] - node _T_691 = and(_T_690, btb_wr_en_way1) @[ifu_bp_ctl.scala 443:107] - node _T_692 = bits(_T_691, 0, 0) @[ifu_bp_ctl.scala 443:125] + node _T_688 = eq(btb_wr_addr, UInt<4>("h0a")) @[ifu_bp_ctl.scala 449:98] + node _T_689 = and(_T_688, btb_wr_en_way1) @[ifu_bp_ctl.scala 449:107] + node _T_690 = bits(_T_689, 0, 0) @[ifu_bp_ctl.scala 449:125] inst rvclkhdr_35 of rvclkhdr_35 @[lib.scala 399:23] rvclkhdr_35.clock <= clock rvclkhdr_35.reset <= reset rvclkhdr_35.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_35.io.en <= _T_692 @[lib.scala 402:17] + rvclkhdr_35.io.en <= _T_690 @[lib.scala 402:17] rvclkhdr_35.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way1_out_10 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_692 : @[Reg.scala 28:19] + when _T_690 : @[Reg.scala 28:19] btb_bank0_rd_data_way1_out_10 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_693 = eq(btb_wr_addr, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:98] - node _T_694 = and(_T_693, btb_wr_en_way1) @[ifu_bp_ctl.scala 443:107] - node _T_695 = bits(_T_694, 0, 0) @[ifu_bp_ctl.scala 443:125] + node _T_691 = eq(btb_wr_addr, UInt<4>("h0b")) @[ifu_bp_ctl.scala 449:98] + node _T_692 = and(_T_691, btb_wr_en_way1) @[ifu_bp_ctl.scala 449:107] + node _T_693 = bits(_T_692, 0, 0) @[ifu_bp_ctl.scala 449:125] inst rvclkhdr_36 of rvclkhdr_36 @[lib.scala 399:23] rvclkhdr_36.clock <= clock rvclkhdr_36.reset <= reset rvclkhdr_36.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_36.io.en <= _T_695 @[lib.scala 402:17] + rvclkhdr_36.io.en <= _T_693 @[lib.scala 402:17] rvclkhdr_36.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way1_out_11 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_695 : @[Reg.scala 28:19] + when _T_693 : @[Reg.scala 28:19] btb_bank0_rd_data_way1_out_11 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_696 = eq(btb_wr_addr, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:98] - node _T_697 = and(_T_696, btb_wr_en_way1) @[ifu_bp_ctl.scala 443:107] - node _T_698 = bits(_T_697, 0, 0) @[ifu_bp_ctl.scala 443:125] + node _T_694 = eq(btb_wr_addr, UInt<4>("h0c")) @[ifu_bp_ctl.scala 449:98] + node _T_695 = and(_T_694, btb_wr_en_way1) @[ifu_bp_ctl.scala 449:107] + node _T_696 = bits(_T_695, 0, 0) @[ifu_bp_ctl.scala 449:125] inst rvclkhdr_37 of rvclkhdr_37 @[lib.scala 399:23] rvclkhdr_37.clock <= clock rvclkhdr_37.reset <= reset rvclkhdr_37.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_37.io.en <= _T_698 @[lib.scala 402:17] + rvclkhdr_37.io.en <= _T_696 @[lib.scala 402:17] rvclkhdr_37.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way1_out_12 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_698 : @[Reg.scala 28:19] + when _T_696 : @[Reg.scala 28:19] btb_bank0_rd_data_way1_out_12 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_699 = eq(btb_wr_addr, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:98] - node _T_700 = and(_T_699, btb_wr_en_way1) @[ifu_bp_ctl.scala 443:107] - node _T_701 = bits(_T_700, 0, 0) @[ifu_bp_ctl.scala 443:125] + node _T_697 = eq(btb_wr_addr, UInt<4>("h0d")) @[ifu_bp_ctl.scala 449:98] + node _T_698 = and(_T_697, btb_wr_en_way1) @[ifu_bp_ctl.scala 449:107] + node _T_699 = bits(_T_698, 0, 0) @[ifu_bp_ctl.scala 449:125] inst rvclkhdr_38 of rvclkhdr_38 @[lib.scala 399:23] rvclkhdr_38.clock <= clock rvclkhdr_38.reset <= reset rvclkhdr_38.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_38.io.en <= _T_701 @[lib.scala 402:17] + rvclkhdr_38.io.en <= _T_699 @[lib.scala 402:17] rvclkhdr_38.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way1_out_13 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_701 : @[Reg.scala 28:19] + when _T_699 : @[Reg.scala 28:19] btb_bank0_rd_data_way1_out_13 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_702 = eq(btb_wr_addr, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:98] - node _T_703 = and(_T_702, btb_wr_en_way1) @[ifu_bp_ctl.scala 443:107] - node _T_704 = bits(_T_703, 0, 0) @[ifu_bp_ctl.scala 443:125] + node _T_700 = eq(btb_wr_addr, UInt<4>("h0e")) @[ifu_bp_ctl.scala 449:98] + node _T_701 = and(_T_700, btb_wr_en_way1) @[ifu_bp_ctl.scala 449:107] + node _T_702 = bits(_T_701, 0, 0) @[ifu_bp_ctl.scala 449:125] inst rvclkhdr_39 of rvclkhdr_39 @[lib.scala 399:23] rvclkhdr_39.clock <= clock rvclkhdr_39.reset <= reset rvclkhdr_39.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_39.io.en <= _T_704 @[lib.scala 402:17] + rvclkhdr_39.io.en <= _T_702 @[lib.scala 402:17] rvclkhdr_39.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way1_out_14 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_704 : @[Reg.scala 28:19] + when _T_702 : @[Reg.scala 28:19] btb_bank0_rd_data_way1_out_14 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_705 = eq(btb_wr_addr, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:98] - node _T_706 = and(_T_705, btb_wr_en_way1) @[ifu_bp_ctl.scala 443:107] - node _T_707 = bits(_T_706, 0, 0) @[ifu_bp_ctl.scala 443:125] + node _T_703 = eq(btb_wr_addr, UInt<4>("h0f")) @[ifu_bp_ctl.scala 449:98] + node _T_704 = and(_T_703, btb_wr_en_way1) @[ifu_bp_ctl.scala 449:107] + node _T_705 = bits(_T_704, 0, 0) @[ifu_bp_ctl.scala 449:125] inst rvclkhdr_40 of rvclkhdr_40 @[lib.scala 399:23] rvclkhdr_40.clock <= clock rvclkhdr_40.reset <= reset rvclkhdr_40.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_40.io.en <= _T_707 @[lib.scala 402:17] + rvclkhdr_40.io.en <= _T_705 @[lib.scala 402:17] rvclkhdr_40.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] reg btb_bank0_rd_data_way1_out_15 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_707 : @[Reg.scala 28:19] + when _T_705 : @[Reg.scala 28:19] btb_bank0_rd_data_way1_out_15 <= btb_wr_data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_708 = eq(btb_rd_addr_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 445:80] - node _T_709 = bits(_T_708, 0, 0) @[ifu_bp_ctl.scala 445:89] - node _T_710 = eq(btb_rd_addr_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 445:80] - node _T_711 = bits(_T_710, 0, 0) @[ifu_bp_ctl.scala 445:89] - node _T_712 = eq(btb_rd_addr_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 445:80] - node _T_713 = bits(_T_712, 0, 0) @[ifu_bp_ctl.scala 445:89] - node _T_714 = eq(btb_rd_addr_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 445:80] - node _T_715 = bits(_T_714, 0, 0) @[ifu_bp_ctl.scala 445:89] - node _T_716 = eq(btb_rd_addr_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 445:80] - node _T_717 = bits(_T_716, 0, 0) @[ifu_bp_ctl.scala 445:89] - node _T_718 = eq(btb_rd_addr_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 445:80] - node _T_719 = bits(_T_718, 0, 0) @[ifu_bp_ctl.scala 445:89] - node _T_720 = eq(btb_rd_addr_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 445:80] - node _T_721 = bits(_T_720, 0, 0) @[ifu_bp_ctl.scala 445:89] - node _T_722 = eq(btb_rd_addr_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 445:80] - node _T_723 = bits(_T_722, 0, 0) @[ifu_bp_ctl.scala 445:89] - node _T_724 = eq(btb_rd_addr_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 445:80] - node _T_725 = bits(_T_724, 0, 0) @[ifu_bp_ctl.scala 445:89] - node _T_726 = eq(btb_rd_addr_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 445:80] - node _T_727 = bits(_T_726, 0, 0) @[ifu_bp_ctl.scala 445:89] - node _T_728 = eq(btb_rd_addr_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 445:80] - node _T_729 = bits(_T_728, 0, 0) @[ifu_bp_ctl.scala 445:89] - node _T_730 = eq(btb_rd_addr_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 445:80] - node _T_731 = bits(_T_730, 0, 0) @[ifu_bp_ctl.scala 445:89] - node _T_732 = eq(btb_rd_addr_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 445:80] - node _T_733 = bits(_T_732, 0, 0) @[ifu_bp_ctl.scala 445:89] - node _T_734 = eq(btb_rd_addr_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 445:80] - node _T_735 = bits(_T_734, 0, 0) @[ifu_bp_ctl.scala 445:89] - node _T_736 = eq(btb_rd_addr_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 445:80] - node _T_737 = bits(_T_736, 0, 0) @[ifu_bp_ctl.scala 445:89] - node _T_738 = eq(btb_rd_addr_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 445:80] - node _T_739 = bits(_T_738, 0, 0) @[ifu_bp_ctl.scala 445:89] - node _T_740 = mux(_T_709, btb_bank0_rd_data_way0_out_0, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_741 = mux(_T_711, btb_bank0_rd_data_way0_out_1, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_742 = mux(_T_713, btb_bank0_rd_data_way0_out_2, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_743 = mux(_T_715, btb_bank0_rd_data_way0_out_3, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_744 = mux(_T_717, btb_bank0_rd_data_way0_out_4, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_745 = mux(_T_719, btb_bank0_rd_data_way0_out_5, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_746 = mux(_T_721, btb_bank0_rd_data_way0_out_6, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_747 = mux(_T_723, btb_bank0_rd_data_way0_out_7, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_748 = mux(_T_725, btb_bank0_rd_data_way0_out_8, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_749 = mux(_T_727, btb_bank0_rd_data_way0_out_9, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_750 = mux(_T_729, btb_bank0_rd_data_way0_out_10, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_751 = mux(_T_731, btb_bank0_rd_data_way0_out_11, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_752 = mux(_T_733, btb_bank0_rd_data_way0_out_12, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_753 = mux(_T_735, btb_bank0_rd_data_way0_out_13, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_754 = mux(_T_737, btb_bank0_rd_data_way0_out_14, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_755 = mux(_T_739, btb_bank0_rd_data_way0_out_15, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_756 = or(_T_740, _T_741) @[Mux.scala 27:72] + node _T_706 = eq(btb_rd_addr_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 451:80] + node _T_707 = bits(_T_706, 0, 0) @[ifu_bp_ctl.scala 451:89] + node _T_708 = eq(btb_rd_addr_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 451:80] + node _T_709 = bits(_T_708, 0, 0) @[ifu_bp_ctl.scala 451:89] + node _T_710 = eq(btb_rd_addr_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 451:80] + node _T_711 = bits(_T_710, 0, 0) @[ifu_bp_ctl.scala 451:89] + node _T_712 = eq(btb_rd_addr_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 451:80] + node _T_713 = bits(_T_712, 0, 0) @[ifu_bp_ctl.scala 451:89] + node _T_714 = eq(btb_rd_addr_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 451:80] + node _T_715 = bits(_T_714, 0, 0) @[ifu_bp_ctl.scala 451:89] + node _T_716 = eq(btb_rd_addr_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 451:80] + node _T_717 = bits(_T_716, 0, 0) @[ifu_bp_ctl.scala 451:89] + node _T_718 = eq(btb_rd_addr_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 451:80] + node _T_719 = bits(_T_718, 0, 0) @[ifu_bp_ctl.scala 451:89] + node _T_720 = eq(btb_rd_addr_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 451:80] + node _T_721 = bits(_T_720, 0, 0) @[ifu_bp_ctl.scala 451:89] + node _T_722 = eq(btb_rd_addr_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 451:80] + node _T_723 = bits(_T_722, 0, 0) @[ifu_bp_ctl.scala 451:89] + node _T_724 = eq(btb_rd_addr_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 451:80] + node _T_725 = bits(_T_724, 0, 0) @[ifu_bp_ctl.scala 451:89] + node _T_726 = eq(btb_rd_addr_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 451:80] + node _T_727 = bits(_T_726, 0, 0) @[ifu_bp_ctl.scala 451:89] + node _T_728 = eq(btb_rd_addr_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 451:80] + node _T_729 = bits(_T_728, 0, 0) @[ifu_bp_ctl.scala 451:89] + node _T_730 = eq(btb_rd_addr_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 451:80] + node _T_731 = bits(_T_730, 0, 0) @[ifu_bp_ctl.scala 451:89] + node _T_732 = eq(btb_rd_addr_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 451:80] + node _T_733 = bits(_T_732, 0, 0) @[ifu_bp_ctl.scala 451:89] + node _T_734 = eq(btb_rd_addr_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 451:80] + node _T_735 = bits(_T_734, 0, 0) @[ifu_bp_ctl.scala 451:89] + node _T_736 = eq(btb_rd_addr_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 451:80] + node _T_737 = bits(_T_736, 0, 0) @[ifu_bp_ctl.scala 451:89] + node _T_738 = mux(_T_707, btb_bank0_rd_data_way0_out_0, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_739 = mux(_T_709, btb_bank0_rd_data_way0_out_1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_740 = mux(_T_711, btb_bank0_rd_data_way0_out_2, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_741 = mux(_T_713, btb_bank0_rd_data_way0_out_3, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_742 = mux(_T_715, btb_bank0_rd_data_way0_out_4, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_743 = mux(_T_717, btb_bank0_rd_data_way0_out_5, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_744 = mux(_T_719, btb_bank0_rd_data_way0_out_6, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_745 = mux(_T_721, btb_bank0_rd_data_way0_out_7, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_746 = mux(_T_723, btb_bank0_rd_data_way0_out_8, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_747 = mux(_T_725, btb_bank0_rd_data_way0_out_9, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_748 = mux(_T_727, btb_bank0_rd_data_way0_out_10, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_749 = mux(_T_729, btb_bank0_rd_data_way0_out_11, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_750 = mux(_T_731, btb_bank0_rd_data_way0_out_12, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_751 = mux(_T_733, btb_bank0_rd_data_way0_out_13, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_752 = mux(_T_735, btb_bank0_rd_data_way0_out_14, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_753 = mux(_T_737, btb_bank0_rd_data_way0_out_15, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_754 = or(_T_738, _T_739) @[Mux.scala 27:72] + node _T_755 = or(_T_754, _T_740) @[Mux.scala 27:72] + node _T_756 = or(_T_755, _T_741) @[Mux.scala 27:72] node _T_757 = or(_T_756, _T_742) @[Mux.scala 27:72] node _T_758 = or(_T_757, _T_743) @[Mux.scala 27:72] node _T_759 = or(_T_758, _T_744) @[Mux.scala 27:72] @@ -2457,60 +2458,60 @@ circuit ifu_bp_ctl : node _T_766 = or(_T_765, _T_751) @[Mux.scala 27:72] node _T_767 = or(_T_766, _T_752) @[Mux.scala 27:72] node _T_768 = or(_T_767, _T_753) @[Mux.scala 27:72] - node _T_769 = or(_T_768, _T_754) @[Mux.scala 27:72] - node _T_770 = or(_T_769, _T_755) @[Mux.scala 27:72] - wire _T_771 : UInt @[Mux.scala 27:72] - _T_771 <= _T_770 @[Mux.scala 27:72] - btb_bank0_rd_data_way0_f <= _T_771 @[ifu_bp_ctl.scala 445:28] - node _T_772 = eq(btb_rd_addr_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 446:80] - node _T_773 = bits(_T_772, 0, 0) @[ifu_bp_ctl.scala 446:89] - node _T_774 = eq(btb_rd_addr_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 446:80] - node _T_775 = bits(_T_774, 0, 0) @[ifu_bp_ctl.scala 446:89] - node _T_776 = eq(btb_rd_addr_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 446:80] - node _T_777 = bits(_T_776, 0, 0) @[ifu_bp_ctl.scala 446:89] - node _T_778 = eq(btb_rd_addr_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 446:80] - node _T_779 = bits(_T_778, 0, 0) @[ifu_bp_ctl.scala 446:89] - node _T_780 = eq(btb_rd_addr_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 446:80] - node _T_781 = bits(_T_780, 0, 0) @[ifu_bp_ctl.scala 446:89] - node _T_782 = eq(btb_rd_addr_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 446:80] - node _T_783 = bits(_T_782, 0, 0) @[ifu_bp_ctl.scala 446:89] - node _T_784 = eq(btb_rd_addr_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 446:80] - node _T_785 = bits(_T_784, 0, 0) @[ifu_bp_ctl.scala 446:89] - node _T_786 = eq(btb_rd_addr_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 446:80] - node _T_787 = bits(_T_786, 0, 0) @[ifu_bp_ctl.scala 446:89] - node _T_788 = eq(btb_rd_addr_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 446:80] - node _T_789 = bits(_T_788, 0, 0) @[ifu_bp_ctl.scala 446:89] - node _T_790 = eq(btb_rd_addr_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 446:80] - node _T_791 = bits(_T_790, 0, 0) @[ifu_bp_ctl.scala 446:89] - node _T_792 = eq(btb_rd_addr_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 446:80] - node _T_793 = bits(_T_792, 0, 0) @[ifu_bp_ctl.scala 446:89] - node _T_794 = eq(btb_rd_addr_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 446:80] - node _T_795 = bits(_T_794, 0, 0) @[ifu_bp_ctl.scala 446:89] - node _T_796 = eq(btb_rd_addr_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 446:80] - node _T_797 = bits(_T_796, 0, 0) @[ifu_bp_ctl.scala 446:89] - node _T_798 = eq(btb_rd_addr_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 446:80] - node _T_799 = bits(_T_798, 0, 0) @[ifu_bp_ctl.scala 446:89] - node _T_800 = eq(btb_rd_addr_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 446:80] - node _T_801 = bits(_T_800, 0, 0) @[ifu_bp_ctl.scala 446:89] - node _T_802 = eq(btb_rd_addr_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 446:80] - node _T_803 = bits(_T_802, 0, 0) @[ifu_bp_ctl.scala 446:89] - node _T_804 = mux(_T_773, btb_bank0_rd_data_way1_out_0, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_805 = mux(_T_775, btb_bank0_rd_data_way1_out_1, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_806 = mux(_T_777, btb_bank0_rd_data_way1_out_2, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_807 = mux(_T_779, btb_bank0_rd_data_way1_out_3, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_808 = mux(_T_781, btb_bank0_rd_data_way1_out_4, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_809 = mux(_T_783, btb_bank0_rd_data_way1_out_5, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_810 = mux(_T_785, btb_bank0_rd_data_way1_out_6, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_811 = mux(_T_787, btb_bank0_rd_data_way1_out_7, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_812 = mux(_T_789, btb_bank0_rd_data_way1_out_8, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_813 = mux(_T_791, btb_bank0_rd_data_way1_out_9, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_814 = mux(_T_793, btb_bank0_rd_data_way1_out_10, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_815 = mux(_T_795, btb_bank0_rd_data_way1_out_11, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_816 = mux(_T_797, btb_bank0_rd_data_way1_out_12, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_817 = mux(_T_799, btb_bank0_rd_data_way1_out_13, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_818 = mux(_T_801, btb_bank0_rd_data_way1_out_14, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_819 = mux(_T_803, btb_bank0_rd_data_way1_out_15, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_820 = or(_T_804, _T_805) @[Mux.scala 27:72] + wire _T_769 : UInt @[Mux.scala 27:72] + _T_769 <= _T_768 @[Mux.scala 27:72] + btb_bank0_rd_data_way0_f <= _T_769 @[ifu_bp_ctl.scala 451:28] + node _T_770 = eq(btb_rd_addr_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 452:80] + node _T_771 = bits(_T_770, 0, 0) @[ifu_bp_ctl.scala 452:89] + node _T_772 = eq(btb_rd_addr_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 452:80] + node _T_773 = bits(_T_772, 0, 0) @[ifu_bp_ctl.scala 452:89] + node _T_774 = eq(btb_rd_addr_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 452:80] + node _T_775 = bits(_T_774, 0, 0) @[ifu_bp_ctl.scala 452:89] + node _T_776 = eq(btb_rd_addr_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 452:80] + node _T_777 = bits(_T_776, 0, 0) @[ifu_bp_ctl.scala 452:89] + node _T_778 = eq(btb_rd_addr_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 452:80] + node _T_779 = bits(_T_778, 0, 0) @[ifu_bp_ctl.scala 452:89] + node _T_780 = eq(btb_rd_addr_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 452:80] + node _T_781 = bits(_T_780, 0, 0) @[ifu_bp_ctl.scala 452:89] + node _T_782 = eq(btb_rd_addr_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 452:80] + node _T_783 = bits(_T_782, 0, 0) @[ifu_bp_ctl.scala 452:89] + node _T_784 = eq(btb_rd_addr_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 452:80] + node _T_785 = bits(_T_784, 0, 0) @[ifu_bp_ctl.scala 452:89] + node _T_786 = eq(btb_rd_addr_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 452:80] + node _T_787 = bits(_T_786, 0, 0) @[ifu_bp_ctl.scala 452:89] + node _T_788 = eq(btb_rd_addr_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 452:80] + node _T_789 = bits(_T_788, 0, 0) @[ifu_bp_ctl.scala 452:89] + node _T_790 = eq(btb_rd_addr_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 452:80] + node _T_791 = bits(_T_790, 0, 0) @[ifu_bp_ctl.scala 452:89] + node _T_792 = eq(btb_rd_addr_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 452:80] + node _T_793 = bits(_T_792, 0, 0) @[ifu_bp_ctl.scala 452:89] + node _T_794 = eq(btb_rd_addr_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 452:80] + node _T_795 = bits(_T_794, 0, 0) @[ifu_bp_ctl.scala 452:89] + node _T_796 = eq(btb_rd_addr_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 452:80] + node _T_797 = bits(_T_796, 0, 0) @[ifu_bp_ctl.scala 452:89] + node _T_798 = eq(btb_rd_addr_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 452:80] + node _T_799 = bits(_T_798, 0, 0) @[ifu_bp_ctl.scala 452:89] + node _T_800 = eq(btb_rd_addr_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 452:80] + node _T_801 = bits(_T_800, 0, 0) @[ifu_bp_ctl.scala 452:89] + node _T_802 = mux(_T_771, btb_bank0_rd_data_way1_out_0, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_803 = mux(_T_773, btb_bank0_rd_data_way1_out_1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_804 = mux(_T_775, btb_bank0_rd_data_way1_out_2, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_805 = mux(_T_777, btb_bank0_rd_data_way1_out_3, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_806 = mux(_T_779, btb_bank0_rd_data_way1_out_4, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_807 = mux(_T_781, btb_bank0_rd_data_way1_out_5, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_808 = mux(_T_783, btb_bank0_rd_data_way1_out_6, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_809 = mux(_T_785, btb_bank0_rd_data_way1_out_7, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_810 = mux(_T_787, btb_bank0_rd_data_way1_out_8, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_811 = mux(_T_789, btb_bank0_rd_data_way1_out_9, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_812 = mux(_T_791, btb_bank0_rd_data_way1_out_10, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_813 = mux(_T_793, btb_bank0_rd_data_way1_out_11, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_814 = mux(_T_795, btb_bank0_rd_data_way1_out_12, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_815 = mux(_T_797, btb_bank0_rd_data_way1_out_13, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_816 = mux(_T_799, btb_bank0_rd_data_way1_out_14, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_817 = mux(_T_801, btb_bank0_rd_data_way1_out_15, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_818 = or(_T_802, _T_803) @[Mux.scala 27:72] + node _T_819 = or(_T_818, _T_804) @[Mux.scala 27:72] + node _T_820 = or(_T_819, _T_805) @[Mux.scala 27:72] node _T_821 = or(_T_820, _T_806) @[Mux.scala 27:72] node _T_822 = or(_T_821, _T_807) @[Mux.scala 27:72] node _T_823 = or(_T_822, _T_808) @[Mux.scala 27:72] @@ -2523,60 +2524,60 @@ circuit ifu_bp_ctl : node _T_830 = or(_T_829, _T_815) @[Mux.scala 27:72] node _T_831 = or(_T_830, _T_816) @[Mux.scala 27:72] node _T_832 = or(_T_831, _T_817) @[Mux.scala 27:72] - node _T_833 = or(_T_832, _T_818) @[Mux.scala 27:72] - node _T_834 = or(_T_833, _T_819) @[Mux.scala 27:72] - wire _T_835 : UInt @[Mux.scala 27:72] - _T_835 <= _T_834 @[Mux.scala 27:72] - btb_bank0_rd_data_way1_f <= _T_835 @[ifu_bp_ctl.scala 446:28] - node _T_836 = eq(btb_rd_addr_p1_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 449:86] - node _T_837 = bits(_T_836, 0, 0) @[ifu_bp_ctl.scala 449:95] - node _T_838 = eq(btb_rd_addr_p1_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 449:86] - node _T_839 = bits(_T_838, 0, 0) @[ifu_bp_ctl.scala 449:95] - node _T_840 = eq(btb_rd_addr_p1_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 449:86] - node _T_841 = bits(_T_840, 0, 0) @[ifu_bp_ctl.scala 449:95] - node _T_842 = eq(btb_rd_addr_p1_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 449:86] - node _T_843 = bits(_T_842, 0, 0) @[ifu_bp_ctl.scala 449:95] - node _T_844 = eq(btb_rd_addr_p1_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 449:86] - node _T_845 = bits(_T_844, 0, 0) @[ifu_bp_ctl.scala 449:95] - node _T_846 = eq(btb_rd_addr_p1_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 449:86] - node _T_847 = bits(_T_846, 0, 0) @[ifu_bp_ctl.scala 449:95] - node _T_848 = eq(btb_rd_addr_p1_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 449:86] - node _T_849 = bits(_T_848, 0, 0) @[ifu_bp_ctl.scala 449:95] - node _T_850 = eq(btb_rd_addr_p1_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 449:86] - node _T_851 = bits(_T_850, 0, 0) @[ifu_bp_ctl.scala 449:95] - node _T_852 = eq(btb_rd_addr_p1_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 449:86] - node _T_853 = bits(_T_852, 0, 0) @[ifu_bp_ctl.scala 449:95] - node _T_854 = eq(btb_rd_addr_p1_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 449:86] - node _T_855 = bits(_T_854, 0, 0) @[ifu_bp_ctl.scala 449:95] - node _T_856 = eq(btb_rd_addr_p1_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 449:86] - node _T_857 = bits(_T_856, 0, 0) @[ifu_bp_ctl.scala 449:95] - node _T_858 = eq(btb_rd_addr_p1_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 449:86] - node _T_859 = bits(_T_858, 0, 0) @[ifu_bp_ctl.scala 449:95] - node _T_860 = eq(btb_rd_addr_p1_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 449:86] - node _T_861 = bits(_T_860, 0, 0) @[ifu_bp_ctl.scala 449:95] - node _T_862 = eq(btb_rd_addr_p1_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 449:86] - node _T_863 = bits(_T_862, 0, 0) @[ifu_bp_ctl.scala 449:95] - node _T_864 = eq(btb_rd_addr_p1_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 449:86] - node _T_865 = bits(_T_864, 0, 0) @[ifu_bp_ctl.scala 449:95] - node _T_866 = eq(btb_rd_addr_p1_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 449:86] - node _T_867 = bits(_T_866, 0, 0) @[ifu_bp_ctl.scala 449:95] - node _T_868 = mux(_T_837, btb_bank0_rd_data_way0_out_0, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_869 = mux(_T_839, btb_bank0_rd_data_way0_out_1, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_870 = mux(_T_841, btb_bank0_rd_data_way0_out_2, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_871 = mux(_T_843, btb_bank0_rd_data_way0_out_3, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_872 = mux(_T_845, btb_bank0_rd_data_way0_out_4, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_873 = mux(_T_847, btb_bank0_rd_data_way0_out_5, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_874 = mux(_T_849, btb_bank0_rd_data_way0_out_6, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_875 = mux(_T_851, btb_bank0_rd_data_way0_out_7, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_876 = mux(_T_853, btb_bank0_rd_data_way0_out_8, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_877 = mux(_T_855, btb_bank0_rd_data_way0_out_9, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_878 = mux(_T_857, btb_bank0_rd_data_way0_out_10, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_879 = mux(_T_859, btb_bank0_rd_data_way0_out_11, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_880 = mux(_T_861, btb_bank0_rd_data_way0_out_12, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_881 = mux(_T_863, btb_bank0_rd_data_way0_out_13, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_882 = mux(_T_865, btb_bank0_rd_data_way0_out_14, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_883 = mux(_T_867, btb_bank0_rd_data_way0_out_15, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_884 = or(_T_868, _T_869) @[Mux.scala 27:72] + wire _T_833 : UInt @[Mux.scala 27:72] + _T_833 <= _T_832 @[Mux.scala 27:72] + btb_bank0_rd_data_way1_f <= _T_833 @[ifu_bp_ctl.scala 452:28] + node _T_834 = eq(btb_rd_addr_p1_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 455:86] + node _T_835 = bits(_T_834, 0, 0) @[ifu_bp_ctl.scala 455:95] + node _T_836 = eq(btb_rd_addr_p1_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 455:86] + node _T_837 = bits(_T_836, 0, 0) @[ifu_bp_ctl.scala 455:95] + node _T_838 = eq(btb_rd_addr_p1_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 455:86] + node _T_839 = bits(_T_838, 0, 0) @[ifu_bp_ctl.scala 455:95] + node _T_840 = eq(btb_rd_addr_p1_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 455:86] + node _T_841 = bits(_T_840, 0, 0) @[ifu_bp_ctl.scala 455:95] + node _T_842 = eq(btb_rd_addr_p1_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 455:86] + node _T_843 = bits(_T_842, 0, 0) @[ifu_bp_ctl.scala 455:95] + node _T_844 = eq(btb_rd_addr_p1_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 455:86] + node _T_845 = bits(_T_844, 0, 0) @[ifu_bp_ctl.scala 455:95] + node _T_846 = eq(btb_rd_addr_p1_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 455:86] + node _T_847 = bits(_T_846, 0, 0) @[ifu_bp_ctl.scala 455:95] + node _T_848 = eq(btb_rd_addr_p1_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 455:86] + node _T_849 = bits(_T_848, 0, 0) @[ifu_bp_ctl.scala 455:95] + node _T_850 = eq(btb_rd_addr_p1_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 455:86] + node _T_851 = bits(_T_850, 0, 0) @[ifu_bp_ctl.scala 455:95] + node _T_852 = eq(btb_rd_addr_p1_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 455:86] + node _T_853 = bits(_T_852, 0, 0) @[ifu_bp_ctl.scala 455:95] + node _T_854 = eq(btb_rd_addr_p1_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 455:86] + node _T_855 = bits(_T_854, 0, 0) @[ifu_bp_ctl.scala 455:95] + node _T_856 = eq(btb_rd_addr_p1_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 455:86] + node _T_857 = bits(_T_856, 0, 0) @[ifu_bp_ctl.scala 455:95] + node _T_858 = eq(btb_rd_addr_p1_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 455:86] + node _T_859 = bits(_T_858, 0, 0) @[ifu_bp_ctl.scala 455:95] + node _T_860 = eq(btb_rd_addr_p1_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 455:86] + node _T_861 = bits(_T_860, 0, 0) @[ifu_bp_ctl.scala 455:95] + node _T_862 = eq(btb_rd_addr_p1_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 455:86] + node _T_863 = bits(_T_862, 0, 0) @[ifu_bp_ctl.scala 455:95] + node _T_864 = eq(btb_rd_addr_p1_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 455:86] + node _T_865 = bits(_T_864, 0, 0) @[ifu_bp_ctl.scala 455:95] + node _T_866 = mux(_T_835, btb_bank0_rd_data_way0_out_0, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_867 = mux(_T_837, btb_bank0_rd_data_way0_out_1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_868 = mux(_T_839, btb_bank0_rd_data_way0_out_2, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_869 = mux(_T_841, btb_bank0_rd_data_way0_out_3, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_870 = mux(_T_843, btb_bank0_rd_data_way0_out_4, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_871 = mux(_T_845, btb_bank0_rd_data_way0_out_5, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_872 = mux(_T_847, btb_bank0_rd_data_way0_out_6, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_873 = mux(_T_849, btb_bank0_rd_data_way0_out_7, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_874 = mux(_T_851, btb_bank0_rd_data_way0_out_8, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_875 = mux(_T_853, btb_bank0_rd_data_way0_out_9, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_876 = mux(_T_855, btb_bank0_rd_data_way0_out_10, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_877 = mux(_T_857, btb_bank0_rd_data_way0_out_11, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_878 = mux(_T_859, btb_bank0_rd_data_way0_out_12, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_879 = mux(_T_861, btb_bank0_rd_data_way0_out_13, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_880 = mux(_T_863, btb_bank0_rd_data_way0_out_14, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_881 = mux(_T_865, btb_bank0_rd_data_way0_out_15, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_882 = or(_T_866, _T_867) @[Mux.scala 27:72] + node _T_883 = or(_T_882, _T_868) @[Mux.scala 27:72] + node _T_884 = or(_T_883, _T_869) @[Mux.scala 27:72] node _T_885 = or(_T_884, _T_870) @[Mux.scala 27:72] node _T_886 = or(_T_885, _T_871) @[Mux.scala 27:72] node _T_887 = or(_T_886, _T_872) @[Mux.scala 27:72] @@ -2589,60 +2590,60 @@ circuit ifu_bp_ctl : node _T_894 = or(_T_893, _T_879) @[Mux.scala 27:72] node _T_895 = or(_T_894, _T_880) @[Mux.scala 27:72] node _T_896 = or(_T_895, _T_881) @[Mux.scala 27:72] - node _T_897 = or(_T_896, _T_882) @[Mux.scala 27:72] - node _T_898 = or(_T_897, _T_883) @[Mux.scala 27:72] - wire _T_899 : UInt @[Mux.scala 27:72] - _T_899 <= _T_898 @[Mux.scala 27:72] - btb_bank0_rd_data_way0_p1_f <= _T_899 @[ifu_bp_ctl.scala 449:31] - node _T_900 = eq(btb_rd_addr_p1_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 450:86] - node _T_901 = bits(_T_900, 0, 0) @[ifu_bp_ctl.scala 450:95] - node _T_902 = eq(btb_rd_addr_p1_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 450:86] - node _T_903 = bits(_T_902, 0, 0) @[ifu_bp_ctl.scala 450:95] - node _T_904 = eq(btb_rd_addr_p1_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 450:86] - node _T_905 = bits(_T_904, 0, 0) @[ifu_bp_ctl.scala 450:95] - node _T_906 = eq(btb_rd_addr_p1_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 450:86] - node _T_907 = bits(_T_906, 0, 0) @[ifu_bp_ctl.scala 450:95] - node _T_908 = eq(btb_rd_addr_p1_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 450:86] - node _T_909 = bits(_T_908, 0, 0) @[ifu_bp_ctl.scala 450:95] - node _T_910 = eq(btb_rd_addr_p1_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 450:86] - node _T_911 = bits(_T_910, 0, 0) @[ifu_bp_ctl.scala 450:95] - node _T_912 = eq(btb_rd_addr_p1_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 450:86] - node _T_913 = bits(_T_912, 0, 0) @[ifu_bp_ctl.scala 450:95] - node _T_914 = eq(btb_rd_addr_p1_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 450:86] - node _T_915 = bits(_T_914, 0, 0) @[ifu_bp_ctl.scala 450:95] - node _T_916 = eq(btb_rd_addr_p1_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 450:86] - node _T_917 = bits(_T_916, 0, 0) @[ifu_bp_ctl.scala 450:95] - node _T_918 = eq(btb_rd_addr_p1_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 450:86] - node _T_919 = bits(_T_918, 0, 0) @[ifu_bp_ctl.scala 450:95] - node _T_920 = eq(btb_rd_addr_p1_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 450:86] - node _T_921 = bits(_T_920, 0, 0) @[ifu_bp_ctl.scala 450:95] - node _T_922 = eq(btb_rd_addr_p1_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 450:86] - node _T_923 = bits(_T_922, 0, 0) @[ifu_bp_ctl.scala 450:95] - node _T_924 = eq(btb_rd_addr_p1_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 450:86] - node _T_925 = bits(_T_924, 0, 0) @[ifu_bp_ctl.scala 450:95] - node _T_926 = eq(btb_rd_addr_p1_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 450:86] - node _T_927 = bits(_T_926, 0, 0) @[ifu_bp_ctl.scala 450:95] - node _T_928 = eq(btb_rd_addr_p1_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 450:86] - node _T_929 = bits(_T_928, 0, 0) @[ifu_bp_ctl.scala 450:95] - node _T_930 = eq(btb_rd_addr_p1_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 450:86] - node _T_931 = bits(_T_930, 0, 0) @[ifu_bp_ctl.scala 450:95] - node _T_932 = mux(_T_901, btb_bank0_rd_data_way1_out_0, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_933 = mux(_T_903, btb_bank0_rd_data_way1_out_1, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_934 = mux(_T_905, btb_bank0_rd_data_way1_out_2, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_935 = mux(_T_907, btb_bank0_rd_data_way1_out_3, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_936 = mux(_T_909, btb_bank0_rd_data_way1_out_4, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_937 = mux(_T_911, btb_bank0_rd_data_way1_out_5, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_938 = mux(_T_913, btb_bank0_rd_data_way1_out_6, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_939 = mux(_T_915, btb_bank0_rd_data_way1_out_7, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_940 = mux(_T_917, btb_bank0_rd_data_way1_out_8, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_941 = mux(_T_919, btb_bank0_rd_data_way1_out_9, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_942 = mux(_T_921, btb_bank0_rd_data_way1_out_10, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_943 = mux(_T_923, btb_bank0_rd_data_way1_out_11, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_944 = mux(_T_925, btb_bank0_rd_data_way1_out_12, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_945 = mux(_T_927, btb_bank0_rd_data_way1_out_13, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_946 = mux(_T_929, btb_bank0_rd_data_way1_out_14, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_947 = mux(_T_931, btb_bank0_rd_data_way1_out_15, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_948 = or(_T_932, _T_933) @[Mux.scala 27:72] + wire _T_897 : UInt @[Mux.scala 27:72] + _T_897 <= _T_896 @[Mux.scala 27:72] + btb_bank0_rd_data_way0_p1_f <= _T_897 @[ifu_bp_ctl.scala 455:31] + node _T_898 = eq(btb_rd_addr_p1_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 456:86] + node _T_899 = bits(_T_898, 0, 0) @[ifu_bp_ctl.scala 456:95] + node _T_900 = eq(btb_rd_addr_p1_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 456:86] + node _T_901 = bits(_T_900, 0, 0) @[ifu_bp_ctl.scala 456:95] + node _T_902 = eq(btb_rd_addr_p1_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 456:86] + node _T_903 = bits(_T_902, 0, 0) @[ifu_bp_ctl.scala 456:95] + node _T_904 = eq(btb_rd_addr_p1_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 456:86] + node _T_905 = bits(_T_904, 0, 0) @[ifu_bp_ctl.scala 456:95] + node _T_906 = eq(btb_rd_addr_p1_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 456:86] + node _T_907 = bits(_T_906, 0, 0) @[ifu_bp_ctl.scala 456:95] + node _T_908 = eq(btb_rd_addr_p1_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 456:86] + node _T_909 = bits(_T_908, 0, 0) @[ifu_bp_ctl.scala 456:95] + node _T_910 = eq(btb_rd_addr_p1_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 456:86] + node _T_911 = bits(_T_910, 0, 0) @[ifu_bp_ctl.scala 456:95] + node _T_912 = eq(btb_rd_addr_p1_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 456:86] + node _T_913 = bits(_T_912, 0, 0) @[ifu_bp_ctl.scala 456:95] + node _T_914 = eq(btb_rd_addr_p1_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 456:86] + node _T_915 = bits(_T_914, 0, 0) @[ifu_bp_ctl.scala 456:95] + node _T_916 = eq(btb_rd_addr_p1_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 456:86] + node _T_917 = bits(_T_916, 0, 0) @[ifu_bp_ctl.scala 456:95] + node _T_918 = eq(btb_rd_addr_p1_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 456:86] + node _T_919 = bits(_T_918, 0, 0) @[ifu_bp_ctl.scala 456:95] + node _T_920 = eq(btb_rd_addr_p1_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 456:86] + node _T_921 = bits(_T_920, 0, 0) @[ifu_bp_ctl.scala 456:95] + node _T_922 = eq(btb_rd_addr_p1_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 456:86] + node _T_923 = bits(_T_922, 0, 0) @[ifu_bp_ctl.scala 456:95] + node _T_924 = eq(btb_rd_addr_p1_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 456:86] + node _T_925 = bits(_T_924, 0, 0) @[ifu_bp_ctl.scala 456:95] + node _T_926 = eq(btb_rd_addr_p1_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 456:86] + node _T_927 = bits(_T_926, 0, 0) @[ifu_bp_ctl.scala 456:95] + node _T_928 = eq(btb_rd_addr_p1_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 456:86] + node _T_929 = bits(_T_928, 0, 0) @[ifu_bp_ctl.scala 456:95] + node _T_930 = mux(_T_899, btb_bank0_rd_data_way1_out_0, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_931 = mux(_T_901, btb_bank0_rd_data_way1_out_1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_932 = mux(_T_903, btb_bank0_rd_data_way1_out_2, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_933 = mux(_T_905, btb_bank0_rd_data_way1_out_3, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_934 = mux(_T_907, btb_bank0_rd_data_way1_out_4, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_935 = mux(_T_909, btb_bank0_rd_data_way1_out_5, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_936 = mux(_T_911, btb_bank0_rd_data_way1_out_6, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_937 = mux(_T_913, btb_bank0_rd_data_way1_out_7, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_938 = mux(_T_915, btb_bank0_rd_data_way1_out_8, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_939 = mux(_T_917, btb_bank0_rd_data_way1_out_9, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_940 = mux(_T_919, btb_bank0_rd_data_way1_out_10, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_941 = mux(_T_921, btb_bank0_rd_data_way1_out_11, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_942 = mux(_T_923, btb_bank0_rd_data_way1_out_12, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_943 = mux(_T_925, btb_bank0_rd_data_way1_out_13, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_944 = mux(_T_927, btb_bank0_rd_data_way1_out_14, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_945 = mux(_T_929, btb_bank0_rd_data_way1_out_15, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_946 = or(_T_930, _T_931) @[Mux.scala 27:72] + node _T_947 = or(_T_946, _T_932) @[Mux.scala 27:72] + node _T_948 = or(_T_947, _T_933) @[Mux.scala 27:72] node _T_949 = or(_T_948, _T_934) @[Mux.scala 27:72] node _T_950 = or(_T_949, _T_935) @[Mux.scala 27:72] node _T_951 = or(_T_950, _T_936) @[Mux.scala 27:72] @@ -2655,1190 +2656,1190 @@ circuit ifu_bp_ctl : node _T_958 = or(_T_957, _T_943) @[Mux.scala 27:72] node _T_959 = or(_T_958, _T_944) @[Mux.scala 27:72] node _T_960 = or(_T_959, _T_945) @[Mux.scala 27:72] - node _T_961 = or(_T_960, _T_946) @[Mux.scala 27:72] - node _T_962 = or(_T_961, _T_947) @[Mux.scala 27:72] - wire _T_963 : UInt @[Mux.scala 27:72] - _T_963 <= _T_962 @[Mux.scala 27:72] - btb_bank0_rd_data_way1_p1_f <= _T_963 @[ifu_bp_ctl.scala 450:31] - wire bht_bank_clken : UInt<1>[1][2] @[ifu_bp_ctl.scala 506:28] - wire bht_bank_clk : Clock[1][2] @[ifu_bp_ctl.scala 508:26] + wire _T_961 : UInt @[Mux.scala 27:72] + _T_961 <= _T_960 @[Mux.scala 27:72] + btb_bank0_rd_data_way1_p1_f <= _T_961 @[ifu_bp_ctl.scala 456:31] + wire bht_bank_clken : UInt<1>[1][2] @[ifu_bp_ctl.scala 513:28] + wire bht_bank_clk : Clock[1][2] @[ifu_bp_ctl.scala 515:26] inst rvclkhdr_41 of rvclkhdr_41 @[lib.scala 343:22] rvclkhdr_41.clock <= clock rvclkhdr_41.reset <= reset rvclkhdr_41.io.clk <= clock @[lib.scala 344:17] rvclkhdr_41.io.en <= bht_bank_clken[0][0] @[lib.scala 345:16] rvclkhdr_41.io.scan_mode <= UInt<1>("h00") @[lib.scala 346:23] - bht_bank_clk[0][0] <= rvclkhdr_41.io.l1clk @[ifu_bp_ctl.scala 510:84] + bht_bank_clk[0][0] <= rvclkhdr_41.io.l1clk @[ifu_bp_ctl.scala 517:84] inst rvclkhdr_42 of rvclkhdr_42 @[lib.scala 343:22] rvclkhdr_42.clock <= clock rvclkhdr_42.reset <= reset rvclkhdr_42.io.clk <= clock @[lib.scala 344:17] rvclkhdr_42.io.en <= bht_bank_clken[1][0] @[lib.scala 345:16] rvclkhdr_42.io.scan_mode <= UInt<1>("h00") @[lib.scala 346:23] - bht_bank_clk[1][0] <= rvclkhdr_42.io.l1clk @[ifu_bp_ctl.scala 510:84] - node _T_964 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 515:40] - node _T_965 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 515:60] - node _T_966 = eq(_T_965, UInt<1>("h00")) @[ifu_bp_ctl.scala 515:109] - node _T_967 = or(_T_966, UInt<1>("h01")) @[ifu_bp_ctl.scala 515:117] - node _T_968 = and(_T_964, _T_967) @[ifu_bp_ctl.scala 515:44] - node _T_969 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 516:40] - node _T_970 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 516:60] - node _T_971 = eq(_T_970, UInt<1>("h00")) @[ifu_bp_ctl.scala 516:109] - node _T_972 = or(_T_971, UInt<1>("h01")) @[ifu_bp_ctl.scala 516:117] - node _T_973 = and(_T_969, _T_972) @[ifu_bp_ctl.scala 516:44] - node _T_974 = or(_T_968, _T_973) @[ifu_bp_ctl.scala 515:142] - bht_bank_clken[0][0] <= _T_974 @[ifu_bp_ctl.scala 515:26] - node _T_975 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 515:40] - node _T_976 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 515:60] - node _T_977 = eq(_T_976, UInt<1>("h00")) @[ifu_bp_ctl.scala 515:109] - node _T_978 = or(_T_977, UInt<1>("h01")) @[ifu_bp_ctl.scala 515:117] - node _T_979 = and(_T_975, _T_978) @[ifu_bp_ctl.scala 515:44] - node _T_980 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 516:40] - node _T_981 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 516:60] - node _T_982 = eq(_T_981, UInt<1>("h00")) @[ifu_bp_ctl.scala 516:109] - node _T_983 = or(_T_982, UInt<1>("h01")) @[ifu_bp_ctl.scala 516:117] - node _T_984 = and(_T_980, _T_983) @[ifu_bp_ctl.scala 516:44] - node _T_985 = or(_T_979, _T_984) @[ifu_bp_ctl.scala 515:142] - bht_bank_clken[1][0] <= _T_985 @[ifu_bp_ctl.scala 515:26] - node _T_986 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 521:20] - node _T_987 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_988 = eq(_T_987, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:74] - node _T_989 = and(_T_986, _T_988) @[ifu_bp_ctl.scala 521:23] - node _T_990 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_991 = eq(_T_990, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_992 = and(_T_989, _T_991) @[ifu_bp_ctl.scala 521:81] - node _T_993 = or(_T_992, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_994 = bits(_T_993, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_0_0_0 = mux(_T_994, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_995 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 521:20] - node _T_996 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_997 = eq(_T_996, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:74] - node _T_998 = and(_T_995, _T_997) @[ifu_bp_ctl.scala 521:23] - node _T_999 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1000 = eq(_T_999, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1001 = and(_T_998, _T_1000) @[ifu_bp_ctl.scala 521:81] - node _T_1002 = or(_T_1001, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1003 = bits(_T_1002, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_0_0_1 = mux(_T_1003, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1004 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 521:20] - node _T_1005 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1006 = eq(_T_1005, UInt<2>("h02")) @[ifu_bp_ctl.scala 521:74] - node _T_1007 = and(_T_1004, _T_1006) @[ifu_bp_ctl.scala 521:23] - node _T_1008 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1009 = eq(_T_1008, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1010 = and(_T_1007, _T_1009) @[ifu_bp_ctl.scala 521:81] - node _T_1011 = or(_T_1010, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1012 = bits(_T_1011, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_0_0_2 = mux(_T_1012, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1013 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 521:20] - node _T_1014 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1015 = eq(_T_1014, UInt<2>("h03")) @[ifu_bp_ctl.scala 521:74] - node _T_1016 = and(_T_1013, _T_1015) @[ifu_bp_ctl.scala 521:23] - node _T_1017 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1018 = eq(_T_1017, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1019 = and(_T_1016, _T_1018) @[ifu_bp_ctl.scala 521:81] - node _T_1020 = or(_T_1019, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1021 = bits(_T_1020, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_0_0_3 = mux(_T_1021, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1022 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 521:20] - node _T_1023 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1024 = eq(_T_1023, UInt<3>("h04")) @[ifu_bp_ctl.scala 521:74] - node _T_1025 = and(_T_1022, _T_1024) @[ifu_bp_ctl.scala 521:23] - node _T_1026 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1028 = and(_T_1025, _T_1027) @[ifu_bp_ctl.scala 521:81] - node _T_1029 = or(_T_1028, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1030 = bits(_T_1029, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_0_0_4 = mux(_T_1030, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1031 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 521:20] - node _T_1032 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1033 = eq(_T_1032, UInt<3>("h05")) @[ifu_bp_ctl.scala 521:74] - node _T_1034 = and(_T_1031, _T_1033) @[ifu_bp_ctl.scala 521:23] - node _T_1035 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1036 = eq(_T_1035, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1037 = and(_T_1034, _T_1036) @[ifu_bp_ctl.scala 521:81] - node _T_1038 = or(_T_1037, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1039 = bits(_T_1038, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_0_0_5 = mux(_T_1039, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1040 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 521:20] - node _T_1041 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1042 = eq(_T_1041, UInt<3>("h06")) @[ifu_bp_ctl.scala 521:74] - node _T_1043 = and(_T_1040, _T_1042) @[ifu_bp_ctl.scala 521:23] - node _T_1044 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1045 = eq(_T_1044, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1046 = and(_T_1043, _T_1045) @[ifu_bp_ctl.scala 521:81] - node _T_1047 = or(_T_1046, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1048 = bits(_T_1047, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_0_0_6 = mux(_T_1048, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1049 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 521:20] - node _T_1050 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1051 = eq(_T_1050, UInt<3>("h07")) @[ifu_bp_ctl.scala 521:74] - node _T_1052 = and(_T_1049, _T_1051) @[ifu_bp_ctl.scala 521:23] - node _T_1053 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1054 = eq(_T_1053, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1055 = and(_T_1052, _T_1054) @[ifu_bp_ctl.scala 521:81] - node _T_1056 = or(_T_1055, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1057 = bits(_T_1056, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_0_0_7 = mux(_T_1057, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1058 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 521:20] - node _T_1059 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1060 = eq(_T_1059, UInt<4>("h08")) @[ifu_bp_ctl.scala 521:74] - node _T_1061 = and(_T_1058, _T_1060) @[ifu_bp_ctl.scala 521:23] - node _T_1062 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1063 = eq(_T_1062, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1064 = and(_T_1061, _T_1063) @[ifu_bp_ctl.scala 521:81] - node _T_1065 = or(_T_1064, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1066 = bits(_T_1065, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_0_0_8 = mux(_T_1066, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1067 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 521:20] - node _T_1068 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1069 = eq(_T_1068, UInt<4>("h09")) @[ifu_bp_ctl.scala 521:74] - node _T_1070 = and(_T_1067, _T_1069) @[ifu_bp_ctl.scala 521:23] - node _T_1071 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1072 = eq(_T_1071, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1073 = and(_T_1070, _T_1072) @[ifu_bp_ctl.scala 521:81] - node _T_1074 = or(_T_1073, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1075 = bits(_T_1074, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_0_0_9 = mux(_T_1075, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1076 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 521:20] - node _T_1077 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1078 = eq(_T_1077, UInt<4>("h0a")) @[ifu_bp_ctl.scala 521:74] - node _T_1079 = and(_T_1076, _T_1078) @[ifu_bp_ctl.scala 521:23] - node _T_1080 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1081 = eq(_T_1080, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1082 = and(_T_1079, _T_1081) @[ifu_bp_ctl.scala 521:81] - node _T_1083 = or(_T_1082, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1084 = bits(_T_1083, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_0_0_10 = mux(_T_1084, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1085 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 521:20] - node _T_1086 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1087 = eq(_T_1086, UInt<4>("h0b")) @[ifu_bp_ctl.scala 521:74] - node _T_1088 = and(_T_1085, _T_1087) @[ifu_bp_ctl.scala 521:23] - node _T_1089 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1090 = eq(_T_1089, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1091 = and(_T_1088, _T_1090) @[ifu_bp_ctl.scala 521:81] - node _T_1092 = or(_T_1091, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1093 = bits(_T_1092, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_0_0_11 = mux(_T_1093, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1094 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 521:20] - node _T_1095 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1096 = eq(_T_1095, UInt<4>("h0c")) @[ifu_bp_ctl.scala 521:74] - node _T_1097 = and(_T_1094, _T_1096) @[ifu_bp_ctl.scala 521:23] - node _T_1098 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1099 = eq(_T_1098, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1100 = and(_T_1097, _T_1099) @[ifu_bp_ctl.scala 521:81] - node _T_1101 = or(_T_1100, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1102 = bits(_T_1101, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_0_0_12 = mux(_T_1102, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1103 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 521:20] - node _T_1104 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1105 = eq(_T_1104, UInt<4>("h0d")) @[ifu_bp_ctl.scala 521:74] - node _T_1106 = and(_T_1103, _T_1105) @[ifu_bp_ctl.scala 521:23] - node _T_1107 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1108 = eq(_T_1107, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1109 = and(_T_1106, _T_1108) @[ifu_bp_ctl.scala 521:81] - node _T_1110 = or(_T_1109, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1111 = bits(_T_1110, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_0_0_13 = mux(_T_1111, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1112 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 521:20] - node _T_1113 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1114 = eq(_T_1113, UInt<4>("h0e")) @[ifu_bp_ctl.scala 521:74] - node _T_1115 = and(_T_1112, _T_1114) @[ifu_bp_ctl.scala 521:23] - node _T_1116 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1117 = eq(_T_1116, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1118 = and(_T_1115, _T_1117) @[ifu_bp_ctl.scala 521:81] - node _T_1119 = or(_T_1118, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1120 = bits(_T_1119, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_0_0_14 = mux(_T_1120, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1121 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 521:20] - node _T_1122 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1123 = eq(_T_1122, UInt<4>("h0f")) @[ifu_bp_ctl.scala 521:74] - node _T_1124 = and(_T_1121, _T_1123) @[ifu_bp_ctl.scala 521:23] - node _T_1125 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1126 = eq(_T_1125, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1127 = and(_T_1124, _T_1126) @[ifu_bp_ctl.scala 521:81] - node _T_1128 = or(_T_1127, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1129 = bits(_T_1128, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_0_0_15 = mux(_T_1129, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1130 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 521:20] - node _T_1131 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1132 = eq(_T_1131, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:74] - node _T_1133 = and(_T_1130, _T_1132) @[ifu_bp_ctl.scala 521:23] - node _T_1134 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1135 = eq(_T_1134, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1136 = and(_T_1133, _T_1135) @[ifu_bp_ctl.scala 521:81] - node _T_1137 = or(_T_1136, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1138 = bits(_T_1137, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_1_0_0 = mux(_T_1138, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1139 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 521:20] - node _T_1140 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1141 = eq(_T_1140, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:74] - node _T_1142 = and(_T_1139, _T_1141) @[ifu_bp_ctl.scala 521:23] - node _T_1143 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1144 = eq(_T_1143, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1145 = and(_T_1142, _T_1144) @[ifu_bp_ctl.scala 521:81] - node _T_1146 = or(_T_1145, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1147 = bits(_T_1146, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_1_0_1 = mux(_T_1147, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1148 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 521:20] - node _T_1149 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1150 = eq(_T_1149, UInt<2>("h02")) @[ifu_bp_ctl.scala 521:74] - node _T_1151 = and(_T_1148, _T_1150) @[ifu_bp_ctl.scala 521:23] - node _T_1152 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1153 = eq(_T_1152, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1154 = and(_T_1151, _T_1153) @[ifu_bp_ctl.scala 521:81] - node _T_1155 = or(_T_1154, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1156 = bits(_T_1155, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_1_0_2 = mux(_T_1156, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1157 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 521:20] - node _T_1158 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1159 = eq(_T_1158, UInt<2>("h03")) @[ifu_bp_ctl.scala 521:74] - node _T_1160 = and(_T_1157, _T_1159) @[ifu_bp_ctl.scala 521:23] - node _T_1161 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1162 = eq(_T_1161, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1163 = and(_T_1160, _T_1162) @[ifu_bp_ctl.scala 521:81] - node _T_1164 = or(_T_1163, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1165 = bits(_T_1164, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_1_0_3 = mux(_T_1165, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1166 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 521:20] - node _T_1167 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1168 = eq(_T_1167, UInt<3>("h04")) @[ifu_bp_ctl.scala 521:74] - node _T_1169 = and(_T_1166, _T_1168) @[ifu_bp_ctl.scala 521:23] - node _T_1170 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1171 = eq(_T_1170, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1172 = and(_T_1169, _T_1171) @[ifu_bp_ctl.scala 521:81] - node _T_1173 = or(_T_1172, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1174 = bits(_T_1173, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_1_0_4 = mux(_T_1174, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1175 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 521:20] - node _T_1176 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1177 = eq(_T_1176, UInt<3>("h05")) @[ifu_bp_ctl.scala 521:74] - node _T_1178 = and(_T_1175, _T_1177) @[ifu_bp_ctl.scala 521:23] - node _T_1179 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1180 = eq(_T_1179, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1181 = and(_T_1178, _T_1180) @[ifu_bp_ctl.scala 521:81] - node _T_1182 = or(_T_1181, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1183 = bits(_T_1182, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_1_0_5 = mux(_T_1183, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1184 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 521:20] - node _T_1185 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1186 = eq(_T_1185, UInt<3>("h06")) @[ifu_bp_ctl.scala 521:74] - node _T_1187 = and(_T_1184, _T_1186) @[ifu_bp_ctl.scala 521:23] - node _T_1188 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1190 = and(_T_1187, _T_1189) @[ifu_bp_ctl.scala 521:81] - node _T_1191 = or(_T_1190, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1192 = bits(_T_1191, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_1_0_6 = mux(_T_1192, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1193 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 521:20] - node _T_1194 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1195 = eq(_T_1194, UInt<3>("h07")) @[ifu_bp_ctl.scala 521:74] - node _T_1196 = and(_T_1193, _T_1195) @[ifu_bp_ctl.scala 521:23] - node _T_1197 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1198 = eq(_T_1197, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1199 = and(_T_1196, _T_1198) @[ifu_bp_ctl.scala 521:81] - node _T_1200 = or(_T_1199, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1201 = bits(_T_1200, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_1_0_7 = mux(_T_1201, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1202 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 521:20] - node _T_1203 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1204 = eq(_T_1203, UInt<4>("h08")) @[ifu_bp_ctl.scala 521:74] - node _T_1205 = and(_T_1202, _T_1204) @[ifu_bp_ctl.scala 521:23] - node _T_1206 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1208 = and(_T_1205, _T_1207) @[ifu_bp_ctl.scala 521:81] - node _T_1209 = or(_T_1208, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1210 = bits(_T_1209, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_1_0_8 = mux(_T_1210, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1211 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 521:20] - node _T_1212 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1213 = eq(_T_1212, UInt<4>("h09")) @[ifu_bp_ctl.scala 521:74] - node _T_1214 = and(_T_1211, _T_1213) @[ifu_bp_ctl.scala 521:23] - node _T_1215 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1217 = and(_T_1214, _T_1216) @[ifu_bp_ctl.scala 521:81] - node _T_1218 = or(_T_1217, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1219 = bits(_T_1218, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_1_0_9 = mux(_T_1219, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1220 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 521:20] - node _T_1221 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1222 = eq(_T_1221, UInt<4>("h0a")) @[ifu_bp_ctl.scala 521:74] - node _T_1223 = and(_T_1220, _T_1222) @[ifu_bp_ctl.scala 521:23] - node _T_1224 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1225 = eq(_T_1224, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1226 = and(_T_1223, _T_1225) @[ifu_bp_ctl.scala 521:81] - node _T_1227 = or(_T_1226, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1228 = bits(_T_1227, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_1_0_10 = mux(_T_1228, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1229 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 521:20] - node _T_1230 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1231 = eq(_T_1230, UInt<4>("h0b")) @[ifu_bp_ctl.scala 521:74] - node _T_1232 = and(_T_1229, _T_1231) @[ifu_bp_ctl.scala 521:23] - node _T_1233 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1234 = eq(_T_1233, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1235 = and(_T_1232, _T_1234) @[ifu_bp_ctl.scala 521:81] - node _T_1236 = or(_T_1235, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1237 = bits(_T_1236, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_1_0_11 = mux(_T_1237, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1238 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 521:20] - node _T_1239 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1240 = eq(_T_1239, UInt<4>("h0c")) @[ifu_bp_ctl.scala 521:74] - node _T_1241 = and(_T_1238, _T_1240) @[ifu_bp_ctl.scala 521:23] - node _T_1242 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1243 = eq(_T_1242, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1244 = and(_T_1241, _T_1243) @[ifu_bp_ctl.scala 521:81] - node _T_1245 = or(_T_1244, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1246 = bits(_T_1245, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_1_0_12 = mux(_T_1246, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1247 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 521:20] - node _T_1248 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1249 = eq(_T_1248, UInt<4>("h0d")) @[ifu_bp_ctl.scala 521:74] - node _T_1250 = and(_T_1247, _T_1249) @[ifu_bp_ctl.scala 521:23] - node _T_1251 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1252 = eq(_T_1251, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1253 = and(_T_1250, _T_1252) @[ifu_bp_ctl.scala 521:81] - node _T_1254 = or(_T_1253, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1255 = bits(_T_1254, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_1_0_13 = mux(_T_1255, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1256 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 521:20] - node _T_1257 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1258 = eq(_T_1257, UInt<4>("h0e")) @[ifu_bp_ctl.scala 521:74] - node _T_1259 = and(_T_1256, _T_1258) @[ifu_bp_ctl.scala 521:23] - node _T_1260 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1261 = eq(_T_1260, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1262 = and(_T_1259, _T_1261) @[ifu_bp_ctl.scala 521:81] - node _T_1263 = or(_T_1262, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1264 = bits(_T_1263, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_1_0_14 = mux(_T_1264, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - node _T_1265 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 521:20] - node _T_1266 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:37] - node _T_1267 = eq(_T_1266, UInt<4>("h0f")) @[ifu_bp_ctl.scala 521:74] - node _T_1268 = and(_T_1265, _T_1267) @[ifu_bp_ctl.scala 521:23] - node _T_1269 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 521:95] - node _T_1270 = eq(_T_1269, UInt<1>("h00")) @[ifu_bp_ctl.scala 521:154] - node _T_1271 = and(_T_1268, _T_1270) @[ifu_bp_ctl.scala 521:81] - node _T_1272 = or(_T_1271, UInt<1>("h01")) @[ifu_bp_ctl.scala 521:161] - node _T_1273 = bits(_T_1272, 0, 0) @[ifu_bp_ctl.scala 521:183] - node bht_bank_wr_data_1_0_15 = mux(_T_1273, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 521:8] - wire bht_bank_sel : UInt<1>[16][1][2] @[ifu_bp_ctl.scala 523:26] - node _T_1274 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 529:41] - node _T_1275 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1276 = eq(_T_1275, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:97] - node _T_1277 = and(_T_1274, _T_1276) @[ifu_bp_ctl.scala 529:45] - node _T_1278 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1279 = eq(_T_1278, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1280 = or(_T_1279, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1281 = and(_T_1277, _T_1280) @[ifu_bp_ctl.scala 529:110] - node _T_1282 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 530:18] - node _T_1283 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:74] - node _T_1285 = and(_T_1282, _T_1284) @[ifu_bp_ctl.scala 530:22] - node _T_1286 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1287 = eq(_T_1286, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1288 = or(_T_1287, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1289 = and(_T_1285, _T_1288) @[ifu_bp_ctl.scala 530:87] - node _T_1290 = or(_T_1281, _T_1289) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[0][0][0] <= _T_1290 @[ifu_bp_ctl.scala 529:27] - node _T_1291 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 529:41] - node _T_1292 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1293 = eq(_T_1292, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:97] - node _T_1294 = and(_T_1291, _T_1293) @[ifu_bp_ctl.scala 529:45] - node _T_1295 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1296 = eq(_T_1295, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1297 = or(_T_1296, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1298 = and(_T_1294, _T_1297) @[ifu_bp_ctl.scala 529:110] - node _T_1299 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 530:18] - node _T_1300 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1301 = eq(_T_1300, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:74] - node _T_1302 = and(_T_1299, _T_1301) @[ifu_bp_ctl.scala 530:22] - node _T_1303 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1304 = eq(_T_1303, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1305 = or(_T_1304, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1306 = and(_T_1302, _T_1305) @[ifu_bp_ctl.scala 530:87] - node _T_1307 = or(_T_1298, _T_1306) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[0][0][1] <= _T_1307 @[ifu_bp_ctl.scala 529:27] - node _T_1308 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 529:41] - node _T_1309 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1310 = eq(_T_1309, UInt<2>("h02")) @[ifu_bp_ctl.scala 529:97] - node _T_1311 = and(_T_1308, _T_1310) @[ifu_bp_ctl.scala 529:45] - node _T_1312 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1313 = eq(_T_1312, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1314 = or(_T_1313, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1315 = and(_T_1311, _T_1314) @[ifu_bp_ctl.scala 529:110] - node _T_1316 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 530:18] - node _T_1317 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1318 = eq(_T_1317, UInt<2>("h02")) @[ifu_bp_ctl.scala 530:74] - node _T_1319 = and(_T_1316, _T_1318) @[ifu_bp_ctl.scala 530:22] - node _T_1320 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1321 = eq(_T_1320, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1322 = or(_T_1321, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1323 = and(_T_1319, _T_1322) @[ifu_bp_ctl.scala 530:87] - node _T_1324 = or(_T_1315, _T_1323) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[0][0][2] <= _T_1324 @[ifu_bp_ctl.scala 529:27] - node _T_1325 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 529:41] - node _T_1326 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1327 = eq(_T_1326, UInt<2>("h03")) @[ifu_bp_ctl.scala 529:97] - node _T_1328 = and(_T_1325, _T_1327) @[ifu_bp_ctl.scala 529:45] - node _T_1329 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1331 = or(_T_1330, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1332 = and(_T_1328, _T_1331) @[ifu_bp_ctl.scala 529:110] - node _T_1333 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 530:18] - node _T_1334 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1335 = eq(_T_1334, UInt<2>("h03")) @[ifu_bp_ctl.scala 530:74] - node _T_1336 = and(_T_1333, _T_1335) @[ifu_bp_ctl.scala 530:22] - node _T_1337 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1338 = eq(_T_1337, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1339 = or(_T_1338, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1340 = and(_T_1336, _T_1339) @[ifu_bp_ctl.scala 530:87] - node _T_1341 = or(_T_1332, _T_1340) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[0][0][3] <= _T_1341 @[ifu_bp_ctl.scala 529:27] - node _T_1342 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 529:41] - node _T_1343 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1344 = eq(_T_1343, UInt<3>("h04")) @[ifu_bp_ctl.scala 529:97] - node _T_1345 = and(_T_1342, _T_1344) @[ifu_bp_ctl.scala 529:45] - node _T_1346 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1347 = eq(_T_1346, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1348 = or(_T_1347, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1349 = and(_T_1345, _T_1348) @[ifu_bp_ctl.scala 529:110] - node _T_1350 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 530:18] - node _T_1351 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1352 = eq(_T_1351, UInt<3>("h04")) @[ifu_bp_ctl.scala 530:74] - node _T_1353 = and(_T_1350, _T_1352) @[ifu_bp_ctl.scala 530:22] - node _T_1354 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1355 = eq(_T_1354, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1356 = or(_T_1355, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1357 = and(_T_1353, _T_1356) @[ifu_bp_ctl.scala 530:87] - node _T_1358 = or(_T_1349, _T_1357) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[0][0][4] <= _T_1358 @[ifu_bp_ctl.scala 529:27] - node _T_1359 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 529:41] - node _T_1360 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1361 = eq(_T_1360, UInt<3>("h05")) @[ifu_bp_ctl.scala 529:97] - node _T_1362 = and(_T_1359, _T_1361) @[ifu_bp_ctl.scala 529:45] - node _T_1363 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1365 = or(_T_1364, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1366 = and(_T_1362, _T_1365) @[ifu_bp_ctl.scala 529:110] - node _T_1367 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 530:18] - node _T_1368 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1369 = eq(_T_1368, UInt<3>("h05")) @[ifu_bp_ctl.scala 530:74] - node _T_1370 = and(_T_1367, _T_1369) @[ifu_bp_ctl.scala 530:22] - node _T_1371 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1372 = eq(_T_1371, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1373 = or(_T_1372, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1374 = and(_T_1370, _T_1373) @[ifu_bp_ctl.scala 530:87] - node _T_1375 = or(_T_1366, _T_1374) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[0][0][5] <= _T_1375 @[ifu_bp_ctl.scala 529:27] - node _T_1376 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 529:41] - node _T_1377 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1378 = eq(_T_1377, UInt<3>("h06")) @[ifu_bp_ctl.scala 529:97] - node _T_1379 = and(_T_1376, _T_1378) @[ifu_bp_ctl.scala 529:45] - node _T_1380 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1381 = eq(_T_1380, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1382 = or(_T_1381, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1383 = and(_T_1379, _T_1382) @[ifu_bp_ctl.scala 529:110] - node _T_1384 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 530:18] - node _T_1385 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1386 = eq(_T_1385, UInt<3>("h06")) @[ifu_bp_ctl.scala 530:74] - node _T_1387 = and(_T_1384, _T_1386) @[ifu_bp_ctl.scala 530:22] - node _T_1388 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1389 = eq(_T_1388, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1390 = or(_T_1389, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1391 = and(_T_1387, _T_1390) @[ifu_bp_ctl.scala 530:87] - node _T_1392 = or(_T_1383, _T_1391) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[0][0][6] <= _T_1392 @[ifu_bp_ctl.scala 529:27] - node _T_1393 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 529:41] - node _T_1394 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1395 = eq(_T_1394, UInt<3>("h07")) @[ifu_bp_ctl.scala 529:97] - node _T_1396 = and(_T_1393, _T_1395) @[ifu_bp_ctl.scala 529:45] - node _T_1397 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1399 = or(_T_1398, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1400 = and(_T_1396, _T_1399) @[ifu_bp_ctl.scala 529:110] - node _T_1401 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 530:18] - node _T_1402 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1403 = eq(_T_1402, UInt<3>("h07")) @[ifu_bp_ctl.scala 530:74] - node _T_1404 = and(_T_1401, _T_1403) @[ifu_bp_ctl.scala 530:22] - node _T_1405 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1406 = eq(_T_1405, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1407 = or(_T_1406, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1408 = and(_T_1404, _T_1407) @[ifu_bp_ctl.scala 530:87] - node _T_1409 = or(_T_1400, _T_1408) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[0][0][7] <= _T_1409 @[ifu_bp_ctl.scala 529:27] - node _T_1410 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 529:41] - node _T_1411 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1412 = eq(_T_1411, UInt<4>("h08")) @[ifu_bp_ctl.scala 529:97] - node _T_1413 = and(_T_1410, _T_1412) @[ifu_bp_ctl.scala 529:45] - node _T_1414 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1415 = eq(_T_1414, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1416 = or(_T_1415, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1417 = and(_T_1413, _T_1416) @[ifu_bp_ctl.scala 529:110] - node _T_1418 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 530:18] - node _T_1419 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1420 = eq(_T_1419, UInt<4>("h08")) @[ifu_bp_ctl.scala 530:74] - node _T_1421 = and(_T_1418, _T_1420) @[ifu_bp_ctl.scala 530:22] - node _T_1422 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1423 = eq(_T_1422, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1424 = or(_T_1423, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1425 = and(_T_1421, _T_1424) @[ifu_bp_ctl.scala 530:87] - node _T_1426 = or(_T_1417, _T_1425) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[0][0][8] <= _T_1426 @[ifu_bp_ctl.scala 529:27] - node _T_1427 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 529:41] - node _T_1428 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1429 = eq(_T_1428, UInt<4>("h09")) @[ifu_bp_ctl.scala 529:97] - node _T_1430 = and(_T_1427, _T_1429) @[ifu_bp_ctl.scala 529:45] - node _T_1431 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1432 = eq(_T_1431, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1433 = or(_T_1432, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1434 = and(_T_1430, _T_1433) @[ifu_bp_ctl.scala 529:110] - node _T_1435 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 530:18] - node _T_1436 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1437 = eq(_T_1436, UInt<4>("h09")) @[ifu_bp_ctl.scala 530:74] - node _T_1438 = and(_T_1435, _T_1437) @[ifu_bp_ctl.scala 530:22] - node _T_1439 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1440 = eq(_T_1439, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1441 = or(_T_1440, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1442 = and(_T_1438, _T_1441) @[ifu_bp_ctl.scala 530:87] - node _T_1443 = or(_T_1434, _T_1442) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[0][0][9] <= _T_1443 @[ifu_bp_ctl.scala 529:27] - node _T_1444 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 529:41] - node _T_1445 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1446 = eq(_T_1445, UInt<4>("h0a")) @[ifu_bp_ctl.scala 529:97] - node _T_1447 = and(_T_1444, _T_1446) @[ifu_bp_ctl.scala 529:45] - node _T_1448 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1449 = eq(_T_1448, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1450 = or(_T_1449, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1451 = and(_T_1447, _T_1450) @[ifu_bp_ctl.scala 529:110] - node _T_1452 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 530:18] - node _T_1453 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1454 = eq(_T_1453, UInt<4>("h0a")) @[ifu_bp_ctl.scala 530:74] - node _T_1455 = and(_T_1452, _T_1454) @[ifu_bp_ctl.scala 530:22] - node _T_1456 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1457 = eq(_T_1456, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1458 = or(_T_1457, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1459 = and(_T_1455, _T_1458) @[ifu_bp_ctl.scala 530:87] - node _T_1460 = or(_T_1451, _T_1459) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[0][0][10] <= _T_1460 @[ifu_bp_ctl.scala 529:27] - node _T_1461 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 529:41] - node _T_1462 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1463 = eq(_T_1462, UInt<4>("h0b")) @[ifu_bp_ctl.scala 529:97] - node _T_1464 = and(_T_1461, _T_1463) @[ifu_bp_ctl.scala 529:45] - node _T_1465 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1467 = or(_T_1466, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1468 = and(_T_1464, _T_1467) @[ifu_bp_ctl.scala 529:110] - node _T_1469 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 530:18] - node _T_1470 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1471 = eq(_T_1470, UInt<4>("h0b")) @[ifu_bp_ctl.scala 530:74] - node _T_1472 = and(_T_1469, _T_1471) @[ifu_bp_ctl.scala 530:22] - node _T_1473 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1474 = eq(_T_1473, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1475 = or(_T_1474, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1476 = and(_T_1472, _T_1475) @[ifu_bp_ctl.scala 530:87] - node _T_1477 = or(_T_1468, _T_1476) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[0][0][11] <= _T_1477 @[ifu_bp_ctl.scala 529:27] - node _T_1478 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 529:41] - node _T_1479 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1480 = eq(_T_1479, UInt<4>("h0c")) @[ifu_bp_ctl.scala 529:97] - node _T_1481 = and(_T_1478, _T_1480) @[ifu_bp_ctl.scala 529:45] - node _T_1482 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1483 = eq(_T_1482, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1484 = or(_T_1483, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1485 = and(_T_1481, _T_1484) @[ifu_bp_ctl.scala 529:110] - node _T_1486 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 530:18] - node _T_1487 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1488 = eq(_T_1487, UInt<4>("h0c")) @[ifu_bp_ctl.scala 530:74] - node _T_1489 = and(_T_1486, _T_1488) @[ifu_bp_ctl.scala 530:22] - node _T_1490 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1492 = or(_T_1491, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1493 = and(_T_1489, _T_1492) @[ifu_bp_ctl.scala 530:87] - node _T_1494 = or(_T_1485, _T_1493) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[0][0][12] <= _T_1494 @[ifu_bp_ctl.scala 529:27] - node _T_1495 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 529:41] - node _T_1496 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1497 = eq(_T_1496, UInt<4>("h0d")) @[ifu_bp_ctl.scala 529:97] - node _T_1498 = and(_T_1495, _T_1497) @[ifu_bp_ctl.scala 529:45] - node _T_1499 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1500 = eq(_T_1499, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1501 = or(_T_1500, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1502 = and(_T_1498, _T_1501) @[ifu_bp_ctl.scala 529:110] - node _T_1503 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 530:18] - node _T_1504 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1505 = eq(_T_1504, UInt<4>("h0d")) @[ifu_bp_ctl.scala 530:74] - node _T_1506 = and(_T_1503, _T_1505) @[ifu_bp_ctl.scala 530:22] - node _T_1507 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1508 = eq(_T_1507, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1509 = or(_T_1508, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1510 = and(_T_1506, _T_1509) @[ifu_bp_ctl.scala 530:87] - node _T_1511 = or(_T_1502, _T_1510) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[0][0][13] <= _T_1511 @[ifu_bp_ctl.scala 529:27] - node _T_1512 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 529:41] - node _T_1513 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1514 = eq(_T_1513, UInt<4>("h0e")) @[ifu_bp_ctl.scala 529:97] - node _T_1515 = and(_T_1512, _T_1514) @[ifu_bp_ctl.scala 529:45] - node _T_1516 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1518 = or(_T_1517, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1519 = and(_T_1515, _T_1518) @[ifu_bp_ctl.scala 529:110] - node _T_1520 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 530:18] - node _T_1521 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1522 = eq(_T_1521, UInt<4>("h0e")) @[ifu_bp_ctl.scala 530:74] - node _T_1523 = and(_T_1520, _T_1522) @[ifu_bp_ctl.scala 530:22] - node _T_1524 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1525 = eq(_T_1524, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1526 = or(_T_1525, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1527 = and(_T_1523, _T_1526) @[ifu_bp_ctl.scala 530:87] - node _T_1528 = or(_T_1519, _T_1527) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[0][0][14] <= _T_1528 @[ifu_bp_ctl.scala 529:27] - node _T_1529 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 529:41] - node _T_1530 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1531 = eq(_T_1530, UInt<4>("h0f")) @[ifu_bp_ctl.scala 529:97] - node _T_1532 = and(_T_1529, _T_1531) @[ifu_bp_ctl.scala 529:45] - node _T_1533 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1534 = eq(_T_1533, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1535 = or(_T_1534, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1536 = and(_T_1532, _T_1535) @[ifu_bp_ctl.scala 529:110] - node _T_1537 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 530:18] - node _T_1538 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1539 = eq(_T_1538, UInt<4>("h0f")) @[ifu_bp_ctl.scala 530:74] - node _T_1540 = and(_T_1537, _T_1539) @[ifu_bp_ctl.scala 530:22] - node _T_1541 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1542 = eq(_T_1541, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1543 = or(_T_1542, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1544 = and(_T_1540, _T_1543) @[ifu_bp_ctl.scala 530:87] - node _T_1545 = or(_T_1536, _T_1544) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[0][0][15] <= _T_1545 @[ifu_bp_ctl.scala 529:27] - node _T_1546 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 529:41] - node _T_1547 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1548 = eq(_T_1547, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:97] - node _T_1549 = and(_T_1546, _T_1548) @[ifu_bp_ctl.scala 529:45] - node _T_1550 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1551 = eq(_T_1550, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1552 = or(_T_1551, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1553 = and(_T_1549, _T_1552) @[ifu_bp_ctl.scala 529:110] - node _T_1554 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 530:18] - node _T_1555 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1556 = eq(_T_1555, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:74] - node _T_1557 = and(_T_1554, _T_1556) @[ifu_bp_ctl.scala 530:22] - node _T_1558 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1559 = eq(_T_1558, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1560 = or(_T_1559, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1561 = and(_T_1557, _T_1560) @[ifu_bp_ctl.scala 530:87] - node _T_1562 = or(_T_1553, _T_1561) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[1][0][0] <= _T_1562 @[ifu_bp_ctl.scala 529:27] - node _T_1563 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 529:41] - node _T_1564 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1565 = eq(_T_1564, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:97] - node _T_1566 = and(_T_1563, _T_1565) @[ifu_bp_ctl.scala 529:45] - node _T_1567 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1568 = eq(_T_1567, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1569 = or(_T_1568, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1570 = and(_T_1566, _T_1569) @[ifu_bp_ctl.scala 529:110] - node _T_1571 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 530:18] - node _T_1572 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1573 = eq(_T_1572, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:74] - node _T_1574 = and(_T_1571, _T_1573) @[ifu_bp_ctl.scala 530:22] - node _T_1575 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1576 = eq(_T_1575, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1577 = or(_T_1576, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1578 = and(_T_1574, _T_1577) @[ifu_bp_ctl.scala 530:87] - node _T_1579 = or(_T_1570, _T_1578) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[1][0][1] <= _T_1579 @[ifu_bp_ctl.scala 529:27] - node _T_1580 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 529:41] - node _T_1581 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1582 = eq(_T_1581, UInt<2>("h02")) @[ifu_bp_ctl.scala 529:97] - node _T_1583 = and(_T_1580, _T_1582) @[ifu_bp_ctl.scala 529:45] - node _T_1584 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1585 = eq(_T_1584, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1586 = or(_T_1585, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1587 = and(_T_1583, _T_1586) @[ifu_bp_ctl.scala 529:110] - node _T_1588 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 530:18] - node _T_1589 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1590 = eq(_T_1589, UInt<2>("h02")) @[ifu_bp_ctl.scala 530:74] - node _T_1591 = and(_T_1588, _T_1590) @[ifu_bp_ctl.scala 530:22] - node _T_1592 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1593 = eq(_T_1592, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1594 = or(_T_1593, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1595 = and(_T_1591, _T_1594) @[ifu_bp_ctl.scala 530:87] - node _T_1596 = or(_T_1587, _T_1595) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[1][0][2] <= _T_1596 @[ifu_bp_ctl.scala 529:27] - node _T_1597 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 529:41] - node _T_1598 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1599 = eq(_T_1598, UInt<2>("h03")) @[ifu_bp_ctl.scala 529:97] - node _T_1600 = and(_T_1597, _T_1599) @[ifu_bp_ctl.scala 529:45] - node _T_1601 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1602 = eq(_T_1601, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1603 = or(_T_1602, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1604 = and(_T_1600, _T_1603) @[ifu_bp_ctl.scala 529:110] - node _T_1605 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 530:18] - node _T_1606 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1607 = eq(_T_1606, UInt<2>("h03")) @[ifu_bp_ctl.scala 530:74] - node _T_1608 = and(_T_1605, _T_1607) @[ifu_bp_ctl.scala 530:22] - node _T_1609 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1610 = eq(_T_1609, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1611 = or(_T_1610, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1612 = and(_T_1608, _T_1611) @[ifu_bp_ctl.scala 530:87] - node _T_1613 = or(_T_1604, _T_1612) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[1][0][3] <= _T_1613 @[ifu_bp_ctl.scala 529:27] - node _T_1614 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 529:41] - node _T_1615 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1616 = eq(_T_1615, UInt<3>("h04")) @[ifu_bp_ctl.scala 529:97] - node _T_1617 = and(_T_1614, _T_1616) @[ifu_bp_ctl.scala 529:45] - node _T_1618 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1619 = eq(_T_1618, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1620 = or(_T_1619, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1621 = and(_T_1617, _T_1620) @[ifu_bp_ctl.scala 529:110] - node _T_1622 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 530:18] - node _T_1623 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1624 = eq(_T_1623, UInt<3>("h04")) @[ifu_bp_ctl.scala 530:74] - node _T_1625 = and(_T_1622, _T_1624) @[ifu_bp_ctl.scala 530:22] - node _T_1626 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1627 = eq(_T_1626, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1628 = or(_T_1627, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1629 = and(_T_1625, _T_1628) @[ifu_bp_ctl.scala 530:87] - node _T_1630 = or(_T_1621, _T_1629) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[1][0][4] <= _T_1630 @[ifu_bp_ctl.scala 529:27] - node _T_1631 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 529:41] - node _T_1632 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1633 = eq(_T_1632, UInt<3>("h05")) @[ifu_bp_ctl.scala 529:97] - node _T_1634 = and(_T_1631, _T_1633) @[ifu_bp_ctl.scala 529:45] - node _T_1635 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1636 = eq(_T_1635, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1637 = or(_T_1636, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1638 = and(_T_1634, _T_1637) @[ifu_bp_ctl.scala 529:110] - node _T_1639 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 530:18] - node _T_1640 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1641 = eq(_T_1640, UInt<3>("h05")) @[ifu_bp_ctl.scala 530:74] - node _T_1642 = and(_T_1639, _T_1641) @[ifu_bp_ctl.scala 530:22] - node _T_1643 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1644 = eq(_T_1643, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1645 = or(_T_1644, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1646 = and(_T_1642, _T_1645) @[ifu_bp_ctl.scala 530:87] - node _T_1647 = or(_T_1638, _T_1646) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[1][0][5] <= _T_1647 @[ifu_bp_ctl.scala 529:27] - node _T_1648 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 529:41] - node _T_1649 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1650 = eq(_T_1649, UInt<3>("h06")) @[ifu_bp_ctl.scala 529:97] - node _T_1651 = and(_T_1648, _T_1650) @[ifu_bp_ctl.scala 529:45] - node _T_1652 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1653 = eq(_T_1652, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1654 = or(_T_1653, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1655 = and(_T_1651, _T_1654) @[ifu_bp_ctl.scala 529:110] - node _T_1656 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 530:18] - node _T_1657 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1658 = eq(_T_1657, UInt<3>("h06")) @[ifu_bp_ctl.scala 530:74] - node _T_1659 = and(_T_1656, _T_1658) @[ifu_bp_ctl.scala 530:22] - node _T_1660 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1661 = eq(_T_1660, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1662 = or(_T_1661, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1663 = and(_T_1659, _T_1662) @[ifu_bp_ctl.scala 530:87] - node _T_1664 = or(_T_1655, _T_1663) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[1][0][6] <= _T_1664 @[ifu_bp_ctl.scala 529:27] - node _T_1665 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 529:41] - node _T_1666 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1667 = eq(_T_1666, UInt<3>("h07")) @[ifu_bp_ctl.scala 529:97] - node _T_1668 = and(_T_1665, _T_1667) @[ifu_bp_ctl.scala 529:45] - node _T_1669 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1670 = eq(_T_1669, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1671 = or(_T_1670, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1672 = and(_T_1668, _T_1671) @[ifu_bp_ctl.scala 529:110] - node _T_1673 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 530:18] - node _T_1674 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1675 = eq(_T_1674, UInt<3>("h07")) @[ifu_bp_ctl.scala 530:74] - node _T_1676 = and(_T_1673, _T_1675) @[ifu_bp_ctl.scala 530:22] - node _T_1677 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1678 = eq(_T_1677, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1679 = or(_T_1678, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1680 = and(_T_1676, _T_1679) @[ifu_bp_ctl.scala 530:87] - node _T_1681 = or(_T_1672, _T_1680) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[1][0][7] <= _T_1681 @[ifu_bp_ctl.scala 529:27] - node _T_1682 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 529:41] - node _T_1683 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1684 = eq(_T_1683, UInt<4>("h08")) @[ifu_bp_ctl.scala 529:97] - node _T_1685 = and(_T_1682, _T_1684) @[ifu_bp_ctl.scala 529:45] - node _T_1686 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1687 = eq(_T_1686, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1688 = or(_T_1687, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1689 = and(_T_1685, _T_1688) @[ifu_bp_ctl.scala 529:110] - node _T_1690 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 530:18] - node _T_1691 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1692 = eq(_T_1691, UInt<4>("h08")) @[ifu_bp_ctl.scala 530:74] - node _T_1693 = and(_T_1690, _T_1692) @[ifu_bp_ctl.scala 530:22] - node _T_1694 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1695 = eq(_T_1694, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1696 = or(_T_1695, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1697 = and(_T_1693, _T_1696) @[ifu_bp_ctl.scala 530:87] - node _T_1698 = or(_T_1689, _T_1697) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[1][0][8] <= _T_1698 @[ifu_bp_ctl.scala 529:27] - node _T_1699 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 529:41] - node _T_1700 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1701 = eq(_T_1700, UInt<4>("h09")) @[ifu_bp_ctl.scala 529:97] - node _T_1702 = and(_T_1699, _T_1701) @[ifu_bp_ctl.scala 529:45] - node _T_1703 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1704 = eq(_T_1703, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1705 = or(_T_1704, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1706 = and(_T_1702, _T_1705) @[ifu_bp_ctl.scala 529:110] - node _T_1707 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 530:18] - node _T_1708 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1709 = eq(_T_1708, UInt<4>("h09")) @[ifu_bp_ctl.scala 530:74] - node _T_1710 = and(_T_1707, _T_1709) @[ifu_bp_ctl.scala 530:22] - node _T_1711 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1712 = eq(_T_1711, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1713 = or(_T_1712, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1714 = and(_T_1710, _T_1713) @[ifu_bp_ctl.scala 530:87] - node _T_1715 = or(_T_1706, _T_1714) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[1][0][9] <= _T_1715 @[ifu_bp_ctl.scala 529:27] - node _T_1716 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 529:41] - node _T_1717 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1718 = eq(_T_1717, UInt<4>("h0a")) @[ifu_bp_ctl.scala 529:97] - node _T_1719 = and(_T_1716, _T_1718) @[ifu_bp_ctl.scala 529:45] - node _T_1720 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1721 = eq(_T_1720, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1722 = or(_T_1721, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1723 = and(_T_1719, _T_1722) @[ifu_bp_ctl.scala 529:110] - node _T_1724 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 530:18] - node _T_1725 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1726 = eq(_T_1725, UInt<4>("h0a")) @[ifu_bp_ctl.scala 530:74] - node _T_1727 = and(_T_1724, _T_1726) @[ifu_bp_ctl.scala 530:22] - node _T_1728 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1729 = eq(_T_1728, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1730 = or(_T_1729, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1731 = and(_T_1727, _T_1730) @[ifu_bp_ctl.scala 530:87] - node _T_1732 = or(_T_1723, _T_1731) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[1][0][10] <= _T_1732 @[ifu_bp_ctl.scala 529:27] - node _T_1733 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 529:41] - node _T_1734 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1735 = eq(_T_1734, UInt<4>("h0b")) @[ifu_bp_ctl.scala 529:97] - node _T_1736 = and(_T_1733, _T_1735) @[ifu_bp_ctl.scala 529:45] - node _T_1737 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1738 = eq(_T_1737, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1739 = or(_T_1738, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1740 = and(_T_1736, _T_1739) @[ifu_bp_ctl.scala 529:110] - node _T_1741 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 530:18] - node _T_1742 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1743 = eq(_T_1742, UInt<4>("h0b")) @[ifu_bp_ctl.scala 530:74] - node _T_1744 = and(_T_1741, _T_1743) @[ifu_bp_ctl.scala 530:22] - node _T_1745 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1746 = eq(_T_1745, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1747 = or(_T_1746, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1748 = and(_T_1744, _T_1747) @[ifu_bp_ctl.scala 530:87] - node _T_1749 = or(_T_1740, _T_1748) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[1][0][11] <= _T_1749 @[ifu_bp_ctl.scala 529:27] - node _T_1750 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 529:41] - node _T_1751 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1752 = eq(_T_1751, UInt<4>("h0c")) @[ifu_bp_ctl.scala 529:97] - node _T_1753 = and(_T_1750, _T_1752) @[ifu_bp_ctl.scala 529:45] - node _T_1754 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1755 = eq(_T_1754, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1756 = or(_T_1755, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1757 = and(_T_1753, _T_1756) @[ifu_bp_ctl.scala 529:110] - node _T_1758 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 530:18] - node _T_1759 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1760 = eq(_T_1759, UInt<4>("h0c")) @[ifu_bp_ctl.scala 530:74] - node _T_1761 = and(_T_1758, _T_1760) @[ifu_bp_ctl.scala 530:22] - node _T_1762 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1763 = eq(_T_1762, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1764 = or(_T_1763, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1765 = and(_T_1761, _T_1764) @[ifu_bp_ctl.scala 530:87] - node _T_1766 = or(_T_1757, _T_1765) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[1][0][12] <= _T_1766 @[ifu_bp_ctl.scala 529:27] - node _T_1767 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 529:41] - node _T_1768 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1769 = eq(_T_1768, UInt<4>("h0d")) @[ifu_bp_ctl.scala 529:97] - node _T_1770 = and(_T_1767, _T_1769) @[ifu_bp_ctl.scala 529:45] - node _T_1771 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1772 = eq(_T_1771, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1773 = or(_T_1772, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1774 = and(_T_1770, _T_1773) @[ifu_bp_ctl.scala 529:110] - node _T_1775 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 530:18] - node _T_1776 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1777 = eq(_T_1776, UInt<4>("h0d")) @[ifu_bp_ctl.scala 530:74] - node _T_1778 = and(_T_1775, _T_1777) @[ifu_bp_ctl.scala 530:22] - node _T_1779 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1780 = eq(_T_1779, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1781 = or(_T_1780, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1782 = and(_T_1778, _T_1781) @[ifu_bp_ctl.scala 530:87] - node _T_1783 = or(_T_1774, _T_1782) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[1][0][13] <= _T_1783 @[ifu_bp_ctl.scala 529:27] - node _T_1784 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 529:41] - node _T_1785 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1786 = eq(_T_1785, UInt<4>("h0e")) @[ifu_bp_ctl.scala 529:97] - node _T_1787 = and(_T_1784, _T_1786) @[ifu_bp_ctl.scala 529:45] - node _T_1788 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1789 = eq(_T_1788, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1790 = or(_T_1789, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1791 = and(_T_1787, _T_1790) @[ifu_bp_ctl.scala 529:110] - node _T_1792 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 530:18] - node _T_1793 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1794 = eq(_T_1793, UInt<4>("h0e")) @[ifu_bp_ctl.scala 530:74] - node _T_1795 = and(_T_1792, _T_1794) @[ifu_bp_ctl.scala 530:22] - node _T_1796 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1797 = eq(_T_1796, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1798 = or(_T_1797, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1799 = and(_T_1795, _T_1798) @[ifu_bp_ctl.scala 530:87] - node _T_1800 = or(_T_1791, _T_1799) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[1][0][14] <= _T_1800 @[ifu_bp_ctl.scala 529:27] - node _T_1801 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 529:41] - node _T_1802 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:60] - node _T_1803 = eq(_T_1802, UInt<4>("h0f")) @[ifu_bp_ctl.scala 529:97] - node _T_1804 = and(_T_1801, _T_1803) @[ifu_bp_ctl.scala 529:45] - node _T_1805 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 529:126] - node _T_1806 = eq(_T_1805, UInt<1>("h00")) @[ifu_bp_ctl.scala 529:186] - node _T_1807 = or(_T_1806, UInt<1>("h01")) @[ifu_bp_ctl.scala 529:199] - node _T_1808 = and(_T_1804, _T_1807) @[ifu_bp_ctl.scala 529:110] - node _T_1809 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 530:18] - node _T_1810 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:37] - node _T_1811 = eq(_T_1810, UInt<4>("h0f")) @[ifu_bp_ctl.scala 530:74] - node _T_1812 = and(_T_1809, _T_1811) @[ifu_bp_ctl.scala 530:22] - node _T_1813 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 530:103] - node _T_1814 = eq(_T_1813, UInt<1>("h00")) @[ifu_bp_ctl.scala 530:163] - node _T_1815 = or(_T_1814, UInt<1>("h01")) @[ifu_bp_ctl.scala 530:176] - node _T_1816 = and(_T_1812, _T_1815) @[ifu_bp_ctl.scala 530:87] - node _T_1817 = or(_T_1808, _T_1816) @[ifu_bp_ctl.scala 529:223] - bht_bank_sel[1][0][15] <= _T_1817 @[ifu_bp_ctl.scala 529:27] - wire bht_bank_rd_data_out : UInt<2>[16][2] @[ifu_bp_ctl.scala 533:34] - node _T_1818 = and(bht_bank_sel[0][0][0], bht_bank_sel[0][0][0]) @[lib.scala 383:57] + bht_bank_clk[1][0] <= rvclkhdr_42.io.l1clk @[ifu_bp_ctl.scala 517:84] + node _T_962 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 522:40] + node _T_963 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 522:60] + node _T_964 = eq(_T_963, UInt<1>("h00")) @[ifu_bp_ctl.scala 522:109] + node _T_965 = or(_T_964, UInt<1>("h01")) @[ifu_bp_ctl.scala 522:117] + node _T_966 = and(_T_962, _T_965) @[ifu_bp_ctl.scala 522:44] + node _T_967 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 523:40] + node _T_968 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 523:60] + node _T_969 = eq(_T_968, UInt<1>("h00")) @[ifu_bp_ctl.scala 523:109] + node _T_970 = or(_T_969, UInt<1>("h01")) @[ifu_bp_ctl.scala 523:117] + node _T_971 = and(_T_967, _T_970) @[ifu_bp_ctl.scala 523:44] + node _T_972 = or(_T_966, _T_971) @[ifu_bp_ctl.scala 522:142] + bht_bank_clken[0][0] <= _T_972 @[ifu_bp_ctl.scala 522:26] + node _T_973 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 522:40] + node _T_974 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 522:60] + node _T_975 = eq(_T_974, UInt<1>("h00")) @[ifu_bp_ctl.scala 522:109] + node _T_976 = or(_T_975, UInt<1>("h01")) @[ifu_bp_ctl.scala 522:117] + node _T_977 = and(_T_973, _T_976) @[ifu_bp_ctl.scala 522:44] + node _T_978 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 523:40] + node _T_979 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 523:60] + node _T_980 = eq(_T_979, UInt<1>("h00")) @[ifu_bp_ctl.scala 523:109] + node _T_981 = or(_T_980, UInt<1>("h01")) @[ifu_bp_ctl.scala 523:117] + node _T_982 = and(_T_978, _T_981) @[ifu_bp_ctl.scala 523:44] + node _T_983 = or(_T_977, _T_982) @[ifu_bp_ctl.scala 522:142] + bht_bank_clken[1][0] <= _T_983 @[ifu_bp_ctl.scala 522:26] + node _T_984 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 528:20] + node _T_985 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_986 = eq(_T_985, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:74] + node _T_987 = and(_T_984, _T_986) @[ifu_bp_ctl.scala 528:23] + node _T_988 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_989 = eq(_T_988, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_990 = and(_T_987, _T_989) @[ifu_bp_ctl.scala 528:81] + node _T_991 = or(_T_990, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_992 = bits(_T_991, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_0_0_0 = mux(_T_992, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_993 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 528:20] + node _T_994 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_995 = eq(_T_994, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:74] + node _T_996 = and(_T_993, _T_995) @[ifu_bp_ctl.scala 528:23] + node _T_997 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_998 = eq(_T_997, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_999 = and(_T_996, _T_998) @[ifu_bp_ctl.scala 528:81] + node _T_1000 = or(_T_999, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1001 = bits(_T_1000, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_0_0_1 = mux(_T_1001, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1002 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 528:20] + node _T_1003 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1004 = eq(_T_1003, UInt<2>("h02")) @[ifu_bp_ctl.scala 528:74] + node _T_1005 = and(_T_1002, _T_1004) @[ifu_bp_ctl.scala 528:23] + node _T_1006 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1008 = and(_T_1005, _T_1007) @[ifu_bp_ctl.scala 528:81] + node _T_1009 = or(_T_1008, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1010 = bits(_T_1009, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_0_0_2 = mux(_T_1010, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1011 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 528:20] + node _T_1012 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1013 = eq(_T_1012, UInt<2>("h03")) @[ifu_bp_ctl.scala 528:74] + node _T_1014 = and(_T_1011, _T_1013) @[ifu_bp_ctl.scala 528:23] + node _T_1015 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1016 = eq(_T_1015, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1017 = and(_T_1014, _T_1016) @[ifu_bp_ctl.scala 528:81] + node _T_1018 = or(_T_1017, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1019 = bits(_T_1018, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_0_0_3 = mux(_T_1019, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1020 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 528:20] + node _T_1021 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1022 = eq(_T_1021, UInt<3>("h04")) @[ifu_bp_ctl.scala 528:74] + node _T_1023 = and(_T_1020, _T_1022) @[ifu_bp_ctl.scala 528:23] + node _T_1024 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1026 = and(_T_1023, _T_1025) @[ifu_bp_ctl.scala 528:81] + node _T_1027 = or(_T_1026, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1028 = bits(_T_1027, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_0_0_4 = mux(_T_1028, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1029 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 528:20] + node _T_1030 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1031 = eq(_T_1030, UInt<3>("h05")) @[ifu_bp_ctl.scala 528:74] + node _T_1032 = and(_T_1029, _T_1031) @[ifu_bp_ctl.scala 528:23] + node _T_1033 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1034 = eq(_T_1033, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1035 = and(_T_1032, _T_1034) @[ifu_bp_ctl.scala 528:81] + node _T_1036 = or(_T_1035, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1037 = bits(_T_1036, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_0_0_5 = mux(_T_1037, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1038 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 528:20] + node _T_1039 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1040 = eq(_T_1039, UInt<3>("h06")) @[ifu_bp_ctl.scala 528:74] + node _T_1041 = and(_T_1038, _T_1040) @[ifu_bp_ctl.scala 528:23] + node _T_1042 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1043 = eq(_T_1042, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1044 = and(_T_1041, _T_1043) @[ifu_bp_ctl.scala 528:81] + node _T_1045 = or(_T_1044, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1046 = bits(_T_1045, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_0_0_6 = mux(_T_1046, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1047 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 528:20] + node _T_1048 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1049 = eq(_T_1048, UInt<3>("h07")) @[ifu_bp_ctl.scala 528:74] + node _T_1050 = and(_T_1047, _T_1049) @[ifu_bp_ctl.scala 528:23] + node _T_1051 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1053 = and(_T_1050, _T_1052) @[ifu_bp_ctl.scala 528:81] + node _T_1054 = or(_T_1053, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1055 = bits(_T_1054, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_0_0_7 = mux(_T_1055, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1056 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 528:20] + node _T_1057 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1058 = eq(_T_1057, UInt<4>("h08")) @[ifu_bp_ctl.scala 528:74] + node _T_1059 = and(_T_1056, _T_1058) @[ifu_bp_ctl.scala 528:23] + node _T_1060 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1062 = and(_T_1059, _T_1061) @[ifu_bp_ctl.scala 528:81] + node _T_1063 = or(_T_1062, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1064 = bits(_T_1063, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_0_0_8 = mux(_T_1064, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1065 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 528:20] + node _T_1066 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1067 = eq(_T_1066, UInt<4>("h09")) @[ifu_bp_ctl.scala 528:74] + node _T_1068 = and(_T_1065, _T_1067) @[ifu_bp_ctl.scala 528:23] + node _T_1069 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1070 = eq(_T_1069, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1071 = and(_T_1068, _T_1070) @[ifu_bp_ctl.scala 528:81] + node _T_1072 = or(_T_1071, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1073 = bits(_T_1072, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_0_0_9 = mux(_T_1073, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1074 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 528:20] + node _T_1075 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1076 = eq(_T_1075, UInt<4>("h0a")) @[ifu_bp_ctl.scala 528:74] + node _T_1077 = and(_T_1074, _T_1076) @[ifu_bp_ctl.scala 528:23] + node _T_1078 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1079 = eq(_T_1078, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1080 = and(_T_1077, _T_1079) @[ifu_bp_ctl.scala 528:81] + node _T_1081 = or(_T_1080, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1082 = bits(_T_1081, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_0_0_10 = mux(_T_1082, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1083 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 528:20] + node _T_1084 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1085 = eq(_T_1084, UInt<4>("h0b")) @[ifu_bp_ctl.scala 528:74] + node _T_1086 = and(_T_1083, _T_1085) @[ifu_bp_ctl.scala 528:23] + node _T_1087 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1088 = eq(_T_1087, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1089 = and(_T_1086, _T_1088) @[ifu_bp_ctl.scala 528:81] + node _T_1090 = or(_T_1089, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1091 = bits(_T_1090, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_0_0_11 = mux(_T_1091, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1092 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 528:20] + node _T_1093 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1094 = eq(_T_1093, UInt<4>("h0c")) @[ifu_bp_ctl.scala 528:74] + node _T_1095 = and(_T_1092, _T_1094) @[ifu_bp_ctl.scala 528:23] + node _T_1096 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1098 = and(_T_1095, _T_1097) @[ifu_bp_ctl.scala 528:81] + node _T_1099 = or(_T_1098, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1100 = bits(_T_1099, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_0_0_12 = mux(_T_1100, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1101 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 528:20] + node _T_1102 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1103 = eq(_T_1102, UInt<4>("h0d")) @[ifu_bp_ctl.scala 528:74] + node _T_1104 = and(_T_1101, _T_1103) @[ifu_bp_ctl.scala 528:23] + node _T_1105 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1106 = eq(_T_1105, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1107 = and(_T_1104, _T_1106) @[ifu_bp_ctl.scala 528:81] + node _T_1108 = or(_T_1107, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1109 = bits(_T_1108, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_0_0_13 = mux(_T_1109, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1110 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 528:20] + node _T_1111 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1112 = eq(_T_1111, UInt<4>("h0e")) @[ifu_bp_ctl.scala 528:74] + node _T_1113 = and(_T_1110, _T_1112) @[ifu_bp_ctl.scala 528:23] + node _T_1114 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1115 = eq(_T_1114, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1116 = and(_T_1113, _T_1115) @[ifu_bp_ctl.scala 528:81] + node _T_1117 = or(_T_1116, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1118 = bits(_T_1117, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_0_0_14 = mux(_T_1118, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1119 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 528:20] + node _T_1120 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1121 = eq(_T_1120, UInt<4>("h0f")) @[ifu_bp_ctl.scala 528:74] + node _T_1122 = and(_T_1119, _T_1121) @[ifu_bp_ctl.scala 528:23] + node _T_1123 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1124 = eq(_T_1123, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1125 = and(_T_1122, _T_1124) @[ifu_bp_ctl.scala 528:81] + node _T_1126 = or(_T_1125, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1127 = bits(_T_1126, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_0_0_15 = mux(_T_1127, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1128 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 528:20] + node _T_1129 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1130 = eq(_T_1129, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:74] + node _T_1131 = and(_T_1128, _T_1130) @[ifu_bp_ctl.scala 528:23] + node _T_1132 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1133 = eq(_T_1132, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1134 = and(_T_1131, _T_1133) @[ifu_bp_ctl.scala 528:81] + node _T_1135 = or(_T_1134, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1136 = bits(_T_1135, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_1_0_0 = mux(_T_1136, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1137 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 528:20] + node _T_1138 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1139 = eq(_T_1138, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:74] + node _T_1140 = and(_T_1137, _T_1139) @[ifu_bp_ctl.scala 528:23] + node _T_1141 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1142 = eq(_T_1141, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1143 = and(_T_1140, _T_1142) @[ifu_bp_ctl.scala 528:81] + node _T_1144 = or(_T_1143, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1145 = bits(_T_1144, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_1_0_1 = mux(_T_1145, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1146 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 528:20] + node _T_1147 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1148 = eq(_T_1147, UInt<2>("h02")) @[ifu_bp_ctl.scala 528:74] + node _T_1149 = and(_T_1146, _T_1148) @[ifu_bp_ctl.scala 528:23] + node _T_1150 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1151 = eq(_T_1150, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1152 = and(_T_1149, _T_1151) @[ifu_bp_ctl.scala 528:81] + node _T_1153 = or(_T_1152, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1154 = bits(_T_1153, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_1_0_2 = mux(_T_1154, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1155 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 528:20] + node _T_1156 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1157 = eq(_T_1156, UInt<2>("h03")) @[ifu_bp_ctl.scala 528:74] + node _T_1158 = and(_T_1155, _T_1157) @[ifu_bp_ctl.scala 528:23] + node _T_1159 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1160 = eq(_T_1159, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1161 = and(_T_1158, _T_1160) @[ifu_bp_ctl.scala 528:81] + node _T_1162 = or(_T_1161, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1163 = bits(_T_1162, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_1_0_3 = mux(_T_1163, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1164 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 528:20] + node _T_1165 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1166 = eq(_T_1165, UInt<3>("h04")) @[ifu_bp_ctl.scala 528:74] + node _T_1167 = and(_T_1164, _T_1166) @[ifu_bp_ctl.scala 528:23] + node _T_1168 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1169 = eq(_T_1168, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1170 = and(_T_1167, _T_1169) @[ifu_bp_ctl.scala 528:81] + node _T_1171 = or(_T_1170, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1172 = bits(_T_1171, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_1_0_4 = mux(_T_1172, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1173 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 528:20] + node _T_1174 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1175 = eq(_T_1174, UInt<3>("h05")) @[ifu_bp_ctl.scala 528:74] + node _T_1176 = and(_T_1173, _T_1175) @[ifu_bp_ctl.scala 528:23] + node _T_1177 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1178 = eq(_T_1177, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1179 = and(_T_1176, _T_1178) @[ifu_bp_ctl.scala 528:81] + node _T_1180 = or(_T_1179, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1181 = bits(_T_1180, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_1_0_5 = mux(_T_1181, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1182 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 528:20] + node _T_1183 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1184 = eq(_T_1183, UInt<3>("h06")) @[ifu_bp_ctl.scala 528:74] + node _T_1185 = and(_T_1182, _T_1184) @[ifu_bp_ctl.scala 528:23] + node _T_1186 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1187 = eq(_T_1186, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1188 = and(_T_1185, _T_1187) @[ifu_bp_ctl.scala 528:81] + node _T_1189 = or(_T_1188, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1190 = bits(_T_1189, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_1_0_6 = mux(_T_1190, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1191 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 528:20] + node _T_1192 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1193 = eq(_T_1192, UInt<3>("h07")) @[ifu_bp_ctl.scala 528:74] + node _T_1194 = and(_T_1191, _T_1193) @[ifu_bp_ctl.scala 528:23] + node _T_1195 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1196 = eq(_T_1195, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1197 = and(_T_1194, _T_1196) @[ifu_bp_ctl.scala 528:81] + node _T_1198 = or(_T_1197, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1199 = bits(_T_1198, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_1_0_7 = mux(_T_1199, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1200 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 528:20] + node _T_1201 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1202 = eq(_T_1201, UInt<4>("h08")) @[ifu_bp_ctl.scala 528:74] + node _T_1203 = and(_T_1200, _T_1202) @[ifu_bp_ctl.scala 528:23] + node _T_1204 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1205 = eq(_T_1204, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1206 = and(_T_1203, _T_1205) @[ifu_bp_ctl.scala 528:81] + node _T_1207 = or(_T_1206, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1208 = bits(_T_1207, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_1_0_8 = mux(_T_1208, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1209 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 528:20] + node _T_1210 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1211 = eq(_T_1210, UInt<4>("h09")) @[ifu_bp_ctl.scala 528:74] + node _T_1212 = and(_T_1209, _T_1211) @[ifu_bp_ctl.scala 528:23] + node _T_1213 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1215 = and(_T_1212, _T_1214) @[ifu_bp_ctl.scala 528:81] + node _T_1216 = or(_T_1215, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1217 = bits(_T_1216, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_1_0_9 = mux(_T_1217, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1218 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 528:20] + node _T_1219 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1220 = eq(_T_1219, UInt<4>("h0a")) @[ifu_bp_ctl.scala 528:74] + node _T_1221 = and(_T_1218, _T_1220) @[ifu_bp_ctl.scala 528:23] + node _T_1222 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1223 = eq(_T_1222, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1224 = and(_T_1221, _T_1223) @[ifu_bp_ctl.scala 528:81] + node _T_1225 = or(_T_1224, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1226 = bits(_T_1225, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_1_0_10 = mux(_T_1226, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1227 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 528:20] + node _T_1228 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1229 = eq(_T_1228, UInt<4>("h0b")) @[ifu_bp_ctl.scala 528:74] + node _T_1230 = and(_T_1227, _T_1229) @[ifu_bp_ctl.scala 528:23] + node _T_1231 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1233 = and(_T_1230, _T_1232) @[ifu_bp_ctl.scala 528:81] + node _T_1234 = or(_T_1233, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1235 = bits(_T_1234, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_1_0_11 = mux(_T_1235, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1236 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 528:20] + node _T_1237 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1238 = eq(_T_1237, UInt<4>("h0c")) @[ifu_bp_ctl.scala 528:74] + node _T_1239 = and(_T_1236, _T_1238) @[ifu_bp_ctl.scala 528:23] + node _T_1240 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1241 = eq(_T_1240, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1242 = and(_T_1239, _T_1241) @[ifu_bp_ctl.scala 528:81] + node _T_1243 = or(_T_1242, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1244 = bits(_T_1243, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_1_0_12 = mux(_T_1244, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1245 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 528:20] + node _T_1246 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1247 = eq(_T_1246, UInt<4>("h0d")) @[ifu_bp_ctl.scala 528:74] + node _T_1248 = and(_T_1245, _T_1247) @[ifu_bp_ctl.scala 528:23] + node _T_1249 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1250 = eq(_T_1249, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1251 = and(_T_1248, _T_1250) @[ifu_bp_ctl.scala 528:81] + node _T_1252 = or(_T_1251, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1253 = bits(_T_1252, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_1_0_13 = mux(_T_1253, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1254 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 528:20] + node _T_1255 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1256 = eq(_T_1255, UInt<4>("h0e")) @[ifu_bp_ctl.scala 528:74] + node _T_1257 = and(_T_1254, _T_1256) @[ifu_bp_ctl.scala 528:23] + node _T_1258 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1259 = eq(_T_1258, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1260 = and(_T_1257, _T_1259) @[ifu_bp_ctl.scala 528:81] + node _T_1261 = or(_T_1260, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1262 = bits(_T_1261, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_1_0_14 = mux(_T_1262, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + node _T_1263 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 528:20] + node _T_1264 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:37] + node _T_1265 = eq(_T_1264, UInt<4>("h0f")) @[ifu_bp_ctl.scala 528:74] + node _T_1266 = and(_T_1263, _T_1265) @[ifu_bp_ctl.scala 528:23] + node _T_1267 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 528:95] + node _T_1268 = eq(_T_1267, UInt<1>("h00")) @[ifu_bp_ctl.scala 528:154] + node _T_1269 = and(_T_1266, _T_1268) @[ifu_bp_ctl.scala 528:81] + node _T_1270 = or(_T_1269, UInt<1>("h01")) @[ifu_bp_ctl.scala 528:161] + node _T_1271 = bits(_T_1270, 0, 0) @[ifu_bp_ctl.scala 528:183] + node bht_bank_wr_data_1_0_15 = mux(_T_1271, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 528:8] + wire bht_bank_sel : UInt<1>[16][1][2] @[ifu_bp_ctl.scala 530:26] + node _T_1272 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 536:41] + node _T_1273 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1274 = eq(_T_1273, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:97] + node _T_1275 = and(_T_1272, _T_1274) @[ifu_bp_ctl.scala 536:45] + node _T_1276 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1277 = eq(_T_1276, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1278 = or(_T_1277, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1279 = and(_T_1275, _T_1278) @[ifu_bp_ctl.scala 536:110] + node _T_1280 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 537:18] + node _T_1281 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1282 = eq(_T_1281, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:74] + node _T_1283 = and(_T_1280, _T_1282) @[ifu_bp_ctl.scala 537:22] + node _T_1284 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1285 = eq(_T_1284, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1286 = or(_T_1285, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1287 = and(_T_1283, _T_1286) @[ifu_bp_ctl.scala 537:87] + node _T_1288 = or(_T_1279, _T_1287) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[0][0][0] <= _T_1288 @[ifu_bp_ctl.scala 536:27] + node _T_1289 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 536:41] + node _T_1290 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1291 = eq(_T_1290, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:97] + node _T_1292 = and(_T_1289, _T_1291) @[ifu_bp_ctl.scala 536:45] + node _T_1293 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1294 = eq(_T_1293, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1295 = or(_T_1294, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1296 = and(_T_1292, _T_1295) @[ifu_bp_ctl.scala 536:110] + node _T_1297 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 537:18] + node _T_1298 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1299 = eq(_T_1298, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:74] + node _T_1300 = and(_T_1297, _T_1299) @[ifu_bp_ctl.scala 537:22] + node _T_1301 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1302 = eq(_T_1301, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1303 = or(_T_1302, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1304 = and(_T_1300, _T_1303) @[ifu_bp_ctl.scala 537:87] + node _T_1305 = or(_T_1296, _T_1304) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[0][0][1] <= _T_1305 @[ifu_bp_ctl.scala 536:27] + node _T_1306 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 536:41] + node _T_1307 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1308 = eq(_T_1307, UInt<2>("h02")) @[ifu_bp_ctl.scala 536:97] + node _T_1309 = and(_T_1306, _T_1308) @[ifu_bp_ctl.scala 536:45] + node _T_1310 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1312 = or(_T_1311, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1313 = and(_T_1309, _T_1312) @[ifu_bp_ctl.scala 536:110] + node _T_1314 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 537:18] + node _T_1315 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1316 = eq(_T_1315, UInt<2>("h02")) @[ifu_bp_ctl.scala 537:74] + node _T_1317 = and(_T_1314, _T_1316) @[ifu_bp_ctl.scala 537:22] + node _T_1318 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1319 = eq(_T_1318, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1320 = or(_T_1319, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1321 = and(_T_1317, _T_1320) @[ifu_bp_ctl.scala 537:87] + node _T_1322 = or(_T_1313, _T_1321) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[0][0][2] <= _T_1322 @[ifu_bp_ctl.scala 536:27] + node _T_1323 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 536:41] + node _T_1324 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1325 = eq(_T_1324, UInt<2>("h03")) @[ifu_bp_ctl.scala 536:97] + node _T_1326 = and(_T_1323, _T_1325) @[ifu_bp_ctl.scala 536:45] + node _T_1327 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1329 = or(_T_1328, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1330 = and(_T_1326, _T_1329) @[ifu_bp_ctl.scala 536:110] + node _T_1331 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 537:18] + node _T_1332 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1333 = eq(_T_1332, UInt<2>("h03")) @[ifu_bp_ctl.scala 537:74] + node _T_1334 = and(_T_1331, _T_1333) @[ifu_bp_ctl.scala 537:22] + node _T_1335 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1336 = eq(_T_1335, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1337 = or(_T_1336, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1338 = and(_T_1334, _T_1337) @[ifu_bp_ctl.scala 537:87] + node _T_1339 = or(_T_1330, _T_1338) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[0][0][3] <= _T_1339 @[ifu_bp_ctl.scala 536:27] + node _T_1340 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 536:41] + node _T_1341 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1342 = eq(_T_1341, UInt<3>("h04")) @[ifu_bp_ctl.scala 536:97] + node _T_1343 = and(_T_1340, _T_1342) @[ifu_bp_ctl.scala 536:45] + node _T_1344 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1345 = eq(_T_1344, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1346 = or(_T_1345, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1347 = and(_T_1343, _T_1346) @[ifu_bp_ctl.scala 536:110] + node _T_1348 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 537:18] + node _T_1349 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1350 = eq(_T_1349, UInt<3>("h04")) @[ifu_bp_ctl.scala 537:74] + node _T_1351 = and(_T_1348, _T_1350) @[ifu_bp_ctl.scala 537:22] + node _T_1352 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1353 = eq(_T_1352, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1354 = or(_T_1353, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1355 = and(_T_1351, _T_1354) @[ifu_bp_ctl.scala 537:87] + node _T_1356 = or(_T_1347, _T_1355) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[0][0][4] <= _T_1356 @[ifu_bp_ctl.scala 536:27] + node _T_1357 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 536:41] + node _T_1358 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1359 = eq(_T_1358, UInt<3>("h05")) @[ifu_bp_ctl.scala 536:97] + node _T_1360 = and(_T_1357, _T_1359) @[ifu_bp_ctl.scala 536:45] + node _T_1361 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1362 = eq(_T_1361, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1363 = or(_T_1362, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1364 = and(_T_1360, _T_1363) @[ifu_bp_ctl.scala 536:110] + node _T_1365 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 537:18] + node _T_1366 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1367 = eq(_T_1366, UInt<3>("h05")) @[ifu_bp_ctl.scala 537:74] + node _T_1368 = and(_T_1365, _T_1367) @[ifu_bp_ctl.scala 537:22] + node _T_1369 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1370 = eq(_T_1369, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1371 = or(_T_1370, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1372 = and(_T_1368, _T_1371) @[ifu_bp_ctl.scala 537:87] + node _T_1373 = or(_T_1364, _T_1372) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[0][0][5] <= _T_1373 @[ifu_bp_ctl.scala 536:27] + node _T_1374 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 536:41] + node _T_1375 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1376 = eq(_T_1375, UInt<3>("h06")) @[ifu_bp_ctl.scala 536:97] + node _T_1377 = and(_T_1374, _T_1376) @[ifu_bp_ctl.scala 536:45] + node _T_1378 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1379 = eq(_T_1378, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1380 = or(_T_1379, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1381 = and(_T_1377, _T_1380) @[ifu_bp_ctl.scala 536:110] + node _T_1382 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 537:18] + node _T_1383 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1384 = eq(_T_1383, UInt<3>("h06")) @[ifu_bp_ctl.scala 537:74] + node _T_1385 = and(_T_1382, _T_1384) @[ifu_bp_ctl.scala 537:22] + node _T_1386 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1388 = or(_T_1387, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1389 = and(_T_1385, _T_1388) @[ifu_bp_ctl.scala 537:87] + node _T_1390 = or(_T_1381, _T_1389) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[0][0][6] <= _T_1390 @[ifu_bp_ctl.scala 536:27] + node _T_1391 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 536:41] + node _T_1392 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1393 = eq(_T_1392, UInt<3>("h07")) @[ifu_bp_ctl.scala 536:97] + node _T_1394 = and(_T_1391, _T_1393) @[ifu_bp_ctl.scala 536:45] + node _T_1395 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1397 = or(_T_1396, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1398 = and(_T_1394, _T_1397) @[ifu_bp_ctl.scala 536:110] + node _T_1399 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 537:18] + node _T_1400 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1401 = eq(_T_1400, UInt<3>("h07")) @[ifu_bp_ctl.scala 537:74] + node _T_1402 = and(_T_1399, _T_1401) @[ifu_bp_ctl.scala 537:22] + node _T_1403 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1404 = eq(_T_1403, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1405 = or(_T_1404, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1406 = and(_T_1402, _T_1405) @[ifu_bp_ctl.scala 537:87] + node _T_1407 = or(_T_1398, _T_1406) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[0][0][7] <= _T_1407 @[ifu_bp_ctl.scala 536:27] + node _T_1408 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 536:41] + node _T_1409 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1410 = eq(_T_1409, UInt<4>("h08")) @[ifu_bp_ctl.scala 536:97] + node _T_1411 = and(_T_1408, _T_1410) @[ifu_bp_ctl.scala 536:45] + node _T_1412 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1413 = eq(_T_1412, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1414 = or(_T_1413, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1415 = and(_T_1411, _T_1414) @[ifu_bp_ctl.scala 536:110] + node _T_1416 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 537:18] + node _T_1417 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1418 = eq(_T_1417, UInt<4>("h08")) @[ifu_bp_ctl.scala 537:74] + node _T_1419 = and(_T_1416, _T_1418) @[ifu_bp_ctl.scala 537:22] + node _T_1420 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1422 = or(_T_1421, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1423 = and(_T_1419, _T_1422) @[ifu_bp_ctl.scala 537:87] + node _T_1424 = or(_T_1415, _T_1423) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[0][0][8] <= _T_1424 @[ifu_bp_ctl.scala 536:27] + node _T_1425 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 536:41] + node _T_1426 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1427 = eq(_T_1426, UInt<4>("h09")) @[ifu_bp_ctl.scala 536:97] + node _T_1428 = and(_T_1425, _T_1427) @[ifu_bp_ctl.scala 536:45] + node _T_1429 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1430 = eq(_T_1429, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1431 = or(_T_1430, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1432 = and(_T_1428, _T_1431) @[ifu_bp_ctl.scala 536:110] + node _T_1433 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 537:18] + node _T_1434 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1435 = eq(_T_1434, UInt<4>("h09")) @[ifu_bp_ctl.scala 537:74] + node _T_1436 = and(_T_1433, _T_1435) @[ifu_bp_ctl.scala 537:22] + node _T_1437 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1438 = eq(_T_1437, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1439 = or(_T_1438, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1440 = and(_T_1436, _T_1439) @[ifu_bp_ctl.scala 537:87] + node _T_1441 = or(_T_1432, _T_1440) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[0][0][9] <= _T_1441 @[ifu_bp_ctl.scala 536:27] + node _T_1442 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 536:41] + node _T_1443 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1444 = eq(_T_1443, UInt<4>("h0a")) @[ifu_bp_ctl.scala 536:97] + node _T_1445 = and(_T_1442, _T_1444) @[ifu_bp_ctl.scala 536:45] + node _T_1446 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1447 = eq(_T_1446, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1448 = or(_T_1447, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1449 = and(_T_1445, _T_1448) @[ifu_bp_ctl.scala 536:110] + node _T_1450 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 537:18] + node _T_1451 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1452 = eq(_T_1451, UInt<4>("h0a")) @[ifu_bp_ctl.scala 537:74] + node _T_1453 = and(_T_1450, _T_1452) @[ifu_bp_ctl.scala 537:22] + node _T_1454 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1455 = eq(_T_1454, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1456 = or(_T_1455, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1457 = and(_T_1453, _T_1456) @[ifu_bp_ctl.scala 537:87] + node _T_1458 = or(_T_1449, _T_1457) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[0][0][10] <= _T_1458 @[ifu_bp_ctl.scala 536:27] + node _T_1459 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 536:41] + node _T_1460 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1461 = eq(_T_1460, UInt<4>("h0b")) @[ifu_bp_ctl.scala 536:97] + node _T_1462 = and(_T_1459, _T_1461) @[ifu_bp_ctl.scala 536:45] + node _T_1463 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1464 = eq(_T_1463, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1465 = or(_T_1464, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1466 = and(_T_1462, _T_1465) @[ifu_bp_ctl.scala 536:110] + node _T_1467 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 537:18] + node _T_1468 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1469 = eq(_T_1468, UInt<4>("h0b")) @[ifu_bp_ctl.scala 537:74] + node _T_1470 = and(_T_1467, _T_1469) @[ifu_bp_ctl.scala 537:22] + node _T_1471 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1472 = eq(_T_1471, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1473 = or(_T_1472, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1474 = and(_T_1470, _T_1473) @[ifu_bp_ctl.scala 537:87] + node _T_1475 = or(_T_1466, _T_1474) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[0][0][11] <= _T_1475 @[ifu_bp_ctl.scala 536:27] + node _T_1476 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 536:41] + node _T_1477 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1478 = eq(_T_1477, UInt<4>("h0c")) @[ifu_bp_ctl.scala 536:97] + node _T_1479 = and(_T_1476, _T_1478) @[ifu_bp_ctl.scala 536:45] + node _T_1480 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1481 = eq(_T_1480, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1482 = or(_T_1481, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1483 = and(_T_1479, _T_1482) @[ifu_bp_ctl.scala 536:110] + node _T_1484 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 537:18] + node _T_1485 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1486 = eq(_T_1485, UInt<4>("h0c")) @[ifu_bp_ctl.scala 537:74] + node _T_1487 = and(_T_1484, _T_1486) @[ifu_bp_ctl.scala 537:22] + node _T_1488 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1489 = eq(_T_1488, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1490 = or(_T_1489, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1491 = and(_T_1487, _T_1490) @[ifu_bp_ctl.scala 537:87] + node _T_1492 = or(_T_1483, _T_1491) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[0][0][12] <= _T_1492 @[ifu_bp_ctl.scala 536:27] + node _T_1493 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 536:41] + node _T_1494 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1495 = eq(_T_1494, UInt<4>("h0d")) @[ifu_bp_ctl.scala 536:97] + node _T_1496 = and(_T_1493, _T_1495) @[ifu_bp_ctl.scala 536:45] + node _T_1497 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1498 = eq(_T_1497, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1499 = or(_T_1498, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1500 = and(_T_1496, _T_1499) @[ifu_bp_ctl.scala 536:110] + node _T_1501 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 537:18] + node _T_1502 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1503 = eq(_T_1502, UInt<4>("h0d")) @[ifu_bp_ctl.scala 537:74] + node _T_1504 = and(_T_1501, _T_1503) @[ifu_bp_ctl.scala 537:22] + node _T_1505 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1506 = eq(_T_1505, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1507 = or(_T_1506, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1508 = and(_T_1504, _T_1507) @[ifu_bp_ctl.scala 537:87] + node _T_1509 = or(_T_1500, _T_1508) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[0][0][13] <= _T_1509 @[ifu_bp_ctl.scala 536:27] + node _T_1510 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 536:41] + node _T_1511 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1512 = eq(_T_1511, UInt<4>("h0e")) @[ifu_bp_ctl.scala 536:97] + node _T_1513 = and(_T_1510, _T_1512) @[ifu_bp_ctl.scala 536:45] + node _T_1514 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1516 = or(_T_1515, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1517 = and(_T_1513, _T_1516) @[ifu_bp_ctl.scala 536:110] + node _T_1518 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 537:18] + node _T_1519 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1520 = eq(_T_1519, UInt<4>("h0e")) @[ifu_bp_ctl.scala 537:74] + node _T_1521 = and(_T_1518, _T_1520) @[ifu_bp_ctl.scala 537:22] + node _T_1522 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1523 = eq(_T_1522, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1524 = or(_T_1523, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1525 = and(_T_1521, _T_1524) @[ifu_bp_ctl.scala 537:87] + node _T_1526 = or(_T_1517, _T_1525) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[0][0][14] <= _T_1526 @[ifu_bp_ctl.scala 536:27] + node _T_1527 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 536:41] + node _T_1528 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1529 = eq(_T_1528, UInt<4>("h0f")) @[ifu_bp_ctl.scala 536:97] + node _T_1530 = and(_T_1527, _T_1529) @[ifu_bp_ctl.scala 536:45] + node _T_1531 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1532 = eq(_T_1531, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1533 = or(_T_1532, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1534 = and(_T_1530, _T_1533) @[ifu_bp_ctl.scala 536:110] + node _T_1535 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 537:18] + node _T_1536 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1537 = eq(_T_1536, UInt<4>("h0f")) @[ifu_bp_ctl.scala 537:74] + node _T_1538 = and(_T_1535, _T_1537) @[ifu_bp_ctl.scala 537:22] + node _T_1539 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1540 = eq(_T_1539, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1541 = or(_T_1540, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1542 = and(_T_1538, _T_1541) @[ifu_bp_ctl.scala 537:87] + node _T_1543 = or(_T_1534, _T_1542) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[0][0][15] <= _T_1543 @[ifu_bp_ctl.scala 536:27] + node _T_1544 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 536:41] + node _T_1545 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1546 = eq(_T_1545, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:97] + node _T_1547 = and(_T_1544, _T_1546) @[ifu_bp_ctl.scala 536:45] + node _T_1548 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1549 = eq(_T_1548, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1550 = or(_T_1549, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1551 = and(_T_1547, _T_1550) @[ifu_bp_ctl.scala 536:110] + node _T_1552 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 537:18] + node _T_1553 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1554 = eq(_T_1553, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:74] + node _T_1555 = and(_T_1552, _T_1554) @[ifu_bp_ctl.scala 537:22] + node _T_1556 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1557 = eq(_T_1556, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1558 = or(_T_1557, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1559 = and(_T_1555, _T_1558) @[ifu_bp_ctl.scala 537:87] + node _T_1560 = or(_T_1551, _T_1559) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[1][0][0] <= _T_1560 @[ifu_bp_ctl.scala 536:27] + node _T_1561 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 536:41] + node _T_1562 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1563 = eq(_T_1562, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:97] + node _T_1564 = and(_T_1561, _T_1563) @[ifu_bp_ctl.scala 536:45] + node _T_1565 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1566 = eq(_T_1565, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1567 = or(_T_1566, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1568 = and(_T_1564, _T_1567) @[ifu_bp_ctl.scala 536:110] + node _T_1569 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 537:18] + node _T_1570 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1571 = eq(_T_1570, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:74] + node _T_1572 = and(_T_1569, _T_1571) @[ifu_bp_ctl.scala 537:22] + node _T_1573 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1574 = eq(_T_1573, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1575 = or(_T_1574, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1576 = and(_T_1572, _T_1575) @[ifu_bp_ctl.scala 537:87] + node _T_1577 = or(_T_1568, _T_1576) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[1][0][1] <= _T_1577 @[ifu_bp_ctl.scala 536:27] + node _T_1578 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 536:41] + node _T_1579 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1580 = eq(_T_1579, UInt<2>("h02")) @[ifu_bp_ctl.scala 536:97] + node _T_1581 = and(_T_1578, _T_1580) @[ifu_bp_ctl.scala 536:45] + node _T_1582 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1583 = eq(_T_1582, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1584 = or(_T_1583, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1585 = and(_T_1581, _T_1584) @[ifu_bp_ctl.scala 536:110] + node _T_1586 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 537:18] + node _T_1587 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1588 = eq(_T_1587, UInt<2>("h02")) @[ifu_bp_ctl.scala 537:74] + node _T_1589 = and(_T_1586, _T_1588) @[ifu_bp_ctl.scala 537:22] + node _T_1590 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1592 = or(_T_1591, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1593 = and(_T_1589, _T_1592) @[ifu_bp_ctl.scala 537:87] + node _T_1594 = or(_T_1585, _T_1593) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[1][0][2] <= _T_1594 @[ifu_bp_ctl.scala 536:27] + node _T_1595 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 536:41] + node _T_1596 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1597 = eq(_T_1596, UInt<2>("h03")) @[ifu_bp_ctl.scala 536:97] + node _T_1598 = and(_T_1595, _T_1597) @[ifu_bp_ctl.scala 536:45] + node _T_1599 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1600 = eq(_T_1599, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1601 = or(_T_1600, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1602 = and(_T_1598, _T_1601) @[ifu_bp_ctl.scala 536:110] + node _T_1603 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 537:18] + node _T_1604 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1605 = eq(_T_1604, UInt<2>("h03")) @[ifu_bp_ctl.scala 537:74] + node _T_1606 = and(_T_1603, _T_1605) @[ifu_bp_ctl.scala 537:22] + node _T_1607 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1608 = eq(_T_1607, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1609 = or(_T_1608, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1610 = and(_T_1606, _T_1609) @[ifu_bp_ctl.scala 537:87] + node _T_1611 = or(_T_1602, _T_1610) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[1][0][3] <= _T_1611 @[ifu_bp_ctl.scala 536:27] + node _T_1612 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 536:41] + node _T_1613 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1614 = eq(_T_1613, UInt<3>("h04")) @[ifu_bp_ctl.scala 536:97] + node _T_1615 = and(_T_1612, _T_1614) @[ifu_bp_ctl.scala 536:45] + node _T_1616 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1617 = eq(_T_1616, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1618 = or(_T_1617, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1619 = and(_T_1615, _T_1618) @[ifu_bp_ctl.scala 536:110] + node _T_1620 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 537:18] + node _T_1621 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1622 = eq(_T_1621, UInt<3>("h04")) @[ifu_bp_ctl.scala 537:74] + node _T_1623 = and(_T_1620, _T_1622) @[ifu_bp_ctl.scala 537:22] + node _T_1624 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1625 = eq(_T_1624, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1626 = or(_T_1625, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1627 = and(_T_1623, _T_1626) @[ifu_bp_ctl.scala 537:87] + node _T_1628 = or(_T_1619, _T_1627) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[1][0][4] <= _T_1628 @[ifu_bp_ctl.scala 536:27] + node _T_1629 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 536:41] + node _T_1630 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1631 = eq(_T_1630, UInt<3>("h05")) @[ifu_bp_ctl.scala 536:97] + node _T_1632 = and(_T_1629, _T_1631) @[ifu_bp_ctl.scala 536:45] + node _T_1633 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1634 = eq(_T_1633, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1635 = or(_T_1634, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1636 = and(_T_1632, _T_1635) @[ifu_bp_ctl.scala 536:110] + node _T_1637 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 537:18] + node _T_1638 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1639 = eq(_T_1638, UInt<3>("h05")) @[ifu_bp_ctl.scala 537:74] + node _T_1640 = and(_T_1637, _T_1639) @[ifu_bp_ctl.scala 537:22] + node _T_1641 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1642 = eq(_T_1641, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1643 = or(_T_1642, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1644 = and(_T_1640, _T_1643) @[ifu_bp_ctl.scala 537:87] + node _T_1645 = or(_T_1636, _T_1644) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[1][0][5] <= _T_1645 @[ifu_bp_ctl.scala 536:27] + node _T_1646 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 536:41] + node _T_1647 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1648 = eq(_T_1647, UInt<3>("h06")) @[ifu_bp_ctl.scala 536:97] + node _T_1649 = and(_T_1646, _T_1648) @[ifu_bp_ctl.scala 536:45] + node _T_1650 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1651 = eq(_T_1650, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1652 = or(_T_1651, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1653 = and(_T_1649, _T_1652) @[ifu_bp_ctl.scala 536:110] + node _T_1654 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 537:18] + node _T_1655 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1656 = eq(_T_1655, UInt<3>("h06")) @[ifu_bp_ctl.scala 537:74] + node _T_1657 = and(_T_1654, _T_1656) @[ifu_bp_ctl.scala 537:22] + node _T_1658 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1659 = eq(_T_1658, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1660 = or(_T_1659, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1661 = and(_T_1657, _T_1660) @[ifu_bp_ctl.scala 537:87] + node _T_1662 = or(_T_1653, _T_1661) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[1][0][6] <= _T_1662 @[ifu_bp_ctl.scala 536:27] + node _T_1663 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 536:41] + node _T_1664 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1665 = eq(_T_1664, UInt<3>("h07")) @[ifu_bp_ctl.scala 536:97] + node _T_1666 = and(_T_1663, _T_1665) @[ifu_bp_ctl.scala 536:45] + node _T_1667 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1668 = eq(_T_1667, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1669 = or(_T_1668, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1670 = and(_T_1666, _T_1669) @[ifu_bp_ctl.scala 536:110] + node _T_1671 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 537:18] + node _T_1672 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1673 = eq(_T_1672, UInt<3>("h07")) @[ifu_bp_ctl.scala 537:74] + node _T_1674 = and(_T_1671, _T_1673) @[ifu_bp_ctl.scala 537:22] + node _T_1675 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1676 = eq(_T_1675, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1677 = or(_T_1676, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1678 = and(_T_1674, _T_1677) @[ifu_bp_ctl.scala 537:87] + node _T_1679 = or(_T_1670, _T_1678) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[1][0][7] <= _T_1679 @[ifu_bp_ctl.scala 536:27] + node _T_1680 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 536:41] + node _T_1681 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1682 = eq(_T_1681, UInt<4>("h08")) @[ifu_bp_ctl.scala 536:97] + node _T_1683 = and(_T_1680, _T_1682) @[ifu_bp_ctl.scala 536:45] + node _T_1684 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1685 = eq(_T_1684, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1686 = or(_T_1685, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1687 = and(_T_1683, _T_1686) @[ifu_bp_ctl.scala 536:110] + node _T_1688 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 537:18] + node _T_1689 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1690 = eq(_T_1689, UInt<4>("h08")) @[ifu_bp_ctl.scala 537:74] + node _T_1691 = and(_T_1688, _T_1690) @[ifu_bp_ctl.scala 537:22] + node _T_1692 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1693 = eq(_T_1692, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1694 = or(_T_1693, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1695 = and(_T_1691, _T_1694) @[ifu_bp_ctl.scala 537:87] + node _T_1696 = or(_T_1687, _T_1695) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[1][0][8] <= _T_1696 @[ifu_bp_ctl.scala 536:27] + node _T_1697 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 536:41] + node _T_1698 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1699 = eq(_T_1698, UInt<4>("h09")) @[ifu_bp_ctl.scala 536:97] + node _T_1700 = and(_T_1697, _T_1699) @[ifu_bp_ctl.scala 536:45] + node _T_1701 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1702 = eq(_T_1701, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1703 = or(_T_1702, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1704 = and(_T_1700, _T_1703) @[ifu_bp_ctl.scala 536:110] + node _T_1705 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 537:18] + node _T_1706 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1707 = eq(_T_1706, UInt<4>("h09")) @[ifu_bp_ctl.scala 537:74] + node _T_1708 = and(_T_1705, _T_1707) @[ifu_bp_ctl.scala 537:22] + node _T_1709 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1710 = eq(_T_1709, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1711 = or(_T_1710, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1712 = and(_T_1708, _T_1711) @[ifu_bp_ctl.scala 537:87] + node _T_1713 = or(_T_1704, _T_1712) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[1][0][9] <= _T_1713 @[ifu_bp_ctl.scala 536:27] + node _T_1714 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 536:41] + node _T_1715 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1716 = eq(_T_1715, UInt<4>("h0a")) @[ifu_bp_ctl.scala 536:97] + node _T_1717 = and(_T_1714, _T_1716) @[ifu_bp_ctl.scala 536:45] + node _T_1718 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1719 = eq(_T_1718, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1720 = or(_T_1719, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1721 = and(_T_1717, _T_1720) @[ifu_bp_ctl.scala 536:110] + node _T_1722 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 537:18] + node _T_1723 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1724 = eq(_T_1723, UInt<4>("h0a")) @[ifu_bp_ctl.scala 537:74] + node _T_1725 = and(_T_1722, _T_1724) @[ifu_bp_ctl.scala 537:22] + node _T_1726 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1727 = eq(_T_1726, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1728 = or(_T_1727, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1729 = and(_T_1725, _T_1728) @[ifu_bp_ctl.scala 537:87] + node _T_1730 = or(_T_1721, _T_1729) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[1][0][10] <= _T_1730 @[ifu_bp_ctl.scala 536:27] + node _T_1731 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 536:41] + node _T_1732 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1733 = eq(_T_1732, UInt<4>("h0b")) @[ifu_bp_ctl.scala 536:97] + node _T_1734 = and(_T_1731, _T_1733) @[ifu_bp_ctl.scala 536:45] + node _T_1735 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1736 = eq(_T_1735, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1737 = or(_T_1736, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1738 = and(_T_1734, _T_1737) @[ifu_bp_ctl.scala 536:110] + node _T_1739 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 537:18] + node _T_1740 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1741 = eq(_T_1740, UInt<4>("h0b")) @[ifu_bp_ctl.scala 537:74] + node _T_1742 = and(_T_1739, _T_1741) @[ifu_bp_ctl.scala 537:22] + node _T_1743 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1744 = eq(_T_1743, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1745 = or(_T_1744, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1746 = and(_T_1742, _T_1745) @[ifu_bp_ctl.scala 537:87] + node _T_1747 = or(_T_1738, _T_1746) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[1][0][11] <= _T_1747 @[ifu_bp_ctl.scala 536:27] + node _T_1748 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 536:41] + node _T_1749 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1750 = eq(_T_1749, UInt<4>("h0c")) @[ifu_bp_ctl.scala 536:97] + node _T_1751 = and(_T_1748, _T_1750) @[ifu_bp_ctl.scala 536:45] + node _T_1752 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1753 = eq(_T_1752, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1754 = or(_T_1753, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1755 = and(_T_1751, _T_1754) @[ifu_bp_ctl.scala 536:110] + node _T_1756 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 537:18] + node _T_1757 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1758 = eq(_T_1757, UInt<4>("h0c")) @[ifu_bp_ctl.scala 537:74] + node _T_1759 = and(_T_1756, _T_1758) @[ifu_bp_ctl.scala 537:22] + node _T_1760 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1761 = eq(_T_1760, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1762 = or(_T_1761, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1763 = and(_T_1759, _T_1762) @[ifu_bp_ctl.scala 537:87] + node _T_1764 = or(_T_1755, _T_1763) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[1][0][12] <= _T_1764 @[ifu_bp_ctl.scala 536:27] + node _T_1765 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 536:41] + node _T_1766 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1767 = eq(_T_1766, UInt<4>("h0d")) @[ifu_bp_ctl.scala 536:97] + node _T_1768 = and(_T_1765, _T_1767) @[ifu_bp_ctl.scala 536:45] + node _T_1769 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1770 = eq(_T_1769, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1771 = or(_T_1770, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1772 = and(_T_1768, _T_1771) @[ifu_bp_ctl.scala 536:110] + node _T_1773 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 537:18] + node _T_1774 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1775 = eq(_T_1774, UInt<4>("h0d")) @[ifu_bp_ctl.scala 537:74] + node _T_1776 = and(_T_1773, _T_1775) @[ifu_bp_ctl.scala 537:22] + node _T_1777 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1778 = eq(_T_1777, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1779 = or(_T_1778, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1780 = and(_T_1776, _T_1779) @[ifu_bp_ctl.scala 537:87] + node _T_1781 = or(_T_1772, _T_1780) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[1][0][13] <= _T_1781 @[ifu_bp_ctl.scala 536:27] + node _T_1782 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 536:41] + node _T_1783 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1784 = eq(_T_1783, UInt<4>("h0e")) @[ifu_bp_ctl.scala 536:97] + node _T_1785 = and(_T_1782, _T_1784) @[ifu_bp_ctl.scala 536:45] + node _T_1786 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1787 = eq(_T_1786, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1788 = or(_T_1787, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1789 = and(_T_1785, _T_1788) @[ifu_bp_ctl.scala 536:110] + node _T_1790 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 537:18] + node _T_1791 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1792 = eq(_T_1791, UInt<4>("h0e")) @[ifu_bp_ctl.scala 537:74] + node _T_1793 = and(_T_1790, _T_1792) @[ifu_bp_ctl.scala 537:22] + node _T_1794 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1795 = eq(_T_1794, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1796 = or(_T_1795, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1797 = and(_T_1793, _T_1796) @[ifu_bp_ctl.scala 537:87] + node _T_1798 = or(_T_1789, _T_1797) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[1][0][14] <= _T_1798 @[ifu_bp_ctl.scala 536:27] + node _T_1799 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 536:41] + node _T_1800 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:60] + node _T_1801 = eq(_T_1800, UInt<4>("h0f")) @[ifu_bp_ctl.scala 536:97] + node _T_1802 = and(_T_1799, _T_1801) @[ifu_bp_ctl.scala 536:45] + node _T_1803 = bits(mp_hashed, 7, 0) @[ifu_bp_ctl.scala 536:126] + node _T_1804 = eq(_T_1803, UInt<1>("h00")) @[ifu_bp_ctl.scala 536:186] + node _T_1805 = or(_T_1804, UInt<1>("h01")) @[ifu_bp_ctl.scala 536:199] + node _T_1806 = and(_T_1802, _T_1805) @[ifu_bp_ctl.scala 536:110] + node _T_1807 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 537:18] + node _T_1808 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:37] + node _T_1809 = eq(_T_1808, UInt<4>("h0f")) @[ifu_bp_ctl.scala 537:74] + node _T_1810 = and(_T_1807, _T_1809) @[ifu_bp_ctl.scala 537:22] + node _T_1811 = bits(br0_hashed_wb, 7, 0) @[ifu_bp_ctl.scala 537:103] + node _T_1812 = eq(_T_1811, UInt<1>("h00")) @[ifu_bp_ctl.scala 537:163] + node _T_1813 = or(_T_1812, UInt<1>("h01")) @[ifu_bp_ctl.scala 537:176] + node _T_1814 = and(_T_1810, _T_1813) @[ifu_bp_ctl.scala 537:87] + node _T_1815 = or(_T_1806, _T_1814) @[ifu_bp_ctl.scala 536:223] + bht_bank_sel[1][0][15] <= _T_1815 @[ifu_bp_ctl.scala 536:27] + wire bht_bank_rd_data_out : UInt<2>[16][2] @[ifu_bp_ctl.scala 540:34] + node _T_1816 = and(bht_bank_sel[0][0][0], bht_bank_sel[0][0][0]) @[lib.scala 383:57] + reg _T_1817 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1816 : @[Reg.scala 28:19] + _T_1817 <= bht_bank_wr_data_0_0_0 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + bht_bank_rd_data_out[0][0] <= _T_1817 @[ifu_bp_ctl.scala 542:39] + node _T_1818 = and(bht_bank_sel[0][0][1], bht_bank_sel[0][0][1]) @[lib.scala 383:57] reg _T_1819 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1818 : @[Reg.scala 28:19] - _T_1819 <= bht_bank_wr_data_0_0_0 @[Reg.scala 28:23] + _T_1819 <= bht_bank_wr_data_0_0_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][0] <= _T_1819 @[ifu_bp_ctl.scala 535:39] - node _T_1820 = and(bht_bank_sel[0][0][1], bht_bank_sel[0][0][1]) @[lib.scala 383:57] + bht_bank_rd_data_out[0][1] <= _T_1819 @[ifu_bp_ctl.scala 542:39] + node _T_1820 = and(bht_bank_sel[0][0][2], bht_bank_sel[0][0][2]) @[lib.scala 383:57] reg _T_1821 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1820 : @[Reg.scala 28:19] - _T_1821 <= bht_bank_wr_data_0_0_1 @[Reg.scala 28:23] + _T_1821 <= bht_bank_wr_data_0_0_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][1] <= _T_1821 @[ifu_bp_ctl.scala 535:39] - node _T_1822 = and(bht_bank_sel[0][0][2], bht_bank_sel[0][0][2]) @[lib.scala 383:57] + bht_bank_rd_data_out[0][2] <= _T_1821 @[ifu_bp_ctl.scala 542:39] + node _T_1822 = and(bht_bank_sel[0][0][3], bht_bank_sel[0][0][3]) @[lib.scala 383:57] reg _T_1823 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1822 : @[Reg.scala 28:19] - _T_1823 <= bht_bank_wr_data_0_0_2 @[Reg.scala 28:23] + _T_1823 <= bht_bank_wr_data_0_0_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][2] <= _T_1823 @[ifu_bp_ctl.scala 535:39] - node _T_1824 = and(bht_bank_sel[0][0][3], bht_bank_sel[0][0][3]) @[lib.scala 383:57] + bht_bank_rd_data_out[0][3] <= _T_1823 @[ifu_bp_ctl.scala 542:39] + node _T_1824 = and(bht_bank_sel[0][0][4], bht_bank_sel[0][0][4]) @[lib.scala 383:57] reg _T_1825 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1824 : @[Reg.scala 28:19] - _T_1825 <= bht_bank_wr_data_0_0_3 @[Reg.scala 28:23] + _T_1825 <= bht_bank_wr_data_0_0_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][3] <= _T_1825 @[ifu_bp_ctl.scala 535:39] - node _T_1826 = and(bht_bank_sel[0][0][4], bht_bank_sel[0][0][4]) @[lib.scala 383:57] + bht_bank_rd_data_out[0][4] <= _T_1825 @[ifu_bp_ctl.scala 542:39] + node _T_1826 = and(bht_bank_sel[0][0][5], bht_bank_sel[0][0][5]) @[lib.scala 383:57] reg _T_1827 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1826 : @[Reg.scala 28:19] - _T_1827 <= bht_bank_wr_data_0_0_4 @[Reg.scala 28:23] + _T_1827 <= bht_bank_wr_data_0_0_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][4] <= _T_1827 @[ifu_bp_ctl.scala 535:39] - node _T_1828 = and(bht_bank_sel[0][0][5], bht_bank_sel[0][0][5]) @[lib.scala 383:57] + bht_bank_rd_data_out[0][5] <= _T_1827 @[ifu_bp_ctl.scala 542:39] + node _T_1828 = and(bht_bank_sel[0][0][6], bht_bank_sel[0][0][6]) @[lib.scala 383:57] reg _T_1829 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1828 : @[Reg.scala 28:19] - _T_1829 <= bht_bank_wr_data_0_0_5 @[Reg.scala 28:23] + _T_1829 <= bht_bank_wr_data_0_0_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][5] <= _T_1829 @[ifu_bp_ctl.scala 535:39] - node _T_1830 = and(bht_bank_sel[0][0][6], bht_bank_sel[0][0][6]) @[lib.scala 383:57] + bht_bank_rd_data_out[0][6] <= _T_1829 @[ifu_bp_ctl.scala 542:39] + node _T_1830 = and(bht_bank_sel[0][0][7], bht_bank_sel[0][0][7]) @[lib.scala 383:57] reg _T_1831 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1830 : @[Reg.scala 28:19] - _T_1831 <= bht_bank_wr_data_0_0_6 @[Reg.scala 28:23] + _T_1831 <= bht_bank_wr_data_0_0_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][6] <= _T_1831 @[ifu_bp_ctl.scala 535:39] - node _T_1832 = and(bht_bank_sel[0][0][7], bht_bank_sel[0][0][7]) @[lib.scala 383:57] + bht_bank_rd_data_out[0][7] <= _T_1831 @[ifu_bp_ctl.scala 542:39] + node _T_1832 = and(bht_bank_sel[0][0][8], bht_bank_sel[0][0][8]) @[lib.scala 383:57] reg _T_1833 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1832 : @[Reg.scala 28:19] - _T_1833 <= bht_bank_wr_data_0_0_7 @[Reg.scala 28:23] + _T_1833 <= bht_bank_wr_data_0_0_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][7] <= _T_1833 @[ifu_bp_ctl.scala 535:39] - node _T_1834 = and(bht_bank_sel[0][0][8], bht_bank_sel[0][0][8]) @[lib.scala 383:57] + bht_bank_rd_data_out[0][8] <= _T_1833 @[ifu_bp_ctl.scala 542:39] + node _T_1834 = and(bht_bank_sel[0][0][9], bht_bank_sel[0][0][9]) @[lib.scala 383:57] reg _T_1835 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1834 : @[Reg.scala 28:19] - _T_1835 <= bht_bank_wr_data_0_0_8 @[Reg.scala 28:23] + _T_1835 <= bht_bank_wr_data_0_0_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][8] <= _T_1835 @[ifu_bp_ctl.scala 535:39] - node _T_1836 = and(bht_bank_sel[0][0][9], bht_bank_sel[0][0][9]) @[lib.scala 383:57] + bht_bank_rd_data_out[0][9] <= _T_1835 @[ifu_bp_ctl.scala 542:39] + node _T_1836 = and(bht_bank_sel[0][0][10], bht_bank_sel[0][0][10]) @[lib.scala 383:57] reg _T_1837 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1836 : @[Reg.scala 28:19] - _T_1837 <= bht_bank_wr_data_0_0_9 @[Reg.scala 28:23] + _T_1837 <= bht_bank_wr_data_0_0_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][9] <= _T_1837 @[ifu_bp_ctl.scala 535:39] - node _T_1838 = and(bht_bank_sel[0][0][10], bht_bank_sel[0][0][10]) @[lib.scala 383:57] + bht_bank_rd_data_out[0][10] <= _T_1837 @[ifu_bp_ctl.scala 542:39] + node _T_1838 = and(bht_bank_sel[0][0][11], bht_bank_sel[0][0][11]) @[lib.scala 383:57] reg _T_1839 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1838 : @[Reg.scala 28:19] - _T_1839 <= bht_bank_wr_data_0_0_10 @[Reg.scala 28:23] + _T_1839 <= bht_bank_wr_data_0_0_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][10] <= _T_1839 @[ifu_bp_ctl.scala 535:39] - node _T_1840 = and(bht_bank_sel[0][0][11], bht_bank_sel[0][0][11]) @[lib.scala 383:57] + bht_bank_rd_data_out[0][11] <= _T_1839 @[ifu_bp_ctl.scala 542:39] + node _T_1840 = and(bht_bank_sel[0][0][12], bht_bank_sel[0][0][12]) @[lib.scala 383:57] reg _T_1841 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1840 : @[Reg.scala 28:19] - _T_1841 <= bht_bank_wr_data_0_0_11 @[Reg.scala 28:23] + _T_1841 <= bht_bank_wr_data_0_0_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][11] <= _T_1841 @[ifu_bp_ctl.scala 535:39] - node _T_1842 = and(bht_bank_sel[0][0][12], bht_bank_sel[0][0][12]) @[lib.scala 383:57] + bht_bank_rd_data_out[0][12] <= _T_1841 @[ifu_bp_ctl.scala 542:39] + node _T_1842 = and(bht_bank_sel[0][0][13], bht_bank_sel[0][0][13]) @[lib.scala 383:57] reg _T_1843 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1842 : @[Reg.scala 28:19] - _T_1843 <= bht_bank_wr_data_0_0_12 @[Reg.scala 28:23] + _T_1843 <= bht_bank_wr_data_0_0_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][12] <= _T_1843 @[ifu_bp_ctl.scala 535:39] - node _T_1844 = and(bht_bank_sel[0][0][13], bht_bank_sel[0][0][13]) @[lib.scala 383:57] + bht_bank_rd_data_out[0][13] <= _T_1843 @[ifu_bp_ctl.scala 542:39] + node _T_1844 = and(bht_bank_sel[0][0][14], bht_bank_sel[0][0][14]) @[lib.scala 383:57] reg _T_1845 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1844 : @[Reg.scala 28:19] - _T_1845 <= bht_bank_wr_data_0_0_13 @[Reg.scala 28:23] + _T_1845 <= bht_bank_wr_data_0_0_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][13] <= _T_1845 @[ifu_bp_ctl.scala 535:39] - node _T_1846 = and(bht_bank_sel[0][0][14], bht_bank_sel[0][0][14]) @[lib.scala 383:57] + bht_bank_rd_data_out[0][14] <= _T_1845 @[ifu_bp_ctl.scala 542:39] + node _T_1846 = and(bht_bank_sel[0][0][15], bht_bank_sel[0][0][15]) @[lib.scala 383:57] reg _T_1847 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1846 : @[Reg.scala 28:19] - _T_1847 <= bht_bank_wr_data_0_0_14 @[Reg.scala 28:23] + _T_1847 <= bht_bank_wr_data_0_0_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][14] <= _T_1847 @[ifu_bp_ctl.scala 535:39] - node _T_1848 = and(bht_bank_sel[0][0][15], bht_bank_sel[0][0][15]) @[lib.scala 383:57] + bht_bank_rd_data_out[0][15] <= _T_1847 @[ifu_bp_ctl.scala 542:39] + node _T_1848 = and(bht_bank_sel[1][0][0], bht_bank_sel[1][0][0]) @[lib.scala 383:57] reg _T_1849 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1848 : @[Reg.scala 28:19] - _T_1849 <= bht_bank_wr_data_0_0_15 @[Reg.scala 28:23] + _T_1849 <= bht_bank_wr_data_1_0_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][15] <= _T_1849 @[ifu_bp_ctl.scala 535:39] - node _T_1850 = and(bht_bank_sel[1][0][0], bht_bank_sel[1][0][0]) @[lib.scala 383:57] + bht_bank_rd_data_out[1][0] <= _T_1849 @[ifu_bp_ctl.scala 542:39] + node _T_1850 = and(bht_bank_sel[1][0][1], bht_bank_sel[1][0][1]) @[lib.scala 383:57] reg _T_1851 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1850 : @[Reg.scala 28:19] - _T_1851 <= bht_bank_wr_data_1_0_0 @[Reg.scala 28:23] + _T_1851 <= bht_bank_wr_data_1_0_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][0] <= _T_1851 @[ifu_bp_ctl.scala 535:39] - node _T_1852 = and(bht_bank_sel[1][0][1], bht_bank_sel[1][0][1]) @[lib.scala 383:57] + bht_bank_rd_data_out[1][1] <= _T_1851 @[ifu_bp_ctl.scala 542:39] + node _T_1852 = and(bht_bank_sel[1][0][2], bht_bank_sel[1][0][2]) @[lib.scala 383:57] reg _T_1853 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1852 : @[Reg.scala 28:19] - _T_1853 <= bht_bank_wr_data_1_0_1 @[Reg.scala 28:23] + _T_1853 <= bht_bank_wr_data_1_0_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][1] <= _T_1853 @[ifu_bp_ctl.scala 535:39] - node _T_1854 = and(bht_bank_sel[1][0][2], bht_bank_sel[1][0][2]) @[lib.scala 383:57] + bht_bank_rd_data_out[1][2] <= _T_1853 @[ifu_bp_ctl.scala 542:39] + node _T_1854 = and(bht_bank_sel[1][0][3], bht_bank_sel[1][0][3]) @[lib.scala 383:57] reg _T_1855 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1854 : @[Reg.scala 28:19] - _T_1855 <= bht_bank_wr_data_1_0_2 @[Reg.scala 28:23] + _T_1855 <= bht_bank_wr_data_1_0_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][2] <= _T_1855 @[ifu_bp_ctl.scala 535:39] - node _T_1856 = and(bht_bank_sel[1][0][3], bht_bank_sel[1][0][3]) @[lib.scala 383:57] + bht_bank_rd_data_out[1][3] <= _T_1855 @[ifu_bp_ctl.scala 542:39] + node _T_1856 = and(bht_bank_sel[1][0][4], bht_bank_sel[1][0][4]) @[lib.scala 383:57] reg _T_1857 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1856 : @[Reg.scala 28:19] - _T_1857 <= bht_bank_wr_data_1_0_3 @[Reg.scala 28:23] + _T_1857 <= bht_bank_wr_data_1_0_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][3] <= _T_1857 @[ifu_bp_ctl.scala 535:39] - node _T_1858 = and(bht_bank_sel[1][0][4], bht_bank_sel[1][0][4]) @[lib.scala 383:57] + bht_bank_rd_data_out[1][4] <= _T_1857 @[ifu_bp_ctl.scala 542:39] + node _T_1858 = and(bht_bank_sel[1][0][5], bht_bank_sel[1][0][5]) @[lib.scala 383:57] reg _T_1859 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1858 : @[Reg.scala 28:19] - _T_1859 <= bht_bank_wr_data_1_0_4 @[Reg.scala 28:23] + _T_1859 <= bht_bank_wr_data_1_0_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][4] <= _T_1859 @[ifu_bp_ctl.scala 535:39] - node _T_1860 = and(bht_bank_sel[1][0][5], bht_bank_sel[1][0][5]) @[lib.scala 383:57] + bht_bank_rd_data_out[1][5] <= _T_1859 @[ifu_bp_ctl.scala 542:39] + node _T_1860 = and(bht_bank_sel[1][0][6], bht_bank_sel[1][0][6]) @[lib.scala 383:57] reg _T_1861 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1860 : @[Reg.scala 28:19] - _T_1861 <= bht_bank_wr_data_1_0_5 @[Reg.scala 28:23] + _T_1861 <= bht_bank_wr_data_1_0_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][5] <= _T_1861 @[ifu_bp_ctl.scala 535:39] - node _T_1862 = and(bht_bank_sel[1][0][6], bht_bank_sel[1][0][6]) @[lib.scala 383:57] + bht_bank_rd_data_out[1][6] <= _T_1861 @[ifu_bp_ctl.scala 542:39] + node _T_1862 = and(bht_bank_sel[1][0][7], bht_bank_sel[1][0][7]) @[lib.scala 383:57] reg _T_1863 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1862 : @[Reg.scala 28:19] - _T_1863 <= bht_bank_wr_data_1_0_6 @[Reg.scala 28:23] + _T_1863 <= bht_bank_wr_data_1_0_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][6] <= _T_1863 @[ifu_bp_ctl.scala 535:39] - node _T_1864 = and(bht_bank_sel[1][0][7], bht_bank_sel[1][0][7]) @[lib.scala 383:57] + bht_bank_rd_data_out[1][7] <= _T_1863 @[ifu_bp_ctl.scala 542:39] + node _T_1864 = and(bht_bank_sel[1][0][8], bht_bank_sel[1][0][8]) @[lib.scala 383:57] reg _T_1865 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1864 : @[Reg.scala 28:19] - _T_1865 <= bht_bank_wr_data_1_0_7 @[Reg.scala 28:23] + _T_1865 <= bht_bank_wr_data_1_0_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][7] <= _T_1865 @[ifu_bp_ctl.scala 535:39] - node _T_1866 = and(bht_bank_sel[1][0][8], bht_bank_sel[1][0][8]) @[lib.scala 383:57] + bht_bank_rd_data_out[1][8] <= _T_1865 @[ifu_bp_ctl.scala 542:39] + node _T_1866 = and(bht_bank_sel[1][0][9], bht_bank_sel[1][0][9]) @[lib.scala 383:57] reg _T_1867 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1866 : @[Reg.scala 28:19] - _T_1867 <= bht_bank_wr_data_1_0_8 @[Reg.scala 28:23] + _T_1867 <= bht_bank_wr_data_1_0_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][8] <= _T_1867 @[ifu_bp_ctl.scala 535:39] - node _T_1868 = and(bht_bank_sel[1][0][9], bht_bank_sel[1][0][9]) @[lib.scala 383:57] + bht_bank_rd_data_out[1][9] <= _T_1867 @[ifu_bp_ctl.scala 542:39] + node _T_1868 = and(bht_bank_sel[1][0][10], bht_bank_sel[1][0][10]) @[lib.scala 383:57] reg _T_1869 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1868 : @[Reg.scala 28:19] - _T_1869 <= bht_bank_wr_data_1_0_9 @[Reg.scala 28:23] + _T_1869 <= bht_bank_wr_data_1_0_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][9] <= _T_1869 @[ifu_bp_ctl.scala 535:39] - node _T_1870 = and(bht_bank_sel[1][0][10], bht_bank_sel[1][0][10]) @[lib.scala 383:57] + bht_bank_rd_data_out[1][10] <= _T_1869 @[ifu_bp_ctl.scala 542:39] + node _T_1870 = and(bht_bank_sel[1][0][11], bht_bank_sel[1][0][11]) @[lib.scala 383:57] reg _T_1871 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1870 : @[Reg.scala 28:19] - _T_1871 <= bht_bank_wr_data_1_0_10 @[Reg.scala 28:23] + _T_1871 <= bht_bank_wr_data_1_0_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][10] <= _T_1871 @[ifu_bp_ctl.scala 535:39] - node _T_1872 = and(bht_bank_sel[1][0][11], bht_bank_sel[1][0][11]) @[lib.scala 383:57] + bht_bank_rd_data_out[1][11] <= _T_1871 @[ifu_bp_ctl.scala 542:39] + node _T_1872 = and(bht_bank_sel[1][0][12], bht_bank_sel[1][0][12]) @[lib.scala 383:57] reg _T_1873 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1872 : @[Reg.scala 28:19] - _T_1873 <= bht_bank_wr_data_1_0_11 @[Reg.scala 28:23] + _T_1873 <= bht_bank_wr_data_1_0_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][11] <= _T_1873 @[ifu_bp_ctl.scala 535:39] - node _T_1874 = and(bht_bank_sel[1][0][12], bht_bank_sel[1][0][12]) @[lib.scala 383:57] + bht_bank_rd_data_out[1][12] <= _T_1873 @[ifu_bp_ctl.scala 542:39] + node _T_1874 = and(bht_bank_sel[1][0][13], bht_bank_sel[1][0][13]) @[lib.scala 383:57] reg _T_1875 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1874 : @[Reg.scala 28:19] - _T_1875 <= bht_bank_wr_data_1_0_12 @[Reg.scala 28:23] + _T_1875 <= bht_bank_wr_data_1_0_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][12] <= _T_1875 @[ifu_bp_ctl.scala 535:39] - node _T_1876 = and(bht_bank_sel[1][0][13], bht_bank_sel[1][0][13]) @[lib.scala 383:57] + bht_bank_rd_data_out[1][13] <= _T_1875 @[ifu_bp_ctl.scala 542:39] + node _T_1876 = and(bht_bank_sel[1][0][14], bht_bank_sel[1][0][14]) @[lib.scala 383:57] reg _T_1877 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1876 : @[Reg.scala 28:19] - _T_1877 <= bht_bank_wr_data_1_0_13 @[Reg.scala 28:23] + _T_1877 <= bht_bank_wr_data_1_0_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][13] <= _T_1877 @[ifu_bp_ctl.scala 535:39] - node _T_1878 = and(bht_bank_sel[1][0][14], bht_bank_sel[1][0][14]) @[lib.scala 383:57] + bht_bank_rd_data_out[1][14] <= _T_1877 @[ifu_bp_ctl.scala 542:39] + node _T_1878 = and(bht_bank_sel[1][0][15], bht_bank_sel[1][0][15]) @[lib.scala 383:57] reg _T_1879 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1878 : @[Reg.scala 28:19] - _T_1879 <= bht_bank_wr_data_1_0_14 @[Reg.scala 28:23] + _T_1879 <= bht_bank_wr_data_1_0_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][14] <= _T_1879 @[ifu_bp_ctl.scala 535:39] - node _T_1880 = and(bht_bank_sel[1][0][15], bht_bank_sel[1][0][15]) @[lib.scala 383:57] - reg _T_1881 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_1880 : @[Reg.scala 28:19] - _T_1881 <= bht_bank_wr_data_1_0_15 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][15] <= _T_1881 @[ifu_bp_ctl.scala 535:39] - node _T_1882 = eq(bht_rd_addr_hashed_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 539:79] - node _T_1883 = bits(_T_1882, 0, 0) @[ifu_bp_ctl.scala 539:87] - node _T_1884 = eq(bht_rd_addr_hashed_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 539:79] - node _T_1885 = bits(_T_1884, 0, 0) @[ifu_bp_ctl.scala 539:87] - node _T_1886 = eq(bht_rd_addr_hashed_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 539:79] - node _T_1887 = bits(_T_1886, 0, 0) @[ifu_bp_ctl.scala 539:87] - node _T_1888 = eq(bht_rd_addr_hashed_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 539:79] - node _T_1889 = bits(_T_1888, 0, 0) @[ifu_bp_ctl.scala 539:87] - node _T_1890 = eq(bht_rd_addr_hashed_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 539:79] - node _T_1891 = bits(_T_1890, 0, 0) @[ifu_bp_ctl.scala 539:87] - node _T_1892 = eq(bht_rd_addr_hashed_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 539:79] - node _T_1893 = bits(_T_1892, 0, 0) @[ifu_bp_ctl.scala 539:87] - node _T_1894 = eq(bht_rd_addr_hashed_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 539:79] - node _T_1895 = bits(_T_1894, 0, 0) @[ifu_bp_ctl.scala 539:87] - node _T_1896 = eq(bht_rd_addr_hashed_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 539:79] - node _T_1897 = bits(_T_1896, 0, 0) @[ifu_bp_ctl.scala 539:87] - node _T_1898 = eq(bht_rd_addr_hashed_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 539:79] - node _T_1899 = bits(_T_1898, 0, 0) @[ifu_bp_ctl.scala 539:87] - node _T_1900 = eq(bht_rd_addr_hashed_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 539:79] - node _T_1901 = bits(_T_1900, 0, 0) @[ifu_bp_ctl.scala 539:87] - node _T_1902 = eq(bht_rd_addr_hashed_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 539:79] - node _T_1903 = bits(_T_1902, 0, 0) @[ifu_bp_ctl.scala 539:87] - node _T_1904 = eq(bht_rd_addr_hashed_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 539:79] - node _T_1905 = bits(_T_1904, 0, 0) @[ifu_bp_ctl.scala 539:87] - node _T_1906 = eq(bht_rd_addr_hashed_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 539:79] - node _T_1907 = bits(_T_1906, 0, 0) @[ifu_bp_ctl.scala 539:87] - node _T_1908 = eq(bht_rd_addr_hashed_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 539:79] - node _T_1909 = bits(_T_1908, 0, 0) @[ifu_bp_ctl.scala 539:87] - node _T_1910 = eq(bht_rd_addr_hashed_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 539:79] - node _T_1911 = bits(_T_1910, 0, 0) @[ifu_bp_ctl.scala 539:87] - node _T_1912 = eq(bht_rd_addr_hashed_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 539:79] - node _T_1913 = bits(_T_1912, 0, 0) @[ifu_bp_ctl.scala 539:87] - node _T_1914 = mux(_T_1883, bht_bank_rd_data_out[0][0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1915 = mux(_T_1885, bht_bank_rd_data_out[0][1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1916 = mux(_T_1887, bht_bank_rd_data_out[0][2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1917 = mux(_T_1889, bht_bank_rd_data_out[0][3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1918 = mux(_T_1891, bht_bank_rd_data_out[0][4], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1919 = mux(_T_1893, bht_bank_rd_data_out[0][5], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1920 = mux(_T_1895, bht_bank_rd_data_out[0][6], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1921 = mux(_T_1897, bht_bank_rd_data_out[0][7], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1922 = mux(_T_1899, bht_bank_rd_data_out[0][8], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1923 = mux(_T_1901, bht_bank_rd_data_out[0][9], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1924 = mux(_T_1903, bht_bank_rd_data_out[0][10], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1925 = mux(_T_1905, bht_bank_rd_data_out[0][11], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1926 = mux(_T_1907, bht_bank_rd_data_out[0][12], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1927 = mux(_T_1909, bht_bank_rd_data_out[0][13], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1928 = mux(_T_1911, bht_bank_rd_data_out[0][14], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1929 = mux(_T_1913, bht_bank_rd_data_out[0][15], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1930 = or(_T_1914, _T_1915) @[Mux.scala 27:72] + bht_bank_rd_data_out[1][15] <= _T_1879 @[ifu_bp_ctl.scala 542:39] + node _T_1880 = eq(bht_rd_addr_hashed_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 546:79] + node _T_1881 = bits(_T_1880, 0, 0) @[ifu_bp_ctl.scala 546:87] + node _T_1882 = eq(bht_rd_addr_hashed_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 546:79] + node _T_1883 = bits(_T_1882, 0, 0) @[ifu_bp_ctl.scala 546:87] + node _T_1884 = eq(bht_rd_addr_hashed_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 546:79] + node _T_1885 = bits(_T_1884, 0, 0) @[ifu_bp_ctl.scala 546:87] + node _T_1886 = eq(bht_rd_addr_hashed_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 546:79] + node _T_1887 = bits(_T_1886, 0, 0) @[ifu_bp_ctl.scala 546:87] + node _T_1888 = eq(bht_rd_addr_hashed_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 546:79] + node _T_1889 = bits(_T_1888, 0, 0) @[ifu_bp_ctl.scala 546:87] + node _T_1890 = eq(bht_rd_addr_hashed_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 546:79] + node _T_1891 = bits(_T_1890, 0, 0) @[ifu_bp_ctl.scala 546:87] + node _T_1892 = eq(bht_rd_addr_hashed_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 546:79] + node _T_1893 = bits(_T_1892, 0, 0) @[ifu_bp_ctl.scala 546:87] + node _T_1894 = eq(bht_rd_addr_hashed_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 546:79] + node _T_1895 = bits(_T_1894, 0, 0) @[ifu_bp_ctl.scala 546:87] + node _T_1896 = eq(bht_rd_addr_hashed_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 546:79] + node _T_1897 = bits(_T_1896, 0, 0) @[ifu_bp_ctl.scala 546:87] + node _T_1898 = eq(bht_rd_addr_hashed_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 546:79] + node _T_1899 = bits(_T_1898, 0, 0) @[ifu_bp_ctl.scala 546:87] + node _T_1900 = eq(bht_rd_addr_hashed_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 546:79] + node _T_1901 = bits(_T_1900, 0, 0) @[ifu_bp_ctl.scala 546:87] + node _T_1902 = eq(bht_rd_addr_hashed_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 546:79] + node _T_1903 = bits(_T_1902, 0, 0) @[ifu_bp_ctl.scala 546:87] + node _T_1904 = eq(bht_rd_addr_hashed_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 546:79] + node _T_1905 = bits(_T_1904, 0, 0) @[ifu_bp_ctl.scala 546:87] + node _T_1906 = eq(bht_rd_addr_hashed_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 546:79] + node _T_1907 = bits(_T_1906, 0, 0) @[ifu_bp_ctl.scala 546:87] + node _T_1908 = eq(bht_rd_addr_hashed_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 546:79] + node _T_1909 = bits(_T_1908, 0, 0) @[ifu_bp_ctl.scala 546:87] + node _T_1910 = eq(bht_rd_addr_hashed_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 546:79] + node _T_1911 = bits(_T_1910, 0, 0) @[ifu_bp_ctl.scala 546:87] + node _T_1912 = mux(_T_1881, bht_bank_rd_data_out[0][0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1913 = mux(_T_1883, bht_bank_rd_data_out[0][1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1914 = mux(_T_1885, bht_bank_rd_data_out[0][2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1915 = mux(_T_1887, bht_bank_rd_data_out[0][3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1916 = mux(_T_1889, bht_bank_rd_data_out[0][4], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1917 = mux(_T_1891, bht_bank_rd_data_out[0][5], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1918 = mux(_T_1893, bht_bank_rd_data_out[0][6], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1919 = mux(_T_1895, bht_bank_rd_data_out[0][7], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1920 = mux(_T_1897, bht_bank_rd_data_out[0][8], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1921 = mux(_T_1899, bht_bank_rd_data_out[0][9], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1922 = mux(_T_1901, bht_bank_rd_data_out[0][10], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1923 = mux(_T_1903, bht_bank_rd_data_out[0][11], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1924 = mux(_T_1905, bht_bank_rd_data_out[0][12], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1925 = mux(_T_1907, bht_bank_rd_data_out[0][13], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1926 = mux(_T_1909, bht_bank_rd_data_out[0][14], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1927 = mux(_T_1911, bht_bank_rd_data_out[0][15], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1928 = or(_T_1912, _T_1913) @[Mux.scala 27:72] + node _T_1929 = or(_T_1928, _T_1914) @[Mux.scala 27:72] + node _T_1930 = or(_T_1929, _T_1915) @[Mux.scala 27:72] node _T_1931 = or(_T_1930, _T_1916) @[Mux.scala 27:72] node _T_1932 = or(_T_1931, _T_1917) @[Mux.scala 27:72] node _T_1933 = or(_T_1932, _T_1918) @[Mux.scala 27:72] @@ -3851,60 +3852,60 @@ circuit ifu_bp_ctl : node _T_1940 = or(_T_1939, _T_1925) @[Mux.scala 27:72] node _T_1941 = or(_T_1940, _T_1926) @[Mux.scala 27:72] node _T_1942 = or(_T_1941, _T_1927) @[Mux.scala 27:72] - node _T_1943 = or(_T_1942, _T_1928) @[Mux.scala 27:72] - node _T_1944 = or(_T_1943, _T_1929) @[Mux.scala 27:72] - wire _T_1945 : UInt<2> @[Mux.scala 27:72] - _T_1945 <= _T_1944 @[Mux.scala 27:72] - bht_bank0_rd_data_f <= _T_1945 @[ifu_bp_ctl.scala 539:23] - node _T_1946 = eq(bht_rd_addr_hashed_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 540:79] - node _T_1947 = bits(_T_1946, 0, 0) @[ifu_bp_ctl.scala 540:87] - node _T_1948 = eq(bht_rd_addr_hashed_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 540:79] - node _T_1949 = bits(_T_1948, 0, 0) @[ifu_bp_ctl.scala 540:87] - node _T_1950 = eq(bht_rd_addr_hashed_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 540:79] - node _T_1951 = bits(_T_1950, 0, 0) @[ifu_bp_ctl.scala 540:87] - node _T_1952 = eq(bht_rd_addr_hashed_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 540:79] - node _T_1953 = bits(_T_1952, 0, 0) @[ifu_bp_ctl.scala 540:87] - node _T_1954 = eq(bht_rd_addr_hashed_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 540:79] - node _T_1955 = bits(_T_1954, 0, 0) @[ifu_bp_ctl.scala 540:87] - node _T_1956 = eq(bht_rd_addr_hashed_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 540:79] - node _T_1957 = bits(_T_1956, 0, 0) @[ifu_bp_ctl.scala 540:87] - node _T_1958 = eq(bht_rd_addr_hashed_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 540:79] - node _T_1959 = bits(_T_1958, 0, 0) @[ifu_bp_ctl.scala 540:87] - node _T_1960 = eq(bht_rd_addr_hashed_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 540:79] - node _T_1961 = bits(_T_1960, 0, 0) @[ifu_bp_ctl.scala 540:87] - node _T_1962 = eq(bht_rd_addr_hashed_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 540:79] - node _T_1963 = bits(_T_1962, 0, 0) @[ifu_bp_ctl.scala 540:87] - node _T_1964 = eq(bht_rd_addr_hashed_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 540:79] - node _T_1965 = bits(_T_1964, 0, 0) @[ifu_bp_ctl.scala 540:87] - node _T_1966 = eq(bht_rd_addr_hashed_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 540:79] - node _T_1967 = bits(_T_1966, 0, 0) @[ifu_bp_ctl.scala 540:87] - node _T_1968 = eq(bht_rd_addr_hashed_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 540:79] - node _T_1969 = bits(_T_1968, 0, 0) @[ifu_bp_ctl.scala 540:87] - node _T_1970 = eq(bht_rd_addr_hashed_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 540:79] - node _T_1971 = bits(_T_1970, 0, 0) @[ifu_bp_ctl.scala 540:87] - node _T_1972 = eq(bht_rd_addr_hashed_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 540:79] - node _T_1973 = bits(_T_1972, 0, 0) @[ifu_bp_ctl.scala 540:87] - node _T_1974 = eq(bht_rd_addr_hashed_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 540:79] - node _T_1975 = bits(_T_1974, 0, 0) @[ifu_bp_ctl.scala 540:87] - node _T_1976 = eq(bht_rd_addr_hashed_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 540:79] - node _T_1977 = bits(_T_1976, 0, 0) @[ifu_bp_ctl.scala 540:87] - node _T_1978 = mux(_T_1947, bht_bank_rd_data_out[1][0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1979 = mux(_T_1949, bht_bank_rd_data_out[1][1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1980 = mux(_T_1951, bht_bank_rd_data_out[1][2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1981 = mux(_T_1953, bht_bank_rd_data_out[1][3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1982 = mux(_T_1955, bht_bank_rd_data_out[1][4], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1983 = mux(_T_1957, bht_bank_rd_data_out[1][5], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1984 = mux(_T_1959, bht_bank_rd_data_out[1][6], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1985 = mux(_T_1961, bht_bank_rd_data_out[1][7], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1986 = mux(_T_1963, bht_bank_rd_data_out[1][8], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1987 = mux(_T_1965, bht_bank_rd_data_out[1][9], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1988 = mux(_T_1967, bht_bank_rd_data_out[1][10], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1989 = mux(_T_1969, bht_bank_rd_data_out[1][11], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1990 = mux(_T_1971, bht_bank_rd_data_out[1][12], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1991 = mux(_T_1973, bht_bank_rd_data_out[1][13], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1992 = mux(_T_1975, bht_bank_rd_data_out[1][14], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1993 = mux(_T_1977, bht_bank_rd_data_out[1][15], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1994 = or(_T_1978, _T_1979) @[Mux.scala 27:72] + wire _T_1943 : UInt<2> @[Mux.scala 27:72] + _T_1943 <= _T_1942 @[Mux.scala 27:72] + bht_bank0_rd_data_f <= _T_1943 @[ifu_bp_ctl.scala 546:23] + node _T_1944 = eq(bht_rd_addr_hashed_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 547:79] + node _T_1945 = bits(_T_1944, 0, 0) @[ifu_bp_ctl.scala 547:87] + node _T_1946 = eq(bht_rd_addr_hashed_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 547:79] + node _T_1947 = bits(_T_1946, 0, 0) @[ifu_bp_ctl.scala 547:87] + node _T_1948 = eq(bht_rd_addr_hashed_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 547:79] + node _T_1949 = bits(_T_1948, 0, 0) @[ifu_bp_ctl.scala 547:87] + node _T_1950 = eq(bht_rd_addr_hashed_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 547:79] + node _T_1951 = bits(_T_1950, 0, 0) @[ifu_bp_ctl.scala 547:87] + node _T_1952 = eq(bht_rd_addr_hashed_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 547:79] + node _T_1953 = bits(_T_1952, 0, 0) @[ifu_bp_ctl.scala 547:87] + node _T_1954 = eq(bht_rd_addr_hashed_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 547:79] + node _T_1955 = bits(_T_1954, 0, 0) @[ifu_bp_ctl.scala 547:87] + node _T_1956 = eq(bht_rd_addr_hashed_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 547:79] + node _T_1957 = bits(_T_1956, 0, 0) @[ifu_bp_ctl.scala 547:87] + node _T_1958 = eq(bht_rd_addr_hashed_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 547:79] + node _T_1959 = bits(_T_1958, 0, 0) @[ifu_bp_ctl.scala 547:87] + node _T_1960 = eq(bht_rd_addr_hashed_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 547:79] + node _T_1961 = bits(_T_1960, 0, 0) @[ifu_bp_ctl.scala 547:87] + node _T_1962 = eq(bht_rd_addr_hashed_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 547:79] + node _T_1963 = bits(_T_1962, 0, 0) @[ifu_bp_ctl.scala 547:87] + node _T_1964 = eq(bht_rd_addr_hashed_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 547:79] + node _T_1965 = bits(_T_1964, 0, 0) @[ifu_bp_ctl.scala 547:87] + node _T_1966 = eq(bht_rd_addr_hashed_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 547:79] + node _T_1967 = bits(_T_1966, 0, 0) @[ifu_bp_ctl.scala 547:87] + node _T_1968 = eq(bht_rd_addr_hashed_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 547:79] + node _T_1969 = bits(_T_1968, 0, 0) @[ifu_bp_ctl.scala 547:87] + node _T_1970 = eq(bht_rd_addr_hashed_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 547:79] + node _T_1971 = bits(_T_1970, 0, 0) @[ifu_bp_ctl.scala 547:87] + node _T_1972 = eq(bht_rd_addr_hashed_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 547:79] + node _T_1973 = bits(_T_1972, 0, 0) @[ifu_bp_ctl.scala 547:87] + node _T_1974 = eq(bht_rd_addr_hashed_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 547:79] + node _T_1975 = bits(_T_1974, 0, 0) @[ifu_bp_ctl.scala 547:87] + node _T_1976 = mux(_T_1945, bht_bank_rd_data_out[1][0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1977 = mux(_T_1947, bht_bank_rd_data_out[1][1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1978 = mux(_T_1949, bht_bank_rd_data_out[1][2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1979 = mux(_T_1951, bht_bank_rd_data_out[1][3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1980 = mux(_T_1953, bht_bank_rd_data_out[1][4], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1981 = mux(_T_1955, bht_bank_rd_data_out[1][5], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1982 = mux(_T_1957, bht_bank_rd_data_out[1][6], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1983 = mux(_T_1959, bht_bank_rd_data_out[1][7], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1984 = mux(_T_1961, bht_bank_rd_data_out[1][8], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1985 = mux(_T_1963, bht_bank_rd_data_out[1][9], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1986 = mux(_T_1965, bht_bank_rd_data_out[1][10], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1987 = mux(_T_1967, bht_bank_rd_data_out[1][11], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1988 = mux(_T_1969, bht_bank_rd_data_out[1][12], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1989 = mux(_T_1971, bht_bank_rd_data_out[1][13], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1990 = mux(_T_1973, bht_bank_rd_data_out[1][14], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1991 = mux(_T_1975, bht_bank_rd_data_out[1][15], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1992 = or(_T_1976, _T_1977) @[Mux.scala 27:72] + node _T_1993 = or(_T_1992, _T_1978) @[Mux.scala 27:72] + node _T_1994 = or(_T_1993, _T_1979) @[Mux.scala 27:72] node _T_1995 = or(_T_1994, _T_1980) @[Mux.scala 27:72] node _T_1996 = or(_T_1995, _T_1981) @[Mux.scala 27:72] node _T_1997 = or(_T_1996, _T_1982) @[Mux.scala 27:72] @@ -3917,60 +3918,60 @@ circuit ifu_bp_ctl : node _T_2004 = or(_T_2003, _T_1989) @[Mux.scala 27:72] node _T_2005 = or(_T_2004, _T_1990) @[Mux.scala 27:72] node _T_2006 = or(_T_2005, _T_1991) @[Mux.scala 27:72] - node _T_2007 = or(_T_2006, _T_1992) @[Mux.scala 27:72] - node _T_2008 = or(_T_2007, _T_1993) @[Mux.scala 27:72] - wire _T_2009 : UInt<2> @[Mux.scala 27:72] - _T_2009 <= _T_2008 @[Mux.scala 27:72] - bht_bank1_rd_data_f <= _T_2009 @[ifu_bp_ctl.scala 540:23] - node _T_2010 = eq(bht_rd_addr_hashed_p1_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 541:85] - node _T_2011 = bits(_T_2010, 0, 0) @[ifu_bp_ctl.scala 541:93] - node _T_2012 = eq(bht_rd_addr_hashed_p1_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 541:85] - node _T_2013 = bits(_T_2012, 0, 0) @[ifu_bp_ctl.scala 541:93] - node _T_2014 = eq(bht_rd_addr_hashed_p1_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 541:85] - node _T_2015 = bits(_T_2014, 0, 0) @[ifu_bp_ctl.scala 541:93] - node _T_2016 = eq(bht_rd_addr_hashed_p1_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 541:85] - node _T_2017 = bits(_T_2016, 0, 0) @[ifu_bp_ctl.scala 541:93] - node _T_2018 = eq(bht_rd_addr_hashed_p1_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 541:85] - node _T_2019 = bits(_T_2018, 0, 0) @[ifu_bp_ctl.scala 541:93] - node _T_2020 = eq(bht_rd_addr_hashed_p1_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 541:85] - node _T_2021 = bits(_T_2020, 0, 0) @[ifu_bp_ctl.scala 541:93] - node _T_2022 = eq(bht_rd_addr_hashed_p1_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 541:85] - node _T_2023 = bits(_T_2022, 0, 0) @[ifu_bp_ctl.scala 541:93] - node _T_2024 = eq(bht_rd_addr_hashed_p1_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 541:85] - node _T_2025 = bits(_T_2024, 0, 0) @[ifu_bp_ctl.scala 541:93] - node _T_2026 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 541:85] - node _T_2027 = bits(_T_2026, 0, 0) @[ifu_bp_ctl.scala 541:93] - node _T_2028 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 541:85] - node _T_2029 = bits(_T_2028, 0, 0) @[ifu_bp_ctl.scala 541:93] - node _T_2030 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 541:85] - node _T_2031 = bits(_T_2030, 0, 0) @[ifu_bp_ctl.scala 541:93] - node _T_2032 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 541:85] - node _T_2033 = bits(_T_2032, 0, 0) @[ifu_bp_ctl.scala 541:93] - node _T_2034 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 541:85] - node _T_2035 = bits(_T_2034, 0, 0) @[ifu_bp_ctl.scala 541:93] - node _T_2036 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 541:85] - node _T_2037 = bits(_T_2036, 0, 0) @[ifu_bp_ctl.scala 541:93] - node _T_2038 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 541:85] - node _T_2039 = bits(_T_2038, 0, 0) @[ifu_bp_ctl.scala 541:93] - node _T_2040 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 541:85] - node _T_2041 = bits(_T_2040, 0, 0) @[ifu_bp_ctl.scala 541:93] - node _T_2042 = mux(_T_2011, bht_bank_rd_data_out[0][0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2043 = mux(_T_2013, bht_bank_rd_data_out[0][1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2044 = mux(_T_2015, bht_bank_rd_data_out[0][2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2045 = mux(_T_2017, bht_bank_rd_data_out[0][3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2046 = mux(_T_2019, bht_bank_rd_data_out[0][4], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2047 = mux(_T_2021, bht_bank_rd_data_out[0][5], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2048 = mux(_T_2023, bht_bank_rd_data_out[0][6], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2049 = mux(_T_2025, bht_bank_rd_data_out[0][7], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2050 = mux(_T_2027, bht_bank_rd_data_out[0][8], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2051 = mux(_T_2029, bht_bank_rd_data_out[0][9], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2052 = mux(_T_2031, bht_bank_rd_data_out[0][10], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2053 = mux(_T_2033, bht_bank_rd_data_out[0][11], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2054 = mux(_T_2035, bht_bank_rd_data_out[0][12], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2055 = mux(_T_2037, bht_bank_rd_data_out[0][13], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2056 = mux(_T_2039, bht_bank_rd_data_out[0][14], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2057 = mux(_T_2041, bht_bank_rd_data_out[0][15], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2058 = or(_T_2042, _T_2043) @[Mux.scala 27:72] + wire _T_2007 : UInt<2> @[Mux.scala 27:72] + _T_2007 <= _T_2006 @[Mux.scala 27:72] + bht_bank1_rd_data_f <= _T_2007 @[ifu_bp_ctl.scala 547:23] + node _T_2008 = eq(bht_rd_addr_hashed_p1_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 548:85] + node _T_2009 = bits(_T_2008, 0, 0) @[ifu_bp_ctl.scala 548:93] + node _T_2010 = eq(bht_rd_addr_hashed_p1_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 548:85] + node _T_2011 = bits(_T_2010, 0, 0) @[ifu_bp_ctl.scala 548:93] + node _T_2012 = eq(bht_rd_addr_hashed_p1_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 548:85] + node _T_2013 = bits(_T_2012, 0, 0) @[ifu_bp_ctl.scala 548:93] + node _T_2014 = eq(bht_rd_addr_hashed_p1_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 548:85] + node _T_2015 = bits(_T_2014, 0, 0) @[ifu_bp_ctl.scala 548:93] + node _T_2016 = eq(bht_rd_addr_hashed_p1_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 548:85] + node _T_2017 = bits(_T_2016, 0, 0) @[ifu_bp_ctl.scala 548:93] + node _T_2018 = eq(bht_rd_addr_hashed_p1_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 548:85] + node _T_2019 = bits(_T_2018, 0, 0) @[ifu_bp_ctl.scala 548:93] + node _T_2020 = eq(bht_rd_addr_hashed_p1_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 548:85] + node _T_2021 = bits(_T_2020, 0, 0) @[ifu_bp_ctl.scala 548:93] + node _T_2022 = eq(bht_rd_addr_hashed_p1_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 548:85] + node _T_2023 = bits(_T_2022, 0, 0) @[ifu_bp_ctl.scala 548:93] + node _T_2024 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 548:85] + node _T_2025 = bits(_T_2024, 0, 0) @[ifu_bp_ctl.scala 548:93] + node _T_2026 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 548:85] + node _T_2027 = bits(_T_2026, 0, 0) @[ifu_bp_ctl.scala 548:93] + node _T_2028 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 548:85] + node _T_2029 = bits(_T_2028, 0, 0) @[ifu_bp_ctl.scala 548:93] + node _T_2030 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 548:85] + node _T_2031 = bits(_T_2030, 0, 0) @[ifu_bp_ctl.scala 548:93] + node _T_2032 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 548:85] + node _T_2033 = bits(_T_2032, 0, 0) @[ifu_bp_ctl.scala 548:93] + node _T_2034 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 548:85] + node _T_2035 = bits(_T_2034, 0, 0) @[ifu_bp_ctl.scala 548:93] + node _T_2036 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 548:85] + node _T_2037 = bits(_T_2036, 0, 0) @[ifu_bp_ctl.scala 548:93] + node _T_2038 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 548:85] + node _T_2039 = bits(_T_2038, 0, 0) @[ifu_bp_ctl.scala 548:93] + node _T_2040 = mux(_T_2009, bht_bank_rd_data_out[0][0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2041 = mux(_T_2011, bht_bank_rd_data_out[0][1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2042 = mux(_T_2013, bht_bank_rd_data_out[0][2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2043 = mux(_T_2015, bht_bank_rd_data_out[0][3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2044 = mux(_T_2017, bht_bank_rd_data_out[0][4], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2045 = mux(_T_2019, bht_bank_rd_data_out[0][5], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2046 = mux(_T_2021, bht_bank_rd_data_out[0][6], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2047 = mux(_T_2023, bht_bank_rd_data_out[0][7], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2048 = mux(_T_2025, bht_bank_rd_data_out[0][8], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2049 = mux(_T_2027, bht_bank_rd_data_out[0][9], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2050 = mux(_T_2029, bht_bank_rd_data_out[0][10], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2051 = mux(_T_2031, bht_bank_rd_data_out[0][11], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2052 = mux(_T_2033, bht_bank_rd_data_out[0][12], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2053 = mux(_T_2035, bht_bank_rd_data_out[0][13], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2054 = mux(_T_2037, bht_bank_rd_data_out[0][14], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2055 = mux(_T_2039, bht_bank_rd_data_out[0][15], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2056 = or(_T_2040, _T_2041) @[Mux.scala 27:72] + node _T_2057 = or(_T_2056, _T_2042) @[Mux.scala 27:72] + node _T_2058 = or(_T_2057, _T_2043) @[Mux.scala 27:72] node _T_2059 = or(_T_2058, _T_2044) @[Mux.scala 27:72] node _T_2060 = or(_T_2059, _T_2045) @[Mux.scala 27:72] node _T_2061 = or(_T_2060, _T_2046) @[Mux.scala 27:72] @@ -3983,9 +3984,7 @@ circuit ifu_bp_ctl : node _T_2068 = or(_T_2067, _T_2053) @[Mux.scala 27:72] node _T_2069 = or(_T_2068, _T_2054) @[Mux.scala 27:72] node _T_2070 = or(_T_2069, _T_2055) @[Mux.scala 27:72] - node _T_2071 = or(_T_2070, _T_2056) @[Mux.scala 27:72] - node _T_2072 = or(_T_2071, _T_2057) @[Mux.scala 27:72] - wire _T_2073 : UInt<2> @[Mux.scala 27:72] - _T_2073 <= _T_2072 @[Mux.scala 27:72] - bht_bank0_rd_data_p1_f <= _T_2073 @[ifu_bp_ctl.scala 541:26] + wire _T_2071 : UInt<2> @[Mux.scala 27:72] + _T_2071 <= _T_2070 @[Mux.scala 27:72] + bht_bank0_rd_data_p1_f <= _T_2071 @[ifu_bp_ctl.scala 548:26] diff --git a/ifu_bp_ctl.v b/ifu_bp_ctl.v index b7ec9645..8b3ac1e1 100644 --- a/ifu_bp_ctl.v +++ b/ifu_bp_ctl.v @@ -122,24 +122,8 @@ module ifu_bp_ctl( reg [31:0] _RAND_48; reg [31:0] _RAND_49; reg [31:0] _RAND_50; - reg [31:0] _RAND_51; + reg [255:0] _RAND_51; reg [31:0] _RAND_52; - reg [31:0] _RAND_53; - reg [31:0] _RAND_54; - reg [31:0] _RAND_55; - reg [31:0] _RAND_56; - reg [31:0] _RAND_57; - reg [31:0] _RAND_58; - reg [31:0] _RAND_59; - reg [31:0] _RAND_60; - reg [31:0] _RAND_61; - reg [31:0] _RAND_62; - reg [31:0] _RAND_63; - reg [31:0] _RAND_64; - reg [31:0] _RAND_65; - reg [31:0] _RAND_66; - reg [255:0] _RAND_67; - reg [31:0] _RAND_68; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_clk; // @[lib.scala 399:23] wire rvclkhdr_io_en; // @[lib.scala 399:23] @@ -245,433 +229,181 @@ module ifu_bp_ctl( wire [9:0] _T_580 = {btb_rd_addr_f,2'h0}; // @[Cat.scala 29:58] reg [7:0] fghr; // @[Reg.scala 27:20] wire [7:0] bht_rd_addr_hashed_f = _T_580[9:2] ^ fghr; // @[lib.scala 56:35] - wire _T_1946 = bht_rd_addr_hashed_f == 8'h0; // @[ifu_bp_ctl.scala 540:79] + wire _T_1944 = bht_rd_addr_hashed_f == 8'h0; // @[ifu_bp_ctl.scala 547:79] reg [1:0] bht_bank_rd_data_out_1_0; // @[Reg.scala 27:20] - wire [1:0] _T_1978 = _T_1946 ? bht_bank_rd_data_out_1_0 : 2'h0; // @[Mux.scala 27:72] - wire _T_1948 = bht_rd_addr_hashed_f == 8'h1; // @[ifu_bp_ctl.scala 540:79] + wire [1:0] _T_1976 = _T_1944 ? bht_bank_rd_data_out_1_0 : 2'h0; // @[Mux.scala 27:72] + wire _T_1946 = bht_rd_addr_hashed_f == 8'h1; // @[ifu_bp_ctl.scala 547:79] reg [1:0] bht_bank_rd_data_out_1_1; // @[Reg.scala 27:20] - wire [1:0] _T_1979 = _T_1948 ? bht_bank_rd_data_out_1_1 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_1994 = _T_1978 | _T_1979; // @[Mux.scala 27:72] - wire _T_1950 = bht_rd_addr_hashed_f == 8'h2; // @[ifu_bp_ctl.scala 540:79] + wire [1:0] _T_1977 = _T_1946 ? bht_bank_rd_data_out_1_1 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1992 = _T_1976 | _T_1977; // @[Mux.scala 27:72] + wire _T_1948 = bht_rd_addr_hashed_f == 8'h2; // @[ifu_bp_ctl.scala 547:79] reg [1:0] bht_bank_rd_data_out_1_2; // @[Reg.scala 27:20] - wire [1:0] _T_1980 = _T_1950 ? bht_bank_rd_data_out_1_2 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_1995 = _T_1994 | _T_1980; // @[Mux.scala 27:72] - wire _T_1952 = bht_rd_addr_hashed_f == 8'h3; // @[ifu_bp_ctl.scala 540:79] + wire [1:0] _T_1978 = _T_1948 ? bht_bank_rd_data_out_1_2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1993 = _T_1992 | _T_1978; // @[Mux.scala 27:72] + wire _T_1950 = bht_rd_addr_hashed_f == 8'h3; // @[ifu_bp_ctl.scala 547:79] reg [1:0] bht_bank_rd_data_out_1_3; // @[Reg.scala 27:20] - wire [1:0] _T_1981 = _T_1952 ? bht_bank_rd_data_out_1_3 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_1996 = _T_1995 | _T_1981; // @[Mux.scala 27:72] - wire _T_1954 = bht_rd_addr_hashed_f == 8'h4; // @[ifu_bp_ctl.scala 540:79] + wire [1:0] _T_1979 = _T_1950 ? bht_bank_rd_data_out_1_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1994 = _T_1993 | _T_1979; // @[Mux.scala 27:72] + wire _T_1952 = bht_rd_addr_hashed_f == 8'h4; // @[ifu_bp_ctl.scala 547:79] reg [1:0] bht_bank_rd_data_out_1_4; // @[Reg.scala 27:20] - wire [1:0] _T_1982 = _T_1954 ? bht_bank_rd_data_out_1_4 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_1997 = _T_1996 | _T_1982; // @[Mux.scala 27:72] - wire _T_1956 = bht_rd_addr_hashed_f == 8'h5; // @[ifu_bp_ctl.scala 540:79] + wire [1:0] _T_1980 = _T_1952 ? bht_bank_rd_data_out_1_4 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1995 = _T_1994 | _T_1980; // @[Mux.scala 27:72] + wire _T_1954 = bht_rd_addr_hashed_f == 8'h5; // @[ifu_bp_ctl.scala 547:79] reg [1:0] bht_bank_rd_data_out_1_5; // @[Reg.scala 27:20] - wire [1:0] _T_1983 = _T_1956 ? bht_bank_rd_data_out_1_5 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_1998 = _T_1997 | _T_1983; // @[Mux.scala 27:72] - wire _T_1958 = bht_rd_addr_hashed_f == 8'h6; // @[ifu_bp_ctl.scala 540:79] + wire [1:0] _T_1981 = _T_1954 ? bht_bank_rd_data_out_1_5 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1996 = _T_1995 | _T_1981; // @[Mux.scala 27:72] + wire _T_1956 = bht_rd_addr_hashed_f == 8'h6; // @[ifu_bp_ctl.scala 547:79] reg [1:0] bht_bank_rd_data_out_1_6; // @[Reg.scala 27:20] - wire [1:0] _T_1984 = _T_1958 ? bht_bank_rd_data_out_1_6 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_1999 = _T_1998 | _T_1984; // @[Mux.scala 27:72] - wire _T_1960 = bht_rd_addr_hashed_f == 8'h7; // @[ifu_bp_ctl.scala 540:79] + wire [1:0] _T_1982 = _T_1956 ? bht_bank_rd_data_out_1_6 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1997 = _T_1996 | _T_1982; // @[Mux.scala 27:72] + wire _T_1958 = bht_rd_addr_hashed_f == 8'h7; // @[ifu_bp_ctl.scala 547:79] reg [1:0] bht_bank_rd_data_out_1_7; // @[Reg.scala 27:20] - wire [1:0] _T_1985 = _T_1960 ? bht_bank_rd_data_out_1_7 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2000 = _T_1999 | _T_1985; // @[Mux.scala 27:72] - wire _T_1962 = bht_rd_addr_hashed_f == 8'h8; // @[ifu_bp_ctl.scala 540:79] + wire [1:0] _T_1983 = _T_1958 ? bht_bank_rd_data_out_1_7 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1998 = _T_1997 | _T_1983; // @[Mux.scala 27:72] + wire _T_1960 = bht_rd_addr_hashed_f == 8'h8; // @[ifu_bp_ctl.scala 547:79] reg [1:0] bht_bank_rd_data_out_1_8; // @[Reg.scala 27:20] - wire [1:0] _T_1986 = _T_1962 ? bht_bank_rd_data_out_1_8 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2001 = _T_2000 | _T_1986; // @[Mux.scala 27:72] - wire _T_1964 = bht_rd_addr_hashed_f == 8'h9; // @[ifu_bp_ctl.scala 540:79] + wire [1:0] _T_1984 = _T_1960 ? bht_bank_rd_data_out_1_8 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1999 = _T_1998 | _T_1984; // @[Mux.scala 27:72] + wire _T_1962 = bht_rd_addr_hashed_f == 8'h9; // @[ifu_bp_ctl.scala 547:79] reg [1:0] bht_bank_rd_data_out_1_9; // @[Reg.scala 27:20] - wire [1:0] _T_1987 = _T_1964 ? bht_bank_rd_data_out_1_9 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2002 = _T_2001 | _T_1987; // @[Mux.scala 27:72] - wire _T_1966 = bht_rd_addr_hashed_f == 8'ha; // @[ifu_bp_ctl.scala 540:79] + wire [1:0] _T_1985 = _T_1962 ? bht_bank_rd_data_out_1_9 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2000 = _T_1999 | _T_1985; // @[Mux.scala 27:72] + wire _T_1964 = bht_rd_addr_hashed_f == 8'ha; // @[ifu_bp_ctl.scala 547:79] reg [1:0] bht_bank_rd_data_out_1_10; // @[Reg.scala 27:20] - wire [1:0] _T_1988 = _T_1966 ? bht_bank_rd_data_out_1_10 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2003 = _T_2002 | _T_1988; // @[Mux.scala 27:72] - wire _T_1968 = bht_rd_addr_hashed_f == 8'hb; // @[ifu_bp_ctl.scala 540:79] + wire [1:0] _T_1986 = _T_1964 ? bht_bank_rd_data_out_1_10 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2001 = _T_2000 | _T_1986; // @[Mux.scala 27:72] + wire _T_1966 = bht_rd_addr_hashed_f == 8'hb; // @[ifu_bp_ctl.scala 547:79] reg [1:0] bht_bank_rd_data_out_1_11; // @[Reg.scala 27:20] - wire [1:0] _T_1989 = _T_1968 ? bht_bank_rd_data_out_1_11 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2004 = _T_2003 | _T_1989; // @[Mux.scala 27:72] - wire _T_1970 = bht_rd_addr_hashed_f == 8'hc; // @[ifu_bp_ctl.scala 540:79] + wire [1:0] _T_1987 = _T_1966 ? bht_bank_rd_data_out_1_11 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2002 = _T_2001 | _T_1987; // @[Mux.scala 27:72] + wire _T_1968 = bht_rd_addr_hashed_f == 8'hc; // @[ifu_bp_ctl.scala 547:79] reg [1:0] bht_bank_rd_data_out_1_12; // @[Reg.scala 27:20] - wire [1:0] _T_1990 = _T_1970 ? bht_bank_rd_data_out_1_12 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2005 = _T_2004 | _T_1990; // @[Mux.scala 27:72] - wire _T_1972 = bht_rd_addr_hashed_f == 8'hd; // @[ifu_bp_ctl.scala 540:79] + wire [1:0] _T_1988 = _T_1968 ? bht_bank_rd_data_out_1_12 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2003 = _T_2002 | _T_1988; // @[Mux.scala 27:72] + wire _T_1970 = bht_rd_addr_hashed_f == 8'hd; // @[ifu_bp_ctl.scala 547:79] reg [1:0] bht_bank_rd_data_out_1_13; // @[Reg.scala 27:20] - wire [1:0] _T_1991 = _T_1972 ? bht_bank_rd_data_out_1_13 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2006 = _T_2005 | _T_1991; // @[Mux.scala 27:72] - wire _T_1974 = bht_rd_addr_hashed_f == 8'he; // @[ifu_bp_ctl.scala 540:79] + wire [1:0] _T_1989 = _T_1970 ? bht_bank_rd_data_out_1_13 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2004 = _T_2003 | _T_1989; // @[Mux.scala 27:72] + wire _T_1972 = bht_rd_addr_hashed_f == 8'he; // @[ifu_bp_ctl.scala 547:79] reg [1:0] bht_bank_rd_data_out_1_14; // @[Reg.scala 27:20] - wire [1:0] _T_1992 = _T_1974 ? bht_bank_rd_data_out_1_14 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2007 = _T_2006 | _T_1992; // @[Mux.scala 27:72] - wire _T_1976 = bht_rd_addr_hashed_f == 8'hf; // @[ifu_bp_ctl.scala 540:79] + wire [1:0] _T_1990 = _T_1972 ? bht_bank_rd_data_out_1_14 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2005 = _T_2004 | _T_1990; // @[Mux.scala 27:72] + wire _T_1974 = bht_rd_addr_hashed_f == 8'hf; // @[ifu_bp_ctl.scala 547:79] reg [1:0] bht_bank_rd_data_out_1_15; // @[Reg.scala 27:20] - wire [1:0] _T_1993 = _T_1976 ? bht_bank_rd_data_out_1_15 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] bht_bank1_rd_data_f = _T_2007 | _T_1993; // @[Mux.scala 27:72] + wire [1:0] _T_1991 = _T_1974 ? bht_bank_rd_data_out_1_15 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] bht_bank1_rd_data_f = _T_2005 | _T_1991; // @[Mux.scala 27:72] wire [1:0] _T_251 = _T_248 ? bht_bank1_rd_data_f : 2'h0; // @[Mux.scala 27:72] wire [9:0] _T_583 = {btb_rd_addr_p1_f,2'h0}; // @[Cat.scala 29:58] wire [7:0] bht_rd_addr_hashed_p1_f = _T_583[9:2] ^ fghr; // @[lib.scala 56:35] - wire _T_2010 = bht_rd_addr_hashed_p1_f == 8'h0; // @[ifu_bp_ctl.scala 541:85] + wire _T_2008 = bht_rd_addr_hashed_p1_f == 8'h0; // @[ifu_bp_ctl.scala 548:85] reg [1:0] bht_bank_rd_data_out_0_0; // @[Reg.scala 27:20] - wire [1:0] _T_2042 = _T_2010 ? bht_bank_rd_data_out_0_0 : 2'h0; // @[Mux.scala 27:72] - wire _T_2012 = bht_rd_addr_hashed_p1_f == 8'h1; // @[ifu_bp_ctl.scala 541:85] + wire [1:0] _T_2040 = _T_2008 ? bht_bank_rd_data_out_0_0 : 2'h0; // @[Mux.scala 27:72] + wire _T_2010 = bht_rd_addr_hashed_p1_f == 8'h1; // @[ifu_bp_ctl.scala 548:85] reg [1:0] bht_bank_rd_data_out_0_1; // @[Reg.scala 27:20] - wire [1:0] _T_2043 = _T_2012 ? bht_bank_rd_data_out_0_1 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2058 = _T_2042 | _T_2043; // @[Mux.scala 27:72] - wire _T_2014 = bht_rd_addr_hashed_p1_f == 8'h2; // @[ifu_bp_ctl.scala 541:85] + wire [1:0] _T_2041 = _T_2010 ? bht_bank_rd_data_out_0_1 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2056 = _T_2040 | _T_2041; // @[Mux.scala 27:72] + wire _T_2012 = bht_rd_addr_hashed_p1_f == 8'h2; // @[ifu_bp_ctl.scala 548:85] reg [1:0] bht_bank_rd_data_out_0_2; // @[Reg.scala 27:20] - wire [1:0] _T_2044 = _T_2014 ? bht_bank_rd_data_out_0_2 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2059 = _T_2058 | _T_2044; // @[Mux.scala 27:72] - wire _T_2016 = bht_rd_addr_hashed_p1_f == 8'h3; // @[ifu_bp_ctl.scala 541:85] + wire [1:0] _T_2042 = _T_2012 ? bht_bank_rd_data_out_0_2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2057 = _T_2056 | _T_2042; // @[Mux.scala 27:72] + wire _T_2014 = bht_rd_addr_hashed_p1_f == 8'h3; // @[ifu_bp_ctl.scala 548:85] reg [1:0] bht_bank_rd_data_out_0_3; // @[Reg.scala 27:20] - wire [1:0] _T_2045 = _T_2016 ? bht_bank_rd_data_out_0_3 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2060 = _T_2059 | _T_2045; // @[Mux.scala 27:72] - wire _T_2018 = bht_rd_addr_hashed_p1_f == 8'h4; // @[ifu_bp_ctl.scala 541:85] + wire [1:0] _T_2043 = _T_2014 ? bht_bank_rd_data_out_0_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2058 = _T_2057 | _T_2043; // @[Mux.scala 27:72] + wire _T_2016 = bht_rd_addr_hashed_p1_f == 8'h4; // @[ifu_bp_ctl.scala 548:85] reg [1:0] bht_bank_rd_data_out_0_4; // @[Reg.scala 27:20] - wire [1:0] _T_2046 = _T_2018 ? bht_bank_rd_data_out_0_4 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2061 = _T_2060 | _T_2046; // @[Mux.scala 27:72] - wire _T_2020 = bht_rd_addr_hashed_p1_f == 8'h5; // @[ifu_bp_ctl.scala 541:85] + wire [1:0] _T_2044 = _T_2016 ? bht_bank_rd_data_out_0_4 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2059 = _T_2058 | _T_2044; // @[Mux.scala 27:72] + wire _T_2018 = bht_rd_addr_hashed_p1_f == 8'h5; // @[ifu_bp_ctl.scala 548:85] reg [1:0] bht_bank_rd_data_out_0_5; // @[Reg.scala 27:20] - wire [1:0] _T_2047 = _T_2020 ? bht_bank_rd_data_out_0_5 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2062 = _T_2061 | _T_2047; // @[Mux.scala 27:72] - wire _T_2022 = bht_rd_addr_hashed_p1_f == 8'h6; // @[ifu_bp_ctl.scala 541:85] + wire [1:0] _T_2045 = _T_2018 ? bht_bank_rd_data_out_0_5 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2060 = _T_2059 | _T_2045; // @[Mux.scala 27:72] + wire _T_2020 = bht_rd_addr_hashed_p1_f == 8'h6; // @[ifu_bp_ctl.scala 548:85] reg [1:0] bht_bank_rd_data_out_0_6; // @[Reg.scala 27:20] - wire [1:0] _T_2048 = _T_2022 ? bht_bank_rd_data_out_0_6 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2063 = _T_2062 | _T_2048; // @[Mux.scala 27:72] - wire _T_2024 = bht_rd_addr_hashed_p1_f == 8'h7; // @[ifu_bp_ctl.scala 541:85] + wire [1:0] _T_2046 = _T_2020 ? bht_bank_rd_data_out_0_6 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2061 = _T_2060 | _T_2046; // @[Mux.scala 27:72] + wire _T_2022 = bht_rd_addr_hashed_p1_f == 8'h7; // @[ifu_bp_ctl.scala 548:85] reg [1:0] bht_bank_rd_data_out_0_7; // @[Reg.scala 27:20] - wire [1:0] _T_2049 = _T_2024 ? bht_bank_rd_data_out_0_7 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2064 = _T_2063 | _T_2049; // @[Mux.scala 27:72] - wire _T_2026 = bht_rd_addr_hashed_p1_f == 8'h8; // @[ifu_bp_ctl.scala 541:85] + wire [1:0] _T_2047 = _T_2022 ? bht_bank_rd_data_out_0_7 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2062 = _T_2061 | _T_2047; // @[Mux.scala 27:72] + wire _T_2024 = bht_rd_addr_hashed_p1_f == 8'h8; // @[ifu_bp_ctl.scala 548:85] reg [1:0] bht_bank_rd_data_out_0_8; // @[Reg.scala 27:20] - wire [1:0] _T_2050 = _T_2026 ? bht_bank_rd_data_out_0_8 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2065 = _T_2064 | _T_2050; // @[Mux.scala 27:72] - wire _T_2028 = bht_rd_addr_hashed_p1_f == 8'h9; // @[ifu_bp_ctl.scala 541:85] + wire [1:0] _T_2048 = _T_2024 ? bht_bank_rd_data_out_0_8 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2063 = _T_2062 | _T_2048; // @[Mux.scala 27:72] + wire _T_2026 = bht_rd_addr_hashed_p1_f == 8'h9; // @[ifu_bp_ctl.scala 548:85] reg [1:0] bht_bank_rd_data_out_0_9; // @[Reg.scala 27:20] - wire [1:0] _T_2051 = _T_2028 ? bht_bank_rd_data_out_0_9 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2066 = _T_2065 | _T_2051; // @[Mux.scala 27:72] - wire _T_2030 = bht_rd_addr_hashed_p1_f == 8'ha; // @[ifu_bp_ctl.scala 541:85] + wire [1:0] _T_2049 = _T_2026 ? bht_bank_rd_data_out_0_9 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2064 = _T_2063 | _T_2049; // @[Mux.scala 27:72] + wire _T_2028 = bht_rd_addr_hashed_p1_f == 8'ha; // @[ifu_bp_ctl.scala 548:85] reg [1:0] bht_bank_rd_data_out_0_10; // @[Reg.scala 27:20] - wire [1:0] _T_2052 = _T_2030 ? bht_bank_rd_data_out_0_10 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2067 = _T_2066 | _T_2052; // @[Mux.scala 27:72] - wire _T_2032 = bht_rd_addr_hashed_p1_f == 8'hb; // @[ifu_bp_ctl.scala 541:85] + wire [1:0] _T_2050 = _T_2028 ? bht_bank_rd_data_out_0_10 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2065 = _T_2064 | _T_2050; // @[Mux.scala 27:72] + wire _T_2030 = bht_rd_addr_hashed_p1_f == 8'hb; // @[ifu_bp_ctl.scala 548:85] reg [1:0] bht_bank_rd_data_out_0_11; // @[Reg.scala 27:20] - wire [1:0] _T_2053 = _T_2032 ? bht_bank_rd_data_out_0_11 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2068 = _T_2067 | _T_2053; // @[Mux.scala 27:72] - wire _T_2034 = bht_rd_addr_hashed_p1_f == 8'hc; // @[ifu_bp_ctl.scala 541:85] + wire [1:0] _T_2051 = _T_2030 ? bht_bank_rd_data_out_0_11 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2066 = _T_2065 | _T_2051; // @[Mux.scala 27:72] + wire _T_2032 = bht_rd_addr_hashed_p1_f == 8'hc; // @[ifu_bp_ctl.scala 548:85] reg [1:0] bht_bank_rd_data_out_0_12; // @[Reg.scala 27:20] - wire [1:0] _T_2054 = _T_2034 ? bht_bank_rd_data_out_0_12 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2069 = _T_2068 | _T_2054; // @[Mux.scala 27:72] - wire _T_2036 = bht_rd_addr_hashed_p1_f == 8'hd; // @[ifu_bp_ctl.scala 541:85] + wire [1:0] _T_2052 = _T_2032 ? bht_bank_rd_data_out_0_12 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2067 = _T_2066 | _T_2052; // @[Mux.scala 27:72] + wire _T_2034 = bht_rd_addr_hashed_p1_f == 8'hd; // @[ifu_bp_ctl.scala 548:85] reg [1:0] bht_bank_rd_data_out_0_13; // @[Reg.scala 27:20] - wire [1:0] _T_2055 = _T_2036 ? bht_bank_rd_data_out_0_13 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2070 = _T_2069 | _T_2055; // @[Mux.scala 27:72] - wire _T_2038 = bht_rd_addr_hashed_p1_f == 8'he; // @[ifu_bp_ctl.scala 541:85] + wire [1:0] _T_2053 = _T_2034 ? bht_bank_rd_data_out_0_13 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2068 = _T_2067 | _T_2053; // @[Mux.scala 27:72] + wire _T_2036 = bht_rd_addr_hashed_p1_f == 8'he; // @[ifu_bp_ctl.scala 548:85] reg [1:0] bht_bank_rd_data_out_0_14; // @[Reg.scala 27:20] - wire [1:0] _T_2056 = _T_2038 ? bht_bank_rd_data_out_0_14 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_2071 = _T_2070 | _T_2056; // @[Mux.scala 27:72] - wire _T_2040 = bht_rd_addr_hashed_p1_f == 8'hf; // @[ifu_bp_ctl.scala 541:85] + wire [1:0] _T_2054 = _T_2036 ? bht_bank_rd_data_out_0_14 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_2069 = _T_2068 | _T_2054; // @[Mux.scala 27:72] + wire _T_2038 = bht_rd_addr_hashed_p1_f == 8'hf; // @[ifu_bp_ctl.scala 548:85] reg [1:0] bht_bank_rd_data_out_0_15; // @[Reg.scala 27:20] - wire [1:0] _T_2057 = _T_2040 ? bht_bank_rd_data_out_0_15 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] bht_bank0_rd_data_p1_f = _T_2071 | _T_2057; // @[Mux.scala 27:72] + wire [1:0] _T_2055 = _T_2038 ? bht_bank_rd_data_out_0_15 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] bht_bank0_rd_data_p1_f = _T_2069 | _T_2055; // @[Mux.scala 27:72] wire [1:0] _T_252 = io_ifc_fetch_addr_f[0] ? bht_bank0_rd_data_p1_f : 2'h0; // @[Mux.scala 27:72] wire [1:0] bht_vbank1_rd_data_f = _T_251 | _T_252; // @[Mux.scala 27:72] - wire [1:0] _T_599 = io_ifc_fetch_addr_f[0] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_708 = btb_rd_addr_f == 8'h0; // @[ifu_bp_ctl.scala 445:80] - reg [21:0] btb_bank0_rd_data_way0_out_0; // @[Reg.scala 27:20] - wire [21:0] _T_740 = _T_708 ? btb_bank0_rd_data_way0_out_0 : 22'h0; // @[Mux.scala 27:72] - wire _T_710 = btb_rd_addr_f == 8'h1; // @[ifu_bp_ctl.scala 445:80] - reg [21:0] btb_bank0_rd_data_way0_out_1; // @[Reg.scala 27:20] - wire [21:0] _T_741 = _T_710 ? btb_bank0_rd_data_way0_out_1 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_756 = _T_740 | _T_741; // @[Mux.scala 27:72] - wire _T_712 = btb_rd_addr_f == 8'h2; // @[ifu_bp_ctl.scala 445:80] - reg [21:0] btb_bank0_rd_data_way0_out_2; // @[Reg.scala 27:20] - wire [21:0] _T_742 = _T_712 ? btb_bank0_rd_data_way0_out_2 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_757 = _T_756 | _T_742; // @[Mux.scala 27:72] - wire _T_714 = btb_rd_addr_f == 8'h3; // @[ifu_bp_ctl.scala 445:80] - reg [21:0] btb_bank0_rd_data_way0_out_3; // @[Reg.scala 27:20] - wire [21:0] _T_743 = _T_714 ? btb_bank0_rd_data_way0_out_3 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_758 = _T_757 | _T_743; // @[Mux.scala 27:72] - wire _T_716 = btb_rd_addr_f == 8'h4; // @[ifu_bp_ctl.scala 445:80] - reg [21:0] btb_bank0_rd_data_way0_out_4; // @[Reg.scala 27:20] - wire [21:0] _T_744 = _T_716 ? btb_bank0_rd_data_way0_out_4 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_759 = _T_758 | _T_744; // @[Mux.scala 27:72] - wire _T_718 = btb_rd_addr_f == 8'h5; // @[ifu_bp_ctl.scala 445:80] - reg [21:0] btb_bank0_rd_data_way0_out_5; // @[Reg.scala 27:20] - wire [21:0] _T_745 = _T_718 ? btb_bank0_rd_data_way0_out_5 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_760 = _T_759 | _T_745; // @[Mux.scala 27:72] - wire _T_720 = btb_rd_addr_f == 8'h6; // @[ifu_bp_ctl.scala 445:80] - reg [21:0] btb_bank0_rd_data_way0_out_6; // @[Reg.scala 27:20] - wire [21:0] _T_746 = _T_720 ? btb_bank0_rd_data_way0_out_6 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_761 = _T_760 | _T_746; // @[Mux.scala 27:72] - wire _T_722 = btb_rd_addr_f == 8'h7; // @[ifu_bp_ctl.scala 445:80] - reg [21:0] btb_bank0_rd_data_way0_out_7; // @[Reg.scala 27:20] - wire [21:0] _T_747 = _T_722 ? btb_bank0_rd_data_way0_out_7 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_762 = _T_761 | _T_747; // @[Mux.scala 27:72] - wire _T_724 = btb_rd_addr_f == 8'h8; // @[ifu_bp_ctl.scala 445:80] - reg [21:0] btb_bank0_rd_data_way0_out_8; // @[Reg.scala 27:20] - wire [21:0] _T_748 = _T_724 ? btb_bank0_rd_data_way0_out_8 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_763 = _T_762 | _T_748; // @[Mux.scala 27:72] - wire _T_726 = btb_rd_addr_f == 8'h9; // @[ifu_bp_ctl.scala 445:80] - reg [21:0] btb_bank0_rd_data_way0_out_9; // @[Reg.scala 27:20] - wire [21:0] _T_749 = _T_726 ? btb_bank0_rd_data_way0_out_9 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_764 = _T_763 | _T_749; // @[Mux.scala 27:72] - wire _T_728 = btb_rd_addr_f == 8'ha; // @[ifu_bp_ctl.scala 445:80] - reg [21:0] btb_bank0_rd_data_way0_out_10; // @[Reg.scala 27:20] - wire [21:0] _T_750 = _T_728 ? btb_bank0_rd_data_way0_out_10 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_765 = _T_764 | _T_750; // @[Mux.scala 27:72] - wire _T_730 = btb_rd_addr_f == 8'hb; // @[ifu_bp_ctl.scala 445:80] - reg [21:0] btb_bank0_rd_data_way0_out_11; // @[Reg.scala 27:20] - wire [21:0] _T_751 = _T_730 ? btb_bank0_rd_data_way0_out_11 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_766 = _T_765 | _T_751; // @[Mux.scala 27:72] - wire _T_732 = btb_rd_addr_f == 8'hc; // @[ifu_bp_ctl.scala 445:80] - reg [21:0] btb_bank0_rd_data_way0_out_12; // @[Reg.scala 27:20] - wire [21:0] _T_752 = _T_732 ? btb_bank0_rd_data_way0_out_12 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_767 = _T_766 | _T_752; // @[Mux.scala 27:72] - wire _T_734 = btb_rd_addr_f == 8'hd; // @[ifu_bp_ctl.scala 445:80] - reg [21:0] btb_bank0_rd_data_way0_out_13; // @[Reg.scala 27:20] - wire [21:0] _T_753 = _T_734 ? btb_bank0_rd_data_way0_out_13 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_768 = _T_767 | _T_753; // @[Mux.scala 27:72] - wire _T_736 = btb_rd_addr_f == 8'he; // @[ifu_bp_ctl.scala 445:80] - reg [21:0] btb_bank0_rd_data_way0_out_14; // @[Reg.scala 27:20] - wire [21:0] _T_754 = _T_736 ? btb_bank0_rd_data_way0_out_14 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_769 = _T_768 | _T_754; // @[Mux.scala 27:72] - wire _T_738 = btb_rd_addr_f == 8'hf; // @[ifu_bp_ctl.scala 445:80] - reg [21:0] btb_bank0_rd_data_way0_out_15; // @[Reg.scala 27:20] - wire [21:0] _T_755 = _T_738 ? btb_bank0_rd_data_way0_out_15 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] btb_bank0_rd_data_way0_f = _T_769 | _T_755; // @[Mux.scala 27:72] - wire [4:0] _T_29 = io_ifc_fetch_addr_f[13:9] ^ io_ifc_fetch_addr_f[18:14]; // @[lib.scala 42:111] - wire [4:0] fetch_rd_tag_f = _T_29 ^ io_ifc_fetch_addr_f[23:19]; // @[lib.scala 42:111] - wire _T_46 = btb_bank0_rd_data_way0_f[21:17] == fetch_rd_tag_f; // @[ifu_bp_ctl.scala 144:98] - wire _T_47 = btb_bank0_rd_data_way0_f[0] & _T_46; // @[ifu_bp_ctl.scala 144:55] - wire _T_19 = io_exu_bp_exu_i0_br_index_r == btb_rd_addr_f; // @[ifu_bp_ctl.scala 125:72] - wire branch_error_collision_f = dec_tlu_error_wb & _T_19; // @[ifu_bp_ctl.scala 125:51] - wire branch_error_bank_conflict_f = branch_error_collision_f & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 129:63] - wire _T_48 = io_dec_bp_dec_tlu_br0_r_pkt_bits_way & branch_error_bank_conflict_f; // @[ifu_bp_ctl.scala 145:22] - wire _T_49 = ~_T_48; // @[ifu_bp_ctl.scala 145:5] - wire _T_50 = _T_47 & _T_49; // @[ifu_bp_ctl.scala 144:118] - wire _T_51 = _T_50 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 145:54] - wire tag_match_way0_f = _T_51 & _T; // @[ifu_bp_ctl.scala 145:75] - wire _T_82 = btb_bank0_rd_data_way0_f[3] ^ btb_bank0_rd_data_way0_f[4]; // @[ifu_bp_ctl.scala 159:90] - wire _T_83 = tag_match_way0_f & _T_82; // @[ifu_bp_ctl.scala 159:56] - wire _T_87 = ~_T_82; // @[ifu_bp_ctl.scala 160:24] - wire _T_88 = tag_match_way0_f & _T_87; // @[ifu_bp_ctl.scala 160:22] - wire [1:0] tag_match_way0_expanded_f = {_T_83,_T_88}; // @[Cat.scala 29:58] - reg [21:0] btb_bank0_rd_data_way1_out_0; // @[Reg.scala 27:20] - wire [21:0] _T_804 = _T_708 ? btb_bank0_rd_data_way1_out_0 : 22'h0; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_1; // @[Reg.scala 27:20] - wire [21:0] _T_805 = _T_710 ? btb_bank0_rd_data_way1_out_1 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_820 = _T_804 | _T_805; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_2; // @[Reg.scala 27:20] - wire [21:0] _T_806 = _T_712 ? btb_bank0_rd_data_way1_out_2 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_821 = _T_820 | _T_806; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_3; // @[Reg.scala 27:20] - wire [21:0] _T_807 = _T_714 ? btb_bank0_rd_data_way1_out_3 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_822 = _T_821 | _T_807; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_4; // @[Reg.scala 27:20] - wire [21:0] _T_808 = _T_716 ? btb_bank0_rd_data_way1_out_4 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_823 = _T_822 | _T_808; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_5; // @[Reg.scala 27:20] - wire [21:0] _T_809 = _T_718 ? btb_bank0_rd_data_way1_out_5 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_824 = _T_823 | _T_809; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_6; // @[Reg.scala 27:20] - wire [21:0] _T_810 = _T_720 ? btb_bank0_rd_data_way1_out_6 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_825 = _T_824 | _T_810; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_7; // @[Reg.scala 27:20] - wire [21:0] _T_811 = _T_722 ? btb_bank0_rd_data_way1_out_7 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_826 = _T_825 | _T_811; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_8; // @[Reg.scala 27:20] - wire [21:0] _T_812 = _T_724 ? btb_bank0_rd_data_way1_out_8 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_827 = _T_826 | _T_812; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_9; // @[Reg.scala 27:20] - wire [21:0] _T_813 = _T_726 ? btb_bank0_rd_data_way1_out_9 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_828 = _T_827 | _T_813; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_10; // @[Reg.scala 27:20] - wire [21:0] _T_814 = _T_728 ? btb_bank0_rd_data_way1_out_10 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_829 = _T_828 | _T_814; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_11; // @[Reg.scala 27:20] - wire [21:0] _T_815 = _T_730 ? btb_bank0_rd_data_way1_out_11 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_830 = _T_829 | _T_815; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_12; // @[Reg.scala 27:20] - wire [21:0] _T_816 = _T_732 ? btb_bank0_rd_data_way1_out_12 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_831 = _T_830 | _T_816; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_13; // @[Reg.scala 27:20] - wire [21:0] _T_817 = _T_734 ? btb_bank0_rd_data_way1_out_13 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_832 = _T_831 | _T_817; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_14; // @[Reg.scala 27:20] - wire [21:0] _T_818 = _T_736 ? btb_bank0_rd_data_way1_out_14 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_833 = _T_832 | _T_818; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_15; // @[Reg.scala 27:20] - wire [21:0] _T_819 = _T_738 ? btb_bank0_rd_data_way1_out_15 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] btb_bank0_rd_data_way1_f = _T_833 | _T_819; // @[Mux.scala 27:72] - wire _T_55 = btb_bank0_rd_data_way1_f[21:17] == fetch_rd_tag_f; // @[ifu_bp_ctl.scala 148:98] - wire _T_56 = btb_bank0_rd_data_way1_f[0] & _T_55; // @[ifu_bp_ctl.scala 148:55] - wire _T_59 = _T_56 & _T_49; // @[ifu_bp_ctl.scala 148:118] - wire _T_60 = _T_59 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 149:54] - wire tag_match_way1_f = _T_60 & _T; // @[ifu_bp_ctl.scala 149:75] - wire _T_91 = btb_bank0_rd_data_way1_f[3] ^ btb_bank0_rd_data_way1_f[4]; // @[ifu_bp_ctl.scala 162:90] - wire _T_92 = tag_match_way1_f & _T_91; // @[ifu_bp_ctl.scala 162:56] - wire _T_96 = ~_T_91; // @[ifu_bp_ctl.scala 163:24] - wire _T_97 = tag_match_way1_f & _T_96; // @[ifu_bp_ctl.scala 163:22] - wire [1:0] tag_match_way1_expanded_f = {_T_92,_T_97}; // @[Cat.scala 29:58] - wire [1:0] wayhit_f = tag_match_way0_expanded_f | tag_match_way1_expanded_f; // @[ifu_bp_ctl.scala 172:41] - wire [1:0] _T_601 = _T_599 & wayhit_f; // @[ifu_bp_ctl.scala 440:48] - wire [1:0] _T_604 = io_ifc_fetch_addr_f[1] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_836 = btb_rd_addr_p1_f == 8'h0; // @[ifu_bp_ctl.scala 449:86] - wire [21:0] _T_868 = _T_836 ? btb_bank0_rd_data_way0_out_0 : 22'h0; // @[Mux.scala 27:72] - wire _T_838 = btb_rd_addr_p1_f == 8'h1; // @[ifu_bp_ctl.scala 449:86] - wire [21:0] _T_869 = _T_838 ? btb_bank0_rd_data_way0_out_1 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_884 = _T_868 | _T_869; // @[Mux.scala 27:72] - wire _T_840 = btb_rd_addr_p1_f == 8'h2; // @[ifu_bp_ctl.scala 449:86] - wire [21:0] _T_870 = _T_840 ? btb_bank0_rd_data_way0_out_2 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_885 = _T_884 | _T_870; // @[Mux.scala 27:72] - wire _T_842 = btb_rd_addr_p1_f == 8'h3; // @[ifu_bp_ctl.scala 449:86] - wire [21:0] _T_871 = _T_842 ? btb_bank0_rd_data_way0_out_3 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_886 = _T_885 | _T_871; // @[Mux.scala 27:72] - wire _T_844 = btb_rd_addr_p1_f == 8'h4; // @[ifu_bp_ctl.scala 449:86] - wire [21:0] _T_872 = _T_844 ? btb_bank0_rd_data_way0_out_4 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_887 = _T_886 | _T_872; // @[Mux.scala 27:72] - wire _T_846 = btb_rd_addr_p1_f == 8'h5; // @[ifu_bp_ctl.scala 449:86] - wire [21:0] _T_873 = _T_846 ? btb_bank0_rd_data_way0_out_5 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_888 = _T_887 | _T_873; // @[Mux.scala 27:72] - wire _T_848 = btb_rd_addr_p1_f == 8'h6; // @[ifu_bp_ctl.scala 449:86] - wire [21:0] _T_874 = _T_848 ? btb_bank0_rd_data_way0_out_6 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_889 = _T_888 | _T_874; // @[Mux.scala 27:72] - wire _T_850 = btb_rd_addr_p1_f == 8'h7; // @[ifu_bp_ctl.scala 449:86] - wire [21:0] _T_875 = _T_850 ? btb_bank0_rd_data_way0_out_7 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_890 = _T_889 | _T_875; // @[Mux.scala 27:72] - wire _T_852 = btb_rd_addr_p1_f == 8'h8; // @[ifu_bp_ctl.scala 449:86] - wire [21:0] _T_876 = _T_852 ? btb_bank0_rd_data_way0_out_8 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_891 = _T_890 | _T_876; // @[Mux.scala 27:72] - wire _T_854 = btb_rd_addr_p1_f == 8'h9; // @[ifu_bp_ctl.scala 449:86] - wire [21:0] _T_877 = _T_854 ? btb_bank0_rd_data_way0_out_9 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_892 = _T_891 | _T_877; // @[Mux.scala 27:72] - wire _T_856 = btb_rd_addr_p1_f == 8'ha; // @[ifu_bp_ctl.scala 449:86] - wire [21:0] _T_878 = _T_856 ? btb_bank0_rd_data_way0_out_10 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_893 = _T_892 | _T_878; // @[Mux.scala 27:72] - wire _T_858 = btb_rd_addr_p1_f == 8'hb; // @[ifu_bp_ctl.scala 449:86] - wire [21:0] _T_879 = _T_858 ? btb_bank0_rd_data_way0_out_11 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_894 = _T_893 | _T_879; // @[Mux.scala 27:72] - wire _T_860 = btb_rd_addr_p1_f == 8'hc; // @[ifu_bp_ctl.scala 449:86] - wire [21:0] _T_880 = _T_860 ? btb_bank0_rd_data_way0_out_12 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_895 = _T_894 | _T_880; // @[Mux.scala 27:72] - wire _T_862 = btb_rd_addr_p1_f == 8'hd; // @[ifu_bp_ctl.scala 449:86] - wire [21:0] _T_881 = _T_862 ? btb_bank0_rd_data_way0_out_13 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_896 = _T_895 | _T_881; // @[Mux.scala 27:72] - wire _T_864 = btb_rd_addr_p1_f == 8'he; // @[ifu_bp_ctl.scala 449:86] - wire [21:0] _T_882 = _T_864 ? btb_bank0_rd_data_way0_out_14 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_897 = _T_896 | _T_882; // @[Mux.scala 27:72] - wire _T_866 = btb_rd_addr_p1_f == 8'hf; // @[ifu_bp_ctl.scala 449:86] - wire [21:0] _T_883 = _T_866 ? btb_bank0_rd_data_way0_out_15 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] btb_bank0_rd_data_way0_p1_f = _T_897 | _T_883; // @[Mux.scala 27:72] - wire [4:0] _T_35 = _T_8[13:9] ^ _T_8[18:14]; // @[lib.scala 42:111] - wire [4:0] fetch_rd_tag_p1_f = _T_35 ^ _T_8[23:19]; // @[lib.scala 42:111] - wire _T_64 = btb_bank0_rd_data_way0_p1_f[21:17] == fetch_rd_tag_p1_f; // @[ifu_bp_ctl.scala 152:107] - wire _T_65 = btb_bank0_rd_data_way0_p1_f[0] & _T_64; // @[ifu_bp_ctl.scala 152:61] - wire _T_20 = io_exu_bp_exu_i0_br_index_r == btb_rd_addr_p1_f; // @[ifu_bp_ctl.scala 126:75] - wire branch_error_collision_p1_f = dec_tlu_error_wb & _T_20; // @[ifu_bp_ctl.scala 126:54] - wire branch_error_bank_conflict_p1_f = branch_error_collision_p1_f & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 130:69] - wire _T_66 = io_dec_bp_dec_tlu_br0_r_pkt_bits_way & branch_error_bank_conflict_p1_f; // @[ifu_bp_ctl.scala 153:22] - wire _T_67 = ~_T_66; // @[ifu_bp_ctl.scala 153:5] - wire _T_68 = _T_65 & _T_67; // @[ifu_bp_ctl.scala 152:130] - wire _T_69 = _T_68 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 153:57] - wire tag_match_way0_p1_f = _T_69 & _T; // @[ifu_bp_ctl.scala 153:78] - wire _T_100 = btb_bank0_rd_data_way0_p1_f[3] ^ btb_bank0_rd_data_way0_p1_f[4]; // @[ifu_bp_ctl.scala 165:99] - wire _T_101 = tag_match_way0_p1_f & _T_100; // @[ifu_bp_ctl.scala 165:62] - wire _T_105 = ~_T_100; // @[ifu_bp_ctl.scala 166:27] - wire _T_106 = tag_match_way0_p1_f & _T_105; // @[ifu_bp_ctl.scala 166:25] - wire [1:0] tag_match_way0_expanded_p1_f = {_T_101,_T_106}; // @[Cat.scala 29:58] - wire [21:0] _T_932 = _T_836 ? btb_bank0_rd_data_way1_out_0 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_933 = _T_838 ? btb_bank0_rd_data_way1_out_1 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_948 = _T_932 | _T_933; // @[Mux.scala 27:72] - wire [21:0] _T_934 = _T_840 ? btb_bank0_rd_data_way1_out_2 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_949 = _T_948 | _T_934; // @[Mux.scala 27:72] - wire [21:0] _T_935 = _T_842 ? btb_bank0_rd_data_way1_out_3 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_950 = _T_949 | _T_935; // @[Mux.scala 27:72] - wire [21:0] _T_936 = _T_844 ? btb_bank0_rd_data_way1_out_4 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_951 = _T_950 | _T_936; // @[Mux.scala 27:72] - wire [21:0] _T_937 = _T_846 ? btb_bank0_rd_data_way1_out_5 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_952 = _T_951 | _T_937; // @[Mux.scala 27:72] - wire [21:0] _T_938 = _T_848 ? btb_bank0_rd_data_way1_out_6 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_953 = _T_952 | _T_938; // @[Mux.scala 27:72] - wire [21:0] _T_939 = _T_850 ? btb_bank0_rd_data_way1_out_7 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_954 = _T_953 | _T_939; // @[Mux.scala 27:72] - wire [21:0] _T_940 = _T_852 ? btb_bank0_rd_data_way1_out_8 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_955 = _T_954 | _T_940; // @[Mux.scala 27:72] - wire [21:0] _T_941 = _T_854 ? btb_bank0_rd_data_way1_out_9 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_956 = _T_955 | _T_941; // @[Mux.scala 27:72] - wire [21:0] _T_942 = _T_856 ? btb_bank0_rd_data_way1_out_10 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_957 = _T_956 | _T_942; // @[Mux.scala 27:72] - wire [21:0] _T_943 = _T_858 ? btb_bank0_rd_data_way1_out_11 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_958 = _T_957 | _T_943; // @[Mux.scala 27:72] - wire [21:0] _T_944 = _T_860 ? btb_bank0_rd_data_way1_out_12 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_959 = _T_958 | _T_944; // @[Mux.scala 27:72] - wire [21:0] _T_945 = _T_862 ? btb_bank0_rd_data_way1_out_13 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_960 = _T_959 | _T_945; // @[Mux.scala 27:72] - wire [21:0] _T_946 = _T_864 ? btb_bank0_rd_data_way1_out_14 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] _T_961 = _T_960 | _T_946; // @[Mux.scala 27:72] - wire [21:0] _T_947 = _T_866 ? btb_bank0_rd_data_way1_out_15 : 22'h0; // @[Mux.scala 27:72] - wire [21:0] btb_bank0_rd_data_way1_p1_f = _T_961 | _T_947; // @[Mux.scala 27:72] - wire _T_73 = btb_bank0_rd_data_way1_p1_f[21:17] == fetch_rd_tag_p1_f; // @[ifu_bp_ctl.scala 155:107] - wire _T_74 = btb_bank0_rd_data_way1_p1_f[0] & _T_73; // @[ifu_bp_ctl.scala 155:61] - wire _T_77 = _T_74 & _T_67; // @[ifu_bp_ctl.scala 155:130] - wire _T_78 = _T_77 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 156:57] - wire tag_match_way1_p1_f = _T_78 & _T; // @[ifu_bp_ctl.scala 156:78] - wire _T_109 = btb_bank0_rd_data_way1_p1_f[3] ^ btb_bank0_rd_data_way1_p1_f[4]; // @[ifu_bp_ctl.scala 168:99] - wire _T_110 = tag_match_way1_p1_f & _T_109; // @[ifu_bp_ctl.scala 168:62] - wire _T_114 = ~_T_109; // @[ifu_bp_ctl.scala 169:27] - wire _T_115 = tag_match_way1_p1_f & _T_114; // @[ifu_bp_ctl.scala 169:25] - wire [1:0] tag_match_way1_expanded_p1_f = {_T_110,_T_115}; // @[Cat.scala 29:58] - wire [1:0] wayhit_p1_f = tag_match_way0_expanded_p1_f | tag_match_way1_expanded_p1_f; // @[ifu_bp_ctl.scala 174:47] - wire [1:0] _T_607 = {wayhit_p1_f[0],wayhit_f[1]}; // @[Cat.scala 29:58] - wire [1:0] _T_608 = _T_604 & _T_607; // @[ifu_bp_ctl.scala 440:100] - wire eoc_near = &io_ifc_fetch_addr_f[4:2]; // @[ifu_bp_ctl.scala 257:64] - wire _T_210 = ~eoc_near; // @[ifu_bp_ctl.scala 259:15] - wire [1:0] _T_212 = ~io_ifc_fetch_addr_f[1:0]; // @[ifu_bp_ctl.scala 259:28] - wire _T_213 = |_T_212; // @[ifu_bp_ctl.scala 259:58] - wire eoc_mask = _T_210 | _T_213; // @[ifu_bp_ctl.scala 259:25] - wire [1:0] _T_609 = {eoc_mask,1'h1}; // @[Cat.scala 29:58] - wire [1:0] _T_610 = _T_608 & _T_609; // @[ifu_bp_ctl.scala 440:135] - wire [1:0] vwayhit_f = _T_601 | _T_610; // @[ifu_bp_ctl.scala 440:65] - wire _T_258 = bht_vbank1_rd_data_f[1] & vwayhit_f[1]; // @[ifu_bp_ctl.scala 296:69] - wire [1:0] _T_1914 = _T_1946 ? bht_bank_rd_data_out_0_0 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_1915 = _T_1948 ? bht_bank_rd_data_out_0_1 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_1930 = _T_1914 | _T_1915; // @[Mux.scala 27:72] - wire [1:0] _T_1916 = _T_1950 ? bht_bank_rd_data_out_0_2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1912 = _T_1944 ? bht_bank_rd_data_out_0_0 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1913 = _T_1946 ? bht_bank_rd_data_out_0_1 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1928 = _T_1912 | _T_1913; // @[Mux.scala 27:72] + wire [1:0] _T_1914 = _T_1948 ? bht_bank_rd_data_out_0_2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1929 = _T_1928 | _T_1914; // @[Mux.scala 27:72] + wire [1:0] _T_1915 = _T_1950 ? bht_bank_rd_data_out_0_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1930 = _T_1929 | _T_1915; // @[Mux.scala 27:72] + wire [1:0] _T_1916 = _T_1952 ? bht_bank_rd_data_out_0_4 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1931 = _T_1930 | _T_1916; // @[Mux.scala 27:72] - wire [1:0] _T_1917 = _T_1952 ? bht_bank_rd_data_out_0_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1917 = _T_1954 ? bht_bank_rd_data_out_0_5 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1932 = _T_1931 | _T_1917; // @[Mux.scala 27:72] - wire [1:0] _T_1918 = _T_1954 ? bht_bank_rd_data_out_0_4 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1918 = _T_1956 ? bht_bank_rd_data_out_0_6 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1933 = _T_1932 | _T_1918; // @[Mux.scala 27:72] - wire [1:0] _T_1919 = _T_1956 ? bht_bank_rd_data_out_0_5 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1919 = _T_1958 ? bht_bank_rd_data_out_0_7 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1934 = _T_1933 | _T_1919; // @[Mux.scala 27:72] - wire [1:0] _T_1920 = _T_1958 ? bht_bank_rd_data_out_0_6 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1920 = _T_1960 ? bht_bank_rd_data_out_0_8 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1935 = _T_1934 | _T_1920; // @[Mux.scala 27:72] - wire [1:0] _T_1921 = _T_1960 ? bht_bank_rd_data_out_0_7 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1921 = _T_1962 ? bht_bank_rd_data_out_0_9 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1936 = _T_1935 | _T_1921; // @[Mux.scala 27:72] - wire [1:0] _T_1922 = _T_1962 ? bht_bank_rd_data_out_0_8 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1922 = _T_1964 ? bht_bank_rd_data_out_0_10 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1937 = _T_1936 | _T_1922; // @[Mux.scala 27:72] - wire [1:0] _T_1923 = _T_1964 ? bht_bank_rd_data_out_0_9 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1923 = _T_1966 ? bht_bank_rd_data_out_0_11 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1938 = _T_1937 | _T_1923; // @[Mux.scala 27:72] - wire [1:0] _T_1924 = _T_1966 ? bht_bank_rd_data_out_0_10 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1924 = _T_1968 ? bht_bank_rd_data_out_0_12 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1939 = _T_1938 | _T_1924; // @[Mux.scala 27:72] - wire [1:0] _T_1925 = _T_1968 ? bht_bank_rd_data_out_0_11 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1925 = _T_1970 ? bht_bank_rd_data_out_0_13 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1940 = _T_1939 | _T_1925; // @[Mux.scala 27:72] - wire [1:0] _T_1926 = _T_1970 ? bht_bank_rd_data_out_0_12 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1926 = _T_1972 ? bht_bank_rd_data_out_0_14 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1941 = _T_1940 | _T_1926; // @[Mux.scala 27:72] - wire [1:0] _T_1927 = _T_1972 ? bht_bank_rd_data_out_0_13 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_1942 = _T_1941 | _T_1927; // @[Mux.scala 27:72] - wire [1:0] _T_1928 = _T_1974 ? bht_bank_rd_data_out_0_14 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_1943 = _T_1942 | _T_1928; // @[Mux.scala 27:72] - wire [1:0] _T_1929 = _T_1976 ? bht_bank_rd_data_out_0_15 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] bht_bank0_rd_data_f = _T_1943 | _T_1929; // @[Mux.scala 27:72] + wire [1:0] _T_1927 = _T_1974 ? bht_bank_rd_data_out_0_15 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] bht_bank0_rd_data_f = _T_1941 | _T_1927; // @[Mux.scala 27:72] wire [1:0] _T_243 = _T_248 ? bht_bank0_rd_data_f : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_244 = io_ifc_fetch_addr_f[0] ? bht_bank1_rd_data_f : 2'h0; // @[Mux.scala 27:72] wire [1:0] bht_vbank0_rd_data_f = _T_243 | _T_244; // @[Mux.scala 27:72] - wire _T_263 = bht_vbank0_rd_data_f[1] & vwayhit_f[0]; // @[ifu_bp_ctl.scala 297:72] - wire [1:0] bht_dir_f = {_T_258,_T_263}; // @[Cat.scala 29:58] - wire _T_14 = ~bht_dir_f[0]; // @[ifu_bp_ctl.scala 119:23] - wire [1:0] btb_sel_f = {_T_14,bht_dir_f[0]}; // @[Cat.scala 29:58] + wire _T_19 = io_exu_bp_exu_i0_br_index_r == btb_rd_addr_f; // @[ifu_bp_ctl.scala 125:72] + wire branch_error_collision_f = dec_tlu_error_wb & _T_19; // @[ifu_bp_ctl.scala 125:51] + wire _T_20 = io_exu_bp_exu_i0_br_index_r == btb_rd_addr_p1_f; // @[ifu_bp_ctl.scala 126:75] + wire branch_error_collision_p1_f = dec_tlu_error_wb & _T_20; // @[ifu_bp_ctl.scala 126:54] + wire branch_error_bank_conflict_f = branch_error_collision_f & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 129:63] + wire branch_error_bank_conflict_p1_f = branch_error_collision_p1_f & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 130:69] + wire [4:0] _T_29 = io_ifc_fetch_addr_f[13:9] ^ io_ifc_fetch_addr_f[18:14]; // @[lib.scala 42:111] + wire [4:0] fetch_rd_tag_f = _T_29 ^ io_ifc_fetch_addr_f[23:19]; // @[lib.scala 42:111] + wire [4:0] _T_35 = _T_8[13:9] ^ _T_8[18:14]; // @[lib.scala 42:111] + wire [4:0] fetch_rd_tag_p1_f = _T_35 ^ _T_8[23:19]; // @[lib.scala 42:111] wire _T_36 = io_exu_bp_exu_mp_btag == fetch_rd_tag_f; // @[ifu_bp_ctl.scala 140:53] wire _T_37 = _T_36 & exu_mp_valid; // @[ifu_bp_ctl.scala 140:73] wire _T_38 = _T_37 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 140:88] @@ -682,7 +414,140 @@ module ifu_bp_ctl( wire _T_42 = _T_41 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 141:94] wire _T_43 = io_exu_bp_exu_mp_index == btb_rd_addr_p1_f; // @[ifu_bp_ctl.scala 141:130] wire fetch_mp_collision_p1_f = _T_42 & _T_43; // @[ifu_bp_ctl.scala 141:115] - wire [1:0] _T_151 = ~vwayhit_f; // @[ifu_bp_ctl.scala 194:44] + wire _T_706 = btb_rd_addr_f == 8'h0; // @[ifu_bp_ctl.scala 451:80] + wire _T_708 = btb_rd_addr_f == 8'h1; // @[ifu_bp_ctl.scala 451:80] + wire _T_710 = btb_rd_addr_f == 8'h2; // @[ifu_bp_ctl.scala 451:80] + wire _T_712 = btb_rd_addr_f == 8'h3; // @[ifu_bp_ctl.scala 451:80] + wire _T_714 = btb_rd_addr_f == 8'h4; // @[ifu_bp_ctl.scala 451:80] + wire _T_716 = btb_rd_addr_f == 8'h5; // @[ifu_bp_ctl.scala 451:80] + wire _T_718 = btb_rd_addr_f == 8'h6; // @[ifu_bp_ctl.scala 451:80] + wire _T_720 = btb_rd_addr_f == 8'h7; // @[ifu_bp_ctl.scala 451:80] + wire _T_722 = btb_rd_addr_f == 8'h8; // @[ifu_bp_ctl.scala 451:80] + wire _T_724 = btb_rd_addr_f == 8'h9; // @[ifu_bp_ctl.scala 451:80] + wire _T_726 = btb_rd_addr_f == 8'ha; // @[ifu_bp_ctl.scala 451:80] + wire _T_728 = btb_rd_addr_f == 8'hb; // @[ifu_bp_ctl.scala 451:80] + wire _T_730 = btb_rd_addr_f == 8'hc; // @[ifu_bp_ctl.scala 451:80] + wire _T_732 = btb_rd_addr_f == 8'hd; // @[ifu_bp_ctl.scala 451:80] + wire _T_734 = btb_rd_addr_f == 8'he; // @[ifu_bp_ctl.scala 451:80] + wire _T_736 = btb_rd_addr_f == 8'hf; // @[ifu_bp_ctl.scala 451:80] + wire _T_48 = io_dec_bp_dec_tlu_br0_r_pkt_bits_way & branch_error_bank_conflict_f; // @[ifu_bp_ctl.scala 145:22] + wire _T_49 = ~_T_48; // @[ifu_bp_ctl.scala 145:5] + reg [21:0] btb_bank0_rd_data_way1_out_0; // @[Reg.scala 27:20] + wire [21:0] _T_802 = _T_706 ? btb_bank0_rd_data_way1_out_0 : 22'h0; // @[Mux.scala 27:72] + reg [21:0] btb_bank0_rd_data_way1_out_1; // @[Reg.scala 27:20] + wire [21:0] _T_803 = _T_708 ? btb_bank0_rd_data_way1_out_1 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_818 = _T_802 | _T_803; // @[Mux.scala 27:72] + reg [21:0] btb_bank0_rd_data_way1_out_2; // @[Reg.scala 27:20] + wire [21:0] _T_804 = _T_710 ? btb_bank0_rd_data_way1_out_2 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_819 = _T_818 | _T_804; // @[Mux.scala 27:72] + reg [21:0] btb_bank0_rd_data_way1_out_3; // @[Reg.scala 27:20] + wire [21:0] _T_805 = _T_712 ? btb_bank0_rd_data_way1_out_3 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_820 = _T_819 | _T_805; // @[Mux.scala 27:72] + reg [21:0] btb_bank0_rd_data_way1_out_4; // @[Reg.scala 27:20] + wire [21:0] _T_806 = _T_714 ? btb_bank0_rd_data_way1_out_4 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_821 = _T_820 | _T_806; // @[Mux.scala 27:72] + reg [21:0] btb_bank0_rd_data_way1_out_5; // @[Reg.scala 27:20] + wire [21:0] _T_807 = _T_716 ? btb_bank0_rd_data_way1_out_5 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_822 = _T_821 | _T_807; // @[Mux.scala 27:72] + reg [21:0] btb_bank0_rd_data_way1_out_6; // @[Reg.scala 27:20] + wire [21:0] _T_808 = _T_718 ? btb_bank0_rd_data_way1_out_6 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_823 = _T_822 | _T_808; // @[Mux.scala 27:72] + reg [21:0] btb_bank0_rd_data_way1_out_7; // @[Reg.scala 27:20] + wire [21:0] _T_809 = _T_720 ? btb_bank0_rd_data_way1_out_7 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_824 = _T_823 | _T_809; // @[Mux.scala 27:72] + reg [21:0] btb_bank0_rd_data_way1_out_8; // @[Reg.scala 27:20] + wire [21:0] _T_810 = _T_722 ? btb_bank0_rd_data_way1_out_8 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_825 = _T_824 | _T_810; // @[Mux.scala 27:72] + reg [21:0] btb_bank0_rd_data_way1_out_9; // @[Reg.scala 27:20] + wire [21:0] _T_811 = _T_724 ? btb_bank0_rd_data_way1_out_9 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_826 = _T_825 | _T_811; // @[Mux.scala 27:72] + reg [21:0] btb_bank0_rd_data_way1_out_10; // @[Reg.scala 27:20] + wire [21:0] _T_812 = _T_726 ? btb_bank0_rd_data_way1_out_10 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_827 = _T_826 | _T_812; // @[Mux.scala 27:72] + reg [21:0] btb_bank0_rd_data_way1_out_11; // @[Reg.scala 27:20] + wire [21:0] _T_813 = _T_728 ? btb_bank0_rd_data_way1_out_11 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_828 = _T_827 | _T_813; // @[Mux.scala 27:72] + reg [21:0] btb_bank0_rd_data_way1_out_12; // @[Reg.scala 27:20] + wire [21:0] _T_814 = _T_730 ? btb_bank0_rd_data_way1_out_12 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_829 = _T_828 | _T_814; // @[Mux.scala 27:72] + reg [21:0] btb_bank0_rd_data_way1_out_13; // @[Reg.scala 27:20] + wire [21:0] _T_815 = _T_732 ? btb_bank0_rd_data_way1_out_13 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_830 = _T_829 | _T_815; // @[Mux.scala 27:72] + reg [21:0] btb_bank0_rd_data_way1_out_14; // @[Reg.scala 27:20] + wire [21:0] _T_816 = _T_734 ? btb_bank0_rd_data_way1_out_14 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_831 = _T_830 | _T_816; // @[Mux.scala 27:72] + reg [21:0] btb_bank0_rd_data_way1_out_15; // @[Reg.scala 27:20] + wire [21:0] _T_817 = _T_736 ? btb_bank0_rd_data_way1_out_15 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] btb_bank0_rd_data_way1_f = _T_831 | _T_817; // @[Mux.scala 27:72] + wire _T_55 = btb_bank0_rd_data_way1_f[21:17] == fetch_rd_tag_f; // @[ifu_bp_ctl.scala 148:98] + wire _T_56 = btb_bank0_rd_data_way1_f[0] & _T_55; // @[ifu_bp_ctl.scala 148:55] + wire _T_59 = _T_56 & _T_49; // @[ifu_bp_ctl.scala 148:118] + wire _T_60 = _T_59 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 149:54] + wire tag_match_way1_f = _T_60 & _T; // @[ifu_bp_ctl.scala 149:75] + wire _T_834 = btb_rd_addr_p1_f == 8'h0; // @[ifu_bp_ctl.scala 455:86] + wire _T_836 = btb_rd_addr_p1_f == 8'h1; // @[ifu_bp_ctl.scala 455:86] + wire _T_838 = btb_rd_addr_p1_f == 8'h2; // @[ifu_bp_ctl.scala 455:86] + wire _T_840 = btb_rd_addr_p1_f == 8'h3; // @[ifu_bp_ctl.scala 455:86] + wire _T_842 = btb_rd_addr_p1_f == 8'h4; // @[ifu_bp_ctl.scala 455:86] + wire _T_844 = btb_rd_addr_p1_f == 8'h5; // @[ifu_bp_ctl.scala 455:86] + wire _T_846 = btb_rd_addr_p1_f == 8'h6; // @[ifu_bp_ctl.scala 455:86] + wire _T_848 = btb_rd_addr_p1_f == 8'h7; // @[ifu_bp_ctl.scala 455:86] + wire _T_850 = btb_rd_addr_p1_f == 8'h8; // @[ifu_bp_ctl.scala 455:86] + wire _T_852 = btb_rd_addr_p1_f == 8'h9; // @[ifu_bp_ctl.scala 455:86] + wire _T_854 = btb_rd_addr_p1_f == 8'ha; // @[ifu_bp_ctl.scala 455:86] + wire _T_856 = btb_rd_addr_p1_f == 8'hb; // @[ifu_bp_ctl.scala 455:86] + wire _T_858 = btb_rd_addr_p1_f == 8'hc; // @[ifu_bp_ctl.scala 455:86] + wire _T_860 = btb_rd_addr_p1_f == 8'hd; // @[ifu_bp_ctl.scala 455:86] + wire _T_862 = btb_rd_addr_p1_f == 8'he; // @[ifu_bp_ctl.scala 455:86] + wire _T_864 = btb_rd_addr_p1_f == 8'hf; // @[ifu_bp_ctl.scala 455:86] + wire _T_66 = io_dec_bp_dec_tlu_br0_r_pkt_bits_way & branch_error_bank_conflict_p1_f; // @[ifu_bp_ctl.scala 153:22] + wire _T_67 = ~_T_66; // @[ifu_bp_ctl.scala 153:5] + wire [21:0] _T_930 = _T_834 ? btb_bank0_rd_data_way1_out_0 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_931 = _T_836 ? btb_bank0_rd_data_way1_out_1 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_946 = _T_930 | _T_931; // @[Mux.scala 27:72] + wire [21:0] _T_932 = _T_838 ? btb_bank0_rd_data_way1_out_2 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_947 = _T_946 | _T_932; // @[Mux.scala 27:72] + wire [21:0] _T_933 = _T_840 ? btb_bank0_rd_data_way1_out_3 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_948 = _T_947 | _T_933; // @[Mux.scala 27:72] + wire [21:0] _T_934 = _T_842 ? btb_bank0_rd_data_way1_out_4 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_949 = _T_948 | _T_934; // @[Mux.scala 27:72] + wire [21:0] _T_935 = _T_844 ? btb_bank0_rd_data_way1_out_5 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_950 = _T_949 | _T_935; // @[Mux.scala 27:72] + wire [21:0] _T_936 = _T_846 ? btb_bank0_rd_data_way1_out_6 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_951 = _T_950 | _T_936; // @[Mux.scala 27:72] + wire [21:0] _T_937 = _T_848 ? btb_bank0_rd_data_way1_out_7 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_952 = _T_951 | _T_937; // @[Mux.scala 27:72] + wire [21:0] _T_938 = _T_850 ? btb_bank0_rd_data_way1_out_8 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_953 = _T_952 | _T_938; // @[Mux.scala 27:72] + wire [21:0] _T_939 = _T_852 ? btb_bank0_rd_data_way1_out_9 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_954 = _T_953 | _T_939; // @[Mux.scala 27:72] + wire [21:0] _T_940 = _T_854 ? btb_bank0_rd_data_way1_out_10 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_955 = _T_954 | _T_940; // @[Mux.scala 27:72] + wire [21:0] _T_941 = _T_856 ? btb_bank0_rd_data_way1_out_11 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_956 = _T_955 | _T_941; // @[Mux.scala 27:72] + wire [21:0] _T_942 = _T_858 ? btb_bank0_rd_data_way1_out_12 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_957 = _T_956 | _T_942; // @[Mux.scala 27:72] + wire [21:0] _T_943 = _T_860 ? btb_bank0_rd_data_way1_out_13 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_958 = _T_957 | _T_943; // @[Mux.scala 27:72] + wire [21:0] _T_944 = _T_862 ? btb_bank0_rd_data_way1_out_14 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] _T_959 = _T_958 | _T_944; // @[Mux.scala 27:72] + wire [21:0] _T_945 = _T_864 ? btb_bank0_rd_data_way1_out_15 : 22'h0; // @[Mux.scala 27:72] + wire [21:0] btb_bank0_rd_data_way1_p1_f = _T_959 | _T_945; // @[Mux.scala 27:72] + wire _T_73 = btb_bank0_rd_data_way1_p1_f[21:17] == fetch_rd_tag_p1_f; // @[ifu_bp_ctl.scala 155:107] + wire _T_74 = btb_bank0_rd_data_way1_p1_f[0] & _T_73; // @[ifu_bp_ctl.scala 155:61] + wire _T_77 = _T_74 & _T_67; // @[ifu_bp_ctl.scala 155:130] + wire _T_78 = _T_77 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 156:57] + wire tag_match_way1_p1_f = _T_78 & _T; // @[ifu_bp_ctl.scala 156:78] + wire _T_91 = btb_bank0_rd_data_way1_f[3] ^ btb_bank0_rd_data_way1_f[4]; // @[ifu_bp_ctl.scala 162:90] + wire _T_92 = tag_match_way1_f & _T_91; // @[ifu_bp_ctl.scala 162:56] + wire _T_96 = ~_T_91; // @[ifu_bp_ctl.scala 163:24] + wire _T_97 = tag_match_way1_f & _T_96; // @[ifu_bp_ctl.scala 163:22] + wire [1:0] tag_match_way1_expanded_f = {_T_92,_T_97}; // @[Cat.scala 29:58] + wire _T_109 = btb_bank0_rd_data_way1_p1_f[3] ^ btb_bank0_rd_data_way1_p1_f[4]; // @[ifu_bp_ctl.scala 168:99] + wire _T_110 = tag_match_way1_p1_f & _T_109; // @[ifu_bp_ctl.scala 168:62] + wire _T_114 = ~_T_109; // @[ifu_bp_ctl.scala 169:27] + wire _T_115 = tag_match_way1_p1_f & _T_114; // @[ifu_bp_ctl.scala 169:25] + wire [1:0] tag_match_way1_expanded_p1_f = {_T_110,_T_115}; // @[Cat.scala 29:58] reg exu_mp_way_f; // @[Reg.scala 27:20] wire [255:0] fetch_wrindex_dec = 256'h1 << btb_rd_addr_f; // @[ifu_bp_ctl.scala 213:31] reg [255:0] _T_208; // @[Reg.scala 27:20] @@ -700,7 +565,6 @@ module ifu_bp_ctl( wire [1:0] _T_189 = {btb_lru_rd_p1_f,btb_lru_rd_f}; // @[Cat.scala 29:58] wire [1:0] _T_191 = io_ifc_fetch_addr_f[0] ? _T_189 : 2'h0; // @[Mux.scala 27:72] wire [1:0] btb_vlru_rd_f = _T_190 | _T_191; // @[Mux.scala 27:72] - wire [1:0] _T_152 = _T_151 & btb_vlru_rd_f; // @[ifu_bp_ctl.scala 194:55] wire [1:0] _T_202 = _T_248 ? tag_match_way1_expanded_f : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_201 = {tag_match_way1_expanded_p1_f[0],tag_match_way1_expanded_f[1]}; // @[Cat.scala 29:58] wire [1:0] _T_203 = io_ifc_fetch_addr_f[0] ? _T_201 : 2'h0; // @[Mux.scala 27:72] @@ -709,47 +573,14 @@ module ifu_bp_ctl( wire [15:0] _T_155 = exu_mp_valid ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] wire [255:0] _GEN_80 = {{240'd0}, _T_155}; // @[ifu_bp_ctl.scala 219:36] wire [255:0] mp_wrlru_b0 = mp_wrindex_dec & _GEN_80; // @[ifu_bp_ctl.scala 219:36] - wire _T_158 = vwayhit_f[0] | vwayhit_f[1]; // @[ifu_bp_ctl.scala 222:42] - wire _T_159 = _T_158 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 222:58] - wire lru_update_valid_f = _T_159 & _T; // @[ifu_bp_ctl.scala 222:79] - wire [15:0] _T_162 = lru_update_valid_f ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] - wire [255:0] _GEN_81 = {{240'd0}, _T_162}; // @[ifu_bp_ctl.scala 224:42] - wire [255:0] fetch_wrlru_b0 = fetch_wrindex_dec & _GEN_81; // @[ifu_bp_ctl.scala 224:42] - wire [255:0] fetch_wrlru_p1_b0 = fetch_wrindex_p1_dec & _GEN_81; // @[ifu_bp_ctl.scala 225:48] - wire [255:0] _T_165 = ~mp_wrlru_b0; // @[ifu_bp_ctl.scala 227:25] - wire [255:0] _T_166 = ~fetch_wrlru_b0; // @[ifu_bp_ctl.scala 227:40] - wire [255:0] btb_lru_b0_hold = _T_165 & _T_166; // @[ifu_bp_ctl.scala 227:38] + wire [255:0] btb_lru_b0_hold = ~mp_wrlru_b0; // @[ifu_bp_ctl.scala 227:25] wire _T_168 = ~io_exu_bp_exu_mp_pkt_bits_way; // @[ifu_bp_ctl.scala 234:39] wire [255:0] _T_171 = _T_168 ? mp_wrlru_b0 : 256'h0; // @[Mux.scala 27:72] - wire [255:0] _T_172 = tag_match_way0_f ? fetch_wrlru_b0 : 256'h0; // @[Mux.scala 27:72] - wire [255:0] _T_173 = tag_match_way0_p1_f ? fetch_wrlru_p1_b0 : 256'h0; // @[Mux.scala 27:72] - wire [255:0] _T_174 = _T_171 | _T_172; // @[Mux.scala 27:72] - wire [255:0] _T_175 = _T_174 | _T_173; // @[Mux.scala 27:72] wire [255:0] _T_177 = btb_lru_b0_hold & _GEN_78; // @[ifu_bp_ctl.scala 236:73] - wire [255:0] btb_lru_b0_ns = _T_175 | _T_177; // @[ifu_bp_ctl.scala 236:55] + wire [255:0] btb_lru_b0_ns = _T_171 | _T_177; // @[ifu_bp_ctl.scala 236:55] wire _T_206 = io_ifc_fetch_req_f | exu_mp_valid; // @[ifu_bp_ctl.scala 251:60] - wire [1:0] hist1_raw = {bht_vbank1_rd_data_f[1],bht_vbank0_rd_data_f[1]}; // @[Cat.scala 29:58] - wire [1:0] _T_225 = vwayhit_f & hist1_raw; // @[ifu_bp_ctl.scala 276:39] - wire _T_226 = |_T_225; // @[ifu_bp_ctl.scala 276:52] - wire _T_227 = _T_226 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 276:56] wire _T_228 = ~leak_one_f_d1; // @[ifu_bp_ctl.scala 276:79] - wire _T_229 = _T_227 & _T_228; // @[ifu_bp_ctl.scala 276:77] - wire _T_230 = ~io_dec_bp_dec_tlu_bpred_disable; // @[ifu_bp_ctl.scala 276:96] - wire _T_266 = io_ifu_bp_hit_taken_f & btb_sel_f[1]; // @[ifu_bp_ctl.scala 300:51] wire _T_267 = ~io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 300:69] - wire [1:0] num_valids = vwayhit_f[1] + vwayhit_f[0]; // @[ifu_bp_ctl.scala 317:35] - wire [1:0] _T_295 = btb_sel_f & bht_dir_f; // @[ifu_bp_ctl.scala 320:28] - wire final_h = |_T_295; // @[ifu_bp_ctl.scala 320:41] - wire _T_296 = num_valids == 2'h2; // @[ifu_bp_ctl.scala 324:41] - wire [7:0] _T_300 = {fghr[5:0],1'h0,final_h}; // @[Cat.scala 29:58] - wire _T_301 = num_valids == 2'h1; // @[ifu_bp_ctl.scala 325:41] - wire [7:0] _T_304 = {fghr[6:0],final_h}; // @[Cat.scala 29:58] - wire _T_305 = num_valids == 2'h0; // @[ifu_bp_ctl.scala 326:41] - wire [7:0] _T_308 = _T_296 ? _T_300 : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_309 = _T_301 ? _T_304 : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_310 = _T_305 ? fghr : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_311 = _T_308 | _T_309; // @[Mux.scala 27:72] - wire [7:0] merged_ghr = _T_311 | _T_310; // @[Mux.scala 27:72] reg exu_flush_final_d1; // @[Reg.scala 27:20] wire _T_314 = ~exu_flush_final_d1; // @[ifu_bp_ctl.scala 335:27] wire _T_315 = _T_314 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 335:47] @@ -760,7 +591,7 @@ module ifu_bp_ctl( wire _T_324 = ~_T_323; // @[ifu_bp_ctl.scala 336:49] wire _T_325 = _T_314 & _T_324; // @[ifu_bp_ctl.scala 336:47] wire [7:0] _T_327 = exu_flush_final_d1 ? io_exu_bp_exu_mp_fghr : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_328 = _T_318 ? merged_ghr : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_328 = _T_318 ? fghr : 8'h0; // @[Mux.scala 27:72] wire [7:0] _T_329 = _T_325 ? fghr : 8'h0; // @[Mux.scala 27:72] wire [7:0] _T_330 = _T_327 | _T_328; // @[Mux.scala 27:72] wire [7:0] fghr_ns = _T_330 | _T_329; // @[Mux.scala 27:72] @@ -772,221 +603,203 @@ module ifu_bp_ctl( wire _T_343 = |_T_342; // @[lib.scala 458:29] wire [7:0] _T_346 = fghr_ns ^ fghr; // @[lib.scala 436:21] wire _T_347 = |_T_346; // @[lib.scala 436:29] - wire [1:0] _T_350 = io_dec_bp_dec_tlu_bpred_disable ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_351 = ~_T_350; // @[ifu_bp_ctl.scala 348:36] - wire _T_550 = ~dec_tlu_error_wb; // @[ifu_bp_ctl.scala 395:35] - wire btb_valid = exu_mp_valid & _T_550; // @[ifu_bp_ctl.scala 395:32] - wire _T_551 = io_exu_bp_exu_mp_pkt_bits_pcall | io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 409:89] - wire _T_552 = io_exu_bp_exu_mp_pkt_bits_pret | io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 409:113] + wire _T_550 = ~dec_tlu_error_wb; // @[ifu_bp_ctl.scala 397:35] + wire btb_valid = exu_mp_valid & _T_550; // @[ifu_bp_ctl.scala 397:32] + wire _T_551 = io_exu_bp_exu_mp_pkt_bits_pcall | io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 411:89] + wire _T_552 = io_exu_bp_exu_mp_pkt_bits_pret | io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 411:113] wire [21:0] btb_wr_data = {io_exu_bp_exu_mp_btag,io_exu_bp_exu_mp_pkt_bits_toffset,io_exu_bp_exu_mp_pkt_bits_pc4,io_exu_bp_exu_mp_pkt_bits_boffset,_T_551,_T_552,btb_valid}; // @[Cat.scala 29:58] - wire _T_558 = exu_mp_valid & io_exu_bp_exu_mp_pkt_bits_ataken; // @[ifu_bp_ctl.scala 410:41] - wire _T_559 = ~io_exu_bp_exu_mp_pkt_valid; // @[ifu_bp_ctl.scala 410:59] - wire exu_mp_valid_write = _T_558 & _T_559; // @[ifu_bp_ctl.scala 410:57] - wire middle_of_bank = io_exu_bp_exu_mp_pkt_bits_pc4 ^ io_exu_bp_exu_mp_pkt_bits_boffset; // @[ifu_bp_ctl.scala 411:35] - wire _T_560 = ~io_exu_bp_exu_mp_pkt_bits_pcall; // @[ifu_bp_ctl.scala 414:43] - wire _T_561 = exu_mp_valid & _T_560; // @[ifu_bp_ctl.scala 414:41] - wire _T_562 = ~io_exu_bp_exu_mp_pkt_bits_pret; // @[ifu_bp_ctl.scala 414:58] - wire _T_563 = _T_561 & _T_562; // @[ifu_bp_ctl.scala 414:56] - wire _T_564 = ~io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 414:72] - wire _T_565 = _T_563 & _T_564; // @[ifu_bp_ctl.scala 414:70] + wire _T_558 = exu_mp_valid & io_exu_bp_exu_mp_pkt_bits_ataken; // @[ifu_bp_ctl.scala 412:41] + wire _T_559 = ~io_exu_bp_exu_mp_pkt_valid; // @[ifu_bp_ctl.scala 412:59] + wire exu_mp_valid_write = _T_558 & _T_559; // @[ifu_bp_ctl.scala 412:57] + wire middle_of_bank = io_exu_bp_exu_mp_pkt_bits_pc4 ^ io_exu_bp_exu_mp_pkt_bits_boffset; // @[ifu_bp_ctl.scala 413:35] + wire _T_560 = ~io_exu_bp_exu_mp_pkt_bits_pcall; // @[ifu_bp_ctl.scala 416:43] + wire _T_561 = exu_mp_valid & _T_560; // @[ifu_bp_ctl.scala 416:41] + wire _T_562 = ~io_exu_bp_exu_mp_pkt_bits_pret; // @[ifu_bp_ctl.scala 416:58] + wire _T_563 = _T_561 & _T_562; // @[ifu_bp_ctl.scala 416:56] + wire _T_564 = ~io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 416:72] + wire _T_565 = _T_563 & _T_564; // @[ifu_bp_ctl.scala 416:70] wire [1:0] _T_567 = _T_565 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_568 = ~middle_of_bank; // @[ifu_bp_ctl.scala 414:106] + wire _T_568 = ~middle_of_bank; // @[ifu_bp_ctl.scala 416:106] wire [1:0] _T_569 = {middle_of_bank,_T_568}; // @[Cat.scala 29:58] - wire [1:0] bht_wr_en0 = _T_567 & _T_569; // @[ifu_bp_ctl.scala 414:84] + wire [1:0] bht_wr_en0 = _T_567 & _T_569; // @[ifu_bp_ctl.scala 416:84] wire [1:0] _T_571 = io_dec_bp_dec_tlu_br0_r_pkt_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_572 = ~io_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[ifu_bp_ctl.scala 415:75] + wire _T_572 = ~io_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[ifu_bp_ctl.scala 417:75] wire [1:0] _T_573 = {io_dec_bp_dec_tlu_br0_r_pkt_bits_middle,_T_572}; // @[Cat.scala 29:58] - wire [1:0] bht_wr_en2 = _T_571 & _T_573; // @[ifu_bp_ctl.scala 415:46] + wire [1:0] bht_wr_en2 = _T_571 & _T_573; // @[ifu_bp_ctl.scala 417:46] wire [9:0] _T_574 = {io_exu_bp_exu_mp_index,2'h0}; // @[Cat.scala 29:58] wire [7:0] mp_hashed = _T_574[9:2] ^ io_exu_bp_exu_mp_eghr; // @[lib.scala 56:35] wire [9:0] _T_577 = {io_exu_bp_exu_i0_br_index_r,2'h0}; // @[Cat.scala 29:58] wire [7:0] br0_hashed_wb = _T_577[9:2] ^ io_exu_bp_exu_i0_br_fghr_r; // @[lib.scala 56:35] - wire _T_587 = _T_168 & exu_mp_valid_write; // @[ifu_bp_ctl.scala 434:39] - wire _T_589 = _T_587 & _T_550; // @[ifu_bp_ctl.scala 434:60] - wire _T_590 = ~io_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[ifu_bp_ctl.scala 434:87] - wire _T_591 = _T_590 & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 434:104] - wire btb_wr_en_way0 = _T_589 | _T_591; // @[ifu_bp_ctl.scala 434:83] - wire _T_592 = io_exu_bp_exu_mp_pkt_bits_way & exu_mp_valid_write; // @[ifu_bp_ctl.scala 435:36] - wire _T_594 = _T_592 & _T_550; // @[ifu_bp_ctl.scala 435:57] - wire _T_595 = io_dec_bp_dec_tlu_br0_r_pkt_bits_way & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 435:98] - wire btb_wr_en_way1 = _T_594 | _T_595; // @[ifu_bp_ctl.scala 435:80] - wire [7:0] btb_wr_addr = dec_tlu_error_wb ? io_exu_bp_exu_i0_br_index_r : io_exu_bp_exu_mp_index; // @[ifu_bp_ctl.scala 438:24] - wire _T_612 = btb_wr_addr == 8'h0; // @[ifu_bp_ctl.scala 442:98] - wire _T_613 = _T_612 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107] - wire _T_615 = btb_wr_addr == 8'h1; // @[ifu_bp_ctl.scala 442:98] - wire _T_616 = _T_615 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107] - wire _T_618 = btb_wr_addr == 8'h2; // @[ifu_bp_ctl.scala 442:98] - wire _T_619 = _T_618 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107] - wire _T_621 = btb_wr_addr == 8'h3; // @[ifu_bp_ctl.scala 442:98] - wire _T_622 = _T_621 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107] - wire _T_624 = btb_wr_addr == 8'h4; // @[ifu_bp_ctl.scala 442:98] - wire _T_625 = _T_624 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107] - wire _T_627 = btb_wr_addr == 8'h5; // @[ifu_bp_ctl.scala 442:98] - wire _T_628 = _T_627 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107] - wire _T_630 = btb_wr_addr == 8'h6; // @[ifu_bp_ctl.scala 442:98] - wire _T_631 = _T_630 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107] - wire _T_633 = btb_wr_addr == 8'h7; // @[ifu_bp_ctl.scala 442:98] - wire _T_634 = _T_633 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107] - wire _T_636 = btb_wr_addr == 8'h8; // @[ifu_bp_ctl.scala 442:98] - wire _T_637 = _T_636 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107] - wire _T_639 = btb_wr_addr == 8'h9; // @[ifu_bp_ctl.scala 442:98] - wire _T_640 = _T_639 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107] - wire _T_642 = btb_wr_addr == 8'ha; // @[ifu_bp_ctl.scala 442:98] - wire _T_643 = _T_642 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107] - wire _T_645 = btb_wr_addr == 8'hb; // @[ifu_bp_ctl.scala 442:98] - wire _T_646 = _T_645 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107] - wire _T_648 = btb_wr_addr == 8'hc; // @[ifu_bp_ctl.scala 442:98] - wire _T_649 = _T_648 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107] - wire _T_651 = btb_wr_addr == 8'hd; // @[ifu_bp_ctl.scala 442:98] - wire _T_652 = _T_651 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107] - wire _T_654 = btb_wr_addr == 8'he; // @[ifu_bp_ctl.scala 442:98] - wire _T_655 = _T_654 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107] - wire _T_657 = btb_wr_addr == 8'hf; // @[ifu_bp_ctl.scala 442:98] - wire _T_658 = _T_657 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107] - wire _T_661 = _T_612 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107] - wire _T_664 = _T_615 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107] - wire _T_667 = _T_618 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107] - wire _T_670 = _T_621 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107] - wire _T_673 = _T_624 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107] - wire _T_676 = _T_627 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107] - wire _T_679 = _T_630 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107] - wire _T_682 = _T_633 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107] - wire _T_685 = _T_636 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107] - wire _T_688 = _T_639 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107] - wire _T_691 = _T_642 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107] - wire _T_694 = _T_645 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107] - wire _T_697 = _T_648 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107] - wire _T_700 = _T_651 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107] - wire _T_703 = _T_654 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107] - wire _T_706 = _T_657 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107] - wire _T_966 = mp_hashed == 8'h0; // @[ifu_bp_ctl.scala 515:109] - wire _T_971 = br0_hashed_wb == 8'h0; // @[ifu_bp_ctl.scala 516:109] - wire _T_989 = bht_wr_en2[0] & _T_971; // @[ifu_bp_ctl.scala 521:23] - wire _T_997 = br0_hashed_wb == 8'h1; // @[ifu_bp_ctl.scala 521:74] - wire _T_998 = bht_wr_en2[0] & _T_997; // @[ifu_bp_ctl.scala 521:23] - wire _T_1006 = br0_hashed_wb == 8'h2; // @[ifu_bp_ctl.scala 521:74] - wire _T_1007 = bht_wr_en2[0] & _T_1006; // @[ifu_bp_ctl.scala 521:23] - wire _T_1015 = br0_hashed_wb == 8'h3; // @[ifu_bp_ctl.scala 521:74] - wire _T_1016 = bht_wr_en2[0] & _T_1015; // @[ifu_bp_ctl.scala 521:23] - wire _T_1024 = br0_hashed_wb == 8'h4; // @[ifu_bp_ctl.scala 521:74] - wire _T_1025 = bht_wr_en2[0] & _T_1024; // @[ifu_bp_ctl.scala 521:23] - wire _T_1033 = br0_hashed_wb == 8'h5; // @[ifu_bp_ctl.scala 521:74] - wire _T_1034 = bht_wr_en2[0] & _T_1033; // @[ifu_bp_ctl.scala 521:23] - wire _T_1042 = br0_hashed_wb == 8'h6; // @[ifu_bp_ctl.scala 521:74] - wire _T_1043 = bht_wr_en2[0] & _T_1042; // @[ifu_bp_ctl.scala 521:23] - wire _T_1051 = br0_hashed_wb == 8'h7; // @[ifu_bp_ctl.scala 521:74] - wire _T_1052 = bht_wr_en2[0] & _T_1051; // @[ifu_bp_ctl.scala 521:23] - wire _T_1060 = br0_hashed_wb == 8'h8; // @[ifu_bp_ctl.scala 521:74] - wire _T_1061 = bht_wr_en2[0] & _T_1060; // @[ifu_bp_ctl.scala 521:23] - wire _T_1069 = br0_hashed_wb == 8'h9; // @[ifu_bp_ctl.scala 521:74] - wire _T_1070 = bht_wr_en2[0] & _T_1069; // @[ifu_bp_ctl.scala 521:23] - wire _T_1078 = br0_hashed_wb == 8'ha; // @[ifu_bp_ctl.scala 521:74] - wire _T_1079 = bht_wr_en2[0] & _T_1078; // @[ifu_bp_ctl.scala 521:23] - wire _T_1087 = br0_hashed_wb == 8'hb; // @[ifu_bp_ctl.scala 521:74] - wire _T_1088 = bht_wr_en2[0] & _T_1087; // @[ifu_bp_ctl.scala 521:23] - wire _T_1096 = br0_hashed_wb == 8'hc; // @[ifu_bp_ctl.scala 521:74] - wire _T_1097 = bht_wr_en2[0] & _T_1096; // @[ifu_bp_ctl.scala 521:23] - wire _T_1105 = br0_hashed_wb == 8'hd; // @[ifu_bp_ctl.scala 521:74] - wire _T_1106 = bht_wr_en2[0] & _T_1105; // @[ifu_bp_ctl.scala 521:23] - wire _T_1114 = br0_hashed_wb == 8'he; // @[ifu_bp_ctl.scala 521:74] - wire _T_1115 = bht_wr_en2[0] & _T_1114; // @[ifu_bp_ctl.scala 521:23] - wire _T_1123 = br0_hashed_wb == 8'hf; // @[ifu_bp_ctl.scala 521:74] - wire _T_1124 = bht_wr_en2[0] & _T_1123; // @[ifu_bp_ctl.scala 521:23] - wire _T_1133 = bht_wr_en2[1] & _T_971; // @[ifu_bp_ctl.scala 521:23] - wire _T_1142 = bht_wr_en2[1] & _T_997; // @[ifu_bp_ctl.scala 521:23] - wire _T_1151 = bht_wr_en2[1] & _T_1006; // @[ifu_bp_ctl.scala 521:23] - wire _T_1160 = bht_wr_en2[1] & _T_1015; // @[ifu_bp_ctl.scala 521:23] - wire _T_1169 = bht_wr_en2[1] & _T_1024; // @[ifu_bp_ctl.scala 521:23] - wire _T_1178 = bht_wr_en2[1] & _T_1033; // @[ifu_bp_ctl.scala 521:23] - wire _T_1187 = bht_wr_en2[1] & _T_1042; // @[ifu_bp_ctl.scala 521:23] - wire _T_1196 = bht_wr_en2[1] & _T_1051; // @[ifu_bp_ctl.scala 521:23] - wire _T_1205 = bht_wr_en2[1] & _T_1060; // @[ifu_bp_ctl.scala 521:23] - wire _T_1214 = bht_wr_en2[1] & _T_1069; // @[ifu_bp_ctl.scala 521:23] - wire _T_1223 = bht_wr_en2[1] & _T_1078; // @[ifu_bp_ctl.scala 521:23] - wire _T_1232 = bht_wr_en2[1] & _T_1087; // @[ifu_bp_ctl.scala 521:23] - wire _T_1241 = bht_wr_en2[1] & _T_1096; // @[ifu_bp_ctl.scala 521:23] - wire _T_1250 = bht_wr_en2[1] & _T_1105; // @[ifu_bp_ctl.scala 521:23] - wire _T_1259 = bht_wr_en2[1] & _T_1114; // @[ifu_bp_ctl.scala 521:23] - wire _T_1268 = bht_wr_en2[1] & _T_1123; // @[ifu_bp_ctl.scala 521:23] - wire _T_1277 = bht_wr_en0[0] & _T_966; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_0_0_0 = _T_1277 | _T_989; // @[ifu_bp_ctl.scala 529:223] - wire _T_1293 = mp_hashed == 8'h1; // @[ifu_bp_ctl.scala 529:97] - wire _T_1294 = bht_wr_en0[0] & _T_1293; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_0_0_1 = _T_1294 | _T_998; // @[ifu_bp_ctl.scala 529:223] - wire _T_1310 = mp_hashed == 8'h2; // @[ifu_bp_ctl.scala 529:97] - wire _T_1311 = bht_wr_en0[0] & _T_1310; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_0_0_2 = _T_1311 | _T_1007; // @[ifu_bp_ctl.scala 529:223] - wire _T_1327 = mp_hashed == 8'h3; // @[ifu_bp_ctl.scala 529:97] - wire _T_1328 = bht_wr_en0[0] & _T_1327; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_0_0_3 = _T_1328 | _T_1016; // @[ifu_bp_ctl.scala 529:223] - wire _T_1344 = mp_hashed == 8'h4; // @[ifu_bp_ctl.scala 529:97] - wire _T_1345 = bht_wr_en0[0] & _T_1344; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_0_0_4 = _T_1345 | _T_1025; // @[ifu_bp_ctl.scala 529:223] - wire _T_1361 = mp_hashed == 8'h5; // @[ifu_bp_ctl.scala 529:97] - wire _T_1362 = bht_wr_en0[0] & _T_1361; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_0_0_5 = _T_1362 | _T_1034; // @[ifu_bp_ctl.scala 529:223] - wire _T_1378 = mp_hashed == 8'h6; // @[ifu_bp_ctl.scala 529:97] - wire _T_1379 = bht_wr_en0[0] & _T_1378; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_0_0_6 = _T_1379 | _T_1043; // @[ifu_bp_ctl.scala 529:223] - wire _T_1395 = mp_hashed == 8'h7; // @[ifu_bp_ctl.scala 529:97] - wire _T_1396 = bht_wr_en0[0] & _T_1395; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_0_0_7 = _T_1396 | _T_1052; // @[ifu_bp_ctl.scala 529:223] - wire _T_1412 = mp_hashed == 8'h8; // @[ifu_bp_ctl.scala 529:97] - wire _T_1413 = bht_wr_en0[0] & _T_1412; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_0_0_8 = _T_1413 | _T_1061; // @[ifu_bp_ctl.scala 529:223] - wire _T_1429 = mp_hashed == 8'h9; // @[ifu_bp_ctl.scala 529:97] - wire _T_1430 = bht_wr_en0[0] & _T_1429; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_0_0_9 = _T_1430 | _T_1070; // @[ifu_bp_ctl.scala 529:223] - wire _T_1446 = mp_hashed == 8'ha; // @[ifu_bp_ctl.scala 529:97] - wire _T_1447 = bht_wr_en0[0] & _T_1446; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_0_0_10 = _T_1447 | _T_1079; // @[ifu_bp_ctl.scala 529:223] - wire _T_1463 = mp_hashed == 8'hb; // @[ifu_bp_ctl.scala 529:97] - wire _T_1464 = bht_wr_en0[0] & _T_1463; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_0_0_11 = _T_1464 | _T_1088; // @[ifu_bp_ctl.scala 529:223] - wire _T_1480 = mp_hashed == 8'hc; // @[ifu_bp_ctl.scala 529:97] - wire _T_1481 = bht_wr_en0[0] & _T_1480; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_0_0_12 = _T_1481 | _T_1097; // @[ifu_bp_ctl.scala 529:223] - wire _T_1497 = mp_hashed == 8'hd; // @[ifu_bp_ctl.scala 529:97] - wire _T_1498 = bht_wr_en0[0] & _T_1497; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_0_0_13 = _T_1498 | _T_1106; // @[ifu_bp_ctl.scala 529:223] - wire _T_1514 = mp_hashed == 8'he; // @[ifu_bp_ctl.scala 529:97] - wire _T_1515 = bht_wr_en0[0] & _T_1514; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_0_0_14 = _T_1515 | _T_1115; // @[ifu_bp_ctl.scala 529:223] - wire _T_1531 = mp_hashed == 8'hf; // @[ifu_bp_ctl.scala 529:97] - wire _T_1532 = bht_wr_en0[0] & _T_1531; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_0_0_15 = _T_1532 | _T_1124; // @[ifu_bp_ctl.scala 529:223] - wire _T_1549 = bht_wr_en0[1] & _T_966; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_1_0_0 = _T_1549 | _T_1133; // @[ifu_bp_ctl.scala 529:223] - wire _T_1566 = bht_wr_en0[1] & _T_1293; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_1_0_1 = _T_1566 | _T_1142; // @[ifu_bp_ctl.scala 529:223] - wire _T_1583 = bht_wr_en0[1] & _T_1310; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_1_0_2 = _T_1583 | _T_1151; // @[ifu_bp_ctl.scala 529:223] - wire _T_1600 = bht_wr_en0[1] & _T_1327; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_1_0_3 = _T_1600 | _T_1160; // @[ifu_bp_ctl.scala 529:223] - wire _T_1617 = bht_wr_en0[1] & _T_1344; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_1_0_4 = _T_1617 | _T_1169; // @[ifu_bp_ctl.scala 529:223] - wire _T_1634 = bht_wr_en0[1] & _T_1361; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_1_0_5 = _T_1634 | _T_1178; // @[ifu_bp_ctl.scala 529:223] - wire _T_1651 = bht_wr_en0[1] & _T_1378; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_1_0_6 = _T_1651 | _T_1187; // @[ifu_bp_ctl.scala 529:223] - wire _T_1668 = bht_wr_en0[1] & _T_1395; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_1_0_7 = _T_1668 | _T_1196; // @[ifu_bp_ctl.scala 529:223] - wire _T_1685 = bht_wr_en0[1] & _T_1412; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_1_0_8 = _T_1685 | _T_1205; // @[ifu_bp_ctl.scala 529:223] - wire _T_1702 = bht_wr_en0[1] & _T_1429; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_1_0_9 = _T_1702 | _T_1214; // @[ifu_bp_ctl.scala 529:223] - wire _T_1719 = bht_wr_en0[1] & _T_1446; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_1_0_10 = _T_1719 | _T_1223; // @[ifu_bp_ctl.scala 529:223] - wire _T_1736 = bht_wr_en0[1] & _T_1463; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_1_0_11 = _T_1736 | _T_1232; // @[ifu_bp_ctl.scala 529:223] - wire _T_1753 = bht_wr_en0[1] & _T_1480; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_1_0_12 = _T_1753 | _T_1241; // @[ifu_bp_ctl.scala 529:223] - wire _T_1770 = bht_wr_en0[1] & _T_1497; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_1_0_13 = _T_1770 | _T_1250; // @[ifu_bp_ctl.scala 529:223] - wire _T_1787 = bht_wr_en0[1] & _T_1514; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_1_0_14 = _T_1787 | _T_1259; // @[ifu_bp_ctl.scala 529:223] - wire _T_1804 = bht_wr_en0[1] & _T_1531; // @[ifu_bp_ctl.scala 529:45] - wire bht_bank_sel_1_0_15 = _T_1804 | _T_1268; // @[ifu_bp_ctl.scala 529:223] + wire _T_587 = _T_168 & exu_mp_valid_write; // @[ifu_bp_ctl.scala 436:39] + wire _T_589 = _T_587 & _T_550; // @[ifu_bp_ctl.scala 436:60] + wire _T_590 = ~io_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[ifu_bp_ctl.scala 436:87] + wire _T_591 = _T_590 & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 436:104] + wire btb_wr_en_way0 = _T_589 | _T_591; // @[ifu_bp_ctl.scala 436:83] + wire _T_592 = io_exu_bp_exu_mp_pkt_bits_way & exu_mp_valid_write; // @[ifu_bp_ctl.scala 437:36] + wire _T_594 = _T_592 & _T_550; // @[ifu_bp_ctl.scala 437:57] + wire _T_595 = io_dec_bp_dec_tlu_br0_r_pkt_bits_way & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 437:98] + wire btb_wr_en_way1 = _T_594 | _T_595; // @[ifu_bp_ctl.scala 437:80] + wire [7:0] btb_wr_addr = dec_tlu_error_wb ? io_exu_bp_exu_i0_br_index_r : io_exu_bp_exu_mp_index; // @[ifu_bp_ctl.scala 440:24] + wire _T_610 = btb_wr_addr == 8'h0; // @[ifu_bp_ctl.scala 448:98] + wire _T_613 = btb_wr_addr == 8'h1; // @[ifu_bp_ctl.scala 448:98] + wire _T_616 = btb_wr_addr == 8'h2; // @[ifu_bp_ctl.scala 448:98] + wire _T_619 = btb_wr_addr == 8'h3; // @[ifu_bp_ctl.scala 448:98] + wire _T_622 = btb_wr_addr == 8'h4; // @[ifu_bp_ctl.scala 448:98] + wire _T_625 = btb_wr_addr == 8'h5; // @[ifu_bp_ctl.scala 448:98] + wire _T_628 = btb_wr_addr == 8'h6; // @[ifu_bp_ctl.scala 448:98] + wire _T_631 = btb_wr_addr == 8'h7; // @[ifu_bp_ctl.scala 448:98] + wire _T_634 = btb_wr_addr == 8'h8; // @[ifu_bp_ctl.scala 448:98] + wire _T_637 = btb_wr_addr == 8'h9; // @[ifu_bp_ctl.scala 448:98] + wire _T_640 = btb_wr_addr == 8'ha; // @[ifu_bp_ctl.scala 448:98] + wire _T_643 = btb_wr_addr == 8'hb; // @[ifu_bp_ctl.scala 448:98] + wire _T_646 = btb_wr_addr == 8'hc; // @[ifu_bp_ctl.scala 448:98] + wire _T_649 = btb_wr_addr == 8'hd; // @[ifu_bp_ctl.scala 448:98] + wire _T_652 = btb_wr_addr == 8'he; // @[ifu_bp_ctl.scala 448:98] + wire _T_655 = btb_wr_addr == 8'hf; // @[ifu_bp_ctl.scala 448:98] + wire _T_659 = _T_610 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 449:107] + wire _T_662 = _T_613 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 449:107] + wire _T_665 = _T_616 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 449:107] + wire _T_668 = _T_619 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 449:107] + wire _T_671 = _T_622 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 449:107] + wire _T_674 = _T_625 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 449:107] + wire _T_677 = _T_628 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 449:107] + wire _T_680 = _T_631 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 449:107] + wire _T_683 = _T_634 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 449:107] + wire _T_686 = _T_637 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 449:107] + wire _T_689 = _T_640 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 449:107] + wire _T_692 = _T_643 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 449:107] + wire _T_695 = _T_646 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 449:107] + wire _T_698 = _T_649 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 449:107] + wire _T_701 = _T_652 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 449:107] + wire _T_704 = _T_655 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 449:107] + wire _T_964 = mp_hashed == 8'h0; // @[ifu_bp_ctl.scala 522:109] + wire _T_969 = br0_hashed_wb == 8'h0; // @[ifu_bp_ctl.scala 523:109] + wire _T_987 = bht_wr_en2[0] & _T_969; // @[ifu_bp_ctl.scala 528:23] + wire _T_995 = br0_hashed_wb == 8'h1; // @[ifu_bp_ctl.scala 528:74] + wire _T_996 = bht_wr_en2[0] & _T_995; // @[ifu_bp_ctl.scala 528:23] + wire _T_1004 = br0_hashed_wb == 8'h2; // @[ifu_bp_ctl.scala 528:74] + wire _T_1005 = bht_wr_en2[0] & _T_1004; // @[ifu_bp_ctl.scala 528:23] + wire _T_1013 = br0_hashed_wb == 8'h3; // @[ifu_bp_ctl.scala 528:74] + wire _T_1014 = bht_wr_en2[0] & _T_1013; // @[ifu_bp_ctl.scala 528:23] + wire _T_1022 = br0_hashed_wb == 8'h4; // @[ifu_bp_ctl.scala 528:74] + wire _T_1023 = bht_wr_en2[0] & _T_1022; // @[ifu_bp_ctl.scala 528:23] + wire _T_1031 = br0_hashed_wb == 8'h5; // @[ifu_bp_ctl.scala 528:74] + wire _T_1032 = bht_wr_en2[0] & _T_1031; // @[ifu_bp_ctl.scala 528:23] + wire _T_1040 = br0_hashed_wb == 8'h6; // @[ifu_bp_ctl.scala 528:74] + wire _T_1041 = bht_wr_en2[0] & _T_1040; // @[ifu_bp_ctl.scala 528:23] + wire _T_1049 = br0_hashed_wb == 8'h7; // @[ifu_bp_ctl.scala 528:74] + wire _T_1050 = bht_wr_en2[0] & _T_1049; // @[ifu_bp_ctl.scala 528:23] + wire _T_1058 = br0_hashed_wb == 8'h8; // @[ifu_bp_ctl.scala 528:74] + wire _T_1059 = bht_wr_en2[0] & _T_1058; // @[ifu_bp_ctl.scala 528:23] + wire _T_1067 = br0_hashed_wb == 8'h9; // @[ifu_bp_ctl.scala 528:74] + wire _T_1068 = bht_wr_en2[0] & _T_1067; // @[ifu_bp_ctl.scala 528:23] + wire _T_1076 = br0_hashed_wb == 8'ha; // @[ifu_bp_ctl.scala 528:74] + wire _T_1077 = bht_wr_en2[0] & _T_1076; // @[ifu_bp_ctl.scala 528:23] + wire _T_1085 = br0_hashed_wb == 8'hb; // @[ifu_bp_ctl.scala 528:74] + wire _T_1086 = bht_wr_en2[0] & _T_1085; // @[ifu_bp_ctl.scala 528:23] + wire _T_1094 = br0_hashed_wb == 8'hc; // @[ifu_bp_ctl.scala 528:74] + wire _T_1095 = bht_wr_en2[0] & _T_1094; // @[ifu_bp_ctl.scala 528:23] + wire _T_1103 = br0_hashed_wb == 8'hd; // @[ifu_bp_ctl.scala 528:74] + wire _T_1104 = bht_wr_en2[0] & _T_1103; // @[ifu_bp_ctl.scala 528:23] + wire _T_1112 = br0_hashed_wb == 8'he; // @[ifu_bp_ctl.scala 528:74] + wire _T_1113 = bht_wr_en2[0] & _T_1112; // @[ifu_bp_ctl.scala 528:23] + wire _T_1121 = br0_hashed_wb == 8'hf; // @[ifu_bp_ctl.scala 528:74] + wire _T_1122 = bht_wr_en2[0] & _T_1121; // @[ifu_bp_ctl.scala 528:23] + wire _T_1131 = bht_wr_en2[1] & _T_969; // @[ifu_bp_ctl.scala 528:23] + wire _T_1140 = bht_wr_en2[1] & _T_995; // @[ifu_bp_ctl.scala 528:23] + wire _T_1149 = bht_wr_en2[1] & _T_1004; // @[ifu_bp_ctl.scala 528:23] + wire _T_1158 = bht_wr_en2[1] & _T_1013; // @[ifu_bp_ctl.scala 528:23] + wire _T_1167 = bht_wr_en2[1] & _T_1022; // @[ifu_bp_ctl.scala 528:23] + wire _T_1176 = bht_wr_en2[1] & _T_1031; // @[ifu_bp_ctl.scala 528:23] + wire _T_1185 = bht_wr_en2[1] & _T_1040; // @[ifu_bp_ctl.scala 528:23] + wire _T_1194 = bht_wr_en2[1] & _T_1049; // @[ifu_bp_ctl.scala 528:23] + wire _T_1203 = bht_wr_en2[1] & _T_1058; // @[ifu_bp_ctl.scala 528:23] + wire _T_1212 = bht_wr_en2[1] & _T_1067; // @[ifu_bp_ctl.scala 528:23] + wire _T_1221 = bht_wr_en2[1] & _T_1076; // @[ifu_bp_ctl.scala 528:23] + wire _T_1230 = bht_wr_en2[1] & _T_1085; // @[ifu_bp_ctl.scala 528:23] + wire _T_1239 = bht_wr_en2[1] & _T_1094; // @[ifu_bp_ctl.scala 528:23] + wire _T_1248 = bht_wr_en2[1] & _T_1103; // @[ifu_bp_ctl.scala 528:23] + wire _T_1257 = bht_wr_en2[1] & _T_1112; // @[ifu_bp_ctl.scala 528:23] + wire _T_1266 = bht_wr_en2[1] & _T_1121; // @[ifu_bp_ctl.scala 528:23] + wire _T_1275 = bht_wr_en0[0] & _T_964; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_0_0_0 = _T_1275 | _T_987; // @[ifu_bp_ctl.scala 536:223] + wire _T_1291 = mp_hashed == 8'h1; // @[ifu_bp_ctl.scala 536:97] + wire _T_1292 = bht_wr_en0[0] & _T_1291; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_0_0_1 = _T_1292 | _T_996; // @[ifu_bp_ctl.scala 536:223] + wire _T_1308 = mp_hashed == 8'h2; // @[ifu_bp_ctl.scala 536:97] + wire _T_1309 = bht_wr_en0[0] & _T_1308; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_0_0_2 = _T_1309 | _T_1005; // @[ifu_bp_ctl.scala 536:223] + wire _T_1325 = mp_hashed == 8'h3; // @[ifu_bp_ctl.scala 536:97] + wire _T_1326 = bht_wr_en0[0] & _T_1325; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_0_0_3 = _T_1326 | _T_1014; // @[ifu_bp_ctl.scala 536:223] + wire _T_1342 = mp_hashed == 8'h4; // @[ifu_bp_ctl.scala 536:97] + wire _T_1343 = bht_wr_en0[0] & _T_1342; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_0_0_4 = _T_1343 | _T_1023; // @[ifu_bp_ctl.scala 536:223] + wire _T_1359 = mp_hashed == 8'h5; // @[ifu_bp_ctl.scala 536:97] + wire _T_1360 = bht_wr_en0[0] & _T_1359; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_0_0_5 = _T_1360 | _T_1032; // @[ifu_bp_ctl.scala 536:223] + wire _T_1376 = mp_hashed == 8'h6; // @[ifu_bp_ctl.scala 536:97] + wire _T_1377 = bht_wr_en0[0] & _T_1376; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_0_0_6 = _T_1377 | _T_1041; // @[ifu_bp_ctl.scala 536:223] + wire _T_1393 = mp_hashed == 8'h7; // @[ifu_bp_ctl.scala 536:97] + wire _T_1394 = bht_wr_en0[0] & _T_1393; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_0_0_7 = _T_1394 | _T_1050; // @[ifu_bp_ctl.scala 536:223] + wire _T_1410 = mp_hashed == 8'h8; // @[ifu_bp_ctl.scala 536:97] + wire _T_1411 = bht_wr_en0[0] & _T_1410; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_0_0_8 = _T_1411 | _T_1059; // @[ifu_bp_ctl.scala 536:223] + wire _T_1427 = mp_hashed == 8'h9; // @[ifu_bp_ctl.scala 536:97] + wire _T_1428 = bht_wr_en0[0] & _T_1427; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_0_0_9 = _T_1428 | _T_1068; // @[ifu_bp_ctl.scala 536:223] + wire _T_1444 = mp_hashed == 8'ha; // @[ifu_bp_ctl.scala 536:97] + wire _T_1445 = bht_wr_en0[0] & _T_1444; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_0_0_10 = _T_1445 | _T_1077; // @[ifu_bp_ctl.scala 536:223] + wire _T_1461 = mp_hashed == 8'hb; // @[ifu_bp_ctl.scala 536:97] + wire _T_1462 = bht_wr_en0[0] & _T_1461; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_0_0_11 = _T_1462 | _T_1086; // @[ifu_bp_ctl.scala 536:223] + wire _T_1478 = mp_hashed == 8'hc; // @[ifu_bp_ctl.scala 536:97] + wire _T_1479 = bht_wr_en0[0] & _T_1478; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_0_0_12 = _T_1479 | _T_1095; // @[ifu_bp_ctl.scala 536:223] + wire _T_1495 = mp_hashed == 8'hd; // @[ifu_bp_ctl.scala 536:97] + wire _T_1496 = bht_wr_en0[0] & _T_1495; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_0_0_13 = _T_1496 | _T_1104; // @[ifu_bp_ctl.scala 536:223] + wire _T_1512 = mp_hashed == 8'he; // @[ifu_bp_ctl.scala 536:97] + wire _T_1513 = bht_wr_en0[0] & _T_1512; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_0_0_14 = _T_1513 | _T_1113; // @[ifu_bp_ctl.scala 536:223] + wire _T_1529 = mp_hashed == 8'hf; // @[ifu_bp_ctl.scala 536:97] + wire _T_1530 = bht_wr_en0[0] & _T_1529; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_0_0_15 = _T_1530 | _T_1122; // @[ifu_bp_ctl.scala 536:223] + wire _T_1547 = bht_wr_en0[1] & _T_964; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_1_0_0 = _T_1547 | _T_1131; // @[ifu_bp_ctl.scala 536:223] + wire _T_1564 = bht_wr_en0[1] & _T_1291; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_1_0_1 = _T_1564 | _T_1140; // @[ifu_bp_ctl.scala 536:223] + wire _T_1581 = bht_wr_en0[1] & _T_1308; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_1_0_2 = _T_1581 | _T_1149; // @[ifu_bp_ctl.scala 536:223] + wire _T_1598 = bht_wr_en0[1] & _T_1325; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_1_0_3 = _T_1598 | _T_1158; // @[ifu_bp_ctl.scala 536:223] + wire _T_1615 = bht_wr_en0[1] & _T_1342; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_1_0_4 = _T_1615 | _T_1167; // @[ifu_bp_ctl.scala 536:223] + wire _T_1632 = bht_wr_en0[1] & _T_1359; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_1_0_5 = _T_1632 | _T_1176; // @[ifu_bp_ctl.scala 536:223] + wire _T_1649 = bht_wr_en0[1] & _T_1376; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_1_0_6 = _T_1649 | _T_1185; // @[ifu_bp_ctl.scala 536:223] + wire _T_1666 = bht_wr_en0[1] & _T_1393; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_1_0_7 = _T_1666 | _T_1194; // @[ifu_bp_ctl.scala 536:223] + wire _T_1683 = bht_wr_en0[1] & _T_1410; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_1_0_8 = _T_1683 | _T_1203; // @[ifu_bp_ctl.scala 536:223] + wire _T_1700 = bht_wr_en0[1] & _T_1427; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_1_0_9 = _T_1700 | _T_1212; // @[ifu_bp_ctl.scala 536:223] + wire _T_1717 = bht_wr_en0[1] & _T_1444; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_1_0_10 = _T_1717 | _T_1221; // @[ifu_bp_ctl.scala 536:223] + wire _T_1734 = bht_wr_en0[1] & _T_1461; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_1_0_11 = _T_1734 | _T_1230; // @[ifu_bp_ctl.scala 536:223] + wire _T_1751 = bht_wr_en0[1] & _T_1478; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_1_0_12 = _T_1751 | _T_1239; // @[ifu_bp_ctl.scala 536:223] + wire _T_1768 = bht_wr_en0[1] & _T_1495; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_1_0_13 = _T_1768 | _T_1248; // @[ifu_bp_ctl.scala 536:223] + wire _T_1785 = bht_wr_en0[1] & _T_1512; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_1_0_14 = _T_1785 | _T_1257; // @[ifu_bp_ctl.scala 536:223] + wire _T_1802 = bht_wr_en0[1] & _T_1529; // @[ifu_bp_ctl.scala 536:45] + wire bht_bank_sel_1_0_15 = _T_1802 | _T_1266; // @[ifu_bp_ctl.scala 536:223] rvclkhdr rvclkhdr ( // @[lib.scala 399:23] .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en) @@ -1159,16 +972,16 @@ module ifu_bp_ctl( .io_clk(rvclkhdr_42_io_clk), .io_en(rvclkhdr_42_io_en) ); - assign io_ifu_bp_hit_taken_f = _T_229 & _T_230; // @[ifu_bp_ctl.scala 276:25] - assign io_ifu_bp_btb_target_f = 31'h0; // @[ifu_bp_ctl.scala 373:26] - assign io_ifu_bp_inst_mask_f = _T_266 | _T_267; // @[ifu_bp_ctl.scala 300:25] + assign io_ifu_bp_hit_taken_f = 1'h0; // @[ifu_bp_ctl.scala 276:25] + assign io_ifu_bp_btb_target_f = 31'h0; // @[ifu_bp_ctl.scala 375:27] + assign io_ifu_bp_inst_mask_f = io_ifu_bp_hit_taken_f | _T_267; // @[ifu_bp_ctl.scala 300:25] assign io_ifu_bp_fghr_f = fghr; // @[ifu_bp_ctl.scala 343:20] - assign io_ifu_bp_way_f = tag_match_vway1_expanded_f | _T_152; // @[ifu_bp_ctl.scala 253:19] + assign io_ifu_bp_way_f = tag_match_vway1_expanded_f | btb_vlru_rd_f; // @[ifu_bp_ctl.scala 253:19] assign io_ifu_bp_ret_f = 2'h0; // @[ifu_bp_ctl.scala 349:19] assign io_ifu_bp_hist1_f = {bht_vbank1_rd_data_f[1],bht_vbank0_rd_data_f[1]}; // @[ifu_bp_ctl.scala 344:21] assign io_ifu_bp_hist0_f = {bht_vbank1_rd_data_f[0],bht_vbank0_rd_data_f[0]}; // @[ifu_bp_ctl.scala 345:21] assign io_ifu_bp_pc4_f = 2'h0; // @[ifu_bp_ctl.scala 346:19] - assign io_ifu_bp_valid_f = vwayhit_f & _T_351; // @[ifu_bp_ctl.scala 348:21] + assign io_ifu_bp_valid_f = 2'h0; // @[ifu_bp_ctl.scala 348:21] assign io_ifu_bp_poffset_f = 12'h0; // @[ifu_bp_ctl.scala 361:23] assign io_ifu_bp_fa_index_f_0 = 4'h0; // @[ifu_bp_ctl.scala 35:24] assign io_ifu_bp_fa_index_f_1 = 4'h0; // @[ifu_bp_ctl.scala 35:24] @@ -1191,69 +1004,69 @@ module ifu_bp_ctl( assign rvclkhdr_8_io_clk = clock; // @[lib.scala 401:18] assign rvclkhdr_8_io_en = 1'h0; // @[lib.scala 402:17] assign rvclkhdr_9_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_9_io_en = _T_612 & btb_wr_en_way0; // @[lib.scala 402:17] + assign rvclkhdr_9_io_en = _T_610 & btb_wr_en_way0; // @[lib.scala 402:17] assign rvclkhdr_10_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_10_io_en = _T_615 & btb_wr_en_way0; // @[lib.scala 402:17] + assign rvclkhdr_10_io_en = _T_613 & btb_wr_en_way0; // @[lib.scala 402:17] assign rvclkhdr_11_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_11_io_en = _T_618 & btb_wr_en_way0; // @[lib.scala 402:17] + assign rvclkhdr_11_io_en = _T_616 & btb_wr_en_way0; // @[lib.scala 402:17] assign rvclkhdr_12_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_12_io_en = _T_621 & btb_wr_en_way0; // @[lib.scala 402:17] + assign rvclkhdr_12_io_en = _T_619 & btb_wr_en_way0; // @[lib.scala 402:17] assign rvclkhdr_13_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_13_io_en = _T_624 & btb_wr_en_way0; // @[lib.scala 402:17] + assign rvclkhdr_13_io_en = _T_622 & btb_wr_en_way0; // @[lib.scala 402:17] assign rvclkhdr_14_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_14_io_en = _T_627 & btb_wr_en_way0; // @[lib.scala 402:17] + assign rvclkhdr_14_io_en = _T_625 & btb_wr_en_way0; // @[lib.scala 402:17] assign rvclkhdr_15_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_15_io_en = _T_630 & btb_wr_en_way0; // @[lib.scala 402:17] + assign rvclkhdr_15_io_en = _T_628 & btb_wr_en_way0; // @[lib.scala 402:17] assign rvclkhdr_16_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_16_io_en = _T_633 & btb_wr_en_way0; // @[lib.scala 402:17] + assign rvclkhdr_16_io_en = _T_631 & btb_wr_en_way0; // @[lib.scala 402:17] assign rvclkhdr_17_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_17_io_en = _T_636 & btb_wr_en_way0; // @[lib.scala 402:17] + assign rvclkhdr_17_io_en = _T_634 & btb_wr_en_way0; // @[lib.scala 402:17] assign rvclkhdr_18_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_18_io_en = _T_639 & btb_wr_en_way0; // @[lib.scala 402:17] + assign rvclkhdr_18_io_en = _T_637 & btb_wr_en_way0; // @[lib.scala 402:17] assign rvclkhdr_19_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_19_io_en = _T_642 & btb_wr_en_way0; // @[lib.scala 402:17] + assign rvclkhdr_19_io_en = _T_640 & btb_wr_en_way0; // @[lib.scala 402:17] assign rvclkhdr_20_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_20_io_en = _T_645 & btb_wr_en_way0; // @[lib.scala 402:17] + assign rvclkhdr_20_io_en = _T_643 & btb_wr_en_way0; // @[lib.scala 402:17] assign rvclkhdr_21_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_21_io_en = _T_648 & btb_wr_en_way0; // @[lib.scala 402:17] + assign rvclkhdr_21_io_en = _T_646 & btb_wr_en_way0; // @[lib.scala 402:17] assign rvclkhdr_22_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_22_io_en = _T_651 & btb_wr_en_way0; // @[lib.scala 402:17] + assign rvclkhdr_22_io_en = _T_649 & btb_wr_en_way0; // @[lib.scala 402:17] assign rvclkhdr_23_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_23_io_en = _T_654 & btb_wr_en_way0; // @[lib.scala 402:17] + assign rvclkhdr_23_io_en = _T_652 & btb_wr_en_way0; // @[lib.scala 402:17] assign rvclkhdr_24_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_24_io_en = _T_657 & btb_wr_en_way0; // @[lib.scala 402:17] + assign rvclkhdr_24_io_en = _T_655 & btb_wr_en_way0; // @[lib.scala 402:17] assign rvclkhdr_25_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_25_io_en = _T_612 & btb_wr_en_way1; // @[lib.scala 402:17] + assign rvclkhdr_25_io_en = _T_610 & btb_wr_en_way1; // @[lib.scala 402:17] assign rvclkhdr_26_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_26_io_en = _T_615 & btb_wr_en_way1; // @[lib.scala 402:17] + assign rvclkhdr_26_io_en = _T_613 & btb_wr_en_way1; // @[lib.scala 402:17] assign rvclkhdr_27_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_27_io_en = _T_618 & btb_wr_en_way1; // @[lib.scala 402:17] + assign rvclkhdr_27_io_en = _T_616 & btb_wr_en_way1; // @[lib.scala 402:17] assign rvclkhdr_28_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_28_io_en = _T_621 & btb_wr_en_way1; // @[lib.scala 402:17] + assign rvclkhdr_28_io_en = _T_619 & btb_wr_en_way1; // @[lib.scala 402:17] assign rvclkhdr_29_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_29_io_en = _T_624 & btb_wr_en_way1; // @[lib.scala 402:17] + assign rvclkhdr_29_io_en = _T_622 & btb_wr_en_way1; // @[lib.scala 402:17] assign rvclkhdr_30_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_30_io_en = _T_627 & btb_wr_en_way1; // @[lib.scala 402:17] + assign rvclkhdr_30_io_en = _T_625 & btb_wr_en_way1; // @[lib.scala 402:17] assign rvclkhdr_31_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_31_io_en = _T_630 & btb_wr_en_way1; // @[lib.scala 402:17] + assign rvclkhdr_31_io_en = _T_628 & btb_wr_en_way1; // @[lib.scala 402:17] assign rvclkhdr_32_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_32_io_en = _T_633 & btb_wr_en_way1; // @[lib.scala 402:17] + assign rvclkhdr_32_io_en = _T_631 & btb_wr_en_way1; // @[lib.scala 402:17] assign rvclkhdr_33_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_33_io_en = _T_636 & btb_wr_en_way1; // @[lib.scala 402:17] + assign rvclkhdr_33_io_en = _T_634 & btb_wr_en_way1; // @[lib.scala 402:17] assign rvclkhdr_34_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_34_io_en = _T_639 & btb_wr_en_way1; // @[lib.scala 402:17] + assign rvclkhdr_34_io_en = _T_637 & btb_wr_en_way1; // @[lib.scala 402:17] assign rvclkhdr_35_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_35_io_en = _T_642 & btb_wr_en_way1; // @[lib.scala 402:17] + assign rvclkhdr_35_io_en = _T_640 & btb_wr_en_way1; // @[lib.scala 402:17] assign rvclkhdr_36_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_36_io_en = _T_645 & btb_wr_en_way1; // @[lib.scala 402:17] + assign rvclkhdr_36_io_en = _T_643 & btb_wr_en_way1; // @[lib.scala 402:17] assign rvclkhdr_37_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_37_io_en = _T_648 & btb_wr_en_way1; // @[lib.scala 402:17] + assign rvclkhdr_37_io_en = _T_646 & btb_wr_en_way1; // @[lib.scala 402:17] assign rvclkhdr_38_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_38_io_en = _T_651 & btb_wr_en_way1; // @[lib.scala 402:17] + assign rvclkhdr_38_io_en = _T_649 & btb_wr_en_way1; // @[lib.scala 402:17] assign rvclkhdr_39_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_39_io_en = _T_654 & btb_wr_en_way1; // @[lib.scala 402:17] + assign rvclkhdr_39_io_en = _T_652 & btb_wr_en_way1; // @[lib.scala 402:17] assign rvclkhdr_40_io_clk = clock; // @[lib.scala 401:18] - assign rvclkhdr_40_io_en = _T_657 & btb_wr_en_way1; // @[lib.scala 402:17] + assign rvclkhdr_40_io_en = _T_655 & btb_wr_en_way1; // @[lib.scala 402:17] assign rvclkhdr_41_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_41_io_en = bht_wr_en0[0] | bht_wr_en2[0]; // @[lib.scala 345:16] assign rvclkhdr_42_io_clk = clock; // @[lib.scala 344:17] @@ -1362,75 +1175,43 @@ initial begin _RAND_33 = {1{`RANDOM}}; bht_bank_rd_data_out_0_15 = _RAND_33[1:0]; _RAND_34 = {1{`RANDOM}}; - btb_bank0_rd_data_way0_out_0 = _RAND_34[21:0]; + btb_bank0_rd_data_way1_out_0 = _RAND_34[21:0]; _RAND_35 = {1{`RANDOM}}; - btb_bank0_rd_data_way0_out_1 = _RAND_35[21:0]; + btb_bank0_rd_data_way1_out_1 = _RAND_35[21:0]; _RAND_36 = {1{`RANDOM}}; - btb_bank0_rd_data_way0_out_2 = _RAND_36[21:0]; + btb_bank0_rd_data_way1_out_2 = _RAND_36[21:0]; _RAND_37 = {1{`RANDOM}}; - btb_bank0_rd_data_way0_out_3 = _RAND_37[21:0]; + btb_bank0_rd_data_way1_out_3 = _RAND_37[21:0]; _RAND_38 = {1{`RANDOM}}; - btb_bank0_rd_data_way0_out_4 = _RAND_38[21:0]; + btb_bank0_rd_data_way1_out_4 = _RAND_38[21:0]; _RAND_39 = {1{`RANDOM}}; - btb_bank0_rd_data_way0_out_5 = _RAND_39[21:0]; + btb_bank0_rd_data_way1_out_5 = _RAND_39[21:0]; _RAND_40 = {1{`RANDOM}}; - btb_bank0_rd_data_way0_out_6 = _RAND_40[21:0]; + btb_bank0_rd_data_way1_out_6 = _RAND_40[21:0]; _RAND_41 = {1{`RANDOM}}; - btb_bank0_rd_data_way0_out_7 = _RAND_41[21:0]; + btb_bank0_rd_data_way1_out_7 = _RAND_41[21:0]; _RAND_42 = {1{`RANDOM}}; - btb_bank0_rd_data_way0_out_8 = _RAND_42[21:0]; + btb_bank0_rd_data_way1_out_8 = _RAND_42[21:0]; _RAND_43 = {1{`RANDOM}}; - btb_bank0_rd_data_way0_out_9 = _RAND_43[21:0]; + btb_bank0_rd_data_way1_out_9 = _RAND_43[21:0]; _RAND_44 = {1{`RANDOM}}; - btb_bank0_rd_data_way0_out_10 = _RAND_44[21:0]; + btb_bank0_rd_data_way1_out_10 = _RAND_44[21:0]; _RAND_45 = {1{`RANDOM}}; - btb_bank0_rd_data_way0_out_11 = _RAND_45[21:0]; + btb_bank0_rd_data_way1_out_11 = _RAND_45[21:0]; _RAND_46 = {1{`RANDOM}}; - btb_bank0_rd_data_way0_out_12 = _RAND_46[21:0]; + btb_bank0_rd_data_way1_out_12 = _RAND_46[21:0]; _RAND_47 = {1{`RANDOM}}; - btb_bank0_rd_data_way0_out_13 = _RAND_47[21:0]; + btb_bank0_rd_data_way1_out_13 = _RAND_47[21:0]; _RAND_48 = {1{`RANDOM}}; - btb_bank0_rd_data_way0_out_14 = _RAND_48[21:0]; + btb_bank0_rd_data_way1_out_14 = _RAND_48[21:0]; _RAND_49 = {1{`RANDOM}}; - btb_bank0_rd_data_way0_out_15 = _RAND_49[21:0]; + btb_bank0_rd_data_way1_out_15 = _RAND_49[21:0]; _RAND_50 = {1{`RANDOM}}; - btb_bank0_rd_data_way1_out_0 = _RAND_50[21:0]; - _RAND_51 = {1{`RANDOM}}; - btb_bank0_rd_data_way1_out_1 = _RAND_51[21:0]; + exu_mp_way_f = _RAND_50[0:0]; + _RAND_51 = {8{`RANDOM}}; + _T_208 = _RAND_51[255:0]; _RAND_52 = {1{`RANDOM}}; - btb_bank0_rd_data_way1_out_2 = _RAND_52[21:0]; - _RAND_53 = {1{`RANDOM}}; - btb_bank0_rd_data_way1_out_3 = _RAND_53[21:0]; - _RAND_54 = {1{`RANDOM}}; - btb_bank0_rd_data_way1_out_4 = _RAND_54[21:0]; - _RAND_55 = {1{`RANDOM}}; - btb_bank0_rd_data_way1_out_5 = _RAND_55[21:0]; - _RAND_56 = {1{`RANDOM}}; - btb_bank0_rd_data_way1_out_6 = _RAND_56[21:0]; - _RAND_57 = {1{`RANDOM}}; - btb_bank0_rd_data_way1_out_7 = _RAND_57[21:0]; - _RAND_58 = {1{`RANDOM}}; - btb_bank0_rd_data_way1_out_8 = _RAND_58[21:0]; - _RAND_59 = {1{`RANDOM}}; - btb_bank0_rd_data_way1_out_9 = _RAND_59[21:0]; - _RAND_60 = {1{`RANDOM}}; - btb_bank0_rd_data_way1_out_10 = _RAND_60[21:0]; - _RAND_61 = {1{`RANDOM}}; - btb_bank0_rd_data_way1_out_11 = _RAND_61[21:0]; - _RAND_62 = {1{`RANDOM}}; - btb_bank0_rd_data_way1_out_12 = _RAND_62[21:0]; - _RAND_63 = {1{`RANDOM}}; - btb_bank0_rd_data_way1_out_13 = _RAND_63[21:0]; - _RAND_64 = {1{`RANDOM}}; - btb_bank0_rd_data_way1_out_14 = _RAND_64[21:0]; - _RAND_65 = {1{`RANDOM}}; - btb_bank0_rd_data_way1_out_15 = _RAND_65[21:0]; - _RAND_66 = {1{`RANDOM}}; - exu_mp_way_f = _RAND_66[0:0]; - _RAND_67 = {8{`RANDOM}}; - _T_208 = _RAND_67[255:0]; - _RAND_68 = {1{`RANDOM}}; - exu_flush_final_d1 = _RAND_68[0:0]; + exu_flush_final_d1 = _RAND_52[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin leak_one_f_d1 = 1'h0; @@ -1534,54 +1315,6 @@ initial begin if (reset) begin bht_bank_rd_data_out_0_15 = 2'h0; end - if (reset) begin - btb_bank0_rd_data_way0_out_0 = 22'h0; - end - if (reset) begin - btb_bank0_rd_data_way0_out_1 = 22'h0; - end - if (reset) begin - btb_bank0_rd_data_way0_out_2 = 22'h0; - end - if (reset) begin - btb_bank0_rd_data_way0_out_3 = 22'h0; - end - if (reset) begin - btb_bank0_rd_data_way0_out_4 = 22'h0; - end - if (reset) begin - btb_bank0_rd_data_way0_out_5 = 22'h0; - end - if (reset) begin - btb_bank0_rd_data_way0_out_6 = 22'h0; - end - if (reset) begin - btb_bank0_rd_data_way0_out_7 = 22'h0; - end - if (reset) begin - btb_bank0_rd_data_way0_out_8 = 22'h0; - end - if (reset) begin - btb_bank0_rd_data_way0_out_9 = 22'h0; - end - if (reset) begin - btb_bank0_rd_data_way0_out_10 = 22'h0; - end - if (reset) begin - btb_bank0_rd_data_way0_out_11 = 22'h0; - end - if (reset) begin - btb_bank0_rd_data_way0_out_12 = 22'h0; - end - if (reset) begin - btb_bank0_rd_data_way0_out_13 = 22'h0; - end - if (reset) begin - btb_bank0_rd_data_way0_out_14 = 22'h0; - end - if (reset) begin - btb_bank0_rd_data_way0_out_15 = 22'h0; - end if (reset) begin btb_bank0_rd_data_way1_out_0 = 22'h0; end @@ -1883,227 +1616,115 @@ end // initial bht_bank_rd_data_out_0_15 <= io_dec_bp_dec_tlu_br0_r_pkt_bits_hist; end end - always @(posedge clock or posedge reset) begin - if (reset) begin - btb_bank0_rd_data_way0_out_0 <= 22'h0; - end else if (_T_613) begin - btb_bank0_rd_data_way0_out_0 <= btb_wr_data; - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - btb_bank0_rd_data_way0_out_1 <= 22'h0; - end else if (_T_616) begin - btb_bank0_rd_data_way0_out_1 <= btb_wr_data; - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - btb_bank0_rd_data_way0_out_2 <= 22'h0; - end else if (_T_619) begin - btb_bank0_rd_data_way0_out_2 <= btb_wr_data; - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - btb_bank0_rd_data_way0_out_3 <= 22'h0; - end else if (_T_622) begin - btb_bank0_rd_data_way0_out_3 <= btb_wr_data; - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - btb_bank0_rd_data_way0_out_4 <= 22'h0; - end else if (_T_625) begin - btb_bank0_rd_data_way0_out_4 <= btb_wr_data; - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - btb_bank0_rd_data_way0_out_5 <= 22'h0; - end else if (_T_628) begin - btb_bank0_rd_data_way0_out_5 <= btb_wr_data; - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - btb_bank0_rd_data_way0_out_6 <= 22'h0; - end else if (_T_631) begin - btb_bank0_rd_data_way0_out_6 <= btb_wr_data; - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - btb_bank0_rd_data_way0_out_7 <= 22'h0; - end else if (_T_634) begin - btb_bank0_rd_data_way0_out_7 <= btb_wr_data; - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - btb_bank0_rd_data_way0_out_8 <= 22'h0; - end else if (_T_637) begin - btb_bank0_rd_data_way0_out_8 <= btb_wr_data; - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - btb_bank0_rd_data_way0_out_9 <= 22'h0; - end else if (_T_640) begin - btb_bank0_rd_data_way0_out_9 <= btb_wr_data; - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - btb_bank0_rd_data_way0_out_10 <= 22'h0; - end else if (_T_643) begin - btb_bank0_rd_data_way0_out_10 <= btb_wr_data; - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - btb_bank0_rd_data_way0_out_11 <= 22'h0; - end else if (_T_646) begin - btb_bank0_rd_data_way0_out_11 <= btb_wr_data; - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - btb_bank0_rd_data_way0_out_12 <= 22'h0; - end else if (_T_649) begin - btb_bank0_rd_data_way0_out_12 <= btb_wr_data; - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - btb_bank0_rd_data_way0_out_13 <= 22'h0; - end else if (_T_652) begin - btb_bank0_rd_data_way0_out_13 <= btb_wr_data; - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - btb_bank0_rd_data_way0_out_14 <= 22'h0; - end else if (_T_655) begin - btb_bank0_rd_data_way0_out_14 <= btb_wr_data; - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - btb_bank0_rd_data_way0_out_15 <= 22'h0; - end else if (_T_658) begin - btb_bank0_rd_data_way0_out_15 <= btb_wr_data; - end - end always @(posedge clock or posedge reset) begin if (reset) begin btb_bank0_rd_data_way1_out_0 <= 22'h0; - end else if (_T_661) begin + end else if (_T_659) begin btb_bank0_rd_data_way1_out_0 <= btb_wr_data; end end always @(posedge clock or posedge reset) begin if (reset) begin btb_bank0_rd_data_way1_out_1 <= 22'h0; - end else if (_T_664) begin + end else if (_T_662) begin btb_bank0_rd_data_way1_out_1 <= btb_wr_data; end end always @(posedge clock or posedge reset) begin if (reset) begin btb_bank0_rd_data_way1_out_2 <= 22'h0; - end else if (_T_667) begin + end else if (_T_665) begin btb_bank0_rd_data_way1_out_2 <= btb_wr_data; end end always @(posedge clock or posedge reset) begin if (reset) begin btb_bank0_rd_data_way1_out_3 <= 22'h0; - end else if (_T_670) begin + end else if (_T_668) begin btb_bank0_rd_data_way1_out_3 <= btb_wr_data; end end always @(posedge clock or posedge reset) begin if (reset) begin btb_bank0_rd_data_way1_out_4 <= 22'h0; - end else if (_T_673) begin + end else if (_T_671) begin btb_bank0_rd_data_way1_out_4 <= btb_wr_data; end end always @(posedge clock or posedge reset) begin if (reset) begin btb_bank0_rd_data_way1_out_5 <= 22'h0; - end else if (_T_676) begin + end else if (_T_674) begin btb_bank0_rd_data_way1_out_5 <= btb_wr_data; end end always @(posedge clock or posedge reset) begin if (reset) begin btb_bank0_rd_data_way1_out_6 <= 22'h0; - end else if (_T_679) begin + end else if (_T_677) begin btb_bank0_rd_data_way1_out_6 <= btb_wr_data; end end always @(posedge clock or posedge reset) begin if (reset) begin btb_bank0_rd_data_way1_out_7 <= 22'h0; - end else if (_T_682) begin + end else if (_T_680) begin btb_bank0_rd_data_way1_out_7 <= btb_wr_data; end end always @(posedge clock or posedge reset) begin if (reset) begin btb_bank0_rd_data_way1_out_8 <= 22'h0; - end else if (_T_685) begin + end else if (_T_683) begin btb_bank0_rd_data_way1_out_8 <= btb_wr_data; end end always @(posedge clock or posedge reset) begin if (reset) begin btb_bank0_rd_data_way1_out_9 <= 22'h0; - end else if (_T_688) begin + end else if (_T_686) begin btb_bank0_rd_data_way1_out_9 <= btb_wr_data; end end always @(posedge clock or posedge reset) begin if (reset) begin btb_bank0_rd_data_way1_out_10 <= 22'h0; - end else if (_T_691) begin + end else if (_T_689) begin btb_bank0_rd_data_way1_out_10 <= btb_wr_data; end end always @(posedge clock or posedge reset) begin if (reset) begin btb_bank0_rd_data_way1_out_11 <= 22'h0; - end else if (_T_694) begin + end else if (_T_692) begin btb_bank0_rd_data_way1_out_11 <= btb_wr_data; end end always @(posedge clock or posedge reset) begin if (reset) begin btb_bank0_rd_data_way1_out_12 <= 22'h0; - end else if (_T_697) begin + end else if (_T_695) begin btb_bank0_rd_data_way1_out_12 <= btb_wr_data; end end always @(posedge clock or posedge reset) begin if (reset) begin btb_bank0_rd_data_way1_out_13 <= 22'h0; - end else if (_T_700) begin + end else if (_T_698) begin btb_bank0_rd_data_way1_out_13 <= btb_wr_data; end end always @(posedge clock or posedge reset) begin if (reset) begin btb_bank0_rd_data_way1_out_14 <= 22'h0; - end else if (_T_703) begin + end else if (_T_701) begin btb_bank0_rd_data_way1_out_14 <= btb_wr_data; end end always @(posedge clock or posedge reset) begin if (reset) begin btb_bank0_rd_data_way1_out_15 <= 22'h0; - end else if (_T_706) begin + end else if (_T_704) begin btb_bank0_rd_data_way1_out_15 <= btb_wr_data; end end diff --git a/src/main/scala/ifu/ifu_bp_ctl.scala b/src/main/scala/ifu/ifu_bp_ctl.scala index 39afaac3..d439e7c0 100644 --- a/src/main/scala/ifu/ifu_bp_ctl.scala +++ b/src/main/scala/ifu/ifu_bp_ctl.scala @@ -370,7 +370,9 @@ if(!BTB_FULLYA) { val rets_out = Wire(Vec(RET_STACK_SIZE, UInt(32.W))) rets_out := (0 until RET_STACK_SIZE).map(i=>0.U) // Final target if its a RET then pop else take the target pc - io.ifu_bp_btb_target_f := ((Fill(31,(btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0) & io.ifu_bp_hit_taken_f)) & rets_out(0)(31,1)) | + + // mux in the return stack address here for a predicted return assuming the RS is valid, quite if no prediction + io.ifu_bp_btb_target_f := ((Fill(31,(btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0) & io.ifu_bp_hit_taken_f)) & rets_out(0)(31,1)) | (Fill(31,(!btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0) & io.ifu_bp_hit_taken_f)) & bp_btb_target_adder_f(31,1))) // Return stack @@ -437,7 +439,11 @@ if(!BTB_FULLYA) { // Writing is always done from dec or exu check if the dec have a valid data val btb_wr_addr = Mux(dec_tlu_error_wb.asBool, btb_error_addr_wb, exu_mp_addr) - vwayhit_f := (Fill(2,io.ifc_fetch_addr_f(0)) & wayhit_f(1,0)) | ((Fill(2,io.ifc_fetch_addr_f(1)) & Cat(wayhit_p1_f(0),wayhit_f(1))) & Cat(eoc_mask,1.U)) + val vwayhit_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool->wayhit_f, + io.ifc_fetch_addr_f(0).asBool->Cat(wayhit_p1_f(0), wayhit_f(1)))) & Cat(eoc_mask, 1.U(1.W)) + + + // vwayhit_f := (Fill(2,io.ifc_fetch_addr_f(0)) & wayhit_f(1,0)) | ((Fill(2,io.ifc_fetch_addr_f(1)) & Cat(wayhit_p1_f(0),wayhit_f(1))) & Cat(eoc_mask,1.U)) val btb_bank0_rd_data_way0_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way0).asBool, clock, io.scan_mode)) val btb_bank0_rd_data_way1_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way1).asBool, clock, io.scan_mode)) @@ -449,59 +455,60 @@ if(!BTB_FULLYA) { btb_bank0_rd_data_way0_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way0_out(i))) btb_bank0_rd_data_way1_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way1_out(i))) } - if(BTB_FULLYA){ - val fetch_mp_collision_f = WireInit(Bool(),init = false.B) - val fetch_mp_collision_p1_f = WireInit(Bool() ,init = false.B) - - // Fully Associative tag hash uses bits 31:3. Bits 2:1 are the offset bits used for the 4 tag comp banks - // Full tag used to speed up lookup. There is one 31:3 cmp per entry, and 4 2:1 cmps per entry. - val ifc_fetch_addr_p1_f = io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1) + 1.U - - // val fetch_mp_collision_f = ((io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === io.ifc_fetch_addr_f) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way) - // val fetch_mp_collision_p1_f = ( (io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === Cat(io.ifc_fetch_addr_f(30,FA_CMP_LOWER), ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1))) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way) - // val btb_upper_hit = Wire(Vec(BTB_SIZE,Bool())) - val btb_offset_0 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U) - val btb_used = WireInit(UInt(BTB_SIZE.W) ,init = 0.U) - val btb_offset_1 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U) - val wr0_en = WireInit(UInt(BTB_SIZE.W) ,init = 0.U) - val btbdata = Wire(Vec(BTB_SIZE,UInt(BTB_DWIDTH.W))) - btbdata := btbdata.map(i=> 0.U) - val hit0 = WireInit(UInt(1.W) ,init = 0.U) - val hit1 = WireInit(UInt(1.W) ,init = 0.U) - - // btb_upper_hit := (0 until BTB_SIZE).map(i=> ((btbdata(i)(BTB_DWIDTH_TOP,FA_TAG_END_UPPER) === io.ifc_fetch_addr_f(30,FA_CMP_LOWER)) & btbdata(i)(0) & ~wr0_en(i))) - // val btb_offset_0 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i)) - // val btb_offset_1 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i)) - - // hit unless we are also writing this entry at the same time - val hit0_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_0(i) -> i.U)) - val hit1_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_1(i) -> i.U)) - // Mux out the 2 potential branches - btb_vbank0_rd_data_f := (0 until BTB_SIZE ).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_f,btb_wr_data,btbdata(i)) else 0.U ).reverse.reduce(Cat(_,_)) - btb_vbank1_rd_data_f :=(0 until BTB_SIZE).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_p1_f,btb_wr_data,btbdata(i)) else 0.U).reverse.reduce(Cat(_,_)) - val btb_fa_wr_addr0 = MuxCase(1.U, (0 until BTB_SIZE).map(i=> !btb_used(i) -> i.U)) - - vwayhit_f := Cat(hit1,hit0) & Cat(eoc_mask,1.U) - way_raw := vwayhit_f | Cat(fetch_mp_collision_p1_f, fetch_mp_collision_f) - wr0_en := (0 until BTB_SIZE).map(i=> ((btb_fa_wr_addr0(BTB_FA_INDEX,0) === i.asUInt()) & (exu_mp_valid_write & ~io.exu_bp.exu_mp_pkt.bits.way)) | - ((io.dec_fa_error_index === i.asUInt()) & dec_tlu_error_wb)).reverse.reduce(Cat(_,_)) - btbdata := (0 until BTB_SIZE).map(i=> rvdffe(btb_wr_data,wr0_en(i),clock,io.scan_mode)) - - io.ifu_bp_fa_index_f(1) := Mux(hit1,hit1_index,0.U) - io.ifu_bp_fa_index_f(0) := Mux(hit0,hit0_index,0.U) - - val btb_used_reset = btb_used.andR() - val btb_used_ns = Mux1H(Seq( - vwayhit_f(1).asBool -> (1.U(32.W) << hit1_index(BTB_FA_INDEX,0)), - vwayhit_f(0).asBool() -> (1.U(32.W) << hit0_index(BTB_FA_INDEX,0)), - (exu_mp_valid_write & !io.exu_bp.exu_mp_pkt.bits.way & !dec_tlu_error_wb).asBool() -> (1.U(32.W) << btb_fa_wr_addr0(BTB_FA_INDEX,0)), - btb_used_reset.asBool -> Fill(BTB_SIZE,0.U), - (!btb_used_reset & dec_tlu_error_wb ).asBool -> (btb_used & ~(1.U(32.W) << io.dec_fa_error_index(BTB_FA_INDEX,0))), - !(btb_used_reset | dec_tlu_error_wb ).asBool() -> btb_used - )) - val write_used = btb_used_reset | io.ifu_bp_hit_taken_f | exu_mp_valid_write | dec_tlu_error_wb - btb_used := rvdffe(btb_used_ns,write_used.asBool(),clock,io.scan_mode) - } +// if(BTB_FULLYA){ +// val fetch_mp_collision_f = WireInit(Bool(),init = false.B) +// val fetch_mp_collision_p1_f = WireInit(Bool() ,init = false.B) +// +// // Fully Associative tag hash uses bits 31:3. Bits 2:1 are the offset bits used for the 4 tag comp banks +// // Full tag used to speed up lookup. There is one 31:3 cmp per entry, and 4 2:1 cmps per entry. +// val ifc_fetch_addr_p1_f = io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1) + 1.U +// +// +// // val fetch_mp_collision_f = ((io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === io.ifc_fetch_addr_f) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way) +// // val fetch_mp_collision_p1_f = ( (io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === Cat(io.ifc_fetch_addr_f(30,FA_CMP_LOWER), ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1))) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way) +// // val btb_upper_hit = Wire(Vec(BTB_SIZE,Bool())) +// val btb_offset_0 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U) +// val btb_used = WireInit(UInt(BTB_SIZE.W) ,init = 0.U) +// val btb_offset_1 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U) +// val wr0_en = WireInit(UInt(BTB_SIZE.W) ,init = 0.U) +// val btbdata = Wire(Vec(BTB_SIZE,UInt(BTB_DWIDTH.W))) +// btbdata := btbdata.map(i=> 0.U) +// val hit0 = WireInit(UInt(1.W) ,init = 0.U) +// val hit1 = WireInit(UInt(1.W) ,init = 0.U) +// +// // btb_upper_hit := (0 until BTB_SIZE).map(i=> ((btbdata(i)(BTB_DWIDTH_TOP,FA_TAG_END_UPPER) === io.ifc_fetch_addr_f(30,FA_CMP_LOWER)) & btbdata(i)(0) & ~wr0_en(i))) +// // val btb_offset_0 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i)) +// // val btb_offset_1 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i)) +// +// // hit unless we are also writing this entry at the same time +// val hit0_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_0(i) -> i.U)) +// val hit1_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_1(i) -> i.U)) +// // Mux out the 2 potential branches +// btb_vbank0_rd_data_f := (0 until BTB_SIZE ).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_f,btb_wr_data,btbdata(i)) else 0.U ).reverse.reduce(Cat(_,_)) +// btb_vbank1_rd_data_f :=(0 until BTB_SIZE).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_p1_f,btb_wr_data,btbdata(i)) else 0.U).reverse.reduce(Cat(_,_)) +// val btb_fa_wr_addr0 = MuxCase(1.U, (0 until BTB_SIZE).map(i=> !btb_used(i) -> i.U)) +// +// vwayhit_f := Cat(hit1,hit0) & Cat(eoc_mask,1.U) +// way_raw := vwayhit_f | Cat(fetch_mp_collision_p1_f, fetch_mp_collision_f) +// wr0_en := (0 until BTB_SIZE).map(i=> ((btb_fa_wr_addr0(BTB_FA_INDEX,0) === i.asUInt()) & (exu_mp_valid_write & ~io.exu_bp.exu_mp_pkt.bits.way)) | +// ((io.dec_fa_error_index === i.asUInt()) & dec_tlu_error_wb)).reverse.reduce(Cat(_,_)) +// btbdata := (0 until BTB_SIZE).map(i=> rvdffe(btb_wr_data,wr0_en(i),clock,io.scan_mode)) +// +// io.ifu_bp_fa_index_f(1) := Mux(hit1,hit1_index,0.U) +// io.ifu_bp_fa_index_f(0) := Mux(hit0,hit0_index,0.U) +// +// val btb_used_reset = btb_used.andR() +// val btb_used_ns = Mux1H(Seq( +// vwayhit_f(1).asBool -> (1.U(32.W) << hit1_index(BTB_FA_INDEX,0)), +// vwayhit_f(0).asBool() -> (1.U(32.W) << hit0_index(BTB_FA_INDEX,0)), +// (exu_mp_valid_write & !io.exu_bp.exu_mp_pkt.bits.way & !dec_tlu_error_wb).asBool() -> (1.U(32.W) << btb_fa_wr_addr0(BTB_FA_INDEX,0)), +// btb_used_reset.asBool -> Fill(BTB_SIZE,0.U), +// (!btb_used_reset & dec_tlu_error_wb ).asBool -> (btb_used & ~(1.U(32.W) << io.dec_fa_error_index(BTB_FA_INDEX,0))), +// !(btb_used_reset | dec_tlu_error_wb ).asBool() -> btb_used +// )) +// val write_used = btb_used_reset | io.ifu_bp_hit_taken_f | exu_mp_valid_write | dec_tlu_error_wb +// btb_used := rvdffe(btb_used_ns,write_used.asBool(),clock,io.scan_mode) +// } val bht_bank_clken = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH/NUM_BHT_LOOP, Bool()))) @@ -540,6 +547,6 @@ if(!BTB_FULLYA) { bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f===i.U).asBool->bht_bank_rd_data_out(1)(i))) bht_bank0_rd_data_p1_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_p1_f===i.U).asBool->bht_bank_rd_data_out(0)(i))) } -object bp extends App { +object bp_MAIN extends App { println((new chisel3.stage.ChiselStage).emitVerilog(new ifu_bp_ctl())) } \ No newline at end of file diff --git a/src/main/scala/lib/param.scala b/src/main/scala/lib/param.scala index 9690eea7..b1fd6ff6 100644 --- a/src/main/scala/lib/param.scala +++ b/src/main/scala/lib/param.scala @@ -161,5 +161,4 @@ trait param { val BTB_ENABLE = 0x1 val BTB_TOFFSET_SIZE = 0x00C val BTB_FULLYA = 0x00 - } diff --git a/target/scala-2.12/classes/ifu/bp$delayedInit$body.class b/target/scala-2.12/classes/ifu/bp$delayedInit$body.class deleted file mode 100644 index f19fe8ce74188bed9f0b1d555cb3ad8d890469ef..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 701 zcmZ`%O>fgc5Pjn$Hc8VaEu|lPrGSglR>D+*QxFm$Dn)V%QrcdtwY{a=I=1Dk5&2hu z_>efj5s4p#n03v8N?dk!-p;&z^LBsz{`MWfBitvfs*}PCGB=X3n8|3EDD4JmG;=_N z-ZT`k@bV(jY9hU7!BpoW)O$q|YLzAr9n=V2W;hPA<50&B%6fwBriGR{q3Kuj142V& zSv(^w_qY5r@m6@TNZxp_f-@QFK^r!lCM>iFPSxX}O<1dhy-cDkRf%@_&}F^5gj#>= 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