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Debug rd data

This commit is contained in:
waleed-lm 2020-10-26 11:17:36 +05:00
parent ed0a261ff1
commit ef58d385a4
7 changed files with 10299 additions and 10283 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

228
el2_ifu_mem_ctl.anno.json
View File

@ -7,6 +7,20 @@
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_access_fault_type_f",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_double_err",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_sel_premux_data",
@ -32,16 +46,57 @@
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_single_err",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rw_addr",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_addr",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_addr_bf",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_addr",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_dicawics"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_async_error_start",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_single_err",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_error_start",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_eccerr",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_tag_perr",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rid",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rvalid",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bus_clk_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_way",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_dicawics"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_wren",
@ -55,33 +110,7 @@
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_addr",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_dicawics"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_way",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_dicawics"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_access_fault_type_f",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_double_err",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
@ -94,32 +123,19 @@
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_double_err",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_access_fault_f",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rden",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rw_addr",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_addr",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_iccm_access_bf",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_req_bf",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_addr_bf",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_write",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
@ -127,16 +143,10 @@
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_access_fault_f",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_en",
@ -151,22 +161,6 @@
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_wr_data",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_wdata",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_premux_data",
@ -217,6 +211,35 @@
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_ready",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
@ -235,6 +258,16 @@
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bus_clk_en"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_tag_array",
@ -244,24 +277,10 @@
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_wr_data",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rden",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_iccm_access_bf",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_req_bf",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_iccm_req",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_write",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_wdata",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
@ -269,6 +288,7 @@
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
@ -281,15 +301,14 @@
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_ready",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_single_err",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_dma_sb_error",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_dma_access_ok",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
@ -317,29 +336,22 @@
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_wr_data",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_double_err",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_wrdata"
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_inst_mask_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_async_error_start",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_wr_data",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_single_err",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_error_start",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_eccerr",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_tag_perr",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rid",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_axi_rvalid",
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bus_clk_en"
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_wrdata"
]
},
{

14477
el2_ifu_mem_ctl.fir
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5872
el2_ifu_mem_ctl.v
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5
src/main/scala/ifu/el2_ifu_mem_ctl.scala
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@ -310,7 +310,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
reset_ic_ff := RegNext(reset_ic_in)
val fetch_uncacheable_ff = RegNext(io.ifc_fetch_uncacheable_bf, 0.U)
ifu_fetch_addr_int_f := RegNext(io.ifc_fetch_addr_bf, 0.U)
val vaddr_f = ifu_fetch_addr_int_f
val vaddr_f = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1, 0)
uncacheable_miss_ff := RegNext(uncacheable_miss_in, 0.U)
imb_ff := RegNext(imb_in)
val miss_addr = WireInit(UInt((31-ICACHE_BEAT_ADDR_HI).W), 0.U)
@ -399,8 +399,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
io.ic_access_fault_type_f := Mux(io.iccm_rd_ecc_double_err.asBool, 1.U,
Mux(ifc_region_acc_fault_f.asBool, 2.U,
Mux(ifc_region_acc_fault_memory_f.asBool(), 3.U, 0.U)))
val ifu_bp_inst_mask_f = WireInit(Bool(), 0.U)
io.ic_fetch_val_f := Cat(fetch_req_f_qual & ifu_bp_inst_mask_f & !(vaddr_f===Fill(ICACHE_BEAT_ADDR_HI,1.U)) & (err_stop_state=/=err_fetch2_C), fetch_req_f_qual)
io.ic_fetch_val_f := Cat(fetch_req_f_qual & io.ifu_bp_inst_mask_f & !(vaddr_f===Fill(ICACHE_BEAT_ADDR_HI,1.U)) & (err_stop_state=/=err_fetch2_C), fetch_req_f_qual)
val two_byte_instr = io.ic_data_f(1,0) =/= 3.U
//// Creating full buffer
val ifu_bus_rsp_rdata = WireInit(UInt(64.W), 0.U)

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target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class
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target/scala-2.12/classes/ifu/ifu_mem$.class
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target/scala-2.12/classes/ifu/ifu_mem$delayedInit$body.class
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