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axi to ahb update

This commit is contained in:
​Laraib Khan 2020-12-01 16:57:34 +05:00
parent a91a14fd34
commit eff5d74c44
3 changed files with 19 additions and 19 deletions
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32
axi4_to_ahb.fir
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@ -997,14 +997,14 @@ circuit axi4_to_ahb :
node _T_447 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 345:132] node _T_447 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 345:132]
wire _T_448 : UInt<8> wire _T_448 : UInt<8>
_T_448 <= UInt<8>("h00") _T_448 <= UInt<8>("h00")
node _T_449 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 174:44] node _T_449 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 174:45]
node _T_450 = eq(_T_449, UInt<8>("h0ff")) @[axi4_to_ahb.scala 174:51] node _T_450 = eq(_T_449, UInt<8>("h0ff")) @[axi4_to_ahb.scala 174:52]
node _T_451 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 174:75] node _T_451 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 174:76]
node _T_452 = eq(_T_451, UInt<4>("h0f")) @[axi4_to_ahb.scala 174:82] node _T_452 = eq(_T_451, UInt<4>("h0f")) @[axi4_to_ahb.scala 174:83]
node _T_453 = or(_T_450, _T_452) @[axi4_to_ahb.scala 174:64] node _T_453 = or(_T_450, _T_452) @[axi4_to_ahb.scala 174:65]
node _T_454 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 174:106] node _T_454 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 174:107]
node _T_455 = eq(_T_454, UInt<2>("h03")) @[axi4_to_ahb.scala 174:113] node _T_455 = eq(_T_454, UInt<2>("h03")) @[axi4_to_ahb.scala 174:114]
node _T_456 = or(_T_453, _T_455) @[axi4_to_ahb.scala 174:95] node _T_456 = or(_T_453, _T_455) @[axi4_to_ahb.scala 174:96]
node _T_457 = bits(_T_456, 0, 0) @[Bitwise.scala 72:15] node _T_457 = bits(_T_456, 0, 0) @[Bitwise.scala 72:15]
node _T_458 = mux(_T_457, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_458 = mux(_T_457, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_459 = and(UInt<1>("h00"), _T_458) @[axi4_to_ahb.scala 174:24] node _T_459 = and(UInt<1>("h00"), _T_458) @[axi4_to_ahb.scala 174:24]
@ -1013,7 +1013,7 @@ circuit axi4_to_ahb :
node _T_462 = bits(_T_461, 0, 0) @[Bitwise.scala 72:15] node _T_462 = bits(_T_461, 0, 0) @[Bitwise.scala 72:15]
node _T_463 = mux(_T_462, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_463 = mux(_T_462, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_464 = and(UInt<2>("h02"), _T_463) @[axi4_to_ahb.scala 175:15] node _T_464 = and(UInt<2>("h02"), _T_463) @[axi4_to_ahb.scala 175:15]
node _T_465 = or(_T_459, _T_464) @[axi4_to_ahb.scala 174:128] node _T_465 = or(_T_459, _T_464) @[axi4_to_ahb.scala 174:131]
node _T_466 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 176:36] node _T_466 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 176:36]
node _T_467 = eq(_T_466, UInt<8>("h0f0")) @[axi4_to_ahb.scala 176:43] node _T_467 = eq(_T_466, UInt<8>("h0f0")) @[axi4_to_ahb.scala 176:43]
node _T_468 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 176:67] node _T_468 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 176:67]
@ -1022,13 +1022,13 @@ circuit axi4_to_ahb :
node _T_471 = bits(_T_470, 0, 0) @[Bitwise.scala 72:15] node _T_471 = bits(_T_470, 0, 0) @[Bitwise.scala 72:15]
node _T_472 = mux(_T_471, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_472 = mux(_T_471, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_473 = and(UInt<3>("h04"), _T_472) @[axi4_to_ahb.scala 176:15] node _T_473 = and(UInt<3>("h04"), _T_472) @[axi4_to_ahb.scala 176:15]
node _T_474 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 177:37] node _T_474 = or(_T_465, _T_473) @[axi4_to_ahb.scala 175:58]
node _T_475 = eq(_T_474, UInt<8>("h0c0")) @[axi4_to_ahb.scala 177:44] node _T_475 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 177:37]
node _T_476 = bits(_T_475, 0, 0) @[Bitwise.scala 72:15] node _T_476 = eq(_T_475, UInt<8>("h0c0")) @[axi4_to_ahb.scala 177:44]
node _T_477 = mux(_T_476, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_477 = bits(_T_476, 0, 0) @[Bitwise.scala 72:15]
node _T_478 = and(UInt<3>("h06"), _T_477) @[axi4_to_ahb.scala 177:17] node _T_478 = mux(_T_477, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_479 = or(_T_473, _T_478) @[axi4_to_ahb.scala 176:90] node _T_479 = and(UInt<3>("h06"), _T_478) @[axi4_to_ahb.scala 177:17]
node _T_480 = or(_T_465, _T_479) @[axi4_to_ahb.scala 175:58] node _T_480 = or(_T_474, _T_479) @[axi4_to_ahb.scala 176:91]
node _T_481 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 345:152] node _T_481 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 345:152]
node _T_482 = mux(_T_446, _T_480, _T_481) @[axi4_to_ahb.scala 345:43] node _T_482 = mux(_T_446, _T_480, _T_481) @[axi4_to_ahb.scala 345:43]
node _T_483 = cat(_T_442, _T_482) @[Cat.scala 29:58] node _T_483 = cat(_T_442, _T_482) @[Cat.scala 29:58]

6
src/main/scala/lib/axi4_to_ahb.scala
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@ -171,10 +171,10 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
def get_write_addr(byteen_e: UInt) = { def get_write_addr(byteen_e: UInt) = {
val byteen_e = WireInit(0.U(8.W)) val byteen_e = WireInit(0.U(8.W))
val addr = ("h0".U & (Fill(3, (byteen_e(7, 0) === "hff".U) | (byteen_e(7, 0) === "h0f".U) | (byteen_e(7, 0) === "h03".U))) | val addr = ("h0".U & (Fill(3, ((byteen_e(7, 0) === "hff".U) | (byteen_e(7, 0) === "h0f".U) | (byteen_e(7, 0) === "h03".U))))) |
("h2".U & (Fill(3, (byteen_e(7, 0) === "h0c".U)))) | ("h2".U & (Fill(3, (byteen_e(7, 0) === "h0c".U)))) |
("h4".U & (Fill(3, ((byteen_e(7, 0) === "hf0".U) | (byteen_e(7, 0) === "h03".U)))) | ("h4".U & (Fill(3, ((byteen_e(7, 0) === "hf0".U) | (byteen_e(7, 0) === "h03".U))))) |
("h6".U & (Fill(3, (byteen_e(7, 0) === "hc0".U)))))) ("h6".U & (Fill(3, (byteen_e(7, 0) === "hc0".U))))
addr addr
} }

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target/scala-2.12/classes/lib/axi4_to_ahb.class
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