From effba077f4c633917aa1c92dfd52b4ccdabb1a00 Mon Sep 17 00:00:00 2001
From: waleed-lm <waleed.ehsan@lampromellon.com>
Date: Thu, 1 Oct 2020 18:31:31 +0500
Subject: [PATCH] Bug introduced

---
 el2_ifu_ifc_ctl.fir                           | 351 +++++++++---------
 el2_ifu_ifc_ctl.v                             | 209 ++++++-----
 src/main/scala/ifu/el2_ifu_ifc_ctl.scala      |  55 +--
 .../classes/ifu/el2_ifu_ifc_ctl.class         | Bin 116300 -> 116259 bytes
 4 files changed, 307 insertions(+), 308 deletions(-)

diff --git a/el2_ifu_ifc_ctl.fir b/el2_ifu_ifc_ctl.fir
index 7e167e5d..9cc3dc93 100644
--- a/el2_ifu_ifc_ctl.fir
+++ b/el2_ifu_ifc_ctl.fir
@@ -85,187 +85,186 @@ circuit el2_ifu_ifc_ctl :
     node _T_25 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctl.scala 77:42]
     node _T_26 = add(_T_25, UInt<1>("h01")) @[el2_ifu_ifc_ctl.scala 77:48]
     node address_upper = tail(_T_26, 1) @[el2_ifu_ifc_ctl.scala 77:48]
-    node _T_27 = bits(address_upper, 5, 5) @[el2_ifu_ifc_ctl.scala 78:39]
-    node _T_28 = bits(io.ifc_fetch_addr_f, 5, 5) @[el2_ifu_ifc_ctl.scala 78:84]
-    node _T_29 = xor(_T_27, _T_28) @[el2_ifu_ifc_ctl.scala 78:63]
-    node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 78:24]
-    node _T_31 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctl.scala 78:130]
-    node _T_32 = and(_T_30, _T_31) @[el2_ifu_ifc_ctl.scala 78:109]
-    fetch_addr_next_0 <= _T_32 @[el2_ifu_ifc_ctl.scala 78:21]
-    node _T_33 = cat(address_upper, fetch_addr_next_0) @[Cat.scala 29:58]
-    fetch_addr_next <= _T_33 @[el2_ifu_ifc_ctl.scala 80:19]
-    node _T_34 = not(idle) @[el2_ifu_ifc_ctl.scala 82:30]
-    io.ifc_fetch_req_bf_raw <= _T_34 @[el2_ifu_ifc_ctl.scala 82:27]
-    node _T_35 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 84:91]
-    node _T_36 = eq(_T_35, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:70]
-    node _T_37 = and(fb_full_f_ns, _T_36) @[el2_ifu_ifc_ctl.scala 84:68]
-    node _T_38 = eq(_T_37, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:53]
-    node _T_39 = and(io.ifc_fetch_req_bf_raw, _T_38) @[el2_ifu_ifc_ctl.scala 84:51]
-    node _T_40 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:5]
-    node _T_41 = and(_T_39, _T_40) @[el2_ifu_ifc_ctl.scala 84:114]
-    node _T_42 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:18]
-    node _T_43 = and(_T_41, _T_42) @[el2_ifu_ifc_ctl.scala 85:16]
-    node _T_44 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:39]
-    node _T_45 = and(_T_43, _T_44) @[el2_ifu_ifc_ctl.scala 85:37]
-    io.ifc_fetch_req_bf <= _T_45 @[el2_ifu_ifc_ctl.scala 84:23]
-    node _T_46 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 87:37]
-    fetch_bf_en <= _T_46 @[el2_ifu_ifc_ctl.scala 87:15]
-    node _T_47 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:34]
-    node _T_48 = and(io.ifc_fetch_req_f, _T_47) @[el2_ifu_ifc_ctl.scala 89:32]
-    node _T_49 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:49]
-    node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctl.scala 89:47]
-    miss_f <= _T_50 @[el2_ifu_ifc_ctl.scala 89:10]
-    node _T_51 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 91:39]
-    node _T_52 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:63]
-    node _T_53 = and(_T_51, _T_52) @[el2_ifu_ifc_ctl.scala 91:61]
-    node _T_54 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:76]
-    node _T_55 = and(_T_53, _T_54) @[el2_ifu_ifc_ctl.scala 91:74]
-    node _T_56 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:86]
-    node _T_57 = and(_T_55, _T_56) @[el2_ifu_ifc_ctl.scala 91:84]
-    mb_empty_mod <= _T_57 @[el2_ifu_ifc_ctl.scala 91:16]
-    node _T_58 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctl.scala 93:35]
-    goto_idle <= _T_58 @[el2_ifu_ifc_ctl.scala 93:13]
-    node _T_59 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 95:38]
-    node _T_60 = and(io.exu_flush_final, _T_59) @[el2_ifu_ifc_ctl.scala 95:36]
-    node _T_61 = and(_T_60, idle) @[el2_ifu_ifc_ctl.scala 95:67]
-    leave_idle <= _T_61 @[el2_ifu_ifc_ctl.scala 95:14]
-    node _T_62 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 97:29]
-    node _T_63 = eq(_T_62, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:23]
-    node _T_64 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 97:40]
-    node _T_65 = and(_T_63, _T_64) @[el2_ifu_ifc_ctl.scala 97:33]
-    node _T_66 = and(_T_65, miss_f) @[el2_ifu_ifc_ctl.scala 97:44]
-    node _T_67 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:55]
-    node _T_68 = and(_T_66, _T_67) @[el2_ifu_ifc_ctl.scala 97:53]
-    node _T_69 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 98:11]
-    node _T_70 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:17]
-    node _T_71 = and(_T_69, _T_70) @[el2_ifu_ifc_ctl.scala 98:15]
-    node _T_72 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:33]
-    node _T_73 = and(_T_71, _T_72) @[el2_ifu_ifc_ctl.scala 98:31]
-    node next_state_1 = or(_T_68, _T_73) @[el2_ifu_ifc_ctl.scala 97:67]
-    node _T_74 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:23]
-    node _T_75 = and(_T_74, leave_idle) @[el2_ifu_ifc_ctl.scala 100:34]
-    node _T_76 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 100:56]
-    node _T_77 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:62]
-    node _T_78 = and(_T_76, _T_77) @[el2_ifu_ifc_ctl.scala 100:60]
-    node next_state_0 = or(_T_75, _T_78) @[el2_ifu_ifc_ctl.scala 100:48]
-    node _T_79 = cat(next_state_1, next_state_0) @[Cat.scala 29:58]
-    reg _T_80 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 102:19]
-    _T_80 <= _T_79 @[el2_ifu_ifc_ctl.scala 102:19]
-    state <= _T_80 @[el2_ifu_ifc_ctl.scala 102:9]
+    node _T_27 = bits(address_upper, 5, 5) @[el2_ifu_ifc_ctl.scala 78:38]
+    node _T_28 = bits(io.ifc_fetch_addr_f, 5, 5) @[el2_ifu_ifc_ctl.scala 78:83]
+    node _T_29 = xor(_T_27, _T_28) @[el2_ifu_ifc_ctl.scala 78:62]
+    node _T_30 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctl.scala 78:129]
+    node _T_31 = and(_T_29, _T_30) @[el2_ifu_ifc_ctl.scala 78:108]
+    fetch_addr_next_0 <= _T_31 @[el2_ifu_ifc_ctl.scala 78:21]
+    node _T_32 = cat(address_upper, fetch_addr_next_0) @[Cat.scala 29:58]
+    fetch_addr_next <= _T_32 @[el2_ifu_ifc_ctl.scala 80:19]
+    node _T_33 = not(idle) @[el2_ifu_ifc_ctl.scala 82:30]
+    io.ifc_fetch_req_bf_raw <= _T_33 @[el2_ifu_ifc_ctl.scala 82:27]
+    node _T_34 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 84:91]
+    node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:70]
+    node _T_36 = and(fb_full_f_ns, _T_35) @[el2_ifu_ifc_ctl.scala 84:68]
+    node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:53]
+    node _T_38 = and(io.ifc_fetch_req_bf_raw, _T_37) @[el2_ifu_ifc_ctl.scala 84:51]
+    node _T_39 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:5]
+    node _T_40 = and(_T_38, _T_39) @[el2_ifu_ifc_ctl.scala 84:114]
+    node _T_41 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:18]
+    node _T_42 = and(_T_40, _T_41) @[el2_ifu_ifc_ctl.scala 85:16]
+    node _T_43 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:39]
+    node _T_44 = and(_T_42, _T_43) @[el2_ifu_ifc_ctl.scala 85:37]
+    io.ifc_fetch_req_bf <= _T_44 @[el2_ifu_ifc_ctl.scala 84:23]
+    node _T_45 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 87:37]
+    fetch_bf_en <= _T_45 @[el2_ifu_ifc_ctl.scala 87:15]
+    node _T_46 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:34]
+    node _T_47 = and(io.ifc_fetch_req_f, _T_46) @[el2_ifu_ifc_ctl.scala 89:32]
+    node _T_48 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:49]
+    node _T_49 = and(_T_47, _T_48) @[el2_ifu_ifc_ctl.scala 89:47]
+    miss_f <= _T_49 @[el2_ifu_ifc_ctl.scala 89:10]
+    node _T_50 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 91:39]
+    node _T_51 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:63]
+    node _T_52 = and(_T_50, _T_51) @[el2_ifu_ifc_ctl.scala 91:61]
+    node _T_53 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:76]
+    node _T_54 = and(_T_52, _T_53) @[el2_ifu_ifc_ctl.scala 91:74]
+    node _T_55 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:86]
+    node _T_56 = and(_T_54, _T_55) @[el2_ifu_ifc_ctl.scala 91:84]
+    mb_empty_mod <= _T_56 @[el2_ifu_ifc_ctl.scala 91:16]
+    node _T_57 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctl.scala 93:35]
+    goto_idle <= _T_57 @[el2_ifu_ifc_ctl.scala 93:13]
+    node _T_58 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 95:38]
+    node _T_59 = and(io.exu_flush_final, _T_58) @[el2_ifu_ifc_ctl.scala 95:36]
+    node _T_60 = and(_T_59, idle) @[el2_ifu_ifc_ctl.scala 95:67]
+    leave_idle <= _T_60 @[el2_ifu_ifc_ctl.scala 95:14]
+    node _T_61 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 97:29]
+    node _T_62 = eq(_T_61, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:23]
+    node _T_63 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 97:40]
+    node _T_64 = and(_T_62, _T_63) @[el2_ifu_ifc_ctl.scala 97:33]
+    node _T_65 = and(_T_64, miss_f) @[el2_ifu_ifc_ctl.scala 97:44]
+    node _T_66 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:55]
+    node _T_67 = and(_T_65, _T_66) @[el2_ifu_ifc_ctl.scala 97:53]
+    node _T_68 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 98:11]
+    node _T_69 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:17]
+    node _T_70 = and(_T_68, _T_69) @[el2_ifu_ifc_ctl.scala 98:15]
+    node _T_71 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:33]
+    node _T_72 = and(_T_70, _T_71) @[el2_ifu_ifc_ctl.scala 98:31]
+    node next_state_1 = or(_T_67, _T_72) @[el2_ifu_ifc_ctl.scala 97:67]
+    node _T_73 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:23]
+    node _T_74 = and(_T_73, leave_idle) @[el2_ifu_ifc_ctl.scala 100:34]
+    node _T_75 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 100:56]
+    node _T_76 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:62]
+    node _T_77 = and(_T_75, _T_76) @[el2_ifu_ifc_ctl.scala 100:60]
+    node next_state_0 = or(_T_74, _T_77) @[el2_ifu_ifc_ctl.scala 100:48]
+    node _T_78 = cat(next_state_1, next_state_0) @[Cat.scala 29:58]
+    reg _T_79 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 102:19]
+    _T_79 <= _T_78 @[el2_ifu_ifc_ctl.scala 102:19]
+    state <= _T_79 @[el2_ifu_ifc_ctl.scala 102:9]
     flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctl.scala 104:12]
-    node _T_81 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:38]
-    node _T_82 = and(io.ifu_fb_consume1, _T_81) @[el2_ifu_ifc_ctl.scala 106:36]
-    node _T_83 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:61]
-    node _T_84 = or(_T_83, miss_f) @[el2_ifu_ifc_ctl.scala 106:81]
-    node _T_85 = and(_T_82, _T_84) @[el2_ifu_ifc_ctl.scala 106:58]
-    node _T_86 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 107:25]
-    node _T_87 = or(_T_85, _T_86) @[el2_ifu_ifc_ctl.scala 106:92]
-    fb_right <= _T_87 @[el2_ifu_ifc_ctl.scala 106:12]
-    node _T_88 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 109:39]
-    node _T_89 = or(_T_88, miss_f) @[el2_ifu_ifc_ctl.scala 109:59]
-    node _T_90 = and(io.ifu_fb_consume2, _T_89) @[el2_ifu_ifc_ctl.scala 109:36]
-    fb_right2 <= _T_90 @[el2_ifu_ifc_ctl.scala 109:13]
-    node _T_91 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctl.scala 110:56]
-    node _T_92 = eq(_T_91, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:35]
-    node _T_93 = and(io.ifc_fetch_req_f, _T_92) @[el2_ifu_ifc_ctl.scala 110:33]
-    node _T_94 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:80]
-    node _T_95 = and(_T_93, _T_94) @[el2_ifu_ifc_ctl.scala 110:78]
-    fb_left <= _T_95 @[el2_ifu_ifc_ctl.scala 110:11]
-    node _T_96 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctl.scala 112:37]
-    node _T_97 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 113:6]
-    node _T_98 = and(_T_97, fb_right) @[el2_ifu_ifc_ctl.scala 113:16]
-    node _T_99 = bits(_T_98, 0, 0) @[el2_ifu_ifc_ctl.scala 113:28]
-    node _T_100 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctl.scala 113:62]
-    node _T_101 = cat(UInt<1>("h00"), _T_100) @[Cat.scala 29:58]
-    node _T_102 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 114:6]
-    node _T_103 = and(_T_102, fb_right2) @[el2_ifu_ifc_ctl.scala 114:16]
-    node _T_104 = bits(_T_103, 0, 0) @[el2_ifu_ifc_ctl.scala 114:29]
-    node _T_105 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctl.scala 114:63]
-    node _T_106 = cat(UInt<2>("h00"), _T_105) @[Cat.scala 29:58]
-    node _T_107 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 115:6]
-    node _T_108 = and(_T_107, fb_left) @[el2_ifu_ifc_ctl.scala 115:16]
-    node _T_109 = bits(_T_108, 0, 0) @[el2_ifu_ifc_ctl.scala 115:27]
-    node _T_110 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctl.scala 115:51]
-    node _T_111 = cat(_T_110, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_112 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:6]
-    node _T_113 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:18]
-    node _T_114 = and(_T_112, _T_113) @[el2_ifu_ifc_ctl.scala 116:16]
-    node _T_115 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:30]
-    node _T_116 = and(_T_114, _T_115) @[el2_ifu_ifc_ctl.scala 116:28]
-    node _T_117 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:43]
-    node _T_118 = and(_T_116, _T_117) @[el2_ifu_ifc_ctl.scala 116:41]
-    node _T_119 = bits(_T_118, 0, 0) @[el2_ifu_ifc_ctl.scala 116:53]
-    node _T_120 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctl.scala 116:73]
-    node _T_121 = mux(_T_96, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_122 = mux(_T_99, _T_101, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_123 = mux(_T_104, _T_106, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_124 = mux(_T_109, _T_111, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_125 = mux(_T_119, _T_120, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_126 = or(_T_121, _T_122) @[Mux.scala 27:72]
+    node _T_80 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:38]
+    node _T_81 = and(io.ifu_fb_consume1, _T_80) @[el2_ifu_ifc_ctl.scala 106:36]
+    node _T_82 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:61]
+    node _T_83 = or(_T_82, miss_f) @[el2_ifu_ifc_ctl.scala 106:81]
+    node _T_84 = and(_T_81, _T_83) @[el2_ifu_ifc_ctl.scala 106:58]
+    node _T_85 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 107:25]
+    node _T_86 = or(_T_84, _T_85) @[el2_ifu_ifc_ctl.scala 106:92]
+    fb_right <= _T_86 @[el2_ifu_ifc_ctl.scala 106:12]
+    node _T_87 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 109:39]
+    node _T_88 = or(_T_87, miss_f) @[el2_ifu_ifc_ctl.scala 109:59]
+    node _T_89 = and(io.ifu_fb_consume2, _T_88) @[el2_ifu_ifc_ctl.scala 109:36]
+    fb_right2 <= _T_89 @[el2_ifu_ifc_ctl.scala 109:13]
+    node _T_90 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctl.scala 110:56]
+    node _T_91 = eq(_T_90, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:35]
+    node _T_92 = and(io.ifc_fetch_req_f, _T_91) @[el2_ifu_ifc_ctl.scala 110:33]
+    node _T_93 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:80]
+    node _T_94 = and(_T_92, _T_93) @[el2_ifu_ifc_ctl.scala 110:78]
+    fb_left <= _T_94 @[el2_ifu_ifc_ctl.scala 110:11]
+    node _T_95 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctl.scala 112:37]
+    node _T_96 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 113:6]
+    node _T_97 = and(_T_96, fb_right) @[el2_ifu_ifc_ctl.scala 113:16]
+    node _T_98 = bits(_T_97, 0, 0) @[el2_ifu_ifc_ctl.scala 113:28]
+    node _T_99 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctl.scala 113:62]
+    node _T_100 = cat(UInt<1>("h00"), _T_99) @[Cat.scala 29:58]
+    node _T_101 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 114:6]
+    node _T_102 = and(_T_101, fb_right2) @[el2_ifu_ifc_ctl.scala 114:16]
+    node _T_103 = bits(_T_102, 0, 0) @[el2_ifu_ifc_ctl.scala 114:29]
+    node _T_104 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctl.scala 114:63]
+    node _T_105 = cat(UInt<2>("h00"), _T_104) @[Cat.scala 29:58]
+    node _T_106 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 115:6]
+    node _T_107 = and(_T_106, fb_left) @[el2_ifu_ifc_ctl.scala 115:16]
+    node _T_108 = bits(_T_107, 0, 0) @[el2_ifu_ifc_ctl.scala 115:27]
+    node _T_109 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctl.scala 115:51]
+    node _T_110 = cat(_T_109, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_111 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:6]
+    node _T_112 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:18]
+    node _T_113 = and(_T_111, _T_112) @[el2_ifu_ifc_ctl.scala 116:16]
+    node _T_114 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:30]
+    node _T_115 = and(_T_113, _T_114) @[el2_ifu_ifc_ctl.scala 116:28]
+    node _T_116 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:43]
+    node _T_117 = and(_T_115, _T_116) @[el2_ifu_ifc_ctl.scala 116:41]
+    node _T_118 = bits(_T_117, 0, 0) @[el2_ifu_ifc_ctl.scala 116:53]
+    node _T_119 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctl.scala 116:73]
+    node _T_120 = mux(_T_95, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_121 = mux(_T_98, _T_100, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_122 = mux(_T_103, _T_105, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_123 = mux(_T_108, _T_110, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_124 = mux(_T_118, _T_119, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_125 = or(_T_120, _T_121) @[Mux.scala 27:72]
+    node _T_126 = or(_T_125, _T_122) @[Mux.scala 27:72]
     node _T_127 = or(_T_126, _T_123) @[Mux.scala 27:72]
     node _T_128 = or(_T_127, _T_124) @[Mux.scala 27:72]
-    node _T_129 = or(_T_128, _T_125) @[Mux.scala 27:72]
-    wire _T_130 : UInt<4> @[Mux.scala 27:72]
-    _T_130 <= _T_129 @[Mux.scala 27:72]
-    fb_write_ns <= _T_130 @[el2_ifu_ifc_ctl.scala 112:15]
-    node _T_131 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 119:38]
-    reg _T_132 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 119:26]
-    _T_132 <= _T_131 @[el2_ifu_ifc_ctl.scala 119:26]
-    fb_full_f_ns <= _T_132 @[el2_ifu_ifc_ctl.scala 119:16]
-    node _T_133 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctl.scala 121:17]
-    idle <= _T_133 @[el2_ifu_ifc_ctl.scala 121:8]
-    node _T_134 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctl.scala 122:16]
-    wfm <= _T_134 @[el2_ifu_ifc_ctl.scala 122:7]
-    node _T_135 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 124:30]
-    fb_full_f_ns <= _T_135 @[el2_ifu_ifc_ctl.scala 124:16]
+    wire _T_129 : UInt<4> @[Mux.scala 27:72]
+    _T_129 <= _T_128 @[Mux.scala 27:72]
+    fb_write_ns <= _T_129 @[el2_ifu_ifc_ctl.scala 112:15]
+    node _T_130 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 119:38]
+    reg _T_131 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 119:26]
+    _T_131 <= _T_130 @[el2_ifu_ifc_ctl.scala 119:26]
+    fb_full_f_ns <= _T_131 @[el2_ifu_ifc_ctl.scala 119:16]
+    node _T_132 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctl.scala 121:17]
+    idle <= _T_132 @[el2_ifu_ifc_ctl.scala 121:8]
+    node _T_133 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctl.scala 122:16]
+    wfm <= _T_133 @[el2_ifu_ifc_ctl.scala 122:7]
+    node _T_134 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 124:30]
+    fb_full_f_ns <= _T_134 @[el2_ifu_ifc_ctl.scala 124:16]
     reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 125:26]
     fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctl.scala 125:26]
-    reg _T_136 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 126:24]
-    _T_136 <= fb_write_ns @[el2_ifu_ifc_ctl.scala 126:24]
-    fb_write_f <= _T_136 @[el2_ifu_ifc_ctl.scala 126:14]
-    node _T_137 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 129:40]
-    node _T_138 = or(_T_137, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 129:61]
-    node _T_139 = eq(_T_138, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 129:19]
-    node _T_140 = and(fb_full_f, _T_139) @[el2_ifu_ifc_ctl.scala 129:17]
-    node _T_141 = or(_T_140, dma_stall) @[el2_ifu_ifc_ctl.scala 129:84]
-    node _T_142 = and(io.ifc_fetch_req_bf_raw, _T_141) @[el2_ifu_ifc_ctl.scala 128:60]
-    node _T_143 = or(wfm, _T_142) @[el2_ifu_ifc_ctl.scala 128:33]
-    io.ifu_pmu_fetch_stall <= _T_143 @[el2_ifu_ifc_ctl.scala 128:26]
-    node _T_144 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_145 = bits(_T_144, 31, 28) @[el2_lib.scala 211:25]
-    node iccm_acc_in_region_bf = eq(_T_145, UInt<4>("h0e")) @[el2_lib.scala 211:47]
-    node _T_146 = bits(_T_144, 31, 16) @[el2_lib.scala 214:14]
-    node iccm_acc_in_range_bf = eq(_T_146, UInt<16>("h0ee00")) @[el2_lib.scala 214:29]
+    reg _T_135 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 126:24]
+    _T_135 <= fb_write_ns @[el2_ifu_ifc_ctl.scala 126:24]
+    fb_write_f <= _T_135 @[el2_ifu_ifc_ctl.scala 126:14]
+    node _T_136 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 129:40]
+    node _T_137 = or(_T_136, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 129:61]
+    node _T_138 = eq(_T_137, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 129:19]
+    node _T_139 = and(fb_full_f, _T_138) @[el2_ifu_ifc_ctl.scala 129:17]
+    node _T_140 = or(_T_139, dma_stall) @[el2_ifu_ifc_ctl.scala 129:84]
+    node _T_141 = and(io.ifc_fetch_req_bf_raw, _T_140) @[el2_ifu_ifc_ctl.scala 128:60]
+    node _T_142 = or(wfm, _T_141) @[el2_ifu_ifc_ctl.scala 128:33]
+    io.ifu_pmu_fetch_stall <= _T_142 @[el2_ifu_ifc_ctl.scala 128:26]
+    node _T_143 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_144 = bits(_T_143, 31, 28) @[el2_lib.scala 211:25]
+    node iccm_acc_in_region_bf = eq(_T_144, UInt<4>("h0e")) @[el2_lib.scala 211:47]
+    node _T_145 = bits(_T_143, 31, 16) @[el2_lib.scala 214:14]
+    node iccm_acc_in_range_bf = eq(_T_145, UInt<16>("h0ee00")) @[el2_lib.scala 214:29]
     io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctl.scala 134:25]
-    node _T_147 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:30]
-    node _T_148 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 136:39]
-    node _T_149 = eq(_T_148, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 136:18]
-    node _T_150 = and(fb_full_f, _T_149) @[el2_ifu_ifc_ctl.scala 136:16]
-    node _T_151 = or(_T_147, _T_150) @[el2_ifu_ifc_ctl.scala 135:53]
-    node _T_152 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:13]
-    node _T_153 = and(wfm, _T_152) @[el2_ifu_ifc_ctl.scala 137:11]
-    node _T_154 = or(_T_151, _T_153) @[el2_ifu_ifc_ctl.scala 136:62]
-    node _T_155 = or(_T_154, idle) @[el2_ifu_ifc_ctl.scala 137:35]
-    node _T_156 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:46]
-    node _T_157 = and(_T_155, _T_156) @[el2_ifu_ifc_ctl.scala 137:44]
-    node _T_158 = or(_T_157, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 137:67]
-    io.ifc_dma_access_ok <= _T_158 @[el2_ifu_ifc_ctl.scala 135:24]
-    node _T_159 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 139:33]
-    node _T_160 = and(_T_159, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctl.scala 139:55]
-    io.ifc_region_acc_fault_bf <= _T_160 @[el2_ifu_ifc_ctl.scala 139:30]
-    node _T_161 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctl.scala 140:78]
-    node _T_162 = cat(_T_161, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_163 = dshr(io.dec_tlu_mrac_ff, _T_162) @[el2_ifu_ifc_ctl.scala 140:53]
-    node _T_164 = bits(_T_163, 0, 0) @[el2_ifu_ifc_ctl.scala 140:53]
-    node _T_165 = not(_T_164) @[el2_ifu_ifc_ctl.scala 140:34]
-    io.ifc_fetch_uncacheable_bf <= _T_165 @[el2_ifu_ifc_ctl.scala 140:31]
-    reg _T_166 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 142:32]
-    _T_166 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 142:32]
-    io.ifc_fetch_req_f <= _T_166 @[el2_ifu_ifc_ctl.scala 142:22]
-    node _T_167 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 144:88]
-    reg _T_168 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_167 : @[Reg.scala 28:19]
-      _T_168 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
+    node _T_146 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:30]
+    node _T_147 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 136:39]
+    node _T_148 = eq(_T_147, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 136:18]
+    node _T_149 = and(fb_full_f, _T_148) @[el2_ifu_ifc_ctl.scala 136:16]
+    node _T_150 = or(_T_146, _T_149) @[el2_ifu_ifc_ctl.scala 135:53]
+    node _T_151 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:13]
+    node _T_152 = and(wfm, _T_151) @[el2_ifu_ifc_ctl.scala 137:11]
+    node _T_153 = or(_T_150, _T_152) @[el2_ifu_ifc_ctl.scala 136:62]
+    node _T_154 = or(_T_153, idle) @[el2_ifu_ifc_ctl.scala 137:35]
+    node _T_155 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:46]
+    node _T_156 = and(_T_154, _T_155) @[el2_ifu_ifc_ctl.scala 137:44]
+    node _T_157 = or(_T_156, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 137:67]
+    io.ifc_dma_access_ok <= _T_157 @[el2_ifu_ifc_ctl.scala 135:24]
+    node _T_158 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 139:33]
+    node _T_159 = and(_T_158, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctl.scala 139:55]
+    io.ifc_region_acc_fault_bf <= _T_159 @[el2_ifu_ifc_ctl.scala 139:30]
+    node _T_160 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctl.scala 140:78]
+    node _T_161 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_162 = dshr(io.dec_tlu_mrac_ff, _T_161) @[el2_ifu_ifc_ctl.scala 140:53]
+    node _T_163 = bits(_T_162, 0, 0) @[el2_ifu_ifc_ctl.scala 140:53]
+    node _T_164 = not(_T_163) @[el2_ifu_ifc_ctl.scala 140:34]
+    io.ifc_fetch_uncacheable_bf <= _T_164 @[el2_ifu_ifc_ctl.scala 140:31]
+    reg _T_165 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 142:32]
+    _T_165 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 142:32]
+    io.ifc_fetch_req_f <= _T_165 @[el2_ifu_ifc_ctl.scala 142:22]
+    node _T_166 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 144:88]
+    reg _T_167 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_166 : @[Reg.scala 28:19]
+      _T_167 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    io.ifc_fetch_addr_f <= _T_168 @[el2_ifu_ifc_ctl.scala 144:23]
+    io.ifc_fetch_addr_f <= _T_167 @[el2_ifu_ifc_ctl.scala 144:23]
     
diff --git a/el2_ifu_ifc_ctl.v b/el2_ifu_ifc_ctl.v
index cf50ac2e..873deb1d 100644
--- a/el2_ifu_ifc_ctl.v
+++ b/el2_ifu_ifc_ctl.v
@@ -55,116 +55,115 @@ module el2_ifu_ifc_ctl(
   wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
   wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
   wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctl.scala 77:48]
-  wire  _T_29 = address_upper[5] ^ io_ifc_fetch_addr_f[5]; // @[el2_ifu_ifc_ctl.scala 78:63]
-  wire  _T_30 = ~_T_29; // @[el2_ifu_ifc_ctl.scala 78:24]
-  wire  fetch_addr_next_0 = _T_30 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctl.scala 78:109]
+  wire  _T_29 = address_upper[5] ^ io_ifc_fetch_addr_f[5]; // @[el2_ifu_ifc_ctl.scala 78:62]
+  wire  fetch_addr_next_0 = _T_29 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctl.scala 78:108]
   wire [30:0] fetch_addr_next = {address_upper,fetch_addr_next_0}; // @[Cat.scala 29:58]
   wire [30:0] _T_20 = sel_next_addr_bf ? fetch_addr_next : 31'h0; // @[Mux.scala 27:72]
   wire [30:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72]
   wire [30:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72]
   reg [1:0] state; // @[el2_ifu_ifc_ctl.scala 102:19]
   wire  idle = state == 2'h0; // @[el2_ifu_ifc_ctl.scala 121:17]
-  wire  _T_35 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctl.scala 84:91]
-  wire  _T_36 = ~_T_35; // @[el2_ifu_ifc_ctl.scala 84:70]
-  wire [3:0] _T_121 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
-  wire  _T_81 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 106:38]
-  wire  _T_82 = io_ifu_fb_consume1 & _T_81; // @[el2_ifu_ifc_ctl.scala 106:36]
-  wire  _T_48 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctl.scala 89:32]
-  wire  miss_f = _T_48 & _T_2; // @[el2_ifu_ifc_ctl.scala 89:47]
-  wire  _T_84 = _T_3 | miss_f; // @[el2_ifu_ifc_ctl.scala 106:81]
-  wire  _T_85 = _T_82 & _T_84; // @[el2_ifu_ifc_ctl.scala 106:58]
-  wire  _T_86 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 107:25]
-  wire  fb_right = _T_85 | _T_86; // @[el2_ifu_ifc_ctl.scala 106:92]
-  wire  _T_98 = _T_2 & fb_right; // @[el2_ifu_ifc_ctl.scala 113:16]
+  wire  _T_34 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctl.scala 84:91]
+  wire  _T_35 = ~_T_34; // @[el2_ifu_ifc_ctl.scala 84:70]
+  wire [3:0] _T_120 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
+  wire  _T_80 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 106:38]
+  wire  _T_81 = io_ifu_fb_consume1 & _T_80; // @[el2_ifu_ifc_ctl.scala 106:36]
+  wire  _T_47 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctl.scala 89:32]
+  wire  miss_f = _T_47 & _T_2; // @[el2_ifu_ifc_ctl.scala 89:47]
+  wire  _T_83 = _T_3 | miss_f; // @[el2_ifu_ifc_ctl.scala 106:81]
+  wire  _T_84 = _T_81 & _T_83; // @[el2_ifu_ifc_ctl.scala 106:58]
+  wire  _T_85 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 107:25]
+  wire  fb_right = _T_84 | _T_85; // @[el2_ifu_ifc_ctl.scala 106:92]
+  wire  _T_97 = _T_2 & fb_right; // @[el2_ifu_ifc_ctl.scala 113:16]
   reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctl.scala 126:24]
-  wire [3:0] _T_101 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
-  wire [3:0] _T_122 = _T_98 ? _T_101 : 4'h0; // @[Mux.scala 27:72]
-  wire [3:0] _T_126 = _T_121 | _T_122; // @[Mux.scala 27:72]
-  wire  fb_right2 = io_ifu_fb_consume2 & _T_84; // @[el2_ifu_ifc_ctl.scala 109:36]
-  wire  _T_103 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctl.scala 114:16]
-  wire [3:0] _T_106 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
-  wire [3:0] _T_123 = _T_103 ? _T_106 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_100 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
+  wire [3:0] _T_121 = _T_97 ? _T_100 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_125 = _T_120 | _T_121; // @[Mux.scala 27:72]
+  wire  fb_right2 = io_ifu_fb_consume2 & _T_83; // @[el2_ifu_ifc_ctl.scala 109:36]
+  wire  _T_102 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctl.scala 114:16]
+  wire [3:0] _T_105 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
+  wire [3:0] _T_122 = _T_102 ? _T_105 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_126 = _T_125 | _T_122; // @[Mux.scala 27:72]
+  wire  _T_90 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 110:56]
+  wire  _T_91 = ~_T_90; // @[el2_ifu_ifc_ctl.scala 110:35]
+  wire  _T_92 = io_ifc_fetch_req_f & _T_91; // @[el2_ifu_ifc_ctl.scala 110:33]
+  wire  _T_93 = ~miss_f; // @[el2_ifu_ifc_ctl.scala 110:80]
+  wire  fb_left = _T_92 & _T_93; // @[el2_ifu_ifc_ctl.scala 110:78]
+  wire  _T_107 = _T_2 & fb_left; // @[el2_ifu_ifc_ctl.scala 115:16]
+  wire [3:0] _T_110 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
+  wire [3:0] _T_123 = _T_107 ? _T_110 : 4'h0; // @[Mux.scala 27:72]
   wire [3:0] _T_127 = _T_126 | _T_123; // @[Mux.scala 27:72]
-  wire  _T_91 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 110:56]
-  wire  _T_92 = ~_T_91; // @[el2_ifu_ifc_ctl.scala 110:35]
-  wire  _T_93 = io_ifc_fetch_req_f & _T_92; // @[el2_ifu_ifc_ctl.scala 110:33]
-  wire  _T_94 = ~miss_f; // @[el2_ifu_ifc_ctl.scala 110:80]
-  wire  fb_left = _T_93 & _T_94; // @[el2_ifu_ifc_ctl.scala 110:78]
-  wire  _T_108 = _T_2 & fb_left; // @[el2_ifu_ifc_ctl.scala 115:16]
-  wire [3:0] _T_111 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
-  wire [3:0] _T_124 = _T_108 ? _T_111 : 4'h0; // @[Mux.scala 27:72]
-  wire [3:0] _T_128 = _T_127 | _T_124; // @[Mux.scala 27:72]
-  wire  _T_113 = ~fb_right; // @[el2_ifu_ifc_ctl.scala 116:18]
-  wire  _T_114 = _T_2 & _T_113; // @[el2_ifu_ifc_ctl.scala 116:16]
-  wire  _T_115 = ~fb_right2; // @[el2_ifu_ifc_ctl.scala 116:30]
-  wire  _T_116 = _T_114 & _T_115; // @[el2_ifu_ifc_ctl.scala 116:28]
-  wire  _T_117 = ~fb_left; // @[el2_ifu_ifc_ctl.scala 116:43]
-  wire  _T_118 = _T_116 & _T_117; // @[el2_ifu_ifc_ctl.scala 116:41]
-  wire [3:0] _T_125 = _T_118 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
-  wire [3:0] fb_write_ns = _T_128 | _T_125; // @[Mux.scala 27:72]
+  wire  _T_112 = ~fb_right; // @[el2_ifu_ifc_ctl.scala 116:18]
+  wire  _T_113 = _T_2 & _T_112; // @[el2_ifu_ifc_ctl.scala 116:16]
+  wire  _T_114 = ~fb_right2; // @[el2_ifu_ifc_ctl.scala 116:30]
+  wire  _T_115 = _T_113 & _T_114; // @[el2_ifu_ifc_ctl.scala 116:28]
+  wire  _T_116 = ~fb_left; // @[el2_ifu_ifc_ctl.scala 116:43]
+  wire  _T_117 = _T_115 & _T_116; // @[el2_ifu_ifc_ctl.scala 116:41]
+  wire [3:0] _T_124 = _T_117 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] fb_write_ns = _T_127 | _T_124; // @[Mux.scala 27:72]
   wire  fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctl.scala 124:30]
-  wire  _T_37 = fb_full_f_ns & _T_36; // @[el2_ifu_ifc_ctl.scala 84:68]
-  wire  _T_38 = ~_T_37; // @[el2_ifu_ifc_ctl.scala 84:53]
-  wire  _T_39 = io_ifc_fetch_req_bf_raw & _T_38; // @[el2_ifu_ifc_ctl.scala 84:51]
-  wire  _T_40 = ~dma_stall; // @[el2_ifu_ifc_ctl.scala 85:5]
-  wire  _T_41 = _T_39 & _T_40; // @[el2_ifu_ifc_ctl.scala 84:114]
-  wire  _T_42 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctl.scala 85:18]
-  wire  _T_43 = _T_41 & _T_42; // @[el2_ifu_ifc_ctl.scala 85:16]
-  wire  _T_44 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 85:39]
+  wire  _T_36 = fb_full_f_ns & _T_35; // @[el2_ifu_ifc_ctl.scala 84:68]
+  wire  _T_37 = ~_T_36; // @[el2_ifu_ifc_ctl.scala 84:53]
+  wire  _T_38 = io_ifc_fetch_req_bf_raw & _T_37; // @[el2_ifu_ifc_ctl.scala 84:51]
+  wire  _T_39 = ~dma_stall; // @[el2_ifu_ifc_ctl.scala 85:5]
+  wire  _T_40 = _T_38 & _T_39; // @[el2_ifu_ifc_ctl.scala 84:114]
+  wire  _T_41 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctl.scala 85:18]
+  wire  _T_42 = _T_40 & _T_41; // @[el2_ifu_ifc_ctl.scala 85:16]
+  wire  _T_43 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 85:39]
   wire  fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 87:37]
-  wire  _T_51 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 91:39]
-  wire  _T_53 = _T_51 & _T_40; // @[el2_ifu_ifc_ctl.scala 91:61]
-  wire  _T_55 = _T_53 & _T_94; // @[el2_ifu_ifc_ctl.scala 91:74]
-  wire  _T_56 = ~miss_a; // @[el2_ifu_ifc_ctl.scala 91:86]
-  wire  mb_empty_mod = _T_55 & _T_56; // @[el2_ifu_ifc_ctl.scala 91:84]
+  wire  _T_50 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 91:39]
+  wire  _T_52 = _T_50 & _T_39; // @[el2_ifu_ifc_ctl.scala 91:61]
+  wire  _T_54 = _T_52 & _T_93; // @[el2_ifu_ifc_ctl.scala 91:74]
+  wire  _T_55 = ~miss_a; // @[el2_ifu_ifc_ctl.scala 91:86]
+  wire  mb_empty_mod = _T_54 & _T_55; // @[el2_ifu_ifc_ctl.scala 91:84]
   wire  goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 93:35]
-  wire  _T_60 = io_exu_flush_final & _T_44; // @[el2_ifu_ifc_ctl.scala 95:36]
-  wire  leave_idle = _T_60 & idle; // @[el2_ifu_ifc_ctl.scala 95:67]
-  wire  _T_63 = ~state[1]; // @[el2_ifu_ifc_ctl.scala 97:23]
-  wire  _T_65 = _T_63 & state[0]; // @[el2_ifu_ifc_ctl.scala 97:33]
-  wire  _T_66 = _T_65 & miss_f; // @[el2_ifu_ifc_ctl.scala 97:44]
-  wire  _T_67 = ~goto_idle; // @[el2_ifu_ifc_ctl.scala 97:55]
-  wire  _T_68 = _T_66 & _T_67; // @[el2_ifu_ifc_ctl.scala 97:53]
-  wire  _T_70 = ~mb_empty_mod; // @[el2_ifu_ifc_ctl.scala 98:17]
-  wire  _T_71 = state[1] & _T_70; // @[el2_ifu_ifc_ctl.scala 98:15]
-  wire  _T_73 = _T_71 & _T_67; // @[el2_ifu_ifc_ctl.scala 98:31]
-  wire  next_state_1 = _T_68 | _T_73; // @[el2_ifu_ifc_ctl.scala 97:67]
-  wire  _T_75 = _T_67 & leave_idle; // @[el2_ifu_ifc_ctl.scala 100:34]
-  wire  _T_78 = state[0] & _T_67; // @[el2_ifu_ifc_ctl.scala 100:60]
-  wire  next_state_0 = _T_75 | _T_78; // @[el2_ifu_ifc_ctl.scala 100:48]
+  wire  _T_59 = io_exu_flush_final & _T_43; // @[el2_ifu_ifc_ctl.scala 95:36]
+  wire  leave_idle = _T_59 & idle; // @[el2_ifu_ifc_ctl.scala 95:67]
+  wire  _T_62 = ~state[1]; // @[el2_ifu_ifc_ctl.scala 97:23]
+  wire  _T_64 = _T_62 & state[0]; // @[el2_ifu_ifc_ctl.scala 97:33]
+  wire  _T_65 = _T_64 & miss_f; // @[el2_ifu_ifc_ctl.scala 97:44]
+  wire  _T_66 = ~goto_idle; // @[el2_ifu_ifc_ctl.scala 97:55]
+  wire  _T_67 = _T_65 & _T_66; // @[el2_ifu_ifc_ctl.scala 97:53]
+  wire  _T_69 = ~mb_empty_mod; // @[el2_ifu_ifc_ctl.scala 98:17]
+  wire  _T_70 = state[1] & _T_69; // @[el2_ifu_ifc_ctl.scala 98:15]
+  wire  _T_72 = _T_70 & _T_66; // @[el2_ifu_ifc_ctl.scala 98:31]
+  wire  next_state_1 = _T_67 | _T_72; // @[el2_ifu_ifc_ctl.scala 97:67]
+  wire  _T_74 = _T_66 & leave_idle; // @[el2_ifu_ifc_ctl.scala 100:34]
+  wire  _T_77 = state[0] & _T_66; // @[el2_ifu_ifc_ctl.scala 100:60]
+  wire  next_state_0 = _T_74 | _T_77; // @[el2_ifu_ifc_ctl.scala 100:48]
   wire  wfm = state == 2'h3; // @[el2_ifu_ifc_ctl.scala 122:16]
   reg  fb_full_f; // @[el2_ifu_ifc_ctl.scala 125:26]
-  wire  _T_138 = _T_35 | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 129:61]
-  wire  _T_139 = ~_T_138; // @[el2_ifu_ifc_ctl.scala 129:19]
-  wire  _T_140 = fb_full_f & _T_139; // @[el2_ifu_ifc_ctl.scala 129:17]
-  wire  _T_141 = _T_140 | dma_stall; // @[el2_ifu_ifc_ctl.scala 129:84]
-  wire  _T_142 = io_ifc_fetch_req_bf_raw & _T_141; // @[el2_ifu_ifc_ctl.scala 128:60]
-  wire [31:0] _T_144 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
-  wire  iccm_acc_in_region_bf = _T_144[31:28] == 4'he; // @[el2_lib.scala 211:47]
-  wire  iccm_acc_in_range_bf = _T_144[31:16] == 16'hee00; // @[el2_lib.scala 214:29]
-  wire  _T_147 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 135:30]
-  wire  _T_150 = fb_full_f & _T_36; // @[el2_ifu_ifc_ctl.scala 136:16]
-  wire  _T_151 = _T_147 | _T_150; // @[el2_ifu_ifc_ctl.scala 135:53]
-  wire  _T_152 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctl.scala 137:13]
-  wire  _T_153 = wfm & _T_152; // @[el2_ifu_ifc_ctl.scala 137:11]
-  wire  _T_154 = _T_151 | _T_153; // @[el2_ifu_ifc_ctl.scala 136:62]
-  wire  _T_155 = _T_154 | idle; // @[el2_ifu_ifc_ctl.scala 137:35]
-  wire  _T_157 = _T_155 & _T_2; // @[el2_ifu_ifc_ctl.scala 137:44]
-  wire  _T_159 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctl.scala 139:33]
-  wire [4:0] _T_162 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
-  wire [31:0] _T_163 = io_dec_tlu_mrac_ff >> _T_162; // @[el2_ifu_ifc_ctl.scala 140:53]
-  reg  _T_166; // @[el2_ifu_ifc_ctl.scala 142:32]
-  reg [30:0] _T_168; // @[Reg.scala 27:20]
-  assign io_ifc_fetch_addr_f = _T_168; // @[el2_ifu_ifc_ctl.scala 144:23]
+  wire  _T_137 = _T_34 | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 129:61]
+  wire  _T_138 = ~_T_137; // @[el2_ifu_ifc_ctl.scala 129:19]
+  wire  _T_139 = fb_full_f & _T_138; // @[el2_ifu_ifc_ctl.scala 129:17]
+  wire  _T_140 = _T_139 | dma_stall; // @[el2_ifu_ifc_ctl.scala 129:84]
+  wire  _T_141 = io_ifc_fetch_req_bf_raw & _T_140; // @[el2_ifu_ifc_ctl.scala 128:60]
+  wire [31:0] _T_143 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
+  wire  iccm_acc_in_region_bf = _T_143[31:28] == 4'he; // @[el2_lib.scala 211:47]
+  wire  iccm_acc_in_range_bf = _T_143[31:16] == 16'hee00; // @[el2_lib.scala 214:29]
+  wire  _T_146 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 135:30]
+  wire  _T_149 = fb_full_f & _T_35; // @[el2_ifu_ifc_ctl.scala 136:16]
+  wire  _T_150 = _T_146 | _T_149; // @[el2_ifu_ifc_ctl.scala 135:53]
+  wire  _T_151 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctl.scala 137:13]
+  wire  _T_152 = wfm & _T_151; // @[el2_ifu_ifc_ctl.scala 137:11]
+  wire  _T_153 = _T_150 | _T_152; // @[el2_ifu_ifc_ctl.scala 136:62]
+  wire  _T_154 = _T_153 | idle; // @[el2_ifu_ifc_ctl.scala 137:35]
+  wire  _T_156 = _T_154 & _T_2; // @[el2_ifu_ifc_ctl.scala 137:44]
+  wire  _T_158 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctl.scala 139:33]
+  wire [4:0] _T_161 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
+  wire [31:0] _T_162 = io_dec_tlu_mrac_ff >> _T_161; // @[el2_ifu_ifc_ctl.scala 140:53]
+  reg  _T_165; // @[el2_ifu_ifc_ctl.scala 142:32]
+  reg [30:0] _T_167; // @[Reg.scala 27:20]
+  assign io_ifc_fetch_addr_f = _T_167; // @[el2_ifu_ifc_ctl.scala 144:23]
   assign io_ifc_fetch_addr_bf = _T_22 | _T_20; // @[el2_ifu_ifc_ctl.scala 72:24]
-  assign io_ifc_fetch_req_f = _T_166; // @[el2_ifu_ifc_ctl.scala 142:22]
-  assign io_ifu_pmu_fetch_stall = wfm | _T_142; // @[el2_ifu_ifc_ctl.scala 128:26]
-  assign io_ifc_fetch_uncacheable_bf = ~_T_163[0]; // @[el2_ifu_ifc_ctl.scala 140:31]
-  assign io_ifc_fetch_req_bf = _T_43 & _T_44; // @[el2_ifu_ifc_ctl.scala 84:23]
+  assign io_ifc_fetch_req_f = _T_165; // @[el2_ifu_ifc_ctl.scala 142:22]
+  assign io_ifu_pmu_fetch_stall = wfm | _T_141; // @[el2_ifu_ifc_ctl.scala 128:26]
+  assign io_ifc_fetch_uncacheable_bf = ~_T_162[0]; // @[el2_ifu_ifc_ctl.scala 140:31]
+  assign io_ifc_fetch_req_bf = _T_42 & _T_43; // @[el2_ifu_ifc_ctl.scala 84:23]
   assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctl.scala 82:27]
-  assign io_ifc_iccm_access_bf = _T_144[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 134:25]
-  assign io_ifc_region_acc_fault_bf = _T_159 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 139:30]
-  assign io_ifc_dma_access_ok = _T_157 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 135:24]
+  assign io_ifc_iccm_access_bf = _T_143[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 134:25]
+  assign io_ifc_region_acc_fault_bf = _T_158 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 139:30]
+  assign io_ifc_dma_access_ok = _T_156 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 135:24]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
 `endif
@@ -211,9 +210,9 @@ initial begin
   _RAND_4 = {1{`RANDOM}};
   fb_full_f = _RAND_4[0:0];
   _RAND_5 = {1{`RANDOM}};
-  _T_166 = _RAND_5[0:0];
+  _T_165 = _RAND_5[0:0];
   _RAND_6 = {1{`RANDOM}};
-  _T_168 = _RAND_6[30:0];
+  _T_167 = _RAND_6[30:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
     dma_iccm_stall_any_f = 1'h0;
@@ -231,10 +230,10 @@ initial begin
     fb_full_f = 1'h0;
   end
   if (reset) begin
-    _T_166 = 1'h0;
+    _T_165 = 1'h0;
   end
   if (reset) begin
-    _T_168 = 31'h0;
+    _T_167 = 31'h0;
   end
   `endif // RANDOMIZE
 end // initial
@@ -253,7 +252,7 @@ end // initial
     if (reset) begin
       miss_a <= 1'h0;
     end else begin
-      miss_a <= _T_48 & _T_2;
+      miss_a <= _T_47 & _T_2;
     end
   end
   always @(posedge clock or posedge reset) begin
@@ -267,7 +266,7 @@ end // initial
     if (reset) begin
       fb_write_f <= 4'h0;
     end else begin
-      fb_write_f <= _T_128 | _T_125;
+      fb_write_f <= _T_127 | _T_124;
     end
   end
   always @(posedge clock or posedge reset) begin
@@ -279,16 +278,16 @@ end // initial
   end
   always @(posedge clock or posedge reset) begin
     if (reset) begin
-      _T_166 <= 1'h0;
+      _T_165 <= 1'h0;
     end else begin
-      _T_166 <= io_ifc_fetch_req_bf;
+      _T_165 <= io_ifc_fetch_req_bf;
     end
   end
   always @(posedge clock or posedge reset) begin
     if (reset) begin
-      _T_168 <= 31'h0;
+      _T_167 <= 31'h0;
     end else if (fetch_bf_en) begin
-      _T_168 <= io_ifc_fetch_addr_bf;
+      _T_167 <= io_ifc_fetch_addr_bf;
     end
   end
 endmodule
diff --git a/src/main/scala/ifu/el2_ifu_ifc_ctl.scala b/src/main/scala/ifu/el2_ifu_ifc_ctl.scala
index fd2a7bcb..2fb291f2 100644
--- a/src/main/scala/ifu/el2_ifu_ifc_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_ifc_ctl.scala
@@ -5,34 +5,34 @@ import chisel3.util._
 
 class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
   val io = IO(new Bundle{
-    val free_clk                  = Input(Clock())
-    val active_clk                = Input(Bool())
-    val scan_mode                 = Input(Bool())
-    val ic_hit_f                  = Input(Bool())
-    val ifu_ic_mb_empty           = Input(Bool())
-    val ifu_fb_consume1           = Input(Bool())
-    val ifu_fb_consume2           = Input(Bool())
-    val dec_tlu_flush_noredir_wb  = Input(Bool())
-    val exu_flush_final           = Input(Bool())
-    val exu_flush_path_final      = Input(UInt(31.W))
-    val ifu_bp_hit_taken_f        = Input(Bool())
-    val ifu_bp_btb_target_f       = Input(UInt(31.W))
-    val ic_dma_active             = Input(Bool())
-    val ic_write_stall            = Input(Bool())
-    val dma_iccm_stall_any        = Input(Bool())
-    val dec_tlu_mrac_ff           = Input(UInt(32.W))
+    val free_clk = Input(Clock())
+    val active_clk = Input(Bool())
+    val scan_mode = Input(Bool())
+    val ic_hit_f = Input(Bool())
+    val ifu_ic_mb_empty = Input(Bool())
+    val ifu_fb_consume1 = Input(Bool())
+    val ifu_fb_consume2 = Input(Bool())
+    val dec_tlu_flush_noredir_wb = Input(Bool())
+    val exu_flush_final = Input(Bool())
+    val exu_flush_path_final = Input(UInt(31.W))
+    val ifu_bp_hit_taken_f = Input(Bool())
+    val ifu_bp_btb_target_f = Input(UInt(31.W))
+    val ic_dma_active = Input(Bool())
+    val ic_write_stall = Input(Bool())
+    val dma_iccm_stall_any = Input(Bool())
+    val dec_tlu_mrac_ff = Input(UInt(32.W))
 
-    val ifc_fetch_addr_f          = Output(UInt(31.W))
-    val ifc_fetch_addr_bf         = Output(UInt(31.W))
+    val ifc_fetch_addr_f = Output(UInt(31.W))
+    val ifc_fetch_addr_bf = Output(UInt(31.W))
 
-    val ifc_fetch_req_f           = Output(Bool())
-    val ifu_pmu_fetch_stall       = Output(Bool())
-    val ifc_fetch_uncacheable_bf  = Output(Bool())
-    val ifc_fetch_req_bf          = Output(Bool())
-    val ifc_fetch_req_bf_raw      = Output(Bool())
-    val ifc_iccm_access_bf        = Output(Bool())
-    val ifc_region_acc_fault_bf   = Output(Bool())
-    val ifc_dma_access_ok         = Output(Bool())
+    val ifc_fetch_req_f = Output(Bool())
+    val ifu_pmu_fetch_stall = Output(Bool())
+    val ifc_fetch_uncacheable_bf = Output(Bool())
+    val ifc_fetch_req_bf = Output(Bool())
+    val ifc_fetch_req_bf_raw = Output(Bool())
+    val ifc_iccm_access_bf = Output(Bool())
+    val ifc_region_acc_fault_bf = Output(Bool())
+    val ifc_dma_access_ok = Output(Bool())
   })
 
   val fetch_addr_bf = WireInit(UInt(31.W), init = 0.U)
@@ -75,7 +75,7 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
     sel_next_addr_bf.asBool -> fetch_addr_next))            // PC+4
 
   val address_upper = io.ifc_fetch_addr_f(30,1)+1.U
-  fetch_addr_next_0 := !(address_upper(ICACHE_TAG_INDEX_LO-1) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO-1)) & io.ifc_fetch_addr_f(0)
+  fetch_addr_next_0 := (address_upper(ICACHE_TAG_INDEX_LO-1) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO-1)) & io.ifc_fetch_addr_f(0)
 
   fetch_addr_next := Cat(address_upper, fetch_addr_next_0)
 
@@ -147,3 +147,4 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
 object ifu_ifc extends App {
   println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ifc_ctl()))
 }
+
diff --git a/target/scala-2.12/classes/ifu/el2_ifu_ifc_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_ifc_ctl.class
index 99549546da0207d067568f2602f57ee9cdb2cbb6..044a8e5f1f3791e0acf926dd1995459779bfd144 100644
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