diff --git a/dec.anno.json b/dec.anno.json new file mode 100644 index 00000000..859bcab3 --- /dev/null +++ b/dec.anno.json @@ -0,0 +1,2522 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_tlu_core_empty", + "sources":[ + "~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle", + "~dec|dec>io_lsu_idle_any", + "~dec|dec>io_mpc_reset_run_req", + "~dec|dec>io_dbg_halt_req" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_i0_predict_p_d_valid", + "sources":[ + "~dec|dec>io_lsu_load_stall_any", + "~dec|dec>io_dec_dma_dctl_dma_dma_dccm_stall_any", + "~dec|dec>io_lsu_store_stall_any", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m", + "~dec|dec>io_dec_dbg_dbg_dctl_dbg_cmd_wrdata", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_mpc_reset_run_req", + "~dec|dec>io_lsu_fastint_stall_any", + "~dec|dec>io_lsu_fir_error", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dbg_halt_req", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_dec_pic_mhwakeup", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle", + "~dec|dec>io_lsu_idle_any", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist", + "~dec|dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_sll", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_beq", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_sbset", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error", + "sources":[ + "~dec|dec>io_lsu_load_stall_any", + "~dec|dec>io_dec_dma_dctl_dma_dma_dccm_stall_any", + "~dec|dec>io_lsu_store_stall_any", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m", + "~dec|dec>io_dec_dbg_dbg_dctl_dbg_cmd_wrdata", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_mpc_reset_run_req", + "~dec|dec>io_lsu_fastint_stall_any", + "~dec|dec>io_lsu_fir_error", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dbg_halt_req", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_dec_pic_mhwakeup", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle", + "~dec|dec>io_lsu_idle_any", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist", + "~dec|dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_jal", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_land", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_slt", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_predict_index_d", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_clz", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way", + "sources":[ + "~dec|dec>io_exu_i0_br_way_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_sub", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_sh3add", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_pred_correct_npc_x", + "sources":[ + "~dec|dec>io_dec_exu_dec_alu_exu_i0_pc_x" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_crc32_b", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_lsu_p_bits_by", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_dbg_cmd_fail", + "sources":[ + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_dbg_halt_req" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_predict_nt", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_lsu_p_bits_load", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d", + "sources":[ + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_dbg_halt_req", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_sbinv", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_sh1add", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_lsu_p_bits_half", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_csr_imm", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_max", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d", + "sources":[ + "~dec|dec>io_lsu_load_stall_any", + "~dec|dec>io_dec_dma_dctl_dma_dma_dccm_stall_any", + "~dec|dec>io_lsu_store_stall_any", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m", + "~dec|dec>io_dec_dbg_dbg_dctl_dbg_cmd_wrdata", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_mpc_reset_run_req", + "~dec|dec>io_lsu_fastint_stall_any", + "~dec|dec>io_lsu_fir_error", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dbg_halt_req", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_dec_pic_mhwakeup", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle", + "~dec|dec>io_lsu_idle_any", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist", + "~dec|dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_sbext", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_bdep", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_crc32c_b", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_i0_select_pc_d", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_predict_t", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_low", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_gpr_exu_gpr_i0_rs2_d", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_sext_h", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_dbg_rddata", + "sources":[ + "~dec|dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_packh", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_bge", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_packu", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_lor", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist", + "sources":[ + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_hist_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_lsu_p_bits_unsign", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_bext", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_lsu_p_bits_load_ldst_bypass_d", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_crc32_w", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_dec_div_div_p_valid", + "sources":[ + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m", + "~dec|dec>io_dec_dbg_dbg_dctl_dbg_cmd_wrdata", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_mpc_reset_run_req", + "~dec|dec>io_lsu_fastint_stall_any", + "~dec|dec>io_lsu_fir_error", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dbg_halt_req", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_dec_pic_mhwakeup", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle", + "~dec|dec>io_lsu_idle_any", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist", + "~dec|dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_gorc", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_pack", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_dec_alu_dec_csr_ren_d", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_lsu_p_bits_store", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_tlu_exu_dec_tlu_flush_lower_r", + "sources":[ + "~dec|dec>io_mpc_reset_run_req", + "~dec|dec>io_lsu_fastint_stall_any", + "~dec|dec>io_lsu_fir_error", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dbg_halt_req", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_dec_pic_mhwakeup", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle", + "~dec|dec>io_lsu_idle_any", + "~dec|dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_dec_div_div_p_bits_unsign", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_valid", + "sources":[ + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m", + "~dec|dec>io_dec_dbg_dbg_dctl_dbg_cmd_wrdata", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_mpc_reset_run_req", + "~dec|dec>io_lsu_fastint_stall_any", + "~dec|dec>io_lsu_fir_error", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dbg_halt_req", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_dec_pic_mhwakeup", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle", + "~dec|dec>io_lsu_idle_any", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist", + "~dec|dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_sext_b", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_crc32_h", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_i0_rs1_en_d", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_data_en", + "sources":[ + "~dec|dec>io_lsu_load_stall_any", + "~dec|dec>io_dec_dma_dctl_dma_dma_dccm_stall_any", + "~dec|dec>io_lsu_store_stall_any", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m", + "~dec|dec>io_dec_dbg_dbg_dctl_dbg_cmd_wrdata", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_mpc_reset_run_req", + "~dec|dec>io_lsu_fastint_stall_any", + "~dec|dec>io_lsu_fir_error", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dbg_halt_req", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_dec_pic_mhwakeup", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle", + "~dec|dec>io_lsu_idle_any", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist", + "~dec|dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_dec_div_div_p_bits_rem", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_clmulr", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_rol", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_zba", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_dec_alu_dec_i0_alu_decode_d", + "sources":[ + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m", + "~dec|dec>io_dec_dbg_dbg_dctl_dbg_cmd_wrdata", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_mpc_reset_run_req", + "~dec|dec>io_lsu_fastint_stall_any", + "~dec|dec>io_lsu_fir_error", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dbg_halt_req", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_dec_pic_mhwakeup", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle", + "~dec|dec>io_lsu_idle_any", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist", + "~dec|dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb", + "sources":[ + "~dec|dec>io_lsu_fastint_stall_any", + "~dec|dec>io_lsu_fir_error", + "~dec|dec>io_mpc_reset_run_req", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dbg_halt_req", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_dec_pic_mhwakeup", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle", + "~dec|dec>io_lsu_idle_any", + "~dec|dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_sra", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_i0_branch_d", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_add", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid", + "sources":[ + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_valid_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_mp_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_dec_alu_dec_i0_br_immed_d", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_csr_write", + "sources":[ + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_sh2add", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb", + "sources":[ + "~dec|dec>io_mpc_reset_run_req", + "~dec|dec>io_lsu_fastint_stall_any", + "~dec|dec>io_lsu_fir_error", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dbg_halt_req", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_dec_pic_mhwakeup", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle", + "~dec|dec>io_lsu_idle_any", + "~dec|dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_shfl", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_lsu_offset_d", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_crc32c_w", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error", + "sources":[ + "~dec|dec>io_lsu_load_stall_any", + "~dec|dec>io_dec_dma_dctl_dma_dma_dccm_stall_any", + "~dec|dec>io_lsu_store_stall_any", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m", + "~dec|dec>io_dec_dbg_dbg_dctl_dbg_cmd_wrdata", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_mpc_reset_run_req", + "~dec|dec>io_lsu_fastint_stall_any", + "~dec|dec>io_lsu_fir_error", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dbg_halt_req", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_dec_pic_mhwakeup", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle", + "~dec|dec>io_lsu_idle_any", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_zbb", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_ror", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_predict_btag_d", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_lsu_valid_raw_d", + "sources":[ + "~dec|dec>io_dec_dma_dctl_dma_dma_dccm_stall_any", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m", + "~dec|dec>io_dec_dbg_dbg_dctl_dbg_cmd_wrdata", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error", + "sources":[ + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_lsu_p_valid", + "sources":[ + "~dec|dec>io_lsu_load_stall_any", + "~dec|dec>io_dec_dma_dctl_dma_dma_dccm_stall_any", + "~dec|dec>io_lsu_store_stall_any", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m", + "~dec|dec>io_dec_dbg_dbg_dctl_dbg_cmd_wrdata", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid", + "~dec|dec>io_mpc_reset_run_req", + "~dec|dec>io_lsu_fastint_stall_any", + "~dec|dec>io_lsu_fir_error", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dbg_halt_req", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_dec_pic_mhwakeup", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle", + "~dec|dec>io_lsu_idle_any", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist", + "~dec|dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_lxor", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_bne", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_ctz", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_bfp", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_unsign", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_tlu_exu_dec_tlu_flush_path_r", + "sources":[ + "~dec|dec>io_rst_vec", + "~dec|dec>io_mpc_reset_run_req", + "~dec|dec>io_nmi_vec", + "~dec|dec>io_lsu_fir_addr", + "~dec|dec>io_lsu_fir_error", + "~dec|dec>io_lsu_fastint_stall_any", + "~dec|dec>io_lsu_error_pkt_r_bits_exc_type", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dbg_halt_req", + "~dec|dec>io_dec_exu_tlu_exu_exu_npc_r", + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_dec_pic_mhwakeup", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle", + "~dec|dec>io_lsu_idle_any", + "~dec|dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error", + "sources":[ + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_qual_lsu_d", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle", + "sources":[ + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_middle_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_sro", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_rs1_sign", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_dec_div_dec_div_cancel", + "sources":[ + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_dbg_halt_req", + "~dec|dec>io_mpc_reset_run_req", + "~dec|dec>io_lsu_fastint_stall_any", + "~dec|dec>io_lsu_fir_error", + "~dec|dec>io_dec_pic_mhwakeup", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle", + "~dec|dec>io_lsu_idle_any", + "~dec|dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d", + "sources":[ + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_dbg_halt_req", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb", + "sources":[ + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_dbg_halt_req" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_ib_exu_dec_i0_pc_d", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_gpr_exu_gpr_i0_rs1_d", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_crc32c_h", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_pcnt", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_ctl_en", + "sources":[ + "~dec|dec>io_lsu_load_stall_any", + "~dec|dec>io_dec_dma_dctl_dma_dma_dccm_stall_any", + "~dec|dec>io_lsu_store_stall_any", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m", + "~dec|dec>io_dec_dbg_dbg_dctl_dbg_cmd_wrdata", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error", + "~dec|dec>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_mpc_reset_run_req", + "~dec|dec>io_lsu_fastint_stall_any", + "~dec|dec>io_lsu_fir_error", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dbg_halt_req", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_dec_pic_mhwakeup", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle", + "~dec|dec>io_lsu_idle_any", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist", + "~dec|dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_lsu_p_bits_store_data_bypass_d", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_gorc", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_blt", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_min", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_grev", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_lsu_p_bits_word", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_lsu_p_bits_stack", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_grev", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_rs2_sign", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_ib_exu_dec_debug_wdata_rs1_d", + "sources":[ + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_sbclr", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_i0_rs2_en_d", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_unshfl", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb", + "sources":[ + "~dec|dec>io_mpc_reset_run_req", + "~dec|dec>io_lsu_fastint_stall_any", + "~dec|dec>io_lsu_fir_error", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dbg_halt_req", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_dec_pic_mhwakeup", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec|dec>io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec|dec>io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle", + "~dec|dec>io_lsu_idle_any", + "~dec|dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_csr_rddata_d", + "sources":[ + "~dec|dec>io_core_id", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_clmulh", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_slo", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_tlu_i0_kill_writeb_r", + "sources":[ + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_dbg_halt_req" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_predict_fghr_d", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_mul_p_bits_clmul", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt", + "sources":[ + "~dec|dec>io_lsu_error_pkt_r_valid", + "~dec|dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_error_r", + "~dec|dec>io_dec_exu_tlu_exu_exu_i0_br_start_error_r", + "~dec|dec>io_lsu_error_pkt_r_bits_inst_type", + "~dec|dec>io_dbg_halt_req" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_dec_i0_immed_d", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec|dec>io_dec_exu_decode_exu_i0_ap_srl", + "sources":[ + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_valid", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_type", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_addr", + "~dec|dec>io_dec_dbg_dbg_ib_dbg_cmd_write", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_valid", + "~dec|dec>io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~dec|dec_trigger>io_dec_i0_trigger_match_d" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"dec.gated_latch", + "resourceId":"/vsrc/gated_latch.sv" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"dec" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/dec.fir b/dec.fir new file mode 100644 index 00000000..81fec2ea --- /dev/null +++ b/dec.fir @@ -0,0 +1,21733 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit dec : + module dec_ib_ctl : + input clock : Clock + input reset : Reset + output io : {flip ifu_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_second : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, flip ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dec_debug_valid_d : UInt<1>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, flip ifu_i0_fa_index : UInt<9>, dec_i0_bp_fa_index : UInt<9>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_second_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_fence_d : UInt<1>} + + io.dec_i0_icaf_second_d <= io.ifu_ib.ifu_i0_icaf_second @[dec_ib_ctl.scala 34:35] + io.dec_i0_dbecc_d <= io.ifu_ib.ifu_i0_dbecc @[dec_ib_ctl.scala 35:31] + io.dec_i0_icaf_d <= io.ifu_ib.ifu_i0_icaf @[dec_ib_ctl.scala 36:31] + io.ib_exu.dec_i0_pc_d <= io.ifu_ib.ifu_i0_pc @[dec_ib_ctl.scala 37:31] + io.dec_i0_pc4_d <= io.ifu_ib.ifu_i0_pc4 @[dec_ib_ctl.scala 38:31] + io.dec_i0_icaf_type_d <= io.ifu_ib.ifu_i0_icaf_type @[dec_ib_ctl.scala 39:31] + io.dec_i0_brp.bits.ret <= io.ifu_ib.i0_brp.bits.ret @[dec_ib_ctl.scala 40:31] + io.dec_i0_brp.bits.way <= io.ifu_ib.i0_brp.bits.way @[dec_ib_ctl.scala 40:31] + io.dec_i0_brp.bits.prett <= io.ifu_ib.i0_brp.bits.prett @[dec_ib_ctl.scala 40:31] + io.dec_i0_brp.bits.bank <= io.ifu_ib.i0_brp.bits.bank @[dec_ib_ctl.scala 40:31] + io.dec_i0_brp.bits.br_start_error <= io.ifu_ib.i0_brp.bits.br_start_error @[dec_ib_ctl.scala 40:31] + io.dec_i0_brp.bits.br_error <= io.ifu_ib.i0_brp.bits.br_error @[dec_ib_ctl.scala 40:31] + io.dec_i0_brp.bits.hist <= io.ifu_ib.i0_brp.bits.hist @[dec_ib_ctl.scala 40:31] + io.dec_i0_brp.bits.toffset <= io.ifu_ib.i0_brp.bits.toffset @[dec_ib_ctl.scala 40:31] + io.dec_i0_brp.valid <= io.ifu_ib.i0_brp.valid @[dec_ib_ctl.scala 40:31] + io.dec_i0_bp_index <= io.ifu_ib.ifu_i0_bp_index @[dec_ib_ctl.scala 41:31] + io.dec_i0_bp_fghr <= io.ifu_ib.ifu_i0_bp_fghr @[dec_ib_ctl.scala 42:31] + io.dec_i0_bp_btag <= io.ifu_ib.ifu_i0_bp_btag @[dec_ib_ctl.scala 43:31] + io.dec_i0_bp_fa_index <= io.ifu_i0_fa_index @[dec_ib_ctl.scala 44:25] + node _T = neq(io.dbg_ib.dbg_cmd_type, UInt<2>("h02")) @[dec_ib_ctl.scala 58:74] + node debug_valid = and(io.dbg_ib.dbg_cmd_valid, _T) @[dec_ib_ctl.scala 58:48] + node _T_1 = eq(io.dbg_ib.dbg_cmd_write, UInt<1>("h00")) @[dec_ib_ctl.scala 59:38] + node debug_read = and(debug_valid, _T_1) @[dec_ib_ctl.scala 59:36] + node debug_write = and(debug_valid, io.dbg_ib.dbg_cmd_write) @[dec_ib_ctl.scala 60:36] + io.dec_debug_valid_d <= debug_valid @[dec_ib_ctl.scala 61:24] + node _T_2 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h00")) @[dec_ib_ctl.scala 62:62] + node debug_read_gpr = and(debug_read, _T_2) @[dec_ib_ctl.scala 62:37] + node _T_3 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h00")) @[dec_ib_ctl.scala 63:62] + node debug_write_gpr = and(debug_write, _T_3) @[dec_ib_ctl.scala 63:37] + node _T_4 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h01")) @[dec_ib_ctl.scala 64:62] + node debug_read_csr = and(debug_read, _T_4) @[dec_ib_ctl.scala 64:37] + node _T_5 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h01")) @[dec_ib_ctl.scala 65:62] + node debug_write_csr = and(debug_write, _T_5) @[dec_ib_ctl.scala 65:37] + node dreg = bits(io.dbg_ib.dbg_cmd_addr, 4, 0) @[dec_ib_ctl.scala 67:47] + node dcsr = bits(io.dbg_ib.dbg_cmd_addr, 11, 0) @[dec_ib_ctl.scala 68:47] + node _T_6 = bits(debug_read_gpr, 0, 0) @[dec_ib_ctl.scala 71:20] + node _T_7 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] + node _T_8 = cat(_T_7, dreg) @[Cat.scala 29:58] + node _T_9 = cat(_T_8, UInt<15>("h06033")) @[Cat.scala 29:58] + node _T_10 = bits(debug_write_gpr, 0, 0) @[dec_ib_ctl.scala 72:21] + node _T_11 = cat(UInt<20>("h06"), dreg) @[Cat.scala 29:58] + node _T_12 = cat(_T_11, UInt<7>("h033")) @[Cat.scala 29:58] + node _T_13 = bits(debug_read_csr, 0, 0) @[dec_ib_ctl.scala 73:20] + node _T_14 = cat(dcsr, UInt<20>("h02073")) @[Cat.scala 29:58] + node _T_15 = bits(debug_write_csr, 0, 0) @[dec_ib_ctl.scala 74:21] + node _T_16 = cat(dcsr, UInt<20>("h01073")) @[Cat.scala 29:58] + node _T_17 = mux(_T_6, _T_9, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_18 = mux(_T_10, _T_12, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_19 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_20 = mux(_T_15, _T_16, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72] + node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72] + node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72] + wire ib0_debug_in : UInt<32> @[Mux.scala 27:72] + ib0_debug_in <= _T_23 @[Mux.scala 27:72] + node _T_24 = or(debug_write_gpr, debug_write_csr) @[dec_ib_ctl.scala 78:54] + io.ib_exu.dec_debug_wdata_rs1_d <= _T_24 @[dec_ib_ctl.scala 78:35] + node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[dec_ib_ctl.scala 81:51] + node _T_26 = and(debug_write_csr, _T_25) @[dec_ib_ctl.scala 81:43] + io.dec_debug_fence_d <= _T_26 @[dec_ib_ctl.scala 81:24] + node _T_27 = or(io.ifu_ib.ifu_i0_valid, debug_valid) @[dec_ib_ctl.scala 83:48] + io.dec_ib0_valid_d <= _T_27 @[dec_ib_ctl.scala 83:22] + node _T_28 = bits(debug_valid, 0, 0) @[dec_ib_ctl.scala 84:41] + node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_ib.ifu_i0_instr) @[dec_ib_ctl.scala 84:28] + io.dec_i0_instr_d <= _T_29 @[dec_ib_ctl.scala 84:22] + + module dec_dec_ctl : + input clock : Clock + input reset : Reset + output io : {flip ins : UInt<32>, out : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, zbs : UInt<1>, bext : UInt<1>, bdep : UInt<1>, zbe : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, zbc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, zbp : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, zbr : UInt<1>, bfp : UInt<1>, zbf : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>}} + + node _T = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_3 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_4 = eq(_T_3, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_5 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_6 = eq(_T_5, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_7 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_8 = eq(_T_7, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_9 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_10 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_11 = eq(_T_10, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_12 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_13 = and(_T, _T_1) @[dec_dec_ctl.scala 17:17] + node _T_14 = and(_T_13, _T_2) @[dec_dec_ctl.scala 17:17] + node _T_15 = and(_T_14, _T_4) @[dec_dec_ctl.scala 17:17] + node _T_16 = and(_T_15, _T_6) @[dec_dec_ctl.scala 17:17] + node _T_17 = and(_T_16, _T_8) @[dec_dec_ctl.scala 17:17] + node _T_18 = and(_T_17, _T_9) @[dec_dec_ctl.scala 17:17] + node _T_19 = and(_T_18, _T_11) @[dec_dec_ctl.scala 17:17] + node _T_20 = and(_T_19, _T_12) @[dec_dec_ctl.scala 17:17] + node _T_21 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_22 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_23 = eq(_T_22, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_24 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_25 = eq(_T_24, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_26 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_27 = and(_T_21, _T_23) @[dec_dec_ctl.scala 17:17] + node _T_28 = and(_T_27, _T_25) @[dec_dec_ctl.scala 17:17] + node _T_29 = and(_T_28, _T_26) @[dec_dec_ctl.scala 17:17] + node _T_30 = or(_T_20, _T_29) @[dec_dec_ctl.scala 20:62] + node _T_31 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_32 = eq(_T_31, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_33 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_34 = eq(_T_33, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_35 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_36 = eq(_T_35, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_37 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_38 = and(_T_32, _T_34) @[dec_dec_ctl.scala 17:17] + node _T_39 = and(_T_38, _T_36) @[dec_dec_ctl.scala 17:17] + node _T_40 = and(_T_39, _T_37) @[dec_dec_ctl.scala 17:17] + node _T_41 = or(_T_30, _T_40) @[dec_dec_ctl.scala 20:92] + node _T_42 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_43 = eq(_T_42, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_44 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_45 = eq(_T_44, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_46 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_47 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_48 = and(_T_43, _T_45) @[dec_dec_ctl.scala 17:17] + node _T_49 = and(_T_48, _T_46) @[dec_dec_ctl.scala 17:17] + node _T_50 = and(_T_49, _T_47) @[dec_dec_ctl.scala 17:17] + node _T_51 = or(_T_41, _T_50) @[dec_dec_ctl.scala 21:34] + node _T_52 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_53 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_54 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_55 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_56 = and(_T_52, _T_53) @[dec_dec_ctl.scala 17:17] + node _T_57 = and(_T_56, _T_54) @[dec_dec_ctl.scala 17:17] + node _T_58 = and(_T_57, _T_55) @[dec_dec_ctl.scala 17:17] + node _T_59 = or(_T_51, _T_58) @[dec_dec_ctl.scala 21:66] + node _T_60 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_61 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_62 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_63 = eq(_T_62, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_64 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_65 = and(_T_60, _T_61) @[dec_dec_ctl.scala 17:17] + node _T_66 = and(_T_65, _T_63) @[dec_dec_ctl.scala 17:17] + node _T_67 = and(_T_66, _T_64) @[dec_dec_ctl.scala 17:17] + node _T_68 = or(_T_59, _T_67) @[dec_dec_ctl.scala 21:94] + node _T_69 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_70 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_71 = eq(_T_70, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_72 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_73 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_74 = and(_T_69, _T_71) @[dec_dec_ctl.scala 17:17] + node _T_75 = and(_T_74, _T_72) @[dec_dec_ctl.scala 17:17] + node _T_76 = and(_T_75, _T_73) @[dec_dec_ctl.scala 17:17] + node _T_77 = or(_T_68, _T_76) @[dec_dec_ctl.scala 22:32] + node _T_78 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_79 = eq(_T_78, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_80 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_81 = eq(_T_80, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_82 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_83 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_84 = and(_T_79, _T_81) @[dec_dec_ctl.scala 17:17] + node _T_85 = and(_T_84, _T_82) @[dec_dec_ctl.scala 17:17] + node _T_86 = and(_T_85, _T_83) @[dec_dec_ctl.scala 17:17] + node _T_87 = or(_T_77, _T_86) @[dec_dec_ctl.scala 22:60] + node _T_88 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_89 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_90 = eq(_T_89, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_91 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_93 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_94 = and(_T_88, _T_90) @[dec_dec_ctl.scala 17:17] + node _T_95 = and(_T_94, _T_92) @[dec_dec_ctl.scala 17:17] + node _T_96 = and(_T_95, _T_93) @[dec_dec_ctl.scala 17:17] + node _T_97 = or(_T_87, _T_96) @[dec_dec_ctl.scala 22:90] + node _T_98 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_99 = eq(_T_98, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_100 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_101 = eq(_T_100, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_102 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_104 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_105 = and(_T_99, _T_101) @[dec_dec_ctl.scala 17:17] + node _T_106 = and(_T_105, _T_103) @[dec_dec_ctl.scala 17:17] + node _T_107 = and(_T_106, _T_104) @[dec_dec_ctl.scala 17:17] + node _T_108 = or(_T_97, _T_107) @[dec_dec_ctl.scala 23:33] + node _T_109 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_110 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_111 = eq(_T_110, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_112 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_113 = and(_T_109, _T_111) @[dec_dec_ctl.scala 17:17] + node _T_114 = and(_T_113, _T_112) @[dec_dec_ctl.scala 17:17] + node _T_115 = or(_T_108, _T_114) @[dec_dec_ctl.scala 23:64] + node _T_116 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_117 = eq(_T_116, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_118 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_119 = eq(_T_118, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_120 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_121 = and(_T_117, _T_119) @[dec_dec_ctl.scala 17:17] + node _T_122 = and(_T_121, _T_120) @[dec_dec_ctl.scala 17:17] + node _T_123 = or(_T_115, _T_122) @[dec_dec_ctl.scala 23:89] + node _T_124 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_125 = or(_T_123, _T_124) @[dec_dec_ctl.scala 24:29] + node _T_126 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_127 = or(_T_125, _T_126) @[dec_dec_ctl.scala 24:48] + node _T_128 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_129 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_130 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_131 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_132 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_133 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_134 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_135 = eq(_T_134, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_136 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_137 = and(_T_128, _T_129) @[dec_dec_ctl.scala 17:17] + node _T_138 = and(_T_137, _T_130) @[dec_dec_ctl.scala 17:17] + node _T_139 = and(_T_138, _T_131) @[dec_dec_ctl.scala 17:17] + node _T_140 = and(_T_139, _T_132) @[dec_dec_ctl.scala 17:17] + node _T_141 = and(_T_140, _T_133) @[dec_dec_ctl.scala 17:17] + node _T_142 = and(_T_141, _T_135) @[dec_dec_ctl.scala 17:17] + node _T_143 = and(_T_142, _T_136) @[dec_dec_ctl.scala 17:17] + node _T_144 = or(_T_127, _T_143) @[dec_dec_ctl.scala 24:67] + node _T_145 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_147 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_148 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_149 = eq(_T_148, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_150 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_152 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_153 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_154 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_155 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_156 = eq(_T_155, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_157 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_158 = and(_T_146, _T_147) @[dec_dec_ctl.scala 17:17] + node _T_159 = and(_T_158, _T_149) @[dec_dec_ctl.scala 17:17] + node _T_160 = and(_T_159, _T_151) @[dec_dec_ctl.scala 17:17] + node _T_161 = and(_T_160, _T_152) @[dec_dec_ctl.scala 17:17] + node _T_162 = and(_T_161, _T_153) @[dec_dec_ctl.scala 17:17] + node _T_163 = and(_T_162, _T_154) @[dec_dec_ctl.scala 17:17] + node _T_164 = and(_T_163, _T_156) @[dec_dec_ctl.scala 17:17] + node _T_165 = and(_T_164, _T_157) @[dec_dec_ctl.scala 17:17] + node _T_166 = or(_T_144, _T_165) @[dec_dec_ctl.scala 24:107] + node _T_167 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_169 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_170 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_172 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_173 = eq(_T_172, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_174 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_175 = eq(_T_174, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_176 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_177 = eq(_T_176, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_178 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_180 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_181 = and(_T_168, _T_169) @[dec_dec_ctl.scala 17:17] + node _T_182 = and(_T_181, _T_171) @[dec_dec_ctl.scala 17:17] + node _T_183 = and(_T_182, _T_173) @[dec_dec_ctl.scala 17:17] + node _T_184 = and(_T_183, _T_175) @[dec_dec_ctl.scala 17:17] + node _T_185 = and(_T_184, _T_177) @[dec_dec_ctl.scala 17:17] + node _T_186 = and(_T_185, _T_179) @[dec_dec_ctl.scala 17:17] + node _T_187 = and(_T_186, _T_180) @[dec_dec_ctl.scala 17:17] + node _T_188 = or(_T_166, _T_187) @[dec_dec_ctl.scala 25:49] + io.out.alu <= _T_188 @[dec_dec_ctl.scala 20:14] + node _T_189 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_190 = eq(_T_189, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_191 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_192 = eq(_T_191, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_193 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_194 = eq(_T_193, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_195 = and(_T_190, _T_192) @[dec_dec_ctl.scala 17:17] + node _T_196 = and(_T_195, _T_194) @[dec_dec_ctl.scala 17:17] + node _T_197 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_198 = eq(_T_197, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_199 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34] + node _T_200 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_201 = eq(_T_200, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_202 = and(_T_198, _T_199) @[dec_dec_ctl.scala 17:17] + node _T_203 = and(_T_202, _T_201) @[dec_dec_ctl.scala 17:17] + node _T_204 = or(_T_196, _T_203) @[dec_dec_ctl.scala 27:43] + node _T_205 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34] + node _T_206 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_207 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_208 = eq(_T_207, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_209 = and(_T_205, _T_206) @[dec_dec_ctl.scala 17:17] + node _T_210 = and(_T_209, _T_208) @[dec_dec_ctl.scala 17:17] + node _T_211 = or(_T_204, _T_210) @[dec_dec_ctl.scala 27:70] + node _T_212 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_213 = eq(_T_212, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_214 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34] + node _T_215 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_217 = and(_T_213, _T_214) @[dec_dec_ctl.scala 17:17] + node _T_218 = and(_T_217, _T_216) @[dec_dec_ctl.scala 17:17] + node _T_219 = or(_T_211, _T_218) @[dec_dec_ctl.scala 27:96] + node _T_220 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34] + node _T_221 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_222 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_223 = eq(_T_222, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_224 = and(_T_220, _T_221) @[dec_dec_ctl.scala 17:17] + node _T_225 = and(_T_224, _T_223) @[dec_dec_ctl.scala 17:17] + node _T_226 = or(_T_219, _T_225) @[dec_dec_ctl.scala 28:30] + node _T_227 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_228 = eq(_T_227, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_229 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34] + node _T_230 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_231 = eq(_T_230, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_232 = and(_T_228, _T_229) @[dec_dec_ctl.scala 17:17] + node _T_233 = and(_T_232, _T_231) @[dec_dec_ctl.scala 17:17] + node _T_234 = or(_T_226, _T_233) @[dec_dec_ctl.scala 28:57] + node _T_235 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34] + node _T_236 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_237 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_238 = eq(_T_237, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_239 = and(_T_235, _T_236) @[dec_dec_ctl.scala 17:17] + node _T_240 = and(_T_239, _T_238) @[dec_dec_ctl.scala 17:17] + node _T_241 = or(_T_234, _T_240) @[dec_dec_ctl.scala 28:83] + node _T_242 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_243 = eq(_T_242, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_244 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34] + node _T_245 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_246 = eq(_T_245, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_247 = and(_T_243, _T_244) @[dec_dec_ctl.scala 17:17] + node _T_248 = and(_T_247, _T_246) @[dec_dec_ctl.scala 17:17] + node _T_249 = or(_T_241, _T_248) @[dec_dec_ctl.scala 28:109] + node _T_250 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34] + node _T_251 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_252 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_254 = and(_T_250, _T_251) @[dec_dec_ctl.scala 17:17] + node _T_255 = and(_T_254, _T_253) @[dec_dec_ctl.scala 17:17] + node _T_256 = or(_T_249, _T_255) @[dec_dec_ctl.scala 29:29] + node _T_257 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_258 = eq(_T_257, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_259 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34] + node _T_260 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_261 = eq(_T_260, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_262 = and(_T_258, _T_259) @[dec_dec_ctl.scala 17:17] + node _T_263 = and(_T_262, _T_261) @[dec_dec_ctl.scala 17:17] + node _T_264 = or(_T_256, _T_263) @[dec_dec_ctl.scala 29:55] + node _T_265 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34] + node _T_266 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_267 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_268 = eq(_T_267, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_269 = and(_T_265, _T_266) @[dec_dec_ctl.scala 17:17] + node _T_270 = and(_T_269, _T_268) @[dec_dec_ctl.scala 17:17] + node _T_271 = or(_T_264, _T_270) @[dec_dec_ctl.scala 29:81] + node _T_272 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_274 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_275 = eq(_T_274, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_276 = and(_T_273, _T_275) @[dec_dec_ctl.scala 17:17] + node _T_277 = or(_T_271, _T_276) @[dec_dec_ctl.scala 30:29] + node _T_278 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_279 = eq(_T_278, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_280 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_281 = eq(_T_280, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_282 = and(_T_279, _T_281) @[dec_dec_ctl.scala 17:17] + node _T_283 = or(_T_277, _T_282) @[dec_dec_ctl.scala 30:52] + io.out.rs1 <= _T_283 @[dec_dec_ctl.scala 27:14] + node _T_284 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_285 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_286 = eq(_T_285, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_287 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_288 = eq(_T_287, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_289 = and(_T_284, _T_286) @[dec_dec_ctl.scala 17:17] + node _T_290 = and(_T_289, _T_288) @[dec_dec_ctl.scala 17:17] + node _T_291 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_292 = eq(_T_291, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_293 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_294 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_295 = eq(_T_294, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_296 = and(_T_292, _T_293) @[dec_dec_ctl.scala 17:17] + node _T_297 = and(_T_296, _T_295) @[dec_dec_ctl.scala 17:17] + node _T_298 = or(_T_290, _T_297) @[dec_dec_ctl.scala 32:40] + io.out.rs2 <= _T_298 @[dec_dec_ctl.scala 32:14] + node _T_299 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_300 = eq(_T_299, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_301 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_302 = eq(_T_301, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_303 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_304 = and(_T_300, _T_302) @[dec_dec_ctl.scala 17:17] + node _T_305 = and(_T_304, _T_303) @[dec_dec_ctl.scala 17:17] + node _T_306 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_307 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_308 = eq(_T_307, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_309 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_310 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_311 = eq(_T_310, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_312 = and(_T_306, _T_308) @[dec_dec_ctl.scala 17:17] + node _T_313 = and(_T_312, _T_309) @[dec_dec_ctl.scala 17:17] + node _T_314 = and(_T_313, _T_311) @[dec_dec_ctl.scala 17:17] + node _T_315 = or(_T_305, _T_314) @[dec_dec_ctl.scala 34:42] + node _T_316 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_317 = eq(_T_316, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_318 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_319 = eq(_T_318, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_320 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_321 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_322 = and(_T_317, _T_319) @[dec_dec_ctl.scala 17:17] + node _T_323 = and(_T_322, _T_320) @[dec_dec_ctl.scala 17:17] + node _T_324 = and(_T_323, _T_321) @[dec_dec_ctl.scala 17:17] + node _T_325 = or(_T_315, _T_324) @[dec_dec_ctl.scala 34:70] + node _T_326 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_328 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_330 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_331 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_332 = eq(_T_331, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_333 = and(_T_327, _T_329) @[dec_dec_ctl.scala 17:17] + node _T_334 = and(_T_333, _T_330) @[dec_dec_ctl.scala 17:17] + node _T_335 = and(_T_334, _T_332) @[dec_dec_ctl.scala 17:17] + node _T_336 = or(_T_325, _T_335) @[dec_dec_ctl.scala 34:99] + io.out.imm12 <= _T_336 @[dec_dec_ctl.scala 34:16] + node _T_337 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_339 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_340 = eq(_T_339, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_341 = and(_T_338, _T_340) @[dec_dec_ctl.scala 17:17] + node _T_342 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_343 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_344 = and(_T_342, _T_343) @[dec_dec_ctl.scala 17:17] + node _T_345 = or(_T_341, _T_344) @[dec_dec_ctl.scala 36:37] + node _T_346 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_347 = or(_T_345, _T_346) @[dec_dec_ctl.scala 36:58] + io.out.rd <= _T_347 @[dec_dec_ctl.scala 36:13] + node _T_348 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_349 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_350 = eq(_T_349, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_351 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_352 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_354 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_355 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_356 = eq(_T_355, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_357 = and(_T_348, _T_350) @[dec_dec_ctl.scala 17:17] + node _T_358 = and(_T_357, _T_351) @[dec_dec_ctl.scala 17:17] + node _T_359 = and(_T_358, _T_353) @[dec_dec_ctl.scala 17:17] + node _T_360 = and(_T_359, _T_354) @[dec_dec_ctl.scala 17:17] + node _T_361 = and(_T_360, _T_356) @[dec_dec_ctl.scala 17:17] + node _T_362 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_363 = eq(_T_362, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_364 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_365 = eq(_T_364, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_366 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_367 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_369 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_370 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_371 = eq(_T_370, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_372 = and(_T_363, _T_365) @[dec_dec_ctl.scala 17:17] + node _T_373 = and(_T_372, _T_366) @[dec_dec_ctl.scala 17:17] + node _T_374 = and(_T_373, _T_368) @[dec_dec_ctl.scala 17:17] + node _T_375 = and(_T_374, _T_369) @[dec_dec_ctl.scala 17:17] + node _T_376 = and(_T_375, _T_371) @[dec_dec_ctl.scala 17:17] + node _T_377 = or(_T_361, _T_376) @[dec_dec_ctl.scala 38:53] + node _T_378 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_379 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_380 = eq(_T_379, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_381 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_382 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_383 = eq(_T_382, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_384 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_385 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_387 = and(_T_378, _T_380) @[dec_dec_ctl.scala 17:17] + node _T_388 = and(_T_387, _T_381) @[dec_dec_ctl.scala 17:17] + node _T_389 = and(_T_388, _T_383) @[dec_dec_ctl.scala 17:17] + node _T_390 = and(_T_389, _T_384) @[dec_dec_ctl.scala 17:17] + node _T_391 = and(_T_390, _T_386) @[dec_dec_ctl.scala 17:17] + node _T_392 = or(_T_377, _T_391) @[dec_dec_ctl.scala 38:89] + io.out.shimm5 <= _T_392 @[dec_dec_ctl.scala 38:17] + node _T_393 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_394 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_395 = and(_T_393, _T_394) @[dec_dec_ctl.scala 17:17] + node _T_396 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_397 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_398 = and(_T_396, _T_397) @[dec_dec_ctl.scala 17:17] + node _T_399 = or(_T_395, _T_398) @[dec_dec_ctl.scala 40:38] + io.out.imm20 <= _T_399 @[dec_dec_ctl.scala 40:16] + node _T_400 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_401 = eq(_T_400, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_402 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_403 = eq(_T_402, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_404 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_405 = and(_T_401, _T_403) @[dec_dec_ctl.scala 17:17] + node _T_406 = and(_T_405, _T_404) @[dec_dec_ctl.scala 17:17] + node _T_407 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_408 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_409 = and(_T_407, _T_408) @[dec_dec_ctl.scala 17:17] + node _T_410 = or(_T_406, _T_409) @[dec_dec_ctl.scala 42:39] + io.out.pc <= _T_410 @[dec_dec_ctl.scala 42:13] + node _T_411 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_412 = eq(_T_411, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_413 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_414 = eq(_T_413, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_415 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_416 = eq(_T_415, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_417 = and(_T_412, _T_414) @[dec_dec_ctl.scala 17:17] + node _T_418 = and(_T_417, _T_416) @[dec_dec_ctl.scala 17:17] + io.out.load <= _T_418 @[dec_dec_ctl.scala 44:15] + node _T_419 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_420 = eq(_T_419, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_421 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_422 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_424 = and(_T_420, _T_421) @[dec_dec_ctl.scala 17:17] + node _T_425 = and(_T_424, _T_423) @[dec_dec_ctl.scala 17:17] + io.out.store <= _T_425 @[dec_dec_ctl.scala 46:16] + node _T_426 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_427 = eq(_T_426, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_428 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_429 = eq(_T_428, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_430 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_431 = eq(_T_430, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_432 = and(_T_427, _T_429) @[dec_dec_ctl.scala 17:17] + node _T_433 = and(_T_432, _T_431) @[dec_dec_ctl.scala 17:17] + io.out.lsu <= _T_433 @[dec_dec_ctl.scala 48:14] + node _T_434 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_436 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_438 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_439 = eq(_T_438, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_440 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_441 = eq(_T_440, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_442 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_443 = and(_T_435, _T_437) @[dec_dec_ctl.scala 17:17] + node _T_444 = and(_T_443, _T_439) @[dec_dec_ctl.scala 17:17] + node _T_445 = and(_T_444, _T_441) @[dec_dec_ctl.scala 17:17] + node _T_446 = and(_T_445, _T_442) @[dec_dec_ctl.scala 17:17] + node _T_447 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_448 = eq(_T_447, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_449 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_450 = eq(_T_449, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_451 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_452 = and(_T_448, _T_450) @[dec_dec_ctl.scala 17:17] + node _T_453 = and(_T_452, _T_451) @[dec_dec_ctl.scala 17:17] + node _T_454 = or(_T_446, _T_453) @[dec_dec_ctl.scala 50:49] + node _T_455 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_457 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_458 = eq(_T_457, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_459 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_460 = eq(_T_459, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_461 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_462 = eq(_T_461, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_463 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_464 = eq(_T_463, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_465 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_466 = eq(_T_465, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_467 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_468 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_470 = and(_T_456, _T_458) @[dec_dec_ctl.scala 17:17] + node _T_471 = and(_T_470, _T_460) @[dec_dec_ctl.scala 17:17] + node _T_472 = and(_T_471, _T_462) @[dec_dec_ctl.scala 17:17] + node _T_473 = and(_T_472, _T_464) @[dec_dec_ctl.scala 17:17] + node _T_474 = and(_T_473, _T_466) @[dec_dec_ctl.scala 17:17] + node _T_475 = and(_T_474, _T_467) @[dec_dec_ctl.scala 17:17] + node _T_476 = and(_T_475, _T_469) @[dec_dec_ctl.scala 17:17] + node _T_477 = or(_T_454, _T_476) @[dec_dec_ctl.scala 50:74] + io.out.add <= _T_477 @[dec_dec_ctl.scala 50:14] + node _T_478 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_479 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_480 = eq(_T_479, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_481 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_482 = eq(_T_481, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_483 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_485 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_486 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_487 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_489 = and(_T_478, _T_480) @[dec_dec_ctl.scala 17:17] + node _T_490 = and(_T_489, _T_482) @[dec_dec_ctl.scala 17:17] + node _T_491 = and(_T_490, _T_484) @[dec_dec_ctl.scala 17:17] + node _T_492 = and(_T_491, _T_485) @[dec_dec_ctl.scala 17:17] + node _T_493 = and(_T_492, _T_486) @[dec_dec_ctl.scala 17:17] + node _T_494 = and(_T_493, _T_488) @[dec_dec_ctl.scala 17:17] + node _T_495 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_496 = eq(_T_495, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_497 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_498 = eq(_T_497, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_499 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_500 = eq(_T_499, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_501 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_502 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_503 = eq(_T_502, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_504 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_505 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_506 = eq(_T_505, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_507 = and(_T_496, _T_498) @[dec_dec_ctl.scala 17:17] + node _T_508 = and(_T_507, _T_500) @[dec_dec_ctl.scala 17:17] + node _T_509 = and(_T_508, _T_501) @[dec_dec_ctl.scala 17:17] + node _T_510 = and(_T_509, _T_503) @[dec_dec_ctl.scala 17:17] + node _T_511 = and(_T_510, _T_504) @[dec_dec_ctl.scala 17:17] + node _T_512 = and(_T_511, _T_506) @[dec_dec_ctl.scala 17:17] + node _T_513 = or(_T_494, _T_512) @[dec_dec_ctl.scala 52:53] + node _T_514 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_515 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_516 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_517 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_518 = eq(_T_517, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_519 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_520 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_521 = eq(_T_520, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_522 = and(_T_514, _T_515) @[dec_dec_ctl.scala 17:17] + node _T_523 = and(_T_522, _T_516) @[dec_dec_ctl.scala 17:17] + node _T_524 = and(_T_523, _T_518) @[dec_dec_ctl.scala 17:17] + node _T_525 = and(_T_524, _T_519) @[dec_dec_ctl.scala 17:17] + node _T_526 = and(_T_525, _T_521) @[dec_dec_ctl.scala 17:17] + node _T_527 = or(_T_513, _T_526) @[dec_dec_ctl.scala 52:93] + node _T_528 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_529 = eq(_T_528, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_530 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_531 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_533 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_534 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_536 = and(_T_529, _T_530) @[dec_dec_ctl.scala 17:17] + node _T_537 = and(_T_536, _T_532) @[dec_dec_ctl.scala 17:17] + node _T_538 = and(_T_537, _T_533) @[dec_dec_ctl.scala 17:17] + node _T_539 = and(_T_538, _T_535) @[dec_dec_ctl.scala 17:17] + node _T_540 = or(_T_527, _T_539) @[dec_dec_ctl.scala 53:37] + node _T_541 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_542 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_543 = eq(_T_542, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_544 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_545 = eq(_T_544, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_546 = and(_T_541, _T_543) @[dec_dec_ctl.scala 17:17] + node _T_547 = and(_T_546, _T_545) @[dec_dec_ctl.scala 17:17] + node _T_548 = or(_T_540, _T_547) @[dec_dec_ctl.scala 53:69] + io.out.sub <= _T_548 @[dec_dec_ctl.scala 52:14] + node _T_549 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_550 = eq(_T_549, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_551 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_552 = eq(_T_551, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_553 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_554 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_555 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_556 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_557 = eq(_T_556, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_558 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_560 = and(_T_550, _T_552) @[dec_dec_ctl.scala 17:17] + node _T_561 = and(_T_560, _T_553) @[dec_dec_ctl.scala 17:17] + node _T_562 = and(_T_561, _T_554) @[dec_dec_ctl.scala 17:17] + node _T_563 = and(_T_562, _T_555) @[dec_dec_ctl.scala 17:17] + node _T_564 = and(_T_563, _T_557) @[dec_dec_ctl.scala 17:17] + node _T_565 = and(_T_564, _T_559) @[dec_dec_ctl.scala 17:17] + node _T_566 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_567 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_568 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_569 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_570 = eq(_T_569, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_571 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_572 = eq(_T_571, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_573 = and(_T_566, _T_567) @[dec_dec_ctl.scala 17:17] + node _T_574 = and(_T_573, _T_568) @[dec_dec_ctl.scala 17:17] + node _T_575 = and(_T_574, _T_570) @[dec_dec_ctl.scala 17:17] + node _T_576 = and(_T_575, _T_572) @[dec_dec_ctl.scala 17:17] + node _T_577 = or(_T_565, _T_576) @[dec_dec_ctl.scala 55:56] + io.out.land <= _T_577 @[dec_dec_ctl.scala 55:15] + node _T_578 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_579 = eq(_T_578, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_580 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_581 = and(_T_579, _T_580) @[dec_dec_ctl.scala 17:17] + node _T_582 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_583 = eq(_T_582, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_584 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_585 = eq(_T_584, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_586 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_587 = eq(_T_586, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_588 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_589 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_590 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_591 = eq(_T_590, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_592 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_593 = eq(_T_592, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_594 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_595 = eq(_T_594, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_596 = and(_T_583, _T_585) @[dec_dec_ctl.scala 17:17] + node _T_597 = and(_T_596, _T_587) @[dec_dec_ctl.scala 17:17] + node _T_598 = and(_T_597, _T_588) @[dec_dec_ctl.scala 17:17] + node _T_599 = and(_T_598, _T_589) @[dec_dec_ctl.scala 17:17] + node _T_600 = and(_T_599, _T_591) @[dec_dec_ctl.scala 17:17] + node _T_601 = and(_T_600, _T_593) @[dec_dec_ctl.scala 17:17] + node _T_602 = and(_T_601, _T_595) @[dec_dec_ctl.scala 17:17] + node _T_603 = or(_T_581, _T_602) @[dec_dec_ctl.scala 57:37] + node _T_604 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_605 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_606 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_607 = and(_T_604, _T_605) @[dec_dec_ctl.scala 17:17] + node _T_608 = and(_T_607, _T_606) @[dec_dec_ctl.scala 17:17] + node _T_609 = or(_T_603, _T_608) @[dec_dec_ctl.scala 57:82] + node _T_610 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_611 = eq(_T_610, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_612 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_613 = eq(_T_612, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_614 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_615 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_616 = and(_T_611, _T_613) @[dec_dec_ctl.scala 17:17] + node _T_617 = and(_T_616, _T_614) @[dec_dec_ctl.scala 17:17] + node _T_618 = and(_T_617, _T_615) @[dec_dec_ctl.scala 17:17] + node _T_619 = or(_T_609, _T_618) @[dec_dec_ctl.scala 57:105] + node _T_620 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_621 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_622 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_623 = eq(_T_622, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_624 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_625 = eq(_T_624, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_626 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_627 = eq(_T_626, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_628 = and(_T_620, _T_621) @[dec_dec_ctl.scala 17:17] + node _T_629 = and(_T_628, _T_623) @[dec_dec_ctl.scala 17:17] + node _T_630 = and(_T_629, _T_625) @[dec_dec_ctl.scala 17:17] + node _T_631 = and(_T_630, _T_627) @[dec_dec_ctl.scala 17:17] + node _T_632 = or(_T_619, _T_631) @[dec_dec_ctl.scala 58:32] + io.out.lor <= _T_632 @[dec_dec_ctl.scala 57:14] + node _T_633 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_634 = eq(_T_633, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_635 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_636 = eq(_T_635, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_637 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_638 = eq(_T_637, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_639 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_640 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_641 = eq(_T_640, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_642 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_643 = eq(_T_642, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_644 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_645 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_646 = eq(_T_645, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_647 = and(_T_634, _T_636) @[dec_dec_ctl.scala 17:17] + node _T_648 = and(_T_647, _T_638) @[dec_dec_ctl.scala 17:17] + node _T_649 = and(_T_648, _T_639) @[dec_dec_ctl.scala 17:17] + node _T_650 = and(_T_649, _T_641) @[dec_dec_ctl.scala 17:17] + node _T_651 = and(_T_650, _T_643) @[dec_dec_ctl.scala 17:17] + node _T_652 = and(_T_651, _T_644) @[dec_dec_ctl.scala 17:17] + node _T_653 = and(_T_652, _T_646) @[dec_dec_ctl.scala 17:17] + node _T_654 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_655 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_656 = eq(_T_655, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_657 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_658 = eq(_T_657, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_659 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_660 = eq(_T_659, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_661 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_662 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_663 = eq(_T_662, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_664 = and(_T_654, _T_656) @[dec_dec_ctl.scala 17:17] + node _T_665 = and(_T_664, _T_658) @[dec_dec_ctl.scala 17:17] + node _T_666 = and(_T_665, _T_660) @[dec_dec_ctl.scala 17:17] + node _T_667 = and(_T_666, _T_661) @[dec_dec_ctl.scala 17:17] + node _T_668 = and(_T_667, _T_663) @[dec_dec_ctl.scala 17:17] + node _T_669 = or(_T_653, _T_668) @[dec_dec_ctl.scala 60:61] + io.out.lxor <= _T_669 @[dec_dec_ctl.scala 60:15] + node _T_670 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_671 = eq(_T_670, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_672 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_673 = eq(_T_672, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_674 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_675 = eq(_T_674, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_676 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_677 = eq(_T_676, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_678 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_679 = eq(_T_678, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_680 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_681 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_682 = eq(_T_681, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_683 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_684 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_685 = eq(_T_684, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_686 = and(_T_671, _T_673) @[dec_dec_ctl.scala 17:17] + node _T_687 = and(_T_686, _T_675) @[dec_dec_ctl.scala 17:17] + node _T_688 = and(_T_687, _T_677) @[dec_dec_ctl.scala 17:17] + node _T_689 = and(_T_688, _T_679) @[dec_dec_ctl.scala 17:17] + node _T_690 = and(_T_689, _T_680) @[dec_dec_ctl.scala 17:17] + node _T_691 = and(_T_690, _T_682) @[dec_dec_ctl.scala 17:17] + node _T_692 = and(_T_691, _T_683) @[dec_dec_ctl.scala 17:17] + node _T_693 = and(_T_692, _T_685) @[dec_dec_ctl.scala 17:17] + io.out.sll <= _T_693 @[dec_dec_ctl.scala 62:14] + node _T_694 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_695 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_696 = eq(_T_695, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_697 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_698 = eq(_T_697, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_699 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_700 = eq(_T_699, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_701 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_702 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_703 = eq(_T_702, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_704 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_705 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_706 = eq(_T_705, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_707 = and(_T_694, _T_696) @[dec_dec_ctl.scala 17:17] + node _T_708 = and(_T_707, _T_698) @[dec_dec_ctl.scala 17:17] + node _T_709 = and(_T_708, _T_700) @[dec_dec_ctl.scala 17:17] + node _T_710 = and(_T_709, _T_701) @[dec_dec_ctl.scala 17:17] + node _T_711 = and(_T_710, _T_703) @[dec_dec_ctl.scala 17:17] + node _T_712 = and(_T_711, _T_704) @[dec_dec_ctl.scala 17:17] + node _T_713 = and(_T_712, _T_706) @[dec_dec_ctl.scala 17:17] + io.out.sra <= _T_713 @[dec_dec_ctl.scala 64:14] + node _T_714 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_715 = eq(_T_714, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_716 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_717 = eq(_T_716, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_718 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_719 = eq(_T_718, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_720 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_721 = eq(_T_720, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_722 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_723 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_724 = eq(_T_723, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_725 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_726 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_727 = eq(_T_726, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_728 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_729 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_730 = eq(_T_729, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_731 = and(_T_715, _T_717) @[dec_dec_ctl.scala 17:17] + node _T_732 = and(_T_731, _T_719) @[dec_dec_ctl.scala 17:17] + node _T_733 = and(_T_732, _T_721) @[dec_dec_ctl.scala 17:17] + node _T_734 = and(_T_733, _T_722) @[dec_dec_ctl.scala 17:17] + node _T_735 = and(_T_734, _T_724) @[dec_dec_ctl.scala 17:17] + node _T_736 = and(_T_735, _T_725) @[dec_dec_ctl.scala 17:17] + node _T_737 = and(_T_736, _T_727) @[dec_dec_ctl.scala 17:17] + node _T_738 = and(_T_737, _T_728) @[dec_dec_ctl.scala 17:17] + node _T_739 = and(_T_738, _T_730) @[dec_dec_ctl.scala 17:17] + io.out.srl <= _T_739 @[dec_dec_ctl.scala 66:14] + node _T_740 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_741 = eq(_T_740, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_742 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_743 = eq(_T_742, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_744 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_745 = eq(_T_744, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_746 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_747 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_748 = eq(_T_747, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_749 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_750 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_751 = eq(_T_750, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_752 = and(_T_741, _T_743) @[dec_dec_ctl.scala 17:17] + node _T_753 = and(_T_752, _T_745) @[dec_dec_ctl.scala 17:17] + node _T_754 = and(_T_753, _T_746) @[dec_dec_ctl.scala 17:17] + node _T_755 = and(_T_754, _T_748) @[dec_dec_ctl.scala 17:17] + node _T_756 = and(_T_755, _T_749) @[dec_dec_ctl.scala 17:17] + node _T_757 = and(_T_756, _T_751) @[dec_dec_ctl.scala 17:17] + node _T_758 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_759 = eq(_T_758, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_760 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_761 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_762 = eq(_T_761, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_763 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_764 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_765 = eq(_T_764, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_766 = and(_T_759, _T_760) @[dec_dec_ctl.scala 17:17] + node _T_767 = and(_T_766, _T_762) @[dec_dec_ctl.scala 17:17] + node _T_768 = and(_T_767, _T_763) @[dec_dec_ctl.scala 17:17] + node _T_769 = and(_T_768, _T_765) @[dec_dec_ctl.scala 17:17] + node _T_770 = or(_T_757, _T_769) @[dec_dec_ctl.scala 68:55] + io.out.slt <= _T_770 @[dec_dec_ctl.scala 68:14] + node _T_771 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_773 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_774 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_775 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_776 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_778 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_779 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_780 = eq(_T_779, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_781 = and(_T_772, _T_773) @[dec_dec_ctl.scala 17:17] + node _T_782 = and(_T_781, _T_774) @[dec_dec_ctl.scala 17:17] + node _T_783 = and(_T_782, _T_775) @[dec_dec_ctl.scala 17:17] + node _T_784 = and(_T_783, _T_777) @[dec_dec_ctl.scala 17:17] + node _T_785 = and(_T_784, _T_778) @[dec_dec_ctl.scala 17:17] + node _T_786 = and(_T_785, _T_780) @[dec_dec_ctl.scala 17:17] + node _T_787 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_788 = eq(_T_787, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_789 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_790 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_791 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_792 = eq(_T_791, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_793 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_794 = eq(_T_793, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_795 = and(_T_788, _T_789) @[dec_dec_ctl.scala 17:17] + node _T_796 = and(_T_795, _T_790) @[dec_dec_ctl.scala 17:17] + node _T_797 = and(_T_796, _T_792) @[dec_dec_ctl.scala 17:17] + node _T_798 = and(_T_797, _T_794) @[dec_dec_ctl.scala 17:17] + node _T_799 = or(_T_786, _T_798) @[dec_dec_ctl.scala 70:56] + node _T_800 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_801 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_802 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_803 = eq(_T_802, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_804 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_805 = eq(_T_804, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_806 = and(_T_800, _T_801) @[dec_dec_ctl.scala 17:17] + node _T_807 = and(_T_806, _T_803) @[dec_dec_ctl.scala 17:17] + node _T_808 = and(_T_807, _T_805) @[dec_dec_ctl.scala 17:17] + node _T_809 = or(_T_799, _T_808) @[dec_dec_ctl.scala 70:89] + node _T_810 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_811 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_813 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_814 = eq(_T_813, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_815 = and(_T_810, _T_812) @[dec_dec_ctl.scala 17:17] + node _T_816 = and(_T_815, _T_814) @[dec_dec_ctl.scala 17:17] + node _T_817 = or(_T_809, _T_816) @[dec_dec_ctl.scala 71:31] + node _T_818 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_819 = eq(_T_818, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_820 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_821 = eq(_T_820, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_822 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_823 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_824 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_825 = eq(_T_824, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_826 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_827 = eq(_T_826, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_828 = and(_T_819, _T_821) @[dec_dec_ctl.scala 17:17] + node _T_829 = and(_T_828, _T_822) @[dec_dec_ctl.scala 17:17] + node _T_830 = and(_T_829, _T_823) @[dec_dec_ctl.scala 17:17] + node _T_831 = and(_T_830, _T_825) @[dec_dec_ctl.scala 17:17] + node _T_832 = and(_T_831, _T_827) @[dec_dec_ctl.scala 17:17] + node _T_833 = or(_T_817, _T_832) @[dec_dec_ctl.scala 71:57] + node _T_834 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_835 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_836 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_837 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_838 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_840 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_841 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_842 = eq(_T_841, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_843 = and(_T_834, _T_835) @[dec_dec_ctl.scala 17:17] + node _T_844 = and(_T_843, _T_836) @[dec_dec_ctl.scala 17:17] + node _T_845 = and(_T_844, _T_837) @[dec_dec_ctl.scala 17:17] + node _T_846 = and(_T_845, _T_839) @[dec_dec_ctl.scala 17:17] + node _T_847 = and(_T_846, _T_840) @[dec_dec_ctl.scala 17:17] + node _T_848 = and(_T_847, _T_842) @[dec_dec_ctl.scala 17:17] + node _T_849 = or(_T_833, _T_848) @[dec_dec_ctl.scala 71:94] + io.out.unsign <= _T_849 @[dec_dec_ctl.scala 70:17] + node _T_850 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_851 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_852 = eq(_T_851, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_853 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_854 = eq(_T_853, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_855 = and(_T_850, _T_852) @[dec_dec_ctl.scala 17:17] + node _T_856 = and(_T_855, _T_854) @[dec_dec_ctl.scala 17:17] + io.out.condbr <= _T_856 @[dec_dec_ctl.scala 74:17] + node _T_857 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_858 = eq(_T_857, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_859 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_860 = eq(_T_859, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_861 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_862 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_863 = eq(_T_862, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_864 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_865 = eq(_T_864, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_866 = and(_T_858, _T_860) @[dec_dec_ctl.scala 17:17] + node _T_867 = and(_T_866, _T_861) @[dec_dec_ctl.scala 17:17] + node _T_868 = and(_T_867, _T_863) @[dec_dec_ctl.scala 17:17] + node _T_869 = and(_T_868, _T_865) @[dec_dec_ctl.scala 17:17] + io.out.beq <= _T_869 @[dec_dec_ctl.scala 76:14] + node _T_870 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_871 = eq(_T_870, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_872 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_873 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_874 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_875 = eq(_T_874, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_876 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_877 = eq(_T_876, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_878 = and(_T_871, _T_872) @[dec_dec_ctl.scala 17:17] + node _T_879 = and(_T_878, _T_873) @[dec_dec_ctl.scala 17:17] + node _T_880 = and(_T_879, _T_875) @[dec_dec_ctl.scala 17:17] + node _T_881 = and(_T_880, _T_877) @[dec_dec_ctl.scala 17:17] + io.out.bne <= _T_881 @[dec_dec_ctl.scala 78:14] + node _T_882 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_883 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_884 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_885 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_886 = eq(_T_885, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_887 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_888 = eq(_T_887, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_889 = and(_T_882, _T_883) @[dec_dec_ctl.scala 17:17] + node _T_890 = and(_T_889, _T_884) @[dec_dec_ctl.scala 17:17] + node _T_891 = and(_T_890, _T_886) @[dec_dec_ctl.scala 17:17] + node _T_892 = and(_T_891, _T_888) @[dec_dec_ctl.scala 17:17] + io.out.bge <= _T_892 @[dec_dec_ctl.scala 80:14] + node _T_893 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_894 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_896 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_897 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_898 = eq(_T_897, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_899 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_900 = eq(_T_899, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_901 = and(_T_893, _T_895) @[dec_dec_ctl.scala 17:17] + node _T_902 = and(_T_901, _T_896) @[dec_dec_ctl.scala 17:17] + node _T_903 = and(_T_902, _T_898) @[dec_dec_ctl.scala 17:17] + node _T_904 = and(_T_903, _T_900) @[dec_dec_ctl.scala 17:17] + io.out.blt <= _T_904 @[dec_dec_ctl.scala 82:14] + node _T_905 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_906 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_907 = and(_T_905, _T_906) @[dec_dec_ctl.scala 17:17] + io.out.jal <= _T_907 @[dec_dec_ctl.scala 84:14] + node _T_908 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_909 = eq(_T_908, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_910 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_911 = eq(_T_910, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_912 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_913 = eq(_T_912, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_914 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_915 = eq(_T_914, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_916 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_917 = eq(_T_916, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_918 = and(_T_909, _T_911) @[dec_dec_ctl.scala 17:17] + node _T_919 = and(_T_918, _T_913) @[dec_dec_ctl.scala 17:17] + node _T_920 = and(_T_919, _T_915) @[dec_dec_ctl.scala 17:17] + node _T_921 = and(_T_920, _T_917) @[dec_dec_ctl.scala 17:17] + io.out.by <= _T_921 @[dec_dec_ctl.scala 86:13] + node _T_922 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_923 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_924 = eq(_T_923, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_925 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_926 = eq(_T_925, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_927 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_928 = eq(_T_927, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_929 = and(_T_922, _T_924) @[dec_dec_ctl.scala 17:17] + node _T_930 = and(_T_929, _T_926) @[dec_dec_ctl.scala 17:17] + node _T_931 = and(_T_930, _T_928) @[dec_dec_ctl.scala 17:17] + io.out.half <= _T_931 @[dec_dec_ctl.scala 88:15] + node _T_932 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_933 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_934 = eq(_T_933, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_935 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_936 = eq(_T_935, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_937 = and(_T_932, _T_934) @[dec_dec_ctl.scala 17:17] + node _T_938 = and(_T_937, _T_936) @[dec_dec_ctl.scala 17:17] + io.out.word <= _T_938 @[dec_dec_ctl.scala 90:15] + node _T_939 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_940 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_941 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_942 = and(_T_939, _T_940) @[dec_dec_ctl.scala 17:17] + node _T_943 = and(_T_942, _T_941) @[dec_dec_ctl.scala 17:17] + node _T_944 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34] + node _T_945 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_946 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_947 = and(_T_944, _T_945) @[dec_dec_ctl.scala 17:17] + node _T_948 = and(_T_947, _T_946) @[dec_dec_ctl.scala 17:17] + node _T_949 = or(_T_943, _T_948) @[dec_dec_ctl.scala 92:44] + node _T_950 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34] + node _T_951 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_952 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_953 = and(_T_950, _T_951) @[dec_dec_ctl.scala 17:17] + node _T_954 = and(_T_953, _T_952) @[dec_dec_ctl.scala 17:17] + node _T_955 = or(_T_949, _T_954) @[dec_dec_ctl.scala 92:67] + node _T_956 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34] + node _T_957 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_958 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_959 = and(_T_956, _T_957) @[dec_dec_ctl.scala 17:17] + node _T_960 = and(_T_959, _T_958) @[dec_dec_ctl.scala 17:17] + node _T_961 = or(_T_955, _T_960) @[dec_dec_ctl.scala 92:90] + node _T_962 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34] + node _T_963 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_964 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_965 = and(_T_962, _T_963) @[dec_dec_ctl.scala 17:17] + node _T_966 = and(_T_965, _T_964) @[dec_dec_ctl.scala 17:17] + node _T_967 = or(_T_961, _T_966) @[dec_dec_ctl.scala 93:26] + node _T_968 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34] + node _T_969 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_970 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_971 = and(_T_968, _T_969) @[dec_dec_ctl.scala 17:17] + node _T_972 = and(_T_971, _T_970) @[dec_dec_ctl.scala 17:17] + node _T_973 = or(_T_967, _T_972) @[dec_dec_ctl.scala 93:50] + io.out.csr_read <= _T_973 @[dec_dec_ctl.scala 92:19] + node _T_974 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34] + node _T_975 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_976 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_977 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_978 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_979 = and(_T_974, _T_975) @[dec_dec_ctl.scala 17:17] + node _T_980 = and(_T_979, _T_976) @[dec_dec_ctl.scala 17:17] + node _T_981 = and(_T_980, _T_977) @[dec_dec_ctl.scala 17:17] + node _T_982 = and(_T_981, _T_978) @[dec_dec_ctl.scala 17:17] + node _T_983 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34] + node _T_984 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_985 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_986 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_987 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_988 = and(_T_983, _T_984) @[dec_dec_ctl.scala 17:17] + node _T_989 = and(_T_988, _T_985) @[dec_dec_ctl.scala 17:17] + node _T_990 = and(_T_989, _T_986) @[dec_dec_ctl.scala 17:17] + node _T_991 = and(_T_990, _T_987) @[dec_dec_ctl.scala 17:17] + node _T_992 = or(_T_982, _T_991) @[dec_dec_ctl.scala 95:49] + node _T_993 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34] + node _T_994 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_995 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_996 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_997 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_998 = and(_T_993, _T_994) @[dec_dec_ctl.scala 17:17] + node _T_999 = and(_T_998, _T_995) @[dec_dec_ctl.scala 17:17] + node _T_1000 = and(_T_999, _T_996) @[dec_dec_ctl.scala 17:17] + node _T_1001 = and(_T_1000, _T_997) @[dec_dec_ctl.scala 17:17] + node _T_1002 = or(_T_992, _T_1001) @[dec_dec_ctl.scala 95:79] + node _T_1003 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34] + node _T_1004 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1005 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1006 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1007 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1008 = and(_T_1003, _T_1004) @[dec_dec_ctl.scala 17:17] + node _T_1009 = and(_T_1008, _T_1005) @[dec_dec_ctl.scala 17:17] + node _T_1010 = and(_T_1009, _T_1006) @[dec_dec_ctl.scala 17:17] + node _T_1011 = and(_T_1010, _T_1007) @[dec_dec_ctl.scala 17:17] + node _T_1012 = or(_T_1002, _T_1011) @[dec_dec_ctl.scala 96:33] + node _T_1013 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34] + node _T_1014 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1015 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1016 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1017 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1018 = and(_T_1013, _T_1014) @[dec_dec_ctl.scala 17:17] + node _T_1019 = and(_T_1018, _T_1015) @[dec_dec_ctl.scala 17:17] + node _T_1020 = and(_T_1019, _T_1016) @[dec_dec_ctl.scala 17:17] + node _T_1021 = and(_T_1020, _T_1017) @[dec_dec_ctl.scala 17:17] + node _T_1022 = or(_T_1012, _T_1021) @[dec_dec_ctl.scala 96:63] + io.out.csr_clr <= _T_1022 @[dec_dec_ctl.scala 95:18] + node _T_1023 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34] + node _T_1024 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1026 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1027 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1028 = and(_T_1023, _T_1025) @[dec_dec_ctl.scala 17:17] + node _T_1029 = and(_T_1028, _T_1026) @[dec_dec_ctl.scala 17:17] + node _T_1030 = and(_T_1029, _T_1027) @[dec_dec_ctl.scala 17:17] + node _T_1031 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34] + node _T_1032 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1033 = eq(_T_1032, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1034 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1035 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1036 = and(_T_1031, _T_1033) @[dec_dec_ctl.scala 17:17] + node _T_1037 = and(_T_1036, _T_1034) @[dec_dec_ctl.scala 17:17] + node _T_1038 = and(_T_1037, _T_1035) @[dec_dec_ctl.scala 17:17] + node _T_1039 = or(_T_1030, _T_1038) @[dec_dec_ctl.scala 98:47] + node _T_1040 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34] + node _T_1041 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1042 = eq(_T_1041, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1043 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1044 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1045 = and(_T_1040, _T_1042) @[dec_dec_ctl.scala 17:17] + node _T_1046 = and(_T_1045, _T_1043) @[dec_dec_ctl.scala 17:17] + node _T_1047 = and(_T_1046, _T_1044) @[dec_dec_ctl.scala 17:17] + node _T_1048 = or(_T_1039, _T_1047) @[dec_dec_ctl.scala 98:75] + node _T_1049 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34] + node _T_1050 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1051 = eq(_T_1050, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1052 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1053 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1054 = and(_T_1049, _T_1051) @[dec_dec_ctl.scala 17:17] + node _T_1055 = and(_T_1054, _T_1052) @[dec_dec_ctl.scala 17:17] + node _T_1056 = and(_T_1055, _T_1053) @[dec_dec_ctl.scala 17:17] + node _T_1057 = or(_T_1048, _T_1056) @[dec_dec_ctl.scala 98:103] + node _T_1058 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34] + node _T_1059 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1060 = eq(_T_1059, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1061 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1062 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1063 = and(_T_1058, _T_1060) @[dec_dec_ctl.scala 17:17] + node _T_1064 = and(_T_1063, _T_1061) @[dec_dec_ctl.scala 17:17] + node _T_1065 = and(_T_1064, _T_1062) @[dec_dec_ctl.scala 17:17] + node _T_1066 = or(_T_1057, _T_1065) @[dec_dec_ctl.scala 99:31] + io.out.csr_set <= _T_1066 @[dec_dec_ctl.scala 98:18] + node _T_1067 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1068 = eq(_T_1067, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1069 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1070 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1071 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1072 = and(_T_1068, _T_1069) @[dec_dec_ctl.scala 17:17] + node _T_1073 = and(_T_1072, _T_1070) @[dec_dec_ctl.scala 17:17] + node _T_1074 = and(_T_1073, _T_1071) @[dec_dec_ctl.scala 17:17] + io.out.csr_write <= _T_1074 @[dec_dec_ctl.scala 101:20] + node _T_1075 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1076 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1077 = eq(_T_1076, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1078 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1079 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1080 = and(_T_1075, _T_1077) @[dec_dec_ctl.scala 17:17] + node _T_1081 = and(_T_1080, _T_1078) @[dec_dec_ctl.scala 17:17] + node _T_1082 = and(_T_1081, _T_1079) @[dec_dec_ctl.scala 17:17] + node _T_1083 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34] + node _T_1084 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1085 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1086 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1087 = and(_T_1083, _T_1084) @[dec_dec_ctl.scala 17:17] + node _T_1088 = and(_T_1087, _T_1085) @[dec_dec_ctl.scala 17:17] + node _T_1089 = and(_T_1088, _T_1086) @[dec_dec_ctl.scala 17:17] + node _T_1090 = or(_T_1082, _T_1089) @[dec_dec_ctl.scala 103:47] + node _T_1091 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34] + node _T_1092 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1093 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1094 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1095 = and(_T_1091, _T_1092) @[dec_dec_ctl.scala 17:17] + node _T_1096 = and(_T_1095, _T_1093) @[dec_dec_ctl.scala 17:17] + node _T_1097 = and(_T_1096, _T_1094) @[dec_dec_ctl.scala 17:17] + node _T_1098 = or(_T_1090, _T_1097) @[dec_dec_ctl.scala 103:74] + node _T_1099 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34] + node _T_1100 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1101 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1102 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1103 = and(_T_1099, _T_1100) @[dec_dec_ctl.scala 17:17] + node _T_1104 = and(_T_1103, _T_1101) @[dec_dec_ctl.scala 17:17] + node _T_1105 = and(_T_1104, _T_1102) @[dec_dec_ctl.scala 17:17] + node _T_1106 = or(_T_1098, _T_1105) @[dec_dec_ctl.scala 103:101] + node _T_1107 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34] + node _T_1108 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1109 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1110 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1111 = and(_T_1107, _T_1108) @[dec_dec_ctl.scala 17:17] + node _T_1112 = and(_T_1111, _T_1109) @[dec_dec_ctl.scala 17:17] + node _T_1113 = and(_T_1112, _T_1110) @[dec_dec_ctl.scala 17:17] + node _T_1114 = or(_T_1106, _T_1113) @[dec_dec_ctl.scala 104:30] + node _T_1115 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34] + node _T_1116 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1117 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1118 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1119 = and(_T_1115, _T_1116) @[dec_dec_ctl.scala 17:17] + node _T_1120 = and(_T_1119, _T_1117) @[dec_dec_ctl.scala 17:17] + node _T_1121 = and(_T_1120, _T_1118) @[dec_dec_ctl.scala 17:17] + node _T_1122 = or(_T_1114, _T_1121) @[dec_dec_ctl.scala 104:57] + io.out.csr_imm <= _T_1122 @[dec_dec_ctl.scala 103:18] + node _T_1123 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1124 = eq(_T_1123, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1125 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_1126 = and(_T_1124, _T_1125) @[dec_dec_ctl.scala 17:17] + node _T_1127 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1129 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34] + node _T_1130 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1131 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1132 = and(_T_1128, _T_1129) @[dec_dec_ctl.scala 17:17] + node _T_1133 = and(_T_1132, _T_1130) @[dec_dec_ctl.scala 17:17] + node _T_1134 = and(_T_1133, _T_1131) @[dec_dec_ctl.scala 17:17] + node _T_1135 = or(_T_1126, _T_1134) @[dec_dec_ctl.scala 106:41] + node _T_1136 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1137 = eq(_T_1136, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1138 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34] + node _T_1139 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1140 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1141 = and(_T_1137, _T_1138) @[dec_dec_ctl.scala 17:17] + node _T_1142 = and(_T_1141, _T_1139) @[dec_dec_ctl.scala 17:17] + node _T_1143 = and(_T_1142, _T_1140) @[dec_dec_ctl.scala 17:17] + node _T_1144 = or(_T_1135, _T_1143) @[dec_dec_ctl.scala 106:68] + node _T_1145 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1146 = eq(_T_1145, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1147 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34] + node _T_1148 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1149 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1150 = and(_T_1146, _T_1147) @[dec_dec_ctl.scala 17:17] + node _T_1151 = and(_T_1150, _T_1148) @[dec_dec_ctl.scala 17:17] + node _T_1152 = and(_T_1151, _T_1149) @[dec_dec_ctl.scala 17:17] + node _T_1153 = or(_T_1144, _T_1152) @[dec_dec_ctl.scala 106:95] + node _T_1154 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1155 = eq(_T_1154, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1156 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34] + node _T_1157 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1158 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1159 = and(_T_1155, _T_1156) @[dec_dec_ctl.scala 17:17] + node _T_1160 = and(_T_1159, _T_1157) @[dec_dec_ctl.scala 17:17] + node _T_1161 = and(_T_1160, _T_1158) @[dec_dec_ctl.scala 17:17] + node _T_1162 = or(_T_1153, _T_1161) @[dec_dec_ctl.scala 107:30] + node _T_1163 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1164 = eq(_T_1163, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1165 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34] + node _T_1166 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1167 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1168 = and(_T_1164, _T_1165) @[dec_dec_ctl.scala 17:17] + node _T_1169 = and(_T_1168, _T_1166) @[dec_dec_ctl.scala 17:17] + node _T_1170 = and(_T_1169, _T_1167) @[dec_dec_ctl.scala 17:17] + node _T_1171 = or(_T_1162, _T_1170) @[dec_dec_ctl.scala 107:58] + node _T_1172 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34] + node _T_1173 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1174 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1175 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1176 = and(_T_1172, _T_1173) @[dec_dec_ctl.scala 17:17] + node _T_1177 = and(_T_1176, _T_1174) @[dec_dec_ctl.scala 17:17] + node _T_1178 = and(_T_1177, _T_1175) @[dec_dec_ctl.scala 17:17] + node _T_1179 = or(_T_1171, _T_1178) @[dec_dec_ctl.scala 107:86] + node _T_1180 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34] + node _T_1181 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1182 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1183 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1184 = and(_T_1180, _T_1181) @[dec_dec_ctl.scala 17:17] + node _T_1185 = and(_T_1184, _T_1182) @[dec_dec_ctl.scala 17:17] + node _T_1186 = and(_T_1185, _T_1183) @[dec_dec_ctl.scala 17:17] + node _T_1187 = or(_T_1179, _T_1186) @[dec_dec_ctl.scala 108:30] + node _T_1188 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34] + node _T_1189 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1190 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1191 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1192 = and(_T_1188, _T_1189) @[dec_dec_ctl.scala 17:17] + node _T_1193 = and(_T_1192, _T_1190) @[dec_dec_ctl.scala 17:17] + node _T_1194 = and(_T_1193, _T_1191) @[dec_dec_ctl.scala 17:17] + node _T_1195 = or(_T_1187, _T_1194) @[dec_dec_ctl.scala 108:57] + node _T_1196 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34] + node _T_1197 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1198 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1199 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1200 = and(_T_1196, _T_1197) @[dec_dec_ctl.scala 17:17] + node _T_1201 = and(_T_1200, _T_1198) @[dec_dec_ctl.scala 17:17] + node _T_1202 = and(_T_1201, _T_1199) @[dec_dec_ctl.scala 17:17] + node _T_1203 = or(_T_1195, _T_1202) @[dec_dec_ctl.scala 108:84] + node _T_1204 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34] + node _T_1205 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1206 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1207 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1208 = and(_T_1204, _T_1205) @[dec_dec_ctl.scala 17:17] + node _T_1209 = and(_T_1208, _T_1206) @[dec_dec_ctl.scala 17:17] + node _T_1210 = and(_T_1209, _T_1207) @[dec_dec_ctl.scala 17:17] + node _T_1211 = or(_T_1203, _T_1210) @[dec_dec_ctl.scala 109:30] + io.out.presync <= _T_1211 @[dec_dec_ctl.scala 106:18] + node _T_1212 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1213 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1215 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_1216 = and(_T_1212, _T_1214) @[dec_dec_ctl.scala 17:17] + node _T_1217 = and(_T_1216, _T_1215) @[dec_dec_ctl.scala 17:17] + node _T_1218 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_1219 = eq(_T_1218, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1220 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1221 = eq(_T_1220, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1222 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1223 = eq(_T_1222, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1224 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1225 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1226 = and(_T_1219, _T_1221) @[dec_dec_ctl.scala 17:17] + node _T_1227 = and(_T_1226, _T_1223) @[dec_dec_ctl.scala 17:17] + node _T_1228 = and(_T_1227, _T_1224) @[dec_dec_ctl.scala 17:17] + node _T_1229 = and(_T_1228, _T_1225) @[dec_dec_ctl.scala 17:17] + node _T_1230 = or(_T_1217, _T_1229) @[dec_dec_ctl.scala 111:45] + node _T_1231 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1233 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34] + node _T_1234 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1235 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1236 = and(_T_1232, _T_1233) @[dec_dec_ctl.scala 17:17] + node _T_1237 = and(_T_1236, _T_1234) @[dec_dec_ctl.scala 17:17] + node _T_1238 = and(_T_1237, _T_1235) @[dec_dec_ctl.scala 17:17] + node _T_1239 = or(_T_1230, _T_1238) @[dec_dec_ctl.scala 111:78] + node _T_1240 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1241 = eq(_T_1240, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1242 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34] + node _T_1243 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1244 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1245 = and(_T_1241, _T_1242) @[dec_dec_ctl.scala 17:17] + node _T_1246 = and(_T_1245, _T_1243) @[dec_dec_ctl.scala 17:17] + node _T_1247 = and(_T_1246, _T_1244) @[dec_dec_ctl.scala 17:17] + node _T_1248 = or(_T_1239, _T_1247) @[dec_dec_ctl.scala 112:30] + node _T_1249 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1250 = eq(_T_1249, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1251 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34] + node _T_1252 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1253 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1254 = and(_T_1250, _T_1251) @[dec_dec_ctl.scala 17:17] + node _T_1255 = and(_T_1254, _T_1252) @[dec_dec_ctl.scala 17:17] + node _T_1256 = and(_T_1255, _T_1253) @[dec_dec_ctl.scala 17:17] + node _T_1257 = or(_T_1248, _T_1256) @[dec_dec_ctl.scala 112:57] + node _T_1258 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1259 = eq(_T_1258, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1260 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34] + node _T_1261 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1262 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1263 = and(_T_1259, _T_1260) @[dec_dec_ctl.scala 17:17] + node _T_1264 = and(_T_1263, _T_1261) @[dec_dec_ctl.scala 17:17] + node _T_1265 = and(_T_1264, _T_1262) @[dec_dec_ctl.scala 17:17] + node _T_1266 = or(_T_1257, _T_1265) @[dec_dec_ctl.scala 112:84] + node _T_1267 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1268 = eq(_T_1267, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1269 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34] + node _T_1270 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1271 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1272 = and(_T_1268, _T_1269) @[dec_dec_ctl.scala 17:17] + node _T_1273 = and(_T_1272, _T_1270) @[dec_dec_ctl.scala 17:17] + node _T_1274 = and(_T_1273, _T_1271) @[dec_dec_ctl.scala 17:17] + node _T_1275 = or(_T_1266, _T_1274) @[dec_dec_ctl.scala 112:112] + node _T_1276 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34] + node _T_1277 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1278 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1279 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1280 = and(_T_1276, _T_1277) @[dec_dec_ctl.scala 17:17] + node _T_1281 = and(_T_1280, _T_1278) @[dec_dec_ctl.scala 17:17] + node _T_1282 = and(_T_1281, _T_1279) @[dec_dec_ctl.scala 17:17] + node _T_1283 = or(_T_1275, _T_1282) @[dec_dec_ctl.scala 113:31] + node _T_1284 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34] + node _T_1285 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1286 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1287 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1288 = and(_T_1284, _T_1285) @[dec_dec_ctl.scala 17:17] + node _T_1289 = and(_T_1288, _T_1286) @[dec_dec_ctl.scala 17:17] + node _T_1290 = and(_T_1289, _T_1287) @[dec_dec_ctl.scala 17:17] + node _T_1291 = or(_T_1283, _T_1290) @[dec_dec_ctl.scala 113:58] + node _T_1292 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34] + node _T_1293 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1294 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1295 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1296 = and(_T_1292, _T_1293) @[dec_dec_ctl.scala 17:17] + node _T_1297 = and(_T_1296, _T_1294) @[dec_dec_ctl.scala 17:17] + node _T_1298 = and(_T_1297, _T_1295) @[dec_dec_ctl.scala 17:17] + node _T_1299 = or(_T_1291, _T_1298) @[dec_dec_ctl.scala 113:85] + node _T_1300 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34] + node _T_1301 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1302 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1303 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1304 = and(_T_1300, _T_1301) @[dec_dec_ctl.scala 17:17] + node _T_1305 = and(_T_1304, _T_1302) @[dec_dec_ctl.scala 17:17] + node _T_1306 = and(_T_1305, _T_1303) @[dec_dec_ctl.scala 17:17] + node _T_1307 = or(_T_1299, _T_1306) @[dec_dec_ctl.scala 113:112] + node _T_1308 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34] + node _T_1309 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1310 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1311 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1312 = and(_T_1308, _T_1309) @[dec_dec_ctl.scala 17:17] + node _T_1313 = and(_T_1312, _T_1310) @[dec_dec_ctl.scala 17:17] + node _T_1314 = and(_T_1313, _T_1311) @[dec_dec_ctl.scala 17:17] + node _T_1315 = or(_T_1307, _T_1314) @[dec_dec_ctl.scala 114:30] + io.out.postsync <= _T_1315 @[dec_dec_ctl.scala 111:19] + node _T_1316 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_1317 = eq(_T_1316, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1318 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_1319 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1320 = eq(_T_1319, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1321 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1322 = eq(_T_1321, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1323 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1324 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1325 = and(_T_1317, _T_1318) @[dec_dec_ctl.scala 17:17] + node _T_1326 = and(_T_1325, _T_1320) @[dec_dec_ctl.scala 17:17] + node _T_1327 = and(_T_1326, _T_1322) @[dec_dec_ctl.scala 17:17] + node _T_1328 = and(_T_1327, _T_1323) @[dec_dec_ctl.scala 17:17] + node _T_1329 = and(_T_1328, _T_1324) @[dec_dec_ctl.scala 17:17] + io.out.ebreak <= _T_1329 @[dec_dec_ctl.scala 116:17] + node _T_1330 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_1331 = eq(_T_1330, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1332 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1334 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1336 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1337 = eq(_T_1336, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1338 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1339 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1340 = and(_T_1331, _T_1333) @[dec_dec_ctl.scala 17:17] + node _T_1341 = and(_T_1340, _T_1335) @[dec_dec_ctl.scala 17:17] + node _T_1342 = and(_T_1341, _T_1337) @[dec_dec_ctl.scala 17:17] + node _T_1343 = and(_T_1342, _T_1338) @[dec_dec_ctl.scala 17:17] + node _T_1344 = and(_T_1343, _T_1339) @[dec_dec_ctl.scala 17:17] + io.out.ecall <= _T_1344 @[dec_dec_ctl.scala 118:16] + node _T_1345 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1346 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1347 = eq(_T_1346, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1348 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1349 = eq(_T_1348, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1350 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1351 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1352 = and(_T_1345, _T_1347) @[dec_dec_ctl.scala 17:17] + node _T_1353 = and(_T_1352, _T_1349) @[dec_dec_ctl.scala 17:17] + node _T_1354 = and(_T_1353, _T_1350) @[dec_dec_ctl.scala 17:17] + node _T_1355 = and(_T_1354, _T_1351) @[dec_dec_ctl.scala 17:17] + io.out.mret <= _T_1355 @[dec_dec_ctl.scala 120:15] + node _T_1356 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_1357 = eq(_T_1356, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1358 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1359 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_1360 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_1361 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1362 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1363 = eq(_T_1362, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1364 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1365 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1366 = eq(_T_1365, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1367 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1368 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1369 = eq(_T_1368, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1370 = and(_T_1357, _T_1358) @[dec_dec_ctl.scala 17:17] + node _T_1371 = and(_T_1370, _T_1359) @[dec_dec_ctl.scala 17:17] + node _T_1372 = and(_T_1371, _T_1360) @[dec_dec_ctl.scala 17:17] + node _T_1373 = and(_T_1372, _T_1361) @[dec_dec_ctl.scala 17:17] + node _T_1374 = and(_T_1373, _T_1363) @[dec_dec_ctl.scala 17:17] + node _T_1375 = and(_T_1374, _T_1364) @[dec_dec_ctl.scala 17:17] + node _T_1376 = and(_T_1375, _T_1366) @[dec_dec_ctl.scala 17:17] + node _T_1377 = and(_T_1376, _T_1367) @[dec_dec_ctl.scala 17:17] + node _T_1378 = and(_T_1377, _T_1369) @[dec_dec_ctl.scala 17:17] + node _T_1379 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1380 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1381 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_1382 = eq(_T_1381, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1383 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_1384 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1385 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1386 = eq(_T_1385, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1387 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1388 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1389 = eq(_T_1388, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1390 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1391 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1392 = eq(_T_1391, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1393 = and(_T_1379, _T_1380) @[dec_dec_ctl.scala 17:17] + node _T_1394 = and(_T_1393, _T_1382) @[dec_dec_ctl.scala 17:17] + node _T_1395 = and(_T_1394, _T_1383) @[dec_dec_ctl.scala 17:17] + node _T_1396 = and(_T_1395, _T_1384) @[dec_dec_ctl.scala 17:17] + node _T_1397 = and(_T_1396, _T_1386) @[dec_dec_ctl.scala 17:17] + node _T_1398 = and(_T_1397, _T_1387) @[dec_dec_ctl.scala 17:17] + node _T_1399 = and(_T_1398, _T_1389) @[dec_dec_ctl.scala 17:17] + node _T_1400 = and(_T_1399, _T_1390) @[dec_dec_ctl.scala 17:17] + node _T_1401 = and(_T_1400, _T_1392) @[dec_dec_ctl.scala 17:17] + node _T_1402 = or(_T_1378, _T_1401) @[dec_dec_ctl.scala 122:63] + node _T_1403 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1404 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1405 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_1406 = eq(_T_1405, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1407 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_1408 = eq(_T_1407, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1409 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1410 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1411 = eq(_T_1410, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1412 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1413 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1414 = eq(_T_1413, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1415 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1416 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1417 = eq(_T_1416, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1418 = and(_T_1403, _T_1404) @[dec_dec_ctl.scala 17:17] + node _T_1419 = and(_T_1418, _T_1406) @[dec_dec_ctl.scala 17:17] + node _T_1420 = and(_T_1419, _T_1408) @[dec_dec_ctl.scala 17:17] + node _T_1421 = and(_T_1420, _T_1409) @[dec_dec_ctl.scala 17:17] + node _T_1422 = and(_T_1421, _T_1411) @[dec_dec_ctl.scala 17:17] + node _T_1423 = and(_T_1422, _T_1412) @[dec_dec_ctl.scala 17:17] + node _T_1424 = and(_T_1423, _T_1414) @[dec_dec_ctl.scala 17:17] + node _T_1425 = and(_T_1424, _T_1415) @[dec_dec_ctl.scala 17:17] + node _T_1426 = and(_T_1425, _T_1417) @[dec_dec_ctl.scala 17:17] + node _T_1427 = or(_T_1402, _T_1426) @[dec_dec_ctl.scala 122:111] + node _T_1428 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1429 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_1430 = eq(_T_1429, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1431 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1432 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1434 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1435 = eq(_T_1434, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1436 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1437 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1438 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1440 = and(_T_1428, _T_1430) @[dec_dec_ctl.scala 17:17] + node _T_1441 = and(_T_1440, _T_1431) @[dec_dec_ctl.scala 17:17] + node _T_1442 = and(_T_1441, _T_1433) @[dec_dec_ctl.scala 17:17] + node _T_1443 = and(_T_1442, _T_1435) @[dec_dec_ctl.scala 17:17] + node _T_1444 = and(_T_1443, _T_1436) @[dec_dec_ctl.scala 17:17] + node _T_1445 = and(_T_1444, _T_1437) @[dec_dec_ctl.scala 17:17] + node _T_1446 = and(_T_1445, _T_1439) @[dec_dec_ctl.scala 17:17] + node _T_1447 = or(_T_1427, _T_1446) @[dec_dec_ctl.scala 123:52] + node _T_1448 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1449 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1450 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1451 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1452 = eq(_T_1451, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1453 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1454 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1455 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1456 = eq(_T_1455, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1457 = and(_T_1448, _T_1449) @[dec_dec_ctl.scala 17:17] + node _T_1458 = and(_T_1457, _T_1450) @[dec_dec_ctl.scala 17:17] + node _T_1459 = and(_T_1458, _T_1452) @[dec_dec_ctl.scala 17:17] + node _T_1460 = and(_T_1459, _T_1453) @[dec_dec_ctl.scala 17:17] + node _T_1461 = and(_T_1460, _T_1454) @[dec_dec_ctl.scala 17:17] + node _T_1462 = and(_T_1461, _T_1456) @[dec_dec_ctl.scala 17:17] + node _T_1463 = or(_T_1447, _T_1462) @[dec_dec_ctl.scala 123:93] + node _T_1464 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1465 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1466 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_1467 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1469 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1470 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1471 = eq(_T_1470, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1472 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1473 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1474 = eq(_T_1473, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1475 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1476 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1477 = eq(_T_1476, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1478 = and(_T_1464, _T_1465) @[dec_dec_ctl.scala 17:17] + node _T_1479 = and(_T_1478, _T_1466) @[dec_dec_ctl.scala 17:17] + node _T_1480 = and(_T_1479, _T_1468) @[dec_dec_ctl.scala 17:17] + node _T_1481 = and(_T_1480, _T_1469) @[dec_dec_ctl.scala 17:17] + node _T_1482 = and(_T_1481, _T_1471) @[dec_dec_ctl.scala 17:17] + node _T_1483 = and(_T_1482, _T_1472) @[dec_dec_ctl.scala 17:17] + node _T_1484 = and(_T_1483, _T_1474) @[dec_dec_ctl.scala 17:17] + node _T_1485 = and(_T_1484, _T_1475) @[dec_dec_ctl.scala 17:17] + node _T_1486 = and(_T_1485, _T_1477) @[dec_dec_ctl.scala 17:17] + node _T_1487 = or(_T_1463, _T_1486) @[dec_dec_ctl.scala 124:39] + node _T_1488 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1489 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1490 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1492 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_1493 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1494 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1495 = eq(_T_1494, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1496 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1497 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1498 = eq(_T_1497, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1499 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1500 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1501 = eq(_T_1500, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1502 = and(_T_1488, _T_1489) @[dec_dec_ctl.scala 17:17] + node _T_1503 = and(_T_1502, _T_1491) @[dec_dec_ctl.scala 17:17] + node _T_1504 = and(_T_1503, _T_1492) @[dec_dec_ctl.scala 17:17] + node _T_1505 = and(_T_1504, _T_1493) @[dec_dec_ctl.scala 17:17] + node _T_1506 = and(_T_1505, _T_1495) @[dec_dec_ctl.scala 17:17] + node _T_1507 = and(_T_1506, _T_1496) @[dec_dec_ctl.scala 17:17] + node _T_1508 = and(_T_1507, _T_1498) @[dec_dec_ctl.scala 17:17] + node _T_1509 = and(_T_1508, _T_1499) @[dec_dec_ctl.scala 17:17] + node _T_1510 = and(_T_1509, _T_1501) @[dec_dec_ctl.scala 17:17] + node _T_1511 = or(_T_1487, _T_1510) @[dec_dec_ctl.scala 124:87] + node _T_1512 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1513 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1514 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1516 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_1517 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1518 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1520 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1521 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1522 = eq(_T_1521, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1523 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1524 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1525 = eq(_T_1524, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1526 = and(_T_1512, _T_1513) @[dec_dec_ctl.scala 17:17] + node _T_1527 = and(_T_1526, _T_1515) @[dec_dec_ctl.scala 17:17] + node _T_1528 = and(_T_1527, _T_1516) @[dec_dec_ctl.scala 17:17] + node _T_1529 = and(_T_1528, _T_1517) @[dec_dec_ctl.scala 17:17] + node _T_1530 = and(_T_1529, _T_1519) @[dec_dec_ctl.scala 17:17] + node _T_1531 = and(_T_1530, _T_1520) @[dec_dec_ctl.scala 17:17] + node _T_1532 = and(_T_1531, _T_1522) @[dec_dec_ctl.scala 17:17] + node _T_1533 = and(_T_1532, _T_1523) @[dec_dec_ctl.scala 17:17] + node _T_1534 = and(_T_1533, _T_1525) @[dec_dec_ctl.scala 17:17] + node _T_1535 = or(_T_1511, _T_1534) @[dec_dec_ctl.scala 125:51] + node _T_1536 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1537 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1538 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1539 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_1540 = eq(_T_1539, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1541 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1542 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1543 = eq(_T_1542, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1544 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1545 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1546 = eq(_T_1545, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1547 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1548 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1549 = eq(_T_1548, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1550 = and(_T_1536, _T_1537) @[dec_dec_ctl.scala 17:17] + node _T_1551 = and(_T_1550, _T_1538) @[dec_dec_ctl.scala 17:17] + node _T_1552 = and(_T_1551, _T_1540) @[dec_dec_ctl.scala 17:17] + node _T_1553 = and(_T_1552, _T_1541) @[dec_dec_ctl.scala 17:17] + node _T_1554 = and(_T_1553, _T_1543) @[dec_dec_ctl.scala 17:17] + node _T_1555 = and(_T_1554, _T_1544) @[dec_dec_ctl.scala 17:17] + node _T_1556 = and(_T_1555, _T_1546) @[dec_dec_ctl.scala 17:17] + node _T_1557 = and(_T_1556, _T_1547) @[dec_dec_ctl.scala 17:17] + node _T_1558 = and(_T_1557, _T_1549) @[dec_dec_ctl.scala 17:17] + node _T_1559 = or(_T_1535, _T_1558) @[dec_dec_ctl.scala 125:99] + node _T_1560 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_1561 = eq(_T_1560, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1562 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1563 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_1564 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1565 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1566 = eq(_T_1565, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1567 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1568 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1569 = eq(_T_1568, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1570 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1571 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1573 = and(_T_1561, _T_1562) @[dec_dec_ctl.scala 17:17] + node _T_1574 = and(_T_1573, _T_1563) @[dec_dec_ctl.scala 17:17] + node _T_1575 = and(_T_1574, _T_1564) @[dec_dec_ctl.scala 17:17] + node _T_1576 = and(_T_1575, _T_1566) @[dec_dec_ctl.scala 17:17] + node _T_1577 = and(_T_1576, _T_1567) @[dec_dec_ctl.scala 17:17] + node _T_1578 = and(_T_1577, _T_1569) @[dec_dec_ctl.scala 17:17] + node _T_1579 = and(_T_1578, _T_1570) @[dec_dec_ctl.scala 17:17] + node _T_1580 = and(_T_1579, _T_1572) @[dec_dec_ctl.scala 17:17] + node _T_1581 = or(_T_1559, _T_1580) @[dec_dec_ctl.scala 126:51] + node _T_1582 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_1583 = eq(_T_1582, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1584 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_1585 = eq(_T_1584, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1586 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1587 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_1588 = eq(_T_1587, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1589 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1590 = eq(_T_1589, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1591 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1592 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1593 = eq(_T_1592, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1594 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1595 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1596 = eq(_T_1595, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1597 = and(_T_1583, _T_1585) @[dec_dec_ctl.scala 17:17] + node _T_1598 = and(_T_1597, _T_1586) @[dec_dec_ctl.scala 17:17] + node _T_1599 = and(_T_1598, _T_1588) @[dec_dec_ctl.scala 17:17] + node _T_1600 = and(_T_1599, _T_1590) @[dec_dec_ctl.scala 17:17] + node _T_1601 = and(_T_1600, _T_1591) @[dec_dec_ctl.scala 17:17] + node _T_1602 = and(_T_1601, _T_1593) @[dec_dec_ctl.scala 17:17] + node _T_1603 = and(_T_1602, _T_1594) @[dec_dec_ctl.scala 17:17] + node _T_1604 = and(_T_1603, _T_1596) @[dec_dec_ctl.scala 17:17] + node _T_1605 = or(_T_1581, _T_1604) @[dec_dec_ctl.scala 126:96] + node _T_1606 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1607 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1608 = eq(_T_1607, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1609 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1610 = eq(_T_1609, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1611 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1612 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1613 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1614 = eq(_T_1613, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1615 = and(_T_1606, _T_1608) @[dec_dec_ctl.scala 17:17] + node _T_1616 = and(_T_1615, _T_1610) @[dec_dec_ctl.scala 17:17] + node _T_1617 = and(_T_1616, _T_1611) @[dec_dec_ctl.scala 17:17] + node _T_1618 = and(_T_1617, _T_1612) @[dec_dec_ctl.scala 17:17] + node _T_1619 = and(_T_1618, _T_1614) @[dec_dec_ctl.scala 17:17] + node _T_1620 = or(_T_1605, _T_1619) @[dec_dec_ctl.scala 127:50] + node _T_1621 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1622 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1623 = eq(_T_1622, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1624 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_1625 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1626 = eq(_T_1625, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1627 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1628 = eq(_T_1627, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1629 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1630 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1631 = eq(_T_1630, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1632 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1633 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1634 = eq(_T_1633, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1635 = and(_T_1621, _T_1623) @[dec_dec_ctl.scala 17:17] + node _T_1636 = and(_T_1635, _T_1624) @[dec_dec_ctl.scala 17:17] + node _T_1637 = and(_T_1636, _T_1626) @[dec_dec_ctl.scala 17:17] + node _T_1638 = and(_T_1637, _T_1628) @[dec_dec_ctl.scala 17:17] + node _T_1639 = and(_T_1638, _T_1629) @[dec_dec_ctl.scala 17:17] + node _T_1640 = and(_T_1639, _T_1631) @[dec_dec_ctl.scala 17:17] + node _T_1641 = and(_T_1640, _T_1632) @[dec_dec_ctl.scala 17:17] + node _T_1642 = and(_T_1641, _T_1634) @[dec_dec_ctl.scala 17:17] + node _T_1643 = or(_T_1620, _T_1642) @[dec_dec_ctl.scala 127:84] + node _T_1644 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1645 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1646 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1647 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1648 = eq(_T_1647, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1649 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1650 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1651 = eq(_T_1650, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1652 = and(_T_1644, _T_1645) @[dec_dec_ctl.scala 17:17] + node _T_1653 = and(_T_1652, _T_1646) @[dec_dec_ctl.scala 17:17] + node _T_1654 = and(_T_1653, _T_1648) @[dec_dec_ctl.scala 17:17] + node _T_1655 = and(_T_1654, _T_1649) @[dec_dec_ctl.scala 17:17] + node _T_1656 = and(_T_1655, _T_1651) @[dec_dec_ctl.scala 17:17] + node _T_1657 = or(_T_1643, _T_1656) @[dec_dec_ctl.scala 128:49] + io.out.mul <= _T_1657 @[dec_dec_ctl.scala 122:14] + node _T_1658 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1659 = eq(_T_1658, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1660 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1661 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1662 = eq(_T_1661, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1663 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1664 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1665 = eq(_T_1664, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1666 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1667 = eq(_T_1666, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1668 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1669 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1670 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1671 = eq(_T_1670, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1672 = and(_T_1659, _T_1660) @[dec_dec_ctl.scala 17:17] + node _T_1673 = and(_T_1672, _T_1662) @[dec_dec_ctl.scala 17:17] + node _T_1674 = and(_T_1673, _T_1663) @[dec_dec_ctl.scala 17:17] + node _T_1675 = and(_T_1674, _T_1665) @[dec_dec_ctl.scala 17:17] + node _T_1676 = and(_T_1675, _T_1667) @[dec_dec_ctl.scala 17:17] + node _T_1677 = and(_T_1676, _T_1668) @[dec_dec_ctl.scala 17:17] + node _T_1678 = and(_T_1677, _T_1669) @[dec_dec_ctl.scala 17:17] + node _T_1679 = and(_T_1678, _T_1671) @[dec_dec_ctl.scala 17:17] + node _T_1680 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1681 = eq(_T_1680, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1682 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1683 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1684 = eq(_T_1683, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1685 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1686 = eq(_T_1685, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1687 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1688 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1689 = eq(_T_1688, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1690 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1691 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1692 = eq(_T_1691, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1693 = and(_T_1681, _T_1682) @[dec_dec_ctl.scala 17:17] + node _T_1694 = and(_T_1693, _T_1684) @[dec_dec_ctl.scala 17:17] + node _T_1695 = and(_T_1694, _T_1686) @[dec_dec_ctl.scala 17:17] + node _T_1696 = and(_T_1695, _T_1687) @[dec_dec_ctl.scala 17:17] + node _T_1697 = and(_T_1696, _T_1689) @[dec_dec_ctl.scala 17:17] + node _T_1698 = and(_T_1697, _T_1690) @[dec_dec_ctl.scala 17:17] + node _T_1699 = and(_T_1698, _T_1692) @[dec_dec_ctl.scala 17:17] + node _T_1700 = or(_T_1679, _T_1699) @[dec_dec_ctl.scala 130:65] + io.out.rs1_sign <= _T_1700 @[dec_dec_ctl.scala 130:19] + node _T_1701 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1702 = eq(_T_1701, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1703 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1704 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1705 = eq(_T_1704, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1706 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1707 = eq(_T_1706, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1708 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1709 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1710 = eq(_T_1709, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1711 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1712 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1713 = eq(_T_1712, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1714 = and(_T_1702, _T_1703) @[dec_dec_ctl.scala 17:17] + node _T_1715 = and(_T_1714, _T_1705) @[dec_dec_ctl.scala 17:17] + node _T_1716 = and(_T_1715, _T_1707) @[dec_dec_ctl.scala 17:17] + node _T_1717 = and(_T_1716, _T_1708) @[dec_dec_ctl.scala 17:17] + node _T_1718 = and(_T_1717, _T_1710) @[dec_dec_ctl.scala 17:17] + node _T_1719 = and(_T_1718, _T_1711) @[dec_dec_ctl.scala 17:17] + node _T_1720 = and(_T_1719, _T_1713) @[dec_dec_ctl.scala 17:17] + io.out.rs2_sign <= _T_1720 @[dec_dec_ctl.scala 132:19] + node _T_1721 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1722 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1723 = eq(_T_1722, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1724 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1725 = eq(_T_1724, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1726 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1727 = eq(_T_1726, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1728 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1729 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1730 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1731 = eq(_T_1730, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1732 = and(_T_1721, _T_1723) @[dec_dec_ctl.scala 17:17] + node _T_1733 = and(_T_1732, _T_1725) @[dec_dec_ctl.scala 17:17] + node _T_1734 = and(_T_1733, _T_1727) @[dec_dec_ctl.scala 17:17] + node _T_1735 = and(_T_1734, _T_1728) @[dec_dec_ctl.scala 17:17] + node _T_1736 = and(_T_1735, _T_1729) @[dec_dec_ctl.scala 17:17] + node _T_1737 = and(_T_1736, _T_1731) @[dec_dec_ctl.scala 17:17] + io.out.low <= _T_1737 @[dec_dec_ctl.scala 134:14] + node _T_1738 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1739 = eq(_T_1738, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1740 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1741 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1742 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1743 = eq(_T_1742, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1744 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1745 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1746 = eq(_T_1745, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1747 = and(_T_1739, _T_1740) @[dec_dec_ctl.scala 17:17] + node _T_1748 = and(_T_1747, _T_1741) @[dec_dec_ctl.scala 17:17] + node _T_1749 = and(_T_1748, _T_1743) @[dec_dec_ctl.scala 17:17] + node _T_1750 = and(_T_1749, _T_1744) @[dec_dec_ctl.scala 17:17] + node _T_1751 = and(_T_1750, _T_1746) @[dec_dec_ctl.scala 17:17] + io.out.div <= _T_1751 @[dec_dec_ctl.scala 136:14] + node _T_1752 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1753 = eq(_T_1752, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1754 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1755 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1756 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1757 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1758 = eq(_T_1757, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1759 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1760 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1761 = eq(_T_1760, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1762 = and(_T_1753, _T_1754) @[dec_dec_ctl.scala 17:17] + node _T_1763 = and(_T_1762, _T_1755) @[dec_dec_ctl.scala 17:17] + node _T_1764 = and(_T_1763, _T_1756) @[dec_dec_ctl.scala 17:17] + node _T_1765 = and(_T_1764, _T_1758) @[dec_dec_ctl.scala 17:17] + node _T_1766 = and(_T_1765, _T_1759) @[dec_dec_ctl.scala 17:17] + node _T_1767 = and(_T_1766, _T_1761) @[dec_dec_ctl.scala 17:17] + io.out.rem <= _T_1767 @[dec_dec_ctl.scala 138:14] + node _T_1768 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1769 = eq(_T_1768, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1770 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_1771 = and(_T_1769, _T_1770) @[dec_dec_ctl.scala 17:17] + io.out.fence <= _T_1771 @[dec_dec_ctl.scala 140:16] + node _T_1772 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1773 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1774 = eq(_T_1773, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1775 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_1776 = and(_T_1772, _T_1774) @[dec_dec_ctl.scala 17:17] + node _T_1777 = and(_T_1776, _T_1775) @[dec_dec_ctl.scala 17:17] + io.out.fence_i <= _T_1777 @[dec_dec_ctl.scala 142:18] + node _T_1778 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1779 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1780 = eq(_T_1779, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1781 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_1782 = eq(_T_1781, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1783 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_1784 = eq(_T_1783, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1785 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_1786 = eq(_T_1785, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1787 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_1788 = eq(_T_1787, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1789 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1790 = eq(_T_1789, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1791 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1792 = eq(_T_1791, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1793 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1794 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1795 = eq(_T_1794, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1796 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1797 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1798 = eq(_T_1797, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1799 = and(_T_1778, _T_1780) @[dec_dec_ctl.scala 17:17] + node _T_1800 = and(_T_1799, _T_1782) @[dec_dec_ctl.scala 17:17] + node _T_1801 = and(_T_1800, _T_1784) @[dec_dec_ctl.scala 17:17] + node _T_1802 = and(_T_1801, _T_1786) @[dec_dec_ctl.scala 17:17] + node _T_1803 = and(_T_1802, _T_1788) @[dec_dec_ctl.scala 17:17] + node _T_1804 = and(_T_1803, _T_1790) @[dec_dec_ctl.scala 17:17] + node _T_1805 = and(_T_1804, _T_1792) @[dec_dec_ctl.scala 17:17] + node _T_1806 = and(_T_1805, _T_1793) @[dec_dec_ctl.scala 17:17] + node _T_1807 = and(_T_1806, _T_1795) @[dec_dec_ctl.scala 17:17] + node _T_1808 = and(_T_1807, _T_1796) @[dec_dec_ctl.scala 17:17] + node _T_1809 = and(_T_1808, _T_1798) @[dec_dec_ctl.scala 17:17] + io.out.clz <= _T_1809 @[dec_dec_ctl.scala 144:14] + node _T_1810 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1811 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1812 = eq(_T_1811, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1813 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_1814 = eq(_T_1813, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1815 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_1816 = eq(_T_1815, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1817 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_1818 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1819 = eq(_T_1818, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1820 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1821 = eq(_T_1820, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1822 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1823 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1824 = eq(_T_1823, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1825 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1826 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1827 = eq(_T_1826, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1828 = and(_T_1810, _T_1812) @[dec_dec_ctl.scala 17:17] + node _T_1829 = and(_T_1828, _T_1814) @[dec_dec_ctl.scala 17:17] + node _T_1830 = and(_T_1829, _T_1816) @[dec_dec_ctl.scala 17:17] + node _T_1831 = and(_T_1830, _T_1817) @[dec_dec_ctl.scala 17:17] + node _T_1832 = and(_T_1831, _T_1819) @[dec_dec_ctl.scala 17:17] + node _T_1833 = and(_T_1832, _T_1821) @[dec_dec_ctl.scala 17:17] + node _T_1834 = and(_T_1833, _T_1822) @[dec_dec_ctl.scala 17:17] + node _T_1835 = and(_T_1834, _T_1824) @[dec_dec_ctl.scala 17:17] + node _T_1836 = and(_T_1835, _T_1825) @[dec_dec_ctl.scala 17:17] + node _T_1837 = and(_T_1836, _T_1827) @[dec_dec_ctl.scala 17:17] + io.out.ctz <= _T_1837 @[dec_dec_ctl.scala 146:14] + node _T_1838 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1839 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1840 = eq(_T_1839, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1841 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_1842 = eq(_T_1841, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1843 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_1844 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1845 = eq(_T_1844, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1846 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1847 = eq(_T_1846, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1848 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1849 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1850 = eq(_T_1849, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1851 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1852 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1853 = eq(_T_1852, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1854 = and(_T_1838, _T_1840) @[dec_dec_ctl.scala 17:17] + node _T_1855 = and(_T_1854, _T_1842) @[dec_dec_ctl.scala 17:17] + node _T_1856 = and(_T_1855, _T_1843) @[dec_dec_ctl.scala 17:17] + node _T_1857 = and(_T_1856, _T_1845) @[dec_dec_ctl.scala 17:17] + node _T_1858 = and(_T_1857, _T_1847) @[dec_dec_ctl.scala 17:17] + node _T_1859 = and(_T_1858, _T_1848) @[dec_dec_ctl.scala 17:17] + node _T_1860 = and(_T_1859, _T_1850) @[dec_dec_ctl.scala 17:17] + node _T_1861 = and(_T_1860, _T_1851) @[dec_dec_ctl.scala 17:17] + node _T_1862 = and(_T_1861, _T_1853) @[dec_dec_ctl.scala 17:17] + io.out.pcnt <= _T_1862 @[dec_dec_ctl.scala 148:15] + node _T_1863 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1864 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1865 = eq(_T_1864, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1866 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_1867 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_1868 = eq(_T_1867, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1869 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1870 = eq(_T_1869, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1871 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1872 = eq(_T_1871, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1873 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1874 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1875 = eq(_T_1874, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1876 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1877 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1878 = eq(_T_1877, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1879 = and(_T_1863, _T_1865) @[dec_dec_ctl.scala 17:17] + node _T_1880 = and(_T_1879, _T_1866) @[dec_dec_ctl.scala 17:17] + node _T_1881 = and(_T_1880, _T_1868) @[dec_dec_ctl.scala 17:17] + node _T_1882 = and(_T_1881, _T_1870) @[dec_dec_ctl.scala 17:17] + node _T_1883 = and(_T_1882, _T_1872) @[dec_dec_ctl.scala 17:17] + node _T_1884 = and(_T_1883, _T_1873) @[dec_dec_ctl.scala 17:17] + node _T_1885 = and(_T_1884, _T_1875) @[dec_dec_ctl.scala 17:17] + node _T_1886 = and(_T_1885, _T_1876) @[dec_dec_ctl.scala 17:17] + node _T_1887 = and(_T_1886, _T_1878) @[dec_dec_ctl.scala 17:17] + io.out.sext_b <= _T_1887 @[dec_dec_ctl.scala 150:17] + node _T_1888 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1889 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1890 = eq(_T_1889, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1891 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_1892 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_1893 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1895 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1896 = eq(_T_1895, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1897 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1898 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1899 = eq(_T_1898, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1900 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1901 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1902 = eq(_T_1901, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1903 = and(_T_1888, _T_1890) @[dec_dec_ctl.scala 17:17] + node _T_1904 = and(_T_1903, _T_1891) @[dec_dec_ctl.scala 17:17] + node _T_1905 = and(_T_1904, _T_1892) @[dec_dec_ctl.scala 17:17] + node _T_1906 = and(_T_1905, _T_1894) @[dec_dec_ctl.scala 17:17] + node _T_1907 = and(_T_1906, _T_1896) @[dec_dec_ctl.scala 17:17] + node _T_1908 = and(_T_1907, _T_1897) @[dec_dec_ctl.scala 17:17] + node _T_1909 = and(_T_1908, _T_1899) @[dec_dec_ctl.scala 17:17] + node _T_1910 = and(_T_1909, _T_1900) @[dec_dec_ctl.scala 17:17] + node _T_1911 = and(_T_1910, _T_1902) @[dec_dec_ctl.scala 17:17] + io.out.sext_h <= _T_1911 @[dec_dec_ctl.scala 152:17] + node _T_1912 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1914 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1915 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1916 = eq(_T_1915, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1917 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1918 = eq(_T_1917, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1919 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1920 = eq(_T_1919, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1921 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1922 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1923 = eq(_T_1922, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1924 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1925 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1926 = eq(_T_1925, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1927 = and(_T_1913, _T_1914) @[dec_dec_ctl.scala 17:17] + node _T_1928 = and(_T_1927, _T_1916) @[dec_dec_ctl.scala 17:17] + node _T_1929 = and(_T_1928, _T_1918) @[dec_dec_ctl.scala 17:17] + node _T_1930 = and(_T_1929, _T_1920) @[dec_dec_ctl.scala 17:17] + node _T_1931 = and(_T_1930, _T_1921) @[dec_dec_ctl.scala 17:17] + node _T_1932 = and(_T_1931, _T_1923) @[dec_dec_ctl.scala 17:17] + node _T_1933 = and(_T_1932, _T_1924) @[dec_dec_ctl.scala 17:17] + node _T_1934 = and(_T_1933, _T_1926) @[dec_dec_ctl.scala 17:17] + io.out.slo <= _T_1934 @[dec_dec_ctl.scala 154:14] + node _T_1935 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_1936 = eq(_T_1935, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1937 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1938 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1939 = eq(_T_1938, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1940 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1941 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1942 = eq(_T_1941, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1943 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1944 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1945 = eq(_T_1944, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1946 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1947 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1948 = eq(_T_1947, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1949 = and(_T_1936, _T_1937) @[dec_dec_ctl.scala 17:17] + node _T_1950 = and(_T_1949, _T_1939) @[dec_dec_ctl.scala 17:17] + node _T_1951 = and(_T_1950, _T_1940) @[dec_dec_ctl.scala 17:17] + node _T_1952 = and(_T_1951, _T_1942) @[dec_dec_ctl.scala 17:17] + node _T_1953 = and(_T_1952, _T_1943) @[dec_dec_ctl.scala 17:17] + node _T_1954 = and(_T_1953, _T_1945) @[dec_dec_ctl.scala 17:17] + node _T_1955 = and(_T_1954, _T_1946) @[dec_dec_ctl.scala 17:17] + node _T_1956 = and(_T_1955, _T_1948) @[dec_dec_ctl.scala 17:17] + io.out.sro <= _T_1956 @[dec_dec_ctl.scala 156:14] + node _T_1957 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1958 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1959 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1960 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1961 = eq(_T_1960, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1962 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1963 = eq(_T_1962, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1964 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1965 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1966 = eq(_T_1965, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1967 = and(_T_1957, _T_1958) @[dec_dec_ctl.scala 17:17] + node _T_1968 = and(_T_1967, _T_1959) @[dec_dec_ctl.scala 17:17] + node _T_1969 = and(_T_1968, _T_1961) @[dec_dec_ctl.scala 17:17] + node _T_1970 = and(_T_1969, _T_1963) @[dec_dec_ctl.scala 17:17] + node _T_1971 = and(_T_1970, _T_1964) @[dec_dec_ctl.scala 17:17] + node _T_1972 = and(_T_1971, _T_1966) @[dec_dec_ctl.scala 17:17] + io.out.min <= _T_1972 @[dec_dec_ctl.scala 158:14] + node _T_1973 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1974 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1975 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1976 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1977 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1978 = eq(_T_1977, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1979 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1980 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1981 = eq(_T_1980, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1982 = and(_T_1973, _T_1974) @[dec_dec_ctl.scala 17:17] + node _T_1983 = and(_T_1982, _T_1975) @[dec_dec_ctl.scala 17:17] + node _T_1984 = and(_T_1983, _T_1976) @[dec_dec_ctl.scala 17:17] + node _T_1985 = and(_T_1984, _T_1978) @[dec_dec_ctl.scala 17:17] + node _T_1986 = and(_T_1985, _T_1979) @[dec_dec_ctl.scala 17:17] + node _T_1987 = and(_T_1986, _T_1981) @[dec_dec_ctl.scala 17:17] + io.out.max <= _T_1987 @[dec_dec_ctl.scala 160:14] + node _T_1988 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_1989 = eq(_T_1988, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1990 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1991 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_1992 = eq(_T_1991, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1993 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1994 = eq(_T_1993, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1995 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1996 = eq(_T_1995, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1997 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1998 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1999 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2000 = eq(_T_1999, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2001 = and(_T_1989, _T_1990) @[dec_dec_ctl.scala 17:17] + node _T_2002 = and(_T_2001, _T_1992) @[dec_dec_ctl.scala 17:17] + node _T_2003 = and(_T_2002, _T_1994) @[dec_dec_ctl.scala 17:17] + node _T_2004 = and(_T_2003, _T_1996) @[dec_dec_ctl.scala 17:17] + node _T_2005 = and(_T_2004, _T_1997) @[dec_dec_ctl.scala 17:17] + node _T_2006 = and(_T_2005, _T_1998) @[dec_dec_ctl.scala 17:17] + node _T_2007 = and(_T_2006, _T_2000) @[dec_dec_ctl.scala 17:17] + io.out.pack <= _T_2007 @[dec_dec_ctl.scala 162:15] + node _T_2008 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2009 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2010 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2011 = eq(_T_2010, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2012 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2013 = eq(_T_2012, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2014 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2015 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2016 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2017 = eq(_T_2016, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2018 = and(_T_2008, _T_2009) @[dec_dec_ctl.scala 17:17] + node _T_2019 = and(_T_2018, _T_2011) @[dec_dec_ctl.scala 17:17] + node _T_2020 = and(_T_2019, _T_2013) @[dec_dec_ctl.scala 17:17] + node _T_2021 = and(_T_2020, _T_2014) @[dec_dec_ctl.scala 17:17] + node _T_2022 = and(_T_2021, _T_2015) @[dec_dec_ctl.scala 17:17] + node _T_2023 = and(_T_2022, _T_2017) @[dec_dec_ctl.scala 17:17] + io.out.packu <= _T_2023 @[dec_dec_ctl.scala 164:16] + node _T_2024 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2025 = eq(_T_2024, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2026 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2027 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2028 = eq(_T_2027, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2029 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2030 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2031 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2032 = eq(_T_2031, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2033 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2034 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2035 = eq(_T_2034, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2036 = and(_T_2025, _T_2026) @[dec_dec_ctl.scala 17:17] + node _T_2037 = and(_T_2036, _T_2028) @[dec_dec_ctl.scala 17:17] + node _T_2038 = and(_T_2037, _T_2029) @[dec_dec_ctl.scala 17:17] + node _T_2039 = and(_T_2038, _T_2030) @[dec_dec_ctl.scala 17:17] + node _T_2040 = and(_T_2039, _T_2032) @[dec_dec_ctl.scala 17:17] + node _T_2041 = and(_T_2040, _T_2033) @[dec_dec_ctl.scala 17:17] + node _T_2042 = and(_T_2041, _T_2035) @[dec_dec_ctl.scala 17:17] + io.out.packh <= _T_2042 @[dec_dec_ctl.scala 166:16] + node _T_2043 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2044 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2045 = eq(_T_2044, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2046 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2047 = eq(_T_2046, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2048 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2049 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2050 = eq(_T_2049, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2051 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2052 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2053 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2054 = eq(_T_2053, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2055 = and(_T_2043, _T_2045) @[dec_dec_ctl.scala 17:17] + node _T_2056 = and(_T_2055, _T_2047) @[dec_dec_ctl.scala 17:17] + node _T_2057 = and(_T_2056, _T_2048) @[dec_dec_ctl.scala 17:17] + node _T_2058 = and(_T_2057, _T_2050) @[dec_dec_ctl.scala 17:17] + node _T_2059 = and(_T_2058, _T_2051) @[dec_dec_ctl.scala 17:17] + node _T_2060 = and(_T_2059, _T_2052) @[dec_dec_ctl.scala 17:17] + node _T_2061 = and(_T_2060, _T_2054) @[dec_dec_ctl.scala 17:17] + io.out.rol <= _T_2061 @[dec_dec_ctl.scala 168:14] + node _T_2062 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2063 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2064 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2065 = eq(_T_2064, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2066 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2067 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2068 = eq(_T_2067, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2069 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2070 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2071 = eq(_T_2070, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2072 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2073 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2074 = eq(_T_2073, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2075 = and(_T_2062, _T_2063) @[dec_dec_ctl.scala 17:17] + node _T_2076 = and(_T_2075, _T_2065) @[dec_dec_ctl.scala 17:17] + node _T_2077 = and(_T_2076, _T_2066) @[dec_dec_ctl.scala 17:17] + node _T_2078 = and(_T_2077, _T_2068) @[dec_dec_ctl.scala 17:17] + node _T_2079 = and(_T_2078, _T_2069) @[dec_dec_ctl.scala 17:17] + node _T_2080 = and(_T_2079, _T_2071) @[dec_dec_ctl.scala 17:17] + node _T_2081 = and(_T_2080, _T_2072) @[dec_dec_ctl.scala 17:17] + node _T_2082 = and(_T_2081, _T_2074) @[dec_dec_ctl.scala 17:17] + io.out.ror <= _T_2082 @[dec_dec_ctl.scala 170:14] + node _T_2083 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2084 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2085 = eq(_T_2084, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2086 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_2087 = eq(_T_2086, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2088 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2089 = eq(_T_2088, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2090 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2091 = eq(_T_2090, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2092 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2093 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2094 = eq(_T_2093, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2095 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2096 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2097 = eq(_T_2096, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2098 = and(_T_2083, _T_2085) @[dec_dec_ctl.scala 17:17] + node _T_2099 = and(_T_2098, _T_2087) @[dec_dec_ctl.scala 17:17] + node _T_2100 = and(_T_2099, _T_2089) @[dec_dec_ctl.scala 17:17] + node _T_2101 = and(_T_2100, _T_2091) @[dec_dec_ctl.scala 17:17] + node _T_2102 = and(_T_2101, _T_2092) @[dec_dec_ctl.scala 17:17] + node _T_2103 = and(_T_2102, _T_2094) @[dec_dec_ctl.scala 17:17] + node _T_2104 = and(_T_2103, _T_2095) @[dec_dec_ctl.scala 17:17] + node _T_2105 = and(_T_2104, _T_2097) @[dec_dec_ctl.scala 17:17] + node _T_2106 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2107 = eq(_T_2106, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2108 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2109 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2110 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2111 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2112 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2113 = eq(_T_2112, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2114 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2115 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2116 = eq(_T_2115, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2117 = and(_T_2107, _T_2108) @[dec_dec_ctl.scala 17:17] + node _T_2118 = and(_T_2117, _T_2109) @[dec_dec_ctl.scala 17:17] + node _T_2119 = and(_T_2118, _T_2110) @[dec_dec_ctl.scala 17:17] + node _T_2120 = and(_T_2119, _T_2111) @[dec_dec_ctl.scala 17:17] + node _T_2121 = and(_T_2120, _T_2113) @[dec_dec_ctl.scala 17:17] + node _T_2122 = and(_T_2121, _T_2114) @[dec_dec_ctl.scala 17:17] + node _T_2123 = and(_T_2122, _T_2116) @[dec_dec_ctl.scala 17:17] + node _T_2124 = or(_T_2105, _T_2123) @[dec_dec_ctl.scala 172:62] + node _T_2125 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2126 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2127 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2128 = eq(_T_2127, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2129 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2130 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2131 = eq(_T_2130, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2132 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2133 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2134 = eq(_T_2133, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2135 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2136 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2137 = eq(_T_2136, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2138 = and(_T_2125, _T_2126) @[dec_dec_ctl.scala 17:17] + node _T_2139 = and(_T_2138, _T_2128) @[dec_dec_ctl.scala 17:17] + node _T_2140 = and(_T_2139, _T_2129) @[dec_dec_ctl.scala 17:17] + node _T_2141 = and(_T_2140, _T_2131) @[dec_dec_ctl.scala 17:17] + node _T_2142 = and(_T_2141, _T_2132) @[dec_dec_ctl.scala 17:17] + node _T_2143 = and(_T_2142, _T_2134) @[dec_dec_ctl.scala 17:17] + node _T_2144 = and(_T_2143, _T_2135) @[dec_dec_ctl.scala 17:17] + node _T_2145 = and(_T_2144, _T_2137) @[dec_dec_ctl.scala 17:17] + node _T_2146 = or(_T_2124, _T_2145) @[dec_dec_ctl.scala 172:103] + node _T_2147 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2148 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2149 = eq(_T_2148, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2150 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2151 = eq(_T_2150, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2152 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2153 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2154 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2155 = eq(_T_2154, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2156 = and(_T_2147, _T_2149) @[dec_dec_ctl.scala 17:17] + node _T_2157 = and(_T_2156, _T_2151) @[dec_dec_ctl.scala 17:17] + node _T_2158 = and(_T_2157, _T_2152) @[dec_dec_ctl.scala 17:17] + node _T_2159 = and(_T_2158, _T_2153) @[dec_dec_ctl.scala 17:17] + node _T_2160 = and(_T_2159, _T_2155) @[dec_dec_ctl.scala 17:17] + node _T_2161 = or(_T_2146, _T_2160) @[dec_dec_ctl.scala 173:48] + node _T_2162 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2163 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2164 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2165 = eq(_T_2164, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2166 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2167 = eq(_T_2166, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2168 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2169 = eq(_T_2168, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2170 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2171 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2172 = eq(_T_2171, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2173 = and(_T_2162, _T_2163) @[dec_dec_ctl.scala 17:17] + node _T_2174 = and(_T_2173, _T_2165) @[dec_dec_ctl.scala 17:17] + node _T_2175 = and(_T_2174, _T_2167) @[dec_dec_ctl.scala 17:17] + node _T_2176 = and(_T_2175, _T_2169) @[dec_dec_ctl.scala 17:17] + node _T_2177 = and(_T_2176, _T_2170) @[dec_dec_ctl.scala 17:17] + node _T_2178 = and(_T_2177, _T_2172) @[dec_dec_ctl.scala 17:17] + node _T_2179 = or(_T_2161, _T_2178) @[dec_dec_ctl.scala 173:83] + node _T_2180 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2181 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2182 = eq(_T_2181, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2183 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2184 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2185 = eq(_T_2184, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2186 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2187 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2188 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2189 = eq(_T_2188, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2190 = and(_T_2180, _T_2182) @[dec_dec_ctl.scala 17:17] + node _T_2191 = and(_T_2190, _T_2183) @[dec_dec_ctl.scala 17:17] + node _T_2192 = and(_T_2191, _T_2185) @[dec_dec_ctl.scala 17:17] + node _T_2193 = and(_T_2192, _T_2186) @[dec_dec_ctl.scala 17:17] + node _T_2194 = and(_T_2193, _T_2187) @[dec_dec_ctl.scala 17:17] + node _T_2195 = and(_T_2194, _T_2189) @[dec_dec_ctl.scala 17:17] + node _T_2196 = or(_T_2179, _T_2195) @[dec_dec_ctl.scala 174:42] + node _T_2197 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2198 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2199 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2200 = eq(_T_2199, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2201 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2202 = eq(_T_2201, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2203 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2204 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2205 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2206 = eq(_T_2205, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2207 = and(_T_2197, _T_2198) @[dec_dec_ctl.scala 17:17] + node _T_2208 = and(_T_2207, _T_2200) @[dec_dec_ctl.scala 17:17] + node _T_2209 = and(_T_2208, _T_2202) @[dec_dec_ctl.scala 17:17] + node _T_2210 = and(_T_2209, _T_2203) @[dec_dec_ctl.scala 17:17] + node _T_2211 = and(_T_2210, _T_2204) @[dec_dec_ctl.scala 17:17] + node _T_2212 = and(_T_2211, _T_2206) @[dec_dec_ctl.scala 17:17] + node _T_2213 = or(_T_2196, _T_2212) @[dec_dec_ctl.scala 174:79] + node _T_2214 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2215 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2216 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2217 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_2218 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_2219 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_2220 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_2221 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2222 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2223 = eq(_T_2222, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2224 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2225 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2226 = eq(_T_2225, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2227 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2228 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2229 = eq(_T_2228, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2230 = and(_T_2214, _T_2215) @[dec_dec_ctl.scala 17:17] + node _T_2231 = and(_T_2230, _T_2216) @[dec_dec_ctl.scala 17:17] + node _T_2232 = and(_T_2231, _T_2217) @[dec_dec_ctl.scala 17:17] + node _T_2233 = and(_T_2232, _T_2218) @[dec_dec_ctl.scala 17:17] + node _T_2234 = and(_T_2233, _T_2219) @[dec_dec_ctl.scala 17:17] + node _T_2235 = and(_T_2234, _T_2220) @[dec_dec_ctl.scala 17:17] + node _T_2236 = and(_T_2235, _T_2221) @[dec_dec_ctl.scala 17:17] + node _T_2237 = and(_T_2236, _T_2223) @[dec_dec_ctl.scala 17:17] + node _T_2238 = and(_T_2237, _T_2224) @[dec_dec_ctl.scala 17:17] + node _T_2239 = and(_T_2238, _T_2226) @[dec_dec_ctl.scala 17:17] + node _T_2240 = and(_T_2239, _T_2227) @[dec_dec_ctl.scala 17:17] + node _T_2241 = and(_T_2240, _T_2229) @[dec_dec_ctl.scala 17:17] + node _T_2242 = or(_T_2213, _T_2241) @[dec_dec_ctl.scala 175:40] + node _T_2243 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2244 = eq(_T_2243, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2245 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2246 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2247 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_2248 = eq(_T_2247, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2249 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_2250 = eq(_T_2249, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2251 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_2252 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_2253 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_2254 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2255 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2256 = eq(_T_2255, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2257 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2258 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2259 = eq(_T_2258, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2260 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2261 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2262 = eq(_T_2261, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2263 = and(_T_2244, _T_2245) @[dec_dec_ctl.scala 17:17] + node _T_2264 = and(_T_2263, _T_2246) @[dec_dec_ctl.scala 17:17] + node _T_2265 = and(_T_2264, _T_2248) @[dec_dec_ctl.scala 17:17] + node _T_2266 = and(_T_2265, _T_2250) @[dec_dec_ctl.scala 17:17] + node _T_2267 = and(_T_2266, _T_2251) @[dec_dec_ctl.scala 17:17] + node _T_2268 = and(_T_2267, _T_2252) @[dec_dec_ctl.scala 17:17] + node _T_2269 = and(_T_2268, _T_2253) @[dec_dec_ctl.scala 17:17] + node _T_2270 = and(_T_2269, _T_2254) @[dec_dec_ctl.scala 17:17] + node _T_2271 = and(_T_2270, _T_2256) @[dec_dec_ctl.scala 17:17] + node _T_2272 = and(_T_2271, _T_2257) @[dec_dec_ctl.scala 17:17] + node _T_2273 = and(_T_2272, _T_2259) @[dec_dec_ctl.scala 17:17] + node _T_2274 = and(_T_2273, _T_2260) @[dec_dec_ctl.scala 17:17] + node _T_2275 = and(_T_2274, _T_2262) @[dec_dec_ctl.scala 17:17] + node _T_2276 = or(_T_2242, _T_2275) @[dec_dec_ctl.scala 175:96] + node _T_2277 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2278 = eq(_T_2277, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2279 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2280 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2281 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_2282 = eq(_T_2281, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2283 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_2284 = eq(_T_2283, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2285 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_2286 = eq(_T_2285, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2287 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_2288 = eq(_T_2287, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2289 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2290 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2291 = eq(_T_2290, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2292 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2293 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2294 = eq(_T_2293, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2295 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2296 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2297 = eq(_T_2296, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2298 = and(_T_2278, _T_2279) @[dec_dec_ctl.scala 17:17] + node _T_2299 = and(_T_2298, _T_2280) @[dec_dec_ctl.scala 17:17] + node _T_2300 = and(_T_2299, _T_2282) @[dec_dec_ctl.scala 17:17] + node _T_2301 = and(_T_2300, _T_2284) @[dec_dec_ctl.scala 17:17] + node _T_2302 = and(_T_2301, _T_2286) @[dec_dec_ctl.scala 17:17] + node _T_2303 = and(_T_2302, _T_2288) @[dec_dec_ctl.scala 17:17] + node _T_2304 = and(_T_2303, _T_2289) @[dec_dec_ctl.scala 17:17] + node _T_2305 = and(_T_2304, _T_2291) @[dec_dec_ctl.scala 17:17] + node _T_2306 = and(_T_2305, _T_2292) @[dec_dec_ctl.scala 17:17] + node _T_2307 = and(_T_2306, _T_2294) @[dec_dec_ctl.scala 17:17] + node _T_2308 = and(_T_2307, _T_2295) @[dec_dec_ctl.scala 17:17] + node _T_2309 = and(_T_2308, _T_2297) @[dec_dec_ctl.scala 17:17] + node _T_2310 = or(_T_2276, _T_2309) @[dec_dec_ctl.scala 176:65] + node _T_2311 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2312 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2313 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2314 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_2315 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_2316 = eq(_T_2315, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2317 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_2318 = eq(_T_2317, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2319 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_2320 = eq(_T_2319, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2321 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2322 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2323 = eq(_T_2322, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2324 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2325 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2326 = eq(_T_2325, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2327 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2328 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2329 = eq(_T_2328, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2330 = and(_T_2311, _T_2312) @[dec_dec_ctl.scala 17:17] + node _T_2331 = and(_T_2330, _T_2313) @[dec_dec_ctl.scala 17:17] + node _T_2332 = and(_T_2331, _T_2314) @[dec_dec_ctl.scala 17:17] + node _T_2333 = and(_T_2332, _T_2316) @[dec_dec_ctl.scala 17:17] + node _T_2334 = and(_T_2333, _T_2318) @[dec_dec_ctl.scala 17:17] + node _T_2335 = and(_T_2334, _T_2320) @[dec_dec_ctl.scala 17:17] + node _T_2336 = and(_T_2335, _T_2321) @[dec_dec_ctl.scala 17:17] + node _T_2337 = and(_T_2336, _T_2323) @[dec_dec_ctl.scala 17:17] + node _T_2338 = and(_T_2337, _T_2324) @[dec_dec_ctl.scala 17:17] + node _T_2339 = and(_T_2338, _T_2326) @[dec_dec_ctl.scala 17:17] + node _T_2340 = and(_T_2339, _T_2327) @[dec_dec_ctl.scala 17:17] + node _T_2341 = and(_T_2340, _T_2329) @[dec_dec_ctl.scala 17:17] + node _T_2342 = or(_T_2310, _T_2341) @[dec_dec_ctl.scala 177:64] + node _T_2343 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2344 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_2345 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2346 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2347 = eq(_T_2346, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2348 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2349 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2350 = eq(_T_2349, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2351 = and(_T_2343, _T_2344) @[dec_dec_ctl.scala 17:17] + node _T_2352 = and(_T_2351, _T_2345) @[dec_dec_ctl.scala 17:17] + node _T_2353 = and(_T_2352, _T_2347) @[dec_dec_ctl.scala 17:17] + node _T_2354 = and(_T_2353, _T_2348) @[dec_dec_ctl.scala 17:17] + node _T_2355 = and(_T_2354, _T_2350) @[dec_dec_ctl.scala 17:17] + node _T_2356 = or(_T_2342, _T_2355) @[dec_dec_ctl.scala 178:62] + io.out.zbb <= _T_2356 @[dec_dec_ctl.scala 172:14] + node _T_2357 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2358 = eq(_T_2357, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2359 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2360 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2361 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2362 = eq(_T_2361, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2363 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2364 = eq(_T_2363, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2365 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2366 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2367 = eq(_T_2366, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2368 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2369 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2370 = eq(_T_2369, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2371 = and(_T_2358, _T_2359) @[dec_dec_ctl.scala 17:17] + node _T_2372 = and(_T_2371, _T_2360) @[dec_dec_ctl.scala 17:17] + node _T_2373 = and(_T_2372, _T_2362) @[dec_dec_ctl.scala 17:17] + node _T_2374 = and(_T_2373, _T_2364) @[dec_dec_ctl.scala 17:17] + node _T_2375 = and(_T_2374, _T_2365) @[dec_dec_ctl.scala 17:17] + node _T_2376 = and(_T_2375, _T_2367) @[dec_dec_ctl.scala 17:17] + node _T_2377 = and(_T_2376, _T_2368) @[dec_dec_ctl.scala 17:17] + node _T_2378 = and(_T_2377, _T_2370) @[dec_dec_ctl.scala 17:17] + io.out.sbset <= _T_2378 @[dec_dec_ctl.scala 180:16] + node _T_2379 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2380 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2381 = eq(_T_2380, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2382 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2383 = eq(_T_2382, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2384 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2385 = eq(_T_2384, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2386 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2387 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2388 = eq(_T_2387, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2389 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2390 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2391 = eq(_T_2390, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2392 = and(_T_2379, _T_2381) @[dec_dec_ctl.scala 17:17] + node _T_2393 = and(_T_2392, _T_2383) @[dec_dec_ctl.scala 17:17] + node _T_2394 = and(_T_2393, _T_2385) @[dec_dec_ctl.scala 17:17] + node _T_2395 = and(_T_2394, _T_2386) @[dec_dec_ctl.scala 17:17] + node _T_2396 = and(_T_2395, _T_2388) @[dec_dec_ctl.scala 17:17] + node _T_2397 = and(_T_2396, _T_2389) @[dec_dec_ctl.scala 17:17] + node _T_2398 = and(_T_2397, _T_2391) @[dec_dec_ctl.scala 17:17] + io.out.sbclr <= _T_2398 @[dec_dec_ctl.scala 182:16] + node _T_2399 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2400 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2401 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2402 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2403 = eq(_T_2402, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2404 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2405 = eq(_T_2404, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2406 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2407 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2408 = eq(_T_2407, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2409 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2410 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2411 = eq(_T_2410, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2412 = and(_T_2399, _T_2400) @[dec_dec_ctl.scala 17:17] + node _T_2413 = and(_T_2412, _T_2401) @[dec_dec_ctl.scala 17:17] + node _T_2414 = and(_T_2413, _T_2403) @[dec_dec_ctl.scala 17:17] + node _T_2415 = and(_T_2414, _T_2405) @[dec_dec_ctl.scala 17:17] + node _T_2416 = and(_T_2415, _T_2406) @[dec_dec_ctl.scala 17:17] + node _T_2417 = and(_T_2416, _T_2408) @[dec_dec_ctl.scala 17:17] + node _T_2418 = and(_T_2417, _T_2409) @[dec_dec_ctl.scala 17:17] + node _T_2419 = and(_T_2418, _T_2411) @[dec_dec_ctl.scala 17:17] + io.out.sbinv <= _T_2419 @[dec_dec_ctl.scala 184:16] + node _T_2420 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2421 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2422 = eq(_T_2421, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2423 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2424 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2425 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2426 = eq(_T_2425, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2427 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2428 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2429 = eq(_T_2428, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2430 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2431 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2432 = eq(_T_2431, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2433 = and(_T_2420, _T_2422) @[dec_dec_ctl.scala 17:17] + node _T_2434 = and(_T_2433, _T_2423) @[dec_dec_ctl.scala 17:17] + node _T_2435 = and(_T_2434, _T_2424) @[dec_dec_ctl.scala 17:17] + node _T_2436 = and(_T_2435, _T_2426) @[dec_dec_ctl.scala 17:17] + node _T_2437 = and(_T_2436, _T_2427) @[dec_dec_ctl.scala 17:17] + node _T_2438 = and(_T_2437, _T_2429) @[dec_dec_ctl.scala 17:17] + node _T_2439 = and(_T_2438, _T_2430) @[dec_dec_ctl.scala 17:17] + node _T_2440 = and(_T_2439, _T_2432) @[dec_dec_ctl.scala 17:17] + io.out.sbext <= _T_2440 @[dec_dec_ctl.scala 186:16] + node _T_2441 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2442 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2443 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2444 = eq(_T_2443, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2445 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2446 = eq(_T_2445, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2447 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2448 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2449 = eq(_T_2448, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2450 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2451 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2452 = eq(_T_2451, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2453 = and(_T_2441, _T_2442) @[dec_dec_ctl.scala 17:17] + node _T_2454 = and(_T_2453, _T_2444) @[dec_dec_ctl.scala 17:17] + node _T_2455 = and(_T_2454, _T_2446) @[dec_dec_ctl.scala 17:17] + node _T_2456 = and(_T_2455, _T_2447) @[dec_dec_ctl.scala 17:17] + node _T_2457 = and(_T_2456, _T_2449) @[dec_dec_ctl.scala 17:17] + node _T_2458 = and(_T_2457, _T_2450) @[dec_dec_ctl.scala 17:17] + node _T_2459 = and(_T_2458, _T_2452) @[dec_dec_ctl.scala 17:17] + node _T_2460 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2461 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2462 = eq(_T_2461, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2463 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2464 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2465 = eq(_T_2464, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2466 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2467 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2468 = eq(_T_2467, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2469 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2470 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2471 = eq(_T_2470, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2472 = and(_T_2460, _T_2462) @[dec_dec_ctl.scala 17:17] + node _T_2473 = and(_T_2472, _T_2463) @[dec_dec_ctl.scala 17:17] + node _T_2474 = and(_T_2473, _T_2465) @[dec_dec_ctl.scala 17:17] + node _T_2475 = and(_T_2474, _T_2466) @[dec_dec_ctl.scala 17:17] + node _T_2476 = and(_T_2475, _T_2468) @[dec_dec_ctl.scala 17:17] + node _T_2477 = and(_T_2476, _T_2469) @[dec_dec_ctl.scala 17:17] + node _T_2478 = and(_T_2477, _T_2471) @[dec_dec_ctl.scala 17:17] + node _T_2479 = or(_T_2459, _T_2478) @[dec_dec_ctl.scala 188:57] + io.out.zbs <= _T_2479 @[dec_dec_ctl.scala 188:14] + node _T_2480 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2481 = eq(_T_2480, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2482 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2483 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2484 = eq(_T_2483, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2485 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2486 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2487 = eq(_T_2486, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2488 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2489 = eq(_T_2488, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2490 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2491 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2492 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2493 = eq(_T_2492, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2494 = and(_T_2481, _T_2482) @[dec_dec_ctl.scala 17:17] + node _T_2495 = and(_T_2494, _T_2484) @[dec_dec_ctl.scala 17:17] + node _T_2496 = and(_T_2495, _T_2485) @[dec_dec_ctl.scala 17:17] + node _T_2497 = and(_T_2496, _T_2487) @[dec_dec_ctl.scala 17:17] + node _T_2498 = and(_T_2497, _T_2489) @[dec_dec_ctl.scala 17:17] + node _T_2499 = and(_T_2498, _T_2490) @[dec_dec_ctl.scala 17:17] + node _T_2500 = and(_T_2499, _T_2491) @[dec_dec_ctl.scala 17:17] + node _T_2501 = and(_T_2500, _T_2493) @[dec_dec_ctl.scala 17:17] + io.out.bext <= _T_2501 @[dec_dec_ctl.scala 190:15] + node _T_2502 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2503 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2504 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2505 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2506 = eq(_T_2505, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2507 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2508 = eq(_T_2507, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2509 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2510 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2511 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2512 = eq(_T_2511, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2513 = and(_T_2502, _T_2503) @[dec_dec_ctl.scala 17:17] + node _T_2514 = and(_T_2513, _T_2504) @[dec_dec_ctl.scala 17:17] + node _T_2515 = and(_T_2514, _T_2506) @[dec_dec_ctl.scala 17:17] + node _T_2516 = and(_T_2515, _T_2508) @[dec_dec_ctl.scala 17:17] + node _T_2517 = and(_T_2516, _T_2509) @[dec_dec_ctl.scala 17:17] + node _T_2518 = and(_T_2517, _T_2510) @[dec_dec_ctl.scala 17:17] + node _T_2519 = and(_T_2518, _T_2512) @[dec_dec_ctl.scala 17:17] + io.out.bdep <= _T_2519 @[dec_dec_ctl.scala 192:15] + node _T_2520 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2521 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2522 = eq(_T_2521, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2523 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2524 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2525 = eq(_T_2524, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2526 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2527 = eq(_T_2526, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2528 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2529 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2530 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2531 = eq(_T_2530, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2532 = and(_T_2520, _T_2522) @[dec_dec_ctl.scala 17:17] + node _T_2533 = and(_T_2532, _T_2523) @[dec_dec_ctl.scala 17:17] + node _T_2534 = and(_T_2533, _T_2525) @[dec_dec_ctl.scala 17:17] + node _T_2535 = and(_T_2534, _T_2527) @[dec_dec_ctl.scala 17:17] + node _T_2536 = and(_T_2535, _T_2528) @[dec_dec_ctl.scala 17:17] + node _T_2537 = and(_T_2536, _T_2529) @[dec_dec_ctl.scala 17:17] + node _T_2538 = and(_T_2537, _T_2531) @[dec_dec_ctl.scala 17:17] + io.out.zbe <= _T_2538 @[dec_dec_ctl.scala 194:14] + node _T_2539 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2540 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_2541 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2542 = eq(_T_2541, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2543 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2544 = eq(_T_2543, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2545 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2546 = eq(_T_2545, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2547 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2548 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2549 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2550 = eq(_T_2549, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2551 = and(_T_2539, _T_2540) @[dec_dec_ctl.scala 17:17] + node _T_2552 = and(_T_2551, _T_2542) @[dec_dec_ctl.scala 17:17] + node _T_2553 = and(_T_2552, _T_2544) @[dec_dec_ctl.scala 17:17] + node _T_2554 = and(_T_2553, _T_2546) @[dec_dec_ctl.scala 17:17] + node _T_2555 = and(_T_2554, _T_2547) @[dec_dec_ctl.scala 17:17] + node _T_2556 = and(_T_2555, _T_2548) @[dec_dec_ctl.scala 17:17] + node _T_2557 = and(_T_2556, _T_2550) @[dec_dec_ctl.scala 17:17] + io.out.clmul <= _T_2557 @[dec_dec_ctl.scala 196:16] + node _T_2558 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2559 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2560 = eq(_T_2559, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2561 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2562 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2563 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2564 = eq(_T_2563, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2565 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2566 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2567 = eq(_T_2566, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2568 = and(_T_2558, _T_2560) @[dec_dec_ctl.scala 17:17] + node _T_2569 = and(_T_2568, _T_2561) @[dec_dec_ctl.scala 17:17] + node _T_2570 = and(_T_2569, _T_2562) @[dec_dec_ctl.scala 17:17] + node _T_2571 = and(_T_2570, _T_2564) @[dec_dec_ctl.scala 17:17] + node _T_2572 = and(_T_2571, _T_2565) @[dec_dec_ctl.scala 17:17] + node _T_2573 = and(_T_2572, _T_2567) @[dec_dec_ctl.scala 17:17] + io.out.clmulh <= _T_2573 @[dec_dec_ctl.scala 198:17] + node _T_2574 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2575 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2576 = eq(_T_2575, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2577 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2578 = eq(_T_2577, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2579 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2580 = eq(_T_2579, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2581 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2582 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2583 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2584 = eq(_T_2583, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2585 = and(_T_2574, _T_2576) @[dec_dec_ctl.scala 17:17] + node _T_2586 = and(_T_2585, _T_2578) @[dec_dec_ctl.scala 17:17] + node _T_2587 = and(_T_2586, _T_2580) @[dec_dec_ctl.scala 17:17] + node _T_2588 = and(_T_2587, _T_2581) @[dec_dec_ctl.scala 17:17] + node _T_2589 = and(_T_2588, _T_2582) @[dec_dec_ctl.scala 17:17] + node _T_2590 = and(_T_2589, _T_2584) @[dec_dec_ctl.scala 17:17] + io.out.clmulr <= _T_2590 @[dec_dec_ctl.scala 200:17] + node _T_2591 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2592 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_2593 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2594 = eq(_T_2593, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2595 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2596 = eq(_T_2595, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2597 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2598 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2599 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2600 = eq(_T_2599, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2601 = and(_T_2591, _T_2592) @[dec_dec_ctl.scala 17:17] + node _T_2602 = and(_T_2601, _T_2594) @[dec_dec_ctl.scala 17:17] + node _T_2603 = and(_T_2602, _T_2596) @[dec_dec_ctl.scala 17:17] + node _T_2604 = and(_T_2603, _T_2597) @[dec_dec_ctl.scala 17:17] + node _T_2605 = and(_T_2604, _T_2598) @[dec_dec_ctl.scala 17:17] + node _T_2606 = and(_T_2605, _T_2600) @[dec_dec_ctl.scala 17:17] + io.out.zbc <= _T_2606 @[dec_dec_ctl.scala 202:14] + node _T_2607 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2608 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2609 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2610 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2611 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2612 = eq(_T_2611, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2613 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2614 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2615 = eq(_T_2614, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2616 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2617 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2618 = eq(_T_2617, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2619 = and(_T_2607, _T_2608) @[dec_dec_ctl.scala 17:17] + node _T_2620 = and(_T_2619, _T_2609) @[dec_dec_ctl.scala 17:17] + node _T_2621 = and(_T_2620, _T_2610) @[dec_dec_ctl.scala 17:17] + node _T_2622 = and(_T_2621, _T_2612) @[dec_dec_ctl.scala 17:17] + node _T_2623 = and(_T_2622, _T_2613) @[dec_dec_ctl.scala 17:17] + node _T_2624 = and(_T_2623, _T_2615) @[dec_dec_ctl.scala 17:17] + node _T_2625 = and(_T_2624, _T_2616) @[dec_dec_ctl.scala 17:17] + node _T_2626 = and(_T_2625, _T_2618) @[dec_dec_ctl.scala 17:17] + io.out.grev <= _T_2626 @[dec_dec_ctl.scala 204:15] + node _T_2627 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2628 = eq(_T_2627, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2629 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2630 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2631 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2632 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2633 = eq(_T_2632, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2634 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2635 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2636 = eq(_T_2635, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2637 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2638 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2639 = eq(_T_2638, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2640 = and(_T_2628, _T_2629) @[dec_dec_ctl.scala 17:17] + node _T_2641 = and(_T_2640, _T_2630) @[dec_dec_ctl.scala 17:17] + node _T_2642 = and(_T_2641, _T_2631) @[dec_dec_ctl.scala 17:17] + node _T_2643 = and(_T_2642, _T_2633) @[dec_dec_ctl.scala 17:17] + node _T_2644 = and(_T_2643, _T_2634) @[dec_dec_ctl.scala 17:17] + node _T_2645 = and(_T_2644, _T_2636) @[dec_dec_ctl.scala 17:17] + node _T_2646 = and(_T_2645, _T_2637) @[dec_dec_ctl.scala 17:17] + node _T_2647 = and(_T_2646, _T_2639) @[dec_dec_ctl.scala 17:17] + io.out.gorc <= _T_2647 @[dec_dec_ctl.scala 206:15] + node _T_2648 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2649 = eq(_T_2648, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2650 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2651 = eq(_T_2650, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2652 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2653 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2654 = eq(_T_2653, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2655 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2656 = eq(_T_2655, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2657 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2658 = eq(_T_2657, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2659 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2660 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2661 = eq(_T_2660, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2662 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2663 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2664 = eq(_T_2663, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2665 = and(_T_2649, _T_2651) @[dec_dec_ctl.scala 17:17] + node _T_2666 = and(_T_2665, _T_2652) @[dec_dec_ctl.scala 17:17] + node _T_2667 = and(_T_2666, _T_2654) @[dec_dec_ctl.scala 17:17] + node _T_2668 = and(_T_2667, _T_2656) @[dec_dec_ctl.scala 17:17] + node _T_2669 = and(_T_2668, _T_2658) @[dec_dec_ctl.scala 17:17] + node _T_2670 = and(_T_2669, _T_2659) @[dec_dec_ctl.scala 17:17] + node _T_2671 = and(_T_2670, _T_2661) @[dec_dec_ctl.scala 17:17] + node _T_2672 = and(_T_2671, _T_2662) @[dec_dec_ctl.scala 17:17] + node _T_2673 = and(_T_2672, _T_2664) @[dec_dec_ctl.scala 17:17] + io.out.shfl <= _T_2673 @[dec_dec_ctl.scala 208:15] + node _T_2674 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2675 = eq(_T_2674, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2676 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2677 = eq(_T_2676, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2678 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2679 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2680 = eq(_T_2679, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2681 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2682 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2683 = eq(_T_2682, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2684 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2685 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2686 = eq(_T_2685, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2687 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2688 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2689 = eq(_T_2688, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2690 = and(_T_2675, _T_2677) @[dec_dec_ctl.scala 17:17] + node _T_2691 = and(_T_2690, _T_2678) @[dec_dec_ctl.scala 17:17] + node _T_2692 = and(_T_2691, _T_2680) @[dec_dec_ctl.scala 17:17] + node _T_2693 = and(_T_2692, _T_2681) @[dec_dec_ctl.scala 17:17] + node _T_2694 = and(_T_2693, _T_2683) @[dec_dec_ctl.scala 17:17] + node _T_2695 = and(_T_2694, _T_2684) @[dec_dec_ctl.scala 17:17] + node _T_2696 = and(_T_2695, _T_2686) @[dec_dec_ctl.scala 17:17] + node _T_2697 = and(_T_2696, _T_2687) @[dec_dec_ctl.scala 17:17] + node _T_2698 = and(_T_2697, _T_2689) @[dec_dec_ctl.scala 17:17] + io.out.unshfl <= _T_2698 @[dec_dec_ctl.scala 210:17] + node _T_2699 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2700 = eq(_T_2699, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2701 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2702 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2703 = eq(_T_2702, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2704 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2705 = eq(_T_2704, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2706 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2707 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2708 = eq(_T_2707, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2709 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2710 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2711 = eq(_T_2710, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2712 = and(_T_2700, _T_2701) @[dec_dec_ctl.scala 17:17] + node _T_2713 = and(_T_2712, _T_2703) @[dec_dec_ctl.scala 17:17] + node _T_2714 = and(_T_2713, _T_2705) @[dec_dec_ctl.scala 17:17] + node _T_2715 = and(_T_2714, _T_2706) @[dec_dec_ctl.scala 17:17] + node _T_2716 = and(_T_2715, _T_2708) @[dec_dec_ctl.scala 17:17] + node _T_2717 = and(_T_2716, _T_2709) @[dec_dec_ctl.scala 17:17] + node _T_2718 = and(_T_2717, _T_2711) @[dec_dec_ctl.scala 17:17] + node _T_2719 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2720 = eq(_T_2719, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2721 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2722 = eq(_T_2721, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2723 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2724 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2725 = eq(_T_2724, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2726 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2727 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2728 = eq(_T_2727, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2729 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2730 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2731 = eq(_T_2730, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2732 = and(_T_2720, _T_2722) @[dec_dec_ctl.scala 17:17] + node _T_2733 = and(_T_2732, _T_2723) @[dec_dec_ctl.scala 17:17] + node _T_2734 = and(_T_2733, _T_2725) @[dec_dec_ctl.scala 17:17] + node _T_2735 = and(_T_2734, _T_2726) @[dec_dec_ctl.scala 17:17] + node _T_2736 = and(_T_2735, _T_2728) @[dec_dec_ctl.scala 17:17] + node _T_2737 = and(_T_2736, _T_2729) @[dec_dec_ctl.scala 17:17] + node _T_2738 = and(_T_2737, _T_2731) @[dec_dec_ctl.scala 17:17] + node _T_2739 = or(_T_2718, _T_2738) @[dec_dec_ctl.scala 212:58] + node _T_2740 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2741 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2742 = eq(_T_2741, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2743 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2744 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2745 = eq(_T_2744, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2746 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2747 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2748 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2749 = eq(_T_2748, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2750 = and(_T_2740, _T_2742) @[dec_dec_ctl.scala 17:17] + node _T_2751 = and(_T_2750, _T_2743) @[dec_dec_ctl.scala 17:17] + node _T_2752 = and(_T_2751, _T_2745) @[dec_dec_ctl.scala 17:17] + node _T_2753 = and(_T_2752, _T_2746) @[dec_dec_ctl.scala 17:17] + node _T_2754 = and(_T_2753, _T_2747) @[dec_dec_ctl.scala 17:17] + node _T_2755 = and(_T_2754, _T_2749) @[dec_dec_ctl.scala 17:17] + node _T_2756 = or(_T_2739, _T_2755) @[dec_dec_ctl.scala 212:101] + node _T_2757 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2758 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2759 = eq(_T_2758, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2760 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2761 = eq(_T_2760, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2762 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2763 = eq(_T_2762, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2764 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2765 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2766 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2767 = eq(_T_2766, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2768 = and(_T_2757, _T_2759) @[dec_dec_ctl.scala 17:17] + node _T_2769 = and(_T_2768, _T_2761) @[dec_dec_ctl.scala 17:17] + node _T_2770 = and(_T_2769, _T_2763) @[dec_dec_ctl.scala 17:17] + node _T_2771 = and(_T_2770, _T_2764) @[dec_dec_ctl.scala 17:17] + node _T_2772 = and(_T_2771, _T_2765) @[dec_dec_ctl.scala 17:17] + node _T_2773 = and(_T_2772, _T_2767) @[dec_dec_ctl.scala 17:17] + node _T_2774 = or(_T_2756, _T_2773) @[dec_dec_ctl.scala 213:40] + node _T_2775 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2776 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2777 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2778 = eq(_T_2777, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2779 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2780 = eq(_T_2779, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2781 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2782 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2783 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2784 = eq(_T_2783, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2785 = and(_T_2775, _T_2776) @[dec_dec_ctl.scala 17:17] + node _T_2786 = and(_T_2785, _T_2778) @[dec_dec_ctl.scala 17:17] + node _T_2787 = and(_T_2786, _T_2780) @[dec_dec_ctl.scala 17:17] + node _T_2788 = and(_T_2787, _T_2781) @[dec_dec_ctl.scala 17:17] + node _T_2789 = and(_T_2788, _T_2782) @[dec_dec_ctl.scala 17:17] + node _T_2790 = and(_T_2789, _T_2784) @[dec_dec_ctl.scala 17:17] + node _T_2791 = or(_T_2774, _T_2790) @[dec_dec_ctl.scala 213:79] + node _T_2792 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2793 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2794 = eq(_T_2793, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2795 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2796 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2797 = eq(_T_2796, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2798 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2799 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2800 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2801 = eq(_T_2800, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2802 = and(_T_2792, _T_2794) @[dec_dec_ctl.scala 17:17] + node _T_2803 = and(_T_2802, _T_2795) @[dec_dec_ctl.scala 17:17] + node _T_2804 = and(_T_2803, _T_2797) @[dec_dec_ctl.scala 17:17] + node _T_2805 = and(_T_2804, _T_2798) @[dec_dec_ctl.scala 17:17] + node _T_2806 = and(_T_2805, _T_2799) @[dec_dec_ctl.scala 17:17] + node _T_2807 = and(_T_2806, _T_2801) @[dec_dec_ctl.scala 17:17] + node _T_2808 = or(_T_2791, _T_2807) @[dec_dec_ctl.scala 214:41] + node _T_2809 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2810 = eq(_T_2809, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2811 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2812 = eq(_T_2811, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2813 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2814 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2815 = eq(_T_2814, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2816 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2817 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2818 = eq(_T_2817, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2819 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2820 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2821 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2822 = eq(_T_2821, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2823 = and(_T_2810, _T_2812) @[dec_dec_ctl.scala 17:17] + node _T_2824 = and(_T_2823, _T_2813) @[dec_dec_ctl.scala 17:17] + node _T_2825 = and(_T_2824, _T_2815) @[dec_dec_ctl.scala 17:17] + node _T_2826 = and(_T_2825, _T_2816) @[dec_dec_ctl.scala 17:17] + node _T_2827 = and(_T_2826, _T_2818) @[dec_dec_ctl.scala 17:17] + node _T_2828 = and(_T_2827, _T_2819) @[dec_dec_ctl.scala 17:17] + node _T_2829 = and(_T_2828, _T_2820) @[dec_dec_ctl.scala 17:17] + node _T_2830 = and(_T_2829, _T_2822) @[dec_dec_ctl.scala 17:17] + node _T_2831 = or(_T_2808, _T_2830) @[dec_dec_ctl.scala 214:78] + node _T_2832 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2833 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2834 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2835 = eq(_T_2834, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2836 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2837 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2838 = eq(_T_2837, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2839 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2840 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2841 = eq(_T_2840, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2842 = and(_T_2832, _T_2833) @[dec_dec_ctl.scala 17:17] + node _T_2843 = and(_T_2842, _T_2835) @[dec_dec_ctl.scala 17:17] + node _T_2844 = and(_T_2843, _T_2836) @[dec_dec_ctl.scala 17:17] + node _T_2845 = and(_T_2844, _T_2838) @[dec_dec_ctl.scala 17:17] + node _T_2846 = and(_T_2845, _T_2839) @[dec_dec_ctl.scala 17:17] + node _T_2847 = and(_T_2846, _T_2841) @[dec_dec_ctl.scala 17:17] + node _T_2848 = or(_T_2831, _T_2847) @[dec_dec_ctl.scala 215:48] + io.out.zbp <= _T_2848 @[dec_dec_ctl.scala 212:14] + node _T_2849 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2850 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2851 = eq(_T_2850, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2852 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2853 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_2854 = eq(_T_2853, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2855 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_2856 = eq(_T_2855, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2857 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_2858 = eq(_T_2857, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2859 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2860 = eq(_T_2859, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2861 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2862 = eq(_T_2861, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2863 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2864 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2865 = eq(_T_2864, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2866 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2867 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2868 = eq(_T_2867, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2869 = and(_T_2849, _T_2851) @[dec_dec_ctl.scala 17:17] + node _T_2870 = and(_T_2869, _T_2852) @[dec_dec_ctl.scala 17:17] + node _T_2871 = and(_T_2870, _T_2854) @[dec_dec_ctl.scala 17:17] + node _T_2872 = and(_T_2871, _T_2856) @[dec_dec_ctl.scala 17:17] + node _T_2873 = and(_T_2872, _T_2858) @[dec_dec_ctl.scala 17:17] + node _T_2874 = and(_T_2873, _T_2860) @[dec_dec_ctl.scala 17:17] + node _T_2875 = and(_T_2874, _T_2862) @[dec_dec_ctl.scala 17:17] + node _T_2876 = and(_T_2875, _T_2863) @[dec_dec_ctl.scala 17:17] + node _T_2877 = and(_T_2876, _T_2865) @[dec_dec_ctl.scala 17:17] + node _T_2878 = and(_T_2877, _T_2866) @[dec_dec_ctl.scala 17:17] + node _T_2879 = and(_T_2878, _T_2868) @[dec_dec_ctl.scala 17:17] + io.out.crc32_b <= _T_2879 @[dec_dec_ctl.scala 217:18] + node _T_2880 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2881 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2882 = eq(_T_2881, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2883 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2884 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_2885 = eq(_T_2884, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2886 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_2887 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2888 = eq(_T_2887, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2889 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2890 = eq(_T_2889, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2891 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2892 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2893 = eq(_T_2892, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2894 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2895 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2896 = eq(_T_2895, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2897 = and(_T_2880, _T_2882) @[dec_dec_ctl.scala 17:17] + node _T_2898 = and(_T_2897, _T_2883) @[dec_dec_ctl.scala 17:17] + node _T_2899 = and(_T_2898, _T_2885) @[dec_dec_ctl.scala 17:17] + node _T_2900 = and(_T_2899, _T_2886) @[dec_dec_ctl.scala 17:17] + node _T_2901 = and(_T_2900, _T_2888) @[dec_dec_ctl.scala 17:17] + node _T_2902 = and(_T_2901, _T_2890) @[dec_dec_ctl.scala 17:17] + node _T_2903 = and(_T_2902, _T_2891) @[dec_dec_ctl.scala 17:17] + node _T_2904 = and(_T_2903, _T_2893) @[dec_dec_ctl.scala 17:17] + node _T_2905 = and(_T_2904, _T_2894) @[dec_dec_ctl.scala 17:17] + node _T_2906 = and(_T_2905, _T_2896) @[dec_dec_ctl.scala 17:17] + io.out.crc32_h <= _T_2906 @[dec_dec_ctl.scala 219:18] + node _T_2907 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2908 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2909 = eq(_T_2908, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2910 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2911 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_2912 = eq(_T_2911, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2913 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_2914 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2915 = eq(_T_2914, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2916 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2917 = eq(_T_2916, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2918 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2919 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2920 = eq(_T_2919, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2921 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2922 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2923 = eq(_T_2922, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2924 = and(_T_2907, _T_2909) @[dec_dec_ctl.scala 17:17] + node _T_2925 = and(_T_2924, _T_2910) @[dec_dec_ctl.scala 17:17] + node _T_2926 = and(_T_2925, _T_2912) @[dec_dec_ctl.scala 17:17] + node _T_2927 = and(_T_2926, _T_2913) @[dec_dec_ctl.scala 17:17] + node _T_2928 = and(_T_2927, _T_2915) @[dec_dec_ctl.scala 17:17] + node _T_2929 = and(_T_2928, _T_2917) @[dec_dec_ctl.scala 17:17] + node _T_2930 = and(_T_2929, _T_2918) @[dec_dec_ctl.scala 17:17] + node _T_2931 = and(_T_2930, _T_2920) @[dec_dec_ctl.scala 17:17] + node _T_2932 = and(_T_2931, _T_2921) @[dec_dec_ctl.scala 17:17] + node _T_2933 = and(_T_2932, _T_2923) @[dec_dec_ctl.scala 17:17] + io.out.crc32_w <= _T_2933 @[dec_dec_ctl.scala 221:18] + node _T_2934 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2935 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2936 = eq(_T_2935, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2937 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_2938 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_2939 = eq(_T_2938, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2940 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_2941 = eq(_T_2940, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2942 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2943 = eq(_T_2942, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2944 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2945 = eq(_T_2944, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2946 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2947 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2948 = eq(_T_2947, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2949 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2950 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2951 = eq(_T_2950, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2952 = and(_T_2934, _T_2936) @[dec_dec_ctl.scala 17:17] + node _T_2953 = and(_T_2952, _T_2937) @[dec_dec_ctl.scala 17:17] + node _T_2954 = and(_T_2953, _T_2939) @[dec_dec_ctl.scala 17:17] + node _T_2955 = and(_T_2954, _T_2941) @[dec_dec_ctl.scala 17:17] + node _T_2956 = and(_T_2955, _T_2943) @[dec_dec_ctl.scala 17:17] + node _T_2957 = and(_T_2956, _T_2945) @[dec_dec_ctl.scala 17:17] + node _T_2958 = and(_T_2957, _T_2946) @[dec_dec_ctl.scala 17:17] + node _T_2959 = and(_T_2958, _T_2948) @[dec_dec_ctl.scala 17:17] + node _T_2960 = and(_T_2959, _T_2949) @[dec_dec_ctl.scala 17:17] + node _T_2961 = and(_T_2960, _T_2951) @[dec_dec_ctl.scala 17:17] + io.out.crc32c_b <= _T_2961 @[dec_dec_ctl.scala 223:19] + node _T_2962 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2963 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2964 = eq(_T_2963, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2965 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_2966 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_2967 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2968 = eq(_T_2967, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2969 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2970 = eq(_T_2969, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2971 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2972 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2973 = eq(_T_2972, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2974 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2975 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2976 = eq(_T_2975, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2977 = and(_T_2962, _T_2964) @[dec_dec_ctl.scala 17:17] + node _T_2978 = and(_T_2977, _T_2965) @[dec_dec_ctl.scala 17:17] + node _T_2979 = and(_T_2978, _T_2966) @[dec_dec_ctl.scala 17:17] + node _T_2980 = and(_T_2979, _T_2968) @[dec_dec_ctl.scala 17:17] + node _T_2981 = and(_T_2980, _T_2970) @[dec_dec_ctl.scala 17:17] + node _T_2982 = and(_T_2981, _T_2971) @[dec_dec_ctl.scala 17:17] + node _T_2983 = and(_T_2982, _T_2973) @[dec_dec_ctl.scala 17:17] + node _T_2984 = and(_T_2983, _T_2974) @[dec_dec_ctl.scala 17:17] + node _T_2985 = and(_T_2984, _T_2976) @[dec_dec_ctl.scala 17:17] + io.out.crc32c_h <= _T_2985 @[dec_dec_ctl.scala 225:19] + node _T_2986 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2987 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2988 = eq(_T_2987, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2989 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_2990 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_2991 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2992 = eq(_T_2991, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2993 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2994 = eq(_T_2993, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2995 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2996 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2997 = eq(_T_2996, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2998 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2999 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3000 = eq(_T_2999, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3001 = and(_T_2986, _T_2988) @[dec_dec_ctl.scala 17:17] + node _T_3002 = and(_T_3001, _T_2989) @[dec_dec_ctl.scala 17:17] + node _T_3003 = and(_T_3002, _T_2990) @[dec_dec_ctl.scala 17:17] + node _T_3004 = and(_T_3003, _T_2992) @[dec_dec_ctl.scala 17:17] + node _T_3005 = and(_T_3004, _T_2994) @[dec_dec_ctl.scala 17:17] + node _T_3006 = and(_T_3005, _T_2995) @[dec_dec_ctl.scala 17:17] + node _T_3007 = and(_T_3006, _T_2997) @[dec_dec_ctl.scala 17:17] + node _T_3008 = and(_T_3007, _T_2998) @[dec_dec_ctl.scala 17:17] + node _T_3009 = and(_T_3008, _T_3000) @[dec_dec_ctl.scala 17:17] + io.out.crc32c_w <= _T_3009 @[dec_dec_ctl.scala 227:19] + node _T_3010 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_3011 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3012 = eq(_T_3011, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3013 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_3014 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3015 = eq(_T_3014, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3016 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3017 = eq(_T_3016, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3018 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_3019 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3020 = eq(_T_3019, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3021 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3022 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3023 = eq(_T_3022, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3024 = and(_T_3010, _T_3012) @[dec_dec_ctl.scala 17:17] + node _T_3025 = and(_T_3024, _T_3013) @[dec_dec_ctl.scala 17:17] + node _T_3026 = and(_T_3025, _T_3015) @[dec_dec_ctl.scala 17:17] + node _T_3027 = and(_T_3026, _T_3017) @[dec_dec_ctl.scala 17:17] + node _T_3028 = and(_T_3027, _T_3018) @[dec_dec_ctl.scala 17:17] + node _T_3029 = and(_T_3028, _T_3020) @[dec_dec_ctl.scala 17:17] + node _T_3030 = and(_T_3029, _T_3021) @[dec_dec_ctl.scala 17:17] + node _T_3031 = and(_T_3030, _T_3023) @[dec_dec_ctl.scala 17:17] + io.out.zbr <= _T_3031 @[dec_dec_ctl.scala 229:14] + node _T_3032 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_3033 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_3034 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_3035 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_3036 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3037 = eq(_T_3036, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3038 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3039 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3040 = eq(_T_3039, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3041 = and(_T_3032, _T_3033) @[dec_dec_ctl.scala 17:17] + node _T_3042 = and(_T_3041, _T_3034) @[dec_dec_ctl.scala 17:17] + node _T_3043 = and(_T_3042, _T_3035) @[dec_dec_ctl.scala 17:17] + node _T_3044 = and(_T_3043, _T_3037) @[dec_dec_ctl.scala 17:17] + node _T_3045 = and(_T_3044, _T_3038) @[dec_dec_ctl.scala 17:17] + node _T_3046 = and(_T_3045, _T_3040) @[dec_dec_ctl.scala 17:17] + io.out.bfp <= _T_3046 @[dec_dec_ctl.scala 231:14] + node _T_3047 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_3048 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_3049 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_3050 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_3051 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3052 = eq(_T_3051, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3053 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3054 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3055 = eq(_T_3054, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3056 = and(_T_3047, _T_3048) @[dec_dec_ctl.scala 17:17] + node _T_3057 = and(_T_3056, _T_3049) @[dec_dec_ctl.scala 17:17] + node _T_3058 = and(_T_3057, _T_3050) @[dec_dec_ctl.scala 17:17] + node _T_3059 = and(_T_3058, _T_3052) @[dec_dec_ctl.scala 17:17] + node _T_3060 = and(_T_3059, _T_3053) @[dec_dec_ctl.scala 17:17] + node _T_3061 = and(_T_3060, _T_3055) @[dec_dec_ctl.scala 17:17] + io.out.zbf <= _T_3061 @[dec_dec_ctl.scala 233:14] + node _T_3062 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3063 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3064 = eq(_T_3063, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3065 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3066 = eq(_T_3065, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3067 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3068 = eq(_T_3067, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3069 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3070 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3071 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3072 = eq(_T_3071, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3073 = and(_T_3062, _T_3064) @[dec_dec_ctl.scala 17:17] + node _T_3074 = and(_T_3073, _T_3066) @[dec_dec_ctl.scala 17:17] + node _T_3075 = and(_T_3074, _T_3068) @[dec_dec_ctl.scala 17:17] + node _T_3076 = and(_T_3075, _T_3069) @[dec_dec_ctl.scala 17:17] + node _T_3077 = and(_T_3076, _T_3070) @[dec_dec_ctl.scala 17:17] + node _T_3078 = and(_T_3077, _T_3072) @[dec_dec_ctl.scala 17:17] + io.out.sh1add <= _T_3078 @[dec_dec_ctl.scala 235:17] + node _T_3079 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3080 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_3081 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3082 = eq(_T_3081, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3083 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3084 = eq(_T_3083, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3085 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3086 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3087 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3088 = eq(_T_3087, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3089 = and(_T_3079, _T_3080) @[dec_dec_ctl.scala 17:17] + node _T_3090 = and(_T_3089, _T_3082) @[dec_dec_ctl.scala 17:17] + node _T_3091 = and(_T_3090, _T_3084) @[dec_dec_ctl.scala 17:17] + node _T_3092 = and(_T_3091, _T_3085) @[dec_dec_ctl.scala 17:17] + node _T_3093 = and(_T_3092, _T_3086) @[dec_dec_ctl.scala 17:17] + node _T_3094 = and(_T_3093, _T_3088) @[dec_dec_ctl.scala 17:17] + io.out.sh2add <= _T_3094 @[dec_dec_ctl.scala 237:17] + node _T_3095 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3096 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_3097 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_3098 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3099 = eq(_T_3098, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3100 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3101 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3102 = eq(_T_3101, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3103 = and(_T_3095, _T_3096) @[dec_dec_ctl.scala 17:17] + node _T_3104 = and(_T_3103, _T_3097) @[dec_dec_ctl.scala 17:17] + node _T_3105 = and(_T_3104, _T_3099) @[dec_dec_ctl.scala 17:17] + node _T_3106 = and(_T_3105, _T_3100) @[dec_dec_ctl.scala 17:17] + node _T_3107 = and(_T_3106, _T_3102) @[dec_dec_ctl.scala 17:17] + io.out.sh3add <= _T_3107 @[dec_dec_ctl.scala 239:17] + node _T_3108 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3109 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3110 = eq(_T_3109, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3111 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3112 = eq(_T_3111, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3113 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3114 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3115 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3116 = eq(_T_3115, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3117 = and(_T_3108, _T_3110) @[dec_dec_ctl.scala 17:17] + node _T_3118 = and(_T_3117, _T_3112) @[dec_dec_ctl.scala 17:17] + node _T_3119 = and(_T_3118, _T_3113) @[dec_dec_ctl.scala 17:17] + node _T_3120 = and(_T_3119, _T_3114) @[dec_dec_ctl.scala 17:17] + node _T_3121 = and(_T_3120, _T_3116) @[dec_dec_ctl.scala 17:17] + io.out.zba <= _T_3121 @[dec_dec_ctl.scala 241:14] + node _T_3122 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:34] + node _T_3123 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_3124 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3125 = eq(_T_3124, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3126 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3127 = eq(_T_3126, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3128 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3129 = and(_T_3122, _T_3123) @[dec_dec_ctl.scala 17:17] + node _T_3130 = and(_T_3129, _T_3125) @[dec_dec_ctl.scala 17:17] + node _T_3131 = and(_T_3130, _T_3127) @[dec_dec_ctl.scala 17:17] + node _T_3132 = and(_T_3131, _T_3128) @[dec_dec_ctl.scala 17:17] + node _T_3133 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3134 = eq(_T_3133, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3135 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3136 = eq(_T_3135, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3137 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3138 = eq(_T_3137, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3139 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3140 = eq(_T_3139, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3141 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3142 = eq(_T_3141, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3143 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3144 = and(_T_3134, _T_3136) @[dec_dec_ctl.scala 17:17] + node _T_3145 = and(_T_3144, _T_3138) @[dec_dec_ctl.scala 17:17] + node _T_3146 = and(_T_3145, _T_3140) @[dec_dec_ctl.scala 17:17] + node _T_3147 = and(_T_3146, _T_3142) @[dec_dec_ctl.scala 17:17] + node _T_3148 = and(_T_3147, _T_3143) @[dec_dec_ctl.scala 17:17] + node _T_3149 = or(_T_3132, _T_3148) @[dec_dec_ctl.scala 243:51] + node _T_3150 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3151 = eq(_T_3150, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3152 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3153 = eq(_T_3152, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3154 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3155 = eq(_T_3154, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3156 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3157 = eq(_T_3156, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3158 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_3159 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3160 = eq(_T_3159, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3161 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3162 = and(_T_3151, _T_3153) @[dec_dec_ctl.scala 17:17] + node _T_3163 = and(_T_3162, _T_3155) @[dec_dec_ctl.scala 17:17] + node _T_3164 = and(_T_3163, _T_3157) @[dec_dec_ctl.scala 17:17] + node _T_3165 = and(_T_3164, _T_3158) @[dec_dec_ctl.scala 17:17] + node _T_3166 = and(_T_3165, _T_3160) @[dec_dec_ctl.scala 17:17] + node _T_3167 = and(_T_3166, _T_3161) @[dec_dec_ctl.scala 17:17] + node _T_3168 = or(_T_3149, _T_3167) @[dec_dec_ctl.scala 243:89] + node _T_3169 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3170 = eq(_T_3169, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3171 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3172 = eq(_T_3171, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3173 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3174 = eq(_T_3173, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3175 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3176 = eq(_T_3175, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3177 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3178 = eq(_T_3177, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3179 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3180 = and(_T_3170, _T_3172) @[dec_dec_ctl.scala 17:17] + node _T_3181 = and(_T_3180, _T_3174) @[dec_dec_ctl.scala 17:17] + node _T_3182 = and(_T_3181, _T_3176) @[dec_dec_ctl.scala 17:17] + node _T_3183 = and(_T_3182, _T_3178) @[dec_dec_ctl.scala 17:17] + node _T_3184 = and(_T_3183, _T_3179) @[dec_dec_ctl.scala 17:17] + node _T_3185 = or(_T_3168, _T_3184) @[dec_dec_ctl.scala 244:44] + node _T_3186 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_3187 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3188 = eq(_T_3187, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3189 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3190 = and(_T_3186, _T_3188) @[dec_dec_ctl.scala 17:17] + node _T_3191 = and(_T_3190, _T_3189) @[dec_dec_ctl.scala 17:17] + node _T_3192 = or(_T_3185, _T_3191) @[dec_dec_ctl.scala 244:82] + node _T_3193 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3194 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_3195 = and(_T_3193, _T_3194) @[dec_dec_ctl.scala 17:17] + node _T_3196 = or(_T_3192, _T_3195) @[dec_dec_ctl.scala 245:28] + node _T_3197 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3198 = eq(_T_3197, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3199 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3200 = eq(_T_3199, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3201 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3202 = and(_T_3198, _T_3200) @[dec_dec_ctl.scala 17:17] + node _T_3203 = and(_T_3202, _T_3201) @[dec_dec_ctl.scala 17:17] + node _T_3204 = or(_T_3196, _T_3203) @[dec_dec_ctl.scala 245:49] + io.out.pm_alu <= _T_3204 @[dec_dec_ctl.scala 243:17] + node _T_3205 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3206 = eq(_T_3205, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3207 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3208 = eq(_T_3207, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3209 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3210 = eq(_T_3209, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3211 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:34] + node _T_3212 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3213 = eq(_T_3212, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3214 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3215 = eq(_T_3214, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3216 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3217 = eq(_T_3216, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3218 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_3219 = eq(_T_3218, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3220 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_3221 = eq(_T_3220, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3222 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_3223 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_3224 = eq(_T_3223, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3225 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_3226 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53] + node _T_3227 = eq(_T_3226, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3228 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53] + node _T_3229 = eq(_T_3228, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3230 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53] + node _T_3231 = eq(_T_3230, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3232 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53] + node _T_3233 = eq(_T_3232, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3234 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53] + node _T_3235 = eq(_T_3234, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3236 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3237 = eq(_T_3236, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3238 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53] + node _T_3239 = eq(_T_3238, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3240 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53] + node _T_3241 = eq(_T_3240, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3242 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53] + node _T_3243 = eq(_T_3242, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3244 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53] + node _T_3245 = eq(_T_3244, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3246 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53] + node _T_3247 = eq(_T_3246, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3248 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_3249 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3250 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3251 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3252 = eq(_T_3251, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3253 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3254 = eq(_T_3253, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3255 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3256 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3257 = and(_T_3206, _T_3208) @[dec_dec_ctl.scala 17:17] + node _T_3258 = and(_T_3257, _T_3210) @[dec_dec_ctl.scala 17:17] + node _T_3259 = and(_T_3258, _T_3211) @[dec_dec_ctl.scala 17:17] + node _T_3260 = and(_T_3259, _T_3213) @[dec_dec_ctl.scala 17:17] + node _T_3261 = and(_T_3260, _T_3215) @[dec_dec_ctl.scala 17:17] + node _T_3262 = and(_T_3261, _T_3217) @[dec_dec_ctl.scala 17:17] + node _T_3263 = and(_T_3262, _T_3219) @[dec_dec_ctl.scala 17:17] + node _T_3264 = and(_T_3263, _T_3221) @[dec_dec_ctl.scala 17:17] + node _T_3265 = and(_T_3264, _T_3222) @[dec_dec_ctl.scala 17:17] + node _T_3266 = and(_T_3265, _T_3224) @[dec_dec_ctl.scala 17:17] + node _T_3267 = and(_T_3266, _T_3225) @[dec_dec_ctl.scala 17:17] + node _T_3268 = and(_T_3267, _T_3227) @[dec_dec_ctl.scala 17:17] + node _T_3269 = and(_T_3268, _T_3229) @[dec_dec_ctl.scala 17:17] + node _T_3270 = and(_T_3269, _T_3231) @[dec_dec_ctl.scala 17:17] + node _T_3271 = and(_T_3270, _T_3233) @[dec_dec_ctl.scala 17:17] + node _T_3272 = and(_T_3271, _T_3235) @[dec_dec_ctl.scala 17:17] + node _T_3273 = and(_T_3272, _T_3237) @[dec_dec_ctl.scala 17:17] + node _T_3274 = and(_T_3273, _T_3239) @[dec_dec_ctl.scala 17:17] + node _T_3275 = and(_T_3274, _T_3241) @[dec_dec_ctl.scala 17:17] + node _T_3276 = and(_T_3275, _T_3243) @[dec_dec_ctl.scala 17:17] + node _T_3277 = and(_T_3276, _T_3245) @[dec_dec_ctl.scala 17:17] + node _T_3278 = and(_T_3277, _T_3247) @[dec_dec_ctl.scala 17:17] + node _T_3279 = and(_T_3278, _T_3248) @[dec_dec_ctl.scala 17:17] + node _T_3280 = and(_T_3279, _T_3249) @[dec_dec_ctl.scala 17:17] + node _T_3281 = and(_T_3280, _T_3250) @[dec_dec_ctl.scala 17:17] + node _T_3282 = and(_T_3281, _T_3252) @[dec_dec_ctl.scala 17:17] + node _T_3283 = and(_T_3282, _T_3254) @[dec_dec_ctl.scala 17:17] + node _T_3284 = and(_T_3283, _T_3255) @[dec_dec_ctl.scala 17:17] + node _T_3285 = and(_T_3284, _T_3256) @[dec_dec_ctl.scala 17:17] + node _T_3286 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3287 = eq(_T_3286, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3288 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3289 = eq(_T_3288, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3290 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3291 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:34] + node _T_3292 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3293 = eq(_T_3292, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3294 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3295 = eq(_T_3294, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3296 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3297 = eq(_T_3296, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3298 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_3299 = eq(_T_3298, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3300 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_3301 = eq(_T_3300, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3302 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_3303 = eq(_T_3302, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3304 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_3305 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_3306 = eq(_T_3305, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3307 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53] + node _T_3308 = eq(_T_3307, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3309 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53] + node _T_3310 = eq(_T_3309, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3311 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53] + node _T_3312 = eq(_T_3311, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3313 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53] + node _T_3314 = eq(_T_3313, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3315 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53] + node _T_3316 = eq(_T_3315, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3317 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3318 = eq(_T_3317, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3319 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53] + node _T_3320 = eq(_T_3319, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3321 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53] + node _T_3322 = eq(_T_3321, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3323 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53] + node _T_3324 = eq(_T_3323, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3325 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53] + node _T_3326 = eq(_T_3325, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3327 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53] + node _T_3328 = eq(_T_3327, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3329 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_3330 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3331 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3332 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3333 = eq(_T_3332, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3334 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3335 = eq(_T_3334, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3336 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3337 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3338 = and(_T_3287, _T_3289) @[dec_dec_ctl.scala 17:17] + node _T_3339 = and(_T_3338, _T_3290) @[dec_dec_ctl.scala 17:17] + node _T_3340 = and(_T_3339, _T_3291) @[dec_dec_ctl.scala 17:17] + node _T_3341 = and(_T_3340, _T_3293) @[dec_dec_ctl.scala 17:17] + node _T_3342 = and(_T_3341, _T_3295) @[dec_dec_ctl.scala 17:17] + node _T_3343 = and(_T_3342, _T_3297) @[dec_dec_ctl.scala 17:17] + node _T_3344 = and(_T_3343, _T_3299) @[dec_dec_ctl.scala 17:17] + node _T_3345 = and(_T_3344, _T_3301) @[dec_dec_ctl.scala 17:17] + node _T_3346 = and(_T_3345, _T_3303) @[dec_dec_ctl.scala 17:17] + node _T_3347 = and(_T_3346, _T_3304) @[dec_dec_ctl.scala 17:17] + node _T_3348 = and(_T_3347, _T_3306) @[dec_dec_ctl.scala 17:17] + node _T_3349 = and(_T_3348, _T_3308) @[dec_dec_ctl.scala 17:17] + node _T_3350 = and(_T_3349, _T_3310) @[dec_dec_ctl.scala 17:17] + node _T_3351 = and(_T_3350, _T_3312) @[dec_dec_ctl.scala 17:17] + node _T_3352 = and(_T_3351, _T_3314) @[dec_dec_ctl.scala 17:17] + node _T_3353 = and(_T_3352, _T_3316) @[dec_dec_ctl.scala 17:17] + node _T_3354 = and(_T_3353, _T_3318) @[dec_dec_ctl.scala 17:17] + node _T_3355 = and(_T_3354, _T_3320) @[dec_dec_ctl.scala 17:17] + node _T_3356 = and(_T_3355, _T_3322) @[dec_dec_ctl.scala 17:17] + node _T_3357 = and(_T_3356, _T_3324) @[dec_dec_ctl.scala 17:17] + node _T_3358 = and(_T_3357, _T_3326) @[dec_dec_ctl.scala 17:17] + node _T_3359 = and(_T_3358, _T_3328) @[dec_dec_ctl.scala 17:17] + node _T_3360 = and(_T_3359, _T_3329) @[dec_dec_ctl.scala 17:17] + node _T_3361 = and(_T_3360, _T_3330) @[dec_dec_ctl.scala 17:17] + node _T_3362 = and(_T_3361, _T_3331) @[dec_dec_ctl.scala 17:17] + node _T_3363 = and(_T_3362, _T_3333) @[dec_dec_ctl.scala 17:17] + node _T_3364 = and(_T_3363, _T_3335) @[dec_dec_ctl.scala 17:17] + node _T_3365 = and(_T_3364, _T_3336) @[dec_dec_ctl.scala 17:17] + node _T_3366 = and(_T_3365, _T_3337) @[dec_dec_ctl.scala 17:17] + node _T_3367 = or(_T_3285, _T_3366) @[dec_dec_ctl.scala 248:136] + node _T_3368 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3369 = eq(_T_3368, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3370 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3371 = eq(_T_3370, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3372 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3373 = eq(_T_3372, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3374 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3375 = eq(_T_3374, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3376 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3377 = eq(_T_3376, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3378 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3379 = eq(_T_3378, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3380 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3381 = eq(_T_3380, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3382 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_3383 = eq(_T_3382, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3384 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_3385 = eq(_T_3384, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3386 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_3387 = eq(_T_3386, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3388 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_3389 = eq(_T_3388, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3390 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53] + node _T_3391 = eq(_T_3390, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3392 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53] + node _T_3393 = eq(_T_3392, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3394 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53] + node _T_3395 = eq(_T_3394, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3396 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53] + node _T_3397 = eq(_T_3396, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3398 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53] + node _T_3399 = eq(_T_3398, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3400 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3401 = eq(_T_3400, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3402 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53] + node _T_3403 = eq(_T_3402, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3404 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53] + node _T_3405 = eq(_T_3404, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3406 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53] + node _T_3407 = eq(_T_3406, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3408 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53] + node _T_3409 = eq(_T_3408, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3410 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53] + node _T_3411 = eq(_T_3410, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3412 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3413 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3414 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3415 = eq(_T_3414, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3416 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3417 = eq(_T_3416, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3418 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3419 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3420 = and(_T_3369, _T_3371) @[dec_dec_ctl.scala 17:17] + node _T_3421 = and(_T_3420, _T_3373) @[dec_dec_ctl.scala 17:17] + node _T_3422 = and(_T_3421, _T_3375) @[dec_dec_ctl.scala 17:17] + node _T_3423 = and(_T_3422, _T_3377) @[dec_dec_ctl.scala 17:17] + node _T_3424 = and(_T_3423, _T_3379) @[dec_dec_ctl.scala 17:17] + node _T_3425 = and(_T_3424, _T_3381) @[dec_dec_ctl.scala 17:17] + node _T_3426 = and(_T_3425, _T_3383) @[dec_dec_ctl.scala 17:17] + node _T_3427 = and(_T_3426, _T_3385) @[dec_dec_ctl.scala 17:17] + node _T_3428 = and(_T_3427, _T_3387) @[dec_dec_ctl.scala 17:17] + node _T_3429 = and(_T_3428, _T_3389) @[dec_dec_ctl.scala 17:17] + node _T_3430 = and(_T_3429, _T_3391) @[dec_dec_ctl.scala 17:17] + node _T_3431 = and(_T_3430, _T_3393) @[dec_dec_ctl.scala 17:17] + node _T_3432 = and(_T_3431, _T_3395) @[dec_dec_ctl.scala 17:17] + node _T_3433 = and(_T_3432, _T_3397) @[dec_dec_ctl.scala 17:17] + node _T_3434 = and(_T_3433, _T_3399) @[dec_dec_ctl.scala 17:17] + node _T_3435 = and(_T_3434, _T_3401) @[dec_dec_ctl.scala 17:17] + node _T_3436 = and(_T_3435, _T_3403) @[dec_dec_ctl.scala 17:17] + node _T_3437 = and(_T_3436, _T_3405) @[dec_dec_ctl.scala 17:17] + node _T_3438 = and(_T_3437, _T_3407) @[dec_dec_ctl.scala 17:17] + node _T_3439 = and(_T_3438, _T_3409) @[dec_dec_ctl.scala 17:17] + node _T_3440 = and(_T_3439, _T_3411) @[dec_dec_ctl.scala 17:17] + node _T_3441 = and(_T_3440, _T_3412) @[dec_dec_ctl.scala 17:17] + node _T_3442 = and(_T_3441, _T_3413) @[dec_dec_ctl.scala 17:17] + node _T_3443 = and(_T_3442, _T_3415) @[dec_dec_ctl.scala 17:17] + node _T_3444 = and(_T_3443, _T_3417) @[dec_dec_ctl.scala 17:17] + node _T_3445 = and(_T_3444, _T_3418) @[dec_dec_ctl.scala 17:17] + node _T_3446 = and(_T_3445, _T_3419) @[dec_dec_ctl.scala 17:17] + node _T_3447 = or(_T_3367, _T_3446) @[dec_dec_ctl.scala 249:122] + node _T_3448 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3449 = eq(_T_3448, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3450 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3451 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3452 = eq(_T_3451, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3453 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3454 = eq(_T_3453, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3455 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3456 = eq(_T_3455, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3457 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_3458 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_3459 = eq(_T_3458, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3460 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_3461 = eq(_T_3460, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3462 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3463 = eq(_T_3462, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3464 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3465 = eq(_T_3464, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3466 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3467 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3468 = eq(_T_3467, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3469 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3470 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3471 = and(_T_3449, _T_3450) @[dec_dec_ctl.scala 17:17] + node _T_3472 = and(_T_3471, _T_3452) @[dec_dec_ctl.scala 17:17] + node _T_3473 = and(_T_3472, _T_3454) @[dec_dec_ctl.scala 17:17] + node _T_3474 = and(_T_3473, _T_3456) @[dec_dec_ctl.scala 17:17] + node _T_3475 = and(_T_3474, _T_3457) @[dec_dec_ctl.scala 17:17] + node _T_3476 = and(_T_3475, _T_3459) @[dec_dec_ctl.scala 17:17] + node _T_3477 = and(_T_3476, _T_3461) @[dec_dec_ctl.scala 17:17] + node _T_3478 = and(_T_3477, _T_3463) @[dec_dec_ctl.scala 17:17] + node _T_3479 = and(_T_3478, _T_3465) @[dec_dec_ctl.scala 17:17] + node _T_3480 = and(_T_3479, _T_3466) @[dec_dec_ctl.scala 17:17] + node _T_3481 = and(_T_3480, _T_3468) @[dec_dec_ctl.scala 17:17] + node _T_3482 = and(_T_3481, _T_3469) @[dec_dec_ctl.scala 17:17] + node _T_3483 = and(_T_3482, _T_3470) @[dec_dec_ctl.scala 17:17] + node _T_3484 = or(_T_3447, _T_3483) @[dec_dec_ctl.scala 250:119] + node _T_3485 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3486 = eq(_T_3485, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3487 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3488 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3489 = eq(_T_3488, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3490 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3491 = eq(_T_3490, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3492 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3493 = eq(_T_3492, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3494 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_3495 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_3496 = eq(_T_3495, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3497 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_3498 = eq(_T_3497, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3499 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3500 = eq(_T_3499, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3501 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3502 = eq(_T_3501, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3503 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3504 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3505 = eq(_T_3504, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3506 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3507 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3508 = and(_T_3486, _T_3487) @[dec_dec_ctl.scala 17:17] + node _T_3509 = and(_T_3508, _T_3489) @[dec_dec_ctl.scala 17:17] + node _T_3510 = and(_T_3509, _T_3491) @[dec_dec_ctl.scala 17:17] + node _T_3511 = and(_T_3510, _T_3493) @[dec_dec_ctl.scala 17:17] + node _T_3512 = and(_T_3511, _T_3494) @[dec_dec_ctl.scala 17:17] + node _T_3513 = and(_T_3512, _T_3496) @[dec_dec_ctl.scala 17:17] + node _T_3514 = and(_T_3513, _T_3498) @[dec_dec_ctl.scala 17:17] + node _T_3515 = and(_T_3514, _T_3500) @[dec_dec_ctl.scala 17:17] + node _T_3516 = and(_T_3515, _T_3502) @[dec_dec_ctl.scala 17:17] + node _T_3517 = and(_T_3516, _T_3503) @[dec_dec_ctl.scala 17:17] + node _T_3518 = and(_T_3517, _T_3505) @[dec_dec_ctl.scala 17:17] + node _T_3519 = and(_T_3518, _T_3506) @[dec_dec_ctl.scala 17:17] + node _T_3520 = and(_T_3519, _T_3507) @[dec_dec_ctl.scala 17:17] + node _T_3521 = or(_T_3484, _T_3520) @[dec_dec_ctl.scala 251:65] + node _T_3522 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3523 = eq(_T_3522, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3524 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3525 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3526 = eq(_T_3525, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3527 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3528 = eq(_T_3527, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3529 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3530 = eq(_T_3529, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3531 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_3532 = eq(_T_3531, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3533 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_3534 = eq(_T_3533, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3535 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_3536 = eq(_T_3535, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3537 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3538 = eq(_T_3537, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3539 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3540 = eq(_T_3539, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3541 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3542 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3543 = eq(_T_3542, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3544 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3545 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3546 = and(_T_3523, _T_3524) @[dec_dec_ctl.scala 17:17] + node _T_3547 = and(_T_3546, _T_3526) @[dec_dec_ctl.scala 17:17] + node _T_3548 = and(_T_3547, _T_3528) @[dec_dec_ctl.scala 17:17] + node _T_3549 = and(_T_3548, _T_3530) @[dec_dec_ctl.scala 17:17] + node _T_3550 = and(_T_3549, _T_3532) @[dec_dec_ctl.scala 17:17] + node _T_3551 = and(_T_3550, _T_3534) @[dec_dec_ctl.scala 17:17] + node _T_3552 = and(_T_3551, _T_3536) @[dec_dec_ctl.scala 17:17] + node _T_3553 = and(_T_3552, _T_3538) @[dec_dec_ctl.scala 17:17] + node _T_3554 = and(_T_3553, _T_3540) @[dec_dec_ctl.scala 17:17] + node _T_3555 = and(_T_3554, _T_3541) @[dec_dec_ctl.scala 17:17] + node _T_3556 = and(_T_3555, _T_3543) @[dec_dec_ctl.scala 17:17] + node _T_3557 = and(_T_3556, _T_3544) @[dec_dec_ctl.scala 17:17] + node _T_3558 = and(_T_3557, _T_3545) @[dec_dec_ctl.scala 17:17] + node _T_3559 = or(_T_3521, _T_3558) @[dec_dec_ctl.scala 251:127] + node _T_3560 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3561 = eq(_T_3560, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3562 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3563 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3564 = eq(_T_3563, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3565 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3566 = eq(_T_3565, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3567 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3568 = eq(_T_3567, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3569 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_3570 = eq(_T_3569, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3571 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_3572 = eq(_T_3571, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3573 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_3574 = eq(_T_3573, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3575 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3576 = eq(_T_3575, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3577 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3578 = eq(_T_3577, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3579 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3580 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3581 = eq(_T_3580, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3582 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3583 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3584 = and(_T_3561, _T_3562) @[dec_dec_ctl.scala 17:17] + node _T_3585 = and(_T_3584, _T_3564) @[dec_dec_ctl.scala 17:17] + node _T_3586 = and(_T_3585, _T_3566) @[dec_dec_ctl.scala 17:17] + node _T_3587 = and(_T_3586, _T_3568) @[dec_dec_ctl.scala 17:17] + node _T_3588 = and(_T_3587, _T_3570) @[dec_dec_ctl.scala 17:17] + node _T_3589 = and(_T_3588, _T_3572) @[dec_dec_ctl.scala 17:17] + node _T_3590 = and(_T_3589, _T_3574) @[dec_dec_ctl.scala 17:17] + node _T_3591 = and(_T_3590, _T_3576) @[dec_dec_ctl.scala 17:17] + node _T_3592 = and(_T_3591, _T_3578) @[dec_dec_ctl.scala 17:17] + node _T_3593 = and(_T_3592, _T_3579) @[dec_dec_ctl.scala 17:17] + node _T_3594 = and(_T_3593, _T_3581) @[dec_dec_ctl.scala 17:17] + node _T_3595 = and(_T_3594, _T_3582) @[dec_dec_ctl.scala 17:17] + node _T_3596 = and(_T_3595, _T_3583) @[dec_dec_ctl.scala 17:17] + node _T_3597 = or(_T_3559, _T_3596) @[dec_dec_ctl.scala 252:66] + node _T_3598 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3599 = eq(_T_3598, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3600 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3601 = eq(_T_3600, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3602 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3603 = eq(_T_3602, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3604 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3605 = eq(_T_3604, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3606 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3607 = eq(_T_3606, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3608 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_3609 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_3610 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3611 = eq(_T_3610, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3612 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3613 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3614 = eq(_T_3613, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3615 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3616 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3617 = and(_T_3599, _T_3601) @[dec_dec_ctl.scala 17:17] + node _T_3618 = and(_T_3617, _T_3603) @[dec_dec_ctl.scala 17:17] + node _T_3619 = and(_T_3618, _T_3605) @[dec_dec_ctl.scala 17:17] + node _T_3620 = and(_T_3619, _T_3607) @[dec_dec_ctl.scala 17:17] + node _T_3621 = and(_T_3620, _T_3608) @[dec_dec_ctl.scala 17:17] + node _T_3622 = and(_T_3621, _T_3609) @[dec_dec_ctl.scala 17:17] + node _T_3623 = and(_T_3622, _T_3611) @[dec_dec_ctl.scala 17:17] + node _T_3624 = and(_T_3623, _T_3612) @[dec_dec_ctl.scala 17:17] + node _T_3625 = and(_T_3624, _T_3614) @[dec_dec_ctl.scala 17:17] + node _T_3626 = and(_T_3625, _T_3615) @[dec_dec_ctl.scala 17:17] + node _T_3627 = and(_T_3626, _T_3616) @[dec_dec_ctl.scala 17:17] + node _T_3628 = or(_T_3597, _T_3627) @[dec_dec_ctl.scala 252:129] + node _T_3629 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3630 = eq(_T_3629, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3631 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3632 = eq(_T_3631, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3633 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3634 = eq(_T_3633, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3635 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3636 = eq(_T_3635, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3637 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3638 = eq(_T_3637, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3639 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_3640 = eq(_T_3639, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3641 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3642 = eq(_T_3641, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3643 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3644 = eq(_T_3643, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3645 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3646 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3647 = eq(_T_3646, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3648 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3649 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3650 = and(_T_3630, _T_3632) @[dec_dec_ctl.scala 17:17] + node _T_3651 = and(_T_3650, _T_3634) @[dec_dec_ctl.scala 17:17] + node _T_3652 = and(_T_3651, _T_3636) @[dec_dec_ctl.scala 17:17] + node _T_3653 = and(_T_3652, _T_3638) @[dec_dec_ctl.scala 17:17] + node _T_3654 = and(_T_3653, _T_3640) @[dec_dec_ctl.scala 17:17] + node _T_3655 = and(_T_3654, _T_3642) @[dec_dec_ctl.scala 17:17] + node _T_3656 = and(_T_3655, _T_3644) @[dec_dec_ctl.scala 17:17] + node _T_3657 = and(_T_3656, _T_3645) @[dec_dec_ctl.scala 17:17] + node _T_3658 = and(_T_3657, _T_3647) @[dec_dec_ctl.scala 17:17] + node _T_3659 = and(_T_3658, _T_3648) @[dec_dec_ctl.scala 17:17] + node _T_3660 = and(_T_3659, _T_3649) @[dec_dec_ctl.scala 17:17] + node _T_3661 = or(_T_3628, _T_3660) @[dec_dec_ctl.scala 253:58] + node _T_3662 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3663 = eq(_T_3662, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3664 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3665 = eq(_T_3664, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3666 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3667 = eq(_T_3666, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3668 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3669 = eq(_T_3668, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3670 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3671 = eq(_T_3670, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3672 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3673 = eq(_T_3672, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3674 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_3675 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3676 = eq(_T_3675, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3677 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3678 = eq(_T_3677, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3679 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3680 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3681 = eq(_T_3680, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3682 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3683 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3684 = and(_T_3663, _T_3665) @[dec_dec_ctl.scala 17:17] + node _T_3685 = and(_T_3684, _T_3667) @[dec_dec_ctl.scala 17:17] + node _T_3686 = and(_T_3685, _T_3669) @[dec_dec_ctl.scala 17:17] + node _T_3687 = and(_T_3686, _T_3671) @[dec_dec_ctl.scala 17:17] + node _T_3688 = and(_T_3687, _T_3673) @[dec_dec_ctl.scala 17:17] + node _T_3689 = and(_T_3688, _T_3674) @[dec_dec_ctl.scala 17:17] + node _T_3690 = and(_T_3689, _T_3676) @[dec_dec_ctl.scala 17:17] + node _T_3691 = and(_T_3690, _T_3678) @[dec_dec_ctl.scala 17:17] + node _T_3692 = and(_T_3691, _T_3679) @[dec_dec_ctl.scala 17:17] + node _T_3693 = and(_T_3692, _T_3681) @[dec_dec_ctl.scala 17:17] + node _T_3694 = and(_T_3693, _T_3682) @[dec_dec_ctl.scala 17:17] + node _T_3695 = and(_T_3694, _T_3683) @[dec_dec_ctl.scala 17:17] + node _T_3696 = or(_T_3661, _T_3695) @[dec_dec_ctl.scala 253:114] + node _T_3697 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3698 = eq(_T_3697, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3699 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3700 = eq(_T_3699, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3701 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3702 = eq(_T_3701, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3703 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3704 = eq(_T_3703, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3705 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3706 = eq(_T_3705, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3707 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3708 = eq(_T_3707, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3709 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_3710 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3711 = eq(_T_3710, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3712 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3713 = eq(_T_3712, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3714 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3715 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3716 = eq(_T_3715, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3717 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3718 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3719 = and(_T_3698, _T_3700) @[dec_dec_ctl.scala 17:17] + node _T_3720 = and(_T_3719, _T_3702) @[dec_dec_ctl.scala 17:17] + node _T_3721 = and(_T_3720, _T_3704) @[dec_dec_ctl.scala 17:17] + node _T_3722 = and(_T_3721, _T_3706) @[dec_dec_ctl.scala 17:17] + node _T_3723 = and(_T_3722, _T_3708) @[dec_dec_ctl.scala 17:17] + node _T_3724 = and(_T_3723, _T_3709) @[dec_dec_ctl.scala 17:17] + node _T_3725 = and(_T_3724, _T_3711) @[dec_dec_ctl.scala 17:17] + node _T_3726 = and(_T_3725, _T_3713) @[dec_dec_ctl.scala 17:17] + node _T_3727 = and(_T_3726, _T_3714) @[dec_dec_ctl.scala 17:17] + node _T_3728 = and(_T_3727, _T_3716) @[dec_dec_ctl.scala 17:17] + node _T_3729 = and(_T_3728, _T_3717) @[dec_dec_ctl.scala 17:17] + node _T_3730 = and(_T_3729, _T_3718) @[dec_dec_ctl.scala 17:17] + node _T_3731 = or(_T_3696, _T_3730) @[dec_dec_ctl.scala 254:63] + node _T_3732 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3733 = eq(_T_3732, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3734 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3735 = eq(_T_3734, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3736 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3737 = eq(_T_3736, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3738 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3739 = eq(_T_3738, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3740 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3741 = eq(_T_3740, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3742 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3743 = eq(_T_3742, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3744 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3745 = eq(_T_3744, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3746 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3747 = eq(_T_3746, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3748 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3749 = eq(_T_3748, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3750 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3751 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3752 = eq(_T_3751, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3753 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3754 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3755 = and(_T_3733, _T_3735) @[dec_dec_ctl.scala 17:17] + node _T_3756 = and(_T_3755, _T_3737) @[dec_dec_ctl.scala 17:17] + node _T_3757 = and(_T_3756, _T_3739) @[dec_dec_ctl.scala 17:17] + node _T_3758 = and(_T_3757, _T_3741) @[dec_dec_ctl.scala 17:17] + node _T_3759 = and(_T_3758, _T_3743) @[dec_dec_ctl.scala 17:17] + node _T_3760 = and(_T_3759, _T_3745) @[dec_dec_ctl.scala 17:17] + node _T_3761 = and(_T_3760, _T_3747) @[dec_dec_ctl.scala 17:17] + node _T_3762 = and(_T_3761, _T_3749) @[dec_dec_ctl.scala 17:17] + node _T_3763 = and(_T_3762, _T_3750) @[dec_dec_ctl.scala 17:17] + node _T_3764 = and(_T_3763, _T_3752) @[dec_dec_ctl.scala 17:17] + node _T_3765 = and(_T_3764, _T_3753) @[dec_dec_ctl.scala 17:17] + node _T_3766 = and(_T_3765, _T_3754) @[dec_dec_ctl.scala 17:17] + node _T_3767 = or(_T_3731, _T_3766) @[dec_dec_ctl.scala 254:123] + node _T_3768 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3769 = eq(_T_3768, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3770 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3771 = eq(_T_3770, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3772 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3773 = eq(_T_3772, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3774 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3775 = eq(_T_3774, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3776 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3777 = eq(_T_3776, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3778 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_3779 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3780 = eq(_T_3779, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3781 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3782 = eq(_T_3781, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3783 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3784 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3785 = eq(_T_3784, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3786 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3787 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3788 = and(_T_3769, _T_3771) @[dec_dec_ctl.scala 17:17] + node _T_3789 = and(_T_3788, _T_3773) @[dec_dec_ctl.scala 17:17] + node _T_3790 = and(_T_3789, _T_3775) @[dec_dec_ctl.scala 17:17] + node _T_3791 = and(_T_3790, _T_3777) @[dec_dec_ctl.scala 17:17] + node _T_3792 = and(_T_3791, _T_3778) @[dec_dec_ctl.scala 17:17] + node _T_3793 = and(_T_3792, _T_3780) @[dec_dec_ctl.scala 17:17] + node _T_3794 = and(_T_3793, _T_3782) @[dec_dec_ctl.scala 17:17] + node _T_3795 = and(_T_3794, _T_3783) @[dec_dec_ctl.scala 17:17] + node _T_3796 = and(_T_3795, _T_3785) @[dec_dec_ctl.scala 17:17] + node _T_3797 = and(_T_3796, _T_3786) @[dec_dec_ctl.scala 17:17] + node _T_3798 = and(_T_3797, _T_3787) @[dec_dec_ctl.scala 17:17] + node _T_3799 = or(_T_3767, _T_3798) @[dec_dec_ctl.scala 255:64] + node _T_3800 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3801 = eq(_T_3800, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3802 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3803 = eq(_T_3802, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3804 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3805 = eq(_T_3804, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3806 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3807 = eq(_T_3806, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3808 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3809 = eq(_T_3808, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3810 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3811 = eq(_T_3810, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3812 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_3813 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3814 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3815 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3816 = eq(_T_3815, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3817 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3818 = eq(_T_3817, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3819 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3820 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3821 = and(_T_3801, _T_3803) @[dec_dec_ctl.scala 17:17] + node _T_3822 = and(_T_3821, _T_3805) @[dec_dec_ctl.scala 17:17] + node _T_3823 = and(_T_3822, _T_3807) @[dec_dec_ctl.scala 17:17] + node _T_3824 = and(_T_3823, _T_3809) @[dec_dec_ctl.scala 17:17] + node _T_3825 = and(_T_3824, _T_3811) @[dec_dec_ctl.scala 17:17] + node _T_3826 = and(_T_3825, _T_3812) @[dec_dec_ctl.scala 17:17] + node _T_3827 = and(_T_3826, _T_3813) @[dec_dec_ctl.scala 17:17] + node _T_3828 = and(_T_3827, _T_3814) @[dec_dec_ctl.scala 17:17] + node _T_3829 = and(_T_3828, _T_3816) @[dec_dec_ctl.scala 17:17] + node _T_3830 = and(_T_3829, _T_3818) @[dec_dec_ctl.scala 17:17] + node _T_3831 = and(_T_3830, _T_3819) @[dec_dec_ctl.scala 17:17] + node _T_3832 = and(_T_3831, _T_3820) @[dec_dec_ctl.scala 17:17] + node _T_3833 = or(_T_3799, _T_3832) @[dec_dec_ctl.scala 255:119] + node _T_3834 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3835 = eq(_T_3834, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3836 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3837 = eq(_T_3836, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3838 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3839 = eq(_T_3838, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3840 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3841 = eq(_T_3840, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3842 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3843 = eq(_T_3842, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3844 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_3845 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3846 = eq(_T_3845, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3847 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3848 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3849 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3850 = eq(_T_3849, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3851 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3852 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3853 = and(_T_3835, _T_3837) @[dec_dec_ctl.scala 17:17] + node _T_3854 = and(_T_3853, _T_3839) @[dec_dec_ctl.scala 17:17] + node _T_3855 = and(_T_3854, _T_3841) @[dec_dec_ctl.scala 17:17] + node _T_3856 = and(_T_3855, _T_3843) @[dec_dec_ctl.scala 17:17] + node _T_3857 = and(_T_3856, _T_3844) @[dec_dec_ctl.scala 17:17] + node _T_3858 = and(_T_3857, _T_3846) @[dec_dec_ctl.scala 17:17] + node _T_3859 = and(_T_3858, _T_3847) @[dec_dec_ctl.scala 17:17] + node _T_3860 = and(_T_3859, _T_3848) @[dec_dec_ctl.scala 17:17] + node _T_3861 = and(_T_3860, _T_3850) @[dec_dec_ctl.scala 17:17] + node _T_3862 = and(_T_3861, _T_3851) @[dec_dec_ctl.scala 17:17] + node _T_3863 = and(_T_3862, _T_3852) @[dec_dec_ctl.scala 17:17] + node _T_3864 = or(_T_3833, _T_3863) @[dec_dec_ctl.scala 256:61] + node _T_3865 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3866 = eq(_T_3865, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3867 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_3868 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3869 = eq(_T_3868, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3870 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_3871 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3872 = eq(_T_3871, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3873 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3874 = eq(_T_3873, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3875 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3876 = eq(_T_3875, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3877 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_3878 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3879 = eq(_T_3878, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3880 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3881 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3882 = eq(_T_3881, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3883 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3884 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3885 = and(_T_3866, _T_3867) @[dec_dec_ctl.scala 17:17] + node _T_3886 = and(_T_3885, _T_3869) @[dec_dec_ctl.scala 17:17] + node _T_3887 = and(_T_3886, _T_3870) @[dec_dec_ctl.scala 17:17] + node _T_3888 = and(_T_3887, _T_3872) @[dec_dec_ctl.scala 17:17] + node _T_3889 = and(_T_3888, _T_3874) @[dec_dec_ctl.scala 17:17] + node _T_3890 = and(_T_3889, _T_3876) @[dec_dec_ctl.scala 17:17] + node _T_3891 = and(_T_3890, _T_3877) @[dec_dec_ctl.scala 17:17] + node _T_3892 = and(_T_3891, _T_3879) @[dec_dec_ctl.scala 17:17] + node _T_3893 = and(_T_3892, _T_3880) @[dec_dec_ctl.scala 17:17] + node _T_3894 = and(_T_3893, _T_3882) @[dec_dec_ctl.scala 17:17] + node _T_3895 = and(_T_3894, _T_3883) @[dec_dec_ctl.scala 17:17] + node _T_3896 = and(_T_3895, _T_3884) @[dec_dec_ctl.scala 17:17] + node _T_3897 = or(_T_3864, _T_3896) @[dec_dec_ctl.scala 256:115] + node _T_3898 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3899 = eq(_T_3898, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3900 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3901 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3902 = eq(_T_3901, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3903 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_3904 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3905 = eq(_T_3904, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3906 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3907 = eq(_T_3906, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3908 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3909 = eq(_T_3908, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3910 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3911 = eq(_T_3910, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3912 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3913 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3914 = eq(_T_3913, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3915 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3916 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3917 = and(_T_3899, _T_3900) @[dec_dec_ctl.scala 17:17] + node _T_3918 = and(_T_3917, _T_3902) @[dec_dec_ctl.scala 17:17] + node _T_3919 = and(_T_3918, _T_3903) @[dec_dec_ctl.scala 17:17] + node _T_3920 = and(_T_3919, _T_3905) @[dec_dec_ctl.scala 17:17] + node _T_3921 = and(_T_3920, _T_3907) @[dec_dec_ctl.scala 17:17] + node _T_3922 = and(_T_3921, _T_3909) @[dec_dec_ctl.scala 17:17] + node _T_3923 = and(_T_3922, _T_3911) @[dec_dec_ctl.scala 17:17] + node _T_3924 = and(_T_3923, _T_3912) @[dec_dec_ctl.scala 17:17] + node _T_3925 = and(_T_3924, _T_3914) @[dec_dec_ctl.scala 17:17] + node _T_3926 = and(_T_3925, _T_3915) @[dec_dec_ctl.scala 17:17] + node _T_3927 = and(_T_3926, _T_3916) @[dec_dec_ctl.scala 17:17] + node _T_3928 = or(_T_3897, _T_3927) @[dec_dec_ctl.scala 257:61] + node _T_3929 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3930 = eq(_T_3929, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3931 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3932 = eq(_T_3931, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3933 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3934 = eq(_T_3933, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3935 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3936 = eq(_T_3935, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3937 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3938 = eq(_T_3937, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3939 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3940 = eq(_T_3939, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3941 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3942 = eq(_T_3941, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3943 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3944 = eq(_T_3943, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3945 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3946 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3947 = eq(_T_3946, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3948 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3949 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3950 = and(_T_3930, _T_3932) @[dec_dec_ctl.scala 17:17] + node _T_3951 = and(_T_3950, _T_3934) @[dec_dec_ctl.scala 17:17] + node _T_3952 = and(_T_3951, _T_3936) @[dec_dec_ctl.scala 17:17] + node _T_3953 = and(_T_3952, _T_3938) @[dec_dec_ctl.scala 17:17] + node _T_3954 = and(_T_3953, _T_3940) @[dec_dec_ctl.scala 17:17] + node _T_3955 = and(_T_3954, _T_3942) @[dec_dec_ctl.scala 17:17] + node _T_3956 = and(_T_3955, _T_3944) @[dec_dec_ctl.scala 17:17] + node _T_3957 = and(_T_3956, _T_3945) @[dec_dec_ctl.scala 17:17] + node _T_3958 = and(_T_3957, _T_3947) @[dec_dec_ctl.scala 17:17] + node _T_3959 = and(_T_3958, _T_3948) @[dec_dec_ctl.scala 17:17] + node _T_3960 = and(_T_3959, _T_3949) @[dec_dec_ctl.scala 17:17] + node _T_3961 = or(_T_3928, _T_3960) @[dec_dec_ctl.scala 257:116] + node _T_3962 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3963 = eq(_T_3962, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3964 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3965 = eq(_T_3964, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3966 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3967 = eq(_T_3966, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3968 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3969 = eq(_T_3968, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3970 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3971 = eq(_T_3970, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3972 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3973 = eq(_T_3972, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3974 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3975 = eq(_T_3974, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3976 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3977 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3978 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3979 = eq(_T_3978, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3980 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3981 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3982 = and(_T_3963, _T_3965) @[dec_dec_ctl.scala 17:17] + node _T_3983 = and(_T_3982, _T_3967) @[dec_dec_ctl.scala 17:17] + node _T_3984 = and(_T_3983, _T_3969) @[dec_dec_ctl.scala 17:17] + node _T_3985 = and(_T_3984, _T_3971) @[dec_dec_ctl.scala 17:17] + node _T_3986 = and(_T_3985, _T_3973) @[dec_dec_ctl.scala 17:17] + node _T_3987 = and(_T_3986, _T_3975) @[dec_dec_ctl.scala 17:17] + node _T_3988 = and(_T_3987, _T_3976) @[dec_dec_ctl.scala 17:17] + node _T_3989 = and(_T_3988, _T_3977) @[dec_dec_ctl.scala 17:17] + node _T_3990 = and(_T_3989, _T_3979) @[dec_dec_ctl.scala 17:17] + node _T_3991 = and(_T_3990, _T_3980) @[dec_dec_ctl.scala 17:17] + node _T_3992 = and(_T_3991, _T_3981) @[dec_dec_ctl.scala 17:17] + node _T_3993 = or(_T_3961, _T_3992) @[dec_dec_ctl.scala 258:59] + node _T_3994 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3995 = eq(_T_3994, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3996 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3997 = eq(_T_3996, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3998 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3999 = eq(_T_3998, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4000 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_4001 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4002 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4003 = eq(_T_4002, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4004 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4005 = eq(_T_4004, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4006 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4007 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4008 = and(_T_3995, _T_3997) @[dec_dec_ctl.scala 17:17] + node _T_4009 = and(_T_4008, _T_3999) @[dec_dec_ctl.scala 17:17] + node _T_4010 = and(_T_4009, _T_4000) @[dec_dec_ctl.scala 17:17] + node _T_4011 = and(_T_4010, _T_4001) @[dec_dec_ctl.scala 17:17] + node _T_4012 = and(_T_4011, _T_4003) @[dec_dec_ctl.scala 17:17] + node _T_4013 = and(_T_4012, _T_4005) @[dec_dec_ctl.scala 17:17] + node _T_4014 = and(_T_4013, _T_4006) @[dec_dec_ctl.scala 17:17] + node _T_4015 = and(_T_4014, _T_4007) @[dec_dec_ctl.scala 17:17] + node _T_4016 = or(_T_3993, _T_4015) @[dec_dec_ctl.scala 258:114] + node _T_4017 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_4018 = eq(_T_4017, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4019 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_4020 = eq(_T_4019, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4021 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_4022 = eq(_T_4021, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4023 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_4024 = eq(_T_4023, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4025 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_4026 = eq(_T_4025, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4027 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_4028 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4029 = eq(_T_4028, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4030 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4031 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_4032 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4033 = eq(_T_4032, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4034 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4035 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4036 = and(_T_4018, _T_4020) @[dec_dec_ctl.scala 17:17] + node _T_4037 = and(_T_4036, _T_4022) @[dec_dec_ctl.scala 17:17] + node _T_4038 = and(_T_4037, _T_4024) @[dec_dec_ctl.scala 17:17] + node _T_4039 = and(_T_4038, _T_4026) @[dec_dec_ctl.scala 17:17] + node _T_4040 = and(_T_4039, _T_4027) @[dec_dec_ctl.scala 17:17] + node _T_4041 = and(_T_4040, _T_4029) @[dec_dec_ctl.scala 17:17] + node _T_4042 = and(_T_4041, _T_4030) @[dec_dec_ctl.scala 17:17] + node _T_4043 = and(_T_4042, _T_4031) @[dec_dec_ctl.scala 17:17] + node _T_4044 = and(_T_4043, _T_4033) @[dec_dec_ctl.scala 17:17] + node _T_4045 = and(_T_4044, _T_4034) @[dec_dec_ctl.scala 17:17] + node _T_4046 = and(_T_4045, _T_4035) @[dec_dec_ctl.scala 17:17] + node _T_4047 = or(_T_4016, _T_4046) @[dec_dec_ctl.scala 259:46] + node _T_4048 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_4049 = eq(_T_4048, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4050 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_4051 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_4052 = eq(_T_4051, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4053 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_4054 = eq(_T_4053, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4055 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_4056 = eq(_T_4055, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4057 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_4058 = eq(_T_4057, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4059 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_4060 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4061 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_4062 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4063 = eq(_T_4062, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4064 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4065 = eq(_T_4064, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4066 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4067 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4068 = and(_T_4049, _T_4050) @[dec_dec_ctl.scala 17:17] + node _T_4069 = and(_T_4068, _T_4052) @[dec_dec_ctl.scala 17:17] + node _T_4070 = and(_T_4069, _T_4054) @[dec_dec_ctl.scala 17:17] + node _T_4071 = and(_T_4070, _T_4056) @[dec_dec_ctl.scala 17:17] + node _T_4072 = and(_T_4071, _T_4058) @[dec_dec_ctl.scala 17:17] + node _T_4073 = and(_T_4072, _T_4059) @[dec_dec_ctl.scala 17:17] + node _T_4074 = and(_T_4073, _T_4060) @[dec_dec_ctl.scala 17:17] + node _T_4075 = and(_T_4074, _T_4061) @[dec_dec_ctl.scala 17:17] + node _T_4076 = and(_T_4075, _T_4063) @[dec_dec_ctl.scala 17:17] + node _T_4077 = and(_T_4076, _T_4065) @[dec_dec_ctl.scala 17:17] + node _T_4078 = and(_T_4077, _T_4066) @[dec_dec_ctl.scala 17:17] + node _T_4079 = and(_T_4078, _T_4067) @[dec_dec_ctl.scala 17:17] + node _T_4080 = or(_T_4047, _T_4079) @[dec_dec_ctl.scala 259:100] + node _T_4081 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_4082 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_4083 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4084 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4085 = eq(_T_4084, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4086 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4087 = eq(_T_4086, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4088 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4089 = eq(_T_4088, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4090 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4091 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4092 = and(_T_4081, _T_4082) @[dec_dec_ctl.scala 17:17] + node _T_4093 = and(_T_4092, _T_4083) @[dec_dec_ctl.scala 17:17] + node _T_4094 = and(_T_4093, _T_4085) @[dec_dec_ctl.scala 17:17] + node _T_4095 = and(_T_4094, _T_4087) @[dec_dec_ctl.scala 17:17] + node _T_4096 = and(_T_4095, _T_4089) @[dec_dec_ctl.scala 17:17] + node _T_4097 = and(_T_4096, _T_4090) @[dec_dec_ctl.scala 17:17] + node _T_4098 = and(_T_4097, _T_4091) @[dec_dec_ctl.scala 17:17] + node _T_4099 = or(_T_4080, _T_4098) @[dec_dec_ctl.scala 260:60] + node _T_4100 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_4101 = eq(_T_4100, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4102 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_4103 = eq(_T_4102, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4104 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4105 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4106 = eq(_T_4105, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4107 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4108 = eq(_T_4107, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4109 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4110 = eq(_T_4109, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4111 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4112 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4113 = and(_T_4101, _T_4103) @[dec_dec_ctl.scala 17:17] + node _T_4114 = and(_T_4113, _T_4104) @[dec_dec_ctl.scala 17:17] + node _T_4115 = and(_T_4114, _T_4106) @[dec_dec_ctl.scala 17:17] + node _T_4116 = and(_T_4115, _T_4108) @[dec_dec_ctl.scala 17:17] + node _T_4117 = and(_T_4116, _T_4110) @[dec_dec_ctl.scala 17:17] + node _T_4118 = and(_T_4117, _T_4111) @[dec_dec_ctl.scala 17:17] + node _T_4119 = and(_T_4118, _T_4112) @[dec_dec_ctl.scala 17:17] + node _T_4120 = or(_T_4099, _T_4119) @[dec_dec_ctl.scala 260:97] + node _T_4121 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_4122 = eq(_T_4121, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4123 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4124 = eq(_T_4123, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4125 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_4126 = eq(_T_4125, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4127 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_4128 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4129 = eq(_T_4128, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4130 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4131 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4132 = and(_T_4122, _T_4124) @[dec_dec_ctl.scala 17:17] + node _T_4133 = and(_T_4132, _T_4126) @[dec_dec_ctl.scala 17:17] + node _T_4134 = and(_T_4133, _T_4127) @[dec_dec_ctl.scala 17:17] + node _T_4135 = and(_T_4134, _T_4129) @[dec_dec_ctl.scala 17:17] + node _T_4136 = and(_T_4135, _T_4130) @[dec_dec_ctl.scala 17:17] + node _T_4137 = and(_T_4136, _T_4131) @[dec_dec_ctl.scala 17:17] + node _T_4138 = or(_T_4120, _T_4137) @[dec_dec_ctl.scala 261:43] + node _T_4139 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_4140 = eq(_T_4139, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4141 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_4142 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_4143 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4144 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4145 = eq(_T_4144, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4146 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4147 = eq(_T_4146, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4148 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4149 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4150 = and(_T_4140, _T_4141) @[dec_dec_ctl.scala 17:17] + node _T_4151 = and(_T_4150, _T_4142) @[dec_dec_ctl.scala 17:17] + node _T_4152 = and(_T_4151, _T_4143) @[dec_dec_ctl.scala 17:17] + node _T_4153 = and(_T_4152, _T_4145) @[dec_dec_ctl.scala 17:17] + node _T_4154 = and(_T_4153, _T_4147) @[dec_dec_ctl.scala 17:17] + node _T_4155 = and(_T_4154, _T_4148) @[dec_dec_ctl.scala 17:17] + node _T_4156 = and(_T_4155, _T_4149) @[dec_dec_ctl.scala 17:17] + node _T_4157 = or(_T_4138, _T_4156) @[dec_dec_ctl.scala 261:79] + node _T_4158 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_4159 = eq(_T_4158, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4160 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_4161 = eq(_T_4160, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4162 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_4163 = eq(_T_4162, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4164 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_4165 = eq(_T_4164, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4166 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_4167 = eq(_T_4166, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4168 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_4169 = eq(_T_4168, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4170 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_4171 = eq(_T_4170, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4172 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_4173 = eq(_T_4172, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4174 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_4175 = eq(_T_4174, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4176 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_4177 = eq(_T_4176, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4178 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_4179 = eq(_T_4178, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4180 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_4181 = eq(_T_4180, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4182 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53] + node _T_4183 = eq(_T_4182, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4184 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53] + node _T_4185 = eq(_T_4184, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4186 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53] + node _T_4187 = eq(_T_4186, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4188 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53] + node _T_4189 = eq(_T_4188, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4190 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53] + node _T_4191 = eq(_T_4190, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4192 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_4193 = eq(_T_4192, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4194 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_4195 = eq(_T_4194, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4196 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53] + node _T_4197 = eq(_T_4196, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4198 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53] + node _T_4199 = eq(_T_4198, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4200 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53] + node _T_4201 = eq(_T_4200, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4202 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53] + node _T_4203 = eq(_T_4202, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4204 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53] + node _T_4205 = eq(_T_4204, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4206 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4207 = eq(_T_4206, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4208 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_4209 = eq(_T_4208, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4210 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4211 = eq(_T_4210, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4212 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_4213 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_4214 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4215 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4216 = and(_T_4159, _T_4161) @[dec_dec_ctl.scala 17:17] + node _T_4217 = and(_T_4216, _T_4163) @[dec_dec_ctl.scala 17:17] + node _T_4218 = and(_T_4217, _T_4165) @[dec_dec_ctl.scala 17:17] + node _T_4219 = and(_T_4218, _T_4167) @[dec_dec_ctl.scala 17:17] + node _T_4220 = and(_T_4219, _T_4169) @[dec_dec_ctl.scala 17:17] + node _T_4221 = and(_T_4220, _T_4171) @[dec_dec_ctl.scala 17:17] + node _T_4222 = and(_T_4221, _T_4173) @[dec_dec_ctl.scala 17:17] + node _T_4223 = and(_T_4222, _T_4175) @[dec_dec_ctl.scala 17:17] + node _T_4224 = and(_T_4223, _T_4177) @[dec_dec_ctl.scala 17:17] + node _T_4225 = and(_T_4224, _T_4179) @[dec_dec_ctl.scala 17:17] + node _T_4226 = and(_T_4225, _T_4181) @[dec_dec_ctl.scala 17:17] + node _T_4227 = and(_T_4226, _T_4183) @[dec_dec_ctl.scala 17:17] + node _T_4228 = and(_T_4227, _T_4185) @[dec_dec_ctl.scala 17:17] + node _T_4229 = and(_T_4228, _T_4187) @[dec_dec_ctl.scala 17:17] + node _T_4230 = and(_T_4229, _T_4189) @[dec_dec_ctl.scala 17:17] + node _T_4231 = and(_T_4230, _T_4191) @[dec_dec_ctl.scala 17:17] + node _T_4232 = and(_T_4231, _T_4193) @[dec_dec_ctl.scala 17:17] + node _T_4233 = and(_T_4232, _T_4195) @[dec_dec_ctl.scala 17:17] + node _T_4234 = and(_T_4233, _T_4197) @[dec_dec_ctl.scala 17:17] + node _T_4235 = and(_T_4234, _T_4199) @[dec_dec_ctl.scala 17:17] + node _T_4236 = and(_T_4235, _T_4201) @[dec_dec_ctl.scala 17:17] + node _T_4237 = and(_T_4236, _T_4203) @[dec_dec_ctl.scala 17:17] + node _T_4238 = and(_T_4237, _T_4205) @[dec_dec_ctl.scala 17:17] + node _T_4239 = and(_T_4238, _T_4207) @[dec_dec_ctl.scala 17:17] + node _T_4240 = and(_T_4239, _T_4209) @[dec_dec_ctl.scala 17:17] + node _T_4241 = and(_T_4240, _T_4211) @[dec_dec_ctl.scala 17:17] + node _T_4242 = and(_T_4241, _T_4212) @[dec_dec_ctl.scala 17:17] + node _T_4243 = and(_T_4242, _T_4213) @[dec_dec_ctl.scala 17:17] + node _T_4244 = and(_T_4243, _T_4214) @[dec_dec_ctl.scala 17:17] + node _T_4245 = and(_T_4244, _T_4215) @[dec_dec_ctl.scala 17:17] + node _T_4246 = or(_T_4157, _T_4245) @[dec_dec_ctl.scala 261:117] + node _T_4247 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_4248 = eq(_T_4247, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4249 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_4250 = eq(_T_4249, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4251 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_4252 = eq(_T_4251, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4253 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_4254 = eq(_T_4253, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4255 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53] + node _T_4256 = eq(_T_4255, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4257 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53] + node _T_4258 = eq(_T_4257, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4259 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53] + node _T_4260 = eq(_T_4259, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4261 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53] + node _T_4262 = eq(_T_4261, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4263 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53] + node _T_4264 = eq(_T_4263, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4265 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_4266 = eq(_T_4265, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4267 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_4268 = eq(_T_4267, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4269 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_4270 = eq(_T_4269, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4271 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53] + node _T_4272 = eq(_T_4271, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4273 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53] + node _T_4274 = eq(_T_4273, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4275 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53] + node _T_4276 = eq(_T_4275, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4277 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53] + node _T_4278 = eq(_T_4277, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4279 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53] + node _T_4280 = eq(_T_4279, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4281 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4282 = eq(_T_4281, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4283 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_4284 = eq(_T_4283, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4285 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4286 = eq(_T_4285, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4287 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_4288 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_4289 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4290 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4291 = and(_T_4248, _T_4250) @[dec_dec_ctl.scala 17:17] + node _T_4292 = and(_T_4291, _T_4252) @[dec_dec_ctl.scala 17:17] + node _T_4293 = and(_T_4292, _T_4254) @[dec_dec_ctl.scala 17:17] + node _T_4294 = and(_T_4293, _T_4256) @[dec_dec_ctl.scala 17:17] + node _T_4295 = and(_T_4294, _T_4258) @[dec_dec_ctl.scala 17:17] + node _T_4296 = and(_T_4295, _T_4260) @[dec_dec_ctl.scala 17:17] + node _T_4297 = and(_T_4296, _T_4262) @[dec_dec_ctl.scala 17:17] + node _T_4298 = and(_T_4297, _T_4264) @[dec_dec_ctl.scala 17:17] + node _T_4299 = and(_T_4298, _T_4266) @[dec_dec_ctl.scala 17:17] + node _T_4300 = and(_T_4299, _T_4268) @[dec_dec_ctl.scala 17:17] + node _T_4301 = and(_T_4300, _T_4270) @[dec_dec_ctl.scala 17:17] + node _T_4302 = and(_T_4301, _T_4272) @[dec_dec_ctl.scala 17:17] + node _T_4303 = and(_T_4302, _T_4274) @[dec_dec_ctl.scala 17:17] + node _T_4304 = and(_T_4303, _T_4276) @[dec_dec_ctl.scala 17:17] + node _T_4305 = and(_T_4304, _T_4278) @[dec_dec_ctl.scala 17:17] + node _T_4306 = and(_T_4305, _T_4280) @[dec_dec_ctl.scala 17:17] + node _T_4307 = and(_T_4306, _T_4282) @[dec_dec_ctl.scala 17:17] + node _T_4308 = and(_T_4307, _T_4284) @[dec_dec_ctl.scala 17:17] + node _T_4309 = and(_T_4308, _T_4286) @[dec_dec_ctl.scala 17:17] + node _T_4310 = and(_T_4309, _T_4287) @[dec_dec_ctl.scala 17:17] + node _T_4311 = and(_T_4310, _T_4288) @[dec_dec_ctl.scala 17:17] + node _T_4312 = and(_T_4311, _T_4289) @[dec_dec_ctl.scala 17:17] + node _T_4313 = and(_T_4312, _T_4290) @[dec_dec_ctl.scala 17:17] + node _T_4314 = or(_T_4246, _T_4313) @[dec_dec_ctl.scala 262:130] + node _T_4315 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_4316 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_4317 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4318 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_4319 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4320 = eq(_T_4319, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4321 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4322 = eq(_T_4321, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4323 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4324 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4325 = and(_T_4315, _T_4316) @[dec_dec_ctl.scala 17:17] + node _T_4326 = and(_T_4325, _T_4317) @[dec_dec_ctl.scala 17:17] + node _T_4327 = and(_T_4326, _T_4318) @[dec_dec_ctl.scala 17:17] + node _T_4328 = and(_T_4327, _T_4320) @[dec_dec_ctl.scala 17:17] + node _T_4329 = and(_T_4328, _T_4322) @[dec_dec_ctl.scala 17:17] + node _T_4330 = and(_T_4329, _T_4323) @[dec_dec_ctl.scala 17:17] + node _T_4331 = and(_T_4330, _T_4324) @[dec_dec_ctl.scala 17:17] + node _T_4332 = or(_T_4314, _T_4331) @[dec_dec_ctl.scala 263:102] + node _T_4333 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_4334 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4335 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4336 = eq(_T_4335, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4337 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_4338 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_4339 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4340 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4341 = and(_T_4333, _T_4334) @[dec_dec_ctl.scala 17:17] + node _T_4342 = and(_T_4341, _T_4336) @[dec_dec_ctl.scala 17:17] + node _T_4343 = and(_T_4342, _T_4337) @[dec_dec_ctl.scala 17:17] + node _T_4344 = and(_T_4343, _T_4338) @[dec_dec_ctl.scala 17:17] + node _T_4345 = and(_T_4344, _T_4339) @[dec_dec_ctl.scala 17:17] + node _T_4346 = and(_T_4345, _T_4340) @[dec_dec_ctl.scala 17:17] + node _T_4347 = or(_T_4332, _T_4346) @[dec_dec_ctl.scala 264:39] + node _T_4348 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_4349 = eq(_T_4348, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4350 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_4351 = eq(_T_4350, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4352 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4353 = eq(_T_4352, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4354 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4355 = eq(_T_4354, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4356 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4357 = eq(_T_4356, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4358 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4359 = eq(_T_4358, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4360 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4361 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4362 = and(_T_4349, _T_4351) @[dec_dec_ctl.scala 17:17] + node _T_4363 = and(_T_4362, _T_4353) @[dec_dec_ctl.scala 17:17] + node _T_4364 = and(_T_4363, _T_4355) @[dec_dec_ctl.scala 17:17] + node _T_4365 = and(_T_4364, _T_4357) @[dec_dec_ctl.scala 17:17] + node _T_4366 = and(_T_4365, _T_4359) @[dec_dec_ctl.scala 17:17] + node _T_4367 = and(_T_4366, _T_4360) @[dec_dec_ctl.scala 17:17] + node _T_4368 = and(_T_4367, _T_4361) @[dec_dec_ctl.scala 17:17] + node _T_4369 = or(_T_4347, _T_4368) @[dec_dec_ctl.scala 264:71] + node _T_4370 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_4371 = eq(_T_4370, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4372 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4373 = eq(_T_4372, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4374 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_4375 = eq(_T_4374, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4376 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4377 = eq(_T_4376, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4378 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4379 = eq(_T_4378, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4380 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4381 = eq(_T_4380, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4382 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4383 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4384 = and(_T_4371, _T_4373) @[dec_dec_ctl.scala 17:17] + node _T_4385 = and(_T_4384, _T_4375) @[dec_dec_ctl.scala 17:17] + node _T_4386 = and(_T_4385, _T_4377) @[dec_dec_ctl.scala 17:17] + node _T_4387 = and(_T_4386, _T_4379) @[dec_dec_ctl.scala 17:17] + node _T_4388 = and(_T_4387, _T_4381) @[dec_dec_ctl.scala 17:17] + node _T_4389 = and(_T_4388, _T_4382) @[dec_dec_ctl.scala 17:17] + node _T_4390 = and(_T_4389, _T_4383) @[dec_dec_ctl.scala 17:17] + node _T_4391 = or(_T_4369, _T_4390) @[dec_dec_ctl.scala 264:112] + node _T_4392 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_4393 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4394 = eq(_T_4393, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4395 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_4396 = eq(_T_4395, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4397 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_4398 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4399 = eq(_T_4398, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4400 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4401 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4402 = and(_T_4392, _T_4394) @[dec_dec_ctl.scala 17:17] + node _T_4403 = and(_T_4402, _T_4396) @[dec_dec_ctl.scala 17:17] + node _T_4404 = and(_T_4403, _T_4397) @[dec_dec_ctl.scala 17:17] + node _T_4405 = and(_T_4404, _T_4399) @[dec_dec_ctl.scala 17:17] + node _T_4406 = and(_T_4405, _T_4400) @[dec_dec_ctl.scala 17:17] + node _T_4407 = and(_T_4406, _T_4401) @[dec_dec_ctl.scala 17:17] + node _T_4408 = or(_T_4391, _T_4407) @[dec_dec_ctl.scala 265:43] + node _T_4409 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4410 = eq(_T_4409, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4411 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_4412 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4413 = eq(_T_4412, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4414 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_4415 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4416 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4417 = and(_T_4410, _T_4411) @[dec_dec_ctl.scala 17:17] + node _T_4418 = and(_T_4417, _T_4413) @[dec_dec_ctl.scala 17:17] + node _T_4419 = and(_T_4418, _T_4414) @[dec_dec_ctl.scala 17:17] + node _T_4420 = and(_T_4419, _T_4415) @[dec_dec_ctl.scala 17:17] + node _T_4421 = and(_T_4420, _T_4416) @[dec_dec_ctl.scala 17:17] + node _T_4422 = or(_T_4408, _T_4421) @[dec_dec_ctl.scala 265:78] + io.out.legal <= _T_4422 @[dec_dec_ctl.scala 248:16] + + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_10 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module dec_decode_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_branch_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_result_r : UInt<32>, flip dec_qual_lsu_d : UInt<1>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<4>, flip dec_i0_rs2_bypass_en_d : UInt<4>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, flip dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, flip dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>}, dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, flip dec_aln : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}, flip dec_tlu_trace_disable : UInt<1>, flip dec_debug_valid_d : UInt<1>, flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_i0_inst_wb : UInt<32>, dec_i0_pc_wb : UInt<31>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_second_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_bp_fa_index : UInt<9>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip active_clk : Clock, flip free_l2clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, div_waddr_wb : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, dec_fa_error_index : UInt<9>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>} + + wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[dec_decode_ctl.scala 117:40] + _T.bits.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.crc32c_w <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.crc32c_h <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.crc32c_b <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.crc32_w <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.crc32_h <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.crc32_b <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.unshfl <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.shfl <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.gorc <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.grev <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.clmulr <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.clmulh <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.clmul <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.bdep <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.bext <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.low <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + io.decode_exu.mul_p.bits.bfp <= _T.bits.bfp @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.crc32c_w <= _T.bits.crc32c_w @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.crc32c_h <= _T.bits.crc32c_h @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.crc32c_b <= _T.bits.crc32c_b @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.crc32_w <= _T.bits.crc32_w @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.crc32_h <= _T.bits.crc32_h @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.crc32_b <= _T.bits.crc32_b @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.unshfl <= _T.bits.unshfl @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.shfl <= _T.bits.shfl @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.gorc <= _T.bits.gorc @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.grev <= _T.bits.grev @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.clmulr <= _T.bits.clmulr @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.clmulh <= _T.bits.clmulh @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.clmul <= _T.bits.clmul @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.bdep <= _T.bits.bdep @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.bext <= _T.bits.bext @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.low <= _T.bits.low @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.rs2_sign <= _T.bits.rs2_sign @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.rs1_sign <= _T.bits.rs1_sign @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.valid <= _T.valid @[dec_decode_ctl.scala 117:25] + wire leak1_i1_stall_in : UInt<1> + leak1_i1_stall_in <= UInt<1>("h00") + wire leak1_i0_stall_in : UInt<1> + leak1_i0_stall_in <= UInt<1>("h00") + wire i0r : {rs1 : UInt<5>, rs2 : UInt<5>, rd : UInt<5>} @[dec_decode_ctl.scala 121:37] + wire d_t : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 122:37] + wire x_t : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 123:37] + wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 124:37] + wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 125:37] + wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 126:37] + wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 127:37] + wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 128:37] + wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 129:37] + wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 130:37] + wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 131:37] + wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 132:37] + wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 133:37] + wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 134:37] + wire i0_rs1_depth_d : UInt<2> + i0_rs1_depth_d <= UInt<1>("h00") + wire i0_rs2_depth_d : UInt<2> + i0_rs2_depth_d <= UInt<1>("h00") + wire cam_wen : UInt<4> + cam_wen <= UInt<1>("h00") + wire cam : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 138:37] + wire cam_write : UInt<1> + cam_write <= UInt<1>("h00") + wire cam_inv_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 140:37] + wire cam_data_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 141:37] + wire nonblock_load_write : UInt<1>[4] @[dec_decode_ctl.scala 142:37] + wire cam_raw : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 143:37] + wire cam_in : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 144:37] + wire i0_dp : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, zbs : UInt<1>, bext : UInt<1>, bdep : UInt<1>, zbe : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, zbc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, zbp : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, zbr : UInt<1>, bfp : UInt<1>, zbf : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 145:37] + wire i0_dp_raw : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, zbs : UInt<1>, bext : UInt<1>, bdep : UInt<1>, zbe : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, zbc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, zbp : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, zbr : UInt<1>, bfp : UInt<1>, zbf : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 146:37] + wire i0_rs1bypass : UInt<3> + i0_rs1bypass <= UInt<1>("h00") + wire i0_rs2bypass : UInt<3> + i0_rs2bypass <= UInt<1>("h00") + wire illegal_lockout : UInt<1> + illegal_lockout <= UInt<1>("h00") + wire postsync_stall : UInt<1> + postsync_stall <= UInt<1>("h00") + wire ps_stall_in : UInt<1> + ps_stall_in <= UInt<1>("h00") + wire i0_pipe_en : UInt<4> + i0_pipe_en <= UInt<1>("h00") + wire i0_load_block_d : UInt<1> + i0_load_block_d <= UInt<1>("h00") + wire load_ldst_bypass_d : UInt<1> + load_ldst_bypass_d <= UInt<1>("h00") + wire store_data_bypass_d : UInt<1> + store_data_bypass_d <= UInt<1>("h00") + wire store_data_bypass_m : UInt<1> + store_data_bypass_m <= UInt<1>("h00") + wire tlu_wr_pause_r1 : UInt<1> + tlu_wr_pause_r1 <= UInt<1>("h00") + wire tlu_wr_pause_r2 : UInt<1> + tlu_wr_pause_r2 <= UInt<1>("h00") + wire leak1_i1_stall : UInt<1> + leak1_i1_stall <= UInt<1>("h00") + wire leak1_i0_stall : UInt<1> + leak1_i0_stall <= UInt<1>("h00") + wire pause_stall : UInt<1> + pause_stall <= UInt<1>("h00") + wire flush_final_r : UInt<1> + flush_final_r <= UInt<1>("h00") + wire illegal_lockout_in : UInt<1> + illegal_lockout_in <= UInt<1>("h00") + wire lsu_idle : UInt<1> + lsu_idle <= UInt<1>("h00") + wire pause_state_in : UInt<1> + pause_state_in <= UInt<1>("h00") + wire leak1_mode : UInt<1> + leak1_mode <= UInt<1>("h00") + wire i0_pcall : UInt<1> + i0_pcall <= UInt<1>("h00") + wire i0_pja : UInt<1> + i0_pja <= UInt<1>("h00") + wire i0_pret : UInt<1> + i0_pret <= UInt<1>("h00") + wire i0_legal_decode_d : UInt<1> + i0_legal_decode_d <= UInt<1>("h00") + wire i0_pcall_raw : UInt<1> + i0_pcall_raw <= UInt<1>("h00") + wire i0_pja_raw : UInt<1> + i0_pja_raw <= UInt<1>("h00") + wire i0_pret_raw : UInt<1> + i0_pret_raw <= UInt<1>("h00") + wire i0_br_offset : UInt<12> + i0_br_offset <= UInt<1>("h00") + wire i0_csr_write_only_d : UInt<1> + i0_csr_write_only_d <= UInt<1>("h00") + wire i0_jal : UInt<1> + i0_jal <= UInt<1>("h00") + wire i0_wen_r : UInt<1> + i0_wen_r <= UInt<1>("h00") + wire i0_x_ctl_en : UInt<1> + i0_x_ctl_en <= UInt<1>("h00") + wire i0_r_ctl_en : UInt<1> + i0_r_ctl_en <= UInt<1>("h00") + wire i0_wb_ctl_en : UInt<1> + i0_wb_ctl_en <= UInt<1>("h00") + wire i0_x_data_en : UInt<1> + i0_x_data_en <= UInt<1>("h00") + wire i0_r_data_en : UInt<1> + i0_r_data_en <= UInt<1>("h00") + wire i0_wb_data_en : UInt<1> + i0_wb_data_en <= UInt<1>("h00") + wire i0_wb1_data_en : UInt<1> + i0_wb1_data_en <= UInt<1>("h00") + wire i0_nonblock_load_stall : UInt<1> + i0_nonblock_load_stall <= UInt<1>("h00") + wire csr_read : UInt<1> + csr_read <= UInt<1>("h00") + wire lsu_decode_d : UInt<1> + lsu_decode_d <= UInt<1>("h00") + wire mul_decode_d : UInt<1> + mul_decode_d <= UInt<1>("h00") + wire div_decode_d : UInt<1> + div_decode_d <= UInt<1>("h00") + wire write_csr_data : UInt<32> + write_csr_data <= UInt<1>("h00") + wire i0_result_corr_r : UInt<32> + i0_result_corr_r <= UInt<1>("h00") + wire presync_stall : UInt<1> + presync_stall <= UInt<1>("h00") + wire i0_nonblock_div_stall : UInt<1> + i0_nonblock_div_stall <= UInt<1>("h00") + wire debug_fence : UInt<1> + debug_fence <= UInt<1>("h00") + wire i0_immed_d : UInt<32> + i0_immed_d <= UInt<1>("h00") + wire i0_result_x : UInt<32> + i0_result_x <= UInt<1>("h00") + wire i0_result_r : UInt<32> + i0_result_r <= UInt<1>("h00") + wire i0_br_error_all : UInt<1> + i0_br_error_all <= UInt<1>("h00") + wire i0_brp_valid : UInt<1> + i0_brp_valid <= UInt<1>("h00") + wire btb_error_found_f : UInt<1> + btb_error_found_f <= UInt<1>("h00") + wire fa_error_index_ns : UInt<1> + fa_error_index_ns <= UInt<1>("h00") + wire btb_error_found : UInt<1> + btb_error_found <= UInt<1>("h00") + wire div_active_in : UInt<1> + div_active_in <= UInt<1>("h00") + wire _T_1 : UInt + _T_1 <= UInt<1>("h00") + node _T_2 = xor(leak1_i1_stall_in, _T_1) @[lib.scala 448:21] + node _T_3 = orr(_T_2) @[lib.scala 448:29] + reg _T_4 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3 : @[Reg.scala 28:19] + _T_4 <= leak1_i1_stall_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1 <= _T_4 @[lib.scala 451:16] + leak1_i1_stall <= _T_1 @[dec_decode_ctl.scala 206:35] + wire _T_5 : UInt + _T_5 <= UInt<1>("h00") + node _T_6 = xor(leak1_i0_stall_in, _T_5) @[lib.scala 448:21] + node _T_7 = orr(_T_6) @[lib.scala 448:29] + reg _T_8 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7 : @[Reg.scala 28:19] + _T_8 <= leak1_i0_stall_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_5 <= _T_8 @[lib.scala 451:16] + leak1_i0_stall <= _T_5 @[dec_decode_ctl.scala 207:35] + wire _T_9 : UInt<1> + _T_9 <= UInt<1>("h00") + node _T_10 = xor(io.dec_tlu_flush_extint, _T_9) @[lib.scala 470:21] + node _T_11 = orr(_T_10) @[lib.scala 470:29] + reg _T_12 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_11 : @[Reg.scala 28:19] + _T_12 <= io.dec_tlu_flush_extint @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_9 <= _T_12 @[lib.scala 473:16] + io.decode_exu.dec_extint_stall <= _T_9 @[dec_decode_ctl.scala 208:35] + wire _T_13 : UInt<1> + _T_13 <= UInt<1>("h00") + node _T_14 = xor(pause_state_in, _T_13) @[lib.scala 470:21] + node _T_15 = orr(_T_14) @[lib.scala 470:29] + reg _T_16 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_15 : @[Reg.scala 28:19] + _T_16 <= pause_state_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_13 <= _T_16 @[lib.scala 473:16] + pause_stall <= _T_13 @[dec_decode_ctl.scala 209:35] + wire _T_17 : UInt<1> + _T_17 <= UInt<1>("h00") + node _T_18 = xor(io.dec_tlu_wr_pause_r, _T_17) @[lib.scala 470:21] + node _T_19 = orr(_T_18) @[lib.scala 470:29] + reg _T_20 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_19 : @[Reg.scala 28:19] + _T_20 <= io.dec_tlu_wr_pause_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_17 <= _T_20 @[lib.scala 473:16] + tlu_wr_pause_r1 <= _T_17 @[dec_decode_ctl.scala 210:35] + wire _T_21 : UInt + _T_21 <= UInt<1>("h00") + node _T_22 = xor(tlu_wr_pause_r1, _T_21) @[lib.scala 448:21] + node _T_23 = orr(_T_22) @[lib.scala 448:29] + reg _T_24 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_23 : @[Reg.scala 28:19] + _T_24 <= tlu_wr_pause_r1 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_21 <= _T_24 @[lib.scala 451:16] + tlu_wr_pause_r2 <= _T_21 @[dec_decode_ctl.scala 211:35] + wire _T_25 : UInt + _T_25 <= UInt<1>("h00") + node _T_26 = xor(illegal_lockout_in, _T_25) @[lib.scala 448:21] + node _T_27 = orr(_T_26) @[lib.scala 448:29] + reg _T_28 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_27 : @[Reg.scala 28:19] + _T_28 <= illegal_lockout_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_25 <= _T_28 @[lib.scala 451:16] + illegal_lockout <= _T_25 @[dec_decode_ctl.scala 212:35] + wire _T_29 : UInt + _T_29 <= UInt<1>("h00") + node _T_30 = xor(ps_stall_in, _T_29) @[lib.scala 448:21] + node _T_31 = orr(_T_30) @[lib.scala 448:29] + reg _T_32 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_31 : @[Reg.scala 28:19] + _T_32 <= ps_stall_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_29 <= _T_32 @[lib.scala 451:16] + postsync_stall <= _T_29 @[dec_decode_ctl.scala 213:35] + wire lsu_trigger_match_r : UInt + lsu_trigger_match_r <= UInt<1>("h00") + node _T_33 = xor(io.lsu_trigger_match_m, lsu_trigger_match_r) @[lib.scala 448:21] + node _T_34 = orr(_T_33) @[lib.scala 448:29] + reg _T_35 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_34 : @[Reg.scala 28:19] + _T_35 <= io.lsu_trigger_match_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + lsu_trigger_match_r <= _T_35 @[lib.scala 451:16] + wire lsu_pmu_misaligned_r : UInt<1> + lsu_pmu_misaligned_r <= UInt<1>("h00") + node _T_36 = xor(io.lsu_pmu_misaligned_m, lsu_pmu_misaligned_r) @[lib.scala 470:21] + node _T_37 = orr(_T_36) @[lib.scala 470:29] + reg _T_38 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_37 : @[Reg.scala 28:19] + _T_38 <= io.lsu_pmu_misaligned_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + lsu_pmu_misaligned_r <= _T_38 @[lib.scala 473:16] + wire _T_39 : UInt<1> + _T_39 <= UInt<1>("h00") + node _T_40 = xor(div_active_in, _T_39) @[lib.scala 470:21] + node _T_41 = orr(_T_40) @[lib.scala 470:29] + reg _T_42 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_41 : @[Reg.scala 28:19] + _T_42 <= div_active_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_39 <= _T_42 @[lib.scala 473:16] + io.dec_div_active <= _T_39 @[dec_decode_ctl.scala 217:35] + wire _T_43 : UInt<1> + _T_43 <= UInt<1>("h00") + node _T_44 = xor(io.exu_flush_final, _T_43) @[lib.scala 470:21] + node _T_45 = orr(_T_44) @[lib.scala 470:29] + reg _T_46 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_45 : @[Reg.scala 28:19] + _T_46 <= io.exu_flush_final @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_43 <= _T_46 @[lib.scala 473:16] + flush_final_r <= _T_43 @[dec_decode_ctl.scala 218:35] + wire debug_valid_x : UInt<1> + debug_valid_x <= UInt<1>("h00") + node _T_47 = xor(io.dec_debug_valid_d, debug_valid_x) @[lib.scala 470:21] + node _T_48 = orr(_T_47) @[lib.scala 470:29] + reg _T_49 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_48 : @[Reg.scala 28:19] + _T_49 <= io.dec_debug_valid_d @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + debug_valid_x <= _T_49 @[lib.scala 473:16] + node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[dec_decode_ctl.scala 220:43] + node _T_50 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 222:82] + node _T_51 = and(io.dec_i0_brp.valid, _T_50) @[dec_decode_ctl.scala 222:80] + node _T_52 = eq(i0_icaf_d, UInt<1>("h00")) @[dec_decode_ctl.scala 222:96] + node _T_53 = and(_T_51, _T_52) @[dec_decode_ctl.scala 222:94] + i0_brp_valid <= _T_53 @[dec_decode_ctl.scala 222:57] + io.decode_exu.dec_i0_predict_p_d.bits.misp <= UInt<1>("h00") @[dec_decode_ctl.scala 223:57] + io.decode_exu.dec_i0_predict_p_d.bits.ataken <= UInt<1>("h00") @[dec_decode_ctl.scala 224:57] + io.decode_exu.dec_i0_predict_p_d.bits.boffset <= UInt<1>("h00") @[dec_decode_ctl.scala 225:57] + io.decode_exu.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[dec_decode_ctl.scala 226:57] + io.decode_exu.dec_i0_predict_p_d.bits.pja <= i0_pja @[dec_decode_ctl.scala 227:57] + io.decode_exu.dec_i0_predict_p_d.bits.pret <= i0_pret @[dec_decode_ctl.scala 228:57] + io.decode_exu.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[dec_decode_ctl.scala 229:57] + io.decode_exu.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[dec_decode_ctl.scala 230:57] + io.decode_exu.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[dec_decode_ctl.scala 231:57] + node _T_54 = and(i0_brp_valid, i0_legal_decode_d) @[dec_decode_ctl.scala 232:73] + io.decode_exu.dec_i0_predict_p_d.valid <= _T_54 @[dec_decode_ctl.scala 232:57] + node _T_55 = or(i0_dp_raw.condbr, i0_pcall_raw) @[dec_decode_ctl.scala 233:94] + node _T_56 = or(_T_55, i0_pja_raw) @[dec_decode_ctl.scala 233:109] + node _T_57 = or(_T_56, i0_pret_raw) @[dec_decode_ctl.scala 233:122] + node _T_58 = eq(_T_57, UInt<1>("h00")) @[dec_decode_ctl.scala 233:75] + node _T_59 = and(i0_brp_valid, _T_58) @[dec_decode_ctl.scala 233:73] + node _T_60 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 236:99] + node _T_61 = and(i0_brp_valid, _T_60) @[dec_decode_ctl.scala 236:74] + node _T_62 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[dec_decode_ctl.scala 236:133] + node _T_63 = and(_T_61, _T_62) @[dec_decode_ctl.scala 236:103] + node _T_64 = eq(i0_pret_raw, UInt<1>("h00")) @[dec_decode_ctl.scala 236:153] + node _T_65 = and(_T_63, _T_64) @[dec_decode_ctl.scala 236:151] + node _T_66 = xor(io.dec_i0_brp.bits.ret, i0_pret_raw) @[dec_decode_ctl.scala 237:100] + node _T_67 = and(i0_brp_valid, _T_66) @[dec_decode_ctl.scala 237:74] + node _T_68 = or(io.dec_i0_brp.bits.br_error, _T_59) @[dec_decode_ctl.scala 238:89] + node _T_69 = or(_T_68, _T_65) @[dec_decode_ctl.scala 238:106] + node _T_70 = or(_T_69, _T_67) @[dec_decode_ctl.scala 238:128] + node _T_71 = and(_T_70, i0_legal_decode_d) @[dec_decode_ctl.scala 239:74] + node _T_72 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 239:96] + node _T_73 = and(_T_71, _T_72) @[dec_decode_ctl.scala 239:94] + io.decode_exu.dec_i0_predict_p_d.bits.br_error <= _T_73 @[dec_decode_ctl.scala 239:58] + node _T_74 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[dec_decode_ctl.scala 240:96] + node _T_75 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 240:118] + node _T_76 = and(_T_74, _T_75) @[dec_decode_ctl.scala 240:116] + io.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= _T_76 @[dec_decode_ctl.scala 240:58] + io.decode_exu.i0_predict_index_d <= io.dec_i0_bp_index @[dec_decode_ctl.scala 241:58] + io.decode_exu.i0_predict_btag_d <= io.dec_i0_bp_btag @[dec_decode_ctl.scala 242:58] + node _T_77 = or(_T_70, io.dec_i0_brp.bits.br_start_error) @[dec_decode_ctl.scala 243:74] + node _T_78 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 243:113] + node _T_79 = and(_T_77, _T_78) @[dec_decode_ctl.scala 243:111] + i0_br_error_all <= _T_79 @[dec_decode_ctl.scala 243:58] + io.decode_exu.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[dec_decode_ctl.scala 244:58] + io.decode_exu.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[dec_decode_ctl.scala 245:58] + io.decode_exu.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[dec_decode_ctl.scala 246:58] + io.dec_fa_error_index <= UInt<1>("h00") @[dec_decode_ctl.scala 255:29] + i0_dp.legal <= i0_dp_raw.legal @[dec_decode_ctl.scala 279:23] + i0_dp.pm_alu <= i0_dp_raw.pm_alu @[dec_decode_ctl.scala 279:23] + i0_dp.fence_i <= i0_dp_raw.fence_i @[dec_decode_ctl.scala 279:23] + i0_dp.fence <= i0_dp_raw.fence @[dec_decode_ctl.scala 279:23] + i0_dp.rem <= i0_dp_raw.rem @[dec_decode_ctl.scala 279:23] + i0_dp.div <= i0_dp_raw.div @[dec_decode_ctl.scala 279:23] + i0_dp.low <= i0_dp_raw.low @[dec_decode_ctl.scala 279:23] + i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[dec_decode_ctl.scala 279:23] + i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[dec_decode_ctl.scala 279:23] + i0_dp.mul <= i0_dp_raw.mul @[dec_decode_ctl.scala 279:23] + i0_dp.mret <= i0_dp_raw.mret @[dec_decode_ctl.scala 279:23] + i0_dp.ecall <= i0_dp_raw.ecall @[dec_decode_ctl.scala 279:23] + i0_dp.ebreak <= i0_dp_raw.ebreak @[dec_decode_ctl.scala 279:23] + i0_dp.postsync <= i0_dp_raw.postsync @[dec_decode_ctl.scala 279:23] + i0_dp.presync <= i0_dp_raw.presync @[dec_decode_ctl.scala 279:23] + i0_dp.csr_imm <= i0_dp_raw.csr_imm @[dec_decode_ctl.scala 279:23] + i0_dp.csr_write <= i0_dp_raw.csr_write @[dec_decode_ctl.scala 279:23] + i0_dp.csr_set <= i0_dp_raw.csr_set @[dec_decode_ctl.scala 279:23] + i0_dp.csr_clr <= i0_dp_raw.csr_clr @[dec_decode_ctl.scala 279:23] + i0_dp.csr_read <= i0_dp_raw.csr_read @[dec_decode_ctl.scala 279:23] + i0_dp.word <= i0_dp_raw.word @[dec_decode_ctl.scala 279:23] + i0_dp.half <= i0_dp_raw.half @[dec_decode_ctl.scala 279:23] + i0_dp.by <= i0_dp_raw.by @[dec_decode_ctl.scala 279:23] + i0_dp.jal <= i0_dp_raw.jal @[dec_decode_ctl.scala 279:23] + i0_dp.blt <= i0_dp_raw.blt @[dec_decode_ctl.scala 279:23] + i0_dp.bge <= i0_dp_raw.bge @[dec_decode_ctl.scala 279:23] + i0_dp.bne <= i0_dp_raw.bne @[dec_decode_ctl.scala 279:23] + i0_dp.beq <= i0_dp_raw.beq @[dec_decode_ctl.scala 279:23] + i0_dp.condbr <= i0_dp_raw.condbr @[dec_decode_ctl.scala 279:23] + i0_dp.unsign <= i0_dp_raw.unsign @[dec_decode_ctl.scala 279:23] + i0_dp.slt <= i0_dp_raw.slt @[dec_decode_ctl.scala 279:23] + i0_dp.srl <= i0_dp_raw.srl @[dec_decode_ctl.scala 279:23] + i0_dp.sra <= i0_dp_raw.sra @[dec_decode_ctl.scala 279:23] + i0_dp.sll <= i0_dp_raw.sll @[dec_decode_ctl.scala 279:23] + i0_dp.lxor <= i0_dp_raw.lxor @[dec_decode_ctl.scala 279:23] + i0_dp.lor <= i0_dp_raw.lor @[dec_decode_ctl.scala 279:23] + i0_dp.land <= i0_dp_raw.land @[dec_decode_ctl.scala 279:23] + i0_dp.sub <= i0_dp_raw.sub @[dec_decode_ctl.scala 279:23] + i0_dp.add <= i0_dp_raw.add @[dec_decode_ctl.scala 279:23] + i0_dp.lsu <= i0_dp_raw.lsu @[dec_decode_ctl.scala 279:23] + i0_dp.store <= i0_dp_raw.store @[dec_decode_ctl.scala 279:23] + i0_dp.load <= i0_dp_raw.load @[dec_decode_ctl.scala 279:23] + i0_dp.pc <= i0_dp_raw.pc @[dec_decode_ctl.scala 279:23] + i0_dp.imm20 <= i0_dp_raw.imm20 @[dec_decode_ctl.scala 279:23] + i0_dp.shimm5 <= i0_dp_raw.shimm5 @[dec_decode_ctl.scala 279:23] + i0_dp.rd <= i0_dp_raw.rd @[dec_decode_ctl.scala 279:23] + i0_dp.imm12 <= i0_dp_raw.imm12 @[dec_decode_ctl.scala 279:23] + i0_dp.rs2 <= i0_dp_raw.rs2 @[dec_decode_ctl.scala 279:23] + i0_dp.rs1 <= i0_dp_raw.rs1 @[dec_decode_ctl.scala 279:23] + i0_dp.alu <= i0_dp_raw.alu @[dec_decode_ctl.scala 279:23] + i0_dp.zba <= i0_dp_raw.zba @[dec_decode_ctl.scala 279:23] + i0_dp.sh3add <= i0_dp_raw.sh3add @[dec_decode_ctl.scala 279:23] + i0_dp.sh2add <= i0_dp_raw.sh2add @[dec_decode_ctl.scala 279:23] + i0_dp.sh1add <= i0_dp_raw.sh1add @[dec_decode_ctl.scala 279:23] + i0_dp.zbf <= i0_dp_raw.zbf @[dec_decode_ctl.scala 279:23] + i0_dp.bfp <= i0_dp_raw.bfp @[dec_decode_ctl.scala 279:23] + i0_dp.zbr <= i0_dp_raw.zbr @[dec_decode_ctl.scala 279:23] + i0_dp.crc32c_w <= i0_dp_raw.crc32c_w @[dec_decode_ctl.scala 279:23] + i0_dp.crc32c_h <= i0_dp_raw.crc32c_h @[dec_decode_ctl.scala 279:23] + i0_dp.crc32c_b <= i0_dp_raw.crc32c_b @[dec_decode_ctl.scala 279:23] + i0_dp.crc32_w <= i0_dp_raw.crc32_w @[dec_decode_ctl.scala 279:23] + i0_dp.crc32_h <= i0_dp_raw.crc32_h @[dec_decode_ctl.scala 279:23] + i0_dp.crc32_b <= i0_dp_raw.crc32_b @[dec_decode_ctl.scala 279:23] + i0_dp.zbp <= i0_dp_raw.zbp @[dec_decode_ctl.scala 279:23] + i0_dp.unshfl <= i0_dp_raw.unshfl @[dec_decode_ctl.scala 279:23] + i0_dp.shfl <= i0_dp_raw.shfl @[dec_decode_ctl.scala 279:23] + i0_dp.zbc <= i0_dp_raw.zbc @[dec_decode_ctl.scala 279:23] + i0_dp.clmulr <= i0_dp_raw.clmulr @[dec_decode_ctl.scala 279:23] + i0_dp.clmulh <= i0_dp_raw.clmulh @[dec_decode_ctl.scala 279:23] + i0_dp.clmul <= i0_dp_raw.clmul @[dec_decode_ctl.scala 279:23] + i0_dp.zbe <= i0_dp_raw.zbe @[dec_decode_ctl.scala 279:23] + i0_dp.bdep <= i0_dp_raw.bdep @[dec_decode_ctl.scala 279:23] + i0_dp.bext <= i0_dp_raw.bext @[dec_decode_ctl.scala 279:23] + i0_dp.zbs <= i0_dp_raw.zbs @[dec_decode_ctl.scala 279:23] + i0_dp.sbext <= i0_dp_raw.sbext @[dec_decode_ctl.scala 279:23] + i0_dp.sbinv <= i0_dp_raw.sbinv @[dec_decode_ctl.scala 279:23] + i0_dp.sbclr <= i0_dp_raw.sbclr @[dec_decode_ctl.scala 279:23] + i0_dp.sbset <= i0_dp_raw.sbset @[dec_decode_ctl.scala 279:23] + i0_dp.zbb <= i0_dp_raw.zbb @[dec_decode_ctl.scala 279:23] + i0_dp.gorc <= i0_dp_raw.gorc @[dec_decode_ctl.scala 279:23] + i0_dp.grev <= i0_dp_raw.grev @[dec_decode_ctl.scala 279:23] + i0_dp.ror <= i0_dp_raw.ror @[dec_decode_ctl.scala 279:23] + i0_dp.rol <= i0_dp_raw.rol @[dec_decode_ctl.scala 279:23] + i0_dp.packh <= i0_dp_raw.packh @[dec_decode_ctl.scala 279:23] + i0_dp.packu <= i0_dp_raw.packu @[dec_decode_ctl.scala 279:23] + i0_dp.pack <= i0_dp_raw.pack @[dec_decode_ctl.scala 279:23] + i0_dp.max <= i0_dp_raw.max @[dec_decode_ctl.scala 279:23] + i0_dp.min <= i0_dp_raw.min @[dec_decode_ctl.scala 279:23] + i0_dp.sro <= i0_dp_raw.sro @[dec_decode_ctl.scala 279:23] + i0_dp.slo <= i0_dp_raw.slo @[dec_decode_ctl.scala 279:23] + i0_dp.sext_h <= i0_dp_raw.sext_h @[dec_decode_ctl.scala 279:23] + i0_dp.sext_b <= i0_dp_raw.sext_b @[dec_decode_ctl.scala 279:23] + i0_dp.pcnt <= i0_dp_raw.pcnt @[dec_decode_ctl.scala 279:23] + i0_dp.ctz <= i0_dp_raw.ctz @[dec_decode_ctl.scala 279:23] + i0_dp.clz <= i0_dp_raw.clz @[dec_decode_ctl.scala 279:23] + node _T_80 = or(i0_br_error_all, i0_icaf_d) @[dec_decode_ctl.scala 280:25] + node _T_81 = bits(_T_80, 0, 0) @[dec_decode_ctl.scala 280:43] + when _T_81 : @[dec_decode_ctl.scala 280:50] + wire _T_82 : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, zbs : UInt<1>, bext : UInt<1>, bdep : UInt<1>, zbe : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, zbc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, zbp : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, zbr : UInt<1>, bfp : UInt<1>, zbf : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 281:38] + _T_82.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.pm_alu <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.fence <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.rem <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.div <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.low <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.mret <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.ecall <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.ebreak <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.postsync <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.presync <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.csr_imm <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.csr_write <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.csr_set <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.csr_clr <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.csr_read <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.word <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.half <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.by <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.jal <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.blt <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.bge <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.bne <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.beq <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.condbr <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.slt <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.srl <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sra <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sll <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.lxor <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.lor <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.land <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sub <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.add <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.lsu <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.store <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.load <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.pc <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.imm20 <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.shimm5 <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.rd <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.imm12 <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.rs2 <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.rs1 <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.zba <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sh3add <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sh2add <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sh1add <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.zbf <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.zbr <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.crc32c_w <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.crc32c_h <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.crc32c_b <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.crc32_w <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.crc32_h <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.crc32_b <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.zbp <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.unshfl <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.shfl <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.zbc <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.clmulr <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.clmulh <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.clmul <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.zbe <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.bdep <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.bext <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.zbs <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sbext <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sbinv <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sbclr <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sbset <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.zbb <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.gorc <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.grev <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.ror <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.rol <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.packh <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.packu <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.pack <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.max <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.min <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sro <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.slo <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sext_h <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sext_b <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.pcnt <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.ctz <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.clz <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + i0_dp.legal <= _T_82.legal @[dec_decode_ctl.scala 281:23] + i0_dp.pm_alu <= _T_82.pm_alu @[dec_decode_ctl.scala 281:23] + i0_dp.fence_i <= _T_82.fence_i @[dec_decode_ctl.scala 281:23] + i0_dp.fence <= _T_82.fence @[dec_decode_ctl.scala 281:23] + i0_dp.rem <= _T_82.rem @[dec_decode_ctl.scala 281:23] + i0_dp.div <= _T_82.div @[dec_decode_ctl.scala 281:23] + i0_dp.low <= _T_82.low @[dec_decode_ctl.scala 281:23] + i0_dp.rs2_sign <= _T_82.rs2_sign @[dec_decode_ctl.scala 281:23] + i0_dp.rs1_sign <= _T_82.rs1_sign @[dec_decode_ctl.scala 281:23] + i0_dp.mul <= _T_82.mul @[dec_decode_ctl.scala 281:23] + i0_dp.mret <= _T_82.mret @[dec_decode_ctl.scala 281:23] + i0_dp.ecall <= _T_82.ecall @[dec_decode_ctl.scala 281:23] + i0_dp.ebreak <= _T_82.ebreak @[dec_decode_ctl.scala 281:23] + i0_dp.postsync <= _T_82.postsync @[dec_decode_ctl.scala 281:23] + i0_dp.presync <= _T_82.presync @[dec_decode_ctl.scala 281:23] + i0_dp.csr_imm <= _T_82.csr_imm @[dec_decode_ctl.scala 281:23] + i0_dp.csr_write <= _T_82.csr_write @[dec_decode_ctl.scala 281:23] + i0_dp.csr_set <= _T_82.csr_set @[dec_decode_ctl.scala 281:23] + i0_dp.csr_clr <= _T_82.csr_clr @[dec_decode_ctl.scala 281:23] + i0_dp.csr_read <= _T_82.csr_read @[dec_decode_ctl.scala 281:23] + i0_dp.word <= _T_82.word @[dec_decode_ctl.scala 281:23] + i0_dp.half <= _T_82.half @[dec_decode_ctl.scala 281:23] + i0_dp.by <= _T_82.by @[dec_decode_ctl.scala 281:23] + i0_dp.jal <= _T_82.jal @[dec_decode_ctl.scala 281:23] + i0_dp.blt <= _T_82.blt @[dec_decode_ctl.scala 281:23] + i0_dp.bge <= _T_82.bge @[dec_decode_ctl.scala 281:23] + i0_dp.bne <= _T_82.bne @[dec_decode_ctl.scala 281:23] + i0_dp.beq <= _T_82.beq @[dec_decode_ctl.scala 281:23] + i0_dp.condbr <= _T_82.condbr @[dec_decode_ctl.scala 281:23] + i0_dp.unsign <= _T_82.unsign @[dec_decode_ctl.scala 281:23] + i0_dp.slt <= _T_82.slt @[dec_decode_ctl.scala 281:23] + i0_dp.srl <= _T_82.srl @[dec_decode_ctl.scala 281:23] + i0_dp.sra <= _T_82.sra @[dec_decode_ctl.scala 281:23] + i0_dp.sll <= _T_82.sll @[dec_decode_ctl.scala 281:23] + i0_dp.lxor <= _T_82.lxor @[dec_decode_ctl.scala 281:23] + i0_dp.lor <= _T_82.lor @[dec_decode_ctl.scala 281:23] + i0_dp.land <= _T_82.land @[dec_decode_ctl.scala 281:23] + i0_dp.sub <= _T_82.sub @[dec_decode_ctl.scala 281:23] + i0_dp.add <= _T_82.add @[dec_decode_ctl.scala 281:23] + i0_dp.lsu <= _T_82.lsu @[dec_decode_ctl.scala 281:23] + i0_dp.store <= _T_82.store @[dec_decode_ctl.scala 281:23] + i0_dp.load <= _T_82.load @[dec_decode_ctl.scala 281:23] + i0_dp.pc <= _T_82.pc @[dec_decode_ctl.scala 281:23] + i0_dp.imm20 <= _T_82.imm20 @[dec_decode_ctl.scala 281:23] + i0_dp.shimm5 <= _T_82.shimm5 @[dec_decode_ctl.scala 281:23] + i0_dp.rd <= _T_82.rd @[dec_decode_ctl.scala 281:23] + i0_dp.imm12 <= _T_82.imm12 @[dec_decode_ctl.scala 281:23] + i0_dp.rs2 <= _T_82.rs2 @[dec_decode_ctl.scala 281:23] + i0_dp.rs1 <= _T_82.rs1 @[dec_decode_ctl.scala 281:23] + i0_dp.alu <= _T_82.alu @[dec_decode_ctl.scala 281:23] + i0_dp.zba <= _T_82.zba @[dec_decode_ctl.scala 281:23] + i0_dp.sh3add <= _T_82.sh3add @[dec_decode_ctl.scala 281:23] + i0_dp.sh2add <= _T_82.sh2add @[dec_decode_ctl.scala 281:23] + i0_dp.sh1add <= _T_82.sh1add @[dec_decode_ctl.scala 281:23] + i0_dp.zbf <= _T_82.zbf @[dec_decode_ctl.scala 281:23] + i0_dp.bfp <= _T_82.bfp @[dec_decode_ctl.scala 281:23] + i0_dp.zbr <= _T_82.zbr @[dec_decode_ctl.scala 281:23] + i0_dp.crc32c_w <= _T_82.crc32c_w @[dec_decode_ctl.scala 281:23] + i0_dp.crc32c_h <= _T_82.crc32c_h @[dec_decode_ctl.scala 281:23] + i0_dp.crc32c_b <= _T_82.crc32c_b @[dec_decode_ctl.scala 281:23] + i0_dp.crc32_w <= _T_82.crc32_w @[dec_decode_ctl.scala 281:23] + i0_dp.crc32_h <= _T_82.crc32_h @[dec_decode_ctl.scala 281:23] + i0_dp.crc32_b <= _T_82.crc32_b @[dec_decode_ctl.scala 281:23] + i0_dp.zbp <= _T_82.zbp @[dec_decode_ctl.scala 281:23] + i0_dp.unshfl <= _T_82.unshfl @[dec_decode_ctl.scala 281:23] + i0_dp.shfl <= _T_82.shfl @[dec_decode_ctl.scala 281:23] + i0_dp.zbc <= _T_82.zbc @[dec_decode_ctl.scala 281:23] + i0_dp.clmulr <= _T_82.clmulr @[dec_decode_ctl.scala 281:23] + i0_dp.clmulh <= _T_82.clmulh @[dec_decode_ctl.scala 281:23] + i0_dp.clmul <= _T_82.clmul @[dec_decode_ctl.scala 281:23] + i0_dp.zbe <= _T_82.zbe @[dec_decode_ctl.scala 281:23] + i0_dp.bdep <= _T_82.bdep @[dec_decode_ctl.scala 281:23] + i0_dp.bext <= _T_82.bext @[dec_decode_ctl.scala 281:23] + i0_dp.zbs <= _T_82.zbs @[dec_decode_ctl.scala 281:23] + i0_dp.sbext <= _T_82.sbext @[dec_decode_ctl.scala 281:23] + i0_dp.sbinv <= _T_82.sbinv @[dec_decode_ctl.scala 281:23] + i0_dp.sbclr <= _T_82.sbclr @[dec_decode_ctl.scala 281:23] + i0_dp.sbset <= _T_82.sbset @[dec_decode_ctl.scala 281:23] + i0_dp.zbb <= _T_82.zbb @[dec_decode_ctl.scala 281:23] + i0_dp.gorc <= _T_82.gorc @[dec_decode_ctl.scala 281:23] + i0_dp.grev <= _T_82.grev @[dec_decode_ctl.scala 281:23] + i0_dp.ror <= _T_82.ror @[dec_decode_ctl.scala 281:23] + i0_dp.rol <= _T_82.rol @[dec_decode_ctl.scala 281:23] + i0_dp.packh <= _T_82.packh @[dec_decode_ctl.scala 281:23] + i0_dp.packu <= _T_82.packu @[dec_decode_ctl.scala 281:23] + i0_dp.pack <= _T_82.pack @[dec_decode_ctl.scala 281:23] + i0_dp.max <= _T_82.max @[dec_decode_ctl.scala 281:23] + i0_dp.min <= _T_82.min @[dec_decode_ctl.scala 281:23] + i0_dp.sro <= _T_82.sro @[dec_decode_ctl.scala 281:23] + i0_dp.slo <= _T_82.slo @[dec_decode_ctl.scala 281:23] + i0_dp.sext_h <= _T_82.sext_h @[dec_decode_ctl.scala 281:23] + i0_dp.sext_b <= _T_82.sext_b @[dec_decode_ctl.scala 281:23] + i0_dp.pcnt <= _T_82.pcnt @[dec_decode_ctl.scala 281:23] + i0_dp.ctz <= _T_82.ctz @[dec_decode_ctl.scala 281:23] + i0_dp.clz <= _T_82.clz @[dec_decode_ctl.scala 281:23] + i0_dp.alu <= UInt<1>("h01") @[dec_decode_ctl.scala 282:23] + i0_dp.rs1 <= UInt<1>("h01") @[dec_decode_ctl.scala 283:23] + i0_dp.rs2 <= UInt<1>("h01") @[dec_decode_ctl.scala 284:23] + i0_dp.lor <= UInt<1>("h01") @[dec_decode_ctl.scala 285:23] + i0_dp.legal <= UInt<1>("h01") @[dec_decode_ctl.scala 286:23] + i0_dp.postsync <= UInt<1>("h01") @[dec_decode_ctl.scala 287:23] + skip @[dec_decode_ctl.scala 280:50] + io.decode_exu.dec_i0_select_pc_d <= i0_dp.pc @[dec_decode_ctl.scala 291:36] + node _T_83 = or(i0_dp.condbr, i0_pcall) @[dec_decode_ctl.scala 294:54] + node _T_84 = or(_T_83, i0_pja) @[dec_decode_ctl.scala 294:65] + node i0_predict_br = or(_T_84, i0_pret) @[dec_decode_ctl.scala 294:74] + node _T_85 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 295:65] + node _T_86 = and(_T_85, i0_brp_valid) @[dec_decode_ctl.scala 295:69] + node _T_87 = eq(_T_86, UInt<1>("h00")) @[dec_decode_ctl.scala 295:40] + node i0_predict_nt = and(_T_87, i0_predict_br) @[dec_decode_ctl.scala 295:85] + node _T_88 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 296:65] + node _T_89 = and(_T_88, i0_brp_valid) @[dec_decode_ctl.scala 296:69] + node i0_predict_t = and(_T_89, i0_predict_br) @[dec_decode_ctl.scala 296:85] + node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[dec_decode_ctl.scala 297:40] + io.decode_exu.i0_ap.predict_nt <= i0_predict_nt @[dec_decode_ctl.scala 299:37] + io.decode_exu.i0_ap.predict_t <= i0_predict_t @[dec_decode_ctl.scala 300:37] + io.decode_exu.i0_ap.add <= i0_dp.add @[dec_decode_ctl.scala 303:33] + io.decode_exu.i0_ap.sub <= i0_dp.sub @[dec_decode_ctl.scala 304:33] + io.decode_exu.i0_ap.land <= i0_dp.land @[dec_decode_ctl.scala 305:33] + io.decode_exu.i0_ap.lor <= i0_dp.lor @[dec_decode_ctl.scala 306:33] + io.decode_exu.i0_ap.lxor <= i0_dp.lxor @[dec_decode_ctl.scala 307:33] + io.decode_exu.i0_ap.sll <= i0_dp.sll @[dec_decode_ctl.scala 308:33] + io.decode_exu.i0_ap.srl <= i0_dp.srl @[dec_decode_ctl.scala 309:33] + io.decode_exu.i0_ap.sra <= i0_dp.sra @[dec_decode_ctl.scala 310:33] + io.decode_exu.i0_ap.slt <= i0_dp.slt @[dec_decode_ctl.scala 311:33] + io.decode_exu.i0_ap.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 312:33] + io.decode_exu.i0_ap.beq <= i0_dp.beq @[dec_decode_ctl.scala 313:33] + io.decode_exu.i0_ap.bne <= i0_dp.bne @[dec_decode_ctl.scala 314:33] + io.decode_exu.i0_ap.blt <= i0_dp.blt @[dec_decode_ctl.scala 315:33] + io.decode_exu.i0_ap.bge <= i0_dp.bge @[dec_decode_ctl.scala 316:33] + io.decode_exu.i0_ap.clz <= i0_dp.clz @[dec_decode_ctl.scala 317:33] + io.decode_exu.i0_ap.ctz <= i0_dp.ctz @[dec_decode_ctl.scala 318:33] + io.decode_exu.i0_ap.pcnt <= i0_dp.pcnt @[dec_decode_ctl.scala 319:33] + io.decode_exu.i0_ap.sext_b <= i0_dp.sext_b @[dec_decode_ctl.scala 320:33] + io.decode_exu.i0_ap.sext_h <= i0_dp.sext_h @[dec_decode_ctl.scala 321:33] + io.decode_exu.i0_ap.sh1add <= i0_dp.sh1add @[dec_decode_ctl.scala 322:33] + io.decode_exu.i0_ap.sh2add <= i0_dp.sh2add @[dec_decode_ctl.scala 323:33] + io.decode_exu.i0_ap.sh3add <= i0_dp.sh3add @[dec_decode_ctl.scala 324:33] + io.decode_exu.i0_ap.zba <= i0_dp.zba @[dec_decode_ctl.scala 325:33] + io.decode_exu.i0_ap.slo <= i0_dp.slo @[dec_decode_ctl.scala 326:33] + io.decode_exu.i0_ap.sro <= i0_dp.sro @[dec_decode_ctl.scala 327:33] + io.decode_exu.i0_ap.min <= i0_dp.min @[dec_decode_ctl.scala 328:33] + io.decode_exu.i0_ap.max <= i0_dp.max @[dec_decode_ctl.scala 329:33] + io.decode_exu.i0_ap.pack <= i0_dp.pack @[dec_decode_ctl.scala 330:33] + io.decode_exu.i0_ap.packu <= i0_dp.packu @[dec_decode_ctl.scala 331:33] + io.decode_exu.i0_ap.packh <= i0_dp.packh @[dec_decode_ctl.scala 332:33] + io.decode_exu.i0_ap.rol <= i0_dp.rol @[dec_decode_ctl.scala 333:33] + io.decode_exu.i0_ap.ror <= i0_dp.ror @[dec_decode_ctl.scala 334:33] + io.decode_exu.i0_ap.grev <= i0_dp.grev @[dec_decode_ctl.scala 335:33] + io.decode_exu.i0_ap.gorc <= i0_dp.gorc @[dec_decode_ctl.scala 336:33] + io.decode_exu.i0_ap.zbb <= i0_dp.zbb @[dec_decode_ctl.scala 337:33] + io.decode_exu.i0_ap.sbset <= i0_dp.sbset @[dec_decode_ctl.scala 338:33] + io.decode_exu.i0_ap.sbclr <= i0_dp.sbclr @[dec_decode_ctl.scala 339:33] + io.decode_exu.i0_ap.sbinv <= i0_dp.sbinv @[dec_decode_ctl.scala 340:33] + io.decode_exu.i0_ap.sbext <= i0_dp.sbext @[dec_decode_ctl.scala 341:33] + io.decode_exu.i0_ap.csr_write <= i0_csr_write_only_d @[dec_decode_ctl.scala 342:33] + io.decode_exu.i0_ap.csr_imm <= i0_dp.csr_imm @[dec_decode_ctl.scala 343:33] + io.decode_exu.i0_ap.jal <= i0_jal @[dec_decode_ctl.scala 344:33] + node _T_90 = eq(cam[0].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 348:78] + node _T_91 = bits(_T_90, 0, 0) @[dec_decode_ctl.scala 348:137] + node _T_92 = shl(cam_write, 0) @[dec_decode_ctl.scala 348:158] + node _T_93 = eq(cam[1].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 348:78] + node _T_94 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 348:120] + node _T_95 = bits(_T_93, 0, 0) @[dec_decode_ctl.scala 348:129] + node _T_96 = and(_T_94, _T_95) @[dec_decode_ctl.scala 348:126] + node _T_97 = bits(_T_96, 0, 0) @[dec_decode_ctl.scala 348:137] + node _T_98 = shl(cam_write, 1) @[dec_decode_ctl.scala 348:158] + node _T_99 = eq(cam[2].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 348:78] + node _T_100 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 348:120] + node _T_101 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 348:129] + node _T_102 = and(_T_100, _T_101) @[dec_decode_ctl.scala 348:126] + node _T_103 = bits(_T_102, 0, 0) @[dec_decode_ctl.scala 348:120] + node _T_104 = bits(_T_99, 0, 0) @[dec_decode_ctl.scala 348:129] + node _T_105 = and(_T_103, _T_104) @[dec_decode_ctl.scala 348:126] + node _T_106 = bits(_T_105, 0, 0) @[dec_decode_ctl.scala 348:137] + node _T_107 = shl(cam_write, 2) @[dec_decode_ctl.scala 348:158] + node _T_108 = eq(cam[3].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 348:78] + node _T_109 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 348:120] + node _T_110 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 348:129] + node _T_111 = and(_T_109, _T_110) @[dec_decode_ctl.scala 348:126] + node _T_112 = bits(_T_111, 0, 0) @[dec_decode_ctl.scala 348:120] + node _T_113 = bits(cam[2].valid, 0, 0) @[dec_decode_ctl.scala 348:129] + node _T_114 = and(_T_112, _T_113) @[dec_decode_ctl.scala 348:126] + node _T_115 = bits(_T_114, 0, 0) @[dec_decode_ctl.scala 348:120] + node _T_116 = bits(_T_108, 0, 0) @[dec_decode_ctl.scala 348:129] + node _T_117 = and(_T_115, _T_116) @[dec_decode_ctl.scala 348:126] + node _T_118 = bits(_T_117, 0, 0) @[dec_decode_ctl.scala 348:137] + node _T_119 = shl(cam_write, 3) @[dec_decode_ctl.scala 348:158] + node _T_120 = mux(_T_91, _T_92, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_121 = mux(_T_97, _T_98, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_122 = mux(_T_106, _T_107, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_123 = mux(_T_118, _T_119, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_124 = or(_T_120, _T_121) @[Mux.scala 27:72] + node _T_125 = or(_T_124, _T_122) @[Mux.scala 27:72] + node _T_126 = or(_T_125, _T_123) @[Mux.scala 27:72] + wire _T_127 : UInt<4> @[Mux.scala 27:72] + _T_127 <= _T_126 @[Mux.scala 27:72] + cam_wen <= _T_127 @[dec_decode_ctl.scala 348:11] + cam_write <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[dec_decode_ctl.scala 350:25] + node cam_write_tag = bits(io.dctl_busbuff.lsu_nonblock_load_tag_m, 1, 0) @[dec_decode_ctl.scala 351:67] + node cam_data_reset = or(io.dctl_busbuff.lsu_nonblock_load_data_valid, io.dctl_busbuff.lsu_nonblock_load_data_error) @[dec_decode_ctl.scala 356:76] + node _T_128 = bits(x_d.bits.i0load, 0, 0) @[dec_decode_ctl.scala 359:48] + node nonblock_load_rd = mux(_T_128, x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 359:31] + node _T_129 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 363:129] + reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_129 : @[Reg.scala 28:19] + nonblock_load_valid_m_delay <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[dec_decode_ctl.scala 364:56] + node _T_130 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 366:66] + node _T_131 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_130) @[dec_decode_ctl.scala 366:45] + node _T_132 = and(_T_131, cam[0].valid) @[dec_decode_ctl.scala 366:87] + cam_inv_reset_val[0] <= _T_132 @[dec_decode_ctl.scala 366:26] + node _T_133 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[0].bits.tag) @[dec_decode_ctl.scala 367:67] + node _T_134 = and(cam_data_reset, _T_133) @[dec_decode_ctl.scala 367:45] + node _T_135 = and(_T_134, cam_raw[0].valid) @[dec_decode_ctl.scala 367:88] + cam_data_reset_val[0] <= _T_135 @[dec_decode_ctl.scala 367:27] + wire _T_136 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 368:28] + _T_136.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 368:28] + _T_136.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 368:28] + _T_136.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28] + _T_136.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28] + cam_in[0].bits.rd <= _T_136.bits.rd @[dec_decode_ctl.scala 368:14] + cam_in[0].bits.tag <= _T_136.bits.tag @[dec_decode_ctl.scala 368:14] + cam_in[0].bits.wb <= _T_136.bits.wb @[dec_decode_ctl.scala 368:14] + cam_in[0].valid <= _T_136.valid @[dec_decode_ctl.scala 368:14] + cam[0].bits.rd <= cam_raw[0].bits.rd @[dec_decode_ctl.scala 369:11] + cam[0].bits.tag <= cam_raw[0].bits.tag @[dec_decode_ctl.scala 369:11] + cam[0].bits.wb <= cam_raw[0].bits.wb @[dec_decode_ctl.scala 369:11] + cam[0].valid <= cam_raw[0].valid @[dec_decode_ctl.scala 369:11] + node _T_137 = bits(cam_data_reset_val[0], 0, 0) @[dec_decode_ctl.scala 371:32] + when _T_137 : @[dec_decode_ctl.scala 371:39] + cam[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 372:20] + skip @[dec_decode_ctl.scala 371:39] + node _T_138 = bits(cam_wen, 0, 0) @[dec_decode_ctl.scala 374:17] + node _T_139 = bits(_T_138, 0, 0) @[dec_decode_ctl.scala 374:21] + when _T_139 : @[dec_decode_ctl.scala 374:28] + cam_in[0].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 375:27] + cam_in[0].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 376:32] + cam_in[0].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 377:32] + cam_in[0].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 378:32] + skip @[dec_decode_ctl.scala 374:28] + else : @[dec_decode_ctl.scala 379:131] + node _T_140 = bits(cam_inv_reset_val[0], 0, 0) @[dec_decode_ctl.scala 379:37] + node _T_141 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 379:57] + node _T_142 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[dec_decode_ctl.scala 379:85] + node _T_143 = and(_T_141, _T_142) @[dec_decode_ctl.scala 379:64] + node _T_144 = bits(cam[0].bits.wb, 0, 0) @[dec_decode_ctl.scala 379:123] + node _T_145 = and(_T_143, _T_144) @[dec_decode_ctl.scala 379:105] + node _T_146 = or(_T_140, _T_145) @[dec_decode_ctl.scala 379:44] + when _T_146 : @[dec_decode_ctl.scala 379:131] + cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 380:23] + skip @[dec_decode_ctl.scala 379:131] + else : @[dec_decode_ctl.scala 381:16] + cam_in[0].bits.rd <= cam[0].bits.rd @[dec_decode_ctl.scala 382:22] + cam_in[0].bits.tag <= cam[0].bits.tag @[dec_decode_ctl.scala 382:22] + cam_in[0].bits.wb <= cam[0].bits.wb @[dec_decode_ctl.scala 382:22] + cam_in[0].valid <= cam[0].valid @[dec_decode_ctl.scala 382:22] + skip @[dec_decode_ctl.scala 381:16] + node _T_147 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 384:37] + node _T_148 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 384:92] + node _T_149 = and(_T_147, _T_148) @[dec_decode_ctl.scala 384:44] + node _T_150 = eq(cam[0].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 384:128] + node _T_151 = and(_T_149, _T_150) @[dec_decode_ctl.scala 384:113] + when _T_151 : @[dec_decode_ctl.scala 384:135] + cam_in[0].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 385:25] + skip @[dec_decode_ctl.scala 384:135] + when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 388:32] + cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 389:23] + skip @[dec_decode_ctl.scala 388:32] + wire _T_152 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} + _T_152.bits.rd <= cam_in[0].bits.rd + _T_152.bits.tag <= cam_in[0].bits.tag + _T_152.bits.wb <= cam_in[0].bits.wb + _T_152.valid <= cam_in[0].valid + node _T_153 = cat(cam_in[0].bits.wb, cam_in[0].bits.tag) @[lib.scala 494:61] + node _T_154 = cat(_T_153, cam_in[0].bits.rd) @[lib.scala 494:61] + node _T_155 = cat(_T_152.bits.wb, _T_152.bits.tag) @[lib.scala 494:74] + node _T_156 = cat(_T_155, _T_152.bits.rd) @[lib.scala 494:74] + node _T_157 = xor(_T_154, _T_156) @[lib.scala 494:68] + node _T_158 = orr(_T_157) @[lib.scala 494:82] + node _T_159 = xor(cam_in[0].valid, _T_152.valid) @[lib.scala 494:68] + node _T_160 = orr(_T_159) @[lib.scala 494:82] + node _T_161 = or(_T_158, _T_160) @[lib.scala 494:97] + wire _T_162 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[lib.scala 497:46] + _T_162.bits.rd <= UInt<5>("h00") @[lib.scala 497:46] + _T_162.bits.tag <= UInt<3>("h00") @[lib.scala 497:46] + _T_162.bits.wb <= UInt<1>("h00") @[lib.scala 497:46] + _T_162.valid <= UInt<1>("h00") @[lib.scala 497:46] + reg _T_163 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, clock with : (reset => (reset, _T_162)) @[Reg.scala 27:20] + when _T_161 : @[Reg.scala 28:19] + _T_163.bits.rd <= cam_in[0].bits.rd @[Reg.scala 28:23] + _T_163.bits.tag <= cam_in[0].bits.tag @[Reg.scala 28:23] + _T_163.bits.wb <= cam_in[0].bits.wb @[Reg.scala 28:23] + _T_163.valid <= cam_in[0].valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_152.bits.rd <= _T_163.bits.rd @[lib.scala 497:16] + _T_152.bits.tag <= _T_163.bits.tag @[lib.scala 497:16] + _T_152.bits.wb <= _T_163.bits.wb @[lib.scala 497:16] + _T_152.valid <= _T_163.valid @[lib.scala 497:16] + cam_raw[0].bits.rd <= _T_152.bits.rd @[dec_decode_ctl.scala 392:15] + cam_raw[0].bits.tag <= _T_152.bits.tag @[dec_decode_ctl.scala 392:15] + cam_raw[0].bits.wb <= _T_152.bits.wb @[dec_decode_ctl.scala 392:15] + cam_raw[0].valid <= _T_152.valid @[dec_decode_ctl.scala 392:15] + node _T_164 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[dec_decode_ctl.scala 393:46] + node _T_165 = and(_T_164, cam_raw[0].valid) @[dec_decode_ctl.scala 393:71] + nonblock_load_write[0] <= _T_165 @[dec_decode_ctl.scala 393:28] + node _T_166 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 366:66] + node _T_167 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_166) @[dec_decode_ctl.scala 366:45] + node _T_168 = and(_T_167, cam[1].valid) @[dec_decode_ctl.scala 366:87] + cam_inv_reset_val[1] <= _T_168 @[dec_decode_ctl.scala 366:26] + node _T_169 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[1].bits.tag) @[dec_decode_ctl.scala 367:67] + node _T_170 = and(cam_data_reset, _T_169) @[dec_decode_ctl.scala 367:45] + node _T_171 = and(_T_170, cam_raw[1].valid) @[dec_decode_ctl.scala 367:88] + cam_data_reset_val[1] <= _T_171 @[dec_decode_ctl.scala 367:27] + wire _T_172 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 368:28] + _T_172.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 368:28] + _T_172.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 368:28] + _T_172.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28] + _T_172.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28] + cam_in[1].bits.rd <= _T_172.bits.rd @[dec_decode_ctl.scala 368:14] + cam_in[1].bits.tag <= _T_172.bits.tag @[dec_decode_ctl.scala 368:14] + cam_in[1].bits.wb <= _T_172.bits.wb @[dec_decode_ctl.scala 368:14] + cam_in[1].valid <= _T_172.valid @[dec_decode_ctl.scala 368:14] + cam[1].bits.rd <= cam_raw[1].bits.rd @[dec_decode_ctl.scala 369:11] + cam[1].bits.tag <= cam_raw[1].bits.tag @[dec_decode_ctl.scala 369:11] + cam[1].bits.wb <= cam_raw[1].bits.wb @[dec_decode_ctl.scala 369:11] + cam[1].valid <= cam_raw[1].valid @[dec_decode_ctl.scala 369:11] + node _T_173 = bits(cam_data_reset_val[1], 0, 0) @[dec_decode_ctl.scala 371:32] + when _T_173 : @[dec_decode_ctl.scala 371:39] + cam[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 372:20] + skip @[dec_decode_ctl.scala 371:39] + node _T_174 = bits(cam_wen, 1, 1) @[dec_decode_ctl.scala 374:17] + node _T_175 = bits(_T_174, 0, 0) @[dec_decode_ctl.scala 374:21] + when _T_175 : @[dec_decode_ctl.scala 374:28] + cam_in[1].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 375:27] + cam_in[1].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 376:32] + cam_in[1].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 377:32] + cam_in[1].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 378:32] + skip @[dec_decode_ctl.scala 374:28] + else : @[dec_decode_ctl.scala 379:131] + node _T_176 = bits(cam_inv_reset_val[1], 0, 0) @[dec_decode_ctl.scala 379:37] + node _T_177 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 379:57] + node _T_178 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[dec_decode_ctl.scala 379:85] + node _T_179 = and(_T_177, _T_178) @[dec_decode_ctl.scala 379:64] + node _T_180 = bits(cam[1].bits.wb, 0, 0) @[dec_decode_ctl.scala 379:123] + node _T_181 = and(_T_179, _T_180) @[dec_decode_ctl.scala 379:105] + node _T_182 = or(_T_176, _T_181) @[dec_decode_ctl.scala 379:44] + when _T_182 : @[dec_decode_ctl.scala 379:131] + cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 380:23] + skip @[dec_decode_ctl.scala 379:131] + else : @[dec_decode_ctl.scala 381:16] + cam_in[1].bits.rd <= cam[1].bits.rd @[dec_decode_ctl.scala 382:22] + cam_in[1].bits.tag <= cam[1].bits.tag @[dec_decode_ctl.scala 382:22] + cam_in[1].bits.wb <= cam[1].bits.wb @[dec_decode_ctl.scala 382:22] + cam_in[1].valid <= cam[1].valid @[dec_decode_ctl.scala 382:22] + skip @[dec_decode_ctl.scala 381:16] + node _T_183 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 384:37] + node _T_184 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 384:92] + node _T_185 = and(_T_183, _T_184) @[dec_decode_ctl.scala 384:44] + node _T_186 = eq(cam[1].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 384:128] + node _T_187 = and(_T_185, _T_186) @[dec_decode_ctl.scala 384:113] + when _T_187 : @[dec_decode_ctl.scala 384:135] + cam_in[1].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 385:25] + skip @[dec_decode_ctl.scala 384:135] + when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 388:32] + cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 389:23] + skip @[dec_decode_ctl.scala 388:32] + wire _T_188 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} + _T_188.bits.rd <= cam_in[1].bits.rd + _T_188.bits.tag <= cam_in[1].bits.tag + _T_188.bits.wb <= cam_in[1].bits.wb + _T_188.valid <= cam_in[1].valid + node _T_189 = cat(cam_in[1].bits.wb, cam_in[1].bits.tag) @[lib.scala 494:61] + node _T_190 = cat(_T_189, cam_in[1].bits.rd) @[lib.scala 494:61] + node _T_191 = cat(_T_188.bits.wb, _T_188.bits.tag) @[lib.scala 494:74] + node _T_192 = cat(_T_191, _T_188.bits.rd) @[lib.scala 494:74] + node _T_193 = xor(_T_190, _T_192) @[lib.scala 494:68] + node _T_194 = orr(_T_193) @[lib.scala 494:82] + node _T_195 = xor(cam_in[1].valid, _T_188.valid) @[lib.scala 494:68] + node _T_196 = orr(_T_195) @[lib.scala 494:82] + node _T_197 = or(_T_194, _T_196) @[lib.scala 494:97] + wire _T_198 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[lib.scala 497:46] + _T_198.bits.rd <= UInt<5>("h00") @[lib.scala 497:46] + _T_198.bits.tag <= UInt<3>("h00") @[lib.scala 497:46] + _T_198.bits.wb <= UInt<1>("h00") @[lib.scala 497:46] + _T_198.valid <= UInt<1>("h00") @[lib.scala 497:46] + reg _T_199 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, clock with : (reset => (reset, _T_198)) @[Reg.scala 27:20] + when _T_197 : @[Reg.scala 28:19] + _T_199.bits.rd <= cam_in[1].bits.rd @[Reg.scala 28:23] + _T_199.bits.tag <= cam_in[1].bits.tag @[Reg.scala 28:23] + _T_199.bits.wb <= cam_in[1].bits.wb @[Reg.scala 28:23] + _T_199.valid <= cam_in[1].valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_188.bits.rd <= _T_199.bits.rd @[lib.scala 497:16] + _T_188.bits.tag <= _T_199.bits.tag @[lib.scala 497:16] + _T_188.bits.wb <= _T_199.bits.wb @[lib.scala 497:16] + _T_188.valid <= _T_199.valid @[lib.scala 497:16] + cam_raw[1].bits.rd <= _T_188.bits.rd @[dec_decode_ctl.scala 392:15] + cam_raw[1].bits.tag <= _T_188.bits.tag @[dec_decode_ctl.scala 392:15] + cam_raw[1].bits.wb <= _T_188.bits.wb @[dec_decode_ctl.scala 392:15] + cam_raw[1].valid <= _T_188.valid @[dec_decode_ctl.scala 392:15] + node _T_200 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[dec_decode_ctl.scala 393:46] + node _T_201 = and(_T_200, cam_raw[1].valid) @[dec_decode_ctl.scala 393:71] + nonblock_load_write[1] <= _T_201 @[dec_decode_ctl.scala 393:28] + node _T_202 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 366:66] + node _T_203 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_202) @[dec_decode_ctl.scala 366:45] + node _T_204 = and(_T_203, cam[2].valid) @[dec_decode_ctl.scala 366:87] + cam_inv_reset_val[2] <= _T_204 @[dec_decode_ctl.scala 366:26] + node _T_205 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[2].bits.tag) @[dec_decode_ctl.scala 367:67] + node _T_206 = and(cam_data_reset, _T_205) @[dec_decode_ctl.scala 367:45] + node _T_207 = and(_T_206, cam_raw[2].valid) @[dec_decode_ctl.scala 367:88] + cam_data_reset_val[2] <= _T_207 @[dec_decode_ctl.scala 367:27] + wire _T_208 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 368:28] + _T_208.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 368:28] + _T_208.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 368:28] + _T_208.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28] + _T_208.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28] + cam_in[2].bits.rd <= _T_208.bits.rd @[dec_decode_ctl.scala 368:14] + cam_in[2].bits.tag <= _T_208.bits.tag @[dec_decode_ctl.scala 368:14] + cam_in[2].bits.wb <= _T_208.bits.wb @[dec_decode_ctl.scala 368:14] + cam_in[2].valid <= _T_208.valid @[dec_decode_ctl.scala 368:14] + cam[2].bits.rd <= cam_raw[2].bits.rd @[dec_decode_ctl.scala 369:11] + cam[2].bits.tag <= cam_raw[2].bits.tag @[dec_decode_ctl.scala 369:11] + cam[2].bits.wb <= cam_raw[2].bits.wb @[dec_decode_ctl.scala 369:11] + cam[2].valid <= cam_raw[2].valid @[dec_decode_ctl.scala 369:11] + node _T_209 = bits(cam_data_reset_val[2], 0, 0) @[dec_decode_ctl.scala 371:32] + when _T_209 : @[dec_decode_ctl.scala 371:39] + cam[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 372:20] + skip @[dec_decode_ctl.scala 371:39] + node _T_210 = bits(cam_wen, 2, 2) @[dec_decode_ctl.scala 374:17] + node _T_211 = bits(_T_210, 0, 0) @[dec_decode_ctl.scala 374:21] + when _T_211 : @[dec_decode_ctl.scala 374:28] + cam_in[2].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 375:27] + cam_in[2].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 376:32] + cam_in[2].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 377:32] + cam_in[2].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 378:32] + skip @[dec_decode_ctl.scala 374:28] + else : @[dec_decode_ctl.scala 379:131] + node _T_212 = bits(cam_inv_reset_val[2], 0, 0) @[dec_decode_ctl.scala 379:37] + node _T_213 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 379:57] + node _T_214 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[dec_decode_ctl.scala 379:85] + node _T_215 = and(_T_213, _T_214) @[dec_decode_ctl.scala 379:64] + node _T_216 = bits(cam[2].bits.wb, 0, 0) @[dec_decode_ctl.scala 379:123] + node _T_217 = and(_T_215, _T_216) @[dec_decode_ctl.scala 379:105] + node _T_218 = or(_T_212, _T_217) @[dec_decode_ctl.scala 379:44] + when _T_218 : @[dec_decode_ctl.scala 379:131] + cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 380:23] + skip @[dec_decode_ctl.scala 379:131] + else : @[dec_decode_ctl.scala 381:16] + cam_in[2].bits.rd <= cam[2].bits.rd @[dec_decode_ctl.scala 382:22] + cam_in[2].bits.tag <= cam[2].bits.tag @[dec_decode_ctl.scala 382:22] + cam_in[2].bits.wb <= cam[2].bits.wb @[dec_decode_ctl.scala 382:22] + cam_in[2].valid <= cam[2].valid @[dec_decode_ctl.scala 382:22] + skip @[dec_decode_ctl.scala 381:16] + node _T_219 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 384:37] + node _T_220 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 384:92] + node _T_221 = and(_T_219, _T_220) @[dec_decode_ctl.scala 384:44] + node _T_222 = eq(cam[2].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 384:128] + node _T_223 = and(_T_221, _T_222) @[dec_decode_ctl.scala 384:113] + when _T_223 : @[dec_decode_ctl.scala 384:135] + cam_in[2].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 385:25] + skip @[dec_decode_ctl.scala 384:135] + when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 388:32] + cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 389:23] + skip @[dec_decode_ctl.scala 388:32] + wire _T_224 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} + _T_224.bits.rd <= cam_in[2].bits.rd + _T_224.bits.tag <= cam_in[2].bits.tag + _T_224.bits.wb <= cam_in[2].bits.wb + _T_224.valid <= cam_in[2].valid + node _T_225 = cat(cam_in[2].bits.wb, cam_in[2].bits.tag) @[lib.scala 494:61] + node _T_226 = cat(_T_225, cam_in[2].bits.rd) @[lib.scala 494:61] + node _T_227 = cat(_T_224.bits.wb, _T_224.bits.tag) @[lib.scala 494:74] + node _T_228 = cat(_T_227, _T_224.bits.rd) @[lib.scala 494:74] + node _T_229 = xor(_T_226, _T_228) @[lib.scala 494:68] + node _T_230 = orr(_T_229) @[lib.scala 494:82] + node _T_231 = xor(cam_in[2].valid, _T_224.valid) @[lib.scala 494:68] + node _T_232 = orr(_T_231) @[lib.scala 494:82] + node _T_233 = or(_T_230, _T_232) @[lib.scala 494:97] + wire _T_234 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[lib.scala 497:46] + _T_234.bits.rd <= UInt<5>("h00") @[lib.scala 497:46] + _T_234.bits.tag <= UInt<3>("h00") @[lib.scala 497:46] + _T_234.bits.wb <= UInt<1>("h00") @[lib.scala 497:46] + _T_234.valid <= UInt<1>("h00") @[lib.scala 497:46] + reg _T_235 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, clock with : (reset => (reset, _T_234)) @[Reg.scala 27:20] + when _T_233 : @[Reg.scala 28:19] + _T_235.bits.rd <= cam_in[2].bits.rd @[Reg.scala 28:23] + _T_235.bits.tag <= cam_in[2].bits.tag @[Reg.scala 28:23] + _T_235.bits.wb <= cam_in[2].bits.wb @[Reg.scala 28:23] + _T_235.valid <= cam_in[2].valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_224.bits.rd <= _T_235.bits.rd @[lib.scala 497:16] + _T_224.bits.tag <= _T_235.bits.tag @[lib.scala 497:16] + _T_224.bits.wb <= _T_235.bits.wb @[lib.scala 497:16] + _T_224.valid <= _T_235.valid @[lib.scala 497:16] + cam_raw[2].bits.rd <= _T_224.bits.rd @[dec_decode_ctl.scala 392:15] + cam_raw[2].bits.tag <= _T_224.bits.tag @[dec_decode_ctl.scala 392:15] + cam_raw[2].bits.wb <= _T_224.bits.wb @[dec_decode_ctl.scala 392:15] + cam_raw[2].valid <= _T_224.valid @[dec_decode_ctl.scala 392:15] + node _T_236 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[dec_decode_ctl.scala 393:46] + node _T_237 = and(_T_236, cam_raw[2].valid) @[dec_decode_ctl.scala 393:71] + nonblock_load_write[2] <= _T_237 @[dec_decode_ctl.scala 393:28] + node _T_238 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 366:66] + node _T_239 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_238) @[dec_decode_ctl.scala 366:45] + node _T_240 = and(_T_239, cam[3].valid) @[dec_decode_ctl.scala 366:87] + cam_inv_reset_val[3] <= _T_240 @[dec_decode_ctl.scala 366:26] + node _T_241 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[3].bits.tag) @[dec_decode_ctl.scala 367:67] + node _T_242 = and(cam_data_reset, _T_241) @[dec_decode_ctl.scala 367:45] + node _T_243 = and(_T_242, cam_raw[3].valid) @[dec_decode_ctl.scala 367:88] + cam_data_reset_val[3] <= _T_243 @[dec_decode_ctl.scala 367:27] + wire _T_244 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 368:28] + _T_244.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 368:28] + _T_244.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 368:28] + _T_244.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28] + _T_244.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28] + cam_in[3].bits.rd <= _T_244.bits.rd @[dec_decode_ctl.scala 368:14] + cam_in[3].bits.tag <= _T_244.bits.tag @[dec_decode_ctl.scala 368:14] + cam_in[3].bits.wb <= _T_244.bits.wb @[dec_decode_ctl.scala 368:14] + cam_in[3].valid <= _T_244.valid @[dec_decode_ctl.scala 368:14] + cam[3].bits.rd <= cam_raw[3].bits.rd @[dec_decode_ctl.scala 369:11] + cam[3].bits.tag <= cam_raw[3].bits.tag @[dec_decode_ctl.scala 369:11] + cam[3].bits.wb <= cam_raw[3].bits.wb @[dec_decode_ctl.scala 369:11] + cam[3].valid <= cam_raw[3].valid @[dec_decode_ctl.scala 369:11] + node _T_245 = bits(cam_data_reset_val[3], 0, 0) @[dec_decode_ctl.scala 371:32] + when _T_245 : @[dec_decode_ctl.scala 371:39] + cam[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 372:20] + skip @[dec_decode_ctl.scala 371:39] + node _T_246 = bits(cam_wen, 3, 3) @[dec_decode_ctl.scala 374:17] + node _T_247 = bits(_T_246, 0, 0) @[dec_decode_ctl.scala 374:21] + when _T_247 : @[dec_decode_ctl.scala 374:28] + cam_in[3].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 375:27] + cam_in[3].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 376:32] + cam_in[3].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 377:32] + cam_in[3].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 378:32] + skip @[dec_decode_ctl.scala 374:28] + else : @[dec_decode_ctl.scala 379:131] + node _T_248 = bits(cam_inv_reset_val[3], 0, 0) @[dec_decode_ctl.scala 379:37] + node _T_249 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 379:57] + node _T_250 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[dec_decode_ctl.scala 379:85] + node _T_251 = and(_T_249, _T_250) @[dec_decode_ctl.scala 379:64] + node _T_252 = bits(cam[3].bits.wb, 0, 0) @[dec_decode_ctl.scala 379:123] + node _T_253 = and(_T_251, _T_252) @[dec_decode_ctl.scala 379:105] + node _T_254 = or(_T_248, _T_253) @[dec_decode_ctl.scala 379:44] + when _T_254 : @[dec_decode_ctl.scala 379:131] + cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 380:23] + skip @[dec_decode_ctl.scala 379:131] + else : @[dec_decode_ctl.scala 381:16] + cam_in[3].bits.rd <= cam[3].bits.rd @[dec_decode_ctl.scala 382:22] + cam_in[3].bits.tag <= cam[3].bits.tag @[dec_decode_ctl.scala 382:22] + cam_in[3].bits.wb <= cam[3].bits.wb @[dec_decode_ctl.scala 382:22] + cam_in[3].valid <= cam[3].valid @[dec_decode_ctl.scala 382:22] + skip @[dec_decode_ctl.scala 381:16] + node _T_255 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 384:37] + node _T_256 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 384:92] + node _T_257 = and(_T_255, _T_256) @[dec_decode_ctl.scala 384:44] + node _T_258 = eq(cam[3].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 384:128] + node _T_259 = and(_T_257, _T_258) @[dec_decode_ctl.scala 384:113] + when _T_259 : @[dec_decode_ctl.scala 384:135] + cam_in[3].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 385:25] + skip @[dec_decode_ctl.scala 384:135] + when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 388:32] + cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 389:23] + skip @[dec_decode_ctl.scala 388:32] + wire _T_260 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} + _T_260.bits.rd <= cam_in[3].bits.rd + _T_260.bits.tag <= cam_in[3].bits.tag + _T_260.bits.wb <= cam_in[3].bits.wb + _T_260.valid <= cam_in[3].valid + node _T_261 = cat(cam_in[3].bits.wb, cam_in[3].bits.tag) @[lib.scala 494:61] + node _T_262 = cat(_T_261, cam_in[3].bits.rd) @[lib.scala 494:61] + node _T_263 = cat(_T_260.bits.wb, _T_260.bits.tag) @[lib.scala 494:74] + node _T_264 = cat(_T_263, _T_260.bits.rd) @[lib.scala 494:74] + node _T_265 = xor(_T_262, _T_264) @[lib.scala 494:68] + node _T_266 = orr(_T_265) @[lib.scala 494:82] + node _T_267 = xor(cam_in[3].valid, _T_260.valid) @[lib.scala 494:68] + node _T_268 = orr(_T_267) @[lib.scala 494:82] + node _T_269 = or(_T_266, _T_268) @[lib.scala 494:97] + wire _T_270 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[lib.scala 497:46] + _T_270.bits.rd <= UInt<5>("h00") @[lib.scala 497:46] + _T_270.bits.tag <= UInt<3>("h00") @[lib.scala 497:46] + _T_270.bits.wb <= UInt<1>("h00") @[lib.scala 497:46] + _T_270.valid <= UInt<1>("h00") @[lib.scala 497:46] + reg _T_271 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, clock with : (reset => (reset, _T_270)) @[Reg.scala 27:20] + when _T_269 : @[Reg.scala 28:19] + _T_271.bits.rd <= cam_in[3].bits.rd @[Reg.scala 28:23] + _T_271.bits.tag <= cam_in[3].bits.tag @[Reg.scala 28:23] + _T_271.bits.wb <= cam_in[3].bits.wb @[Reg.scala 28:23] + _T_271.valid <= cam_in[3].valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_260.bits.rd <= _T_271.bits.rd @[lib.scala 497:16] + _T_260.bits.tag <= _T_271.bits.tag @[lib.scala 497:16] + _T_260.bits.wb <= _T_271.bits.wb @[lib.scala 497:16] + _T_260.valid <= _T_271.valid @[lib.scala 497:16] + cam_raw[3].bits.rd <= _T_260.bits.rd @[dec_decode_ctl.scala 392:15] + cam_raw[3].bits.tag <= _T_260.bits.tag @[dec_decode_ctl.scala 392:15] + cam_raw[3].bits.wb <= _T_260.bits.wb @[dec_decode_ctl.scala 392:15] + cam_raw[3].valid <= _T_260.valid @[dec_decode_ctl.scala 392:15] + node _T_272 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[dec_decode_ctl.scala 393:46] + node _T_273 = and(_T_272, cam_raw[3].valid) @[dec_decode_ctl.scala 393:71] + nonblock_load_write[3] <= _T_273 @[dec_decode_ctl.scala 393:28] + io.dec_nonblock_load_waddr <= UInt<5>("h00") @[dec_decode_ctl.scala 396:29] + node _T_274 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[dec_decode_ctl.scala 398:49] + node nonblock_load_cancel = and(_T_274, i0_wen_r) @[dec_decode_ctl.scala 398:81] + node _T_275 = or(nonblock_load_write[0], nonblock_load_write[1]) @[dec_decode_ctl.scala 399:108] + node _T_276 = or(_T_275, nonblock_load_write[2]) @[dec_decode_ctl.scala 399:108] + node _T_277 = or(_T_276, nonblock_load_write[3]) @[dec_decode_ctl.scala 399:108] + node _T_278 = bits(_T_277, 0, 0) @[dec_decode_ctl.scala 399:112] + node _T_279 = and(io.dctl_busbuff.lsu_nonblock_load_data_valid, _T_278) @[dec_decode_ctl.scala 399:77] + node _T_280 = eq(nonblock_load_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 399:122] + node _T_281 = and(_T_279, _T_280) @[dec_decode_ctl.scala 399:119] + io.dec_nonblock_load_wen <= _T_281 @[dec_decode_ctl.scala 399:28] + node _T_282 = eq(nonblock_load_rd, i0r.rs1) @[dec_decode_ctl.scala 400:54] + node _T_283 = and(_T_282, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 400:66] + node _T_284 = and(_T_283, io.decode_exu.dec_i0_rs1_en_d) @[dec_decode_ctl.scala 400:110] + node _T_285 = eq(nonblock_load_rd, i0r.rs2) @[dec_decode_ctl.scala 400:161] + node _T_286 = and(_T_285, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 400:173] + node _T_287 = and(_T_286, io.decode_exu.dec_i0_rs2_en_d) @[dec_decode_ctl.scala 400:217] + node i0_nonblock_boundary_stall = or(_T_284, _T_287) @[dec_decode_ctl.scala 400:142] + i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[dec_decode_ctl.scala 402:26] + node _T_288 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15] + node _T_289 = mux(_T_288, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_290 = and(_T_289, cam[0].bits.rd) @[dec_decode_ctl.scala 404:88] + node _T_291 = and(io.decode_exu.dec_i0_rs1_en_d, cam[0].valid) @[dec_decode_ctl.scala 404:137] + node _T_292 = eq(cam[0].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 404:170] + node _T_293 = and(_T_291, _T_292) @[dec_decode_ctl.scala 404:152] + node _T_294 = and(io.decode_exu.dec_i0_rs2_en_d, cam[0].valid) @[dec_decode_ctl.scala 404:214] + node _T_295 = eq(cam[0].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 404:247] + node _T_296 = and(_T_294, _T_295) @[dec_decode_ctl.scala 404:229] + node _T_297 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15] + node _T_298 = mux(_T_297, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_299 = and(_T_298, cam[1].bits.rd) @[dec_decode_ctl.scala 404:88] + node _T_300 = and(io.decode_exu.dec_i0_rs1_en_d, cam[1].valid) @[dec_decode_ctl.scala 404:137] + node _T_301 = eq(cam[1].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 404:170] + node _T_302 = and(_T_300, _T_301) @[dec_decode_ctl.scala 404:152] + node _T_303 = and(io.decode_exu.dec_i0_rs2_en_d, cam[1].valid) @[dec_decode_ctl.scala 404:214] + node _T_304 = eq(cam[1].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 404:247] + node _T_305 = and(_T_303, _T_304) @[dec_decode_ctl.scala 404:229] + node _T_306 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15] + node _T_307 = mux(_T_306, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_308 = and(_T_307, cam[2].bits.rd) @[dec_decode_ctl.scala 404:88] + node _T_309 = and(io.decode_exu.dec_i0_rs1_en_d, cam[2].valid) @[dec_decode_ctl.scala 404:137] + node _T_310 = eq(cam[2].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 404:170] + node _T_311 = and(_T_309, _T_310) @[dec_decode_ctl.scala 404:152] + node _T_312 = and(io.decode_exu.dec_i0_rs2_en_d, cam[2].valid) @[dec_decode_ctl.scala 404:214] + node _T_313 = eq(cam[2].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 404:247] + node _T_314 = and(_T_312, _T_313) @[dec_decode_ctl.scala 404:229] + node _T_315 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15] + node _T_316 = mux(_T_315, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_317 = and(_T_316, cam[3].bits.rd) @[dec_decode_ctl.scala 404:88] + node _T_318 = and(io.decode_exu.dec_i0_rs1_en_d, cam[3].valid) @[dec_decode_ctl.scala 404:137] + node _T_319 = eq(cam[3].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 404:170] + node _T_320 = and(_T_318, _T_319) @[dec_decode_ctl.scala 404:152] + node _T_321 = and(io.decode_exu.dec_i0_rs2_en_d, cam[3].valid) @[dec_decode_ctl.scala 404:214] + node _T_322 = eq(cam[3].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 404:247] + node _T_323 = and(_T_321, _T_322) @[dec_decode_ctl.scala 404:229] + node _T_324 = or(_T_290, _T_299) @[dec_decode_ctl.scala 405:69] + node _T_325 = or(_T_324, _T_308) @[dec_decode_ctl.scala 405:69] + node waddr = or(_T_325, _T_317) @[dec_decode_ctl.scala 405:69] + node _T_326 = or(_T_293, _T_302) @[dec_decode_ctl.scala 405:102] + node _T_327 = or(_T_326, _T_311) @[dec_decode_ctl.scala 405:102] + node ld_stall_1 = or(_T_327, _T_320) @[dec_decode_ctl.scala 405:102] + node _T_328 = or(_T_296, _T_305) @[dec_decode_ctl.scala 405:134] + node _T_329 = or(_T_328, _T_314) @[dec_decode_ctl.scala 405:134] + node ld_stall_2 = or(_T_329, _T_323) @[dec_decode_ctl.scala 405:134] + io.dec_nonblock_load_waddr <= waddr @[dec_decode_ctl.scala 406:29] + node _T_330 = or(ld_stall_1, ld_stall_2) @[dec_decode_ctl.scala 407:38] + node _T_331 = or(_T_330, i0_nonblock_boundary_stall) @[dec_decode_ctl.scala 407:51] + i0_nonblock_load_stall <= _T_331 @[dec_decode_ctl.scala 407:25] + node _T_332 = eq(i0_predict_br, UInt<1>("h00")) @[dec_decode_ctl.scala 416:34] + node i0_br_unpred = and(i0_dp.jal, _T_332) @[dec_decode_ctl.scala 416:32] + node _T_333 = bits(i0_legal_decode_d, 0, 0) @[Bitwise.scala 72:15] + node _T_334 = mux(_T_333, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_335 = and(csr_read, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 428:16] + node _T_336 = bits(_T_335, 0, 0) @[dec_decode_ctl.scala 428:30] + node _T_337 = eq(csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 429:6] + node _T_338 = and(_T_337, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 429:16] + node _T_339 = bits(_T_338, 0, 0) @[dec_decode_ctl.scala 429:30] + node _T_340 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[dec_decode_ctl.scala 430:18] + node _T_341 = and(csr_read, _T_340) @[dec_decode_ctl.scala 430:16] + node _T_342 = bits(_T_341, 0, 0) @[dec_decode_ctl.scala 430:30] + node _T_343 = or(i0_dp.zbb, i0_dp.zbs) @[dec_decode_ctl.scala 431:16] + node _T_344 = or(_T_343, i0_dp.zbe) @[dec_decode_ctl.scala 431:28] + node _T_345 = or(_T_344, i0_dp.zbc) @[dec_decode_ctl.scala 431:40] + node _T_346 = or(_T_345, i0_dp.zbp) @[dec_decode_ctl.scala 431:52] + node _T_347 = or(_T_346, i0_dp.zbr) @[dec_decode_ctl.scala 431:65] + node _T_348 = or(_T_347, i0_dp.zbf) @[dec_decode_ctl.scala 431:77] + node _T_349 = or(_T_348, i0_dp.zba) @[dec_decode_ctl.scala 431:89] + node _T_350 = mux(i0_dp.mul, UInt<4>("h01"), UInt<4>("h00")) @[Mux.scala 98:16] + node _T_351 = mux(i0_dp.load, UInt<4>("h02"), _T_350) @[Mux.scala 98:16] + node _T_352 = mux(i0_dp.store, UInt<4>("h03"), _T_351) @[Mux.scala 98:16] + node _T_353 = mux(i0_dp.pm_alu, UInt<4>("h04"), _T_352) @[Mux.scala 98:16] + node _T_354 = mux(_T_349, UInt<4>("h0f"), _T_353) @[Mux.scala 98:16] + node _T_355 = mux(_T_342, UInt<4>("h05"), _T_354) @[Mux.scala 98:16] + node _T_356 = mux(_T_339, UInt<4>("h06"), _T_355) @[Mux.scala 98:16] + node _T_357 = mux(_T_336, UInt<4>("h07"), _T_356) @[Mux.scala 98:16] + node _T_358 = mux(i0_dp.ebreak, UInt<4>("h08"), _T_357) @[Mux.scala 98:16] + node _T_359 = mux(i0_dp.ecall, UInt<4>("h09"), _T_358) @[Mux.scala 98:16] + node _T_360 = mux(i0_dp.fence, UInt<4>("h0a"), _T_359) @[Mux.scala 98:16] + node _T_361 = mux(i0_dp.fence_i, UInt<4>("h0b"), _T_360) @[Mux.scala 98:16] + node _T_362 = mux(i0_dp.mret, UInt<4>("h0c"), _T_361) @[Mux.scala 98:16] + node _T_363 = mux(i0_dp.condbr, UInt<4>("h0d"), _T_362) @[Mux.scala 98:16] + node _T_364 = mux(i0_dp.jal, UInt<4>("h0e"), _T_363) @[Mux.scala 98:16] + node _T_365 = and(_T_334, _T_364) @[dec_decode_ctl.scala 420:49] + d_t.pmu_i0_itype <= _T_365 @[dec_decode_ctl.scala 420:21] + inst i0_dec of dec_dec_ctl @[dec_decode_ctl.scala 438:22] + i0_dec.clock <= clock + i0_dec.reset <= reset + i0_dec.io.ins <= io.dec_i0_instr_d @[dec_decode_ctl.scala 439:16] + i0_dp_raw.legal <= i0_dec.io.out.legal @[dec_decode_ctl.scala 440:12] + i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[dec_decode_ctl.scala 440:12] + i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[dec_decode_ctl.scala 440:12] + i0_dp_raw.fence <= i0_dec.io.out.fence @[dec_decode_ctl.scala 440:12] + i0_dp_raw.rem <= i0_dec.io.out.rem @[dec_decode_ctl.scala 440:12] + i0_dp_raw.div <= i0_dec.io.out.div @[dec_decode_ctl.scala 440:12] + i0_dp_raw.low <= i0_dec.io.out.low @[dec_decode_ctl.scala 440:12] + i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[dec_decode_ctl.scala 440:12] + i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[dec_decode_ctl.scala 440:12] + i0_dp_raw.mul <= i0_dec.io.out.mul @[dec_decode_ctl.scala 440:12] + i0_dp_raw.mret <= i0_dec.io.out.mret @[dec_decode_ctl.scala 440:12] + i0_dp_raw.ecall <= i0_dec.io.out.ecall @[dec_decode_ctl.scala 440:12] + i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[dec_decode_ctl.scala 440:12] + i0_dp_raw.postsync <= i0_dec.io.out.postsync @[dec_decode_ctl.scala 440:12] + i0_dp_raw.presync <= i0_dec.io.out.presync @[dec_decode_ctl.scala 440:12] + i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[dec_decode_ctl.scala 440:12] + i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[dec_decode_ctl.scala 440:12] + i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[dec_decode_ctl.scala 440:12] + i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[dec_decode_ctl.scala 440:12] + i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[dec_decode_ctl.scala 440:12] + i0_dp_raw.word <= i0_dec.io.out.word @[dec_decode_ctl.scala 440:12] + i0_dp_raw.half <= i0_dec.io.out.half @[dec_decode_ctl.scala 440:12] + i0_dp_raw.by <= i0_dec.io.out.by @[dec_decode_ctl.scala 440:12] + i0_dp_raw.jal <= i0_dec.io.out.jal @[dec_decode_ctl.scala 440:12] + i0_dp_raw.blt <= i0_dec.io.out.blt @[dec_decode_ctl.scala 440:12] + i0_dp_raw.bge <= i0_dec.io.out.bge @[dec_decode_ctl.scala 440:12] + i0_dp_raw.bne <= i0_dec.io.out.bne @[dec_decode_ctl.scala 440:12] + i0_dp_raw.beq <= i0_dec.io.out.beq @[dec_decode_ctl.scala 440:12] + i0_dp_raw.condbr <= i0_dec.io.out.condbr @[dec_decode_ctl.scala 440:12] + i0_dp_raw.unsign <= i0_dec.io.out.unsign @[dec_decode_ctl.scala 440:12] + i0_dp_raw.slt <= i0_dec.io.out.slt @[dec_decode_ctl.scala 440:12] + i0_dp_raw.srl <= i0_dec.io.out.srl @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sra <= i0_dec.io.out.sra @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sll <= i0_dec.io.out.sll @[dec_decode_ctl.scala 440:12] + i0_dp_raw.lxor <= i0_dec.io.out.lxor @[dec_decode_ctl.scala 440:12] + i0_dp_raw.lor <= i0_dec.io.out.lor @[dec_decode_ctl.scala 440:12] + i0_dp_raw.land <= i0_dec.io.out.land @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sub <= i0_dec.io.out.sub @[dec_decode_ctl.scala 440:12] + i0_dp_raw.add <= i0_dec.io.out.add @[dec_decode_ctl.scala 440:12] + i0_dp_raw.lsu <= i0_dec.io.out.lsu @[dec_decode_ctl.scala 440:12] + i0_dp_raw.store <= i0_dec.io.out.store @[dec_decode_ctl.scala 440:12] + i0_dp_raw.load <= i0_dec.io.out.load @[dec_decode_ctl.scala 440:12] + i0_dp_raw.pc <= i0_dec.io.out.pc @[dec_decode_ctl.scala 440:12] + i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[dec_decode_ctl.scala 440:12] + i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[dec_decode_ctl.scala 440:12] + i0_dp_raw.rd <= i0_dec.io.out.rd @[dec_decode_ctl.scala 440:12] + i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[dec_decode_ctl.scala 440:12] + i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[dec_decode_ctl.scala 440:12] + i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[dec_decode_ctl.scala 440:12] + i0_dp_raw.alu <= i0_dec.io.out.alu @[dec_decode_ctl.scala 440:12] + i0_dp_raw.zba <= i0_dec.io.out.zba @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sh3add <= i0_dec.io.out.sh3add @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sh2add <= i0_dec.io.out.sh2add @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sh1add <= i0_dec.io.out.sh1add @[dec_decode_ctl.scala 440:12] + i0_dp_raw.zbf <= i0_dec.io.out.zbf @[dec_decode_ctl.scala 440:12] + i0_dp_raw.bfp <= i0_dec.io.out.bfp @[dec_decode_ctl.scala 440:12] + i0_dp_raw.zbr <= i0_dec.io.out.zbr @[dec_decode_ctl.scala 440:12] + i0_dp_raw.crc32c_w <= i0_dec.io.out.crc32c_w @[dec_decode_ctl.scala 440:12] + i0_dp_raw.crc32c_h <= i0_dec.io.out.crc32c_h @[dec_decode_ctl.scala 440:12] + i0_dp_raw.crc32c_b <= i0_dec.io.out.crc32c_b @[dec_decode_ctl.scala 440:12] + i0_dp_raw.crc32_w <= i0_dec.io.out.crc32_w @[dec_decode_ctl.scala 440:12] + i0_dp_raw.crc32_h <= i0_dec.io.out.crc32_h @[dec_decode_ctl.scala 440:12] + i0_dp_raw.crc32_b <= i0_dec.io.out.crc32_b @[dec_decode_ctl.scala 440:12] + i0_dp_raw.zbp <= i0_dec.io.out.zbp @[dec_decode_ctl.scala 440:12] + i0_dp_raw.unshfl <= i0_dec.io.out.unshfl @[dec_decode_ctl.scala 440:12] + i0_dp_raw.shfl <= i0_dec.io.out.shfl @[dec_decode_ctl.scala 440:12] + i0_dp_raw.zbc <= i0_dec.io.out.zbc @[dec_decode_ctl.scala 440:12] + i0_dp_raw.clmulr <= i0_dec.io.out.clmulr @[dec_decode_ctl.scala 440:12] + i0_dp_raw.clmulh <= i0_dec.io.out.clmulh @[dec_decode_ctl.scala 440:12] + i0_dp_raw.clmul <= i0_dec.io.out.clmul @[dec_decode_ctl.scala 440:12] + i0_dp_raw.zbe <= i0_dec.io.out.zbe @[dec_decode_ctl.scala 440:12] + i0_dp_raw.bdep <= i0_dec.io.out.bdep @[dec_decode_ctl.scala 440:12] + i0_dp_raw.bext <= i0_dec.io.out.bext @[dec_decode_ctl.scala 440:12] + i0_dp_raw.zbs <= i0_dec.io.out.zbs @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sbext <= i0_dec.io.out.sbext @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sbinv <= i0_dec.io.out.sbinv @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sbclr <= i0_dec.io.out.sbclr @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sbset <= i0_dec.io.out.sbset @[dec_decode_ctl.scala 440:12] + i0_dp_raw.zbb <= i0_dec.io.out.zbb @[dec_decode_ctl.scala 440:12] + i0_dp_raw.gorc <= i0_dec.io.out.gorc @[dec_decode_ctl.scala 440:12] + i0_dp_raw.grev <= i0_dec.io.out.grev @[dec_decode_ctl.scala 440:12] + i0_dp_raw.ror <= i0_dec.io.out.ror @[dec_decode_ctl.scala 440:12] + i0_dp_raw.rol <= i0_dec.io.out.rol @[dec_decode_ctl.scala 440:12] + i0_dp_raw.packh <= i0_dec.io.out.packh @[dec_decode_ctl.scala 440:12] + i0_dp_raw.packu <= i0_dec.io.out.packu @[dec_decode_ctl.scala 440:12] + i0_dp_raw.pack <= i0_dec.io.out.pack @[dec_decode_ctl.scala 440:12] + i0_dp_raw.max <= i0_dec.io.out.max @[dec_decode_ctl.scala 440:12] + i0_dp_raw.min <= i0_dec.io.out.min @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sro <= i0_dec.io.out.sro @[dec_decode_ctl.scala 440:12] + i0_dp_raw.slo <= i0_dec.io.out.slo @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sext_h <= i0_dec.io.out.sext_h @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sext_b <= i0_dec.io.out.sext_b @[dec_decode_ctl.scala 440:12] + i0_dp_raw.pcnt <= i0_dec.io.out.pcnt @[dec_decode_ctl.scala 440:12] + i0_dp_raw.ctz <= i0_dec.io.out.ctz @[dec_decode_ctl.scala 440:12] + i0_dp_raw.clz <= i0_dec.io.out.clz @[dec_decode_ctl.scala 440:12] + reg _T_366 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 442:45] + _T_366 <= io.lsu_idle_any @[dec_decode_ctl.scala 442:45] + lsu_idle <= _T_366 @[dec_decode_ctl.scala 442:11] + node _T_367 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 445:73] + node _T_368 = and(leak1_i1_stall, _T_367) @[dec_decode_ctl.scala 445:71] + node _T_369 = or(io.dec_tlu_flush_leak_one_r, _T_368) @[dec_decode_ctl.scala 445:53] + leak1_i1_stall_in <= _T_369 @[dec_decode_ctl.scala 445:21] + leak1_mode <= leak1_i1_stall @[dec_decode_ctl.scala 446:14] + node _T_370 = and(io.dec_aln.dec_i0_decode_d, leak1_i1_stall) @[dec_decode_ctl.scala 447:53] + node _T_371 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 447:91] + node _T_372 = and(leak1_i0_stall, _T_371) @[dec_decode_ctl.scala 447:89] + node _T_373 = or(_T_370, _T_372) @[dec_decode_ctl.scala 447:71] + leak1_i0_stall_in <= _T_373 @[dec_decode_ctl.scala 447:21] + node _T_374 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 451:29] + node _T_375 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 451:36] + node _T_376 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 451:46] + node _T_377 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 451:53] + node _T_378 = cat(_T_376, _T_377) @[Cat.scala 29:58] + node _T_379 = cat(_T_374, _T_375) @[Cat.scala 29:58] + node i0_pcall_imm = cat(_T_379, _T_378) @[Cat.scala 29:58] + node _T_380 = bits(i0_pcall_imm, 11, 11) @[dec_decode_ctl.scala 452:46] + node _T_381 = bits(_T_380, 0, 0) @[dec_decode_ctl.scala 452:51] + node _T_382 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 452:71] + node _T_383 = eq(_T_382, UInt<8>("h0ff")) @[dec_decode_ctl.scala 452:79] + node _T_384 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 452:104] + node _T_385 = eq(_T_384, UInt<8>("h00")) @[dec_decode_ctl.scala 452:112] + node i0_pcall_12b_offset = mux(_T_381, _T_383, _T_385) @[dec_decode_ctl.scala 452:33] + node _T_386 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 453:47] + node _T_387 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 453:76] + node _T_388 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 453:98] + node _T_389 = or(_T_387, _T_388) @[dec_decode_ctl.scala 453:89] + node i0_pcall_case = and(_T_386, _T_389) @[dec_decode_ctl.scala 453:65] + node _T_390 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 454:47] + node _T_391 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 454:76] + node _T_392 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 454:98] + node _T_393 = or(_T_391, _T_392) @[dec_decode_ctl.scala 454:89] + node _T_394 = eq(_T_393, UInt<1>("h00")) @[dec_decode_ctl.scala 454:67] + node i0_pja_case = and(_T_390, _T_394) @[dec_decode_ctl.scala 454:65] + node _T_395 = and(i0_dp_raw.jal, i0_pcall_case) @[dec_decode_ctl.scala 455:38] + i0_pcall_raw <= _T_395 @[dec_decode_ctl.scala 455:20] + node _T_396 = and(i0_dp.jal, i0_pcall_case) @[dec_decode_ctl.scala 456:38] + i0_pcall <= _T_396 @[dec_decode_ctl.scala 456:20] + node _T_397 = and(i0_dp_raw.jal, i0_pja_case) @[dec_decode_ctl.scala 457:38] + i0_pja_raw <= _T_397 @[dec_decode_ctl.scala 457:20] + node _T_398 = and(i0_dp.jal, i0_pja_case) @[dec_decode_ctl.scala 458:38] + i0_pja <= _T_398 @[dec_decode_ctl.scala 458:20] + node _T_399 = or(i0_pcall_raw, i0_pja_raw) @[dec_decode_ctl.scala 459:41] + node _T_400 = bits(_T_399, 0, 0) @[dec_decode_ctl.scala 459:55] + node _T_401 = bits(i0_pcall_imm, 11, 0) @[dec_decode_ctl.scala 459:75] + node _T_402 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 459:90] + node _T_403 = bits(io.dec_i0_instr_d, 7, 7) @[dec_decode_ctl.scala 459:97] + node _T_404 = bits(io.dec_i0_instr_d, 30, 25) @[dec_decode_ctl.scala 459:103] + node _T_405 = bits(io.dec_i0_instr_d, 11, 8) @[dec_decode_ctl.scala 459:113] + node _T_406 = cat(_T_404, _T_405) @[Cat.scala 29:58] + node _T_407 = cat(_T_402, _T_403) @[Cat.scala 29:58] + node _T_408 = cat(_T_407, _T_406) @[Cat.scala 29:58] + node _T_409 = mux(_T_400, _T_401, _T_408) @[dec_decode_ctl.scala 459:26] + i0_br_offset <= _T_409 @[dec_decode_ctl.scala 459:20] + node _T_410 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[dec_decode_ctl.scala 461:37] + node _T_411 = eq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 461:65] + node _T_412 = and(_T_410, _T_411) @[dec_decode_ctl.scala 461:55] + node _T_413 = eq(i0r.rs1, UInt<5>("h01")) @[dec_decode_ctl.scala 461:89] + node _T_414 = eq(i0r.rs1, UInt<5>("h05")) @[dec_decode_ctl.scala 461:111] + node _T_415 = or(_T_413, _T_414) @[dec_decode_ctl.scala 461:101] + node i0_pret_case = and(_T_412, _T_415) @[dec_decode_ctl.scala 461:79] + node _T_416 = and(i0_dp_raw.jal, i0_pret_case) @[dec_decode_ctl.scala 462:32] + i0_pret_raw <= _T_416 @[dec_decode_ctl.scala 462:15] + node _T_417 = and(i0_dp.jal, i0_pret_case) @[dec_decode_ctl.scala 463:32] + i0_pret <= _T_417 @[dec_decode_ctl.scala 463:15] + node _T_418 = eq(i0_pcall_case, UInt<1>("h00")) @[dec_decode_ctl.scala 464:35] + node _T_419 = and(i0_dp.jal, _T_418) @[dec_decode_ctl.scala 464:32] + node _T_420 = eq(i0_pja_case, UInt<1>("h00")) @[dec_decode_ctl.scala 464:52] + node _T_421 = and(_T_419, _T_420) @[dec_decode_ctl.scala 464:50] + node _T_422 = eq(i0_pret_case, UInt<1>("h00")) @[dec_decode_ctl.scala 464:67] + node _T_423 = and(_T_421, _T_422) @[dec_decode_ctl.scala 464:65] + i0_jal <= _T_423 @[dec_decode_ctl.scala 464:15] + io.dec_div.div_p.valid <= div_decode_d @[dec_decode_ctl.scala 467:29] + io.dec_div.div_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 468:34] + io.dec_div.div_p.bits.rem <= i0_dp.rem @[dec_decode_ctl.scala 469:34] + io.decode_exu.mul_p.valid <= mul_decode_d @[dec_decode_ctl.scala 471:32] + io.decode_exu.mul_p.bits.rs1_sign <= i0_dp.rs1_sign @[dec_decode_ctl.scala 472:37] + io.decode_exu.mul_p.bits.rs2_sign <= i0_dp.rs2_sign @[dec_decode_ctl.scala 473:37] + io.decode_exu.mul_p.bits.low <= i0_dp.low @[dec_decode_ctl.scala 474:37] + io.decode_exu.mul_p.bits.bext <= i0_dp.bext @[dec_decode_ctl.scala 475:37] + io.decode_exu.mul_p.bits.bdep <= i0_dp.bdep @[dec_decode_ctl.scala 476:37] + io.decode_exu.mul_p.bits.clmul <= i0_dp.clmul @[dec_decode_ctl.scala 477:37] + io.decode_exu.mul_p.bits.clmulh <= i0_dp.clmulh @[dec_decode_ctl.scala 478:37] + io.decode_exu.mul_p.bits.clmulr <= i0_dp.clmulr @[dec_decode_ctl.scala 479:37] + io.decode_exu.mul_p.bits.grev <= i0_dp.grev @[dec_decode_ctl.scala 480:37] + io.decode_exu.mul_p.bits.gorc <= i0_dp.gorc @[dec_decode_ctl.scala 481:37] + io.decode_exu.mul_p.bits.shfl <= i0_dp.shfl @[dec_decode_ctl.scala 482:37] + io.decode_exu.mul_p.bits.unshfl <= i0_dp.unshfl @[dec_decode_ctl.scala 483:37] + io.decode_exu.mul_p.bits.crc32_b <= i0_dp.crc32_b @[dec_decode_ctl.scala 484:37] + io.decode_exu.mul_p.bits.crc32_h <= i0_dp.crc32_h @[dec_decode_ctl.scala 485:37] + io.decode_exu.mul_p.bits.crc32_w <= i0_dp.crc32_w @[dec_decode_ctl.scala 486:37] + io.decode_exu.mul_p.bits.crc32c_b <= i0_dp.crc32c_b @[dec_decode_ctl.scala 487:37] + io.decode_exu.mul_p.bits.crc32c_h <= i0_dp.crc32c_h @[dec_decode_ctl.scala 488:37] + io.decode_exu.mul_p.bits.crc32c_w <= i0_dp.crc32c_w @[dec_decode_ctl.scala 489:37] + io.decode_exu.mul_p.bits.bfp <= i0_dp.bfp @[dec_decode_ctl.scala 490:37] + wire _T_424 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[dec_decode_ctl.scala 493:27] + _T_424.bits.store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.load_ldst_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.store_data_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.dma <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.store <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.load <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.dword <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.word <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.half <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.by <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.stack <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.fast_int <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + io.lsu_p.bits.store_data_bypass_m <= _T_424.bits.store_data_bypass_m @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.load_ldst_bypass_d <= _T_424.bits.load_ldst_bypass_d @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.store_data_bypass_d <= _T_424.bits.store_data_bypass_d @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.dma <= _T_424.bits.dma @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.unsign <= _T_424.bits.unsign @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.store <= _T_424.bits.store @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.load <= _T_424.bits.load @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.dword <= _T_424.bits.dword @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.word <= _T_424.bits.word @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.half <= _T_424.bits.half @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.by <= _T_424.bits.by @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.stack <= _T_424.bits.stack @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.fast_int <= _T_424.bits.fast_int @[dec_decode_ctl.scala 493:12] + io.lsu_p.valid <= _T_424.valid @[dec_decode_ctl.scala 493:12] + when io.decode_exu.dec_extint_stall : @[dec_decode_ctl.scala 494:40] + io.lsu_p.bits.load <= UInt<1>("h01") @[dec_decode_ctl.scala 495:29] + io.lsu_p.bits.word <= UInt<1>("h01") @[dec_decode_ctl.scala 496:29] + io.lsu_p.bits.fast_int <= UInt<1>("h01") @[dec_decode_ctl.scala 497:29] + io.lsu_p.valid <= UInt<1>("h01") @[dec_decode_ctl.scala 498:24] + skip @[dec_decode_ctl.scala 494:40] + else : @[dec_decode_ctl.scala 501:15] + io.lsu_p.valid <= lsu_decode_d @[dec_decode_ctl.scala 502:35] + io.lsu_p.bits.load <= i0_dp.load @[dec_decode_ctl.scala 503:40] + io.lsu_p.bits.store <= i0_dp.store @[dec_decode_ctl.scala 504:40] + io.lsu_p.bits.by <= i0_dp.by @[dec_decode_ctl.scala 505:40] + io.lsu_p.bits.half <= i0_dp.half @[dec_decode_ctl.scala 506:40] + io.lsu_p.bits.word <= i0_dp.word @[dec_decode_ctl.scala 507:40] + node _T_425 = eq(i0r.rs1, UInt<5>("h02")) @[dec_decode_ctl.scala 508:41] + io.lsu_p.bits.stack <= _T_425 @[dec_decode_ctl.scala 508:29] + io.lsu_p.bits.load_ldst_bypass_d <= load_ldst_bypass_d @[dec_decode_ctl.scala 509:40] + io.lsu_p.bits.store_data_bypass_d <= store_data_bypass_d @[dec_decode_ctl.scala 510:40] + io.lsu_p.bits.store_data_bypass_m <= store_data_bypass_m @[dec_decode_ctl.scala 511:40] + io.lsu_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 512:40] + skip @[dec_decode_ctl.scala 501:15] + node _T_426 = and(i0_dp.csr_read, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 516:47] + io.dec_alu.dec_csr_ren_d <= _T_426 @[dec_decode_ctl.scala 516:29] + node _T_427 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 517:56] + node _T_428 = and(i0_dp.csr_read, _T_427) @[dec_decode_ctl.scala 517:36] + csr_read <= _T_428 @[dec_decode_ctl.scala 517:18] + node _T_429 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[dec_decode_ctl.scala 519:42] + node i0_csr_write = and(i0_dp.csr_write, _T_429) @[dec_decode_ctl.scala 519:40] + node _T_430 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 520:61] + node csr_clr_d = and(i0_dp.csr_clr, _T_430) @[dec_decode_ctl.scala 520:41] + node _T_431 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 521:59] + node csr_set_d = and(i0_dp.csr_set, _T_431) @[dec_decode_ctl.scala 521:39] + node _T_432 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 522:59] + node csr_write_d = and(i0_csr_write, _T_432) @[dec_decode_ctl.scala 522:39] + node _T_433 = eq(i0_dp.csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 524:41] + node _T_434 = and(i0_csr_write, _T_433) @[dec_decode_ctl.scala 524:39] + i0_csr_write_only_d <= _T_434 @[dec_decode_ctl.scala 524:23] + node _T_435 = or(i0_dp.csr_clr, i0_dp.csr_set) @[dec_decode_ctl.scala 525:42] + node _T_436 = or(_T_435, i0_csr_write) @[dec_decode_ctl.scala 525:58] + node _T_437 = and(_T_436, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 525:74] + io.dec_csr_wen_unq_d <= _T_437 @[dec_decode_ctl.scala 525:24] + node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[dec_decode_ctl.scala 527:34] + node _T_438 = and(any_csr_d, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 528:37] + io.dec_csr_any_unq_d <= _T_438 @[dec_decode_ctl.scala 528:24] + node _T_439 = bits(io.dec_csr_any_unq_d, 0, 0) @[Bitwise.scala 72:15] + node _T_440 = mux(_T_439, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] + node _T_441 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 529:62] + node _T_442 = and(_T_440, _T_441) @[dec_decode_ctl.scala 529:58] + io.dec_csr_rdaddr_d <= _T_442 @[dec_decode_ctl.scala 529:24] + node _T_443 = and(r_d.bits.csrwen, r_d.valid) @[dec_decode_ctl.scala 530:53] + node _T_444 = bits(_T_443, 0, 0) @[Bitwise.scala 72:15] + node _T_445 = mux(_T_444, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] + node _T_446 = and(_T_445, r_d.bits.csrwaddr) @[dec_decode_ctl.scala 530:67] + io.dec_csr_wraddr_r <= _T_446 @[dec_decode_ctl.scala 530:24] + node _T_447 = and(r_d.bits.csrwen, r_d.valid) @[dec_decode_ctl.scala 534:39] + node _T_448 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 534:53] + node _T_449 = and(_T_447, _T_448) @[dec_decode_ctl.scala 534:51] + io.dec_csr_wen_r <= _T_449 @[dec_decode_ctl.scala 534:20] + node _T_450 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[dec_decode_ctl.scala 537:50] + node _T_451 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[dec_decode_ctl.scala 537:85] + node _T_452 = or(_T_450, _T_451) @[dec_decode_ctl.scala 537:64] + node _T_453 = and(_T_452, r_d.bits.csrwen) @[dec_decode_ctl.scala 537:100] + node _T_454 = and(_T_453, r_d.valid) @[dec_decode_ctl.scala 537:118] + node _T_455 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 537:132] + node _T_456 = and(_T_454, _T_455) @[dec_decode_ctl.scala 537:130] + io.dec_csr_stall_int_ff <= _T_456 @[dec_decode_ctl.scala 537:27] + reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 539:52] + csr_read_x <= csr_read @[dec_decode_ctl.scala 539:52] + reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 540:51] + csr_clr_x <= csr_clr_d @[dec_decode_ctl.scala 540:51] + reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 541:51] + csr_set_x <= csr_set_d @[dec_decode_ctl.scala 541:51] + reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 542:53] + csr_write_x <= csr_write_d @[dec_decode_ctl.scala 542:53] + reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 543:51] + csr_imm_x <= i0_dp.csr_imm @[dec_decode_ctl.scala 543:51] + node _T_457 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 546:27] + node _T_458 = bits(any_csr_d, 0, 0) @[dec_decode_ctl.scala 546:60] + node _T_459 = and(i0_x_data_en, _T_458) @[dec_decode_ctl.scala 546:48] + node _T_460 = bits(_T_459, 0, 0) @[lib.scala 8:44] + inst rvclkhdr of rvclkhdr @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= _T_460 @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg csrimm_x : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_460 : @[Reg.scala 28:19] + csrimm_x <= _T_457 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_461 = bits(any_csr_d, 0, 0) @[dec_decode_ctl.scala 547:74] + node _T_462 = and(i0_x_data_en, _T_461) @[dec_decode_ctl.scala 547:62] + node _T_463 = bits(_T_462, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_463 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg csr_rddata_x : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_463 : @[Reg.scala 28:19] + csr_rddata_x <= io.dec_csr_rddata_d @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_464 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 550:15] + wire _T_465 : UInt<1>[27] @[lib.scala 12:48] + _T_465[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[9] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[10] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[11] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[12] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[13] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[14] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[15] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[16] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[17] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[18] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[19] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[20] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[21] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[22] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[23] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[24] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[25] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[26] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_466 = cat(_T_465[0], _T_465[1]) @[Cat.scala 29:58] + node _T_467 = cat(_T_466, _T_465[2]) @[Cat.scala 29:58] + node _T_468 = cat(_T_467, _T_465[3]) @[Cat.scala 29:58] + node _T_469 = cat(_T_468, _T_465[4]) @[Cat.scala 29:58] + node _T_470 = cat(_T_469, _T_465[5]) @[Cat.scala 29:58] + node _T_471 = cat(_T_470, _T_465[6]) @[Cat.scala 29:58] + node _T_472 = cat(_T_471, _T_465[7]) @[Cat.scala 29:58] + node _T_473 = cat(_T_472, _T_465[8]) @[Cat.scala 29:58] + node _T_474 = cat(_T_473, _T_465[9]) @[Cat.scala 29:58] + node _T_475 = cat(_T_474, _T_465[10]) @[Cat.scala 29:58] + node _T_476 = cat(_T_475, _T_465[11]) @[Cat.scala 29:58] + node _T_477 = cat(_T_476, _T_465[12]) @[Cat.scala 29:58] + node _T_478 = cat(_T_477, _T_465[13]) @[Cat.scala 29:58] + node _T_479 = cat(_T_478, _T_465[14]) @[Cat.scala 29:58] + node _T_480 = cat(_T_479, _T_465[15]) @[Cat.scala 29:58] + node _T_481 = cat(_T_480, _T_465[16]) @[Cat.scala 29:58] + node _T_482 = cat(_T_481, _T_465[17]) @[Cat.scala 29:58] + node _T_483 = cat(_T_482, _T_465[18]) @[Cat.scala 29:58] + node _T_484 = cat(_T_483, _T_465[19]) @[Cat.scala 29:58] + node _T_485 = cat(_T_484, _T_465[20]) @[Cat.scala 29:58] + node _T_486 = cat(_T_485, _T_465[21]) @[Cat.scala 29:58] + node _T_487 = cat(_T_486, _T_465[22]) @[Cat.scala 29:58] + node _T_488 = cat(_T_487, _T_465[23]) @[Cat.scala 29:58] + node _T_489 = cat(_T_488, _T_465[24]) @[Cat.scala 29:58] + node _T_490 = cat(_T_489, _T_465[25]) @[Cat.scala 29:58] + node _T_491 = cat(_T_490, _T_465[26]) @[Cat.scala 29:58] + node _T_492 = bits(csrimm_x, 4, 0) @[dec_decode_ctl.scala 550:53] + node _T_493 = cat(_T_491, _T_492) @[Cat.scala 29:58] + node _T_494 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 551:16] + node _T_495 = eq(_T_494, UInt<1>("h00")) @[dec_decode_ctl.scala 551:5] + node _T_496 = mux(_T_464, _T_493, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_497 = mux(_T_495, io.decode_exu.exu_csr_rs1_x, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_498 = or(_T_496, _T_497) @[Mux.scala 27:72] + wire csr_mask_x : UInt<32> @[Mux.scala 27:72] + csr_mask_x <= _T_498 @[Mux.scala 27:72] + node _T_499 = not(csr_mask_x) @[dec_decode_ctl.scala 554:38] + node _T_500 = and(csr_rddata_x, _T_499) @[dec_decode_ctl.scala 554:35] + node _T_501 = or(csr_rddata_x, csr_mask_x) @[dec_decode_ctl.scala 555:35] + node _T_502 = mux(csr_clr_x, _T_500, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_503 = mux(csr_set_x, _T_501, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_504 = mux(csr_write_x, csr_mask_x, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_505 = or(_T_502, _T_503) @[Mux.scala 27:72] + node _T_506 = or(_T_505, _T_504) @[Mux.scala 27:72] + wire write_csr_data_x : UInt @[Mux.scala 27:72] + write_csr_data_x <= _T_506 @[Mux.scala 27:72] + node _T_507 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[dec_decode_ctl.scala 558:49] + node _T_508 = and(io.dec_tlu_flush_lower_r, _T_507) @[dec_decode_ctl.scala 558:47] + node _T_509 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] + node _T_510 = bits(write_csr_data, 0, 0) @[dec_decode_ctl.scala 558:145] + node _T_511 = cat(_T_509, _T_510) @[Cat.scala 29:58] + node _T_512 = eq(write_csr_data, _T_511) @[dec_decode_ctl.scala 558:109] + node _T_513 = and(pause_stall, _T_512) @[dec_decode_ctl.scala 558:91] + node clear_pause = or(_T_508, _T_513) @[dec_decode_ctl.scala 558:76] + node _T_514 = or(io.dec_tlu_wr_pause_r, pause_stall) @[dec_decode_ctl.scala 559:44] + node _T_515 = eq(clear_pause, UInt<1>("h00")) @[dec_decode_ctl.scala 559:61] + node _T_516 = and(_T_514, _T_515) @[dec_decode_ctl.scala 559:59] + pause_state_in <= _T_516 @[dec_decode_ctl.scala 559:18] + io.dec_pause_state <= pause_stall @[dec_decode_ctl.scala 560:22] + node _T_517 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[dec_decode_ctl.scala 562:44] + node _T_518 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[dec_decode_ctl.scala 562:64] + node _T_519 = and(_T_517, _T_518) @[dec_decode_ctl.scala 562:61] + node _T_520 = and(pause_stall, _T_519) @[dec_decode_ctl.scala 562:41] + io.dec_pause_state_cg <= _T_520 @[dec_decode_ctl.scala 562:25] + node _T_521 = sub(write_csr_data, UInt<32>("h01")) @[dec_decode_ctl.scala 565:59] + node _T_522 = tail(_T_521, 1) @[dec_decode_ctl.scala 565:59] + node _T_523 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[dec_decode_ctl.scala 566:8] + node write_csr_data_in = mux(pause_stall, _T_522, _T_523) @[dec_decode_ctl.scala 565:30] + node _T_524 = or(csr_clr_x, csr_set_x) @[dec_decode_ctl.scala 567:34] + node _T_525 = or(_T_524, csr_write_x) @[dec_decode_ctl.scala 567:46] + node _T_526 = and(_T_525, csr_read_x) @[dec_decode_ctl.scala 567:61] + node _T_527 = or(_T_526, io.dec_tlu_wr_pause_r) @[dec_decode_ctl.scala 567:75] + node csr_data_wen = or(_T_527, pause_stall) @[dec_decode_ctl.scala 567:99] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_2.io.en <= csr_data_wen @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_528 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when csr_data_wen : @[Reg.scala 28:19] + _T_528 <= write_csr_data_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + write_csr_data <= _T_528 @[dec_decode_ctl.scala 568:18] + node _T_529 = and(r_d.bits.csrwonly, r_d.valid) @[dec_decode_ctl.scala 574:50] + node _T_530 = bits(_T_529, 0, 0) @[dec_decode_ctl.scala 574:63] + node _T_531 = mux(_T_530, i0_result_corr_r, write_csr_data) @[dec_decode_ctl.scala 574:30] + io.dec_csr_wrdata_r <= _T_531 @[dec_decode_ctl.scala 574:24] + node _T_532 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[dec_decode_ctl.scala 576:43] + node prior_csr_write = or(_T_532, wbd.bits.csrwonly) @[dec_decode_ctl.scala 576:63] + node _T_533 = bits(io.dbg_dctl.dbg_cmd_wrdata, 0, 0) @[dec_decode_ctl.scala 578:76] + node debug_fence_i = and(io.dec_debug_fence_d, _T_533) @[dec_decode_ctl.scala 578:48] + node _T_534 = bits(io.dbg_dctl.dbg_cmd_wrdata, 1, 1) @[dec_decode_ctl.scala 579:76] + node debug_fence_raw = and(io.dec_debug_fence_d, _T_534) @[dec_decode_ctl.scala 579:48] + node _T_535 = or(debug_fence_raw, debug_fence_i) @[dec_decode_ctl.scala 580:40] + debug_fence <= _T_535 @[dec_decode_ctl.scala 580:21] + node _T_536 = or(i0_dp.presync, io.dec_tlu_presync_d) @[dec_decode_ctl.scala 583:34] + node _T_537 = or(_T_536, debug_fence_i) @[dec_decode_ctl.scala 583:57] + node _T_538 = or(_T_537, debug_fence_raw) @[dec_decode_ctl.scala 583:73] + node i0_presync = or(_T_538, io.dec_tlu_pipelining_disable) @[dec_decode_ctl.scala 583:91] + node _T_539 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[dec_decode_ctl.scala 586:36] + node _T_540 = or(_T_539, debug_fence_i) @[dec_decode_ctl.scala 586:60] + node _T_541 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 586:104] + node _T_542 = eq(_T_541, UInt<11>("h07c2")) @[dec_decode_ctl.scala 586:112] + node _T_543 = and(i0_csr_write_only_d, _T_542) @[dec_decode_ctl.scala 586:99] + node i0_postsync = or(_T_540, _T_543) @[dec_decode_ctl.scala 586:76] + node _T_544 = eq(any_csr_d, UInt<1>("h00")) @[dec_decode_ctl.scala 590:40] + node _T_545 = or(_T_544, io.dec_csr_legal_d) @[dec_decode_ctl.scala 590:51] + node i0_legal = and(i0_dp.legal, _T_545) @[dec_decode_ctl.scala 590:37] + wire _T_546 : UInt<1>[16] @[lib.scala 12:48] + _T_546[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[9] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[10] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[11] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[12] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[13] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[14] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[15] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_547 = cat(_T_546[0], _T_546[1]) @[Cat.scala 29:58] + node _T_548 = cat(_T_547, _T_546[2]) @[Cat.scala 29:58] + node _T_549 = cat(_T_548, _T_546[3]) @[Cat.scala 29:58] + node _T_550 = cat(_T_549, _T_546[4]) @[Cat.scala 29:58] + node _T_551 = cat(_T_550, _T_546[5]) @[Cat.scala 29:58] + node _T_552 = cat(_T_551, _T_546[6]) @[Cat.scala 29:58] + node _T_553 = cat(_T_552, _T_546[7]) @[Cat.scala 29:58] + node _T_554 = cat(_T_553, _T_546[8]) @[Cat.scala 29:58] + node _T_555 = cat(_T_554, _T_546[9]) @[Cat.scala 29:58] + node _T_556 = cat(_T_555, _T_546[10]) @[Cat.scala 29:58] + node _T_557 = cat(_T_556, _T_546[11]) @[Cat.scala 29:58] + node _T_558 = cat(_T_557, _T_546[12]) @[Cat.scala 29:58] + node _T_559 = cat(_T_558, _T_546[13]) @[Cat.scala 29:58] + node _T_560 = cat(_T_559, _T_546[14]) @[Cat.scala 29:58] + node _T_561 = cat(_T_560, _T_546[15]) @[Cat.scala 29:58] + node _T_562 = cat(_T_561, io.dec_aln.ifu_i0_cinst) @[Cat.scala 29:58] + node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_562) @[dec_decode_ctl.scala 591:27] + node _T_563 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 594:57] + node shift_illegal = and(io.dec_aln.dec_i0_decode_d, _T_563) @[dec_decode_ctl.scala 594:55] + node _T_564 = eq(illegal_lockout, UInt<1>("h00")) @[dec_decode_ctl.scala 595:44] + node illegal_inst_en = and(shift_illegal, _T_564) @[dec_decode_ctl.scala 595:42] + inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= illegal_inst_en @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_565 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when illegal_inst_en : @[Reg.scala 28:19] + _T_565 <= i0_inst_d @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.dec_illegal_inst <= _T_565 @[dec_decode_ctl.scala 596:23] + node _T_566 = or(shift_illegal, illegal_lockout) @[dec_decode_ctl.scala 597:40] + node _T_567 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 597:61] + node _T_568 = and(_T_566, _T_567) @[dec_decode_ctl.scala 597:59] + illegal_lockout_in <= _T_568 @[dec_decode_ctl.scala 597:22] + node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[dec_decode_ctl.scala 598:42] + node _T_569 = and(i0_dp.csr_read, prior_csr_write) @[dec_decode_ctl.scala 600:40] + node _T_570 = or(_T_569, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 600:59] + node _T_571 = or(_T_570, pause_stall) @[dec_decode_ctl.scala 600:92] + node _T_572 = or(_T_571, leak1_i0_stall) @[dec_decode_ctl.scala 600:106] + node _T_573 = or(_T_572, io.dec_tlu_debug_stall) @[dec_decode_ctl.scala 601:20] + node _T_574 = or(_T_573, postsync_stall) @[dec_decode_ctl.scala 601:45] + node _T_575 = or(_T_574, presync_stall) @[dec_decode_ctl.scala 601:62] + node _T_576 = or(i0_dp.fence, debug_fence) @[dec_decode_ctl.scala 602:19] + node _T_577 = eq(lsu_idle, UInt<1>("h00")) @[dec_decode_ctl.scala 602:36] + node _T_578 = and(_T_576, _T_577) @[dec_decode_ctl.scala 602:34] + node _T_579 = or(_T_575, _T_578) @[dec_decode_ctl.scala 601:79] + node _T_580 = or(_T_579, i0_nonblock_load_stall) @[dec_decode_ctl.scala 602:47] + node _T_581 = or(_T_580, i0_load_block_d) @[dec_decode_ctl.scala 602:72] + node _T_582 = or(_T_581, i0_nonblock_div_stall) @[dec_decode_ctl.scala 603:21] + node i0_block_raw_d = or(_T_582, i0_div_prior_div_stall) @[dec_decode_ctl.scala 603:45] + node _T_583 = or(io.lsu_store_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 605:65] + node i0_store_stall_d = and(i0_dp.store, _T_583) @[dec_decode_ctl.scala 605:39] + node _T_584 = or(io.lsu_load_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 606:63] + node i0_load_stall_d = and(i0_dp.load, _T_584) @[dec_decode_ctl.scala 606:38] + node _T_585 = or(i0_block_raw_d, i0_store_stall_d) @[dec_decode_ctl.scala 607:38] + node i0_block_d = or(_T_585, i0_load_stall_d) @[dec_decode_ctl.scala 607:57] + node _T_586 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 611:54] + node _T_587 = and(io.dec_ib0_valid_d, _T_586) @[dec_decode_ctl.scala 611:52] + node _T_588 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 611:71] + node _T_589 = and(_T_587, _T_588) @[dec_decode_ctl.scala 611:69] + node _T_590 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 611:99] + node _T_591 = and(_T_589, _T_590) @[dec_decode_ctl.scala 611:97] + io.dec_aln.dec_i0_decode_d <= _T_591 @[dec_decode_ctl.scala 611:30] + node _T_592 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 612:46] + node _T_593 = and(io.dec_ib0_valid_d, _T_592) @[dec_decode_ctl.scala 612:44] + node _T_594 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 612:63] + node _T_595 = and(_T_593, _T_594) @[dec_decode_ctl.scala 612:61] + node _T_596 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 612:91] + node i0_exudecode_d = and(_T_595, _T_596) @[dec_decode_ctl.scala 612:89] + node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[dec_decode_ctl.scala 613:46] + io.dec_pmu_instr_decoded <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 616:28] + node _T_597 = eq(io.dec_aln.dec_i0_decode_d, UInt<1>("h00")) @[dec_decode_ctl.scala 617:51] + node _T_598 = and(io.dec_ib0_valid_d, _T_597) @[dec_decode_ctl.scala 617:49] + io.dec_pmu_decode_stall <= _T_598 @[dec_decode_ctl.scala 617:27] + node _T_599 = bits(postsync_stall, 0, 0) @[dec_decode_ctl.scala 618:47] + node _T_600 = and(_T_599, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 618:54] + io.dec_pmu_postsync_stall <= _T_600 @[dec_decode_ctl.scala 618:29] + node _T_601 = bits(presync_stall, 0, 0) @[dec_decode_ctl.scala 619:46] + node _T_602 = and(_T_601, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 619:53] + io.dec_pmu_presync_stall <= _T_602 @[dec_decode_ctl.scala 619:29] + node prior_inflight = or(x_d.valid, r_d.valid) @[dec_decode_ctl.scala 623:41] + node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[dec_decode_ctl.scala 624:31] + node _T_603 = and(i0_presync, prior_inflight_eff) @[dec_decode_ctl.scala 626:37] + presync_stall <= _T_603 @[dec_decode_ctl.scala 626:22] + node _T_604 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 628:64] + node _T_605 = or(i0_postsync, _T_604) @[dec_decode_ctl.scala 628:62] + node _T_606 = and(io.dec_aln.dec_i0_decode_d, _T_605) @[dec_decode_ctl.scala 628:47] + node _T_607 = and(postsync_stall, x_d.valid) @[dec_decode_ctl.scala 628:96] + node _T_608 = or(_T_606, _T_607) @[dec_decode_ctl.scala 628:77] + ps_stall_in <= _T_608 @[dec_decode_ctl.scala 628:15] + node _T_609 = and(i0_exulegal_decode_d, i0_dp.alu) @[dec_decode_ctl.scala 630:58] + io.dec_alu.dec_i0_alu_decode_d <= _T_609 @[dec_decode_ctl.scala 630:34] + node _T_610 = or(i0_dp.condbr, i0_dp.jal) @[dec_decode_ctl.scala 631:53] + node _T_611 = or(_T_610, i0_br_error_all) @[dec_decode_ctl.scala 631:65] + io.decode_exu.dec_i0_branch_d <= _T_611 @[dec_decode_ctl.scala 631:37] + node _T_612 = and(i0_legal_decode_d, i0_dp.lsu) @[dec_decode_ctl.scala 633:40] + lsu_decode_d <= _T_612 @[dec_decode_ctl.scala 633:16] + node _T_613 = and(i0_exulegal_decode_d, i0_dp.mul) @[dec_decode_ctl.scala 634:40] + mul_decode_d <= _T_613 @[dec_decode_ctl.scala 634:16] + node _T_614 = and(i0_exulegal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 635:40] + div_decode_d <= _T_614 @[dec_decode_ctl.scala 635:16] + io.decode_exu.dec_qual_lsu_d <= i0_dp.lsu @[dec_decode_ctl.scala 636:32] + node _T_615 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 637:45] + node _T_616 = and(r_d.valid, _T_615) @[dec_decode_ctl.scala 637:43] + io.dec_tlu_i0_valid_r <= _T_616 @[dec_decode_ctl.scala 637:29] + d_t.legal <= i0_legal_decode_d @[dec_decode_ctl.scala 640:26] + node _T_617 = and(i0_icaf_d, i0_legal_decode_d) @[dec_decode_ctl.scala 641:40] + d_t.icaf <= _T_617 @[dec_decode_ctl.scala 641:26] + node _T_618 = and(io.dec_i0_icaf_second_d, i0_legal_decode_d) @[dec_decode_ctl.scala 642:58] + d_t.icaf_second <= _T_618 @[dec_decode_ctl.scala 642:30] + d_t.icaf_type <= io.dec_i0_icaf_type_d @[dec_decode_ctl.scala 643:26] + node _T_619 = or(i0_dp.fence_i, debug_fence_i) @[dec_decode_ctl.scala 645:44] + node _T_620 = and(_T_619, i0_legal_decode_d) @[dec_decode_ctl.scala 645:61] + d_t.fence_i <= _T_620 @[dec_decode_ctl.scala 645:26] + d_t.pmu_i0_br_unpred <= i0_br_unpred @[dec_decode_ctl.scala 648:26] + d_t.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 649:26] + d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 650:26] + wire _T_621 : UInt<1>[4] @[lib.scala 12:48] + _T_621[0] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48] + _T_621[1] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48] + _T_621[2] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48] + _T_621[3] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48] + node _T_622 = cat(_T_621[0], _T_621[1]) @[Cat.scala 29:58] + node _T_623 = cat(_T_622, _T_621[2]) @[Cat.scala 29:58] + node _T_624 = cat(_T_623, _T_621[3]) @[Cat.scala 29:58] + node _T_625 = and(io.dec_i0_trigger_match_d, _T_624) @[dec_decode_ctl.scala 652:56] + d_t.i0trigger <= _T_625 @[dec_decode_ctl.scala 652:26] + node _T_626 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 655:60] + wire _T_627 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[lib.scala 630:37] + _T_627.pmu_lsu_misaligned <= UInt<1>("h00") @[lib.scala 630:37] + _T_627.pmu_divide <= UInt<1>("h00") @[lib.scala 630:37] + _T_627.pmu_i0_br_unpred <= UInt<1>("h00") @[lib.scala 630:37] + _T_627.pmu_i0_itype <= UInt<4>("h00") @[lib.scala 630:37] + _T_627.i0trigger <= UInt<4>("h00") @[lib.scala 630:37] + _T_627.fence_i <= UInt<1>("h00") @[lib.scala 630:37] + _T_627.icaf_type <= UInt<2>("h00") @[lib.scala 630:37] + _T_627.icaf_second <= UInt<1>("h00") @[lib.scala 630:37] + _T_627.icaf <= UInt<1>("h00") @[lib.scala 630:37] + _T_627.legal <= UInt<1>("h00") @[lib.scala 630:37] + reg _T_628 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, clock with : (reset => (reset, _T_627)) @[Reg.scala 27:20] + when _T_626 : @[Reg.scala 28:19] + _T_628.pmu_lsu_misaligned <= d_t.pmu_lsu_misaligned @[Reg.scala 28:23] + _T_628.pmu_divide <= d_t.pmu_divide @[Reg.scala 28:23] + _T_628.pmu_i0_br_unpred <= d_t.pmu_i0_br_unpred @[Reg.scala 28:23] + _T_628.pmu_i0_itype <= d_t.pmu_i0_itype @[Reg.scala 28:23] + _T_628.i0trigger <= d_t.i0trigger @[Reg.scala 28:23] + _T_628.fence_i <= d_t.fence_i @[Reg.scala 28:23] + _T_628.icaf_type <= d_t.icaf_type @[Reg.scala 28:23] + _T_628.icaf_second <= d_t.icaf_second @[Reg.scala 28:23] + _T_628.icaf <= d_t.icaf @[Reg.scala 28:23] + _T_628.legal <= d_t.legal @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + x_t.pmu_lsu_misaligned <= _T_628.pmu_lsu_misaligned @[dec_decode_ctl.scala 655:7] + x_t.pmu_divide <= _T_628.pmu_divide @[dec_decode_ctl.scala 655:7] + x_t.pmu_i0_br_unpred <= _T_628.pmu_i0_br_unpred @[dec_decode_ctl.scala 655:7] + x_t.pmu_i0_itype <= _T_628.pmu_i0_itype @[dec_decode_ctl.scala 655:7] + x_t.i0trigger <= _T_628.i0trigger @[dec_decode_ctl.scala 655:7] + x_t.fence_i <= _T_628.fence_i @[dec_decode_ctl.scala 655:7] + x_t.icaf_type <= _T_628.icaf_type @[dec_decode_ctl.scala 655:7] + x_t.icaf_second <= _T_628.icaf_second @[dec_decode_ctl.scala 655:7] + x_t.icaf <= _T_628.icaf @[dec_decode_ctl.scala 655:7] + x_t.legal <= _T_628.legal @[dec_decode_ctl.scala 655:7] + x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 657:10] + x_t_in.pmu_divide <= x_t.pmu_divide @[dec_decode_ctl.scala 657:10] + x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 657:10] + x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[dec_decode_ctl.scala 657:10] + x_t_in.i0trigger <= x_t.i0trigger @[dec_decode_ctl.scala 657:10] + x_t_in.fence_i <= x_t.fence_i @[dec_decode_ctl.scala 657:10] + x_t_in.icaf_type <= x_t.icaf_type @[dec_decode_ctl.scala 657:10] + x_t_in.icaf_second <= x_t.icaf_second @[dec_decode_ctl.scala 657:10] + x_t_in.icaf <= x_t.icaf @[dec_decode_ctl.scala 657:10] + x_t_in.legal <= x_t.legal @[dec_decode_ctl.scala 657:10] + wire _T_629 : UInt<1>[4] @[lib.scala 12:48] + _T_629[0] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] + _T_629[1] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] + _T_629[2] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] + _T_629[3] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] + node _T_630 = cat(_T_629[0], _T_629[1]) @[Cat.scala 29:58] + node _T_631 = cat(_T_630, _T_629[2]) @[Cat.scala 29:58] + node _T_632 = cat(_T_631, _T_629[3]) @[Cat.scala 29:58] + node _T_633 = not(_T_632) @[dec_decode_ctl.scala 658:39] + node _T_634 = and(x_t.i0trigger, _T_633) @[dec_decode_ctl.scala 658:37] + x_t_in.i0trigger <= _T_634 @[dec_decode_ctl.scala 658:20] + node _T_635 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 660:63] + wire _T_636 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[lib.scala 630:37] + _T_636.pmu_lsu_misaligned <= UInt<1>("h00") @[lib.scala 630:37] + _T_636.pmu_divide <= UInt<1>("h00") @[lib.scala 630:37] + _T_636.pmu_i0_br_unpred <= UInt<1>("h00") @[lib.scala 630:37] + _T_636.pmu_i0_itype <= UInt<4>("h00") @[lib.scala 630:37] + _T_636.i0trigger <= UInt<4>("h00") @[lib.scala 630:37] + _T_636.fence_i <= UInt<1>("h00") @[lib.scala 630:37] + _T_636.icaf_type <= UInt<2>("h00") @[lib.scala 630:37] + _T_636.icaf_second <= UInt<1>("h00") @[lib.scala 630:37] + _T_636.icaf <= UInt<1>("h00") @[lib.scala 630:37] + _T_636.legal <= UInt<1>("h00") @[lib.scala 630:37] + reg _T_637 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, clock with : (reset => (reset, _T_636)) @[Reg.scala 27:20] + when _T_635 : @[Reg.scala 28:19] + _T_637.pmu_lsu_misaligned <= x_t_in.pmu_lsu_misaligned @[Reg.scala 28:23] + _T_637.pmu_divide <= x_t_in.pmu_divide @[Reg.scala 28:23] + _T_637.pmu_i0_br_unpred <= x_t_in.pmu_i0_br_unpred @[Reg.scala 28:23] + _T_637.pmu_i0_itype <= x_t_in.pmu_i0_itype @[Reg.scala 28:23] + _T_637.i0trigger <= x_t_in.i0trigger @[Reg.scala 28:23] + _T_637.fence_i <= x_t_in.fence_i @[Reg.scala 28:23] + _T_637.icaf_type <= x_t_in.icaf_type @[Reg.scala 28:23] + _T_637.icaf_second <= x_t_in.icaf_second @[Reg.scala 28:23] + _T_637.icaf <= x_t_in.icaf @[Reg.scala 28:23] + _T_637.legal <= x_t_in.legal @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + r_t.pmu_lsu_misaligned <= _T_637.pmu_lsu_misaligned @[dec_decode_ctl.scala 660:7] + r_t.pmu_divide <= _T_637.pmu_divide @[dec_decode_ctl.scala 660:7] + r_t.pmu_i0_br_unpred <= _T_637.pmu_i0_br_unpred @[dec_decode_ctl.scala 660:7] + r_t.pmu_i0_itype <= _T_637.pmu_i0_itype @[dec_decode_ctl.scala 660:7] + r_t.i0trigger <= _T_637.i0trigger @[dec_decode_ctl.scala 660:7] + r_t.fence_i <= _T_637.fence_i @[dec_decode_ctl.scala 660:7] + r_t.icaf_type <= _T_637.icaf_type @[dec_decode_ctl.scala 660:7] + r_t.icaf_second <= _T_637.icaf_second @[dec_decode_ctl.scala 660:7] + r_t.icaf <= _T_637.icaf @[dec_decode_ctl.scala 660:7] + r_t.legal <= _T_637.legal @[dec_decode_ctl.scala 660:7] + r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 662:10] + r_t_in.pmu_divide <= r_t.pmu_divide @[dec_decode_ctl.scala 662:10] + r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 662:10] + r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[dec_decode_ctl.scala 662:10] + r_t_in.i0trigger <= r_t.i0trigger @[dec_decode_ctl.scala 662:10] + r_t_in.fence_i <= r_t.fence_i @[dec_decode_ctl.scala 662:10] + r_t_in.icaf_type <= r_t.icaf_type @[dec_decode_ctl.scala 662:10] + r_t_in.icaf_second <= r_t.icaf_second @[dec_decode_ctl.scala 662:10] + r_t_in.icaf <= r_t.icaf @[dec_decode_ctl.scala 662:10] + r_t_in.legal <= r_t.legal @[dec_decode_ctl.scala 662:10] + node _T_638 = or(r_d.bits.i0load, r_d.bits.i0store) @[dec_decode_ctl.scala 664:61] + wire _T_639 : UInt<1>[4] @[lib.scala 12:48] + _T_639[0] <= _T_638 @[lib.scala 12:48] + _T_639[1] <= _T_638 @[lib.scala 12:48] + _T_639[2] <= _T_638 @[lib.scala 12:48] + _T_639[3] <= _T_638 @[lib.scala 12:48] + node _T_640 = cat(_T_639[0], _T_639[1]) @[Cat.scala 29:58] + node _T_641 = cat(_T_640, _T_639[2]) @[Cat.scala 29:58] + node _T_642 = cat(_T_641, _T_639[3]) @[Cat.scala 29:58] + node _T_643 = and(_T_642, lsu_trigger_match_r) @[dec_decode_ctl.scala 664:82] + node _T_644 = or(_T_643, r_t.i0trigger) @[dec_decode_ctl.scala 664:105] + r_t_in.i0trigger <= _T_644 @[dec_decode_ctl.scala 664:33] + r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[dec_decode_ctl.scala 665:33] + node _T_645 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[dec_decode_ctl.scala 667:35] + when _T_645 : @[dec_decode_ctl.scala 667:43] + wire _T_646 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 667:66] + _T_646.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + _T_646.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + _T_646.pmu_i0_br_unpred <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + _T_646.pmu_i0_itype <= UInt<4>("h00") @[dec_decode_ctl.scala 667:66] + _T_646.i0trigger <= UInt<4>("h00") @[dec_decode_ctl.scala 667:66] + _T_646.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + _T_646.icaf_type <= UInt<2>("h00") @[dec_decode_ctl.scala 667:66] + _T_646.icaf_second <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + _T_646.icaf <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + _T_646.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + r_t_in.pmu_lsu_misaligned <= _T_646.pmu_lsu_misaligned @[dec_decode_ctl.scala 667:51] + r_t_in.pmu_divide <= _T_646.pmu_divide @[dec_decode_ctl.scala 667:51] + r_t_in.pmu_i0_br_unpred <= _T_646.pmu_i0_br_unpred @[dec_decode_ctl.scala 667:51] + r_t_in.pmu_i0_itype <= _T_646.pmu_i0_itype @[dec_decode_ctl.scala 667:51] + r_t_in.i0trigger <= _T_646.i0trigger @[dec_decode_ctl.scala 667:51] + r_t_in.fence_i <= _T_646.fence_i @[dec_decode_ctl.scala 667:51] + r_t_in.icaf_type <= _T_646.icaf_type @[dec_decode_ctl.scala 667:51] + r_t_in.icaf_second <= _T_646.icaf_second @[dec_decode_ctl.scala 667:51] + r_t_in.icaf <= _T_646.icaf @[dec_decode_ctl.scala 667:51] + r_t_in.legal <= _T_646.legal @[dec_decode_ctl.scala 667:51] + skip @[dec_decode_ctl.scala 667:43] + io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.icaf_second <= r_t_in.icaf_second @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.legal <= r_t_in.legal @[dec_decode_ctl.scala 669:39] + node _T_647 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 670:58] + io.dec_tlu_packet_r.pmu_divide <= _T_647 @[dec_decode_ctl.scala 670:39] + node _T_648 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 674:54] + node _T_649 = and(io.dec_ib0_valid_d, _T_648) @[dec_decode_ctl.scala 674:52] + node _T_650 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 674:68] + node _T_651 = and(_T_649, _T_650) @[dec_decode_ctl.scala 674:66] + node _T_652 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 674:96] + node _T_653 = and(_T_651, _T_652) @[dec_decode_ctl.scala 674:94] + io.dec_aln.dec_i0_decode_d <= _T_653 @[dec_decode_ctl.scala 674:30] + node _T_654 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 676:16] + i0r.rs1 <= _T_654 @[dec_decode_ctl.scala 676:11] + node _T_655 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 677:16] + i0r.rs2 <= _T_655 @[dec_decode_ctl.scala 677:11] + node _T_656 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 678:16] + i0r.rd <= _T_656 @[dec_decode_ctl.scala 678:11] + node _T_657 = neq(i0r.rs1, UInt<5>("h00")) @[dec_decode_ctl.scala 680:60] + node _T_658 = and(i0_dp.rs1, _T_657) @[dec_decode_ctl.scala 680:49] + io.decode_exu.dec_i0_rs1_en_d <= _T_658 @[dec_decode_ctl.scala 680:35] + node _T_659 = neq(i0r.rs2, UInt<5>("h00")) @[dec_decode_ctl.scala 681:60] + node _T_660 = and(i0_dp.rs2, _T_659) @[dec_decode_ctl.scala 681:49] + io.decode_exu.dec_i0_rs2_en_d <= _T_660 @[dec_decode_ctl.scala 681:35] + node _T_661 = neq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 682:48] + node i0_rd_en_d = and(i0_dp.rd, _T_661) @[dec_decode_ctl.scala 682:37] + io.dec_i0_rs1_d <= i0r.rs1 @[dec_decode_ctl.scala 683:19] + io.dec_i0_rs2_d <= i0r.rs2 @[dec_decode_ctl.scala 684:19] + node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[dec_decode_ctl.scala 686:38] + node _T_662 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 687:27] + node i0_uiimm20 = and(_T_662, i0_dp.imm20) @[dec_decode_ctl.scala 687:38] + node _T_663 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 694:38] + wire _T_664 : UInt<1>[20] @[lib.scala 12:48] + _T_664[0] <= _T_663 @[lib.scala 12:48] + _T_664[1] <= _T_663 @[lib.scala 12:48] + _T_664[2] <= _T_663 @[lib.scala 12:48] + _T_664[3] <= _T_663 @[lib.scala 12:48] + _T_664[4] <= _T_663 @[lib.scala 12:48] + _T_664[5] <= _T_663 @[lib.scala 12:48] + _T_664[6] <= _T_663 @[lib.scala 12:48] + _T_664[7] <= _T_663 @[lib.scala 12:48] + _T_664[8] <= _T_663 @[lib.scala 12:48] + _T_664[9] <= _T_663 @[lib.scala 12:48] + _T_664[10] <= _T_663 @[lib.scala 12:48] + _T_664[11] <= _T_663 @[lib.scala 12:48] + _T_664[12] <= _T_663 @[lib.scala 12:48] + _T_664[13] <= _T_663 @[lib.scala 12:48] + _T_664[14] <= _T_663 @[lib.scala 12:48] + _T_664[15] <= _T_663 @[lib.scala 12:48] + _T_664[16] <= _T_663 @[lib.scala 12:48] + _T_664[17] <= _T_663 @[lib.scala 12:48] + _T_664[18] <= _T_663 @[lib.scala 12:48] + _T_664[19] <= _T_663 @[lib.scala 12:48] + node _T_665 = cat(_T_664[0], _T_664[1]) @[Cat.scala 29:58] + node _T_666 = cat(_T_665, _T_664[2]) @[Cat.scala 29:58] + node _T_667 = cat(_T_666, _T_664[3]) @[Cat.scala 29:58] + node _T_668 = cat(_T_667, _T_664[4]) @[Cat.scala 29:58] + node _T_669 = cat(_T_668, _T_664[5]) @[Cat.scala 29:58] + node _T_670 = cat(_T_669, _T_664[6]) @[Cat.scala 29:58] + node _T_671 = cat(_T_670, _T_664[7]) @[Cat.scala 29:58] + node _T_672 = cat(_T_671, _T_664[8]) @[Cat.scala 29:58] + node _T_673 = cat(_T_672, _T_664[9]) @[Cat.scala 29:58] + node _T_674 = cat(_T_673, _T_664[10]) @[Cat.scala 29:58] + node _T_675 = cat(_T_674, _T_664[11]) @[Cat.scala 29:58] + node _T_676 = cat(_T_675, _T_664[12]) @[Cat.scala 29:58] + node _T_677 = cat(_T_676, _T_664[13]) @[Cat.scala 29:58] + node _T_678 = cat(_T_677, _T_664[14]) @[Cat.scala 29:58] + node _T_679 = cat(_T_678, _T_664[15]) @[Cat.scala 29:58] + node _T_680 = cat(_T_679, _T_664[16]) @[Cat.scala 29:58] + node _T_681 = cat(_T_680, _T_664[17]) @[Cat.scala 29:58] + node _T_682 = cat(_T_681, _T_664[18]) @[Cat.scala 29:58] + node _T_683 = cat(_T_682, _T_664[19]) @[Cat.scala 29:58] + node _T_684 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 694:46] + node _T_685 = cat(_T_683, _T_684) @[Cat.scala 29:58] + wire _T_686 : UInt<1>[27] @[lib.scala 12:48] + _T_686[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[9] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[10] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[11] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[12] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[13] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[14] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[15] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[16] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[17] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[18] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[19] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[20] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[21] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[22] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[23] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[24] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[25] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[26] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_687 = cat(_T_686[0], _T_686[1]) @[Cat.scala 29:58] + node _T_688 = cat(_T_687, _T_686[2]) @[Cat.scala 29:58] + node _T_689 = cat(_T_688, _T_686[3]) @[Cat.scala 29:58] + node _T_690 = cat(_T_689, _T_686[4]) @[Cat.scala 29:58] + node _T_691 = cat(_T_690, _T_686[5]) @[Cat.scala 29:58] + node _T_692 = cat(_T_691, _T_686[6]) @[Cat.scala 29:58] + node _T_693 = cat(_T_692, _T_686[7]) @[Cat.scala 29:58] + node _T_694 = cat(_T_693, _T_686[8]) @[Cat.scala 29:58] + node _T_695 = cat(_T_694, _T_686[9]) @[Cat.scala 29:58] + node _T_696 = cat(_T_695, _T_686[10]) @[Cat.scala 29:58] + node _T_697 = cat(_T_696, _T_686[11]) @[Cat.scala 29:58] + node _T_698 = cat(_T_697, _T_686[12]) @[Cat.scala 29:58] + node _T_699 = cat(_T_698, _T_686[13]) @[Cat.scala 29:58] + node _T_700 = cat(_T_699, _T_686[14]) @[Cat.scala 29:58] + node _T_701 = cat(_T_700, _T_686[15]) @[Cat.scala 29:58] + node _T_702 = cat(_T_701, _T_686[16]) @[Cat.scala 29:58] + node _T_703 = cat(_T_702, _T_686[17]) @[Cat.scala 29:58] + node _T_704 = cat(_T_703, _T_686[18]) @[Cat.scala 29:58] + node _T_705 = cat(_T_704, _T_686[19]) @[Cat.scala 29:58] + node _T_706 = cat(_T_705, _T_686[20]) @[Cat.scala 29:58] + node _T_707 = cat(_T_706, _T_686[21]) @[Cat.scala 29:58] + node _T_708 = cat(_T_707, _T_686[22]) @[Cat.scala 29:58] + node _T_709 = cat(_T_708, _T_686[23]) @[Cat.scala 29:58] + node _T_710 = cat(_T_709, _T_686[24]) @[Cat.scala 29:58] + node _T_711 = cat(_T_710, _T_686[25]) @[Cat.scala 29:58] + node _T_712 = cat(_T_711, _T_686[26]) @[Cat.scala 29:58] + node _T_713 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 695:43] + node _T_714 = cat(_T_712, _T_713) @[Cat.scala 29:58] + node _T_715 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 696:38] + wire _T_716 : UInt<1>[12] @[lib.scala 12:48] + _T_716[0] <= _T_715 @[lib.scala 12:48] + _T_716[1] <= _T_715 @[lib.scala 12:48] + _T_716[2] <= _T_715 @[lib.scala 12:48] + _T_716[3] <= _T_715 @[lib.scala 12:48] + _T_716[4] <= _T_715 @[lib.scala 12:48] + _T_716[5] <= _T_715 @[lib.scala 12:48] + _T_716[6] <= _T_715 @[lib.scala 12:48] + _T_716[7] <= _T_715 @[lib.scala 12:48] + _T_716[8] <= _T_715 @[lib.scala 12:48] + _T_716[9] <= _T_715 @[lib.scala 12:48] + _T_716[10] <= _T_715 @[lib.scala 12:48] + _T_716[11] <= _T_715 @[lib.scala 12:48] + node _T_717 = cat(_T_716[0], _T_716[1]) @[Cat.scala 29:58] + node _T_718 = cat(_T_717, _T_716[2]) @[Cat.scala 29:58] + node _T_719 = cat(_T_718, _T_716[3]) @[Cat.scala 29:58] + node _T_720 = cat(_T_719, _T_716[4]) @[Cat.scala 29:58] + node _T_721 = cat(_T_720, _T_716[5]) @[Cat.scala 29:58] + node _T_722 = cat(_T_721, _T_716[6]) @[Cat.scala 29:58] + node _T_723 = cat(_T_722, _T_716[7]) @[Cat.scala 29:58] + node _T_724 = cat(_T_723, _T_716[8]) @[Cat.scala 29:58] + node _T_725 = cat(_T_724, _T_716[9]) @[Cat.scala 29:58] + node _T_726 = cat(_T_725, _T_716[10]) @[Cat.scala 29:58] + node _T_727 = cat(_T_726, _T_716[11]) @[Cat.scala 29:58] + node _T_728 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 696:46] + node _T_729 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 696:56] + node _T_730 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 696:63] + node _T_731 = cat(_T_730, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_732 = cat(_T_727, _T_728) @[Cat.scala 29:58] + node _T_733 = cat(_T_732, _T_729) @[Cat.scala 29:58] + node _T_734 = cat(_T_733, _T_731) @[Cat.scala 29:58] + node _T_735 = bits(io.dec_i0_instr_d, 31, 12) @[dec_decode_ctl.scala 697:30] + wire _T_736 : UInt<1>[12] @[lib.scala 12:48] + _T_736[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[9] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[10] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[11] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_737 = cat(_T_736[0], _T_736[1]) @[Cat.scala 29:58] + node _T_738 = cat(_T_737, _T_736[2]) @[Cat.scala 29:58] + node _T_739 = cat(_T_738, _T_736[3]) @[Cat.scala 29:58] + node _T_740 = cat(_T_739, _T_736[4]) @[Cat.scala 29:58] + node _T_741 = cat(_T_740, _T_736[5]) @[Cat.scala 29:58] + node _T_742 = cat(_T_741, _T_736[6]) @[Cat.scala 29:58] + node _T_743 = cat(_T_742, _T_736[7]) @[Cat.scala 29:58] + node _T_744 = cat(_T_743, _T_736[8]) @[Cat.scala 29:58] + node _T_745 = cat(_T_744, _T_736[9]) @[Cat.scala 29:58] + node _T_746 = cat(_T_745, _T_736[10]) @[Cat.scala 29:58] + node _T_747 = cat(_T_746, _T_736[11]) @[Cat.scala 29:58] + node _T_748 = cat(_T_735, _T_747) @[Cat.scala 29:58] + node _T_749 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[dec_decode_ctl.scala 698:26] + node _T_750 = bits(_T_749, 0, 0) @[dec_decode_ctl.scala 698:43] + wire _T_751 : UInt<1>[27] @[lib.scala 12:48] + _T_751[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[9] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[10] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[11] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[12] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[13] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[14] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[15] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[16] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[17] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[18] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[19] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[20] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[21] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[22] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[23] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[24] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[25] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[26] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_752 = cat(_T_751[0], _T_751[1]) @[Cat.scala 29:58] + node _T_753 = cat(_T_752, _T_751[2]) @[Cat.scala 29:58] + node _T_754 = cat(_T_753, _T_751[3]) @[Cat.scala 29:58] + node _T_755 = cat(_T_754, _T_751[4]) @[Cat.scala 29:58] + node _T_756 = cat(_T_755, _T_751[5]) @[Cat.scala 29:58] + node _T_757 = cat(_T_756, _T_751[6]) @[Cat.scala 29:58] + node _T_758 = cat(_T_757, _T_751[7]) @[Cat.scala 29:58] + node _T_759 = cat(_T_758, _T_751[8]) @[Cat.scala 29:58] + node _T_760 = cat(_T_759, _T_751[9]) @[Cat.scala 29:58] + node _T_761 = cat(_T_760, _T_751[10]) @[Cat.scala 29:58] + node _T_762 = cat(_T_761, _T_751[11]) @[Cat.scala 29:58] + node _T_763 = cat(_T_762, _T_751[12]) @[Cat.scala 29:58] + node _T_764 = cat(_T_763, _T_751[13]) @[Cat.scala 29:58] + node _T_765 = cat(_T_764, _T_751[14]) @[Cat.scala 29:58] + node _T_766 = cat(_T_765, _T_751[15]) @[Cat.scala 29:58] + node _T_767 = cat(_T_766, _T_751[16]) @[Cat.scala 29:58] + node _T_768 = cat(_T_767, _T_751[17]) @[Cat.scala 29:58] + node _T_769 = cat(_T_768, _T_751[18]) @[Cat.scala 29:58] + node _T_770 = cat(_T_769, _T_751[19]) @[Cat.scala 29:58] + node _T_771 = cat(_T_770, _T_751[20]) @[Cat.scala 29:58] + node _T_772 = cat(_T_771, _T_751[21]) @[Cat.scala 29:58] + node _T_773 = cat(_T_772, _T_751[22]) @[Cat.scala 29:58] + node _T_774 = cat(_T_773, _T_751[23]) @[Cat.scala 29:58] + node _T_775 = cat(_T_774, _T_751[24]) @[Cat.scala 29:58] + node _T_776 = cat(_T_775, _T_751[25]) @[Cat.scala 29:58] + node _T_777 = cat(_T_776, _T_751[26]) @[Cat.scala 29:58] + node _T_778 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 698:72] + node _T_779 = cat(_T_777, _T_778) @[Cat.scala 29:58] + node _T_780 = mux(i0_dp.imm12, _T_685, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_781 = mux(i0_dp.shimm5, _T_714, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_782 = mux(i0_jalimm20, _T_734, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_783 = mux(i0_uiimm20, _T_748, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_784 = mux(_T_750, _T_779, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_785 = or(_T_780, _T_781) @[Mux.scala 27:72] + node _T_786 = or(_T_785, _T_782) @[Mux.scala 27:72] + node _T_787 = or(_T_786, _T_783) @[Mux.scala 27:72] + node _T_788 = or(_T_787, _T_784) @[Mux.scala 27:72] + wire _T_789 : UInt<32> @[Mux.scala 27:72] + _T_789 <= _T_788 @[Mux.scala 27:72] + io.decode_exu.dec_i0_immed_d <= _T_789 @[dec_decode_ctl.scala 693:32] + wire bitmanip_zbb_legal : UInt<1> + bitmanip_zbb_legal <= UInt<1>("h00") + wire bitmanip_zbs_legal : UInt<1> + bitmanip_zbs_legal <= UInt<1>("h00") + wire bitmanip_zbe_legal : UInt<1> + bitmanip_zbe_legal <= UInt<1>("h00") + wire bitmanip_zbc_legal : UInt<1> + bitmanip_zbc_legal <= UInt<1>("h00") + wire bitmanip_zbp_legal : UInt<1> + bitmanip_zbp_legal <= UInt<1>("h00") + wire bitmanip_zbr_legal : UInt<1> + bitmanip_zbr_legal <= UInt<1>("h00") + wire bitmanip_zbf_legal : UInt<1> + bitmanip_zbf_legal <= UInt<1>("h00") + wire bitmanip_zba_legal : UInt<1> + bitmanip_zba_legal <= UInt<1>("h00") + wire bitmanip_zbb_zbp_legal : UInt<1> + bitmanip_zbb_zbp_legal <= UInt<1>("h00") + wire bitmanip_legal : UInt<1> + bitmanip_legal <= UInt<1>("h00") + bitmanip_zbb_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 711:29] + bitmanip_zbs_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 716:29] + node _T_790 = eq(i0_dp.zbe, UInt<1>("h00")) @[dec_decode_ctl.scala 723:32] + bitmanip_zbe_legal <= _T_790 @[dec_decode_ctl.scala 723:29] + node _T_791 = eq(i0_dp.zbc, UInt<1>("h00")) @[dec_decode_ctl.scala 728:32] + bitmanip_zbc_legal <= _T_791 @[dec_decode_ctl.scala 728:29] + node _T_792 = eq(i0_dp.zbb, UInt<1>("h00")) @[dec_decode_ctl.scala 733:46] + node _T_793 = and(i0_dp.zbp, _T_792) @[dec_decode_ctl.scala 733:44] + node _T_794 = eq(_T_793, UInt<1>("h00")) @[dec_decode_ctl.scala 733:32] + bitmanip_zbp_legal <= _T_794 @[dec_decode_ctl.scala 733:29] + node _T_795 = eq(i0_dp.zbr, UInt<1>("h00")) @[dec_decode_ctl.scala 738:32] + bitmanip_zbr_legal <= _T_795 @[dec_decode_ctl.scala 738:29] + node _T_796 = eq(i0_dp.zbf, UInt<1>("h00")) @[dec_decode_ctl.scala 743:32] + bitmanip_zbf_legal <= _T_796 @[dec_decode_ctl.scala 743:29] + node _T_797 = eq(i0_dp.zba, UInt<1>("h00")) @[dec_decode_ctl.scala 748:32] + bitmanip_zba_legal <= _T_797 @[dec_decode_ctl.scala 748:29] + bitmanip_zbb_zbp_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 751:29] + node _T_798 = and(bitmanip_zbb_legal, bitmanip_zbs_legal) @[dec_decode_ctl.scala 755:41] + node _T_799 = and(_T_798, bitmanip_zbe_legal) @[dec_decode_ctl.scala 755:62] + node _T_800 = and(_T_799, bitmanip_zbc_legal) @[dec_decode_ctl.scala 755:83] + node _T_801 = and(_T_800, bitmanip_zbp_legal) @[dec_decode_ctl.scala 755:104] + node _T_802 = and(_T_801, bitmanip_zbr_legal) @[dec_decode_ctl.scala 755:125] + node _T_803 = and(_T_802, bitmanip_zbf_legal) @[dec_decode_ctl.scala 755:146] + node _T_804 = and(_T_803, bitmanip_zba_legal) @[dec_decode_ctl.scala 755:167] + node _T_805 = and(_T_804, bitmanip_zbb_zbp_legal) @[dec_decode_ctl.scala 755:188] + bitmanip_legal <= _T_805 @[dec_decode_ctl.scala 755:18] + node _T_806 = and(io.dec_aln.dec_i0_decode_d, i0_legal) @[dec_decode_ctl.scala 756:54] + i0_legal_decode_d <= _T_806 @[dec_decode_ctl.scala 756:24] + node _T_807 = and(i0_dp.mul, i0_legal_decode_d) @[dec_decode_ctl.scala 758:44] + i0_d_c.mul <= _T_807 @[dec_decode_ctl.scala 758:29] + node _T_808 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 759:44] + i0_d_c.load <= _T_808 @[dec_decode_ctl.scala 759:29] + node _T_809 = and(i0_dp.alu, i0_legal_decode_d) @[dec_decode_ctl.scala 760:44] + i0_d_c.alu <= _T_809 @[dec_decode_ctl.scala 760:29] + wire _T_810 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 762:70] + _T_810.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 762:70] + _T_810.load <= UInt<1>("h00") @[dec_decode_ctl.scala 762:70] + _T_810.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 762:70] + node _T_811 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 762:92] + reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_810)) @[Reg.scala 27:20] + when _T_811 : @[Reg.scala 28:19] + i0_x_c.alu <= i0_d_c.alu @[Reg.scala 28:23] + i0_x_c.load <= i0_d_c.load @[Reg.scala 28:23] + i0_x_c.mul <= i0_d_c.mul @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wire _T_812 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 763:70] + _T_812.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 763:70] + _T_812.load <= UInt<1>("h00") @[dec_decode_ctl.scala 763:70] + _T_812.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 763:70] + node _T_813 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 763:92] + reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_812)) @[Reg.scala 27:20] + when _T_813 : @[Reg.scala 28:19] + i0_r_c.alu <= i0_x_c.alu @[Reg.scala 28:23] + i0_r_c.load <= i0_x_c.load @[Reg.scala 28:23] + i0_r_c.mul <= i0_x_c.mul @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_814 = bits(i0_pipe_en, 3, 1) @[dec_decode_ctl.scala 764:91] + reg _T_815 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 764:80] + _T_815 <= _T_814 @[dec_decode_ctl.scala 764:80] + node _T_816 = cat(io.dec_aln.dec_i0_decode_d, _T_815) @[Cat.scala 29:58] + i0_pipe_en <= _T_816 @[dec_decode_ctl.scala 764:14] + node _T_817 = bits(i0_pipe_en, 3, 2) @[dec_decode_ctl.scala 766:43] + node _T_818 = orr(_T_817) @[dec_decode_ctl.scala 766:49] + node _T_819 = or(_T_818, io.clk_override) @[dec_decode_ctl.scala 766:53] + i0_x_ctl_en <= _T_819 @[dec_decode_ctl.scala 766:29] + node _T_820 = bits(i0_pipe_en, 2, 1) @[dec_decode_ctl.scala 767:43] + node _T_821 = orr(_T_820) @[dec_decode_ctl.scala 767:49] + node _T_822 = or(_T_821, io.clk_override) @[dec_decode_ctl.scala 767:53] + i0_r_ctl_en <= _T_822 @[dec_decode_ctl.scala 767:29] + node _T_823 = bits(i0_pipe_en, 1, 0) @[dec_decode_ctl.scala 768:43] + node _T_824 = orr(_T_823) @[dec_decode_ctl.scala 768:49] + node _T_825 = or(_T_824, io.clk_override) @[dec_decode_ctl.scala 768:53] + i0_wb_ctl_en <= _T_825 @[dec_decode_ctl.scala 768:29] + node _T_826 = bits(i0_pipe_en, 3, 3) @[dec_decode_ctl.scala 769:44] + node _T_827 = or(_T_826, io.clk_override) @[dec_decode_ctl.scala 769:50] + i0_x_data_en <= _T_827 @[dec_decode_ctl.scala 769:29] + node _T_828 = bits(i0_pipe_en, 2, 2) @[dec_decode_ctl.scala 770:44] + node _T_829 = or(_T_828, io.clk_override) @[dec_decode_ctl.scala 770:50] + i0_r_data_en <= _T_829 @[dec_decode_ctl.scala 770:29] + node _T_830 = bits(i0_pipe_en, 1, 1) @[dec_decode_ctl.scala 771:44] + node _T_831 = or(_T_830, io.clk_override) @[dec_decode_ctl.scala 771:50] + i0_wb_data_en <= _T_831 @[dec_decode_ctl.scala 771:29] + node _T_832 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58] + io.decode_exu.dec_data_en <= _T_832 @[dec_decode_ctl.scala 773:38] + node _T_833 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58] + io.decode_exu.dec_ctl_en <= _T_833 @[dec_decode_ctl.scala 774:38] + d_d.bits.i0rd <= i0r.rd @[dec_decode_ctl.scala 776:34] + node _T_834 = and(i0_rd_en_d, i0_legal_decode_d) @[dec_decode_ctl.scala 777:50] + d_d.bits.i0v <= _T_834 @[dec_decode_ctl.scala 777:34] + d_d.valid <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 778:27] + node _T_835 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 780:50] + d_d.bits.i0load <= _T_835 @[dec_decode_ctl.scala 780:34] + node _T_836 = and(i0_dp.store, i0_legal_decode_d) @[dec_decode_ctl.scala 781:50] + d_d.bits.i0store <= _T_836 @[dec_decode_ctl.scala 781:34] + node _T_837 = and(i0_dp.div, i0_legal_decode_d) @[dec_decode_ctl.scala 782:50] + d_d.bits.i0div <= _T_837 @[dec_decode_ctl.scala 782:34] + node _T_838 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[dec_decode_ctl.scala 784:61] + d_d.bits.csrwen <= _T_838 @[dec_decode_ctl.scala 784:34] + node _T_839 = and(i0_csr_write_only_d, io.dec_aln.dec_i0_decode_d) @[dec_decode_ctl.scala 785:58] + d_d.bits.csrwonly <= _T_839 @[dec_decode_ctl.scala 785:34] + node _T_840 = bits(d_d.bits.csrwen, 0, 0) @[lib.scala 8:44] + node _T_841 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 786:61] + node _T_842 = mux(_T_840, _T_841, UInt<1>("h00")) @[dec_decode_ctl.scala 786:41] + d_d.bits.csrwaddr <= _T_842 @[dec_decode_ctl.scala 786:34] + node _T_843 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 788:63] + wire _T_844 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 630:37] + _T_844.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 630:37] + _T_844.bits.csrwonly <= UInt<1>("h00") @[lib.scala 630:37] + _T_844.bits.csrwen <= UInt<1>("h00") @[lib.scala 630:37] + _T_844.bits.i0v <= UInt<1>("h00") @[lib.scala 630:37] + _T_844.bits.i0div <= UInt<1>("h00") @[lib.scala 630:37] + _T_844.bits.i0store <= UInt<1>("h00") @[lib.scala 630:37] + _T_844.bits.i0load <= UInt<1>("h00") @[lib.scala 630:37] + _T_844.bits.i0rd <= UInt<5>("h00") @[lib.scala 630:37] + _T_844.valid <= UInt<1>("h00") @[lib.scala 630:37] + reg _T_845 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, clock with : (reset => (reset, _T_844)) @[Reg.scala 27:20] + when _T_843 : @[Reg.scala 28:19] + _T_845.bits.csrwaddr <= d_d.bits.csrwaddr @[Reg.scala 28:23] + _T_845.bits.csrwonly <= d_d.bits.csrwonly @[Reg.scala 28:23] + _T_845.bits.csrwen <= d_d.bits.csrwen @[Reg.scala 28:23] + _T_845.bits.i0v <= d_d.bits.i0v @[Reg.scala 28:23] + _T_845.bits.i0div <= d_d.bits.i0div @[Reg.scala 28:23] + _T_845.bits.i0store <= d_d.bits.i0store @[Reg.scala 28:23] + _T_845.bits.i0load <= d_d.bits.i0load @[Reg.scala 28:23] + _T_845.bits.i0rd <= d_d.bits.i0rd @[Reg.scala 28:23] + _T_845.valid <= d_d.valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + x_d.bits.csrwaddr <= _T_845.bits.csrwaddr @[dec_decode_ctl.scala 788:7] + x_d.bits.csrwonly <= _T_845.bits.csrwonly @[dec_decode_ctl.scala 788:7] + x_d.bits.csrwen <= _T_845.bits.csrwen @[dec_decode_ctl.scala 788:7] + x_d.bits.i0v <= _T_845.bits.i0v @[dec_decode_ctl.scala 788:7] + x_d.bits.i0div <= _T_845.bits.i0div @[dec_decode_ctl.scala 788:7] + x_d.bits.i0store <= _T_845.bits.i0store @[dec_decode_ctl.scala 788:7] + x_d.bits.i0load <= _T_845.bits.i0load @[dec_decode_ctl.scala 788:7] + x_d.bits.i0rd <= _T_845.bits.i0rd @[dec_decode_ctl.scala 788:7] + x_d.valid <= _T_845.valid @[dec_decode_ctl.scala 788:7] + wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 789:20] + x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[dec_decode_ctl.scala 790:10] + x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[dec_decode_ctl.scala 790:10] + x_d_in.bits.csrwen <= x_d.bits.csrwen @[dec_decode_ctl.scala 790:10] + x_d_in.bits.i0v <= x_d.bits.i0v @[dec_decode_ctl.scala 790:10] + x_d_in.bits.i0div <= x_d.bits.i0div @[dec_decode_ctl.scala 790:10] + x_d_in.bits.i0store <= x_d.bits.i0store @[dec_decode_ctl.scala 790:10] + x_d_in.bits.i0load <= x_d.bits.i0load @[dec_decode_ctl.scala 790:10] + x_d_in.bits.i0rd <= x_d.bits.i0rd @[dec_decode_ctl.scala 790:10] + x_d_in.valid <= x_d.valid @[dec_decode_ctl.scala 790:10] + node _T_846 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 791:49] + node _T_847 = and(x_d.bits.i0v, _T_846) @[dec_decode_ctl.scala 791:47] + node _T_848 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 791:78] + node _T_849 = and(_T_847, _T_848) @[dec_decode_ctl.scala 791:76] + x_d_in.bits.i0v <= _T_849 @[dec_decode_ctl.scala 791:27] + node _T_850 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 792:35] + node _T_851 = and(x_d.valid, _T_850) @[dec_decode_ctl.scala 792:33] + node _T_852 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 792:64] + node _T_853 = and(_T_851, _T_852) @[dec_decode_ctl.scala 792:62] + x_d_in.valid <= _T_853 @[dec_decode_ctl.scala 792:20] + node _T_854 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 794:65] + wire _T_855 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 630:37] + _T_855.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 630:37] + _T_855.bits.csrwonly <= UInt<1>("h00") @[lib.scala 630:37] + _T_855.bits.csrwen <= UInt<1>("h00") @[lib.scala 630:37] + _T_855.bits.i0v <= UInt<1>("h00") @[lib.scala 630:37] + _T_855.bits.i0div <= UInt<1>("h00") @[lib.scala 630:37] + _T_855.bits.i0store <= UInt<1>("h00") @[lib.scala 630:37] + _T_855.bits.i0load <= UInt<1>("h00") @[lib.scala 630:37] + _T_855.bits.i0rd <= UInt<5>("h00") @[lib.scala 630:37] + _T_855.valid <= UInt<1>("h00") @[lib.scala 630:37] + reg _T_856 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, clock with : (reset => (reset, _T_855)) @[Reg.scala 27:20] + when _T_854 : @[Reg.scala 28:19] + _T_856.bits.csrwaddr <= x_d_in.bits.csrwaddr @[Reg.scala 28:23] + _T_856.bits.csrwonly <= x_d_in.bits.csrwonly @[Reg.scala 28:23] + _T_856.bits.csrwen <= x_d_in.bits.csrwen @[Reg.scala 28:23] + _T_856.bits.i0v <= x_d_in.bits.i0v @[Reg.scala 28:23] + _T_856.bits.i0div <= x_d_in.bits.i0div @[Reg.scala 28:23] + _T_856.bits.i0store <= x_d_in.bits.i0store @[Reg.scala 28:23] + _T_856.bits.i0load <= x_d_in.bits.i0load @[Reg.scala 28:23] + _T_856.bits.i0rd <= x_d_in.bits.i0rd @[Reg.scala 28:23] + _T_856.valid <= x_d_in.valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + r_d.bits.csrwaddr <= _T_856.bits.csrwaddr @[dec_decode_ctl.scala 794:7] + r_d.bits.csrwonly <= _T_856.bits.csrwonly @[dec_decode_ctl.scala 794:7] + r_d.bits.csrwen <= _T_856.bits.csrwen @[dec_decode_ctl.scala 794:7] + r_d.bits.i0v <= _T_856.bits.i0v @[dec_decode_ctl.scala 794:7] + r_d.bits.i0div <= _T_856.bits.i0div @[dec_decode_ctl.scala 794:7] + r_d.bits.i0store <= _T_856.bits.i0store @[dec_decode_ctl.scala 794:7] + r_d.bits.i0load <= _T_856.bits.i0load @[dec_decode_ctl.scala 794:7] + r_d.bits.i0rd <= _T_856.bits.i0rd @[dec_decode_ctl.scala 794:7] + r_d.valid <= _T_856.valid @[dec_decode_ctl.scala 794:7] + r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 795:10] + r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[dec_decode_ctl.scala 795:10] + r_d_in.bits.csrwen <= r_d.bits.csrwen @[dec_decode_ctl.scala 795:10] + r_d_in.bits.i0v <= r_d.bits.i0v @[dec_decode_ctl.scala 795:10] + r_d_in.bits.i0div <= r_d.bits.i0div @[dec_decode_ctl.scala 795:10] + r_d_in.bits.i0store <= r_d.bits.i0store @[dec_decode_ctl.scala 795:10] + r_d_in.bits.i0load <= r_d.bits.i0load @[dec_decode_ctl.scala 795:10] + r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 795:10] + r_d_in.valid <= r_d.valid @[dec_decode_ctl.scala 795:10] + r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 796:22] + node _T_857 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 798:51] + node _T_858 = and(r_d.bits.i0v, _T_857) @[dec_decode_ctl.scala 798:49] + r_d_in.bits.i0v <= _T_858 @[dec_decode_ctl.scala 798:27] + node _T_859 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 799:37] + node _T_860 = and(r_d.valid, _T_859) @[dec_decode_ctl.scala 799:35] + r_d_in.valid <= _T_860 @[dec_decode_ctl.scala 799:20] + node _T_861 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 800:51] + node _T_862 = and(r_d.bits.i0load, _T_861) @[dec_decode_ctl.scala 800:49] + r_d_in.bits.i0load <= _T_862 @[dec_decode_ctl.scala 800:27] + node _T_863 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 801:51] + node _T_864 = and(r_d.bits.i0store, _T_863) @[dec_decode_ctl.scala 801:49] + r_d_in.bits.i0store <= _T_864 @[dec_decode_ctl.scala 801:27] + node _T_865 = bits(i0_wb_ctl_en, 0, 0) @[dec_decode_ctl.scala 803:66] + wire _T_866 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 630:37] + _T_866.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 630:37] + _T_866.bits.csrwonly <= UInt<1>("h00") @[lib.scala 630:37] + _T_866.bits.csrwen <= UInt<1>("h00") @[lib.scala 630:37] + _T_866.bits.i0v <= UInt<1>("h00") @[lib.scala 630:37] + _T_866.bits.i0div <= UInt<1>("h00") @[lib.scala 630:37] + _T_866.bits.i0store <= UInt<1>("h00") @[lib.scala 630:37] + _T_866.bits.i0load <= UInt<1>("h00") @[lib.scala 630:37] + _T_866.bits.i0rd <= UInt<5>("h00") @[lib.scala 630:37] + _T_866.valid <= UInt<1>("h00") @[lib.scala 630:37] + reg _T_867 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, clock with : (reset => (reset, _T_866)) @[Reg.scala 27:20] + when _T_865 : @[Reg.scala 28:19] + _T_867.bits.csrwaddr <= r_d_in.bits.csrwaddr @[Reg.scala 28:23] + _T_867.bits.csrwonly <= r_d_in.bits.csrwonly @[Reg.scala 28:23] + _T_867.bits.csrwen <= r_d_in.bits.csrwen @[Reg.scala 28:23] + _T_867.bits.i0v <= r_d_in.bits.i0v @[Reg.scala 28:23] + _T_867.bits.i0div <= r_d_in.bits.i0div @[Reg.scala 28:23] + _T_867.bits.i0store <= r_d_in.bits.i0store @[Reg.scala 28:23] + _T_867.bits.i0load <= r_d_in.bits.i0load @[Reg.scala 28:23] + _T_867.bits.i0rd <= r_d_in.bits.i0rd @[Reg.scala 28:23] + _T_867.valid <= r_d_in.valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wbd.bits.csrwaddr <= _T_867.bits.csrwaddr @[dec_decode_ctl.scala 803:7] + wbd.bits.csrwonly <= _T_867.bits.csrwonly @[dec_decode_ctl.scala 803:7] + wbd.bits.csrwen <= _T_867.bits.csrwen @[dec_decode_ctl.scala 803:7] + wbd.bits.i0v <= _T_867.bits.i0v @[dec_decode_ctl.scala 803:7] + wbd.bits.i0div <= _T_867.bits.i0div @[dec_decode_ctl.scala 803:7] + wbd.bits.i0store <= _T_867.bits.i0store @[dec_decode_ctl.scala 803:7] + wbd.bits.i0load <= _T_867.bits.i0load @[dec_decode_ctl.scala 803:7] + wbd.bits.i0rd <= _T_867.bits.i0rd @[dec_decode_ctl.scala 803:7] + wbd.valid <= _T_867.valid @[dec_decode_ctl.scala 803:7] + io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[dec_decode_ctl.scala 805:27] + node _T_868 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 806:47] + node _T_869 = and(r_d_in.bits.i0v, _T_868) @[dec_decode_ctl.scala 806:45] + i0_wen_r <= _T_869 @[dec_decode_ctl.scala 806:25] + node _T_870 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[dec_decode_ctl.scala 807:49] + node _T_871 = and(i0_wen_r, _T_870) @[dec_decode_ctl.scala 807:47] + node _T_872 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[dec_decode_ctl.scala 807:70] + node _T_873 = and(_T_871, _T_872) @[dec_decode_ctl.scala 807:68] + io.dec_i0_wen_r <= _T_873 @[dec_decode_ctl.scala 807:32] + io.dec_i0_wdata_r <= i0_result_corr_r @[dec_decode_ctl.scala 808:26] + node _T_874 = or(x_d.bits.i0v, x_d.bits.csrwen) @[dec_decode_ctl.scala 811:74] + node _T_875 = or(_T_874, debug_valid_x) @[dec_decode_ctl.scala 811:92] + node _T_876 = and(i0_r_data_en, _T_875) @[dec_decode_ctl.scala 811:58] + node _T_877 = eq(_T_876, UInt<1>("h01")) @[dec_decode_ctl.scala 811:110] + inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 404:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_4.io.en <= _T_877 @[lib.scala 407:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg i0_result_r_raw : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_877 : @[Reg.scala 28:19] + i0_result_r_raw <= i0_result_x @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_878 = and(x_d.bits.i0v, x_d.bits.i0load) @[dec_decode_ctl.scala 817:47] + node _T_879 = bits(_T_878, 0, 0) @[dec_decode_ctl.scala 817:66] + node _T_880 = mux(_T_879, io.lsu_result_m, io.decode_exu.exu_i0_result_x) @[dec_decode_ctl.scala 817:32] + i0_result_x <= _T_880 @[dec_decode_ctl.scala 817:26] + i0_result_r <= i0_result_r_raw @[dec_decode_ctl.scala 818:26] + node _T_881 = and(r_d.bits.i0v, r_d.bits.i0load) @[dec_decode_ctl.scala 822:42] + node _T_882 = bits(_T_881, 0, 0) @[dec_decode_ctl.scala 822:61] + node _T_883 = mux(_T_882, io.lsu_result_corr_r, i0_result_r_raw) @[dec_decode_ctl.scala 822:27] + i0_result_corr_r <= _T_883 @[dec_decode_ctl.scala 822:21] + node _T_884 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 823:73] + node _T_885 = and(io.decode_exu.i0_ap.predict_nt, _T_884) @[dec_decode_ctl.scala 823:71] + node _T_886 = bits(_T_885, 0, 0) @[dec_decode_ctl.scala 823:85] + wire _T_887 : UInt<1>[10] @[lib.scala 12:48] + _T_887[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_887[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_887[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_887[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_887[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_887[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_887[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_887[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_887[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_887[9] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_888 = cat(_T_887[0], _T_887[1]) @[Cat.scala 29:58] + node _T_889 = cat(_T_888, _T_887[2]) @[Cat.scala 29:58] + node _T_890 = cat(_T_889, _T_887[3]) @[Cat.scala 29:58] + node _T_891 = cat(_T_890, _T_887[4]) @[Cat.scala 29:58] + node _T_892 = cat(_T_891, _T_887[5]) @[Cat.scala 29:58] + node _T_893 = cat(_T_892, _T_887[6]) @[Cat.scala 29:58] + node _T_894 = cat(_T_893, _T_887[7]) @[Cat.scala 29:58] + node _T_895 = cat(_T_894, _T_887[8]) @[Cat.scala 29:58] + node _T_896 = cat(_T_895, _T_887[9]) @[Cat.scala 29:58] + node _T_897 = cat(_T_896, io.dec_i0_pc4_d) @[Cat.scala 29:58] + node _T_898 = cat(_T_897, i0_ap_pc2) @[Cat.scala 29:58] + node _T_899 = mux(_T_886, i0_br_offset, _T_898) @[dec_decode_ctl.scala 823:38] + io.dec_alu.dec_i0_br_immed_d <= _T_899 @[dec_decode_ctl.scala 823:32] + wire last_br_immed_d : UInt<12> + last_br_immed_d <= UInt<1>("h00") + node _T_900 = bits(io.decode_exu.i0_ap.predict_nt, 0, 0) @[dec_decode_ctl.scala 825:59] + wire _T_901 : UInt<1>[10] @[lib.scala 12:48] + _T_901[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_901[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_901[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_901[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_901[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_901[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_901[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_901[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_901[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_901[9] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_902 = cat(_T_901[0], _T_901[1]) @[Cat.scala 29:58] + node _T_903 = cat(_T_902, _T_901[2]) @[Cat.scala 29:58] + node _T_904 = cat(_T_903, _T_901[3]) @[Cat.scala 29:58] + node _T_905 = cat(_T_904, _T_901[4]) @[Cat.scala 29:58] + node _T_906 = cat(_T_905, _T_901[5]) @[Cat.scala 29:58] + node _T_907 = cat(_T_906, _T_901[6]) @[Cat.scala 29:58] + node _T_908 = cat(_T_907, _T_901[7]) @[Cat.scala 29:58] + node _T_909 = cat(_T_908, _T_901[8]) @[Cat.scala 29:58] + node _T_910 = cat(_T_909, _T_901[9]) @[Cat.scala 29:58] + node _T_911 = cat(_T_910, io.dec_i0_pc4_d) @[Cat.scala 29:58] + node _T_912 = cat(_T_911, i0_ap_pc2) @[Cat.scala 29:58] + node _T_913 = mux(_T_900, _T_912, i0_br_offset) @[dec_decode_ctl.scala 825:25] + last_br_immed_d <= _T_913 @[dec_decode_ctl.scala 825:19] + wire last_br_immed_x : UInt<12> + last_br_immed_x <= UInt<1>("h00") + node _T_914 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 827:58] + inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 404:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_5.io.en <= _T_914 @[lib.scala 407:17] + rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_915 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_914 : @[Reg.scala 28:19] + _T_915 <= last_br_immed_d @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + last_br_immed_x <= _T_915 @[dec_decode_ctl.scala 827:19] + node _T_916 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 831:45] + node _T_917 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 831:76] + node div_e1_to_r = or(_T_916, _T_917) @[dec_decode_ctl.scala 831:58] + node _T_918 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 833:48] + node _T_919 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 833:77] + node _T_920 = and(_T_918, _T_919) @[dec_decode_ctl.scala 833:60] + node _T_921 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 834:21] + node _T_922 = and(_T_921, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 834:33] + node _T_923 = or(_T_920, _T_922) @[dec_decode_ctl.scala 833:94] + node _T_924 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 835:21] + node _T_925 = and(_T_924, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 835:33] + node _T_926 = and(_T_925, io.dec_tlu_i0_kill_writeb_r) @[dec_decode_ctl.scala 835:60] + node div_flush = or(_T_923, _T_926) @[dec_decode_ctl.scala 834:62] + node _T_927 = and(io.dec_div_active, div_flush) @[dec_decode_ctl.scala 839:51] + node _T_928 = eq(div_e1_to_r, UInt<1>("h00")) @[dec_decode_ctl.scala 840:26] + node _T_929 = and(io.dec_div_active, _T_928) @[dec_decode_ctl.scala 840:24] + node _T_930 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[dec_decode_ctl.scala 840:56] + node _T_931 = and(_T_929, _T_930) @[dec_decode_ctl.scala 840:39] + node _T_932 = and(_T_931, i0_wen_r) @[dec_decode_ctl.scala 840:77] + node nonblock_div_cancel = or(_T_927, _T_932) @[dec_decode_ctl.scala 839:65] + node _T_933 = bits(nonblock_div_cancel, 0, 0) @[dec_decode_ctl.scala 842:61] + io.dec_div.dec_div_cancel <= _T_933 @[dec_decode_ctl.scala 842:37] + node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 843:55] + node _T_934 = eq(io.exu_div_wren, UInt<1>("h00")) @[dec_decode_ctl.scala 845:59] + node _T_935 = and(io.dec_div_active, _T_934) @[dec_decode_ctl.scala 845:57] + node _T_936 = eq(nonblock_div_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 845:78] + node _T_937 = and(_T_935, _T_936) @[dec_decode_ctl.scala 845:76] + node _T_938 = or(i0_div_decode_d, _T_937) @[dec_decode_ctl.scala 845:36] + div_active_in <= _T_938 @[dec_decode_ctl.scala 845:17] + node _T_939 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_div_active) @[dec_decode_ctl.scala 850:60] + node _T_940 = eq(io.div_waddr_wb, i0r.rs1) @[dec_decode_ctl.scala 850:99] + node _T_941 = and(_T_939, _T_940) @[dec_decode_ctl.scala 850:80] + node _T_942 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_div_active) @[dec_decode_ctl.scala 851:36] + node _T_943 = eq(io.div_waddr_wb, i0r.rs2) @[dec_decode_ctl.scala 851:75] + node _T_944 = and(_T_942, _T_943) @[dec_decode_ctl.scala 851:56] + node _T_945 = or(_T_941, _T_944) @[dec_decode_ctl.scala 850:113] + i0_nonblock_div_stall <= _T_945 @[dec_decode_ctl.scala 850:26] + node trace_enable = not(io.dec_tlu_trace_disable) @[dec_decode_ctl.scala 858:22] + node _T_946 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 860:58] + inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 404:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_6.io.en <= _T_946 @[lib.scala 407:17] + rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_947 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_946 : @[Reg.scala 28:19] + _T_947 <= i0r.rd @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.div_waddr_wb <= _T_947 @[dec_decode_ctl.scala 860:19] + node _T_948 = and(i0_x_data_en, trace_enable) @[dec_decode_ctl.scala 862:50] + node _T_949 = bits(_T_948, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 404:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_7.io.en <= _T_949 @[lib.scala 407:17] + rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg i0_inst_x : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_949 : @[Reg.scala 28:19] + i0_inst_x <= i0_inst_d @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_950 = and(i0_r_data_en, trace_enable) @[dec_decode_ctl.scala 863:50] + node _T_951 = bits(_T_950, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 404:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_8.io.en <= _T_951 @[lib.scala 407:17] + rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg i0_inst_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_951 : @[Reg.scala 28:19] + i0_inst_r <= i0_inst_x @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_952 = and(i0_wb_data_en, trace_enable) @[dec_decode_ctl.scala 865:51] + node _T_953 = bits(_T_952, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 404:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_9.io.en <= _T_953 @[lib.scala 407:17] + rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg i0_inst_wb : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_953 : @[Reg.scala 28:19] + i0_inst_wb <= i0_inst_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_954 = and(i0_wb_data_en, trace_enable) @[dec_decode_ctl.scala 866:54] + node _T_955 = bits(_T_954, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 404:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_10.io.en <= _T_955 @[lib.scala 407:17] + rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg i0_pc_wb : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_955 : @[Reg.scala 28:19] + i0_pc_wb <= io.dec_tlu_i0_pc_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.dec_i0_inst_wb <= i0_inst_wb @[dec_decode_ctl.scala 868:21] + io.dec_i0_pc_wb <= i0_pc_wb @[dec_decode_ctl.scala 869:19] + node _T_956 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 870:67] + wire _T_957 : UInt<31> @[lib.scala 648:38] + _T_957 <= UInt<1>("h00") @[lib.scala 648:38] + reg dec_i0_pc_r : UInt, clock with : (reset => (reset, _T_957)) @[Reg.scala 27:20] + when _T_956 : @[Reg.scala 28:19] + dec_i0_pc_r <= io.dec_alu.exu_i0_pc_x @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[dec_decode_ctl.scala 872:27] + node _T_958 = cat(io.dec_alu.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_959 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_960 = bits(_T_958, 12, 1) @[lib.scala 68:24] + node _T_961 = bits(_T_959, 12, 1) @[lib.scala 68:40] + node _T_962 = add(_T_960, _T_961) @[lib.scala 68:31] + node _T_963 = bits(_T_958, 31, 13) @[lib.scala 69:20] + node _T_964 = add(_T_963, UInt<1>("h01")) @[lib.scala 69:27] + node _T_965 = tail(_T_964, 1) @[lib.scala 69:27] + node _T_966 = bits(_T_958, 31, 13) @[lib.scala 70:20] + node _T_967 = sub(_T_966, UInt<1>("h01")) @[lib.scala 70:27] + node _T_968 = tail(_T_967, 1) @[lib.scala 70:27] + node _T_969 = bits(_T_959, 12, 12) @[lib.scala 71:22] + node _T_970 = bits(_T_962, 12, 12) @[lib.scala 72:39] + node _T_971 = eq(_T_970, UInt<1>("h00")) @[lib.scala 72:28] + node _T_972 = xor(_T_969, _T_971) @[lib.scala 72:26] + node _T_973 = bits(_T_972, 0, 0) @[lib.scala 72:64] + node _T_974 = bits(_T_958, 31, 13) @[lib.scala 72:76] + node _T_975 = eq(_T_969, UInt<1>("h00")) @[lib.scala 73:20] + node _T_976 = bits(_T_962, 12, 12) @[lib.scala 73:39] + node _T_977 = and(_T_975, _T_976) @[lib.scala 73:26] + node _T_978 = bits(_T_977, 0, 0) @[lib.scala 73:64] + node _T_979 = bits(_T_962, 12, 12) @[lib.scala 74:39] + node _T_980 = eq(_T_979, UInt<1>("h00")) @[lib.scala 74:28] + node _T_981 = and(_T_969, _T_980) @[lib.scala 74:26] + node _T_982 = bits(_T_981, 0, 0) @[lib.scala 74:64] + node _T_983 = mux(_T_973, _T_974, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_984 = mux(_T_978, _T_965, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_985 = mux(_T_982, _T_968, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_986 = or(_T_983, _T_984) @[Mux.scala 27:72] + node _T_987 = or(_T_986, _T_985) @[Mux.scala 27:72] + wire _T_988 : UInt<19> @[Mux.scala 27:72] + _T_988 <= _T_987 @[Mux.scala 27:72] + node _T_989 = bits(_T_962, 11, 0) @[lib.scala 74:94] + node _T_990 = cat(_T_988, _T_989) @[Cat.scala 29:58] + node temp_pred_correct_npc_x = cat(_T_990, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_991 = bits(temp_pred_correct_npc_x, 31, 1) @[dec_decode_ctl.scala 877:62] + io.decode_exu.pred_correct_npc_x <= _T_991 @[dec_decode_ctl.scala 877:36] + node _T_992 = and(io.decode_exu.dec_i0_rs1_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 881:59] + node _T_993 = eq(x_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 881:91] + node i0_rs1_depend_i0_x = and(_T_992, _T_993) @[dec_decode_ctl.scala 881:74] + node _T_994 = and(io.decode_exu.dec_i0_rs1_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 882:59] + node _T_995 = eq(r_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 882:91] + node i0_rs1_depend_i0_r = and(_T_994, _T_995) @[dec_decode_ctl.scala 882:74] + node _T_996 = and(io.decode_exu.dec_i0_rs2_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 884:59] + node _T_997 = eq(x_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 884:91] + node i0_rs2_depend_i0_x = and(_T_996, _T_997) @[dec_decode_ctl.scala 884:74] + node _T_998 = and(io.decode_exu.dec_i0_rs2_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 885:59] + node _T_999 = eq(r_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 885:91] + node i0_rs2_depend_i0_r = and(_T_998, _T_999) @[dec_decode_ctl.scala 885:74] + node _T_1000 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 887:44] + node _T_1001 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 887:81] + wire _T_1002 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 887:109] + _T_1002.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 887:109] + _T_1002.load <= UInt<1>("h00") @[dec_decode_ctl.scala 887:109] + _T_1002.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 887:109] + node _T_1003 = mux(_T_1001, i0_r_c, _T_1002) @[dec_decode_ctl.scala 887:61] + node _T_1004 = mux(_T_1000, i0_x_c, _T_1003) @[dec_decode_ctl.scala 887:24] + i0_rs1_class_d.alu <= _T_1004.alu @[dec_decode_ctl.scala 887:18] + i0_rs1_class_d.load <= _T_1004.load @[dec_decode_ctl.scala 887:18] + i0_rs1_class_d.mul <= _T_1004.mul @[dec_decode_ctl.scala 887:18] + node _T_1005 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 888:44] + node _T_1006 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 888:83] + node _T_1007 = mux(_T_1006, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 888:63] + node _T_1008 = mux(_T_1005, UInt<2>("h01"), _T_1007) @[dec_decode_ctl.scala 888:24] + i0_rs1_depth_d <= _T_1008 @[dec_decode_ctl.scala 888:18] + node _T_1009 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 889:44] + node _T_1010 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 889:81] + wire _T_1011 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 889:109] + _T_1011.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109] + _T_1011.load <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109] + _T_1011.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109] + node _T_1012 = mux(_T_1010, i0_r_c, _T_1011) @[dec_decode_ctl.scala 889:61] + node _T_1013 = mux(_T_1009, i0_x_c, _T_1012) @[dec_decode_ctl.scala 889:24] + i0_rs2_class_d.alu <= _T_1013.alu @[dec_decode_ctl.scala 889:18] + i0_rs2_class_d.load <= _T_1013.load @[dec_decode_ctl.scala 889:18] + i0_rs2_class_d.mul <= _T_1013.mul @[dec_decode_ctl.scala 889:18] + node _T_1014 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 890:44] + node _T_1015 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 890:83] + node _T_1016 = mux(_T_1015, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 890:63] + node _T_1017 = mux(_T_1014, UInt<2>("h01"), _T_1016) @[dec_decode_ctl.scala 890:24] + i0_rs2_depth_d <= _T_1017 @[dec_decode_ctl.scala 890:18] + i0_load_block_d <= UInt<1>("h00") @[dec_decode_ctl.scala 900:21] + node _T_1018 = or(i0_dp.load, i0_dp.store) @[dec_decode_ctl.scala 901:43] + node _T_1019 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 901:74] + node _T_1020 = and(_T_1018, _T_1019) @[dec_decode_ctl.scala 901:58] + node _T_1021 = and(_T_1020, i0_rs1_class_d.load) @[dec_decode_ctl.scala 901:78] + load_ldst_bypass_d <= _T_1021 @[dec_decode_ctl.scala 901:27] + node _T_1022 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 902:59] + node _T_1023 = and(i0_dp.store, _T_1022) @[dec_decode_ctl.scala 902:43] + node _T_1024 = and(_T_1023, i0_rs2_class_d.load) @[dec_decode_ctl.scala 902:63] + store_data_bypass_d <= _T_1024 @[dec_decode_ctl.scala 902:25] + store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 903:25] + node _T_1025 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 907:73] + node _T_1026 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[dec_decode_ctl.scala 907:130] + node i0_rs1_nonblock_load_bypass_en_d = and(_T_1025, _T_1026) @[dec_decode_ctl.scala 907:100] + node _T_1027 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 909:73] + node _T_1028 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[dec_decode_ctl.scala 909:130] + node i0_rs2_nonblock_load_bypass_en_d = and(_T_1027, _T_1028) @[dec_decode_ctl.scala 909:100] + node _T_1029 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 912:41] + node _T_1030 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 912:66] + node _T_1031 = and(_T_1029, _T_1030) @[dec_decode_ctl.scala 912:45] + node _T_1032 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 912:104] + node _T_1033 = and(_T_1032, i0_rs1_class_d.load) @[dec_decode_ctl.scala 912:108] + node _T_1034 = bits(i0_rs1_depth_d, 1, 1) @[dec_decode_ctl.scala 912:149] + node _T_1035 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 912:175] + node _T_1036 = or(_T_1035, i0_rs1_class_d.load) @[dec_decode_ctl.scala 912:196] + node _T_1037 = and(_T_1034, _T_1036) @[dec_decode_ctl.scala 912:153] + node _T_1038 = cat(_T_1031, _T_1033) @[Cat.scala 29:58] + node _T_1039 = cat(_T_1038, _T_1037) @[Cat.scala 29:58] + i0_rs1bypass <= _T_1039 @[dec_decode_ctl.scala 912:18] + node _T_1040 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 914:41] + node _T_1041 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 914:67] + node _T_1042 = and(_T_1040, _T_1041) @[dec_decode_ctl.scala 914:45] + node _T_1043 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 914:105] + node _T_1044 = and(_T_1043, i0_rs2_class_d.load) @[dec_decode_ctl.scala 914:109] + node _T_1045 = bits(i0_rs2_depth_d, 1, 1) @[dec_decode_ctl.scala 914:149] + node _T_1046 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 914:175] + node _T_1047 = or(_T_1046, i0_rs2_class_d.load) @[dec_decode_ctl.scala 914:196] + node _T_1048 = and(_T_1045, _T_1047) @[dec_decode_ctl.scala 914:153] + node _T_1049 = cat(_T_1042, _T_1044) @[Cat.scala 29:58] + node _T_1050 = cat(_T_1049, _T_1048) @[Cat.scala 29:58] + i0_rs2bypass <= _T_1050 @[dec_decode_ctl.scala 914:18] + node _T_1051 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 916:66] + node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[dec_decode_ctl.scala 916:53] + node _T_1053 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 916:85] + node _T_1054 = eq(_T_1053, UInt<1>("h00")) @[dec_decode_ctl.scala 916:72] + node _T_1055 = and(_T_1052, _T_1054) @[dec_decode_ctl.scala 916:70] + node _T_1056 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 916:104] + node _T_1057 = eq(_T_1056, UInt<1>("h00")) @[dec_decode_ctl.scala 916:91] + node _T_1058 = and(_T_1055, _T_1057) @[dec_decode_ctl.scala 916:89] + node _T_1059 = and(_T_1058, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 916:108] + node _T_1060 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 916:155] + node _T_1061 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 916:171] + node _T_1062 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 916:187] + node _T_1063 = cat(_T_1061, _T_1062) @[Cat.scala 29:58] + node _T_1064 = cat(_T_1059, _T_1060) @[Cat.scala 29:58] + node _T_1065 = cat(_T_1064, _T_1063) @[Cat.scala 29:58] + io.decode_exu.dec_i0_rs1_bypass_en_d <= _T_1065 @[dec_decode_ctl.scala 916:45] + node _T_1066 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 917:66] + node _T_1067 = eq(_T_1066, UInt<1>("h00")) @[dec_decode_ctl.scala 917:53] + node _T_1068 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 917:85] + node _T_1069 = eq(_T_1068, UInt<1>("h00")) @[dec_decode_ctl.scala 917:72] + node _T_1070 = and(_T_1067, _T_1069) @[dec_decode_ctl.scala 917:70] + node _T_1071 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 917:104] + node _T_1072 = eq(_T_1071, UInt<1>("h00")) @[dec_decode_ctl.scala 917:91] + node _T_1073 = and(_T_1070, _T_1072) @[dec_decode_ctl.scala 917:89] + node _T_1074 = and(_T_1073, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 917:108] + node _T_1075 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 917:155] + node _T_1076 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 917:171] + node _T_1077 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 917:187] + node _T_1078 = cat(_T_1076, _T_1077) @[Cat.scala 29:58] + node _T_1079 = cat(_T_1074, _T_1075) @[Cat.scala 29:58] + node _T_1080 = cat(_T_1079, _T_1078) @[Cat.scala 29:58] + io.decode_exu.dec_i0_rs2_bypass_en_d <= _T_1080 @[dec_decode_ctl.scala 917:45] + io.decode_exu.dec_i0_result_r <= i0_result_r @[dec_decode_ctl.scala 919:41] + node _T_1081 = or(i0_dp_raw.load, i0_dp_raw.store) @[dec_decode_ctl.scala 921:68] + node _T_1082 = and(io.dec_ib0_valid_d, _T_1081) @[dec_decode_ctl.scala 921:50] + node _T_1083 = eq(io.dctl_dma.dma_dccm_stall_any, UInt<1>("h00")) @[dec_decode_ctl.scala 921:89] + node _T_1084 = and(_T_1082, _T_1083) @[dec_decode_ctl.scala 921:87] + node _T_1085 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 921:123] + node _T_1086 = and(_T_1084, _T_1085) @[dec_decode_ctl.scala 921:121] + node _T_1087 = or(_T_1086, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 921:140] + io.dec_lsu_valid_raw_d <= _T_1087 @[dec_decode_ctl.scala 921:26] + node _T_1088 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 923:6] + node _T_1089 = and(_T_1088, i0_dp.lsu) @[dec_decode_ctl.scala 923:38] + node _T_1090 = and(_T_1089, i0_dp.load) @[dec_decode_ctl.scala 923:50] + node _T_1091 = bits(_T_1090, 0, 0) @[dec_decode_ctl.scala 923:64] + node _T_1092 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 923:81] + node _T_1093 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 924:6] + node _T_1094 = and(_T_1093, i0_dp.lsu) @[dec_decode_ctl.scala 924:38] + node _T_1095 = and(_T_1094, i0_dp.store) @[dec_decode_ctl.scala 924:50] + node _T_1096 = bits(_T_1095, 0, 0) @[dec_decode_ctl.scala 924:65] + node _T_1097 = bits(io.dec_i0_instr_d, 31, 25) @[dec_decode_ctl.scala 924:85] + node _T_1098 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 924:95] + node _T_1099 = cat(_T_1097, _T_1098) @[Cat.scala 29:58] + node _T_1100 = mux(_T_1091, _T_1092, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1101 = mux(_T_1096, _T_1099, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1102 = or(_T_1100, _T_1101) @[Mux.scala 27:72] + wire _T_1103 : UInt<12> @[Mux.scala 27:72] + _T_1103 <= _T_1102 @[Mux.scala 27:72] + io.dec_lsu_offset_d <= _T_1103 @[dec_decode_ctl.scala 922:23] + + extmodule gated_latch_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_11 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_12 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_12 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_12 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_13 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_13 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_13 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_14 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_14 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_14 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_15 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_15 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_15 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_16 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_16 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_16 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_17 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_17 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_17 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_18 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_18 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_18 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_19 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_19 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_19 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_20 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_20 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_20 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_21 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_21 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_21 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_22 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_22 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_22 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_23 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_23 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_23 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_24 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_24 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_24 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_25 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_25 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_25 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_26 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_26 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_26 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_27 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_27 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_27 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_28 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_28 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_28 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_29 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_29 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_29 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_30 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_30 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_30 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_31 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_31 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_31 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_32 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_32 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_32 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_33 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_33 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_33 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_34 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_34 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_34 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_35 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_35 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_35 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_36 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_36 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_36 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_37 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_37 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_37 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_38 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_38 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_38 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_39 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_39 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_39 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_40 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_40 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_40 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_41 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_41 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_41 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module dec_gpr_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip raddr0 : UInt<5>, flip raddr1 : UInt<5>, flip wen0 : UInt<1>, flip waddr0 : UInt<5>, flip wd0 : UInt<32>, flip wen1 : UInt<1>, flip waddr1 : UInt<5>, flip wd1 : UInt<32>, flip wen2 : UInt<1>, flip waddr2 : UInt<5>, flip wd2 : UInt<32>, flip scan_mode : UInt<1>, flip gpr_exu : {flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>}} + + wire w0v : UInt<1>[32] @[dec_gpr_ctl.scala 27:30] + w0v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + wire w1v : UInt<1>[32] @[dec_gpr_ctl.scala 30:30] + w1v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + wire w2v : UInt<1>[32] @[dec_gpr_ctl.scala 33:30] + w2v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + wire gpr_in : UInt<32>[32] @[dec_gpr_ctl.scala 36:30] + gpr_in[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + wire gpr_out : UInt<32>[32] @[dec_gpr_ctl.scala 39:30] + gpr_out[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + wire gpr_wr_en : UInt<32> + gpr_wr_en <= UInt<1>("h00") + w0v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 43:15] + w1v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 44:15] + w2v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 45:15] + gpr_out[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 46:19] + gpr_in[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 47:18] + io.gpr_exu.gpr_i0_rs1_d <= UInt<1>("h00") @[dec_gpr_ctl.scala 48:32] + io.gpr_exu.gpr_i0_rs2_d <= UInt<1>("h00") @[dec_gpr_ctl.scala 49:32] + node _T = eq(io.waddr0, UInt<1>("h01")) @[dec_gpr_ctl.scala 52:52] + node _T_1 = and(io.wen0, _T) @[dec_gpr_ctl.scala 52:40] + w0v[1] <= _T_1 @[dec_gpr_ctl.scala 52:28] + node _T_2 = eq(io.waddr1, UInt<1>("h01")) @[dec_gpr_ctl.scala 53:52] + node _T_3 = and(io.wen1, _T_2) @[dec_gpr_ctl.scala 53:40] + w1v[1] <= _T_3 @[dec_gpr_ctl.scala 53:28] + node _T_4 = eq(io.waddr2, UInt<1>("h01")) @[dec_gpr_ctl.scala 54:52] + node _T_5 = and(io.wen2, _T_4) @[dec_gpr_ctl.scala 54:40] + w2v[1] <= _T_5 @[dec_gpr_ctl.scala 54:28] + node _T_6 = bits(w0v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_7 = mux(_T_6, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_8 = and(_T_7, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_9 = bits(w1v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_10 = mux(_T_9, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_11 = and(_T_10, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_12 = or(_T_8, _T_11) @[dec_gpr_ctl.scala 55:59] + node _T_13 = bits(w2v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_14 = mux(_T_13, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_15 = and(_T_14, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_16 = or(_T_12, _T_15) @[dec_gpr_ctl.scala 55:88] + gpr_in[1] <= _T_16 @[dec_gpr_ctl.scala 55:28] + node _T_17 = eq(io.waddr0, UInt<2>("h02")) @[dec_gpr_ctl.scala 52:52] + node _T_18 = and(io.wen0, _T_17) @[dec_gpr_ctl.scala 52:40] + w0v[2] <= _T_18 @[dec_gpr_ctl.scala 52:28] + node _T_19 = eq(io.waddr1, UInt<2>("h02")) @[dec_gpr_ctl.scala 53:52] + node _T_20 = and(io.wen1, _T_19) @[dec_gpr_ctl.scala 53:40] + w1v[2] <= _T_20 @[dec_gpr_ctl.scala 53:28] + node _T_21 = eq(io.waddr2, UInt<2>("h02")) @[dec_gpr_ctl.scala 54:52] + node _T_22 = and(io.wen2, _T_21) @[dec_gpr_ctl.scala 54:40] + w2v[2] <= _T_22 @[dec_gpr_ctl.scala 54:28] + node _T_23 = bits(w0v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_24 = mux(_T_23, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_25 = and(_T_24, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_26 = bits(w1v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_27 = mux(_T_26, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_28 = and(_T_27, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_29 = or(_T_25, _T_28) @[dec_gpr_ctl.scala 55:59] + node _T_30 = bits(w2v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_31 = mux(_T_30, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_32 = and(_T_31, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_33 = or(_T_29, _T_32) @[dec_gpr_ctl.scala 55:88] + gpr_in[2] <= _T_33 @[dec_gpr_ctl.scala 55:28] + node _T_34 = eq(io.waddr0, UInt<2>("h03")) @[dec_gpr_ctl.scala 52:52] + node _T_35 = and(io.wen0, _T_34) @[dec_gpr_ctl.scala 52:40] + w0v[3] <= _T_35 @[dec_gpr_ctl.scala 52:28] + node _T_36 = eq(io.waddr1, UInt<2>("h03")) @[dec_gpr_ctl.scala 53:52] + node _T_37 = and(io.wen1, _T_36) @[dec_gpr_ctl.scala 53:40] + w1v[3] <= _T_37 @[dec_gpr_ctl.scala 53:28] + node _T_38 = eq(io.waddr2, UInt<2>("h03")) @[dec_gpr_ctl.scala 54:52] + node _T_39 = and(io.wen2, _T_38) @[dec_gpr_ctl.scala 54:40] + w2v[3] <= _T_39 @[dec_gpr_ctl.scala 54:28] + node _T_40 = bits(w0v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_41 = mux(_T_40, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_42 = and(_T_41, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_43 = bits(w1v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_44 = mux(_T_43, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_45 = and(_T_44, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_46 = or(_T_42, _T_45) @[dec_gpr_ctl.scala 55:59] + node _T_47 = bits(w2v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_48 = mux(_T_47, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_49 = and(_T_48, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_50 = or(_T_46, _T_49) @[dec_gpr_ctl.scala 55:88] + gpr_in[3] <= _T_50 @[dec_gpr_ctl.scala 55:28] + node _T_51 = eq(io.waddr0, UInt<3>("h04")) @[dec_gpr_ctl.scala 52:52] + node _T_52 = and(io.wen0, _T_51) @[dec_gpr_ctl.scala 52:40] + w0v[4] <= _T_52 @[dec_gpr_ctl.scala 52:28] + node _T_53 = eq(io.waddr1, UInt<3>("h04")) @[dec_gpr_ctl.scala 53:52] + node _T_54 = and(io.wen1, _T_53) @[dec_gpr_ctl.scala 53:40] + w1v[4] <= _T_54 @[dec_gpr_ctl.scala 53:28] + node _T_55 = eq(io.waddr2, UInt<3>("h04")) @[dec_gpr_ctl.scala 54:52] + node _T_56 = and(io.wen2, _T_55) @[dec_gpr_ctl.scala 54:40] + w2v[4] <= _T_56 @[dec_gpr_ctl.scala 54:28] + node _T_57 = bits(w0v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_58 = mux(_T_57, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_59 = and(_T_58, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_60 = bits(w1v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_61 = mux(_T_60, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_62 = and(_T_61, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_63 = or(_T_59, _T_62) @[dec_gpr_ctl.scala 55:59] + node _T_64 = bits(w2v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_65 = mux(_T_64, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_66 = and(_T_65, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_67 = or(_T_63, _T_66) @[dec_gpr_ctl.scala 55:88] + gpr_in[4] <= _T_67 @[dec_gpr_ctl.scala 55:28] + node _T_68 = eq(io.waddr0, UInt<3>("h05")) @[dec_gpr_ctl.scala 52:52] + node _T_69 = and(io.wen0, _T_68) @[dec_gpr_ctl.scala 52:40] + w0v[5] <= _T_69 @[dec_gpr_ctl.scala 52:28] + node _T_70 = eq(io.waddr1, UInt<3>("h05")) @[dec_gpr_ctl.scala 53:52] + node _T_71 = and(io.wen1, _T_70) @[dec_gpr_ctl.scala 53:40] + w1v[5] <= _T_71 @[dec_gpr_ctl.scala 53:28] + node _T_72 = eq(io.waddr2, UInt<3>("h05")) @[dec_gpr_ctl.scala 54:52] + node _T_73 = and(io.wen2, _T_72) @[dec_gpr_ctl.scala 54:40] + w2v[5] <= _T_73 @[dec_gpr_ctl.scala 54:28] + node _T_74 = bits(w0v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_75 = mux(_T_74, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_76 = and(_T_75, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_77 = bits(w1v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_78 = mux(_T_77, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_79 = and(_T_78, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_80 = or(_T_76, _T_79) @[dec_gpr_ctl.scala 55:59] + node _T_81 = bits(w2v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_82 = mux(_T_81, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_83 = and(_T_82, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_84 = or(_T_80, _T_83) @[dec_gpr_ctl.scala 55:88] + gpr_in[5] <= _T_84 @[dec_gpr_ctl.scala 55:28] + node _T_85 = eq(io.waddr0, UInt<3>("h06")) @[dec_gpr_ctl.scala 52:52] + node _T_86 = and(io.wen0, _T_85) @[dec_gpr_ctl.scala 52:40] + w0v[6] <= _T_86 @[dec_gpr_ctl.scala 52:28] + node _T_87 = eq(io.waddr1, UInt<3>("h06")) @[dec_gpr_ctl.scala 53:52] + node _T_88 = and(io.wen1, _T_87) @[dec_gpr_ctl.scala 53:40] + w1v[6] <= _T_88 @[dec_gpr_ctl.scala 53:28] + node _T_89 = eq(io.waddr2, UInt<3>("h06")) @[dec_gpr_ctl.scala 54:52] + node _T_90 = and(io.wen2, _T_89) @[dec_gpr_ctl.scala 54:40] + w2v[6] <= _T_90 @[dec_gpr_ctl.scala 54:28] + node _T_91 = bits(w0v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_92 = mux(_T_91, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_93 = and(_T_92, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_94 = bits(w1v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_95 = mux(_T_94, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_96 = and(_T_95, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_97 = or(_T_93, _T_96) @[dec_gpr_ctl.scala 55:59] + node _T_98 = bits(w2v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_99 = mux(_T_98, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_100 = and(_T_99, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_101 = or(_T_97, _T_100) @[dec_gpr_ctl.scala 55:88] + gpr_in[6] <= _T_101 @[dec_gpr_ctl.scala 55:28] + node _T_102 = eq(io.waddr0, UInt<3>("h07")) @[dec_gpr_ctl.scala 52:52] + node _T_103 = and(io.wen0, _T_102) @[dec_gpr_ctl.scala 52:40] + w0v[7] <= _T_103 @[dec_gpr_ctl.scala 52:28] + node _T_104 = eq(io.waddr1, UInt<3>("h07")) @[dec_gpr_ctl.scala 53:52] + node _T_105 = and(io.wen1, _T_104) @[dec_gpr_ctl.scala 53:40] + w1v[7] <= _T_105 @[dec_gpr_ctl.scala 53:28] + node _T_106 = eq(io.waddr2, UInt<3>("h07")) @[dec_gpr_ctl.scala 54:52] + node _T_107 = and(io.wen2, _T_106) @[dec_gpr_ctl.scala 54:40] + w2v[7] <= _T_107 @[dec_gpr_ctl.scala 54:28] + node _T_108 = bits(w0v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_109 = mux(_T_108, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_110 = and(_T_109, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_111 = bits(w1v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_112 = mux(_T_111, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_113 = and(_T_112, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_114 = or(_T_110, _T_113) @[dec_gpr_ctl.scala 55:59] + node _T_115 = bits(w2v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_116 = mux(_T_115, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_117 = and(_T_116, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_118 = or(_T_114, _T_117) @[dec_gpr_ctl.scala 55:88] + gpr_in[7] <= _T_118 @[dec_gpr_ctl.scala 55:28] + node _T_119 = eq(io.waddr0, UInt<4>("h08")) @[dec_gpr_ctl.scala 52:52] + node _T_120 = and(io.wen0, _T_119) @[dec_gpr_ctl.scala 52:40] + w0v[8] <= _T_120 @[dec_gpr_ctl.scala 52:28] + node _T_121 = eq(io.waddr1, UInt<4>("h08")) @[dec_gpr_ctl.scala 53:52] + node _T_122 = and(io.wen1, _T_121) @[dec_gpr_ctl.scala 53:40] + w1v[8] <= _T_122 @[dec_gpr_ctl.scala 53:28] + node _T_123 = eq(io.waddr2, UInt<4>("h08")) @[dec_gpr_ctl.scala 54:52] + node _T_124 = and(io.wen2, _T_123) @[dec_gpr_ctl.scala 54:40] + w2v[8] <= _T_124 @[dec_gpr_ctl.scala 54:28] + node _T_125 = bits(w0v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_126 = mux(_T_125, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_127 = and(_T_126, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_128 = bits(w1v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_129 = mux(_T_128, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_130 = and(_T_129, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_131 = or(_T_127, _T_130) @[dec_gpr_ctl.scala 55:59] + node _T_132 = bits(w2v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_133 = mux(_T_132, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_134 = and(_T_133, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_135 = or(_T_131, _T_134) @[dec_gpr_ctl.scala 55:88] + gpr_in[8] <= _T_135 @[dec_gpr_ctl.scala 55:28] + node _T_136 = eq(io.waddr0, UInt<4>("h09")) @[dec_gpr_ctl.scala 52:52] + node _T_137 = and(io.wen0, _T_136) @[dec_gpr_ctl.scala 52:40] + w0v[9] <= _T_137 @[dec_gpr_ctl.scala 52:28] + node _T_138 = eq(io.waddr1, UInt<4>("h09")) @[dec_gpr_ctl.scala 53:52] + node _T_139 = and(io.wen1, _T_138) @[dec_gpr_ctl.scala 53:40] + w1v[9] <= _T_139 @[dec_gpr_ctl.scala 53:28] + node _T_140 = eq(io.waddr2, UInt<4>("h09")) @[dec_gpr_ctl.scala 54:52] + node _T_141 = and(io.wen2, _T_140) @[dec_gpr_ctl.scala 54:40] + w2v[9] <= _T_141 @[dec_gpr_ctl.scala 54:28] + node _T_142 = bits(w0v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_143 = mux(_T_142, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_144 = and(_T_143, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_145 = bits(w1v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_146 = mux(_T_145, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_147 = and(_T_146, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_148 = or(_T_144, _T_147) @[dec_gpr_ctl.scala 55:59] + node _T_149 = bits(w2v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_150 = mux(_T_149, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_151 = and(_T_150, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_152 = or(_T_148, _T_151) @[dec_gpr_ctl.scala 55:88] + gpr_in[9] <= _T_152 @[dec_gpr_ctl.scala 55:28] + node _T_153 = eq(io.waddr0, UInt<4>("h0a")) @[dec_gpr_ctl.scala 52:52] + node _T_154 = and(io.wen0, _T_153) @[dec_gpr_ctl.scala 52:40] + w0v[10] <= _T_154 @[dec_gpr_ctl.scala 52:28] + node _T_155 = eq(io.waddr1, UInt<4>("h0a")) @[dec_gpr_ctl.scala 53:52] + node _T_156 = and(io.wen1, _T_155) @[dec_gpr_ctl.scala 53:40] + w1v[10] <= _T_156 @[dec_gpr_ctl.scala 53:28] + node _T_157 = eq(io.waddr2, UInt<4>("h0a")) @[dec_gpr_ctl.scala 54:52] + node _T_158 = and(io.wen2, _T_157) @[dec_gpr_ctl.scala 54:40] + w2v[10] <= _T_158 @[dec_gpr_ctl.scala 54:28] + node _T_159 = bits(w0v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_160 = mux(_T_159, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_161 = and(_T_160, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_162 = bits(w1v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_163 = mux(_T_162, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_164 = and(_T_163, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_165 = or(_T_161, _T_164) @[dec_gpr_ctl.scala 55:59] + node _T_166 = bits(w2v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_167 = mux(_T_166, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_168 = and(_T_167, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_169 = or(_T_165, _T_168) @[dec_gpr_ctl.scala 55:88] + gpr_in[10] <= _T_169 @[dec_gpr_ctl.scala 55:28] + node _T_170 = eq(io.waddr0, UInt<4>("h0b")) @[dec_gpr_ctl.scala 52:52] + node _T_171 = and(io.wen0, _T_170) @[dec_gpr_ctl.scala 52:40] + w0v[11] <= _T_171 @[dec_gpr_ctl.scala 52:28] + node _T_172 = eq(io.waddr1, UInt<4>("h0b")) @[dec_gpr_ctl.scala 53:52] + node _T_173 = and(io.wen1, _T_172) @[dec_gpr_ctl.scala 53:40] + w1v[11] <= _T_173 @[dec_gpr_ctl.scala 53:28] + node _T_174 = eq(io.waddr2, UInt<4>("h0b")) @[dec_gpr_ctl.scala 54:52] + node _T_175 = and(io.wen2, _T_174) @[dec_gpr_ctl.scala 54:40] + w2v[11] <= _T_175 @[dec_gpr_ctl.scala 54:28] + node _T_176 = bits(w0v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_177 = mux(_T_176, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_178 = and(_T_177, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_179 = bits(w1v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_180 = mux(_T_179, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_181 = and(_T_180, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_182 = or(_T_178, _T_181) @[dec_gpr_ctl.scala 55:59] + node _T_183 = bits(w2v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_184 = mux(_T_183, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_185 = and(_T_184, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_186 = or(_T_182, _T_185) @[dec_gpr_ctl.scala 55:88] + gpr_in[11] <= _T_186 @[dec_gpr_ctl.scala 55:28] + node _T_187 = eq(io.waddr0, UInt<4>("h0c")) @[dec_gpr_ctl.scala 52:52] + node _T_188 = and(io.wen0, _T_187) @[dec_gpr_ctl.scala 52:40] + w0v[12] <= _T_188 @[dec_gpr_ctl.scala 52:28] + node _T_189 = eq(io.waddr1, UInt<4>("h0c")) @[dec_gpr_ctl.scala 53:52] + node _T_190 = and(io.wen1, _T_189) @[dec_gpr_ctl.scala 53:40] + w1v[12] <= _T_190 @[dec_gpr_ctl.scala 53:28] + node _T_191 = eq(io.waddr2, UInt<4>("h0c")) @[dec_gpr_ctl.scala 54:52] + node _T_192 = and(io.wen2, _T_191) @[dec_gpr_ctl.scala 54:40] + w2v[12] <= _T_192 @[dec_gpr_ctl.scala 54:28] + node _T_193 = bits(w0v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_194 = mux(_T_193, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_195 = and(_T_194, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_196 = bits(w1v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_197 = mux(_T_196, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_198 = and(_T_197, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_199 = or(_T_195, _T_198) @[dec_gpr_ctl.scala 55:59] + node _T_200 = bits(w2v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_201 = mux(_T_200, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_202 = and(_T_201, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_203 = or(_T_199, _T_202) @[dec_gpr_ctl.scala 55:88] + gpr_in[12] <= _T_203 @[dec_gpr_ctl.scala 55:28] + node _T_204 = eq(io.waddr0, UInt<4>("h0d")) @[dec_gpr_ctl.scala 52:52] + node _T_205 = and(io.wen0, _T_204) @[dec_gpr_ctl.scala 52:40] + w0v[13] <= _T_205 @[dec_gpr_ctl.scala 52:28] + node _T_206 = eq(io.waddr1, UInt<4>("h0d")) @[dec_gpr_ctl.scala 53:52] + node _T_207 = and(io.wen1, _T_206) @[dec_gpr_ctl.scala 53:40] + w1v[13] <= _T_207 @[dec_gpr_ctl.scala 53:28] + node _T_208 = eq(io.waddr2, UInt<4>("h0d")) @[dec_gpr_ctl.scala 54:52] + node _T_209 = and(io.wen2, _T_208) @[dec_gpr_ctl.scala 54:40] + w2v[13] <= _T_209 @[dec_gpr_ctl.scala 54:28] + node _T_210 = bits(w0v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_211 = mux(_T_210, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_212 = and(_T_211, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_213 = bits(w1v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_214 = mux(_T_213, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_215 = and(_T_214, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_216 = or(_T_212, _T_215) @[dec_gpr_ctl.scala 55:59] + node _T_217 = bits(w2v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_218 = mux(_T_217, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_219 = and(_T_218, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_220 = or(_T_216, _T_219) @[dec_gpr_ctl.scala 55:88] + gpr_in[13] <= _T_220 @[dec_gpr_ctl.scala 55:28] + node _T_221 = eq(io.waddr0, UInt<4>("h0e")) @[dec_gpr_ctl.scala 52:52] + node _T_222 = and(io.wen0, _T_221) @[dec_gpr_ctl.scala 52:40] + w0v[14] <= _T_222 @[dec_gpr_ctl.scala 52:28] + node _T_223 = eq(io.waddr1, UInt<4>("h0e")) @[dec_gpr_ctl.scala 53:52] + node _T_224 = and(io.wen1, _T_223) @[dec_gpr_ctl.scala 53:40] + w1v[14] <= _T_224 @[dec_gpr_ctl.scala 53:28] + node _T_225 = eq(io.waddr2, UInt<4>("h0e")) @[dec_gpr_ctl.scala 54:52] + node _T_226 = and(io.wen2, _T_225) @[dec_gpr_ctl.scala 54:40] + w2v[14] <= _T_226 @[dec_gpr_ctl.scala 54:28] + node _T_227 = bits(w0v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_228 = mux(_T_227, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_229 = and(_T_228, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_230 = bits(w1v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_231 = mux(_T_230, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_232 = and(_T_231, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_233 = or(_T_229, _T_232) @[dec_gpr_ctl.scala 55:59] + node _T_234 = bits(w2v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_236 = and(_T_235, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_237 = or(_T_233, _T_236) @[dec_gpr_ctl.scala 55:88] + gpr_in[14] <= _T_237 @[dec_gpr_ctl.scala 55:28] + node _T_238 = eq(io.waddr0, UInt<4>("h0f")) @[dec_gpr_ctl.scala 52:52] + node _T_239 = and(io.wen0, _T_238) @[dec_gpr_ctl.scala 52:40] + w0v[15] <= _T_239 @[dec_gpr_ctl.scala 52:28] + node _T_240 = eq(io.waddr1, UInt<4>("h0f")) @[dec_gpr_ctl.scala 53:52] + node _T_241 = and(io.wen1, _T_240) @[dec_gpr_ctl.scala 53:40] + w1v[15] <= _T_241 @[dec_gpr_ctl.scala 53:28] + node _T_242 = eq(io.waddr2, UInt<4>("h0f")) @[dec_gpr_ctl.scala 54:52] + node _T_243 = and(io.wen2, _T_242) @[dec_gpr_ctl.scala 54:40] + w2v[15] <= _T_243 @[dec_gpr_ctl.scala 54:28] + node _T_244 = bits(w0v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_245 = mux(_T_244, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_246 = and(_T_245, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_247 = bits(w1v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_248 = mux(_T_247, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_249 = and(_T_248, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_250 = or(_T_246, _T_249) @[dec_gpr_ctl.scala 55:59] + node _T_251 = bits(w2v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_252 = mux(_T_251, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_253 = and(_T_252, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_254 = or(_T_250, _T_253) @[dec_gpr_ctl.scala 55:88] + gpr_in[15] <= _T_254 @[dec_gpr_ctl.scala 55:28] + node _T_255 = eq(io.waddr0, UInt<5>("h010")) @[dec_gpr_ctl.scala 52:52] + node _T_256 = and(io.wen0, _T_255) @[dec_gpr_ctl.scala 52:40] + w0v[16] <= _T_256 @[dec_gpr_ctl.scala 52:28] + node _T_257 = eq(io.waddr1, UInt<5>("h010")) @[dec_gpr_ctl.scala 53:52] + node _T_258 = and(io.wen1, _T_257) @[dec_gpr_ctl.scala 53:40] + w1v[16] <= _T_258 @[dec_gpr_ctl.scala 53:28] + node _T_259 = eq(io.waddr2, UInt<5>("h010")) @[dec_gpr_ctl.scala 54:52] + node _T_260 = and(io.wen2, _T_259) @[dec_gpr_ctl.scala 54:40] + w2v[16] <= _T_260 @[dec_gpr_ctl.scala 54:28] + node _T_261 = bits(w0v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_262 = mux(_T_261, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_263 = and(_T_262, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_264 = bits(w1v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_265 = mux(_T_264, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_266 = and(_T_265, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_267 = or(_T_263, _T_266) @[dec_gpr_ctl.scala 55:59] + node _T_268 = bits(w2v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_269 = mux(_T_268, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_270 = and(_T_269, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_271 = or(_T_267, _T_270) @[dec_gpr_ctl.scala 55:88] + gpr_in[16] <= _T_271 @[dec_gpr_ctl.scala 55:28] + node _T_272 = eq(io.waddr0, UInt<5>("h011")) @[dec_gpr_ctl.scala 52:52] + node _T_273 = and(io.wen0, _T_272) @[dec_gpr_ctl.scala 52:40] + w0v[17] <= _T_273 @[dec_gpr_ctl.scala 52:28] + node _T_274 = eq(io.waddr1, UInt<5>("h011")) @[dec_gpr_ctl.scala 53:52] + node _T_275 = and(io.wen1, _T_274) @[dec_gpr_ctl.scala 53:40] + w1v[17] <= _T_275 @[dec_gpr_ctl.scala 53:28] + node _T_276 = eq(io.waddr2, UInt<5>("h011")) @[dec_gpr_ctl.scala 54:52] + node _T_277 = and(io.wen2, _T_276) @[dec_gpr_ctl.scala 54:40] + w2v[17] <= _T_277 @[dec_gpr_ctl.scala 54:28] + node _T_278 = bits(w0v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_279 = mux(_T_278, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_280 = and(_T_279, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_281 = bits(w1v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_282 = mux(_T_281, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_283 = and(_T_282, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_284 = or(_T_280, _T_283) @[dec_gpr_ctl.scala 55:59] + node _T_285 = bits(w2v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_286 = mux(_T_285, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_287 = and(_T_286, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_288 = or(_T_284, _T_287) @[dec_gpr_ctl.scala 55:88] + gpr_in[17] <= _T_288 @[dec_gpr_ctl.scala 55:28] + node _T_289 = eq(io.waddr0, UInt<5>("h012")) @[dec_gpr_ctl.scala 52:52] + node _T_290 = and(io.wen0, _T_289) @[dec_gpr_ctl.scala 52:40] + w0v[18] <= _T_290 @[dec_gpr_ctl.scala 52:28] + node _T_291 = eq(io.waddr1, UInt<5>("h012")) @[dec_gpr_ctl.scala 53:52] + node _T_292 = and(io.wen1, _T_291) @[dec_gpr_ctl.scala 53:40] + w1v[18] <= _T_292 @[dec_gpr_ctl.scala 53:28] + node _T_293 = eq(io.waddr2, UInt<5>("h012")) @[dec_gpr_ctl.scala 54:52] + node _T_294 = and(io.wen2, _T_293) @[dec_gpr_ctl.scala 54:40] + w2v[18] <= _T_294 @[dec_gpr_ctl.scala 54:28] + node _T_295 = bits(w0v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_296 = mux(_T_295, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_297 = and(_T_296, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_298 = bits(w1v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_299 = mux(_T_298, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_300 = and(_T_299, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_301 = or(_T_297, _T_300) @[dec_gpr_ctl.scala 55:59] + node _T_302 = bits(w2v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_303 = mux(_T_302, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_304 = and(_T_303, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_305 = or(_T_301, _T_304) @[dec_gpr_ctl.scala 55:88] + gpr_in[18] <= _T_305 @[dec_gpr_ctl.scala 55:28] + node _T_306 = eq(io.waddr0, UInt<5>("h013")) @[dec_gpr_ctl.scala 52:52] + node _T_307 = and(io.wen0, _T_306) @[dec_gpr_ctl.scala 52:40] + w0v[19] <= _T_307 @[dec_gpr_ctl.scala 52:28] + node _T_308 = eq(io.waddr1, UInt<5>("h013")) @[dec_gpr_ctl.scala 53:52] + node _T_309 = and(io.wen1, _T_308) @[dec_gpr_ctl.scala 53:40] + w1v[19] <= _T_309 @[dec_gpr_ctl.scala 53:28] + node _T_310 = eq(io.waddr2, UInt<5>("h013")) @[dec_gpr_ctl.scala 54:52] + node _T_311 = and(io.wen2, _T_310) @[dec_gpr_ctl.scala 54:40] + w2v[19] <= _T_311 @[dec_gpr_ctl.scala 54:28] + node _T_312 = bits(w0v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_313 = mux(_T_312, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_314 = and(_T_313, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_315 = bits(w1v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_316 = mux(_T_315, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_317 = and(_T_316, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_318 = or(_T_314, _T_317) @[dec_gpr_ctl.scala 55:59] + node _T_319 = bits(w2v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_320 = mux(_T_319, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_321 = and(_T_320, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_322 = or(_T_318, _T_321) @[dec_gpr_ctl.scala 55:88] + gpr_in[19] <= _T_322 @[dec_gpr_ctl.scala 55:28] + node _T_323 = eq(io.waddr0, UInt<5>("h014")) @[dec_gpr_ctl.scala 52:52] + node _T_324 = and(io.wen0, _T_323) @[dec_gpr_ctl.scala 52:40] + w0v[20] <= _T_324 @[dec_gpr_ctl.scala 52:28] + node _T_325 = eq(io.waddr1, UInt<5>("h014")) @[dec_gpr_ctl.scala 53:52] + node _T_326 = and(io.wen1, _T_325) @[dec_gpr_ctl.scala 53:40] + w1v[20] <= _T_326 @[dec_gpr_ctl.scala 53:28] + node _T_327 = eq(io.waddr2, UInt<5>("h014")) @[dec_gpr_ctl.scala 54:52] + node _T_328 = and(io.wen2, _T_327) @[dec_gpr_ctl.scala 54:40] + w2v[20] <= _T_328 @[dec_gpr_ctl.scala 54:28] + node _T_329 = bits(w0v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_330 = mux(_T_329, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_331 = and(_T_330, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_332 = bits(w1v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_333 = mux(_T_332, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_334 = and(_T_333, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_335 = or(_T_331, _T_334) @[dec_gpr_ctl.scala 55:59] + node _T_336 = bits(w2v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_337 = mux(_T_336, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_338 = and(_T_337, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_339 = or(_T_335, _T_338) @[dec_gpr_ctl.scala 55:88] + gpr_in[20] <= _T_339 @[dec_gpr_ctl.scala 55:28] + node _T_340 = eq(io.waddr0, UInt<5>("h015")) @[dec_gpr_ctl.scala 52:52] + node _T_341 = and(io.wen0, _T_340) @[dec_gpr_ctl.scala 52:40] + w0v[21] <= _T_341 @[dec_gpr_ctl.scala 52:28] + node _T_342 = eq(io.waddr1, UInt<5>("h015")) @[dec_gpr_ctl.scala 53:52] + node _T_343 = and(io.wen1, _T_342) @[dec_gpr_ctl.scala 53:40] + w1v[21] <= _T_343 @[dec_gpr_ctl.scala 53:28] + node _T_344 = eq(io.waddr2, UInt<5>("h015")) @[dec_gpr_ctl.scala 54:52] + node _T_345 = and(io.wen2, _T_344) @[dec_gpr_ctl.scala 54:40] + w2v[21] <= _T_345 @[dec_gpr_ctl.scala 54:28] + node _T_346 = bits(w0v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_347 = mux(_T_346, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_348 = and(_T_347, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_349 = bits(w1v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_350 = mux(_T_349, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_351 = and(_T_350, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_352 = or(_T_348, _T_351) @[dec_gpr_ctl.scala 55:59] + node _T_353 = bits(w2v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_354 = mux(_T_353, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_355 = and(_T_354, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_356 = or(_T_352, _T_355) @[dec_gpr_ctl.scala 55:88] + gpr_in[21] <= _T_356 @[dec_gpr_ctl.scala 55:28] + node _T_357 = eq(io.waddr0, UInt<5>("h016")) @[dec_gpr_ctl.scala 52:52] + node _T_358 = and(io.wen0, _T_357) @[dec_gpr_ctl.scala 52:40] + w0v[22] <= _T_358 @[dec_gpr_ctl.scala 52:28] + node _T_359 = eq(io.waddr1, UInt<5>("h016")) @[dec_gpr_ctl.scala 53:52] + node _T_360 = and(io.wen1, _T_359) @[dec_gpr_ctl.scala 53:40] + w1v[22] <= _T_360 @[dec_gpr_ctl.scala 53:28] + node _T_361 = eq(io.waddr2, UInt<5>("h016")) @[dec_gpr_ctl.scala 54:52] + node _T_362 = and(io.wen2, _T_361) @[dec_gpr_ctl.scala 54:40] + w2v[22] <= _T_362 @[dec_gpr_ctl.scala 54:28] + node _T_363 = bits(w0v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_364 = mux(_T_363, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_365 = and(_T_364, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_366 = bits(w1v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_367 = mux(_T_366, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_368 = and(_T_367, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_369 = or(_T_365, _T_368) @[dec_gpr_ctl.scala 55:59] + node _T_370 = bits(w2v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_371 = mux(_T_370, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_372 = and(_T_371, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_373 = or(_T_369, _T_372) @[dec_gpr_ctl.scala 55:88] + gpr_in[22] <= _T_373 @[dec_gpr_ctl.scala 55:28] + node _T_374 = eq(io.waddr0, UInt<5>("h017")) @[dec_gpr_ctl.scala 52:52] + node _T_375 = and(io.wen0, _T_374) @[dec_gpr_ctl.scala 52:40] + w0v[23] <= _T_375 @[dec_gpr_ctl.scala 52:28] + node _T_376 = eq(io.waddr1, UInt<5>("h017")) @[dec_gpr_ctl.scala 53:52] + node _T_377 = and(io.wen1, _T_376) @[dec_gpr_ctl.scala 53:40] + w1v[23] <= _T_377 @[dec_gpr_ctl.scala 53:28] + node _T_378 = eq(io.waddr2, UInt<5>("h017")) @[dec_gpr_ctl.scala 54:52] + node _T_379 = and(io.wen2, _T_378) @[dec_gpr_ctl.scala 54:40] + w2v[23] <= _T_379 @[dec_gpr_ctl.scala 54:28] + node _T_380 = bits(w0v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_381 = mux(_T_380, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_382 = and(_T_381, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_383 = bits(w1v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_384 = mux(_T_383, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_385 = and(_T_384, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_386 = or(_T_382, _T_385) @[dec_gpr_ctl.scala 55:59] + node _T_387 = bits(w2v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_388 = mux(_T_387, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_389 = and(_T_388, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_390 = or(_T_386, _T_389) @[dec_gpr_ctl.scala 55:88] + gpr_in[23] <= _T_390 @[dec_gpr_ctl.scala 55:28] + node _T_391 = eq(io.waddr0, UInt<5>("h018")) @[dec_gpr_ctl.scala 52:52] + node _T_392 = and(io.wen0, _T_391) @[dec_gpr_ctl.scala 52:40] + w0v[24] <= _T_392 @[dec_gpr_ctl.scala 52:28] + node _T_393 = eq(io.waddr1, UInt<5>("h018")) @[dec_gpr_ctl.scala 53:52] + node _T_394 = and(io.wen1, _T_393) @[dec_gpr_ctl.scala 53:40] + w1v[24] <= _T_394 @[dec_gpr_ctl.scala 53:28] + node _T_395 = eq(io.waddr2, UInt<5>("h018")) @[dec_gpr_ctl.scala 54:52] + node _T_396 = and(io.wen2, _T_395) @[dec_gpr_ctl.scala 54:40] + w2v[24] <= _T_396 @[dec_gpr_ctl.scala 54:28] + node _T_397 = bits(w0v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_398 = mux(_T_397, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_399 = and(_T_398, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_400 = bits(w1v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_401 = mux(_T_400, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_402 = and(_T_401, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_403 = or(_T_399, _T_402) @[dec_gpr_ctl.scala 55:59] + node _T_404 = bits(w2v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_405 = mux(_T_404, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_406 = and(_T_405, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_407 = or(_T_403, _T_406) @[dec_gpr_ctl.scala 55:88] + gpr_in[24] <= _T_407 @[dec_gpr_ctl.scala 55:28] + node _T_408 = eq(io.waddr0, UInt<5>("h019")) @[dec_gpr_ctl.scala 52:52] + node _T_409 = and(io.wen0, _T_408) @[dec_gpr_ctl.scala 52:40] + w0v[25] <= _T_409 @[dec_gpr_ctl.scala 52:28] + node _T_410 = eq(io.waddr1, UInt<5>("h019")) @[dec_gpr_ctl.scala 53:52] + node _T_411 = and(io.wen1, _T_410) @[dec_gpr_ctl.scala 53:40] + w1v[25] <= _T_411 @[dec_gpr_ctl.scala 53:28] + node _T_412 = eq(io.waddr2, UInt<5>("h019")) @[dec_gpr_ctl.scala 54:52] + node _T_413 = and(io.wen2, _T_412) @[dec_gpr_ctl.scala 54:40] + w2v[25] <= _T_413 @[dec_gpr_ctl.scala 54:28] + node _T_414 = bits(w0v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_415 = mux(_T_414, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_416 = and(_T_415, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_417 = bits(w1v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_418 = mux(_T_417, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_419 = and(_T_418, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_420 = or(_T_416, _T_419) @[dec_gpr_ctl.scala 55:59] + node _T_421 = bits(w2v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_422 = mux(_T_421, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_423 = and(_T_422, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_424 = or(_T_420, _T_423) @[dec_gpr_ctl.scala 55:88] + gpr_in[25] <= _T_424 @[dec_gpr_ctl.scala 55:28] + node _T_425 = eq(io.waddr0, UInt<5>("h01a")) @[dec_gpr_ctl.scala 52:52] + node _T_426 = and(io.wen0, _T_425) @[dec_gpr_ctl.scala 52:40] + w0v[26] <= _T_426 @[dec_gpr_ctl.scala 52:28] + node _T_427 = eq(io.waddr1, UInt<5>("h01a")) @[dec_gpr_ctl.scala 53:52] + node _T_428 = and(io.wen1, _T_427) @[dec_gpr_ctl.scala 53:40] + w1v[26] <= _T_428 @[dec_gpr_ctl.scala 53:28] + node _T_429 = eq(io.waddr2, UInt<5>("h01a")) @[dec_gpr_ctl.scala 54:52] + node _T_430 = and(io.wen2, _T_429) @[dec_gpr_ctl.scala 54:40] + w2v[26] <= _T_430 @[dec_gpr_ctl.scala 54:28] + node _T_431 = bits(w0v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_432 = mux(_T_431, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_433 = and(_T_432, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_434 = bits(w1v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_435 = mux(_T_434, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_436 = and(_T_435, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_437 = or(_T_433, _T_436) @[dec_gpr_ctl.scala 55:59] + node _T_438 = bits(w2v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_439 = mux(_T_438, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_440 = and(_T_439, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_441 = or(_T_437, _T_440) @[dec_gpr_ctl.scala 55:88] + gpr_in[26] <= _T_441 @[dec_gpr_ctl.scala 55:28] + node _T_442 = eq(io.waddr0, UInt<5>("h01b")) @[dec_gpr_ctl.scala 52:52] + node _T_443 = and(io.wen0, _T_442) @[dec_gpr_ctl.scala 52:40] + w0v[27] <= _T_443 @[dec_gpr_ctl.scala 52:28] + node _T_444 = eq(io.waddr1, UInt<5>("h01b")) @[dec_gpr_ctl.scala 53:52] + node _T_445 = and(io.wen1, _T_444) @[dec_gpr_ctl.scala 53:40] + w1v[27] <= _T_445 @[dec_gpr_ctl.scala 53:28] + node _T_446 = eq(io.waddr2, UInt<5>("h01b")) @[dec_gpr_ctl.scala 54:52] + node _T_447 = and(io.wen2, _T_446) @[dec_gpr_ctl.scala 54:40] + w2v[27] <= _T_447 @[dec_gpr_ctl.scala 54:28] + node _T_448 = bits(w0v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_449 = mux(_T_448, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_450 = and(_T_449, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_451 = bits(w1v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_452 = mux(_T_451, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_453 = and(_T_452, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_454 = or(_T_450, _T_453) @[dec_gpr_ctl.scala 55:59] + node _T_455 = bits(w2v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_456 = mux(_T_455, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_457 = and(_T_456, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_458 = or(_T_454, _T_457) @[dec_gpr_ctl.scala 55:88] + gpr_in[27] <= _T_458 @[dec_gpr_ctl.scala 55:28] + node _T_459 = eq(io.waddr0, UInt<5>("h01c")) @[dec_gpr_ctl.scala 52:52] + node _T_460 = and(io.wen0, _T_459) @[dec_gpr_ctl.scala 52:40] + w0v[28] <= _T_460 @[dec_gpr_ctl.scala 52:28] + node _T_461 = eq(io.waddr1, UInt<5>("h01c")) @[dec_gpr_ctl.scala 53:52] + node _T_462 = and(io.wen1, _T_461) @[dec_gpr_ctl.scala 53:40] + w1v[28] <= _T_462 @[dec_gpr_ctl.scala 53:28] + node _T_463 = eq(io.waddr2, UInt<5>("h01c")) @[dec_gpr_ctl.scala 54:52] + node _T_464 = and(io.wen2, _T_463) @[dec_gpr_ctl.scala 54:40] + w2v[28] <= _T_464 @[dec_gpr_ctl.scala 54:28] + node _T_465 = bits(w0v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_466 = mux(_T_465, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_467 = and(_T_466, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_468 = bits(w1v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_469 = mux(_T_468, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_470 = and(_T_469, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_471 = or(_T_467, _T_470) @[dec_gpr_ctl.scala 55:59] + node _T_472 = bits(w2v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_473 = mux(_T_472, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_474 = and(_T_473, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_475 = or(_T_471, _T_474) @[dec_gpr_ctl.scala 55:88] + gpr_in[28] <= _T_475 @[dec_gpr_ctl.scala 55:28] + node _T_476 = eq(io.waddr0, UInt<5>("h01d")) @[dec_gpr_ctl.scala 52:52] + node _T_477 = and(io.wen0, _T_476) @[dec_gpr_ctl.scala 52:40] + w0v[29] <= _T_477 @[dec_gpr_ctl.scala 52:28] + node _T_478 = eq(io.waddr1, UInt<5>("h01d")) @[dec_gpr_ctl.scala 53:52] + node _T_479 = and(io.wen1, _T_478) @[dec_gpr_ctl.scala 53:40] + w1v[29] <= _T_479 @[dec_gpr_ctl.scala 53:28] + node _T_480 = eq(io.waddr2, UInt<5>("h01d")) @[dec_gpr_ctl.scala 54:52] + node _T_481 = and(io.wen2, _T_480) @[dec_gpr_ctl.scala 54:40] + w2v[29] <= _T_481 @[dec_gpr_ctl.scala 54:28] + node _T_482 = bits(w0v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_483 = mux(_T_482, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_484 = and(_T_483, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_485 = bits(w1v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_486 = mux(_T_485, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_487 = and(_T_486, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_488 = or(_T_484, _T_487) @[dec_gpr_ctl.scala 55:59] + node _T_489 = bits(w2v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_490 = mux(_T_489, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_491 = and(_T_490, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_492 = or(_T_488, _T_491) @[dec_gpr_ctl.scala 55:88] + gpr_in[29] <= _T_492 @[dec_gpr_ctl.scala 55:28] + node _T_493 = eq(io.waddr0, UInt<5>("h01e")) @[dec_gpr_ctl.scala 52:52] + node _T_494 = and(io.wen0, _T_493) @[dec_gpr_ctl.scala 52:40] + w0v[30] <= _T_494 @[dec_gpr_ctl.scala 52:28] + node _T_495 = eq(io.waddr1, UInt<5>("h01e")) @[dec_gpr_ctl.scala 53:52] + node _T_496 = and(io.wen1, _T_495) @[dec_gpr_ctl.scala 53:40] + w1v[30] <= _T_496 @[dec_gpr_ctl.scala 53:28] + node _T_497 = eq(io.waddr2, UInt<5>("h01e")) @[dec_gpr_ctl.scala 54:52] + node _T_498 = and(io.wen2, _T_497) @[dec_gpr_ctl.scala 54:40] + w2v[30] <= _T_498 @[dec_gpr_ctl.scala 54:28] + node _T_499 = bits(w0v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_500 = mux(_T_499, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_501 = and(_T_500, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_502 = bits(w1v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_503 = mux(_T_502, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_504 = and(_T_503, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_505 = or(_T_501, _T_504) @[dec_gpr_ctl.scala 55:59] + node _T_506 = bits(w2v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_507 = mux(_T_506, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_508 = and(_T_507, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_509 = or(_T_505, _T_508) @[dec_gpr_ctl.scala 55:88] + gpr_in[30] <= _T_509 @[dec_gpr_ctl.scala 55:28] + node _T_510 = eq(io.waddr0, UInt<5>("h01f")) @[dec_gpr_ctl.scala 52:52] + node _T_511 = and(io.wen0, _T_510) @[dec_gpr_ctl.scala 52:40] + w0v[31] <= _T_511 @[dec_gpr_ctl.scala 52:28] + node _T_512 = eq(io.waddr1, UInt<5>("h01f")) @[dec_gpr_ctl.scala 53:52] + node _T_513 = and(io.wen1, _T_512) @[dec_gpr_ctl.scala 53:40] + w1v[31] <= _T_513 @[dec_gpr_ctl.scala 53:28] + node _T_514 = eq(io.waddr2, UInt<5>("h01f")) @[dec_gpr_ctl.scala 54:52] + node _T_515 = and(io.wen2, _T_514) @[dec_gpr_ctl.scala 54:40] + w2v[31] <= _T_515 @[dec_gpr_ctl.scala 54:28] + node _T_516 = bits(w0v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_517 = mux(_T_516, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_518 = and(_T_517, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_519 = bits(w1v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_520 = mux(_T_519, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_521 = and(_T_520, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_522 = or(_T_518, _T_521) @[dec_gpr_ctl.scala 55:59] + node _T_523 = bits(w2v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_524 = mux(_T_523, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_525 = and(_T_524, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_526 = or(_T_522, _T_525) @[dec_gpr_ctl.scala 55:88] + gpr_in[31] <= _T_526 @[dec_gpr_ctl.scala 55:28] + node _T_527 = cat(w0v[1], w0v[0]) @[Cat.scala 29:58] + node _T_528 = cat(w0v[2], _T_527) @[Cat.scala 29:58] + node _T_529 = cat(w0v[3], _T_528) @[Cat.scala 29:58] + node _T_530 = cat(w0v[4], _T_529) @[Cat.scala 29:58] + node _T_531 = cat(w0v[5], _T_530) @[Cat.scala 29:58] + node _T_532 = cat(w0v[6], _T_531) @[Cat.scala 29:58] + node _T_533 = cat(w0v[7], _T_532) @[Cat.scala 29:58] + node _T_534 = cat(w0v[8], _T_533) @[Cat.scala 29:58] + node _T_535 = cat(w0v[9], _T_534) @[Cat.scala 29:58] + node _T_536 = cat(w0v[10], _T_535) @[Cat.scala 29:58] + node _T_537 = cat(w0v[11], _T_536) @[Cat.scala 29:58] + node _T_538 = cat(w0v[12], _T_537) @[Cat.scala 29:58] + node _T_539 = cat(w0v[13], _T_538) @[Cat.scala 29:58] + node _T_540 = cat(w0v[14], _T_539) @[Cat.scala 29:58] + node _T_541 = cat(w0v[15], _T_540) @[Cat.scala 29:58] + node _T_542 = cat(w0v[16], _T_541) @[Cat.scala 29:58] + node _T_543 = cat(w0v[17], _T_542) @[Cat.scala 29:58] + node _T_544 = cat(w0v[18], _T_543) @[Cat.scala 29:58] + node _T_545 = cat(w0v[19], _T_544) @[Cat.scala 29:58] + node _T_546 = cat(w0v[20], _T_545) @[Cat.scala 29:58] + node _T_547 = cat(w0v[21], _T_546) @[Cat.scala 29:58] + node _T_548 = cat(w0v[22], _T_547) @[Cat.scala 29:58] + node _T_549 = cat(w0v[23], _T_548) @[Cat.scala 29:58] + node _T_550 = cat(w0v[24], _T_549) @[Cat.scala 29:58] + node _T_551 = cat(w0v[25], _T_550) @[Cat.scala 29:58] + node _T_552 = cat(w0v[26], _T_551) @[Cat.scala 29:58] + node _T_553 = cat(w0v[27], _T_552) @[Cat.scala 29:58] + node _T_554 = cat(w0v[28], _T_553) @[Cat.scala 29:58] + node _T_555 = cat(w0v[29], _T_554) @[Cat.scala 29:58] + node _T_556 = cat(w0v[30], _T_555) @[Cat.scala 29:58] + node _T_557 = cat(w0v[31], _T_556) @[Cat.scala 29:58] + node _T_558 = cat(w1v[1], w1v[0]) @[Cat.scala 29:58] + node _T_559 = cat(w1v[2], _T_558) @[Cat.scala 29:58] + node _T_560 = cat(w1v[3], _T_559) @[Cat.scala 29:58] + node _T_561 = cat(w1v[4], _T_560) @[Cat.scala 29:58] + node _T_562 = cat(w1v[5], _T_561) @[Cat.scala 29:58] + node _T_563 = cat(w1v[6], _T_562) @[Cat.scala 29:58] + node _T_564 = cat(w1v[7], _T_563) @[Cat.scala 29:58] + node _T_565 = cat(w1v[8], _T_564) @[Cat.scala 29:58] + node _T_566 = cat(w1v[9], _T_565) @[Cat.scala 29:58] + node _T_567 = cat(w1v[10], _T_566) @[Cat.scala 29:58] + node _T_568 = cat(w1v[11], _T_567) @[Cat.scala 29:58] + node _T_569 = cat(w1v[12], _T_568) @[Cat.scala 29:58] + node _T_570 = cat(w1v[13], _T_569) @[Cat.scala 29:58] + node _T_571 = cat(w1v[14], _T_570) @[Cat.scala 29:58] + node _T_572 = cat(w1v[15], _T_571) @[Cat.scala 29:58] + node _T_573 = cat(w1v[16], _T_572) @[Cat.scala 29:58] + node _T_574 = cat(w1v[17], _T_573) @[Cat.scala 29:58] + node _T_575 = cat(w1v[18], _T_574) @[Cat.scala 29:58] + node _T_576 = cat(w1v[19], _T_575) @[Cat.scala 29:58] + node _T_577 = cat(w1v[20], _T_576) @[Cat.scala 29:58] + node _T_578 = cat(w1v[21], _T_577) @[Cat.scala 29:58] + node _T_579 = cat(w1v[22], _T_578) @[Cat.scala 29:58] + node _T_580 = cat(w1v[23], _T_579) @[Cat.scala 29:58] + node _T_581 = cat(w1v[24], _T_580) @[Cat.scala 29:58] + node _T_582 = cat(w1v[25], _T_581) @[Cat.scala 29:58] + node _T_583 = cat(w1v[26], _T_582) @[Cat.scala 29:58] + node _T_584 = cat(w1v[27], _T_583) @[Cat.scala 29:58] + node _T_585 = cat(w1v[28], _T_584) @[Cat.scala 29:58] + node _T_586 = cat(w1v[29], _T_585) @[Cat.scala 29:58] + node _T_587 = cat(w1v[30], _T_586) @[Cat.scala 29:58] + node _T_588 = cat(w1v[31], _T_587) @[Cat.scala 29:58] + node _T_589 = or(_T_557, _T_588) @[dec_gpr_ctl.scala 57:57] + node _T_590 = cat(w2v[1], w2v[0]) @[Cat.scala 29:58] + node _T_591 = cat(w2v[2], _T_590) @[Cat.scala 29:58] + node _T_592 = cat(w2v[3], _T_591) @[Cat.scala 29:58] + node _T_593 = cat(w2v[4], _T_592) @[Cat.scala 29:58] + node _T_594 = cat(w2v[5], _T_593) @[Cat.scala 29:58] + node _T_595 = cat(w2v[6], _T_594) @[Cat.scala 29:58] + node _T_596 = cat(w2v[7], _T_595) @[Cat.scala 29:58] + node _T_597 = cat(w2v[8], _T_596) @[Cat.scala 29:58] + node _T_598 = cat(w2v[9], _T_597) @[Cat.scala 29:58] + node _T_599 = cat(w2v[10], _T_598) @[Cat.scala 29:58] + node _T_600 = cat(w2v[11], _T_599) @[Cat.scala 29:58] + node _T_601 = cat(w2v[12], _T_600) @[Cat.scala 29:58] + node _T_602 = cat(w2v[13], _T_601) @[Cat.scala 29:58] + node _T_603 = cat(w2v[14], _T_602) @[Cat.scala 29:58] + node _T_604 = cat(w2v[15], _T_603) @[Cat.scala 29:58] + node _T_605 = cat(w2v[16], _T_604) @[Cat.scala 29:58] + node _T_606 = cat(w2v[17], _T_605) @[Cat.scala 29:58] + node _T_607 = cat(w2v[18], _T_606) @[Cat.scala 29:58] + node _T_608 = cat(w2v[19], _T_607) @[Cat.scala 29:58] + node _T_609 = cat(w2v[20], _T_608) @[Cat.scala 29:58] + node _T_610 = cat(w2v[21], _T_609) @[Cat.scala 29:58] + node _T_611 = cat(w2v[22], _T_610) @[Cat.scala 29:58] + node _T_612 = cat(w2v[23], _T_611) @[Cat.scala 29:58] + node _T_613 = cat(w2v[24], _T_612) @[Cat.scala 29:58] + node _T_614 = cat(w2v[25], _T_613) @[Cat.scala 29:58] + node _T_615 = cat(w2v[26], _T_614) @[Cat.scala 29:58] + node _T_616 = cat(w2v[27], _T_615) @[Cat.scala 29:58] + node _T_617 = cat(w2v[28], _T_616) @[Cat.scala 29:58] + node _T_618 = cat(w2v[29], _T_617) @[Cat.scala 29:58] + node _T_619 = cat(w2v[30], _T_618) @[Cat.scala 29:58] + node _T_620 = cat(w2v[31], _T_619) @[Cat.scala 29:58] + node _T_621 = or(_T_589, _T_620) @[dec_gpr_ctl.scala 57:95] + gpr_wr_en <= _T_621 @[dec_gpr_ctl.scala 57:18] + node _T_622 = bits(gpr_wr_en, 1, 1) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr of rvclkhdr_11 @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= _T_622 @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_623 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_622 : @[Reg.scala 28:19] + _T_623 <= gpr_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[1] <= _T_623 @[dec_gpr_ctl.scala 61:27] + node _T_624 = bits(gpr_wr_en, 2, 2) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_1 of rvclkhdr_12 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_624 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_625 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_624 : @[Reg.scala 28:19] + _T_625 <= gpr_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[2] <= _T_625 @[dec_gpr_ctl.scala 61:27] + node _T_626 = bits(gpr_wr_en, 3, 3) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_2 of rvclkhdr_13 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_2.io.en <= _T_626 @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_627 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_626 : @[Reg.scala 28:19] + _T_627 <= gpr_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[3] <= _T_627 @[dec_gpr_ctl.scala 61:27] + node _T_628 = bits(gpr_wr_en, 4, 4) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_3 of rvclkhdr_14 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= _T_628 @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_629 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_628 : @[Reg.scala 28:19] + _T_629 <= gpr_in[4] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[4] <= _T_629 @[dec_gpr_ctl.scala 61:27] + node _T_630 = bits(gpr_wr_en, 5, 5) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_4 of rvclkhdr_15 @[lib.scala 404:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_4.io.en <= _T_630 @[lib.scala 407:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_631 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_630 : @[Reg.scala 28:19] + _T_631 <= gpr_in[5] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[5] <= _T_631 @[dec_gpr_ctl.scala 61:27] + node _T_632 = bits(gpr_wr_en, 6, 6) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_5 of rvclkhdr_16 @[lib.scala 404:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_5.io.en <= _T_632 @[lib.scala 407:17] + rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_633 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_632 : @[Reg.scala 28:19] + _T_633 <= gpr_in[6] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[6] <= _T_633 @[dec_gpr_ctl.scala 61:27] + node _T_634 = bits(gpr_wr_en, 7, 7) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_6 of rvclkhdr_17 @[lib.scala 404:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_6.io.en <= _T_634 @[lib.scala 407:17] + rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_635 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_634 : @[Reg.scala 28:19] + _T_635 <= gpr_in[7] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[7] <= _T_635 @[dec_gpr_ctl.scala 61:27] + node _T_636 = bits(gpr_wr_en, 8, 8) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_7 of rvclkhdr_18 @[lib.scala 404:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_7.io.en <= _T_636 @[lib.scala 407:17] + rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_637 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_636 : @[Reg.scala 28:19] + _T_637 <= gpr_in[8] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[8] <= _T_637 @[dec_gpr_ctl.scala 61:27] + node _T_638 = bits(gpr_wr_en, 9, 9) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_8 of rvclkhdr_19 @[lib.scala 404:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_8.io.en <= _T_638 @[lib.scala 407:17] + rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_639 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_638 : @[Reg.scala 28:19] + _T_639 <= gpr_in[9] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[9] <= _T_639 @[dec_gpr_ctl.scala 61:27] + node _T_640 = bits(gpr_wr_en, 10, 10) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_9 of rvclkhdr_20 @[lib.scala 404:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_9.io.en <= _T_640 @[lib.scala 407:17] + rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_641 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_640 : @[Reg.scala 28:19] + _T_641 <= gpr_in[10] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[10] <= _T_641 @[dec_gpr_ctl.scala 61:27] + node _T_642 = bits(gpr_wr_en, 11, 11) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_10 of rvclkhdr_21 @[lib.scala 404:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_10.io.en <= _T_642 @[lib.scala 407:17] + rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_643 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_642 : @[Reg.scala 28:19] + _T_643 <= gpr_in[11] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[11] <= _T_643 @[dec_gpr_ctl.scala 61:27] + node _T_644 = bits(gpr_wr_en, 12, 12) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_11 of rvclkhdr_22 @[lib.scala 404:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_11.io.en <= _T_644 @[lib.scala 407:17] + rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_645 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_644 : @[Reg.scala 28:19] + _T_645 <= gpr_in[12] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[12] <= _T_645 @[dec_gpr_ctl.scala 61:27] + node _T_646 = bits(gpr_wr_en, 13, 13) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_12 of rvclkhdr_23 @[lib.scala 404:23] + rvclkhdr_12.clock <= clock + rvclkhdr_12.reset <= reset + rvclkhdr_12.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_12.io.en <= _T_646 @[lib.scala 407:17] + rvclkhdr_12.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_647 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_646 : @[Reg.scala 28:19] + _T_647 <= gpr_in[13] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[13] <= _T_647 @[dec_gpr_ctl.scala 61:27] + node _T_648 = bits(gpr_wr_en, 14, 14) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_13 of rvclkhdr_24 @[lib.scala 404:23] + rvclkhdr_13.clock <= clock + rvclkhdr_13.reset <= reset + rvclkhdr_13.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_13.io.en <= _T_648 @[lib.scala 407:17] + rvclkhdr_13.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_649 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_648 : @[Reg.scala 28:19] + _T_649 <= gpr_in[14] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[14] <= _T_649 @[dec_gpr_ctl.scala 61:27] + node _T_650 = bits(gpr_wr_en, 15, 15) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_14 of rvclkhdr_25 @[lib.scala 404:23] + rvclkhdr_14.clock <= clock + rvclkhdr_14.reset <= reset + rvclkhdr_14.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_14.io.en <= _T_650 @[lib.scala 407:17] + rvclkhdr_14.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_651 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_650 : @[Reg.scala 28:19] + _T_651 <= gpr_in[15] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[15] <= _T_651 @[dec_gpr_ctl.scala 61:27] + node _T_652 = bits(gpr_wr_en, 16, 16) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_15 of rvclkhdr_26 @[lib.scala 404:23] + rvclkhdr_15.clock <= clock + rvclkhdr_15.reset <= reset + rvclkhdr_15.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_15.io.en <= _T_652 @[lib.scala 407:17] + rvclkhdr_15.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_653 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_652 : @[Reg.scala 28:19] + _T_653 <= gpr_in[16] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[16] <= _T_653 @[dec_gpr_ctl.scala 61:27] + node _T_654 = bits(gpr_wr_en, 17, 17) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_16 of rvclkhdr_27 @[lib.scala 404:23] + rvclkhdr_16.clock <= clock + rvclkhdr_16.reset <= reset + rvclkhdr_16.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_16.io.en <= _T_654 @[lib.scala 407:17] + rvclkhdr_16.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_655 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_654 : @[Reg.scala 28:19] + _T_655 <= gpr_in[17] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[17] <= _T_655 @[dec_gpr_ctl.scala 61:27] + node _T_656 = bits(gpr_wr_en, 18, 18) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_17 of rvclkhdr_28 @[lib.scala 404:23] + rvclkhdr_17.clock <= clock + rvclkhdr_17.reset <= reset + rvclkhdr_17.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_17.io.en <= _T_656 @[lib.scala 407:17] + rvclkhdr_17.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_657 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_656 : @[Reg.scala 28:19] + _T_657 <= gpr_in[18] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[18] <= _T_657 @[dec_gpr_ctl.scala 61:27] + node _T_658 = bits(gpr_wr_en, 19, 19) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_18 of rvclkhdr_29 @[lib.scala 404:23] + rvclkhdr_18.clock <= clock + rvclkhdr_18.reset <= reset + rvclkhdr_18.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_18.io.en <= _T_658 @[lib.scala 407:17] + rvclkhdr_18.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_659 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_658 : @[Reg.scala 28:19] + _T_659 <= gpr_in[19] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[19] <= _T_659 @[dec_gpr_ctl.scala 61:27] + node _T_660 = bits(gpr_wr_en, 20, 20) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_19 of rvclkhdr_30 @[lib.scala 404:23] + rvclkhdr_19.clock <= clock + rvclkhdr_19.reset <= reset + rvclkhdr_19.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_19.io.en <= _T_660 @[lib.scala 407:17] + rvclkhdr_19.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_661 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_660 : @[Reg.scala 28:19] + _T_661 <= gpr_in[20] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[20] <= _T_661 @[dec_gpr_ctl.scala 61:27] + node _T_662 = bits(gpr_wr_en, 21, 21) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_20 of rvclkhdr_31 @[lib.scala 404:23] + rvclkhdr_20.clock <= clock + rvclkhdr_20.reset <= reset + rvclkhdr_20.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_20.io.en <= _T_662 @[lib.scala 407:17] + rvclkhdr_20.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_663 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_662 : @[Reg.scala 28:19] + _T_663 <= gpr_in[21] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[21] <= _T_663 @[dec_gpr_ctl.scala 61:27] + node _T_664 = bits(gpr_wr_en, 22, 22) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_21 of rvclkhdr_32 @[lib.scala 404:23] + rvclkhdr_21.clock <= clock + rvclkhdr_21.reset <= reset + rvclkhdr_21.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_21.io.en <= _T_664 @[lib.scala 407:17] + rvclkhdr_21.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_665 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_664 : @[Reg.scala 28:19] + _T_665 <= gpr_in[22] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[22] <= _T_665 @[dec_gpr_ctl.scala 61:27] + node _T_666 = bits(gpr_wr_en, 23, 23) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_22 of rvclkhdr_33 @[lib.scala 404:23] + rvclkhdr_22.clock <= clock + rvclkhdr_22.reset <= reset + rvclkhdr_22.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_22.io.en <= _T_666 @[lib.scala 407:17] + rvclkhdr_22.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_667 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_666 : @[Reg.scala 28:19] + _T_667 <= gpr_in[23] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[23] <= _T_667 @[dec_gpr_ctl.scala 61:27] + node _T_668 = bits(gpr_wr_en, 24, 24) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_23 of rvclkhdr_34 @[lib.scala 404:23] + rvclkhdr_23.clock <= clock + rvclkhdr_23.reset <= reset + rvclkhdr_23.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_23.io.en <= _T_668 @[lib.scala 407:17] + rvclkhdr_23.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_669 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_668 : @[Reg.scala 28:19] + _T_669 <= gpr_in[24] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[24] <= _T_669 @[dec_gpr_ctl.scala 61:27] + node _T_670 = bits(gpr_wr_en, 25, 25) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_24 of rvclkhdr_35 @[lib.scala 404:23] + rvclkhdr_24.clock <= clock + rvclkhdr_24.reset <= reset + rvclkhdr_24.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_24.io.en <= _T_670 @[lib.scala 407:17] + rvclkhdr_24.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_671 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_670 : @[Reg.scala 28:19] + _T_671 <= gpr_in[25] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[25] <= _T_671 @[dec_gpr_ctl.scala 61:27] + node _T_672 = bits(gpr_wr_en, 26, 26) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_25 of rvclkhdr_36 @[lib.scala 404:23] + rvclkhdr_25.clock <= clock + rvclkhdr_25.reset <= reset + rvclkhdr_25.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_25.io.en <= _T_672 @[lib.scala 407:17] + rvclkhdr_25.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_673 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_672 : @[Reg.scala 28:19] + _T_673 <= gpr_in[26] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[26] <= _T_673 @[dec_gpr_ctl.scala 61:27] + node _T_674 = bits(gpr_wr_en, 27, 27) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_26 of rvclkhdr_37 @[lib.scala 404:23] + rvclkhdr_26.clock <= clock + rvclkhdr_26.reset <= reset + rvclkhdr_26.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_26.io.en <= _T_674 @[lib.scala 407:17] + rvclkhdr_26.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_675 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_674 : @[Reg.scala 28:19] + _T_675 <= gpr_in[27] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[27] <= _T_675 @[dec_gpr_ctl.scala 61:27] + node _T_676 = bits(gpr_wr_en, 28, 28) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_27 of rvclkhdr_38 @[lib.scala 404:23] + rvclkhdr_27.clock <= clock + rvclkhdr_27.reset <= reset + rvclkhdr_27.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_27.io.en <= _T_676 @[lib.scala 407:17] + rvclkhdr_27.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_677 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_676 : @[Reg.scala 28:19] + _T_677 <= gpr_in[28] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[28] <= _T_677 @[dec_gpr_ctl.scala 61:27] + node _T_678 = bits(gpr_wr_en, 29, 29) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_28 of rvclkhdr_39 @[lib.scala 404:23] + rvclkhdr_28.clock <= clock + rvclkhdr_28.reset <= reset + rvclkhdr_28.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_28.io.en <= _T_678 @[lib.scala 407:17] + rvclkhdr_28.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_679 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_678 : @[Reg.scala 28:19] + _T_679 <= gpr_in[29] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[29] <= _T_679 @[dec_gpr_ctl.scala 61:27] + node _T_680 = bits(gpr_wr_en, 30, 30) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_29 of rvclkhdr_40 @[lib.scala 404:23] + rvclkhdr_29.clock <= clock + rvclkhdr_29.reset <= reset + rvclkhdr_29.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_29.io.en <= _T_680 @[lib.scala 407:17] + rvclkhdr_29.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_681 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_680 : @[Reg.scala 28:19] + _T_681 <= gpr_in[30] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[30] <= _T_681 @[dec_gpr_ctl.scala 61:27] + node _T_682 = bits(gpr_wr_en, 31, 31) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_30 of rvclkhdr_41 @[lib.scala 404:23] + rvclkhdr_30.clock <= clock + rvclkhdr_30.reset <= reset + rvclkhdr_30.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_30.io.en <= _T_682 @[lib.scala 407:17] + rvclkhdr_30.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_683 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_682 : @[Reg.scala 28:19] + _T_683 <= gpr_in[31] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[31] <= _T_683 @[dec_gpr_ctl.scala 61:27] + node _T_684 = eq(io.raddr0, UInt<1>("h01")) @[dec_gpr_ctl.scala 64:72] + node _T_685 = bits(_T_684, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_686 = eq(io.raddr0, UInt<2>("h02")) @[dec_gpr_ctl.scala 64:72] + node _T_687 = bits(_T_686, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_688 = eq(io.raddr0, UInt<2>("h03")) @[dec_gpr_ctl.scala 64:72] + node _T_689 = bits(_T_688, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_690 = eq(io.raddr0, UInt<3>("h04")) @[dec_gpr_ctl.scala 64:72] + node _T_691 = bits(_T_690, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_692 = eq(io.raddr0, UInt<3>("h05")) @[dec_gpr_ctl.scala 64:72] + node _T_693 = bits(_T_692, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_694 = eq(io.raddr0, UInt<3>("h06")) @[dec_gpr_ctl.scala 64:72] + node _T_695 = bits(_T_694, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_696 = eq(io.raddr0, UInt<3>("h07")) @[dec_gpr_ctl.scala 64:72] + node _T_697 = bits(_T_696, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_698 = eq(io.raddr0, UInt<4>("h08")) @[dec_gpr_ctl.scala 64:72] + node _T_699 = bits(_T_698, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_700 = eq(io.raddr0, UInt<4>("h09")) @[dec_gpr_ctl.scala 64:72] + node _T_701 = bits(_T_700, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_702 = eq(io.raddr0, UInt<4>("h0a")) @[dec_gpr_ctl.scala 64:72] + node _T_703 = bits(_T_702, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_704 = eq(io.raddr0, UInt<4>("h0b")) @[dec_gpr_ctl.scala 64:72] + node _T_705 = bits(_T_704, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_706 = eq(io.raddr0, UInt<4>("h0c")) @[dec_gpr_ctl.scala 64:72] + node _T_707 = bits(_T_706, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_708 = eq(io.raddr0, UInt<4>("h0d")) @[dec_gpr_ctl.scala 64:72] + node _T_709 = bits(_T_708, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_710 = eq(io.raddr0, UInt<4>("h0e")) @[dec_gpr_ctl.scala 64:72] + node _T_711 = bits(_T_710, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_712 = eq(io.raddr0, UInt<4>("h0f")) @[dec_gpr_ctl.scala 64:72] + node _T_713 = bits(_T_712, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_714 = eq(io.raddr0, UInt<5>("h010")) @[dec_gpr_ctl.scala 64:72] + node _T_715 = bits(_T_714, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_716 = eq(io.raddr0, UInt<5>("h011")) @[dec_gpr_ctl.scala 64:72] + node _T_717 = bits(_T_716, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_718 = eq(io.raddr0, UInt<5>("h012")) @[dec_gpr_ctl.scala 64:72] + node _T_719 = bits(_T_718, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_720 = eq(io.raddr0, UInt<5>("h013")) @[dec_gpr_ctl.scala 64:72] + node _T_721 = bits(_T_720, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_722 = eq(io.raddr0, UInt<5>("h014")) @[dec_gpr_ctl.scala 64:72] + node _T_723 = bits(_T_722, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_724 = eq(io.raddr0, UInt<5>("h015")) @[dec_gpr_ctl.scala 64:72] + node _T_725 = bits(_T_724, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_726 = eq(io.raddr0, UInt<5>("h016")) @[dec_gpr_ctl.scala 64:72] + node _T_727 = bits(_T_726, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_728 = eq(io.raddr0, UInt<5>("h017")) @[dec_gpr_ctl.scala 64:72] + node _T_729 = bits(_T_728, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_730 = eq(io.raddr0, UInt<5>("h018")) @[dec_gpr_ctl.scala 64:72] + node _T_731 = bits(_T_730, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_732 = eq(io.raddr0, UInt<5>("h019")) @[dec_gpr_ctl.scala 64:72] + node _T_733 = bits(_T_732, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_734 = eq(io.raddr0, UInt<5>("h01a")) @[dec_gpr_ctl.scala 64:72] + node _T_735 = bits(_T_734, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_736 = eq(io.raddr0, UInt<5>("h01b")) @[dec_gpr_ctl.scala 64:72] + node _T_737 = bits(_T_736, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_738 = eq(io.raddr0, UInt<5>("h01c")) @[dec_gpr_ctl.scala 64:72] + node _T_739 = bits(_T_738, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_740 = eq(io.raddr0, UInt<5>("h01d")) @[dec_gpr_ctl.scala 64:72] + node _T_741 = bits(_T_740, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_742 = eq(io.raddr0, UInt<5>("h01e")) @[dec_gpr_ctl.scala 64:72] + node _T_743 = bits(_T_742, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_744 = eq(io.raddr0, UInt<5>("h01f")) @[dec_gpr_ctl.scala 64:72] + node _T_745 = bits(_T_744, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_746 = mux(_T_685, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_747 = mux(_T_687, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_748 = mux(_T_689, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_749 = mux(_T_691, gpr_out[4], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_750 = mux(_T_693, gpr_out[5], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_751 = mux(_T_695, gpr_out[6], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_752 = mux(_T_697, gpr_out[7], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_753 = mux(_T_699, gpr_out[8], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_754 = mux(_T_701, gpr_out[9], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_755 = mux(_T_703, gpr_out[10], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_756 = mux(_T_705, gpr_out[11], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_757 = mux(_T_707, gpr_out[12], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_758 = mux(_T_709, gpr_out[13], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_759 = mux(_T_711, gpr_out[14], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_760 = mux(_T_713, gpr_out[15], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_761 = mux(_T_715, gpr_out[16], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_762 = mux(_T_717, gpr_out[17], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_763 = mux(_T_719, gpr_out[18], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_764 = mux(_T_721, gpr_out[19], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_765 = mux(_T_723, gpr_out[20], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_766 = mux(_T_725, gpr_out[21], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_767 = mux(_T_727, gpr_out[22], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_768 = mux(_T_729, gpr_out[23], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_769 = mux(_T_731, gpr_out[24], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_770 = mux(_T_733, gpr_out[25], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_771 = mux(_T_735, gpr_out[26], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_772 = mux(_T_737, gpr_out[27], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_773 = mux(_T_739, gpr_out[28], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_774 = mux(_T_741, gpr_out[29], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_775 = mux(_T_743, gpr_out[30], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_776 = mux(_T_745, gpr_out[31], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_777 = or(_T_746, _T_747) @[Mux.scala 27:72] + node _T_778 = or(_T_777, _T_748) @[Mux.scala 27:72] + node _T_779 = or(_T_778, _T_749) @[Mux.scala 27:72] + node _T_780 = or(_T_779, _T_750) @[Mux.scala 27:72] + node _T_781 = or(_T_780, _T_751) @[Mux.scala 27:72] + node _T_782 = or(_T_781, _T_752) @[Mux.scala 27:72] + node _T_783 = or(_T_782, _T_753) @[Mux.scala 27:72] + node _T_784 = or(_T_783, _T_754) @[Mux.scala 27:72] + node _T_785 = or(_T_784, _T_755) @[Mux.scala 27:72] + node _T_786 = or(_T_785, _T_756) @[Mux.scala 27:72] + node _T_787 = or(_T_786, _T_757) @[Mux.scala 27:72] + node _T_788 = or(_T_787, _T_758) @[Mux.scala 27:72] + node _T_789 = or(_T_788, _T_759) @[Mux.scala 27:72] + node _T_790 = or(_T_789, _T_760) @[Mux.scala 27:72] + node _T_791 = or(_T_790, _T_761) @[Mux.scala 27:72] + node _T_792 = or(_T_791, _T_762) @[Mux.scala 27:72] + node _T_793 = or(_T_792, _T_763) @[Mux.scala 27:72] + node _T_794 = or(_T_793, _T_764) @[Mux.scala 27:72] + node _T_795 = or(_T_794, _T_765) @[Mux.scala 27:72] + node _T_796 = or(_T_795, _T_766) @[Mux.scala 27:72] + node _T_797 = or(_T_796, _T_767) @[Mux.scala 27:72] + node _T_798 = or(_T_797, _T_768) @[Mux.scala 27:72] + node _T_799 = or(_T_798, _T_769) @[Mux.scala 27:72] + node _T_800 = or(_T_799, _T_770) @[Mux.scala 27:72] + node _T_801 = or(_T_800, _T_771) @[Mux.scala 27:72] + node _T_802 = or(_T_801, _T_772) @[Mux.scala 27:72] + node _T_803 = or(_T_802, _T_773) @[Mux.scala 27:72] + node _T_804 = or(_T_803, _T_774) @[Mux.scala 27:72] + node _T_805 = or(_T_804, _T_775) @[Mux.scala 27:72] + node _T_806 = or(_T_805, _T_776) @[Mux.scala 27:72] + wire _T_807 : UInt<32> @[Mux.scala 27:72] + _T_807 <= _T_806 @[Mux.scala 27:72] + io.gpr_exu.gpr_i0_rs1_d <= _T_807 @[dec_gpr_ctl.scala 64:32] + node _T_808 = eq(io.raddr1, UInt<1>("h01")) @[dec_gpr_ctl.scala 65:72] + node _T_809 = bits(_T_808, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_810 = eq(io.raddr1, UInt<2>("h02")) @[dec_gpr_ctl.scala 65:72] + node _T_811 = bits(_T_810, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_812 = eq(io.raddr1, UInt<2>("h03")) @[dec_gpr_ctl.scala 65:72] + node _T_813 = bits(_T_812, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_814 = eq(io.raddr1, UInt<3>("h04")) @[dec_gpr_ctl.scala 65:72] + node _T_815 = bits(_T_814, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_816 = eq(io.raddr1, UInt<3>("h05")) @[dec_gpr_ctl.scala 65:72] + node _T_817 = bits(_T_816, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_818 = eq(io.raddr1, UInt<3>("h06")) @[dec_gpr_ctl.scala 65:72] + node _T_819 = bits(_T_818, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_820 = eq(io.raddr1, UInt<3>("h07")) @[dec_gpr_ctl.scala 65:72] + node _T_821 = bits(_T_820, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_822 = eq(io.raddr1, UInt<4>("h08")) @[dec_gpr_ctl.scala 65:72] + node _T_823 = bits(_T_822, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_824 = eq(io.raddr1, UInt<4>("h09")) @[dec_gpr_ctl.scala 65:72] + node _T_825 = bits(_T_824, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_826 = eq(io.raddr1, UInt<4>("h0a")) @[dec_gpr_ctl.scala 65:72] + node _T_827 = bits(_T_826, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_828 = eq(io.raddr1, UInt<4>("h0b")) @[dec_gpr_ctl.scala 65:72] + node _T_829 = bits(_T_828, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_830 = eq(io.raddr1, UInt<4>("h0c")) @[dec_gpr_ctl.scala 65:72] + node _T_831 = bits(_T_830, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_832 = eq(io.raddr1, UInt<4>("h0d")) @[dec_gpr_ctl.scala 65:72] + node _T_833 = bits(_T_832, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_834 = eq(io.raddr1, UInt<4>("h0e")) @[dec_gpr_ctl.scala 65:72] + node _T_835 = bits(_T_834, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_836 = eq(io.raddr1, UInt<4>("h0f")) @[dec_gpr_ctl.scala 65:72] + node _T_837 = bits(_T_836, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_838 = eq(io.raddr1, UInt<5>("h010")) @[dec_gpr_ctl.scala 65:72] + node _T_839 = bits(_T_838, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_840 = eq(io.raddr1, UInt<5>("h011")) @[dec_gpr_ctl.scala 65:72] + node _T_841 = bits(_T_840, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_842 = eq(io.raddr1, UInt<5>("h012")) @[dec_gpr_ctl.scala 65:72] + node _T_843 = bits(_T_842, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_844 = eq(io.raddr1, UInt<5>("h013")) @[dec_gpr_ctl.scala 65:72] + node _T_845 = bits(_T_844, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_846 = eq(io.raddr1, UInt<5>("h014")) @[dec_gpr_ctl.scala 65:72] + node _T_847 = bits(_T_846, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_848 = eq(io.raddr1, UInt<5>("h015")) @[dec_gpr_ctl.scala 65:72] + node _T_849 = bits(_T_848, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_850 = eq(io.raddr1, UInt<5>("h016")) @[dec_gpr_ctl.scala 65:72] + node _T_851 = bits(_T_850, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_852 = eq(io.raddr1, UInt<5>("h017")) @[dec_gpr_ctl.scala 65:72] + node _T_853 = bits(_T_852, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_854 = eq(io.raddr1, UInt<5>("h018")) @[dec_gpr_ctl.scala 65:72] + node _T_855 = bits(_T_854, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_856 = eq(io.raddr1, UInt<5>("h019")) @[dec_gpr_ctl.scala 65:72] + node _T_857 = bits(_T_856, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_858 = eq(io.raddr1, UInt<5>("h01a")) @[dec_gpr_ctl.scala 65:72] + node _T_859 = bits(_T_858, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_860 = eq(io.raddr1, UInt<5>("h01b")) @[dec_gpr_ctl.scala 65:72] + node _T_861 = bits(_T_860, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_862 = eq(io.raddr1, UInt<5>("h01c")) @[dec_gpr_ctl.scala 65:72] + node _T_863 = bits(_T_862, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_864 = eq(io.raddr1, UInt<5>("h01d")) @[dec_gpr_ctl.scala 65:72] + node _T_865 = bits(_T_864, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_866 = eq(io.raddr1, UInt<5>("h01e")) @[dec_gpr_ctl.scala 65:72] + node _T_867 = bits(_T_866, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_868 = eq(io.raddr1, UInt<5>("h01f")) @[dec_gpr_ctl.scala 65:72] + node _T_869 = bits(_T_868, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_870 = mux(_T_809, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_871 = mux(_T_811, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_872 = mux(_T_813, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_873 = mux(_T_815, gpr_out[4], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_874 = mux(_T_817, gpr_out[5], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_875 = mux(_T_819, gpr_out[6], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_876 = mux(_T_821, gpr_out[7], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_877 = mux(_T_823, gpr_out[8], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_878 = mux(_T_825, gpr_out[9], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_879 = mux(_T_827, gpr_out[10], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_880 = mux(_T_829, gpr_out[11], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_881 = mux(_T_831, gpr_out[12], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_882 = mux(_T_833, gpr_out[13], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_883 = mux(_T_835, gpr_out[14], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_884 = mux(_T_837, gpr_out[15], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_885 = mux(_T_839, gpr_out[16], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_886 = mux(_T_841, gpr_out[17], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_887 = mux(_T_843, gpr_out[18], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_888 = mux(_T_845, gpr_out[19], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_889 = mux(_T_847, gpr_out[20], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_890 = mux(_T_849, gpr_out[21], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_891 = mux(_T_851, gpr_out[22], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_892 = mux(_T_853, gpr_out[23], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_893 = mux(_T_855, gpr_out[24], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_894 = mux(_T_857, gpr_out[25], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_895 = mux(_T_859, gpr_out[26], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_896 = mux(_T_861, gpr_out[27], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_897 = mux(_T_863, gpr_out[28], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_898 = mux(_T_865, gpr_out[29], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_899 = mux(_T_867, gpr_out[30], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_900 = mux(_T_869, gpr_out[31], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_901 = or(_T_870, _T_871) @[Mux.scala 27:72] + node _T_902 = or(_T_901, _T_872) @[Mux.scala 27:72] + node _T_903 = or(_T_902, _T_873) @[Mux.scala 27:72] + node _T_904 = or(_T_903, _T_874) @[Mux.scala 27:72] + node _T_905 = or(_T_904, _T_875) @[Mux.scala 27:72] + node _T_906 = or(_T_905, _T_876) @[Mux.scala 27:72] + node _T_907 = or(_T_906, _T_877) @[Mux.scala 27:72] + node _T_908 = or(_T_907, _T_878) @[Mux.scala 27:72] + node _T_909 = or(_T_908, _T_879) @[Mux.scala 27:72] + node _T_910 = or(_T_909, _T_880) @[Mux.scala 27:72] + node _T_911 = or(_T_910, _T_881) @[Mux.scala 27:72] + node _T_912 = or(_T_911, _T_882) @[Mux.scala 27:72] + node _T_913 = or(_T_912, _T_883) @[Mux.scala 27:72] + node _T_914 = or(_T_913, _T_884) @[Mux.scala 27:72] + node _T_915 = or(_T_914, _T_885) @[Mux.scala 27:72] + node _T_916 = or(_T_915, _T_886) @[Mux.scala 27:72] + node _T_917 = or(_T_916, _T_887) @[Mux.scala 27:72] + node _T_918 = or(_T_917, _T_888) @[Mux.scala 27:72] + node _T_919 = or(_T_918, _T_889) @[Mux.scala 27:72] + node _T_920 = or(_T_919, _T_890) @[Mux.scala 27:72] + node _T_921 = or(_T_920, _T_891) @[Mux.scala 27:72] + node _T_922 = or(_T_921, _T_892) @[Mux.scala 27:72] + node _T_923 = or(_T_922, _T_893) @[Mux.scala 27:72] + node _T_924 = or(_T_923, _T_894) @[Mux.scala 27:72] + node _T_925 = or(_T_924, _T_895) @[Mux.scala 27:72] + node _T_926 = or(_T_925, _T_896) @[Mux.scala 27:72] + node _T_927 = or(_T_926, _T_897) @[Mux.scala 27:72] + node _T_928 = or(_T_927, _T_898) @[Mux.scala 27:72] + node _T_929 = or(_T_928, _T_899) @[Mux.scala 27:72] + node _T_930 = or(_T_929, _T_900) @[Mux.scala 27:72] + wire _T_931 : UInt<32> @[Mux.scala 27:72] + _T_931 <= _T_930 @[Mux.scala 27:72] + io.gpr_exu.gpr_i0_rs2_d <= _T_931 @[dec_gpr_ctl.scala 65:32] + + module int_exc : + input clock : Clock + input reset : AsyncReset + output io : {mhwakeup_ready : UInt<1>, ext_int_ready : UInt<1>, ce_int_ready : UInt<1>, soft_int_ready : UInt<1>, timer_int_ready : UInt<1>, int_timer0_int_hold : UInt<1>, int_timer1_int_hold : UInt<1>, internal_dbg_halt_timers : UInt<1>, take_ext_int_start : UInt<1>, flip ext_int_freeze_d1 : UInt<1>, flip take_ext_int_start_d1 : UInt<1>, flip take_ext_int_start_d2 : UInt<1>, flip take_ext_int_start_d3 : UInt<1>, ext_int_freeze : UInt<1>, take_ext_int : UInt<1>, fast_int_meicpct : UInt<1>, ignore_ext_int_due_to_lsu_stall : UInt<1>, take_ce_int : UInt<1>, take_soft_int : UInt<1>, take_timer_int : UInt<1>, take_int_timer0_int : UInt<1>, take_int_timer1_int : UInt<1>, take_reset : UInt<1>, take_nmi : UInt<1>, synchronous_flush_r : UInt<1>, tlu_flush_lower_r : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, interrupt_valid_r_d1 : UInt<1>, i0_exception_valid_r_d1 : UInt<1>, exc_or_int_valid_r_d1 : UInt<1>, exc_cause_wb : UInt<5>, i0_valid_wb : UInt<1>, trigger_hit_r_d1 : UInt<1>, take_nmi_r_d1 : UInt<1>, pause_expired_wb : UInt<1>, interrupt_valid_r : UInt<1>, exc_cause_r : UInt<5>, i0_exception_valid_r : UInt<1>, tlu_flush_path_r_d1 : UInt<31>, exc_or_int_valid_r : UInt<1>, flip free_l2clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_stall_int_ff : UInt<1>, flip mstatus_mie_ns : UInt<1>, flip mip : UInt<6>, flip mie_ns : UInt<6>, flip mret_r : UInt<1>, flip pmu_fw_tlu_halted_f : UInt<1>, flip int_timer0_int_hold_f : UInt<1>, flip int_timer1_int_hold_f : UInt<1>, flip internal_dbg_halt_mode_f : UInt<1>, flip dcsr_single_step_running : UInt<1>, flip internal_dbg_halt_mode : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip internal_pmu_fw_halt_mode : UInt<1>, flip i_cpu_halt_req_d1 : UInt<1>, flip ebreak_to_debug_mode_r : UInt<1>, flip lsu_fir_error : UInt<2>, flip csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_meicpct : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}, flip dec_csr_any_unq_d : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip reset_delayed : UInt<1>, flip mpc_reset_run_req : UInt<1>, flip nmi_int_detected : UInt<1>, flip dcsr_single_step_running_f : UInt<1>, flip dcsr_single_step_done_f : UInt<1>, flip dcsr : UInt<16>, flip mtvec : UInt<31>, flip tlu_i0_commit_cmt : UInt<1>, flip i0_trigger_hit_r : UInt<1>, flip pause_expired_r : UInt<1>, flip nmi_vec : UInt<31>, flip lsu_i0_rfnpc_r : UInt<1>, flip fence_i_r : UInt<1>, flip iccm_repair_state_rfnpc : UInt<1>, flip i_cpu_run_req_d1 : UInt<1>, flip rfpc_i0_r : UInt<1>, flip lsu_exc_valid_r : UInt<1>, flip trigger_hit_dmode_r : UInt<1>, flip take_halt : UInt<1>, flip rst_vec : UInt<31>, flip lsu_fir_addr : UInt<31>, flip dec_tlu_i0_pc_r : UInt<31>, flip npc_r : UInt<31>, flip mepc : UInt<31>, flip debug_resume_req_f : UInt<1>, flip dpc : UInt<31>, flip npc_r_d1 : UInt<31>, flip tlu_flush_lower_r_d1 : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip ebreak_r : UInt<1>, flip ecall_r : UInt<1>, flip illegal_r : UInt<1>, flip inst_acc_r : UInt<1>, flip lsu_i0_exc_r : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip dec_tlu_wr_pause_r_d1 : UInt<1>} + + node _T = eq(io.lsu_error_pkt_r.bits.exc_type, UInt<1>("h00")) @[dec_tlu_ctl.scala 3017:48] + node lsu_exc_ma_r = and(io.lsu_i0_exc_r, _T) @[dec_tlu_ctl.scala 3017:46] + node lsu_exc_acc_r = and(io.lsu_i0_exc_r, io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 3018:46] + node lsu_exc_st_r = and(io.lsu_i0_exc_r, io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 3019:46] + node _T_1 = or(io.ebreak_r, io.ecall_r) @[dec_tlu_ctl.scala 3031:49] + node _T_2 = or(_T_1, io.illegal_r) @[dec_tlu_ctl.scala 3031:62] + node _T_3 = or(_T_2, io.inst_acc_r) @[dec_tlu_ctl.scala 3031:77] + node _T_4 = not(io.rfpc_i0_r) @[dec_tlu_ctl.scala 3031:96] + node _T_5 = and(_T_3, _T_4) @[dec_tlu_ctl.scala 3031:94] + node _T_6 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 3031:112] + node _T_7 = and(_T_5, _T_6) @[dec_tlu_ctl.scala 3031:110] + io.i0_exception_valid_r <= _T_7 @[dec_tlu_ctl.scala 3031:33] + node _T_8 = bits(io.take_nmi, 0, 0) @[Bitwise.scala 72:15] + node _T_9 = mux(_T_8, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_10 = not(_T_9) @[dec_tlu_ctl.scala 3039:27] + node _T_11 = bits(io.take_ext_int, 0, 0) @[dec_tlu_ctl.scala 3040:35] + node _T_12 = bits(io.take_timer_int, 0, 0) @[dec_tlu_ctl.scala 3041:38] + node _T_13 = bits(io.take_soft_int, 0, 0) @[dec_tlu_ctl.scala 3042:36] + node _T_14 = bits(io.take_int_timer0_int, 0, 0) @[dec_tlu_ctl.scala 3043:43] + node _T_15 = bits(io.take_int_timer1_int, 0, 0) @[dec_tlu_ctl.scala 3044:42] + node _T_16 = bits(io.take_ce_int, 0, 0) @[dec_tlu_ctl.scala 3045:34] + node _T_17 = bits(io.illegal_r, 0, 0) @[dec_tlu_ctl.scala 3046:32] + node _T_18 = bits(io.ecall_r, 0, 0) @[dec_tlu_ctl.scala 3047:30] + node _T_19 = bits(io.inst_acc_r, 0, 0) @[dec_tlu_ctl.scala 3048:34] + node _T_20 = or(io.ebreak_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 3049:31] + node _T_21 = bits(_T_20, 0, 0) @[dec_tlu_ctl.scala 3049:55] + node _T_22 = eq(lsu_exc_st_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 3050:33] + node _T_23 = and(lsu_exc_ma_r, _T_22) @[dec_tlu_ctl.scala 3050:31] + node _T_24 = bits(_T_23, 0, 0) @[dec_tlu_ctl.scala 3050:48] + node _T_25 = eq(lsu_exc_st_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 3051:34] + node _T_26 = and(lsu_exc_acc_r, _T_25) @[dec_tlu_ctl.scala 3051:32] + node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 3051:49] + node _T_28 = and(lsu_exc_ma_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 3052:31] + node _T_29 = bits(_T_28, 0, 0) @[dec_tlu_ctl.scala 3052:48] + node _T_30 = and(lsu_exc_acc_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 3053:32] + node _T_31 = bits(_T_30, 0, 0) @[dec_tlu_ctl.scala 3053:49] + node _T_32 = mux(_T_11, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_33 = mux(_T_12, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_34 = mux(_T_13, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_35 = mux(_T_14, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_36 = mux(_T_15, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_37 = mux(_T_16, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_38 = mux(_T_17, UInt<5>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_39 = mux(_T_18, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_40 = mux(_T_19, UInt<5>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_41 = mux(_T_21, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_42 = mux(_T_24, UInt<5>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_43 = mux(_T_27, UInt<5>("h05"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_44 = mux(_T_29, UInt<5>("h06"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_45 = mux(_T_31, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_46 = or(_T_32, _T_33) @[Mux.scala 27:72] + node _T_47 = or(_T_46, _T_34) @[Mux.scala 27:72] + node _T_48 = or(_T_47, _T_35) @[Mux.scala 27:72] + node _T_49 = or(_T_48, _T_36) @[Mux.scala 27:72] + node _T_50 = or(_T_49, _T_37) @[Mux.scala 27:72] + node _T_51 = or(_T_50, _T_38) @[Mux.scala 27:72] + node _T_52 = or(_T_51, _T_39) @[Mux.scala 27:72] + node _T_53 = or(_T_52, _T_40) @[Mux.scala 27:72] + node _T_54 = or(_T_53, _T_41) @[Mux.scala 27:72] + node _T_55 = or(_T_54, _T_42) @[Mux.scala 27:72] + node _T_56 = or(_T_55, _T_43) @[Mux.scala 27:72] + node _T_57 = or(_T_56, _T_44) @[Mux.scala 27:72] + node _T_58 = or(_T_57, _T_45) @[Mux.scala 27:72] + wire _T_59 : UInt<5> @[Mux.scala 27:72] + _T_59 <= _T_58 @[Mux.scala 27:72] + node _T_60 = and(_T_10, _T_59) @[dec_tlu_ctl.scala 3039:48] + io.exc_cause_r <= _T_60 @[dec_tlu_ctl.scala 3039:24] + node _T_61 = eq(io.dec_csr_stall_int_ff, UInt<1>("h00")) @[dec_tlu_ctl.scala 3064:31] + node _T_62 = and(_T_61, io.mstatus_mie_ns) @[dec_tlu_ctl.scala 3064:56] + node _T_63 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 3064:84] + node _T_64 = and(_T_62, _T_63) @[dec_tlu_ctl.scala 3064:76] + node _T_65 = bits(io.mie_ns, 2, 2) @[dec_tlu_ctl.scala 3064:108] + node _T_66 = and(_T_64, _T_65) @[dec_tlu_ctl.scala 3064:97] + io.mhwakeup_ready <= _T_66 @[dec_tlu_ctl.scala 3064:28] + node _T_67 = eq(io.dec_csr_stall_int_ff, UInt<1>("h00")) @[dec_tlu_ctl.scala 3065:31] + node _T_68 = and(_T_67, io.mstatus_mie_ns) @[dec_tlu_ctl.scala 3065:56] + node _T_69 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 3065:84] + node _T_70 = and(_T_68, _T_69) @[dec_tlu_ctl.scala 3065:76] + node _T_71 = bits(io.mie_ns, 2, 2) @[dec_tlu_ctl.scala 3065:108] + node _T_72 = and(_T_70, _T_71) @[dec_tlu_ctl.scala 3065:97] + node _T_73 = not(io.ignore_ext_int_due_to_lsu_stall) @[dec_tlu_ctl.scala 3065:121] + node _T_74 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 3065:119] + io.ext_int_ready <= _T_74 @[dec_tlu_ctl.scala 3065:28] + node _T_75 = eq(io.dec_csr_stall_int_ff, UInt<1>("h00")) @[dec_tlu_ctl.scala 3066:31] + node _T_76 = and(_T_75, io.mstatus_mie_ns) @[dec_tlu_ctl.scala 3066:56] + node _T_77 = dshr(io.mip, UInt<3>("h05")) @[dec_tlu_ctl.scala 3066:84] + node _T_78 = bits(_T_77, 0, 0) @[dec_tlu_ctl.scala 3066:84] + node _T_79 = and(_T_76, _T_78) @[dec_tlu_ctl.scala 3066:76] + node _T_80 = bits(io.mie_ns, 5, 5) @[dec_tlu_ctl.scala 3066:108] + node _T_81 = and(_T_79, _T_80) @[dec_tlu_ctl.scala 3066:97] + io.ce_int_ready <= _T_81 @[dec_tlu_ctl.scala 3066:28] + node _T_82 = eq(io.dec_csr_stall_int_ff, UInt<1>("h00")) @[dec_tlu_ctl.scala 3067:31] + node _T_83 = and(_T_82, io.mstatus_mie_ns) @[dec_tlu_ctl.scala 3067:56] + node _T_84 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 3067:84] + node _T_85 = and(_T_83, _T_84) @[dec_tlu_ctl.scala 3067:76] + node _T_86 = bits(io.mie_ns, 0, 0) @[dec_tlu_ctl.scala 3067:108] + node _T_87 = and(_T_85, _T_86) @[dec_tlu_ctl.scala 3067:97] + io.soft_int_ready <= _T_87 @[dec_tlu_ctl.scala 3067:28] + node _T_88 = eq(io.dec_csr_stall_int_ff, UInt<1>("h00")) @[dec_tlu_ctl.scala 3068:31] + node _T_89 = and(_T_88, io.mstatus_mie_ns) @[dec_tlu_ctl.scala 3068:56] + node _T_90 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 3068:84] + node _T_91 = and(_T_89, _T_90) @[dec_tlu_ctl.scala 3068:76] + node _T_92 = bits(io.mie_ns, 1, 1) @[dec_tlu_ctl.scala 3068:108] + node _T_93 = and(_T_91, _T_92) @[dec_tlu_ctl.scala 3068:97] + io.timer_int_ready <= _T_93 @[dec_tlu_ctl.scala 3068:28] + node _T_94 = bits(io.mie_ns, 4, 4) @[dec_tlu_ctl.scala 3071:68] + node int_timer0_int_possible = and(io.mstatus_mie_ns, _T_94) @[dec_tlu_ctl.scala 3071:57] + node _T_95 = dshr(io.mip, UInt<3>("h04")) @[dec_tlu_ctl.scala 3072:42] + node _T_96 = bits(_T_95, 0, 0) @[dec_tlu_ctl.scala 3072:42] + node int_timer0_int_ready = and(_T_96, int_timer0_int_possible) @[dec_tlu_ctl.scala 3072:55] + node _T_97 = bits(io.mie_ns, 3, 3) @[dec_tlu_ctl.scala 3073:68] + node int_timer1_int_possible = and(io.mstatus_mie_ns, _T_97) @[dec_tlu_ctl.scala 3073:57] + node _T_98 = dshr(io.mip, UInt<2>("h03")) @[dec_tlu_ctl.scala 3074:42] + node _T_99 = bits(_T_98, 0, 0) @[dec_tlu_ctl.scala 3074:42] + node int_timer1_int_ready = and(_T_99, int_timer1_int_possible) @[dec_tlu_ctl.scala 3074:55] + node _T_100 = or(io.dec_csr_stall_int_ff, io.synchronous_flush_r) @[dec_tlu_ctl.scala 3078:57] + node _T_101 = or(_T_100, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 3078:82] + node int_timer_stalled = or(_T_101, io.mret_r) @[dec_tlu_ctl.scala 3078:109] + node _T_102 = or(io.pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 3080:83] + node _T_103 = and(int_timer0_int_ready, _T_102) @[dec_tlu_ctl.scala 3080:57] + node _T_104 = and(int_timer0_int_possible, io.int_timer0_int_hold_f) @[dec_tlu_ctl.scala 3080:132] + node _T_105 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 3080:161] + node _T_106 = and(_T_104, _T_105) @[dec_tlu_ctl.scala 3080:159] + node _T_107 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 3080:185] + node _T_108 = and(_T_106, _T_107) @[dec_tlu_ctl.scala 3080:183] + node _T_109 = not(io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 3080:210] + node _T_110 = and(_T_108, _T_109) @[dec_tlu_ctl.scala 3080:208] + node _T_111 = or(_T_103, _T_110) @[dec_tlu_ctl.scala 3080:105] + io.int_timer0_int_hold <= _T_111 @[dec_tlu_ctl.scala 3080:32] + node _T_112 = or(io.pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 3081:83] + node _T_113 = and(int_timer1_int_ready, _T_112) @[dec_tlu_ctl.scala 3081:57] + node _T_114 = and(int_timer1_int_possible, io.int_timer1_int_hold_f) @[dec_tlu_ctl.scala 3081:132] + node _T_115 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 3081:161] + node _T_116 = and(_T_114, _T_115) @[dec_tlu_ctl.scala 3081:159] + node _T_117 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 3081:185] + node _T_118 = and(_T_116, _T_117) @[dec_tlu_ctl.scala 3081:183] + node _T_119 = not(io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 3081:210] + node _T_120 = and(_T_118, _T_119) @[dec_tlu_ctl.scala 3081:208] + node _T_121 = or(_T_113, _T_120) @[dec_tlu_ctl.scala 3081:105] + io.int_timer1_int_hold <= _T_121 @[dec_tlu_ctl.scala 3081:32] + node _T_122 = not(io.dcsr_single_step_running) @[dec_tlu_ctl.scala 3083:70] + node _T_123 = and(io.internal_dbg_halt_mode_f, _T_122) @[dec_tlu_ctl.scala 3083:68] + io.internal_dbg_halt_timers <= _T_123 @[dec_tlu_ctl.scala 3083:37] + node _T_124 = not(io.dcsr_single_step_running) @[dec_tlu_ctl.scala 3085:63] + node _T_125 = or(_T_124, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 3085:92] + node _T_126 = and(io.internal_dbg_halt_mode, _T_125) @[dec_tlu_ctl.scala 3085:60] + node _T_127 = or(_T_126, io.internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 3085:118] + node _T_128 = or(_T_127, io.i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 3085:149] + node _T_129 = or(_T_128, io.take_nmi) @[dec_tlu_ctl.scala 3085:172] + node _T_130 = or(_T_129, io.ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 3085:186] + node _T_131 = or(_T_130, io.synchronous_flush_r) @[dec_tlu_ctl.scala 3085:214] + node _T_132 = or(_T_131, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 3085:240] + node _T_133 = or(_T_132, io.mret_r) @[dec_tlu_ctl.scala 3085:267] + node block_interrupts = or(_T_133, io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 3085:279] + node _T_134 = not(block_interrupts) @[dec_tlu_ctl.scala 3093:61] + node _T_135 = and(io.ext_int_ready, _T_134) @[dec_tlu_ctl.scala 3093:59] + io.take_ext_int_start <= _T_135 @[dec_tlu_ctl.scala 3093:39] + node _T_136 = or(io.take_ext_int_start, io.take_ext_int_start_d1) @[dec_tlu_ctl.scala 3094:60] + node _T_137 = or(_T_136, io.take_ext_int_start_d2) @[dec_tlu_ctl.scala 3094:87] + node _T_138 = or(_T_137, io.take_ext_int_start_d3) @[dec_tlu_ctl.scala 3094:114] + io.ext_int_freeze <= _T_138 @[dec_tlu_ctl.scala 3094:35] + node _T_139 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 3095:81] + node _T_140 = not(_T_139) @[dec_tlu_ctl.scala 3095:63] + node _T_141 = and(io.take_ext_int_start_d3, _T_140) @[dec_tlu_ctl.scala 3095:61] + io.take_ext_int <= _T_141 @[dec_tlu_ctl.scala 3095:33] + node _T_142 = and(io.csr_pkt.csr_meicpct, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 3096:63] + io.fast_int_meicpct <= _T_142 @[dec_tlu_ctl.scala 3096:37] + io.ignore_ext_int_due_to_lsu_stall <= io.lsu_fastint_stall_any @[dec_tlu_ctl.scala 3097:52] + node _T_143 = not(io.ext_int_ready) @[dec_tlu_ctl.scala 3110:46] + node _T_144 = and(io.ce_int_ready, _T_143) @[dec_tlu_ctl.scala 3110:44] + node _T_145 = not(block_interrupts) @[dec_tlu_ctl.scala 3110:66] + node _T_146 = and(_T_144, _T_145) @[dec_tlu_ctl.scala 3110:64] + io.take_ce_int <= _T_146 @[dec_tlu_ctl.scala 3110:25] + node _T_147 = not(io.ext_int_ready) @[dec_tlu_ctl.scala 3111:49] + node _T_148 = and(io.soft_int_ready, _T_147) @[dec_tlu_ctl.scala 3111:47] + node _T_149 = not(io.ce_int_ready) @[dec_tlu_ctl.scala 3111:69] + node _T_150 = and(_T_148, _T_149) @[dec_tlu_ctl.scala 3111:67] + node _T_151 = not(block_interrupts) @[dec_tlu_ctl.scala 3111:88] + node _T_152 = and(_T_150, _T_151) @[dec_tlu_ctl.scala 3111:86] + io.take_soft_int <= _T_152 @[dec_tlu_ctl.scala 3111:26] + node _T_153 = not(io.soft_int_ready) @[dec_tlu_ctl.scala 3112:51] + node _T_154 = and(io.timer_int_ready, _T_153) @[dec_tlu_ctl.scala 3112:49] + node _T_155 = not(io.ext_int_ready) @[dec_tlu_ctl.scala 3112:72] + node _T_156 = and(_T_154, _T_155) @[dec_tlu_ctl.scala 3112:70] + node _T_157 = not(io.ce_int_ready) @[dec_tlu_ctl.scala 3112:92] + node _T_158 = and(_T_156, _T_157) @[dec_tlu_ctl.scala 3112:90] + node _T_159 = not(block_interrupts) @[dec_tlu_ctl.scala 3112:111] + node _T_160 = and(_T_158, _T_159) @[dec_tlu_ctl.scala 3112:109] + io.take_timer_int <= _T_160 @[dec_tlu_ctl.scala 3112:27] + node _T_161 = or(int_timer0_int_ready, io.int_timer0_int_hold_f) @[dec_tlu_ctl.scala 3113:57] + node _T_162 = and(_T_161, int_timer0_int_possible) @[dec_tlu_ctl.scala 3113:85] + node _T_163 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 3113:113] + node _T_164 = and(_T_162, _T_163) @[dec_tlu_ctl.scala 3113:111] + node _T_165 = not(io.timer_int_ready) @[dec_tlu_ctl.scala 3113:140] + node _T_166 = and(_T_164, _T_165) @[dec_tlu_ctl.scala 3113:138] + node _T_167 = not(io.soft_int_ready) @[dec_tlu_ctl.scala 3113:162] + node _T_168 = and(_T_166, _T_167) @[dec_tlu_ctl.scala 3113:160] + node _T_169 = not(io.ext_int_ready) @[dec_tlu_ctl.scala 3113:183] + node _T_170 = and(_T_168, _T_169) @[dec_tlu_ctl.scala 3113:181] + node _T_171 = not(io.ce_int_ready) @[dec_tlu_ctl.scala 3113:203] + node _T_172 = and(_T_170, _T_171) @[dec_tlu_ctl.scala 3113:201] + node _T_173 = not(block_interrupts) @[dec_tlu_ctl.scala 3113:222] + node _T_174 = and(_T_172, _T_173) @[dec_tlu_ctl.scala 3113:220] + io.take_int_timer0_int <= _T_174 @[dec_tlu_ctl.scala 3113:32] + node _T_175 = or(int_timer1_int_ready, io.int_timer1_int_hold_f) @[dec_tlu_ctl.scala 3114:57] + node _T_176 = and(_T_175, int_timer1_int_possible) @[dec_tlu_ctl.scala 3114:85] + node _T_177 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 3114:113] + node _T_178 = and(_T_176, _T_177) @[dec_tlu_ctl.scala 3114:111] + node _T_179 = or(int_timer0_int_ready, io.int_timer0_int_hold_f) @[dec_tlu_ctl.scala 3114:163] + node _T_180 = not(_T_179) @[dec_tlu_ctl.scala 3114:140] + node _T_181 = and(_T_178, _T_180) @[dec_tlu_ctl.scala 3114:138] + node _T_182 = not(io.timer_int_ready) @[dec_tlu_ctl.scala 3114:193] + node _T_183 = and(_T_181, _T_182) @[dec_tlu_ctl.scala 3114:191] + node _T_184 = not(io.soft_int_ready) @[dec_tlu_ctl.scala 3114:215] + node _T_185 = and(_T_183, _T_184) @[dec_tlu_ctl.scala 3114:213] + node _T_186 = not(io.ext_int_ready) @[dec_tlu_ctl.scala 3114:236] + node _T_187 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 3114:234] + node _T_188 = not(io.ce_int_ready) @[dec_tlu_ctl.scala 3114:256] + node _T_189 = and(_T_187, _T_188) @[dec_tlu_ctl.scala 3114:254] + node _T_190 = not(block_interrupts) @[dec_tlu_ctl.scala 3114:275] + node _T_191 = and(_T_189, _T_190) @[dec_tlu_ctl.scala 3114:273] + io.take_int_timer1_int <= _T_191 @[dec_tlu_ctl.scala 3114:32] + node _T_192 = and(io.reset_delayed, io.mpc_reset_run_req) @[dec_tlu_ctl.scala 3115:43] + io.take_reset <= _T_192 @[dec_tlu_ctl.scala 3115:23] + node _T_193 = not(io.internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 3116:46] + node _T_194 = and(io.nmi_int_detected, _T_193) @[dec_tlu_ctl.scala 3116:44] + node _T_195 = not(io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 3116:79] + node _T_196 = bits(io.dcsr, 11, 11) @[dec_tlu_ctl.scala 3116:148] + node _T_197 = and(io.dcsr_single_step_running_f, _T_196) @[dec_tlu_ctl.scala 3116:139] + node _T_198 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 3116:164] + node _T_199 = and(_T_197, _T_198) @[dec_tlu_ctl.scala 3116:162] + node _T_200 = not(io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 3116:189] + node _T_201 = and(_T_199, _T_200) @[dec_tlu_ctl.scala 3116:187] + node _T_202 = or(_T_195, _T_201) @[dec_tlu_ctl.scala 3116:106] + node _T_203 = and(_T_194, _T_202) @[dec_tlu_ctl.scala 3116:76] + node _T_204 = not(io.synchronous_flush_r) @[dec_tlu_ctl.scala 3116:220] + node _T_205 = and(_T_203, _T_204) @[dec_tlu_ctl.scala 3116:218] + node _T_206 = not(io.mret_r) @[dec_tlu_ctl.scala 3116:246] + node _T_207 = and(_T_205, _T_206) @[dec_tlu_ctl.scala 3116:244] + node _T_208 = not(io.take_reset) @[dec_tlu_ctl.scala 3116:259] + node _T_209 = and(_T_207, _T_208) @[dec_tlu_ctl.scala 3116:257] + node _T_210 = not(io.ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 3116:276] + node _T_211 = and(_T_209, _T_210) @[dec_tlu_ctl.scala 3116:274] + node _T_212 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 3116:306] + node _T_213 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 3116:375] + node _T_214 = and(io.take_ext_int_start_d3, _T_213) @[dec_tlu_ctl.scala 3116:356] + node _T_215 = or(_T_212, _T_214) @[dec_tlu_ctl.scala 3116:328] + node _T_216 = and(_T_211, _T_215) @[dec_tlu_ctl.scala 3116:303] + io.take_nmi <= _T_216 @[dec_tlu_ctl.scala 3116:21] + node _T_217 = or(io.take_ext_int, io.take_timer_int) @[dec_tlu_ctl.scala 3120:49] + node _T_218 = or(_T_217, io.take_soft_int) @[dec_tlu_ctl.scala 3120:69] + node _T_219 = or(_T_218, io.take_nmi) @[dec_tlu_ctl.scala 3120:88] + node _T_220 = or(_T_219, io.take_ce_int) @[dec_tlu_ctl.scala 3120:102] + node _T_221 = or(_T_220, io.take_int_timer0_int) @[dec_tlu_ctl.scala 3120:119] + node _T_222 = or(_T_221, io.take_int_timer1_int) @[dec_tlu_ctl.scala 3120:144] + io.interrupt_valid_r <= _T_222 @[dec_tlu_ctl.scala 3120:30] + node _T_223 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 3125:42] + node _T_224 = cat(_T_223, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_225 = cat(UInt<25>("h00"), io.exc_cause_r) @[Cat.scala 29:58] + node _T_226 = cat(_T_225, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_227 = add(_T_224, _T_226) @[dec_tlu_ctl.scala 3125:59] + node vectored_path = tail(_T_227, 1) @[dec_tlu_ctl.scala 3125:59] + node _T_228 = bits(io.take_nmi, 0, 0) @[dec_tlu_ctl.scala 3126:46] + node _T_229 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 3126:78] + node _T_230 = eq(_T_229, UInt<1>("h01")) @[dec_tlu_ctl.scala 3126:82] + node _T_231 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 3126:118] + node _T_232 = cat(_T_231, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_233 = mux(_T_230, vectored_path, _T_232) @[dec_tlu_ctl.scala 3126:69] + node interrupt_path = mux(_T_228, io.nmi_vec, _T_233) @[dec_tlu_ctl.scala 3126:33] + node _T_234 = or(io.lsu_i0_rfnpc_r, io.fence_i_r) @[dec_tlu_ctl.scala 3127:44] + node _T_235 = or(_T_234, io.iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 3127:59] + node _T_236 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 3127:113] + node _T_237 = and(io.i_cpu_run_req_d1, _T_236) @[dec_tlu_ctl.scala 3127:111] + node _T_238 = or(_T_235, _T_237) @[dec_tlu_ctl.scala 3127:88] + node _T_239 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 3127:154] + node _T_240 = and(io.rfpc_i0_r, _T_239) @[dec_tlu_ctl.scala 3127:152] + node sel_npc_r = or(_T_238, _T_240) @[dec_tlu_ctl.scala 3127:136] + node _T_241 = and(io.i_cpu_run_req_d1, io.pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 3128:51] + node sel_npc_resume = or(_T_241, io.pause_expired_r) @[dec_tlu_ctl.scala 3128:77] + node _T_242 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 3129:74] + node _T_243 = eq(_T_242, UInt<1>("h00")) @[dec_tlu_ctl.scala 3129:55] + node sel_fir_addr = and(io.take_ext_int_start_d3, _T_243) @[dec_tlu_ctl.scala 3129:53] + node _T_244 = or(io.i0_exception_valid_r, io.rfpc_i0_r) @[dec_tlu_ctl.scala 3130:60] + node _T_245 = or(_T_244, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 3130:75] + node _T_246 = or(_T_245, io.fence_i_r) @[dec_tlu_ctl.scala 3130:96] + node _T_247 = or(_T_246, io.lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 3130:111] + node _T_248 = or(_T_247, io.iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 3130:131] + node _T_249 = or(_T_248, io.debug_resume_req_f) @[dec_tlu_ctl.scala 3130:161] + node _T_250 = or(_T_249, sel_npc_resume) @[dec_tlu_ctl.scala 3130:186] + node _T_251 = or(_T_250, io.dec_tlu_wr_pause_r_d1) @[dec_tlu_ctl.scala 3130:204] + node _T_252 = or(_T_251, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 3130:232] + io.synchronous_flush_r <= _T_252 @[dec_tlu_ctl.scala 3130:33] + node _T_253 = or(io.interrupt_valid_r, io.mret_r) @[dec_tlu_ctl.scala 3131:54] + node _T_254 = or(_T_253, io.synchronous_flush_r) @[dec_tlu_ctl.scala 3131:66] + node _T_255 = or(_T_254, io.take_halt) @[dec_tlu_ctl.scala 3131:91] + node _T_256 = or(_T_255, io.take_reset) @[dec_tlu_ctl.scala 3131:106] + node _T_257 = or(_T_256, io.take_ext_int_start) @[dec_tlu_ctl.scala 3131:122] + io.tlu_flush_lower_r <= _T_257 @[dec_tlu_ctl.scala 3131:30] + node _T_258 = bits(io.take_reset, 0, 0) @[dec_tlu_ctl.scala 3133:50] + node _T_259 = bits(sel_fir_addr, 0, 0) @[dec_tlu_ctl.scala 3134:32] + node _T_260 = eq(io.take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 3135:29] + node _T_261 = eq(sel_npc_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 3135:47] + node _T_262 = and(_T_260, _T_261) @[dec_tlu_ctl.scala 3135:36] + node _T_263 = eq(io.take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 3136:29] + node _T_264 = eq(io.rfpc_i0_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 3136:50] + node _T_265 = and(_T_263, _T_264) @[dec_tlu_ctl.scala 3136:36] + node _T_266 = eq(io.dec_tlu_i0_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 3136:80] + node _T_267 = and(_T_265, _T_266) @[dec_tlu_ctl.scala 3136:57] + node _T_268 = eq(sel_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 3136:98] + node _T_269 = and(_T_267, _T_268) @[dec_tlu_ctl.scala 3136:87] + node _T_270 = eq(io.interrupt_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 3137:38] + node _T_271 = eq(sel_fir_addr, UInt<1>("h00")) @[dec_tlu_ctl.scala 3137:59] + node _T_272 = and(_T_270, _T_271) @[dec_tlu_ctl.scala 3137:45] + node _T_273 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 3138:43] + node _T_274 = not(io.trigger_hit_dmode_r) @[dec_tlu_ctl.scala 3138:89] + node _T_275 = and(io.i0_trigger_hit_r, _T_274) @[dec_tlu_ctl.scala 3138:87] + node _T_276 = or(_T_273, _T_275) @[dec_tlu_ctl.scala 3138:64] + node _T_277 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 3138:117] + node _T_278 = and(_T_276, _T_277) @[dec_tlu_ctl.scala 3138:115] + node _T_279 = not(sel_fir_addr) @[dec_tlu_ctl.scala 3138:141] + node _T_280 = and(_T_278, _T_279) @[dec_tlu_ctl.scala 3138:139] + node _T_281 = bits(_T_280, 0, 0) @[dec_tlu_ctl.scala 3138:156] + node _T_282 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 3138:184] + node _T_283 = cat(_T_282, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_284 = not(io.take_nmi) @[dec_tlu_ctl.scala 3139:18] + node _T_285 = and(_T_284, io.mret_r) @[dec_tlu_ctl.scala 3139:31] + node _T_286 = bits(_T_285, 0, 0) @[dec_tlu_ctl.scala 3139:44] + node _T_287 = not(io.take_nmi) @[dec_tlu_ctl.scala 3140:18] + node _T_288 = and(_T_287, io.debug_resume_req_f) @[dec_tlu_ctl.scala 3140:31] + node _T_289 = bits(_T_288, 0, 0) @[dec_tlu_ctl.scala 3140:56] + node _T_290 = not(io.take_nmi) @[dec_tlu_ctl.scala 3141:18] + node _T_291 = and(_T_290, sel_npc_resume) @[dec_tlu_ctl.scala 3141:31] + node _T_292 = bits(_T_291, 0, 0) @[dec_tlu_ctl.scala 3141:49] + node _T_293 = mux(_T_259, io.lsu_fir_addr, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_294 = mux(_T_262, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_295 = mux(_T_269, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_296 = mux(_T_272, interrupt_path, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_297 = mux(_T_281, _T_283, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_298 = mux(_T_286, io.mepc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_299 = mux(_T_289, io.dpc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_300 = mux(_T_292, io.npc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_301 = or(_T_293, _T_294) @[Mux.scala 27:72] + node _T_302 = or(_T_301, _T_295) @[Mux.scala 27:72] + node _T_303 = or(_T_302, _T_296) @[Mux.scala 27:72] + node _T_304 = or(_T_303, _T_297) @[Mux.scala 27:72] + node _T_305 = or(_T_304, _T_298) @[Mux.scala 27:72] + node _T_306 = or(_T_305, _T_299) @[Mux.scala 27:72] + node _T_307 = or(_T_306, _T_300) @[Mux.scala 27:72] + wire _T_308 : UInt<31> @[Mux.scala 27:72] + _T_308 <= _T_307 @[Mux.scala 27:72] + node tlu_flush_path_r = mux(_T_258, io.rst_vec, _T_308) @[dec_tlu_ctl.scala 3133:35] + node _T_309 = bits(io.tlu_flush_lower_r, 0, 0) @[lib.scala 8:44] + wire _T_310 : UInt<31> @[lib.scala 648:38] + _T_310 <= UInt<1>("h00") @[lib.scala 648:38] + reg _T_311 : UInt, clock with : (reset => (reset, _T_310)) @[Reg.scala 27:20] + when _T_309 : @[Reg.scala 28:19] + _T_311 <= tlu_flush_path_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.tlu_flush_path_r_d1 <= _T_311 @[dec_tlu_ctl.scala 3144:31] + io.dec_tlu_flush_lower_wb <= io.tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 3146:41] + io.dec_tlu_flush_lower_r <= io.tlu_flush_lower_r @[dec_tlu_ctl.scala 3148:41] + io.dec_tlu_flush_path_r <= tlu_flush_path_r @[dec_tlu_ctl.scala 3149:41] + node _T_312 = or(io.lsu_exc_valid_r, io.i0_exception_valid_r) @[dec_tlu_ctl.scala 3152:53] + node _T_313 = or(_T_312, io.interrupt_valid_r) @[dec_tlu_ctl.scala 3152:79] + node _T_314 = not(io.trigger_hit_dmode_r) @[dec_tlu_ctl.scala 3152:127] + node _T_315 = and(io.i0_trigger_hit_r, _T_314) @[dec_tlu_ctl.scala 3152:125] + node _T_316 = or(_T_313, _T_315) @[dec_tlu_ctl.scala 3152:102] + io.exc_or_int_valid_r <= _T_316 @[dec_tlu_ctl.scala 3152:31] + wire _T_317 : UInt + _T_317 <= UInt<1>("h00") + node _T_318 = xor(io.interrupt_valid_r, _T_317) @[lib.scala 448:21] + node _T_319 = orr(_T_318) @[lib.scala 448:29] + reg _T_320 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_319 : @[Reg.scala 28:19] + _T_320 <= io.interrupt_valid_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_317 <= _T_320 @[lib.scala 451:16] + io.interrupt_valid_r_d1 <= _T_317 @[dec_tlu_ctl.scala 3154:59] + wire _T_321 : UInt + _T_321 <= UInt<1>("h00") + node _T_322 = xor(io.i0_exception_valid_r, _T_321) @[lib.scala 448:21] + node _T_323 = orr(_T_322) @[lib.scala 448:29] + reg _T_324 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_323 : @[Reg.scala 28:19] + _T_324 <= io.i0_exception_valid_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_321 <= _T_324 @[lib.scala 451:16] + io.i0_exception_valid_r_d1 <= _T_321 @[dec_tlu_ctl.scala 3155:51] + wire _T_325 : UInt + _T_325 <= UInt<1>("h00") + node _T_326 = xor(io.exc_or_int_valid_r, _T_325) @[lib.scala 448:21] + node _T_327 = orr(_T_326) @[lib.scala 448:29] + reg _T_328 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_327 : @[Reg.scala 28:19] + _T_328 <= io.exc_or_int_valid_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_325 <= _T_328 @[lib.scala 451:16] + io.exc_or_int_valid_r_d1 <= _T_325 @[dec_tlu_ctl.scala 3156:53] + wire _T_329 : UInt + _T_329 <= UInt<1>("h00") + node _T_330 = xor(io.exc_cause_r, _T_329) @[lib.scala 448:21] + node _T_331 = orr(_T_330) @[lib.scala 448:29] + reg _T_332 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_331 : @[Reg.scala 28:19] + _T_332 <= io.exc_cause_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_329 <= _T_332 @[lib.scala 451:16] + io.exc_cause_wb <= _T_329 @[dec_tlu_ctl.scala 3157:65] + node _T_333 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 3158:104] + node _T_334 = and(io.tlu_i0_commit_cmt, _T_333) @[dec_tlu_ctl.scala 3158:102] + wire _T_335 : UInt + _T_335 <= UInt<1>("h00") + node _T_336 = xor(_T_334, _T_335) @[lib.scala 448:21] + node _T_337 = orr(_T_336) @[lib.scala 448:29] + reg _T_338 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_337 : @[Reg.scala 28:19] + _T_338 <= _T_334 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_335 <= _T_338 @[lib.scala 451:16] + io.i0_valid_wb <= _T_335 @[dec_tlu_ctl.scala 3158:71] + wire _T_339 : UInt + _T_339 <= UInt<1>("h00") + node _T_340 = xor(io.i0_trigger_hit_r, _T_339) @[lib.scala 448:21] + node _T_341 = orr(_T_340) @[lib.scala 448:29] + reg _T_342 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_341 : @[Reg.scala 28:19] + _T_342 <= io.i0_trigger_hit_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_339 <= _T_342 @[lib.scala 451:16] + io.trigger_hit_r_d1 <= _T_339 @[dec_tlu_ctl.scala 3159:63] + wire _T_343 : UInt + _T_343 <= UInt<1>("h00") + node _T_344 = xor(io.take_nmi, _T_343) @[lib.scala 448:21] + node _T_345 = orr(_T_344) @[lib.scala 448:29] + reg _T_346 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_345 : @[Reg.scala 28:19] + _T_346 <= io.take_nmi @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_343 <= _T_346 @[lib.scala 451:16] + io.take_nmi_r_d1 <= _T_343 @[dec_tlu_ctl.scala 3160:73] + wire _T_347 : UInt + _T_347 <= UInt<1>("h00") + node _T_348 = xor(io.pause_expired_r, _T_347) @[lib.scala 448:21] + node _T_349 = orr(_T_348) @[lib.scala 448:29] + reg _T_350 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_349 : @[Reg.scala 28:19] + _T_350 <= io.pause_expired_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_347 <= _T_350 @[lib.scala 451:16] + io.pause_expired_wb <= _T_347 @[dec_tlu_ctl.scala 3161:69] + + module perf_mux_and_flops : + input clock : Clock + input reset : AsyncReset + output io : {mhpmc_inc_r : UInt<1>[4], flip mcountinhibit : UInt<7>, flip mhpme_vec : UInt<10>[4], flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip tlu_i0_commit_cmt : UInt<1>, flip illegal_r : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip exu_pmu_i0_br_misp : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip i0_exception_valid_r : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip lsu_pmu_load_external_r : UInt<1>, flip lsu_pmu_store_external_r : UInt<1>, mstatus : UInt<2>, flip mie : UInt<6>, flip ifu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip i0_trigger_hit_r : UInt<1>, flip lsu_exc_valid_r : UInt<1>, flip take_timer_int : UInt<1>, flip take_int_timer0_int : UInt<1>, flip take_int_timer1_int : UInt<1>, flip take_ext_int : UInt<1>, flip tlu_flush_lower_r : UInt<1>, flip dec_tlu_br0_error_r : UInt<1>, flip rfpc_i0_r : UInt<1>, flip dec_tlu_br0_start_error_r : UInt<1>, mcyclel_cout_f : UInt<1>, minstret_enable_f : UInt<1>, minstretl_cout_f : UInt<1>, fw_halted : UInt<1>, meicidpl : UInt<4>, icache_rd_valid_f : UInt<1>, icache_wr_valid_f : UInt<1>, mhpmc_inc_r_d1 : UInt<1>[4], perfcnt_halted_d1 : UInt<1>, mdseac_locked_f : UInt<1>, lsu_single_ecc_error_r_d1 : UInt<1>, lsu_exc_valid_r_d1 : UInt<1>, lsu_i0_exc_r_d1 : UInt<1>, take_ext_int_start_d1 : UInt<1>, take_ext_int_start_d2 : UInt<1>, take_ext_int_start_d3 : UInt<1>, ext_int_freeze_d1 : UInt<1>, mip : UInt<6>, flip mdseac_locked_ns : UInt<1>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_i0_exc_r : UInt<1>, flip take_ext_int_start : UInt<1>, flip ext_int_freeze : UInt<1>, flip mip_ns : UInt<6>, flip mcyclel_cout : UInt<1>, flip wr_mcycleh_r : UInt<1>, flip mcyclel_cout_in : UInt<1>, flip minstret_enable : UInt<1>, flip minstretl_cout_ns : UInt<1>, flip fw_halted_ns : UInt<1>, flip meicidpl_ns : UInt<4>, flip icache_rd_valid : UInt<1>, flip icache_wr_valid : UInt<1>, flip perfcnt_halted : UInt<1>, flip mstatus_ns : UInt<2>, flip scan_mode : UInt<1>, flip free_l2clk : Clock} + + node _T = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] + node _T_1 = mux(_T, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1) @[dec_tlu_ctl.scala 2795:66] + node _T_2 = bits(io.mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2797:57] + node _T_3 = not(_T_2) @[dec_tlu_ctl.scala 2797:40] + node _T_4 = eq(io.mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2798:42] + node _T_5 = bits(_T_4, 0, 0) @[dec_tlu_ctl.scala 2798:70] + node _T_6 = eq(io.mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2799:42] + node _T_7 = bits(_T_6, 0, 0) @[dec_tlu_ctl.scala 2799:70] + node _T_8 = eq(io.mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2800:42] + node _T_9 = bits(_T_8, 0, 0) @[dec_tlu_ctl.scala 2800:70] + node _T_10 = eq(io.mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2801:42] + node _T_11 = bits(_T_10, 0, 0) @[dec_tlu_ctl.scala 2801:70] + node _T_12 = not(io.illegal_r) @[dec_tlu_ctl.scala 2801:104] + node _T_13 = and(io.tlu_i0_commit_cmt, _T_12) @[dec_tlu_ctl.scala 2801:102] + node _T_14 = eq(io.mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2802:42] + node _T_15 = bits(_T_14, 0, 0) @[dec_tlu_ctl.scala 2802:70] + node _T_16 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2802:104] + node _T_17 = and(io.tlu_i0_commit_cmt, _T_16) @[dec_tlu_ctl.scala 2802:102] + node _T_18 = not(io.illegal_r) @[dec_tlu_ctl.scala 2802:125] + node _T_19 = and(_T_17, _T_18) @[dec_tlu_ctl.scala 2802:123] + node _T_20 = eq(io.mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2803:42] + node _T_21 = bits(_T_20, 0, 0) @[dec_tlu_ctl.scala 2803:70] + node _T_22 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2803:102] + node _T_23 = not(io.illegal_r) @[dec_tlu_ctl.scala 2803:125] + node _T_24 = and(_T_22, _T_23) @[dec_tlu_ctl.scala 2803:123] + node _T_25 = eq(io.mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2805:42] + node _T_26 = bits(_T_25, 0, 0) @[dec_tlu_ctl.scala 2805:70] + node _T_27 = eq(io.mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2806:42] + node _T_28 = bits(_T_27, 0, 0) @[dec_tlu_ctl.scala 2806:70] + node _T_29 = eq(io.mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2807:42] + node _T_30 = bits(_T_29, 0, 0) @[dec_tlu_ctl.scala 2807:70] + node _T_31 = eq(io.mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2808:42] + node _T_32 = bits(_T_31, 0, 0) @[dec_tlu_ctl.scala 2808:70] + node _T_33 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2808:99] + node _T_34 = eq(io.mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2809:42] + node _T_35 = bits(_T_34, 0, 0) @[dec_tlu_ctl.scala 2809:70] + node _T_36 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2809:113] + node _T_37 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2809:138] + node _T_38 = and(_T_36, _T_37) @[dec_tlu_ctl.scala 2809:136] + node _T_39 = eq(io.mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2810:42] + node _T_40 = bits(_T_39, 0, 0) @[dec_tlu_ctl.scala 2810:70] + node _T_41 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2810:99] + node _T_42 = eq(io.mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2811:42] + node _T_43 = bits(_T_42, 0, 0) @[dec_tlu_ctl.scala 2811:70] + node _T_44 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2811:99] + node _T_45 = eq(io.mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2812:42] + node _T_46 = bits(_T_45, 0, 0) @[dec_tlu_ctl.scala 2812:70] + node _T_47 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2812:99] + node _T_48 = and(_T_47, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2812:108] + node _T_49 = eq(io.mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2813:42] + node _T_50 = bits(_T_49, 0, 0) @[dec_tlu_ctl.scala 2813:70] + node _T_51 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2813:99] + node _T_52 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2813:150] + node _T_53 = and(_T_51, _T_52) @[dec_tlu_ctl.scala 2813:109] + node _T_54 = eq(io.mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2815:42] + node _T_55 = bits(_T_54, 0, 0) @[dec_tlu_ctl.scala 2815:67] + node _T_56 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2815:97] + node _T_57 = eq(io.mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2816:42] + node _T_58 = bits(_T_57, 0, 0) @[dec_tlu_ctl.scala 2816:67] + node _T_59 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2816:97] + node _T_60 = eq(io.mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2817:42] + node _T_61 = bits(_T_60, 0, 0) @[dec_tlu_ctl.scala 2817:67] + node _T_62 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2817:97] + node _T_63 = eq(io.mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2818:42] + node _T_64 = bits(_T_63, 0, 0) @[dec_tlu_ctl.scala 2818:67] + node _T_65 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2818:97] + node _T_66 = eq(io.mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2819:42] + node _T_67 = bits(_T_66, 0, 0) @[dec_tlu_ctl.scala 2819:67] + node _T_68 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2819:97] + node _T_69 = eq(io.mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2820:42] + node _T_70 = bits(_T_69, 0, 0) @[dec_tlu_ctl.scala 2820:67] + node _T_71 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2820:97] + node _T_72 = eq(io.mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2821:42] + node _T_73 = bits(_T_72, 0, 0) @[dec_tlu_ctl.scala 2821:67] + node _T_74 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2821:97] + node _T_75 = eq(io.mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2822:42] + node _T_76 = bits(_T_75, 0, 0) @[dec_tlu_ctl.scala 2822:67] + node _T_77 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2822:97] + node _T_78 = eq(io.mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2823:42] + node _T_79 = bits(_T_78, 0, 0) @[dec_tlu_ctl.scala 2823:67] + node _T_80 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2823:97] + node _T_81 = eq(io.mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2824:42] + node _T_82 = bits(_T_81, 0, 0) @[dec_tlu_ctl.scala 2824:67] + node _T_83 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2824:97] + node _T_84 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2824:130] + node _T_85 = or(_T_83, _T_84) @[dec_tlu_ctl.scala 2824:109] + node _T_86 = eq(io.mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2826:42] + node _T_87 = bits(_T_86, 0, 0) @[dec_tlu_ctl.scala 2826:70] + node _T_88 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2826:103] + node _T_89 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2826:128] + node _T_90 = and(_T_88, _T_89) @[dec_tlu_ctl.scala 2826:126] + node _T_91 = eq(io.mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2827:42] + node _T_92 = bits(_T_91, 0, 0) @[dec_tlu_ctl.scala 2827:70] + node _T_93 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2827:105] + node _T_94 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2827:130] + node _T_95 = and(_T_93, _T_94) @[dec_tlu_ctl.scala 2827:128] + node _T_96 = eq(io.mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2828:42] + node _T_97 = bits(_T_96, 0, 0) @[dec_tlu_ctl.scala 2828:70] + node _T_98 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2828:118] + node _T_99 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2828:143] + node _T_100 = and(_T_98, _T_99) @[dec_tlu_ctl.scala 2828:141] + node _T_101 = eq(io.mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2829:42] + node _T_102 = bits(_T_101, 0, 0) @[dec_tlu_ctl.scala 2829:70] + node _T_103 = eq(io.mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2830:42] + node _T_104 = bits(_T_103, 0, 0) @[dec_tlu_ctl.scala 2830:70] + node _T_105 = eq(io.mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2831:42] + node _T_106 = bits(_T_105, 0, 0) @[dec_tlu_ctl.scala 2831:70] + node _T_107 = eq(io.mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2832:42] + node _T_108 = bits(_T_107, 0, 0) @[dec_tlu_ctl.scala 2832:70] + node _T_109 = eq(io.mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2833:42] + node _T_110 = bits(_T_109, 0, 0) @[dec_tlu_ctl.scala 2833:70] + node _T_111 = eq(io.mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2834:42] + node _T_112 = bits(_T_111, 0, 0) @[dec_tlu_ctl.scala 2834:70] + node _T_113 = eq(io.mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2835:42] + node _T_114 = bits(_T_113, 0, 0) @[dec_tlu_ctl.scala 2835:70] + node _T_115 = eq(io.mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2836:42] + node _T_116 = bits(_T_115, 0, 0) @[dec_tlu_ctl.scala 2836:70] + node _T_117 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2836:106] + node _T_118 = or(_T_117, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2836:128] + node _T_119 = eq(io.mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2837:42] + node _T_120 = bits(_T_119, 0, 0) @[dec_tlu_ctl.scala 2837:70] + node _T_121 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2837:100] + node _T_122 = or(_T_121, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2837:125] + node _T_123 = eq(io.mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2838:42] + node _T_124 = bits(_T_123, 0, 0) @[dec_tlu_ctl.scala 2838:70] + node _T_125 = eq(io.mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2839:42] + node _T_126 = bits(_T_125, 0, 0) @[dec_tlu_ctl.scala 2839:70] + node _T_127 = eq(io.mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2840:42] + node _T_128 = bits(_T_127, 0, 0) @[dec_tlu_ctl.scala 2840:70] + node _T_129 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2840:105] + node _T_130 = and(_T_129, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2840:137] + node _T_131 = eq(io.mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2842:42] + node _T_132 = bits(_T_131, 0, 0) @[dec_tlu_ctl.scala 2842:70] + node _T_133 = eq(io.mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2843:42] + node _T_134 = bits(_T_133, 0, 0) @[dec_tlu_ctl.scala 2843:70] + node _T_135 = eq(io.mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2844:42] + node _T_136 = bits(_T_135, 0, 0) @[dec_tlu_ctl.scala 2844:70] + node _T_137 = eq(io.mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2845:42] + node _T_138 = bits(_T_137, 0, 0) @[dec_tlu_ctl.scala 2845:70] + node _T_139 = eq(io.mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2846:42] + node _T_140 = bits(_T_139, 0, 0) @[dec_tlu_ctl.scala 2846:70] + node _T_141 = eq(io.mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2847:42] + node _T_142 = bits(_T_141, 0, 0) @[dec_tlu_ctl.scala 2847:70] + node _T_143 = eq(io.mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2848:42] + node _T_144 = bits(_T_143, 0, 0) @[dec_tlu_ctl.scala 2848:70] + node _T_145 = eq(io.mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2849:42] + node _T_146 = bits(_T_145, 0, 0) @[dec_tlu_ctl.scala 2849:70] + node _T_147 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2849:92] + node _T_148 = bits(_T_147, 0, 0) @[dec_tlu_ctl.scala 2849:92] + node _T_149 = not(_T_148) @[dec_tlu_ctl.scala 2849:81] + node _T_150 = eq(io.mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2850:42] + node _T_151 = bits(_T_150, 0, 0) @[dec_tlu_ctl.scala 2850:70] + node _T_152 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2850:92] + node _T_153 = bits(_T_152, 0, 0) @[dec_tlu_ctl.scala 2850:92] + node _T_154 = not(_T_153) @[dec_tlu_ctl.scala 2850:81] + node _T_155 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2850:115] + node _T_156 = bits(io.mie, 5, 0) @[dec_tlu_ctl.scala 2850:129] + node _T_157 = and(_T_155, _T_156) @[dec_tlu_ctl.scala 2850:121] + node _T_158 = orr(_T_157) @[dec_tlu_ctl.scala 2850:136] + node _T_159 = and(_T_154, _T_158) @[dec_tlu_ctl.scala 2850:106] + node _T_160 = eq(io.mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2851:42] + node _T_161 = bits(_T_160, 0, 0) @[dec_tlu_ctl.scala 2851:70] + node _T_162 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2851:99] + node _T_163 = eq(io.mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2852:42] + node _T_164 = bits(_T_163, 0, 0) @[dec_tlu_ctl.scala 2852:70] + node _T_165 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2852:102] + node _T_166 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2852:133] + node _T_167 = and(_T_165, _T_166) @[dec_tlu_ctl.scala 2852:131] + node _T_168 = eq(io.mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2853:42] + node _T_169 = bits(_T_168, 0, 0) @[dec_tlu_ctl.scala 2853:70] + node _T_170 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2853:102] + node _T_171 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2853:134] + node _T_172 = and(_T_170, _T_171) @[dec_tlu_ctl.scala 2853:132] + node _T_173 = eq(io.mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2855:42] + node _T_174 = bits(_T_173, 0, 0) @[dec_tlu_ctl.scala 2855:70] + node _T_175 = eq(io.mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2856:42] + node _T_176 = bits(_T_175, 0, 0) @[dec_tlu_ctl.scala 2856:70] + node _T_177 = eq(io.mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2857:42] + node _T_178 = bits(_T_177, 0, 0) @[dec_tlu_ctl.scala 2857:70] + node _T_179 = eq(io.mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2858:42] + node _T_180 = bits(_T_179, 0, 0) @[dec_tlu_ctl.scala 2858:70] + node _T_181 = eq(io.mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2859:42] + node _T_182 = bits(_T_181, 0, 0) @[dec_tlu_ctl.scala 2859:70] + node _T_183 = mux(_T_5, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_184 = mux(_T_7, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_185 = mux(_T_9, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_186 = mux(_T_11, _T_13, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_187 = mux(_T_15, _T_19, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_188 = mux(_T_21, _T_24, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_189 = mux(_T_26, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_190 = mux(_T_28, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_191 = mux(_T_30, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_192 = mux(_T_32, _T_33, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_193 = mux(_T_35, _T_38, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_194 = mux(_T_40, _T_41, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_195 = mux(_T_43, _T_44, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_196 = mux(_T_46, _T_48, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_197 = mux(_T_50, _T_53, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_198 = mux(_T_55, _T_56, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_199 = mux(_T_58, _T_59, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_200 = mux(_T_61, _T_62, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_201 = mux(_T_64, _T_65, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_202 = mux(_T_67, _T_68, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_203 = mux(_T_70, _T_71, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_204 = mux(_T_73, _T_74, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_205 = mux(_T_76, _T_77, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_206 = mux(_T_79, _T_80, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_207 = mux(_T_82, _T_85, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_208 = mux(_T_87, _T_90, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_209 = mux(_T_92, _T_95, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_210 = mux(_T_97, _T_100, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_211 = mux(_T_102, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_212 = mux(_T_104, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_213 = mux(_T_106, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_214 = mux(_T_108, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_215 = mux(_T_110, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_216 = mux(_T_112, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_217 = mux(_T_114, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_218 = mux(_T_116, _T_118, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_219 = mux(_T_120, _T_122, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_220 = mux(_T_124, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_221 = mux(_T_126, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_222 = mux(_T_128, _T_130, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_223 = mux(_T_132, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_224 = mux(_T_134, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_225 = mux(_T_136, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_226 = mux(_T_138, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_227 = mux(_T_140, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_228 = mux(_T_142, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_229 = mux(_T_144, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_230 = mux(_T_146, _T_149, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_231 = mux(_T_151, _T_159, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_232 = mux(_T_161, _T_162, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_233 = mux(_T_164, _T_167, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_234 = mux(_T_169, _T_172, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_235 = mux(_T_174, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_236 = mux(_T_176, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_237 = mux(_T_178, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_238 = mux(_T_180, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_239 = mux(_T_182, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_240 = or(_T_183, _T_184) @[Mux.scala 27:72] + node _T_241 = or(_T_240, _T_185) @[Mux.scala 27:72] + node _T_242 = or(_T_241, _T_186) @[Mux.scala 27:72] + node _T_243 = or(_T_242, _T_187) @[Mux.scala 27:72] + node _T_244 = or(_T_243, _T_188) @[Mux.scala 27:72] + node _T_245 = or(_T_244, _T_189) @[Mux.scala 27:72] + node _T_246 = or(_T_245, _T_190) @[Mux.scala 27:72] + node _T_247 = or(_T_246, _T_191) @[Mux.scala 27:72] + node _T_248 = or(_T_247, _T_192) @[Mux.scala 27:72] + node _T_249 = or(_T_248, _T_193) @[Mux.scala 27:72] + node _T_250 = or(_T_249, _T_194) @[Mux.scala 27:72] + node _T_251 = or(_T_250, _T_195) @[Mux.scala 27:72] + node _T_252 = or(_T_251, _T_196) @[Mux.scala 27:72] + node _T_253 = or(_T_252, _T_197) @[Mux.scala 27:72] + node _T_254 = or(_T_253, _T_198) @[Mux.scala 27:72] + node _T_255 = or(_T_254, _T_199) @[Mux.scala 27:72] + node _T_256 = or(_T_255, _T_200) @[Mux.scala 27:72] + node _T_257 = or(_T_256, _T_201) @[Mux.scala 27:72] + node _T_258 = or(_T_257, _T_202) @[Mux.scala 27:72] + node _T_259 = or(_T_258, _T_203) @[Mux.scala 27:72] + node _T_260 = or(_T_259, _T_204) @[Mux.scala 27:72] + node _T_261 = or(_T_260, _T_205) @[Mux.scala 27:72] + node _T_262 = or(_T_261, _T_206) @[Mux.scala 27:72] + node _T_263 = or(_T_262, _T_207) @[Mux.scala 27:72] + node _T_264 = or(_T_263, _T_208) @[Mux.scala 27:72] + node _T_265 = or(_T_264, _T_209) @[Mux.scala 27:72] + node _T_266 = or(_T_265, _T_210) @[Mux.scala 27:72] + node _T_267 = or(_T_266, _T_211) @[Mux.scala 27:72] + node _T_268 = or(_T_267, _T_212) @[Mux.scala 27:72] + node _T_269 = or(_T_268, _T_213) @[Mux.scala 27:72] + node _T_270 = or(_T_269, _T_214) @[Mux.scala 27:72] + node _T_271 = or(_T_270, _T_215) @[Mux.scala 27:72] + node _T_272 = or(_T_271, _T_216) @[Mux.scala 27:72] + node _T_273 = or(_T_272, _T_217) @[Mux.scala 27:72] + node _T_274 = or(_T_273, _T_218) @[Mux.scala 27:72] + node _T_275 = or(_T_274, _T_219) @[Mux.scala 27:72] + node _T_276 = or(_T_275, _T_220) @[Mux.scala 27:72] + node _T_277 = or(_T_276, _T_221) @[Mux.scala 27:72] + node _T_278 = or(_T_277, _T_222) @[Mux.scala 27:72] + node _T_279 = or(_T_278, _T_223) @[Mux.scala 27:72] + node _T_280 = or(_T_279, _T_224) @[Mux.scala 27:72] + node _T_281 = or(_T_280, _T_225) @[Mux.scala 27:72] + node _T_282 = or(_T_281, _T_226) @[Mux.scala 27:72] + node _T_283 = or(_T_282, _T_227) @[Mux.scala 27:72] + node _T_284 = or(_T_283, _T_228) @[Mux.scala 27:72] + node _T_285 = or(_T_284, _T_229) @[Mux.scala 27:72] + node _T_286 = or(_T_285, _T_230) @[Mux.scala 27:72] + node _T_287 = or(_T_286, _T_231) @[Mux.scala 27:72] + node _T_288 = or(_T_287, _T_232) @[Mux.scala 27:72] + node _T_289 = or(_T_288, _T_233) @[Mux.scala 27:72] + node _T_290 = or(_T_289, _T_234) @[Mux.scala 27:72] + node _T_291 = or(_T_290, _T_235) @[Mux.scala 27:72] + node _T_292 = or(_T_291, _T_236) @[Mux.scala 27:72] + node _T_293 = or(_T_292, _T_237) @[Mux.scala 27:72] + node _T_294 = or(_T_293, _T_238) @[Mux.scala 27:72] + node _T_295 = or(_T_294, _T_239) @[Mux.scala 27:72] + wire _T_296 : UInt<1> @[Mux.scala 27:72] + _T_296 <= _T_295 @[Mux.scala 27:72] + node _T_297 = and(_T_3, _T_296) @[dec_tlu_ctl.scala 2797:63] + io.mhpmc_inc_r[0] <= _T_297 @[dec_tlu_ctl.scala 2797:35] + node _T_298 = bits(io.mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2797:57] + node _T_299 = not(_T_298) @[dec_tlu_ctl.scala 2797:40] + node _T_300 = eq(io.mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2798:42] + node _T_301 = bits(_T_300, 0, 0) @[dec_tlu_ctl.scala 2798:70] + node _T_302 = eq(io.mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2799:42] + node _T_303 = bits(_T_302, 0, 0) @[dec_tlu_ctl.scala 2799:70] + node _T_304 = eq(io.mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2800:42] + node _T_305 = bits(_T_304, 0, 0) @[dec_tlu_ctl.scala 2800:70] + node _T_306 = eq(io.mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2801:42] + node _T_307 = bits(_T_306, 0, 0) @[dec_tlu_ctl.scala 2801:70] + node _T_308 = not(io.illegal_r) @[dec_tlu_ctl.scala 2801:104] + node _T_309 = and(io.tlu_i0_commit_cmt, _T_308) @[dec_tlu_ctl.scala 2801:102] + node _T_310 = eq(io.mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2802:42] + node _T_311 = bits(_T_310, 0, 0) @[dec_tlu_ctl.scala 2802:70] + node _T_312 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2802:104] + node _T_313 = and(io.tlu_i0_commit_cmt, _T_312) @[dec_tlu_ctl.scala 2802:102] + node _T_314 = not(io.illegal_r) @[dec_tlu_ctl.scala 2802:125] + node _T_315 = and(_T_313, _T_314) @[dec_tlu_ctl.scala 2802:123] + node _T_316 = eq(io.mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2803:42] + node _T_317 = bits(_T_316, 0, 0) @[dec_tlu_ctl.scala 2803:70] + node _T_318 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2803:102] + node _T_319 = not(io.illegal_r) @[dec_tlu_ctl.scala 2803:125] + node _T_320 = and(_T_318, _T_319) @[dec_tlu_ctl.scala 2803:123] + node _T_321 = eq(io.mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2805:42] + node _T_322 = bits(_T_321, 0, 0) @[dec_tlu_ctl.scala 2805:70] + node _T_323 = eq(io.mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2806:42] + node _T_324 = bits(_T_323, 0, 0) @[dec_tlu_ctl.scala 2806:70] + node _T_325 = eq(io.mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2807:42] + node _T_326 = bits(_T_325, 0, 0) @[dec_tlu_ctl.scala 2807:70] + node _T_327 = eq(io.mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2808:42] + node _T_328 = bits(_T_327, 0, 0) @[dec_tlu_ctl.scala 2808:70] + node _T_329 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2808:99] + node _T_330 = eq(io.mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2809:42] + node _T_331 = bits(_T_330, 0, 0) @[dec_tlu_ctl.scala 2809:70] + node _T_332 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2809:113] + node _T_333 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2809:138] + node _T_334 = and(_T_332, _T_333) @[dec_tlu_ctl.scala 2809:136] + node _T_335 = eq(io.mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2810:42] + node _T_336 = bits(_T_335, 0, 0) @[dec_tlu_ctl.scala 2810:70] + node _T_337 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2810:99] + node _T_338 = eq(io.mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2811:42] + node _T_339 = bits(_T_338, 0, 0) @[dec_tlu_ctl.scala 2811:70] + node _T_340 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2811:99] + node _T_341 = eq(io.mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2812:42] + node _T_342 = bits(_T_341, 0, 0) @[dec_tlu_ctl.scala 2812:70] + node _T_343 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2812:99] + node _T_344 = and(_T_343, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2812:108] + node _T_345 = eq(io.mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2813:42] + node _T_346 = bits(_T_345, 0, 0) @[dec_tlu_ctl.scala 2813:70] + node _T_347 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2813:99] + node _T_348 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2813:150] + node _T_349 = and(_T_347, _T_348) @[dec_tlu_ctl.scala 2813:109] + node _T_350 = eq(io.mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2815:42] + node _T_351 = bits(_T_350, 0, 0) @[dec_tlu_ctl.scala 2815:67] + node _T_352 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2815:97] + node _T_353 = eq(io.mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2816:42] + node _T_354 = bits(_T_353, 0, 0) @[dec_tlu_ctl.scala 2816:67] + node _T_355 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2816:97] + node _T_356 = eq(io.mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2817:42] + node _T_357 = bits(_T_356, 0, 0) @[dec_tlu_ctl.scala 2817:67] + node _T_358 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2817:97] + node _T_359 = eq(io.mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2818:42] + node _T_360 = bits(_T_359, 0, 0) @[dec_tlu_ctl.scala 2818:67] + node _T_361 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2818:97] + node _T_362 = eq(io.mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2819:42] + node _T_363 = bits(_T_362, 0, 0) @[dec_tlu_ctl.scala 2819:67] + node _T_364 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2819:97] + node _T_365 = eq(io.mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2820:42] + node _T_366 = bits(_T_365, 0, 0) @[dec_tlu_ctl.scala 2820:67] + node _T_367 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2820:97] + node _T_368 = eq(io.mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2821:42] + node _T_369 = bits(_T_368, 0, 0) @[dec_tlu_ctl.scala 2821:67] + node _T_370 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2821:97] + node _T_371 = eq(io.mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2822:42] + node _T_372 = bits(_T_371, 0, 0) @[dec_tlu_ctl.scala 2822:67] + node _T_373 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2822:97] + node _T_374 = eq(io.mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2823:42] + node _T_375 = bits(_T_374, 0, 0) @[dec_tlu_ctl.scala 2823:67] + node _T_376 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2823:97] + node _T_377 = eq(io.mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2824:42] + node _T_378 = bits(_T_377, 0, 0) @[dec_tlu_ctl.scala 2824:67] + node _T_379 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2824:97] + node _T_380 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2824:130] + node _T_381 = or(_T_379, _T_380) @[dec_tlu_ctl.scala 2824:109] + node _T_382 = eq(io.mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2826:42] + node _T_383 = bits(_T_382, 0, 0) @[dec_tlu_ctl.scala 2826:70] + node _T_384 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2826:103] + node _T_385 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2826:128] + node _T_386 = and(_T_384, _T_385) @[dec_tlu_ctl.scala 2826:126] + node _T_387 = eq(io.mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2827:42] + node _T_388 = bits(_T_387, 0, 0) @[dec_tlu_ctl.scala 2827:70] + node _T_389 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2827:105] + node _T_390 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2827:130] + node _T_391 = and(_T_389, _T_390) @[dec_tlu_ctl.scala 2827:128] + node _T_392 = eq(io.mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2828:42] + node _T_393 = bits(_T_392, 0, 0) @[dec_tlu_ctl.scala 2828:70] + node _T_394 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2828:118] + node _T_395 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2828:143] + node _T_396 = and(_T_394, _T_395) @[dec_tlu_ctl.scala 2828:141] + node _T_397 = eq(io.mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2829:42] + node _T_398 = bits(_T_397, 0, 0) @[dec_tlu_ctl.scala 2829:70] + node _T_399 = eq(io.mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2830:42] + node _T_400 = bits(_T_399, 0, 0) @[dec_tlu_ctl.scala 2830:70] + node _T_401 = eq(io.mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2831:42] + node _T_402 = bits(_T_401, 0, 0) @[dec_tlu_ctl.scala 2831:70] + node _T_403 = eq(io.mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2832:42] + node _T_404 = bits(_T_403, 0, 0) @[dec_tlu_ctl.scala 2832:70] + node _T_405 = eq(io.mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2833:42] + node _T_406 = bits(_T_405, 0, 0) @[dec_tlu_ctl.scala 2833:70] + node _T_407 = eq(io.mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2834:42] + node _T_408 = bits(_T_407, 0, 0) @[dec_tlu_ctl.scala 2834:70] + node _T_409 = eq(io.mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2835:42] + node _T_410 = bits(_T_409, 0, 0) @[dec_tlu_ctl.scala 2835:70] + node _T_411 = eq(io.mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2836:42] + node _T_412 = bits(_T_411, 0, 0) @[dec_tlu_ctl.scala 2836:70] + node _T_413 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2836:106] + node _T_414 = or(_T_413, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2836:128] + node _T_415 = eq(io.mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2837:42] + node _T_416 = bits(_T_415, 0, 0) @[dec_tlu_ctl.scala 2837:70] + node _T_417 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2837:100] + node _T_418 = or(_T_417, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2837:125] + node _T_419 = eq(io.mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2838:42] + node _T_420 = bits(_T_419, 0, 0) @[dec_tlu_ctl.scala 2838:70] + node _T_421 = eq(io.mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2839:42] + node _T_422 = bits(_T_421, 0, 0) @[dec_tlu_ctl.scala 2839:70] + node _T_423 = eq(io.mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2840:42] + node _T_424 = bits(_T_423, 0, 0) @[dec_tlu_ctl.scala 2840:70] + node _T_425 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2840:105] + node _T_426 = and(_T_425, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2840:137] + node _T_427 = eq(io.mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2842:42] + node _T_428 = bits(_T_427, 0, 0) @[dec_tlu_ctl.scala 2842:70] + node _T_429 = eq(io.mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2843:42] + node _T_430 = bits(_T_429, 0, 0) @[dec_tlu_ctl.scala 2843:70] + node _T_431 = eq(io.mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2844:42] + node _T_432 = bits(_T_431, 0, 0) @[dec_tlu_ctl.scala 2844:70] + node _T_433 = eq(io.mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2845:42] + node _T_434 = bits(_T_433, 0, 0) @[dec_tlu_ctl.scala 2845:70] + node _T_435 = eq(io.mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2846:42] + node _T_436 = bits(_T_435, 0, 0) @[dec_tlu_ctl.scala 2846:70] + node _T_437 = eq(io.mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2847:42] + node _T_438 = bits(_T_437, 0, 0) @[dec_tlu_ctl.scala 2847:70] + node _T_439 = eq(io.mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2848:42] + node _T_440 = bits(_T_439, 0, 0) @[dec_tlu_ctl.scala 2848:70] + node _T_441 = eq(io.mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2849:42] + node _T_442 = bits(_T_441, 0, 0) @[dec_tlu_ctl.scala 2849:70] + node _T_443 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2849:92] + node _T_444 = bits(_T_443, 0, 0) @[dec_tlu_ctl.scala 2849:92] + node _T_445 = not(_T_444) @[dec_tlu_ctl.scala 2849:81] + node _T_446 = eq(io.mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2850:42] + node _T_447 = bits(_T_446, 0, 0) @[dec_tlu_ctl.scala 2850:70] + node _T_448 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2850:92] + node _T_449 = bits(_T_448, 0, 0) @[dec_tlu_ctl.scala 2850:92] + node _T_450 = not(_T_449) @[dec_tlu_ctl.scala 2850:81] + node _T_451 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2850:115] + node _T_452 = bits(io.mie, 5, 0) @[dec_tlu_ctl.scala 2850:129] + node _T_453 = and(_T_451, _T_452) @[dec_tlu_ctl.scala 2850:121] + node _T_454 = orr(_T_453) @[dec_tlu_ctl.scala 2850:136] + node _T_455 = and(_T_450, _T_454) @[dec_tlu_ctl.scala 2850:106] + node _T_456 = eq(io.mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2851:42] + node _T_457 = bits(_T_456, 0, 0) @[dec_tlu_ctl.scala 2851:70] + node _T_458 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2851:99] + node _T_459 = eq(io.mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2852:42] + node _T_460 = bits(_T_459, 0, 0) @[dec_tlu_ctl.scala 2852:70] + node _T_461 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2852:102] + node _T_462 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2852:133] + node _T_463 = and(_T_461, _T_462) @[dec_tlu_ctl.scala 2852:131] + node _T_464 = eq(io.mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2853:42] + node _T_465 = bits(_T_464, 0, 0) @[dec_tlu_ctl.scala 2853:70] + node _T_466 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2853:102] + node _T_467 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2853:134] + node _T_468 = and(_T_466, _T_467) @[dec_tlu_ctl.scala 2853:132] + node _T_469 = eq(io.mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2855:42] + node _T_470 = bits(_T_469, 0, 0) @[dec_tlu_ctl.scala 2855:70] + node _T_471 = eq(io.mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2856:42] + node _T_472 = bits(_T_471, 0, 0) @[dec_tlu_ctl.scala 2856:70] + node _T_473 = eq(io.mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2857:42] + node _T_474 = bits(_T_473, 0, 0) @[dec_tlu_ctl.scala 2857:70] + node _T_475 = eq(io.mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2858:42] + node _T_476 = bits(_T_475, 0, 0) @[dec_tlu_ctl.scala 2858:70] + node _T_477 = eq(io.mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2859:42] + node _T_478 = bits(_T_477, 0, 0) @[dec_tlu_ctl.scala 2859:70] + node _T_479 = mux(_T_301, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_480 = mux(_T_303, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_481 = mux(_T_305, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_482 = mux(_T_307, _T_309, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_483 = mux(_T_311, _T_315, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_484 = mux(_T_317, _T_320, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_485 = mux(_T_322, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_486 = mux(_T_324, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_487 = mux(_T_326, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_488 = mux(_T_328, _T_329, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_489 = mux(_T_331, _T_334, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_490 = mux(_T_336, _T_337, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_491 = mux(_T_339, _T_340, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_492 = mux(_T_342, _T_344, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_493 = mux(_T_346, _T_349, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_494 = mux(_T_351, _T_352, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_495 = mux(_T_354, _T_355, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_496 = mux(_T_357, _T_358, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_497 = mux(_T_360, _T_361, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_498 = mux(_T_363, _T_364, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_499 = mux(_T_366, _T_367, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_500 = mux(_T_369, _T_370, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_501 = mux(_T_372, _T_373, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_502 = mux(_T_375, _T_376, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_503 = mux(_T_378, _T_381, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_504 = mux(_T_383, _T_386, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_505 = mux(_T_388, _T_391, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_506 = mux(_T_393, _T_396, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_507 = mux(_T_398, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_508 = mux(_T_400, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_509 = mux(_T_402, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_510 = mux(_T_404, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_511 = mux(_T_406, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_512 = mux(_T_408, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_513 = mux(_T_410, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_514 = mux(_T_412, _T_414, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_515 = mux(_T_416, _T_418, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_516 = mux(_T_420, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_517 = mux(_T_422, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_518 = mux(_T_424, _T_426, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_519 = mux(_T_428, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_520 = mux(_T_430, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_521 = mux(_T_432, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_522 = mux(_T_434, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_523 = mux(_T_436, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_524 = mux(_T_438, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_525 = mux(_T_440, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_526 = mux(_T_442, _T_445, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_527 = mux(_T_447, _T_455, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_528 = mux(_T_457, _T_458, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_529 = mux(_T_460, _T_463, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_530 = mux(_T_465, _T_468, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_531 = mux(_T_470, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_532 = mux(_T_472, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_533 = mux(_T_474, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_534 = mux(_T_476, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_535 = mux(_T_478, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_536 = or(_T_479, _T_480) @[Mux.scala 27:72] + node _T_537 = or(_T_536, _T_481) @[Mux.scala 27:72] + node _T_538 = or(_T_537, _T_482) @[Mux.scala 27:72] + node _T_539 = or(_T_538, _T_483) @[Mux.scala 27:72] + node _T_540 = or(_T_539, _T_484) @[Mux.scala 27:72] + node _T_541 = or(_T_540, _T_485) @[Mux.scala 27:72] + node _T_542 = or(_T_541, _T_486) @[Mux.scala 27:72] + node _T_543 = or(_T_542, _T_487) @[Mux.scala 27:72] + node _T_544 = or(_T_543, _T_488) @[Mux.scala 27:72] + node _T_545 = or(_T_544, _T_489) @[Mux.scala 27:72] + node _T_546 = or(_T_545, _T_490) @[Mux.scala 27:72] + node _T_547 = or(_T_546, _T_491) @[Mux.scala 27:72] + node _T_548 = or(_T_547, _T_492) @[Mux.scala 27:72] + node _T_549 = or(_T_548, _T_493) @[Mux.scala 27:72] + node _T_550 = or(_T_549, _T_494) @[Mux.scala 27:72] + node _T_551 = or(_T_550, _T_495) @[Mux.scala 27:72] + node _T_552 = or(_T_551, _T_496) @[Mux.scala 27:72] + node _T_553 = or(_T_552, _T_497) @[Mux.scala 27:72] + node _T_554 = or(_T_553, _T_498) @[Mux.scala 27:72] + node _T_555 = or(_T_554, _T_499) @[Mux.scala 27:72] + node _T_556 = or(_T_555, _T_500) @[Mux.scala 27:72] + node _T_557 = or(_T_556, _T_501) @[Mux.scala 27:72] + node _T_558 = or(_T_557, _T_502) @[Mux.scala 27:72] + node _T_559 = or(_T_558, _T_503) @[Mux.scala 27:72] + node _T_560 = or(_T_559, _T_504) @[Mux.scala 27:72] + node _T_561 = or(_T_560, _T_505) @[Mux.scala 27:72] + node _T_562 = or(_T_561, _T_506) @[Mux.scala 27:72] + node _T_563 = or(_T_562, _T_507) @[Mux.scala 27:72] + node _T_564 = or(_T_563, _T_508) @[Mux.scala 27:72] + node _T_565 = or(_T_564, _T_509) @[Mux.scala 27:72] + node _T_566 = or(_T_565, _T_510) @[Mux.scala 27:72] + node _T_567 = or(_T_566, _T_511) @[Mux.scala 27:72] + node _T_568 = or(_T_567, _T_512) @[Mux.scala 27:72] + node _T_569 = or(_T_568, _T_513) @[Mux.scala 27:72] + node _T_570 = or(_T_569, _T_514) @[Mux.scala 27:72] + node _T_571 = or(_T_570, _T_515) @[Mux.scala 27:72] + node _T_572 = or(_T_571, _T_516) @[Mux.scala 27:72] + node _T_573 = or(_T_572, _T_517) @[Mux.scala 27:72] + node _T_574 = or(_T_573, _T_518) @[Mux.scala 27:72] + node _T_575 = or(_T_574, _T_519) @[Mux.scala 27:72] + node _T_576 = or(_T_575, _T_520) @[Mux.scala 27:72] + node _T_577 = or(_T_576, _T_521) @[Mux.scala 27:72] + node _T_578 = or(_T_577, _T_522) @[Mux.scala 27:72] + node _T_579 = or(_T_578, _T_523) @[Mux.scala 27:72] + node _T_580 = or(_T_579, _T_524) @[Mux.scala 27:72] + node _T_581 = or(_T_580, _T_525) @[Mux.scala 27:72] + node _T_582 = or(_T_581, _T_526) @[Mux.scala 27:72] + node _T_583 = or(_T_582, _T_527) @[Mux.scala 27:72] + node _T_584 = or(_T_583, _T_528) @[Mux.scala 27:72] + node _T_585 = or(_T_584, _T_529) @[Mux.scala 27:72] + node _T_586 = or(_T_585, _T_530) @[Mux.scala 27:72] + node _T_587 = or(_T_586, _T_531) @[Mux.scala 27:72] + node _T_588 = or(_T_587, _T_532) @[Mux.scala 27:72] + node _T_589 = or(_T_588, _T_533) @[Mux.scala 27:72] + node _T_590 = or(_T_589, _T_534) @[Mux.scala 27:72] + node _T_591 = or(_T_590, _T_535) @[Mux.scala 27:72] + wire _T_592 : UInt<1> @[Mux.scala 27:72] + _T_592 <= _T_591 @[Mux.scala 27:72] + node _T_593 = and(_T_299, _T_592) @[dec_tlu_ctl.scala 2797:63] + io.mhpmc_inc_r[1] <= _T_593 @[dec_tlu_ctl.scala 2797:35] + node _T_594 = bits(io.mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2797:57] + node _T_595 = not(_T_594) @[dec_tlu_ctl.scala 2797:40] + node _T_596 = eq(io.mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2798:42] + node _T_597 = bits(_T_596, 0, 0) @[dec_tlu_ctl.scala 2798:70] + node _T_598 = eq(io.mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2799:42] + node _T_599 = bits(_T_598, 0, 0) @[dec_tlu_ctl.scala 2799:70] + node _T_600 = eq(io.mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2800:42] + node _T_601 = bits(_T_600, 0, 0) @[dec_tlu_ctl.scala 2800:70] + node _T_602 = eq(io.mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2801:42] + node _T_603 = bits(_T_602, 0, 0) @[dec_tlu_ctl.scala 2801:70] + node _T_604 = not(io.illegal_r) @[dec_tlu_ctl.scala 2801:104] + node _T_605 = and(io.tlu_i0_commit_cmt, _T_604) @[dec_tlu_ctl.scala 2801:102] + node _T_606 = eq(io.mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2802:42] + node _T_607 = bits(_T_606, 0, 0) @[dec_tlu_ctl.scala 2802:70] + node _T_608 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2802:104] + node _T_609 = and(io.tlu_i0_commit_cmt, _T_608) @[dec_tlu_ctl.scala 2802:102] + node _T_610 = not(io.illegal_r) @[dec_tlu_ctl.scala 2802:125] + node _T_611 = and(_T_609, _T_610) @[dec_tlu_ctl.scala 2802:123] + node _T_612 = eq(io.mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2803:42] + node _T_613 = bits(_T_612, 0, 0) @[dec_tlu_ctl.scala 2803:70] + node _T_614 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2803:102] + node _T_615 = not(io.illegal_r) @[dec_tlu_ctl.scala 2803:125] + node _T_616 = and(_T_614, _T_615) @[dec_tlu_ctl.scala 2803:123] + node _T_617 = eq(io.mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2805:42] + node _T_618 = bits(_T_617, 0, 0) @[dec_tlu_ctl.scala 2805:70] + node _T_619 = eq(io.mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2806:42] + node _T_620 = bits(_T_619, 0, 0) @[dec_tlu_ctl.scala 2806:70] + node _T_621 = eq(io.mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2807:42] + node _T_622 = bits(_T_621, 0, 0) @[dec_tlu_ctl.scala 2807:70] + node _T_623 = eq(io.mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2808:42] + node _T_624 = bits(_T_623, 0, 0) @[dec_tlu_ctl.scala 2808:70] + node _T_625 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2808:99] + node _T_626 = eq(io.mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2809:42] + node _T_627 = bits(_T_626, 0, 0) @[dec_tlu_ctl.scala 2809:70] + node _T_628 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2809:113] + node _T_629 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2809:138] + node _T_630 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 2809:136] + node _T_631 = eq(io.mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2810:42] + node _T_632 = bits(_T_631, 0, 0) @[dec_tlu_ctl.scala 2810:70] + node _T_633 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2810:99] + node _T_634 = eq(io.mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2811:42] + node _T_635 = bits(_T_634, 0, 0) @[dec_tlu_ctl.scala 2811:70] + node _T_636 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2811:99] + node _T_637 = eq(io.mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2812:42] + node _T_638 = bits(_T_637, 0, 0) @[dec_tlu_ctl.scala 2812:70] + node _T_639 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2812:99] + node _T_640 = and(_T_639, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2812:108] + node _T_641 = eq(io.mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2813:42] + node _T_642 = bits(_T_641, 0, 0) @[dec_tlu_ctl.scala 2813:70] + node _T_643 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2813:99] + node _T_644 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2813:150] + node _T_645 = and(_T_643, _T_644) @[dec_tlu_ctl.scala 2813:109] + node _T_646 = eq(io.mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2815:42] + node _T_647 = bits(_T_646, 0, 0) @[dec_tlu_ctl.scala 2815:67] + node _T_648 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2815:97] + node _T_649 = eq(io.mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2816:42] + node _T_650 = bits(_T_649, 0, 0) @[dec_tlu_ctl.scala 2816:67] + node _T_651 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2816:97] + node _T_652 = eq(io.mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2817:42] + node _T_653 = bits(_T_652, 0, 0) @[dec_tlu_ctl.scala 2817:67] + node _T_654 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2817:97] + node _T_655 = eq(io.mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2818:42] + node _T_656 = bits(_T_655, 0, 0) @[dec_tlu_ctl.scala 2818:67] + node _T_657 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2818:97] + node _T_658 = eq(io.mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2819:42] + node _T_659 = bits(_T_658, 0, 0) @[dec_tlu_ctl.scala 2819:67] + node _T_660 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2819:97] + node _T_661 = eq(io.mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2820:42] + node _T_662 = bits(_T_661, 0, 0) @[dec_tlu_ctl.scala 2820:67] + node _T_663 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2820:97] + node _T_664 = eq(io.mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2821:42] + node _T_665 = bits(_T_664, 0, 0) @[dec_tlu_ctl.scala 2821:67] + node _T_666 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2821:97] + node _T_667 = eq(io.mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2822:42] + node _T_668 = bits(_T_667, 0, 0) @[dec_tlu_ctl.scala 2822:67] + node _T_669 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2822:97] + node _T_670 = eq(io.mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2823:42] + node _T_671 = bits(_T_670, 0, 0) @[dec_tlu_ctl.scala 2823:67] + node _T_672 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2823:97] + node _T_673 = eq(io.mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2824:42] + node _T_674 = bits(_T_673, 0, 0) @[dec_tlu_ctl.scala 2824:67] + node _T_675 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2824:97] + node _T_676 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2824:130] + node _T_677 = or(_T_675, _T_676) @[dec_tlu_ctl.scala 2824:109] + node _T_678 = eq(io.mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2826:42] + node _T_679 = bits(_T_678, 0, 0) @[dec_tlu_ctl.scala 2826:70] + node _T_680 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2826:103] + node _T_681 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2826:128] + node _T_682 = and(_T_680, _T_681) @[dec_tlu_ctl.scala 2826:126] + node _T_683 = eq(io.mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2827:42] + node _T_684 = bits(_T_683, 0, 0) @[dec_tlu_ctl.scala 2827:70] + node _T_685 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2827:105] + node _T_686 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2827:130] + node _T_687 = and(_T_685, _T_686) @[dec_tlu_ctl.scala 2827:128] + node _T_688 = eq(io.mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2828:42] + node _T_689 = bits(_T_688, 0, 0) @[dec_tlu_ctl.scala 2828:70] + node _T_690 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2828:118] + node _T_691 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2828:143] + node _T_692 = and(_T_690, _T_691) @[dec_tlu_ctl.scala 2828:141] + node _T_693 = eq(io.mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2829:42] + node _T_694 = bits(_T_693, 0, 0) @[dec_tlu_ctl.scala 2829:70] + node _T_695 = eq(io.mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2830:42] + node _T_696 = bits(_T_695, 0, 0) @[dec_tlu_ctl.scala 2830:70] + node _T_697 = eq(io.mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2831:42] + node _T_698 = bits(_T_697, 0, 0) @[dec_tlu_ctl.scala 2831:70] + node _T_699 = eq(io.mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2832:42] + node _T_700 = bits(_T_699, 0, 0) @[dec_tlu_ctl.scala 2832:70] + node _T_701 = eq(io.mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2833:42] + node _T_702 = bits(_T_701, 0, 0) @[dec_tlu_ctl.scala 2833:70] + node _T_703 = eq(io.mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2834:42] + node _T_704 = bits(_T_703, 0, 0) @[dec_tlu_ctl.scala 2834:70] + node _T_705 = eq(io.mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2835:42] + node _T_706 = bits(_T_705, 0, 0) @[dec_tlu_ctl.scala 2835:70] + node _T_707 = eq(io.mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2836:42] + node _T_708 = bits(_T_707, 0, 0) @[dec_tlu_ctl.scala 2836:70] + node _T_709 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2836:106] + node _T_710 = or(_T_709, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2836:128] + node _T_711 = eq(io.mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2837:42] + node _T_712 = bits(_T_711, 0, 0) @[dec_tlu_ctl.scala 2837:70] + node _T_713 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2837:100] + node _T_714 = or(_T_713, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2837:125] + node _T_715 = eq(io.mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2838:42] + node _T_716 = bits(_T_715, 0, 0) @[dec_tlu_ctl.scala 2838:70] + node _T_717 = eq(io.mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2839:42] + node _T_718 = bits(_T_717, 0, 0) @[dec_tlu_ctl.scala 2839:70] + node _T_719 = eq(io.mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2840:42] + node _T_720 = bits(_T_719, 0, 0) @[dec_tlu_ctl.scala 2840:70] + node _T_721 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2840:105] + node _T_722 = and(_T_721, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2840:137] + node _T_723 = eq(io.mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2842:42] + node _T_724 = bits(_T_723, 0, 0) @[dec_tlu_ctl.scala 2842:70] + node _T_725 = eq(io.mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2843:42] + node _T_726 = bits(_T_725, 0, 0) @[dec_tlu_ctl.scala 2843:70] + node _T_727 = eq(io.mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2844:42] + node _T_728 = bits(_T_727, 0, 0) @[dec_tlu_ctl.scala 2844:70] + node _T_729 = eq(io.mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2845:42] + node _T_730 = bits(_T_729, 0, 0) @[dec_tlu_ctl.scala 2845:70] + node _T_731 = eq(io.mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2846:42] + node _T_732 = bits(_T_731, 0, 0) @[dec_tlu_ctl.scala 2846:70] + node _T_733 = eq(io.mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2847:42] + node _T_734 = bits(_T_733, 0, 0) @[dec_tlu_ctl.scala 2847:70] + node _T_735 = eq(io.mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2848:42] + node _T_736 = bits(_T_735, 0, 0) @[dec_tlu_ctl.scala 2848:70] + node _T_737 = eq(io.mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2849:42] + node _T_738 = bits(_T_737, 0, 0) @[dec_tlu_ctl.scala 2849:70] + node _T_739 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2849:92] + node _T_740 = bits(_T_739, 0, 0) @[dec_tlu_ctl.scala 2849:92] + node _T_741 = not(_T_740) @[dec_tlu_ctl.scala 2849:81] + node _T_742 = eq(io.mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2850:42] + node _T_743 = bits(_T_742, 0, 0) @[dec_tlu_ctl.scala 2850:70] + node _T_744 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2850:92] + node _T_745 = bits(_T_744, 0, 0) @[dec_tlu_ctl.scala 2850:92] + node _T_746 = not(_T_745) @[dec_tlu_ctl.scala 2850:81] + node _T_747 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2850:115] + node _T_748 = bits(io.mie, 5, 0) @[dec_tlu_ctl.scala 2850:129] + node _T_749 = and(_T_747, _T_748) @[dec_tlu_ctl.scala 2850:121] + node _T_750 = orr(_T_749) @[dec_tlu_ctl.scala 2850:136] + node _T_751 = and(_T_746, _T_750) @[dec_tlu_ctl.scala 2850:106] + node _T_752 = eq(io.mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2851:42] + node _T_753 = bits(_T_752, 0, 0) @[dec_tlu_ctl.scala 2851:70] + node _T_754 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2851:99] + node _T_755 = eq(io.mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2852:42] + node _T_756 = bits(_T_755, 0, 0) @[dec_tlu_ctl.scala 2852:70] + node _T_757 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2852:102] + node _T_758 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2852:133] + node _T_759 = and(_T_757, _T_758) @[dec_tlu_ctl.scala 2852:131] + node _T_760 = eq(io.mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2853:42] + node _T_761 = bits(_T_760, 0, 0) @[dec_tlu_ctl.scala 2853:70] + node _T_762 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2853:102] + node _T_763 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2853:134] + node _T_764 = and(_T_762, _T_763) @[dec_tlu_ctl.scala 2853:132] + node _T_765 = eq(io.mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2855:42] + node _T_766 = bits(_T_765, 0, 0) @[dec_tlu_ctl.scala 2855:70] + node _T_767 = eq(io.mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2856:42] + node _T_768 = bits(_T_767, 0, 0) @[dec_tlu_ctl.scala 2856:70] + node _T_769 = eq(io.mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2857:42] + node _T_770 = bits(_T_769, 0, 0) @[dec_tlu_ctl.scala 2857:70] + node _T_771 = eq(io.mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2858:42] + node _T_772 = bits(_T_771, 0, 0) @[dec_tlu_ctl.scala 2858:70] + node _T_773 = eq(io.mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2859:42] + node _T_774 = bits(_T_773, 0, 0) @[dec_tlu_ctl.scala 2859:70] + node _T_775 = mux(_T_597, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_776 = mux(_T_599, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_777 = mux(_T_601, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_778 = mux(_T_603, _T_605, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_779 = mux(_T_607, _T_611, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_780 = mux(_T_613, _T_616, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_781 = mux(_T_618, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_782 = mux(_T_620, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_783 = mux(_T_622, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_784 = mux(_T_624, _T_625, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_785 = mux(_T_627, _T_630, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_786 = mux(_T_632, _T_633, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_787 = mux(_T_635, _T_636, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_788 = mux(_T_638, _T_640, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_789 = mux(_T_642, _T_645, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_790 = mux(_T_647, _T_648, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_791 = mux(_T_650, _T_651, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_792 = mux(_T_653, _T_654, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_793 = mux(_T_656, _T_657, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_794 = mux(_T_659, _T_660, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_795 = mux(_T_662, _T_663, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_796 = mux(_T_665, _T_666, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_797 = mux(_T_668, _T_669, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_798 = mux(_T_671, _T_672, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_799 = mux(_T_674, _T_677, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_800 = mux(_T_679, _T_682, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_801 = mux(_T_684, _T_687, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_802 = mux(_T_689, _T_692, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_803 = mux(_T_694, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_804 = mux(_T_696, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_805 = mux(_T_698, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_806 = mux(_T_700, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_807 = mux(_T_702, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_808 = mux(_T_704, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_809 = mux(_T_706, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_810 = mux(_T_708, _T_710, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_811 = mux(_T_712, _T_714, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_812 = mux(_T_716, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_813 = mux(_T_718, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_814 = mux(_T_720, _T_722, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_815 = mux(_T_724, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_816 = mux(_T_726, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_817 = mux(_T_728, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_818 = mux(_T_730, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_819 = mux(_T_732, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_820 = mux(_T_734, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_821 = mux(_T_736, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_822 = mux(_T_738, _T_741, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_823 = mux(_T_743, _T_751, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_824 = mux(_T_753, _T_754, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_825 = mux(_T_756, _T_759, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_826 = mux(_T_761, _T_764, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_827 = mux(_T_766, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_828 = mux(_T_768, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_829 = mux(_T_770, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_830 = mux(_T_772, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_831 = mux(_T_774, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_832 = or(_T_775, _T_776) @[Mux.scala 27:72] + node _T_833 = or(_T_832, _T_777) @[Mux.scala 27:72] + node _T_834 = or(_T_833, _T_778) @[Mux.scala 27:72] + node _T_835 = or(_T_834, _T_779) @[Mux.scala 27:72] + node _T_836 = or(_T_835, _T_780) @[Mux.scala 27:72] + node _T_837 = or(_T_836, _T_781) @[Mux.scala 27:72] + node _T_838 = or(_T_837, _T_782) @[Mux.scala 27:72] + node _T_839 = or(_T_838, _T_783) @[Mux.scala 27:72] + node _T_840 = or(_T_839, _T_784) @[Mux.scala 27:72] + node _T_841 = or(_T_840, _T_785) @[Mux.scala 27:72] + node _T_842 = or(_T_841, _T_786) @[Mux.scala 27:72] + node _T_843 = or(_T_842, _T_787) @[Mux.scala 27:72] + node _T_844 = or(_T_843, _T_788) @[Mux.scala 27:72] + node _T_845 = or(_T_844, _T_789) @[Mux.scala 27:72] + node _T_846 = or(_T_845, _T_790) @[Mux.scala 27:72] + node _T_847 = or(_T_846, _T_791) @[Mux.scala 27:72] + node _T_848 = or(_T_847, _T_792) @[Mux.scala 27:72] + node _T_849 = or(_T_848, _T_793) @[Mux.scala 27:72] + node _T_850 = or(_T_849, _T_794) @[Mux.scala 27:72] + node _T_851 = or(_T_850, _T_795) @[Mux.scala 27:72] + node _T_852 = or(_T_851, _T_796) @[Mux.scala 27:72] + node _T_853 = or(_T_852, _T_797) @[Mux.scala 27:72] + node _T_854 = or(_T_853, _T_798) @[Mux.scala 27:72] + node _T_855 = or(_T_854, _T_799) @[Mux.scala 27:72] + node _T_856 = or(_T_855, _T_800) @[Mux.scala 27:72] + node _T_857 = or(_T_856, _T_801) @[Mux.scala 27:72] + node _T_858 = or(_T_857, _T_802) @[Mux.scala 27:72] + node _T_859 = or(_T_858, _T_803) @[Mux.scala 27:72] + node _T_860 = or(_T_859, _T_804) @[Mux.scala 27:72] + node _T_861 = or(_T_860, _T_805) @[Mux.scala 27:72] + node _T_862 = or(_T_861, _T_806) @[Mux.scala 27:72] + node _T_863 = or(_T_862, _T_807) @[Mux.scala 27:72] + node _T_864 = or(_T_863, _T_808) @[Mux.scala 27:72] + node _T_865 = or(_T_864, _T_809) @[Mux.scala 27:72] + node _T_866 = or(_T_865, _T_810) @[Mux.scala 27:72] + node _T_867 = or(_T_866, _T_811) @[Mux.scala 27:72] + node _T_868 = or(_T_867, _T_812) @[Mux.scala 27:72] + node _T_869 = or(_T_868, _T_813) @[Mux.scala 27:72] + node _T_870 = or(_T_869, _T_814) @[Mux.scala 27:72] + node _T_871 = or(_T_870, _T_815) @[Mux.scala 27:72] + node _T_872 = or(_T_871, _T_816) @[Mux.scala 27:72] + node _T_873 = or(_T_872, _T_817) @[Mux.scala 27:72] + node _T_874 = or(_T_873, _T_818) @[Mux.scala 27:72] + node _T_875 = or(_T_874, _T_819) @[Mux.scala 27:72] + node _T_876 = or(_T_875, _T_820) @[Mux.scala 27:72] + node _T_877 = or(_T_876, _T_821) @[Mux.scala 27:72] + node _T_878 = or(_T_877, _T_822) @[Mux.scala 27:72] + node _T_879 = or(_T_878, _T_823) @[Mux.scala 27:72] + node _T_880 = or(_T_879, _T_824) @[Mux.scala 27:72] + node _T_881 = or(_T_880, _T_825) @[Mux.scala 27:72] + node _T_882 = or(_T_881, _T_826) @[Mux.scala 27:72] + node _T_883 = or(_T_882, _T_827) @[Mux.scala 27:72] + node _T_884 = or(_T_883, _T_828) @[Mux.scala 27:72] + node _T_885 = or(_T_884, _T_829) @[Mux.scala 27:72] + node _T_886 = or(_T_885, _T_830) @[Mux.scala 27:72] + node _T_887 = or(_T_886, _T_831) @[Mux.scala 27:72] + wire _T_888 : UInt<1> @[Mux.scala 27:72] + _T_888 <= _T_887 @[Mux.scala 27:72] + node _T_889 = and(_T_595, _T_888) @[dec_tlu_ctl.scala 2797:63] + io.mhpmc_inc_r[2] <= _T_889 @[dec_tlu_ctl.scala 2797:35] + node _T_890 = bits(io.mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2797:57] + node _T_891 = not(_T_890) @[dec_tlu_ctl.scala 2797:40] + node _T_892 = eq(io.mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2798:42] + node _T_893 = bits(_T_892, 0, 0) @[dec_tlu_ctl.scala 2798:70] + node _T_894 = eq(io.mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2799:42] + node _T_895 = bits(_T_894, 0, 0) @[dec_tlu_ctl.scala 2799:70] + node _T_896 = eq(io.mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2800:42] + node _T_897 = bits(_T_896, 0, 0) @[dec_tlu_ctl.scala 2800:70] + node _T_898 = eq(io.mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2801:42] + node _T_899 = bits(_T_898, 0, 0) @[dec_tlu_ctl.scala 2801:70] + node _T_900 = not(io.illegal_r) @[dec_tlu_ctl.scala 2801:104] + node _T_901 = and(io.tlu_i0_commit_cmt, _T_900) @[dec_tlu_ctl.scala 2801:102] + node _T_902 = eq(io.mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2802:42] + node _T_903 = bits(_T_902, 0, 0) @[dec_tlu_ctl.scala 2802:70] + node _T_904 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2802:104] + node _T_905 = and(io.tlu_i0_commit_cmt, _T_904) @[dec_tlu_ctl.scala 2802:102] + node _T_906 = not(io.illegal_r) @[dec_tlu_ctl.scala 2802:125] + node _T_907 = and(_T_905, _T_906) @[dec_tlu_ctl.scala 2802:123] + node _T_908 = eq(io.mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2803:42] + node _T_909 = bits(_T_908, 0, 0) @[dec_tlu_ctl.scala 2803:70] + node _T_910 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2803:102] + node _T_911 = not(io.illegal_r) @[dec_tlu_ctl.scala 2803:125] + node _T_912 = and(_T_910, _T_911) @[dec_tlu_ctl.scala 2803:123] + node _T_913 = eq(io.mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2805:42] + node _T_914 = bits(_T_913, 0, 0) @[dec_tlu_ctl.scala 2805:70] + node _T_915 = eq(io.mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2806:42] + node _T_916 = bits(_T_915, 0, 0) @[dec_tlu_ctl.scala 2806:70] + node _T_917 = eq(io.mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2807:42] + node _T_918 = bits(_T_917, 0, 0) @[dec_tlu_ctl.scala 2807:70] + node _T_919 = eq(io.mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2808:42] + node _T_920 = bits(_T_919, 0, 0) @[dec_tlu_ctl.scala 2808:70] + node _T_921 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2808:99] + node _T_922 = eq(io.mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2809:42] + node _T_923 = bits(_T_922, 0, 0) @[dec_tlu_ctl.scala 2809:70] + node _T_924 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2809:113] + node _T_925 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2809:138] + node _T_926 = and(_T_924, _T_925) @[dec_tlu_ctl.scala 2809:136] + node _T_927 = eq(io.mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2810:42] + node _T_928 = bits(_T_927, 0, 0) @[dec_tlu_ctl.scala 2810:70] + node _T_929 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2810:99] + node _T_930 = eq(io.mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2811:42] + node _T_931 = bits(_T_930, 0, 0) @[dec_tlu_ctl.scala 2811:70] + node _T_932 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2811:99] + node _T_933 = eq(io.mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2812:42] + node _T_934 = bits(_T_933, 0, 0) @[dec_tlu_ctl.scala 2812:70] + node _T_935 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2812:99] + node _T_936 = and(_T_935, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2812:108] + node _T_937 = eq(io.mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2813:42] + node _T_938 = bits(_T_937, 0, 0) @[dec_tlu_ctl.scala 2813:70] + node _T_939 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2813:99] + node _T_940 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2813:150] + node _T_941 = and(_T_939, _T_940) @[dec_tlu_ctl.scala 2813:109] + node _T_942 = eq(io.mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2815:42] + node _T_943 = bits(_T_942, 0, 0) @[dec_tlu_ctl.scala 2815:67] + node _T_944 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2815:97] + node _T_945 = eq(io.mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2816:42] + node _T_946 = bits(_T_945, 0, 0) @[dec_tlu_ctl.scala 2816:67] + node _T_947 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2816:97] + node _T_948 = eq(io.mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2817:42] + node _T_949 = bits(_T_948, 0, 0) @[dec_tlu_ctl.scala 2817:67] + node _T_950 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2817:97] + node _T_951 = eq(io.mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2818:42] + node _T_952 = bits(_T_951, 0, 0) @[dec_tlu_ctl.scala 2818:67] + node _T_953 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2818:97] + node _T_954 = eq(io.mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2819:42] + node _T_955 = bits(_T_954, 0, 0) @[dec_tlu_ctl.scala 2819:67] + node _T_956 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2819:97] + node _T_957 = eq(io.mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2820:42] + node _T_958 = bits(_T_957, 0, 0) @[dec_tlu_ctl.scala 2820:67] + node _T_959 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2820:97] + node _T_960 = eq(io.mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2821:42] + node _T_961 = bits(_T_960, 0, 0) @[dec_tlu_ctl.scala 2821:67] + node _T_962 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2821:97] + node _T_963 = eq(io.mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2822:42] + node _T_964 = bits(_T_963, 0, 0) @[dec_tlu_ctl.scala 2822:67] + node _T_965 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2822:97] + node _T_966 = eq(io.mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2823:42] + node _T_967 = bits(_T_966, 0, 0) @[dec_tlu_ctl.scala 2823:67] + node _T_968 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2823:97] + node _T_969 = eq(io.mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2824:42] + node _T_970 = bits(_T_969, 0, 0) @[dec_tlu_ctl.scala 2824:67] + node _T_971 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2824:97] + node _T_972 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2824:130] + node _T_973 = or(_T_971, _T_972) @[dec_tlu_ctl.scala 2824:109] + node _T_974 = eq(io.mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2826:42] + node _T_975 = bits(_T_974, 0, 0) @[dec_tlu_ctl.scala 2826:70] + node _T_976 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2826:103] + node _T_977 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2826:128] + node _T_978 = and(_T_976, _T_977) @[dec_tlu_ctl.scala 2826:126] + node _T_979 = eq(io.mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2827:42] + node _T_980 = bits(_T_979, 0, 0) @[dec_tlu_ctl.scala 2827:70] + node _T_981 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2827:105] + node _T_982 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2827:130] + node _T_983 = and(_T_981, _T_982) @[dec_tlu_ctl.scala 2827:128] + node _T_984 = eq(io.mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2828:42] + node _T_985 = bits(_T_984, 0, 0) @[dec_tlu_ctl.scala 2828:70] + node _T_986 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2828:118] + node _T_987 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2828:143] + node _T_988 = and(_T_986, _T_987) @[dec_tlu_ctl.scala 2828:141] + node _T_989 = eq(io.mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2829:42] + node _T_990 = bits(_T_989, 0, 0) @[dec_tlu_ctl.scala 2829:70] + node _T_991 = eq(io.mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2830:42] + node _T_992 = bits(_T_991, 0, 0) @[dec_tlu_ctl.scala 2830:70] + node _T_993 = eq(io.mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2831:42] + node _T_994 = bits(_T_993, 0, 0) @[dec_tlu_ctl.scala 2831:70] + node _T_995 = eq(io.mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2832:42] + node _T_996 = bits(_T_995, 0, 0) @[dec_tlu_ctl.scala 2832:70] + node _T_997 = eq(io.mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2833:42] + node _T_998 = bits(_T_997, 0, 0) @[dec_tlu_ctl.scala 2833:70] + node _T_999 = eq(io.mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2834:42] + node _T_1000 = bits(_T_999, 0, 0) @[dec_tlu_ctl.scala 2834:70] + node _T_1001 = eq(io.mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2835:42] + node _T_1002 = bits(_T_1001, 0, 0) @[dec_tlu_ctl.scala 2835:70] + node _T_1003 = eq(io.mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2836:42] + node _T_1004 = bits(_T_1003, 0, 0) @[dec_tlu_ctl.scala 2836:70] + node _T_1005 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2836:106] + node _T_1006 = or(_T_1005, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2836:128] + node _T_1007 = eq(io.mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2837:42] + node _T_1008 = bits(_T_1007, 0, 0) @[dec_tlu_ctl.scala 2837:70] + node _T_1009 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2837:100] + node _T_1010 = or(_T_1009, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2837:125] + node _T_1011 = eq(io.mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2838:42] + node _T_1012 = bits(_T_1011, 0, 0) @[dec_tlu_ctl.scala 2838:70] + node _T_1013 = eq(io.mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2839:42] + node _T_1014 = bits(_T_1013, 0, 0) @[dec_tlu_ctl.scala 2839:70] + node _T_1015 = eq(io.mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2840:42] + node _T_1016 = bits(_T_1015, 0, 0) @[dec_tlu_ctl.scala 2840:70] + node _T_1017 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2840:105] + node _T_1018 = and(_T_1017, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2840:137] + node _T_1019 = eq(io.mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2842:42] + node _T_1020 = bits(_T_1019, 0, 0) @[dec_tlu_ctl.scala 2842:70] + node _T_1021 = eq(io.mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2843:42] + node _T_1022 = bits(_T_1021, 0, 0) @[dec_tlu_ctl.scala 2843:70] + node _T_1023 = eq(io.mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2844:42] + node _T_1024 = bits(_T_1023, 0, 0) @[dec_tlu_ctl.scala 2844:70] + node _T_1025 = eq(io.mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2845:42] + node _T_1026 = bits(_T_1025, 0, 0) @[dec_tlu_ctl.scala 2845:70] + node _T_1027 = eq(io.mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2846:42] + node _T_1028 = bits(_T_1027, 0, 0) @[dec_tlu_ctl.scala 2846:70] + node _T_1029 = eq(io.mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2847:42] + node _T_1030 = bits(_T_1029, 0, 0) @[dec_tlu_ctl.scala 2847:70] + node _T_1031 = eq(io.mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2848:42] + node _T_1032 = bits(_T_1031, 0, 0) @[dec_tlu_ctl.scala 2848:70] + node _T_1033 = eq(io.mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2849:42] + node _T_1034 = bits(_T_1033, 0, 0) @[dec_tlu_ctl.scala 2849:70] + node _T_1035 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2849:92] + node _T_1036 = bits(_T_1035, 0, 0) @[dec_tlu_ctl.scala 2849:92] + node _T_1037 = not(_T_1036) @[dec_tlu_ctl.scala 2849:81] + node _T_1038 = eq(io.mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2850:42] + node _T_1039 = bits(_T_1038, 0, 0) @[dec_tlu_ctl.scala 2850:70] + node _T_1040 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2850:92] + node _T_1041 = bits(_T_1040, 0, 0) @[dec_tlu_ctl.scala 2850:92] + node _T_1042 = not(_T_1041) @[dec_tlu_ctl.scala 2850:81] + node _T_1043 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2850:115] + node _T_1044 = bits(io.mie, 5, 0) @[dec_tlu_ctl.scala 2850:129] + node _T_1045 = and(_T_1043, _T_1044) @[dec_tlu_ctl.scala 2850:121] + node _T_1046 = orr(_T_1045) @[dec_tlu_ctl.scala 2850:136] + node _T_1047 = and(_T_1042, _T_1046) @[dec_tlu_ctl.scala 2850:106] + node _T_1048 = eq(io.mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2851:42] + node _T_1049 = bits(_T_1048, 0, 0) @[dec_tlu_ctl.scala 2851:70] + node _T_1050 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2851:99] + node _T_1051 = eq(io.mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2852:42] + node _T_1052 = bits(_T_1051, 0, 0) @[dec_tlu_ctl.scala 2852:70] + node _T_1053 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2852:102] + node _T_1054 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2852:133] + node _T_1055 = and(_T_1053, _T_1054) @[dec_tlu_ctl.scala 2852:131] + node _T_1056 = eq(io.mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2853:42] + node _T_1057 = bits(_T_1056, 0, 0) @[dec_tlu_ctl.scala 2853:70] + node _T_1058 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2853:102] + node _T_1059 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2853:134] + node _T_1060 = and(_T_1058, _T_1059) @[dec_tlu_ctl.scala 2853:132] + node _T_1061 = eq(io.mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2855:42] + node _T_1062 = bits(_T_1061, 0, 0) @[dec_tlu_ctl.scala 2855:70] + node _T_1063 = eq(io.mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2856:42] + node _T_1064 = bits(_T_1063, 0, 0) @[dec_tlu_ctl.scala 2856:70] + node _T_1065 = eq(io.mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2857:42] + node _T_1066 = bits(_T_1065, 0, 0) @[dec_tlu_ctl.scala 2857:70] + node _T_1067 = eq(io.mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2858:42] + node _T_1068 = bits(_T_1067, 0, 0) @[dec_tlu_ctl.scala 2858:70] + node _T_1069 = eq(io.mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2859:42] + node _T_1070 = bits(_T_1069, 0, 0) @[dec_tlu_ctl.scala 2859:70] + node _T_1071 = mux(_T_893, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1072 = mux(_T_895, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1073 = mux(_T_897, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1074 = mux(_T_899, _T_901, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1075 = mux(_T_903, _T_907, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1076 = mux(_T_909, _T_912, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1077 = mux(_T_914, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1078 = mux(_T_916, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1079 = mux(_T_918, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1080 = mux(_T_920, _T_921, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1081 = mux(_T_923, _T_926, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1082 = mux(_T_928, _T_929, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1083 = mux(_T_931, _T_932, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1084 = mux(_T_934, _T_936, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1085 = mux(_T_938, _T_941, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1086 = mux(_T_943, _T_944, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1087 = mux(_T_946, _T_947, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1088 = mux(_T_949, _T_950, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1089 = mux(_T_952, _T_953, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1090 = mux(_T_955, _T_956, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1091 = mux(_T_958, _T_959, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1092 = mux(_T_961, _T_962, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1093 = mux(_T_964, _T_965, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1094 = mux(_T_967, _T_968, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1095 = mux(_T_970, _T_973, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1096 = mux(_T_975, _T_978, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1097 = mux(_T_980, _T_983, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1098 = mux(_T_985, _T_988, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1099 = mux(_T_990, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1100 = mux(_T_992, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1101 = mux(_T_994, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1102 = mux(_T_996, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1103 = mux(_T_998, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1104 = mux(_T_1000, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1105 = mux(_T_1002, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1106 = mux(_T_1004, _T_1006, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1107 = mux(_T_1008, _T_1010, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1108 = mux(_T_1012, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1109 = mux(_T_1014, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1110 = mux(_T_1016, _T_1018, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1111 = mux(_T_1020, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1112 = mux(_T_1022, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1113 = mux(_T_1024, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1114 = mux(_T_1026, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1115 = mux(_T_1028, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1116 = mux(_T_1030, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1117 = mux(_T_1032, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1118 = mux(_T_1034, _T_1037, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1119 = mux(_T_1039, _T_1047, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1120 = mux(_T_1049, _T_1050, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1121 = mux(_T_1052, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1122 = mux(_T_1057, _T_1060, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1123 = mux(_T_1062, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1124 = mux(_T_1064, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1125 = mux(_T_1066, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1126 = mux(_T_1068, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1127 = mux(_T_1070, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1128 = or(_T_1071, _T_1072) @[Mux.scala 27:72] + node _T_1129 = or(_T_1128, _T_1073) @[Mux.scala 27:72] + node _T_1130 = or(_T_1129, _T_1074) @[Mux.scala 27:72] + node _T_1131 = or(_T_1130, _T_1075) @[Mux.scala 27:72] + node _T_1132 = or(_T_1131, _T_1076) @[Mux.scala 27:72] + node _T_1133 = or(_T_1132, _T_1077) @[Mux.scala 27:72] + node _T_1134 = or(_T_1133, _T_1078) @[Mux.scala 27:72] + node _T_1135 = or(_T_1134, _T_1079) @[Mux.scala 27:72] + node _T_1136 = or(_T_1135, _T_1080) @[Mux.scala 27:72] + node _T_1137 = or(_T_1136, _T_1081) @[Mux.scala 27:72] + node _T_1138 = or(_T_1137, _T_1082) @[Mux.scala 27:72] + node _T_1139 = or(_T_1138, _T_1083) @[Mux.scala 27:72] + node _T_1140 = or(_T_1139, _T_1084) @[Mux.scala 27:72] + node _T_1141 = or(_T_1140, _T_1085) @[Mux.scala 27:72] + node _T_1142 = or(_T_1141, _T_1086) @[Mux.scala 27:72] + node _T_1143 = or(_T_1142, _T_1087) @[Mux.scala 27:72] + node _T_1144 = or(_T_1143, _T_1088) @[Mux.scala 27:72] + node _T_1145 = or(_T_1144, _T_1089) @[Mux.scala 27:72] + node _T_1146 = or(_T_1145, _T_1090) @[Mux.scala 27:72] + node _T_1147 = or(_T_1146, _T_1091) @[Mux.scala 27:72] + node _T_1148 = or(_T_1147, _T_1092) @[Mux.scala 27:72] + node _T_1149 = or(_T_1148, _T_1093) @[Mux.scala 27:72] + node _T_1150 = or(_T_1149, _T_1094) @[Mux.scala 27:72] + node _T_1151 = or(_T_1150, _T_1095) @[Mux.scala 27:72] + node _T_1152 = or(_T_1151, _T_1096) @[Mux.scala 27:72] + node _T_1153 = or(_T_1152, _T_1097) @[Mux.scala 27:72] + node _T_1154 = or(_T_1153, _T_1098) @[Mux.scala 27:72] + node _T_1155 = or(_T_1154, _T_1099) @[Mux.scala 27:72] + node _T_1156 = or(_T_1155, _T_1100) @[Mux.scala 27:72] + node _T_1157 = or(_T_1156, _T_1101) @[Mux.scala 27:72] + node _T_1158 = or(_T_1157, _T_1102) @[Mux.scala 27:72] + node _T_1159 = or(_T_1158, _T_1103) @[Mux.scala 27:72] + node _T_1160 = or(_T_1159, _T_1104) @[Mux.scala 27:72] + node _T_1161 = or(_T_1160, _T_1105) @[Mux.scala 27:72] + node _T_1162 = or(_T_1161, _T_1106) @[Mux.scala 27:72] + node _T_1163 = or(_T_1162, _T_1107) @[Mux.scala 27:72] + node _T_1164 = or(_T_1163, _T_1108) @[Mux.scala 27:72] + node _T_1165 = or(_T_1164, _T_1109) @[Mux.scala 27:72] + node _T_1166 = or(_T_1165, _T_1110) @[Mux.scala 27:72] + node _T_1167 = or(_T_1166, _T_1111) @[Mux.scala 27:72] + node _T_1168 = or(_T_1167, _T_1112) @[Mux.scala 27:72] + node _T_1169 = or(_T_1168, _T_1113) @[Mux.scala 27:72] + node _T_1170 = or(_T_1169, _T_1114) @[Mux.scala 27:72] + node _T_1171 = or(_T_1170, _T_1115) @[Mux.scala 27:72] + node _T_1172 = or(_T_1171, _T_1116) @[Mux.scala 27:72] + node _T_1173 = or(_T_1172, _T_1117) @[Mux.scala 27:72] + node _T_1174 = or(_T_1173, _T_1118) @[Mux.scala 27:72] + node _T_1175 = or(_T_1174, _T_1119) @[Mux.scala 27:72] + node _T_1176 = or(_T_1175, _T_1120) @[Mux.scala 27:72] + node _T_1177 = or(_T_1176, _T_1121) @[Mux.scala 27:72] + node _T_1178 = or(_T_1177, _T_1122) @[Mux.scala 27:72] + node _T_1179 = or(_T_1178, _T_1123) @[Mux.scala 27:72] + node _T_1180 = or(_T_1179, _T_1124) @[Mux.scala 27:72] + node _T_1181 = or(_T_1180, _T_1125) @[Mux.scala 27:72] + node _T_1182 = or(_T_1181, _T_1126) @[Mux.scala 27:72] + node _T_1183 = or(_T_1182, _T_1127) @[Mux.scala 27:72] + wire _T_1184 : UInt<1> @[Mux.scala 27:72] + _T_1184 <= _T_1183 @[Mux.scala 27:72] + node _T_1185 = and(_T_891, _T_1184) @[dec_tlu_ctl.scala 2797:63] + io.mhpmc_inc_r[3] <= _T_1185 @[dec_tlu_ctl.scala 2797:35] + wire _T_1186 : UInt<1> + _T_1186 <= UInt<1>("h00") + node _T_1187 = xor(io.mdseac_locked_ns, _T_1186) @[lib.scala 470:21] + node _T_1188 = orr(_T_1187) @[lib.scala 470:29] + reg _T_1189 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1188 : @[Reg.scala 28:19] + _T_1189 <= io.mdseac_locked_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1186 <= _T_1189 @[lib.scala 473:16] + io.mdseac_locked_f <= _T_1186 @[dec_tlu_ctl.scala 2870:52] + wire _T_1190 : UInt<1> + _T_1190 <= UInt<1>("h00") + node _T_1191 = xor(io.lsu_single_ecc_error_r, _T_1190) @[lib.scala 470:21] + node _T_1192 = orr(_T_1191) @[lib.scala 470:29] + reg _T_1193 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1192 : @[Reg.scala 28:19] + _T_1193 <= io.lsu_single_ecc_error_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1190 <= _T_1193 @[lib.scala 473:16] + io.lsu_single_ecc_error_r_d1 <= _T_1190 @[dec_tlu_ctl.scala 2871:52] + wire _T_1194 : UInt + _T_1194 <= UInt<1>("h00") + node _T_1195 = xor(io.lsu_exc_valid_r, _T_1194) @[lib.scala 448:21] + node _T_1196 = orr(_T_1195) @[lib.scala 448:29] + reg _T_1197 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1196 : @[Reg.scala 28:19] + _T_1197 <= io.lsu_exc_valid_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1194 <= _T_1197 @[lib.scala 451:16] + io.lsu_exc_valid_r_d1 <= _T_1194 @[dec_tlu_ctl.scala 2872:52] + wire _T_1198 : UInt<1> + _T_1198 <= UInt<1>("h00") + node _T_1199 = xor(io.lsu_i0_exc_r, _T_1198) @[lib.scala 470:21] + node _T_1200 = orr(_T_1199) @[lib.scala 470:29] + reg _T_1201 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1200 : @[Reg.scala 28:19] + _T_1201 <= io.lsu_i0_exc_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1198 <= _T_1201 @[lib.scala 473:16] + io.lsu_i0_exc_r_d1 <= _T_1198 @[dec_tlu_ctl.scala 2873:52] + wire _T_1202 : UInt<1> + _T_1202 <= UInt<1>("h00") + node _T_1203 = xor(io.take_ext_int_start, _T_1202) @[lib.scala 470:21] + node _T_1204 = orr(_T_1203) @[lib.scala 470:29] + reg _T_1205 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1204 : @[Reg.scala 28:19] + _T_1205 <= io.take_ext_int_start @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1202 <= _T_1205 @[lib.scala 473:16] + io.take_ext_int_start_d1 <= _T_1202 @[dec_tlu_ctl.scala 2874:52] + wire _T_1206 : UInt<1> + _T_1206 <= UInt<1>("h00") + node _T_1207 = xor(io.take_ext_int_start_d1, _T_1206) @[lib.scala 470:21] + node _T_1208 = orr(_T_1207) @[lib.scala 470:29] + reg _T_1209 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1208 : @[Reg.scala 28:19] + _T_1209 <= io.take_ext_int_start_d1 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1206 <= _T_1209 @[lib.scala 473:16] + io.take_ext_int_start_d2 <= _T_1206 @[dec_tlu_ctl.scala 2875:52] + wire _T_1210 : UInt<1> + _T_1210 <= UInt<1>("h00") + node _T_1211 = xor(io.take_ext_int_start_d2, _T_1210) @[lib.scala 470:21] + node _T_1212 = orr(_T_1211) @[lib.scala 470:29] + reg _T_1213 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1212 : @[Reg.scala 28:19] + _T_1213 <= io.take_ext_int_start_d2 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1210 <= _T_1213 @[lib.scala 473:16] + io.take_ext_int_start_d3 <= _T_1210 @[dec_tlu_ctl.scala 2876:52] + wire _T_1214 : UInt<1> + _T_1214 <= UInt<1>("h00") + node _T_1215 = xor(io.ext_int_freeze, _T_1214) @[lib.scala 470:21] + node _T_1216 = orr(_T_1215) @[lib.scala 470:29] + reg _T_1217 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1216 : @[Reg.scala 28:19] + _T_1217 <= io.ext_int_freeze @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1214 <= _T_1217 @[lib.scala 473:16] + io.ext_int_freeze_d1 <= _T_1214 @[dec_tlu_ctl.scala 2877:52] + wire _T_1218 : UInt + _T_1218 <= UInt<1>("h00") + node _T_1219 = xor(io.mip_ns, _T_1218) @[lib.scala 448:21] + node _T_1220 = orr(_T_1219) @[lib.scala 448:29] + reg _T_1221 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1220 : @[Reg.scala 28:19] + _T_1221 <= io.mip_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1218 <= _T_1221 @[lib.scala 451:16] + io.mip <= _T_1218 @[dec_tlu_ctl.scala 2878:52] + node _T_1222 = not(io.wr_mcycleh_r) @[dec_tlu_ctl.scala 2879:80] + node _T_1223 = and(io.mcyclel_cout, _T_1222) @[dec_tlu_ctl.scala 2879:78] + node _T_1224 = and(_T_1223, io.mcyclel_cout_in) @[dec_tlu_ctl.scala 2879:97] + wire _T_1225 : UInt<1> + _T_1225 <= UInt<1>("h00") + node _T_1226 = xor(_T_1224, _T_1225) @[lib.scala 470:21] + node _T_1227 = orr(_T_1226) @[lib.scala 470:29] + reg _T_1228 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1227 : @[Reg.scala 28:19] + _T_1228 <= _T_1224 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1225 <= _T_1228 @[lib.scala 473:16] + io.mcyclel_cout_f <= _T_1225 @[dec_tlu_ctl.scala 2879:52] + wire _T_1229 : UInt<1> + _T_1229 <= UInt<1>("h00") + node _T_1230 = xor(io.minstret_enable, _T_1229) @[lib.scala 470:21] + node _T_1231 = orr(_T_1230) @[lib.scala 470:29] + reg _T_1232 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1231 : @[Reg.scala 28:19] + _T_1232 <= io.minstret_enable @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1229 <= _T_1232 @[lib.scala 473:16] + io.minstret_enable_f <= _T_1229 @[dec_tlu_ctl.scala 2880:52] + wire _T_1233 : UInt<1> + _T_1233 <= UInt<1>("h00") + node _T_1234 = xor(io.minstretl_cout_ns, _T_1233) @[lib.scala 470:21] + node _T_1235 = orr(_T_1234) @[lib.scala 470:29] + reg _T_1236 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1235 : @[Reg.scala 28:19] + _T_1236 <= io.minstretl_cout_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1233 <= _T_1236 @[lib.scala 473:16] + io.minstretl_cout_f <= _T_1233 @[dec_tlu_ctl.scala 2881:52] + wire _T_1237 : UInt<1> + _T_1237 <= UInt<1>("h00") + node _T_1238 = xor(io.fw_halted_ns, _T_1237) @[lib.scala 470:21] + node _T_1239 = orr(_T_1238) @[lib.scala 470:29] + reg _T_1240 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1239 : @[Reg.scala 28:19] + _T_1240 <= io.fw_halted_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1237 <= _T_1240 @[lib.scala 473:16] + io.fw_halted <= _T_1237 @[dec_tlu_ctl.scala 2882:52] + wire _T_1241 : UInt + _T_1241 <= UInt<1>("h00") + node _T_1242 = xor(io.meicidpl_ns, _T_1241) @[lib.scala 448:21] + node _T_1243 = orr(_T_1242) @[lib.scala 448:29] + reg _T_1244 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1243 : @[Reg.scala 28:19] + _T_1244 <= io.meicidpl_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1241 <= _T_1244 @[lib.scala 451:16] + io.meicidpl <= _T_1241 @[dec_tlu_ctl.scala 2883:52] + wire _T_1245 : UInt<1> + _T_1245 <= UInt<1>("h00") + node _T_1246 = xor(io.icache_rd_valid, _T_1245) @[lib.scala 470:21] + node _T_1247 = orr(_T_1246) @[lib.scala 470:29] + reg _T_1248 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1247 : @[Reg.scala 28:19] + _T_1248 <= io.icache_rd_valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1245 <= _T_1248 @[lib.scala 473:16] + io.icache_rd_valid_f <= _T_1245 @[dec_tlu_ctl.scala 2884:52] + wire _T_1249 : UInt<1> + _T_1249 <= UInt<1>("h00") + node _T_1250 = xor(io.icache_wr_valid, _T_1249) @[lib.scala 470:21] + node _T_1251 = orr(_T_1250) @[lib.scala 470:29] + reg _T_1252 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1251 : @[Reg.scala 28:19] + _T_1252 <= io.icache_wr_valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1249 <= _T_1252 @[lib.scala 473:16] + io.icache_wr_valid_f <= _T_1249 @[dec_tlu_ctl.scala 2885:52] + wire _T_1253 : UInt<1>[4] + _T_1253[0] <= io.mhpmc_inc_r[0] + _T_1253[1] <= io.mhpmc_inc_r[1] + _T_1253[2] <= io.mhpmc_inc_r[2] + _T_1253[3] <= io.mhpmc_inc_r[3] + node _T_1254 = xor(io.mhpmc_inc_r[0], _T_1253[0]) @[lib.scala 518:68] + node _T_1255 = orr(_T_1254) @[lib.scala 518:82] + node _T_1256 = xor(io.mhpmc_inc_r[1], _T_1253[1]) @[lib.scala 518:68] + node _T_1257 = orr(_T_1256) @[lib.scala 518:82] + node _T_1258 = xor(io.mhpmc_inc_r[2], _T_1253[2]) @[lib.scala 518:68] + node _T_1259 = orr(_T_1258) @[lib.scala 518:82] + node _T_1260 = xor(io.mhpmc_inc_r[3], _T_1253[3]) @[lib.scala 518:68] + node _T_1261 = orr(_T_1260) @[lib.scala 518:82] + node _T_1262 = or(_T_1255, _T_1257) @[lib.scala 518:97] + node _T_1263 = or(_T_1262, _T_1259) @[lib.scala 518:97] + node _T_1264 = or(_T_1263, _T_1261) @[lib.scala 518:97] + wire _T_1265 : UInt<1>[4] @[lib.scala 521:46] + _T_1265[0] <= UInt<1>("h00") @[lib.scala 521:46] + _T_1265[1] <= UInt<1>("h00") @[lib.scala 521:46] + _T_1265[2] <= UInt<1>("h00") @[lib.scala 521:46] + _T_1265[3] <= UInt<1>("h00") @[lib.scala 521:46] + reg _T_1266 : UInt<1>[4], io.free_l2clk with : (reset => (reset, _T_1265)) @[Reg.scala 27:20] + when _T_1264 : @[Reg.scala 28:19] + _T_1266[0] <= io.mhpmc_inc_r[0] @[Reg.scala 28:23] + _T_1266[1] <= io.mhpmc_inc_r[1] @[Reg.scala 28:23] + _T_1266[2] <= io.mhpmc_inc_r[2] @[Reg.scala 28:23] + _T_1266[3] <= io.mhpmc_inc_r[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1253[0] <= _T_1266[0] @[lib.scala 521:16] + _T_1253[1] <= _T_1266[1] @[lib.scala 521:16] + _T_1253[2] <= _T_1266[2] @[lib.scala 521:16] + _T_1253[3] <= _T_1266[3] @[lib.scala 521:16] + io.mhpmc_inc_r_d1[0] <= _T_1253[0] @[dec_tlu_ctl.scala 2886:52] + io.mhpmc_inc_r_d1[1] <= _T_1253[1] @[dec_tlu_ctl.scala 2886:52] + io.mhpmc_inc_r_d1[2] <= _T_1253[2] @[dec_tlu_ctl.scala 2886:52] + io.mhpmc_inc_r_d1[3] <= _T_1253[3] @[dec_tlu_ctl.scala 2886:52] + wire _T_1267 : UInt<1> + _T_1267 <= UInt<1>("h00") + node _T_1268 = xor(io.perfcnt_halted, _T_1267) @[lib.scala 470:21] + node _T_1269 = orr(_T_1268) @[lib.scala 470:29] + reg _T_1270 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1269 : @[Reg.scala 28:19] + _T_1270 <= io.perfcnt_halted @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1267 <= _T_1270 @[lib.scala 473:16] + io.perfcnt_halted_d1 <= _T_1267 @[dec_tlu_ctl.scala 2887:52] + wire _T_1271 : UInt + _T_1271 <= UInt<1>("h00") + node _T_1272 = xor(io.mstatus_ns, _T_1271) @[lib.scala 448:21] + node _T_1273 = orr(_T_1272) @[lib.scala 448:29] + reg _T_1274 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1273 : @[Reg.scala 28:19] + _T_1274 <= io.mstatus_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1271 <= _T_1274 @[lib.scala 451:16] + io.mstatus <= _T_1271 @[dec_tlu_ctl.scala 2888:52] + + extmodule gated_latch_42 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_42 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_42 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_43 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_43 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_43 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_44 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_44 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_44 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_45 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_45 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_45 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_46 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_46 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_46 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_47 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_47 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_47 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_48 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_48 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_48 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_49 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_49 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_49 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_50 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_50 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_50 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_51 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_51 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_51 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_52 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_52 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_52 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_53 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_53 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_53 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module perf_csr : + input clock : Clock + input reset : AsyncReset + output io : {flip free_l2clk : Clock, flip scan_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dcsr : UInt<16>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip mhpme_vec : UInt<10>[4], flip dec_csr_wen_r_mod : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip mhpmc_inc_r : UInt<1>[4], flip mhpmc_inc_r_d1 : UInt<1>[4], flip perfcnt_halted_d1 : UInt<1>, mhpmc3h : UInt<32>, mhpmc3 : UInt<32>, mhpmc4h : UInt<32>, mhpmc4 : UInt<32>, mhpmc5h : UInt<32>, mhpmc5 : UInt<32>, mhpmc6h : UInt<32>, mhpmc6 : UInt<32>, mhpme3 : UInt<10>, mhpme4 : UInt<10>, mhpme5 : UInt<10>, mhpme6 : UInt<10>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>} + + node _T = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2578:63] + node _T_1 = and(io.dec_tlu_dbg_halted, _T) @[dec_tlu_ctl.scala 2578:54] + node perfcnt_halted = or(_T_1, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2578:77] + node _T_2 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2579:77] + node _T_3 = and(io.dec_tlu_dbg_halted, _T_2) @[dec_tlu_ctl.scala 2579:68] + node _T_4 = eq(_T_3, UInt<1>("h00")) @[dec_tlu_ctl.scala 2579:44] + node _T_5 = bits(_T_4, 0, 0) @[Bitwise.scala 72:15] + node _T_6 = mux(_T_5, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_7 = bits(io.mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2579:114] + node _T_8 = bits(io.mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2579:133] + node _T_9 = bits(io.mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2579:152] + node _T_10 = bits(io.mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2579:171] + node _T_11 = cat(_T_9, _T_10) @[Cat.scala 29:58] + node _T_12 = cat(_T_7, _T_8) @[Cat.scala 29:58] + node _T_13 = cat(_T_12, _T_11) @[Cat.scala 29:58] + node perfcnt_during_sleep = and(_T_6, _T_13) @[dec_tlu_ctl.scala 2579:93] + node _T_14 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2582:101] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[dec_tlu_ctl.scala 2582:80] + node _T_16 = and(io.perfcnt_halted_d1, _T_15) @[dec_tlu_ctl.scala 2582:78] + node _T_17 = eq(_T_16, UInt<1>("h00")) @[dec_tlu_ctl.scala 2582:55] + node _T_18 = and(io.mhpmc_inc_r_d1[0], _T_17) @[dec_tlu_ctl.scala 2582:53] + io.dec_tlu_perfcnt0 <= _T_18 @[dec_tlu_ctl.scala 2582:29] + node _T_19 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2583:101] + node _T_20 = eq(_T_19, UInt<1>("h00")) @[dec_tlu_ctl.scala 2583:80] + node _T_21 = and(io.perfcnt_halted_d1, _T_20) @[dec_tlu_ctl.scala 2583:78] + node _T_22 = eq(_T_21, UInt<1>("h00")) @[dec_tlu_ctl.scala 2583:55] + node _T_23 = and(io.mhpmc_inc_r_d1[1], _T_22) @[dec_tlu_ctl.scala 2583:53] + io.dec_tlu_perfcnt1 <= _T_23 @[dec_tlu_ctl.scala 2583:29] + node _T_24 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2584:101] + node _T_25 = eq(_T_24, UInt<1>("h00")) @[dec_tlu_ctl.scala 2584:80] + node _T_26 = and(io.perfcnt_halted_d1, _T_25) @[dec_tlu_ctl.scala 2584:78] + node _T_27 = eq(_T_26, UInt<1>("h00")) @[dec_tlu_ctl.scala 2584:55] + node _T_28 = and(io.mhpmc_inc_r_d1[2], _T_27) @[dec_tlu_ctl.scala 2584:53] + io.dec_tlu_perfcnt2 <= _T_28 @[dec_tlu_ctl.scala 2584:29] + node _T_29 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2585:101] + node _T_30 = eq(_T_29, UInt<1>("h00")) @[dec_tlu_ctl.scala 2585:80] + node _T_31 = and(io.perfcnt_halted_d1, _T_30) @[dec_tlu_ctl.scala 2585:78] + node _T_32 = eq(_T_31, UInt<1>("h00")) @[dec_tlu_ctl.scala 2585:55] + node _T_33 = and(io.mhpmc_inc_r_d1[3], _T_32) @[dec_tlu_ctl.scala 2585:53] + io.dec_tlu_perfcnt3 <= _T_33 @[dec_tlu_ctl.scala 2585:29] + node _T_34 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2591:72] + node _T_35 = eq(_T_34, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2591:79] + node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_35) @[dec_tlu_ctl.scala 2591:50] + node _T_36 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2592:30] + node _T_37 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2592:68] + node _T_38 = or(_T_36, _T_37) @[dec_tlu_ctl.scala 2592:46] + node _T_39 = orr(io.mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2592:96] + node mhpmc3_wr_en1 = and(_T_38, _T_39) @[dec_tlu_ctl.scala 2592:73] + node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2593:43] + node _T_40 = bits(io.mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2596:41] + node _T_41 = bits(io.mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2596:57] + node _T_42 = cat(_T_40, _T_41) @[Cat.scala 29:58] + node _T_43 = cat(UInt<63>("h00"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_44 = add(_T_42, _T_43) @[dec_tlu_ctl.scala 2596:65] + node mhpmc3_incr = tail(_T_44, 1) @[dec_tlu_ctl.scala 2596:65] + node _T_45 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2597:43] + node _T_46 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2597:83] + node mhpmc3_ns = mux(_T_45, io.dec_csr_wrdata_r, _T_46) @[dec_tlu_ctl.scala 2597:28] + node _T_47 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2599:52] + inst rvclkhdr of rvclkhdr_42 @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr.io.en <= _T_47 @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_48 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_47 : @[Reg.scala 28:19] + _T_48 <= mhpmc3_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpmc3 <= _T_48 @[dec_tlu_ctl.scala 2599:19] + node _T_49 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2601:73] + node _T_50 = eq(_T_49, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2601:80] + node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_50) @[dec_tlu_ctl.scala 2601:51] + node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2602:45] + node _T_51 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2603:45] + node _T_52 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2603:85] + node mhpmc3h_ns = mux(_T_51, io.dec_csr_wrdata_r, _T_52) @[dec_tlu_ctl.scala 2603:29] + node _T_53 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2605:56] + inst rvclkhdr_1 of rvclkhdr_43 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_53 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_54 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_53 : @[Reg.scala 28:19] + _T_54 <= mhpmc3h_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpmc3h <= _T_54 @[dec_tlu_ctl.scala 2605:20] + node _T_55 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2612:72] + node _T_56 = eq(_T_55, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2612:79] + node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_56) @[dec_tlu_ctl.scala 2612:50] + node _T_57 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2613:30] + node _T_58 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2613:68] + node _T_59 = or(_T_57, _T_58) @[dec_tlu_ctl.scala 2613:46] + node _T_60 = orr(io.mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2613:96] + node mhpmc4_wr_en1 = and(_T_59, _T_60) @[dec_tlu_ctl.scala 2613:73] + node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2614:43] + node _T_61 = bits(io.mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2618:41] + node _T_62 = bits(io.mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2618:57] + node _T_63 = cat(_T_61, _T_62) @[Cat.scala 29:58] + node _T_64 = cat(UInt<63>("h00"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_65 = add(_T_63, _T_64) @[dec_tlu_ctl.scala 2618:65] + node mhpmc4_incr = tail(_T_65, 1) @[dec_tlu_ctl.scala 2618:65] + node _T_66 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2619:43] + node _T_67 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2619:70] + node _T_68 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2619:89] + node mhpmc4_ns = mux(_T_66, _T_67, _T_68) @[dec_tlu_ctl.scala 2619:28] + node _T_69 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2620:53] + inst rvclkhdr_2 of rvclkhdr_44 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_2.io.en <= _T_69 @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_70 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_69 : @[Reg.scala 28:19] + _T_70 <= mhpmc4_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpmc4 <= _T_70 @[dec_tlu_ctl.scala 2620:19] + node _T_71 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2622:73] + node _T_72 = eq(_T_71, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2622:80] + node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_72) @[dec_tlu_ctl.scala 2622:51] + node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2623:45] + node _T_73 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2624:45] + node _T_74 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2624:85] + node mhpmc4h_ns = mux(_T_73, io.dec_csr_wrdata_r, _T_74) @[dec_tlu_ctl.scala 2624:29] + node _T_75 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2625:56] + inst rvclkhdr_3 of rvclkhdr_45 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_3.io.en <= _T_75 @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_76 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_75 : @[Reg.scala 28:19] + _T_76 <= mhpmc4h_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpmc4h <= _T_76 @[dec_tlu_ctl.scala 2625:20] + node _T_77 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2631:72] + node _T_78 = eq(_T_77, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2631:79] + node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_78) @[dec_tlu_ctl.scala 2631:50] + node _T_79 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2632:30] + node _T_80 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2632:68] + node _T_81 = or(_T_79, _T_80) @[dec_tlu_ctl.scala 2632:46] + node _T_82 = orr(io.mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2632:96] + node mhpmc5_wr_en1 = and(_T_81, _T_82) @[dec_tlu_ctl.scala 2632:73] + node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2633:43] + node _T_83 = bits(io.mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2635:41] + node _T_84 = bits(io.mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2635:57] + node _T_85 = cat(_T_83, _T_84) @[Cat.scala 29:58] + node _T_86 = cat(UInt<63>("h00"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_87 = add(_T_85, _T_86) @[dec_tlu_ctl.scala 2635:65] + node mhpmc5_incr = tail(_T_87, 1) @[dec_tlu_ctl.scala 2635:65] + node _T_88 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2636:43] + node _T_89 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2636:83] + node mhpmc5_ns = mux(_T_88, io.dec_csr_wrdata_r, _T_89) @[dec_tlu_ctl.scala 2636:28] + node _T_90 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2638:53] + inst rvclkhdr_4 of rvclkhdr_46 @[lib.scala 404:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_4.io.en <= _T_90 @[lib.scala 407:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_91 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_90 : @[Reg.scala 28:19] + _T_91 <= mhpmc5_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpmc5 <= _T_91 @[dec_tlu_ctl.scala 2638:19] + node _T_92 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2640:73] + node _T_93 = eq(_T_92, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2640:80] + node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_93) @[dec_tlu_ctl.scala 2640:51] + node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2641:45] + node _T_94 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2642:45] + node _T_95 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2642:85] + node mhpmc5h_ns = mux(_T_94, io.dec_csr_wrdata_r, _T_95) @[dec_tlu_ctl.scala 2642:29] + node _T_96 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2644:56] + inst rvclkhdr_5 of rvclkhdr_47 @[lib.scala 404:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_5.io.en <= _T_96 @[lib.scala 407:17] + rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_97 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_96 : @[Reg.scala 28:19] + _T_97 <= mhpmc5h_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpmc5h <= _T_97 @[dec_tlu_ctl.scala 2644:20] + node _T_98 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2651:72] + node _T_99 = eq(_T_98, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2651:79] + node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_99) @[dec_tlu_ctl.scala 2651:50] + node _T_100 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2652:30] + node _T_101 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2652:68] + node _T_102 = or(_T_100, _T_101) @[dec_tlu_ctl.scala 2652:46] + node _T_103 = orr(io.mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2652:96] + node mhpmc6_wr_en1 = and(_T_102, _T_103) @[dec_tlu_ctl.scala 2652:73] + node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2653:43] + node _T_104 = bits(io.mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2655:41] + node _T_105 = bits(io.mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2655:57] + node _T_106 = cat(_T_104, _T_105) @[Cat.scala 29:58] + node _T_107 = cat(UInt<63>("h00"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_108 = add(_T_106, _T_107) @[dec_tlu_ctl.scala 2655:65] + node mhpmc6_incr = tail(_T_108, 1) @[dec_tlu_ctl.scala 2655:65] + node _T_109 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2656:43] + node _T_110 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2656:83] + node mhpmc6_ns = mux(_T_109, io.dec_csr_wrdata_r, _T_110) @[dec_tlu_ctl.scala 2656:28] + node _T_111 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2659:53] + inst rvclkhdr_6 of rvclkhdr_48 @[lib.scala 404:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_6.io.en <= _T_111 @[lib.scala 407:17] + rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_112 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_111 : @[Reg.scala 28:19] + _T_112 <= mhpmc6_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpmc6 <= _T_112 @[dec_tlu_ctl.scala 2659:19] + node _T_113 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2661:73] + node _T_114 = eq(_T_113, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2661:80] + node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_114) @[dec_tlu_ctl.scala 2661:51] + node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2662:45] + node _T_115 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2663:45] + node _T_116 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2663:85] + node mhpmc6h_ns = mux(_T_115, io.dec_csr_wrdata_r, _T_116) @[dec_tlu_ctl.scala 2663:29] + node _T_117 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2665:56] + inst rvclkhdr_7 of rvclkhdr_49 @[lib.scala 404:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_7.io.en <= _T_117 @[lib.scala 407:17] + rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_118 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_117 : @[Reg.scala 28:19] + _T_118 <= mhpmc6h_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpmc6h <= _T_118 @[dec_tlu_ctl.scala 2665:20] + node _T_119 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2671:50] + node _T_120 = gt(_T_119, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2671:56] + node _T_121 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2671:94] + node _T_122 = orr(_T_121) @[dec_tlu_ctl.scala 2671:102] + node _T_123 = or(_T_120, _T_122) @[dec_tlu_ctl.scala 2671:72] + node _T_124 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2672:38] + node _T_125 = lt(_T_124, UInt<10>("h0200")) @[dec_tlu_ctl.scala 2672:44] + node _T_126 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2672:82] + node _T_127 = gt(_T_126, UInt<10>("h038")) @[dec_tlu_ctl.scala 2672:88] + node _T_128 = and(_T_125, _T_127) @[dec_tlu_ctl.scala 2672:60] + node _T_129 = or(_T_123, _T_128) @[dec_tlu_ctl.scala 2671:107] + node _T_130 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2673:38] + node _T_131 = lt(_T_130, UInt<10>("h036")) @[dec_tlu_ctl.scala 2673:44] + node _T_132 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2673:82] + node _T_133 = gt(_T_132, UInt<10>("h032")) @[dec_tlu_ctl.scala 2673:88] + node _T_134 = and(_T_131, _T_133) @[dec_tlu_ctl.scala 2673:60] + node _T_135 = or(_T_129, _T_134) @[dec_tlu_ctl.scala 2672:103] + node _T_136 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2674:37] + node _T_137 = eq(_T_136, UInt<10>("h01d")) @[dec_tlu_ctl.scala 2674:43] + node _T_138 = or(_T_135, _T_137) @[dec_tlu_ctl.scala 2673:103] + node _T_139 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2674:81] + node _T_140 = eq(_T_139, UInt<10>("h021")) @[dec_tlu_ctl.scala 2674:87] + node zero_event_r = or(_T_138, _T_140) @[dec_tlu_ctl.scala 2674:59] + node _T_141 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2676:71] + node event_r = mux(zero_event_r, UInt<10>("h00"), _T_141) @[dec_tlu_ctl.scala 2676:26] + node _T_142 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2677:70] + node _T_143 = eq(_T_142, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2677:77] + node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_143) @[dec_tlu_ctl.scala 2677:48] + node _T_144 = bits(wr_mhpme3_r, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_8 of rvclkhdr_50 @[lib.scala 404:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_8.io.en <= _T_144 @[lib.scala 407:17] + rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_145 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_144 : @[Reg.scala 28:19] + _T_145 <= event_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpme3 <= _T_145 @[dec_tlu_ctl.scala 2679:19] + node _T_146 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2684:70] + node _T_147 = eq(_T_146, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2684:77] + node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_147) @[dec_tlu_ctl.scala 2684:48] + node _T_148 = bits(wr_mhpme4_r, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_9 of rvclkhdr_51 @[lib.scala 404:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_9.io.en <= _T_148 @[lib.scala 407:17] + rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_149 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_148 : @[Reg.scala 28:19] + _T_149 <= event_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpme4 <= _T_149 @[dec_tlu_ctl.scala 2685:19] + node _T_150 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2691:70] + node _T_151 = eq(_T_150, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2691:77] + node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_151) @[dec_tlu_ctl.scala 2691:48] + node _T_152 = bits(wr_mhpme5_r, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_10 of rvclkhdr_52 @[lib.scala 404:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_10.io.en <= _T_152 @[lib.scala 407:17] + rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_153 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_152 : @[Reg.scala 28:19] + _T_153 <= event_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpme5 <= _T_153 @[dec_tlu_ctl.scala 2692:19] + node _T_154 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2698:70] + node _T_155 = eq(_T_154, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2698:77] + node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_155) @[dec_tlu_ctl.scala 2698:48] + node _T_156 = bits(wr_mhpme6_r, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_11 of rvclkhdr_53 @[lib.scala 404:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_11.io.en <= _T_156 @[lib.scala 407:17] + rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_157 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_156 : @[Reg.scala 28:19] + _T_157 <= event_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpme6 <= _T_157 @[dec_tlu_ctl.scala 2699:19] + + extmodule gated_latch_54 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_54 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_54 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_55 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_55 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_55 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_56 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_56 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_56 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_57 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_57 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_57 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_58 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_58 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_58 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_59 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_59 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_59 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_60 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_60 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_60 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_61 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_61 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_61 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_62 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_62 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_62 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_63 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_63 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_63 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_64 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_64 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_64 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_65 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_65 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_65 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_66 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_66 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_66 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_67 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_67 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_67 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_68 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_68 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_68 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_69 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_69 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_69 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_70 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_70 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_70 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_71 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_71 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_71 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_72 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_72 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_72 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_73 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_73 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_73 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_74 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_74 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_74 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_75 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_75 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_75 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_76 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_76 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_76 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_77 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_77 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_77 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_78 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_78 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_78 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_79 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_79 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_79 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_80 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_80 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_80 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_81 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_81 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_81 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_82 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_82 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_82 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_83 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_83 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_83 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_84 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_84 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_84 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_85 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_85 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_85 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_86 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_86 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_86 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_87 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_87 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_87 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_88 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_88 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_88 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module csr_tlu : + input clock : Clock + input reset : AsyncReset + output io : {flip free_l2clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_i0_decode_d : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip ifu_ic_debug_rd_data_valid : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_pmu_bus_trxn : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, flip dec_csr_wen_r : UInt<1>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_picio_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, dec_tlu_meipt : UInt<4>, flip pic_pl : UInt<4>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meihap : UInt<30>, flip pic_claimid : UInt<8>, flip iccm_dma_sb_error : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_trace_disable : UInt<1>, flip dec_illegal_inst : UInt<32>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip mexintpend : UInt<1>, flip exu_npc_r : UInt<31>, flip mpc_reset_run_req : UInt<1>, flip rst_vec : UInt<31>, flip core_id : UInt<28>, flip dec_timer_rddata_d : UInt<32>, flip dec_timer_read_d : UInt<1>, dec_csr_wen_r_mod : UInt<1>, flip rfpc_i0_r : UInt<1>, flip i0_trigger_hit_r : UInt<1>, fw_halt_req : UInt<1>, mstatus : UInt<2>, flip exc_or_int_valid_r : UInt<1>, flip mret_r : UInt<1>, mstatus_mie_ns : UInt<1>, flip dcsr_single_step_running_f : UInt<1>, dcsr : UInt<16>, mtvec : UInt<31>, mip : UInt<6>, flip dec_timer_t0_pulse : UInt<1>, flip dec_timer_t1_pulse : UInt<1>, flip timer_int_sync : UInt<1>, flip soft_int_sync : UInt<1>, mie_ns : UInt<6>, flip csr_wr_clk : Clock, flip ebreak_to_debug_mode_r : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip lsu_fir_error : UInt<2>, npc_r : UInt<31>, flip tlu_flush_lower_r_d1 : UInt<1>, flip dec_tlu_flush_noredir_r_d1 : UInt<1>, flip tlu_flush_path_r_d1 : UInt<31>, npc_r_d1 : UInt<31>, flip reset_delayed : UInt<1>, mepc : UInt<31>, flip interrupt_valid_r : UInt<1>, flip i0_exception_valid_r : UInt<1>, flip lsu_exc_valid_r : UInt<1>, flip mepc_trigger_hit_sel_pc_r : UInt<1>, flip lsu_single_ecc_error_r : UInt<1>, flip e4e5_int_clk : Clock, flip lsu_i0_exc_r : UInt<1>, flip inst_acc_r : UInt<1>, flip inst_acc_second_r : UInt<1>, flip take_nmi : UInt<1>, flip lsu_error_pkt_addr_r : UInt<32>, flip exc_cause_r : UInt<5>, flip i0_valid_wb : UInt<1>, flip exc_or_int_valid_r_d1 : UInt<1>, flip interrupt_valid_r_d1 : UInt<1>, flip clk_override : UInt<1>, flip i0_exception_valid_r_d1 : UInt<1>, flip exc_cause_wb : UInt<5>, flip nmi_lsu_store_type : UInt<1>, flip nmi_lsu_load_type : UInt<1>, flip tlu_i0_commit_cmt : UInt<1>, flip ebreak_r : UInt<1>, flip ecall_r : UInt<1>, flip illegal_r : UInt<1>, mdseac_locked_ns : UInt<1>, mdseac_locked_f : UInt<1>, flip nmi_int_detected_f : UInt<1>, flip internal_dbg_halt_mode_f2 : UInt<1>, flip ext_int_freeze : UInt<1>, ext_int_freeze_d1 : UInt<1>, take_ext_int_start_d1 : UInt<1>, take_ext_int_start_d2 : UInt<1>, take_ext_int_start_d3 : UInt<1>, flip ic_perr_r : UInt<1>, flip iccm_sbecc_r : UInt<1>, flip ifu_miss_state_idle_f : UInt<1>, flip lsu_idle_any_f : UInt<1>, flip dbg_tlu_halted_f : UInt<1>, flip dbg_tlu_halted : UInt<1>, flip debug_halt_req_f : UInt<1>, force_halt : UInt<1>, flip take_ext_int_start : UInt<1>, flip trigger_hit_dmode_r_d1 : UInt<1>, flip trigger_hit_r_d1 : UInt<1>, flip dcsr_single_step_done_f : UInt<1>, flip ebreak_to_debug_mode_r_d1 : UInt<1>, flip debug_halt_req : UInt<1>, flip allow_dbg_halt_csr_write : UInt<1>, flip internal_dbg_halt_mode_f : UInt<1>, flip enter_debug_halt_req : UInt<1>, flip internal_dbg_halt_mode : UInt<1>, flip request_debug_mode_done : UInt<1>, flip request_debug_mode_r : UInt<1>, dpc : UInt<31>, flip update_hit_bit_r : UInt<4>, flip take_timer_int : UInt<1>, flip take_int_timer0_int : UInt<1>, flip take_int_timer1_int : UInt<1>, flip take_ext_int : UInt<1>, flip tlu_flush_lower_r : UInt<1>, flip dec_tlu_br0_error_r : UInt<1>, flip dec_tlu_br0_start_error_r : UInt<1>, flip lsu_pmu_load_external_r : UInt<1>, flip lsu_pmu_store_external_r : UInt<1>, flip csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_meicpct : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}, mtdata1_t : UInt<10>[4], flip trigger_enabled : UInt<4>, lsu_exc_valid_r_d1 : UInt<1>} + + wire miccme_ce_req : UInt<1> + miccme_ce_req <= UInt<1>("h00") + wire mice_ce_req : UInt<1> + mice_ce_req <= UInt<1>("h00") + wire mdccme_ce_req : UInt<1> + mdccme_ce_req <= UInt<1>("h00") + wire pc_r_d1 : UInt<31> + pc_r_d1 <= UInt<1>("h00") + wire mpmc_b_ns : UInt<1> + mpmc_b_ns <= UInt<1>("h00") + wire mpmc_b : UInt<1> + mpmc_b <= UInt<1>("h00") + wire mcycleh : UInt<32> + mcycleh <= UInt<1>("h00") + wire wr_minstreth_r : UInt<1> + wr_minstreth_r <= UInt<1>("h00") + wire minstretl : UInt<32> + minstretl <= UInt<1>("h00") + wire minstreth : UInt<32> + minstreth <= UInt<1>("h00") + wire mfdc_ns : UInt<16> + mfdc_ns <= UInt<1>("h00") + wire mfdc_int : UInt<16> + mfdc_int <= UInt<1>("h00") + wire mhpme_vec : UInt<10>[4] @[dec_tlu_ctl.scala 1413:47] + wire mtdata2_t : UInt<32>[4] @[dec_tlu_ctl.scala 1414:73] + wire wr_meicpct_r : UInt<1> + wr_meicpct_r <= UInt<1>("h00") + wire force_halt_ctr_f : UInt<32> + force_halt_ctr_f <= UInt<1>("h00") + wire mdccmect_inc : UInt<27> + mdccmect_inc <= UInt<1>("h00") + wire miccmect_inc : UInt<27> + miccmect_inc <= UInt<1>("h00") + wire micect_inc : UInt<27> + micect_inc <= UInt<1>("h00") + wire mdseac_en : UInt<1> + mdseac_en <= UInt<1>("h00") + wire mie : UInt<6> + mie <= UInt<1>("h00") + wire mcyclel : UInt<32> + mcyclel <= UInt<1>("h00") + wire mscratch : UInt<32> + mscratch <= UInt<1>("h00") + wire mcause : UInt<32> + mcause <= UInt<1>("h00") + wire mscause : UInt<4> + mscause <= UInt<1>("h00") + wire mtval : UInt<32> + mtval <= UInt<1>("h00") + wire meicurpl : UInt<4> + meicurpl <= UInt<1>("h00") + wire meipt : UInt<4> + meipt <= UInt<1>("h00") + wire mfdc : UInt<19> + mfdc <= UInt<1>("h00") + wire mtsel : UInt<2> + mtsel <= UInt<1>("h00") + wire micect : UInt<32> + micect <= UInt<1>("h00") + wire miccmect : UInt<32> + miccmect <= UInt<1>("h00") + wire mdccmect : UInt<32> + mdccmect <= UInt<1>("h00") + wire mfdht : UInt<6> + mfdht <= UInt<1>("h00") + wire mfdhs : UInt<2> + mfdhs <= UInt<1>("h00") + wire mcountinhibit : UInt<7> + mcountinhibit <= UInt<1>("h00") + wire mpmc : UInt<1> + mpmc <= UInt<1>("h00") + wire dicad1 : UInt<32> + dicad1 <= UInt<1>("h00") + inst perfmux_flop of perf_mux_and_flops @[dec_tlu_ctl.scala 1455:34] + perfmux_flop.clock <= clock + perfmux_flop.reset <= reset + inst perf_csrs of perf_csr @[dec_tlu_ctl.scala 1456:31] + perf_csrs.clock <= clock + perf_csrs.reset <= reset + node _T = eq(io.i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1472:52] + node _T_1 = and(io.dec_csr_wen_r, _T) @[dec_tlu_ctl.scala 1472:50] + node _T_2 = eq(io.rfpc_i0_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1472:75] + node _T_3 = and(_T_1, _T_2) @[dec_tlu_ctl.scala 1472:73] + io.dec_csr_wen_r_mod <= _T_3 @[dec_tlu_ctl.scala 1472:30] + node _T_4 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1473:71] + node _T_5 = eq(_T_4, UInt<12>("h0300")) @[dec_tlu_ctl.scala 1473:78] + node wr_mstatus_r = and(io.dec_csr_wen_r_mod, _T_5) @[dec_tlu_ctl.scala 1473:49] + node _T_6 = eq(mpmc_b_ns, UInt<1>("h00")) @[dec_tlu_ctl.scala 1476:35] + node set_mie_pmu_fw_halt = and(_T_6, io.fw_halt_req) @[dec_tlu_ctl.scala 1476:46] + node _T_7 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1479:18] + node _T_8 = and(_T_7, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1479:32] + node _T_9 = bits(_T_8, 0, 0) @[dec_tlu_ctl.scala 1479:57] + node _T_10 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1479:81] + node _T_11 = bits(_T_10, 0, 0) @[dec_tlu_ctl.scala 1479:81] + node _T_12 = cat(_T_11, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_13 = and(wr_mstatus_r, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1480:31] + node _T_14 = bits(_T_13, 0, 0) @[dec_tlu_ctl.scala 1480:56] + node _T_15 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1480:89] + node _T_16 = cat(_T_15, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_17 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1481:30] + node _T_18 = and(io.mret_r, _T_17) @[dec_tlu_ctl.scala 1481:28] + node _T_19 = bits(_T_18, 0, 0) @[dec_tlu_ctl.scala 1481:54] + node _T_20 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1481:83] + node _T_21 = cat(UInt<1>("h01"), _T_20) @[Cat.scala 29:58] + node _T_22 = bits(set_mie_pmu_fw_halt, 0, 0) @[dec_tlu_ctl.scala 1482:39] + node _T_23 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1482:63] + node _T_24 = cat(_T_23, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_25 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1483:33] + node _T_26 = and(wr_mstatus_r, _T_25) @[dec_tlu_ctl.scala 1483:31] + node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 1483:57] + node _T_28 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1483:90] + node _T_29 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1483:114] + node _T_30 = cat(_T_28, _T_29) @[Cat.scala 29:58] + node _T_31 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1484:18] + node _T_32 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1484:34] + node _T_33 = and(_T_31, _T_32) @[dec_tlu_ctl.scala 1484:32] + node _T_34 = eq(io.mret_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1484:59] + node _T_35 = and(_T_33, _T_34) @[dec_tlu_ctl.scala 1484:57] + node _T_36 = eq(set_mie_pmu_fw_halt, UInt<1>("h00")) @[dec_tlu_ctl.scala 1484:72] + node _T_37 = and(_T_35, _T_36) @[dec_tlu_ctl.scala 1484:70] + node _T_38 = bits(_T_37, 0, 0) @[dec_tlu_ctl.scala 1484:94] + node _T_39 = mux(_T_9, _T_12, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_40 = mux(_T_14, _T_16, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_41 = mux(_T_19, _T_21, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_42 = mux(_T_22, _T_24, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_43 = mux(_T_27, _T_30, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_44 = mux(_T_38, io.mstatus, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_45 = or(_T_39, _T_40) @[Mux.scala 27:72] + node _T_46 = or(_T_45, _T_41) @[Mux.scala 27:72] + node _T_47 = or(_T_46, _T_42) @[Mux.scala 27:72] + node _T_48 = or(_T_47, _T_43) @[Mux.scala 27:72] + node _T_49 = or(_T_48, _T_44) @[Mux.scala 27:72] + wire mstatus_ns : UInt<2> @[Mux.scala 27:72] + mstatus_ns <= _T_49 @[Mux.scala 27:72] + node _T_50 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1489:40] + node _T_51 = bits(_T_50, 0, 0) @[dec_tlu_ctl.scala 1489:40] + node _T_52 = not(io.dcsr_single_step_running_f) @[dec_tlu_ctl.scala 1489:57] + node _T_53 = bits(io.dcsr, 11, 11) @[dec_tlu_ctl.scala 1489:97] + node _T_54 = or(_T_52, _T_53) @[dec_tlu_ctl.scala 1489:88] + node _T_55 = and(_T_51, _T_54) @[dec_tlu_ctl.scala 1489:54] + io.mstatus_mie_ns <= _T_55 @[dec_tlu_ctl.scala 1489:27] + node _T_56 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1500:69] + node _T_57 = eq(_T_56, UInt<12>("h0305")) @[dec_tlu_ctl.scala 1500:76] + node wr_mtvec_r = and(io.dec_csr_wen_r_mod, _T_57) @[dec_tlu_ctl.scala 1500:47] + node _T_58 = bits(io.dec_csr_wrdata_r, 31, 2) @[dec_tlu_ctl.scala 1501:47] + node _T_59 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1501:75] + node mtvec_ns = cat(_T_58, _T_59) @[Cat.scala 29:58] + node _T_60 = bits(wr_mtvec_r, 0, 0) @[dec_tlu_ctl.scala 1502:49] + inst rvclkhdr of rvclkhdr_54 @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= _T_60 @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_61 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_60 : @[Reg.scala 28:19] + _T_61 <= mtvec_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mtvec <= _T_61 @[dec_tlu_ctl.scala 1502:18] + node _T_62 = or(mdccme_ce_req, miccme_ce_req) @[dec_tlu_ctl.scala 1514:37] + node ce_int = or(_T_62, mice_ce_req) @[dec_tlu_ctl.scala 1514:53] + node _T_63 = cat(io.mexintpend, io.timer_int_sync) @[Cat.scala 29:58] + node _T_64 = cat(_T_63, io.soft_int_sync) @[Cat.scala 29:58] + node _T_65 = cat(ce_int, io.dec_timer_t0_pulse) @[Cat.scala 29:58] + node _T_66 = cat(_T_65, io.dec_timer_t1_pulse) @[Cat.scala 29:58] + node mip_ns = cat(_T_66, _T_64) @[Cat.scala 29:58] + node _T_67 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1530:67] + node _T_68 = eq(_T_67, UInt<12>("h0304")) @[dec_tlu_ctl.scala 1530:74] + node wr_mie_r = and(io.dec_csr_wen_r_mod, _T_68) @[dec_tlu_ctl.scala 1530:45] + node _T_69 = bits(wr_mie_r, 0, 0) @[dec_tlu_ctl.scala 1531:35] + node _T_70 = bits(io.dec_csr_wrdata_r, 30, 28) @[dec_tlu_ctl.scala 1531:66] + node _T_71 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1531:95] + node _T_72 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1531:120] + node _T_73 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1531:144] + node _T_74 = cat(_T_72, _T_73) @[Cat.scala 29:58] + node _T_75 = cat(_T_70, _T_71) @[Cat.scala 29:58] + node _T_76 = cat(_T_75, _T_74) @[Cat.scala 29:58] + node _T_77 = mux(_T_69, _T_76, mie) @[dec_tlu_ctl.scala 1531:25] + io.mie_ns <= _T_77 @[dec_tlu_ctl.scala 1531:19] + reg _T_78 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1533:24] + _T_78 <= io.mie_ns @[dec_tlu_ctl.scala 1533:24] + mie <= _T_78 @[dec_tlu_ctl.scala 1532:13] + node _T_79 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1539:70] + node kill_ebreak_count_r = and(io.ebreak_to_debug_mode_r, _T_79) @[dec_tlu_ctl.scala 1539:61] + node _T_80 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1541:71] + node _T_81 = eq(_T_80, UInt<12>("h0b00")) @[dec_tlu_ctl.scala 1541:78] + node wr_mcyclel_r = and(io.dec_csr_wen_r_mod, _T_81) @[dec_tlu_ctl.scala 1541:49] + node _T_82 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1543:87] + node _T_83 = and(io.dec_tlu_dbg_halted, _T_82) @[dec_tlu_ctl.scala 1543:78] + node _T_84 = or(kill_ebreak_count_r, _T_83) @[dec_tlu_ctl.scala 1543:53] + node _T_85 = or(_T_84, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 1543:101] + node _T_86 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 1543:143] + node _T_87 = or(_T_85, _T_86) @[dec_tlu_ctl.scala 1543:128] + node mcyclel_cout_in = not(_T_87) @[dec_tlu_ctl.scala 1543:31] + wire mcyclel_inc1 : UInt<9> + mcyclel_inc1 <= UInt<1>("h00") + wire mcyclel_inc2 : UInt<25> + mcyclel_inc2 <= UInt<1>("h00") + node _T_88 = bits(mcyclel, 7, 0) @[dec_tlu_ctl.scala 1548:32] + node _T_89 = cat(UInt<7>("h00"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_90 = add(_T_88, _T_89) @[dec_tlu_ctl.scala 1548:38] + mcyclel_inc1 <= _T_90 @[dec_tlu_ctl.scala 1548:22] + node _T_91 = bits(mcyclel, 31, 8) @[dec_tlu_ctl.scala 1549:32] + node _T_92 = bits(mcyclel_inc1, 8, 8) @[dec_tlu_ctl.scala 1549:70] + node _T_93 = cat(UInt<23>("h00"), _T_92) @[Cat.scala 29:58] + node _T_94 = add(_T_91, _T_93) @[dec_tlu_ctl.scala 1549:39] + mcyclel_inc2 <= _T_94 @[dec_tlu_ctl.scala 1549:22] + node _T_95 = bits(mcyclel_inc2, 23, 0) @[dec_tlu_ctl.scala 1550:47] + node _T_96 = bits(mcyclel_inc1, 7, 0) @[dec_tlu_ctl.scala 1550:66] + node mcyclel_inc = cat(_T_95, _T_96) @[Cat.scala 29:58] + node _T_97 = bits(wr_mcyclel_r, 0, 0) @[dec_tlu_ctl.scala 1551:43] + node _T_98 = bits(mcyclel_inc, 31, 0) @[dec_tlu_ctl.scala 1551:83] + node mcyclel_ns = mux(_T_97, io.dec_csr_wrdata_r, _T_98) @[dec_tlu_ctl.scala 1551:29] + node _T_99 = bits(mcyclel_inc2, 24, 24) @[dec_tlu_ctl.scala 1552:40] + node mcyclel_cout = bits(_T_99, 0, 0) @[dec_tlu_ctl.scala 1552:45] + node _T_100 = bits(mcyclel_ns, 31, 8) @[dec_tlu_ctl.scala 1553:41] + node _T_101 = bits(mcyclel_inc1, 8, 8) @[dec_tlu_ctl.scala 1553:78] + node _T_102 = and(_T_101, mcyclel_cout_in) @[dec_tlu_ctl.scala 1553:82] + node _T_103 = bits(_T_102, 0, 0) @[dec_tlu_ctl.scala 1553:108] + node _T_104 = or(wr_mcyclel_r, _T_103) @[dec_tlu_ctl.scala 1553:63] + node _T_105 = bits(_T_104, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_1 of rvclkhdr_55 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_105 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_106 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_105 : @[Reg.scala 28:19] + _T_106 <= _T_100 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_107 = bits(mcyclel_ns, 7, 0) @[dec_tlu_ctl.scala 1553:163] + node _T_108 = or(wr_mcyclel_r, mcyclel_cout_in) @[dec_tlu_ctl.scala 1553:184] + node _T_109 = bits(_T_108, 0, 0) @[dec_tlu_ctl.scala 1553:210] + inst rvclkhdr_2 of rvclkhdr_56 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_2.io.en <= _T_109 @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_110 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_109 : @[Reg.scala 28:19] + _T_110 <= _T_107 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_111 = cat(_T_106, _T_110) @[Cat.scala 29:58] + mcyclel <= _T_111 @[dec_tlu_ctl.scala 1553:17] + node _T_112 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1560:71] + node _T_113 = eq(_T_112, UInt<12>("h0b80")) @[dec_tlu_ctl.scala 1560:78] + node wr_mcycleh_r = and(io.dec_csr_wen_r_mod, _T_113) @[dec_tlu_ctl.scala 1560:49] + node _T_114 = cat(UInt<31>("h00"), perfmux_flop.io.mcyclel_cout_f) @[Cat.scala 29:58] + node _T_115 = add(mcycleh, _T_114) @[dec_tlu_ctl.scala 1562:35] + node mcycleh_inc = tail(_T_115, 1) @[dec_tlu_ctl.scala 1562:35] + node _T_116 = bits(wr_mcycleh_r, 0, 0) @[dec_tlu_ctl.scala 1563:43] + node mcycleh_ns = mux(_T_116, io.dec_csr_wrdata_r, mcycleh_inc) @[dec_tlu_ctl.scala 1563:29] + node _T_117 = or(wr_mcycleh_r, perfmux_flop.io.mcyclel_cout_f) @[dec_tlu_ctl.scala 1565:53] + node _T_118 = bits(_T_117, 0, 0) @[dec_tlu_ctl.scala 1565:87] + inst rvclkhdr_3 of rvclkhdr_57 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_3.io.en <= _T_118 @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_119 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_118 : @[Reg.scala 28:19] + _T_119 <= mcycleh_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mcycleh <= _T_119 @[dec_tlu_ctl.scala 1565:17] + node _T_120 = or(io.ebreak_r, io.ecall_r) @[dec_tlu_ctl.scala 1579:81] + node _T_121 = or(_T_120, io.ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 1579:94] + node _T_122 = or(_T_121, io.illegal_r) @[dec_tlu_ctl.scala 1579:122] + node _T_123 = bits(mcountinhibit, 2, 2) @[dec_tlu_ctl.scala 1579:152] + node _T_124 = or(_T_122, _T_123) @[dec_tlu_ctl.scala 1579:137] + node _T_125 = eq(_T_124, UInt<1>("h00")) @[dec_tlu_ctl.scala 1579:67] + node _T_126 = and(io.dec_tlu_i0_valid_r, _T_125) @[dec_tlu_ctl.scala 1579:65] + node i0_valid_no_ebreak_ecall_r = bits(_T_126, 0, 0) @[dec_tlu_ctl.scala 1579:164] + node _T_127 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1581:73] + node _T_128 = eq(_T_127, UInt<12>("h0b02")) @[dec_tlu_ctl.scala 1581:80] + node wr_minstretl_r = and(io.dec_csr_wen_r_mod, _T_128) @[dec_tlu_ctl.scala 1581:51] + wire minstretl_inc1 : UInt<9> + minstretl_inc1 <= UInt<1>("h00") + wire minstretl_inc2 : UInt<25> + minstretl_inc2 <= UInt<1>("h00") + node _T_129 = bits(minstretl, 7, 0) @[dec_tlu_ctl.scala 1585:36] + node _T_130 = cat(UInt<7>("h00"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_131 = add(_T_129, _T_130) @[dec_tlu_ctl.scala 1585:42] + minstretl_inc1 <= _T_131 @[dec_tlu_ctl.scala 1585:24] + node _T_132 = bits(minstretl, 31, 8) @[dec_tlu_ctl.scala 1586:36] + node _T_133 = bits(minstretl_inc1, 8, 8) @[dec_tlu_ctl.scala 1586:75] + node _T_134 = cat(UInt<23>("h00"), _T_133) @[Cat.scala 29:58] + node _T_135 = add(_T_132, _T_134) @[dec_tlu_ctl.scala 1586:43] + minstretl_inc2 <= _T_135 @[dec_tlu_ctl.scala 1586:24] + node minstretl_cout = bits(minstretl_inc2, 24, 24) @[dec_tlu_ctl.scala 1587:44] + node _T_136 = bits(minstretl_inc2, 23, 0) @[dec_tlu_ctl.scala 1588:47] + node _T_137 = bits(minstretl_inc1, 7, 0) @[dec_tlu_ctl.scala 1588:68] + node minstretl_inc = cat(_T_136, _T_137) @[Cat.scala 29:58] + node _T_138 = and(i0_valid_no_ebreak_ecall_r, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 1589:59] + node minstret_enable = or(_T_138, wr_minstretl_r) @[dec_tlu_ctl.scala 1589:83] + node _T_139 = eq(wr_minstreth_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1590:50] + node _T_140 = and(minstretl_cout, _T_139) @[dec_tlu_ctl.scala 1590:48] + node _T_141 = and(_T_140, i0_valid_no_ebreak_ecall_r) @[dec_tlu_ctl.scala 1590:66] + node _T_142 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1590:97] + node minstretl_cout_ns = and(_T_141, _T_142) @[dec_tlu_ctl.scala 1590:95] + node _T_143 = bits(wr_minstretl_r, 0, 0) @[dec_tlu_ctl.scala 1593:47] + node _T_144 = bits(minstretl_inc, 31, 0) @[dec_tlu_ctl.scala 1593:90] + node minstretl_ns = mux(_T_143, io.dec_csr_wrdata_r, _T_144) @[dec_tlu_ctl.scala 1593:31] + node _T_145 = bits(minstretl_ns, 31, 8) @[dec_tlu_ctl.scala 1595:45] + node _T_146 = bits(minstretl_inc1, 8, 8) @[dec_tlu_ctl.scala 1595:84] + node _T_147 = and(_T_146, minstret_enable) @[dec_tlu_ctl.scala 1595:88] + node _T_148 = or(wr_minstretl_r, _T_147) @[dec_tlu_ctl.scala 1595:67] + node _T_149 = bits(_T_148, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_4 of rvclkhdr_58 @[lib.scala 404:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_4.io.en <= _T_149 @[lib.scala 407:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_150 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_149 : @[Reg.scala 28:19] + _T_150 <= _T_145 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_151 = bits(minstretl_ns, 7, 0) @[dec_tlu_ctl.scala 1595:146] + node _T_152 = bits(minstret_enable, 0, 0) @[dec_tlu_ctl.scala 1595:168] + inst rvclkhdr_5 of rvclkhdr_59 @[lib.scala 404:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_5.io.en <= _T_152 @[lib.scala 407:17] + rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_153 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_152 : @[Reg.scala 28:19] + _T_153 <= _T_151 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_154 = cat(_T_150, _T_153) @[Cat.scala 29:58] + minstretl <= _T_154 @[dec_tlu_ctl.scala 1595:19] + node _T_155 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1605:71] + node _T_156 = eq(_T_155, UInt<12>("h0b82")) @[dec_tlu_ctl.scala 1605:78] + node _T_157 = and(io.dec_csr_wen_r_mod, _T_156) @[dec_tlu_ctl.scala 1605:49] + node _T_158 = bits(_T_157, 0, 0) @[dec_tlu_ctl.scala 1605:94] + wr_minstreth_r <= _T_158 @[dec_tlu_ctl.scala 1605:24] + node _T_159 = cat(UInt<31>("h00"), perfmux_flop.io.minstretl_cout_f) @[Cat.scala 29:58] + node _T_160 = add(minstreth, _T_159) @[dec_tlu_ctl.scala 1609:39] + node minstreth_inc = tail(_T_160, 1) @[dec_tlu_ctl.scala 1609:39] + node _T_161 = bits(wr_minstreth_r, 0, 0) @[dec_tlu_ctl.scala 1610:48] + node minstreth_ns = mux(_T_161, io.dec_csr_wrdata_r, minstreth_inc) @[dec_tlu_ctl.scala 1610:32] + node _T_162 = and(perfmux_flop.io.minstret_enable_f, perfmux_flop.io.minstretl_cout_f) @[dec_tlu_ctl.scala 1612:79] + node _T_163 = or(_T_162, wr_minstreth_r) @[dec_tlu_ctl.scala 1612:116] + node _T_164 = bits(_T_163, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_6 of rvclkhdr_60 @[lib.scala 404:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_6.io.en <= _T_164 @[lib.scala 407:17] + rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_165 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_164 : @[Reg.scala 28:19] + _T_165 <= minstreth_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + minstreth <= _T_165 @[dec_tlu_ctl.scala 1612:19] + node _T_166 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1620:72] + node _T_167 = eq(_T_166, UInt<12>("h0340")) @[dec_tlu_ctl.scala 1620:79] + node wr_mscratch_r = and(io.dec_csr_wen_r_mod, _T_167) @[dec_tlu_ctl.scala 1620:50] + node _T_168 = bits(wr_mscratch_r, 0, 0) @[dec_tlu_ctl.scala 1622:62] + inst rvclkhdr_7 of rvclkhdr_61 @[lib.scala 404:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_7.io.en <= _T_168 @[lib.scala 407:17] + rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_169 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_168 : @[Reg.scala 28:19] + _T_169 <= io.dec_csr_wrdata_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mscratch <= _T_169 @[dec_tlu_ctl.scala 1622:18] + node _T_170 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1631:29] + node _T_171 = eq(io.tlu_flush_lower_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1631:54] + node _T_172 = and(_T_170, _T_171) @[dec_tlu_ctl.scala 1631:52] + node sel_exu_npc_r = and(_T_172, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1631:79] + node _T_173 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1632:31] + node _T_174 = and(_T_173, io.tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 1632:54] + node _T_175 = eq(io.dec_tlu_flush_noredir_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1632:82] + node sel_flush_npc_r = and(_T_174, _T_175) @[dec_tlu_ctl.scala 1632:80] + node _T_176 = eq(sel_exu_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1633:30] + node _T_177 = eq(sel_flush_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1633:47] + node sel_hold_npc_r = and(_T_176, _T_177) @[dec_tlu_ctl.scala 1633:45] + node _T_178 = bits(sel_exu_npc_r, 0, 0) @[dec_tlu_ctl.scala 1636:31] + node _T_179 = eq(io.mpc_reset_run_req, UInt<1>("h00")) @[dec_tlu_ctl.scala 1637:18] + node _T_180 = and(_T_179, io.reset_delayed) @[dec_tlu_ctl.scala 1637:40] + node _T_181 = bits(_T_180, 0, 0) @[dec_tlu_ctl.scala 1637:60] + node _T_182 = bits(sel_flush_npc_r, 0, 0) @[dec_tlu_ctl.scala 1638:33] + node _T_183 = bits(sel_hold_npc_r, 0, 0) @[dec_tlu_ctl.scala 1639:32] + node _T_184 = mux(_T_178, io.exu_npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_185 = mux(_T_181, io.rst_vec, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_186 = mux(_T_182, io.tlu_flush_path_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_187 = mux(_T_183, io.npc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_188 = or(_T_184, _T_185) @[Mux.scala 27:72] + node _T_189 = or(_T_188, _T_186) @[Mux.scala 27:72] + node _T_190 = or(_T_189, _T_187) @[Mux.scala 27:72] + wire _T_191 : UInt<31> @[Mux.scala 27:72] + _T_191 <= _T_190 @[Mux.scala 27:72] + io.npc_r <= _T_191 @[dec_tlu_ctl.scala 1635:18] + node _T_192 = or(sel_exu_npc_r, sel_flush_npc_r) @[dec_tlu_ctl.scala 1641:58] + node _T_193 = or(_T_192, io.reset_delayed) @[dec_tlu_ctl.scala 1641:76] + node _T_194 = bits(_T_193, 0, 0) @[dec_tlu_ctl.scala 1641:96] + wire _T_195 : UInt<31> @[lib.scala 648:38] + _T_195 <= UInt<1>("h00") @[lib.scala 648:38] + reg _T_196 : UInt, clock with : (reset => (reset, _T_195)) @[Reg.scala 27:20] + when _T_194 : @[Reg.scala 28:19] + _T_196 <= io.npc_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.npc_r_d1 <= _T_196 @[dec_tlu_ctl.scala 1641:21] + node _T_197 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1644:28] + node _T_198 = and(_T_197, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1644:51] + node pc0_valid_r = bits(_T_198, 0, 0) @[dec_tlu_ctl.scala 1644:76] + node _T_199 = not(pc0_valid_r) @[dec_tlu_ctl.scala 1648:17] + node _T_200 = mux(pc0_valid_r, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_201 = mux(_T_199, pc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_202 = or(_T_200, _T_201) @[Mux.scala 27:72] + wire pc_r : UInt<31> @[Mux.scala 27:72] + pc_r <= _T_202 @[Mux.scala 27:72] + wire _T_203 : UInt<31> @[lib.scala 648:38] + _T_203 <= UInt<1>("h00") @[lib.scala 648:38] + reg _T_204 : UInt, clock with : (reset => (reset, _T_203)) @[Reg.scala 27:20] + when pc0_valid_r : @[Reg.scala 28:19] + _T_204 <= pc_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + pc_r_d1 <= _T_204 @[dec_tlu_ctl.scala 1650:17] + node _T_205 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1652:68] + node _T_206 = eq(_T_205, UInt<12>("h0341")) @[dec_tlu_ctl.scala 1652:75] + node wr_mepc_r = and(io.dec_csr_wen_r_mod, _T_206) @[dec_tlu_ctl.scala 1652:46] + node _T_207 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1655:42] + node _T_208 = or(_T_207, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1655:63] + node _T_209 = bits(_T_208, 0, 0) @[dec_tlu_ctl.scala 1655:95] + node _T_210 = bits(io.interrupt_valid_r, 0, 0) @[dec_tlu_ctl.scala 1656:40] + node _T_211 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1657:30] + node _T_212 = and(wr_mepc_r, _T_211) @[dec_tlu_ctl.scala 1657:28] + node _T_213 = bits(_T_212, 0, 0) @[dec_tlu_ctl.scala 1657:54] + node _T_214 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 1657:119] + node _T_215 = eq(wr_mepc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1658:18] + node _T_216 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1658:31] + node _T_217 = and(_T_215, _T_216) @[dec_tlu_ctl.scala 1658:29] + node _T_218 = bits(_T_217, 0, 0) @[dec_tlu_ctl.scala 1658:55] + node _T_219 = mux(_T_209, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_220 = mux(_T_210, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_221 = mux(_T_213, _T_214, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_222 = mux(_T_218, io.mepc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_223 = or(_T_219, _T_220) @[Mux.scala 27:72] + node _T_224 = or(_T_223, _T_221) @[Mux.scala 27:72] + node _T_225 = or(_T_224, _T_222) @[Mux.scala 27:72] + wire mepc_ns : UInt<31> @[Mux.scala 27:72] + mepc_ns <= _T_225 @[Mux.scala 27:72] + node _T_226 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1660:59] + node _T_227 = or(_T_226, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1660:80] + node _T_228 = or(_T_227, io.interrupt_valid_r) @[dec_tlu_ctl.scala 1660:111] + node _T_229 = or(_T_228, wr_mepc_r) @[dec_tlu_ctl.scala 1660:134] + node _T_230 = bits(_T_229, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_8 of rvclkhdr_62 @[lib.scala 404:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_8.io.en <= _T_230 @[lib.scala 407:17] + rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_231 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_230 : @[Reg.scala 28:19] + _T_231 <= mepc_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mepc <= _T_231 @[dec_tlu_ctl.scala 1660:17] + node _T_232 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1668:70] + node _T_233 = eq(_T_232, UInt<12>("h0342")) @[dec_tlu_ctl.scala 1668:77] + node wr_mcause_r = and(io.dec_csr_wen_r_mod, _T_233) @[dec_tlu_ctl.scala 1668:48] + node _T_234 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1669:58] + node mcause_sel_nmi_store = and(_T_234, io.nmi_lsu_store_type) @[dec_tlu_ctl.scala 1669:72] + node _T_235 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1670:57] + node mcause_sel_nmi_load = and(_T_235, io.nmi_lsu_load_type) @[dec_tlu_ctl.scala 1670:71] + node _T_236 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1671:55] + node _T_237 = and(_T_236, io.take_ext_int_start_d3) @[dec_tlu_ctl.scala 1671:69] + node _T_238 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1671:115] + node _T_239 = and(_T_237, _T_238) @[dec_tlu_ctl.scala 1671:96] + node _T_240 = eq(io.nmi_int_detected_f, UInt<1>("h00")) @[dec_tlu_ctl.scala 1671:121] + node mcause_sel_nmi_ext = and(_T_239, _T_240) @[dec_tlu_ctl.scala 1671:119] + node _T_241 = andr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1678:58] + node _T_242 = bits(io.lsu_fir_error, 1, 1) @[dec_tlu_ctl.scala 1678:81] + node _T_243 = bits(io.lsu_fir_error, 0, 0) @[dec_tlu_ctl.scala 1678:104] + node _T_244 = not(_T_243) @[dec_tlu_ctl.scala 1678:87] + node _T_245 = and(_T_242, _T_244) @[dec_tlu_ctl.scala 1678:85] + node mcause_fir_error_type = cat(_T_241, _T_245) @[Cat.scala 29:58] + node _T_246 = bits(mcause_sel_nmi_store, 0, 0) @[dec_tlu_ctl.scala 1681:38] + node _T_247 = bits(mcause_sel_nmi_load, 0, 0) @[dec_tlu_ctl.scala 1682:37] + node _T_248 = bits(mcause_sel_nmi_ext, 0, 0) @[dec_tlu_ctl.scala 1683:36] + node _T_249 = cat(UInt<28>("h0f000100"), UInt<2>("h00")) @[Cat.scala 29:58] + node _T_250 = cat(_T_249, mcause_fir_error_type) @[Cat.scala 29:58] + node _T_251 = eq(io.take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 1684:42] + node _T_252 = and(io.exc_or_int_valid_r, _T_251) @[dec_tlu_ctl.scala 1684:40] + node _T_253 = bits(_T_252, 0, 0) @[dec_tlu_ctl.scala 1684:56] + node _T_254 = cat(io.interrupt_valid_r, UInt<26>("h00")) @[Cat.scala 29:58] + node _T_255 = cat(_T_254, io.exc_cause_r) @[Cat.scala 29:58] + node _T_256 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1685:32] + node _T_257 = and(wr_mcause_r, _T_256) @[dec_tlu_ctl.scala 1685:30] + node _T_258 = bits(_T_257, 0, 0) @[dec_tlu_ctl.scala 1685:56] + node _T_259 = eq(wr_mcause_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1686:18] + node _T_260 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1686:33] + node _T_261 = and(_T_259, _T_260) @[dec_tlu_ctl.scala 1686:31] + node _T_262 = bits(_T_261, 0, 0) @[dec_tlu_ctl.scala 1686:57] + node _T_263 = mux(_T_246, UInt<32>("h0f0000000"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_264 = mux(_T_247, UInt<32>("h0f0000001"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_265 = mux(_T_248, _T_250, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_266 = mux(_T_253, _T_255, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_267 = mux(_T_258, io.dec_csr_wrdata_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_268 = mux(_T_262, mcause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_269 = or(_T_263, _T_264) @[Mux.scala 27:72] + node _T_270 = or(_T_269, _T_265) @[Mux.scala 27:72] + node _T_271 = or(_T_270, _T_266) @[Mux.scala 27:72] + node _T_272 = or(_T_271, _T_267) @[Mux.scala 27:72] + node _T_273 = or(_T_272, _T_268) @[Mux.scala 27:72] + wire mcause_ns : UInt<32> @[Mux.scala 27:72] + mcause_ns <= _T_273 @[Mux.scala 27:72] + node _T_274 = or(io.exc_or_int_valid_r, wr_mcause_r) @[dec_tlu_ctl.scala 1688:58] + node _T_275 = bits(_T_274, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_9 of rvclkhdr_63 @[lib.scala 404:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_9.io.en <= _T_275 @[lib.scala 407:17] + rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_276 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_275 : @[Reg.scala 28:19] + _T_276 <= mcause_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mcause <= _T_276 @[dec_tlu_ctl.scala 1688:16] + node _T_277 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1695:71] + node _T_278 = eq(_T_277, UInt<12>("h07ff")) @[dec_tlu_ctl.scala 1695:78] + node wr_mscause_r = and(io.dec_csr_wen_r_mod, _T_278) @[dec_tlu_ctl.scala 1695:49] + node _T_279 = eq(io.dec_tlu_packet_r.icaf_type, UInt<2>("h00")) @[dec_tlu_ctl.scala 1697:63] + node _T_280 = cat(UInt<2>("h00"), io.dec_tlu_packet_r.icaf_type) @[Cat.scala 29:58] + node ifu_mscause = mux(_T_279, UInt<4>("h09"), _T_280) @[dec_tlu_ctl.scala 1697:31] + node _T_281 = bits(io.lsu_i0_exc_r, 0, 0) @[dec_tlu_ctl.scala 1700:33] + node _T_282 = bits(io.i0_trigger_hit_r, 0, 0) @[dec_tlu_ctl.scala 1701:37] + node _T_283 = bits(io.ebreak_r, 0, 0) @[dec_tlu_ctl.scala 1702:29] + node _T_284 = bits(io.inst_acc_r, 0, 0) @[dec_tlu_ctl.scala 1703:31] + node _T_285 = mux(_T_281, io.lsu_error_pkt_r.bits.mscause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_286 = mux(_T_282, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_287 = mux(_T_283, UInt<4>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_288 = mux(_T_284, ifu_mscause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_289 = or(_T_285, _T_286) @[Mux.scala 27:72] + node _T_290 = or(_T_289, _T_287) @[Mux.scala 27:72] + node _T_291 = or(_T_290, _T_288) @[Mux.scala 27:72] + wire mscause_type : UInt<4> @[Mux.scala 27:72] + mscause_type <= _T_291 @[Mux.scala 27:72] + node _T_292 = bits(io.exc_or_int_valid_r, 0, 0) @[dec_tlu_ctl.scala 1707:41] + node _T_293 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1708:33] + node _T_294 = and(wr_mscause_r, _T_293) @[dec_tlu_ctl.scala 1708:31] + node _T_295 = bits(_T_294, 0, 0) @[dec_tlu_ctl.scala 1708:57] + node _T_296 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1708:96] + node _T_297 = eq(wr_mscause_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1709:18] + node _T_298 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1709:34] + node _T_299 = and(_T_297, _T_298) @[dec_tlu_ctl.scala 1709:32] + node _T_300 = bits(_T_299, 0, 0) @[dec_tlu_ctl.scala 1709:58] + node _T_301 = mux(_T_292, mscause_type, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_302 = mux(_T_295, _T_296, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_303 = mux(_T_300, mscause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_304 = or(_T_301, _T_302) @[Mux.scala 27:72] + node _T_305 = or(_T_304, _T_303) @[Mux.scala 27:72] + wire mscause_ns : UInt<4> @[Mux.scala 27:72] + mscause_ns <= _T_305 @[Mux.scala 27:72] + reg _T_306 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1711:54] + _T_306 <= mscause_ns @[dec_tlu_ctl.scala 1711:54] + mscause <= _T_306 @[dec_tlu_ctl.scala 1711:17] + node _T_307 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1718:69] + node _T_308 = eq(_T_307, UInt<12>("h0343")) @[dec_tlu_ctl.scala 1718:76] + node wr_mtval_r = and(io.dec_csr_wen_r_mod, _T_308) @[dec_tlu_ctl.scala 1718:47] + node _T_309 = not(io.inst_acc_second_r) @[dec_tlu_ctl.scala 1719:90] + node _T_310 = and(io.inst_acc_r, _T_309) @[dec_tlu_ctl.scala 1719:88] + node _T_311 = or(io.ebreak_r, _T_310) @[dec_tlu_ctl.scala 1719:71] + node _T_312 = or(_T_311, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1719:113] + node _T_313 = and(io.exc_or_int_valid_r, _T_312) @[dec_tlu_ctl.scala 1719:56] + node _T_314 = not(io.take_nmi) @[dec_tlu_ctl.scala 1719:147] + node mtval_capture_pc_r = and(_T_313, _T_314) @[dec_tlu_ctl.scala 1719:145] + node _T_315 = and(io.inst_acc_r, io.inst_acc_second_r) @[dec_tlu_ctl.scala 1720:79] + node _T_316 = and(io.exc_or_int_valid_r, _T_315) @[dec_tlu_ctl.scala 1720:62] + node _T_317 = not(io.take_nmi) @[dec_tlu_ctl.scala 1720:105] + node mtval_capture_pc_plus2_r = and(_T_316, _T_317) @[dec_tlu_ctl.scala 1720:103] + node _T_318 = and(io.exc_or_int_valid_r, io.illegal_r) @[dec_tlu_ctl.scala 1721:58] + node _T_319 = not(io.take_nmi) @[dec_tlu_ctl.scala 1721:75] + node mtval_capture_inst_r = and(_T_318, _T_319) @[dec_tlu_ctl.scala 1721:73] + node _T_320 = and(io.exc_or_int_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1722:57] + node _T_321 = not(io.take_nmi) @[dec_tlu_ctl.scala 1722:80] + node mtval_capture_lsu_r = and(_T_320, _T_321) @[dec_tlu_ctl.scala 1722:78] + node _T_322 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1723:53] + node _T_323 = and(io.exc_or_int_valid_r, _T_322) @[dec_tlu_ctl.scala 1723:51] + node _T_324 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1723:75] + node _T_325 = and(_T_323, _T_324) @[dec_tlu_ctl.scala 1723:73] + node _T_326 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1723:99] + node _T_327 = and(_T_325, _T_326) @[dec_tlu_ctl.scala 1723:97] + node _T_328 = not(io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1723:122] + node mtval_clear_r = and(_T_327, _T_328) @[dec_tlu_ctl.scala 1723:120] + node _T_329 = bits(mtval_capture_pc_r, 0, 0) @[dec_tlu_ctl.scala 1727:38] + node _T_330 = cat(pc_r, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_331 = bits(mtval_capture_pc_plus2_r, 0, 0) @[dec_tlu_ctl.scala 1728:44] + node _T_332 = add(pc_r, UInt<31>("h01")) @[dec_tlu_ctl.scala 1728:96] + node _T_333 = tail(_T_332, 1) @[dec_tlu_ctl.scala 1728:96] + node _T_334 = cat(_T_333, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_335 = bits(mtval_capture_inst_r, 0, 0) @[dec_tlu_ctl.scala 1729:40] + node _T_336 = bits(mtval_capture_lsu_r, 0, 0) @[dec_tlu_ctl.scala 1730:39] + node _T_337 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1731:31] + node _T_338 = and(wr_mtval_r, _T_337) @[dec_tlu_ctl.scala 1731:29] + node _T_339 = bits(_T_338, 0, 0) @[dec_tlu_ctl.scala 1731:61] + node _T_340 = not(io.take_nmi) @[dec_tlu_ctl.scala 1732:18] + node _T_341 = not(wr_mtval_r) @[dec_tlu_ctl.scala 1732:33] + node _T_342 = and(_T_340, _T_341) @[dec_tlu_ctl.scala 1732:31] + node _T_343 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1732:47] + node _T_344 = and(_T_342, _T_343) @[dec_tlu_ctl.scala 1732:45] + node _T_345 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1732:69] + node _T_346 = and(_T_344, _T_345) @[dec_tlu_ctl.scala 1732:67] + node _T_347 = not(mtval_clear_r) @[dec_tlu_ctl.scala 1732:93] + node _T_348 = and(_T_346, _T_347) @[dec_tlu_ctl.scala 1732:91] + node _T_349 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1732:110] + node _T_350 = and(_T_348, _T_349) @[dec_tlu_ctl.scala 1732:108] + node _T_351 = bits(_T_350, 0, 0) @[dec_tlu_ctl.scala 1732:132] + node _T_352 = mux(_T_329, _T_330, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_353 = mux(_T_331, _T_334, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_354 = mux(_T_335, io.dec_illegal_inst, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_355 = mux(_T_336, io.lsu_error_pkt_addr_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_356 = mux(_T_339, io.dec_csr_wrdata_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_357 = mux(_T_351, mtval, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_358 = or(_T_352, _T_353) @[Mux.scala 27:72] + node _T_359 = or(_T_358, _T_354) @[Mux.scala 27:72] + node _T_360 = or(_T_359, _T_355) @[Mux.scala 27:72] + node _T_361 = or(_T_360, _T_356) @[Mux.scala 27:72] + node _T_362 = or(_T_361, _T_357) @[Mux.scala 27:72] + wire mtval_ns : UInt<32> @[Mux.scala 27:72] + mtval_ns <= _T_362 @[Mux.scala 27:72] + node _T_363 = or(io.tlu_flush_lower_r, wr_mtval_r) @[dec_tlu_ctl.scala 1734:55] + node _T_364 = bits(_T_363, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_10 of rvclkhdr_64 @[lib.scala 404:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_10.io.en <= _T_364 @[lib.scala 407:17] + rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_365 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_364 : @[Reg.scala 28:19] + _T_365 <= mtval_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mtval <= _T_365 @[dec_tlu_ctl.scala 1734:15] + wire mcgc_int : UInt<10> + mcgc_int <= UInt<1>("h00") + node _T_366 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1752:68] + node _T_367 = eq(_T_366, UInt<12>("h07f8")) @[dec_tlu_ctl.scala 1752:75] + node wr_mcgc_r = and(io.dec_csr_wen_r_mod, _T_367) @[dec_tlu_ctl.scala 1752:46] + node _T_368 = bits(wr_mcgc_r, 0, 0) @[lib.scala 8:44] + node _T_369 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1753:62] + node _T_370 = not(_T_369) @[dec_tlu_ctl.scala 1753:42] + node _T_371 = bits(io.dec_csr_wrdata_r, 8, 0) @[dec_tlu_ctl.scala 1753:86] + node _T_372 = cat(_T_370, _T_371) @[Cat.scala 29:58] + node mcgc_ns = mux(_T_368, _T_372, mcgc_int) @[dec_tlu_ctl.scala 1753:26] + node _T_373 = bits(wr_mcgc_r, 0, 0) @[dec_tlu_ctl.scala 1754:46] + inst rvclkhdr_11 of rvclkhdr_65 @[lib.scala 404:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_11.io.en <= _T_373 @[lib.scala 407:17] + rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_374 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_373 : @[Reg.scala 28:19] + _T_374 <= mcgc_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mcgc_int <= _T_374 @[dec_tlu_ctl.scala 1754:18] + node _T_375 = bits(mcgc_int, 9, 9) @[dec_tlu_ctl.scala 1755:33] + node _T_376 = not(_T_375) @[dec_tlu_ctl.scala 1755:24] + node _T_377 = bits(mcgc_int, 8, 0) @[dec_tlu_ctl.scala 1755:46] + node mcgc = cat(_T_376, _T_377) @[Cat.scala 29:58] + node _T_378 = bits(mcgc, 9, 9) @[dec_tlu_ctl.scala 1756:46] + io.dec_tlu_picio_clk_override <= _T_378 @[dec_tlu_ctl.scala 1756:39] + node _T_379 = bits(mcgc, 8, 8) @[dec_tlu_ctl.scala 1757:45] + io.dec_tlu_misc_clk_override <= _T_379 @[dec_tlu_ctl.scala 1757:38] + node _T_380 = bits(mcgc, 7, 7) @[dec_tlu_ctl.scala 1758:45] + io.dec_tlu_dec_clk_override <= _T_380 @[dec_tlu_ctl.scala 1758:38] + node _T_381 = bits(mcgc, 5, 5) @[dec_tlu_ctl.scala 1759:45] + io.dec_tlu_ifu_clk_override <= _T_381 @[dec_tlu_ctl.scala 1759:38] + node _T_382 = bits(mcgc, 4, 4) @[dec_tlu_ctl.scala 1760:45] + io.dec_tlu_lsu_clk_override <= _T_382 @[dec_tlu_ctl.scala 1760:38] + node _T_383 = bits(mcgc, 3, 3) @[dec_tlu_ctl.scala 1761:45] + io.dec_tlu_bus_clk_override <= _T_383 @[dec_tlu_ctl.scala 1761:38] + node _T_384 = bits(mcgc, 2, 2) @[dec_tlu_ctl.scala 1762:45] + io.dec_tlu_pic_clk_override <= _T_384 @[dec_tlu_ctl.scala 1762:38] + node _T_385 = bits(mcgc, 1, 1) @[dec_tlu_ctl.scala 1763:45] + io.dec_tlu_dccm_clk_override <= _T_385 @[dec_tlu_ctl.scala 1763:38] + node _T_386 = bits(mcgc, 0, 0) @[dec_tlu_ctl.scala 1764:45] + io.dec_tlu_icm_clk_override <= _T_386 @[dec_tlu_ctl.scala 1764:38] + node _T_387 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1785:68] + node _T_388 = eq(_T_387, UInt<12>("h07f9")) @[dec_tlu_ctl.scala 1785:75] + node wr_mfdc_r = and(io.dec_csr_wen_r_mod, _T_388) @[dec_tlu_ctl.scala 1785:46] + node _T_389 = bits(wr_mfdc_r, 0, 0) @[dec_tlu_ctl.scala 1789:46] + inst rvclkhdr_12 of rvclkhdr_66 @[lib.scala 404:23] + rvclkhdr_12.clock <= clock + rvclkhdr_12.reset <= reset + rvclkhdr_12.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_12.io.en <= _T_389 @[lib.scala 407:17] + rvclkhdr_12.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_390 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_389 : @[Reg.scala 28:19] + _T_390 <= mfdc_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mfdc_int <= _T_390 @[dec_tlu_ctl.scala 1789:18] + node _T_391 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1795:52] + node _T_392 = not(_T_391) @[dec_tlu_ctl.scala 1795:32] + node _T_393 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1795:79] + node _T_394 = bits(io.dec_csr_wrdata_r, 11, 7) @[dec_tlu_ctl.scala 1795:103] + node _T_395 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1795:131] + node _T_396 = not(_T_395) @[dec_tlu_ctl.scala 1795:111] + node _T_397 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1795:155] + node _T_398 = cat(_T_396, _T_397) @[Cat.scala 29:58] + node _T_399 = cat(_T_392, _T_393) @[Cat.scala 29:58] + node _T_400 = cat(_T_399, _T_394) @[Cat.scala 29:58] + node _T_401 = cat(_T_400, _T_398) @[Cat.scala 29:58] + mfdc_ns <= _T_401 @[dec_tlu_ctl.scala 1795:25] + node _T_402 = bits(mfdc_int, 15, 13) @[dec_tlu_ctl.scala 1796:41] + node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1796:32] + node _T_404 = bits(mfdc_int, 12, 12) @[dec_tlu_ctl.scala 1796:66] + node _T_405 = bits(mfdc_int, 11, 7) @[dec_tlu_ctl.scala 1796:80] + node _T_406 = bits(mfdc_int, 6, 6) @[dec_tlu_ctl.scala 1796:97] + node _T_407 = not(_T_406) @[dec_tlu_ctl.scala 1796:88] + node _T_408 = bits(mfdc_int, 5, 0) @[dec_tlu_ctl.scala 1796:110] + node _T_409 = cat(_T_405, _T_407) @[Cat.scala 29:58] + node _T_410 = cat(_T_409, _T_408) @[Cat.scala 29:58] + node _T_411 = cat(_T_403, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_412 = cat(_T_411, _T_404) @[Cat.scala 29:58] + node _T_413 = cat(_T_412, _T_410) @[Cat.scala 29:58] + mfdc <= _T_413 @[dec_tlu_ctl.scala 1796:25] + node _T_414 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1806:53] + io.dec_tlu_dma_qos_prty <= _T_414 @[dec_tlu_ctl.scala 1806:46] + node _T_415 = bits(mfdc, 12, 12) @[dec_tlu_ctl.scala 1807:53] + io.dec_tlu_trace_disable <= _T_415 @[dec_tlu_ctl.scala 1807:46] + node _T_416 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1808:53] + io.dec_tlu_external_ldfwd_disable <= _T_416 @[dec_tlu_ctl.scala 1808:46] + node _T_417 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1809:53] + io.dec_tlu_core_ecc_disable <= _T_417 @[dec_tlu_ctl.scala 1809:46] + node _T_418 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1810:53] + io.dec_tlu_sideeffect_posted_disable <= _T_418 @[dec_tlu_ctl.scala 1810:46] + node _T_419 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1811:53] + io.dec_tlu_bpred_disable <= _T_419 @[dec_tlu_ctl.scala 1811:46] + node _T_420 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1812:53] + io.dec_tlu_wb_coalescing_disable <= _T_420 @[dec_tlu_ctl.scala 1812:46] + node _T_421 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1813:53] + io.dec_tlu_pipelining_disable <= _T_421 @[dec_tlu_ctl.scala 1813:46] + node _T_422 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1822:77] + node _T_423 = eq(_T_422, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1822:84] + node _T_424 = and(io.dec_csr_wen_r_mod, _T_423) @[dec_tlu_ctl.scala 1822:55] + node _T_425 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1822:96] + node _T_426 = and(_T_424, _T_425) @[dec_tlu_ctl.scala 1822:94] + node _T_427 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1822:120] + node _T_428 = and(_T_426, _T_427) @[dec_tlu_ctl.scala 1822:118] + io.dec_tlu_wr_pause_r <= _T_428 @[dec_tlu_ctl.scala 1822:31] + node _T_429 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1829:68] + node _T_430 = eq(_T_429, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1829:75] + node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_430) @[dec_tlu_ctl.scala 1829:46] + node _T_431 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1832:46] + node _T_432 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1832:71] + node _T_433 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1832:98] + node _T_434 = not(_T_433) @[dec_tlu_ctl.scala 1832:78] + node _T_435 = and(_T_432, _T_434) @[dec_tlu_ctl.scala 1832:76] + node _T_436 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1833:36] + node _T_437 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1833:61] + node _T_438 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1833:88] + node _T_439 = not(_T_438) @[dec_tlu_ctl.scala 1833:68] + node _T_440 = and(_T_437, _T_439) @[dec_tlu_ctl.scala 1833:66] + node _T_441 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1834:36] + node _T_442 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1834:61] + node _T_443 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1834:88] + node _T_444 = not(_T_443) @[dec_tlu_ctl.scala 1834:68] + node _T_445 = and(_T_442, _T_444) @[dec_tlu_ctl.scala 1834:66] + node _T_446 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1835:36] + node _T_447 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1835:61] + node _T_448 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1835:88] + node _T_449 = not(_T_448) @[dec_tlu_ctl.scala 1835:68] + node _T_450 = and(_T_447, _T_449) @[dec_tlu_ctl.scala 1835:66] + node _T_451 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1836:36] + node _T_452 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1836:61] + node _T_453 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1836:88] + node _T_454 = not(_T_453) @[dec_tlu_ctl.scala 1836:68] + node _T_455 = and(_T_452, _T_454) @[dec_tlu_ctl.scala 1836:66] + node _T_456 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1837:36] + node _T_457 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1837:61] + node _T_458 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1837:88] + node _T_459 = not(_T_458) @[dec_tlu_ctl.scala 1837:68] + node _T_460 = and(_T_457, _T_459) @[dec_tlu_ctl.scala 1837:66] + node _T_461 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1838:36] + node _T_462 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1838:61] + node _T_463 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1838:88] + node _T_464 = not(_T_463) @[dec_tlu_ctl.scala 1838:68] + node _T_465 = and(_T_462, _T_464) @[dec_tlu_ctl.scala 1838:66] + node _T_466 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1839:36] + node _T_467 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1839:61] + node _T_468 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1839:88] + node _T_469 = not(_T_468) @[dec_tlu_ctl.scala 1839:68] + node _T_470 = and(_T_467, _T_469) @[dec_tlu_ctl.scala 1839:66] + node _T_471 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1840:36] + node _T_472 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1840:61] + node _T_473 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1840:88] + node _T_474 = not(_T_473) @[dec_tlu_ctl.scala 1840:68] + node _T_475 = and(_T_472, _T_474) @[dec_tlu_ctl.scala 1840:66] + node _T_476 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1841:36] + node _T_477 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1841:61] + node _T_478 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1841:88] + node _T_479 = not(_T_478) @[dec_tlu_ctl.scala 1841:68] + node _T_480 = and(_T_477, _T_479) @[dec_tlu_ctl.scala 1841:66] + node _T_481 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1842:36] + node _T_482 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1842:61] + node _T_483 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1842:88] + node _T_484 = not(_T_483) @[dec_tlu_ctl.scala 1842:68] + node _T_485 = and(_T_482, _T_484) @[dec_tlu_ctl.scala 1842:66] + node _T_486 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1843:36] + node _T_487 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1843:61] + node _T_488 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1843:88] + node _T_489 = not(_T_488) @[dec_tlu_ctl.scala 1843:68] + node _T_490 = and(_T_487, _T_489) @[dec_tlu_ctl.scala 1843:65] + node _T_491 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1844:36] + node _T_492 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1844:61] + node _T_493 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1844:88] + node _T_494 = not(_T_493) @[dec_tlu_ctl.scala 1844:68] + node _T_495 = and(_T_492, _T_494) @[dec_tlu_ctl.scala 1844:65] + node _T_496 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1845:36] + node _T_497 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1845:61] + node _T_498 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1845:88] + node _T_499 = not(_T_498) @[dec_tlu_ctl.scala 1845:68] + node _T_500 = and(_T_497, _T_499) @[dec_tlu_ctl.scala 1845:65] + node _T_501 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1846:36] + node _T_502 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1846:61] + node _T_503 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1846:88] + node _T_504 = not(_T_503) @[dec_tlu_ctl.scala 1846:68] + node _T_505 = and(_T_502, _T_504) @[dec_tlu_ctl.scala 1846:65] + node _T_506 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1847:36] + node _T_507 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1847:61] + node _T_508 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1847:88] + node _T_509 = not(_T_508) @[dec_tlu_ctl.scala 1847:68] + node _T_510 = and(_T_507, _T_509) @[dec_tlu_ctl.scala 1847:65] + node _T_511 = cat(_T_506, _T_510) @[Cat.scala 29:58] + node _T_512 = cat(_T_501, _T_505) @[Cat.scala 29:58] + node _T_513 = cat(_T_512, _T_511) @[Cat.scala 29:58] + node _T_514 = cat(_T_496, _T_500) @[Cat.scala 29:58] + node _T_515 = cat(_T_491, _T_495) @[Cat.scala 29:58] + node _T_516 = cat(_T_515, _T_514) @[Cat.scala 29:58] + node _T_517 = cat(_T_516, _T_513) @[Cat.scala 29:58] + node _T_518 = cat(_T_486, _T_490) @[Cat.scala 29:58] + node _T_519 = cat(_T_481, _T_485) @[Cat.scala 29:58] + node _T_520 = cat(_T_519, _T_518) @[Cat.scala 29:58] + node _T_521 = cat(_T_476, _T_480) @[Cat.scala 29:58] + node _T_522 = cat(_T_471, _T_475) @[Cat.scala 29:58] + node _T_523 = cat(_T_522, _T_521) @[Cat.scala 29:58] + node _T_524 = cat(_T_523, _T_520) @[Cat.scala 29:58] + node _T_525 = cat(_T_524, _T_517) @[Cat.scala 29:58] + node _T_526 = cat(_T_466, _T_470) @[Cat.scala 29:58] + node _T_527 = cat(_T_461, _T_465) @[Cat.scala 29:58] + node _T_528 = cat(_T_527, _T_526) @[Cat.scala 29:58] + node _T_529 = cat(_T_456, _T_460) @[Cat.scala 29:58] + node _T_530 = cat(_T_451, _T_455) @[Cat.scala 29:58] + node _T_531 = cat(_T_530, _T_529) @[Cat.scala 29:58] + node _T_532 = cat(_T_531, _T_528) @[Cat.scala 29:58] + node _T_533 = cat(_T_446, _T_450) @[Cat.scala 29:58] + node _T_534 = cat(_T_441, _T_445) @[Cat.scala 29:58] + node _T_535 = cat(_T_534, _T_533) @[Cat.scala 29:58] + node _T_536 = cat(_T_436, _T_440) @[Cat.scala 29:58] + node _T_537 = cat(_T_431, _T_435) @[Cat.scala 29:58] + node _T_538 = cat(_T_537, _T_536) @[Cat.scala 29:58] + node _T_539 = cat(_T_538, _T_535) @[Cat.scala 29:58] + node _T_540 = cat(_T_539, _T_532) @[Cat.scala 29:58] + node mrac_in = cat(_T_540, _T_525) @[Cat.scala 29:58] + node _T_541 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1850:45] + inst rvclkhdr_13 of rvclkhdr_67 @[lib.scala 404:23] + rvclkhdr_13.clock <= clock + rvclkhdr_13.reset <= reset + rvclkhdr_13.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_13.io.en <= _T_541 @[lib.scala 407:17] + rvclkhdr_13.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg mrac : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_541 : @[Reg.scala 28:19] + mrac <= mrac_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.dec_tlu_mrac_ff <= mrac @[dec_tlu_ctl.scala 1852:28] + node _T_542 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1860:69] + node _T_543 = eq(_T_542, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1860:76] + node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_543) @[dec_tlu_ctl.scala 1860:47] + node _T_544 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1870:66] + node _T_545 = and(io.mdseac_locked_f, _T_544) @[dec_tlu_ctl.scala 1870:64] + node _T_546 = or(mdseac_en, _T_545) @[dec_tlu_ctl.scala 1870:42] + io.mdseac_locked_ns <= _T_546 @[dec_tlu_ctl.scala 1870:29] + node _T_547 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1872:56] + node _T_548 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1872:93] + node _T_549 = and(_T_547, _T_548) @[dec_tlu_ctl.scala 1872:91] + node _T_550 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1872:118] + node _T_551 = and(_T_549, _T_550) @[dec_tlu_ctl.scala 1872:116] + mdseac_en <= _T_551 @[dec_tlu_ctl.scala 1872:19] + node _T_552 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1874:71] + inst rvclkhdr_14 of rvclkhdr_68 @[lib.scala 404:23] + rvclkhdr_14.clock <= clock + rvclkhdr_14.reset <= reset + rvclkhdr_14.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_14.io.en <= _T_552 @[lib.scala 407:17] + rvclkhdr_14.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg mdseac : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_552 : @[Reg.scala 28:19] + mdseac <= io.lsu_imprecise_error_addr_any @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_553 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1883:69] + node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_553) @[dec_tlu_ctl.scala 1883:46] + node _T_554 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1887:58] + node _T_555 = and(wr_mpmc_r, _T_554) @[dec_tlu_ctl.scala 1887:37] + node _T_556 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1887:64] + node _T_557 = and(_T_555, _T_556) @[dec_tlu_ctl.scala 1887:62] + node _T_558 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1887:96] + node _T_559 = and(_T_557, _T_558) @[dec_tlu_ctl.scala 1887:94] + io.fw_halt_req <= _T_559 @[dec_tlu_ctl.scala 1887:24] + wire fw_halted_ns : UInt<1> + fw_halted_ns <= UInt<1>("h00") + node _T_560 = or(io.fw_halt_req, perfmux_flop.io.fw_halted) @[dec_tlu_ctl.scala 1890:41] + node _T_561 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1890:72] + node _T_562 = and(_T_560, _T_561) @[dec_tlu_ctl.scala 1890:70] + fw_halted_ns <= _T_562 @[dec_tlu_ctl.scala 1890:22] + node _T_563 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1891:36] + node _T_564 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1891:64] + node _T_565 = not(_T_564) @[dec_tlu_ctl.scala 1891:44] + node _T_566 = not(mpmc) @[dec_tlu_ctl.scala 1891:69] + node _T_567 = mux(_T_563, _T_565, _T_566) @[dec_tlu_ctl.scala 1891:25] + mpmc_b_ns <= _T_567 @[dec_tlu_ctl.scala 1891:19] + reg _T_568 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1893:51] + _T_568 <= mpmc_b_ns @[dec_tlu_ctl.scala 1893:51] + mpmc_b <= _T_568 @[dec_tlu_ctl.scala 1893:16] + node _T_569 = not(mpmc_b) @[dec_tlu_ctl.scala 1896:17] + mpmc <= _T_569 @[dec_tlu_ctl.scala 1896:14] + node _T_570 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1905:47] + node _T_571 = gt(_T_570, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1905:55] + node _T_572 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1905:99] + node csr_sat = mux(_T_571, UInt<5>("h01a"), _T_572) @[dec_tlu_ctl.scala 1905:26] + node _T_573 = eq(io.dec_csr_wraddr_r, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1907:71] + node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_573) @[dec_tlu_ctl.scala 1907:48] + node _T_574 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1908:29] + node _T_575 = cat(UInt<26>("h00"), io.ic_perr_r) @[Cat.scala 29:58] + node _T_576 = add(_T_574, _T_575) @[dec_tlu_ctl.scala 1908:36] + node _T_577 = tail(_T_576, 1) @[dec_tlu_ctl.scala 1908:36] + micect_inc <= _T_577 @[dec_tlu_ctl.scala 1908:20] + node _T_578 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1909:42] + node _T_579 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1909:82] + node _T_580 = cat(csr_sat, _T_579) @[Cat.scala 29:58] + node _T_581 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1909:102] + node _T_582 = cat(_T_581, micect_inc) @[Cat.scala 29:58] + node micect_ns = mux(_T_578, _T_580, _T_582) @[dec_tlu_ctl.scala 1909:29] + node _T_583 = or(wr_micect_r, io.ic_perr_r) @[dec_tlu_ctl.scala 1911:49] + node _T_584 = bits(_T_583, 0, 0) @[dec_tlu_ctl.scala 1911:65] + inst rvclkhdr_15 of rvclkhdr_69 @[lib.scala 404:23] + rvclkhdr_15.clock <= clock + rvclkhdr_15.reset <= reset + rvclkhdr_15.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_15.io.en <= _T_584 @[lib.scala 407:17] + rvclkhdr_15.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_585 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_584 : @[Reg.scala 28:19] + _T_585 <= micect_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + micect <= _T_585 @[dec_tlu_ctl.scala 1911:16] + node _T_586 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1913:55] + node _T_587 = dshl(UInt<32>("h0ffffffff"), _T_586) @[dec_tlu_ctl.scala 1913:46] + node _T_588 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1913:86] + node _T_589 = cat(UInt<5>("h00"), _T_588) @[Cat.scala 29:58] + node _T_590 = and(_T_587, _T_589) @[dec_tlu_ctl.scala 1913:64] + node _T_591 = orr(_T_590) @[dec_tlu_ctl.scala 1913:95] + mice_ce_req <= _T_591 @[dec_tlu_ctl.scala 1913:21] + node _T_592 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1922:76] + node _T_593 = eq(_T_592, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1922:83] + node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_593) @[dec_tlu_ctl.scala 1922:54] + node _T_594 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1923:33] + node _T_595 = or(io.iccm_sbecc_r, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1923:74] + node _T_596 = cat(UInt<26>("h00"), _T_595) @[Cat.scala 29:58] + node _T_597 = add(_T_594, _T_596) @[dec_tlu_ctl.scala 1923:40] + node _T_598 = tail(_T_597, 1) @[dec_tlu_ctl.scala 1923:40] + miccmect_inc <= _T_598 @[dec_tlu_ctl.scala 1923:22] + node _T_599 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1924:52] + node _T_600 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1924:92] + node _T_601 = cat(csr_sat, _T_600) @[Cat.scala 29:58] + node _T_602 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1924:114] + node _T_603 = cat(_T_602, miccmect_inc) @[Cat.scala 29:58] + node miccmect_ns = mux(_T_599, _T_601, _T_603) @[dec_tlu_ctl.scala 1924:37] + node _T_604 = or(wr_miccmect_r, io.iccm_sbecc_r) @[dec_tlu_ctl.scala 1926:55] + node _T_605 = or(_T_604, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1926:73] + node _T_606 = bits(_T_605, 0, 0) @[dec_tlu_ctl.scala 1926:97] + inst rvclkhdr_16 of rvclkhdr_70 @[lib.scala 404:23] + rvclkhdr_16.clock <= clock + rvclkhdr_16.reset <= reset + rvclkhdr_16.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_16.io.en <= _T_606 @[lib.scala 407:17] + rvclkhdr_16.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_607 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_606 : @[Reg.scala 28:19] + _T_607 <= miccmect_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + miccmect <= _T_607 @[dec_tlu_ctl.scala 1926:18] + node _T_608 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1928:59] + node _T_609 = dshl(UInt<32>("h0ffffffff"), _T_608) @[dec_tlu_ctl.scala 1928:48] + node _T_610 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1928:92] + node _T_611 = cat(UInt<5>("h00"), _T_610) @[Cat.scala 29:58] + node _T_612 = and(_T_609, _T_611) @[dec_tlu_ctl.scala 1928:68] + node _T_613 = orr(_T_612) @[dec_tlu_ctl.scala 1928:101] + miccme_ce_req <= _T_613 @[dec_tlu_ctl.scala 1928:23] + node _T_614 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1937:76] + node _T_615 = eq(_T_614, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1937:83] + node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_615) @[dec_tlu_ctl.scala 1937:54] + node _T_616 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1938:33] + node _T_617 = cat(UInt<26>("h00"), perfmux_flop.io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] + node _T_618 = add(_T_616, _T_617) @[dec_tlu_ctl.scala 1938:40] + node _T_619 = tail(_T_618, 1) @[dec_tlu_ctl.scala 1938:40] + mdccmect_inc <= _T_619 @[dec_tlu_ctl.scala 1938:22] + node _T_620 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1939:52] + node _T_621 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1939:92] + node _T_622 = cat(csr_sat, _T_621) @[Cat.scala 29:58] + node _T_623 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1939:114] + node _T_624 = cat(_T_623, mdccmect_inc) @[Cat.scala 29:58] + node mdccmect_ns = mux(_T_620, _T_622, _T_624) @[dec_tlu_ctl.scala 1939:37] + node _T_625 = or(wr_mdccmect_r, perfmux_flop.io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1941:56] + node _T_626 = bits(_T_625, 0, 0) @[dec_tlu_ctl.scala 1941:103] + inst rvclkhdr_17 of rvclkhdr_71 @[lib.scala 404:23] + rvclkhdr_17.clock <= clock + rvclkhdr_17.reset <= reset + rvclkhdr_17.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_17.io.en <= _T_626 @[lib.scala 407:17] + rvclkhdr_17.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_627 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_626 : @[Reg.scala 28:19] + _T_627 <= mdccmect_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mdccmect <= _T_627 @[dec_tlu_ctl.scala 1941:18] + node _T_628 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1942:59] + node _T_629 = dshl(UInt<32>("h0ffffffff"), _T_628) @[dec_tlu_ctl.scala 1942:48] + node _T_630 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1942:92] + node _T_631 = cat(UInt<5>("h00"), _T_630) @[Cat.scala 29:58] + node _T_632 = and(_T_629, _T_631) @[dec_tlu_ctl.scala 1942:68] + node _T_633 = orr(_T_632) @[dec_tlu_ctl.scala 1942:101] + mdccme_ce_req <= _T_633 @[dec_tlu_ctl.scala 1942:23] + node _T_634 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1952:69] + node _T_635 = eq(_T_634, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1952:76] + node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_635) @[dec_tlu_ctl.scala 1952:47] + node _T_636 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1954:39] + node _T_637 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1954:66] + node mfdht_ns = mux(_T_636, _T_637, mfdht) @[dec_tlu_ctl.scala 1954:27] + node _T_638 = bits(wr_mfdht_r, 0, 0) @[lib.scala 8:44] + reg _T_639 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_638 : @[Reg.scala 28:19] + _T_639 <= mfdht_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mfdht <= _T_639 @[dec_tlu_ctl.scala 1956:15] + node _T_640 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1965:69] + node _T_641 = eq(_T_640, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1965:76] + node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_641) @[dec_tlu_ctl.scala 1965:47] + node _T_642 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1967:39] + node _T_643 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1967:67] + node _T_644 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1968:42] + node _T_645 = and(io.dbg_tlu_halted, _T_644) @[dec_tlu_ctl.scala 1968:40] + node _T_646 = bits(_T_645, 0, 0) @[dec_tlu_ctl.scala 1968:64] + node _T_647 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1968:77] + node _T_648 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1968:97] + node _T_649 = cat(_T_647, _T_648) @[Cat.scala 29:58] + node _T_650 = mux(_T_646, _T_649, mfdhs) @[dec_tlu_ctl.scala 1968:20] + node mfdhs_ns = mux(_T_642, _T_643, _T_650) @[dec_tlu_ctl.scala 1967:27] + node _T_651 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1970:76] + node _T_652 = bits(_T_651, 0, 0) @[dec_tlu_ctl.scala 1970:97] + reg _T_653 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_652 : @[Reg.scala 28:19] + _T_653 <= mfdhs_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mfdhs <= _T_653 @[dec_tlu_ctl.scala 1970:15] + node _T_654 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1972:54] + node _T_655 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1972:81] + node _T_656 = tail(_T_655, 1) @[dec_tlu_ctl.scala 1972:81] + node _T_657 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1973:41] + node _T_658 = mux(_T_657, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1973:20] + node force_halt_ctr = mux(_T_654, _T_656, _T_658) @[dec_tlu_ctl.scala 1972:33] + node _T_659 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1975:56] + inst rvclkhdr_18 of rvclkhdr_72 @[lib.scala 404:23] + rvclkhdr_18.clock <= clock + rvclkhdr_18.reset <= reset + rvclkhdr_18.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_18.io.en <= _T_659 @[lib.scala 407:17] + rvclkhdr_18.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_660 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_659 : @[Reg.scala 28:19] + _T_660 <= force_halt_ctr @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + force_halt_ctr_f <= _T_660 @[dec_tlu_ctl.scala 1975:26] + node _T_661 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1977:31] + node _T_662 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1977:86] + node _T_663 = dshl(UInt<32>("h0ffffffff"), _T_662) @[dec_tlu_ctl.scala 1977:78] + node _T_664 = and(force_halt_ctr_f, _T_663) @[dec_tlu_ctl.scala 1977:55] + node _T_665 = orr(_T_664) @[dec_tlu_ctl.scala 1977:94] + node _T_666 = and(_T_661, _T_665) @[dec_tlu_ctl.scala 1977:35] + io.force_halt <= _T_666 @[dec_tlu_ctl.scala 1977:23] + node _T_667 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1985:69] + node _T_668 = eq(_T_667, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1985:76] + node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_668) @[dec_tlu_ctl.scala 1985:47] + node _T_669 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1987:47] + node _T_670 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1987:66] + inst rvclkhdr_19 of rvclkhdr_73 @[lib.scala 404:23] + rvclkhdr_19.clock <= clock + rvclkhdr_19.reset <= reset + rvclkhdr_19.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_19.io.en <= _T_670 @[lib.scala 407:17] + rvclkhdr_19.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg meivt : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_670 : @[Reg.scala 28:19] + meivt <= _T_669 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_671 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1999:56] + inst rvclkhdr_20 of rvclkhdr_74 @[lib.scala 404:23] + rvclkhdr_20.clock <= clock + rvclkhdr_20.reset <= reset + rvclkhdr_20.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_20.io.en <= _T_671 @[lib.scala 407:17] + rvclkhdr_20.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg meihap : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_671 : @[Reg.scala 28:19] + meihap <= io.pic_claimid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_672 = cat(meivt, meihap) @[Cat.scala 29:58] + io.dec_tlu_meihap <= _T_672 @[dec_tlu_ctl.scala 2000:27] + node _T_673 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2009:72] + node _T_674 = eq(_T_673, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 2009:79] + node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_674) @[dec_tlu_ctl.scala 2009:50] + node _T_675 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 2010:45] + node _T_676 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2010:72] + node meicurpl_ns = mux(_T_675, _T_676, meicurpl) @[dec_tlu_ctl.scala 2010:30] + reg _T_677 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2012:53] + _T_677 <= meicurpl_ns @[dec_tlu_ctl.scala 2012:53] + meicurpl <= _T_677 @[dec_tlu_ctl.scala 2012:18] + io.dec_tlu_meicurpl <= meicurpl @[dec_tlu_ctl.scala 2014:29] + node _T_678 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2024:73] + node _T_679 = eq(_T_678, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 2024:80] + node _T_680 = and(io.dec_csr_wen_r_mod, _T_679) @[dec_tlu_ctl.scala 2024:51] + node wr_meicidpl_r = or(_T_680, io.take_ext_int_start) @[dec_tlu_ctl.scala 2024:95] + node _T_681 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 2026:44] + node _T_682 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 2027:35] + node _T_683 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2027:62] + node _T_684 = mux(_T_682, _T_683, perfmux_flop.io.meicidpl) @[dec_tlu_ctl.scala 2027:20] + node meicidpl_ns = mux(_T_681, io.pic_pl, _T_684) @[dec_tlu_ctl.scala 2026:30] + node _T_685 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2036:69] + node _T_686 = eq(_T_685, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 2036:76] + node _T_687 = and(io.dec_csr_wen_r_mod, _T_686) @[dec_tlu_ctl.scala 2036:47] + node _T_688 = or(_T_687, io.take_ext_int_start) @[dec_tlu_ctl.scala 2036:90] + wr_meicpct_r <= _T_688 @[dec_tlu_ctl.scala 2036:22] + node _T_689 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2045:69] + node _T_690 = eq(_T_689, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 2045:76] + node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_690) @[dec_tlu_ctl.scala 2045:47] + node _T_691 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 2046:39] + node _T_692 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2046:66] + node meipt_ns = mux(_T_691, _T_692, meipt) @[dec_tlu_ctl.scala 2046:27] + reg _T_693 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2048:50] + _T_693 <= meipt_ns @[dec_tlu_ctl.scala 2048:50] + meipt <= _T_693 @[dec_tlu_ctl.scala 2048:15] + io.dec_tlu_meipt <= meipt @[dec_tlu_ctl.scala 2050:26] + node _T_694 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2076:96] + node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_694) @[dec_tlu_ctl.scala 2076:73] + node _T_695 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2079:47] + node _T_696 = and(io.dcsr_single_step_done_f, _T_695) @[dec_tlu_ctl.scala 2079:45] + node _T_697 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2079:79] + node _T_698 = and(_T_696, _T_697) @[dec_tlu_ctl.scala 2079:77] + node _T_699 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2079:114] + node _T_700 = and(_T_698, _T_699) @[dec_tlu_ctl.scala 2079:112] + node _T_701 = bits(_T_700, 0, 0) @[dec_tlu_ctl.scala 2079:134] + node _T_702 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2080:38] + node _T_703 = and(io.debug_halt_req, _T_702) @[dec_tlu_ctl.scala 2080:36] + node _T_704 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2080:70] + node _T_705 = and(_T_703, _T_704) @[dec_tlu_ctl.scala 2080:68] + node _T_706 = bits(_T_705, 0, 0) @[dec_tlu_ctl.scala 2080:104] + node _T_707 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2081:49] + node _T_708 = and(io.ebreak_to_debug_mode_r_d1, _T_707) @[dec_tlu_ctl.scala 2081:47] + node _T_709 = bits(_T_708, 0, 0) @[dec_tlu_ctl.scala 2081:83] + node _T_710 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2082:51] + node _T_711 = mux(_T_701, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_712 = mux(_T_706, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_713 = mux(_T_709, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_714 = mux(_T_710, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_715 = or(_T_711, _T_712) @[Mux.scala 27:72] + node _T_716 = or(_T_715, _T_713) @[Mux.scala 27:72] + node _T_717 = or(_T_716, _T_714) @[Mux.scala 27:72] + wire dcsr_cause : UInt<3> @[Mux.scala 27:72] + dcsr_cause <= _T_717 @[Mux.scala 27:72] + node _T_718 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2084:53] + node _T_719 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2084:98] + node _T_720 = eq(_T_719, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2084:105] + node wr_dcsr_r = and(_T_718, _T_720) @[dec_tlu_ctl.scala 2084:76] + node _T_721 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2090:76] + node _T_722 = eq(_T_721, UInt<3>("h03")) @[dec_tlu_ctl.scala 2090:82] + node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_722) @[dec_tlu_ctl.scala 2090:66] + node _T_723 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2091:66] + node _T_724 = or(_T_723, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2091:85] + node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_724) @[dec_tlu_ctl.scala 2091:63] + node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 2093:55] + node _T_725 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2094:51] + node _T_726 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2094:71] + node _T_727 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2094:98] + node _T_728 = cat(_T_727, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_729 = cat(_T_726, dcsr_cause) @[Cat.scala 29:58] + node _T_730 = cat(_T_729, _T_728) @[Cat.scala 29:58] + node _T_731 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2095:31] + node _T_732 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2095:62] + node _T_733 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2095:97] + node _T_734 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2095:123] + node _T_735 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2095:167] + node _T_736 = or(nmi_in_debug_mode, _T_735) @[dec_tlu_ctl.scala 2095:158] + node _T_737 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2095:191] + node _T_738 = cat(_T_737, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_739 = cat(UInt<2>("h00"), _T_736) @[Cat.scala 29:58] + node _T_740 = cat(_T_739, _T_738) @[Cat.scala 29:58] + node _T_741 = cat(UInt<1>("h00"), _T_734) @[Cat.scala 29:58] + node _T_742 = cat(_T_732, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_743 = cat(_T_742, _T_733) @[Cat.scala 29:58] + node _T_744 = cat(_T_743, _T_741) @[Cat.scala 29:58] + node _T_745 = cat(_T_744, _T_740) @[Cat.scala 29:58] + node _T_746 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2095:224] + node _T_747 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2095:258] + node _T_748 = cat(_T_747, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_749 = cat(_T_746, nmi_in_debug_mode) @[Cat.scala 29:58] + node _T_750 = cat(_T_749, _T_748) @[Cat.scala 29:58] + node _T_751 = mux(_T_731, _T_745, _T_750) @[dec_tlu_ctl.scala 2095:20] + node dcsr_ns = mux(_T_725, _T_730, _T_751) @[dec_tlu_ctl.scala 2094:26] + node _T_752 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2098:61] + node _T_753 = or(_T_752, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2098:73] + node _T_754 = or(_T_753, io.take_nmi) @[dec_tlu_ctl.scala 2098:101] + node _T_755 = bits(_T_754, 0, 0) @[dec_tlu_ctl.scala 2098:116] + inst rvclkhdr_21 of rvclkhdr_75 @[lib.scala 404:23] + rvclkhdr_21.clock <= clock + rvclkhdr_21.reset <= reset + rvclkhdr_21.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_21.io.en <= _T_755 @[lib.scala 407:17] + rvclkhdr_21.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_756 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_755 : @[Reg.scala 28:19] + _T_756 <= dcsr_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.dcsr <= _T_756 @[dec_tlu_ctl.scala 2098:17] + node _T_757 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2106:52] + node _T_758 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2106:97] + node _T_759 = eq(_T_758, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2106:104] + node wr_dpc_r = and(_T_757, _T_759) @[dec_tlu_ctl.scala 2106:75] + node _T_760 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2107:51] + node _T_761 = and(io.dbg_tlu_halted, _T_760) @[dec_tlu_ctl.scala 2107:49] + node _T_762 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2107:74] + node dpc_capture_npc = and(_T_761, _T_762) @[dec_tlu_ctl.scala 2107:72] + node _T_763 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2111:18] + node _T_764 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2111:36] + node _T_765 = and(_T_763, _T_764) @[dec_tlu_ctl.scala 2111:34] + node _T_766 = and(_T_765, wr_dpc_r) @[dec_tlu_ctl.scala 2111:53] + node _T_767 = bits(_T_766, 0, 0) @[dec_tlu_ctl.scala 2111:65] + node _T_768 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2111:94] + node _T_769 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2112:34] + node _T_770 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2113:18] + node _T_771 = and(_T_770, dpc_capture_npc) @[dec_tlu_ctl.scala 2113:34] + node _T_772 = bits(_T_771, 0, 0) @[dec_tlu_ctl.scala 2113:53] + node _T_773 = mux(_T_767, _T_768, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_774 = mux(_T_769, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_775 = mux(_T_772, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_776 = or(_T_773, _T_774) @[Mux.scala 27:72] + node _T_777 = or(_T_776, _T_775) @[Mux.scala 27:72] + wire dpc_ns : UInt<31> @[Mux.scala 27:72] + dpc_ns <= _T_777 @[Mux.scala 27:72] + node _T_778 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2115:43] + node _T_779 = or(_T_778, dpc_capture_npc) @[dec_tlu_ctl.scala 2115:60] + node _T_780 = bits(_T_779, 0, 0) @[dec_tlu_ctl.scala 2115:79] + inst rvclkhdr_22 of rvclkhdr_76 @[lib.scala 404:23] + rvclkhdr_22.clock <= clock + rvclkhdr_22.reset <= reset + rvclkhdr_22.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_22.io.en <= _T_780 @[lib.scala 407:17] + rvclkhdr_22.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_781 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_780 : @[Reg.scala 28:19] + _T_781 <= dpc_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.dpc <= _T_781 @[dec_tlu_ctl.scala 2115:16] + node _T_782 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2129:50] + node _T_783 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2129:75] + node _T_784 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2129:103] + node _T_785 = cat(_T_782, _T_783) @[Cat.scala 29:58] + node dicawics_ns = cat(_T_785, _T_784) @[Cat.scala 29:58] + node _T_786 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2130:57] + node _T_787 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2130:102] + node _T_788 = eq(_T_787, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2130:109] + node wr_dicawics_r = and(_T_786, _T_788) @[dec_tlu_ctl.scala 2130:80] + node _T_789 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2132:57] + inst rvclkhdr_23 of rvclkhdr_77 @[lib.scala 404:23] + rvclkhdr_23.clock <= clock + rvclkhdr_23.reset <= reset + rvclkhdr_23.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_23.io.en <= _T_789 @[lib.scala 407:17] + rvclkhdr_23.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg dicawics : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_789 : @[Reg.scala 28:19] + dicawics <= dicawics_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_790 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2148:55] + node _T_791 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2148:100] + node _T_792 = eq(_T_791, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2148:107] + node wr_dicad0_r = and(_T_790, _T_792) @[dec_tlu_ctl.scala 2148:78] + node _T_793 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2149:41] + node _T_794 = bits(io.ifu_ic_debug_rd_data, 31, 0) @[dec_tlu_ctl.scala 2149:93] + node dicad0_ns = mux(_T_793, io.dec_csr_wrdata_r, _T_794) @[dec_tlu_ctl.scala 2149:28] + node _T_795 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2151:53] + node _T_796 = bits(_T_795, 0, 0) @[dec_tlu_ctl.scala 2151:86] + inst rvclkhdr_24 of rvclkhdr_78 @[lib.scala 404:23] + rvclkhdr_24.clock <= clock + rvclkhdr_24.reset <= reset + rvclkhdr_24.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_24.io.en <= _T_796 @[lib.scala 407:17] + rvclkhdr_24.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg dicad0 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_796 : @[Reg.scala 28:19] + dicad0 <= dicad0_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_797 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2161:56] + node _T_798 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2161:101] + node _T_799 = eq(_T_798, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2161:108] + node wr_dicad0h_r = and(_T_797, _T_799) @[dec_tlu_ctl.scala 2161:79] + node _T_800 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2163:43] + node _T_801 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2163:95] + node dicad0h_ns = mux(_T_800, io.dec_csr_wrdata_r, _T_801) @[dec_tlu_ctl.scala 2163:29] + node _T_802 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2165:55] + node _T_803 = bits(_T_802, 0, 0) @[dec_tlu_ctl.scala 2165:88] + inst rvclkhdr_25 of rvclkhdr_79 @[lib.scala 404:23] + rvclkhdr_25.clock <= clock + rvclkhdr_25.reset <= reset + rvclkhdr_25.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_25.io.en <= _T_803 @[lib.scala 407:17] + rvclkhdr_25.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg dicad0h : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_803 : @[Reg.scala 28:19] + dicad0h <= dicad0h_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wire _T_804 : UInt<7> + _T_804 <= UInt<1>("h00") + node _T_805 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2173:63] + node _T_806 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2173:108] + node _T_807 = eq(_T_806, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2173:115] + node _T_808 = and(_T_805, _T_807) @[dec_tlu_ctl.scala 2173:86] + node _T_809 = bits(_T_808, 0, 0) @[dec_tlu_ctl.scala 2175:49] + node _T_810 = bits(io.dec_csr_wrdata_r, 6, 0) @[dec_tlu_ctl.scala 2175:76] + node _T_811 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2175:106] + node _T_812 = mux(_T_809, _T_810, _T_811) @[dec_tlu_ctl.scala 2175:36] + node _T_813 = or(_T_808, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2177:61] + node _T_814 = bits(_T_813, 0, 0) @[dec_tlu_ctl.scala 2177:94] + inst rvclkhdr_26 of rvclkhdr_80 @[lib.scala 404:23] + rvclkhdr_26.clock <= clock + rvclkhdr_26.reset <= reset + rvclkhdr_26.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_26.io.en <= _T_814 @[lib.scala 407:17] + rvclkhdr_26.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_815 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_814 : @[Reg.scala 28:19] + _T_815 <= _T_812 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_804 <= _T_815 @[dec_tlu_ctl.scala 2177:28] + node _T_816 = cat(UInt<25>("h00"), _T_804) @[Cat.scala 29:58] + dicad1 <= _T_816 @[dec_tlu_ctl.scala 2178:24] + node _T_817 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2200:76] + node _T_818 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2200:90] + node _T_819 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2200:104] + node _T_820 = cat(_T_817, _T_818) @[Cat.scala 29:58] + node _T_821 = cat(_T_820, _T_819) @[Cat.scala 29:58] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_821 @[dec_tlu_ctl.scala 2200:63] + io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2203:48] + node _T_822 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2205:59] + node _T_823 = and(_T_822, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2205:82] + node _T_824 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2205:105] + node _T_825 = and(_T_823, _T_824) @[dec_tlu_ctl.scala 2205:103] + node _T_826 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2205:149] + node _T_827 = eq(_T_826, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2205:156] + node icache_rd_valid = and(_T_825, _T_827) @[dec_tlu_ctl.scala 2205:127] + node _T_828 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2206:59] + node _T_829 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2206:104] + node _T_830 = eq(_T_829, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2206:111] + node icache_wr_valid = and(_T_828, _T_830) @[dec_tlu_ctl.scala 2206:82] + io.dec_tlu_ic_diag_pkt.icache_rd_valid <= perfmux_flop.io.icache_rd_valid_f @[dec_tlu_ctl.scala 2211:48] + io.dec_tlu_ic_diag_pkt.icache_wr_valid <= perfmux_flop.io.icache_wr_valid_f @[dec_tlu_ctl.scala 2212:48] + node _T_831 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2220:69] + node _T_832 = eq(_T_831, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2220:76] + node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_832) @[dec_tlu_ctl.scala 2220:47] + node _T_833 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2221:39] + node _T_834 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2221:66] + node mtsel_ns = mux(_T_833, _T_834, mtsel) @[dec_tlu_ctl.scala 2221:27] + reg _T_835 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2223:50] + _T_835 <= mtsel_ns @[dec_tlu_ctl.scala 2223:50] + mtsel <= _T_835 @[dec_tlu_ctl.scala 2223:15] + node _T_836 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2258:45] + node _T_837 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2258:71] + node _T_838 = not(_T_837) @[dec_tlu_ctl.scala 2258:51] + node tdata_load = and(_T_836, _T_838) @[dec_tlu_ctl.scala 2258:49] + node _T_839 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2260:47] + node _T_840 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2260:73] + node _T_841 = not(_T_840) @[dec_tlu_ctl.scala 2260:53] + node tdata_opcode = and(_T_839, _T_841) @[dec_tlu_ctl.scala 2260:51] + node _T_842 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2262:48] + node _T_843 = and(_T_842, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2262:53] + node _T_844 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2262:97] + node tdata_action = and(_T_843, _T_844) @[dec_tlu_ctl.scala 2262:76] + node _T_845 = bits(mtsel, 0, 0) @[dec_tlu_ctl.scala 2265:36] + node _T_846 = bits(mtsel, 1, 1) @[dec_tlu_ctl.scala 2266:26] + node _T_847 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2266:51] + node _T_848 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2266:75] + node _T_849 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2266:113] + node _T_850 = not(_T_849) @[dec_tlu_ctl.scala 2266:93] + node _T_851 = and(_T_848, _T_850) @[dec_tlu_ctl.scala 2266:91] + node _T_852 = not(_T_851) @[dec_tlu_ctl.scala 2266:58] + node _T_853 = and(_T_847, _T_852) @[dec_tlu_ctl.scala 2266:56] + node _T_854 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2267:44] + node _T_855 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2267:68] + node _T_856 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2267:106] + node _T_857 = not(_T_856) @[dec_tlu_ctl.scala 2267:86] + node _T_858 = and(_T_855, _T_857) @[dec_tlu_ctl.scala 2267:84] + node _T_859 = not(_T_858) @[dec_tlu_ctl.scala 2267:51] + node _T_860 = and(_T_854, _T_859) @[dec_tlu_ctl.scala 2267:49] + node _T_861 = mux(_T_846, _T_853, _T_860) @[dec_tlu_ctl.scala 2266:20] + node tdata_chain = mux(_T_845, UInt<1>("h00"), _T_861) @[dec_tlu_ctl.scala 2265:30] + node _T_862 = bits(mtsel, 1, 1) @[dec_tlu_ctl.scala 2270:41] + node _T_863 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2270:65] + node _T_864 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2270:89] + node _T_865 = not(_T_864) @[dec_tlu_ctl.scala 2270:73] + node _T_866 = bits(io.mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 2270:122] + node _T_867 = and(_T_865, _T_866) @[dec_tlu_ctl.scala 2270:105] + node _T_868 = and(_T_863, _T_867) @[dec_tlu_ctl.scala 2270:70] + node _T_869 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2271:36] + node _T_870 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2271:60] + node _T_871 = not(_T_870) @[dec_tlu_ctl.scala 2271:44] + node _T_872 = bits(io.mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 2271:93] + node _T_873 = and(_T_871, _T_872) @[dec_tlu_ctl.scala 2271:76] + node _T_874 = and(_T_869, _T_873) @[dec_tlu_ctl.scala 2271:41] + node tdata_kill_write = mux(_T_862, _T_868, _T_874) @[dec_tlu_ctl.scala 2270:35] + node _T_875 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2273:54] + node _T_876 = and(_T_875, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2273:59] + node _T_877 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2273:101] + node _T_878 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2273:157] + node _T_879 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2273:197] + node _T_880 = cat(_T_879, tdata_load) @[Cat.scala 29:58] + node _T_881 = cat(_T_878, tdata_opcode) @[Cat.scala 29:58] + node _T_882 = cat(_T_881, _T_880) @[Cat.scala 29:58] + node _T_883 = cat(tdata_action, tdata_chain) @[Cat.scala 29:58] + node _T_884 = cat(_T_876, _T_877) @[Cat.scala 29:58] + node _T_885 = cat(_T_884, _T_883) @[Cat.scala 29:58] + node tdata_wrdata_r = cat(_T_885, _T_882) @[Cat.scala 29:58] + node _T_886 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2276:120] + node _T_887 = eq(_T_886, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2276:127] + node _T_888 = and(io.dec_csr_wen_r_mod, _T_887) @[dec_tlu_ctl.scala 2276:98] + node _T_889 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2276:149] + node _T_890 = and(_T_888, _T_889) @[dec_tlu_ctl.scala 2276:140] + node _T_891 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2276:182] + node _T_892 = eq(_T_891, UInt<1>("h00")) @[dec_tlu_ctl.scala 2276:166] + node _T_893 = or(_T_892, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2276:198] + node _T_894 = and(_T_890, _T_893) @[dec_tlu_ctl.scala 2276:163] + node _T_895 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2276:269] + node _T_896 = eq(_T_895, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2276:276] + node _T_897 = and(io.dec_csr_wen_r_mod, _T_896) @[dec_tlu_ctl.scala 2276:247] + node _T_898 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2276:298] + node _T_899 = and(_T_897, _T_898) @[dec_tlu_ctl.scala 2276:289] + node _T_900 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2276:331] + node _T_901 = eq(_T_900, UInt<1>("h00")) @[dec_tlu_ctl.scala 2276:315] + node _T_902 = or(_T_901, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2276:347] + node _T_903 = and(_T_899, _T_902) @[dec_tlu_ctl.scala 2276:312] + node _T_904 = eq(tdata_kill_write, UInt<1>("h00")) @[dec_tlu_ctl.scala 2276:373] + node _T_905 = and(_T_903, _T_904) @[dec_tlu_ctl.scala 2276:371] + node _T_906 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2276:120] + node _T_907 = eq(_T_906, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2276:127] + node _T_908 = and(io.dec_csr_wen_r_mod, _T_907) @[dec_tlu_ctl.scala 2276:98] + node _T_909 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:149] + node _T_910 = and(_T_908, _T_909) @[dec_tlu_ctl.scala 2276:140] + node _T_911 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2276:182] + node _T_912 = eq(_T_911, UInt<1>("h00")) @[dec_tlu_ctl.scala 2276:166] + node _T_913 = or(_T_912, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2276:198] + node _T_914 = and(_T_910, _T_913) @[dec_tlu_ctl.scala 2276:163] + node _T_915 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2276:269] + node _T_916 = eq(_T_915, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2276:276] + node _T_917 = and(io.dec_csr_wen_r_mod, _T_916) @[dec_tlu_ctl.scala 2276:247] + node _T_918 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:298] + node _T_919 = and(_T_917, _T_918) @[dec_tlu_ctl.scala 2276:289] + node _T_920 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2276:331] + node _T_921 = eq(_T_920, UInt<1>("h00")) @[dec_tlu_ctl.scala 2276:315] + node _T_922 = or(_T_921, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2276:347] + node _T_923 = and(_T_919, _T_922) @[dec_tlu_ctl.scala 2276:312] + node _T_924 = eq(tdata_kill_write, UInt<1>("h00")) @[dec_tlu_ctl.scala 2276:373] + node _T_925 = and(_T_923, _T_924) @[dec_tlu_ctl.scala 2276:371] + wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2276:49] + wr_mtdata1_t_r[0] <= _T_894 @[dec_tlu_ctl.scala 2276:49] + wr_mtdata1_t_r[1] <= _T_905 @[dec_tlu_ctl.scala 2276:49] + wr_mtdata1_t_r[2] <= _T_914 @[dec_tlu_ctl.scala 2276:49] + wr_mtdata1_t_r[3] <= _T_925 @[dec_tlu_ctl.scala 2276:49] + node _T_926 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2278:77] + node _T_927 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2278:120] + node _T_928 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2278:144] + node _T_929 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2278:165] + node _T_930 = or(_T_928, _T_929) @[dec_tlu_ctl.scala 2278:148] + node _T_931 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2278:185] + node _T_932 = cat(_T_927, _T_930) @[Cat.scala 29:58] + node _T_933 = cat(_T_932, _T_931) @[Cat.scala 29:58] + node _T_934 = mux(_T_926, tdata_wrdata_r, _T_933) @[dec_tlu_ctl.scala 2278:58] + node _T_935 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2278:77] + node _T_936 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2278:120] + node _T_937 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2278:144] + node _T_938 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2278:165] + node _T_939 = or(_T_937, _T_938) @[dec_tlu_ctl.scala 2278:148] + node _T_940 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2278:185] + node _T_941 = cat(_T_936, _T_939) @[Cat.scala 29:58] + node _T_942 = cat(_T_941, _T_940) @[Cat.scala 29:58] + node _T_943 = mux(_T_935, tdata_wrdata_r, _T_942) @[dec_tlu_ctl.scala 2278:58] + node _T_944 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2278:77] + node _T_945 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2278:120] + node _T_946 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2278:144] + node _T_947 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2278:165] + node _T_948 = or(_T_946, _T_947) @[dec_tlu_ctl.scala 2278:148] + node _T_949 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2278:185] + node _T_950 = cat(_T_945, _T_948) @[Cat.scala 29:58] + node _T_951 = cat(_T_950, _T_949) @[Cat.scala 29:58] + node _T_952 = mux(_T_944, tdata_wrdata_r, _T_951) @[dec_tlu_ctl.scala 2278:58] + node _T_953 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2278:77] + node _T_954 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2278:120] + node _T_955 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2278:144] + node _T_956 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2278:165] + node _T_957 = or(_T_955, _T_956) @[dec_tlu_ctl.scala 2278:148] + node _T_958 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2278:185] + node _T_959 = cat(_T_954, _T_957) @[Cat.scala 29:58] + node _T_960 = cat(_T_959, _T_958) @[Cat.scala 29:58] + node _T_961 = mux(_T_953, tdata_wrdata_r, _T_960) @[dec_tlu_ctl.scala 2278:58] + wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2278:49] + mtdata1_t_ns[0] <= _T_934 @[dec_tlu_ctl.scala 2278:49] + mtdata1_t_ns[1] <= _T_943 @[dec_tlu_ctl.scala 2278:49] + mtdata1_t_ns[2] <= _T_952 @[dec_tlu_ctl.scala 2278:49] + mtdata1_t_ns[3] <= _T_961 @[dec_tlu_ctl.scala 2278:49] + node _T_962 = bits(io.trigger_enabled, 0, 0) @[dec_tlu_ctl.scala 2282:91] + node _T_963 = or(_T_962, wr_mtdata1_t_r[0]) @[dec_tlu_ctl.scala 2282:95] + node _T_964 = bits(_T_963, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_27 of rvclkhdr_81 @[lib.scala 404:23] + rvclkhdr_27.clock <= clock + rvclkhdr_27.reset <= reset + rvclkhdr_27.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_27.io.en <= _T_964 @[lib.scala 407:17] + rvclkhdr_27.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_965 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_964 : @[Reg.scala 28:19] + _T_965 <= mtdata1_t_ns[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mtdata1_t[0] <= _T_965 @[dec_tlu_ctl.scala 2282:47] + node _T_966 = bits(io.trigger_enabled, 1, 1) @[dec_tlu_ctl.scala 2282:91] + node _T_967 = or(_T_966, wr_mtdata1_t_r[1]) @[dec_tlu_ctl.scala 2282:95] + node _T_968 = bits(_T_967, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_28 of rvclkhdr_82 @[lib.scala 404:23] + rvclkhdr_28.clock <= clock + rvclkhdr_28.reset <= reset + rvclkhdr_28.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_28.io.en <= _T_968 @[lib.scala 407:17] + rvclkhdr_28.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_969 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_968 : @[Reg.scala 28:19] + _T_969 <= mtdata1_t_ns[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mtdata1_t[1] <= _T_969 @[dec_tlu_ctl.scala 2282:47] + node _T_970 = bits(io.trigger_enabled, 2, 2) @[dec_tlu_ctl.scala 2282:91] + node _T_971 = or(_T_970, wr_mtdata1_t_r[2]) @[dec_tlu_ctl.scala 2282:95] + node _T_972 = bits(_T_971, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_29 of rvclkhdr_83 @[lib.scala 404:23] + rvclkhdr_29.clock <= clock + rvclkhdr_29.reset <= reset + rvclkhdr_29.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_29.io.en <= _T_972 @[lib.scala 407:17] + rvclkhdr_29.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_973 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_972 : @[Reg.scala 28:19] + _T_973 <= mtdata1_t_ns[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mtdata1_t[2] <= _T_973 @[dec_tlu_ctl.scala 2282:47] + node _T_974 = bits(io.trigger_enabled, 3, 3) @[dec_tlu_ctl.scala 2282:91] + node _T_975 = or(_T_974, wr_mtdata1_t_r[3]) @[dec_tlu_ctl.scala 2282:95] + node _T_976 = bits(_T_975, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_30 of rvclkhdr_84 @[lib.scala 404:23] + rvclkhdr_30.clock <= clock + rvclkhdr_30.reset <= reset + rvclkhdr_30.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_30.io.en <= _T_976 @[lib.scala 407:17] + rvclkhdr_30.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_977 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_976 : @[Reg.scala 28:19] + _T_977 <= mtdata1_t_ns[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mtdata1_t[3] <= _T_977 @[dec_tlu_ctl.scala 2282:47] + node _T_978 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2285:66] + node _T_979 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2285:112] + node _T_980 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2285:150] + node _T_981 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2285:182] + node _T_982 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2285:214] + node _T_983 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2285:246] + node _T_984 = cat(UInt<3>("h00"), _T_983) @[Cat.scala 29:58] + node _T_985 = cat(_T_981, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_986 = cat(_T_985, _T_982) @[Cat.scala 29:58] + node _T_987 = cat(_T_986, _T_984) @[Cat.scala 29:58] + node _T_988 = cat(_T_980, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_989 = cat(UInt<4>("h02"), _T_979) @[Cat.scala 29:58] + node _T_990 = cat(_T_989, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_991 = cat(_T_990, _T_988) @[Cat.scala 29:58] + node _T_992 = cat(_T_991, _T_987) @[Cat.scala 29:58] + node _T_993 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2285:66] + node _T_994 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2285:112] + node _T_995 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2285:150] + node _T_996 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2285:182] + node _T_997 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2285:214] + node _T_998 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2285:246] + node _T_999 = cat(UInt<3>("h00"), _T_998) @[Cat.scala 29:58] + node _T_1000 = cat(_T_996, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1001 = cat(_T_1000, _T_997) @[Cat.scala 29:58] + node _T_1002 = cat(_T_1001, _T_999) @[Cat.scala 29:58] + node _T_1003 = cat(_T_995, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_1004 = cat(UInt<4>("h02"), _T_994) @[Cat.scala 29:58] + node _T_1005 = cat(_T_1004, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_1006 = cat(_T_1005, _T_1003) @[Cat.scala 29:58] + node _T_1007 = cat(_T_1006, _T_1002) @[Cat.scala 29:58] + node _T_1008 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2285:66] + node _T_1009 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2285:112] + node _T_1010 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2285:150] + node _T_1011 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2285:182] + node _T_1012 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2285:214] + node _T_1013 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2285:246] + node _T_1014 = cat(UInt<3>("h00"), _T_1013) @[Cat.scala 29:58] + node _T_1015 = cat(_T_1011, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1016 = cat(_T_1015, _T_1012) @[Cat.scala 29:58] + node _T_1017 = cat(_T_1016, _T_1014) @[Cat.scala 29:58] + node _T_1018 = cat(_T_1010, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_1019 = cat(UInt<4>("h02"), _T_1009) @[Cat.scala 29:58] + node _T_1020 = cat(_T_1019, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_1021 = cat(_T_1020, _T_1018) @[Cat.scala 29:58] + node _T_1022 = cat(_T_1021, _T_1017) @[Cat.scala 29:58] + node _T_1023 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2285:66] + node _T_1024 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2285:112] + node _T_1025 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2285:150] + node _T_1026 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2285:182] + node _T_1027 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2285:214] + node _T_1028 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2285:246] + node _T_1029 = cat(UInt<3>("h00"), _T_1028) @[Cat.scala 29:58] + node _T_1030 = cat(_T_1026, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1031 = cat(_T_1030, _T_1027) @[Cat.scala 29:58] + node _T_1032 = cat(_T_1031, _T_1029) @[Cat.scala 29:58] + node _T_1033 = cat(_T_1025, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_1034 = cat(UInt<4>("h02"), _T_1024) @[Cat.scala 29:58] + node _T_1035 = cat(_T_1034, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_1036 = cat(_T_1035, _T_1033) @[Cat.scala 29:58] + node _T_1037 = cat(_T_1036, _T_1032) @[Cat.scala 29:58] + node _T_1038 = mux(_T_978, _T_992, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1039 = mux(_T_993, _T_1007, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1040 = mux(_T_1008, _T_1022, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1041 = mux(_T_1023, _T_1037, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1042 = or(_T_1038, _T_1039) @[Mux.scala 27:72] + node _T_1043 = or(_T_1042, _T_1040) @[Mux.scala 27:72] + node _T_1044 = or(_T_1043, _T_1041) @[Mux.scala 27:72] + wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72] + mtdata1_tsel_out <= _T_1044 @[Mux.scala 27:72] + node _T_1045 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2287:66] + io.trigger_pkt_any[0].select <= _T_1045 @[dec_tlu_ctl.scala 2287:48] + node _T_1046 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2288:69] + io.trigger_pkt_any[0].match_pkt <= _T_1046 @[dec_tlu_ctl.scala 2288:51] + node _T_1047 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2289:66] + io.trigger_pkt_any[0].store <= _T_1047 @[dec_tlu_ctl.scala 2289:48] + node _T_1048 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2290:66] + io.trigger_pkt_any[0].load <= _T_1048 @[dec_tlu_ctl.scala 2290:48] + node _T_1049 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2291:66] + io.trigger_pkt_any[0].execute <= _T_1049 @[dec_tlu_ctl.scala 2291:48] + node _T_1050 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2292:66] + io.trigger_pkt_any[0].m <= _T_1050 @[dec_tlu_ctl.scala 2292:48] + node _T_1051 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2287:66] + io.trigger_pkt_any[1].select <= _T_1051 @[dec_tlu_ctl.scala 2287:48] + node _T_1052 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2288:69] + io.trigger_pkt_any[1].match_pkt <= _T_1052 @[dec_tlu_ctl.scala 2288:51] + node _T_1053 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2289:66] + io.trigger_pkt_any[1].store <= _T_1053 @[dec_tlu_ctl.scala 2289:48] + node _T_1054 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2290:66] + io.trigger_pkt_any[1].load <= _T_1054 @[dec_tlu_ctl.scala 2290:48] + node _T_1055 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2291:66] + io.trigger_pkt_any[1].execute <= _T_1055 @[dec_tlu_ctl.scala 2291:48] + node _T_1056 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2292:66] + io.trigger_pkt_any[1].m <= _T_1056 @[dec_tlu_ctl.scala 2292:48] + node _T_1057 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2287:66] + io.trigger_pkt_any[2].select <= _T_1057 @[dec_tlu_ctl.scala 2287:48] + node _T_1058 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2288:69] + io.trigger_pkt_any[2].match_pkt <= _T_1058 @[dec_tlu_ctl.scala 2288:51] + node _T_1059 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2289:66] + io.trigger_pkt_any[2].store <= _T_1059 @[dec_tlu_ctl.scala 2289:48] + node _T_1060 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2290:66] + io.trigger_pkt_any[2].load <= _T_1060 @[dec_tlu_ctl.scala 2290:48] + node _T_1061 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2291:66] + io.trigger_pkt_any[2].execute <= _T_1061 @[dec_tlu_ctl.scala 2291:48] + node _T_1062 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2292:66] + io.trigger_pkt_any[2].m <= _T_1062 @[dec_tlu_ctl.scala 2292:48] + node _T_1063 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2287:66] + io.trigger_pkt_any[3].select <= _T_1063 @[dec_tlu_ctl.scala 2287:48] + node _T_1064 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2288:69] + io.trigger_pkt_any[3].match_pkt <= _T_1064 @[dec_tlu_ctl.scala 2288:51] + node _T_1065 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2289:66] + io.trigger_pkt_any[3].store <= _T_1065 @[dec_tlu_ctl.scala 2289:48] + node _T_1066 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2290:66] + io.trigger_pkt_any[3].load <= _T_1066 @[dec_tlu_ctl.scala 2290:48] + node _T_1067 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2291:66] + io.trigger_pkt_any[3].execute <= _T_1067 @[dec_tlu_ctl.scala 2291:48] + node _T_1068 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2292:66] + io.trigger_pkt_any[3].m <= _T_1068 @[dec_tlu_ctl.scala 2292:48] + node _T_1069 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2299:98] + node _T_1070 = eq(_T_1069, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2299:105] + node _T_1071 = and(io.dec_csr_wen_r_mod, _T_1070) @[dec_tlu_ctl.scala 2299:76] + node _T_1072 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2299:127] + node _T_1073 = and(_T_1071, _T_1072) @[dec_tlu_ctl.scala 2299:118] + node _T_1074 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2299:160] + node _T_1075 = not(_T_1074) @[dec_tlu_ctl.scala 2299:144] + node _T_1076 = or(_T_1075, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2299:176] + node _T_1077 = and(_T_1073, _T_1076) @[dec_tlu_ctl.scala 2299:141] + node _T_1078 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2299:98] + node _T_1079 = eq(_T_1078, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2299:105] + node _T_1080 = and(io.dec_csr_wen_r_mod, _T_1079) @[dec_tlu_ctl.scala 2299:76] + node _T_1081 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2299:127] + node _T_1082 = and(_T_1080, _T_1081) @[dec_tlu_ctl.scala 2299:118] + node _T_1083 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2299:160] + node _T_1084 = not(_T_1083) @[dec_tlu_ctl.scala 2299:144] + node _T_1085 = or(_T_1084, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2299:176] + node _T_1086 = and(_T_1082, _T_1085) @[dec_tlu_ctl.scala 2299:141] + node _T_1087 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2299:98] + node _T_1088 = eq(_T_1087, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2299:105] + node _T_1089 = and(io.dec_csr_wen_r_mod, _T_1088) @[dec_tlu_ctl.scala 2299:76] + node _T_1090 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2299:127] + node _T_1091 = and(_T_1089, _T_1090) @[dec_tlu_ctl.scala 2299:118] + node _T_1092 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2299:160] + node _T_1093 = not(_T_1092) @[dec_tlu_ctl.scala 2299:144] + node _T_1094 = or(_T_1093, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2299:176] + node _T_1095 = and(_T_1091, _T_1094) @[dec_tlu_ctl.scala 2299:141] + node _T_1096 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2299:98] + node _T_1097 = eq(_T_1096, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2299:105] + node _T_1098 = and(io.dec_csr_wen_r_mod, _T_1097) @[dec_tlu_ctl.scala 2299:76] + node _T_1099 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2299:127] + node _T_1100 = and(_T_1098, _T_1099) @[dec_tlu_ctl.scala 2299:118] + node _T_1101 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2299:160] + node _T_1102 = not(_T_1101) @[dec_tlu_ctl.scala 2299:144] + node _T_1103 = or(_T_1102, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2299:176] + node _T_1104 = and(_T_1100, _T_1103) @[dec_tlu_ctl.scala 2299:141] + wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2299:49] + wr_mtdata2_t_r[0] <= _T_1077 @[dec_tlu_ctl.scala 2299:49] + wr_mtdata2_t_r[1] <= _T_1086 @[dec_tlu_ctl.scala 2299:49] + wr_mtdata2_t_r[2] <= _T_1095 @[dec_tlu_ctl.scala 2299:49] + wr_mtdata2_t_r[3] <= _T_1104 @[dec_tlu_ctl.scala 2299:49] + node _T_1105 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2300:92] + inst rvclkhdr_31 of rvclkhdr_85 @[lib.scala 404:23] + rvclkhdr_31.clock <= clock + rvclkhdr_31.reset <= reset + rvclkhdr_31.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_31.io.en <= _T_1105 @[lib.scala 407:17] + rvclkhdr_31.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1106 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1105 : @[Reg.scala 28:19] + _T_1106 <= io.dec_csr_wrdata_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mtdata2_t[0] <= _T_1106 @[dec_tlu_ctl.scala 2300:44] + node _T_1107 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2300:92] + inst rvclkhdr_32 of rvclkhdr_86 @[lib.scala 404:23] + rvclkhdr_32.clock <= clock + rvclkhdr_32.reset <= reset + rvclkhdr_32.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_32.io.en <= _T_1107 @[lib.scala 407:17] + rvclkhdr_32.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1108 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1107 : @[Reg.scala 28:19] + _T_1108 <= io.dec_csr_wrdata_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mtdata2_t[1] <= _T_1108 @[dec_tlu_ctl.scala 2300:44] + node _T_1109 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2300:92] + inst rvclkhdr_33 of rvclkhdr_87 @[lib.scala 404:23] + rvclkhdr_33.clock <= clock + rvclkhdr_33.reset <= reset + rvclkhdr_33.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_33.io.en <= _T_1109 @[lib.scala 407:17] + rvclkhdr_33.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1110 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1109 : @[Reg.scala 28:19] + _T_1110 <= io.dec_csr_wrdata_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mtdata2_t[2] <= _T_1110 @[dec_tlu_ctl.scala 2300:44] + node _T_1111 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2300:92] + inst rvclkhdr_34 of rvclkhdr_88 @[lib.scala 404:23] + rvclkhdr_34.clock <= clock + rvclkhdr_34.reset <= reset + rvclkhdr_34.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_34.io.en <= _T_1111 @[lib.scala 407:17] + rvclkhdr_34.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1112 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1111 : @[Reg.scala 28:19] + _T_1112 <= io.dec_csr_wrdata_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mtdata2_t[3] <= _T_1112 @[dec_tlu_ctl.scala 2300:44] + node _T_1113 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2304:65] + node _T_1114 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2304:65] + node _T_1115 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2304:65] + node _T_1116 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2304:65] + node _T_1117 = mux(_T_1113, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1118 = mux(_T_1114, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1119 = mux(_T_1115, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1120 = mux(_T_1116, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1121 = or(_T_1117, _T_1118) @[Mux.scala 27:72] + node _T_1122 = or(_T_1121, _T_1119) @[Mux.scala 27:72] + node _T_1123 = or(_T_1122, _T_1120) @[Mux.scala 27:72] + wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72] + mtdata2_tsel_out <= _T_1123 @[Mux.scala 27:72] + io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2305:59] + io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2305:59] + io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2305:59] + io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[dec_tlu_ctl.scala 2305:59] + mhpme_vec[0] <= perf_csrs.io.mhpme3 @[dec_tlu_ctl.scala 2313:22] + mhpme_vec[1] <= perf_csrs.io.mhpme4 @[dec_tlu_ctl.scala 2314:22] + mhpme_vec[2] <= perf_csrs.io.mhpme5 @[dec_tlu_ctl.scala 2315:22] + mhpme_vec[3] <= perf_csrs.io.mhpme6 @[dec_tlu_ctl.scala 2316:22] + perfmux_flop.io.mcountinhibit <= mcountinhibit @[dec_tlu_ctl.scala 2321:57] + perfmux_flop.io.mhpme_vec[0] <= mhpme_vec[0] @[dec_tlu_ctl.scala 2322:57] + perfmux_flop.io.mhpme_vec[1] <= mhpme_vec[1] @[dec_tlu_ctl.scala 2322:57] + perfmux_flop.io.mhpme_vec[2] <= mhpme_vec[2] @[dec_tlu_ctl.scala 2322:57] + perfmux_flop.io.mhpme_vec[3] <= mhpme_vec[3] @[dec_tlu_ctl.scala 2322:57] + perfmux_flop.io.ifu_pmu_ic_hit <= io.ifu_pmu_ic_hit @[dec_tlu_ctl.scala 2323:57] + perfmux_flop.io.ifu_pmu_ic_miss <= io.ifu_pmu_ic_miss @[dec_tlu_ctl.scala 2324:57] + perfmux_flop.io.tlu_i0_commit_cmt <= io.tlu_i0_commit_cmt @[dec_tlu_ctl.scala 2325:57] + perfmux_flop.io.illegal_r <= io.illegal_r @[dec_tlu_ctl.scala 2326:57] + perfmux_flop.io.exu_pmu_i0_pc4 <= io.exu_pmu_i0_pc4 @[dec_tlu_ctl.scala 2327:57] + perfmux_flop.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[dec_tlu_ctl.scala 2328:57] + perfmux_flop.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[dec_tlu_ctl.scala 2329:57] + perfmux_flop.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.dec_tlu_packet_r.icaf_second <= io.dec_tlu_packet_r.icaf_second @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.exu_pmu_i0_br_misp <= io.exu_pmu_i0_br_misp @[dec_tlu_ctl.scala 2331:57] + perfmux_flop.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[dec_tlu_ctl.scala 2332:57] + perfmux_flop.io.exu_pmu_i0_br_ataken <= io.exu_pmu_i0_br_ataken @[dec_tlu_ctl.scala 2333:57] + perfmux_flop.io.ifu_pmu_fetch_stall <= io.ifu_pmu_fetch_stall @[dec_tlu_ctl.scala 2334:57] + perfmux_flop.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[dec_tlu_ctl.scala 2335:57] + perfmux_flop.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[dec_tlu_ctl.scala 2336:57] + perfmux_flop.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec_tlu_ctl.scala 2337:57] + perfmux_flop.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[dec_tlu_ctl.scala 2338:57] + perfmux_flop.io.dma_iccm_stall_any <= io.dma_iccm_stall_any @[dec_tlu_ctl.scala 2339:57] + perfmux_flop.io.i0_exception_valid_r <= io.i0_exception_valid_r @[dec_tlu_ctl.scala 2340:57] + perfmux_flop.io.dec_tlu_pmu_fw_halted <= io.dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 2341:57] + perfmux_flop.io.dma_pmu_any_read <= io.dma_pmu_any_read @[dec_tlu_ctl.scala 2342:57] + perfmux_flop.io.dma_pmu_any_write <= io.dma_pmu_any_write @[dec_tlu_ctl.scala 2343:57] + perfmux_flop.io.dma_pmu_dccm_read <= io.dma_pmu_dccm_read @[dec_tlu_ctl.scala 2344:57] + perfmux_flop.io.dma_pmu_dccm_write <= io.dma_pmu_dccm_write @[dec_tlu_ctl.scala 2345:57] + perfmux_flop.io.lsu_pmu_load_external_r <= io.lsu_pmu_load_external_r @[dec_tlu_ctl.scala 2346:57] + perfmux_flop.io.lsu_pmu_store_external_r <= io.lsu_pmu_store_external_r @[dec_tlu_ctl.scala 2347:57] + io.mstatus <= perfmux_flop.io.mstatus @[dec_tlu_ctl.scala 2348:26] + io.mip <= perfmux_flop.io.mip @[dec_tlu_ctl.scala 2349:18] + perfmux_flop.io.mie <= mie @[dec_tlu_ctl.scala 2350:57] + perfmux_flop.io.ifu_pmu_bus_trxn <= io.ifu_pmu_bus_trxn @[dec_tlu_ctl.scala 2351:57] + perfmux_flop.io.lsu_pmu_bus_trxn <= io.lsu_pmu_bus_trxn @[dec_tlu_ctl.scala 2352:57] + perfmux_flop.io.lsu_pmu_bus_misaligned <= io.lsu_pmu_bus_misaligned @[dec_tlu_ctl.scala 2353:57] + perfmux_flop.io.ifu_pmu_bus_error <= io.ifu_pmu_bus_error @[dec_tlu_ctl.scala 2354:57] + perfmux_flop.io.lsu_pmu_bus_error <= io.lsu_pmu_bus_error @[dec_tlu_ctl.scala 2355:57] + perfmux_flop.io.ifu_pmu_bus_busy <= io.ifu_pmu_bus_busy @[dec_tlu_ctl.scala 2356:57] + perfmux_flop.io.lsu_pmu_bus_busy <= io.lsu_pmu_bus_busy @[dec_tlu_ctl.scala 2357:57] + perfmux_flop.io.i0_trigger_hit_r <= io.i0_trigger_hit_r @[dec_tlu_ctl.scala 2358:57] + perfmux_flop.io.lsu_exc_valid_r <= io.lsu_exc_valid_r @[dec_tlu_ctl.scala 2359:57] + perfmux_flop.io.take_timer_int <= io.take_timer_int @[dec_tlu_ctl.scala 2360:57] + perfmux_flop.io.take_int_timer0_int <= io.take_int_timer0_int @[dec_tlu_ctl.scala 2361:57] + perfmux_flop.io.take_int_timer1_int <= io.take_int_timer1_int @[dec_tlu_ctl.scala 2362:57] + perfmux_flop.io.take_ext_int <= io.take_ext_int @[dec_tlu_ctl.scala 2363:57] + perfmux_flop.io.tlu_flush_lower_r <= io.tlu_flush_lower_r @[dec_tlu_ctl.scala 2364:57] + perfmux_flop.io.dec_tlu_br0_error_r <= io.dec_tlu_br0_error_r @[dec_tlu_ctl.scala 2365:57] + perfmux_flop.io.rfpc_i0_r <= io.rfpc_i0_r @[dec_tlu_ctl.scala 2366:57] + perfmux_flop.io.dec_tlu_br0_start_error_r <= io.dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 2367:57] + io.mdseac_locked_f <= perfmux_flop.io.mdseac_locked_f @[dec_tlu_ctl.scala 2378:42] + io.lsu_exc_valid_r_d1 <= perfmux_flop.io.lsu_exc_valid_r_d1 @[dec_tlu_ctl.scala 2380:42] + io.take_ext_int_start_d1 <= perfmux_flop.io.take_ext_int_start_d1 @[dec_tlu_ctl.scala 2382:42] + io.take_ext_int_start_d2 <= perfmux_flop.io.take_ext_int_start_d2 @[dec_tlu_ctl.scala 2383:42] + io.take_ext_int_start_d3 <= perfmux_flop.io.take_ext_int_start_d3 @[dec_tlu_ctl.scala 2384:42] + io.ext_int_freeze_d1 <= perfmux_flop.io.ext_int_freeze_d1 @[dec_tlu_ctl.scala 2385:42] + perfmux_flop.io.mdseac_locked_ns <= io.mdseac_locked_ns @[dec_tlu_ctl.scala 2389:55] + perfmux_flop.io.lsu_single_ecc_error_r <= io.lsu_single_ecc_error_r @[dec_tlu_ctl.scala 2390:55] + perfmux_flop.io.lsu_i0_exc_r <= io.lsu_i0_exc_r @[dec_tlu_ctl.scala 2391:55] + perfmux_flop.io.take_ext_int_start <= io.take_ext_int_start @[dec_tlu_ctl.scala 2392:55] + perfmux_flop.io.ext_int_freeze <= io.ext_int_freeze @[dec_tlu_ctl.scala 2393:55] + perfmux_flop.io.mip_ns <= mip_ns @[dec_tlu_ctl.scala 2394:55] + perfmux_flop.io.mcyclel_cout <= mcyclel_cout @[dec_tlu_ctl.scala 2395:55] + perfmux_flop.io.wr_mcycleh_r <= wr_mcycleh_r @[dec_tlu_ctl.scala 2396:55] + perfmux_flop.io.mcyclel_cout_in <= mcyclel_cout_in @[dec_tlu_ctl.scala 2397:55] + perfmux_flop.io.minstret_enable <= minstret_enable @[dec_tlu_ctl.scala 2398:55] + perfmux_flop.io.minstretl_cout_ns <= minstretl_cout_ns @[dec_tlu_ctl.scala 2399:55] + perfmux_flop.io.fw_halted_ns <= fw_halted_ns @[dec_tlu_ctl.scala 2400:55] + perfmux_flop.io.meicidpl_ns <= meicidpl_ns @[dec_tlu_ctl.scala 2401:55] + perfmux_flop.io.icache_rd_valid <= icache_rd_valid @[dec_tlu_ctl.scala 2402:55] + perfmux_flop.io.icache_wr_valid <= icache_wr_valid @[dec_tlu_ctl.scala 2403:55] + node _T_1124 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2404:91] + node _T_1125 = and(io.dec_tlu_dbg_halted, _T_1124) @[dec_tlu_ctl.scala 2404:82] + node _T_1126 = or(_T_1125, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2404:105] + perfmux_flop.io.perfcnt_halted <= _T_1126 @[dec_tlu_ctl.scala 2404:55] + perfmux_flop.io.mstatus_ns <= mstatus_ns @[dec_tlu_ctl.scala 2405:55] + perfmux_flop.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 2406:55] + perfmux_flop.io.free_l2clk <= io.free_l2clk @[dec_tlu_ctl.scala 2407:56] + perf_csrs.io.free_l2clk <= io.free_l2clk @[dec_tlu_ctl.scala 2411:50] + perf_csrs.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 2412:50] + perf_csrs.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[dec_tlu_ctl.scala 2413:50] + perf_csrs.io.dcsr <= io.dcsr @[dec_tlu_ctl.scala 2414:50] + perf_csrs.io.dec_tlu_pmu_fw_halted <= io.dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 2415:50] + perf_csrs.io.mhpme_vec[0] <= mhpme_vec[0] @[dec_tlu_ctl.scala 2416:50] + perf_csrs.io.mhpme_vec[1] <= mhpme_vec[1] @[dec_tlu_ctl.scala 2416:50] + perf_csrs.io.mhpme_vec[2] <= mhpme_vec[2] @[dec_tlu_ctl.scala 2416:50] + perf_csrs.io.mhpme_vec[3] <= mhpme_vec[3] @[dec_tlu_ctl.scala 2416:50] + perf_csrs.io.dec_csr_wen_r_mod <= io.dec_csr_wen_r_mod @[dec_tlu_ctl.scala 2417:50] + perf_csrs.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 2418:50] + perf_csrs.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 2419:50] + perf_csrs.io.mhpmc_inc_r[0] <= perfmux_flop.io.mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2420:50] + perf_csrs.io.mhpmc_inc_r[1] <= perfmux_flop.io.mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2420:50] + perf_csrs.io.mhpmc_inc_r[2] <= perfmux_flop.io.mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2420:50] + perf_csrs.io.mhpmc_inc_r[3] <= perfmux_flop.io.mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2420:50] + perf_csrs.io.mhpmc_inc_r_d1[0] <= perfmux_flop.io.mhpmc_inc_r_d1[0] @[dec_tlu_ctl.scala 2421:50] + perf_csrs.io.mhpmc_inc_r_d1[1] <= perfmux_flop.io.mhpmc_inc_r_d1[1] @[dec_tlu_ctl.scala 2421:50] + perf_csrs.io.mhpmc_inc_r_d1[2] <= perfmux_flop.io.mhpmc_inc_r_d1[2] @[dec_tlu_ctl.scala 2421:50] + perf_csrs.io.mhpmc_inc_r_d1[3] <= perfmux_flop.io.mhpmc_inc_r_d1[3] @[dec_tlu_ctl.scala 2421:50] + perf_csrs.io.perfcnt_halted_d1 <= perfmux_flop.io.perfcnt_halted_d1 @[dec_tlu_ctl.scala 2422:50] + io.dec_tlu_perfcnt0 <= perf_csrs.io.dec_tlu_perfcnt0 @[dec_tlu_ctl.scala 2436:29] + io.dec_tlu_perfcnt1 <= perf_csrs.io.dec_tlu_perfcnt1 @[dec_tlu_ctl.scala 2437:29] + io.dec_tlu_perfcnt2 <= perf_csrs.io.dec_tlu_perfcnt2 @[dec_tlu_ctl.scala 2438:29] + io.dec_tlu_perfcnt3 <= perf_csrs.io.dec_tlu_perfcnt3 @[dec_tlu_ctl.scala 2439:29] + node _T_1127 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2455:77] + node _T_1128 = eq(_T_1127, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2455:84] + node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_1128) @[dec_tlu_ctl.scala 2455:55] + node _T_1129 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2457:61] + wire temp_ncount0 : UInt<1> + temp_ncount0 <= _T_1129 + node _T_1130 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2458:61] + wire temp_ncount1 : UInt<1> + temp_ncount1 <= _T_1130 + node _T_1131 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2459:62] + wire temp_ncount6_2 : UInt<5> + temp_ncount6_2 <= _T_1131 + node _T_1132 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2460:81] + node _T_1133 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2460:110] + reg _T_1134 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1133 : @[Reg.scala 28:19] + _T_1134 <= _T_1132 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + temp_ncount6_2 <= _T_1134 @[dec_tlu_ctl.scala 2460:24] + node _T_1135 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2462:79] + node _T_1136 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2462:106] + reg _T_1137 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1136 : @[Reg.scala 28:19] + _T_1137 <= _T_1135 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + temp_ncount0 <= _T_1137 @[dec_tlu_ctl.scala 2462:22] + node _T_1138 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_1139 = cat(_T_1138, temp_ncount0) @[Cat.scala 29:58] + mcountinhibit <= _T_1139 @[dec_tlu_ctl.scala 2463:23] + node _T_1140 = eq(io.dec_tlu_trace_disable, UInt<1>("h00")) @[dec_tlu_ctl.scala 2468:42] + node _T_1141 = and(_T_1140, io.i0_valid_wb) @[dec_tlu_ctl.scala 2468:68] + io.dec_tlu_i0_valid_wb1 <= _T_1141 @[dec_tlu_ctl.scala 2468:39] + node _T_1142 = eq(io.dec_tlu_trace_disable, UInt<1>("h00")) @[dec_tlu_ctl.scala 2469:42] + node _T_1143 = or(io.i0_exception_valid_r_d1, perfmux_flop.io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2469:98] + node _T_1144 = eq(io.trigger_hit_dmode_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 2469:158] + node _T_1145 = and(io.trigger_hit_r_d1, _T_1144) @[dec_tlu_ctl.scala 2469:156] + node _T_1146 = or(_T_1143, _T_1145) @[dec_tlu_ctl.scala 2469:133] + node _T_1147 = and(_T_1142, _T_1146) @[dec_tlu_ctl.scala 2469:68] + io.dec_tlu_i0_exc_valid_wb1 <= _T_1147 @[dec_tlu_ctl.scala 2469:39] + node _T_1148 = eq(io.dec_tlu_trace_disable, UInt<1>("h00")) @[dec_tlu_ctl.scala 2470:49] + node _T_1149 = bits(_T_1148, 0, 0) @[Bitwise.scala 72:15] + node _T_1150 = mux(_T_1149, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node dec_tlu_exc_cause_wb1_raw = and(_T_1150, io.exc_cause_wb) @[dec_tlu_ctl.scala 2470:77] + node _T_1151 = eq(io.dec_tlu_trace_disable, UInt<1>("h00")) @[dec_tlu_ctl.scala 2471:42] + node dec_tlu_int_valid_wb1_raw = and(_T_1151, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2471:68] + wire dec_tlu_exc_cause_wb2 : UInt + dec_tlu_exc_cause_wb2 <= UInt<1>("h00") + node _T_1152 = xor(dec_tlu_exc_cause_wb1_raw, dec_tlu_exc_cause_wb2) @[lib.scala 448:21] + node _T_1153 = orr(_T_1152) @[lib.scala 448:29] + reg _T_1154 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1153 : @[Reg.scala 28:19] + _T_1154 <= dec_tlu_exc_cause_wb1_raw @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dec_tlu_exc_cause_wb2 <= _T_1154 @[lib.scala 451:16] + wire dec_tlu_int_valid_wb2 : UInt<1> + dec_tlu_int_valid_wb2 <= UInt<1>("h00") + node _T_1155 = xor(dec_tlu_int_valid_wb1_raw, dec_tlu_int_valid_wb2) @[lib.scala 470:21] + node _T_1156 = orr(_T_1155) @[lib.scala 470:29] + reg _T_1157 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1156 : @[Reg.scala 28:19] + _T_1157 <= dec_tlu_int_valid_wb1_raw @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dec_tlu_int_valid_wb2 <= _T_1157 @[lib.scala 473:16] + node _T_1158 = mux(dec_tlu_int_valid_wb2, dec_tlu_exc_cause_wb2, dec_tlu_exc_cause_wb1_raw) @[dec_tlu_ctl.scala 2477:40] + io.dec_tlu_exc_cause_wb1 <= _T_1158 @[dec_tlu_ctl.scala 2477:34] + io.dec_tlu_int_valid_wb1 <= dec_tlu_int_valid_wb2 @[dec_tlu_ctl.scala 2478:34] + io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2479:31] + node _T_1159 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2486:37] + node _T_1160 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2487:42] + node _T_1161 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2488:40] + node _T_1162 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2489:39] + node _T_1163 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2490:40] + node _T_1164 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1165 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2491:40] + node _T_1166 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2491:103] + node _T_1167 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2491:128] + node _T_1168 = cat(UInt<3>("h00"), _T_1167) @[Cat.scala 29:58] + node _T_1169 = cat(_T_1168, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1170 = cat(UInt<3>("h00"), _T_1166) @[Cat.scala 29:58] + node _T_1171 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] + node _T_1172 = cat(_T_1171, _T_1170) @[Cat.scala 29:58] + node _T_1173 = cat(_T_1172, _T_1169) @[Cat.scala 29:58] + node _T_1174 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2492:38] + node _T_1175 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2492:70] + node _T_1176 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2492:96] + node _T_1177 = cat(_T_1175, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_1178 = cat(_T_1177, _T_1176) @[Cat.scala 29:58] + node _T_1179 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2493:36] + node _T_1180 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2493:78] + node _T_1181 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2493:102] + node _T_1182 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2493:123] + node _T_1183 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2493:144] + node _T_1184 = cat(_T_1183, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1185 = cat(_T_1182, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1186 = cat(_T_1185, _T_1184) @[Cat.scala 29:58] + node _T_1187 = cat(_T_1181, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1188 = cat(UInt<1>("h00"), _T_1180) @[Cat.scala 29:58] + node _T_1189 = cat(_T_1188, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_1190 = cat(_T_1189, _T_1187) @[Cat.scala 29:58] + node _T_1191 = cat(_T_1190, _T_1186) @[Cat.scala 29:58] + node _T_1192 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2494:36] + node _T_1193 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2494:75] + node _T_1194 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2494:96] + node _T_1195 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2494:114] + node _T_1196 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2494:132] + node _T_1197 = cat(_T_1196, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1198 = cat(_T_1195, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1199 = cat(_T_1198, _T_1197) @[Cat.scala 29:58] + node _T_1200 = cat(_T_1194, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1201 = cat(UInt<1>("h00"), _T_1193) @[Cat.scala 29:58] + node _T_1202 = cat(_T_1201, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_1203 = cat(_T_1202, _T_1200) @[Cat.scala 29:58] + node _T_1204 = cat(_T_1203, _T_1199) @[Cat.scala 29:58] + node _T_1205 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2495:40] + node _T_1206 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2495:65] + node _T_1207 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2496:40] + node _T_1208 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2496:69] + node _T_1209 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2497:42] + node _T_1210 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2497:72] + node _T_1211 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2498:42] + node _T_1212 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2498:72] + node _T_1213 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2499:41] + node _T_1214 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2499:66] + node _T_1215 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2500:37] + node _T_1216 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_1217 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2501:39] + node _T_1218 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2501:64] + node _T_1219 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2502:40] + node _T_1220 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2502:80] + node _T_1221 = cat(UInt<28>("h00"), _T_1220) @[Cat.scala 29:58] + node _T_1222 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2503:38] + node _T_1223 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2503:63] + node _T_1224 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2504:37] + node _T_1225 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2504:62] + node _T_1226 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2505:39] + node _T_1227 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2505:64] + node _T_1228 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2506:38] + node _T_1229 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] + node _T_1230 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2507:39] + node _T_1231 = cat(meivt, meihap) @[Cat.scala 29:58] + node _T_1232 = cat(_T_1231, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_1233 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2508:41] + node _T_1234 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2508:81] + node _T_1235 = cat(UInt<28>("h00"), _T_1234) @[Cat.scala 29:58] + node _T_1236 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2509:41] + node _T_1237 = bits(perfmux_flop.io.meicidpl, 3, 0) @[dec_tlu_ctl.scala 2509:97] + node _T_1238 = cat(UInt<28>("h00"), _T_1237) @[Cat.scala 29:58] + node _T_1239 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2510:38] + node _T_1240 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2510:78] + node _T_1241 = cat(UInt<28>("h00"), _T_1240) @[Cat.scala 29:58] + node _T_1242 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2511:37] + node _T_1243 = bits(mcgc, 9, 0) @[dec_tlu_ctl.scala 2511:77] + node _T_1244 = cat(UInt<22>("h00"), _T_1243) @[Cat.scala 29:58] + node _T_1245 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2512:37] + node _T_1246 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2512:77] + node _T_1247 = cat(UInt<13>("h00"), _T_1246) @[Cat.scala 29:58] + node _T_1248 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2513:37] + node _T_1249 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2513:85] + node _T_1250 = cat(UInt<16>("h04000"), _T_1249) @[Cat.scala 29:58] + node _T_1251 = cat(_T_1250, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_1252 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2514:36] + node _T_1253 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_1254 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2515:39] + node _T_1255 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2515:64] + node _T_1256 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2516:40] + node _T_1257 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2516:65] + node _T_1258 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2517:39] + node _T_1259 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2517:64] + node _T_1260 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2518:41] + node _T_1261 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2518:80] + node _T_1262 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2518:104] + node _T_1263 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2518:131] + node _T_1264 = cat(UInt<3>("h00"), _T_1263) @[Cat.scala 29:58] + node _T_1265 = cat(_T_1264, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1266 = cat(UInt<2>("h00"), _T_1262) @[Cat.scala 29:58] + node _T_1267 = cat(UInt<7>("h00"), _T_1261) @[Cat.scala 29:58] + node _T_1268 = cat(_T_1267, _T_1266) @[Cat.scala 29:58] + node _T_1269 = cat(_T_1268, _T_1265) @[Cat.scala 29:58] + node _T_1270 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2519:38] + node _T_1271 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2519:78] + node _T_1272 = cat(UInt<30>("h00"), _T_1271) @[Cat.scala 29:58] + node _T_1273 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2520:40] + node _T_1274 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2520:74] + node _T_1275 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2521:40] + node _T_1276 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2521:74] + node _T_1277 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2522:39] + node _T_1278 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2522:64] + node _T_1279 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2523:41] + node _T_1280 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2523:66] + node _T_1281 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2524:41] + node _T_1282 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2524:66] + node _T_1283 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2525:39] + node _T_1284 = bits(perf_csrs.io.mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2525:77] + node _T_1285 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2526:39] + node _T_1286 = bits(perf_csrs.io.mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2526:77] + node _T_1287 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2527:39] + node _T_1288 = bits(perf_csrs.io.mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2527:77] + node _T_1289 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2528:39] + node _T_1290 = bits(perf_csrs.io.mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2528:77] + node _T_1291 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2529:40] + node _T_1292 = bits(perf_csrs.io.mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2529:78] + node _T_1293 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2530:40] + node _T_1294 = bits(perf_csrs.io.mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2530:78] + node _T_1295 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2531:40] + node _T_1296 = bits(perf_csrs.io.mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2531:78] + node _T_1297 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2532:40] + node _T_1298 = bits(perf_csrs.io.mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2532:78] + node _T_1299 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2533:38] + node _T_1300 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2533:78] + node _T_1301 = cat(UInt<26>("h00"), _T_1300) @[Cat.scala 29:58] + node _T_1302 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2534:38] + node _T_1303 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2534:78] + node _T_1304 = cat(UInt<30>("h00"), _T_1303) @[Cat.scala 29:58] + node _T_1305 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2535:39] + node _T_1306 = bits(perf_csrs.io.mhpme3, 9, 0) @[dec_tlu_ctl.scala 2535:92] + node _T_1307 = cat(UInt<22>("h00"), _T_1306) @[Cat.scala 29:58] + node _T_1308 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2536:39] + node _T_1309 = bits(perf_csrs.io.mhpme4, 9, 0) @[dec_tlu_ctl.scala 2536:92] + node _T_1310 = cat(UInt<22>("h00"), _T_1309) @[Cat.scala 29:58] + node _T_1311 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2537:39] + node _T_1312 = bits(perf_csrs.io.mhpme5, 9, 0) @[dec_tlu_ctl.scala 2537:91] + node _T_1313 = cat(UInt<22>("h00"), _T_1312) @[Cat.scala 29:58] + node _T_1314 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2538:39] + node _T_1315 = bits(perf_csrs.io.mhpme6, 9, 0) @[dec_tlu_ctl.scala 2538:91] + node _T_1316 = cat(UInt<22>("h00"), _T_1315) @[Cat.scala 29:58] + node _T_1317 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2539:46] + node _T_1318 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2539:86] + node _T_1319 = cat(UInt<25>("h00"), _T_1318) @[Cat.scala 29:58] + node _T_1320 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2540:37] + node _T_1321 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] + node _T_1322 = cat(_T_1321, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_1323 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2541:37] + node _T_1324 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2541:76] + node _T_1325 = mux(_T_1159, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1326 = mux(_T_1160, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1327 = mux(_T_1161, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1328 = mux(_T_1162, UInt<32>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1329 = mux(_T_1163, _T_1164, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1330 = mux(_T_1165, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1331 = mux(_T_1174, _T_1178, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1332 = mux(_T_1179, _T_1191, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1333 = mux(_T_1192, _T_1204, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1334 = mux(_T_1205, _T_1206, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1335 = mux(_T_1207, _T_1208, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1336 = mux(_T_1209, _T_1210, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1337 = mux(_T_1211, _T_1212, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1338 = mux(_T_1213, _T_1214, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1339 = mux(_T_1215, _T_1216, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1340 = mux(_T_1217, _T_1218, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1341 = mux(_T_1219, _T_1221, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1342 = mux(_T_1222, _T_1223, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1343 = mux(_T_1224, _T_1225, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1344 = mux(_T_1226, _T_1227, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1345 = mux(_T_1228, _T_1229, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1346 = mux(_T_1230, _T_1232, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1347 = mux(_T_1233, _T_1235, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1348 = mux(_T_1236, _T_1238, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1349 = mux(_T_1239, _T_1241, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1350 = mux(_T_1242, _T_1244, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1351 = mux(_T_1245, _T_1247, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1352 = mux(_T_1248, _T_1251, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1353 = mux(_T_1252, _T_1253, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1354 = mux(_T_1254, _T_1255, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1355 = mux(_T_1256, _T_1257, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1356 = mux(_T_1258, _T_1259, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1357 = mux(_T_1260, _T_1269, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1358 = mux(_T_1270, _T_1272, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1359 = mux(_T_1273, _T_1274, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1360 = mux(_T_1275, _T_1276, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1361 = mux(_T_1277, _T_1278, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1362 = mux(_T_1279, _T_1280, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1363 = mux(_T_1281, _T_1282, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1364 = mux(_T_1283, _T_1284, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1365 = mux(_T_1285, _T_1286, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1366 = mux(_T_1287, _T_1288, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1367 = mux(_T_1289, _T_1290, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1368 = mux(_T_1291, _T_1292, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1369 = mux(_T_1293, _T_1294, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1370 = mux(_T_1295, _T_1296, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1371 = mux(_T_1297, _T_1298, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1372 = mux(_T_1299, _T_1301, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1373 = mux(_T_1302, _T_1304, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1374 = mux(_T_1305, _T_1307, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1375 = mux(_T_1308, _T_1310, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1376 = mux(_T_1311, _T_1313, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1377 = mux(_T_1314, _T_1316, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1378 = mux(_T_1317, _T_1319, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1379 = mux(_T_1320, _T_1322, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1380 = mux(_T_1323, _T_1324, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1381 = or(_T_1325, _T_1326) @[Mux.scala 27:72] + node _T_1382 = or(_T_1381, _T_1327) @[Mux.scala 27:72] + node _T_1383 = or(_T_1382, _T_1328) @[Mux.scala 27:72] + node _T_1384 = or(_T_1383, _T_1329) @[Mux.scala 27:72] + node _T_1385 = or(_T_1384, _T_1330) @[Mux.scala 27:72] + node _T_1386 = or(_T_1385, _T_1331) @[Mux.scala 27:72] + node _T_1387 = or(_T_1386, _T_1332) @[Mux.scala 27:72] + node _T_1388 = or(_T_1387, _T_1333) @[Mux.scala 27:72] + node _T_1389 = or(_T_1388, _T_1334) @[Mux.scala 27:72] + node _T_1390 = or(_T_1389, _T_1335) @[Mux.scala 27:72] + node _T_1391 = or(_T_1390, _T_1336) @[Mux.scala 27:72] + node _T_1392 = or(_T_1391, _T_1337) @[Mux.scala 27:72] + node _T_1393 = or(_T_1392, _T_1338) @[Mux.scala 27:72] + node _T_1394 = or(_T_1393, _T_1339) @[Mux.scala 27:72] + node _T_1395 = or(_T_1394, _T_1340) @[Mux.scala 27:72] + node _T_1396 = or(_T_1395, _T_1341) @[Mux.scala 27:72] + node _T_1397 = or(_T_1396, _T_1342) @[Mux.scala 27:72] + node _T_1398 = or(_T_1397, _T_1343) @[Mux.scala 27:72] + node _T_1399 = or(_T_1398, _T_1344) @[Mux.scala 27:72] + node _T_1400 = or(_T_1399, _T_1345) @[Mux.scala 27:72] + node _T_1401 = or(_T_1400, _T_1346) @[Mux.scala 27:72] + node _T_1402 = or(_T_1401, _T_1347) @[Mux.scala 27:72] + node _T_1403 = or(_T_1402, _T_1348) @[Mux.scala 27:72] + node _T_1404 = or(_T_1403, _T_1349) @[Mux.scala 27:72] + node _T_1405 = or(_T_1404, _T_1350) @[Mux.scala 27:72] + node _T_1406 = or(_T_1405, _T_1351) @[Mux.scala 27:72] + node _T_1407 = or(_T_1406, _T_1352) @[Mux.scala 27:72] + node _T_1408 = or(_T_1407, _T_1353) @[Mux.scala 27:72] + node _T_1409 = or(_T_1408, _T_1354) @[Mux.scala 27:72] + node _T_1410 = or(_T_1409, _T_1355) @[Mux.scala 27:72] + node _T_1411 = or(_T_1410, _T_1356) @[Mux.scala 27:72] + node _T_1412 = or(_T_1411, _T_1357) @[Mux.scala 27:72] + node _T_1413 = or(_T_1412, _T_1358) @[Mux.scala 27:72] + node _T_1414 = or(_T_1413, _T_1359) @[Mux.scala 27:72] + node _T_1415 = or(_T_1414, _T_1360) @[Mux.scala 27:72] + node _T_1416 = or(_T_1415, _T_1361) @[Mux.scala 27:72] + node _T_1417 = or(_T_1416, _T_1362) @[Mux.scala 27:72] + node _T_1418 = or(_T_1417, _T_1363) @[Mux.scala 27:72] + node _T_1419 = or(_T_1418, _T_1364) @[Mux.scala 27:72] + node _T_1420 = or(_T_1419, _T_1365) @[Mux.scala 27:72] + node _T_1421 = or(_T_1420, _T_1366) @[Mux.scala 27:72] + node _T_1422 = or(_T_1421, _T_1367) @[Mux.scala 27:72] + node _T_1423 = or(_T_1422, _T_1368) @[Mux.scala 27:72] + node _T_1424 = or(_T_1423, _T_1369) @[Mux.scala 27:72] + node _T_1425 = or(_T_1424, _T_1370) @[Mux.scala 27:72] + node _T_1426 = or(_T_1425, _T_1371) @[Mux.scala 27:72] + node _T_1427 = or(_T_1426, _T_1372) @[Mux.scala 27:72] + node _T_1428 = or(_T_1427, _T_1373) @[Mux.scala 27:72] + node _T_1429 = or(_T_1428, _T_1374) @[Mux.scala 27:72] + node _T_1430 = or(_T_1429, _T_1375) @[Mux.scala 27:72] + node _T_1431 = or(_T_1430, _T_1376) @[Mux.scala 27:72] + node _T_1432 = or(_T_1431, _T_1377) @[Mux.scala 27:72] + node _T_1433 = or(_T_1432, _T_1378) @[Mux.scala 27:72] + node _T_1434 = or(_T_1433, _T_1379) @[Mux.scala 27:72] + node _T_1435 = or(_T_1434, _T_1380) @[Mux.scala 27:72] + wire _T_1436 : UInt @[Mux.scala 27:72] + _T_1436 <= _T_1435 @[Mux.scala 27:72] + io.dec_csr_rddata_d <= _T_1436 @[dec_tlu_ctl.scala 2485:28] + + extmodule gated_latch_89 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_89 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_89 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_90 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_90 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_90 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_91 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_91 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_91 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_92 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_92 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_92 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_93 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_93 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_93 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_94 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_94 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_94 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module dec_timer_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip free_l2clk : Clock, flip csr_wr_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wen_r_mod : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip csr_mitctl0 : UInt<1>, flip csr_mitctl1 : UInt<1>, flip csr_mitb0 : UInt<1>, flip csr_mitb1 : UInt<1>, flip csr_mitcnt0 : UInt<1>, flip csr_mitcnt1 : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip internal_dbg_halt_timers : UInt<1>, dec_timer_rddata_d : UInt<32>, dec_timer_read_d : UInt<1>, dec_timer_t0_pulse : UInt<1>, dec_timer_t1_pulse : UInt<1>} + + wire mitctl1 : UInt<4> + mitctl1 <= UInt<1>("h00") + wire mitctl0 : UInt<3> + mitctl0 <= UInt<1>("h00") + wire mitb1 : UInt<32> + mitb1 <= UInt<1>("h00") + wire mitb0 : UInt<32> + mitb0 <= UInt<1>("h00") + wire mitcnt1 : UInt<32> + mitcnt1 <= UInt<1>("h00") + wire mitcnt0 : UInt<32> + mitcnt0 <= UInt<1>("h00") + node mit0_match_ns = geq(mitcnt0, mitb0) @[dec_tlu_ctl.scala 3277:36] + node mit1_match_ns = geq(mitcnt1, mitb1) @[dec_tlu_ctl.scala 3278:36] + io.dec_timer_t0_pulse <= mit0_match_ns @[dec_tlu_ctl.scala 3280:31] + io.dec_timer_t1_pulse <= mit1_match_ns @[dec_tlu_ctl.scala 3281:31] + node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[dec_tlu_ctl.scala 3288:72] + node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[dec_tlu_ctl.scala 3288:49] + node _T_1 = bits(mitctl0, 0, 0) @[dec_tlu_ctl.scala 3290:37] + node _T_2 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 3290:56] + node _T_3 = bits(mitctl0, 2, 2) @[dec_tlu_ctl.scala 3290:85] + node _T_4 = or(_T_2, _T_3) @[dec_tlu_ctl.scala 3290:76] + node _T_5 = and(_T_1, _T_4) @[dec_tlu_ctl.scala 3290:53] + node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 3290:112] + node _T_7 = bits(mitctl0, 1, 1) @[dec_tlu_ctl.scala 3290:147] + node _T_8 = or(_T_6, _T_7) @[dec_tlu_ctl.scala 3290:138] + node _T_9 = and(_T_5, _T_8) @[dec_tlu_ctl.scala 3290:109] + node _T_10 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 3290:173] + node mitcnt0_inc_ok = and(_T_9, _T_10) @[dec_tlu_ctl.scala 3290:171] + wire mitcnt0_inc1 : UInt<9> + mitcnt0_inc1 <= UInt<1>("h00") + wire mitcnt0_inc2 : UInt<24> + mitcnt0_inc2 <= UInt<1>("h00") + node _T_11 = bits(mitcnt0, 7, 0) @[dec_tlu_ctl.scala 3293:32] + node _T_12 = cat(UInt<7>("h00"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_13 = add(_T_11, _T_12) @[dec_tlu_ctl.scala 3293:38] + node _T_14 = tail(_T_13, 1) @[dec_tlu_ctl.scala 3293:38] + mitcnt0_inc1 <= _T_14 @[dec_tlu_ctl.scala 3293:22] + node mitcnt0_inc_cout = bits(mitcnt0_inc1, 8, 8) @[dec_tlu_ctl.scala 3294:44] + node _T_15 = bits(mitcnt0, 31, 8) @[dec_tlu_ctl.scala 3295:32] + node _T_16 = cat(UInt<23>("h00"), mitcnt0_inc_cout) @[Cat.scala 29:58] + node _T_17 = add(_T_15, _T_16) @[dec_tlu_ctl.scala 3295:39] + node _T_18 = tail(_T_17, 1) @[dec_tlu_ctl.scala 3295:39] + mitcnt0_inc2 <= _T_18 @[dec_tlu_ctl.scala 3295:22] + node _T_19 = bits(mitcnt0_inc1, 7, 0) @[dec_tlu_ctl.scala 3296:56] + node mitcnt0_inc = cat(mitcnt0_inc2, _T_19) @[Cat.scala 29:58] + node _T_20 = bits(wr_mitcnt0_r, 0, 0) @[lib.scala 8:44] + node _T_21 = bits(mit0_match_ns, 0, 0) @[lib.scala 8:44] + node _T_22 = mux(_T_21, UInt<1>("h00"), mitcnt0_inc) @[dec_tlu_ctl.scala 3298:69] + node mitcnt0_ns = mux(_T_20, io.dec_csr_wrdata_r, _T_22) @[dec_tlu_ctl.scala 3298:30] + node _T_23 = bits(mitcnt0_ns, 31, 8) @[dec_tlu_ctl.scala 3301:48] + node _T_24 = and(mitcnt0_inc_ok, mitcnt0_inc_cout) @[dec_tlu_ctl.scala 3301:87] + node _T_25 = or(wr_mitcnt0_r, _T_24) @[dec_tlu_ctl.scala 3301:69] + node _T_26 = or(_T_25, mit0_match_ns) @[dec_tlu_ctl.scala 3301:107] + node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 3301:124] + inst rvclkhdr of rvclkhdr_89 @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr.io.en <= _T_27 @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_28 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_27 : @[Reg.scala 28:19] + _T_28 <= _T_23 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_29 = bits(mitcnt0_ns, 7, 0) @[dec_tlu_ctl.scala 3302:34] + node _T_30 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[dec_tlu_ctl.scala 3302:54] + node _T_31 = or(_T_30, mit0_match_ns) @[dec_tlu_ctl.scala 3302:71] + node _T_32 = bits(_T_31, 0, 0) @[dec_tlu_ctl.scala 3302:88] + inst rvclkhdr_1 of rvclkhdr_90 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_32 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_33 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_32 : @[Reg.scala 28:19] + _T_33 <= _T_29 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_34 = cat(_T_28, _T_33) @[Cat.scala 29:58] + mitcnt0 <= _T_34 @[dec_tlu_ctl.scala 3301:25] + node _T_35 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[dec_tlu_ctl.scala 3309:72] + node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_35) @[dec_tlu_ctl.scala 3309:49] + node _T_36 = bits(mitctl1, 0, 0) @[dec_tlu_ctl.scala 3311:37] + node _T_37 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 3311:56] + node _T_38 = bits(mitctl1, 2, 2) @[dec_tlu_ctl.scala 3311:85] + node _T_39 = or(_T_37, _T_38) @[dec_tlu_ctl.scala 3311:76] + node _T_40 = and(_T_36, _T_39) @[dec_tlu_ctl.scala 3311:53] + node _T_41 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 3311:112] + node _T_42 = bits(mitctl1, 1, 1) @[dec_tlu_ctl.scala 3311:147] + node _T_43 = or(_T_41, _T_42) @[dec_tlu_ctl.scala 3311:138] + node _T_44 = and(_T_40, _T_43) @[dec_tlu_ctl.scala 3311:109] + node _T_45 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 3311:173] + node _T_46 = and(_T_44, _T_45) @[dec_tlu_ctl.scala 3311:171] + node _T_47 = bits(mitctl1, 3, 3) @[dec_tlu_ctl.scala 3311:213] + node _T_48 = not(_T_47) @[dec_tlu_ctl.scala 3311:205] + node _T_49 = or(_T_48, mit0_match_ns) @[dec_tlu_ctl.scala 3311:217] + node mitcnt1_inc_ok = and(_T_46, _T_49) @[dec_tlu_ctl.scala 3311:202] + wire mitcnt1_inc1 : UInt<9> + mitcnt1_inc1 <= UInt<1>("h00") + wire mitcnt1_inc2 : UInt<24> + mitcnt1_inc2 <= UInt<1>("h00") + node _T_50 = bits(mitcnt1, 7, 0) @[dec_tlu_ctl.scala 3316:32] + node _T_51 = cat(UInt<7>("h00"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_52 = add(_T_50, _T_51) @[dec_tlu_ctl.scala 3316:38] + node _T_53 = tail(_T_52, 1) @[dec_tlu_ctl.scala 3316:38] + mitcnt1_inc1 <= _T_53 @[dec_tlu_ctl.scala 3316:22] + node mitcnt1_inc_cout = bits(mitcnt1_inc1, 8, 8) @[dec_tlu_ctl.scala 3317:44] + node _T_54 = bits(mitcnt1, 31, 8) @[dec_tlu_ctl.scala 3318:32] + node _T_55 = cat(UInt<23>("h00"), mitcnt1_inc_cout) @[Cat.scala 29:58] + node _T_56 = add(_T_54, _T_55) @[dec_tlu_ctl.scala 3318:39] + node _T_57 = tail(_T_56, 1) @[dec_tlu_ctl.scala 3318:39] + mitcnt1_inc2 <= _T_57 @[dec_tlu_ctl.scala 3318:22] + node _T_58 = bits(mitcnt1_inc1, 7, 0) @[dec_tlu_ctl.scala 3319:56] + node mitcnt1_inc = cat(mitcnt1_inc2, _T_58) @[Cat.scala 29:58] + node _T_59 = bits(wr_mitcnt1_r, 0, 0) @[dec_tlu_ctl.scala 3321:43] + node _T_60 = bits(mit1_match_ns, 0, 0) @[dec_tlu_ctl.scala 3321:90] + node _T_61 = mux(_T_60, UInt<1>("h00"), mitcnt1_inc) @[dec_tlu_ctl.scala 3321:75] + node mitcnt1_ns = mux(_T_59, io.dec_csr_wrdata_r, _T_61) @[dec_tlu_ctl.scala 3321:29] + node _T_62 = bits(mitcnt1_ns, 31, 8) @[dec_tlu_ctl.scala 3323:48] + node _T_63 = and(mitcnt1_inc_ok, mitcnt1_inc_cout) @[dec_tlu_ctl.scala 3323:87] + node _T_64 = or(wr_mitcnt1_r, _T_63) @[dec_tlu_ctl.scala 3323:69] + node _T_65 = or(_T_64, mit1_match_ns) @[dec_tlu_ctl.scala 3323:107] + node _T_66 = bits(_T_65, 0, 0) @[dec_tlu_ctl.scala 3323:124] + inst rvclkhdr_2 of rvclkhdr_91 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_2.io.en <= _T_66 @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_67 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_66 : @[Reg.scala 28:19] + _T_67 <= _T_62 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_68 = bits(mitcnt1_ns, 7, 0) @[dec_tlu_ctl.scala 3324:34] + node _T_69 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[dec_tlu_ctl.scala 3324:54] + node _T_70 = or(_T_69, mit1_match_ns) @[dec_tlu_ctl.scala 3324:71] + node _T_71 = bits(_T_70, 0, 0) @[dec_tlu_ctl.scala 3324:88] + inst rvclkhdr_3 of rvclkhdr_92 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_3.io.en <= _T_71 @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_72 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_71 : @[Reg.scala 28:19] + _T_72 <= _T_68 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_73 = cat(_T_67, _T_72) @[Cat.scala 29:58] + mitcnt1 <= _T_73 @[dec_tlu_ctl.scala 3323:25] + node _T_74 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[dec_tlu_ctl.scala 3333:70] + node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_74) @[dec_tlu_ctl.scala 3333:47] + node _T_75 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 3334:38] + node _T_76 = bits(wr_mitb0_r, 0, 0) @[dec_tlu_ctl.scala 3334:71] + inst rvclkhdr_4 of rvclkhdr_93 @[lib.scala 404:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_4.io.en <= _T_76 @[lib.scala 407:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg mitb0_b : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_76 : @[Reg.scala 28:19] + mitb0_b <= _T_75 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_77 = not(mitb0_b) @[dec_tlu_ctl.scala 3335:22] + mitb0 <= _T_77 @[dec_tlu_ctl.scala 3335:19] + node _T_78 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[dec_tlu_ctl.scala 3342:69] + node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_78) @[dec_tlu_ctl.scala 3342:47] + node _T_79 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 3343:29] + node _T_80 = bits(wr_mitb1_r, 0, 0) @[dec_tlu_ctl.scala 3343:62] + inst rvclkhdr_5 of rvclkhdr_94 @[lib.scala 404:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_5.io.en <= _T_80 @[lib.scala 407:17] + rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg mitb1_b : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_80 : @[Reg.scala 28:19] + mitb1_b <= _T_79 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_81 = not(mitb1_b) @[dec_tlu_ctl.scala 3344:18] + mitb1 <= _T_81 @[dec_tlu_ctl.scala 3344:15] + node _T_82 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[dec_tlu_ctl.scala 3355:72] + node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_82) @[dec_tlu_ctl.scala 3355:49] + node _T_83 = bits(wr_mitctl0_r, 0, 0) @[dec_tlu_ctl.scala 3356:45] + node _T_84 = bits(io.dec_csr_wrdata_r, 2, 0) @[dec_tlu_ctl.scala 3356:72] + node _T_85 = bits(mitctl0, 2, 0) @[dec_tlu_ctl.scala 3356:86] + node mitctl0_ns = mux(_T_83, _T_84, _T_85) @[dec_tlu_ctl.scala 3356:31] + node _T_86 = bits(mitctl0_ns, 0, 0) @[dec_tlu_ctl.scala 3358:41] + node mitctl0_0_b_ns = not(_T_86) @[dec_tlu_ctl.scala 3358:30] + node _T_87 = bits(wr_mitctl0_r, 0, 0) @[lib.scala 8:44] + reg mitctl0_0_b : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_87 : @[Reg.scala 28:19] + mitctl0_0_b <= mitctl0_0_b_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_88 = bits(mitctl0_ns, 2, 1) @[dec_tlu_ctl.scala 3360:82] + node _T_89 = bits(wr_mitctl0_r, 0, 0) @[lib.scala 8:44] + reg _T_90 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_89 : @[Reg.scala 28:19] + _T_90 <= _T_88 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_91 = not(mitctl0_0_b) @[dec_tlu_ctl.scala 3360:107] + node _T_92 = cat(_T_90, _T_91) @[Cat.scala 29:58] + mitctl0 <= _T_92 @[dec_tlu_ctl.scala 3360:31] + node _T_93 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[dec_tlu_ctl.scala 3370:71] + node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_93) @[dec_tlu_ctl.scala 3370:49] + node _T_94 = bits(wr_mitctl1_r, 0, 0) @[dec_tlu_ctl.scala 3371:45] + node _T_95 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 3371:71] + node _T_96 = bits(mitctl1, 3, 0) @[dec_tlu_ctl.scala 3371:85] + node mitctl1_ns = mux(_T_94, _T_95, _T_96) @[dec_tlu_ctl.scala 3371:31] + node _T_97 = bits(mitctl1_ns, 0, 0) @[dec_tlu_ctl.scala 3372:40] + node mitctl1_0_b_ns = not(_T_97) @[dec_tlu_ctl.scala 3372:29] + node _T_98 = bits(wr_mitctl1_r, 0, 0) @[lib.scala 8:44] + reg mitctl1_0_b : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_98 : @[Reg.scala 28:19] + mitctl1_0_b <= mitctl1_0_b_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_99 = bits(mitctl1_ns, 3, 1) @[dec_tlu_ctl.scala 3374:67] + node _T_100 = bits(wr_mitctl1_r, 0, 0) @[lib.scala 8:44] + reg _T_101 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_100 : @[Reg.scala 28:19] + _T_101 <= _T_99 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_102 = not(mitctl1_0_b) @[dec_tlu_ctl.scala 3374:92] + node _T_103 = cat(_T_101, _T_102) @[Cat.scala 29:58] + mitctl1 <= _T_103 @[dec_tlu_ctl.scala 3374:16] + node _T_104 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[dec_tlu_ctl.scala 3376:51] + node _T_105 = or(_T_104, io.csr_mitb1) @[dec_tlu_ctl.scala 3376:68] + node _T_106 = or(_T_105, io.csr_mitb0) @[dec_tlu_ctl.scala 3376:83] + node _T_107 = or(_T_106, io.csr_mitctl0) @[dec_tlu_ctl.scala 3376:98] + node _T_108 = or(_T_107, io.csr_mitctl1) @[dec_tlu_ctl.scala 3376:115] + io.dec_timer_read_d <= _T_108 @[dec_tlu_ctl.scala 3376:33] + node _T_109 = bits(io.csr_mitcnt0, 0, 0) @[dec_tlu_ctl.scala 3378:32] + node _T_110 = bits(mitcnt0, 31, 0) @[dec_tlu_ctl.scala 3378:51] + node _T_111 = bits(io.csr_mitcnt1, 0, 0) @[dec_tlu_ctl.scala 3379:32] + node _T_112 = bits(io.csr_mitb0, 0, 0) @[dec_tlu_ctl.scala 3380:30] + node _T_113 = bits(io.csr_mitb1, 0, 0) @[dec_tlu_ctl.scala 3381:30] + node _T_114 = bits(io.csr_mitctl0, 0, 0) @[dec_tlu_ctl.scala 3382:32] + node _T_115 = mux(UInt<1>("h00"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12] + node _T_116 = cat(_T_115, mitctl0) @[Cat.scala 29:58] + node _T_117 = bits(io.csr_mitctl1, 0, 0) @[dec_tlu_ctl.scala 3383:32] + node _T_118 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] + node _T_119 = cat(_T_118, mitctl1) @[Cat.scala 29:58] + node _T_120 = mux(_T_109, _T_110, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_121 = mux(_T_111, mitcnt1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_122 = mux(_T_112, mitb0, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_123 = mux(_T_113, mitb1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_124 = mux(_T_114, _T_116, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_125 = mux(_T_117, _T_119, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_126 = or(_T_120, _T_121) @[Mux.scala 27:72] + node _T_127 = or(_T_126, _T_122) @[Mux.scala 27:72] + node _T_128 = or(_T_127, _T_123) @[Mux.scala 27:72] + node _T_129 = or(_T_128, _T_124) @[Mux.scala 27:72] + node _T_130 = or(_T_129, _T_125) @[Mux.scala 27:72] + wire _T_131 : UInt<32> @[Mux.scala 27:72] + _T_131 <= _T_130 @[Mux.scala 27:72] + io.dec_timer_rddata_d <= _T_131 @[dec_tlu_ctl.scala 3377:33] + + module dec_decode_csr_read : + input clock : Clock + input reset : AsyncReset + output io : {flip dec_csr_rdaddr_d : UInt<12>, csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_meicpct : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}} + + node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1 = eq(_T, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_3 = eq(_T_2, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_5 = eq(_T_4, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_7 = eq(_T_6, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_9 = and(_T_1, _T_3) @[dec_tlu_ctl.scala 3173:198] + node _T_10 = and(_T_9, _T_5) @[dec_tlu_ctl.scala 3173:198] + node _T_11 = and(_T_10, _T_7) @[dec_tlu_ctl.scala 3173:198] + node _T_12 = and(_T_11, _T_8) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_misa <= _T_12 @[dec_tlu_ctl.scala 3175:57] + node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_17 = eq(_T_16, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_19 = and(_T_13, _T_15) @[dec_tlu_ctl.scala 3173:198] + node _T_20 = and(_T_19, _T_17) @[dec_tlu_ctl.scala 3173:198] + node _T_21 = and(_T_20, _T_18) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mvendorid <= _T_21 @[dec_tlu_ctl.scala 3176:57] + node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_27 = eq(_T_26, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_28 = and(_T_22, _T_24) @[dec_tlu_ctl.scala 3173:198] + node _T_29 = and(_T_28, _T_25) @[dec_tlu_ctl.scala 3173:198] + node _T_30 = and(_T_29, _T_27) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_marchid <= _T_30 @[dec_tlu_ctl.scala 3177:57] + node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_36 = and(_T_31, _T_33) @[dec_tlu_ctl.scala 3173:198] + node _T_37 = and(_T_36, _T_34) @[dec_tlu_ctl.scala 3173:198] + node _T_38 = and(_T_37, _T_35) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mimpid <= _T_38 @[dec_tlu_ctl.scala 3178:57] + node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_41 = eq(_T_40, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_43 = and(_T_39, _T_41) @[dec_tlu_ctl.scala 3173:198] + node _T_44 = and(_T_43, _T_42) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhartid <= _T_44 @[dec_tlu_ctl.scala 3179:57] + node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_46 = eq(_T_45, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_50 = eq(_T_49, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_52 = eq(_T_51, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_54 = eq(_T_53, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_55 = and(_T_46, _T_48) @[dec_tlu_ctl.scala 3173:198] + node _T_56 = and(_T_55, _T_50) @[dec_tlu_ctl.scala 3173:198] + node _T_57 = and(_T_56, _T_52) @[dec_tlu_ctl.scala 3173:198] + node _T_58 = and(_T_57, _T_54) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mstatus <= _T_58 @[dec_tlu_ctl.scala 3180:57] + node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_60 = eq(_T_59, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_62 = eq(_T_61, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_64 = eq(_T_63, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_67 = and(_T_60, _T_62) @[dec_tlu_ctl.scala 3173:198] + node _T_68 = and(_T_67, _T_64) @[dec_tlu_ctl.scala 3173:198] + node _T_69 = and(_T_68, _T_65) @[dec_tlu_ctl.scala 3173:198] + node _T_70 = and(_T_69, _T_66) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mtvec <= _T_70 @[dec_tlu_ctl.scala 3181:57] + node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_72 = eq(_T_71, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_75 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 3173:198] + node _T_76 = and(_T_75, _T_74) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mip <= _T_76 @[dec_tlu_ctl.scala 3182:65] + node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_78 = eq(_T_77, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_80 = eq(_T_79, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_85 = eq(_T_84, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_86 = and(_T_78, _T_80) @[dec_tlu_ctl.scala 3173:198] + node _T_87 = and(_T_86, _T_82) @[dec_tlu_ctl.scala 3173:198] + node _T_88 = and(_T_87, _T_83) @[dec_tlu_ctl.scala 3173:198] + node _T_89 = and(_T_88, _T_85) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mie <= _T_89 @[dec_tlu_ctl.scala 3183:65] + node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_94 = eq(_T_93, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_96 = eq(_T_95, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_100 = eq(_T_99, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_101 = and(_T_90, _T_92) @[dec_tlu_ctl.scala 3173:198] + node _T_102 = and(_T_101, _T_94) @[dec_tlu_ctl.scala 3173:198] + node _T_103 = and(_T_102, _T_96) @[dec_tlu_ctl.scala 3173:198] + node _T_104 = and(_T_103, _T_98) @[dec_tlu_ctl.scala 3173:198] + node _T_105 = and(_T_104, _T_100) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mcyclel <= _T_105 @[dec_tlu_ctl.scala 3184:57] + node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_108 = eq(_T_107, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_110 = eq(_T_109, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_112 = eq(_T_111, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_114 = eq(_T_113, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_116 = eq(_T_115, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_119 = and(_T_106, _T_108) @[dec_tlu_ctl.scala 3173:198] + node _T_120 = and(_T_119, _T_110) @[dec_tlu_ctl.scala 3173:198] + node _T_121 = and(_T_120, _T_112) @[dec_tlu_ctl.scala 3173:198] + node _T_122 = and(_T_121, _T_114) @[dec_tlu_ctl.scala 3173:198] + node _T_123 = and(_T_122, _T_116) @[dec_tlu_ctl.scala 3173:198] + node _T_124 = and(_T_123, _T_118) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mcycleh <= _T_124 @[dec_tlu_ctl.scala 3185:57] + node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_126 = eq(_T_125, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_128 = eq(_T_127, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_130 = eq(_T_129, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_134 = eq(_T_133, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_137 = eq(_T_136, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_138 = and(_T_126, _T_128) @[dec_tlu_ctl.scala 3173:198] + node _T_139 = and(_T_138, _T_130) @[dec_tlu_ctl.scala 3173:198] + node _T_140 = and(_T_139, _T_132) @[dec_tlu_ctl.scala 3173:198] + node _T_141 = and(_T_140, _T_134) @[dec_tlu_ctl.scala 3173:198] + node _T_142 = and(_T_141, _T_135) @[dec_tlu_ctl.scala 3173:198] + node _T_143 = and(_T_142, _T_137) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_minstretl <= _T_143 @[dec_tlu_ctl.scala 3186:57] + node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_145 = eq(_T_144, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_148 = eq(_T_147, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_152 = eq(_T_151, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_155 = eq(_T_154, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_156 = and(_T_145, _T_146) @[dec_tlu_ctl.scala 3173:198] + node _T_157 = and(_T_156, _T_148) @[dec_tlu_ctl.scala 3173:198] + node _T_158 = and(_T_157, _T_150) @[dec_tlu_ctl.scala 3173:198] + node _T_159 = and(_T_158, _T_152) @[dec_tlu_ctl.scala 3173:198] + node _T_160 = and(_T_159, _T_153) @[dec_tlu_ctl.scala 3173:198] + node _T_161 = and(_T_160, _T_155) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_minstreth <= _T_161 @[dec_tlu_ctl.scala 3187:57] + node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_163 = eq(_T_162, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_166 = eq(_T_165, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_170 = eq(_T_169, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_171 = and(_T_163, _T_164) @[dec_tlu_ctl.scala 3173:198] + node _T_172 = and(_T_171, _T_166) @[dec_tlu_ctl.scala 3173:198] + node _T_173 = and(_T_172, _T_168) @[dec_tlu_ctl.scala 3173:198] + node _T_174 = and(_T_173, _T_170) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mscratch <= _T_174 @[dec_tlu_ctl.scala 3188:57] + node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_181 = and(_T_176, _T_177) @[dec_tlu_ctl.scala 3173:198] + node _T_182 = and(_T_181, _T_179) @[dec_tlu_ctl.scala 3173:198] + node _T_183 = and(_T_182, _T_180) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mepc <= _T_183 @[dec_tlu_ctl.scala 3189:57] + node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_185 = eq(_T_184, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_189 = eq(_T_188, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_190 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 3173:198] + node _T_191 = and(_T_190, _T_187) @[dec_tlu_ctl.scala 3173:198] + node _T_192 = and(_T_191, _T_189) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mcause <= _T_192 @[dec_tlu_ctl.scala 3190:57] + node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_196 = and(_T_193, _T_194) @[dec_tlu_ctl.scala 3173:198] + node _T_197 = and(_T_196, _T_195) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mscause <= _T_197 @[dec_tlu_ctl.scala 3191:57] + node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_199 = eq(_T_198, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_203 = and(_T_199, _T_200) @[dec_tlu_ctl.scala 3173:198] + node _T_204 = and(_T_203, _T_201) @[dec_tlu_ctl.scala 3173:198] + node _T_205 = and(_T_204, _T_202) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mtval <= _T_205 @[dec_tlu_ctl.scala 3192:57] + node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_207 = eq(_T_206, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_210 = eq(_T_209, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_212 = eq(_T_211, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_214 = eq(_T_213, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_217 = and(_T_207, _T_208) @[dec_tlu_ctl.scala 3173:198] + node _T_218 = and(_T_217, _T_210) @[dec_tlu_ctl.scala 3173:198] + node _T_219 = and(_T_218, _T_212) @[dec_tlu_ctl.scala 3173:198] + node _T_220 = and(_T_219, _T_214) @[dec_tlu_ctl.scala 3173:198] + node _T_221 = and(_T_220, _T_216) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mrac <= _T_221 @[dec_tlu_ctl.scala 3193:57] + node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_224 = eq(_T_223, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_226 = eq(_T_225, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_229 = eq(_T_228, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_230 = and(_T_222, _T_224) @[dec_tlu_ctl.scala 3173:198] + node _T_231 = and(_T_230, _T_226) @[dec_tlu_ctl.scala 3173:198] + node _T_232 = and(_T_231, _T_227) @[dec_tlu_ctl.scala 3173:198] + node _T_233 = and(_T_232, _T_229) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_dmst <= _T_233 @[dec_tlu_ctl.scala 3194:57] + node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_237 = eq(_T_236, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_240 = and(_T_234, _T_235) @[dec_tlu_ctl.scala 3173:198] + node _T_241 = and(_T_240, _T_237) @[dec_tlu_ctl.scala 3173:198] + node _T_242 = and(_T_241, _T_239) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mdseac <= _T_242 @[dec_tlu_ctl.scala 3195:57] + node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_246 = and(_T_243, _T_244) @[dec_tlu_ctl.scala 3173:198] + node _T_247 = and(_T_246, _T_245) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_meihap <= _T_247 @[dec_tlu_ctl.scala 3196:57] + node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_255 = eq(_T_254, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_258 = and(_T_249, _T_250) @[dec_tlu_ctl.scala 3173:198] + node _T_259 = and(_T_258, _T_251) @[dec_tlu_ctl.scala 3173:198] + node _T_260 = and(_T_259, _T_253) @[dec_tlu_ctl.scala 3173:198] + node _T_261 = and(_T_260, _T_255) @[dec_tlu_ctl.scala 3173:198] + node _T_262 = and(_T_261, _T_257) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_meivt <= _T_262 @[dec_tlu_ctl.scala 3197:57] + node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_266 = eq(_T_265, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_268 = and(_T_263, _T_264) @[dec_tlu_ctl.scala 3173:198] + node _T_269 = and(_T_268, _T_266) @[dec_tlu_ctl.scala 3173:198] + node _T_270 = and(_T_269, _T_267) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_meipt <= _T_270 @[dec_tlu_ctl.scala 3198:57] + node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_274 = and(_T_271, _T_272) @[dec_tlu_ctl.scala 3173:198] + node _T_275 = and(_T_274, _T_273) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_meicurpl <= _T_275 @[dec_tlu_ctl.scala 3199:57] + node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_280 = and(_T_276, _T_277) @[dec_tlu_ctl.scala 3173:198] + node _T_281 = and(_T_280, _T_278) @[dec_tlu_ctl.scala 3173:198] + node _T_282 = and(_T_281, _T_279) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_meicidpl <= _T_282 @[dec_tlu_ctl.scala 3200:57] + node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_285 = eq(_T_284, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_289 = eq(_T_288, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_290 = and(_T_283, _T_285) @[dec_tlu_ctl.scala 3173:198] + node _T_291 = and(_T_290, _T_286) @[dec_tlu_ctl.scala 3173:198] + node _T_292 = and(_T_291, _T_287) @[dec_tlu_ctl.scala 3173:198] + node _T_293 = and(_T_292, _T_289) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_dcsr <= _T_293 @[dec_tlu_ctl.scala 3201:57] + node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_298 = eq(_T_297, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_299 = and(_T_294, _T_295) @[dec_tlu_ctl.scala 3173:198] + node _T_300 = and(_T_299, _T_296) @[dec_tlu_ctl.scala 3173:198] + node _T_301 = and(_T_300, _T_298) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mcgc <= _T_301 @[dec_tlu_ctl.scala 3202:57] + node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_308 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 3173:198] + node _T_309 = and(_T_308, _T_304) @[dec_tlu_ctl.scala 3173:198] + node _T_310 = and(_T_309, _T_306) @[dec_tlu_ctl.scala 3173:198] + node _T_311 = and(_T_310, _T_307) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mfdc <= _T_311 @[dec_tlu_ctl.scala 3203:57] + node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_318 = and(_T_312, _T_314) @[dec_tlu_ctl.scala 3173:198] + node _T_319 = and(_T_318, _T_315) @[dec_tlu_ctl.scala 3173:198] + node _T_320 = and(_T_319, _T_316) @[dec_tlu_ctl.scala 3173:198] + node _T_321 = and(_T_320, _T_317) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_dpc <= _T_321 @[dec_tlu_ctl.scala 3204:65] + node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_325 = eq(_T_324, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_330 = and(_T_322, _T_323) @[dec_tlu_ctl.scala 3173:198] + node _T_331 = and(_T_330, _T_325) @[dec_tlu_ctl.scala 3173:198] + node _T_332 = and(_T_331, _T_327) @[dec_tlu_ctl.scala 3173:198] + node _T_333 = and(_T_332, _T_329) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mtsel <= _T_333 @[dec_tlu_ctl.scala 3205:57] + node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_336 = eq(_T_335, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_340 = and(_T_334, _T_336) @[dec_tlu_ctl.scala 3173:198] + node _T_341 = and(_T_340, _T_338) @[dec_tlu_ctl.scala 3173:198] + node _T_342 = and(_T_341, _T_339) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mtdata1 <= _T_342 @[dec_tlu_ctl.scala 3206:57] + node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_348 = and(_T_343, _T_344) @[dec_tlu_ctl.scala 3173:198] + node _T_349 = and(_T_348, _T_346) @[dec_tlu_ctl.scala 3173:198] + node _T_350 = and(_T_349, _T_347) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mtdata2 <= _T_350 @[dec_tlu_ctl.scala 3207:57] + node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_355 = eq(_T_354, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_359 = eq(_T_358, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_361 = and(_T_351, _T_353) @[dec_tlu_ctl.scala 3173:198] + node _T_362 = and(_T_361, _T_355) @[dec_tlu_ctl.scala 3173:198] + node _T_363 = and(_T_362, _T_357) @[dec_tlu_ctl.scala 3173:198] + node _T_364 = and(_T_363, _T_359) @[dec_tlu_ctl.scala 3173:198] + node _T_365 = and(_T_364, _T_360) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpmc3 <= _T_365 @[dec_tlu_ctl.scala 3208:57] + node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_370 = eq(_T_369, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_372 = eq(_T_371, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_375 = eq(_T_374, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_377 = eq(_T_376, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_378 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 3173:198] + node _T_379 = and(_T_378, _T_370) @[dec_tlu_ctl.scala 3173:198] + node _T_380 = and(_T_379, _T_372) @[dec_tlu_ctl.scala 3173:198] + node _T_381 = and(_T_380, _T_373) @[dec_tlu_ctl.scala 3173:198] + node _T_382 = and(_T_381, _T_375) @[dec_tlu_ctl.scala 3173:198] + node _T_383 = and(_T_382, _T_377) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpmc4 <= _T_383 @[dec_tlu_ctl.scala 3209:57] + node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_388 = eq(_T_387, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_390 = eq(_T_389, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_394 = and(_T_384, _T_386) @[dec_tlu_ctl.scala 3173:198] + node _T_395 = and(_T_394, _T_388) @[dec_tlu_ctl.scala 3173:198] + node _T_396 = and(_T_395, _T_390) @[dec_tlu_ctl.scala 3173:198] + node _T_397 = and(_T_396, _T_392) @[dec_tlu_ctl.scala 3173:198] + node _T_398 = and(_T_397, _T_393) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpmc5 <= _T_398 @[dec_tlu_ctl.scala 3210:57] + node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_402 = eq(_T_401, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_404 = eq(_T_403, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_406 = eq(_T_405, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_410 = eq(_T_409, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_411 = and(_T_400, _T_402) @[dec_tlu_ctl.scala 3173:198] + node _T_412 = and(_T_411, _T_404) @[dec_tlu_ctl.scala 3173:198] + node _T_413 = and(_T_412, _T_406) @[dec_tlu_ctl.scala 3173:198] + node _T_414 = and(_T_413, _T_407) @[dec_tlu_ctl.scala 3173:198] + node _T_415 = and(_T_414, _T_408) @[dec_tlu_ctl.scala 3173:198] + node _T_416 = and(_T_415, _T_410) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpmc6 <= _T_416 @[dec_tlu_ctl.scala 3211:57] + node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_421 = eq(_T_420, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_426 = and(_T_417, _T_419) @[dec_tlu_ctl.scala 3173:198] + node _T_427 = and(_T_426, _T_421) @[dec_tlu_ctl.scala 3173:198] + node _T_428 = and(_T_427, _T_423) @[dec_tlu_ctl.scala 3173:198] + node _T_429 = and(_T_428, _T_424) @[dec_tlu_ctl.scala 3173:198] + node _T_430 = and(_T_429, _T_425) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpmc3h <= _T_430 @[dec_tlu_ctl.scala 3212:57] + node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_433 = eq(_T_432, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_440 = eq(_T_439, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_442 = eq(_T_441, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_443 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 3173:198] + node _T_444 = and(_T_443, _T_435) @[dec_tlu_ctl.scala 3173:198] + node _T_445 = and(_T_444, _T_437) @[dec_tlu_ctl.scala 3173:198] + node _T_446 = and(_T_445, _T_438) @[dec_tlu_ctl.scala 3173:198] + node _T_447 = and(_T_446, _T_440) @[dec_tlu_ctl.scala 3173:198] + node _T_448 = and(_T_447, _T_442) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpmc4h <= _T_448 @[dec_tlu_ctl.scala 3213:57] + node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_453 = eq(_T_452, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_458 = and(_T_449, _T_451) @[dec_tlu_ctl.scala 3173:198] + node _T_459 = and(_T_458, _T_453) @[dec_tlu_ctl.scala 3173:198] + node _T_460 = and(_T_459, _T_454) @[dec_tlu_ctl.scala 3173:198] + node _T_461 = and(_T_460, _T_456) @[dec_tlu_ctl.scala 3173:198] + node _T_462 = and(_T_461, _T_457) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpmc5h <= _T_462 @[dec_tlu_ctl.scala 3214:57] + node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_465 = eq(_T_464, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_473 = eq(_T_472, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_474 = and(_T_463, _T_465) @[dec_tlu_ctl.scala 3173:198] + node _T_475 = and(_T_474, _T_467) @[dec_tlu_ctl.scala 3173:198] + node _T_476 = and(_T_475, _T_469) @[dec_tlu_ctl.scala 3173:198] + node _T_477 = and(_T_476, _T_470) @[dec_tlu_ctl.scala 3173:198] + node _T_478 = and(_T_477, _T_471) @[dec_tlu_ctl.scala 3173:198] + node _T_479 = and(_T_478, _T_473) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpmc6h <= _T_479 @[dec_tlu_ctl.scala 3215:57] + node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_490 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 3173:198] + node _T_491 = and(_T_490, _T_484) @[dec_tlu_ctl.scala 3173:198] + node _T_492 = and(_T_491, _T_486) @[dec_tlu_ctl.scala 3173:198] + node _T_493 = and(_T_492, _T_488) @[dec_tlu_ctl.scala 3173:198] + node _T_494 = and(_T_493, _T_489) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpme3 <= _T_494 @[dec_tlu_ctl.scala 3216:57] + node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_499 = eq(_T_498, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_504 = eq(_T_503, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_505 = and(_T_495, _T_497) @[dec_tlu_ctl.scala 3173:198] + node _T_506 = and(_T_505, _T_499) @[dec_tlu_ctl.scala 3173:198] + node _T_507 = and(_T_506, _T_500) @[dec_tlu_ctl.scala 3173:198] + node _T_508 = and(_T_507, _T_502) @[dec_tlu_ctl.scala 3173:198] + node _T_509 = and(_T_508, _T_504) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpme4 <= _T_509 @[dec_tlu_ctl.scala 3217:57] + node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_512 = eq(_T_511, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_514 = eq(_T_513, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_517 = eq(_T_516, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_519 = and(_T_510, _T_512) @[dec_tlu_ctl.scala 3173:198] + node _T_520 = and(_T_519, _T_514) @[dec_tlu_ctl.scala 3173:198] + node _T_521 = and(_T_520, _T_515) @[dec_tlu_ctl.scala 3173:198] + node _T_522 = and(_T_521, _T_517) @[dec_tlu_ctl.scala 3173:198] + node _T_523 = and(_T_522, _T_518) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpme5 <= _T_523 @[dec_tlu_ctl.scala 3218:57] + node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_526 = eq(_T_525, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_528 = eq(_T_527, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_533 = and(_T_524, _T_526) @[dec_tlu_ctl.scala 3173:198] + node _T_534 = and(_T_533, _T_528) @[dec_tlu_ctl.scala 3173:198] + node _T_535 = and(_T_534, _T_529) @[dec_tlu_ctl.scala 3173:198] + node _T_536 = and(_T_535, _T_530) @[dec_tlu_ctl.scala 3173:198] + node _T_537 = and(_T_536, _T_532) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpme6 <= _T_537 @[dec_tlu_ctl.scala 3219:57] + node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_539 = eq(_T_538, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_542 = eq(_T_541, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_544 = eq(_T_543, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_546 = eq(_T_545, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_548 = eq(_T_547, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_549 = and(_T_539, _T_540) @[dec_tlu_ctl.scala 3173:198] + node _T_550 = and(_T_549, _T_542) @[dec_tlu_ctl.scala 3173:198] + node _T_551 = and(_T_550, _T_544) @[dec_tlu_ctl.scala 3173:198] + node _T_552 = and(_T_551, _T_546) @[dec_tlu_ctl.scala 3173:198] + node _T_553 = and(_T_552, _T_548) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mcountinhibit <= _T_553 @[dec_tlu_ctl.scala 3220:49] + node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_556 = eq(_T_555, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_561 = eq(_T_560, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_562 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 3173:198] + node _T_563 = and(_T_562, _T_557) @[dec_tlu_ctl.scala 3173:198] + node _T_564 = and(_T_563, _T_559) @[dec_tlu_ctl.scala 3173:198] + node _T_565 = and(_T_564, _T_561) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mitctl0 <= _T_565 @[dec_tlu_ctl.scala 3221:57] + node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_568 = eq(_T_567, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_572 = and(_T_566, _T_568) @[dec_tlu_ctl.scala 3173:198] + node _T_573 = and(_T_572, _T_569) @[dec_tlu_ctl.scala 3173:198] + node _T_574 = and(_T_573, _T_570) @[dec_tlu_ctl.scala 3173:198] + node _T_575 = and(_T_574, _T_571) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mitctl1 <= _T_575 @[dec_tlu_ctl.scala 3222:57] + node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_578 = eq(_T_577, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_581 = eq(_T_580, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_583 = and(_T_576, _T_578) @[dec_tlu_ctl.scala 3173:198] + node _T_584 = and(_T_583, _T_579) @[dec_tlu_ctl.scala 3173:198] + node _T_585 = and(_T_584, _T_581) @[dec_tlu_ctl.scala 3173:198] + node _T_586 = and(_T_585, _T_582) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mitb0 <= _T_586 @[dec_tlu_ctl.scala 3223:57] + node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_592 = eq(_T_591, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_593 = and(_T_587, _T_588) @[dec_tlu_ctl.scala 3173:198] + node _T_594 = and(_T_593, _T_589) @[dec_tlu_ctl.scala 3173:198] + node _T_595 = and(_T_594, _T_590) @[dec_tlu_ctl.scala 3173:198] + node _T_596 = and(_T_595, _T_592) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mitb1 <= _T_596 @[dec_tlu_ctl.scala 3224:57] + node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_599 = eq(_T_598, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_602 = eq(_T_601, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_605 = and(_T_597, _T_599) @[dec_tlu_ctl.scala 3173:198] + node _T_606 = and(_T_605, _T_600) @[dec_tlu_ctl.scala 3173:198] + node _T_607 = and(_T_606, _T_602) @[dec_tlu_ctl.scala 3173:198] + node _T_608 = and(_T_607, _T_604) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mitcnt0 <= _T_608 @[dec_tlu_ctl.scala 3225:57] + node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_612 = eq(_T_611, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_614 = and(_T_609, _T_610) @[dec_tlu_ctl.scala 3173:198] + node _T_615 = and(_T_614, _T_612) @[dec_tlu_ctl.scala 3173:198] + node _T_616 = and(_T_615, _T_613) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mitcnt1 <= _T_616 @[dec_tlu_ctl.scala 3226:57] + node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_619 = eq(_T_618, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_621 = eq(_T_620, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_624 = and(_T_617, _T_619) @[dec_tlu_ctl.scala 3173:198] + node _T_625 = and(_T_624, _T_621) @[dec_tlu_ctl.scala 3173:198] + node _T_626 = and(_T_625, _T_622) @[dec_tlu_ctl.scala 3173:198] + node _T_627 = and(_T_626, _T_623) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mpmc <= _T_627 @[dec_tlu_ctl.scala 3227:57] + node _T_628 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_630 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_631 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_632 = eq(_T_631, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_633 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 3173:198] + node _T_634 = and(_T_633, _T_630) @[dec_tlu_ctl.scala 3173:198] + node _T_635 = and(_T_634, _T_632) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_meicpct <= _T_635 @[dec_tlu_ctl.scala 3229:57] + node _T_636 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_637 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_638 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_639 = eq(_T_638, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_640 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_641 = eq(_T_640, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_642 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_643 = eq(_T_642, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_644 = and(_T_636, _T_637) @[dec_tlu_ctl.scala 3173:198] + node _T_645 = and(_T_644, _T_639) @[dec_tlu_ctl.scala 3173:198] + node _T_646 = and(_T_645, _T_641) @[dec_tlu_ctl.scala 3173:198] + node _T_647 = and(_T_646, _T_643) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_micect <= _T_647 @[dec_tlu_ctl.scala 3231:57] + node _T_648 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_649 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_650 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_651 = eq(_T_650, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_652 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_653 = and(_T_648, _T_649) @[dec_tlu_ctl.scala 3173:198] + node _T_654 = and(_T_653, _T_651) @[dec_tlu_ctl.scala 3173:198] + node _T_655 = and(_T_654, _T_652) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_miccmect <= _T_655 @[dec_tlu_ctl.scala 3232:57] + node _T_656 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_657 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_658 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_659 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_660 = eq(_T_659, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_661 = and(_T_656, _T_657) @[dec_tlu_ctl.scala 3173:198] + node _T_662 = and(_T_661, _T_658) @[dec_tlu_ctl.scala 3173:198] + node _T_663 = and(_T_662, _T_660) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mdccmect <= _T_663 @[dec_tlu_ctl.scala 3233:57] + node _T_664 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_665 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_666 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_667 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_668 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_669 = eq(_T_668, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_670 = and(_T_664, _T_665) @[dec_tlu_ctl.scala 3173:198] + node _T_671 = and(_T_670, _T_666) @[dec_tlu_ctl.scala 3173:198] + node _T_672 = and(_T_671, _T_667) @[dec_tlu_ctl.scala 3173:198] + node _T_673 = and(_T_672, _T_669) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mfdht <= _T_673 @[dec_tlu_ctl.scala 3234:57] + node _T_674 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_675 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_676 = eq(_T_675, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_677 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_678 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_679 = and(_T_674, _T_676) @[dec_tlu_ctl.scala 3173:198] + node _T_680 = and(_T_679, _T_677) @[dec_tlu_ctl.scala 3173:198] + node _T_681 = and(_T_680, _T_678) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mfdhs <= _T_681 @[dec_tlu_ctl.scala 3235:57] + node _T_682 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_683 = eq(_T_682, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_684 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_685 = eq(_T_684, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_686 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_687 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_688 = eq(_T_687, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_689 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_690 = eq(_T_689, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_692 = eq(_T_691, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_693 = and(_T_683, _T_685) @[dec_tlu_ctl.scala 3173:198] + node _T_694 = and(_T_693, _T_686) @[dec_tlu_ctl.scala 3173:198] + node _T_695 = and(_T_694, _T_688) @[dec_tlu_ctl.scala 3173:198] + node _T_696 = and(_T_695, _T_690) @[dec_tlu_ctl.scala 3173:198] + node _T_697 = and(_T_696, _T_692) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_dicawics <= _T_697 @[dec_tlu_ctl.scala 3236:57] + node _T_698 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_699 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_701 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_702 = eq(_T_701, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_703 = and(_T_698, _T_699) @[dec_tlu_ctl.scala 3173:198] + node _T_704 = and(_T_703, _T_700) @[dec_tlu_ctl.scala 3173:198] + node _T_705 = and(_T_704, _T_702) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_dicad0h <= _T_705 @[dec_tlu_ctl.scala 3237:57] + node _T_706 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_707 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_708 = eq(_T_707, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_710 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_711 = eq(_T_710, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_712 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_713 = and(_T_706, _T_708) @[dec_tlu_ctl.scala 3173:198] + node _T_714 = and(_T_713, _T_709) @[dec_tlu_ctl.scala 3173:198] + node _T_715 = and(_T_714, _T_711) @[dec_tlu_ctl.scala 3173:198] + node _T_716 = and(_T_715, _T_712) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_dicad0 <= _T_716 @[dec_tlu_ctl.scala 3238:57] + node _T_717 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_718 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_719 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_720 = eq(_T_719, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_721 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_722 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_723 = eq(_T_722, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_724 = and(_T_717, _T_718) @[dec_tlu_ctl.scala 3173:198] + node _T_725 = and(_T_724, _T_720) @[dec_tlu_ctl.scala 3173:198] + node _T_726 = and(_T_725, _T_721) @[dec_tlu_ctl.scala 3173:198] + node _T_727 = and(_T_726, _T_723) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_dicad1 <= _T_727 @[dec_tlu_ctl.scala 3239:57] + node _T_728 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_729 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_730 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_731 = eq(_T_730, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_732 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_733 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_734 = and(_T_728, _T_729) @[dec_tlu_ctl.scala 3173:198] + node _T_735 = and(_T_734, _T_731) @[dec_tlu_ctl.scala 3173:198] + node _T_736 = and(_T_735, _T_732) @[dec_tlu_ctl.scala 3173:198] + node _T_737 = and(_T_736, _T_733) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_dicago <= _T_737 @[dec_tlu_ctl.scala 3240:57] + node _T_738 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_739 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_740 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_741 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_742 = eq(_T_741, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_743 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_744 = and(_T_738, _T_739) @[dec_tlu_ctl.scala 3173:198] + node _T_745 = and(_T_744, _T_740) @[dec_tlu_ctl.scala 3173:198] + node _T_746 = and(_T_745, _T_742) @[dec_tlu_ctl.scala 3173:198] + node _T_747 = and(_T_746, _T_743) @[dec_tlu_ctl.scala 3173:198] + node _T_748 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_749 = eq(_T_748, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_750 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_751 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_752 = eq(_T_751, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_753 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_754 = eq(_T_753, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_755 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_756 = eq(_T_755, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_757 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_758 = eq(_T_757, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_759 = and(_T_749, _T_750) @[dec_tlu_ctl.scala 3173:198] + node _T_760 = and(_T_759, _T_752) @[dec_tlu_ctl.scala 3173:198] + node _T_761 = and(_T_760, _T_754) @[dec_tlu_ctl.scala 3173:198] + node _T_762 = and(_T_761, _T_756) @[dec_tlu_ctl.scala 3173:198] + node _T_763 = and(_T_762, _T_758) @[dec_tlu_ctl.scala 3173:198] + node _T_764 = or(_T_747, _T_763) @[dec_tlu_ctl.scala 3241:81] + node _T_765 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_766 = eq(_T_765, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_767 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_768 = eq(_T_767, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_769 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_770 = eq(_T_769, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_771 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_773 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_774 = eq(_T_773, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_775 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_776 = and(_T_766, _T_768) @[dec_tlu_ctl.scala 3173:198] + node _T_777 = and(_T_776, _T_770) @[dec_tlu_ctl.scala 3173:198] + node _T_778 = and(_T_777, _T_772) @[dec_tlu_ctl.scala 3173:198] + node _T_779 = and(_T_778, _T_774) @[dec_tlu_ctl.scala 3173:198] + node _T_780 = and(_T_779, _T_775) @[dec_tlu_ctl.scala 3173:198] + node _T_781 = or(_T_764, _T_780) @[dec_tlu_ctl.scala 3241:121] + node _T_782 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_783 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_784 = eq(_T_783, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_785 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_786 = eq(_T_785, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_787 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_788 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_789 = eq(_T_788, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_790 = and(_T_782, _T_784) @[dec_tlu_ctl.scala 3173:198] + node _T_791 = and(_T_790, _T_786) @[dec_tlu_ctl.scala 3173:198] + node _T_792 = and(_T_791, _T_787) @[dec_tlu_ctl.scala 3173:198] + node _T_793 = and(_T_792, _T_789) @[dec_tlu_ctl.scala 3173:198] + node _T_794 = or(_T_781, _T_793) @[dec_tlu_ctl.scala 3241:155] + node _T_795 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_796 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_797 = eq(_T_796, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_798 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_799 = eq(_T_798, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_800 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_801 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_802 = eq(_T_801, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_803 = and(_T_795, _T_797) @[dec_tlu_ctl.scala 3173:198] + node _T_804 = and(_T_803, _T_799) @[dec_tlu_ctl.scala 3173:198] + node _T_805 = and(_T_804, _T_800) @[dec_tlu_ctl.scala 3173:198] + node _T_806 = and(_T_805, _T_802) @[dec_tlu_ctl.scala 3173:198] + node _T_807 = or(_T_794, _T_806) @[dec_tlu_ctl.scala 3242:49] + node _T_808 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_809 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_810 = eq(_T_809, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_811 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_813 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_814 = eq(_T_813, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_815 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_816 = eq(_T_815, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_817 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_818 = and(_T_808, _T_810) @[dec_tlu_ctl.scala 3173:198] + node _T_819 = and(_T_818, _T_812) @[dec_tlu_ctl.scala 3173:198] + node _T_820 = and(_T_819, _T_814) @[dec_tlu_ctl.scala 3173:198] + node _T_821 = and(_T_820, _T_816) @[dec_tlu_ctl.scala 3173:198] + node _T_822 = and(_T_821, _T_817) @[dec_tlu_ctl.scala 3173:198] + node _T_823 = or(_T_807, _T_822) @[dec_tlu_ctl.scala 3242:89] + io.csr_pkt.presync <= _T_823 @[dec_tlu_ctl.scala 3241:34] + node _T_824 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_825 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_826 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_827 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_828 = eq(_T_827, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_829 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_830 = and(_T_824, _T_825) @[dec_tlu_ctl.scala 3173:198] + node _T_831 = and(_T_830, _T_826) @[dec_tlu_ctl.scala 3173:198] + node _T_832 = and(_T_831, _T_828) @[dec_tlu_ctl.scala 3173:198] + node _T_833 = and(_T_832, _T_829) @[dec_tlu_ctl.scala 3173:198] + node _T_834 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_835 = eq(_T_834, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_836 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_837 = eq(_T_836, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_838 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_840 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_841 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_842 = and(_T_835, _T_837) @[dec_tlu_ctl.scala 3173:198] + node _T_843 = and(_T_842, _T_839) @[dec_tlu_ctl.scala 3173:198] + node _T_844 = and(_T_843, _T_840) @[dec_tlu_ctl.scala 3173:198] + node _T_845 = and(_T_844, _T_841) @[dec_tlu_ctl.scala 3173:198] + node _T_846 = or(_T_833, _T_845) @[dec_tlu_ctl.scala 3243:81] + node _T_847 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_848 = eq(_T_847, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_849 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_851 = eq(_T_850, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_853 = and(_T_848, _T_849) @[dec_tlu_ctl.scala 3173:198] + node _T_854 = and(_T_853, _T_851) @[dec_tlu_ctl.scala 3173:198] + node _T_855 = and(_T_854, _T_852) @[dec_tlu_ctl.scala 3173:198] + node _T_856 = or(_T_846, _T_855) @[dec_tlu_ctl.scala 3243:121] + node _T_857 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_858 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_859 = eq(_T_858, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_860 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_861 = eq(_T_860, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_862 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_863 = and(_T_857, _T_859) @[dec_tlu_ctl.scala 3173:198] + node _T_864 = and(_T_863, _T_861) @[dec_tlu_ctl.scala 3173:198] + node _T_865 = and(_T_864, _T_862) @[dec_tlu_ctl.scala 3173:198] + node _T_866 = or(_T_856, _T_865) @[dec_tlu_ctl.scala 3243:162] + node _T_867 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_868 = eq(_T_867, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_869 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_870 = eq(_T_869, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_871 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_872 = eq(_T_871, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_873 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_874 = eq(_T_873, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_875 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_876 = eq(_T_875, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_877 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_878 = eq(_T_877, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_879 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_880 = eq(_T_879, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_881 = and(_T_868, _T_870) @[dec_tlu_ctl.scala 3173:198] + node _T_882 = and(_T_881, _T_872) @[dec_tlu_ctl.scala 3173:198] + node _T_883 = and(_T_882, _T_874) @[dec_tlu_ctl.scala 3173:198] + node _T_884 = and(_T_883, _T_876) @[dec_tlu_ctl.scala 3173:198] + node _T_885 = and(_T_884, _T_878) @[dec_tlu_ctl.scala 3173:198] + node _T_886 = and(_T_885, _T_880) @[dec_tlu_ctl.scala 3173:198] + node _T_887 = or(_T_866, _T_886) @[dec_tlu_ctl.scala 3244:57] + node _T_888 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_889 = eq(_T_888, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_890 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_891 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_892 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_893 = eq(_T_892, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_894 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_896 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_897 = eq(_T_896, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_898 = and(_T_889, _T_890) @[dec_tlu_ctl.scala 3173:198] + node _T_899 = and(_T_898, _T_891) @[dec_tlu_ctl.scala 3173:198] + node _T_900 = and(_T_899, _T_893) @[dec_tlu_ctl.scala 3173:198] + node _T_901 = and(_T_900, _T_895) @[dec_tlu_ctl.scala 3173:198] + node _T_902 = and(_T_901, _T_897) @[dec_tlu_ctl.scala 3173:198] + node _T_903 = or(_T_887, _T_902) @[dec_tlu_ctl.scala 3244:97] + node _T_904 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_905 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_906 = eq(_T_905, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_907 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_908 = eq(_T_907, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_909 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_910 = eq(_T_909, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_911 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_912 = and(_T_904, _T_906) @[dec_tlu_ctl.scala 3173:198] + node _T_913 = and(_T_912, _T_908) @[dec_tlu_ctl.scala 3173:198] + node _T_914 = and(_T_913, _T_910) @[dec_tlu_ctl.scala 3173:198] + node _T_915 = and(_T_914, _T_911) @[dec_tlu_ctl.scala 3173:198] + node _T_916 = or(_T_903, _T_915) @[dec_tlu_ctl.scala 3244:130] + io.csr_pkt.postsync <= _T_916 @[dec_tlu_ctl.scala 3243:30] + node _T_917 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_918 = eq(_T_917, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_919 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_920 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_921 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_922 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_923 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_924 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_925 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_926 = eq(_T_925, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_927 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_928 = eq(_T_927, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_929 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_930 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_931 = eq(_T_930, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_932 = and(_T_918, _T_919) @[dec_tlu_ctl.scala 3173:198] + node _T_933 = and(_T_932, _T_920) @[dec_tlu_ctl.scala 3173:198] + node _T_934 = and(_T_933, _T_921) @[dec_tlu_ctl.scala 3173:198] + node _T_935 = and(_T_934, _T_922) @[dec_tlu_ctl.scala 3173:198] + node _T_936 = and(_T_935, _T_923) @[dec_tlu_ctl.scala 3173:198] + node _T_937 = and(_T_936, _T_924) @[dec_tlu_ctl.scala 3173:198] + node _T_938 = and(_T_937, _T_926) @[dec_tlu_ctl.scala 3173:198] + node _T_939 = and(_T_938, _T_928) @[dec_tlu_ctl.scala 3173:198] + node _T_940 = and(_T_939, _T_929) @[dec_tlu_ctl.scala 3173:198] + node _T_941 = and(_T_940, _T_931) @[dec_tlu_ctl.scala 3173:198] + node _T_942 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_943 = eq(_T_942, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_944 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_945 = eq(_T_944, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_946 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_947 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_948 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_950 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_951 = eq(_T_950, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_952 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_953 = eq(_T_952, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_954 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_955 = eq(_T_954, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_956 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_957 = eq(_T_956, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_958 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_959 = eq(_T_958, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_960 = and(_T_943, _T_945) @[dec_tlu_ctl.scala 3173:198] + node _T_961 = and(_T_960, _T_946) @[dec_tlu_ctl.scala 3173:198] + node _T_962 = and(_T_961, _T_947) @[dec_tlu_ctl.scala 3173:198] + node _T_963 = and(_T_962, _T_949) @[dec_tlu_ctl.scala 3173:198] + node _T_964 = and(_T_963, _T_951) @[dec_tlu_ctl.scala 3173:198] + node _T_965 = and(_T_964, _T_953) @[dec_tlu_ctl.scala 3173:198] + node _T_966 = and(_T_965, _T_955) @[dec_tlu_ctl.scala 3173:198] + node _T_967 = and(_T_966, _T_957) @[dec_tlu_ctl.scala 3173:198] + node _T_968 = and(_T_967, _T_959) @[dec_tlu_ctl.scala 3173:198] + node _T_969 = or(_T_941, _T_968) @[dec_tlu_ctl.scala 3246:81] + node _T_970 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_971 = eq(_T_970, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_972 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_973 = eq(_T_972, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_974 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_975 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_976 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_977 = eq(_T_976, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_978 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_979 = eq(_T_978, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_980 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_983 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_984 = eq(_T_983, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_985 = and(_T_971, _T_973) @[dec_tlu_ctl.scala 3173:198] + node _T_986 = and(_T_985, _T_974) @[dec_tlu_ctl.scala 3173:198] + node _T_987 = and(_T_986, _T_975) @[dec_tlu_ctl.scala 3173:198] + node _T_988 = and(_T_987, _T_977) @[dec_tlu_ctl.scala 3173:198] + node _T_989 = and(_T_988, _T_979) @[dec_tlu_ctl.scala 3173:198] + node _T_990 = and(_T_989, _T_980) @[dec_tlu_ctl.scala 3173:198] + node _T_991 = and(_T_990, _T_982) @[dec_tlu_ctl.scala 3173:198] + node _T_992 = and(_T_991, _T_984) @[dec_tlu_ctl.scala 3173:198] + node _T_993 = or(_T_969, _T_992) @[dec_tlu_ctl.scala 3246:129] + node _T_994 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_995 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_996 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_997 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_998 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_999 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1000 = eq(_T_999, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1001 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1003 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_1004 = eq(_T_1003, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1005 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_1006 = eq(_T_1005, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1007 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_1008 = eq(_T_1007, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_1009 = and(_T_994, _T_995) @[dec_tlu_ctl.scala 3173:198] + node _T_1010 = and(_T_1009, _T_996) @[dec_tlu_ctl.scala 3173:198] + node _T_1011 = and(_T_1010, _T_997) @[dec_tlu_ctl.scala 3173:198] + node _T_1012 = and(_T_1011, _T_998) @[dec_tlu_ctl.scala 3173:198] + node _T_1013 = and(_T_1012, _T_1000) @[dec_tlu_ctl.scala 3173:198] + node _T_1014 = and(_T_1013, _T_1002) @[dec_tlu_ctl.scala 3173:198] + node _T_1015 = and(_T_1014, _T_1004) @[dec_tlu_ctl.scala 3173:198] + node _T_1016 = and(_T_1015, _T_1006) @[dec_tlu_ctl.scala 3173:198] + node _T_1017 = and(_T_1016, _T_1008) @[dec_tlu_ctl.scala 3173:198] + node _T_1018 = or(_T_993, _T_1017) @[dec_tlu_ctl.scala 3247:73] + node _T_1019 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1020 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1021 = eq(_T_1020, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1022 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1023 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1024 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1026 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1028 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_1030 = and(_T_1019, _T_1021) @[dec_tlu_ctl.scala 3173:198] + node _T_1031 = and(_T_1030, _T_1022) @[dec_tlu_ctl.scala 3173:198] + node _T_1032 = and(_T_1031, _T_1023) @[dec_tlu_ctl.scala 3173:198] + node _T_1033 = and(_T_1032, _T_1025) @[dec_tlu_ctl.scala 3173:198] + node _T_1034 = and(_T_1033, _T_1027) @[dec_tlu_ctl.scala 3173:198] + node _T_1035 = and(_T_1034, _T_1029) @[dec_tlu_ctl.scala 3173:198] + node _T_1036 = or(_T_1018, _T_1035) @[dec_tlu_ctl.scala 3247:121] + node _T_1037 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1038 = eq(_T_1037, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1039 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_1040 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1041 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1042 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1043 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_1044 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_1045 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_1046 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_1047 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_1048 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_1049 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_1050 = and(_T_1038, _T_1039) @[dec_tlu_ctl.scala 3173:198] + node _T_1051 = and(_T_1050, _T_1040) @[dec_tlu_ctl.scala 3173:198] + node _T_1052 = and(_T_1051, _T_1041) @[dec_tlu_ctl.scala 3173:198] + node _T_1053 = and(_T_1052, _T_1042) @[dec_tlu_ctl.scala 3173:198] + node _T_1054 = and(_T_1053, _T_1043) @[dec_tlu_ctl.scala 3173:198] + node _T_1055 = and(_T_1054, _T_1044) @[dec_tlu_ctl.scala 3173:198] + node _T_1056 = and(_T_1055, _T_1045) @[dec_tlu_ctl.scala 3173:198] + node _T_1057 = and(_T_1056, _T_1046) @[dec_tlu_ctl.scala 3173:198] + node _T_1058 = and(_T_1057, _T_1047) @[dec_tlu_ctl.scala 3173:198] + node _T_1059 = and(_T_1058, _T_1048) @[dec_tlu_ctl.scala 3173:198] + node _T_1060 = and(_T_1059, _T_1049) @[dec_tlu_ctl.scala 3173:198] + node _T_1061 = or(_T_1036, _T_1060) @[dec_tlu_ctl.scala 3248:73] + node _T_1062 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1063 = eq(_T_1062, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1064 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_1065 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1066 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1067 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1068 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_1069 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_1070 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_1071 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_1072 = eq(_T_1071, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1073 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_1074 = eq(_T_1073, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1075 = and(_T_1063, _T_1064) @[dec_tlu_ctl.scala 3173:198] + node _T_1076 = and(_T_1075, _T_1065) @[dec_tlu_ctl.scala 3173:198] + node _T_1077 = and(_T_1076, _T_1066) @[dec_tlu_ctl.scala 3173:198] + node _T_1078 = and(_T_1077, _T_1067) @[dec_tlu_ctl.scala 3173:198] + node _T_1079 = and(_T_1078, _T_1068) @[dec_tlu_ctl.scala 3173:198] + node _T_1080 = and(_T_1079, _T_1069) @[dec_tlu_ctl.scala 3173:198] + node _T_1081 = and(_T_1080, _T_1070) @[dec_tlu_ctl.scala 3173:198] + node _T_1082 = and(_T_1081, _T_1072) @[dec_tlu_ctl.scala 3173:198] + node _T_1083 = and(_T_1082, _T_1074) @[dec_tlu_ctl.scala 3173:198] + node _T_1084 = or(_T_1061, _T_1083) @[dec_tlu_ctl.scala 3248:121] + node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1086 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1087 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1088 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_1089 = eq(_T_1088, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1090 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1091 = eq(_T_1090, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1094 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_1095 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_1096 = eq(_T_1095, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1097 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_1098 = eq(_T_1097, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1099 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_1100 = and(_T_1085, _T_1086) @[dec_tlu_ctl.scala 3173:198] + node _T_1101 = and(_T_1100, _T_1087) @[dec_tlu_ctl.scala 3173:198] + node _T_1102 = and(_T_1101, _T_1089) @[dec_tlu_ctl.scala 3173:198] + node _T_1103 = and(_T_1102, _T_1091) @[dec_tlu_ctl.scala 3173:198] + node _T_1104 = and(_T_1103, _T_1093) @[dec_tlu_ctl.scala 3173:198] + node _T_1105 = and(_T_1104, _T_1094) @[dec_tlu_ctl.scala 3173:198] + node _T_1106 = and(_T_1105, _T_1096) @[dec_tlu_ctl.scala 3173:198] + node _T_1107 = and(_T_1106, _T_1098) @[dec_tlu_ctl.scala 3173:198] + node _T_1108 = and(_T_1107, _T_1099) @[dec_tlu_ctl.scala 3173:198] + node _T_1109 = or(_T_1084, _T_1108) @[dec_tlu_ctl.scala 3249:73] + node _T_1110 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1111 = eq(_T_1110, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1112 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_1113 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1114 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1115 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1116 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1117 = eq(_T_1116, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1118 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_1119 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_1120 = eq(_T_1119, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1121 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_1122 = eq(_T_1121, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1123 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_1124 = eq(_T_1123, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1125 = and(_T_1111, _T_1112) @[dec_tlu_ctl.scala 3173:198] + node _T_1126 = and(_T_1125, _T_1113) @[dec_tlu_ctl.scala 3173:198] + node _T_1127 = and(_T_1126, _T_1114) @[dec_tlu_ctl.scala 3173:198] + node _T_1128 = and(_T_1127, _T_1115) @[dec_tlu_ctl.scala 3173:198] + node _T_1129 = and(_T_1128, _T_1117) @[dec_tlu_ctl.scala 3173:198] + node _T_1130 = and(_T_1129, _T_1118) @[dec_tlu_ctl.scala 3173:198] + node _T_1131 = and(_T_1130, _T_1120) @[dec_tlu_ctl.scala 3173:198] + node _T_1132 = and(_T_1131, _T_1122) @[dec_tlu_ctl.scala 3173:198] + node _T_1133 = and(_T_1132, _T_1124) @[dec_tlu_ctl.scala 3173:198] + node _T_1134 = or(_T_1109, _T_1133) @[dec_tlu_ctl.scala 3249:129] + node _T_1135 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1136 = eq(_T_1135, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1137 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1138 = eq(_T_1137, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1139 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1140 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1141 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_1142 = eq(_T_1141, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1143 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1144 = eq(_T_1143, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1145 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_1146 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_1147 = and(_T_1136, _T_1138) @[dec_tlu_ctl.scala 3173:198] + node _T_1148 = and(_T_1147, _T_1139) @[dec_tlu_ctl.scala 3173:198] + node _T_1149 = and(_T_1148, _T_1140) @[dec_tlu_ctl.scala 3173:198] + node _T_1150 = and(_T_1149, _T_1142) @[dec_tlu_ctl.scala 3173:198] + node _T_1151 = and(_T_1150, _T_1144) @[dec_tlu_ctl.scala 3173:198] + node _T_1152 = and(_T_1151, _T_1145) @[dec_tlu_ctl.scala 3173:198] + node _T_1153 = and(_T_1152, _T_1146) @[dec_tlu_ctl.scala 3173:198] + node _T_1154 = or(_T_1134, _T_1153) @[dec_tlu_ctl.scala 3250:73] + node _T_1155 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1156 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1157 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1158 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1160 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1162 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1163 = eq(_T_1162, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1164 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_1165 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_1166 = eq(_T_1165, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1167 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_1168 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_1169 = eq(_T_1168, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1170 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_1171 = eq(_T_1170, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_1172 = and(_T_1155, _T_1156) @[dec_tlu_ctl.scala 3173:198] + node _T_1173 = and(_T_1172, _T_1157) @[dec_tlu_ctl.scala 3173:198] + node _T_1174 = and(_T_1173, _T_1159) @[dec_tlu_ctl.scala 3173:198] + node _T_1175 = and(_T_1174, _T_1161) @[dec_tlu_ctl.scala 3173:198] + node _T_1176 = and(_T_1175, _T_1163) @[dec_tlu_ctl.scala 3173:198] + node _T_1177 = and(_T_1176, _T_1164) @[dec_tlu_ctl.scala 3173:198] + node _T_1178 = and(_T_1177, _T_1166) @[dec_tlu_ctl.scala 3173:198] + node _T_1179 = and(_T_1178, _T_1167) @[dec_tlu_ctl.scala 3173:198] + node _T_1180 = and(_T_1179, _T_1169) @[dec_tlu_ctl.scala 3173:198] + node _T_1181 = and(_T_1180, _T_1171) @[dec_tlu_ctl.scala 3173:198] + node _T_1182 = or(_T_1154, _T_1181) @[dec_tlu_ctl.scala 3250:129] + node _T_1183 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1185 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_1186 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1187 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1188 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1189 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_1190 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1191 = eq(_T_1190, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1192 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_1193 = eq(_T_1192, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1194 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_1195 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_1196 = and(_T_1184, _T_1185) @[dec_tlu_ctl.scala 3173:198] + node _T_1197 = and(_T_1196, _T_1186) @[dec_tlu_ctl.scala 3173:198] + node _T_1198 = and(_T_1197, _T_1187) @[dec_tlu_ctl.scala 3173:198] + node _T_1199 = and(_T_1198, _T_1188) @[dec_tlu_ctl.scala 3173:198] + node _T_1200 = and(_T_1199, _T_1189) @[dec_tlu_ctl.scala 3173:198] + node _T_1201 = and(_T_1200, _T_1191) @[dec_tlu_ctl.scala 3173:198] + node _T_1202 = and(_T_1201, _T_1193) @[dec_tlu_ctl.scala 3173:198] + node _T_1203 = and(_T_1202, _T_1194) @[dec_tlu_ctl.scala 3173:198] + node _T_1204 = and(_T_1203, _T_1195) @[dec_tlu_ctl.scala 3173:198] + node _T_1205 = or(_T_1182, _T_1204) @[dec_tlu_ctl.scala 3251:65] + node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_1216 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_1217 = eq(_T_1216, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1218 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_1219 = and(_T_1207, _T_1208) @[dec_tlu_ctl.scala 3173:198] + node _T_1220 = and(_T_1219, _T_1209) @[dec_tlu_ctl.scala 3173:198] + node _T_1221 = and(_T_1220, _T_1210) @[dec_tlu_ctl.scala 3173:198] + node _T_1222 = and(_T_1221, _T_1211) @[dec_tlu_ctl.scala 3173:198] + node _T_1223 = and(_T_1222, _T_1212) @[dec_tlu_ctl.scala 3173:198] + node _T_1224 = and(_T_1223, _T_1214) @[dec_tlu_ctl.scala 3173:198] + node _T_1225 = and(_T_1224, _T_1215) @[dec_tlu_ctl.scala 3173:198] + node _T_1226 = and(_T_1225, _T_1217) @[dec_tlu_ctl.scala 3173:198] + node _T_1227 = and(_T_1226, _T_1218) @[dec_tlu_ctl.scala 3173:198] + node _T_1228 = or(_T_1205, _T_1227) @[dec_tlu_ctl.scala 3251:121] + node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1230 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1231 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1232 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_1233 = eq(_T_1232, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1234 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1235 = eq(_T_1234, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_1242 = eq(_T_1241, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1243 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_1244 = and(_T_1229, _T_1230) @[dec_tlu_ctl.scala 3173:198] + node _T_1245 = and(_T_1244, _T_1231) @[dec_tlu_ctl.scala 3173:198] + node _T_1246 = and(_T_1245, _T_1233) @[dec_tlu_ctl.scala 3173:198] + node _T_1247 = and(_T_1246, _T_1235) @[dec_tlu_ctl.scala 3173:198] + node _T_1248 = and(_T_1247, _T_1237) @[dec_tlu_ctl.scala 3173:198] + node _T_1249 = and(_T_1248, _T_1238) @[dec_tlu_ctl.scala 3173:198] + node _T_1250 = and(_T_1249, _T_1240) @[dec_tlu_ctl.scala 3173:198] + node _T_1251 = and(_T_1250, _T_1242) @[dec_tlu_ctl.scala 3173:198] + node _T_1252 = and(_T_1251, _T_1243) @[dec_tlu_ctl.scala 3173:198] + node _T_1253 = or(_T_1228, _T_1252) @[dec_tlu_ctl.scala 3252:73] + node _T_1254 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1255 = eq(_T_1254, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1256 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1257 = eq(_T_1256, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1258 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1259 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1260 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_1261 = eq(_T_1260, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1262 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1264 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_1265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_1266 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_1267 = and(_T_1255, _T_1257) @[dec_tlu_ctl.scala 3173:198] + node _T_1268 = and(_T_1267, _T_1258) @[dec_tlu_ctl.scala 3173:198] + node _T_1269 = and(_T_1268, _T_1259) @[dec_tlu_ctl.scala 3173:198] + node _T_1270 = and(_T_1269, _T_1261) @[dec_tlu_ctl.scala 3173:198] + node _T_1271 = and(_T_1270, _T_1263) @[dec_tlu_ctl.scala 3173:198] + node _T_1272 = and(_T_1271, _T_1264) @[dec_tlu_ctl.scala 3173:198] + node _T_1273 = and(_T_1272, _T_1265) @[dec_tlu_ctl.scala 3173:198] + node _T_1274 = and(_T_1273, _T_1266) @[dec_tlu_ctl.scala 3173:198] + node _T_1275 = or(_T_1253, _T_1274) @[dec_tlu_ctl.scala 3252:129] + node _T_1276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1277 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1279 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1280 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1281 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1282 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1283 = eq(_T_1282, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1284 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_1285 = eq(_T_1284, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1286 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_1287 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_1288 = eq(_T_1287, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1289 = and(_T_1276, _T_1278) @[dec_tlu_ctl.scala 3173:198] + node _T_1290 = and(_T_1289, _T_1279) @[dec_tlu_ctl.scala 3173:198] + node _T_1291 = and(_T_1290, _T_1280) @[dec_tlu_ctl.scala 3173:198] + node _T_1292 = and(_T_1291, _T_1281) @[dec_tlu_ctl.scala 3173:198] + node _T_1293 = and(_T_1292, _T_1283) @[dec_tlu_ctl.scala 3173:198] + node _T_1294 = and(_T_1293, _T_1285) @[dec_tlu_ctl.scala 3173:198] + node _T_1295 = and(_T_1294, _T_1286) @[dec_tlu_ctl.scala 3173:198] + node _T_1296 = and(_T_1295, _T_1288) @[dec_tlu_ctl.scala 3173:198] + node _T_1297 = or(_T_1275, _T_1296) @[dec_tlu_ctl.scala 3253:73] + node _T_1298 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1299 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1300 = eq(_T_1299, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1301 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1302 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1303 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1304 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1305 = eq(_T_1304, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1306 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_1307 = eq(_T_1306, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1308 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_1309 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_1310 = eq(_T_1309, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1311 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_1313 = and(_T_1298, _T_1300) @[dec_tlu_ctl.scala 3173:198] + node _T_1314 = and(_T_1313, _T_1301) @[dec_tlu_ctl.scala 3173:198] + node _T_1315 = and(_T_1314, _T_1302) @[dec_tlu_ctl.scala 3173:198] + node _T_1316 = and(_T_1315, _T_1303) @[dec_tlu_ctl.scala 3173:198] + node _T_1317 = and(_T_1316, _T_1305) @[dec_tlu_ctl.scala 3173:198] + node _T_1318 = and(_T_1317, _T_1307) @[dec_tlu_ctl.scala 3173:198] + node _T_1319 = and(_T_1318, _T_1308) @[dec_tlu_ctl.scala 3173:198] + node _T_1320 = and(_T_1319, _T_1310) @[dec_tlu_ctl.scala 3173:198] + node _T_1321 = and(_T_1320, _T_1312) @[dec_tlu_ctl.scala 3173:198] + node _T_1322 = or(_T_1297, _T_1321) @[dec_tlu_ctl.scala 3253:129] + node _T_1323 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1324 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1326 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1327 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1328 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1329 = eq(_T_1328, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1330 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1331 = eq(_T_1330, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1332 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_1333 = and(_T_1323, _T_1325) @[dec_tlu_ctl.scala 3173:198] + node _T_1334 = and(_T_1333, _T_1326) @[dec_tlu_ctl.scala 3173:198] + node _T_1335 = and(_T_1334, _T_1327) @[dec_tlu_ctl.scala 3173:198] + node _T_1336 = and(_T_1335, _T_1329) @[dec_tlu_ctl.scala 3173:198] + node _T_1337 = and(_T_1336, _T_1331) @[dec_tlu_ctl.scala 3173:198] + node _T_1338 = and(_T_1337, _T_1332) @[dec_tlu_ctl.scala 3173:198] + node _T_1339 = or(_T_1322, _T_1338) @[dec_tlu_ctl.scala 3254:73] + node _T_1340 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1341 = eq(_T_1340, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1342 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_1343 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1344 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1345 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1346 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_1347 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1349 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_1350 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_1351 = eq(_T_1350, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1352 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_1353 = and(_T_1341, _T_1342) @[dec_tlu_ctl.scala 3173:198] + node _T_1354 = and(_T_1353, _T_1343) @[dec_tlu_ctl.scala 3173:198] + node _T_1355 = and(_T_1354, _T_1344) @[dec_tlu_ctl.scala 3173:198] + node _T_1356 = and(_T_1355, _T_1345) @[dec_tlu_ctl.scala 3173:198] + node _T_1357 = and(_T_1356, _T_1346) @[dec_tlu_ctl.scala 3173:198] + node _T_1358 = and(_T_1357, _T_1348) @[dec_tlu_ctl.scala 3173:198] + node _T_1359 = and(_T_1358, _T_1349) @[dec_tlu_ctl.scala 3173:198] + node _T_1360 = and(_T_1359, _T_1351) @[dec_tlu_ctl.scala 3173:198] + node _T_1361 = and(_T_1360, _T_1352) @[dec_tlu_ctl.scala 3173:198] + node _T_1362 = or(_T_1339, _T_1361) @[dec_tlu_ctl.scala 3254:129] + node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_1373 = eq(_T_1372, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1374 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_1375 = eq(_T_1374, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_1376 = and(_T_1364, _T_1365) @[dec_tlu_ctl.scala 3173:198] + node _T_1377 = and(_T_1376, _T_1366) @[dec_tlu_ctl.scala 3173:198] + node _T_1378 = and(_T_1377, _T_1367) @[dec_tlu_ctl.scala 3173:198] + node _T_1379 = and(_T_1378, _T_1368) @[dec_tlu_ctl.scala 3173:198] + node _T_1380 = and(_T_1379, _T_1369) @[dec_tlu_ctl.scala 3173:198] + node _T_1381 = and(_T_1380, _T_1371) @[dec_tlu_ctl.scala 3173:198] + node _T_1382 = and(_T_1381, _T_1373) @[dec_tlu_ctl.scala 3173:198] + node _T_1383 = and(_T_1382, _T_1375) @[dec_tlu_ctl.scala 3173:198] + node _T_1384 = or(_T_1362, _T_1383) @[dec_tlu_ctl.scala 3255:73] + node _T_1385 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1386 = eq(_T_1385, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1387 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_1388 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1389 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1390 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1391 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_1392 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1393 = eq(_T_1392, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1394 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_1395 = eq(_T_1394, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1396 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_1397 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1399 = and(_T_1386, _T_1387) @[dec_tlu_ctl.scala 3173:198] + node _T_1400 = and(_T_1399, _T_1388) @[dec_tlu_ctl.scala 3173:198] + node _T_1401 = and(_T_1400, _T_1389) @[dec_tlu_ctl.scala 3173:198] + node _T_1402 = and(_T_1401, _T_1390) @[dec_tlu_ctl.scala 3173:198] + node _T_1403 = and(_T_1402, _T_1391) @[dec_tlu_ctl.scala 3173:198] + node _T_1404 = and(_T_1403, _T_1393) @[dec_tlu_ctl.scala 3173:198] + node _T_1405 = and(_T_1404, _T_1395) @[dec_tlu_ctl.scala 3173:198] + node _T_1406 = and(_T_1405, _T_1396) @[dec_tlu_ctl.scala 3173:198] + node _T_1407 = and(_T_1406, _T_1398) @[dec_tlu_ctl.scala 3173:198] + node _T_1408 = or(_T_1384, _T_1407) @[dec_tlu_ctl.scala 3255:129] + node _T_1409 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1410 = eq(_T_1409, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1411 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_1412 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1413 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1414 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1415 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1417 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_1418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_1419 = eq(_T_1418, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_1423 = eq(_T_1422, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1424 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_1425 = eq(_T_1424, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_1426 = and(_T_1410, _T_1411) @[dec_tlu_ctl.scala 3173:198] + node _T_1427 = and(_T_1426, _T_1412) @[dec_tlu_ctl.scala 3173:198] + node _T_1428 = and(_T_1427, _T_1413) @[dec_tlu_ctl.scala 3173:198] + node _T_1429 = and(_T_1428, _T_1414) @[dec_tlu_ctl.scala 3173:198] + node _T_1430 = and(_T_1429, _T_1416) @[dec_tlu_ctl.scala 3173:198] + node _T_1431 = and(_T_1430, _T_1417) @[dec_tlu_ctl.scala 3173:198] + node _T_1432 = and(_T_1431, _T_1419) @[dec_tlu_ctl.scala 3173:198] + node _T_1433 = and(_T_1432, _T_1421) @[dec_tlu_ctl.scala 3173:198] + node _T_1434 = and(_T_1433, _T_1423) @[dec_tlu_ctl.scala 3173:198] + node _T_1435 = and(_T_1434, _T_1425) @[dec_tlu_ctl.scala 3173:198] + node _T_1436 = or(_T_1408, _T_1435) @[dec_tlu_ctl.scala 3256:73] + node _T_1437 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1438 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1440 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1441 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1442 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1443 = eq(_T_1442, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1444 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1445 = eq(_T_1444, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1446 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_1447 = and(_T_1437, _T_1439) @[dec_tlu_ctl.scala 3173:198] + node _T_1448 = and(_T_1447, _T_1440) @[dec_tlu_ctl.scala 3173:198] + node _T_1449 = and(_T_1448, _T_1441) @[dec_tlu_ctl.scala 3173:198] + node _T_1450 = and(_T_1449, _T_1443) @[dec_tlu_ctl.scala 3173:198] + node _T_1451 = and(_T_1450, _T_1445) @[dec_tlu_ctl.scala 3173:198] + node _T_1452 = and(_T_1451, _T_1446) @[dec_tlu_ctl.scala 3173:198] + node _T_1453 = or(_T_1436, _T_1452) @[dec_tlu_ctl.scala 3256:121] + node _T_1454 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1455 = eq(_T_1454, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1456 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1457 = eq(_T_1456, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1458 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1459 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1460 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_1461 = eq(_T_1460, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1462 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_1463 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1464 = eq(_T_1463, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1465 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1467 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1469 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_1470 = eq(_T_1469, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1471 = and(_T_1455, _T_1457) @[dec_tlu_ctl.scala 3173:198] + node _T_1472 = and(_T_1471, _T_1458) @[dec_tlu_ctl.scala 3173:198] + node _T_1473 = and(_T_1472, _T_1459) @[dec_tlu_ctl.scala 3173:198] + node _T_1474 = and(_T_1473, _T_1461) @[dec_tlu_ctl.scala 3173:198] + node _T_1475 = and(_T_1474, _T_1462) @[dec_tlu_ctl.scala 3173:198] + node _T_1476 = and(_T_1475, _T_1464) @[dec_tlu_ctl.scala 3173:198] + node _T_1477 = and(_T_1476, _T_1466) @[dec_tlu_ctl.scala 3173:198] + node _T_1478 = and(_T_1477, _T_1468) @[dec_tlu_ctl.scala 3173:198] + node _T_1479 = and(_T_1478, _T_1470) @[dec_tlu_ctl.scala 3173:198] + node _T_1480 = or(_T_1453, _T_1479) @[dec_tlu_ctl.scala 3257:81] + node _T_1481 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1482 = eq(_T_1481, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1483 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1485 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1486 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1487 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_1488 = eq(_T_1487, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1489 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1490 = eq(_T_1489, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1491 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_1492 = eq(_T_1491, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1493 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_1494 = eq(_T_1493, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1495 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_1496 = eq(_T_1495, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1497 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_1498 = eq(_T_1497, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_1499 = and(_T_1482, _T_1484) @[dec_tlu_ctl.scala 3173:198] + node _T_1500 = and(_T_1499, _T_1485) @[dec_tlu_ctl.scala 3173:198] + node _T_1501 = and(_T_1500, _T_1486) @[dec_tlu_ctl.scala 3173:198] + node _T_1502 = and(_T_1501, _T_1488) @[dec_tlu_ctl.scala 3173:198] + node _T_1503 = and(_T_1502, _T_1490) @[dec_tlu_ctl.scala 3173:198] + node _T_1504 = and(_T_1503, _T_1492) @[dec_tlu_ctl.scala 3173:198] + node _T_1505 = and(_T_1504, _T_1494) @[dec_tlu_ctl.scala 3173:198] + node _T_1506 = and(_T_1505, _T_1496) @[dec_tlu_ctl.scala 3173:198] + node _T_1507 = and(_T_1506, _T_1498) @[dec_tlu_ctl.scala 3173:198] + node _T_1508 = or(_T_1480, _T_1507) @[dec_tlu_ctl.scala 3257:129] + node _T_1509 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1510 = eq(_T_1509, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1511 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1513 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1514 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1515 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_1516 = eq(_T_1515, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1517 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1518 = eq(_T_1517, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1519 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_1520 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_1521 = and(_T_1510, _T_1512) @[dec_tlu_ctl.scala 3173:198] + node _T_1522 = and(_T_1521, _T_1513) @[dec_tlu_ctl.scala 3173:198] + node _T_1523 = and(_T_1522, _T_1514) @[dec_tlu_ctl.scala 3173:198] + node _T_1524 = and(_T_1523, _T_1516) @[dec_tlu_ctl.scala 3173:198] + node _T_1525 = and(_T_1524, _T_1518) @[dec_tlu_ctl.scala 3173:198] + node _T_1526 = and(_T_1525, _T_1519) @[dec_tlu_ctl.scala 3173:198] + node _T_1527 = and(_T_1526, _T_1520) @[dec_tlu_ctl.scala 3173:198] + node _T_1528 = or(_T_1508, _T_1527) @[dec_tlu_ctl.scala 3258:65] + node _T_1529 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1530 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1531 = eq(_T_1530, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1532 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1533 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1534 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1536 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1537 = eq(_T_1536, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1538 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_1539 = and(_T_1529, _T_1531) @[dec_tlu_ctl.scala 3173:198] + node _T_1540 = and(_T_1539, _T_1532) @[dec_tlu_ctl.scala 3173:198] + node _T_1541 = and(_T_1540, _T_1533) @[dec_tlu_ctl.scala 3173:198] + node _T_1542 = and(_T_1541, _T_1535) @[dec_tlu_ctl.scala 3173:198] + node _T_1543 = and(_T_1542, _T_1537) @[dec_tlu_ctl.scala 3173:198] + node _T_1544 = and(_T_1543, _T_1538) @[dec_tlu_ctl.scala 3173:198] + node _T_1545 = or(_T_1528, _T_1544) @[dec_tlu_ctl.scala 3258:121] + node _T_1546 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1547 = eq(_T_1546, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1548 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1549 = eq(_T_1548, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1550 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1551 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1552 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_1553 = eq(_T_1552, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1555 = eq(_T_1554, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1556 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_1557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_1558 = and(_T_1547, _T_1549) @[dec_tlu_ctl.scala 3173:198] + node _T_1559 = and(_T_1558, _T_1550) @[dec_tlu_ctl.scala 3173:198] + node _T_1560 = and(_T_1559, _T_1551) @[dec_tlu_ctl.scala 3173:198] + node _T_1561 = and(_T_1560, _T_1553) @[dec_tlu_ctl.scala 3173:198] + node _T_1562 = and(_T_1561, _T_1555) @[dec_tlu_ctl.scala 3173:198] + node _T_1563 = and(_T_1562, _T_1556) @[dec_tlu_ctl.scala 3173:198] + node _T_1564 = and(_T_1563, _T_1557) @[dec_tlu_ctl.scala 3173:198] + node _T_1565 = or(_T_1545, _T_1564) @[dec_tlu_ctl.scala 3259:81] + node _T_1566 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1567 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1568 = eq(_T_1567, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1569 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1570 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1571 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1573 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1574 = eq(_T_1573, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1575 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_1576 = and(_T_1566, _T_1568) @[dec_tlu_ctl.scala 3173:198] + node _T_1577 = and(_T_1576, _T_1569) @[dec_tlu_ctl.scala 3173:198] + node _T_1578 = and(_T_1577, _T_1570) @[dec_tlu_ctl.scala 3173:198] + node _T_1579 = and(_T_1578, _T_1572) @[dec_tlu_ctl.scala 3173:198] + node _T_1580 = and(_T_1579, _T_1574) @[dec_tlu_ctl.scala 3173:198] + node _T_1581 = and(_T_1580, _T_1575) @[dec_tlu_ctl.scala 3173:198] + node _T_1582 = or(_T_1565, _T_1581) @[dec_tlu_ctl.scala 3259:137] + io.csr_pkt.legal <= _T_1582 @[dec_tlu_ctl.scala 3246:26] + + module dec_tlu_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}, flip free_clk : Clock, flip free_l2clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_tlu_core_empty : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_extint : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_trace_disable : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_picio_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip tlu_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}, flip tlu_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, flip tlu_mem : {flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, flip tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, flip lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, dec_pic : {flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip mexintpend : UInt<1>}} + + wire mtdata1_t : UInt<10>[4] @[dec_tlu_ctl.scala 162:67] + wire pause_expired_wb : UInt<1> + pause_expired_wb <= UInt<1>("h00") + wire take_nmi_r_d1 : UInt<1> + take_nmi_r_d1 <= UInt<1>("h00") + wire exc_or_int_valid_r_d1 : UInt<1> + exc_or_int_valid_r_d1 <= UInt<1>("h00") + wire interrupt_valid_r_d1 : UInt<1> + interrupt_valid_r_d1 <= UInt<1>("h00") + wire tlu_flush_lower_r : UInt<1> + tlu_flush_lower_r <= UInt<1>("h00") + wire synchronous_flush_r : UInt<1> + synchronous_flush_r <= UInt<1>("h00") + wire interrupt_valid_r : UInt<1> + interrupt_valid_r <= UInt<1>("h00") + wire take_nmi : UInt<1> + take_nmi <= UInt<1>("h00") + wire take_reset : UInt<1> + take_reset <= UInt<1>("h00") + wire take_int_timer1_int : UInt<1> + take_int_timer1_int <= UInt<1>("h00") + wire take_int_timer0_int : UInt<1> + take_int_timer0_int <= UInt<1>("h00") + wire take_timer_int : UInt<1> + take_timer_int <= UInt<1>("h00") + wire take_soft_int : UInt<1> + take_soft_int <= UInt<1>("h00") + wire take_ce_int : UInt<1> + take_ce_int <= UInt<1>("h00") + wire take_ext_int_start : UInt<1> + take_ext_int_start <= UInt<1>("h00") + wire ext_int_freeze : UInt<1> + ext_int_freeze <= UInt<1>("h00") + wire take_ext_int_start_d2 : UInt<1> + take_ext_int_start_d2 <= UInt<1>("h00") + wire take_ext_int_start_d3 : UInt<1> + take_ext_int_start_d3 <= UInt<1>("h00") + wire fast_int_meicpct : UInt<1> + fast_int_meicpct <= UInt<1>("h00") + wire ignore_ext_int_due_to_lsu_stall : UInt<1> + ignore_ext_int_due_to_lsu_stall <= UInt<1>("h00") + wire take_ext_int : UInt<1> + take_ext_int <= UInt<1>("h00") + wire internal_dbg_halt_timers : UInt<1> + internal_dbg_halt_timers <= UInt<1>("h00") + wire int_timer1_int_hold : UInt<1> + int_timer1_int_hold <= UInt<1>("h00") + wire int_timer0_int_hold : UInt<1> + int_timer0_int_hold <= UInt<1>("h00") + wire mhwakeup_ready : UInt<1> + mhwakeup_ready <= UInt<1>("h00") + wire ext_int_ready : UInt<1> + ext_int_ready <= UInt<1>("h00") + wire ce_int_ready : UInt<1> + ce_int_ready <= UInt<1>("h00") + wire soft_int_ready : UInt<1> + soft_int_ready <= UInt<1>("h00") + wire timer_int_ready : UInt<1> + timer_int_ready <= UInt<1>("h00") + wire ebreak_to_debug_mode_r_d1 : UInt<1> + ebreak_to_debug_mode_r_d1 <= UInt<1>("h00") + wire ebreak_to_debug_mode_r : UInt<1> + ebreak_to_debug_mode_r <= UInt<1>("h00") + wire inst_acc_r : UInt<1> + inst_acc_r <= UInt<1>("h00") + wire inst_acc_r_raw : UInt<1> + inst_acc_r_raw <= UInt<1>("h00") + wire iccm_sbecc_r : UInt<1> + iccm_sbecc_r <= UInt<1>("h00") + wire ic_perr_r : UInt<1> + ic_perr_r <= UInt<1>("h00") + wire fence_i_r : UInt<1> + fence_i_r <= UInt<1>("h00") + wire ebreak_r : UInt<1> + ebreak_r <= UInt<1>("h00") + wire ecall_r : UInt<1> + ecall_r <= UInt<1>("h00") + wire illegal_r : UInt<1> + illegal_r <= UInt<1>("h00") + wire mret_r : UInt<1> + mret_r <= UInt<1>("h00") + wire iccm_repair_state_ns : UInt<1> + iccm_repair_state_ns <= UInt<1>("h00") + wire rfpc_i0_r : UInt<1> + rfpc_i0_r <= UInt<1>("h00") + wire tlu_i0_kill_writeb_r : UInt<1> + tlu_i0_kill_writeb_r <= UInt<1>("h00") + wire lsu_exc_valid_r_d1 : UInt<1> + lsu_exc_valid_r_d1 <= UInt<1>("h00") + wire lsu_i0_exc_r_raw : UInt<1> + lsu_i0_exc_r_raw <= UInt<1>("h00") + wire mdseac_locked_f : UInt<1> + mdseac_locked_f <= UInt<1>("h00") + wire i_cpu_run_req_d1 : UInt<1> + i_cpu_run_req_d1 <= UInt<1>("h00") + wire cpu_run_ack : UInt<1> + cpu_run_ack <= UInt<1>("h00") + wire cpu_halt_status : UInt<1> + cpu_halt_status <= UInt<1>("h00") + wire cpu_halt_ack : UInt<1> + cpu_halt_ack <= UInt<1>("h00") + wire pmu_fw_tlu_halted : UInt<1> + pmu_fw_tlu_halted <= UInt<1>("h00") + wire internal_pmu_fw_halt_mode : UInt<1> + internal_pmu_fw_halt_mode <= UInt<1>("h00") + wire pmu_fw_halt_req_ns : UInt<1> + pmu_fw_halt_req_ns <= UInt<1>("h00") + wire pmu_fw_halt_req_f : UInt<1> + pmu_fw_halt_req_f <= UInt<1>("h00") + wire pmu_fw_tlu_halted_f : UInt<1> + pmu_fw_tlu_halted_f <= UInt<1>("h00") + wire int_timer0_int_hold_f : UInt<1> + int_timer0_int_hold_f <= UInt<1>("h00") + wire int_timer1_int_hold_f : UInt<1> + int_timer1_int_hold_f <= UInt<1>("h00") + wire trigger_hit_dmode_r : UInt<1> + trigger_hit_dmode_r <= UInt<1>("h00") + wire i0_trigger_hit_r : UInt<1> + i0_trigger_hit_r <= UInt<1>("h00") + wire pause_expired_r : UInt<1> + pause_expired_r <= UInt<1>("h00") + wire dec_tlu_pmu_fw_halted : UInt<1> + dec_tlu_pmu_fw_halted <= UInt<1>("h00") + wire dec_tlu_flush_noredir_r_d1 : UInt<1> + dec_tlu_flush_noredir_r_d1 <= UInt<1>("h00") + wire halt_taken_f : UInt<1> + halt_taken_f <= UInt<1>("h00") + wire lsu_idle_any_f : UInt<1> + lsu_idle_any_f <= UInt<1>("h00") + wire ifu_miss_state_idle_f : UInt<1> + ifu_miss_state_idle_f <= UInt<1>("h00") + wire dbg_tlu_halted_f : UInt<1> + dbg_tlu_halted_f <= UInt<1>("h00") + wire debug_halt_req_f : UInt<1> + debug_halt_req_f <= UInt<1>("h00") + wire debug_resume_req_f_raw : UInt<1> + debug_resume_req_f_raw <= UInt<1>("h00") + wire debug_resume_req_f : UInt<1> + debug_resume_req_f <= UInt<1>("h00") + wire trigger_hit_dmode_r_d1 : UInt<1> + trigger_hit_dmode_r_d1 <= UInt<1>("h00") + wire dcsr_single_step_done_f : UInt<1> + dcsr_single_step_done_f <= UInt<1>("h00") + wire debug_halt_req_d1 : UInt<1> + debug_halt_req_d1 <= UInt<1>("h00") + wire request_debug_mode_r_d1 : UInt<1> + request_debug_mode_r_d1 <= UInt<1>("h00") + wire request_debug_mode_done_f : UInt<1> + request_debug_mode_done_f <= UInt<1>("h00") + wire dcsr_single_step_running_f : UInt<1> + dcsr_single_step_running_f <= UInt<1>("h00") + wire dec_tlu_flush_pause_r_d1 : UInt<1> + dec_tlu_flush_pause_r_d1 <= UInt<1>("h00") + wire dbg_halt_req_held : UInt<1> + dbg_halt_req_held <= UInt<1>("h00") + wire debug_halt_req_ns : UInt<1> + debug_halt_req_ns <= UInt<1>("h00") + wire internal_dbg_halt_mode : UInt<1> + internal_dbg_halt_mode <= UInt<1>("h00") + wire core_empty : UInt<1> + core_empty <= UInt<1>("h00") + wire dbg_halt_req_final : UInt<1> + dbg_halt_req_final <= UInt<1>("h00") + wire debug_brkpt_status_ns : UInt<1> + debug_brkpt_status_ns <= UInt<1>("h00") + wire mpc_debug_halt_ack_ns : UInt<1> + mpc_debug_halt_ack_ns <= UInt<1>("h00") + wire mpc_debug_run_ack_ns : UInt<1> + mpc_debug_run_ack_ns <= UInt<1>("h00") + wire mpc_halt_state_ns : UInt<1> + mpc_halt_state_ns <= UInt<1>("h00") + wire mpc_run_state_ns : UInt<1> + mpc_run_state_ns <= UInt<1>("h00") + wire dbg_halt_state_ns : UInt<1> + dbg_halt_state_ns <= UInt<1>("h00") + wire dbg_run_state_ns : UInt<1> + dbg_run_state_ns <= UInt<1>("h00") + wire dbg_halt_state_f : UInt<1> + dbg_halt_state_f <= UInt<1>("h00") + wire mpc_halt_state_f : UInt<1> + mpc_halt_state_f <= UInt<1>("h00") + wire nmi_int_detected : UInt<1> + nmi_int_detected <= UInt<1>("h00") + wire nmi_lsu_load_type : UInt<1> + nmi_lsu_load_type <= UInt<1>("h00") + wire nmi_lsu_store_type : UInt<1> + nmi_lsu_store_type <= UInt<1>("h00") + wire reset_delayed : UInt<1> + reset_delayed <= UInt<1>("h00") + wire debug_mode_status : UInt<1> + debug_mode_status <= UInt<1>("h00") + wire e5_valid : UInt<1> + e5_valid <= UInt<1>("h00") + wire ic_perr_r_d1 : UInt<1> + ic_perr_r_d1 <= UInt<1>("h00") + wire iccm_sbecc_r_d1 : UInt<1> + iccm_sbecc_r_d1 <= UInt<1>("h00") + wire npc_r : UInt<31> + npc_r <= UInt<1>("h00") + wire npc_r_d1 : UInt<31> + npc_r_d1 <= UInt<1>("h00") + wire mie_ns : UInt<6> + mie_ns <= UInt<1>("h00") + wire mepc : UInt<31> + mepc <= UInt<1>("h00") + wire mdseac_locked_ns : UInt<1> + mdseac_locked_ns <= UInt<1>("h00") + wire force_halt : UInt<1> + force_halt <= UInt<1>("h00") + wire dpc : UInt<31> + dpc <= UInt<1>("h00") + wire mstatus_mie_ns : UInt<1> + mstatus_mie_ns <= UInt<1>("h00") + wire dec_csr_wen_r_mod : UInt<1> + dec_csr_wen_r_mod <= UInt<1>("h00") + wire fw_halt_req : UInt<1> + fw_halt_req <= UInt<1>("h00") + wire mstatus : UInt<2> + mstatus <= UInt<1>("h00") + wire dcsr : UInt<16> + dcsr <= UInt<1>("h00") + wire mtvec : UInt<31> + mtvec <= UInt<1>("h00") + wire mip : UInt<6> + mip <= UInt<1>("h00") + wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_meicpct : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[dec_tlu_ctl.scala 278:47] + wire dec_tlu_mpc_halted_only_ns : UInt<1> + dec_tlu_mpc_halted_only_ns <= UInt<1>("h00") + node _T = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 281:39] + node _T_1 = and(_T, mpc_halt_state_f) @[dec_tlu_ctl.scala 281:57] + dec_tlu_mpc_halted_only_ns <= _T_1 @[dec_tlu_ctl.scala 281:36] + inst int_exc of int_exc @[dec_tlu_ctl.scala 282:29] + int_exc.clock <= clock + int_exc.reset <= reset + inst csr of csr_tlu @[dec_tlu_ctl.scala 283:23] + csr.clock <= clock + csr.reset <= reset + inst int_timers of dec_timer_ctl @[dec_tlu_ctl.scala 284:30] + int_timers.clock <= clock + int_timers.reset <= reset + int_timers.io.free_l2clk <= io.free_l2clk @[dec_tlu_ctl.scala 285:65] + int_timers.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 286:57] + int_timers.io.dec_csr_wen_r_mod <= dec_csr_wen_r_mod @[dec_tlu_ctl.scala 287:49] + int_timers.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 289:49] + int_timers.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 290:49] + int_timers.io.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 291:57] + int_timers.io.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 292:57] + int_timers.io.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 293:57] + int_timers.io.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 294:57] + int_timers.io.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 295:57] + int_timers.io.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 296:57] + int_timers.io.dec_pause_state <= io.dec_pause_state @[dec_tlu_ctl.scala 297:49] + int_timers.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 298:49] + int_timers.io.internal_dbg_halt_timers <= internal_dbg_halt_timers @[dec_tlu_ctl.scala 299:47] + node _T_2 = cat(io.i_cpu_run_req, io.mpc_debug_halt_req) @[Cat.scala 29:58] + node _T_3 = cat(_T_2, io.mpc_debug_run_req) @[Cat.scala 29:58] + node _T_4 = cat(io.soft_int, io.i_cpu_halt_req) @[Cat.scala 29:58] + node _T_5 = cat(io.nmi_int, io.timer_int) @[Cat.scala 29:58] + node _T_6 = cat(_T_5, _T_4) @[Cat.scala 29:58] + node _T_7 = cat(_T_6, _T_3) @[Cat.scala 29:58] + reg _T_8 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 37:81] + _T_8 <= _T_7 @[lib.scala 37:81] + reg syncro_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 37:58] + syncro_ff <= _T_8 @[lib.scala 37:58] + node nmi_int_sync = bits(syncro_ff, 6, 6) @[dec_tlu_ctl.scala 311:75] + node timer_int_sync = bits(syncro_ff, 5, 5) @[dec_tlu_ctl.scala 312:67] + node soft_int_sync = bits(syncro_ff, 4, 4) @[dec_tlu_ctl.scala 313:67] + node i_cpu_halt_req_sync = bits(syncro_ff, 3, 3) @[dec_tlu_ctl.scala 314:59] + node i_cpu_run_req_sync = bits(syncro_ff, 2, 2) @[dec_tlu_ctl.scala 315:59] + node mpc_debug_halt_req_sync_raw = bits(syncro_ff, 1, 1) @[dec_tlu_ctl.scala 316:51] + node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[dec_tlu_ctl.scala 317:59] + node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 320:59] + node _T_10 = bits(_T_9, 0, 0) @[dec_tlu_ctl.scala 320:75] + int_timers.io.csr_wr_clk <= clock @[dec_tlu_ctl.scala 321:52] + node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[dec_tlu_ctl.scala 325:35] + node _T_11 = or(debug_mode_status, i_cpu_run_req_d1) @[dec_tlu_ctl.scala 326:55] + node _T_12 = or(_T_11, interrupt_valid_r) @[dec_tlu_ctl.scala 326:74] + node _T_13 = or(_T_12, interrupt_valid_r_d1) @[dec_tlu_ctl.scala 326:94] + node _T_14 = or(_T_13, reset_delayed) @[dec_tlu_ctl.scala 326:117] + node _T_15 = or(_T_14, pause_expired_r) @[dec_tlu_ctl.scala 326:133] + node _T_16 = or(_T_15, pause_expired_wb) @[dec_tlu_ctl.scala 326:151] + node _T_17 = or(_T_16, ic_perr_r) @[dec_tlu_ctl.scala 326:170] + node _T_18 = or(_T_17, iccm_sbecc_r) @[dec_tlu_ctl.scala 326:183] + node flush_clkvalid = or(_T_18, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 326:199] + node _T_19 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 329:50] + node _T_20 = bits(_T_19, 0, 0) @[dec_tlu_ctl.scala 329:66] + node _T_21 = or(e4e5_valid, flush_clkvalid) @[dec_tlu_ctl.scala 330:54] + node _T_22 = bits(_T_21, 0, 0) @[dec_tlu_ctl.scala 330:72] + wire ifu_ic_error_start_f : UInt<1> + ifu_ic_error_start_f <= UInt<1>("h00") + node _T_23 = xor(io.tlu_mem.ifu_ic_error_start, ifu_ic_error_start_f) @[lib.scala 470:21] + node _T_24 = orr(_T_23) @[lib.scala 470:29] + reg _T_25 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_24 : @[Reg.scala 28:19] + _T_25 <= io.tlu_mem.ifu_ic_error_start @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ifu_ic_error_start_f <= _T_25 @[lib.scala 473:16] + wire ifu_iccm_rd_ecc_single_err_f : UInt<1> + ifu_iccm_rd_ecc_single_err_f <= UInt<1>("h00") + node _T_26 = xor(io.tlu_mem.ifu_iccm_rd_ecc_single_err, ifu_iccm_rd_ecc_single_err_f) @[lib.scala 470:21] + node _T_27 = orr(_T_26) @[lib.scala 470:29] + reg _T_28 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_27 : @[Reg.scala 28:19] + _T_28 <= io.tlu_mem.ifu_iccm_rd_ecc_single_err @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ifu_iccm_rd_ecc_single_err_f <= _T_28 @[lib.scala 473:16] + wire iccm_repair_state_d1 : UInt + iccm_repair_state_d1 <= UInt<1>("h00") + node _T_29 = xor(iccm_repair_state_ns, iccm_repair_state_d1) @[lib.scala 448:21] + node _T_30 = orr(_T_29) @[lib.scala 448:29] + reg _T_31 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_30 : @[Reg.scala 28:19] + _T_31 <= iccm_repair_state_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + iccm_repair_state_d1 <= _T_31 @[lib.scala 451:16] + wire _T_32 : UInt + _T_32 <= UInt<1>("h00") + node _T_33 = xor(io.dec_tlu_i0_valid_r, _T_32) @[lib.scala 448:21] + node _T_34 = orr(_T_33) @[lib.scala 448:29] + reg _T_35 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_34 : @[Reg.scala 28:19] + _T_35 <= io.dec_tlu_i0_valid_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_32 <= _T_35 @[lib.scala 451:16] + e5_valid <= _T_32 @[dec_tlu_ctl.scala 338:75] + wire _T_36 : UInt + _T_36 <= UInt<1>("h00") + node _T_37 = xor(internal_dbg_halt_mode, _T_36) @[lib.scala 448:21] + node _T_38 = orr(_T_37) @[lib.scala 448:29] + reg _T_39 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_38 : @[Reg.scala 28:19] + _T_39 <= internal_dbg_halt_mode @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_36 <= _T_39 @[lib.scala 451:16] + debug_mode_status <= _T_36 @[dec_tlu_ctl.scala 339:51] + wire lsu_pmu_load_external_r : UInt<1> + lsu_pmu_load_external_r <= UInt<1>("h00") + node _T_40 = xor(io.lsu_tlu.lsu_pmu_load_external_m, lsu_pmu_load_external_r) @[lib.scala 470:21] + node _T_41 = orr(_T_40) @[lib.scala 470:29] + reg _T_42 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_41 : @[Reg.scala 28:19] + _T_42 <= io.lsu_tlu.lsu_pmu_load_external_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + lsu_pmu_load_external_r <= _T_42 @[lib.scala 473:16] + wire lsu_pmu_store_external_r : UInt<1> + lsu_pmu_store_external_r <= UInt<1>("h00") + node _T_43 = xor(io.lsu_tlu.lsu_pmu_store_external_m, lsu_pmu_store_external_r) @[lib.scala 470:21] + node _T_44 = orr(_T_43) @[lib.scala 470:29] + reg _T_45 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_44 : @[Reg.scala 28:19] + _T_45 <= io.lsu_tlu.lsu_pmu_store_external_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + lsu_pmu_store_external_r <= _T_45 @[lib.scala 473:16] + wire tlu_flush_lower_r_d1 : UInt + tlu_flush_lower_r_d1 <= UInt<1>("h00") + node _T_46 = xor(tlu_flush_lower_r, tlu_flush_lower_r_d1) @[lib.scala 448:21] + node _T_47 = orr(_T_46) @[lib.scala 448:29] + reg _T_48 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_47 : @[Reg.scala 28:19] + _T_48 <= tlu_flush_lower_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + tlu_flush_lower_r_d1 <= _T_48 @[lib.scala 451:16] + wire _T_49 : UInt + _T_49 <= UInt<1>("h00") + node _T_50 = xor(tlu_i0_kill_writeb_r, _T_49) @[lib.scala 448:21] + node _T_51 = orr(_T_50) @[lib.scala 448:29] + reg _T_52 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_51 : @[Reg.scala 28:19] + _T_52 <= tlu_i0_kill_writeb_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_49 <= _T_52 @[lib.scala 451:16] + io.dec_tlu_i0_kill_writeb_wb <= _T_49 @[dec_tlu_ctl.scala 343:41] + wire internal_dbg_halt_mode_f2 : UInt + internal_dbg_halt_mode_f2 <= UInt<1>("h00") + node _T_53 = xor(debug_mode_status, internal_dbg_halt_mode_f2) @[lib.scala 448:21] + node _T_54 = orr(_T_53) @[lib.scala 448:29] + reg _T_55 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_54 : @[Reg.scala 28:19] + _T_55 <= debug_mode_status @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + internal_dbg_halt_mode_f2 <= _T_55 @[lib.scala 451:16] + wire _T_56 : UInt + _T_56 <= UInt<1>("h00") + node _T_57 = xor(force_halt, _T_56) @[lib.scala 448:21] + node _T_58 = orr(_T_57) @[lib.scala 448:29] + reg _T_59 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_58 : @[Reg.scala 28:19] + _T_59 <= force_halt @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_56 <= _T_59 @[lib.scala 451:16] + io.tlu_mem.dec_tlu_force_halt <= _T_56 @[dec_tlu_ctl.scala 345:41] + io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 349:41] + wire nmi_int_delayed : UInt<1> + nmi_int_delayed <= UInt<1>("h00") + node _T_60 = xor(nmi_int_sync, nmi_int_delayed) @[lib.scala 470:21] + node _T_61 = orr(_T_60) @[lib.scala 470:29] + reg _T_62 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_61 : @[Reg.scala 28:19] + _T_62 <= nmi_int_sync @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + nmi_int_delayed <= _T_62 @[lib.scala 473:16] + wire nmi_int_detected_f : UInt + nmi_int_detected_f <= UInt<1>("h00") + node _T_63 = xor(nmi_int_detected, nmi_int_detected_f) @[lib.scala 448:21] + node _T_64 = orr(_T_63) @[lib.scala 448:29] + reg _T_65 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_64 : @[Reg.scala 28:19] + _T_65 <= nmi_int_detected @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + nmi_int_detected_f <= _T_65 @[lib.scala 451:16] + wire nmi_lsu_load_type_f : UInt + nmi_lsu_load_type_f <= UInt<1>("h00") + node _T_66 = xor(nmi_lsu_load_type, nmi_lsu_load_type_f) @[lib.scala 448:21] + node _T_67 = orr(_T_66) @[lib.scala 448:29] + reg _T_68 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_67 : @[Reg.scala 28:19] + _T_68 <= nmi_lsu_load_type @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + nmi_lsu_load_type_f <= _T_68 @[lib.scala 451:16] + wire nmi_lsu_store_type_f : UInt + nmi_lsu_store_type_f <= UInt<1>("h00") + node _T_69 = xor(nmi_lsu_store_type, nmi_lsu_store_type_f) @[lib.scala 448:21] + node _T_70 = orr(_T_69) @[lib.scala 448:29] + reg _T_71 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_70 : @[Reg.scala 28:19] + _T_71 <= nmi_lsu_store_type @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + nmi_lsu_store_type_f <= _T_71 @[lib.scala 451:16] + wire nmi_fir_type : UInt<1> + nmi_fir_type <= UInt<1>("h00") + node _T_72 = not(mdseac_locked_f) @[dec_tlu_ctl.scala 357:32] + node _T_73 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 357:96] + node _T_74 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 357:49] + node _T_75 = not(nmi_fir_type) @[dec_tlu_ctl.scala 357:146] + node nmi_lsu_detected = and(_T_74, _T_75) @[dec_tlu_ctl.scala 357:144] + node _T_76 = not(nmi_int_delayed) @[dec_tlu_ctl.scala 360:45] + node _T_77 = and(nmi_int_sync, _T_76) @[dec_tlu_ctl.scala 360:43] + node _T_78 = or(_T_77, nmi_lsu_detected) @[dec_tlu_ctl.scala 360:63] + node _T_79 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 360:106] + node _T_80 = and(nmi_int_detected_f, _T_79) @[dec_tlu_ctl.scala 360:104] + node _T_81 = or(_T_78, _T_80) @[dec_tlu_ctl.scala 360:82] + node _T_82 = or(_T_81, nmi_fir_type) @[dec_tlu_ctl.scala 360:122] + nmi_int_detected <= _T_82 @[dec_tlu_ctl.scala 360:26] + node _T_83 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 362:49] + node _T_84 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 362:121] + node _T_85 = and(nmi_int_detected_f, _T_84) @[dec_tlu_ctl.scala 362:119] + node _T_86 = not(_T_85) @[dec_tlu_ctl.scala 362:98] + node _T_87 = and(_T_83, _T_86) @[dec_tlu_ctl.scala 362:95] + node _T_88 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 362:164] + node _T_89 = and(nmi_lsu_load_type_f, _T_88) @[dec_tlu_ctl.scala 362:162] + node _T_90 = or(_T_87, _T_89) @[dec_tlu_ctl.scala 362:138] + nmi_lsu_load_type <= _T_90 @[dec_tlu_ctl.scala 362:28] + node _T_91 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 363:49] + node _T_92 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 363:121] + node _T_93 = and(nmi_int_detected_f, _T_92) @[dec_tlu_ctl.scala 363:119] + node _T_94 = not(_T_93) @[dec_tlu_ctl.scala 363:98] + node _T_95 = and(_T_91, _T_94) @[dec_tlu_ctl.scala 363:96] + node _T_96 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 363:164] + node _T_97 = and(nmi_lsu_store_type_f, _T_96) @[dec_tlu_ctl.scala 363:162] + node _T_98 = or(_T_95, _T_97) @[dec_tlu_ctl.scala 363:138] + nmi_lsu_store_type <= _T_98 @[dec_tlu_ctl.scala 363:28] + node _T_99 = not(nmi_int_detected_f) @[dec_tlu_ctl.scala 365:25] + node _T_100 = and(_T_99, csr.io.take_ext_int_start_d3) @[dec_tlu_ctl.scala 365:45] + node _T_101 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 365:95] + node _T_102 = and(_T_100, _T_101) @[dec_tlu_ctl.scala 365:76] + nmi_fir_type <= _T_102 @[dec_tlu_ctl.scala 365:22] + wire reset_detect : UInt + reset_detect <= UInt<1>("h00") + node _T_103 = xor(UInt<1>("h01"), reset_detect) @[lib.scala 448:21] + node _T_104 = orr(_T_103) @[lib.scala 448:29] + reg _T_105 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_104 : @[Reg.scala 28:19] + _T_105 <= UInt<1>("h01") @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reset_detect <= _T_105 @[lib.scala 451:16] + wire reset_detected : UInt + reset_detected <= UInt<1>("h00") + node _T_106 = xor(reset_detect, reset_detected) @[lib.scala 448:21] + node _T_107 = orr(_T_106) @[lib.scala 448:29] + reg _T_108 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_107 : @[Reg.scala 28:19] + _T_108 <= reset_detect @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reset_detected <= _T_108 @[lib.scala 451:16] + node _T_109 = xor(reset_detect, reset_detected) @[dec_tlu_ctl.scala 369:64] + reset_delayed <= _T_109 @[dec_tlu_ctl.scala 369:49] + node _T_110 = eq(csr.io.ext_int_freeze_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 376:69] + node mpc_debug_halt_req_sync = and(mpc_debug_halt_req_sync_raw, _T_110) @[dec_tlu_ctl.scala 376:67] + wire mpc_debug_halt_req_sync_f : UInt<1> + mpc_debug_halt_req_sync_f <= UInt<1>("h00") + node _T_111 = xor(mpc_debug_halt_req_sync, mpc_debug_halt_req_sync_f) @[lib.scala 470:21] + node _T_112 = orr(_T_111) @[lib.scala 470:29] + reg _T_113 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_112 : @[Reg.scala 28:19] + _T_113 <= mpc_debug_halt_req_sync @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mpc_debug_halt_req_sync_f <= _T_113 @[lib.scala 473:16] + wire mpc_debug_run_req_sync_f : UInt<1> + mpc_debug_run_req_sync_f <= UInt<1>("h00") + node _T_114 = xor(mpc_debug_run_req_sync, mpc_debug_run_req_sync_f) @[lib.scala 470:21] + node _T_115 = orr(_T_114) @[lib.scala 470:29] + reg _T_116 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_115 : @[Reg.scala 28:19] + _T_116 <= mpc_debug_run_req_sync @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mpc_debug_run_req_sync_f <= _T_116 @[lib.scala 473:16] + wire _T_117 : UInt + _T_117 <= UInt<1>("h00") + node _T_118 = xor(mpc_halt_state_ns, _T_117) @[lib.scala 448:21] + node _T_119 = orr(_T_118) @[lib.scala 448:29] + reg _T_120 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_119 : @[Reg.scala 28:19] + _T_120 <= mpc_halt_state_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_117 <= _T_120 @[lib.scala 451:16] + mpc_halt_state_f <= _T_117 @[dec_tlu_ctl.scala 379:62] + wire mpc_run_state_f : UInt + mpc_run_state_f <= UInt<1>("h00") + node _T_121 = xor(mpc_run_state_ns, mpc_run_state_f) @[lib.scala 448:21] + node _T_122 = orr(_T_121) @[lib.scala 448:29] + reg _T_123 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_122 : @[Reg.scala 28:19] + _T_123 <= mpc_run_state_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mpc_run_state_f <= _T_123 @[lib.scala 451:16] + wire debug_brkpt_status_f : UInt + debug_brkpt_status_f <= UInt<1>("h00") + node _T_124 = xor(debug_brkpt_status_ns, debug_brkpt_status_f) @[lib.scala 448:21] + node _T_125 = orr(_T_124) @[lib.scala 448:29] + reg _T_126 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_125 : @[Reg.scala 28:19] + _T_126 <= debug_brkpt_status_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + debug_brkpt_status_f <= _T_126 @[lib.scala 451:16] + wire mpc_debug_halt_ack_f : UInt + mpc_debug_halt_ack_f <= UInt<1>("h00") + node _T_127 = xor(mpc_debug_halt_ack_ns, mpc_debug_halt_ack_f) @[lib.scala 448:21] + node _T_128 = orr(_T_127) @[lib.scala 448:29] + reg _T_129 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_128 : @[Reg.scala 28:19] + _T_129 <= mpc_debug_halt_ack_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mpc_debug_halt_ack_f <= _T_129 @[lib.scala 451:16] + wire mpc_debug_run_ack_f : UInt + mpc_debug_run_ack_f <= UInt<1>("h00") + node _T_130 = xor(mpc_debug_run_ack_ns, mpc_debug_run_ack_f) @[lib.scala 448:21] + node _T_131 = orr(_T_130) @[lib.scala 448:29] + reg _T_132 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_131 : @[Reg.scala 28:19] + _T_132 <= mpc_debug_run_ack_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mpc_debug_run_ack_f <= _T_132 @[lib.scala 451:16] + wire _T_133 : UInt + _T_133 <= UInt<1>("h00") + node _T_134 = xor(dbg_halt_state_ns, _T_133) @[lib.scala 448:21] + node _T_135 = orr(_T_134) @[lib.scala 448:29] + reg _T_136 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_135 : @[Reg.scala 28:19] + _T_136 <= dbg_halt_state_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_133 <= _T_136 @[lib.scala 451:16] + dbg_halt_state_f <= _T_133 @[dec_tlu_ctl.scala 384:62] + wire dbg_run_state_f : UInt + dbg_run_state_f <= UInt<1>("h00") + node _T_137 = xor(dbg_run_state_ns, dbg_run_state_f) @[lib.scala 448:21] + node _T_138 = orr(_T_137) @[lib.scala 448:29] + reg _T_139 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_138 : @[Reg.scala 28:19] + _T_139 <= dbg_run_state_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dbg_run_state_f <= _T_139 @[lib.scala 451:16] + wire _T_140 : UInt + _T_140 <= UInt<1>("h00") + node _T_141 = xor(dec_tlu_mpc_halted_only_ns, _T_140) @[lib.scala 448:21] + node _T_142 = orr(_T_141) @[lib.scala 448:29] + reg _T_143 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_142 : @[Reg.scala 28:19] + _T_143 <= dec_tlu_mpc_halted_only_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_140 <= _T_143 @[lib.scala 451:16] + io.dec_tlu_mpc_halted_only <= _T_140 @[dec_tlu_ctl.scala 386:42] + node _T_144 = not(mpc_debug_halt_req_sync_f) @[dec_tlu_ctl.scala 390:71] + node mpc_debug_halt_req_sync_pulse = and(mpc_debug_halt_req_sync, _T_144) @[dec_tlu_ctl.scala 390:69] + node _T_145 = not(mpc_debug_run_req_sync_f) @[dec_tlu_ctl.scala 391:70] + node mpc_debug_run_req_sync_pulse = and(mpc_debug_run_req_sync, _T_145) @[dec_tlu_ctl.scala 391:68] + node _T_146 = or(mpc_halt_state_f, mpc_debug_halt_req_sync_pulse) @[dec_tlu_ctl.scala 393:48] + node _T_147 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 393:99] + node _T_148 = and(reset_delayed, _T_147) @[dec_tlu_ctl.scala 393:97] + node _T_149 = or(_T_146, _T_148) @[dec_tlu_ctl.scala 393:80] + node _T_150 = not(mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 393:125] + node _T_151 = and(_T_149, _T_150) @[dec_tlu_ctl.scala 393:123] + mpc_halt_state_ns <= _T_151 @[dec_tlu_ctl.scala 393:27] + node _T_152 = not(mpc_debug_run_ack_f) @[dec_tlu_ctl.scala 394:80] + node _T_153 = and(mpc_debug_run_req_sync_pulse, _T_152) @[dec_tlu_ctl.scala 394:78] + node _T_154 = or(mpc_run_state_f, _T_153) @[dec_tlu_ctl.scala 394:46] + node _T_155 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 394:133] + node _T_156 = and(debug_mode_status, _T_155) @[dec_tlu_ctl.scala 394:131] + node _T_157 = and(_T_154, _T_156) @[dec_tlu_ctl.scala 394:103] + mpc_run_state_ns <= _T_157 @[dec_tlu_ctl.scala 394:26] + node _T_158 = or(dbg_halt_req_final, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 397:70] + node _T_159 = or(_T_158, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 397:96] + node _T_160 = or(_T_159, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 397:121] + node _T_161 = or(dbg_halt_state_f, _T_160) @[dec_tlu_ctl.scala 397:48] + node _T_162 = not(io.dbg_resume_req) @[dec_tlu_ctl.scala 397:153] + node _T_163 = and(_T_161, _T_162) @[dec_tlu_ctl.scala 397:151] + dbg_halt_state_ns <= _T_163 @[dec_tlu_ctl.scala 397:27] + node _T_164 = or(dbg_run_state_f, io.dbg_resume_req) @[dec_tlu_ctl.scala 398:46] + node _T_165 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 398:97] + node _T_166 = and(debug_mode_status, _T_165) @[dec_tlu_ctl.scala 398:95] + node _T_167 = and(_T_164, _T_166) @[dec_tlu_ctl.scala 398:67] + dbg_run_state_ns <= _T_167 @[dec_tlu_ctl.scala 398:26] + node _T_168 = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 401:39] + node _T_169 = and(_T_168, mpc_halt_state_f) @[dec_tlu_ctl.scala 401:57] + dec_tlu_mpc_halted_only_ns <= _T_169 @[dec_tlu_ctl.scala 401:36] + node debug_brkpt_valid = or(ebreak_to_debug_mode_r_d1, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 404:59] + node _T_170 = or(debug_brkpt_valid, debug_brkpt_status_f) @[dec_tlu_ctl.scala 405:53] + node _T_171 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 405:105] + node _T_172 = and(internal_dbg_halt_mode, _T_171) @[dec_tlu_ctl.scala 405:103] + node _T_173 = and(_T_170, _T_172) @[dec_tlu_ctl.scala 405:77] + debug_brkpt_status_ns <= _T_173 @[dec_tlu_ctl.scala 405:31] + node _T_174 = and(mpc_halt_state_f, debug_mode_status) @[dec_tlu_ctl.scala 408:51] + node _T_175 = and(_T_174, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 408:78] + node _T_176 = and(_T_175, core_empty) @[dec_tlu_ctl.scala 408:104] + mpc_debug_halt_ack_ns <= _T_176 @[dec_tlu_ctl.scala 408:31] + node _T_177 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 409:59] + node _T_178 = and(mpc_debug_run_req_sync, _T_177) @[dec_tlu_ctl.scala 409:57] + node _T_179 = not(mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 409:80] + node _T_180 = and(_T_178, _T_179) @[dec_tlu_ctl.scala 409:78] + node _T_181 = and(mpc_debug_run_ack_f, mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 409:129] + node _T_182 = or(_T_180, _T_181) @[dec_tlu_ctl.scala 409:106] + mpc_debug_run_ack_ns <= _T_182 @[dec_tlu_ctl.scala 409:30] + io.mpc_debug_halt_ack <= mpc_debug_halt_ack_f @[dec_tlu_ctl.scala 412:31] + io.mpc_debug_run_ack <= mpc_debug_run_ack_f @[dec_tlu_ctl.scala 413:31] + io.debug_brkpt_status <= debug_brkpt_status_f @[dec_tlu_ctl.scala 414:31] + node _T_183 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 417:53] + node dbg_halt_req_held_ns = and(_T_183, csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 417:74] + node _T_184 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 418:48] + node _T_185 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 418:71] + node _T_186 = and(_T_184, _T_185) @[dec_tlu_ctl.scala 418:69] + dbg_halt_req_final <= _T_186 @[dec_tlu_ctl.scala 418:28] + node _T_187 = or(dbg_halt_req_final, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 421:50] + node _T_188 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 421:95] + node _T_189 = and(reset_delayed, _T_188) @[dec_tlu_ctl.scala 421:93] + node _T_190 = or(_T_187, _T_189) @[dec_tlu_ctl.scala 421:76] + node _T_191 = not(debug_mode_status) @[dec_tlu_ctl.scala 421:121] + node _T_192 = and(_T_190, _T_191) @[dec_tlu_ctl.scala 421:119] + node _T_193 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 421:149] + node debug_halt_req = and(_T_192, _T_193) @[dec_tlu_ctl.scala 421:147] + node _T_194 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 423:32] + node _T_195 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 423:75] + node _T_196 = and(mpc_run_state_ns, _T_195) @[dec_tlu_ctl.scala 423:73] + node _T_197 = not(mpc_halt_state_ns) @[dec_tlu_ctl.scala 423:117] + node _T_198 = and(dbg_run_state_ns, _T_197) @[dec_tlu_ctl.scala 423:115] + node _T_199 = or(_T_196, _T_198) @[dec_tlu_ctl.scala 423:95] + node debug_resume_req = and(_T_194, _T_199) @[dec_tlu_ctl.scala 423:52] + node _T_200 = or(debug_halt_req_f, pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 428:43] + node _T_201 = not(synchronous_flush_r) @[dec_tlu_ctl.scala 428:66] + node _T_202 = and(_T_200, _T_201) @[dec_tlu_ctl.scala 428:64] + node _T_203 = not(mret_r) @[dec_tlu_ctl.scala 428:89] + node _T_204 = and(_T_202, _T_203) @[dec_tlu_ctl.scala 428:87] + node _T_205 = not(halt_taken_f) @[dec_tlu_ctl.scala 428:99] + node _T_206 = and(_T_204, _T_205) @[dec_tlu_ctl.scala 428:97] + node _T_207 = not(dec_tlu_flush_noredir_r_d1) @[dec_tlu_ctl.scala 428:115] + node _T_208 = and(_T_206, _T_207) @[dec_tlu_ctl.scala 428:113] + node _T_209 = not(take_reset) @[dec_tlu_ctl.scala 428:145] + node take_halt = and(_T_208, _T_209) @[dec_tlu_ctl.scala 428:143] + node _T_210 = eq(dec_tlu_flush_pause_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 431:56] + node _T_211 = and(dec_tlu_flush_noredir_r_d1, _T_210) @[dec_tlu_ctl.scala 431:54] + node _T_212 = eq(csr.io.take_ext_int_start_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 431:84] + node _T_213 = and(_T_211, _T_212) @[dec_tlu_ctl.scala 431:82] + node _T_214 = eq(dbg_tlu_halted_f, UInt<1>("h00")) @[dec_tlu_ctl.scala 431:133] + node _T_215 = and(halt_taken_f, _T_214) @[dec_tlu_ctl.scala 431:131] + node _T_216 = eq(pmu_fw_tlu_halted_f, UInt<1>("h00")) @[dec_tlu_ctl.scala 431:153] + node _T_217 = and(_T_215, _T_216) @[dec_tlu_ctl.scala 431:151] + node _T_218 = eq(interrupt_valid_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 431:176] + node _T_219 = and(_T_217, _T_218) @[dec_tlu_ctl.scala 431:174] + node halt_taken = or(_T_213, _T_219) @[dec_tlu_ctl.scala 431:115] + node _T_220 = and(io.lsu_idle_any, lsu_idle_any_f) @[dec_tlu_ctl.scala 435:53] + node _T_221 = and(_T_220, io.tlu_mem.ifu_miss_state_idle) @[dec_tlu_ctl.scala 435:70] + node _T_222 = and(_T_221, ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 435:103] + node _T_223 = not(debug_halt_req) @[dec_tlu_ctl.scala 435:129] + node _T_224 = and(_T_222, _T_223) @[dec_tlu_ctl.scala 435:127] + node _T_225 = not(debug_halt_req_d1) @[dec_tlu_ctl.scala 435:147] + node _T_226 = and(_T_224, _T_225) @[dec_tlu_ctl.scala 435:145] + node _T_227 = not(io.dec_div_active) @[dec_tlu_ctl.scala 435:168] + node _T_228 = and(_T_226, _T_227) @[dec_tlu_ctl.scala 435:166] + node _T_229 = or(force_halt, _T_228) @[dec_tlu_ctl.scala 435:34] + core_empty <= _T_229 @[dec_tlu_ctl.scala 435:20] + io.dec_tlu_core_empty <= core_empty @[dec_tlu_ctl.scala 436:31] + node _T_230 = not(debug_mode_status) @[dec_tlu_ctl.scala 441:37] + node _T_231 = and(_T_230, debug_halt_req) @[dec_tlu_ctl.scala 441:63] + node _T_232 = or(_T_231, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 441:81] + node _T_233 = or(_T_232, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 441:107] + node enter_debug_halt_req = or(_T_233, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 441:132] + node _T_234 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 444:111] + node _T_235 = not(_T_234) @[dec_tlu_ctl.scala 444:106] + node _T_236 = and(debug_resume_req_f, _T_235) @[dec_tlu_ctl.scala 444:104] + node _T_237 = not(_T_236) @[dec_tlu_ctl.scala 444:83] + node _T_238 = and(debug_mode_status, _T_237) @[dec_tlu_ctl.scala 444:81] + node _T_239 = or(debug_halt_req_ns, _T_238) @[dec_tlu_ctl.scala 444:53] + internal_dbg_halt_mode <= _T_239 @[dec_tlu_ctl.scala 444:32] + node _T_240 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 447:67] + node allow_dbg_halt_csr_write = and(debug_mode_status, _T_240) @[dec_tlu_ctl.scala 447:65] + node _T_241 = and(debug_halt_req_f, core_empty) @[dec_tlu_ctl.scala 452:48] + node _T_242 = and(_T_241, halt_taken) @[dec_tlu_ctl.scala 452:61] + node _T_243 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 452:97] + node _T_244 = and(dbg_tlu_halted_f, _T_243) @[dec_tlu_ctl.scala 452:95] + node dbg_tlu_halted = or(_T_242, _T_244) @[dec_tlu_ctl.scala 452:75] + node _T_245 = not(dbg_tlu_halted) @[dec_tlu_ctl.scala 454:73] + node _T_246 = and(debug_halt_req_f, _T_245) @[dec_tlu_ctl.scala 454:71] + node _T_247 = or(enter_debug_halt_req, _T_246) @[dec_tlu_ctl.scala 454:51] + debug_halt_req_ns <= _T_247 @[dec_tlu_ctl.scala 454:27] + node _T_248 = and(debug_resume_req_f, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 455:49] + node resume_ack_ns = and(_T_248, dbg_run_state_ns) @[dec_tlu_ctl.scala 455:68] + node _T_249 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 457:61] + node _T_250 = and(io.dec_tlu_i0_valid_r, _T_249) @[dec_tlu_ctl.scala 457:59] + node _T_251 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 457:90] + node _T_252 = and(_T_250, _T_251) @[dec_tlu_ctl.scala 457:84] + node _T_253 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 457:104] + node dcsr_single_step_done = and(_T_252, _T_253) @[dec_tlu_ctl.scala 457:102] + node _T_254 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 459:66] + node _T_255 = and(debug_resume_req_f, _T_254) @[dec_tlu_ctl.scala 459:60] + node _T_256 = not(dcsr_single_step_done_f) @[dec_tlu_ctl.scala 459:111] + node _T_257 = and(dcsr_single_step_running_f, _T_256) @[dec_tlu_ctl.scala 459:109] + node dcsr_single_step_running = or(_T_255, _T_257) @[dec_tlu_ctl.scala 459:79] + node dbg_cmd_done_ns = and(io.dec_tlu_i0_valid_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 461:53] + node _T_258 = or(trigger_hit_dmode_r, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 464:57] + node _T_259 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 464:112] + node _T_260 = and(request_debug_mode_r_d1, _T_259) @[dec_tlu_ctl.scala 464:110] + node request_debug_mode_r = or(_T_258, _T_260) @[dec_tlu_ctl.scala 464:83] + node _T_261 = or(request_debug_mode_r_d1, request_debug_mode_done_f) @[dec_tlu_ctl.scala 466:64] + node _T_262 = not(dbg_tlu_halted_f) @[dec_tlu_ctl.scala 466:95] + node request_debug_mode_done = and(_T_261, _T_262) @[dec_tlu_ctl.scala 466:93] + wire _T_263 : UInt<1> + _T_263 <= UInt<1>("h00") + node _T_264 = xor(io.tlu_ifc.dec_tlu_flush_noredir_wb, _T_263) @[lib.scala 470:21] + node _T_265 = orr(_T_264) @[lib.scala 470:29] + reg _T_266 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_265 : @[Reg.scala 28:19] + _T_266 <= io.tlu_ifc.dec_tlu_flush_noredir_wb @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_263 <= _T_266 @[lib.scala 473:16] + dec_tlu_flush_noredir_r_d1 <= _T_263 @[dec_tlu_ctl.scala 468:51] + wire _T_267 : UInt + _T_267 <= UInt<1>("h00") + node _T_268 = xor(halt_taken, _T_267) @[lib.scala 448:21] + node _T_269 = orr(_T_268) @[lib.scala 448:29] + reg _T_270 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_269 : @[Reg.scala 28:19] + _T_270 <= halt_taken @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_267 <= _T_270 @[lib.scala 451:16] + halt_taken_f <= _T_267 @[dec_tlu_ctl.scala 469:65] + wire _T_271 : UInt + _T_271 <= UInt<1>("h00") + node _T_272 = xor(io.lsu_idle_any, _T_271) @[lib.scala 448:21] + node _T_273 = orr(_T_272) @[lib.scala 448:29] + reg _T_274 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_273 : @[Reg.scala 28:19] + _T_274 <= io.lsu_idle_any @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_271 <= _T_274 @[lib.scala 451:16] + lsu_idle_any_f <= _T_271 @[dec_tlu_ctl.scala 470:63] + wire _T_275 : UInt<1> + _T_275 <= UInt<1>("h00") + node _T_276 = xor(io.tlu_mem.ifu_miss_state_idle, _T_275) @[lib.scala 470:21] + node _T_277 = orr(_T_276) @[lib.scala 470:29] + reg _T_278 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_277 : @[Reg.scala 28:19] + _T_278 <= io.tlu_mem.ifu_miss_state_idle @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_275 <= _T_278 @[lib.scala 473:16] + ifu_miss_state_idle_f <= _T_275 @[dec_tlu_ctl.scala 471:53] + wire _T_279 : UInt + _T_279 <= UInt<1>("h00") + node _T_280 = xor(dbg_tlu_halted, _T_279) @[lib.scala 448:21] + node _T_281 = orr(_T_280) @[lib.scala 448:29] + reg _T_282 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_281 : @[Reg.scala 28:19] + _T_282 <= dbg_tlu_halted @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_279 <= _T_282 @[lib.scala 451:16] + dbg_tlu_halted_f <= _T_279 @[dec_tlu_ctl.scala 472:63] + wire _T_283 : UInt + _T_283 <= UInt<1>("h00") + node _T_284 = xor(resume_ack_ns, _T_283) @[lib.scala 448:21] + node _T_285 = orr(_T_284) @[lib.scala 448:29] + reg _T_286 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_285 : @[Reg.scala 28:19] + _T_286 <= resume_ack_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_283 <= _T_286 @[lib.scala 451:16] + io.dec_tlu_resume_ack <= _T_283 @[dec_tlu_ctl.scala 473:53] + wire _T_287 : UInt + _T_287 <= UInt<1>("h00") + node _T_288 = xor(debug_halt_req_ns, _T_287) @[lib.scala 448:21] + node _T_289 = orr(_T_288) @[lib.scala 448:29] + reg _T_290 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_289 : @[Reg.scala 28:19] + _T_290 <= debug_halt_req_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_287 <= _T_290 @[lib.scala 451:16] + debug_halt_req_f <= _T_287 @[dec_tlu_ctl.scala 474:63] + wire _T_291 : UInt + _T_291 <= UInt<1>("h00") + node _T_292 = xor(debug_resume_req, _T_291) @[lib.scala 448:21] + node _T_293 = orr(_T_292) @[lib.scala 448:29] + reg _T_294 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_293 : @[Reg.scala 28:19] + _T_294 <= debug_resume_req @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_291 <= _T_294 @[lib.scala 451:16] + debug_resume_req_f_raw <= _T_291 @[dec_tlu_ctl.scala 475:57] + wire _T_295 : UInt + _T_295 <= UInt<1>("h00") + node _T_296 = xor(trigger_hit_dmode_r, _T_295) @[lib.scala 448:21] + node _T_297 = orr(_T_296) @[lib.scala 448:29] + reg _T_298 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_297 : @[Reg.scala 28:19] + _T_298 <= trigger_hit_dmode_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_295 <= _T_298 @[lib.scala 451:16] + trigger_hit_dmode_r_d1 <= _T_295 @[dec_tlu_ctl.scala 476:51] + wire _T_299 : UInt + _T_299 <= UInt<1>("h00") + node _T_300 = xor(dcsr_single_step_done, _T_299) @[lib.scala 448:21] + node _T_301 = orr(_T_300) @[lib.scala 448:29] + reg _T_302 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_301 : @[Reg.scala 28:19] + _T_302 <= dcsr_single_step_done @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_299 <= _T_302 @[lib.scala 451:16] + dcsr_single_step_done_f <= _T_299 @[dec_tlu_ctl.scala 477:51] + wire _T_303 : UInt + _T_303 <= UInt<1>("h00") + node _T_304 = xor(debug_halt_req, _T_303) @[lib.scala 448:21] + node _T_305 = orr(_T_304) @[lib.scala 448:29] + reg _T_306 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_305 : @[Reg.scala 28:19] + _T_306 <= debug_halt_req @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_303 <= _T_306 @[lib.scala 451:16] + debug_halt_req_d1 <= _T_303 @[dec_tlu_ctl.scala 478:63] + wire dec_tlu_wr_pause_r_d1 : UInt + dec_tlu_wr_pause_r_d1 <= UInt<1>("h00") + node _T_307 = xor(io.dec_tlu_wr_pause_r, dec_tlu_wr_pause_r_d1) @[lib.scala 448:21] + node _T_308 = orr(_T_307) @[lib.scala 448:29] + reg _T_309 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_308 : @[Reg.scala 28:19] + _T_309 <= io.dec_tlu_wr_pause_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dec_tlu_wr_pause_r_d1 <= _T_309 @[lib.scala 451:16] + wire dec_pause_state_f : UInt + dec_pause_state_f <= UInt<1>("h00") + node _T_310 = xor(io.dec_pause_state, dec_pause_state_f) @[lib.scala 448:21] + node _T_311 = orr(_T_310) @[lib.scala 448:29] + reg _T_312 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_311 : @[Reg.scala 28:19] + _T_312 <= io.dec_pause_state @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dec_pause_state_f <= _T_312 @[lib.scala 451:16] + wire _T_313 : UInt + _T_313 <= UInt<1>("h00") + node _T_314 = xor(request_debug_mode_r, _T_313) @[lib.scala 448:21] + node _T_315 = orr(_T_314) @[lib.scala 448:29] + reg _T_316 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_315 : @[Reg.scala 28:19] + _T_316 <= request_debug_mode_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_313 <= _T_316 @[lib.scala 451:16] + request_debug_mode_r_d1 <= _T_313 @[dec_tlu_ctl.scala 481:49] + wire _T_317 : UInt + _T_317 <= UInt<1>("h00") + node _T_318 = xor(request_debug_mode_done, _T_317) @[lib.scala 448:21] + node _T_319 = orr(_T_318) @[lib.scala 448:29] + reg _T_320 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_319 : @[Reg.scala 28:19] + _T_320 <= request_debug_mode_done @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_317 <= _T_320 @[lib.scala 451:16] + request_debug_mode_done_f <= _T_317 @[dec_tlu_ctl.scala 482:49] + wire _T_321 : UInt + _T_321 <= UInt<1>("h00") + node _T_322 = xor(dcsr_single_step_running, _T_321) @[lib.scala 448:21] + node _T_323 = orr(_T_322) @[lib.scala 448:29] + reg _T_324 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_323 : @[Reg.scala 28:19] + _T_324 <= dcsr_single_step_running @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_321 <= _T_324 @[lib.scala 451:16] + dcsr_single_step_running_f <= _T_321 @[dec_tlu_ctl.scala 483:49] + wire _T_325 : UInt + _T_325 <= UInt<1>("h00") + node _T_326 = xor(io.dec_tlu_flush_pause_r, _T_325) @[lib.scala 448:21] + node _T_327 = orr(_T_326) @[lib.scala 448:29] + reg _T_328 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_327 : @[Reg.scala 28:19] + _T_328 <= io.dec_tlu_flush_pause_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_325 <= _T_328 @[lib.scala 451:16] + dec_tlu_flush_pause_r_d1 <= _T_325 @[dec_tlu_ctl.scala 484:49] + wire _T_329 : UInt + _T_329 <= UInt<1>("h00") + node _T_330 = xor(dbg_halt_req_held_ns, _T_329) @[lib.scala 448:21] + node _T_331 = orr(_T_330) @[lib.scala 448:29] + reg _T_332 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_331 : @[Reg.scala 28:19] + _T_332 <= dbg_halt_req_held_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_329 <= _T_332 @[lib.scala 451:16] + dbg_halt_req_held <= _T_329 @[dec_tlu_ctl.scala 485:57] + node _T_333 = not(io.dbg_halt_req) @[dec_tlu_ctl.scala 489:56] + node _T_334 = and(debug_resume_req_f_raw, _T_333) @[dec_tlu_ctl.scala 489:54] + debug_resume_req_f <= _T_334 @[dec_tlu_ctl.scala 489:28] + io.dec_tlu_debug_stall <= debug_halt_req_f @[dec_tlu_ctl.scala 491:41] + io.dec_tlu_dbg_halted <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 492:41] + io.dec_tlu_debug_mode <= debug_mode_status @[dec_tlu_ctl.scala 493:41] + dec_tlu_pmu_fw_halted <= pmu_fw_tlu_halted_f @[dec_tlu_ctl.scala 494:41] + node _T_335 = and(fence_i_r, internal_dbg_halt_mode) @[dec_tlu_ctl.scala 497:71] + node _T_336 = or(take_halt, _T_335) @[dec_tlu_ctl.scala 497:58] + node _T_337 = or(_T_336, io.dec_tlu_flush_pause_r) @[dec_tlu_ctl.scala 497:97] + node _T_338 = and(i0_trigger_hit_r, trigger_hit_dmode_r) @[dec_tlu_ctl.scala 497:144] + node _T_339 = or(_T_337, _T_338) @[dec_tlu_ctl.scala 497:124] + node _T_340 = or(_T_339, take_ext_int_start) @[dec_tlu_ctl.scala 497:167] + io.tlu_ifc.dec_tlu_flush_noredir_wb <= _T_340 @[dec_tlu_ctl.scala 497:45] + io.dec_tlu_flush_extint <= take_ext_int_start @[dec_tlu_ctl.scala 499:33] + node _T_341 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 502:61] + node _T_342 = and(dec_tlu_wr_pause_r_d1, _T_341) @[dec_tlu_ctl.scala 502:59] + node _T_343 = not(take_ext_int_start) @[dec_tlu_ctl.scala 502:82] + node _T_344 = and(_T_342, _T_343) @[dec_tlu_ctl.scala 502:80] + io.dec_tlu_flush_pause_r <= _T_344 @[dec_tlu_ctl.scala 502:34] + node _T_345 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 504:28] + node _T_346 = and(_T_345, dec_pause_state_f) @[dec_tlu_ctl.scala 504:48] + node _T_347 = or(ext_int_ready, ce_int_ready) @[dec_tlu_ctl.scala 504:86] + node _T_348 = or(_T_347, timer_int_ready) @[dec_tlu_ctl.scala 504:101] + node _T_349 = or(_T_348, soft_int_ready) @[dec_tlu_ctl.scala 504:119] + node _T_350 = or(_T_349, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 504:136] + node _T_351 = or(_T_350, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 504:160] + node _T_352 = or(_T_351, nmi_int_detected) @[dec_tlu_ctl.scala 504:184] + node _T_353 = or(_T_352, csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 504:203] + node _T_354 = not(_T_353) @[dec_tlu_ctl.scala 504:70] + node _T_355 = and(_T_346, _T_354) @[dec_tlu_ctl.scala 504:68] + node _T_356 = not(interrupt_valid_r_d1) @[dec_tlu_ctl.scala 504:233] + node _T_357 = and(_T_355, _T_356) @[dec_tlu_ctl.scala 504:231] + node _T_358 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 504:257] + node _T_359 = and(_T_357, _T_358) @[dec_tlu_ctl.scala 504:255] + node _T_360 = not(pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 504:277] + node _T_361 = and(_T_359, _T_360) @[dec_tlu_ctl.scala 504:275] + node _T_362 = not(halt_taken_f) @[dec_tlu_ctl.scala 504:298] + node _T_363 = and(_T_361, _T_362) @[dec_tlu_ctl.scala 504:296] + pause_expired_r <= _T_363 @[dec_tlu_ctl.scala 504:25] + node _T_364 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 506:88] + node _T_365 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_364) @[dec_tlu_ctl.scala 506:82] + node _T_366 = or(io.dec_tlu_resume_ack, dcsr_single_step_running) @[dec_tlu_ctl.scala 506:125] + node _T_367 = and(_T_365, _T_366) @[dec_tlu_ctl.scala 506:100] + node _T_368 = not(io.tlu_ifc.dec_tlu_flush_noredir_wb) @[dec_tlu_ctl.scala 506:155] + node _T_369 = and(_T_367, _T_368) @[dec_tlu_ctl.scala 506:153] + io.tlu_bp.dec_tlu_flush_leak_one_wb <= _T_369 @[dec_tlu_ctl.scala 506:45] + node _T_370 = or(ic_perr_r, iccm_sbecc_r) @[dec_tlu_ctl.scala 507:90] + node _T_371 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_370) @[dec_tlu_ctl.scala 507:77] + io.tlu_mem.dec_tlu_flush_err_wb <= _T_371 @[dec_tlu_ctl.scala 507:41] + io.dec_dbg_cmd_done <= dbg_cmd_done_ns @[dec_tlu_ctl.scala 510:29] + node _T_372 = and(illegal_r, io.dec_dbg_cmd_done) @[dec_tlu_ctl.scala 511:42] + io.dec_dbg_cmd_fail <= _T_372 @[dec_tlu_ctl.scala 511:29] + node _T_373 = bits(mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 524:48] + node _T_374 = bits(mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 524:75] + node _T_375 = bits(mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 524:102] + node _T_376 = bits(mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 524:129] + node _T_377 = cat(_T_375, _T_376) @[Cat.scala 29:58] + node _T_378 = cat(_T_373, _T_374) @[Cat.scala 29:58] + node trigger_execute = cat(_T_378, _T_377) @[Cat.scala 29:58] + node _T_379 = bits(mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 525:52] + node _T_380 = bits(mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 525:79] + node _T_381 = bits(mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 525:106] + node _T_382 = bits(mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 525:133] + node _T_383 = cat(_T_381, _T_382) @[Cat.scala 29:58] + node _T_384 = cat(_T_379, _T_380) @[Cat.scala 29:58] + node trigger_data = cat(_T_384, _T_383) @[Cat.scala 29:58] + node _T_385 = bits(mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 526:52] + node _T_386 = bits(mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 526:79] + node _T_387 = bits(mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 526:106] + node _T_388 = bits(mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 526:133] + node _T_389 = cat(_T_387, _T_388) @[Cat.scala 29:58] + node _T_390 = cat(_T_385, _T_386) @[Cat.scala 29:58] + node trigger_store = cat(_T_390, _T_389) @[Cat.scala 29:58] + node _T_391 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 529:53] + node _T_392 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 529:79] + node _T_393 = or(_T_391, _T_392) @[dec_tlu_ctl.scala 529:70] + node _T_394 = bits(mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 529:108] + node _T_395 = and(_T_393, _T_394) @[dec_tlu_ctl.scala 529:94] + node _T_396 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 530:30] + node _T_397 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 530:56] + node _T_398 = or(_T_396, _T_397) @[dec_tlu_ctl.scala 530:47] + node _T_399 = bits(mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 530:85] + node _T_400 = and(_T_398, _T_399) @[dec_tlu_ctl.scala 530:71] + node _T_401 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 531:30] + node _T_402 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 531:56] + node _T_403 = or(_T_401, _T_402) @[dec_tlu_ctl.scala 531:47] + node _T_404 = bits(mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 531:85] + node _T_405 = and(_T_403, _T_404) @[dec_tlu_ctl.scala 531:71] + node _T_406 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 532:30] + node _T_407 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 532:56] + node _T_408 = or(_T_406, _T_407) @[dec_tlu_ctl.scala 532:47] + node _T_409 = bits(mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 532:85] + node _T_410 = and(_T_408, _T_409) @[dec_tlu_ctl.scala 532:71] + node _T_411 = cat(_T_405, _T_410) @[Cat.scala 29:58] + node _T_412 = cat(_T_395, _T_400) @[Cat.scala 29:58] + node trigger_enabled = cat(_T_412, _T_411) @[Cat.scala 29:58] + node _T_413 = and(trigger_execute, trigger_data) @[dec_tlu_ctl.scala 535:62] + node _T_414 = bits(inst_acc_r_raw, 0, 0) @[Bitwise.scala 72:15] + node _T_415 = mux(_T_414, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_416 = and(_T_413, _T_415) @[dec_tlu_ctl.scala 535:77] + node _T_417 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 535:142] + node _T_418 = bits(_T_417, 0, 0) @[Bitwise.scala 72:15] + node _T_419 = mux(_T_418, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_420 = or(_T_416, _T_419) @[dec_tlu_ctl.scala 535:103] + node i0_iside_trigger_has_pri_r = not(_T_420) @[dec_tlu_ctl.scala 535:43] + node _T_421 = and(trigger_store, trigger_data) @[dec_tlu_ctl.scala 538:56] + node _T_422 = bits(lsu_i0_exc_r_raw, 0, 0) @[Bitwise.scala 72:15] + node _T_423 = mux(_T_422, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 538:71] + node i0_lsu_trigger_has_pri_r = not(_T_424) @[dec_tlu_ctl.scala 538:40] + node _T_425 = bits(io.dec_tlu_i0_valid_r, 0, 0) @[Bitwise.scala 72:15] + node _T_426 = mux(_T_425, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_427 = bits(io.dec_tlu_packet_r.i0trigger, 3, 0) @[dec_tlu_ctl.scala 543:89] + node _T_428 = and(_T_426, _T_427) @[dec_tlu_ctl.scala 543:58] + node _T_429 = and(_T_428, i0_iside_trigger_has_pri_r) @[dec_tlu_ctl.scala 543:95] + node _T_430 = and(_T_429, i0_lsu_trigger_has_pri_r) @[dec_tlu_ctl.scala 543:124] + node i0trigger_qual_r = and(_T_430, trigger_enabled) @[dec_tlu_ctl.scala 543:151] + node _T_431 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 545:64] + node _T_432 = bits(_T_431, 0, 0) @[Bitwise.scala 72:15] + node _T_433 = mux(_T_432, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_434 = not(_T_433) @[dec_tlu_ctl.scala 545:29] + node i0_trigger_r = and(_T_434, i0trigger_qual_r) @[dec_tlu_ctl.scala 545:90] + node _T_435 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 548:58] + node _T_436 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 548:78] + node _T_437 = not(_T_436) @[dec_tlu_ctl.scala 548:65] + node _T_438 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 548:108] + node _T_439 = or(_T_437, _T_438) @[dec_tlu_ctl.scala 548:94] + node _T_440 = and(_T_435, _T_439) @[dec_tlu_ctl.scala 548:62] + node _T_441 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 549:29] + node _T_442 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 549:49] + node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 549:36] + node _T_444 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 549:79] + node _T_445 = or(_T_443, _T_444) @[dec_tlu_ctl.scala 549:65] + node _T_446 = and(_T_441, _T_445) @[dec_tlu_ctl.scala 549:33] + node _T_447 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 550:29] + node _T_448 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 550:49] + node _T_449 = not(_T_448) @[dec_tlu_ctl.scala 550:36] + node _T_450 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 550:79] + node _T_451 = or(_T_449, _T_450) @[dec_tlu_ctl.scala 550:65] + node _T_452 = and(_T_447, _T_451) @[dec_tlu_ctl.scala 550:33] + node _T_453 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 551:29] + node _T_454 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 551:49] + node _T_455 = not(_T_454) @[dec_tlu_ctl.scala 551:36] + node _T_456 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 551:79] + node _T_457 = or(_T_455, _T_456) @[dec_tlu_ctl.scala 551:65] + node _T_458 = and(_T_453, _T_457) @[dec_tlu_ctl.scala 551:33] + node _T_459 = cat(_T_452, _T_458) @[Cat.scala 29:58] + node _T_460 = cat(_T_440, _T_446) @[Cat.scala 29:58] + node i0_trigger_chain_masked_r = cat(_T_460, _T_459) @[Cat.scala 29:58] + node i0_trigger_hit_raw_r = orr(i0_trigger_chain_masked_r) @[dec_tlu_ctl.scala 555:62] + i0_trigger_hit_r <= i0_trigger_hit_raw_r @[dec_tlu_ctl.scala 557:33] + node _T_461 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 561:52] + node _T_462 = bits(mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 561:83] + node _T_463 = and(_T_461, _T_462) @[dec_tlu_ctl.scala 561:69] + node _T_464 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 562:29] + node _T_465 = bits(mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 562:60] + node _T_466 = and(_T_464, _T_465) @[dec_tlu_ctl.scala 562:46] + node _T_467 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 562:91] + node _T_468 = not(_T_467) @[dec_tlu_ctl.scala 562:78] + node _T_469 = and(_T_466, _T_468) @[dec_tlu_ctl.scala 562:76] + node _T_470 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 563:29] + node _T_471 = bits(mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 563:60] + node _T_472 = and(_T_470, _T_471) @[dec_tlu_ctl.scala 563:46] + node _T_473 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 564:29] + node _T_474 = bits(mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 564:60] + node _T_475 = and(_T_473, _T_474) @[dec_tlu_ctl.scala 564:46] + node _T_476 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 564:91] + node _T_477 = not(_T_476) @[dec_tlu_ctl.scala 564:78] + node _T_478 = and(_T_475, _T_477) @[dec_tlu_ctl.scala 564:76] + node _T_479 = cat(_T_472, _T_478) @[Cat.scala 29:58] + node _T_480 = cat(_T_463, _T_469) @[Cat.scala 29:58] + node trigger_action = cat(_T_480, _T_479) @[Cat.scala 29:58] + node _T_481 = orr(i0_trigger_r) @[dec_tlu_ctl.scala 567:59] + node _T_482 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 567:65] + node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 567:63] + node _T_484 = bits(_T_483, 0, 0) @[Bitwise.scala 72:15] + node _T_485 = mux(_T_484, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_486 = bits(i0_trigger_chain_masked_r, 3, 3) @[dec_tlu_ctl.scala 567:108] + node _T_487 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 567:125] + node _T_488 = bits(i0_trigger_chain_masked_r, 1, 1) @[dec_tlu_ctl.scala 567:155] + node _T_489 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 567:172] + node _T_490 = cat(_T_488, _T_489) @[Cat.scala 29:58] + node _T_491 = cat(_T_486, _T_487) @[Cat.scala 29:58] + node _T_492 = cat(_T_491, _T_490) @[Cat.scala 29:58] + node update_hit_bit_r = and(_T_485, _T_492) @[dec_tlu_ctl.scala 567:77] + node _T_493 = and(i0_trigger_chain_masked_r, trigger_action) @[dec_tlu_ctl.scala 570:62] + node i0_trigger_action_r = orr(_T_493) @[dec_tlu_ctl.scala 570:80] + node _T_494 = and(i0_trigger_hit_r, i0_trigger_action_r) @[dec_tlu_ctl.scala 572:50] + trigger_hit_dmode_r <= _T_494 @[dec_tlu_ctl.scala 572:29] + node _T_495 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 574:60] + node mepc_trigger_hit_sel_pc_r = and(i0_trigger_hit_r, _T_495) @[dec_tlu_ctl.scala 574:58] + node _T_496 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 601:62] + node _T_497 = and(i_cpu_halt_req_sync, _T_496) @[dec_tlu_ctl.scala 601:60] + node _T_498 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 601:87] + node i_cpu_halt_req_sync_qual = and(_T_497, _T_498) @[dec_tlu_ctl.scala 601:85] + node _T_499 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 602:60] + node _T_500 = and(i_cpu_run_req_sync, _T_499) @[dec_tlu_ctl.scala 602:58] + node _T_501 = and(_T_500, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 602:83] + node _T_502 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 602:107] + node i_cpu_run_req_sync_qual = and(_T_501, _T_502) @[dec_tlu_ctl.scala 602:105] + wire i_cpu_halt_req_d1 : UInt + i_cpu_halt_req_d1 <= UInt<1>("h00") + node _T_503 = xor(i_cpu_halt_req_sync_qual, i_cpu_halt_req_d1) @[lib.scala 448:21] + node _T_504 = orr(_T_503) @[lib.scala 448:29] + reg _T_505 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_504 : @[Reg.scala 28:19] + _T_505 <= i_cpu_halt_req_sync_qual @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + i_cpu_halt_req_d1 <= _T_505 @[lib.scala 451:16] + wire i_cpu_run_req_d1_raw : UInt + i_cpu_run_req_d1_raw <= UInt<1>("h00") + node _T_506 = xor(i_cpu_run_req_sync_qual, i_cpu_run_req_d1_raw) @[lib.scala 448:21] + node _T_507 = orr(_T_506) @[lib.scala 448:29] + reg _T_508 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_507 : @[Reg.scala 28:19] + _T_508 <= i_cpu_run_req_sync_qual @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + i_cpu_run_req_d1_raw <= _T_508 @[lib.scala 451:16] + wire _T_509 : UInt + _T_509 <= UInt<1>("h00") + node _T_510 = xor(cpu_halt_status, _T_509) @[lib.scala 448:21] + node _T_511 = orr(_T_510) @[lib.scala 448:29] + reg _T_512 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_511 : @[Reg.scala 28:19] + _T_512 <= cpu_halt_status @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_509 <= _T_512 @[lib.scala 451:16] + io.o_cpu_halt_status <= _T_509 @[dec_tlu_ctl.scala 606:60] + wire _T_513 : UInt + _T_513 <= UInt<1>("h00") + node _T_514 = xor(cpu_halt_ack, _T_513) @[lib.scala 448:21] + node _T_515 = orr(_T_514) @[lib.scala 448:29] + reg _T_516 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_515 : @[Reg.scala 28:19] + _T_516 <= cpu_halt_ack @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_513 <= _T_516 @[lib.scala 451:16] + io.o_cpu_halt_ack <= _T_513 @[dec_tlu_ctl.scala 607:68] + wire _T_517 : UInt + _T_517 <= UInt<1>("h00") + node _T_518 = xor(cpu_run_ack, _T_517) @[lib.scala 448:21] + node _T_519 = orr(_T_518) @[lib.scala 448:29] + reg _T_520 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_519 : @[Reg.scala 28:19] + _T_520 <= cpu_run_ack @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_517 <= _T_520 @[lib.scala 451:16] + io.o_cpu_run_ack <= _T_517 @[dec_tlu_ctl.scala 608:68] + wire internal_pmu_fw_halt_mode_f : UInt + internal_pmu_fw_halt_mode_f <= UInt<1>("h00") + node _T_521 = xor(internal_pmu_fw_halt_mode, internal_pmu_fw_halt_mode_f) @[lib.scala 448:21] + node _T_522 = orr(_T_521) @[lib.scala 448:29] + reg _T_523 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_522 : @[Reg.scala 28:19] + _T_523 <= internal_pmu_fw_halt_mode @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + internal_pmu_fw_halt_mode_f <= _T_523 @[lib.scala 451:16] + wire _T_524 : UInt + _T_524 <= UInt<1>("h00") + node _T_525 = xor(pmu_fw_halt_req_ns, _T_524) @[lib.scala 448:21] + node _T_526 = orr(_T_525) @[lib.scala 448:29] + reg _T_527 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_526 : @[Reg.scala 28:19] + _T_527 <= pmu_fw_halt_req_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_524 <= _T_527 @[lib.scala 451:16] + pmu_fw_halt_req_f <= _T_524 @[dec_tlu_ctl.scala 610:62] + wire _T_528 : UInt + _T_528 <= UInt<1>("h00") + node _T_529 = xor(pmu_fw_tlu_halted, _T_528) @[lib.scala 448:21] + node _T_530 = orr(_T_529) @[lib.scala 448:29] + reg _T_531 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_530 : @[Reg.scala 28:19] + _T_531 <= pmu_fw_tlu_halted @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_528 <= _T_531 @[lib.scala 451:16] + pmu_fw_tlu_halted_f <= _T_528 @[dec_tlu_ctl.scala 611:60] + wire _T_532 : UInt + _T_532 <= UInt<1>("h00") + node _T_533 = xor(int_timer0_int_hold, _T_532) @[lib.scala 448:21] + node _T_534 = orr(_T_533) @[lib.scala 448:29] + reg _T_535 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_534 : @[Reg.scala 28:19] + _T_535 <= int_timer0_int_hold @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_532 <= _T_535 @[lib.scala 451:16] + int_timer0_int_hold_f <= _T_532 @[dec_tlu_ctl.scala 612:52] + wire _T_536 : UInt + _T_536 <= UInt<1>("h00") + node _T_537 = xor(int_timer1_int_hold, _T_536) @[lib.scala 448:21] + node _T_538 = orr(_T_537) @[lib.scala 448:29] + reg _T_539 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_538 : @[Reg.scala 28:19] + _T_539 <= int_timer1_int_hold @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_536 <= _T_539 @[lib.scala 451:16] + int_timer1_int_hold_f <= _T_536 @[dec_tlu_ctl.scala 613:52] + node _T_540 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 617:57] + node ext_halt_pulse = and(i_cpu_halt_req_sync_qual, _T_540) @[dec_tlu_ctl.scala 617:55] + node enter_pmu_fw_halt_req = or(ext_halt_pulse, fw_halt_req) @[dec_tlu_ctl.scala 618:53] + node _T_541 = not(pmu_fw_tlu_halted) @[dec_tlu_ctl.scala 619:77] + node _T_542 = and(pmu_fw_halt_req_f, _T_541) @[dec_tlu_ctl.scala 619:75] + node _T_543 = or(enter_pmu_fw_halt_req, _T_542) @[dec_tlu_ctl.scala 619:54] + node _T_544 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 619:100] + node _T_545 = and(_T_543, _T_544) @[dec_tlu_ctl.scala 619:98] + pmu_fw_halt_req_ns <= _T_545 @[dec_tlu_ctl.scala 619:28] + node _T_546 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 620:90] + node _T_547 = and(internal_pmu_fw_halt_mode_f, _T_546) @[dec_tlu_ctl.scala 620:88] + node _T_548 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 620:110] + node _T_549 = and(_T_547, _T_548) @[dec_tlu_ctl.scala 620:108] + node _T_550 = or(pmu_fw_halt_req_ns, _T_549) @[dec_tlu_ctl.scala 620:57] + internal_pmu_fw_halt_mode <= _T_550 @[dec_tlu_ctl.scala 620:35] + node _T_551 = and(pmu_fw_halt_req_f, core_empty) @[dec_tlu_ctl.scala 623:50] + node _T_552 = and(_T_551, halt_taken) @[dec_tlu_ctl.scala 623:63] + node _T_553 = not(enter_debug_halt_req) @[dec_tlu_ctl.scala 623:78] + node _T_554 = and(_T_552, _T_553) @[dec_tlu_ctl.scala 623:76] + node _T_555 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 623:126] + node _T_556 = and(pmu_fw_tlu_halted_f, _T_555) @[dec_tlu_ctl.scala 623:124] + node _T_557 = or(_T_554, _T_556) @[dec_tlu_ctl.scala 623:101] + node _T_558 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 623:148] + node _T_559 = and(_T_557, _T_558) @[dec_tlu_ctl.scala 623:146] + pmu_fw_tlu_halted <= _T_559 @[dec_tlu_ctl.scala 623:27] + node _T_560 = and(i_cpu_halt_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 625:44] + node _T_561 = and(io.o_cpu_halt_ack, i_cpu_halt_req_sync) @[dec_tlu_ctl.scala 625:88] + node _T_562 = or(_T_560, _T_561) @[dec_tlu_ctl.scala 625:67] + cpu_halt_ack <= _T_562 @[dec_tlu_ctl.scala 625:22] + node _T_563 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 626:51] + node _T_564 = and(pmu_fw_tlu_halted_f, _T_563) @[dec_tlu_ctl.scala 626:49] + node _T_565 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 626:96] + node _T_566 = and(io.o_cpu_halt_status, _T_565) @[dec_tlu_ctl.scala 626:94] + node _T_567 = not(debug_mode_status) @[dec_tlu_ctl.scala 626:116] + node _T_568 = and(_T_566, _T_567) @[dec_tlu_ctl.scala 626:114] + node _T_569 = or(_T_564, _T_568) @[dec_tlu_ctl.scala 626:70] + cpu_halt_status <= _T_569 @[dec_tlu_ctl.scala 626:25] + node _T_570 = not(pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 627:25] + node _T_571 = and(_T_570, i_cpu_run_req_sync) @[dec_tlu_ctl.scala 627:46] + node _T_572 = and(io.o_cpu_halt_status, i_cpu_run_req_d1_raw) @[dec_tlu_ctl.scala 627:92] + node _T_573 = or(_T_571, _T_572) @[dec_tlu_ctl.scala 627:68] + node _T_574 = and(io.o_cpu_run_ack, i_cpu_run_req_sync) @[dec_tlu_ctl.scala 627:136] + node _T_575 = or(_T_573, _T_574) @[dec_tlu_ctl.scala 627:116] + cpu_run_ack <= _T_575 @[dec_tlu_ctl.scala 627:21] + io.o_debug_mode_status <= debug_mode_status @[dec_tlu_ctl.scala 630:32] + node _T_576 = or(nmi_int_detected, timer_int_ready) @[dec_tlu_ctl.scala 633:71] + node _T_577 = or(_T_576, soft_int_ready) @[dec_tlu_ctl.scala 633:89] + node _T_578 = or(_T_577, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 633:106] + node _T_579 = or(_T_578, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 633:130] + node _T_580 = and(io.dec_pic.mhwakeup, mhwakeup_ready) @[dec_tlu_ctl.scala 633:177] + node _T_581 = or(_T_579, _T_580) @[dec_tlu_ctl.scala 633:154] + node _T_582 = and(_T_581, io.o_cpu_halt_status) @[dec_tlu_ctl.scala 633:196] + node _T_583 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 633:221] + node _T_584 = and(_T_582, _T_583) @[dec_tlu_ctl.scala 633:219] + node _T_585 = or(i_cpu_run_req_d1_raw, _T_584) @[dec_tlu_ctl.scala 633:50] + i_cpu_run_req_d1 <= _T_585 @[dec_tlu_ctl.scala 633:26] + node _T_586 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 642:62] + node lsu_exc_valid_r_raw = and(io.lsu_error_pkt_r.valid, _T_586) @[dec_tlu_ctl.scala 642:60] + lsu_i0_exc_r_raw <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 643:26] + node _T_587 = and(lsu_i0_exc_r_raw, lsu_exc_valid_r_raw) @[dec_tlu_ctl.scala 644:45] + node _T_588 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 644:69] + node _T_589 = and(_T_587, _T_588) @[dec_tlu_ctl.scala 644:67] + node _T_590 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 644:89] + node lsu_exc_valid_r = and(_T_589, _T_590) @[dec_tlu_ctl.scala 644:87] + node _T_591 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 651:54] + node _T_592 = and(io.dec_tlu_i0_valid_r, _T_591) @[dec_tlu_ctl.scala 651:52] + node _T_593 = not(io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 651:75] + node _T_594 = and(_T_593, io.lsu_error_pkt_r.bits.single_ecc_error) @[dec_tlu_ctl.scala 651:110] + node lsu_i0_rfnpc_r = and(_T_592, _T_594) @[dec_tlu_ctl.scala 651:72] + node _T_595 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 654:57] + node _T_596 = and(io.dec_tlu_i0_valid_r, _T_595) @[dec_tlu_ctl.scala 654:55] + node _T_597 = not(lsu_exc_valid_r) @[dec_tlu_ctl.scala 654:70] + node _T_598 = and(_T_596, _T_597) @[dec_tlu_ctl.scala 654:68] + node _T_599 = not(inst_acc_r) @[dec_tlu_ctl.scala 654:87] + node _T_600 = and(_T_598, _T_599) @[dec_tlu_ctl.scala 654:84] + node _T_601 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 654:101] + node _T_602 = and(_T_600, _T_601) @[dec_tlu_ctl.scala 654:99] + node _T_603 = not(request_debug_mode_r_d1) @[dec_tlu_ctl.scala 654:126] + node _T_604 = and(_T_602, _T_603) @[dec_tlu_ctl.scala 654:124] + node _T_605 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 654:153] + node tlu_i0_commit_cmt = and(_T_604, _T_605) @[dec_tlu_ctl.scala 654:151] + node _T_606 = or(rfpc_i0_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 657:43] + node _T_607 = or(_T_606, inst_acc_r) @[dec_tlu_ctl.scala 657:58] + node _T_608 = and(illegal_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 657:84] + node _T_609 = or(_T_607, _T_608) @[dec_tlu_ctl.scala 657:71] + node _T_610 = or(_T_609, i0_trigger_hit_r) @[dec_tlu_ctl.scala 657:109] + tlu_i0_kill_writeb_r <= _T_610 @[dec_tlu_ctl.scala 657:30] + io.tlu_mem.dec_tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 658:42] + node _T_611 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 663:49] + node _T_612 = and(io.dec_tlu_i0_valid_r, _T_611) @[dec_tlu_ctl.scala 663:47] + node _T_613 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 663:103] + node _T_614 = and(_T_612, _T_613) @[dec_tlu_ctl.scala 663:71] + node _T_615 = or(ic_perr_r, iccm_sbecc_r) @[dec_tlu_ctl.scala 663:156] + node _T_616 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 663:174] + node _T_617 = and(_T_615, _T_616) @[dec_tlu_ctl.scala 663:172] + node _T_618 = or(_T_614, _T_617) @[dec_tlu_ctl.scala 663:142] + node _T_619 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 663:205] + node _T_620 = and(_T_618, _T_619) @[dec_tlu_ctl.scala 663:202] + node _T_621 = not(lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 663:226] + node _T_622 = and(_T_620, _T_621) @[dec_tlu_ctl.scala 663:223] + rfpc_i0_r <= _T_622 @[dec_tlu_ctl.scala 663:19] + node _T_623 = not(io.tlu_exu.dec_tlu_flush_lower_r) @[dec_tlu_ctl.scala 666:72] + node _T_624 = and(iccm_repair_state_d1, _T_623) @[dec_tlu_ctl.scala 666:70] + node _T_625 = or(iccm_sbecc_r, _T_624) @[dec_tlu_ctl.scala 666:46] + iccm_repair_state_ns <= _T_625 @[dec_tlu_ctl.scala 666:30] + node _T_626 = and(tlu_i0_commit_cmt, iccm_repair_state_d1) @[dec_tlu_ctl.scala 672:57] + node _T_627 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 672:93] + node _T_628 = or(_T_627, mret_r) @[dec_tlu_ctl.scala 672:103] + node _T_629 = or(_T_628, take_reset) @[dec_tlu_ctl.scala 672:112] + node _T_630 = or(_T_629, illegal_r) @[dec_tlu_ctl.scala 672:125] + node _T_631 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 672:181] + node _T_632 = and(dec_csr_wen_r_mod, _T_631) @[dec_tlu_ctl.scala 672:158] + node _T_633 = or(_T_630, _T_632) @[dec_tlu_ctl.scala 672:137] + node _T_634 = not(_T_633) @[dec_tlu_ctl.scala 672:82] + node iccm_repair_state_rfnpc = and(_T_626, _T_634) @[dec_tlu_ctl.scala 672:80] + wire dec_tlu_br0_error_r : UInt<1> + dec_tlu_br0_error_r <= UInt<1>("h00") + wire dec_tlu_br0_start_error_r : UInt<1> + dec_tlu_br0_start_error_r <= UInt<1>("h00") + wire dec_tlu_br0_v_r : UInt<1> + dec_tlu_br0_v_r <= UInt<1>("h00") + node _T_635 = and(io.tlu_exu.exu_i0_br_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 679:69] + node _T_636 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 679:95] + node _T_637 = and(_T_635, _T_636) @[dec_tlu_ctl.scala 679:93] + dec_tlu_br0_error_r <= _T_637 @[dec_tlu_ctl.scala 679:37] + node _T_638 = and(io.tlu_exu.exu_i0_br_start_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 680:81] + node _T_639 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 680:107] + node _T_640 = and(_T_638, _T_639) @[dec_tlu_ctl.scala 680:105] + dec_tlu_br0_start_error_r <= _T_640 @[dec_tlu_ctl.scala 680:43] + node _T_641 = and(io.tlu_exu.exu_i0_br_valid_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 681:65] + node _T_642 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 681:91] + node _T_643 = and(_T_641, _T_642) @[dec_tlu_ctl.scala 681:89] + node _T_644 = not(io.tlu_exu.exu_i0_br_mp_r) @[dec_tlu_ctl.scala 681:116] + node _T_645 = not(io.tlu_exu.exu_pmu_i0_br_ataken) @[dec_tlu_ctl.scala 681:145] + node _T_646 = or(_T_644, _T_645) @[dec_tlu_ctl.scala 681:143] + node _T_647 = and(_T_643, _T_646) @[dec_tlu_ctl.scala 681:113] + dec_tlu_br0_v_r <= _T_647 @[dec_tlu_ctl.scala 681:33] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist <= io.tlu_exu.exu_i0_br_hist_r @[dec_tlu_ctl.scala 684:73] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 685:73] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 686:73] + io.tlu_bp.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[dec_tlu_ctl.scala 687:73] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[dec_tlu_ctl.scala 688:73] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle <= io.tlu_exu.exu_i0_br_middle_r @[dec_tlu_ctl.scala 689:81] + node _T_648 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 703:57] + node _T_649 = and(_T_648, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 703:70] + node _T_650 = eq(i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 703:96] + node _T_651 = and(_T_649, _T_650) @[dec_tlu_ctl.scala 703:94] + node _T_652 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 703:121] + node _T_653 = not(_T_652) @[dec_tlu_ctl.scala 703:116] + node _T_654 = and(_T_651, _T_653) @[dec_tlu_ctl.scala 703:114] + node _T_655 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 703:138] + node _T_656 = and(_T_654, _T_655) @[dec_tlu_ctl.scala 703:136] + ebreak_r <= _T_656 @[dec_tlu_ctl.scala 703:19] + node _T_657 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h09")) @[dec_tlu_ctl.scala 704:57] + node _T_658 = and(_T_657, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 704:70] + node _T_659 = eq(i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 704:96] + node _T_660 = and(_T_658, _T_659) @[dec_tlu_ctl.scala 704:94] + node _T_661 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 704:116] + node _T_662 = and(_T_660, _T_661) @[dec_tlu_ctl.scala 704:114] + ecall_r <= _T_662 @[dec_tlu_ctl.scala 704:19] + node _T_663 = not(io.dec_tlu_packet_r.legal) @[dec_tlu_ctl.scala 705:23] + node _T_664 = and(_T_663, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 705:52] + node _T_665 = eq(i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 705:78] + node _T_666 = and(_T_664, _T_665) @[dec_tlu_ctl.scala 705:76] + node _T_667 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 705:98] + node _T_668 = and(_T_666, _T_667) @[dec_tlu_ctl.scala 705:96] + illegal_r <= _T_668 @[dec_tlu_ctl.scala 705:19] + node _T_669 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h0c")) @[dec_tlu_ctl.scala 706:57] + node _T_670 = and(_T_669, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 706:70] + node _T_671 = eq(i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 706:96] + node _T_672 = and(_T_670, _T_671) @[dec_tlu_ctl.scala 706:94] + node _T_673 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 706:116] + node _T_674 = and(_T_672, _T_673) @[dec_tlu_ctl.scala 706:114] + mret_r <= _T_674 @[dec_tlu_ctl.scala 706:19] + node _T_675 = and(io.dec_tlu_packet_r.fence_i, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 708:55] + node _T_676 = eq(i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 708:81] + node _T_677 = and(_T_675, _T_676) @[dec_tlu_ctl.scala 708:79] + node _T_678 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 708:102] + node _T_679 = and(_T_677, _T_678) @[dec_tlu_ctl.scala 708:100] + fence_i_r <= _T_679 @[dec_tlu_ctl.scala 708:22] + node _T_680 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 709:49] + node _T_681 = and(ifu_ic_error_start_f, _T_680) @[dec_tlu_ctl.scala 709:47] + node _T_682 = eq(debug_mode_status, UInt<1>("h00")) @[dec_tlu_ctl.scala 709:78] + node _T_683 = or(_T_682, dcsr_single_step_running) @[dec_tlu_ctl.scala 709:104] + node _T_684 = and(_T_681, _T_683) @[dec_tlu_ctl.scala 709:75] + node _T_685 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 709:134] + node _T_686 = and(_T_684, _T_685) @[dec_tlu_ctl.scala 709:132] + ic_perr_r <= _T_686 @[dec_tlu_ctl.scala 709:22] + node _T_687 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 710:57] + node _T_688 = and(ifu_iccm_rd_ecc_single_err_f, _T_687) @[dec_tlu_ctl.scala 710:55] + node _T_689 = eq(debug_mode_status, UInt<1>("h00")) @[dec_tlu_ctl.scala 710:86] + node _T_690 = or(_T_689, dcsr_single_step_running) @[dec_tlu_ctl.scala 710:112] + node _T_691 = and(_T_688, _T_690) @[dec_tlu_ctl.scala 710:83] + node _T_692 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 710:142] + node _T_693 = and(_T_691, _T_692) @[dec_tlu_ctl.scala 710:140] + iccm_sbecc_r <= _T_693 @[dec_tlu_ctl.scala 710:22] + node _T_694 = and(io.dec_tlu_packet_r.icaf, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 712:54] + inst_acc_r_raw <= _T_694 @[dec_tlu_ctl.scala 712:25] + node _T_695 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 713:40] + node _T_696 = and(inst_acc_r_raw, _T_695) @[dec_tlu_ctl.scala 713:38] + node _T_697 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 713:53] + node _T_698 = and(_T_696, _T_697) @[dec_tlu_ctl.scala 713:51] + inst_acc_r <= _T_698 @[dec_tlu_ctl.scala 713:20] + node _T_699 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 716:69] + node _T_700 = and(_T_699, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 716:82] + node _T_701 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 716:108] + node _T_702 = and(_T_700, _T_701) @[dec_tlu_ctl.scala 716:106] + node _T_703 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 716:132] + node _T_704 = and(_T_702, _T_703) @[dec_tlu_ctl.scala 716:126] + node _T_705 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 716:149] + node _T_706 = and(_T_704, _T_705) @[dec_tlu_ctl.scala 716:147] + ebreak_to_debug_mode_r <= _T_706 @[dec_tlu_ctl.scala 716:32] + reg _T_707 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 718:64] + _T_707 <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 718:64] + ebreak_to_debug_mode_r_d1 <= _T_707 @[dec_tlu_ctl.scala 718:34] + io.tlu_mem.dec_tlu_fence_i_wb <= fence_i_r @[dec_tlu_ctl.scala 719:39] + int_exc.io.free_l2clk <= io.free_l2clk @[dec_tlu_ctl.scala 722:49] + int_exc.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 723:49] + int_exc.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[dec_tlu_ctl.scala 724:49] + int_exc.io.mstatus_mie_ns <= mstatus_mie_ns @[dec_tlu_ctl.scala 725:49] + int_exc.io.mip <= mip @[dec_tlu_ctl.scala 726:49] + int_exc.io.mie_ns <= mie_ns @[dec_tlu_ctl.scala 727:49] + int_exc.io.mret_r <= mret_r @[dec_tlu_ctl.scala 728:49] + int_exc.io.pmu_fw_tlu_halted_f <= pmu_fw_tlu_halted_f @[dec_tlu_ctl.scala 729:49] + int_exc.io.int_timer0_int_hold_f <= int_timer0_int_hold_f @[dec_tlu_ctl.scala 730:49] + int_exc.io.int_timer1_int_hold_f <= int_timer1_int_hold_f @[dec_tlu_ctl.scala 731:49] + int_exc.io.internal_dbg_halt_mode_f <= debug_mode_status @[dec_tlu_ctl.scala 732:49] + int_exc.io.dcsr_single_step_running <= dcsr_single_step_running @[dec_tlu_ctl.scala 733:49] + int_exc.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 734:49] + int_exc.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 735:49] + int_exc.io.internal_pmu_fw_halt_mode <= internal_pmu_fw_halt_mode @[dec_tlu_ctl.scala 736:49] + int_exc.io.i_cpu_halt_req_d1 <= i_cpu_halt_req_d1 @[dec_tlu_ctl.scala 737:49] + int_exc.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 738:49] + int_exc.io.lsu_fir_error <= io.lsu_fir_error @[dec_tlu_ctl.scala 739:49] + int_exc.io.csr_pkt.legal <= csr_pkt.legal @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.postsync <= csr_pkt.postsync @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.presync <= csr_pkt.presync @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[dec_tlu_ctl.scala 740:49] + int_exc.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[dec_tlu_ctl.scala 741:49] + int_exc.io.lsu_fastint_stall_any <= io.lsu_fastint_stall_any @[dec_tlu_ctl.scala 742:49] + int_exc.io.reset_delayed <= reset_delayed @[dec_tlu_ctl.scala 743:49] + int_exc.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 744:49] + int_exc.io.nmi_int_detected <= nmi_int_detected @[dec_tlu_ctl.scala 745:49] + int_exc.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[dec_tlu_ctl.scala 746:49] + int_exc.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[dec_tlu_ctl.scala 747:49] + int_exc.io.dcsr <= dcsr @[dec_tlu_ctl.scala 748:49] + int_exc.io.mtvec <= mtvec @[dec_tlu_ctl.scala 749:49] + int_exc.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 750:49] + int_exc.io.i0_trigger_hit_r <= i0_trigger_hit_r @[dec_tlu_ctl.scala 751:49] + int_exc.io.pause_expired_r <= pause_expired_r @[dec_tlu_ctl.scala 752:49] + int_exc.io.nmi_vec <= io.nmi_vec @[dec_tlu_ctl.scala 753:49] + int_exc.io.lsu_i0_rfnpc_r <= lsu_i0_rfnpc_r @[dec_tlu_ctl.scala 754:49] + int_exc.io.fence_i_r <= fence_i_r @[dec_tlu_ctl.scala 755:49] + int_exc.io.iccm_repair_state_rfnpc <= iccm_repair_state_rfnpc @[dec_tlu_ctl.scala 756:49] + int_exc.io.i_cpu_run_req_d1 <= i_cpu_run_req_d1 @[dec_tlu_ctl.scala 757:49] + int_exc.io.rfpc_i0_r <= rfpc_i0_r @[dec_tlu_ctl.scala 758:49] + int_exc.io.lsu_exc_valid_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 759:49] + int_exc.io.trigger_hit_dmode_r <= trigger_hit_dmode_r @[dec_tlu_ctl.scala 760:49] + int_exc.io.take_halt <= take_halt @[dec_tlu_ctl.scala 761:49] + int_exc.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 762:49] + int_exc.io.lsu_fir_addr <= io.lsu_fir_addr @[dec_tlu_ctl.scala 763:49] + int_exc.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[dec_tlu_ctl.scala 764:49] + int_exc.io.npc_r <= npc_r @[dec_tlu_ctl.scala 765:49] + int_exc.io.mepc <= mepc @[dec_tlu_ctl.scala 766:49] + int_exc.io.debug_resume_req_f <= debug_resume_req_f @[dec_tlu_ctl.scala 767:49] + int_exc.io.dpc <= dpc @[dec_tlu_ctl.scala 768:49] + int_exc.io.npc_r_d1 <= npc_r_d1 @[dec_tlu_ctl.scala 769:49] + int_exc.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 770:49] + int_exc.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[dec_tlu_ctl.scala 771:49] + int_exc.io.ebreak_r <= ebreak_r @[dec_tlu_ctl.scala 772:49] + int_exc.io.ecall_r <= ecall_r @[dec_tlu_ctl.scala 773:49] + int_exc.io.illegal_r <= illegal_r @[dec_tlu_ctl.scala 774:49] + int_exc.io.inst_acc_r <= inst_acc_r @[dec_tlu_ctl.scala 775:49] + int_exc.io.lsu_i0_exc_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 776:49] + int_exc.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 777:49] + int_exc.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 777:49] + int_exc.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 777:49] + int_exc.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 777:49] + int_exc.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 777:49] + int_exc.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 777:49] + int_exc.io.dec_tlu_wr_pause_r_d1 <= dec_tlu_wr_pause_r_d1 @[dec_tlu_ctl.scala 778:42] + mhwakeup_ready <= int_exc.io.mhwakeup_ready @[dec_tlu_ctl.scala 780:43] + ext_int_ready <= int_exc.io.ext_int_ready @[dec_tlu_ctl.scala 781:43] + ce_int_ready <= int_exc.io.ce_int_ready @[dec_tlu_ctl.scala 782:43] + soft_int_ready <= int_exc.io.soft_int_ready @[dec_tlu_ctl.scala 783:43] + timer_int_ready <= int_exc.io.timer_int_ready @[dec_tlu_ctl.scala 784:43] + int_timer0_int_hold <= int_exc.io.int_timer0_int_hold @[dec_tlu_ctl.scala 785:43] + int_timer1_int_hold <= int_exc.io.int_timer1_int_hold @[dec_tlu_ctl.scala 786:43] + internal_dbg_halt_timers <= int_exc.io.internal_dbg_halt_timers @[dec_tlu_ctl.scala 787:43] + take_ext_int_start <= int_exc.io.take_ext_int_start @[dec_tlu_ctl.scala 788:43] + int_exc.io.ext_int_freeze_d1 <= csr.io.ext_int_freeze_d1 @[dec_tlu_ctl.scala 789:42] + int_exc.io.take_ext_int_start_d1 <= csr.io.take_ext_int_start_d1 @[dec_tlu_ctl.scala 790:44] + int_exc.io.take_ext_int_start_d2 <= csr.io.take_ext_int_start_d2 @[dec_tlu_ctl.scala 791:44] + int_exc.io.take_ext_int_start_d3 <= csr.io.take_ext_int_start_d3 @[dec_tlu_ctl.scala 792:44] + ext_int_freeze <= int_exc.io.ext_int_freeze @[dec_tlu_ctl.scala 796:43] + take_ext_int <= int_exc.io.take_ext_int @[dec_tlu_ctl.scala 797:43] + fast_int_meicpct <= int_exc.io.fast_int_meicpct @[dec_tlu_ctl.scala 798:43] + ignore_ext_int_due_to_lsu_stall <= int_exc.io.ignore_ext_int_due_to_lsu_stall @[dec_tlu_ctl.scala 799:43] + take_ce_int <= int_exc.io.take_ce_int @[dec_tlu_ctl.scala 800:43] + take_soft_int <= int_exc.io.take_soft_int @[dec_tlu_ctl.scala 801:43] + take_timer_int <= int_exc.io.take_timer_int @[dec_tlu_ctl.scala 802:43] + take_int_timer0_int <= int_exc.io.take_int_timer0_int @[dec_tlu_ctl.scala 803:43] + take_int_timer1_int <= int_exc.io.take_int_timer1_int @[dec_tlu_ctl.scala 804:43] + take_reset <= int_exc.io.take_reset @[dec_tlu_ctl.scala 805:43] + take_nmi <= int_exc.io.take_nmi @[dec_tlu_ctl.scala 806:43] + synchronous_flush_r <= int_exc.io.synchronous_flush_r @[dec_tlu_ctl.scala 807:43] + tlu_flush_lower_r <= int_exc.io.tlu_flush_lower_r @[dec_tlu_ctl.scala 808:43] + io.dec_tlu_flush_lower_wb <= int_exc.io.dec_tlu_flush_lower_wb @[dec_tlu_ctl.scala 809:46] + io.tlu_exu.dec_tlu_flush_lower_r <= int_exc.io.dec_tlu_flush_lower_r @[dec_tlu_ctl.scala 810:54] + io.tlu_exu.dec_tlu_flush_path_r <= int_exc.io.dec_tlu_flush_path_r @[dec_tlu_ctl.scala 811:54] + interrupt_valid_r_d1 <= int_exc.io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 812:43] + exc_or_int_valid_r_d1 <= int_exc.io.exc_or_int_valid_r_d1 @[dec_tlu_ctl.scala 813:43] + take_nmi_r_d1 <= int_exc.io.take_nmi_r_d1 @[dec_tlu_ctl.scala 814:43] + pause_expired_wb <= int_exc.io.pause_expired_wb @[dec_tlu_ctl.scala 815:43] + interrupt_valid_r <= int_exc.io.interrupt_valid_r @[dec_tlu_ctl.scala 816:43] + csr.io.ext_int_freeze <= int_exc.io.ext_int_freeze @[dec_tlu_ctl.scala 820:32] + csr.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 821:50] + csr.io.free_l2clk <= io.free_l2clk @[dec_tlu_ctl.scala 822:50] + csr.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 823:50] + csr.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 824:50] + csr.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 825:50] + csr.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 826:50] + csr.io.dec_csr_wen_unq_d <= io.dec_csr_wen_unq_d @[dec_tlu_ctl.scala 827:50] + csr.io.dec_i0_decode_d <= io.dec_i0_decode_d @[dec_tlu_ctl.scala 828:50] + csr.io.ifu_ic_debug_rd_data_valid <= io.tlu_mem.ifu_ic_debug_rd_data_valid @[dec_tlu_ctl.scala 829:50] + csr.io.ifu_pmu_bus_trxn <= io.tlu_mem.ifu_pmu_bus_trxn @[dec_tlu_ctl.scala 830:50] + csr.io.dma_iccm_stall_any <= io.tlu_dma.dma_iccm_stall_any @[dec_tlu_ctl.scala 831:50] + csr.io.dma_dccm_stall_any <= io.tlu_dma.dma_dccm_stall_any @[dec_tlu_ctl.scala 832:50] + csr.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec_tlu_ctl.scala 833:50] + csr.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[dec_tlu_ctl.scala 834:50] + csr.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[dec_tlu_ctl.scala 835:50] + csr.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[dec_tlu_ctl.scala 836:50] + csr.io.ifu_pmu_fetch_stall <= io.tlu_ifc.ifu_pmu_fetch_stall @[dec_tlu_ctl.scala 837:50] + csr.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec_tlu_ctl.scala 838:50] + csr.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[dec_tlu_ctl.scala 838:50] + csr.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec_tlu_ctl.scala 838:50] + csr.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[dec_tlu_ctl.scala 838:50] + csr.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[dec_tlu_ctl.scala 838:50] + csr.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[dec_tlu_ctl.scala 838:50] + csr.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[dec_tlu_ctl.scala 838:50] + csr.io.dec_tlu_packet_r.icaf_second <= io.dec_tlu_packet_r.icaf_second @[dec_tlu_ctl.scala 838:50] + csr.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[dec_tlu_ctl.scala 838:50] + csr.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[dec_tlu_ctl.scala 838:50] + csr.io.exu_pmu_i0_br_ataken <= io.tlu_exu.exu_pmu_i0_br_ataken @[dec_tlu_ctl.scala 839:50] + csr.io.exu_pmu_i0_br_misp <= io.tlu_exu.exu_pmu_i0_br_misp @[dec_tlu_ctl.scala 840:50] + csr.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[dec_tlu_ctl.scala 841:50] + csr.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[dec_tlu_ctl.scala 842:50] + csr.io.exu_pmu_i0_pc4 <= io.tlu_exu.exu_pmu_i0_pc4 @[dec_tlu_ctl.scala 843:50] + csr.io.ifu_pmu_ic_miss <= io.tlu_mem.ifu_pmu_ic_miss @[dec_tlu_ctl.scala 844:50] + csr.io.ifu_pmu_ic_hit <= io.tlu_mem.ifu_pmu_ic_hit @[dec_tlu_ctl.scala 845:50] + csr.io.dec_csr_wen_r <= io.dec_csr_wen_r @[dec_tlu_ctl.scala 846:50] + csr.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[dec_tlu_ctl.scala 847:50] + csr.io.dma_pmu_dccm_write <= io.tlu_dma.dma_pmu_dccm_write @[dec_tlu_ctl.scala 848:50] + csr.io.dma_pmu_dccm_read <= io.tlu_dma.dma_pmu_dccm_read @[dec_tlu_ctl.scala 849:50] + csr.io.dma_pmu_any_write <= io.tlu_dma.dma_pmu_any_write @[dec_tlu_ctl.scala 850:50] + csr.io.dma_pmu_any_read <= io.tlu_dma.dma_pmu_any_read @[dec_tlu_ctl.scala 851:50] + csr.io.lsu_pmu_bus_busy <= io.tlu_busbuff.lsu_pmu_bus_busy @[dec_tlu_ctl.scala 852:50] + csr.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[dec_tlu_ctl.scala 853:50] + csr.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 854:50] + csr.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[dec_tlu_ctl.scala 855:50] + csr.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[dec_tlu_ctl.scala 856:50] + csr.io.ifu_pmu_bus_busy <= io.tlu_mem.ifu_pmu_bus_busy @[dec_tlu_ctl.scala 857:50] + csr.io.lsu_pmu_bus_error <= io.tlu_busbuff.lsu_pmu_bus_error @[dec_tlu_ctl.scala 858:50] + csr.io.ifu_pmu_bus_error <= io.tlu_mem.ifu_pmu_bus_error @[dec_tlu_ctl.scala 859:50] + csr.io.lsu_pmu_bus_misaligned <= io.tlu_busbuff.lsu_pmu_bus_misaligned @[dec_tlu_ctl.scala 860:50] + csr.io.lsu_pmu_bus_trxn <= io.tlu_busbuff.lsu_pmu_bus_trxn @[dec_tlu_ctl.scala 861:50] + csr.io.ifu_ic_debug_rd_data <= io.tlu_mem.ifu_ic_debug_rd_data @[dec_tlu_ctl.scala 862:50] + csr.io.pic_pl <= io.dec_pic.pic_pl @[dec_tlu_ctl.scala 863:50] + csr.io.pic_claimid <= io.dec_pic.pic_claimid @[dec_tlu_ctl.scala 864:50] + csr.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[dec_tlu_ctl.scala 865:50] + csr.io.lsu_imprecise_error_addr_any <= io.tlu_busbuff.lsu_imprecise_error_addr_any @[dec_tlu_ctl.scala 866:50] + csr.io.lsu_imprecise_error_load_any <= io.tlu_busbuff.lsu_imprecise_error_load_any @[dec_tlu_ctl.scala 867:50] + csr.io.lsu_imprecise_error_store_any <= io.tlu_busbuff.lsu_imprecise_error_store_any @[dec_tlu_ctl.scala 868:50] + csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 869:50] + csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 870:50] + csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 870:50] + csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 870:50] + csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 870:50] + csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 870:50] + csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 870:50] + csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 871:50] + csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 872:50] + csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 873:50] + csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 874:50] + csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 875:50] + csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 876:50] + csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 877:50] + io.dec_pic.dec_tlu_meicurpl <= csr.io.dec_tlu_meicurpl @[dec_tlu_ctl.scala 878:58] + io.tlu_exu.dec_tlu_meihap <= csr.io.dec_tlu_meihap @[dec_tlu_ctl.scala 879:58] + io.dec_pic.dec_tlu_meipt <= csr.io.dec_tlu_meipt @[dec_tlu_ctl.scala 880:58] + io.dec_tlu_int_valid_wb1 <= csr.io.dec_tlu_int_valid_wb1 @[dec_tlu_ctl.scala 881:50] + io.dec_tlu_i0_exc_valid_wb1 <= csr.io.dec_tlu_i0_exc_valid_wb1 @[dec_tlu_ctl.scala 882:50] + io.dec_tlu_i0_valid_wb1 <= csr.io.dec_tlu_i0_valid_wb1 @[dec_tlu_ctl.scala 883:50] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[dec_tlu_ctl.scala 884:58] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[dec_tlu_ctl.scala 884:58] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics <= csr.io.dec_tlu_ic_diag_pkt.icache_dicawics @[dec_tlu_ctl.scala 884:58] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata <= csr.io.dec_tlu_ic_diag_pkt.icache_wrdata @[dec_tlu_ctl.scala 884:58] + io.trigger_pkt_any[0].tdata2 <= csr.io.trigger_pkt_any[0].tdata2 @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[0].m <= csr.io.trigger_pkt_any[0].m @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[0].match_pkt <= csr.io.trigger_pkt_any[0].match_pkt @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[1].match_pkt <= csr.io.trigger_pkt_any[1].match_pkt @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[2].match_pkt <= csr.io.trigger_pkt_any[2].match_pkt @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[3].match_pkt <= csr.io.trigger_pkt_any[3].match_pkt @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[dec_tlu_ctl.scala 885:46] + io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[dec_tlu_ctl.scala 886:46] + io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[dec_tlu_ctl.scala 887:46] + io.dec_tlu_perfcnt0 <= csr.io.dec_tlu_perfcnt0 @[dec_tlu_ctl.scala 888:46] + io.dec_tlu_perfcnt1 <= csr.io.dec_tlu_perfcnt1 @[dec_tlu_ctl.scala 889:46] + io.dec_tlu_perfcnt2 <= csr.io.dec_tlu_perfcnt2 @[dec_tlu_ctl.scala 890:46] + io.dec_tlu_perfcnt3 <= csr.io.dec_tlu_perfcnt3 @[dec_tlu_ctl.scala 891:46] + io.dec_tlu_misc_clk_override <= csr.io.dec_tlu_misc_clk_override @[dec_tlu_ctl.scala 892:46] + io.dec_tlu_picio_clk_override <= csr.io.dec_tlu_picio_clk_override @[dec_tlu_ctl.scala 893:46] + io.dec_tlu_dec_clk_override <= csr.io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 894:46] + io.dec_tlu_ifu_clk_override <= csr.io.dec_tlu_ifu_clk_override @[dec_tlu_ctl.scala 895:46] + io.dec_tlu_lsu_clk_override <= csr.io.dec_tlu_lsu_clk_override @[dec_tlu_ctl.scala 896:46] + io.dec_tlu_bus_clk_override <= csr.io.dec_tlu_bus_clk_override @[dec_tlu_ctl.scala 897:46] + io.dec_tlu_pic_clk_override <= csr.io.dec_tlu_pic_clk_override @[dec_tlu_ctl.scala 898:46] + io.dec_tlu_dccm_clk_override <= csr.io.dec_tlu_dccm_clk_override @[dec_tlu_ctl.scala 899:46] + io.dec_tlu_icm_clk_override <= csr.io.dec_tlu_icm_clk_override @[dec_tlu_ctl.scala 900:46] + io.dec_csr_rddata_d <= csr.io.dec_csr_rddata_d @[dec_tlu_ctl.scala 901:46] + io.dec_tlu_pipelining_disable <= csr.io.dec_tlu_pipelining_disable @[dec_tlu_ctl.scala 902:46] + io.dec_tlu_wr_pause_r <= csr.io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 903:46] + io.tlu_ifc.dec_tlu_mrac_ff <= csr.io.dec_tlu_mrac_ff @[dec_tlu_ctl.scala 904:54] + io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= csr.io.dec_tlu_wb_coalescing_disable @[dec_tlu_ctl.scala 905:58] + io.tlu_bp.dec_tlu_bpred_disable <= csr.io.dec_tlu_bpred_disable @[dec_tlu_ctl.scala 906:53] + io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= csr.io.dec_tlu_sideeffect_posted_disable @[dec_tlu_ctl.scala 907:58] + io.tlu_mem.dec_tlu_core_ecc_disable <= csr.io.dec_tlu_core_ecc_disable @[dec_tlu_ctl.scala 908:54] + io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= csr.io.dec_tlu_external_ldfwd_disable @[dec_tlu_ctl.scala 909:58] + io.tlu_dma.dec_tlu_dma_qos_prty <= csr.io.dec_tlu_dma_qos_prty @[dec_tlu_ctl.scala 910:54] + io.dec_tlu_trace_disable <= csr.io.dec_tlu_trace_disable @[dec_tlu_ctl.scala 911:49] + csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 912:50] + csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 913:50] + csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 913:50] + csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 913:50] + csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 913:50] + csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 913:50] + csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 913:50] + csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 914:50] + csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 915:50] + csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 916:50] + csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 917:50] + csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 918:50] + csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 919:50] + csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 920:50] + csr.io.rfpc_i0_r <= rfpc_i0_r @[dec_tlu_ctl.scala 923:45] + csr.io.i0_trigger_hit_r <= i0_trigger_hit_r @[dec_tlu_ctl.scala 924:45] + csr.io.exc_or_int_valid_r <= int_exc.io.exc_or_int_valid_r @[dec_tlu_ctl.scala 925:45] + csr.io.mret_r <= mret_r @[dec_tlu_ctl.scala 926:45] + csr.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[dec_tlu_ctl.scala 927:45] + csr.io.dec_timer_t0_pulse <= int_timers.io.dec_timer_t0_pulse @[dec_tlu_ctl.scala 928:45] + csr.io.dec_timer_t1_pulse <= int_timers.io.dec_timer_t1_pulse @[dec_tlu_ctl.scala 929:45] + csr.io.timer_int_sync <= timer_int_sync @[dec_tlu_ctl.scala 930:45] + csr.io.soft_int_sync <= soft_int_sync @[dec_tlu_ctl.scala 931:45] + csr.io.csr_wr_clk <= clock @[dec_tlu_ctl.scala 932:45] + csr.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 933:45] + csr.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 934:45] + csr.io.lsu_fir_error <= io.lsu_fir_error @[dec_tlu_ctl.scala 935:45] + csr.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 936:45] + csr.io.dec_tlu_flush_noredir_r_d1 <= dec_tlu_flush_noredir_r_d1 @[dec_tlu_ctl.scala 937:45] + csr.io.tlu_flush_path_r_d1 <= int_exc.io.tlu_flush_path_r_d1 @[dec_tlu_ctl.scala 938:45] + csr.io.reset_delayed <= reset_delayed @[dec_tlu_ctl.scala 939:45] + csr.io.interrupt_valid_r <= interrupt_valid_r @[dec_tlu_ctl.scala 940:45] + csr.io.i0_exception_valid_r <= int_exc.io.i0_exception_valid_r @[dec_tlu_ctl.scala 941:45] + csr.io.lsu_exc_valid_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 942:45] + csr.io.mepc_trigger_hit_sel_pc_r <= mepc_trigger_hit_sel_pc_r @[dec_tlu_ctl.scala 943:45] + csr.io.lsu_single_ecc_error_r <= io.lsu_single_ecc_error_incr @[dec_tlu_ctl.scala 944:45] + csr.io.e4e5_int_clk <= clock @[dec_tlu_ctl.scala 945:45] + csr.io.lsu_i0_exc_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 946:45] + csr.io.inst_acc_r <= inst_acc_r @[dec_tlu_ctl.scala 947:45] + csr.io.inst_acc_second_r <= io.dec_tlu_packet_r.icaf_second @[dec_tlu_ctl.scala 948:45] + csr.io.take_nmi <= take_nmi @[dec_tlu_ctl.scala 949:45] + csr.io.lsu_error_pkt_addr_r <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 950:45] + csr.io.exc_cause_r <= int_exc.io.exc_cause_r @[dec_tlu_ctl.scala 951:45] + csr.io.i0_valid_wb <= int_exc.io.i0_valid_wb @[dec_tlu_ctl.scala 952:45] + csr.io.exc_or_int_valid_r_d1 <= exc_or_int_valid_r_d1 @[dec_tlu_ctl.scala 953:45] + csr.io.interrupt_valid_r_d1 <= interrupt_valid_r_d1 @[dec_tlu_ctl.scala 954:45] + csr.io.clk_override <= io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 955:45] + csr.io.i0_exception_valid_r_d1 <= int_exc.io.i0_exception_valid_r_d1 @[dec_tlu_ctl.scala 956:45] + csr.io.exc_cause_wb <= int_exc.io.exc_cause_wb @[dec_tlu_ctl.scala 958:45] + csr.io.nmi_lsu_store_type <= nmi_lsu_store_type @[dec_tlu_ctl.scala 959:45] + csr.io.nmi_lsu_load_type <= nmi_lsu_load_type @[dec_tlu_ctl.scala 960:45] + csr.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 961:45] + csr.io.ebreak_r <= ebreak_r @[dec_tlu_ctl.scala 962:45] + csr.io.ecall_r <= ecall_r @[dec_tlu_ctl.scala 963:45] + csr.io.illegal_r <= illegal_r @[dec_tlu_ctl.scala 964:45] + mdseac_locked_f <= csr.io.mdseac_locked_f @[dec_tlu_ctl.scala 965:27] + csr.io.nmi_int_detected_f <= nmi_int_detected_f @[dec_tlu_ctl.scala 966:45] + csr.io.internal_dbg_halt_mode_f2 <= internal_dbg_halt_mode_f2 @[dec_tlu_ctl.scala 967:45] + csr.io.ic_perr_r <= ic_perr_r @[dec_tlu_ctl.scala 969:45] + csr.io.iccm_sbecc_r <= iccm_sbecc_r @[dec_tlu_ctl.scala 970:45] + csr.io.ifu_miss_state_idle_f <= ifu_miss_state_idle_f @[dec_tlu_ctl.scala 972:45] + csr.io.lsu_idle_any_f <= lsu_idle_any_f @[dec_tlu_ctl.scala 973:45] + csr.io.dbg_tlu_halted_f <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 974:45] + csr.io.dbg_tlu_halted <= dbg_tlu_halted @[dec_tlu_ctl.scala 975:45] + csr.io.debug_halt_req_f <= debug_halt_req_f @[dec_tlu_ctl.scala 976:59] + csr.io.take_ext_int_start <= take_ext_int_start @[dec_tlu_ctl.scala 977:55] + csr.io.trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r_d1 @[dec_tlu_ctl.scala 978:43] + csr.io.trigger_hit_r_d1 <= int_exc.io.trigger_hit_r_d1 @[dec_tlu_ctl.scala 979:43] + csr.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[dec_tlu_ctl.scala 980:43] + csr.io.ebreak_to_debug_mode_r_d1 <= ebreak_to_debug_mode_r_d1 @[dec_tlu_ctl.scala 981:45] + csr.io.debug_halt_req <= debug_halt_req @[dec_tlu_ctl.scala 982:51] + csr.io.allow_dbg_halt_csr_write <= allow_dbg_halt_csr_write @[dec_tlu_ctl.scala 983:45] + csr.io.internal_dbg_halt_mode_f <= debug_mode_status @[dec_tlu_ctl.scala 984:45] + csr.io.enter_debug_halt_req <= enter_debug_halt_req @[dec_tlu_ctl.scala 985:45] + csr.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 986:45] + csr.io.request_debug_mode_done <= request_debug_mode_done @[dec_tlu_ctl.scala 987:45] + csr.io.request_debug_mode_r <= request_debug_mode_r @[dec_tlu_ctl.scala 988:45] + csr.io.update_hit_bit_r <= update_hit_bit_r @[dec_tlu_ctl.scala 989:45] + csr.io.take_timer_int <= take_timer_int @[dec_tlu_ctl.scala 990:45] + csr.io.take_int_timer0_int <= take_int_timer0_int @[dec_tlu_ctl.scala 991:45] + csr.io.take_int_timer1_int <= take_int_timer1_int @[dec_tlu_ctl.scala 992:45] + csr.io.take_ext_int <= take_ext_int @[dec_tlu_ctl.scala 993:45] + csr.io.tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 994:45] + csr.io.dec_tlu_br0_error_r <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 995:45] + csr.io.dec_tlu_br0_start_error_r <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 996:45] + csr.io.lsu_pmu_load_external_r <= lsu_pmu_load_external_r @[dec_tlu_ctl.scala 997:45] + csr.io.lsu_pmu_store_external_r <= lsu_pmu_store_external_r @[dec_tlu_ctl.scala 998:45] + csr.io.trigger_enabled <= trigger_enabled @[dec_tlu_ctl.scala 999:45] + csr.io.csr_pkt.legal <= csr_pkt.legal @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.postsync <= csr_pkt.postsync @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.presync <= csr_pkt.presync @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[dec_tlu_ctl.scala 1000:45] + npc_r <= csr.io.npc_r @[dec_tlu_ctl.scala 1002:37] + npc_r_d1 <= csr.io.npc_r_d1 @[dec_tlu_ctl.scala 1003:37] + mie_ns <= csr.io.mie_ns @[dec_tlu_ctl.scala 1004:37] + mepc <= csr.io.mepc @[dec_tlu_ctl.scala 1005:37] + mdseac_locked_ns <= csr.io.mdseac_locked_ns @[dec_tlu_ctl.scala 1006:37] + force_halt <= csr.io.force_halt @[dec_tlu_ctl.scala 1007:37] + dpc <= csr.io.dpc @[dec_tlu_ctl.scala 1008:37] + mstatus_mie_ns <= csr.io.mstatus_mie_ns @[dec_tlu_ctl.scala 1009:37] + dec_csr_wen_r_mod <= csr.io.dec_csr_wen_r_mod @[dec_tlu_ctl.scala 1010:37] + fw_halt_req <= csr.io.fw_halt_req @[dec_tlu_ctl.scala 1011:37] + mstatus <= csr.io.mstatus @[dec_tlu_ctl.scala 1012:37] + dcsr <= csr.io.dcsr @[dec_tlu_ctl.scala 1013:37] + mtvec <= csr.io.mtvec @[dec_tlu_ctl.scala 1014:37] + mip <= csr.io.mip @[dec_tlu_ctl.scala 1015:37] + mtdata1_t[0] <= csr.io.mtdata1_t[0] @[dec_tlu_ctl.scala 1016:39] + mtdata1_t[1] <= csr.io.mtdata1_t[1] @[dec_tlu_ctl.scala 1016:39] + mtdata1_t[2] <= csr.io.mtdata1_t[2] @[dec_tlu_ctl.scala 1016:39] + mtdata1_t[3] <= csr.io.mtdata1_t[3] @[dec_tlu_ctl.scala 1016:39] + inst csr_read of dec_decode_csr_read @[dec_tlu_ctl.scala 1017:28] + csr_read.clock <= clock + csr_read.reset <= reset + csr_read.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 1018:37] + csr_pkt.legal <= csr_read.io.csr_pkt.legal @[dec_tlu_ctl.scala 1019:16] + csr_pkt.postsync <= csr_read.io.csr_pkt.postsync @[dec_tlu_ctl.scala 1019:16] + csr_pkt.presync <= csr_read.io.csr_pkt.presync @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_dicago <= csr_read.io.csr_pkt.csr_dicago @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_dicad1 <= csr_read.io.csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_dicad0 <= csr_read.io.csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_dicad0h <= csr_read.io.csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_dicawics <= csr_read.io.csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mfdhs <= csr_read.io.csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mfdht <= csr_read.io.csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mdccmect <= csr_read.io.csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_miccmect <= csr_read.io.csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_micect <= csr_read.io.csr_pkt.csr_micect @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_meicpct <= csr_read.io.csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mpmc <= csr_read.io.csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mitcnt1 <= csr_read.io.csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mitcnt0 <= csr_read.io.csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mitb1 <= csr_read.io.csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mitb0 <= csr_read.io.csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mitctl1 <= csr_read.io.csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mitctl0 <= csr_read.io.csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mcountinhibit <= csr_read.io.csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpme6 <= csr_read.io.csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpme5 <= csr_read.io.csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpme4 <= csr_read.io.csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpme3 <= csr_read.io.csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpmc6h <= csr_read.io.csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpmc5h <= csr_read.io.csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpmc4h <= csr_read.io.csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpmc3h <= csr_read.io.csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpmc6 <= csr_read.io.csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpmc5 <= csr_read.io.csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpmc4 <= csr_read.io.csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpmc3 <= csr_read.io.csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mtdata2 <= csr_read.io.csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mtdata1 <= csr_read.io.csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mtsel <= csr_read.io.csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_dpc <= csr_read.io.csr_pkt.csr_dpc @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mfdc <= csr_read.io.csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mcgc <= csr_read.io.csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_dcsr <= csr_read.io.csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_meicidpl <= csr_read.io.csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_meicurpl <= csr_read.io.csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_meipt <= csr_read.io.csr_pkt.csr_meipt @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_meivt <= csr_read.io.csr_pkt.csr_meivt @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_meihap <= csr_read.io.csr_pkt.csr_meihap @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mdseac <= csr_read.io.csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_dmst <= csr_read.io.csr_pkt.csr_dmst @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mrac <= csr_read.io.csr_pkt.csr_mrac @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mtval <= csr_read.io.csr_pkt.csr_mtval @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mscause <= csr_read.io.csr_pkt.csr_mscause @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mcause <= csr_read.io.csr_pkt.csr_mcause @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mepc <= csr_read.io.csr_pkt.csr_mepc @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mscratch <= csr_read.io.csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_minstreth <= csr_read.io.csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_minstretl <= csr_read.io.csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mcycleh <= csr_read.io.csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mcyclel <= csr_read.io.csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mie <= csr_read.io.csr_pkt.csr_mie @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mip <= csr_read.io.csr_pkt.csr_mip @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mtvec <= csr_read.io.csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mstatus <= csr_read.io.csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhartid <= csr_read.io.csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mimpid <= csr_read.io.csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_marchid <= csr_read.io.csr_pkt.csr_marchid @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mvendorid <= csr_read.io.csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_misa <= csr_read.io.csr_pkt.csr_misa @[dec_tlu_ctl.scala 1019:16] + node _T_708 = and(csr_pkt.presync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1021:50] + node _T_709 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 1021:75] + node _T_710 = and(_T_708, _T_709) @[dec_tlu_ctl.scala 1021:73] + io.dec_tlu_presync_d <= _T_710 @[dec_tlu_ctl.scala 1021:31] + node _T_711 = and(csr_pkt.postsync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1022:51] + io.dec_tlu_postsync_d <= _T_711 @[dec_tlu_ctl.scala 1022:31] + node _T_712 = or(csr_pkt.csr_mitcnt0, csr_pkt.csr_mitcnt1) @[dec_tlu_ctl.scala 1025:58] + node _T_713 = or(_T_712, csr_pkt.csr_mitb0) @[dec_tlu_ctl.scala 1025:80] + node _T_714 = or(_T_713, csr_pkt.csr_mitb1) @[dec_tlu_ctl.scala 1025:100] + node _T_715 = or(_T_714, csr_pkt.csr_mitctl0) @[dec_tlu_ctl.scala 1025:120] + node _T_716 = or(_T_715, csr_pkt.csr_mitctl1) @[dec_tlu_ctl.scala 1025:142] + node _T_717 = not(UInt<1>("h01")) @[dec_tlu_ctl.scala 1025:167] + node conditionally_illegal = and(_T_716, _T_717) @[dec_tlu_ctl.scala 1025:165] + node _T_718 = or(csr_pkt.csr_dcsr, csr_pkt.csr_dpc) @[dec_tlu_ctl.scala 1026:63] + node _T_719 = or(_T_718, csr_pkt.csr_dmst) @[dec_tlu_ctl.scala 1026:81] + node _T_720 = or(_T_719, csr_pkt.csr_dicawics) @[dec_tlu_ctl.scala 1026:100] + node _T_721 = or(_T_720, csr_pkt.csr_dicad0) @[dec_tlu_ctl.scala 1026:123] + node _T_722 = or(_T_721, csr_pkt.csr_dicad0h) @[dec_tlu_ctl.scala 1026:144] + node _T_723 = or(_T_722, csr_pkt.csr_dicad1) @[dec_tlu_ctl.scala 1026:166] + node _T_724 = or(_T_723, csr_pkt.csr_dicago) @[dec_tlu_ctl.scala 1026:187] + node _T_725 = not(_T_724) @[dec_tlu_ctl.scala 1026:44] + node _T_726 = or(_T_725, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1026:209] + node _T_727 = and(csr_pkt.legal, _T_726) @[dec_tlu_ctl.scala 1026:41] + node _T_728 = not(fast_int_meicpct) @[dec_tlu_ctl.scala 1026:231] + node _T_729 = and(_T_727, _T_728) @[dec_tlu_ctl.scala 1026:229] + node _T_730 = not(conditionally_illegal) @[dec_tlu_ctl.scala 1026:251] + node valid_csr = and(_T_729, _T_730) @[dec_tlu_ctl.scala 1026:249] + node _T_731 = and(io.dec_csr_any_unq_d, valid_csr) @[dec_tlu_ctl.scala 1028:54] + node _T_732 = or(csr_pkt.csr_mvendorid, csr_pkt.csr_marchid) @[dec_tlu_ctl.scala 1028:115] + node _T_733 = or(_T_732, csr_pkt.csr_mimpid) @[dec_tlu_ctl.scala 1028:137] + node _T_734 = or(_T_733, csr_pkt.csr_mhartid) @[dec_tlu_ctl.scala 1028:158] + node _T_735 = or(_T_734, csr_pkt.csr_mdseac) @[dec_tlu_ctl.scala 1028:180] + node _T_736 = or(_T_735, csr_pkt.csr_meihap) @[dec_tlu_ctl.scala 1028:201] + node _T_737 = and(io.dec_csr_wen_unq_d, _T_736) @[dec_tlu_ctl.scala 1028:90] + node _T_738 = not(_T_737) @[dec_tlu_ctl.scala 1028:67] + node _T_739 = and(_T_731, _T_738) @[dec_tlu_ctl.scala 1028:65] + io.dec_csr_legal_d <= _T_739 @[dec_tlu_ctl.scala 1028:28] + + module dec_trigger : + input clock : Clock + input reset : Reset + output io : {flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_i0_pc_d : UInt<31>, dec_i0_trigger_match_d : UInt<4>} + + node _T = eq(io.trigger_pkt_any[0].select, UInt<1>("h00")) @[dec_trigger.scala 14:63] + node _T_1 = and(_T, io.trigger_pkt_any[0].execute) @[dec_trigger.scala 14:93] + wire _T_2 : UInt<1>[32] @[lib.scala 12:48] + _T_2[0] <= _T_1 @[lib.scala 12:48] + _T_2[1] <= _T_1 @[lib.scala 12:48] + _T_2[2] <= _T_1 @[lib.scala 12:48] + _T_2[3] <= _T_1 @[lib.scala 12:48] + _T_2[4] <= _T_1 @[lib.scala 12:48] + _T_2[5] <= _T_1 @[lib.scala 12:48] + _T_2[6] <= _T_1 @[lib.scala 12:48] + _T_2[7] <= _T_1 @[lib.scala 12:48] + _T_2[8] <= _T_1 @[lib.scala 12:48] + _T_2[9] <= _T_1 @[lib.scala 12:48] + _T_2[10] <= _T_1 @[lib.scala 12:48] + _T_2[11] <= _T_1 @[lib.scala 12:48] + _T_2[12] <= _T_1 @[lib.scala 12:48] + _T_2[13] <= _T_1 @[lib.scala 12:48] + _T_2[14] <= _T_1 @[lib.scala 12:48] + _T_2[15] <= _T_1 @[lib.scala 12:48] + _T_2[16] <= _T_1 @[lib.scala 12:48] + _T_2[17] <= _T_1 @[lib.scala 12:48] + _T_2[18] <= _T_1 @[lib.scala 12:48] + _T_2[19] <= _T_1 @[lib.scala 12:48] + _T_2[20] <= _T_1 @[lib.scala 12:48] + _T_2[21] <= _T_1 @[lib.scala 12:48] + _T_2[22] <= _T_1 @[lib.scala 12:48] + _T_2[23] <= _T_1 @[lib.scala 12:48] + _T_2[24] <= _T_1 @[lib.scala 12:48] + _T_2[25] <= _T_1 @[lib.scala 12:48] + _T_2[26] <= _T_1 @[lib.scala 12:48] + _T_2[27] <= _T_1 @[lib.scala 12:48] + _T_2[28] <= _T_1 @[lib.scala 12:48] + _T_2[29] <= _T_1 @[lib.scala 12:48] + _T_2[30] <= _T_1 @[lib.scala 12:48] + _T_2[31] <= _T_1 @[lib.scala 12:48] + node _T_3 = cat(_T_2[0], _T_2[1]) @[Cat.scala 29:58] + node _T_4 = cat(_T_3, _T_2[2]) @[Cat.scala 29:58] + node _T_5 = cat(_T_4, _T_2[3]) @[Cat.scala 29:58] + node _T_6 = cat(_T_5, _T_2[4]) @[Cat.scala 29:58] + node _T_7 = cat(_T_6, _T_2[5]) @[Cat.scala 29:58] + node _T_8 = cat(_T_7, _T_2[6]) @[Cat.scala 29:58] + node _T_9 = cat(_T_8, _T_2[7]) @[Cat.scala 29:58] + node _T_10 = cat(_T_9, _T_2[8]) @[Cat.scala 29:58] + node _T_11 = cat(_T_10, _T_2[9]) @[Cat.scala 29:58] + node _T_12 = cat(_T_11, _T_2[10]) @[Cat.scala 29:58] + node _T_13 = cat(_T_12, _T_2[11]) @[Cat.scala 29:58] + node _T_14 = cat(_T_13, _T_2[12]) @[Cat.scala 29:58] + node _T_15 = cat(_T_14, _T_2[13]) @[Cat.scala 29:58] + node _T_16 = cat(_T_15, _T_2[14]) @[Cat.scala 29:58] + node _T_17 = cat(_T_16, _T_2[15]) @[Cat.scala 29:58] + node _T_18 = cat(_T_17, _T_2[16]) @[Cat.scala 29:58] + node _T_19 = cat(_T_18, _T_2[17]) @[Cat.scala 29:58] + node _T_20 = cat(_T_19, _T_2[18]) @[Cat.scala 29:58] + node _T_21 = cat(_T_20, _T_2[19]) @[Cat.scala 29:58] + node _T_22 = cat(_T_21, _T_2[20]) @[Cat.scala 29:58] + node _T_23 = cat(_T_22, _T_2[21]) @[Cat.scala 29:58] + node _T_24 = cat(_T_23, _T_2[22]) @[Cat.scala 29:58] + node _T_25 = cat(_T_24, _T_2[23]) @[Cat.scala 29:58] + node _T_26 = cat(_T_25, _T_2[24]) @[Cat.scala 29:58] + node _T_27 = cat(_T_26, _T_2[25]) @[Cat.scala 29:58] + node _T_28 = cat(_T_27, _T_2[26]) @[Cat.scala 29:58] + node _T_29 = cat(_T_28, _T_2[27]) @[Cat.scala 29:58] + node _T_30 = cat(_T_29, _T_2[28]) @[Cat.scala 29:58] + node _T_31 = cat(_T_30, _T_2[29]) @[Cat.scala 29:58] + node _T_32 = cat(_T_31, _T_2[30]) @[Cat.scala 29:58] + node _T_33 = cat(_T_32, _T_2[31]) @[Cat.scala 29:58] + node _T_34 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[dec_trigger.scala 14:177] + node _T_35 = cat(io.dec_i0_pc_d, _T_34) @[Cat.scala 29:58] + node _T_36 = and(_T_33, _T_35) @[dec_trigger.scala 14:127] + node _T_37 = eq(io.trigger_pkt_any[1].select, UInt<1>("h00")) @[dec_trigger.scala 14:63] + node _T_38 = and(_T_37, io.trigger_pkt_any[1].execute) @[dec_trigger.scala 14:93] + wire _T_39 : UInt<1>[32] @[lib.scala 12:48] + _T_39[0] <= _T_38 @[lib.scala 12:48] + _T_39[1] <= _T_38 @[lib.scala 12:48] + _T_39[2] <= _T_38 @[lib.scala 12:48] + _T_39[3] <= _T_38 @[lib.scala 12:48] + _T_39[4] <= _T_38 @[lib.scala 12:48] + _T_39[5] <= _T_38 @[lib.scala 12:48] + _T_39[6] <= _T_38 @[lib.scala 12:48] + _T_39[7] <= _T_38 @[lib.scala 12:48] + _T_39[8] <= _T_38 @[lib.scala 12:48] + _T_39[9] <= _T_38 @[lib.scala 12:48] + _T_39[10] <= _T_38 @[lib.scala 12:48] + _T_39[11] <= _T_38 @[lib.scala 12:48] + _T_39[12] <= _T_38 @[lib.scala 12:48] + _T_39[13] <= _T_38 @[lib.scala 12:48] + _T_39[14] <= _T_38 @[lib.scala 12:48] + _T_39[15] <= _T_38 @[lib.scala 12:48] + _T_39[16] <= _T_38 @[lib.scala 12:48] + _T_39[17] <= _T_38 @[lib.scala 12:48] + _T_39[18] <= _T_38 @[lib.scala 12:48] + _T_39[19] <= _T_38 @[lib.scala 12:48] + _T_39[20] <= _T_38 @[lib.scala 12:48] + _T_39[21] <= _T_38 @[lib.scala 12:48] + _T_39[22] <= _T_38 @[lib.scala 12:48] + _T_39[23] <= _T_38 @[lib.scala 12:48] + _T_39[24] <= _T_38 @[lib.scala 12:48] + _T_39[25] <= _T_38 @[lib.scala 12:48] + _T_39[26] <= _T_38 @[lib.scala 12:48] + _T_39[27] <= _T_38 @[lib.scala 12:48] + _T_39[28] <= _T_38 @[lib.scala 12:48] + _T_39[29] <= _T_38 @[lib.scala 12:48] + _T_39[30] <= _T_38 @[lib.scala 12:48] + _T_39[31] <= _T_38 @[lib.scala 12:48] + node _T_40 = cat(_T_39[0], _T_39[1]) @[Cat.scala 29:58] + node _T_41 = cat(_T_40, _T_39[2]) @[Cat.scala 29:58] + node _T_42 = cat(_T_41, _T_39[3]) @[Cat.scala 29:58] + node _T_43 = cat(_T_42, _T_39[4]) @[Cat.scala 29:58] + node _T_44 = cat(_T_43, _T_39[5]) @[Cat.scala 29:58] + node _T_45 = cat(_T_44, _T_39[6]) @[Cat.scala 29:58] + node _T_46 = cat(_T_45, _T_39[7]) @[Cat.scala 29:58] + node _T_47 = cat(_T_46, _T_39[8]) @[Cat.scala 29:58] + node _T_48 = cat(_T_47, _T_39[9]) @[Cat.scala 29:58] + node _T_49 = cat(_T_48, _T_39[10]) @[Cat.scala 29:58] + node _T_50 = cat(_T_49, _T_39[11]) @[Cat.scala 29:58] + node _T_51 = cat(_T_50, _T_39[12]) @[Cat.scala 29:58] + node _T_52 = cat(_T_51, _T_39[13]) @[Cat.scala 29:58] + node _T_53 = cat(_T_52, _T_39[14]) @[Cat.scala 29:58] + node _T_54 = cat(_T_53, _T_39[15]) @[Cat.scala 29:58] + node _T_55 = cat(_T_54, _T_39[16]) @[Cat.scala 29:58] + node _T_56 = cat(_T_55, _T_39[17]) @[Cat.scala 29:58] + node _T_57 = cat(_T_56, _T_39[18]) @[Cat.scala 29:58] + node _T_58 = cat(_T_57, _T_39[19]) @[Cat.scala 29:58] + node _T_59 = cat(_T_58, _T_39[20]) @[Cat.scala 29:58] + node _T_60 = cat(_T_59, _T_39[21]) @[Cat.scala 29:58] + node _T_61 = cat(_T_60, _T_39[22]) @[Cat.scala 29:58] + node _T_62 = cat(_T_61, _T_39[23]) @[Cat.scala 29:58] + node _T_63 = cat(_T_62, _T_39[24]) @[Cat.scala 29:58] + node _T_64 = cat(_T_63, _T_39[25]) @[Cat.scala 29:58] + node _T_65 = cat(_T_64, _T_39[26]) @[Cat.scala 29:58] + node _T_66 = cat(_T_65, _T_39[27]) @[Cat.scala 29:58] + node _T_67 = cat(_T_66, _T_39[28]) @[Cat.scala 29:58] + node _T_68 = cat(_T_67, _T_39[29]) @[Cat.scala 29:58] + node _T_69 = cat(_T_68, _T_39[30]) @[Cat.scala 29:58] + node _T_70 = cat(_T_69, _T_39[31]) @[Cat.scala 29:58] + node _T_71 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[dec_trigger.scala 14:177] + node _T_72 = cat(io.dec_i0_pc_d, _T_71) @[Cat.scala 29:58] + node _T_73 = and(_T_70, _T_72) @[dec_trigger.scala 14:127] + node _T_74 = eq(io.trigger_pkt_any[2].select, UInt<1>("h00")) @[dec_trigger.scala 14:63] + node _T_75 = and(_T_74, io.trigger_pkt_any[2].execute) @[dec_trigger.scala 14:93] + wire _T_76 : UInt<1>[32] @[lib.scala 12:48] + _T_76[0] <= _T_75 @[lib.scala 12:48] + _T_76[1] <= _T_75 @[lib.scala 12:48] + _T_76[2] <= _T_75 @[lib.scala 12:48] + _T_76[3] <= _T_75 @[lib.scala 12:48] + _T_76[4] <= _T_75 @[lib.scala 12:48] + _T_76[5] <= _T_75 @[lib.scala 12:48] + _T_76[6] <= _T_75 @[lib.scala 12:48] + _T_76[7] <= _T_75 @[lib.scala 12:48] + _T_76[8] <= _T_75 @[lib.scala 12:48] + _T_76[9] <= _T_75 @[lib.scala 12:48] + _T_76[10] <= _T_75 @[lib.scala 12:48] + _T_76[11] <= _T_75 @[lib.scala 12:48] + _T_76[12] <= _T_75 @[lib.scala 12:48] + _T_76[13] <= _T_75 @[lib.scala 12:48] + _T_76[14] <= _T_75 @[lib.scala 12:48] + _T_76[15] <= _T_75 @[lib.scala 12:48] + _T_76[16] <= _T_75 @[lib.scala 12:48] + _T_76[17] <= _T_75 @[lib.scala 12:48] + _T_76[18] <= _T_75 @[lib.scala 12:48] + _T_76[19] <= _T_75 @[lib.scala 12:48] + _T_76[20] <= _T_75 @[lib.scala 12:48] + _T_76[21] <= _T_75 @[lib.scala 12:48] + _T_76[22] <= _T_75 @[lib.scala 12:48] + _T_76[23] <= _T_75 @[lib.scala 12:48] + _T_76[24] <= _T_75 @[lib.scala 12:48] + _T_76[25] <= _T_75 @[lib.scala 12:48] + _T_76[26] <= _T_75 @[lib.scala 12:48] + _T_76[27] <= _T_75 @[lib.scala 12:48] + _T_76[28] <= _T_75 @[lib.scala 12:48] + _T_76[29] <= _T_75 @[lib.scala 12:48] + _T_76[30] <= _T_75 @[lib.scala 12:48] + _T_76[31] <= _T_75 @[lib.scala 12:48] + node _T_77 = cat(_T_76[0], _T_76[1]) @[Cat.scala 29:58] + node _T_78 = cat(_T_77, _T_76[2]) @[Cat.scala 29:58] + node _T_79 = cat(_T_78, _T_76[3]) @[Cat.scala 29:58] + node _T_80 = cat(_T_79, _T_76[4]) @[Cat.scala 29:58] + node _T_81 = cat(_T_80, _T_76[5]) @[Cat.scala 29:58] + node _T_82 = cat(_T_81, _T_76[6]) @[Cat.scala 29:58] + node _T_83 = cat(_T_82, _T_76[7]) @[Cat.scala 29:58] + node _T_84 = cat(_T_83, _T_76[8]) @[Cat.scala 29:58] + node _T_85 = cat(_T_84, _T_76[9]) @[Cat.scala 29:58] + node _T_86 = cat(_T_85, _T_76[10]) @[Cat.scala 29:58] + node _T_87 = cat(_T_86, _T_76[11]) @[Cat.scala 29:58] + node _T_88 = cat(_T_87, _T_76[12]) @[Cat.scala 29:58] + node _T_89 = cat(_T_88, _T_76[13]) @[Cat.scala 29:58] + node _T_90 = cat(_T_89, _T_76[14]) @[Cat.scala 29:58] + node _T_91 = cat(_T_90, _T_76[15]) @[Cat.scala 29:58] + node _T_92 = cat(_T_91, _T_76[16]) @[Cat.scala 29:58] + node _T_93 = cat(_T_92, _T_76[17]) @[Cat.scala 29:58] + node _T_94 = cat(_T_93, _T_76[18]) @[Cat.scala 29:58] + node _T_95 = cat(_T_94, _T_76[19]) @[Cat.scala 29:58] + node _T_96 = cat(_T_95, _T_76[20]) @[Cat.scala 29:58] + node _T_97 = cat(_T_96, _T_76[21]) @[Cat.scala 29:58] + node _T_98 = cat(_T_97, _T_76[22]) @[Cat.scala 29:58] + node _T_99 = cat(_T_98, _T_76[23]) @[Cat.scala 29:58] + node _T_100 = cat(_T_99, _T_76[24]) @[Cat.scala 29:58] + node _T_101 = cat(_T_100, _T_76[25]) @[Cat.scala 29:58] + node _T_102 = cat(_T_101, _T_76[26]) @[Cat.scala 29:58] + node _T_103 = cat(_T_102, _T_76[27]) @[Cat.scala 29:58] + node _T_104 = cat(_T_103, _T_76[28]) @[Cat.scala 29:58] + node _T_105 = cat(_T_104, _T_76[29]) @[Cat.scala 29:58] + node _T_106 = cat(_T_105, _T_76[30]) @[Cat.scala 29:58] + node _T_107 = cat(_T_106, _T_76[31]) @[Cat.scala 29:58] + node _T_108 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[dec_trigger.scala 14:177] + node _T_109 = cat(io.dec_i0_pc_d, _T_108) @[Cat.scala 29:58] + node _T_110 = and(_T_107, _T_109) @[dec_trigger.scala 14:127] + node _T_111 = eq(io.trigger_pkt_any[3].select, UInt<1>("h00")) @[dec_trigger.scala 14:63] + node _T_112 = and(_T_111, io.trigger_pkt_any[3].execute) @[dec_trigger.scala 14:93] + wire _T_113 : UInt<1>[32] @[lib.scala 12:48] + _T_113[0] <= _T_112 @[lib.scala 12:48] + _T_113[1] <= _T_112 @[lib.scala 12:48] + _T_113[2] <= _T_112 @[lib.scala 12:48] + _T_113[3] <= _T_112 @[lib.scala 12:48] + _T_113[4] <= _T_112 @[lib.scala 12:48] + _T_113[5] <= _T_112 @[lib.scala 12:48] + _T_113[6] <= _T_112 @[lib.scala 12:48] + _T_113[7] <= _T_112 @[lib.scala 12:48] + _T_113[8] <= _T_112 @[lib.scala 12:48] + _T_113[9] <= _T_112 @[lib.scala 12:48] + _T_113[10] <= _T_112 @[lib.scala 12:48] + _T_113[11] <= _T_112 @[lib.scala 12:48] + _T_113[12] <= _T_112 @[lib.scala 12:48] + _T_113[13] <= _T_112 @[lib.scala 12:48] + _T_113[14] <= _T_112 @[lib.scala 12:48] + _T_113[15] <= _T_112 @[lib.scala 12:48] + _T_113[16] <= _T_112 @[lib.scala 12:48] + _T_113[17] <= _T_112 @[lib.scala 12:48] + _T_113[18] <= _T_112 @[lib.scala 12:48] + _T_113[19] <= _T_112 @[lib.scala 12:48] + _T_113[20] <= _T_112 @[lib.scala 12:48] + _T_113[21] <= _T_112 @[lib.scala 12:48] + _T_113[22] <= _T_112 @[lib.scala 12:48] + _T_113[23] <= _T_112 @[lib.scala 12:48] + _T_113[24] <= _T_112 @[lib.scala 12:48] + _T_113[25] <= _T_112 @[lib.scala 12:48] + _T_113[26] <= _T_112 @[lib.scala 12:48] + _T_113[27] <= _T_112 @[lib.scala 12:48] + _T_113[28] <= _T_112 @[lib.scala 12:48] + _T_113[29] <= _T_112 @[lib.scala 12:48] + _T_113[30] <= _T_112 @[lib.scala 12:48] + _T_113[31] <= _T_112 @[lib.scala 12:48] + node _T_114 = cat(_T_113[0], _T_113[1]) @[Cat.scala 29:58] + node _T_115 = cat(_T_114, _T_113[2]) @[Cat.scala 29:58] + node _T_116 = cat(_T_115, _T_113[3]) @[Cat.scala 29:58] + node _T_117 = cat(_T_116, _T_113[4]) @[Cat.scala 29:58] + node _T_118 = cat(_T_117, _T_113[5]) @[Cat.scala 29:58] + node _T_119 = cat(_T_118, _T_113[6]) @[Cat.scala 29:58] + node _T_120 = cat(_T_119, _T_113[7]) @[Cat.scala 29:58] + node _T_121 = cat(_T_120, _T_113[8]) @[Cat.scala 29:58] + node _T_122 = cat(_T_121, _T_113[9]) @[Cat.scala 29:58] + node _T_123 = cat(_T_122, _T_113[10]) @[Cat.scala 29:58] + node _T_124 = cat(_T_123, _T_113[11]) @[Cat.scala 29:58] + node _T_125 = cat(_T_124, _T_113[12]) @[Cat.scala 29:58] + node _T_126 = cat(_T_125, _T_113[13]) @[Cat.scala 29:58] + node _T_127 = cat(_T_126, _T_113[14]) @[Cat.scala 29:58] + node _T_128 = cat(_T_127, _T_113[15]) @[Cat.scala 29:58] + node _T_129 = cat(_T_128, _T_113[16]) @[Cat.scala 29:58] + node _T_130 = cat(_T_129, _T_113[17]) @[Cat.scala 29:58] + node _T_131 = cat(_T_130, _T_113[18]) @[Cat.scala 29:58] + node _T_132 = cat(_T_131, _T_113[19]) @[Cat.scala 29:58] + node _T_133 = cat(_T_132, _T_113[20]) @[Cat.scala 29:58] + node _T_134 = cat(_T_133, _T_113[21]) @[Cat.scala 29:58] + node _T_135 = cat(_T_134, _T_113[22]) @[Cat.scala 29:58] + node _T_136 = cat(_T_135, _T_113[23]) @[Cat.scala 29:58] + node _T_137 = cat(_T_136, _T_113[24]) @[Cat.scala 29:58] + node _T_138 = cat(_T_137, _T_113[25]) @[Cat.scala 29:58] + node _T_139 = cat(_T_138, _T_113[26]) @[Cat.scala 29:58] + node _T_140 = cat(_T_139, _T_113[27]) @[Cat.scala 29:58] + node _T_141 = cat(_T_140, _T_113[28]) @[Cat.scala 29:58] + node _T_142 = cat(_T_141, _T_113[29]) @[Cat.scala 29:58] + node _T_143 = cat(_T_142, _T_113[30]) @[Cat.scala 29:58] + node _T_144 = cat(_T_143, _T_113[31]) @[Cat.scala 29:58] + node _T_145 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[dec_trigger.scala 14:177] + node _T_146 = cat(io.dec_i0_pc_d, _T_145) @[Cat.scala 29:58] + node _T_147 = and(_T_144, _T_146) @[dec_trigger.scala 14:127] + wire dec_i0_match_data : UInt<32>[4] @[dec_trigger.scala 14:46] + dec_i0_match_data[0] <= _T_36 @[dec_trigger.scala 14:46] + dec_i0_match_data[1] <= _T_73 @[dec_trigger.scala 14:46] + dec_i0_match_data[2] <= _T_110 @[dec_trigger.scala 14:46] + dec_i0_match_data[3] <= _T_147 @[dec_trigger.scala 14:46] + node _T_148 = and(io.trigger_pkt_any[0].execute, io.trigger_pkt_any[0].m) @[dec_trigger.scala 15:83] + node _T_149 = bits(io.trigger_pkt_any[0].match_pkt, 0, 0) @[dec_trigger.scala 15:216] + wire _T_150 : UInt<1>[32] @[lib.scala 100:24] + node _T_151 = andr(io.trigger_pkt_any[0].tdata2) @[lib.scala 101:45] + node _T_152 = not(_T_151) @[lib.scala 101:39] + node _T_153 = and(_T_149, _T_152) @[lib.scala 101:37] + node _T_154 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[lib.scala 102:48] + node _T_155 = bits(dec_i0_match_data[0], 0, 0) @[lib.scala 102:60] + node _T_156 = eq(_T_154, _T_155) @[lib.scala 102:52] + node _T_157 = or(_T_153, _T_156) @[lib.scala 102:41] + _T_150[0] <= _T_157 @[lib.scala 102:18] + node _T_158 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[lib.scala 104:28] + node _T_159 = andr(_T_158) @[lib.scala 104:36] + node _T_160 = and(_T_159, _T_153) @[lib.scala 104:41] + node _T_161 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[lib.scala 104:74] + node _T_162 = bits(dec_i0_match_data[0], 1, 1) @[lib.scala 104:86] + node _T_163 = eq(_T_161, _T_162) @[lib.scala 104:78] + node _T_164 = mux(_T_160, UInt<1>("h01"), _T_163) @[lib.scala 104:23] + _T_150[1] <= _T_164 @[lib.scala 104:17] + node _T_165 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[lib.scala 104:28] + node _T_166 = andr(_T_165) @[lib.scala 104:36] + node _T_167 = and(_T_166, _T_153) @[lib.scala 104:41] + node _T_168 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[lib.scala 104:74] + node _T_169 = bits(dec_i0_match_data[0], 2, 2) @[lib.scala 104:86] + node _T_170 = eq(_T_168, _T_169) @[lib.scala 104:78] + node _T_171 = mux(_T_167, UInt<1>("h01"), _T_170) @[lib.scala 104:23] + _T_150[2] <= _T_171 @[lib.scala 104:17] + node _T_172 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[lib.scala 104:28] + node _T_173 = andr(_T_172) @[lib.scala 104:36] + node _T_174 = and(_T_173, _T_153) @[lib.scala 104:41] + node _T_175 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[lib.scala 104:74] + node _T_176 = bits(dec_i0_match_data[0], 3, 3) @[lib.scala 104:86] + node _T_177 = eq(_T_175, _T_176) @[lib.scala 104:78] + node _T_178 = mux(_T_174, UInt<1>("h01"), _T_177) @[lib.scala 104:23] + _T_150[3] <= _T_178 @[lib.scala 104:17] + node _T_179 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[lib.scala 104:28] + node _T_180 = andr(_T_179) @[lib.scala 104:36] + node _T_181 = and(_T_180, _T_153) @[lib.scala 104:41] + node _T_182 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[lib.scala 104:74] + node _T_183 = bits(dec_i0_match_data[0], 4, 4) @[lib.scala 104:86] + node _T_184 = eq(_T_182, _T_183) @[lib.scala 104:78] + node _T_185 = mux(_T_181, UInt<1>("h01"), _T_184) @[lib.scala 104:23] + _T_150[4] <= _T_185 @[lib.scala 104:17] + node _T_186 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[lib.scala 104:28] + node _T_187 = andr(_T_186) @[lib.scala 104:36] + node _T_188 = and(_T_187, _T_153) @[lib.scala 104:41] + node _T_189 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[lib.scala 104:74] + node _T_190 = bits(dec_i0_match_data[0], 5, 5) @[lib.scala 104:86] + node _T_191 = eq(_T_189, _T_190) @[lib.scala 104:78] + node _T_192 = mux(_T_188, UInt<1>("h01"), _T_191) @[lib.scala 104:23] + _T_150[5] <= _T_192 @[lib.scala 104:17] + node _T_193 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[lib.scala 104:28] + node _T_194 = andr(_T_193) @[lib.scala 104:36] + node _T_195 = and(_T_194, _T_153) @[lib.scala 104:41] + node _T_196 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[lib.scala 104:74] + node _T_197 = bits(dec_i0_match_data[0], 6, 6) @[lib.scala 104:86] + node _T_198 = eq(_T_196, _T_197) @[lib.scala 104:78] + node _T_199 = mux(_T_195, UInt<1>("h01"), _T_198) @[lib.scala 104:23] + _T_150[6] <= _T_199 @[lib.scala 104:17] + node _T_200 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[lib.scala 104:28] + node _T_201 = andr(_T_200) @[lib.scala 104:36] + node _T_202 = and(_T_201, _T_153) @[lib.scala 104:41] + node _T_203 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[lib.scala 104:74] + node _T_204 = bits(dec_i0_match_data[0], 7, 7) @[lib.scala 104:86] + node _T_205 = eq(_T_203, _T_204) @[lib.scala 104:78] + node _T_206 = mux(_T_202, UInt<1>("h01"), _T_205) @[lib.scala 104:23] + _T_150[7] <= _T_206 @[lib.scala 104:17] + node _T_207 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[lib.scala 104:28] + node _T_208 = andr(_T_207) @[lib.scala 104:36] + node _T_209 = and(_T_208, _T_153) @[lib.scala 104:41] + node _T_210 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[lib.scala 104:74] + node _T_211 = bits(dec_i0_match_data[0], 8, 8) @[lib.scala 104:86] + node _T_212 = eq(_T_210, _T_211) @[lib.scala 104:78] + node _T_213 = mux(_T_209, UInt<1>("h01"), _T_212) @[lib.scala 104:23] + _T_150[8] <= _T_213 @[lib.scala 104:17] + node _T_214 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[lib.scala 104:28] + node _T_215 = andr(_T_214) @[lib.scala 104:36] + node _T_216 = and(_T_215, _T_153) @[lib.scala 104:41] + node _T_217 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[lib.scala 104:74] + node _T_218 = bits(dec_i0_match_data[0], 9, 9) @[lib.scala 104:86] + node _T_219 = eq(_T_217, _T_218) @[lib.scala 104:78] + node _T_220 = mux(_T_216, UInt<1>("h01"), _T_219) @[lib.scala 104:23] + _T_150[9] <= _T_220 @[lib.scala 104:17] + node _T_221 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[lib.scala 104:28] + node _T_222 = andr(_T_221) @[lib.scala 104:36] + node _T_223 = and(_T_222, _T_153) @[lib.scala 104:41] + node _T_224 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[lib.scala 104:74] + node _T_225 = bits(dec_i0_match_data[0], 10, 10) @[lib.scala 104:86] + node _T_226 = eq(_T_224, _T_225) @[lib.scala 104:78] + node _T_227 = mux(_T_223, UInt<1>("h01"), _T_226) @[lib.scala 104:23] + _T_150[10] <= _T_227 @[lib.scala 104:17] + node _T_228 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[lib.scala 104:28] + node _T_229 = andr(_T_228) @[lib.scala 104:36] + node _T_230 = and(_T_229, _T_153) @[lib.scala 104:41] + node _T_231 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[lib.scala 104:74] + node _T_232 = bits(dec_i0_match_data[0], 11, 11) @[lib.scala 104:86] + node _T_233 = eq(_T_231, _T_232) @[lib.scala 104:78] + node _T_234 = mux(_T_230, UInt<1>("h01"), _T_233) @[lib.scala 104:23] + _T_150[11] <= _T_234 @[lib.scala 104:17] + node _T_235 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[lib.scala 104:28] + node _T_236 = andr(_T_235) @[lib.scala 104:36] + node _T_237 = and(_T_236, _T_153) @[lib.scala 104:41] + node _T_238 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[lib.scala 104:74] + node _T_239 = bits(dec_i0_match_data[0], 12, 12) @[lib.scala 104:86] + node _T_240 = eq(_T_238, _T_239) @[lib.scala 104:78] + node _T_241 = mux(_T_237, UInt<1>("h01"), _T_240) @[lib.scala 104:23] + _T_150[12] <= _T_241 @[lib.scala 104:17] + node _T_242 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[lib.scala 104:28] + node _T_243 = andr(_T_242) @[lib.scala 104:36] + node _T_244 = and(_T_243, _T_153) @[lib.scala 104:41] + node _T_245 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[lib.scala 104:74] + node _T_246 = bits(dec_i0_match_data[0], 13, 13) @[lib.scala 104:86] + node _T_247 = eq(_T_245, _T_246) @[lib.scala 104:78] + node _T_248 = mux(_T_244, UInt<1>("h01"), _T_247) @[lib.scala 104:23] + _T_150[13] <= _T_248 @[lib.scala 104:17] + node _T_249 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[lib.scala 104:28] + node _T_250 = andr(_T_249) @[lib.scala 104:36] + node _T_251 = and(_T_250, _T_153) @[lib.scala 104:41] + node _T_252 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[lib.scala 104:74] + node _T_253 = bits(dec_i0_match_data[0], 14, 14) @[lib.scala 104:86] + node _T_254 = eq(_T_252, _T_253) @[lib.scala 104:78] + node _T_255 = mux(_T_251, UInt<1>("h01"), _T_254) @[lib.scala 104:23] + _T_150[14] <= _T_255 @[lib.scala 104:17] + node _T_256 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[lib.scala 104:28] + node _T_257 = andr(_T_256) @[lib.scala 104:36] + node _T_258 = and(_T_257, _T_153) @[lib.scala 104:41] + node _T_259 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[lib.scala 104:74] + node _T_260 = bits(dec_i0_match_data[0], 15, 15) @[lib.scala 104:86] + node _T_261 = eq(_T_259, _T_260) @[lib.scala 104:78] + node _T_262 = mux(_T_258, UInt<1>("h01"), _T_261) @[lib.scala 104:23] + _T_150[15] <= _T_262 @[lib.scala 104:17] + node _T_263 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[lib.scala 104:28] + node _T_264 = andr(_T_263) @[lib.scala 104:36] + node _T_265 = and(_T_264, _T_153) @[lib.scala 104:41] + node _T_266 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[lib.scala 104:74] + node _T_267 = bits(dec_i0_match_data[0], 16, 16) @[lib.scala 104:86] + node _T_268 = eq(_T_266, _T_267) @[lib.scala 104:78] + node _T_269 = mux(_T_265, UInt<1>("h01"), _T_268) @[lib.scala 104:23] + _T_150[16] <= _T_269 @[lib.scala 104:17] + node _T_270 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[lib.scala 104:28] + node _T_271 = andr(_T_270) @[lib.scala 104:36] + node _T_272 = and(_T_271, _T_153) @[lib.scala 104:41] + node _T_273 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[lib.scala 104:74] + node _T_274 = bits(dec_i0_match_data[0], 17, 17) @[lib.scala 104:86] + node _T_275 = eq(_T_273, _T_274) @[lib.scala 104:78] + node _T_276 = mux(_T_272, UInt<1>("h01"), _T_275) @[lib.scala 104:23] + _T_150[17] <= _T_276 @[lib.scala 104:17] + node _T_277 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[lib.scala 104:28] + node _T_278 = andr(_T_277) @[lib.scala 104:36] + node _T_279 = and(_T_278, _T_153) @[lib.scala 104:41] + node _T_280 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[lib.scala 104:74] + node _T_281 = bits(dec_i0_match_data[0], 18, 18) @[lib.scala 104:86] + node _T_282 = eq(_T_280, _T_281) @[lib.scala 104:78] + node _T_283 = mux(_T_279, UInt<1>("h01"), _T_282) @[lib.scala 104:23] + _T_150[18] <= _T_283 @[lib.scala 104:17] + node _T_284 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[lib.scala 104:28] + node _T_285 = andr(_T_284) @[lib.scala 104:36] + node _T_286 = and(_T_285, _T_153) @[lib.scala 104:41] + node _T_287 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[lib.scala 104:74] + node _T_288 = bits(dec_i0_match_data[0], 19, 19) @[lib.scala 104:86] + node _T_289 = eq(_T_287, _T_288) @[lib.scala 104:78] + node _T_290 = mux(_T_286, UInt<1>("h01"), _T_289) @[lib.scala 104:23] + _T_150[19] <= _T_290 @[lib.scala 104:17] + node _T_291 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[lib.scala 104:28] + node _T_292 = andr(_T_291) @[lib.scala 104:36] + node _T_293 = and(_T_292, _T_153) @[lib.scala 104:41] + node _T_294 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[lib.scala 104:74] + node _T_295 = bits(dec_i0_match_data[0], 20, 20) @[lib.scala 104:86] + node _T_296 = eq(_T_294, _T_295) @[lib.scala 104:78] + node _T_297 = mux(_T_293, UInt<1>("h01"), _T_296) @[lib.scala 104:23] + _T_150[20] <= _T_297 @[lib.scala 104:17] + node _T_298 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[lib.scala 104:28] + node _T_299 = andr(_T_298) @[lib.scala 104:36] + node _T_300 = and(_T_299, _T_153) @[lib.scala 104:41] + node _T_301 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[lib.scala 104:74] + node _T_302 = bits(dec_i0_match_data[0], 21, 21) @[lib.scala 104:86] + node _T_303 = eq(_T_301, _T_302) @[lib.scala 104:78] + node _T_304 = mux(_T_300, UInt<1>("h01"), _T_303) @[lib.scala 104:23] + _T_150[21] <= _T_304 @[lib.scala 104:17] + node _T_305 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[lib.scala 104:28] + node _T_306 = andr(_T_305) @[lib.scala 104:36] + node _T_307 = and(_T_306, _T_153) @[lib.scala 104:41] + node _T_308 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[lib.scala 104:74] + node _T_309 = bits(dec_i0_match_data[0], 22, 22) @[lib.scala 104:86] + node _T_310 = eq(_T_308, _T_309) @[lib.scala 104:78] + node _T_311 = mux(_T_307, UInt<1>("h01"), _T_310) @[lib.scala 104:23] + _T_150[22] <= _T_311 @[lib.scala 104:17] + node _T_312 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[lib.scala 104:28] + node _T_313 = andr(_T_312) @[lib.scala 104:36] + node _T_314 = and(_T_313, _T_153) @[lib.scala 104:41] + node _T_315 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[lib.scala 104:74] + node _T_316 = bits(dec_i0_match_data[0], 23, 23) @[lib.scala 104:86] + node _T_317 = eq(_T_315, _T_316) @[lib.scala 104:78] + node _T_318 = mux(_T_314, UInt<1>("h01"), _T_317) @[lib.scala 104:23] + _T_150[23] <= _T_318 @[lib.scala 104:17] + node _T_319 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[lib.scala 104:28] + node _T_320 = andr(_T_319) @[lib.scala 104:36] + node _T_321 = and(_T_320, _T_153) @[lib.scala 104:41] + node _T_322 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[lib.scala 104:74] + node _T_323 = bits(dec_i0_match_data[0], 24, 24) @[lib.scala 104:86] + node _T_324 = eq(_T_322, _T_323) @[lib.scala 104:78] + node _T_325 = mux(_T_321, UInt<1>("h01"), _T_324) @[lib.scala 104:23] + _T_150[24] <= _T_325 @[lib.scala 104:17] + node _T_326 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[lib.scala 104:28] + node _T_327 = andr(_T_326) @[lib.scala 104:36] + node _T_328 = and(_T_327, _T_153) @[lib.scala 104:41] + node _T_329 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[lib.scala 104:74] + node _T_330 = bits(dec_i0_match_data[0], 25, 25) @[lib.scala 104:86] + node _T_331 = eq(_T_329, _T_330) @[lib.scala 104:78] + node _T_332 = mux(_T_328, UInt<1>("h01"), _T_331) @[lib.scala 104:23] + _T_150[25] <= _T_332 @[lib.scala 104:17] + node _T_333 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[lib.scala 104:28] + node _T_334 = andr(_T_333) @[lib.scala 104:36] + node _T_335 = and(_T_334, _T_153) @[lib.scala 104:41] + node _T_336 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[lib.scala 104:74] + node _T_337 = bits(dec_i0_match_data[0], 26, 26) @[lib.scala 104:86] + node _T_338 = eq(_T_336, _T_337) @[lib.scala 104:78] + node _T_339 = mux(_T_335, UInt<1>("h01"), _T_338) @[lib.scala 104:23] + _T_150[26] <= _T_339 @[lib.scala 104:17] + node _T_340 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[lib.scala 104:28] + node _T_341 = andr(_T_340) @[lib.scala 104:36] + node _T_342 = and(_T_341, _T_153) @[lib.scala 104:41] + node _T_343 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[lib.scala 104:74] + node _T_344 = bits(dec_i0_match_data[0], 27, 27) @[lib.scala 104:86] + node _T_345 = eq(_T_343, _T_344) @[lib.scala 104:78] + node _T_346 = mux(_T_342, UInt<1>("h01"), _T_345) @[lib.scala 104:23] + _T_150[27] <= _T_346 @[lib.scala 104:17] + node _T_347 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[lib.scala 104:28] + node _T_348 = andr(_T_347) @[lib.scala 104:36] + node _T_349 = and(_T_348, _T_153) @[lib.scala 104:41] + node _T_350 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[lib.scala 104:74] + node _T_351 = bits(dec_i0_match_data[0], 28, 28) @[lib.scala 104:86] + node _T_352 = eq(_T_350, _T_351) @[lib.scala 104:78] + node _T_353 = mux(_T_349, UInt<1>("h01"), _T_352) @[lib.scala 104:23] + _T_150[28] <= _T_353 @[lib.scala 104:17] + node _T_354 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[lib.scala 104:28] + node _T_355 = andr(_T_354) @[lib.scala 104:36] + node _T_356 = and(_T_355, _T_153) @[lib.scala 104:41] + node _T_357 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[lib.scala 104:74] + node _T_358 = bits(dec_i0_match_data[0], 29, 29) @[lib.scala 104:86] + node _T_359 = eq(_T_357, _T_358) @[lib.scala 104:78] + node _T_360 = mux(_T_356, UInt<1>("h01"), _T_359) @[lib.scala 104:23] + _T_150[29] <= _T_360 @[lib.scala 104:17] + node _T_361 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[lib.scala 104:28] + node _T_362 = andr(_T_361) @[lib.scala 104:36] + node _T_363 = and(_T_362, _T_153) @[lib.scala 104:41] + node _T_364 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[lib.scala 104:74] + node _T_365 = bits(dec_i0_match_data[0], 30, 30) @[lib.scala 104:86] + node _T_366 = eq(_T_364, _T_365) @[lib.scala 104:78] + node _T_367 = mux(_T_363, UInt<1>("h01"), _T_366) @[lib.scala 104:23] + _T_150[30] <= _T_367 @[lib.scala 104:17] + node _T_368 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[lib.scala 104:28] + node _T_369 = andr(_T_368) @[lib.scala 104:36] + node _T_370 = and(_T_369, _T_153) @[lib.scala 104:41] + node _T_371 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[lib.scala 104:74] + node _T_372 = bits(dec_i0_match_data[0], 31, 31) @[lib.scala 104:86] + node _T_373 = eq(_T_371, _T_372) @[lib.scala 104:78] + node _T_374 = mux(_T_370, UInt<1>("h01"), _T_373) @[lib.scala 104:23] + _T_150[31] <= _T_374 @[lib.scala 104:17] + node _T_375 = cat(_T_150[1], _T_150[0]) @[lib.scala 105:14] + node _T_376 = cat(_T_150[3], _T_150[2]) @[lib.scala 105:14] + node _T_377 = cat(_T_376, _T_375) @[lib.scala 105:14] + node _T_378 = cat(_T_150[5], _T_150[4]) @[lib.scala 105:14] + node _T_379 = cat(_T_150[7], _T_150[6]) @[lib.scala 105:14] + node _T_380 = cat(_T_379, _T_378) @[lib.scala 105:14] + node _T_381 = cat(_T_380, _T_377) @[lib.scala 105:14] + node _T_382 = cat(_T_150[9], _T_150[8]) @[lib.scala 105:14] + node _T_383 = cat(_T_150[11], _T_150[10]) @[lib.scala 105:14] + node _T_384 = cat(_T_383, _T_382) @[lib.scala 105:14] + node _T_385 = cat(_T_150[13], _T_150[12]) @[lib.scala 105:14] + node _T_386 = cat(_T_150[15], _T_150[14]) @[lib.scala 105:14] + node _T_387 = cat(_T_386, _T_385) @[lib.scala 105:14] + node _T_388 = cat(_T_387, _T_384) @[lib.scala 105:14] + node _T_389 = cat(_T_388, _T_381) @[lib.scala 105:14] + node _T_390 = cat(_T_150[17], _T_150[16]) @[lib.scala 105:14] + node _T_391 = cat(_T_150[19], _T_150[18]) @[lib.scala 105:14] + node _T_392 = cat(_T_391, _T_390) @[lib.scala 105:14] + node _T_393 = cat(_T_150[21], _T_150[20]) @[lib.scala 105:14] + node _T_394 = cat(_T_150[23], _T_150[22]) @[lib.scala 105:14] + node _T_395 = cat(_T_394, _T_393) @[lib.scala 105:14] + node _T_396 = cat(_T_395, _T_392) @[lib.scala 105:14] + node _T_397 = cat(_T_150[25], _T_150[24]) @[lib.scala 105:14] + node _T_398 = cat(_T_150[27], _T_150[26]) @[lib.scala 105:14] + node _T_399 = cat(_T_398, _T_397) @[lib.scala 105:14] + node _T_400 = cat(_T_150[29], _T_150[28]) @[lib.scala 105:14] + node _T_401 = cat(_T_150[31], _T_150[30]) @[lib.scala 105:14] + node _T_402 = cat(_T_401, _T_400) @[lib.scala 105:14] + node _T_403 = cat(_T_402, _T_399) @[lib.scala 105:14] + node _T_404 = cat(_T_403, _T_396) @[lib.scala 105:14] + node _T_405 = cat(_T_404, _T_389) @[lib.scala 105:14] + node _T_406 = andr(_T_405) @[lib.scala 105:25] + node _T_407 = and(_T_148, _T_406) @[dec_trigger.scala 15:109] + node _T_408 = and(io.trigger_pkt_any[1].execute, io.trigger_pkt_any[1].m) @[dec_trigger.scala 15:83] + node _T_409 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[dec_trigger.scala 15:216] + wire _T_410 : UInt<1>[32] @[lib.scala 100:24] + node _T_411 = andr(io.trigger_pkt_any[1].tdata2) @[lib.scala 101:45] + node _T_412 = not(_T_411) @[lib.scala 101:39] + node _T_413 = and(_T_409, _T_412) @[lib.scala 101:37] + node _T_414 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 102:48] + node _T_415 = bits(dec_i0_match_data[1], 0, 0) @[lib.scala 102:60] + node _T_416 = eq(_T_414, _T_415) @[lib.scala 102:52] + node _T_417 = or(_T_413, _T_416) @[lib.scala 102:41] + _T_410[0] <= _T_417 @[lib.scala 102:18] + node _T_418 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 104:28] + node _T_419 = andr(_T_418) @[lib.scala 104:36] + node _T_420 = and(_T_419, _T_413) @[lib.scala 104:41] + node _T_421 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[lib.scala 104:74] + node _T_422 = bits(dec_i0_match_data[1], 1, 1) @[lib.scala 104:86] + node _T_423 = eq(_T_421, _T_422) @[lib.scala 104:78] + node _T_424 = mux(_T_420, UInt<1>("h01"), _T_423) @[lib.scala 104:23] + _T_410[1] <= _T_424 @[lib.scala 104:17] + node _T_425 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[lib.scala 104:28] + node _T_426 = andr(_T_425) @[lib.scala 104:36] + node _T_427 = and(_T_426, _T_413) @[lib.scala 104:41] + node _T_428 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[lib.scala 104:74] + node _T_429 = bits(dec_i0_match_data[1], 2, 2) @[lib.scala 104:86] + node _T_430 = eq(_T_428, _T_429) @[lib.scala 104:78] + node _T_431 = mux(_T_427, UInt<1>("h01"), _T_430) @[lib.scala 104:23] + _T_410[2] <= _T_431 @[lib.scala 104:17] + node _T_432 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[lib.scala 104:28] + node _T_433 = andr(_T_432) @[lib.scala 104:36] + node _T_434 = and(_T_433, _T_413) @[lib.scala 104:41] + node _T_435 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[lib.scala 104:74] + node _T_436 = bits(dec_i0_match_data[1], 3, 3) @[lib.scala 104:86] + node _T_437 = eq(_T_435, _T_436) @[lib.scala 104:78] + node _T_438 = mux(_T_434, UInt<1>("h01"), _T_437) @[lib.scala 104:23] + _T_410[3] <= _T_438 @[lib.scala 104:17] + node _T_439 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[lib.scala 104:28] + node _T_440 = andr(_T_439) @[lib.scala 104:36] + node _T_441 = and(_T_440, _T_413) @[lib.scala 104:41] + node _T_442 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[lib.scala 104:74] + node _T_443 = bits(dec_i0_match_data[1], 4, 4) @[lib.scala 104:86] + node _T_444 = eq(_T_442, _T_443) @[lib.scala 104:78] + node _T_445 = mux(_T_441, UInt<1>("h01"), _T_444) @[lib.scala 104:23] + _T_410[4] <= _T_445 @[lib.scala 104:17] + node _T_446 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[lib.scala 104:28] + node _T_447 = andr(_T_446) @[lib.scala 104:36] + node _T_448 = and(_T_447, _T_413) @[lib.scala 104:41] + node _T_449 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[lib.scala 104:74] + node _T_450 = bits(dec_i0_match_data[1], 5, 5) @[lib.scala 104:86] + node _T_451 = eq(_T_449, _T_450) @[lib.scala 104:78] + node _T_452 = mux(_T_448, UInt<1>("h01"), _T_451) @[lib.scala 104:23] + _T_410[5] <= _T_452 @[lib.scala 104:17] + node _T_453 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[lib.scala 104:28] + node _T_454 = andr(_T_453) @[lib.scala 104:36] + node _T_455 = and(_T_454, _T_413) @[lib.scala 104:41] + node _T_456 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[lib.scala 104:74] + node _T_457 = bits(dec_i0_match_data[1], 6, 6) @[lib.scala 104:86] + node _T_458 = eq(_T_456, _T_457) @[lib.scala 104:78] + node _T_459 = mux(_T_455, UInt<1>("h01"), _T_458) @[lib.scala 104:23] + _T_410[6] <= _T_459 @[lib.scala 104:17] + node _T_460 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[lib.scala 104:28] + node _T_461 = andr(_T_460) @[lib.scala 104:36] + node _T_462 = and(_T_461, _T_413) @[lib.scala 104:41] + node _T_463 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[lib.scala 104:74] + node _T_464 = bits(dec_i0_match_data[1], 7, 7) @[lib.scala 104:86] + node _T_465 = eq(_T_463, _T_464) @[lib.scala 104:78] + node _T_466 = mux(_T_462, UInt<1>("h01"), _T_465) @[lib.scala 104:23] + _T_410[7] <= _T_466 @[lib.scala 104:17] + node _T_467 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[lib.scala 104:28] + node _T_468 = andr(_T_467) @[lib.scala 104:36] + node _T_469 = and(_T_468, _T_413) @[lib.scala 104:41] + node _T_470 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[lib.scala 104:74] + node _T_471 = bits(dec_i0_match_data[1], 8, 8) @[lib.scala 104:86] + node _T_472 = eq(_T_470, _T_471) @[lib.scala 104:78] + node _T_473 = mux(_T_469, UInt<1>("h01"), _T_472) @[lib.scala 104:23] + _T_410[8] <= _T_473 @[lib.scala 104:17] + node _T_474 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[lib.scala 104:28] + node _T_475 = andr(_T_474) @[lib.scala 104:36] + node _T_476 = and(_T_475, _T_413) @[lib.scala 104:41] + node _T_477 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[lib.scala 104:74] + node _T_478 = bits(dec_i0_match_data[1], 9, 9) @[lib.scala 104:86] + node _T_479 = eq(_T_477, _T_478) @[lib.scala 104:78] + node _T_480 = mux(_T_476, UInt<1>("h01"), _T_479) @[lib.scala 104:23] + _T_410[9] <= _T_480 @[lib.scala 104:17] + node _T_481 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[lib.scala 104:28] + node _T_482 = andr(_T_481) @[lib.scala 104:36] + node _T_483 = and(_T_482, _T_413) @[lib.scala 104:41] + node _T_484 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[lib.scala 104:74] + node _T_485 = bits(dec_i0_match_data[1], 10, 10) @[lib.scala 104:86] + node _T_486 = eq(_T_484, _T_485) @[lib.scala 104:78] + node _T_487 = mux(_T_483, UInt<1>("h01"), _T_486) @[lib.scala 104:23] + _T_410[10] <= _T_487 @[lib.scala 104:17] + node _T_488 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[lib.scala 104:28] + node _T_489 = andr(_T_488) @[lib.scala 104:36] + node _T_490 = and(_T_489, _T_413) @[lib.scala 104:41] + node _T_491 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[lib.scala 104:74] + node _T_492 = bits(dec_i0_match_data[1], 11, 11) @[lib.scala 104:86] + node _T_493 = eq(_T_491, _T_492) @[lib.scala 104:78] + node _T_494 = mux(_T_490, UInt<1>("h01"), _T_493) @[lib.scala 104:23] + _T_410[11] <= _T_494 @[lib.scala 104:17] + node _T_495 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[lib.scala 104:28] + node _T_496 = andr(_T_495) @[lib.scala 104:36] + node _T_497 = and(_T_496, _T_413) @[lib.scala 104:41] + node _T_498 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[lib.scala 104:74] + node _T_499 = bits(dec_i0_match_data[1], 12, 12) @[lib.scala 104:86] + node _T_500 = eq(_T_498, _T_499) @[lib.scala 104:78] + node _T_501 = mux(_T_497, UInt<1>("h01"), _T_500) @[lib.scala 104:23] + _T_410[12] <= _T_501 @[lib.scala 104:17] + node _T_502 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[lib.scala 104:28] + node _T_503 = andr(_T_502) @[lib.scala 104:36] + node _T_504 = and(_T_503, _T_413) @[lib.scala 104:41] + node _T_505 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[lib.scala 104:74] + node _T_506 = bits(dec_i0_match_data[1], 13, 13) @[lib.scala 104:86] + node _T_507 = eq(_T_505, _T_506) @[lib.scala 104:78] + node _T_508 = mux(_T_504, UInt<1>("h01"), _T_507) @[lib.scala 104:23] + _T_410[13] <= _T_508 @[lib.scala 104:17] + node _T_509 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[lib.scala 104:28] + node _T_510 = andr(_T_509) @[lib.scala 104:36] + node _T_511 = and(_T_510, _T_413) @[lib.scala 104:41] + node _T_512 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[lib.scala 104:74] + node _T_513 = bits(dec_i0_match_data[1], 14, 14) @[lib.scala 104:86] + node _T_514 = eq(_T_512, _T_513) @[lib.scala 104:78] + node _T_515 = mux(_T_511, UInt<1>("h01"), _T_514) @[lib.scala 104:23] + _T_410[14] <= _T_515 @[lib.scala 104:17] + node _T_516 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[lib.scala 104:28] + node _T_517 = andr(_T_516) @[lib.scala 104:36] + node _T_518 = and(_T_517, _T_413) @[lib.scala 104:41] + node _T_519 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[lib.scala 104:74] + node _T_520 = bits(dec_i0_match_data[1], 15, 15) @[lib.scala 104:86] + node _T_521 = eq(_T_519, _T_520) @[lib.scala 104:78] + node _T_522 = mux(_T_518, UInt<1>("h01"), _T_521) @[lib.scala 104:23] + _T_410[15] <= _T_522 @[lib.scala 104:17] + node _T_523 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[lib.scala 104:28] + node _T_524 = andr(_T_523) @[lib.scala 104:36] + node _T_525 = and(_T_524, _T_413) @[lib.scala 104:41] + node _T_526 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[lib.scala 104:74] + node _T_527 = bits(dec_i0_match_data[1], 16, 16) @[lib.scala 104:86] + node _T_528 = eq(_T_526, _T_527) @[lib.scala 104:78] + node _T_529 = mux(_T_525, UInt<1>("h01"), _T_528) @[lib.scala 104:23] + _T_410[16] <= _T_529 @[lib.scala 104:17] + node _T_530 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[lib.scala 104:28] + node _T_531 = andr(_T_530) @[lib.scala 104:36] + node _T_532 = and(_T_531, _T_413) @[lib.scala 104:41] + node _T_533 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[lib.scala 104:74] + node _T_534 = bits(dec_i0_match_data[1], 17, 17) @[lib.scala 104:86] + node _T_535 = eq(_T_533, _T_534) @[lib.scala 104:78] + node _T_536 = mux(_T_532, UInt<1>("h01"), _T_535) @[lib.scala 104:23] + _T_410[17] <= _T_536 @[lib.scala 104:17] + node _T_537 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[lib.scala 104:28] + node _T_538 = andr(_T_537) @[lib.scala 104:36] + node _T_539 = and(_T_538, _T_413) @[lib.scala 104:41] + node _T_540 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[lib.scala 104:74] + node _T_541 = bits(dec_i0_match_data[1], 18, 18) @[lib.scala 104:86] + node _T_542 = eq(_T_540, _T_541) @[lib.scala 104:78] + node _T_543 = mux(_T_539, UInt<1>("h01"), _T_542) @[lib.scala 104:23] + _T_410[18] <= _T_543 @[lib.scala 104:17] + node _T_544 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[lib.scala 104:28] + node _T_545 = andr(_T_544) @[lib.scala 104:36] + node _T_546 = and(_T_545, _T_413) @[lib.scala 104:41] + node _T_547 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[lib.scala 104:74] + node _T_548 = bits(dec_i0_match_data[1], 19, 19) @[lib.scala 104:86] + node _T_549 = eq(_T_547, _T_548) @[lib.scala 104:78] + node _T_550 = mux(_T_546, UInt<1>("h01"), _T_549) @[lib.scala 104:23] + _T_410[19] <= _T_550 @[lib.scala 104:17] + node _T_551 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[lib.scala 104:28] + node _T_552 = andr(_T_551) @[lib.scala 104:36] + node _T_553 = and(_T_552, _T_413) @[lib.scala 104:41] + node _T_554 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[lib.scala 104:74] + node _T_555 = bits(dec_i0_match_data[1], 20, 20) @[lib.scala 104:86] + node _T_556 = eq(_T_554, _T_555) @[lib.scala 104:78] + node _T_557 = mux(_T_553, UInt<1>("h01"), _T_556) @[lib.scala 104:23] + _T_410[20] <= _T_557 @[lib.scala 104:17] + node _T_558 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[lib.scala 104:28] + node _T_559 = andr(_T_558) @[lib.scala 104:36] + node _T_560 = and(_T_559, _T_413) @[lib.scala 104:41] + node _T_561 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[lib.scala 104:74] + node _T_562 = bits(dec_i0_match_data[1], 21, 21) @[lib.scala 104:86] + node _T_563 = eq(_T_561, _T_562) @[lib.scala 104:78] + node _T_564 = mux(_T_560, UInt<1>("h01"), _T_563) @[lib.scala 104:23] + _T_410[21] <= _T_564 @[lib.scala 104:17] + node _T_565 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[lib.scala 104:28] + node _T_566 = andr(_T_565) @[lib.scala 104:36] + node _T_567 = and(_T_566, _T_413) @[lib.scala 104:41] + node _T_568 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[lib.scala 104:74] + node _T_569 = bits(dec_i0_match_data[1], 22, 22) @[lib.scala 104:86] + node _T_570 = eq(_T_568, _T_569) @[lib.scala 104:78] + node _T_571 = mux(_T_567, UInt<1>("h01"), _T_570) @[lib.scala 104:23] + _T_410[22] <= _T_571 @[lib.scala 104:17] + node _T_572 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[lib.scala 104:28] + node _T_573 = andr(_T_572) @[lib.scala 104:36] + node _T_574 = and(_T_573, _T_413) @[lib.scala 104:41] + node _T_575 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[lib.scala 104:74] + node _T_576 = bits(dec_i0_match_data[1], 23, 23) @[lib.scala 104:86] + node _T_577 = eq(_T_575, _T_576) @[lib.scala 104:78] + node _T_578 = mux(_T_574, UInt<1>("h01"), _T_577) @[lib.scala 104:23] + _T_410[23] <= _T_578 @[lib.scala 104:17] + node _T_579 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[lib.scala 104:28] + node _T_580 = andr(_T_579) @[lib.scala 104:36] + node _T_581 = and(_T_580, _T_413) @[lib.scala 104:41] + node _T_582 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[lib.scala 104:74] + node _T_583 = bits(dec_i0_match_data[1], 24, 24) @[lib.scala 104:86] + node _T_584 = eq(_T_582, _T_583) @[lib.scala 104:78] + node _T_585 = mux(_T_581, UInt<1>("h01"), _T_584) @[lib.scala 104:23] + _T_410[24] <= _T_585 @[lib.scala 104:17] + node _T_586 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[lib.scala 104:28] + node _T_587 = andr(_T_586) @[lib.scala 104:36] + node _T_588 = and(_T_587, _T_413) @[lib.scala 104:41] + node _T_589 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[lib.scala 104:74] + node _T_590 = bits(dec_i0_match_data[1], 25, 25) @[lib.scala 104:86] + node _T_591 = eq(_T_589, _T_590) @[lib.scala 104:78] + node _T_592 = mux(_T_588, UInt<1>("h01"), _T_591) @[lib.scala 104:23] + _T_410[25] <= _T_592 @[lib.scala 104:17] + node _T_593 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[lib.scala 104:28] + node _T_594 = andr(_T_593) @[lib.scala 104:36] + node _T_595 = and(_T_594, _T_413) @[lib.scala 104:41] + node _T_596 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[lib.scala 104:74] + node _T_597 = bits(dec_i0_match_data[1], 26, 26) @[lib.scala 104:86] + node _T_598 = eq(_T_596, _T_597) @[lib.scala 104:78] + node _T_599 = mux(_T_595, UInt<1>("h01"), _T_598) @[lib.scala 104:23] + _T_410[26] <= _T_599 @[lib.scala 104:17] + node _T_600 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[lib.scala 104:28] + node _T_601 = andr(_T_600) @[lib.scala 104:36] + node _T_602 = and(_T_601, _T_413) @[lib.scala 104:41] + node _T_603 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[lib.scala 104:74] + node _T_604 = bits(dec_i0_match_data[1], 27, 27) @[lib.scala 104:86] + node _T_605 = eq(_T_603, _T_604) @[lib.scala 104:78] + node _T_606 = mux(_T_602, UInt<1>("h01"), _T_605) @[lib.scala 104:23] + _T_410[27] <= _T_606 @[lib.scala 104:17] + node _T_607 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[lib.scala 104:28] + node _T_608 = andr(_T_607) @[lib.scala 104:36] + node _T_609 = and(_T_608, _T_413) @[lib.scala 104:41] + node _T_610 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[lib.scala 104:74] + node _T_611 = bits(dec_i0_match_data[1], 28, 28) @[lib.scala 104:86] + node _T_612 = eq(_T_610, _T_611) @[lib.scala 104:78] + node _T_613 = mux(_T_609, UInt<1>("h01"), _T_612) @[lib.scala 104:23] + _T_410[28] <= _T_613 @[lib.scala 104:17] + node _T_614 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[lib.scala 104:28] + node _T_615 = andr(_T_614) @[lib.scala 104:36] + node _T_616 = and(_T_615, _T_413) @[lib.scala 104:41] + node _T_617 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[lib.scala 104:74] + node _T_618 = bits(dec_i0_match_data[1], 29, 29) @[lib.scala 104:86] + node _T_619 = eq(_T_617, _T_618) @[lib.scala 104:78] + node _T_620 = mux(_T_616, UInt<1>("h01"), _T_619) @[lib.scala 104:23] + _T_410[29] <= _T_620 @[lib.scala 104:17] + node _T_621 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[lib.scala 104:28] + node _T_622 = andr(_T_621) @[lib.scala 104:36] + node _T_623 = and(_T_622, _T_413) @[lib.scala 104:41] + node _T_624 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[lib.scala 104:74] + node _T_625 = bits(dec_i0_match_data[1], 30, 30) @[lib.scala 104:86] + node _T_626 = eq(_T_624, _T_625) @[lib.scala 104:78] + node _T_627 = mux(_T_623, UInt<1>("h01"), _T_626) @[lib.scala 104:23] + _T_410[30] <= _T_627 @[lib.scala 104:17] + node _T_628 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[lib.scala 104:28] + node _T_629 = andr(_T_628) @[lib.scala 104:36] + node _T_630 = and(_T_629, _T_413) @[lib.scala 104:41] + node _T_631 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[lib.scala 104:74] + node _T_632 = bits(dec_i0_match_data[1], 31, 31) @[lib.scala 104:86] + node _T_633 = eq(_T_631, _T_632) @[lib.scala 104:78] + node _T_634 = mux(_T_630, UInt<1>("h01"), _T_633) @[lib.scala 104:23] + _T_410[31] <= _T_634 @[lib.scala 104:17] + node _T_635 = cat(_T_410[1], _T_410[0]) @[lib.scala 105:14] + node _T_636 = cat(_T_410[3], _T_410[2]) @[lib.scala 105:14] + node _T_637 = cat(_T_636, _T_635) @[lib.scala 105:14] + node _T_638 = cat(_T_410[5], _T_410[4]) @[lib.scala 105:14] + node _T_639 = cat(_T_410[7], _T_410[6]) @[lib.scala 105:14] + node _T_640 = cat(_T_639, _T_638) @[lib.scala 105:14] + node _T_641 = cat(_T_640, _T_637) @[lib.scala 105:14] + node _T_642 = cat(_T_410[9], _T_410[8]) @[lib.scala 105:14] + node _T_643 = cat(_T_410[11], _T_410[10]) @[lib.scala 105:14] + node _T_644 = cat(_T_643, _T_642) @[lib.scala 105:14] + node _T_645 = cat(_T_410[13], _T_410[12]) @[lib.scala 105:14] + node _T_646 = cat(_T_410[15], _T_410[14]) @[lib.scala 105:14] + node _T_647 = cat(_T_646, _T_645) @[lib.scala 105:14] + node _T_648 = cat(_T_647, _T_644) @[lib.scala 105:14] + node _T_649 = cat(_T_648, _T_641) @[lib.scala 105:14] + node _T_650 = cat(_T_410[17], _T_410[16]) @[lib.scala 105:14] + node _T_651 = cat(_T_410[19], _T_410[18]) @[lib.scala 105:14] + node _T_652 = cat(_T_651, _T_650) @[lib.scala 105:14] + node _T_653 = cat(_T_410[21], _T_410[20]) @[lib.scala 105:14] + node _T_654 = cat(_T_410[23], _T_410[22]) @[lib.scala 105:14] + node _T_655 = cat(_T_654, _T_653) @[lib.scala 105:14] + node _T_656 = cat(_T_655, _T_652) @[lib.scala 105:14] + node _T_657 = cat(_T_410[25], _T_410[24]) @[lib.scala 105:14] + node _T_658 = cat(_T_410[27], _T_410[26]) @[lib.scala 105:14] + node _T_659 = cat(_T_658, _T_657) @[lib.scala 105:14] + node _T_660 = cat(_T_410[29], _T_410[28]) @[lib.scala 105:14] + node _T_661 = cat(_T_410[31], _T_410[30]) @[lib.scala 105:14] + node _T_662 = cat(_T_661, _T_660) @[lib.scala 105:14] + node _T_663 = cat(_T_662, _T_659) @[lib.scala 105:14] + node _T_664 = cat(_T_663, _T_656) @[lib.scala 105:14] + node _T_665 = cat(_T_664, _T_649) @[lib.scala 105:14] + node _T_666 = andr(_T_665) @[lib.scala 105:25] + node _T_667 = and(_T_408, _T_666) @[dec_trigger.scala 15:109] + node _T_668 = and(io.trigger_pkt_any[2].execute, io.trigger_pkt_any[2].m) @[dec_trigger.scala 15:83] + node _T_669 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[dec_trigger.scala 15:216] + wire _T_670 : UInt<1>[32] @[lib.scala 100:24] + node _T_671 = andr(io.trigger_pkt_any[2].tdata2) @[lib.scala 101:45] + node _T_672 = not(_T_671) @[lib.scala 101:39] + node _T_673 = and(_T_669, _T_672) @[lib.scala 101:37] + node _T_674 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 102:48] + node _T_675 = bits(dec_i0_match_data[2], 0, 0) @[lib.scala 102:60] + node _T_676 = eq(_T_674, _T_675) @[lib.scala 102:52] + node _T_677 = or(_T_673, _T_676) @[lib.scala 102:41] + _T_670[0] <= _T_677 @[lib.scala 102:18] + node _T_678 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 104:28] + node _T_679 = andr(_T_678) @[lib.scala 104:36] + node _T_680 = and(_T_679, _T_673) @[lib.scala 104:41] + node _T_681 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[lib.scala 104:74] + node _T_682 = bits(dec_i0_match_data[2], 1, 1) @[lib.scala 104:86] + node _T_683 = eq(_T_681, _T_682) @[lib.scala 104:78] + node _T_684 = mux(_T_680, UInt<1>("h01"), _T_683) @[lib.scala 104:23] + _T_670[1] <= _T_684 @[lib.scala 104:17] + node _T_685 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[lib.scala 104:28] + node _T_686 = andr(_T_685) @[lib.scala 104:36] + node _T_687 = and(_T_686, _T_673) @[lib.scala 104:41] + node _T_688 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[lib.scala 104:74] + node _T_689 = bits(dec_i0_match_data[2], 2, 2) @[lib.scala 104:86] + node _T_690 = eq(_T_688, _T_689) @[lib.scala 104:78] + node _T_691 = mux(_T_687, UInt<1>("h01"), _T_690) @[lib.scala 104:23] + _T_670[2] <= _T_691 @[lib.scala 104:17] + node _T_692 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[lib.scala 104:28] + node _T_693 = andr(_T_692) @[lib.scala 104:36] + node _T_694 = and(_T_693, _T_673) @[lib.scala 104:41] + node _T_695 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[lib.scala 104:74] + node _T_696 = bits(dec_i0_match_data[2], 3, 3) @[lib.scala 104:86] + node _T_697 = eq(_T_695, _T_696) @[lib.scala 104:78] + node _T_698 = mux(_T_694, UInt<1>("h01"), _T_697) @[lib.scala 104:23] + _T_670[3] <= _T_698 @[lib.scala 104:17] + node _T_699 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[lib.scala 104:28] + node _T_700 = andr(_T_699) @[lib.scala 104:36] + node _T_701 = and(_T_700, _T_673) @[lib.scala 104:41] + node _T_702 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[lib.scala 104:74] + node _T_703 = bits(dec_i0_match_data[2], 4, 4) @[lib.scala 104:86] + node _T_704 = eq(_T_702, _T_703) @[lib.scala 104:78] + node _T_705 = mux(_T_701, UInt<1>("h01"), _T_704) @[lib.scala 104:23] + _T_670[4] <= _T_705 @[lib.scala 104:17] + node _T_706 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[lib.scala 104:28] + node _T_707 = andr(_T_706) @[lib.scala 104:36] + node _T_708 = and(_T_707, _T_673) @[lib.scala 104:41] + node _T_709 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[lib.scala 104:74] + node _T_710 = bits(dec_i0_match_data[2], 5, 5) @[lib.scala 104:86] + node _T_711 = eq(_T_709, _T_710) @[lib.scala 104:78] + node _T_712 = mux(_T_708, UInt<1>("h01"), _T_711) @[lib.scala 104:23] + _T_670[5] <= _T_712 @[lib.scala 104:17] + node _T_713 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[lib.scala 104:28] + node _T_714 = andr(_T_713) @[lib.scala 104:36] + node _T_715 = and(_T_714, _T_673) @[lib.scala 104:41] + node _T_716 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[lib.scala 104:74] + node _T_717 = bits(dec_i0_match_data[2], 6, 6) @[lib.scala 104:86] + node _T_718 = eq(_T_716, _T_717) @[lib.scala 104:78] + node _T_719 = mux(_T_715, UInt<1>("h01"), _T_718) @[lib.scala 104:23] + _T_670[6] <= _T_719 @[lib.scala 104:17] + node _T_720 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[lib.scala 104:28] + node _T_721 = andr(_T_720) @[lib.scala 104:36] + node _T_722 = and(_T_721, _T_673) @[lib.scala 104:41] + node _T_723 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[lib.scala 104:74] + node _T_724 = bits(dec_i0_match_data[2], 7, 7) @[lib.scala 104:86] + node _T_725 = eq(_T_723, _T_724) @[lib.scala 104:78] + node _T_726 = mux(_T_722, UInt<1>("h01"), _T_725) @[lib.scala 104:23] + _T_670[7] <= _T_726 @[lib.scala 104:17] + node _T_727 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[lib.scala 104:28] + node _T_728 = andr(_T_727) @[lib.scala 104:36] + node _T_729 = and(_T_728, _T_673) @[lib.scala 104:41] + node _T_730 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[lib.scala 104:74] + node _T_731 = bits(dec_i0_match_data[2], 8, 8) @[lib.scala 104:86] + node _T_732 = eq(_T_730, _T_731) @[lib.scala 104:78] + node _T_733 = mux(_T_729, UInt<1>("h01"), _T_732) @[lib.scala 104:23] + _T_670[8] <= _T_733 @[lib.scala 104:17] + node _T_734 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[lib.scala 104:28] + node _T_735 = andr(_T_734) @[lib.scala 104:36] + node _T_736 = and(_T_735, _T_673) @[lib.scala 104:41] + node _T_737 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[lib.scala 104:74] + node _T_738 = bits(dec_i0_match_data[2], 9, 9) @[lib.scala 104:86] + node _T_739 = eq(_T_737, _T_738) @[lib.scala 104:78] + node _T_740 = mux(_T_736, UInt<1>("h01"), _T_739) @[lib.scala 104:23] + _T_670[9] <= _T_740 @[lib.scala 104:17] + node _T_741 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[lib.scala 104:28] + node _T_742 = andr(_T_741) @[lib.scala 104:36] + node _T_743 = and(_T_742, _T_673) @[lib.scala 104:41] + node _T_744 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[lib.scala 104:74] + node _T_745 = bits(dec_i0_match_data[2], 10, 10) @[lib.scala 104:86] + node _T_746 = eq(_T_744, _T_745) @[lib.scala 104:78] + node _T_747 = mux(_T_743, UInt<1>("h01"), _T_746) @[lib.scala 104:23] + _T_670[10] <= _T_747 @[lib.scala 104:17] + node _T_748 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[lib.scala 104:28] + node _T_749 = andr(_T_748) @[lib.scala 104:36] + node _T_750 = and(_T_749, _T_673) @[lib.scala 104:41] + node _T_751 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[lib.scala 104:74] + node _T_752 = bits(dec_i0_match_data[2], 11, 11) @[lib.scala 104:86] + node _T_753 = eq(_T_751, _T_752) @[lib.scala 104:78] + node _T_754 = mux(_T_750, UInt<1>("h01"), _T_753) @[lib.scala 104:23] + _T_670[11] <= _T_754 @[lib.scala 104:17] + node _T_755 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[lib.scala 104:28] + node _T_756 = andr(_T_755) @[lib.scala 104:36] + node _T_757 = and(_T_756, _T_673) @[lib.scala 104:41] + node _T_758 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[lib.scala 104:74] + node _T_759 = bits(dec_i0_match_data[2], 12, 12) @[lib.scala 104:86] + node _T_760 = eq(_T_758, _T_759) @[lib.scala 104:78] + node _T_761 = mux(_T_757, UInt<1>("h01"), _T_760) @[lib.scala 104:23] + _T_670[12] <= _T_761 @[lib.scala 104:17] + node _T_762 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[lib.scala 104:28] + node _T_763 = andr(_T_762) @[lib.scala 104:36] + node _T_764 = and(_T_763, _T_673) @[lib.scala 104:41] + node _T_765 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[lib.scala 104:74] + node _T_766 = bits(dec_i0_match_data[2], 13, 13) @[lib.scala 104:86] + node _T_767 = eq(_T_765, _T_766) @[lib.scala 104:78] + node _T_768 = mux(_T_764, UInt<1>("h01"), _T_767) @[lib.scala 104:23] + _T_670[13] <= _T_768 @[lib.scala 104:17] + node _T_769 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[lib.scala 104:28] + node _T_770 = andr(_T_769) @[lib.scala 104:36] + node _T_771 = and(_T_770, _T_673) @[lib.scala 104:41] + node _T_772 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[lib.scala 104:74] + node _T_773 = bits(dec_i0_match_data[2], 14, 14) @[lib.scala 104:86] + node _T_774 = eq(_T_772, _T_773) @[lib.scala 104:78] + node _T_775 = mux(_T_771, UInt<1>("h01"), _T_774) @[lib.scala 104:23] + _T_670[14] <= _T_775 @[lib.scala 104:17] + node _T_776 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[lib.scala 104:28] + node _T_777 = andr(_T_776) @[lib.scala 104:36] + node _T_778 = and(_T_777, _T_673) @[lib.scala 104:41] + node _T_779 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[lib.scala 104:74] + node _T_780 = bits(dec_i0_match_data[2], 15, 15) @[lib.scala 104:86] + node _T_781 = eq(_T_779, _T_780) @[lib.scala 104:78] + node _T_782 = mux(_T_778, UInt<1>("h01"), _T_781) @[lib.scala 104:23] + _T_670[15] <= _T_782 @[lib.scala 104:17] + node _T_783 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[lib.scala 104:28] + node _T_784 = andr(_T_783) @[lib.scala 104:36] + node _T_785 = and(_T_784, _T_673) @[lib.scala 104:41] + node _T_786 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[lib.scala 104:74] + node _T_787 = bits(dec_i0_match_data[2], 16, 16) @[lib.scala 104:86] + node _T_788 = eq(_T_786, _T_787) @[lib.scala 104:78] + node _T_789 = mux(_T_785, UInt<1>("h01"), _T_788) @[lib.scala 104:23] + _T_670[16] <= _T_789 @[lib.scala 104:17] + node _T_790 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[lib.scala 104:28] + node _T_791 = andr(_T_790) @[lib.scala 104:36] + node _T_792 = and(_T_791, _T_673) @[lib.scala 104:41] + node _T_793 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[lib.scala 104:74] + node _T_794 = bits(dec_i0_match_data[2], 17, 17) @[lib.scala 104:86] + node _T_795 = eq(_T_793, _T_794) @[lib.scala 104:78] + node _T_796 = mux(_T_792, UInt<1>("h01"), _T_795) @[lib.scala 104:23] + _T_670[17] <= _T_796 @[lib.scala 104:17] + node _T_797 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[lib.scala 104:28] + node _T_798 = andr(_T_797) @[lib.scala 104:36] + node _T_799 = and(_T_798, _T_673) @[lib.scala 104:41] + node _T_800 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[lib.scala 104:74] + node _T_801 = bits(dec_i0_match_data[2], 18, 18) @[lib.scala 104:86] + node _T_802 = eq(_T_800, _T_801) @[lib.scala 104:78] + node _T_803 = mux(_T_799, UInt<1>("h01"), _T_802) @[lib.scala 104:23] + _T_670[18] <= _T_803 @[lib.scala 104:17] + node _T_804 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[lib.scala 104:28] + node _T_805 = andr(_T_804) @[lib.scala 104:36] + node _T_806 = and(_T_805, _T_673) @[lib.scala 104:41] + node _T_807 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[lib.scala 104:74] + node _T_808 = bits(dec_i0_match_data[2], 19, 19) @[lib.scala 104:86] + node _T_809 = eq(_T_807, _T_808) @[lib.scala 104:78] + node _T_810 = mux(_T_806, UInt<1>("h01"), _T_809) @[lib.scala 104:23] + _T_670[19] <= _T_810 @[lib.scala 104:17] + node _T_811 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[lib.scala 104:28] + node _T_812 = andr(_T_811) @[lib.scala 104:36] + node _T_813 = and(_T_812, _T_673) @[lib.scala 104:41] + node _T_814 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[lib.scala 104:74] + node _T_815 = bits(dec_i0_match_data[2], 20, 20) @[lib.scala 104:86] + node _T_816 = eq(_T_814, _T_815) @[lib.scala 104:78] + node _T_817 = mux(_T_813, UInt<1>("h01"), _T_816) @[lib.scala 104:23] + _T_670[20] <= _T_817 @[lib.scala 104:17] + node _T_818 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[lib.scala 104:28] + node _T_819 = andr(_T_818) @[lib.scala 104:36] + node _T_820 = and(_T_819, _T_673) @[lib.scala 104:41] + node _T_821 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[lib.scala 104:74] + node _T_822 = bits(dec_i0_match_data[2], 21, 21) @[lib.scala 104:86] + node _T_823 = eq(_T_821, _T_822) @[lib.scala 104:78] + node _T_824 = mux(_T_820, UInt<1>("h01"), _T_823) @[lib.scala 104:23] + _T_670[21] <= _T_824 @[lib.scala 104:17] + node _T_825 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[lib.scala 104:28] + node _T_826 = andr(_T_825) @[lib.scala 104:36] + node _T_827 = and(_T_826, _T_673) @[lib.scala 104:41] + node _T_828 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[lib.scala 104:74] + node _T_829 = bits(dec_i0_match_data[2], 22, 22) @[lib.scala 104:86] + node _T_830 = eq(_T_828, _T_829) @[lib.scala 104:78] + node _T_831 = mux(_T_827, UInt<1>("h01"), _T_830) @[lib.scala 104:23] + _T_670[22] <= _T_831 @[lib.scala 104:17] + node _T_832 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[lib.scala 104:28] + node _T_833 = andr(_T_832) @[lib.scala 104:36] + node _T_834 = and(_T_833, _T_673) @[lib.scala 104:41] + node _T_835 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[lib.scala 104:74] + node _T_836 = bits(dec_i0_match_data[2], 23, 23) @[lib.scala 104:86] + node _T_837 = eq(_T_835, _T_836) @[lib.scala 104:78] + node _T_838 = mux(_T_834, UInt<1>("h01"), _T_837) @[lib.scala 104:23] + _T_670[23] <= _T_838 @[lib.scala 104:17] + node _T_839 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[lib.scala 104:28] + node _T_840 = andr(_T_839) @[lib.scala 104:36] + node _T_841 = and(_T_840, _T_673) @[lib.scala 104:41] + node _T_842 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[lib.scala 104:74] + node _T_843 = bits(dec_i0_match_data[2], 24, 24) @[lib.scala 104:86] + node _T_844 = eq(_T_842, _T_843) @[lib.scala 104:78] + node _T_845 = mux(_T_841, UInt<1>("h01"), _T_844) @[lib.scala 104:23] + _T_670[24] <= _T_845 @[lib.scala 104:17] + node _T_846 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[lib.scala 104:28] + node _T_847 = andr(_T_846) @[lib.scala 104:36] + node _T_848 = and(_T_847, _T_673) @[lib.scala 104:41] + node _T_849 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[lib.scala 104:74] + node _T_850 = bits(dec_i0_match_data[2], 25, 25) @[lib.scala 104:86] + node _T_851 = eq(_T_849, _T_850) @[lib.scala 104:78] + node _T_852 = mux(_T_848, UInt<1>("h01"), _T_851) @[lib.scala 104:23] + _T_670[25] <= _T_852 @[lib.scala 104:17] + node _T_853 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[lib.scala 104:28] + node _T_854 = andr(_T_853) @[lib.scala 104:36] + node _T_855 = and(_T_854, _T_673) @[lib.scala 104:41] + node _T_856 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[lib.scala 104:74] + node _T_857 = bits(dec_i0_match_data[2], 26, 26) @[lib.scala 104:86] + node _T_858 = eq(_T_856, _T_857) @[lib.scala 104:78] + node _T_859 = mux(_T_855, UInt<1>("h01"), _T_858) @[lib.scala 104:23] + _T_670[26] <= _T_859 @[lib.scala 104:17] + node _T_860 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[lib.scala 104:28] + node _T_861 = andr(_T_860) @[lib.scala 104:36] + node _T_862 = and(_T_861, _T_673) @[lib.scala 104:41] + node _T_863 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[lib.scala 104:74] + node _T_864 = bits(dec_i0_match_data[2], 27, 27) @[lib.scala 104:86] + node _T_865 = eq(_T_863, _T_864) @[lib.scala 104:78] + node _T_866 = mux(_T_862, UInt<1>("h01"), _T_865) @[lib.scala 104:23] + _T_670[27] <= _T_866 @[lib.scala 104:17] + node _T_867 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[lib.scala 104:28] + node _T_868 = andr(_T_867) @[lib.scala 104:36] + node _T_869 = and(_T_868, _T_673) @[lib.scala 104:41] + node _T_870 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[lib.scala 104:74] + node _T_871 = bits(dec_i0_match_data[2], 28, 28) @[lib.scala 104:86] + node _T_872 = eq(_T_870, _T_871) @[lib.scala 104:78] + node _T_873 = mux(_T_869, UInt<1>("h01"), _T_872) @[lib.scala 104:23] + _T_670[28] <= _T_873 @[lib.scala 104:17] + node _T_874 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[lib.scala 104:28] + node _T_875 = andr(_T_874) @[lib.scala 104:36] + node _T_876 = and(_T_875, _T_673) @[lib.scala 104:41] + node _T_877 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[lib.scala 104:74] + node _T_878 = bits(dec_i0_match_data[2], 29, 29) @[lib.scala 104:86] + node _T_879 = eq(_T_877, _T_878) @[lib.scala 104:78] + node _T_880 = mux(_T_876, UInt<1>("h01"), _T_879) @[lib.scala 104:23] + _T_670[29] <= _T_880 @[lib.scala 104:17] + node _T_881 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[lib.scala 104:28] + node _T_882 = andr(_T_881) @[lib.scala 104:36] + node _T_883 = and(_T_882, _T_673) @[lib.scala 104:41] + node _T_884 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[lib.scala 104:74] + node _T_885 = bits(dec_i0_match_data[2], 30, 30) @[lib.scala 104:86] + node _T_886 = eq(_T_884, _T_885) @[lib.scala 104:78] + node _T_887 = mux(_T_883, UInt<1>("h01"), _T_886) @[lib.scala 104:23] + _T_670[30] <= _T_887 @[lib.scala 104:17] + node _T_888 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[lib.scala 104:28] + node _T_889 = andr(_T_888) @[lib.scala 104:36] + node _T_890 = and(_T_889, _T_673) @[lib.scala 104:41] + node _T_891 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[lib.scala 104:74] + node _T_892 = bits(dec_i0_match_data[2], 31, 31) @[lib.scala 104:86] + node _T_893 = eq(_T_891, _T_892) @[lib.scala 104:78] + node _T_894 = mux(_T_890, UInt<1>("h01"), _T_893) @[lib.scala 104:23] + _T_670[31] <= _T_894 @[lib.scala 104:17] + node _T_895 = cat(_T_670[1], _T_670[0]) @[lib.scala 105:14] + node _T_896 = cat(_T_670[3], _T_670[2]) @[lib.scala 105:14] + node _T_897 = cat(_T_896, _T_895) @[lib.scala 105:14] + node _T_898 = cat(_T_670[5], _T_670[4]) @[lib.scala 105:14] + node _T_899 = cat(_T_670[7], _T_670[6]) @[lib.scala 105:14] + node _T_900 = cat(_T_899, _T_898) @[lib.scala 105:14] + node _T_901 = cat(_T_900, _T_897) @[lib.scala 105:14] + node _T_902 = cat(_T_670[9], _T_670[8]) @[lib.scala 105:14] + node _T_903 = cat(_T_670[11], _T_670[10]) @[lib.scala 105:14] + node _T_904 = cat(_T_903, _T_902) @[lib.scala 105:14] + node _T_905 = cat(_T_670[13], _T_670[12]) @[lib.scala 105:14] + node _T_906 = cat(_T_670[15], _T_670[14]) @[lib.scala 105:14] + node _T_907 = cat(_T_906, _T_905) @[lib.scala 105:14] + node _T_908 = cat(_T_907, _T_904) @[lib.scala 105:14] + node _T_909 = cat(_T_908, _T_901) @[lib.scala 105:14] + node _T_910 = cat(_T_670[17], _T_670[16]) @[lib.scala 105:14] + node _T_911 = cat(_T_670[19], _T_670[18]) @[lib.scala 105:14] + node _T_912 = cat(_T_911, _T_910) @[lib.scala 105:14] + node _T_913 = cat(_T_670[21], _T_670[20]) @[lib.scala 105:14] + node _T_914 = cat(_T_670[23], _T_670[22]) @[lib.scala 105:14] + node _T_915 = cat(_T_914, _T_913) @[lib.scala 105:14] + node _T_916 = cat(_T_915, _T_912) @[lib.scala 105:14] + node _T_917 = cat(_T_670[25], _T_670[24]) @[lib.scala 105:14] + node _T_918 = cat(_T_670[27], _T_670[26]) @[lib.scala 105:14] + node _T_919 = cat(_T_918, _T_917) @[lib.scala 105:14] + node _T_920 = cat(_T_670[29], _T_670[28]) @[lib.scala 105:14] + node _T_921 = cat(_T_670[31], _T_670[30]) @[lib.scala 105:14] + node _T_922 = cat(_T_921, _T_920) @[lib.scala 105:14] + node _T_923 = cat(_T_922, _T_919) @[lib.scala 105:14] + node _T_924 = cat(_T_923, _T_916) @[lib.scala 105:14] + node _T_925 = cat(_T_924, _T_909) @[lib.scala 105:14] + node _T_926 = andr(_T_925) @[lib.scala 105:25] + node _T_927 = and(_T_668, _T_926) @[dec_trigger.scala 15:109] + node _T_928 = and(io.trigger_pkt_any[3].execute, io.trigger_pkt_any[3].m) @[dec_trigger.scala 15:83] + node _T_929 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[dec_trigger.scala 15:216] + wire _T_930 : UInt<1>[32] @[lib.scala 100:24] + node _T_931 = andr(io.trigger_pkt_any[3].tdata2) @[lib.scala 101:45] + node _T_932 = not(_T_931) @[lib.scala 101:39] + node _T_933 = and(_T_929, _T_932) @[lib.scala 101:37] + node _T_934 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 102:48] + node _T_935 = bits(dec_i0_match_data[3], 0, 0) @[lib.scala 102:60] + node _T_936 = eq(_T_934, _T_935) @[lib.scala 102:52] + node _T_937 = or(_T_933, _T_936) @[lib.scala 102:41] + _T_930[0] <= _T_937 @[lib.scala 102:18] + node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 104:28] + node _T_939 = andr(_T_938) @[lib.scala 104:36] + node _T_940 = and(_T_939, _T_933) @[lib.scala 104:41] + node _T_941 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[lib.scala 104:74] + node _T_942 = bits(dec_i0_match_data[3], 1, 1) @[lib.scala 104:86] + node _T_943 = eq(_T_941, _T_942) @[lib.scala 104:78] + node _T_944 = mux(_T_940, UInt<1>("h01"), _T_943) @[lib.scala 104:23] + _T_930[1] <= _T_944 @[lib.scala 104:17] + node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[lib.scala 104:28] + node _T_946 = andr(_T_945) @[lib.scala 104:36] + node _T_947 = and(_T_946, _T_933) @[lib.scala 104:41] + node _T_948 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[lib.scala 104:74] + node _T_949 = bits(dec_i0_match_data[3], 2, 2) @[lib.scala 104:86] + node _T_950 = eq(_T_948, _T_949) @[lib.scala 104:78] + node _T_951 = mux(_T_947, UInt<1>("h01"), _T_950) @[lib.scala 104:23] + _T_930[2] <= _T_951 @[lib.scala 104:17] + node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[lib.scala 104:28] + node _T_953 = andr(_T_952) @[lib.scala 104:36] + node _T_954 = and(_T_953, _T_933) @[lib.scala 104:41] + node _T_955 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[lib.scala 104:74] + node _T_956 = bits(dec_i0_match_data[3], 3, 3) @[lib.scala 104:86] + node _T_957 = eq(_T_955, _T_956) @[lib.scala 104:78] + node _T_958 = mux(_T_954, UInt<1>("h01"), _T_957) @[lib.scala 104:23] + _T_930[3] <= _T_958 @[lib.scala 104:17] + node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[lib.scala 104:28] + node _T_960 = andr(_T_959) @[lib.scala 104:36] + node _T_961 = and(_T_960, _T_933) @[lib.scala 104:41] + node _T_962 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[lib.scala 104:74] + node _T_963 = bits(dec_i0_match_data[3], 4, 4) @[lib.scala 104:86] + node _T_964 = eq(_T_962, _T_963) @[lib.scala 104:78] + node _T_965 = mux(_T_961, UInt<1>("h01"), _T_964) @[lib.scala 104:23] + _T_930[4] <= _T_965 @[lib.scala 104:17] + node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[lib.scala 104:28] + node _T_967 = andr(_T_966) @[lib.scala 104:36] + node _T_968 = and(_T_967, _T_933) @[lib.scala 104:41] + node _T_969 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[lib.scala 104:74] + node _T_970 = bits(dec_i0_match_data[3], 5, 5) @[lib.scala 104:86] + node _T_971 = eq(_T_969, _T_970) @[lib.scala 104:78] + node _T_972 = mux(_T_968, UInt<1>("h01"), _T_971) @[lib.scala 104:23] + _T_930[5] <= _T_972 @[lib.scala 104:17] + node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[lib.scala 104:28] + node _T_974 = andr(_T_973) @[lib.scala 104:36] + node _T_975 = and(_T_974, _T_933) @[lib.scala 104:41] + node _T_976 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[lib.scala 104:74] + node _T_977 = bits(dec_i0_match_data[3], 6, 6) @[lib.scala 104:86] + node _T_978 = eq(_T_976, _T_977) @[lib.scala 104:78] + node _T_979 = mux(_T_975, UInt<1>("h01"), _T_978) @[lib.scala 104:23] + _T_930[6] <= _T_979 @[lib.scala 104:17] + node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[lib.scala 104:28] + node _T_981 = andr(_T_980) @[lib.scala 104:36] + node _T_982 = and(_T_981, _T_933) @[lib.scala 104:41] + node _T_983 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[lib.scala 104:74] + node _T_984 = bits(dec_i0_match_data[3], 7, 7) @[lib.scala 104:86] + node _T_985 = eq(_T_983, _T_984) @[lib.scala 104:78] + node _T_986 = mux(_T_982, UInt<1>("h01"), _T_985) @[lib.scala 104:23] + _T_930[7] <= _T_986 @[lib.scala 104:17] + node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[lib.scala 104:28] + node _T_988 = andr(_T_987) @[lib.scala 104:36] + node _T_989 = and(_T_988, _T_933) @[lib.scala 104:41] + node _T_990 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[lib.scala 104:74] + node _T_991 = bits(dec_i0_match_data[3], 8, 8) @[lib.scala 104:86] + node _T_992 = eq(_T_990, _T_991) @[lib.scala 104:78] + node _T_993 = mux(_T_989, UInt<1>("h01"), _T_992) @[lib.scala 104:23] + _T_930[8] <= _T_993 @[lib.scala 104:17] + node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[lib.scala 104:28] + node _T_995 = andr(_T_994) @[lib.scala 104:36] + node _T_996 = and(_T_995, _T_933) @[lib.scala 104:41] + node _T_997 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[lib.scala 104:74] + node _T_998 = bits(dec_i0_match_data[3], 9, 9) @[lib.scala 104:86] + node _T_999 = eq(_T_997, _T_998) @[lib.scala 104:78] + node _T_1000 = mux(_T_996, UInt<1>("h01"), _T_999) @[lib.scala 104:23] + _T_930[9] <= _T_1000 @[lib.scala 104:17] + node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[lib.scala 104:28] + node _T_1002 = andr(_T_1001) @[lib.scala 104:36] + node _T_1003 = and(_T_1002, _T_933) @[lib.scala 104:41] + node _T_1004 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[lib.scala 104:74] + node _T_1005 = bits(dec_i0_match_data[3], 10, 10) @[lib.scala 104:86] + node _T_1006 = eq(_T_1004, _T_1005) @[lib.scala 104:78] + node _T_1007 = mux(_T_1003, UInt<1>("h01"), _T_1006) @[lib.scala 104:23] + _T_930[10] <= _T_1007 @[lib.scala 104:17] + node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[lib.scala 104:28] + node _T_1009 = andr(_T_1008) @[lib.scala 104:36] + node _T_1010 = and(_T_1009, _T_933) @[lib.scala 104:41] + node _T_1011 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[lib.scala 104:74] + node _T_1012 = bits(dec_i0_match_data[3], 11, 11) @[lib.scala 104:86] + node _T_1013 = eq(_T_1011, _T_1012) @[lib.scala 104:78] + node _T_1014 = mux(_T_1010, UInt<1>("h01"), _T_1013) @[lib.scala 104:23] + _T_930[11] <= _T_1014 @[lib.scala 104:17] + node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[lib.scala 104:28] + node _T_1016 = andr(_T_1015) @[lib.scala 104:36] + node _T_1017 = and(_T_1016, _T_933) @[lib.scala 104:41] + node _T_1018 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[lib.scala 104:74] + node _T_1019 = bits(dec_i0_match_data[3], 12, 12) @[lib.scala 104:86] + node _T_1020 = eq(_T_1018, _T_1019) @[lib.scala 104:78] + node _T_1021 = mux(_T_1017, UInt<1>("h01"), _T_1020) @[lib.scala 104:23] + _T_930[12] <= _T_1021 @[lib.scala 104:17] + node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[lib.scala 104:28] + node _T_1023 = andr(_T_1022) @[lib.scala 104:36] + node _T_1024 = and(_T_1023, _T_933) @[lib.scala 104:41] + node _T_1025 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[lib.scala 104:74] + node _T_1026 = bits(dec_i0_match_data[3], 13, 13) @[lib.scala 104:86] + node _T_1027 = eq(_T_1025, _T_1026) @[lib.scala 104:78] + node _T_1028 = mux(_T_1024, UInt<1>("h01"), _T_1027) @[lib.scala 104:23] + _T_930[13] <= _T_1028 @[lib.scala 104:17] + node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[lib.scala 104:28] + node _T_1030 = andr(_T_1029) @[lib.scala 104:36] + node _T_1031 = and(_T_1030, _T_933) @[lib.scala 104:41] + node _T_1032 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[lib.scala 104:74] + node _T_1033 = bits(dec_i0_match_data[3], 14, 14) @[lib.scala 104:86] + node _T_1034 = eq(_T_1032, _T_1033) @[lib.scala 104:78] + node _T_1035 = mux(_T_1031, UInt<1>("h01"), _T_1034) @[lib.scala 104:23] + _T_930[14] <= _T_1035 @[lib.scala 104:17] + node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[lib.scala 104:28] + node _T_1037 = andr(_T_1036) @[lib.scala 104:36] + node _T_1038 = and(_T_1037, _T_933) @[lib.scala 104:41] + node _T_1039 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[lib.scala 104:74] + node _T_1040 = bits(dec_i0_match_data[3], 15, 15) @[lib.scala 104:86] + node _T_1041 = eq(_T_1039, _T_1040) @[lib.scala 104:78] + node _T_1042 = mux(_T_1038, UInt<1>("h01"), _T_1041) @[lib.scala 104:23] + _T_930[15] <= _T_1042 @[lib.scala 104:17] + node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[lib.scala 104:28] + node _T_1044 = andr(_T_1043) @[lib.scala 104:36] + node _T_1045 = and(_T_1044, _T_933) @[lib.scala 104:41] + node _T_1046 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[lib.scala 104:74] + node _T_1047 = bits(dec_i0_match_data[3], 16, 16) @[lib.scala 104:86] + node _T_1048 = eq(_T_1046, _T_1047) @[lib.scala 104:78] + node _T_1049 = mux(_T_1045, UInt<1>("h01"), _T_1048) @[lib.scala 104:23] + _T_930[16] <= _T_1049 @[lib.scala 104:17] + node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[lib.scala 104:28] + node _T_1051 = andr(_T_1050) @[lib.scala 104:36] + node _T_1052 = and(_T_1051, _T_933) @[lib.scala 104:41] + node _T_1053 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[lib.scala 104:74] + node _T_1054 = bits(dec_i0_match_data[3], 17, 17) @[lib.scala 104:86] + node _T_1055 = eq(_T_1053, _T_1054) @[lib.scala 104:78] + node _T_1056 = mux(_T_1052, UInt<1>("h01"), _T_1055) @[lib.scala 104:23] + _T_930[17] <= _T_1056 @[lib.scala 104:17] + node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[lib.scala 104:28] + node _T_1058 = andr(_T_1057) @[lib.scala 104:36] + node _T_1059 = and(_T_1058, _T_933) @[lib.scala 104:41] + node _T_1060 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[lib.scala 104:74] + node _T_1061 = bits(dec_i0_match_data[3], 18, 18) @[lib.scala 104:86] + node _T_1062 = eq(_T_1060, _T_1061) @[lib.scala 104:78] + node _T_1063 = mux(_T_1059, UInt<1>("h01"), _T_1062) @[lib.scala 104:23] + _T_930[18] <= _T_1063 @[lib.scala 104:17] + node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[lib.scala 104:28] + node _T_1065 = andr(_T_1064) @[lib.scala 104:36] + node _T_1066 = and(_T_1065, _T_933) @[lib.scala 104:41] + node _T_1067 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[lib.scala 104:74] + node _T_1068 = bits(dec_i0_match_data[3], 19, 19) @[lib.scala 104:86] + node _T_1069 = eq(_T_1067, _T_1068) @[lib.scala 104:78] + node _T_1070 = mux(_T_1066, UInt<1>("h01"), _T_1069) @[lib.scala 104:23] + _T_930[19] <= _T_1070 @[lib.scala 104:17] + node _T_1071 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[lib.scala 104:28] + node _T_1072 = andr(_T_1071) @[lib.scala 104:36] + node _T_1073 = and(_T_1072, _T_933) @[lib.scala 104:41] + node _T_1074 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[lib.scala 104:74] + node _T_1075 = bits(dec_i0_match_data[3], 20, 20) @[lib.scala 104:86] + node _T_1076 = eq(_T_1074, _T_1075) @[lib.scala 104:78] + node _T_1077 = mux(_T_1073, UInt<1>("h01"), _T_1076) @[lib.scala 104:23] + _T_930[20] <= _T_1077 @[lib.scala 104:17] + node _T_1078 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[lib.scala 104:28] + node _T_1079 = andr(_T_1078) @[lib.scala 104:36] + node _T_1080 = and(_T_1079, _T_933) @[lib.scala 104:41] + node _T_1081 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[lib.scala 104:74] + node _T_1082 = bits(dec_i0_match_data[3], 21, 21) @[lib.scala 104:86] + node _T_1083 = eq(_T_1081, _T_1082) @[lib.scala 104:78] + node _T_1084 = mux(_T_1080, UInt<1>("h01"), _T_1083) @[lib.scala 104:23] + _T_930[21] <= _T_1084 @[lib.scala 104:17] + node _T_1085 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[lib.scala 104:28] + node _T_1086 = andr(_T_1085) @[lib.scala 104:36] + node _T_1087 = and(_T_1086, _T_933) @[lib.scala 104:41] + node _T_1088 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[lib.scala 104:74] + node _T_1089 = bits(dec_i0_match_data[3], 22, 22) @[lib.scala 104:86] + node _T_1090 = eq(_T_1088, _T_1089) @[lib.scala 104:78] + node _T_1091 = mux(_T_1087, UInt<1>("h01"), _T_1090) @[lib.scala 104:23] + _T_930[22] <= _T_1091 @[lib.scala 104:17] + node _T_1092 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[lib.scala 104:28] + node _T_1093 = andr(_T_1092) @[lib.scala 104:36] + node _T_1094 = and(_T_1093, _T_933) @[lib.scala 104:41] + node _T_1095 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[lib.scala 104:74] + node _T_1096 = bits(dec_i0_match_data[3], 23, 23) @[lib.scala 104:86] + node _T_1097 = eq(_T_1095, _T_1096) @[lib.scala 104:78] + node _T_1098 = mux(_T_1094, UInt<1>("h01"), _T_1097) @[lib.scala 104:23] + _T_930[23] <= _T_1098 @[lib.scala 104:17] + node _T_1099 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[lib.scala 104:28] + node _T_1100 = andr(_T_1099) @[lib.scala 104:36] + node _T_1101 = and(_T_1100, _T_933) @[lib.scala 104:41] + node _T_1102 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[lib.scala 104:74] + node _T_1103 = bits(dec_i0_match_data[3], 24, 24) @[lib.scala 104:86] + node _T_1104 = eq(_T_1102, _T_1103) @[lib.scala 104:78] + node _T_1105 = mux(_T_1101, UInt<1>("h01"), _T_1104) @[lib.scala 104:23] + _T_930[24] <= _T_1105 @[lib.scala 104:17] + node _T_1106 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[lib.scala 104:28] + node _T_1107 = andr(_T_1106) @[lib.scala 104:36] + node _T_1108 = and(_T_1107, _T_933) @[lib.scala 104:41] + node _T_1109 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[lib.scala 104:74] + node _T_1110 = bits(dec_i0_match_data[3], 25, 25) @[lib.scala 104:86] + node _T_1111 = eq(_T_1109, _T_1110) @[lib.scala 104:78] + node _T_1112 = mux(_T_1108, UInt<1>("h01"), _T_1111) @[lib.scala 104:23] + _T_930[25] <= _T_1112 @[lib.scala 104:17] + node _T_1113 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[lib.scala 104:28] + node _T_1114 = andr(_T_1113) @[lib.scala 104:36] + node _T_1115 = and(_T_1114, _T_933) @[lib.scala 104:41] + node _T_1116 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[lib.scala 104:74] + node _T_1117 = bits(dec_i0_match_data[3], 26, 26) @[lib.scala 104:86] + node _T_1118 = eq(_T_1116, _T_1117) @[lib.scala 104:78] + node _T_1119 = mux(_T_1115, UInt<1>("h01"), _T_1118) @[lib.scala 104:23] + _T_930[26] <= _T_1119 @[lib.scala 104:17] + node _T_1120 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[lib.scala 104:28] + node _T_1121 = andr(_T_1120) @[lib.scala 104:36] + node _T_1122 = and(_T_1121, _T_933) @[lib.scala 104:41] + node _T_1123 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[lib.scala 104:74] + node _T_1124 = bits(dec_i0_match_data[3], 27, 27) @[lib.scala 104:86] + node _T_1125 = eq(_T_1123, _T_1124) @[lib.scala 104:78] + node _T_1126 = mux(_T_1122, UInt<1>("h01"), _T_1125) @[lib.scala 104:23] + _T_930[27] <= _T_1126 @[lib.scala 104:17] + node _T_1127 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[lib.scala 104:28] + node _T_1128 = andr(_T_1127) @[lib.scala 104:36] + node _T_1129 = and(_T_1128, _T_933) @[lib.scala 104:41] + node _T_1130 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[lib.scala 104:74] + node _T_1131 = bits(dec_i0_match_data[3], 28, 28) @[lib.scala 104:86] + node _T_1132 = eq(_T_1130, _T_1131) @[lib.scala 104:78] + node _T_1133 = mux(_T_1129, UInt<1>("h01"), _T_1132) @[lib.scala 104:23] + _T_930[28] <= _T_1133 @[lib.scala 104:17] + node _T_1134 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[lib.scala 104:28] + node _T_1135 = andr(_T_1134) @[lib.scala 104:36] + node _T_1136 = and(_T_1135, _T_933) @[lib.scala 104:41] + node _T_1137 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[lib.scala 104:74] + node _T_1138 = bits(dec_i0_match_data[3], 29, 29) @[lib.scala 104:86] + node _T_1139 = eq(_T_1137, _T_1138) @[lib.scala 104:78] + node _T_1140 = mux(_T_1136, UInt<1>("h01"), _T_1139) @[lib.scala 104:23] + _T_930[29] <= _T_1140 @[lib.scala 104:17] + node _T_1141 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[lib.scala 104:28] + node _T_1142 = andr(_T_1141) @[lib.scala 104:36] + node _T_1143 = and(_T_1142, _T_933) @[lib.scala 104:41] + node _T_1144 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[lib.scala 104:74] + node _T_1145 = bits(dec_i0_match_data[3], 30, 30) @[lib.scala 104:86] + node _T_1146 = eq(_T_1144, _T_1145) @[lib.scala 104:78] + node _T_1147 = mux(_T_1143, UInt<1>("h01"), _T_1146) @[lib.scala 104:23] + _T_930[30] <= _T_1147 @[lib.scala 104:17] + node _T_1148 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[lib.scala 104:28] + node _T_1149 = andr(_T_1148) @[lib.scala 104:36] + node _T_1150 = and(_T_1149, _T_933) @[lib.scala 104:41] + node _T_1151 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[lib.scala 104:74] + node _T_1152 = bits(dec_i0_match_data[3], 31, 31) @[lib.scala 104:86] + node _T_1153 = eq(_T_1151, _T_1152) @[lib.scala 104:78] + node _T_1154 = mux(_T_1150, UInt<1>("h01"), _T_1153) @[lib.scala 104:23] + _T_930[31] <= _T_1154 @[lib.scala 104:17] + node _T_1155 = cat(_T_930[1], _T_930[0]) @[lib.scala 105:14] + node _T_1156 = cat(_T_930[3], _T_930[2]) @[lib.scala 105:14] + node _T_1157 = cat(_T_1156, _T_1155) @[lib.scala 105:14] + node _T_1158 = cat(_T_930[5], _T_930[4]) @[lib.scala 105:14] + node _T_1159 = cat(_T_930[7], _T_930[6]) @[lib.scala 105:14] + node _T_1160 = cat(_T_1159, _T_1158) @[lib.scala 105:14] + node _T_1161 = cat(_T_1160, _T_1157) @[lib.scala 105:14] + node _T_1162 = cat(_T_930[9], _T_930[8]) @[lib.scala 105:14] + node _T_1163 = cat(_T_930[11], _T_930[10]) @[lib.scala 105:14] + node _T_1164 = cat(_T_1163, _T_1162) @[lib.scala 105:14] + node _T_1165 = cat(_T_930[13], _T_930[12]) @[lib.scala 105:14] + node _T_1166 = cat(_T_930[15], _T_930[14]) @[lib.scala 105:14] + node _T_1167 = cat(_T_1166, _T_1165) @[lib.scala 105:14] + node _T_1168 = cat(_T_1167, _T_1164) @[lib.scala 105:14] + node _T_1169 = cat(_T_1168, _T_1161) @[lib.scala 105:14] + node _T_1170 = cat(_T_930[17], _T_930[16]) @[lib.scala 105:14] + node _T_1171 = cat(_T_930[19], _T_930[18]) @[lib.scala 105:14] + node _T_1172 = cat(_T_1171, _T_1170) @[lib.scala 105:14] + node _T_1173 = cat(_T_930[21], _T_930[20]) @[lib.scala 105:14] + node _T_1174 = cat(_T_930[23], _T_930[22]) @[lib.scala 105:14] + node _T_1175 = cat(_T_1174, _T_1173) @[lib.scala 105:14] + node _T_1176 = cat(_T_1175, _T_1172) @[lib.scala 105:14] + node _T_1177 = cat(_T_930[25], _T_930[24]) @[lib.scala 105:14] + node _T_1178 = cat(_T_930[27], _T_930[26]) @[lib.scala 105:14] + node _T_1179 = cat(_T_1178, _T_1177) @[lib.scala 105:14] + node _T_1180 = cat(_T_930[29], _T_930[28]) @[lib.scala 105:14] + node _T_1181 = cat(_T_930[31], _T_930[30]) @[lib.scala 105:14] + node _T_1182 = cat(_T_1181, _T_1180) @[lib.scala 105:14] + node _T_1183 = cat(_T_1182, _T_1179) @[lib.scala 105:14] + node _T_1184 = cat(_T_1183, _T_1176) @[lib.scala 105:14] + node _T_1185 = cat(_T_1184, _T_1169) @[lib.scala 105:14] + node _T_1186 = andr(_T_1185) @[lib.scala 105:25] + node _T_1187 = and(_T_928, _T_1186) @[dec_trigger.scala 15:109] + node _T_1188 = cat(_T_1187, _T_927) @[Cat.scala 29:58] + node _T_1189 = cat(_T_1188, _T_667) @[Cat.scala 29:58] + node _T_1190 = cat(_T_1189, _T_407) @[Cat.scala 29:58] + io.dec_i0_trigger_match_d <= _T_1190 @[dec_trigger.scala 15:29] + + module dec : + input clock : Clock + input reset : AsyncReset + output io : {flip free_clk : Clock, flip active_clk : Clock, flip free_l2clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_pause_state_cg : UInt<1>, dec_tlu_core_empty : UInt<1>, flip rst_vec : UInt<31>, flip ifu_i0_fa_index : UInt<9>, dec_fa_error_index : UInt<9>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip lsu_nonblock_load_data : UInt<32>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip lsu_trigger_match_m : UInt<4>, flip lsu_idle_any : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_dbg_rddata : UInt<32>, dec_csr_rddata_d : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip exu_i0_br_way_r : UInt<1>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, dec_lsu_offset_d : UInt<12>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, trace_rv_trace_pkt : {rv_i_valid_ip : UInt<1>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<1>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<1>, rv_i_tval_ip : UInt<32>}, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_picio_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, flip scan_mode : UInt<1>, flip ifu_dec : {dec_aln : {aln_dec : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, aln_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_second : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, ifu_pmu_instr_aligned : UInt<1>}, dec_mem_ctrl : {flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, dec_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, dec_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}}, flip dec_exu : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_branch_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_result_r : UInt<32>, flip dec_qual_lsu_d : UInt<1>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<4>, flip dec_i0_rs2_bypass_en_d : UInt<4>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, gpr_exu : {flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>}}, flip lsu_dec : {tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>}}, flip lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, dec_dbg : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, dec_dma : {dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}}, dec_pic : {flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip mexintpend : UInt<1>}} + + wire dec_i0_inst_wb1 : UInt<32> + dec_i0_inst_wb1 <= UInt<1>("h00") + wire dec_i0_pc_wb1 : UInt<32> + dec_i0_pc_wb1 <= UInt<1>("h00") + wire dec_tlu_i0_valid_wb1 : UInt<1> + dec_tlu_i0_valid_wb1 <= UInt<1>("h00") + wire dec_tlu_int_valid_wb1 : UInt<1> + dec_tlu_int_valid_wb1 <= UInt<1>("h00") + wire dec_tlu_exc_cause_wb1 : UInt<5> + dec_tlu_exc_cause_wb1 <= UInt<1>("h00") + wire dec_tlu_mtval_wb1 : UInt<32> + dec_tlu_mtval_wb1 <= UInt<1>("h00") + wire dec_tlu_i0_exc_valid_wb1 : UInt<1> + dec_tlu_i0_exc_valid_wb1 <= UInt<1>("h00") + wire dec_tlu_trace_disable : UInt<1> + dec_tlu_trace_disable <= UInt<1>("h00") + inst instbuff of dec_ib_ctl @[dec.scala 128:24] + instbuff.clock <= clock + instbuff.reset <= reset + inst decode of dec_decode_ctl @[dec.scala 129:22] + decode.clock <= clock + decode.reset <= reset + inst gpr of dec_gpr_ctl @[dec.scala 130:19] + gpr.clock <= clock + gpr.reset <= reset + inst tlu of dec_tlu_ctl @[dec.scala 131:19] + tlu.clock <= clock + tlu.reset <= reset + inst dec_trigger of dec_trigger @[dec.scala 132:27] + dec_trigger.clock <= clock + dec_trigger.reset <= reset + instbuff.io.ifu_ib.i0_brp.bits.ret <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[dec.scala 136:22] + instbuff.io.ifu_ib.i0_brp.bits.way <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[dec.scala 136:22] + instbuff.io.ifu_ib.i0_brp.bits.prett <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[dec.scala 136:22] + instbuff.io.ifu_ib.i0_brp.bits.bank <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[dec.scala 136:22] + instbuff.io.ifu_ib.i0_brp.bits.br_start_error <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[dec.scala 136:22] + instbuff.io.ifu_ib.i0_brp.bits.br_error <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[dec.scala 136:22] + instbuff.io.ifu_ib.i0_brp.bits.hist <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[dec.scala 136:22] + instbuff.io.ifu_ib.i0_brp.bits.toffset <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[dec.scala 136:22] + instbuff.io.ifu_ib.i0_brp.valid <= io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[dec.scala 136:22] + instbuff.io.ifu_ib.ifu_i0_pc4 <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[dec.scala 136:22] + instbuff.io.ifu_ib.ifu_i0_pc <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[dec.scala 136:22] + instbuff.io.ifu_ib.ifu_i0_instr <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[dec.scala 136:22] + instbuff.io.ifu_ib.ifu_i0_valid <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[dec.scala 136:22] + instbuff.io.ifu_ib.ifu_i0_bp_btag <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[dec.scala 136:22] + instbuff.io.ifu_ib.ifu_i0_bp_fghr <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[dec.scala 136:22] + instbuff.io.ifu_ib.ifu_i0_bp_index <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[dec.scala 136:22] + instbuff.io.ifu_ib.ifu_i0_dbecc <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[dec.scala 136:22] + instbuff.io.ifu_ib.ifu_i0_icaf_second <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_second @[dec.scala 136:22] + instbuff.io.ifu_ib.ifu_i0_icaf_type <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[dec.scala 136:22] + instbuff.io.ifu_ib.ifu_i0_icaf <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[dec.scala 136:22] + io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= instbuff.io.ib_exu.dec_debug_wdata_rs1_d @[dec.scala 137:22] + io.dec_exu.ib_exu.dec_i0_pc_d <= instbuff.io.ib_exu.dec_i0_pc_d @[dec.scala 137:22] + instbuff.io.dbg_ib.dbg_cmd_addr <= io.dec_dbg.dbg_ib.dbg_cmd_addr @[dec.scala 138:22] + instbuff.io.dbg_ib.dbg_cmd_type <= io.dec_dbg.dbg_ib.dbg_cmd_type @[dec.scala 138:22] + instbuff.io.dbg_ib.dbg_cmd_write <= io.dec_dbg.dbg_ib.dbg_cmd_write @[dec.scala 138:22] + instbuff.io.dbg_ib.dbg_cmd_valid <= io.dec_dbg.dbg_ib.dbg_cmd_valid @[dec.scala 138:22] + instbuff.io.ifu_i0_fa_index <= io.ifu_i0_fa_index @[dec.scala 139:31] + dec_trigger.io.dec_i0_pc_d <= instbuff.io.ib_exu.dec_i0_pc_d @[dec.scala 140:30] + dec_trigger.io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[dec.scala 141:34] + dec_trigger.io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[dec.scala 141:34] + decode.io.dec_aln.ifu_i0_cinst <= io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[dec.scala 145:21] + io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d <= decode.io.dec_aln.dec_i0_decode_d @[dec.scala 145:21] + decode.io.decode_exu.exu_csr_rs1_x <= io.dec_exu.decode_exu.exu_csr_rs1_x @[dec.scala 147:23] + decode.io.decode_exu.exu_i0_result_x <= io.dec_exu.decode_exu.exu_i0_result_x @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_extint_stall <= decode.io.decode_exu.dec_extint_stall @[dec.scala 147:23] + io.dec_exu.decode_exu.pred_correct_npc_x <= decode.io.decode_exu.pred_correct_npc_x @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.bits.bfp <= decode.io.decode_exu.mul_p.bits.bfp @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= decode.io.decode_exu.mul_p.bits.crc32c_w @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= decode.io.decode_exu.mul_p.bits.crc32c_h @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= decode.io.decode_exu.mul_p.bits.crc32c_b @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.bits.crc32_w <= decode.io.decode_exu.mul_p.bits.crc32_w @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.bits.crc32_h <= decode.io.decode_exu.mul_p.bits.crc32_h @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.bits.crc32_b <= decode.io.decode_exu.mul_p.bits.crc32_b @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.bits.unshfl <= decode.io.decode_exu.mul_p.bits.unshfl @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.bits.shfl <= decode.io.decode_exu.mul_p.bits.shfl @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.bits.gorc <= decode.io.decode_exu.mul_p.bits.gorc @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.bits.grev <= decode.io.decode_exu.mul_p.bits.grev @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.bits.clmulr <= decode.io.decode_exu.mul_p.bits.clmulr @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.bits.clmulh <= decode.io.decode_exu.mul_p.bits.clmulh @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.bits.clmul <= decode.io.decode_exu.mul_p.bits.clmul @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.bits.bdep <= decode.io.decode_exu.mul_p.bits.bdep @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.bits.bext <= decode.io.decode_exu.mul_p.bits.bext @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.bits.low <= decode.io.decode_exu.mul_p.bits.low @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= decode.io.decode_exu.mul_p.bits.rs2_sign @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= decode.io.decode_exu.mul_p.bits.rs1_sign @[dec.scala 147:23] + io.dec_exu.decode_exu.mul_p.valid <= decode.io.decode_exu.mul_p.valid @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= decode.io.decode_exu.dec_i0_rs2_bypass_en_d @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= decode.io.decode_exu.dec_i0_rs1_bypass_en_d @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_select_pc_d <= decode.io.decode_exu.dec_i0_select_pc_d @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_qual_lsu_d <= decode.io.decode_exu.dec_qual_lsu_d @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_result_r <= decode.io.decode_exu.dec_i0_result_r @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_immed_d <= decode.io.decode_exu.dec_i0_immed_d @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_rs2_en_d <= decode.io.decode_exu.dec_i0_rs2_en_d @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_branch_d <= decode.io.decode_exu.dec_i0_branch_d @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_rs1_en_d <= decode.io.decode_exu.dec_i0_rs1_en_d @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_predict_btag_d <= decode.io.decode_exu.i0_predict_btag_d @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_predict_index_d <= decode.io.decode_exu.i0_predict_index_d @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_predict_fghr_d <= decode.io.decode_exu.i0_predict_fghr_d @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= decode.io.decode_exu.dec_i0_predict_p_d.bits.prett @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pret @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= decode.io.decode_exu.dec_i0_predict_p_d.bits.way @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pja @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pcall @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= decode.io.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= decode.io.decode_exu.dec_i0_predict_p_d.bits.br_error @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= decode.io.decode_exu.dec_i0_predict_p_d.bits.toffset @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= decode.io.decode_exu.dec_i0_predict_p_d.bits.hist @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pc4 @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= decode.io.decode_exu.dec_i0_predict_p_d.bits.boffset @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= decode.io.decode_exu.dec_i0_predict_p_d.bits.ataken @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= decode.io.decode_exu.dec_i0_predict_p_d.bits.misp @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= decode.io.decode_exu.dec_i0_predict_p_d.valid @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.csr_imm <= decode.io.decode_exu.i0_ap.csr_imm @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.csr_write <= decode.io.decode_exu.i0_ap.csr_write @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.predict_nt <= decode.io.decode_exu.i0_ap.predict_nt @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.predict_t <= decode.io.decode_exu.i0_ap.predict_t @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.jal <= decode.io.decode_exu.i0_ap.jal @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.unsign <= decode.io.decode_exu.i0_ap.unsign @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.slt <= decode.io.decode_exu.i0_ap.slt @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.sub <= decode.io.decode_exu.i0_ap.sub @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.add <= decode.io.decode_exu.i0_ap.add @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.bge <= decode.io.decode_exu.i0_ap.bge @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.blt <= decode.io.decode_exu.i0_ap.blt @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.bne <= decode.io.decode_exu.i0_ap.bne @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.beq <= decode.io.decode_exu.i0_ap.beq @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.sra <= decode.io.decode_exu.i0_ap.sra @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.srl <= decode.io.decode_exu.i0_ap.srl @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.sll <= decode.io.decode_exu.i0_ap.sll @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.lxor <= decode.io.decode_exu.i0_ap.lxor @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.lor <= decode.io.decode_exu.i0_ap.lor @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.land <= decode.io.decode_exu.i0_ap.land @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.zba <= decode.io.decode_exu.i0_ap.zba @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.sh3add <= decode.io.decode_exu.i0_ap.sh3add @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.sh2add <= decode.io.decode_exu.i0_ap.sh2add @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.sh1add <= decode.io.decode_exu.i0_ap.sh1add @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.sbext <= decode.io.decode_exu.i0_ap.sbext @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.sbinv <= decode.io.decode_exu.i0_ap.sbinv @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.sbclr <= decode.io.decode_exu.i0_ap.sbclr @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.sbset <= decode.io.decode_exu.i0_ap.sbset @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.zbb <= decode.io.decode_exu.i0_ap.zbb @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.gorc <= decode.io.decode_exu.i0_ap.gorc @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.grev <= decode.io.decode_exu.i0_ap.grev @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.ror <= decode.io.decode_exu.i0_ap.ror @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.rol <= decode.io.decode_exu.i0_ap.rol @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.packh <= decode.io.decode_exu.i0_ap.packh @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.packu <= decode.io.decode_exu.i0_ap.packu @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.pack <= decode.io.decode_exu.i0_ap.pack @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.max <= decode.io.decode_exu.i0_ap.max @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.min <= decode.io.decode_exu.i0_ap.min @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.sro <= decode.io.decode_exu.i0_ap.sro @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.slo <= decode.io.decode_exu.i0_ap.slo @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.sext_h <= decode.io.decode_exu.i0_ap.sext_h @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.sext_b <= decode.io.decode_exu.i0_ap.sext_b @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.pcnt <= decode.io.decode_exu.i0_ap.pcnt @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.ctz <= decode.io.decode_exu.i0_ap.ctz @[dec.scala 147:23] + io.dec_exu.decode_exu.i0_ap.clz <= decode.io.decode_exu.i0_ap.clz @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_ctl_en <= decode.io.decode_exu.dec_ctl_en @[dec.scala 147:23] + io.dec_exu.decode_exu.dec_data_en <= decode.io.decode_exu.dec_data_en @[dec.scala 147:23] + decode.io.dec_alu.exu_i0_pc_x <= io.dec_exu.dec_alu.exu_i0_pc_x @[dec.scala 148:20] + io.dec_exu.dec_alu.dec_i0_br_immed_d <= decode.io.dec_alu.dec_i0_br_immed_d @[dec.scala 148:20] + io.dec_exu.dec_alu.dec_csr_ren_d <= decode.io.dec_alu.dec_csr_ren_d @[dec.scala 148:20] + io.dec_exu.dec_alu.dec_i0_alu_decode_d <= decode.io.dec_alu.dec_i0_alu_decode_d @[dec.scala 148:20] + io.dec_exu.dec_div.dec_div_cancel <= decode.io.dec_div.dec_div_cancel @[dec.scala 149:20] + io.dec_exu.dec_div.div_p.bits.rem <= decode.io.dec_div.div_p.bits.rem @[dec.scala 149:20] + io.dec_exu.dec_div.div_p.bits.unsign <= decode.io.dec_div.div_p.bits.unsign @[dec.scala 149:20] + io.dec_exu.dec_div.div_p.valid <= decode.io.dec_div.div_p.valid @[dec.scala 149:20] + decode.io.dctl_dma.dma_dccm_stall_any <= io.dec_dma.dctl_dma.dma_dccm_stall_any @[dec.scala 150:22] + decode.io.dec_tlu_trace_disable <= tlu.io.dec_tlu_trace_disable @[dec.scala 151:48] + decode.io.dec_debug_valid_d <= instbuff.io.dec_debug_fence_d @[dec.scala 152:48] + decode.io.dec_tlu_flush_extint <= tlu.io.dec_tlu_flush_extint @[dec.scala 153:48] + decode.io.dec_tlu_force_halt <= tlu.io.tlu_mem.dec_tlu_force_halt @[dec.scala 154:48] + decode.io.dctl_busbuff.lsu_nonblock_load_data_tag <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[dec.scala 155:26] + decode.io.dctl_busbuff.lsu_nonblock_load_data_error <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[dec.scala 155:26] + decode.io.dctl_busbuff.lsu_nonblock_load_data_valid <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[dec.scala 155:26] + decode.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[dec.scala 155:26] + decode.io.dctl_busbuff.lsu_nonblock_load_inv_r <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[dec.scala 155:26] + decode.io.dctl_busbuff.lsu_nonblock_load_tag_m <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[dec.scala 155:26] + decode.io.dctl_busbuff.lsu_nonblock_load_valid_m <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[dec.scala 155:26] + decode.io.dec_i0_trigger_match_d <= dec_trigger.io.dec_i0_trigger_match_d @[dec.scala 156:48] + decode.io.dec_tlu_wr_pause_r <= tlu.io.dec_tlu_wr_pause_r @[dec.scala 157:48] + decode.io.dec_tlu_pipelining_disable <= tlu.io.dec_tlu_pipelining_disable @[dec.scala 158:48] + decode.io.lsu_trigger_match_m <= io.lsu_trigger_match_m @[dec.scala 159:48] + decode.io.lsu_pmu_misaligned_m <= io.lsu_pmu_misaligned_m @[dec.scala 160:48] + decode.io.dec_tlu_debug_stall <= tlu.io.dec_tlu_debug_stall @[dec.scala 161:48] + decode.io.dec_i0_bp_fa_index <= instbuff.io.dec_i0_bp_fa_index @[dec.scala 162:48] + decode.io.dec_tlu_flush_leak_one_r <= tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb @[dec.scala 163:48] + decode.io.dec_debug_fence_d <= instbuff.io.dec_debug_fence_d @[dec.scala 164:48] + decode.io.dbg_dctl.dbg_cmd_wrdata <= io.dec_dbg.dbg_dctl.dbg_cmd_wrdata @[dec.scala 165:22] + decode.io.dec_i0_icaf_d <= instbuff.io.dec_i0_icaf_d @[dec.scala 166:48] + decode.io.dec_i0_icaf_second_d <= instbuff.io.dec_i0_icaf_second_d @[dec.scala 167:48] + decode.io.dec_i0_icaf_type_d <= instbuff.io.dec_i0_icaf_type_d @[dec.scala 168:48] + decode.io.dec_i0_dbecc_d <= instbuff.io.dec_i0_dbecc_d @[dec.scala 169:48] + decode.io.dec_i0_brp.bits.ret <= instbuff.io.dec_i0_brp.bits.ret @[dec.scala 170:48] + decode.io.dec_i0_brp.bits.way <= instbuff.io.dec_i0_brp.bits.way @[dec.scala 170:48] + decode.io.dec_i0_brp.bits.prett <= instbuff.io.dec_i0_brp.bits.prett @[dec.scala 170:48] + decode.io.dec_i0_brp.bits.bank <= instbuff.io.dec_i0_brp.bits.bank @[dec.scala 170:48] + decode.io.dec_i0_brp.bits.br_start_error <= instbuff.io.dec_i0_brp.bits.br_start_error @[dec.scala 170:48] + decode.io.dec_i0_brp.bits.br_error <= instbuff.io.dec_i0_brp.bits.br_error @[dec.scala 170:48] + decode.io.dec_i0_brp.bits.hist <= instbuff.io.dec_i0_brp.bits.hist @[dec.scala 170:48] + decode.io.dec_i0_brp.bits.toffset <= instbuff.io.dec_i0_brp.bits.toffset @[dec.scala 170:48] + decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[dec.scala 170:48] + decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[dec.scala 171:48] + decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[dec.scala 172:48] + decode.io.dec_i0_bp_btag <= instbuff.io.dec_i0_bp_btag @[dec.scala 173:48] + decode.io.lsu_idle_any <= io.lsu_idle_any @[dec.scala 174:48] + decode.io.lsu_load_stall_any <= io.lsu_load_stall_any @[dec.scala 175:48] + decode.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec.scala 176:48] + decode.io.exu_div_wren <= io.exu_div_wren @[dec.scala 177:48] + decode.io.dec_tlu_i0_kill_writeb_wb <= tlu.io.dec_tlu_i0_kill_writeb_wb @[dec.scala 178:48] + decode.io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[dec.scala 179:48] + decode.io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[dec.scala 180:48] + decode.io.dec_tlu_flush_lower_r <= tlu.io.tlu_exu.dec_tlu_flush_lower_r @[dec.scala 181:48] + decode.io.dec_tlu_flush_pause_r <= tlu.io.dec_tlu_flush_pause_r @[dec.scala 182:48] + decode.io.dec_tlu_presync_d <= tlu.io.dec_tlu_presync_d @[dec.scala 183:48] + decode.io.dec_tlu_postsync_d <= tlu.io.dec_tlu_postsync_d @[dec.scala 184:48] + decode.io.dec_i0_pc4_d <= instbuff.io.dec_i0_pc4_d @[dec.scala 185:48] + decode.io.dec_csr_rddata_d <= tlu.io.dec_csr_rddata_d @[dec.scala 186:48] + decode.io.dec_csr_legal_d <= tlu.io.dec_csr_legal_d @[dec.scala 187:48] + decode.io.lsu_result_m <= io.lsu_result_m @[dec.scala 188:48] + decode.io.lsu_result_corr_r <= io.lsu_result_corr_r @[dec.scala 189:48] + decode.io.exu_flush_final <= io.exu_flush_final @[dec.scala 190:48] + decode.io.dec_i0_instr_d <= instbuff.io.dec_i0_instr_d @[dec.scala 191:48] + decode.io.dec_ib0_valid_d <= instbuff.io.dec_ib0_valid_d @[dec.scala 192:48] + decode.io.free_l2clk <= io.free_l2clk @[dec.scala 193:48] + decode.io.active_clk <= io.active_clk @[dec.scala 194:48] + decode.io.clk_override <= tlu.io.dec_tlu_dec_clk_override @[dec.scala 195:48] + decode.io.scan_mode <= io.scan_mode @[dec.scala 196:48] + dec_i0_inst_wb1 <= decode.io.dec_i0_inst_wb @[dec.scala 197:48] + dec_i0_pc_wb1 <= decode.io.dec_i0_pc_wb @[dec.scala 198:48] + io.lsu_p.bits.store_data_bypass_m <= decode.io.lsu_p.bits.store_data_bypass_m @[dec.scala 199:48] + io.lsu_p.bits.load_ldst_bypass_d <= decode.io.lsu_p.bits.load_ldst_bypass_d @[dec.scala 199:48] + io.lsu_p.bits.store_data_bypass_d <= decode.io.lsu_p.bits.store_data_bypass_d @[dec.scala 199:48] + io.lsu_p.bits.dma <= decode.io.lsu_p.bits.dma @[dec.scala 199:48] + io.lsu_p.bits.unsign <= decode.io.lsu_p.bits.unsign @[dec.scala 199:48] + io.lsu_p.bits.store <= decode.io.lsu_p.bits.store @[dec.scala 199:48] + io.lsu_p.bits.load <= decode.io.lsu_p.bits.load @[dec.scala 199:48] + io.lsu_p.bits.dword <= decode.io.lsu_p.bits.dword @[dec.scala 199:48] + io.lsu_p.bits.word <= decode.io.lsu_p.bits.word @[dec.scala 199:48] + io.lsu_p.bits.half <= decode.io.lsu_p.bits.half @[dec.scala 199:48] + io.lsu_p.bits.by <= decode.io.lsu_p.bits.by @[dec.scala 199:48] + io.lsu_p.bits.stack <= decode.io.lsu_p.bits.stack @[dec.scala 199:48] + io.lsu_p.bits.fast_int <= decode.io.lsu_p.bits.fast_int @[dec.scala 199:48] + io.lsu_p.valid <= decode.io.lsu_p.valid @[dec.scala 199:48] + io.dec_lsu_valid_raw_d <= decode.io.dec_lsu_valid_raw_d @[dec.scala 200:48] + io.dec_lsu_offset_d <= decode.io.dec_lsu_offset_d @[dec.scala 201:48] + io.dec_pause_state_cg <= decode.io.dec_pause_state_cg @[dec.scala 202:48] + io.dec_exu.decode_exu.dec_qual_lsu_d <= decode.io.decode_exu.dec_qual_lsu_d @[dec.scala 203:48] + io.dec_fa_error_index <= decode.io.dec_fa_error_index @[dec.scala 204:48] + gpr.io.raddr0 <= decode.io.dec_i0_rs1_d @[dec.scala 206:23] + gpr.io.raddr1 <= decode.io.dec_i0_rs2_d @[dec.scala 207:23] + gpr.io.wen0 <= decode.io.dec_i0_wen_r @[dec.scala 208:23] + gpr.io.waddr0 <= decode.io.dec_i0_waddr_r @[dec.scala 209:23] + gpr.io.wd0 <= decode.io.dec_i0_wdata_r @[dec.scala 210:23] + gpr.io.wen1 <= decode.io.dec_nonblock_load_wen @[dec.scala 211:23] + gpr.io.waddr1 <= decode.io.dec_nonblock_load_waddr @[dec.scala 212:23] + gpr.io.wd1 <= io.lsu_nonblock_load_data @[dec.scala 213:23] + gpr.io.wen2 <= io.exu_div_wren @[dec.scala 214:23] + gpr.io.waddr2 <= decode.io.div_waddr_wb @[dec.scala 215:23] + gpr.io.wd2 <= io.exu_div_result @[dec.scala 216:23] + gpr.io.scan_mode <= io.scan_mode @[dec.scala 217:23] + io.dec_exu.gpr_exu.gpr_i0_rs2_d <= gpr.io.gpr_exu.gpr_i0_rs2_d @[dec.scala 218:22] + io.dec_exu.gpr_exu.gpr_i0_rs1_d <= gpr.io.gpr_exu.gpr_i0_rs1_d @[dec.scala 218:22] + tlu.io.tlu_mem.ifu_miss_state_idle <= io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[dec.scala 220:18] + tlu.io.tlu_mem.ifu_ic_debug_rd_data_valid <= io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[dec.scala 220:18] + tlu.io.tlu_mem.ifu_ic_debug_rd_data <= io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[dec.scala 220:18] + tlu.io.tlu_mem.ifu_iccm_rd_ecc_single_err <= io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[dec.scala 220:18] + tlu.io.tlu_mem.ifu_ic_error_start <= io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[dec.scala 220:18] + tlu.io.tlu_mem.ifu_pmu_bus_trxn <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[dec.scala 220:18] + tlu.io.tlu_mem.ifu_pmu_bus_busy <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[dec.scala 220:18] + tlu.io.tlu_mem.ifu_pmu_bus_error <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[dec.scala 220:18] + tlu.io.tlu_mem.ifu_pmu_ic_hit <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[dec.scala 220:18] + tlu.io.tlu_mem.ifu_pmu_ic_miss <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[dec.scala 220:18] + io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= tlu.io.tlu_mem.dec_tlu_core_ecc_disable @[dec.scala 220:18] + io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid @[dec.scala 220:18] + io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid @[dec.scala 220:18] + io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics @[dec.scala 220:18] + io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata @[dec.scala 220:18] + io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= tlu.io.tlu_mem.dec_tlu_fence_i_wb @[dec.scala 220:18] + io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= tlu.io.tlu_mem.dec_tlu_force_halt @[dec.scala 220:18] + io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= tlu.io.tlu_mem.dec_tlu_i0_commit_cmt @[dec.scala 220:18] + io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= tlu.io.tlu_mem.dec_tlu_flush_err_wb @[dec.scala 220:18] + tlu.io.tlu_ifc.ifu_pmu_fetch_stall <= io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[dec.scala 221:18] + io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= tlu.io.tlu_ifc.dec_tlu_mrac_ff @[dec.scala 221:18] + io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= tlu.io.tlu_ifc.dec_tlu_flush_noredir_wb @[dec.scala 221:18] + io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= tlu.io.tlu_bp.dec_tlu_bpred_disable @[dec.scala 222:18] + io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb @[dec.scala 222:18] + io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle @[dec.scala 222:18] + io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.way @[dec.scala 222:18] + io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[dec.scala 222:18] + io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error @[dec.scala 222:18] + io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist @[dec.scala 222:18] + io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.valid @[dec.scala 222:18] + tlu.io.tlu_exu.exu_npc_r <= io.dec_exu.tlu_exu.exu_npc_r @[dec.scala 223:18] + tlu.io.tlu_exu.exu_pmu_i0_pc4 <= io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[dec.scala 223:18] + tlu.io.tlu_exu.exu_pmu_i0_br_ataken <= io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[dec.scala 223:18] + tlu.io.tlu_exu.exu_pmu_i0_br_misp <= io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[dec.scala 223:18] + tlu.io.tlu_exu.exu_i0_br_middle_r <= io.dec_exu.tlu_exu.exu_i0_br_middle_r @[dec.scala 223:18] + tlu.io.tlu_exu.exu_i0_br_mp_r <= io.dec_exu.tlu_exu.exu_i0_br_mp_r @[dec.scala 223:18] + tlu.io.tlu_exu.exu_i0_br_valid_r <= io.dec_exu.tlu_exu.exu_i0_br_valid_r @[dec.scala 223:18] + tlu.io.tlu_exu.exu_i0_br_index_r <= io.dec_exu.tlu_exu.exu_i0_br_index_r @[dec.scala 223:18] + tlu.io.tlu_exu.exu_i0_br_start_error_r <= io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[dec.scala 223:18] + tlu.io.tlu_exu.exu_i0_br_error_r <= io.dec_exu.tlu_exu.exu_i0_br_error_r @[dec.scala 223:18] + tlu.io.tlu_exu.exu_i0_br_hist_r <= io.dec_exu.tlu_exu.exu_i0_br_hist_r @[dec.scala 223:18] + io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= tlu.io.tlu_exu.dec_tlu_flush_path_r @[dec.scala 223:18] + io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= tlu.io.tlu_exu.dec_tlu_flush_lower_r @[dec.scala 223:18] + io.dec_exu.tlu_exu.dec_tlu_meihap <= tlu.io.tlu_exu.dec_tlu_meihap @[dec.scala 223:18] + tlu.io.tlu_dma.dma_iccm_stall_any <= io.dec_dma.tlu_dma.dma_iccm_stall_any @[dec.scala 224:18] + tlu.io.tlu_dma.dma_dccm_stall_any <= io.dec_dma.tlu_dma.dma_dccm_stall_any @[dec.scala 224:18] + io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty <= tlu.io.tlu_dma.dec_tlu_dma_qos_prty @[dec.scala 224:18] + tlu.io.tlu_dma.dma_pmu_any_write <= io.dec_dma.tlu_dma.dma_pmu_any_write @[dec.scala 224:18] + tlu.io.tlu_dma.dma_pmu_any_read <= io.dec_dma.tlu_dma.dma_pmu_any_read @[dec.scala 224:18] + tlu.io.tlu_dma.dma_pmu_dccm_write <= io.dec_dma.tlu_dma.dma_pmu_dccm_write @[dec.scala 224:18] + tlu.io.tlu_dma.dma_pmu_dccm_read <= io.dec_dma.tlu_dma.dma_pmu_dccm_read @[dec.scala 224:18] + tlu.io.free_l2clk <= io.free_l2clk @[dec.scala 225:45] + tlu.io.free_clk <= io.free_clk @[dec.scala 226:45] + tlu.io.scan_mode <= io.scan_mode @[dec.scala 227:45] + tlu.io.rst_vec <= io.rst_vec @[dec.scala 228:45] + tlu.io.nmi_int <= io.nmi_int @[dec.scala 229:45] + tlu.io.nmi_vec <= io.nmi_vec @[dec.scala 230:45] + tlu.io.i_cpu_halt_req <= io.i_cpu_halt_req @[dec.scala 231:45] + tlu.io.i_cpu_run_req <= io.i_cpu_run_req @[dec.scala 232:45] + tlu.io.lsu_fastint_stall_any <= io.lsu_fastint_stall_any @[dec.scala 233:45] + tlu.io.ifu_pmu_instr_aligned <= io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[dec.scala 234:45] + tlu.io.dec_pmu_instr_decoded <= decode.io.dec_pmu_instr_decoded @[dec.scala 235:45] + tlu.io.dec_pmu_decode_stall <= decode.io.dec_pmu_decode_stall @[dec.scala 236:45] + tlu.io.dec_pmu_presync_stall <= decode.io.dec_pmu_presync_stall @[dec.scala 237:45] + tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_postsync_stall @[dec.scala 238:45] + tlu.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec.scala 239:45] + tlu.io.tlu_busbuff.lsu_imprecise_error_addr_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[dec.scala 240:26] + tlu.io.tlu_busbuff.lsu_imprecise_error_store_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[dec.scala 240:26] + tlu.io.tlu_busbuff.lsu_imprecise_error_load_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[dec.scala 240:26] + io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= tlu.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[dec.scala 240:26] + io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= tlu.io.tlu_busbuff.dec_tlu_wb_coalescing_disable @[dec.scala 240:26] + io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= tlu.io.tlu_busbuff.dec_tlu_external_ldfwd_disable @[dec.scala 240:26] + tlu.io.tlu_busbuff.lsu_pmu_bus_busy <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[dec.scala 240:26] + tlu.io.tlu_busbuff.lsu_pmu_bus_error <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[dec.scala 240:26] + tlu.io.tlu_busbuff.lsu_pmu_bus_misaligned <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[dec.scala 240:26] + tlu.io.tlu_busbuff.lsu_pmu_bus_trxn <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[dec.scala 240:26] + tlu.io.lsu_tlu.lsu_pmu_store_external_m <= io.lsu_tlu.lsu_pmu_store_external_m @[dec.scala 241:14] + tlu.io.lsu_tlu.lsu_pmu_load_external_m <= io.lsu_tlu.lsu_pmu_load_external_m @[dec.scala 241:14] + tlu.io.dec_pic.mexintpend <= io.dec_pic.mexintpend @[dec.scala 242:14] + io.dec_pic.dec_tlu_meipt <= tlu.io.dec_pic.dec_tlu_meipt @[dec.scala 242:14] + io.dec_pic.dec_tlu_meicurpl <= tlu.io.dec_pic.dec_tlu_meicurpl @[dec.scala 242:14] + tlu.io.dec_pic.mhwakeup <= io.dec_pic.mhwakeup @[dec.scala 242:14] + tlu.io.dec_pic.pic_pl <= io.dec_pic.pic_pl @[dec.scala 242:14] + tlu.io.dec_pic.pic_claimid <= io.dec_pic.pic_claimid @[dec.scala 242:14] + tlu.io.lsu_fir_addr <= io.lsu_fir_addr @[dec.scala 243:45] + tlu.io.lsu_fir_error <= io.lsu_fir_error @[dec.scala 244:45] + tlu.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[dec.scala 245:45] + tlu.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec.scala 246:45] + tlu.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec.scala 246:45] + tlu.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec.scala 246:45] + tlu.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec.scala 246:45] + tlu.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec.scala 246:45] + tlu.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec.scala 246:45] + tlu.io.lsu_single_ecc_error_incr <= io.lsu_single_ecc_error_incr @[dec.scala 247:45] + tlu.io.dec_pause_state <= decode.io.dec_pause_state @[dec.scala 248:45] + tlu.io.dec_csr_wen_unq_d <= decode.io.dec_csr_wen_unq_d @[dec.scala 249:45] + tlu.io.dec_csr_any_unq_d <= decode.io.dec_csr_any_unq_d @[dec.scala 250:45] + tlu.io.dec_csr_rdaddr_d <= decode.io.dec_csr_rdaddr_d @[dec.scala 251:45] + tlu.io.dec_csr_wen_r <= decode.io.dec_csr_wen_r @[dec.scala 252:45] + tlu.io.dec_csr_wraddr_r <= decode.io.dec_csr_wraddr_r @[dec.scala 253:45] + tlu.io.dec_csr_wrdata_r <= decode.io.dec_csr_wrdata_r @[dec.scala 254:45] + tlu.io.dec_csr_stall_int_ff <= decode.io.dec_csr_stall_int_ff @[dec.scala 255:45] + tlu.io.dec_tlu_i0_valid_r <= decode.io.dec_tlu_i0_valid_r @[dec.scala 256:45] + tlu.io.dec_tlu_i0_pc_r <= decode.io.dec_tlu_i0_pc_r @[dec.scala 257:45] + tlu.io.dec_tlu_packet_r.pmu_lsu_misaligned <= decode.io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec.scala 258:45] + tlu.io.dec_tlu_packet_r.pmu_divide <= decode.io.dec_tlu_packet_r.pmu_divide @[dec.scala 258:45] + tlu.io.dec_tlu_packet_r.pmu_i0_br_unpred <= decode.io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec.scala 258:45] + tlu.io.dec_tlu_packet_r.pmu_i0_itype <= decode.io.dec_tlu_packet_r.pmu_i0_itype @[dec.scala 258:45] + tlu.io.dec_tlu_packet_r.i0trigger <= decode.io.dec_tlu_packet_r.i0trigger @[dec.scala 258:45] + tlu.io.dec_tlu_packet_r.fence_i <= decode.io.dec_tlu_packet_r.fence_i @[dec.scala 258:45] + tlu.io.dec_tlu_packet_r.icaf_type <= decode.io.dec_tlu_packet_r.icaf_type @[dec.scala 258:45] + tlu.io.dec_tlu_packet_r.icaf_second <= decode.io.dec_tlu_packet_r.icaf_second @[dec.scala 258:45] + tlu.io.dec_tlu_packet_r.icaf <= decode.io.dec_tlu_packet_r.icaf @[dec.scala 258:45] + tlu.io.dec_tlu_packet_r.legal <= decode.io.dec_tlu_packet_r.legal @[dec.scala 258:45] + tlu.io.dec_illegal_inst <= decode.io.dec_illegal_inst @[dec.scala 259:45] + tlu.io.dec_i0_decode_d <= decode.io.dec_aln.dec_i0_decode_d @[dec.scala 260:45] + tlu.io.exu_i0_br_way_r <= io.exu_i0_br_way_r @[dec.scala 261:45] + tlu.io.dbg_halt_req <= io.dbg_halt_req @[dec.scala 262:45] + tlu.io.dbg_resume_req <= io.dbg_resume_req @[dec.scala 263:45] + tlu.io.lsu_idle_any <= io.lsu_idle_any @[dec.scala 264:45] + tlu.io.dec_div_active <= decode.io.dec_div_active @[dec.scala 265:45] + tlu.io.timer_int <= io.timer_int @[dec.scala 266:45] + tlu.io.soft_int <= io.soft_int @[dec.scala 267:45] + tlu.io.core_id <= io.core_id @[dec.scala 268:45] + tlu.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[dec.scala 269:45] + tlu.io.mpc_debug_run_req <= io.mpc_debug_run_req @[dec.scala 270:45] + tlu.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec.scala 271:45] + io.dec_dbg_cmd_done <= tlu.io.dec_dbg_cmd_done @[dec.scala 272:28] + io.dec_dbg_cmd_fail <= tlu.io.dec_dbg_cmd_fail @[dec.scala 273:28] + io.dec_tlu_dbg_halted <= tlu.io.dec_tlu_dbg_halted @[dec.scala 274:28] + io.dec_tlu_debug_mode <= tlu.io.dec_tlu_debug_mode @[dec.scala 275:28] + io.dec_tlu_resume_ack <= tlu.io.dec_tlu_resume_ack @[dec.scala 276:28] + io.dec_tlu_mpc_halted_only <= tlu.io.dec_tlu_mpc_halted_only @[dec.scala 277:51] + io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[dec.scala 278:29] + io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[dec.scala 278:29] + io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[dec.scala 278:29] + io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[dec.scala 278:29] + io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[dec.scala 278:29] + io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[dec.scala 278:29] + io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[dec.scala 278:29] + io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[dec.scala 278:29] + io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[dec.scala 278:29] + io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[dec.scala 278:29] + io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[dec.scala 278:29] + io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[dec.scala 278:29] + io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[dec.scala 278:29] + io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[dec.scala 278:29] + io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[dec.scala 278:29] + io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[dec.scala 278:29] + io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[dec.scala 278:29] + io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[dec.scala 278:29] + io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[dec.scala 278:29] + io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[dec.scala 278:29] + io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[dec.scala 278:29] + io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[dec.scala 278:29] + io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[dec.scala 278:29] + io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[dec.scala 278:29] + io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[dec.scala 278:29] + io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[dec.scala 278:29] + io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[dec.scala 278:29] + io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[dec.scala 278:29] + io.o_cpu_halt_status <= tlu.io.o_cpu_halt_status @[dec.scala 279:29] + io.o_cpu_halt_ack <= tlu.io.o_cpu_halt_ack @[dec.scala 280:29] + io.o_cpu_run_ack <= tlu.io.o_cpu_run_ack @[dec.scala 281:29] + io.o_debug_mode_status <= tlu.io.o_debug_mode_status @[dec.scala 282:29] + io.mpc_debug_halt_ack <= tlu.io.mpc_debug_halt_ack @[dec.scala 283:29] + io.mpc_debug_run_ack <= tlu.io.mpc_debug_run_ack @[dec.scala 284:29] + io.debug_brkpt_status <= tlu.io.debug_brkpt_status @[dec.scala 285:29] + io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[dec.scala 286:34] + io.dec_tlu_perfcnt0 <= tlu.io.dec_tlu_perfcnt0 @[dec.scala 287:29] + io.dec_tlu_perfcnt1 <= tlu.io.dec_tlu_perfcnt1 @[dec.scala 288:29] + io.dec_tlu_perfcnt2 <= tlu.io.dec_tlu_perfcnt2 @[dec.scala 289:29] + io.dec_tlu_perfcnt3 <= tlu.io.dec_tlu_perfcnt3 @[dec.scala 290:29] + dec_tlu_i0_exc_valid_wb1 <= tlu.io.dec_tlu_i0_exc_valid_wb1 @[dec.scala 291:32] + dec_tlu_i0_valid_wb1 <= tlu.io.dec_tlu_i0_valid_wb1 @[dec.scala 292:32] + dec_tlu_int_valid_wb1 <= tlu.io.dec_tlu_int_valid_wb1 @[dec.scala 293:32] + dec_tlu_exc_cause_wb1 <= tlu.io.dec_tlu_exc_cause_wb1 @[dec.scala 294:32] + dec_tlu_mtval_wb1 <= tlu.io.dec_tlu_mtval_wb1 @[dec.scala 295:32] + io.dec_tlu_misc_clk_override <= tlu.io.dec_tlu_misc_clk_override @[dec.scala 296:35] + io.dec_tlu_ifu_clk_override <= tlu.io.dec_tlu_ifu_clk_override @[dec.scala 297:36] + io.dec_tlu_lsu_clk_override <= tlu.io.dec_tlu_lsu_clk_override @[dec.scala 298:36] + io.dec_tlu_bus_clk_override <= tlu.io.dec_tlu_bus_clk_override @[dec.scala 299:36] + io.dec_tlu_pic_clk_override <= tlu.io.dec_tlu_pic_clk_override @[dec.scala 300:36] + io.dec_tlu_dccm_clk_override <= tlu.io.dec_tlu_dccm_clk_override @[dec.scala 301:36] + io.dec_tlu_icm_clk_override <= tlu.io.dec_tlu_icm_clk_override @[dec.scala 302:36] + io.dec_tlu_picio_clk_override <= tlu.io.dec_tlu_icm_clk_override @[dec.scala 303:36] + io.dec_tlu_core_empty <= tlu.io.dec_tlu_core_empty @[dec.scala 304:36] + io.dec_csr_rddata_d <= tlu.io.dec_csr_rddata_d @[dec.scala 305:36] + io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[dec.scala 306:36] + io.trace_rv_trace_pkt.rv_i_insn_ip <= decode.io.dec_i0_inst_wb @[dec.scala 310:38] + node _T = cat(decode.io.dec_i0_pc_wb, UInt<1>("h00")) @[Cat.scala 29:58] + io.trace_rv_trace_pkt.rv_i_address_ip <= _T @[dec.scala 311:41] + node _T_1 = or(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_valid_wb1) @[dec.scala 312:71] + node _T_2 = or(_T_1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[dec.scala 312:101] + io.trace_rv_trace_pkt.rv_i_valid_ip <= _T_2 @[dec.scala 312:39] + node _T_3 = or(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[dec.scala 313:75] + io.trace_rv_trace_pkt.rv_i_exception_ip <= _T_3 @[dec.scala 313:43] + node _T_4 = bits(tlu.io.dec_tlu_exc_cause_wb1, 4, 0) @[dec.scala 314:71] + io.trace_rv_trace_pkt.rv_i_ecause_ip <= _T_4 @[dec.scala 314:40] + io.trace_rv_trace_pkt.rv_i_interrupt_ip <= tlu.io.dec_tlu_int_valid_wb1 @[dec.scala 315:43] + io.trace_rv_trace_pkt.rv_i_tval_ip <= tlu.io.dec_tlu_mtval_wb1 @[dec.scala 316:38] + io.dec_dbg_rddata <= decode.io.dec_i0_wdata_r @[dec.scala 320:21] + diff --git a/dec.v b/dec.v new file mode 100644 index 00000000..2cd946dc --- /dev/null +++ b/dec.v @@ -0,0 +1,16582 @@ +module dec_ib_ctl( + input io_ifu_ib_ifu_i0_icaf, + input [1:0] io_ifu_ib_ifu_i0_icaf_type, + input io_ifu_ib_ifu_i0_icaf_second, + input io_ifu_ib_ifu_i0_dbecc, + input [7:0] io_ifu_ib_ifu_i0_bp_index, + input [7:0] io_ifu_ib_ifu_i0_bp_fghr, + input [4:0] io_ifu_ib_ifu_i0_bp_btag, + input io_ifu_ib_ifu_i0_valid, + input [31:0] io_ifu_ib_ifu_i0_instr, + input [30:0] io_ifu_ib_ifu_i0_pc, + input io_ifu_ib_ifu_i0_pc4, + input io_ifu_ib_i0_brp_valid, + input [11:0] io_ifu_ib_i0_brp_bits_toffset, + input [1:0] io_ifu_ib_i0_brp_bits_hist, + input io_ifu_ib_i0_brp_bits_br_error, + input io_ifu_ib_i0_brp_bits_br_start_error, + input [30:0] io_ifu_ib_i0_brp_bits_prett, + input io_ifu_ib_i0_brp_bits_way, + input io_ifu_ib_i0_brp_bits_ret, + output [30:0] io_ib_exu_dec_i0_pc_d, + output io_ib_exu_dec_debug_wdata_rs1_d, + input io_dbg_ib_dbg_cmd_valid, + input io_dbg_ib_dbg_cmd_write, + input [1:0] io_dbg_ib_dbg_cmd_type, + input [31:0] io_dbg_ib_dbg_cmd_addr, + output io_dec_ib0_valid_d, + output [1:0] io_dec_i0_icaf_type_d, + output [31:0] io_dec_i0_instr_d, + output io_dec_i0_pc4_d, + output io_dec_i0_brp_valid, + output [11:0] io_dec_i0_brp_bits_toffset, + output [1:0] io_dec_i0_brp_bits_hist, + output io_dec_i0_brp_bits_br_error, + output io_dec_i0_brp_bits_br_start_error, + output [30:0] io_dec_i0_brp_bits_prett, + output io_dec_i0_brp_bits_way, + output io_dec_i0_brp_bits_ret, + output [7:0] io_dec_i0_bp_index, + output [7:0] io_dec_i0_bp_fghr, + output [4:0] io_dec_i0_bp_btag, + output io_dec_i0_icaf_d, + output io_dec_i0_icaf_second_d, + output io_dec_i0_dbecc_d, + output io_dec_debug_fence_d +); + wire _T = io_dbg_ib_dbg_cmd_type != 2'h2; // @[dec_ib_ctl.scala 58:74] + wire debug_valid = io_dbg_ib_dbg_cmd_valid & _T; // @[dec_ib_ctl.scala 58:48] + wire _T_1 = ~io_dbg_ib_dbg_cmd_write; // @[dec_ib_ctl.scala 59:38] + wire debug_read = debug_valid & _T_1; // @[dec_ib_ctl.scala 59:36] + wire debug_write = debug_valid & io_dbg_ib_dbg_cmd_write; // @[dec_ib_ctl.scala 60:36] + wire _T_2 = io_dbg_ib_dbg_cmd_type == 2'h0; // @[dec_ib_ctl.scala 62:62] + wire debug_read_gpr = debug_read & _T_2; // @[dec_ib_ctl.scala 62:37] + wire debug_write_gpr = debug_write & _T_2; // @[dec_ib_ctl.scala 63:37] + wire _T_4 = io_dbg_ib_dbg_cmd_type == 2'h1; // @[dec_ib_ctl.scala 64:62] + wire debug_read_csr = debug_read & _T_4; // @[dec_ib_ctl.scala 64:37] + wire debug_write_csr = debug_write & _T_4; // @[dec_ib_ctl.scala 65:37] + wire [4:0] dreg = io_dbg_ib_dbg_cmd_addr[4:0]; // @[dec_ib_ctl.scala 67:47] + wire [11:0] dcsr = io_dbg_ib_dbg_cmd_addr[11:0]; // @[dec_ib_ctl.scala 68:47] + wire [31:0] _T_9 = {12'h0,dreg,15'h6033}; // @[Cat.scala 29:58] + wire [31:0] _T_12 = {20'h6,dreg,7'h33}; // @[Cat.scala 29:58] + wire [31:0] _T_14 = {dcsr,20'h2073}; // @[Cat.scala 29:58] + wire [31:0] _T_16 = {dcsr,20'h1073}; // @[Cat.scala 29:58] + wire [31:0] _T_17 = debug_read_gpr ? _T_9 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_18 = debug_write_gpr ? _T_12 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_19 = debug_read_csr ? _T_14 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_20 = debug_write_csr ? _T_16 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72] + wire [31:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72] + wire [31:0] ib0_debug_in = _T_22 | _T_20; // @[Mux.scala 27:72] + wire _T_25 = dcsr == 12'h7c4; // @[dec_ib_ctl.scala 81:51] + assign io_ib_exu_dec_i0_pc_d = io_ifu_ib_ifu_i0_pc; // @[dec_ib_ctl.scala 37:31] + assign io_ib_exu_dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; // @[dec_ib_ctl.scala 78:35] + assign io_dec_ib0_valid_d = io_ifu_ib_ifu_i0_valid | debug_valid; // @[dec_ib_ctl.scala 83:22] + assign io_dec_i0_icaf_type_d = io_ifu_ib_ifu_i0_icaf_type; // @[dec_ib_ctl.scala 39:31] + assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_ib_ifu_i0_instr; // @[dec_ib_ctl.scala 84:22] + assign io_dec_i0_pc4_d = io_ifu_ib_ifu_i0_pc4; // @[dec_ib_ctl.scala 38:31] + assign io_dec_i0_brp_valid = io_ifu_ib_i0_brp_valid; // @[dec_ib_ctl.scala 40:31] + assign io_dec_i0_brp_bits_toffset = io_ifu_ib_i0_brp_bits_toffset; // @[dec_ib_ctl.scala 40:31] + assign io_dec_i0_brp_bits_hist = io_ifu_ib_i0_brp_bits_hist; // @[dec_ib_ctl.scala 40:31] + assign io_dec_i0_brp_bits_br_error = io_ifu_ib_i0_brp_bits_br_error; // @[dec_ib_ctl.scala 40:31] + assign io_dec_i0_brp_bits_br_start_error = io_ifu_ib_i0_brp_bits_br_start_error; // @[dec_ib_ctl.scala 40:31] + assign io_dec_i0_brp_bits_prett = io_ifu_ib_i0_brp_bits_prett; // @[dec_ib_ctl.scala 40:31] + assign io_dec_i0_brp_bits_way = io_ifu_ib_i0_brp_bits_way; // @[dec_ib_ctl.scala 40:31] + assign io_dec_i0_brp_bits_ret = io_ifu_ib_i0_brp_bits_ret; // @[dec_ib_ctl.scala 40:31] + assign io_dec_i0_bp_index = io_ifu_ib_ifu_i0_bp_index; // @[dec_ib_ctl.scala 41:31] + assign io_dec_i0_bp_fghr = io_ifu_ib_ifu_i0_bp_fghr; // @[dec_ib_ctl.scala 42:31] + assign io_dec_i0_bp_btag = io_ifu_ib_ifu_i0_bp_btag; // @[dec_ib_ctl.scala 43:31] + assign io_dec_i0_icaf_d = io_ifu_ib_ifu_i0_icaf; // @[dec_ib_ctl.scala 36:31] + assign io_dec_i0_icaf_second_d = io_ifu_ib_ifu_i0_icaf_second; // @[dec_ib_ctl.scala 34:35] + assign io_dec_i0_dbecc_d = io_ifu_ib_ifu_i0_dbecc; // @[dec_ib_ctl.scala 35:31] + assign io_dec_debug_fence_d = debug_write_csr & _T_25; // @[dec_ib_ctl.scala 81:24] +endmodule +module dec_dec_ctl( + input [31:0] io_ins, + output io_out_clz, + output io_out_ctz, + output io_out_pcnt, + output io_out_sext_b, + output io_out_sext_h, + output io_out_slo, + output io_out_sro, + output io_out_min, + output io_out_max, + output io_out_pack, + output io_out_packu, + output io_out_packh, + output io_out_rol, + output io_out_ror, + output io_out_grev, + output io_out_gorc, + output io_out_zbb, + output io_out_sbset, + output io_out_sbclr, + output io_out_sbinv, + output io_out_sbext, + output io_out_zbs, + output io_out_bext, + output io_out_bdep, + output io_out_zbe, + output io_out_clmul, + output io_out_clmulh, + output io_out_clmulr, + output io_out_zbc, + output io_out_shfl, + output io_out_unshfl, + output io_out_zbp, + output io_out_crc32_b, + output io_out_crc32_h, + output io_out_crc32_w, + output io_out_crc32c_b, + output io_out_crc32c_h, + output io_out_crc32c_w, + output io_out_zbr, + output io_out_bfp, + output io_out_zbf, + output io_out_sh1add, + output io_out_sh2add, + output io_out_sh3add, + output io_out_zba, + output io_out_alu, + output io_out_rs1, + output io_out_rs2, + output io_out_imm12, + output io_out_rd, + output io_out_shimm5, + output io_out_imm20, + output io_out_pc, + output io_out_load, + output io_out_store, + output io_out_lsu, + output io_out_add, + output io_out_sub, + output io_out_land, + output io_out_lor, + output io_out_lxor, + output io_out_sll, + output io_out_sra, + output io_out_srl, + output io_out_slt, + output io_out_unsign, + output io_out_condbr, + output io_out_beq, + output io_out_bne, + output io_out_bge, + output io_out_blt, + output io_out_jal, + output io_out_by, + output io_out_half, + output io_out_word, + output io_out_csr_read, + output io_out_csr_clr, + output io_out_csr_set, + output io_out_csr_write, + output io_out_csr_imm, + output io_out_presync, + output io_out_postsync, + output io_out_ebreak, + output io_out_ecall, + output io_out_mret, + output io_out_mul, + output io_out_rs1_sign, + output io_out_rs2_sign, + output io_out_low, + output io_out_div, + output io_out_rem, + output io_out_fence, + output io_out_fence_i, + output io_out_pm_alu, + output io_out_legal +); + wire _T_4 = ~io_ins[22]; // @[dec_dec_ctl.scala 15:46] + wire _T_6 = ~io_ins[21]; // @[dec_dec_ctl.scala 15:46] + wire _T_8 = ~io_ins[20]; // @[dec_dec_ctl.scala 15:46] + wire _T_11 = ~io_ins[5]; // @[dec_dec_ctl.scala 15:46] + wire _T_13 = io_ins[30] & io_ins[24]; // @[dec_dec_ctl.scala 17:17] + wire _T_14 = _T_13 & io_ins[23]; // @[dec_dec_ctl.scala 17:17] + wire _T_15 = _T_14 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_16 = _T_15 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_17 = _T_16 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_18 = _T_17 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_19 = _T_18 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_20 = _T_19 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_23 = ~io_ins[27]; // @[dec_dec_ctl.scala 15:46] + wire _T_25 = ~io_ins[24]; // @[dec_dec_ctl.scala 15:46] + wire _T_27 = io_ins[29] & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_28 = _T_27 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_29 = _T_28 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_30 = _T_20 | _T_29; // @[dec_dec_ctl.scala 20:62] + wire _T_32 = ~io_ins[25]; // @[dec_dec_ctl.scala 15:46] + wire _T_34 = ~io_ins[13]; // @[dec_dec_ctl.scala 15:46] + wire _T_36 = ~io_ins[12]; // @[dec_dec_ctl.scala 15:46] + wire _T_38 = _T_32 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_39 = _T_38 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_40 = _T_39 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_41 = _T_30 | _T_40; // @[dec_dec_ctl.scala 20:92] + wire _T_43 = ~io_ins[30]; // @[dec_dec_ctl.scala 15:46] + wire _T_48 = _T_43 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_49 = _T_48 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_50 = _T_49 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_51 = _T_41 | _T_50; // @[dec_dec_ctl.scala 21:34] + wire _T_56 = io_ins[27] & io_ins[25]; // @[dec_dec_ctl.scala 17:17] + wire _T_57 = _T_56 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_58 = _T_57 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_59 = _T_51 | _T_58; // @[dec_dec_ctl.scala 21:66] + wire _T_63 = ~io_ins[14]; // @[dec_dec_ctl.scala 15:46] + wire _T_65 = io_ins[29] & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_66 = _T_65 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_67 = _T_66 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_68 = _T_59 | _T_67; // @[dec_dec_ctl.scala 21:94] + wire _T_74 = io_ins[29] & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_75 = _T_74 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_76 = _T_75 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_77 = _T_68 | _T_76; // @[dec_dec_ctl.scala 22:32] + wire _T_84 = _T_23 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_85 = _T_84 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_86 = _T_85 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_87 = _T_77 | _T_86; // @[dec_dec_ctl.scala 22:60] + wire _T_90 = ~io_ins[29]; // @[dec_dec_ctl.scala 15:46] + wire _T_94 = io_ins[30] & _T_90; // @[dec_dec_ctl.scala 17:17] + wire _T_95 = _T_94 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_96 = _T_95 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_97 = _T_87 | _T_96; // @[dec_dec_ctl.scala 22:90] + wire _T_105 = _T_43 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_106 = _T_105 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_107 = _T_106 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_108 = _T_97 | _T_107; // @[dec_dec_ctl.scala 23:33] + wire _T_113 = io_ins[13] & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_114 = _T_113 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_115 = _T_108 | _T_114; // @[dec_dec_ctl.scala 23:64] + wire _T_121 = _T_36 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_122 = _T_121 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_123 = _T_115 | _T_122; // @[dec_dec_ctl.scala 23:89] + wire _T_125 = _T_123 | io_ins[2]; // @[dec_dec_ctl.scala 24:29] + wire _T_127 = _T_125 | io_ins[6]; // @[dec_dec_ctl.scala 24:48] + wire _T_139 = _T_14 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_140 = _T_139 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_141 = _T_140 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_142 = _T_141 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_143 = _T_142 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_144 = _T_127 | _T_143; // @[dec_dec_ctl.scala 24:67] + wire _T_151 = ~io_ins[23]; // @[dec_dec_ctl.scala 15:46] + wire _T_158 = _T_43 & io_ins[29]; // @[dec_dec_ctl.scala 17:17] + wire _T_159 = _T_158 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_160 = _T_159 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_161 = _T_160 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_162 = _T_161 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_163 = _T_162 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_164 = _T_163 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_165 = _T_164 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_166 = _T_144 | _T_165; // @[dec_dec_ctl.scala 24:107] + wire _T_181 = _T_43 & io_ins[24]; // @[dec_dec_ctl.scala 17:17] + wire _T_182 = _T_181 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_183 = _T_182 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_184 = _T_183 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_185 = _T_184 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_186 = _T_185 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_187 = _T_186 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_194 = ~io_ins[2]; // @[dec_dec_ctl.scala 15:46] + wire _T_195 = _T_63 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_196 = _T_195 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_202 = _T_34 & io_ins[11]; // @[dec_dec_ctl.scala 17:17] + wire _T_203 = _T_202 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_204 = _T_196 | _T_203; // @[dec_dec_ctl.scala 27:43] + wire _T_209 = io_ins[19] & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_210 = _T_209 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_211 = _T_204 | _T_210; // @[dec_dec_ctl.scala 27:70] + wire _T_217 = _T_34 & io_ins[10]; // @[dec_dec_ctl.scala 17:17] + wire _T_218 = _T_217 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_219 = _T_211 | _T_218; // @[dec_dec_ctl.scala 27:96] + wire _T_224 = io_ins[18] & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_225 = _T_224 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_226 = _T_219 | _T_225; // @[dec_dec_ctl.scala 28:30] + wire _T_232 = _T_34 & io_ins[9]; // @[dec_dec_ctl.scala 17:17] + wire _T_233 = _T_232 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_234 = _T_226 | _T_233; // @[dec_dec_ctl.scala 28:57] + wire _T_239 = io_ins[17] & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_240 = _T_239 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_241 = _T_234 | _T_240; // @[dec_dec_ctl.scala 28:83] + wire _T_247 = _T_34 & io_ins[8]; // @[dec_dec_ctl.scala 17:17] + wire _T_248 = _T_247 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_249 = _T_241 | _T_248; // @[dec_dec_ctl.scala 28:109] + wire _T_254 = io_ins[16] & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_255 = _T_254 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_256 = _T_249 | _T_255; // @[dec_dec_ctl.scala 29:29] + wire _T_262 = _T_34 & io_ins[7]; // @[dec_dec_ctl.scala 17:17] + wire _T_263 = _T_262 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_264 = _T_256 | _T_263; // @[dec_dec_ctl.scala 29:55] + wire _T_269 = io_ins[15] & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_270 = _T_269 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_271 = _T_264 | _T_270; // @[dec_dec_ctl.scala 29:81] + wire _T_273 = ~io_ins[4]; // @[dec_dec_ctl.scala 15:46] + wire _T_275 = ~io_ins[3]; // @[dec_dec_ctl.scala 15:46] + wire _T_276 = _T_273 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_277 = _T_271 | _T_276; // @[dec_dec_ctl.scala 30:29] + wire _T_279 = ~io_ins[6]; // @[dec_dec_ctl.scala 15:46] + wire _T_282 = _T_279 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_289 = io_ins[5] & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_290 = _T_289 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_296 = _T_279 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_297 = _T_296 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_305 = _T_276 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_314 = _T_114 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_315 = _T_305 | _T_314; // @[dec_dec_ctl.scala 34:42] + wire _T_322 = _T_34 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_323 = _T_322 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_324 = _T_323 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_325 = _T_315 | _T_324; // @[dec_dec_ctl.scala 34:70] + wire _T_335 = _T_122 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_341 = _T_11 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_344 = io_ins[5] & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_345 = _T_341 | _T_344; // @[dec_dec_ctl.scala 36:37] + wire _T_357 = io_ins[27] & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_358 = _T_357 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_359 = _T_358 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_360 = _T_359 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_361 = _T_360 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_372 = _T_43 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_373 = _T_372 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_374 = _T_373 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_375 = _T_374 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_376 = _T_375 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_377 = _T_361 | _T_376; // @[dec_dec_ctl.scala 38:53] + wire _T_387 = io_ins[14] & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_388 = _T_387 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_389 = _T_388 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_390 = _T_389 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_391 = _T_390 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_395 = io_ins[5] & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_398 = io_ins[4] & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_405 = _T_11 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_406 = _T_405 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_417 = _T_11 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_432 = _T_279 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_444 = _T_195 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_445 = _T_444 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_446 = _T_445 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_454 = _T_446 | _T_406; // @[dec_dec_ctl.scala 50:49] + wire _T_471 = _T_48 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_472 = _T_471 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_473 = _T_472 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_474 = _T_473 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_475 = _T_474 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_476 = _T_475 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_489 = io_ins[30] & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_490 = _T_489 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_491 = _T_490 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_492 = _T_491 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_493 = _T_492 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_494 = _T_493 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_507 = _T_90 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_508 = _T_507 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_509 = _T_508 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_510 = _T_509 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_511 = _T_510 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_512 = _T_511 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_513 = _T_494 | _T_512; // @[dec_dec_ctl.scala 52:53] + wire _T_524 = _T_57 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_525 = _T_524 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_526 = _T_525 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_527 = _T_513 | _T_526; // @[dec_dec_ctl.scala 52:93] + wire _T_536 = _T_63 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_537 = _T_536 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_538 = _T_537 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_539 = _T_538 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_540 = _T_527 | _T_539; // @[dec_dec_ctl.scala 53:37] + wire _T_546 = io_ins[6] & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_547 = _T_546 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_562 = _T_85 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_563 = _T_562 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_564 = _T_563 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_565 = _T_564 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_573 = io_ins[14] & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_574 = _T_573 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_575 = _T_574 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_576 = _T_575 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_581 = _T_279 & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_596 = _T_90 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_597 = _T_596 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_598 = _T_597 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_599 = _T_598 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_600 = _T_599 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_601 = _T_600 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_602 = _T_601 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_603 = _T_581 | _T_602; // @[dec_dec_ctl.scala 57:37] + wire _T_607 = io_ins[5] & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_608 = _T_607 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_609 = _T_603 | _T_608; // @[dec_dec_ctl.scala 57:82] + wire _T_619 = _T_609 | _T_324; // @[dec_dec_ctl.scala 57:105] + wire _T_629 = _T_573 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_630 = _T_629 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_631 = _T_630 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_650 = _T_598 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_651 = _T_650 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_652 = _T_651 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_653 = _T_652 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_665 = _T_387 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_666 = _T_665 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_667 = _T_666 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_668 = _T_667 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_688 = _T_597 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_689 = _T_688 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_690 = _T_689 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_691 = _T_690 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_692 = _T_691 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_708 = _T_94 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_709 = _T_708 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_710 = _T_709 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_711 = _T_710 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_712 = _T_711 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_731 = _T_43 & _T_90; // @[dec_dec_ctl.scala 17:17] + wire _T_732 = _T_731 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_733 = _T_732 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_734 = _T_733 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_735 = _T_734 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_736 = _T_735 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_737 = _T_736 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_738 = _T_737 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_781 = _T_23 & io_ins[25]; // @[dec_dec_ctl.scala 17:17] + wire _T_782 = _T_781 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_783 = _T_782 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_784 = _T_783 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_785 = _T_784 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_786 = _T_785 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_796 = _T_536 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_797 = _T_796 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_798 = _T_797 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_799 = _T_786 | _T_798; // @[dec_dec_ctl.scala 70:56] + wire _T_806 = io_ins[13] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_807 = _T_806 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_808 = _T_807 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_809 = _T_799 | _T_808; // @[dec_dec_ctl.scala 70:89] + wire _T_815 = io_ins[14] & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_816 = _T_815 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_817 = _T_809 | _T_816; // @[dec_dec_ctl.scala 71:31] + wire _T_828 = _T_32 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_829 = _T_828 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_830 = _T_829 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_831 = _T_830 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_832 = _T_831 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_833 = _T_817 | _T_832; // @[dec_dec_ctl.scala 71:57] + wire _T_845 = _T_57 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_846 = _T_845 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_847 = _T_846 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_848 = _T_847 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_866 = _T_63 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_867 = _T_866 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_868 = _T_867 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_878 = _T_63 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_879 = _T_878 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_880 = _T_879 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_889 = io_ins[14] & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_890 = _T_889 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_891 = _T_890 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_901 = io_ins[14] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_902 = _T_901 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_903 = _T_902 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_919 = _T_322 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_920 = _T_919 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_929 = io_ins[12] & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_930 = _T_929 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_937 = io_ins[13] & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_943 = _T_806 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_947 = io_ins[7] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_948 = _T_947 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_949 = _T_943 | _T_948; // @[dec_dec_ctl.scala 92:44] + wire _T_953 = io_ins[8] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_954 = _T_953 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_955 = _T_949 | _T_954; // @[dec_dec_ctl.scala 92:67] + wire _T_959 = io_ins[9] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_960 = _T_959 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_961 = _T_955 | _T_960; // @[dec_dec_ctl.scala 92:90] + wire _T_965 = io_ins[10] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_966 = _T_965 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_967 = _T_961 | _T_966; // @[dec_dec_ctl.scala 93:26] + wire _T_971 = io_ins[11] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_972 = _T_971 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_980 = _T_269 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_981 = _T_980 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_982 = _T_981 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_989 = _T_254 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_990 = _T_989 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_991 = _T_990 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_992 = _T_982 | _T_991; // @[dec_dec_ctl.scala 95:49] + wire _T_999 = _T_239 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1000 = _T_999 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1001 = _T_1000 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1002 = _T_992 | _T_1001; // @[dec_dec_ctl.scala 95:79] + wire _T_1009 = _T_224 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1010 = _T_1009 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1011 = _T_1010 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1012 = _T_1002 | _T_1011; // @[dec_dec_ctl.scala 96:33] + wire _T_1019 = _T_209 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1020 = _T_1019 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1021 = _T_1020 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1028 = io_ins[15] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1029 = _T_1028 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1030 = _T_1029 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1036 = io_ins[16] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1037 = _T_1036 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1038 = _T_1037 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1039 = _T_1030 | _T_1038; // @[dec_dec_ctl.scala 98:47] + wire _T_1045 = io_ins[17] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1046 = _T_1045 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1047 = _T_1046 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1048 = _T_1039 | _T_1047; // @[dec_dec_ctl.scala 98:75] + wire _T_1054 = io_ins[18] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1055 = _T_1054 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1056 = _T_1055 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1057 = _T_1048 | _T_1056; // @[dec_dec_ctl.scala 98:103] + wire _T_1063 = io_ins[19] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1064 = _T_1063 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1065 = _T_1064 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1072 = _T_34 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1073 = _T_1072 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1081 = _T_387 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1082 = _T_1081 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1087 = io_ins[15] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1088 = _T_1087 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1089 = _T_1088 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1090 = _T_1082 | _T_1089; // @[dec_dec_ctl.scala 103:47] + wire _T_1095 = io_ins[16] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1096 = _T_1095 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1097 = _T_1096 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1098 = _T_1090 | _T_1097; // @[dec_dec_ctl.scala 103:74] + wire _T_1103 = io_ins[17] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1104 = _T_1103 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1105 = _T_1104 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1106 = _T_1098 | _T_1105; // @[dec_dec_ctl.scala 103:101] + wire _T_1111 = io_ins[18] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1112 = _T_1111 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1113 = _T_1112 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1114 = _T_1106 | _T_1113; // @[dec_dec_ctl.scala 104:30] + wire _T_1119 = io_ins[19] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1120 = _T_1119 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1121 = _T_1120 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1126 = _T_11 & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_1133 = _T_262 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1134 = _T_1133 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1135 = _T_1126 | _T_1134; // @[dec_dec_ctl.scala 106:41] + wire _T_1142 = _T_247 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1143 = _T_1142 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1144 = _T_1135 | _T_1143; // @[dec_dec_ctl.scala 106:68] + wire _T_1151 = _T_232 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1152 = _T_1151 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1153 = _T_1144 | _T_1152; // @[dec_dec_ctl.scala 106:95] + wire _T_1160 = _T_217 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1161 = _T_1160 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1162 = _T_1153 | _T_1161; // @[dec_dec_ctl.scala 107:30] + wire _T_1169 = _T_202 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1170 = _T_1169 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1171 = _T_1162 | _T_1170; // @[dec_dec_ctl.scala 107:58] + wire _T_1177 = _T_269 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1178 = _T_1177 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1179 = _T_1171 | _T_1178; // @[dec_dec_ctl.scala 107:86] + wire _T_1185 = _T_254 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1186 = _T_1185 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1187 = _T_1179 | _T_1186; // @[dec_dec_ctl.scala 108:30] + wire _T_1193 = _T_239 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1194 = _T_1193 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1195 = _T_1187 | _T_1194; // @[dec_dec_ctl.scala 108:57] + wire _T_1201 = _T_224 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1202 = _T_1201 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1203 = _T_1195 | _T_1202; // @[dec_dec_ctl.scala 108:84] + wire _T_1209 = _T_209 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1210 = _T_1209 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1216 = io_ins[12] & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1217 = _T_1216 & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_1226 = _T_4 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1227 = _T_1226 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1228 = _T_1227 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1229 = _T_1228 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1230 = _T_1217 | _T_1229; // @[dec_dec_ctl.scala 111:45] + wire _T_1239 = _T_1230 | _T_1134; // @[dec_dec_ctl.scala 111:78] + wire _T_1248 = _T_1239 | _T_1143; // @[dec_dec_ctl.scala 112:30] + wire _T_1257 = _T_1248 | _T_1152; // @[dec_dec_ctl.scala 112:57] + wire _T_1266 = _T_1257 | _T_1161; // @[dec_dec_ctl.scala 112:84] + wire _T_1275 = _T_1266 | _T_1170; // @[dec_dec_ctl.scala 112:112] + wire _T_1283 = _T_1275 | _T_1178; // @[dec_dec_ctl.scala 113:31] + wire _T_1291 = _T_1283 | _T_1186; // @[dec_dec_ctl.scala 113:58] + wire _T_1299 = _T_1291 | _T_1194; // @[dec_dec_ctl.scala 113:85] + wire _T_1307 = _T_1299 | _T_1202; // @[dec_dec_ctl.scala 113:112] + wire _T_1325 = _T_4 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_1326 = _T_1325 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1327 = _T_1326 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1328 = _T_1327 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1340 = _T_6 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_1341 = _T_1340 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1342 = _T_1341 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1343 = _T_1342 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1352 = io_ins[29] & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1353 = _T_1352 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1354 = _T_1353 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1370 = _T_43 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_1371 = _T_1370 & io_ins[24]; // @[dec_dec_ctl.scala 17:17] + wire _T_1372 = _T_1371 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_1373 = _T_1372 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1374 = _T_1373 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1375 = _T_1374 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1376 = _T_1375 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1377 = _T_1376 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1378 = _T_1377 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1394 = _T_65 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_1395 = _T_1394 & io_ins[23]; // @[dec_dec_ctl.scala 17:17] + wire _T_1396 = _T_1395 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1397 = _T_1396 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1398 = _T_1397 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1399 = _T_1398 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1400 = _T_1399 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1401 = _T_1400 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1402 = _T_1378 | _T_1401; // @[dec_dec_ctl.scala 122:63] + wire _T_1420 = _T_1394 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_1421 = _T_1420 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1422 = _T_1421 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1423 = _T_1422 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1424 = _T_1423 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1425 = _T_1424 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1426 = _T_1425 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1427 = _T_1402 | _T_1426; // @[dec_dec_ctl.scala 122:111] + wire _T_1440 = io_ins[27] & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_1441 = _T_1440 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_1442 = _T_1441 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1443 = _T_1442 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1444 = _T_1443 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1445 = _T_1444 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1446 = _T_1445 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1447 = _T_1427 | _T_1446; // @[dec_dec_ctl.scala 123:52] + wire _T_1457 = io_ins[30] & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_1458 = _T_1457 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_1459 = _T_1458 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1460 = _T_1459 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1461 = _T_1460 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1462 = _T_1461 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1463 = _T_1447 | _T_1462; // @[dec_dec_ctl.scala 123:93] + wire _T_1479 = _T_65 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_1480 = _T_1479 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_1481 = _T_1480 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1482 = _T_1481 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1483 = _T_1482 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1484 = _T_1483 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1485 = _T_1484 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1486 = _T_1485 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1487 = _T_1463 | _T_1486; // @[dec_dec_ctl.scala 124:39] + wire _T_1503 = _T_65 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_1504 = _T_1503 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_1505 = _T_1504 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1506 = _T_1505 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1507 = _T_1506 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1508 = _T_1507 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1509 = _T_1508 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1510 = _T_1509 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1511 = _T_1487 | _T_1510; // @[dec_dec_ctl.scala 124:87] + wire _T_1527 = _T_65 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_1528 = _T_1527 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_1529 = _T_1528 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1530 = _T_1529 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1531 = _T_1530 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1532 = _T_1531 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1533 = _T_1532 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1534 = _T_1533 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1535 = _T_1511 | _T_1534; // @[dec_dec_ctl.scala 125:51] + wire _T_1550 = io_ins[30] & io_ins[29]; // @[dec_dec_ctl.scala 17:17] + wire _T_1551 = _T_1550 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_1552 = _T_1551 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_1553 = _T_1552 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1554 = _T_1553 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1555 = _T_1554 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1556 = _T_1555 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1557 = _T_1556 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1558 = _T_1557 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1559 = _T_1535 | _T_1558; // @[dec_dec_ctl.scala 125:99] + wire _T_1574 = _T_1370 & io_ins[23]; // @[dec_dec_ctl.scala 17:17] + wire _T_1575 = _T_1574 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1576 = _T_1575 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1577 = _T_1576 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1578 = _T_1577 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1579 = _T_1578 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1580 = _T_1579 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1581 = _T_1559 | _T_1580; // @[dec_dec_ctl.scala 126:51] + wire _T_1598 = _T_731 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_1599 = _T_1598 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_1600 = _T_1599 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1601 = _T_1600 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1602 = _T_1601 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1603 = _T_1602 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1604 = _T_1603 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1605 = _T_1581 | _T_1604; // @[dec_dec_ctl.scala 126:96] + wire _T_1615 = io_ins[25] & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1616 = _T_1615 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1617 = _T_1616 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1618 = _T_1617 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1619 = _T_1618 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1620 = _T_1605 | _T_1619; // @[dec_dec_ctl.scala 127:50] + wire _T_1635 = io_ins[30] & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_1636 = _T_1635 & io_ins[24]; // @[dec_dec_ctl.scala 17:17] + wire _T_1637 = _T_1636 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1638 = _T_1637 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1639 = _T_1638 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1640 = _T_1639 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1641 = _T_1640 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1642 = _T_1641 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1643 = _T_1620 | _T_1642; // @[dec_dec_ctl.scala 127:84] + wire _T_1653 = _T_65 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1654 = _T_1653 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1655 = _T_1654 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1656 = _T_1655 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1673 = _T_781 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1674 = _T_1673 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_1675 = _T_1674 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1676 = _T_1675 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1677 = _T_1676 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1678 = _T_1677 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1679 = _T_1678 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1695 = _T_1673 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1696 = _T_1695 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1697 = _T_1696 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1698 = _T_1697 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1699 = _T_1698 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1733 = _T_1615 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1734 = _T_1733 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1735 = _T_1734 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1736 = _T_1735 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1749 = _T_782 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1750 = _T_1749 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1764 = _T_782 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_1765 = _T_1764 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1766 = _T_1765 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1800 = _T_1635 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_1801 = _T_1800 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_1802 = _T_1801 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_1803 = _T_1802 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_1804 = _T_1803 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1805 = _T_1804 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1806 = _T_1805 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1807 = _T_1806 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1808 = _T_1807 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1831 = _T_1801 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_1832 = _T_1831 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1833 = _T_1832 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1834 = _T_1833 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1835 = _T_1834 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1836 = _T_1835 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1856 = _T_1800 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_1857 = _T_1856 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1858 = _T_1857 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1859 = _T_1858 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1860 = _T_1859 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1861 = _T_1860 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1880 = _T_1635 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_1881 = _T_1880 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_1882 = _T_1881 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1883 = _T_1882 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1884 = _T_1883 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1885 = _T_1884 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1886 = _T_1885 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1905 = _T_1880 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_1906 = _T_1905 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1907 = _T_1906 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1908 = _T_1907 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1909 = _T_1908 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1910 = _T_1909 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1928 = _T_158 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_1929 = _T_1928 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1930 = _T_1929 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1931 = _T_1930 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1932 = _T_1931 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1933 = _T_1932 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1951 = _T_1928 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1952 = _T_1951 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1953 = _T_1952 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1954 = _T_1953 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1955 = _T_1954 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1969 = _T_57 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1970 = _T_1969 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1971 = _T_1970 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1984 = _T_57 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1985 = _T_1984 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1986 = _T_1985 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2002 = _T_1370 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_2003 = _T_2002 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2004 = _T_2003 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2005 = _T_2004 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2006 = _T_2005 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2019 = _T_1457 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2020 = _T_2019 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2021 = _T_2020 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2022 = _T_2021 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2038 = _T_2002 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_2039 = _T_2038 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2040 = _T_2039 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2041 = _T_2040 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2056 = _T_1635 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2057 = _T_2056 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2058 = _T_2057 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2059 = _T_2058 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2060 = _T_2059 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2076 = _T_1550 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_2077 = _T_2076 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2078 = _T_2077 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2079 = _T_2078 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2080 = _T_2079 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2081 = _T_2080 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2100 = _T_1800 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2101 = _T_2100 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2102 = _T_2101 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2103 = _T_2102 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2104 = _T_2103 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2105 = _T_2104 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2118 = _T_1370 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2119 = _T_2118 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_2120 = _T_2119 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2121 = _T_2120 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2122 = _T_2121 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2123 = _T_2122 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2124 = _T_2105 | _T_2123; // @[dec_dec_ctl.scala 172:62] + wire _T_2143 = _T_2079 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2144 = _T_2143 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2145 = _T_2144 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2146 = _T_2124 | _T_2145; // @[dec_dec_ctl.scala 172:103] + wire _T_2157 = _T_357 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2158 = _T_2157 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2159 = _T_2158 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2160 = _T_2159 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2161 = _T_2146 | _T_2160; // @[dec_dec_ctl.scala 173:48] + wire _T_2173 = io_ins[30] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2174 = _T_2173 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2175 = _T_2174 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2176 = _T_2175 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2177 = _T_2176 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2178 = _T_2177 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2179 = _T_2161 | _T_2178; // @[dec_dec_ctl.scala 173:83] + wire _T_2191 = _T_1635 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_2192 = _T_2191 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2193 = _T_2192 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2194 = _T_2193 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2195 = _T_2194 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2196 = _T_2179 | _T_2195; // @[dec_dec_ctl.scala 174:42] + wire _T_2209 = _T_2076 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2210 = _T_2209 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2211 = _T_2210 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2212 = _T_2211 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2213 = _T_2196 | _T_2212; // @[dec_dec_ctl.scala 174:79] + wire _T_2231 = _T_1550 & io_ins[24]; // @[dec_dec_ctl.scala 17:17] + wire _T_2232 = _T_2231 & io_ins[23]; // @[dec_dec_ctl.scala 17:17] + wire _T_2233 = _T_2232 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_2234 = _T_2233 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_2235 = _T_2234 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_2236 = _T_2235 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2237 = _T_2236 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2238 = _T_2237 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2239 = _T_2238 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2240 = _T_2239 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2241 = _T_2240 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2242 = _T_2213 | _T_2241; // @[dec_dec_ctl.scala 175:40] + wire _T_2264 = _T_158 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_2265 = _T_2264 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_2266 = _T_2265 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_2267 = _T_2266 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_2268 = _T_2267 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_2269 = _T_2268 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_2270 = _T_2269 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2271 = _T_2270 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2272 = _T_2271 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2273 = _T_2272 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2274 = _T_2273 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2275 = _T_2274 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2276 = _T_2242 | _T_2275; // @[dec_dec_ctl.scala 175:96] + wire _T_2300 = _T_1371 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_2301 = _T_2300 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_2302 = _T_2301 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_2303 = _T_2302 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_2304 = _T_2303 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2305 = _T_2304 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2306 = _T_2305 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2307 = _T_2306 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2308 = _T_2307 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2309 = _T_2308 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2310 = _T_2276 | _T_2309; // @[dec_dec_ctl.scala 176:65] + wire _T_2333 = _T_2232 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_2334 = _T_2333 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_2335 = _T_2334 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_2336 = _T_2335 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2337 = _T_2336 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2338 = _T_2337 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2339 = _T_2338 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2340 = _T_2339 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2341 = _T_2340 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2342 = _T_2310 | _T_2341; // @[dec_dec_ctl.scala 177:64] + wire _T_2373 = _T_2264 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2374 = _T_2373 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2375 = _T_2374 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2376 = _T_2375 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2377 = _T_2376 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2393 = _T_94 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2394 = _T_2393 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2395 = _T_2394 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2396 = _T_2395 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2397 = _T_2396 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2414 = _T_1551 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2415 = _T_2414 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2416 = _T_2415 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2417 = _T_2416 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2418 = _T_2417 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2434 = _T_94 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_2435 = _T_2434 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2436 = _T_2435 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2437 = _T_2436 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2438 = _T_2437 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2439 = _T_2438 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2455 = _T_66 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2456 = _T_2455 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2457 = _T_2456 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2458 = _T_2457 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2459 = _T_2458 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2474 = _T_2434 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2475 = _T_2474 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2476 = _T_2475 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2477 = _T_2476 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2478 = _T_2477 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2497 = _T_2038 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2498 = _T_2497 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2499 = _T_2498 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2500 = _T_2499 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2515 = _T_1458 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2516 = _T_2515 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2517 = _T_2516 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2518 = _T_2517 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2552 = _T_56 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2553 = _T_2552 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2554 = _T_2553 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2555 = _T_2554 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2556 = _T_2555 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2568 = io_ins[27] & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2569 = _T_2568 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_2570 = _T_2569 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2571 = _T_2570 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2572 = _T_2571 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2586 = _T_2568 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2587 = _T_2586 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2588 = _T_2587 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2589 = _T_2588 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2603 = _T_2552 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2604 = _T_2603 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2605 = _T_2604 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2621 = _T_1551 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2622 = _T_2621 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2623 = _T_2622 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2624 = _T_2623 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2625 = _T_2624 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2642 = _T_2264 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2643 = _T_2642 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2644 = _T_2643 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2645 = _T_2644 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2646 = _T_2645 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2668 = _T_1599 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2669 = _T_2668 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2670 = _T_2669 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2671 = _T_2670 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2672 = _T_2671 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2693 = _T_1599 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2694 = _T_2693 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2695 = _T_2694 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2696 = _T_2695 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2697 = _T_2696 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2714 = _T_1928 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2715 = _T_2714 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2716 = _T_2715 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2717 = _T_2716 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2718 = _T_2717 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2734 = _T_1598 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2735 = _T_2734 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2736 = _T_2735 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2737 = _T_2736 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2738 = _T_2737 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2739 = _T_2718 | _T_2738; // @[dec_dec_ctl.scala 212:58] + wire _T_2756 = _T_2739 | _T_2195; // @[dec_dec_ctl.scala 212:101] + wire _T_2769 = _T_1440 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2770 = _T_2769 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2771 = _T_2770 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2772 = _T_2771 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2773 = _T_2772 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2774 = _T_2756 | _T_2773; // @[dec_dec_ctl.scala 213:40] + wire _T_2788 = _T_2175 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2789 = _T_2788 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2790 = _T_2789 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2791 = _T_2774 | _T_2790; // @[dec_dec_ctl.scala 213:79] + wire _T_2803 = _T_27 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2804 = _T_2803 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2805 = _T_2804 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2806 = _T_2805 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2807 = _T_2806 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2808 = _T_2791 | _T_2807; // @[dec_dec_ctl.scala 214:41] + wire _T_2826 = _T_1599 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2827 = _T_2826 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2828 = _T_2827 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2829 = _T_2828 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2830 = _T_2829 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2831 = _T_2808 | _T_2830; // @[dec_dec_ctl.scala 214:78] + wire _T_2842 = io_ins[29] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2843 = _T_2842 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2844 = _T_2843 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2845 = _T_2844 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2846 = _T_2845 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2847 = _T_2846 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2871 = _T_1636 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_2872 = _T_2871 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_2873 = _T_2872 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_2874 = _T_2873 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2875 = _T_2874 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2876 = _T_2875 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2877 = _T_2876 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2878 = _T_2877 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2900 = _T_2871 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_2901 = _T_2900 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2902 = _T_2901 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2903 = _T_2902 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2904 = _T_2903 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2905 = _T_2904 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2927 = _T_2871 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_2928 = _T_2927 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2929 = _T_2928 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2930 = _T_2929 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2931 = _T_2930 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2932 = _T_2931 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2953 = _T_1635 & io_ins[23]; // @[dec_dec_ctl.scala 17:17] + wire _T_2954 = _T_2953 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_2955 = _T_2954 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_2956 = _T_2955 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2957 = _T_2956 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2958 = _T_2957 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2959 = _T_2958 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2960 = _T_2959 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2979 = _T_2953 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_2980 = _T_2979 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2981 = _T_2980 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2982 = _T_2981 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2983 = _T_2982 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2984 = _T_2983 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3003 = _T_2953 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_3004 = _T_3003 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_3005 = _T_3004 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_3006 = _T_3005 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_3007 = _T_3006 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3008 = _T_3007 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3043 = _T_1458 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_3044 = _T_3043 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3045 = _T_3044 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3074 = _T_74 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3075 = _T_3074 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3076 = _T_3075 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3077 = _T_3076 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3091 = _T_2843 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3092 = _T_3091 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3093 = _T_3092 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3104 = _T_2842 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_3105 = _T_3104 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3106 = _T_3105 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3117 = io_ins[29] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3118 = _T_3117 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3119 = _T_3118 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3120 = _T_3119 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3129 = io_ins[28] & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_3130 = _T_3129 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_3131 = _T_3130 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3132 = _T_3131 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3147 = _T_733 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3148 = _T_3147 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3149 = _T_3132 | _T_3148; // @[dec_dec_ctl.scala 243:51] + wire _T_3164 = _T_597 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_3165 = _T_3164 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_3166 = _T_3165 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3167 = _T_3166 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3168 = _T_3149 | _T_3167; // @[dec_dec_ctl.scala 243:89] + wire _T_3183 = _T_688 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3184 = _T_3183 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3185 = _T_3168 | _T_3184; // @[dec_dec_ctl.scala 244:44] + wire _T_3192 = _T_3185 | _T_114; // @[dec_dec_ctl.scala 244:82] + wire _T_3196 = _T_3192 | _T_398; // @[dec_dec_ctl.scala 245:28] + wire _T_3206 = ~io_ins[31]; // @[dec_dec_ctl.scala 15:46] + wire _T_3215 = ~io_ins[26]; // @[dec_dec_ctl.scala 15:46] + wire _T_3227 = ~io_ins[19]; // @[dec_dec_ctl.scala 15:46] + wire _T_3229 = ~io_ins[18]; // @[dec_dec_ctl.scala 15:46] + wire _T_3231 = ~io_ins[17]; // @[dec_dec_ctl.scala 15:46] + wire _T_3233 = ~io_ins[16]; // @[dec_dec_ctl.scala 15:46] + wire _T_3235 = ~io_ins[15]; // @[dec_dec_ctl.scala 15:46] + wire _T_3239 = ~io_ins[11]; // @[dec_dec_ctl.scala 15:46] + wire _T_3241 = ~io_ins[10]; // @[dec_dec_ctl.scala 15:46] + wire _T_3243 = ~io_ins[9]; // @[dec_dec_ctl.scala 15:46] + wire _T_3245 = ~io_ins[8]; // @[dec_dec_ctl.scala 15:46] + wire _T_3247 = ~io_ins[7]; // @[dec_dec_ctl.scala 15:46] + wire _T_3257 = _T_3206 & _T_43; // @[dec_dec_ctl.scala 17:17] + wire _T_3258 = _T_3257 & _T_90; // @[dec_dec_ctl.scala 17:17] + wire _T_3259 = _T_3258 & io_ins[28]; // @[dec_dec_ctl.scala 17:17] + wire _T_3260 = _T_3259 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_3261 = _T_3260 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3262 = _T_3261 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3263 = _T_3262 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_3264 = _T_3263 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_3265 = _T_3264 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_3266 = _T_3265 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_3267 = _T_3266 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_3268 = _T_3267 & _T_3227; // @[dec_dec_ctl.scala 17:17] + wire _T_3269 = _T_3268 & _T_3229; // @[dec_dec_ctl.scala 17:17] + wire _T_3270 = _T_3269 & _T_3231; // @[dec_dec_ctl.scala 17:17] + wire _T_3271 = _T_3270 & _T_3233; // @[dec_dec_ctl.scala 17:17] + wire _T_3272 = _T_3271 & _T_3235; // @[dec_dec_ctl.scala 17:17] + wire _T_3273 = _T_3272 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_3274 = _T_3273 & _T_3239; // @[dec_dec_ctl.scala 17:17] + wire _T_3275 = _T_3274 & _T_3241; // @[dec_dec_ctl.scala 17:17] + wire _T_3276 = _T_3275 & _T_3243; // @[dec_dec_ctl.scala 17:17] + wire _T_3277 = _T_3276 & _T_3245; // @[dec_dec_ctl.scala 17:17] + wire _T_3278 = _T_3277 & _T_3247; // @[dec_dec_ctl.scala 17:17] + wire _T_3279 = _T_3278 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_3280 = _T_3279 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3281 = _T_3280 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3282 = _T_3281 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3283 = _T_3282 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_3284 = _T_3283 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3285 = _T_3284 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3339 = _T_3257 & io_ins[29]; // @[dec_dec_ctl.scala 17:17] + wire _T_3340 = _T_3339 & io_ins[28]; // @[dec_dec_ctl.scala 17:17] + wire _T_3341 = _T_3340 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_3342 = _T_3341 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3343 = _T_3342 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3344 = _T_3343 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_3345 = _T_3344 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_3346 = _T_3345 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_3347 = _T_3346 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_3348 = _T_3347 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_3349 = _T_3348 & _T_3227; // @[dec_dec_ctl.scala 17:17] + wire _T_3350 = _T_3349 & _T_3229; // @[dec_dec_ctl.scala 17:17] + wire _T_3351 = _T_3350 & _T_3231; // @[dec_dec_ctl.scala 17:17] + wire _T_3352 = _T_3351 & _T_3233; // @[dec_dec_ctl.scala 17:17] + wire _T_3353 = _T_3352 & _T_3235; // @[dec_dec_ctl.scala 17:17] + wire _T_3354 = _T_3353 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_3355 = _T_3354 & _T_3239; // @[dec_dec_ctl.scala 17:17] + wire _T_3356 = _T_3355 & _T_3241; // @[dec_dec_ctl.scala 17:17] + wire _T_3357 = _T_3356 & _T_3243; // @[dec_dec_ctl.scala 17:17] + wire _T_3358 = _T_3357 & _T_3245; // @[dec_dec_ctl.scala 17:17] + wire _T_3359 = _T_3358 & _T_3247; // @[dec_dec_ctl.scala 17:17] + wire _T_3360 = _T_3359 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_3361 = _T_3360 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3362 = _T_3361 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3363 = _T_3362 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3364 = _T_3363 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_3365 = _T_3364 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3366 = _T_3365 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3367 = _T_3285 | _T_3366; // @[dec_dec_ctl.scala 248:136] + wire _T_3375 = ~io_ins[28]; // @[dec_dec_ctl.scala 15:46] + wire _T_3422 = _T_3258 & _T_3375; // @[dec_dec_ctl.scala 17:17] + wire _T_3423 = _T_3422 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_3424 = _T_3423 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3425 = _T_3424 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3426 = _T_3425 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_3427 = _T_3426 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_3428 = _T_3427 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_3429 = _T_3428 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_3430 = _T_3429 & _T_3227; // @[dec_dec_ctl.scala 17:17] + wire _T_3431 = _T_3430 & _T_3229; // @[dec_dec_ctl.scala 17:17] + wire _T_3432 = _T_3431 & _T_3231; // @[dec_dec_ctl.scala 17:17] + wire _T_3433 = _T_3432 & _T_3233; // @[dec_dec_ctl.scala 17:17] + wire _T_3434 = _T_3433 & _T_3235; // @[dec_dec_ctl.scala 17:17] + wire _T_3435 = _T_3434 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_3436 = _T_3435 & _T_3239; // @[dec_dec_ctl.scala 17:17] + wire _T_3437 = _T_3436 & _T_3241; // @[dec_dec_ctl.scala 17:17] + wire _T_3438 = _T_3437 & _T_3243; // @[dec_dec_ctl.scala 17:17] + wire _T_3439 = _T_3438 & _T_3245; // @[dec_dec_ctl.scala 17:17] + wire _T_3440 = _T_3439 & _T_3247; // @[dec_dec_ctl.scala 17:17] + wire _T_3441 = _T_3440 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3442 = _T_3441 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3443 = _T_3442 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3444 = _T_3443 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_3445 = _T_3444 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3446 = _T_3445 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3447 = _T_3367 | _T_3446; // @[dec_dec_ctl.scala 249:122] + wire _T_3471 = _T_3206 & io_ins[29]; // @[dec_dec_ctl.scala 17:17] + wire _T_3472 = _T_3471 & _T_3375; // @[dec_dec_ctl.scala 17:17] + wire _T_3473 = _T_3472 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3474 = _T_3473 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3475 = _T_3474 & io_ins[24]; // @[dec_dec_ctl.scala 17:17] + wire _T_3476 = _T_3475 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_3477 = _T_3476 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_3478 = _T_3477 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3479 = _T_3478 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3480 = _T_3479 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3481 = _T_3480 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3482 = _T_3481 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3483 = _T_3482 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3484 = _T_3447 | _T_3483; // @[dec_dec_ctl.scala 250:119] + wire _T_3514 = _T_3476 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_3515 = _T_3514 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3516 = _T_3515 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3517 = _T_3516 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3518 = _T_3517 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3519 = _T_3518 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3520 = _T_3519 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3521 = _T_3484 | _T_3520; // @[dec_dec_ctl.scala 251:65] + wire _T_3550 = _T_3474 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_3551 = _T_3550 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_3552 = _T_3551 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_3553 = _T_3552 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3554 = _T_3553 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3555 = _T_3554 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3556 = _T_3555 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3557 = _T_3556 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3558 = _T_3557 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3559 = _T_3521 | _T_3558; // @[dec_dec_ctl.scala 251:127] + wire _T_3588 = _T_3474 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_3589 = _T_3588 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_3590 = _T_3589 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_3591 = _T_3590 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3592 = _T_3591 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3593 = _T_3592 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3594 = _T_3593 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3595 = _T_3594 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3596 = _T_3595 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3597 = _T_3559 | _T_3596; // @[dec_dec_ctl.scala 252:66] + wire _T_3620 = _T_3422 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3621 = _T_3620 & io_ins[25]; // @[dec_dec_ctl.scala 17:17] + wire _T_3622 = _T_3621 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_3623 = _T_3622 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3624 = _T_3623 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3625 = _T_3624 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3626 = _T_3625 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3627 = _T_3626 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3628 = _T_3597 | _T_3627; // @[dec_dec_ctl.scala 252:129] + wire _T_3651 = _T_3257 & _T_3375; // @[dec_dec_ctl.scala 17:17] + wire _T_3652 = _T_3651 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3653 = _T_3652 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3654 = _T_3653 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_3655 = _T_3654 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3656 = _T_3655 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3657 = _T_3656 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3658 = _T_3657 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3659 = _T_3658 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3660 = _T_3659 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3661 = _T_3628 | _T_3660; // @[dec_dec_ctl.scala 253:58] + wire _T_3686 = _T_3651 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_3687 = _T_3686 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3688 = _T_3687 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3689 = _T_3688 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_3690 = _T_3689 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3691 = _T_3690 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3692 = _T_3691 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3693 = _T_3692 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3694 = _T_3693 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3695 = _T_3694 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3696 = _T_3661 | _T_3695; // @[dec_dec_ctl.scala 253:114] + wire _T_3724 = _T_3688 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_3725 = _T_3724 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3726 = _T_3725 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3727 = _T_3726 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3728 = _T_3727 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3729 = _T_3728 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3730 = _T_3729 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3731 = _T_3696 | _T_3730; // @[dec_dec_ctl.scala 254:63] + wire _T_3755 = _T_3206 & _T_90; // @[dec_dec_ctl.scala 17:17] + wire _T_3756 = _T_3755 & _T_3375; // @[dec_dec_ctl.scala 17:17] + wire _T_3757 = _T_3756 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_3758 = _T_3757 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3759 = _T_3758 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3760 = _T_3759 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_3761 = _T_3760 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3762 = _T_3761 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3763 = _T_3762 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3764 = _T_3763 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3765 = _T_3764 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3766 = _T_3765 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3767 = _T_3731 | _T_3766; // @[dec_dec_ctl.scala 254:123] + wire _T_3788 = _T_3206 & _T_3375; // @[dec_dec_ctl.scala 17:17] + wire _T_3789 = _T_3788 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_3790 = _T_3789 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3791 = _T_3790 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3792 = _T_3791 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_3793 = _T_3792 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3794 = _T_3793 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3795 = _T_3794 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3796 = _T_3795 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3797 = _T_3796 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3798 = _T_3797 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3799 = _T_3767 | _T_3798; // @[dec_dec_ctl.scala 255:64] + wire _T_3825 = _T_3620 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_3826 = _T_3825 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_3827 = _T_3826 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3828 = _T_3827 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3829 = _T_3828 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3830 = _T_3829 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_3831 = _T_3830 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3832 = _T_3831 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3833 = _T_3799 | _T_3832; // @[dec_dec_ctl.scala 255:119] + wire _T_3857 = _T_3620 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_3858 = _T_3857 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3859 = _T_3858 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3860 = _T_3859 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3861 = _T_3860 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3862 = _T_3861 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3863 = _T_3862 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3864 = _T_3833 | _T_3863; // @[dec_dec_ctl.scala 256:61] + wire _T_3885 = _T_3206 & io_ins[30]; // @[dec_dec_ctl.scala 17:17] + wire _T_3886 = _T_3885 & _T_3375; // @[dec_dec_ctl.scala 17:17] + wire _T_3887 = _T_3886 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_3888 = _T_3887 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3889 = _T_3888 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3890 = _T_3889 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_3891 = _T_3890 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_3892 = _T_3891 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3893 = _T_3892 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3894 = _T_3893 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3895 = _T_3894 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3896 = _T_3895 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3897 = _T_3864 | _T_3896; // @[dec_dec_ctl.scala 256:115] + wire _T_3919 = _T_3472 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_3920 = _T_3919 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3921 = _T_3920 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3922 = _T_3921 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3923 = _T_3922 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3924 = _T_3923 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3925 = _T_3924 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3926 = _T_3925 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3927 = _T_3926 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3928 = _T_3897 | _T_3927; // @[dec_dec_ctl.scala 257:61] + wire _T_3955 = _T_3688 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3956 = _T_3955 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3957 = _T_3956 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3958 = _T_3957 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3959 = _T_3958 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3960 = _T_3959 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3961 = _T_3928 | _T_3960; // @[dec_dec_ctl.scala 257:116] + wire _T_3987 = _T_3424 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3988 = _T_3987 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3989 = _T_3988 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3990 = _T_3989 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3991 = _T_3990 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3992 = _T_3991 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3993 = _T_3961 | _T_3992; // @[dec_dec_ctl.scala 258:59] + wire _T_4010 = _T_444 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_4011 = _T_4010 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4012 = _T_4011 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4013 = _T_4012 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4014 = _T_4013 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4015 = _T_4014 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4016 = _T_3993 | _T_4015; // @[dec_dec_ctl.scala 258:114] + wire _T_4038 = _T_3756 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_4039 = _T_4038 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_4040 = _T_4039 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_4041 = _T_4040 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_4042 = _T_4041 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4043 = _T_4042 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_4044 = _T_4043 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4045 = _T_4044 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4046 = _T_4045 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4047 = _T_4016 | _T_4046; // @[dec_dec_ctl.scala 259:46] + wire _T_4072 = _T_3474 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_4073 = _T_4072 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_4074 = _T_4073 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4075 = _T_4074 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_4076 = _T_4075 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4077 = _T_4076 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4078 = _T_4077 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4079 = _T_4078 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4080 = _T_4047 | _T_4079; // @[dec_dec_ctl.scala 259:100] + wire _T_4092 = io_ins[14] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_4093 = _T_4092 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4094 = _T_4093 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4095 = _T_4094 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4096 = _T_4095 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4097 = _T_4096 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4098 = _T_4097 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4099 = _T_4080 | _T_4098; // @[dec_dec_ctl.scala 260:60] + wire _T_4114 = _T_195 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4115 = _T_4114 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4116 = _T_4115 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4117 = _T_4116 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4118 = _T_4117 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4119 = _T_4118 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4120 = _T_4099 | _T_4119; // @[dec_dec_ctl.scala 260:97] + wire _T_4132 = _T_36 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_4133 = _T_4132 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_4134 = _T_4133 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_4135 = _T_4134 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4136 = _T_4135 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4137 = _T_4136 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4138 = _T_4120 | _T_4137; // @[dec_dec_ctl.scala 261:43] + wire _T_4152 = _T_1073 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4153 = _T_4152 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4154 = _T_4153 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4155 = _T_4154 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4156 = _T_4155 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4157 = _T_4138 | _T_4156; // @[dec_dec_ctl.scala 261:79] + wire _T_4226 = _T_3429 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_4227 = _T_4226 & _T_3227; // @[dec_dec_ctl.scala 17:17] + wire _T_4228 = _T_4227 & _T_3229; // @[dec_dec_ctl.scala 17:17] + wire _T_4229 = _T_4228 & _T_3231; // @[dec_dec_ctl.scala 17:17] + wire _T_4230 = _T_4229 & _T_3233; // @[dec_dec_ctl.scala 17:17] + wire _T_4231 = _T_4230 & _T_3235; // @[dec_dec_ctl.scala 17:17] + wire _T_4232 = _T_4231 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_4233 = _T_4232 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_4234 = _T_4233 & _T_3239; // @[dec_dec_ctl.scala 17:17] + wire _T_4235 = _T_4234 & _T_3241; // @[dec_dec_ctl.scala 17:17] + wire _T_4236 = _T_4235 & _T_3243; // @[dec_dec_ctl.scala 17:17] + wire _T_4237 = _T_4236 & _T_3245; // @[dec_dec_ctl.scala 17:17] + wire _T_4238 = _T_4237 & _T_3247; // @[dec_dec_ctl.scala 17:17] + wire _T_4239 = _T_4238 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_4240 = _T_4239 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_4241 = _T_4240 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4242 = _T_4241 & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_4243 = _T_4242 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_4244 = _T_4243 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4245 = _T_4244 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4246 = _T_4157 | _T_4245; // @[dec_dec_ctl.scala 261:117] + wire _T_4294 = _T_3422 & _T_3227; // @[dec_dec_ctl.scala 17:17] + wire _T_4295 = _T_4294 & _T_3229; // @[dec_dec_ctl.scala 17:17] + wire _T_4296 = _T_4295 & _T_3231; // @[dec_dec_ctl.scala 17:17] + wire _T_4297 = _T_4296 & _T_3233; // @[dec_dec_ctl.scala 17:17] + wire _T_4298 = _T_4297 & _T_3235; // @[dec_dec_ctl.scala 17:17] + wire _T_4299 = _T_4298 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_4300 = _T_4299 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_4301 = _T_4300 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_4302 = _T_4301 & _T_3239; // @[dec_dec_ctl.scala 17:17] + wire _T_4303 = _T_4302 & _T_3241; // @[dec_dec_ctl.scala 17:17] + wire _T_4304 = _T_4303 & _T_3243; // @[dec_dec_ctl.scala 17:17] + wire _T_4305 = _T_4304 & _T_3245; // @[dec_dec_ctl.scala 17:17] + wire _T_4306 = _T_4305 & _T_3247; // @[dec_dec_ctl.scala 17:17] + wire _T_4307 = _T_4306 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_4308 = _T_4307 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_4309 = _T_4308 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4310 = _T_4309 & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_4311 = _T_4310 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_4312 = _T_4311 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4313 = _T_4312 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4314 = _T_4246 | _T_4313; // @[dec_dec_ctl.scala 262:130] + wire _T_4326 = _T_806 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4327 = _T_4326 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_4328 = _T_4327 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4329 = _T_4328 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4330 = _T_4329 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4331 = _T_4330 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4332 = _T_4314 | _T_4331; // @[dec_dec_ctl.scala 263:102] + wire _T_4341 = io_ins[6] & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4342 = _T_4341 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4343 = _T_4342 & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_4344 = _T_4343 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_4345 = _T_4344 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4346 = _T_4345 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4347 = _T_4332 | _T_4346; // @[dec_dec_ctl.scala 264:39] + wire _T_4363 = _T_866 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_4364 = _T_4363 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4365 = _T_4364 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4366 = _T_4365 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4367 = _T_4366 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4368 = _T_4367 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4369 = _T_4347 | _T_4368; // @[dec_dec_ctl.scala 264:71] + wire _T_4384 = _T_34 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_4385 = _T_4384 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_4386 = _T_4385 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4387 = _T_4386 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4388 = _T_4387 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4389 = _T_4388 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4390 = _T_4389 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4391 = _T_4369 | _T_4390; // @[dec_dec_ctl.scala 264:112] + wire _T_4403 = _T_937 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_4404 = _T_4403 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_4405 = _T_4404 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4406 = _T_4405 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4407 = _T_4406 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4408 = _T_4391 | _T_4407; // @[dec_dec_ctl.scala 265:43] + wire _T_4417 = _T_279 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_4418 = _T_4417 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4419 = _T_4418 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_4420 = _T_4419 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4421 = _T_4420 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + assign io_out_clz = _T_1808 & _T_194; // @[dec_dec_ctl.scala 144:14] + assign io_out_ctz = _T_1836 & _T_194; // @[dec_dec_ctl.scala 146:14] + assign io_out_pcnt = _T_1861 & _T_194; // @[dec_dec_ctl.scala 148:15] + assign io_out_sext_b = _T_1886 & _T_194; // @[dec_dec_ctl.scala 150:17] + assign io_out_sext_h = _T_1910 & _T_194; // @[dec_dec_ctl.scala 152:17] + assign io_out_slo = _T_1933 & _T_194; // @[dec_dec_ctl.scala 154:14] + assign io_out_sro = _T_1955 & _T_194; // @[dec_dec_ctl.scala 156:14] + assign io_out_min = _T_1971 & _T_194; // @[dec_dec_ctl.scala 158:14] + assign io_out_max = _T_1986 & _T_194; // @[dec_dec_ctl.scala 160:14] + assign io_out_pack = _T_2006 & _T_194; // @[dec_dec_ctl.scala 162:15] + assign io_out_packu = _T_2022 & _T_194; // @[dec_dec_ctl.scala 164:16] + assign io_out_packh = _T_2041 & _T_194; // @[dec_dec_ctl.scala 166:16] + assign io_out_rol = _T_2060 & _T_194; // @[dec_dec_ctl.scala 168:14] + assign io_out_ror = _T_2081 & _T_194; // @[dec_dec_ctl.scala 170:14] + assign io_out_grev = _T_2625 & _T_194; // @[dec_dec_ctl.scala 204:15] + assign io_out_gorc = _T_2646 & _T_194; // @[dec_dec_ctl.scala 206:15] + assign io_out_zbb = _T_2342 | _T_526; // @[dec_dec_ctl.scala 172:14] + assign io_out_sbset = _T_2377 & _T_194; // @[dec_dec_ctl.scala 180:16] + assign io_out_sbclr = _T_2397 & _T_194; // @[dec_dec_ctl.scala 182:16] + assign io_out_sbinv = _T_2418 & _T_194; // @[dec_dec_ctl.scala 184:16] + assign io_out_sbext = _T_2439 & _T_194; // @[dec_dec_ctl.scala 186:16] + assign io_out_zbs = _T_2459 | _T_2478; // @[dec_dec_ctl.scala 188:14] + assign io_out_bext = _T_2500 & _T_194; // @[dec_dec_ctl.scala 190:15] + assign io_out_bdep = _T_2518 & _T_194; // @[dec_dec_ctl.scala 192:15] + assign io_out_zbe = _T_1445 & _T_194; // @[dec_dec_ctl.scala 194:14] + assign io_out_clmul = _T_2556 & _T_194; // @[dec_dec_ctl.scala 196:16] + assign io_out_clmulh = _T_2572 & _T_194; // @[dec_dec_ctl.scala 198:17] + assign io_out_clmulr = _T_2589 & _T_194; // @[dec_dec_ctl.scala 200:17] + assign io_out_zbc = _T_2605 & _T_194; // @[dec_dec_ctl.scala 202:14] + assign io_out_shfl = _T_2672 & _T_194; // @[dec_dec_ctl.scala 208:15] + assign io_out_unshfl = _T_2697 & _T_194; // @[dec_dec_ctl.scala 210:17] + assign io_out_zbp = _T_2831 | _T_2847; // @[dec_dec_ctl.scala 212:14] + assign io_out_crc32_b = _T_2878 & _T_194; // @[dec_dec_ctl.scala 217:18] + assign io_out_crc32_h = _T_2905 & _T_194; // @[dec_dec_ctl.scala 219:18] + assign io_out_crc32_w = _T_2932 & _T_194; // @[dec_dec_ctl.scala 221:18] + assign io_out_crc32c_b = _T_2960 & _T_194; // @[dec_dec_ctl.scala 223:19] + assign io_out_crc32c_h = _T_2984 & _T_194; // @[dec_dec_ctl.scala 225:19] + assign io_out_crc32c_w = _T_3008 & _T_194; // @[dec_dec_ctl.scala 227:19] + assign io_out_zbr = _T_1641 & _T_194; // @[dec_dec_ctl.scala 229:14] + assign io_out_bfp = _T_3045 & _T_194; // @[dec_dec_ctl.scala 231:14] + assign io_out_zbf = _T_3045 & _T_194; // @[dec_dec_ctl.scala 233:14] + assign io_out_sh1add = _T_3077 & _T_194; // @[dec_dec_ctl.scala 235:17] + assign io_out_sh2add = _T_3093 & _T_194; // @[dec_dec_ctl.scala 237:17] + assign io_out_sh3add = _T_3106 & _T_194; // @[dec_dec_ctl.scala 239:17] + assign io_out_zba = _T_3120 & _T_194; // @[dec_dec_ctl.scala 241:14] + assign io_out_alu = _T_166 | _T_187; // @[dec_dec_ctl.scala 20:14] + assign io_out_rs1 = _T_277 | _T_282; // @[dec_dec_ctl.scala 27:14] + assign io_out_rs2 = _T_290 | _T_297; // @[dec_dec_ctl.scala 32:14] + assign io_out_imm12 = _T_325 | _T_335; // @[dec_dec_ctl.scala 34:16] + assign io_out_rd = _T_345 | io_ins[4]; // @[dec_dec_ctl.scala 36:13] + assign io_out_shimm5 = _T_377 | _T_391; // @[dec_dec_ctl.scala 38:17] + assign io_out_imm20 = _T_395 | _T_398; // @[dec_dec_ctl.scala 40:16] + assign io_out_pc = _T_406 | _T_395; // @[dec_dec_ctl.scala 42:13] + assign io_out_load = _T_417 & _T_194; // @[dec_dec_ctl.scala 44:15] + assign io_out_store = _T_296 & _T_273; // @[dec_dec_ctl.scala 46:16] + assign io_out_lsu = _T_432 & _T_194; // @[dec_dec_ctl.scala 48:14] + assign io_out_add = _T_454 | _T_476; // @[dec_dec_ctl.scala 50:14] + assign io_out_sub = _T_540 | _T_547; // @[dec_dec_ctl.scala 52:14] + assign io_out_land = _T_565 | _T_576; // @[dec_dec_ctl.scala 55:15] + assign io_out_lor = _T_619 | _T_631; // @[dec_dec_ctl.scala 57:14] + assign io_out_lxor = _T_653 | _T_668; // @[dec_dec_ctl.scala 60:15] + assign io_out_sll = _T_692 & _T_194; // @[dec_dec_ctl.scala 62:14] + assign io_out_sra = _T_712 & _T_194; // @[dec_dec_ctl.scala 64:14] + assign io_out_srl = _T_738 & _T_194; // @[dec_dec_ctl.scala 66:14] + assign io_out_slt = _T_512 | _T_539; // @[dec_dec_ctl.scala 68:14] + assign io_out_unsign = _T_833 | _T_848; // @[dec_dec_ctl.scala 70:17] + assign io_out_condbr = _T_546 & _T_194; // @[dec_dec_ctl.scala 74:17] + assign io_out_beq = _T_868 & _T_194; // @[dec_dec_ctl.scala 76:14] + assign io_out_bne = _T_880 & _T_194; // @[dec_dec_ctl.scala 78:14] + assign io_out_bge = _T_891 & _T_194; // @[dec_dec_ctl.scala 80:14] + assign io_out_blt = _T_903 & _T_194; // @[dec_dec_ctl.scala 82:14] + assign io_out_jal = io_ins[6] & io_ins[2]; // @[dec_dec_ctl.scala 84:14] + assign io_out_by = _T_920 & _T_194; // @[dec_dec_ctl.scala 86:13] + assign io_out_half = _T_930 & _T_194; // @[dec_dec_ctl.scala 88:15] + assign io_out_word = _T_937 & _T_273; // @[dec_dec_ctl.scala 90:15] + assign io_out_csr_read = _T_967 | _T_972; // @[dec_dec_ctl.scala 92:19] + assign io_out_csr_clr = _T_1012 | _T_1021; // @[dec_dec_ctl.scala 95:18] + assign io_out_csr_set = _T_1057 | _T_1065; // @[dec_dec_ctl.scala 98:18] + assign io_out_csr_write = _T_1073 & io_ins[4]; // @[dec_dec_ctl.scala 101:20] + assign io_out_csr_imm = _T_1114 | _T_1121; // @[dec_dec_ctl.scala 103:18] + assign io_out_presync = _T_1203 | _T_1210; // @[dec_dec_ctl.scala 106:18] + assign io_out_postsync = _T_1307 | _T_1210; // @[dec_dec_ctl.scala 111:19] + assign io_out_ebreak = _T_1328 & io_ins[4]; // @[dec_dec_ctl.scala 116:17] + assign io_out_ecall = _T_1343 & io_ins[4]; // @[dec_dec_ctl.scala 118:16] + assign io_out_mret = _T_1354 & io_ins[4]; // @[dec_dec_ctl.scala 120:15] + assign io_out_mul = _T_1643 | _T_1656; // @[dec_dec_ctl.scala 122:14] + assign io_out_rs1_sign = _T_1679 | _T_1699; // @[dec_dec_ctl.scala 130:19] + assign io_out_rs2_sign = _T_1698 & _T_194; // @[dec_dec_ctl.scala 132:19] + assign io_out_low = _T_1736 & _T_194; // @[dec_dec_ctl.scala 134:14] + assign io_out_div = _T_1750 & _T_194; // @[dec_dec_ctl.scala 136:14] + assign io_out_rem = _T_1766 & _T_194; // @[dec_dec_ctl.scala 138:14] + assign io_out_fence = _T_11 & io_ins[3]; // @[dec_dec_ctl.scala 140:16] + assign io_out_fence_i = _T_1216 & io_ins[3]; // @[dec_dec_ctl.scala 142:18] + assign io_out_pm_alu = _T_3196 | _T_122; // @[dec_dec_ctl.scala 243:17] + assign io_out_legal = _T_4408 | _T_4421; // @[dec_dec_ctl.scala 248:16] +endmodule +module rvclkhdr( + input io_clk, + input io_en +); + wire clkhdr_Q; // @[lib.scala 334:26] + wire clkhdr_CK; // @[lib.scala 334:26] + wire clkhdr_EN; // @[lib.scala 334:26] + wire clkhdr_SE; // @[lib.scala 334:26] + gated_latch clkhdr ( // @[lib.scala 334:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign clkhdr_CK = io_clk; // @[lib.scala 336:18] + assign clkhdr_EN = io_en; // @[lib.scala 337:18] + assign clkhdr_SE = 1'h0; // @[lib.scala 338:18] +endmodule +module dec_decode_ctl( + input clock, + input reset, + output [1:0] io_decode_exu_dec_data_en, + output [1:0] io_decode_exu_dec_ctl_en, + output io_decode_exu_i0_ap_clz, + output io_decode_exu_i0_ap_ctz, + output io_decode_exu_i0_ap_pcnt, + output io_decode_exu_i0_ap_sext_b, + output io_decode_exu_i0_ap_sext_h, + output io_decode_exu_i0_ap_slo, + output io_decode_exu_i0_ap_sro, + output io_decode_exu_i0_ap_min, + output io_decode_exu_i0_ap_max, + output io_decode_exu_i0_ap_pack, + output io_decode_exu_i0_ap_packu, + output io_decode_exu_i0_ap_packh, + output io_decode_exu_i0_ap_rol, + output io_decode_exu_i0_ap_ror, + output io_decode_exu_i0_ap_grev, + output io_decode_exu_i0_ap_gorc, + output io_decode_exu_i0_ap_zbb, + output io_decode_exu_i0_ap_sbset, + output io_decode_exu_i0_ap_sbclr, + output io_decode_exu_i0_ap_sbinv, + output io_decode_exu_i0_ap_sbext, + output io_decode_exu_i0_ap_sh1add, + output io_decode_exu_i0_ap_sh2add, + output io_decode_exu_i0_ap_sh3add, + output io_decode_exu_i0_ap_zba, + output io_decode_exu_i0_ap_land, + output io_decode_exu_i0_ap_lor, + output io_decode_exu_i0_ap_lxor, + output io_decode_exu_i0_ap_sll, + output io_decode_exu_i0_ap_srl, + output io_decode_exu_i0_ap_sra, + output io_decode_exu_i0_ap_beq, + output io_decode_exu_i0_ap_bne, + output io_decode_exu_i0_ap_blt, + output io_decode_exu_i0_ap_bge, + output io_decode_exu_i0_ap_add, + output io_decode_exu_i0_ap_sub, + output io_decode_exu_i0_ap_slt, + output io_decode_exu_i0_ap_unsign, + output io_decode_exu_i0_ap_jal, + output io_decode_exu_i0_ap_predict_t, + output io_decode_exu_i0_ap_predict_nt, + output io_decode_exu_i0_ap_csr_write, + output io_decode_exu_i0_ap_csr_imm, + output io_decode_exu_dec_i0_predict_p_d_valid, + output io_decode_exu_dec_i0_predict_p_d_bits_pc4, + output [1:0] io_decode_exu_dec_i0_predict_p_d_bits_hist, + output [11:0] io_decode_exu_dec_i0_predict_p_d_bits_toffset, + output io_decode_exu_dec_i0_predict_p_d_bits_br_error, + output io_decode_exu_dec_i0_predict_p_d_bits_br_start_error, + output io_decode_exu_dec_i0_predict_p_d_bits_pcall, + output io_decode_exu_dec_i0_predict_p_d_bits_pja, + output io_decode_exu_dec_i0_predict_p_d_bits_way, + output io_decode_exu_dec_i0_predict_p_d_bits_pret, + output [30:0] io_decode_exu_dec_i0_predict_p_d_bits_prett, + output [7:0] io_decode_exu_i0_predict_fghr_d, + output [7:0] io_decode_exu_i0_predict_index_d, + output [4:0] io_decode_exu_i0_predict_btag_d, + output io_decode_exu_dec_i0_rs1_en_d, + output io_decode_exu_dec_i0_branch_d, + output io_decode_exu_dec_i0_rs2_en_d, + output [31:0] io_decode_exu_dec_i0_immed_d, + output [31:0] io_decode_exu_dec_i0_result_r, + output io_decode_exu_dec_qual_lsu_d, + output io_decode_exu_dec_i0_select_pc_d, + output [3:0] io_decode_exu_dec_i0_rs1_bypass_en_d, + output [3:0] io_decode_exu_dec_i0_rs2_bypass_en_d, + output io_decode_exu_mul_p_valid, + output io_decode_exu_mul_p_bits_rs1_sign, + output io_decode_exu_mul_p_bits_rs2_sign, + output io_decode_exu_mul_p_bits_low, + output io_decode_exu_mul_p_bits_bext, + output io_decode_exu_mul_p_bits_bdep, + output io_decode_exu_mul_p_bits_clmul, + output io_decode_exu_mul_p_bits_clmulh, + output io_decode_exu_mul_p_bits_clmulr, + output io_decode_exu_mul_p_bits_grev, + output io_decode_exu_mul_p_bits_gorc, + output io_decode_exu_mul_p_bits_shfl, + output io_decode_exu_mul_p_bits_unshfl, + output io_decode_exu_mul_p_bits_crc32_b, + output io_decode_exu_mul_p_bits_crc32_h, + output io_decode_exu_mul_p_bits_crc32_w, + output io_decode_exu_mul_p_bits_crc32c_b, + output io_decode_exu_mul_p_bits_crc32c_h, + output io_decode_exu_mul_p_bits_crc32c_w, + output io_decode_exu_mul_p_bits_bfp, + output [30:0] io_decode_exu_pred_correct_npc_x, + output io_decode_exu_dec_extint_stall, + input [31:0] io_decode_exu_exu_i0_result_x, + input [31:0] io_decode_exu_exu_csr_rs1_x, + output io_dec_alu_dec_i0_alu_decode_d, + output io_dec_alu_dec_csr_ren_d, + output [11:0] io_dec_alu_dec_i0_br_immed_d, + input [30:0] io_dec_alu_exu_i0_pc_x, + output io_dec_div_div_p_valid, + output io_dec_div_div_p_bits_unsign, + output io_dec_div_div_p_bits_rem, + output io_dec_div_dec_div_cancel, + input io_dctl_busbuff_lsu_nonblock_load_valid_m, + input [1:0] io_dctl_busbuff_lsu_nonblock_load_tag_m, + input io_dctl_busbuff_lsu_nonblock_load_inv_r, + input [1:0] io_dctl_busbuff_lsu_nonblock_load_inv_tag_r, + input io_dctl_busbuff_lsu_nonblock_load_data_valid, + input io_dctl_busbuff_lsu_nonblock_load_data_error, + input [1:0] io_dctl_busbuff_lsu_nonblock_load_data_tag, + input io_dctl_dma_dma_dccm_stall_any, + output io_dec_aln_dec_i0_decode_d, + input [15:0] io_dec_aln_ifu_i0_cinst, + input [31:0] io_dbg_dctl_dbg_cmd_wrdata, + input io_dec_tlu_trace_disable, + input io_dec_debug_valid_d, + input io_dec_tlu_flush_extint, + input io_dec_tlu_force_halt, + output [31:0] io_dec_i0_inst_wb, + output [30:0] io_dec_i0_pc_wb, + input [3:0] io_dec_i0_trigger_match_d, + input io_dec_tlu_wr_pause_r, + input io_dec_tlu_pipelining_disable, + input [3:0] io_lsu_trigger_match_m, + input io_lsu_pmu_misaligned_m, + input io_dec_tlu_debug_stall, + input io_dec_tlu_flush_leak_one_r, + input io_dec_debug_fence_d, + input io_dec_i0_icaf_d, + input io_dec_i0_icaf_second_d, + input [1:0] io_dec_i0_icaf_type_d, + input io_dec_i0_dbecc_d, + input io_dec_i0_brp_valid, + input [11:0] io_dec_i0_brp_bits_toffset, + input [1:0] io_dec_i0_brp_bits_hist, + input io_dec_i0_brp_bits_br_error, + input io_dec_i0_brp_bits_br_start_error, + input [30:0] io_dec_i0_brp_bits_prett, + input io_dec_i0_brp_bits_way, + input io_dec_i0_brp_bits_ret, + input [7:0] io_dec_i0_bp_index, + input [7:0] io_dec_i0_bp_fghr, + input [4:0] io_dec_i0_bp_btag, + input io_lsu_idle_any, + input io_lsu_load_stall_any, + input io_lsu_store_stall_any, + input io_exu_div_wren, + input io_dec_tlu_i0_kill_writeb_wb, + input io_dec_tlu_flush_lower_wb, + input io_dec_tlu_i0_kill_writeb_r, + input io_dec_tlu_flush_lower_r, + input io_dec_tlu_flush_pause_r, + input io_dec_tlu_presync_d, + input io_dec_tlu_postsync_d, + input io_dec_i0_pc4_d, + input [31:0] io_dec_csr_rddata_d, + input io_dec_csr_legal_d, + input [31:0] io_lsu_result_m, + input [31:0] io_lsu_result_corr_r, + input io_exu_flush_final, + input [31:0] io_dec_i0_instr_d, + input io_dec_ib0_valid_d, + input io_active_clk, + input io_free_l2clk, + input io_clk_override, + output [4:0] io_dec_i0_rs1_d, + output [4:0] io_dec_i0_rs2_d, + output [4:0] io_dec_i0_waddr_r, + output io_dec_i0_wen_r, + output [31:0] io_dec_i0_wdata_r, + output io_lsu_p_valid, + output io_lsu_p_bits_fast_int, + output io_lsu_p_bits_stack, + output io_lsu_p_bits_by, + output io_lsu_p_bits_half, + output io_lsu_p_bits_word, + output io_lsu_p_bits_load, + output io_lsu_p_bits_store, + output io_lsu_p_bits_unsign, + output io_lsu_p_bits_store_data_bypass_d, + output io_lsu_p_bits_load_ldst_bypass_d, + output [4:0] io_div_waddr_wb, + output io_dec_lsu_valid_raw_d, + output [11:0] io_dec_lsu_offset_d, + output io_dec_csr_wen_unq_d, + output io_dec_csr_any_unq_d, + output [11:0] io_dec_csr_rdaddr_d, + output io_dec_csr_wen_r, + output [11:0] io_dec_csr_wraddr_r, + output [31:0] io_dec_csr_wrdata_r, + output io_dec_csr_stall_int_ff, + output io_dec_tlu_i0_valid_r, + output io_dec_tlu_packet_r_legal, + output io_dec_tlu_packet_r_icaf, + output io_dec_tlu_packet_r_icaf_second, + output [1:0] io_dec_tlu_packet_r_icaf_type, + output io_dec_tlu_packet_r_fence_i, + output [3:0] io_dec_tlu_packet_r_i0trigger, + output [3:0] io_dec_tlu_packet_r_pmu_i0_itype, + output io_dec_tlu_packet_r_pmu_i0_br_unpred, + output io_dec_tlu_packet_r_pmu_divide, + output io_dec_tlu_packet_r_pmu_lsu_misaligned, + output [30:0] io_dec_tlu_i0_pc_r, + output [31:0] io_dec_illegal_inst, + output io_dec_pmu_instr_decoded, + output io_dec_pmu_decode_stall, + output io_dec_pmu_presync_stall, + output io_dec_pmu_postsync_stall, + output io_dec_nonblock_load_wen, + output [4:0] io_dec_nonblock_load_waddr, + output io_dec_pause_state, + output io_dec_pause_state_cg, + output io_dec_div_active +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [31:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; + reg [31:0] _RAND_75; + reg [31:0] _RAND_76; + reg [31:0] _RAND_77; + reg [31:0] _RAND_78; + reg [31:0] _RAND_79; + reg [31:0] _RAND_80; + reg [31:0] _RAND_81; + reg [31:0] _RAND_82; + reg [31:0] _RAND_83; + reg [31:0] _RAND_84; + reg [31:0] _RAND_85; + reg [31:0] _RAND_86; + reg [31:0] _RAND_87; + reg [31:0] _RAND_88; + reg [31:0] _RAND_89; +`endif // RANDOMIZE_REG_INIT + wire [31:0] i0_dec_io_ins; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_clz; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_ctz; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_pcnt; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sext_b; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sext_h; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_slo; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sro; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_min; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_max; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_pack; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_packu; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_packh; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_rol; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_ror; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_grev; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_gorc; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_zbb; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sbset; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sbclr; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sbinv; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sbext; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_zbs; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_bext; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_bdep; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_zbe; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_clmul; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_clmulh; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_clmulr; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_zbc; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_shfl; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_unshfl; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_zbp; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_crc32_b; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_crc32_h; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_crc32_w; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_crc32c_b; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_crc32c_h; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_crc32c_w; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_zbr; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_bfp; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_zbf; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sh1add; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sh2add; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sh3add; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_zba; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_alu; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_rd; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_pc; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_load; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_store; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_add; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sub; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_land; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_lor; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sll; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sra; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_srl; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_slt; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_beq; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_bne; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_bge; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_blt; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_jal; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_by; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_half; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_word; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_presync; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_mret; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_mul; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_low; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_div; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_rem; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_fence; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_legal; // @[dec_decode_ctl.scala 438:22] + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_4_io_en; // @[lib.scala 404:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_5_io_en; // @[lib.scala 404:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_6_io_en; // @[lib.scala 404:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_7_io_en; // @[lib.scala 404:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_8_io_en; // @[lib.scala 404:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_9_io_en; // @[lib.scala 404:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_10_io_en; // @[lib.scala 404:23] + reg leak1_i1_stall; // @[Reg.scala 27:20] + wire _T_367 = ~io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 445:73] + wire _T_368 = leak1_i1_stall & _T_367; // @[dec_decode_ctl.scala 445:71] + wire leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_368; // @[dec_decode_ctl.scala 445:53] + wire _T_2 = leak1_i1_stall_in ^ leak1_i1_stall; // @[lib.scala 448:21] + wire _T_3 = |_T_2; // @[lib.scala 448:29] + wire _T_370 = io_dec_aln_dec_i0_decode_d & leak1_i1_stall; // @[dec_decode_ctl.scala 447:53] + reg leak1_i0_stall; // @[Reg.scala 27:20] + wire _T_372 = leak1_i0_stall & _T_367; // @[dec_decode_ctl.scala 447:89] + wire leak1_i0_stall_in = _T_370 | _T_372; // @[dec_decode_ctl.scala 447:71] + wire _T_6 = leak1_i0_stall_in ^ leak1_i0_stall; // @[lib.scala 448:21] + wire _T_7 = |_T_6; // @[lib.scala 448:29] + reg _T_12; // @[Reg.scala 27:20] + wire _T_10 = io_dec_tlu_flush_extint ^ _T_12; // @[lib.scala 470:21] + wire _T_11 = |_T_10; // @[lib.scala 470:29] + reg pause_stall; // @[Reg.scala 27:20] + wire _T_514 = io_dec_tlu_wr_pause_r | pause_stall; // @[dec_decode_ctl.scala 559:44] + wire _T_507 = ~io_dec_tlu_flush_pause_r; // @[dec_decode_ctl.scala 558:49] + wire _T_508 = io_dec_tlu_flush_lower_r & _T_507; // @[dec_decode_ctl.scala 558:47] + reg [31:0] write_csr_data; // @[Reg.scala 27:20] + wire [31:0] _T_511 = {31'h0,write_csr_data[0]}; // @[Cat.scala 29:58] + wire _T_512 = write_csr_data == _T_511; // @[dec_decode_ctl.scala 558:109] + wire _T_513 = pause_stall & _T_512; // @[dec_decode_ctl.scala 558:91] + wire clear_pause = _T_508 | _T_513; // @[dec_decode_ctl.scala 558:76] + wire _T_515 = ~clear_pause; // @[dec_decode_ctl.scala 559:61] + wire pause_state_in = _T_514 & _T_515; // @[dec_decode_ctl.scala 559:59] + wire _T_14 = pause_state_in ^ pause_stall; // @[lib.scala 470:21] + wire _T_15 = |_T_14; // @[lib.scala 470:29] + reg tlu_wr_pause_r1; // @[Reg.scala 27:20] + wire _T_18 = io_dec_tlu_wr_pause_r ^ tlu_wr_pause_r1; // @[lib.scala 470:21] + wire _T_19 = |_T_18; // @[lib.scala 470:29] + reg tlu_wr_pause_r2; // @[Reg.scala 27:20] + wire _T_22 = tlu_wr_pause_r1 ^ tlu_wr_pause_r2; // @[lib.scala 448:21] + wire _T_23 = |_T_22; // @[lib.scala 448:29] + wire _T_50 = ~leak1_i1_stall; // @[dec_decode_ctl.scala 222:82] + wire _T_51 = io_dec_i0_brp_valid & _T_50; // @[dec_decode_ctl.scala 222:80] + wire i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[dec_decode_ctl.scala 220:43] + wire _T_52 = ~i0_icaf_d; // @[dec_decode_ctl.scala 222:96] + wire i0_brp_valid = _T_51 & _T_52; // @[dec_decode_ctl.scala 222:94] + wire i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_jal = i0_dec_io_out_jal; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire [19:0] i0_pcall_imm = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21]}; // @[Cat.scala 29:58] + wire _T_383 = i0_pcall_imm[19:12] == 8'hff; // @[dec_decode_ctl.scala 452:79] + wire _T_385 = i0_pcall_imm[19:12] == 8'h0; // @[dec_decode_ctl.scala 452:112] + wire i0_pcall_12b_offset = i0_pcall_imm[11] ? _T_383 : _T_385; // @[dec_decode_ctl.scala 452:33] + wire i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire _T_386 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[dec_decode_ctl.scala 453:47] + wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[dec_decode_ctl.scala 678:16] + wire _T_387 = i0r_rd == 5'h1; // @[dec_decode_ctl.scala 453:76] + wire _T_388 = i0r_rd == 5'h5; // @[dec_decode_ctl.scala 453:98] + wire _T_389 = _T_387 | _T_388; // @[dec_decode_ctl.scala 453:89] + wire i0_pcall_case = _T_386 & _T_389; // @[dec_decode_ctl.scala 453:65] + wire i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[dec_decode_ctl.scala 455:38] + wire _T_55 = i0_dp_raw_condbr | i0_pcall_raw; // @[dec_decode_ctl.scala 233:94] + wire _T_394 = ~_T_389; // @[dec_decode_ctl.scala 454:67] + wire i0_pja_case = _T_386 & _T_394; // @[dec_decode_ctl.scala 454:65] + wire i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[dec_decode_ctl.scala 457:38] + wire _T_56 = _T_55 | i0_pja_raw; // @[dec_decode_ctl.scala 233:109] + wire i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire _T_410 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[dec_decode_ctl.scala 461:37] + wire _T_411 = i0r_rd == 5'h0; // @[dec_decode_ctl.scala 461:65] + wire _T_412 = _T_410 & _T_411; // @[dec_decode_ctl.scala 461:55] + wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 676:16] + wire _T_413 = i0r_rs1 == 5'h1; // @[dec_decode_ctl.scala 461:89] + wire _T_414 = i0r_rs1 == 5'h5; // @[dec_decode_ctl.scala 461:111] + wire _T_415 = _T_413 | _T_414; // @[dec_decode_ctl.scala 461:101] + wire i0_pret_case = _T_412 & _T_415; // @[dec_decode_ctl.scala 461:79] + wire i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[dec_decode_ctl.scala 462:32] + wire _T_57 = _T_56 | i0_pret_raw; // @[dec_decode_ctl.scala 233:122] + wire _T_58 = ~_T_57; // @[dec_decode_ctl.scala 233:75] + wire _T_59 = i0_brp_valid & _T_58; // @[dec_decode_ctl.scala 233:73] + wire _T_68 = io_dec_i0_brp_bits_br_error | _T_59; // @[dec_decode_ctl.scala 238:89] + wire _T_61 = i0_brp_valid & io_dec_i0_brp_bits_hist[1]; // @[dec_decode_ctl.scala 236:74] + wire _T_399 = i0_pcall_raw | i0_pja_raw; // @[dec_decode_ctl.scala 459:41] + wire [11:0] _T_408 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[7],io_dec_i0_instr_d[30:25],io_dec_i0_instr_d[11:8]}; // @[Cat.scala 29:58] + wire [11:0] i0_br_offset = _T_399 ? i0_pcall_imm[11:0] : _T_408; // @[dec_decode_ctl.scala 459:26] + wire _T_62 = io_dec_i0_brp_bits_toffset != i0_br_offset; // @[dec_decode_ctl.scala 236:133] + wire _T_63 = _T_61 & _T_62; // @[dec_decode_ctl.scala 236:103] + wire _T_64 = ~i0_pret_raw; // @[dec_decode_ctl.scala 236:153] + wire _T_65 = _T_63 & _T_64; // @[dec_decode_ctl.scala 236:151] + wire _T_69 = _T_68 | _T_65; // @[dec_decode_ctl.scala 238:106] + wire _T_66 = io_dec_i0_brp_bits_ret ^ i0_pret_raw; // @[dec_decode_ctl.scala 237:100] + wire _T_67 = i0_brp_valid & _T_66; // @[dec_decode_ctl.scala 237:74] + wire _T_70 = _T_69 | _T_67; // @[dec_decode_ctl.scala 238:128] + wire _T_77 = _T_70 | io_dec_i0_brp_bits_br_start_error; // @[dec_decode_ctl.scala 243:74] + wire i0_br_error_all = _T_77 & _T_50; // @[dec_decode_ctl.scala 243:111] + wire _T_80 = i0_br_error_all | i0_icaf_d; // @[dec_decode_ctl.scala 280:25] + wire i0_dp_raw_legal = i0_dec_io_out_legal; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_legal = _T_80 | i0_dp_raw_legal; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_csr_read = _T_80 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_csr_write = _T_80 ? 1'h0 : i0_dp_raw_csr_write; // @[dec_decode_ctl.scala 280:50] + wire _T_429 = ~io_dec_debug_fence_d; // @[dec_decode_ctl.scala 519:42] + wire i0_csr_write = i0_dp_csr_write & _T_429; // @[dec_decode_ctl.scala 519:40] + wire any_csr_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 527:34] + wire _T_544 = ~any_csr_d; // @[dec_decode_ctl.scala 590:40] + wire _T_545 = _T_544 | io_dec_csr_legal_d; // @[dec_decode_ctl.scala 590:51] + wire i0_legal = i0_dp_legal & _T_545; // @[dec_decode_ctl.scala 590:37] + wire _T_563 = ~i0_legal; // @[dec_decode_ctl.scala 594:57] + wire shift_illegal = io_dec_aln_dec_i0_decode_d & _T_563; // @[dec_decode_ctl.scala 594:55] + reg illegal_lockout; // @[Reg.scala 27:20] + wire _T_566 = shift_illegal | illegal_lockout; // @[dec_decode_ctl.scala 597:40] + reg flush_final_r; // @[Reg.scala 27:20] + wire _T_567 = ~flush_final_r; // @[dec_decode_ctl.scala 597:61] + wire illegal_lockout_in = _T_566 & _T_567; // @[dec_decode_ctl.scala 597:59] + wire _T_26 = illegal_lockout_in ^ illegal_lockout; // @[lib.scala 448:21] + wire _T_27 = |_T_26; // @[lib.scala 448:29] + wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_postsync = _T_80 | i0_dp_raw_postsync; // @[dec_decode_ctl.scala 280:50] + wire _T_539 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[dec_decode_ctl.scala 586:36] + wire debug_fence_i = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[0]; // @[dec_decode_ctl.scala 578:48] + wire _T_540 = _T_539 | debug_fence_i; // @[dec_decode_ctl.scala 586:60] + wire _T_433 = ~i0_dp_csr_read; // @[dec_decode_ctl.scala 524:41] + wire i0_csr_write_only_d = i0_csr_write & _T_433; // @[dec_decode_ctl.scala 524:39] + wire _T_542 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[dec_decode_ctl.scala 586:112] + wire _T_543 = i0_csr_write_only_d & _T_542; // @[dec_decode_ctl.scala 586:99] + wire i0_postsync = _T_540 | _T_543; // @[dec_decode_ctl.scala 586:76] + wire _T_605 = i0_postsync | _T_563; // @[dec_decode_ctl.scala 628:62] + wire _T_606 = io_dec_aln_dec_i0_decode_d & _T_605; // @[dec_decode_ctl.scala 628:47] + reg postsync_stall; // @[Reg.scala 27:20] + reg x_d_valid; // @[Reg.scala 27:20] + wire _T_607 = postsync_stall & x_d_valid; // @[dec_decode_ctl.scala 628:96] + wire ps_stall_in = _T_606 | _T_607; // @[dec_decode_ctl.scala 628:77] + wire _T_30 = ps_stall_in ^ postsync_stall; // @[lib.scala 448:21] + wire _T_31 = |_T_30; // @[lib.scala 448:29] + reg [3:0] lsu_trigger_match_r; // @[Reg.scala 27:20] + wire [3:0] _T_33 = io_lsu_trigger_match_m ^ lsu_trigger_match_r; // @[lib.scala 448:21] + wire _T_34 = |_T_33; // @[lib.scala 448:29] + reg lsu_pmu_misaligned_r; // @[Reg.scala 27:20] + wire _T_36 = io_lsu_pmu_misaligned_m ^ lsu_pmu_misaligned_r; // @[lib.scala 470:21] + wire _T_37 = |_T_36; // @[lib.scala 470:29] + wire i0_legal_decode_d = io_dec_aln_dec_i0_decode_d & i0_legal; // @[dec_decode_ctl.scala 756:54] + wire i0_dp_raw_div = i0_dec_io_out_div; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_div = _T_80 ? 1'h0 : i0_dp_raw_div; // @[dec_decode_ctl.scala 280:50] + wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 843:55] + wire _T_934 = ~io_exu_div_wren; // @[dec_decode_ctl.scala 845:59] + wire _T_935 = io_dec_div_active & _T_934; // @[dec_decode_ctl.scala 845:57] + reg x_d_bits_i0div; // @[Reg.scala 27:20] + wire _T_918 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 833:48] + reg [4:0] x_d_bits_i0rd; // @[Reg.scala 27:20] + wire _T_919 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 833:77] + wire _T_920 = _T_918 & _T_919; // @[dec_decode_ctl.scala 833:60] + wire _T_922 = _T_918 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 834:33] + wire _T_923 = _T_920 | _T_922; // @[dec_decode_ctl.scala 833:94] + reg r_d_bits_i0div; // @[Reg.scala 27:20] + reg r_d_valid; // @[Reg.scala 27:20] + wire _T_924 = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 835:21] + wire _T_925 = _T_924 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 835:33] + wire _T_926 = _T_925 & io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 835:60] + wire div_flush = _T_923 | _T_926; // @[dec_decode_ctl.scala 834:62] + wire _T_927 = io_dec_div_active & div_flush; // @[dec_decode_ctl.scala 839:51] + wire div_e1_to_r = _T_918 | _T_924; // @[dec_decode_ctl.scala 831:58] + wire _T_928 = ~div_e1_to_r; // @[dec_decode_ctl.scala 840:26] + wire _T_929 = io_dec_div_active & _T_928; // @[dec_decode_ctl.scala 840:24] + reg [4:0] r_d_bits_i0rd; // @[Reg.scala 27:20] + wire _T_930 = r_d_bits_i0rd == io_div_waddr_wb; // @[dec_decode_ctl.scala 840:56] + wire _T_931 = _T_929 & _T_930; // @[dec_decode_ctl.scala 840:39] + reg r_d_bits_i0v; // @[Reg.scala 27:20] + wire _T_857 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 798:51] + wire r_d_in_bits_i0v = r_d_bits_i0v & _T_857; // @[dec_decode_ctl.scala 798:49] + wire _T_868 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 806:47] + wire i0_wen_r = r_d_in_bits_i0v & _T_868; // @[dec_decode_ctl.scala 806:45] + wire _T_932 = _T_931 & i0_wen_r; // @[dec_decode_ctl.scala 840:77] + wire nonblock_div_cancel = _T_927 | _T_932; // @[dec_decode_ctl.scala 839:65] + wire _T_936 = ~nonblock_div_cancel; // @[dec_decode_ctl.scala 845:78] + wire _T_937 = _T_935 & _T_936; // @[dec_decode_ctl.scala 845:76] + wire div_active_in = i0_div_decode_d | _T_937; // @[dec_decode_ctl.scala 845:36] + reg _T_42; // @[Reg.scala 27:20] + wire _T_40 = div_active_in ^ _T_42; // @[lib.scala 470:21] + wire _T_41 = |_T_40; // @[lib.scala 470:29] + wire _T_44 = io_exu_flush_final ^ flush_final_r; // @[lib.scala 470:21] + wire _T_45 = |_T_44; // @[lib.scala 470:29] + reg debug_valid_x; // @[Reg.scala 27:20] + wire _T_47 = io_dec_debug_valid_d ^ debug_valid_x; // @[lib.scala 470:21] + wire _T_48 = |_T_47; // @[lib.scala 470:29] + wire _T_71 = _T_70 & i0_legal_decode_d; // @[dec_decode_ctl.scala 239:74] + wire _T_74 = io_dec_i0_brp_bits_br_start_error & i0_legal_decode_d; // @[dec_decode_ctl.scala 240:96] + wire i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_pm_alu = _T_80 ? 1'h0 : i0_dp_raw_pm_alu; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_fence_i = _T_80 ? 1'h0 : i0_dp_raw_fence_i; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_fence = i0_dec_io_out_fence; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_fence = _T_80 ? 1'h0 : i0_dp_raw_fence; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_rem = i0_dec_io_out_rem; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_low = i0_dec_io_out_low; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_mul = i0_dec_io_out_mul; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_mul = _T_80 ? 1'h0 : i0_dp_raw_mul; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_mret = i0_dec_io_out_mret; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_mret = _T_80 ? 1'h0 : i0_dp_raw_mret; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_ecall = _T_80 ? 1'h0 : i0_dp_raw_ecall; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_ebreak = _T_80 ? 1'h0 : i0_dp_raw_ebreak; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_presync = i0_dec_io_out_presync; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_presync = _T_80 ? 1'h0 : i0_dp_raw_presync; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_csr_imm = _T_80 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_csr_set = _T_80 ? 1'h0 : i0_dp_raw_csr_set; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_csr_clr = _T_80 ? 1'h0 : i0_dp_raw_csr_clr; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_word = i0_dec_io_out_word; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_word = _T_80 ? 1'h0 : i0_dp_raw_word; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_half = i0_dec_io_out_half; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_half = _T_80 ? 1'h0 : i0_dp_raw_half; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_by = i0_dec_io_out_by; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_by = _T_80 ? 1'h0 : i0_dp_raw_by; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_jal = _T_80 ? 1'h0 : i0_dp_raw_jal; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_blt = i0_dec_io_out_blt; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_bge = i0_dec_io_out_bge; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_bne = i0_dec_io_out_bne; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_beq = i0_dec_io_out_beq; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_condbr = _T_80 ? 1'h0 : i0_dp_raw_condbr; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_unsign = _T_80 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_slt = i0_dec_io_out_slt; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_srl = i0_dec_io_out_srl; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sra = i0_dec_io_out_sra; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sll = i0_dec_io_out_sll; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_lor = i0_dec_io_out_lor; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_land = i0_dec_io_out_land; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sub = i0_dec_io_out_sub; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_add = i0_dec_io_out_add; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_lsu = _T_80 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_store = i0_dec_io_out_store; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_store = _T_80 ? 1'h0 : i0_dp_raw_store; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_load = i0_dec_io_out_load; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_load = _T_80 ? 1'h0 : i0_dp_raw_load; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_pc = i0_dec_io_out_pc; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_imm20 = _T_80 ? 1'h0 : i0_dp_raw_imm20; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_shimm5 = _T_80 ? 1'h0 : i0_dp_raw_shimm5; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_rd = i0_dec_io_out_rd; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_rd = _T_80 ? 1'h0 : i0_dp_raw_rd; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_imm12 = _T_80 ? 1'h0 : i0_dp_raw_imm12; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_rs2 = _T_80 | i0_dp_raw_rs2; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_rs1 = _T_80 | i0_dp_raw_rs1; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_alu = i0_dec_io_out_alu; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_alu = _T_80 | i0_dp_raw_alu; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_zba = i0_dec_io_out_zba; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_zba = _T_80 ? 1'h0 : i0_dp_raw_zba; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_sh3add = i0_dec_io_out_sh3add; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sh2add = i0_dec_io_out_sh2add; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sh1add = i0_dec_io_out_sh1add; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_zbf = i0_dec_io_out_zbf; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_zbf = _T_80 ? 1'h0 : i0_dp_raw_zbf; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_bfp = i0_dec_io_out_bfp; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_zbr = i0_dec_io_out_zbr; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_zbr = _T_80 ? 1'h0 : i0_dp_raw_zbr; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_crc32c_w = i0_dec_io_out_crc32c_w; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_crc32c_h = i0_dec_io_out_crc32c_h; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_crc32c_b = i0_dec_io_out_crc32c_b; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_crc32_w = i0_dec_io_out_crc32_w; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_crc32_h = i0_dec_io_out_crc32_h; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_crc32_b = i0_dec_io_out_crc32_b; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_zbp = i0_dec_io_out_zbp; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_zbp = _T_80 ? 1'h0 : i0_dp_raw_zbp; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_unshfl = i0_dec_io_out_unshfl; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_shfl = i0_dec_io_out_shfl; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_zbc = i0_dec_io_out_zbc; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_zbc = _T_80 ? 1'h0 : i0_dp_raw_zbc; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_clmulr = i0_dec_io_out_clmulr; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_clmulh = i0_dec_io_out_clmulh; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_clmul = i0_dec_io_out_clmul; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_zbe = i0_dec_io_out_zbe; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_zbe = _T_80 ? 1'h0 : i0_dp_raw_zbe; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_bdep = i0_dec_io_out_bdep; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_bext = i0_dec_io_out_bext; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_zbs = i0_dec_io_out_zbs; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_zbs = _T_80 ? 1'h0 : i0_dp_raw_zbs; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_sbext = i0_dec_io_out_sbext; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sbinv = i0_dec_io_out_sbinv; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sbclr = i0_dec_io_out_sbclr; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sbset = i0_dec_io_out_sbset; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_zbb = i0_dec_io_out_zbb; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_zbb = _T_80 ? 1'h0 : i0_dp_raw_zbb; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_gorc = i0_dec_io_out_gorc; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_grev = i0_dec_io_out_grev; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_ror = i0_dec_io_out_ror; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_rol = i0_dec_io_out_rol; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_packh = i0_dec_io_out_packh; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_packu = i0_dec_io_out_packu; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_pack = i0_dec_io_out_pack; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_max = i0_dec_io_out_max; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_min = i0_dec_io_out_min; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sro = i0_dec_io_out_sro; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_slo = i0_dec_io_out_slo; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sext_h = i0_dec_io_out_sext_h; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sext_b = i0_dec_io_out_sext_b; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_pcnt = i0_dec_io_out_pcnt; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_ctz = i0_dec_io_out_ctz; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_clz = i0_dec_io_out_clz; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 456:38] + wire _T_83 = i0_dp_condbr | i0_pcall; // @[dec_decode_ctl.scala 294:54] + wire i0_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 458:38] + wire _T_84 = _T_83 | i0_pja; // @[dec_decode_ctl.scala 294:65] + wire i0_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 463:32] + wire i0_predict_br = _T_84 | i0_pret; // @[dec_decode_ctl.scala 294:74] + wire _T_86 = io_dec_i0_brp_bits_hist[1] & i0_brp_valid; // @[dec_decode_ctl.scala 295:69] + wire _T_87 = ~_T_86; // @[dec_decode_ctl.scala 295:40] + wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 297:40] + wire cam_data_reset = io_dctl_busbuff_lsu_nonblock_load_data_valid | io_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec_decode_ctl.scala 356:76] + reg [2:0] cam_raw_0_bits_tag; // @[Reg.scala 27:20] + wire [2:0] _GEN_256 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_data_tag}; // @[dec_decode_ctl.scala 367:67] + wire _T_133 = _GEN_256 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 367:67] + wire _T_134 = cam_data_reset & _T_133; // @[dec_decode_ctl.scala 367:45] + reg cam_raw_0_valid; // @[Reg.scala 27:20] + wire cam_data_reset_val_0 = _T_134 & cam_raw_0_valid; // @[dec_decode_ctl.scala 367:88] + wire cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[dec_decode_ctl.scala 371:39] + wire _T_90 = ~cam_0_valid; // @[dec_decode_ctl.scala 348:78] + reg [2:0] cam_raw_1_bits_tag; // @[Reg.scala 27:20] + wire _T_169 = _GEN_256 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 367:67] + wire _T_170 = cam_data_reset & _T_169; // @[dec_decode_ctl.scala 367:45] + reg cam_raw_1_valid; // @[Reg.scala 27:20] + wire cam_data_reset_val_1 = _T_170 & cam_raw_1_valid; // @[dec_decode_ctl.scala 367:88] + wire cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[dec_decode_ctl.scala 371:39] + wire _T_93 = ~cam_1_valid; // @[dec_decode_ctl.scala 348:78] + wire _T_96 = cam_0_valid & _T_93; // @[dec_decode_ctl.scala 348:126] + wire [1:0] _T_98 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 1'h0}; // @[dec_decode_ctl.scala 348:158] + reg [2:0] cam_raw_2_bits_tag; // @[Reg.scala 27:20] + wire _T_205 = _GEN_256 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 367:67] + wire _T_206 = cam_data_reset & _T_205; // @[dec_decode_ctl.scala 367:45] + reg cam_raw_2_valid; // @[Reg.scala 27:20] + wire cam_data_reset_val_2 = _T_206 & cam_raw_2_valid; // @[dec_decode_ctl.scala 367:88] + wire cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[dec_decode_ctl.scala 371:39] + wire _T_99 = ~cam_2_valid; // @[dec_decode_ctl.scala 348:78] + wire _T_102 = cam_0_valid & cam_1_valid; // @[dec_decode_ctl.scala 348:126] + wire _T_105 = _T_102 & _T_99; // @[dec_decode_ctl.scala 348:126] + wire [2:0] _T_107 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 2'h0}; // @[dec_decode_ctl.scala 348:158] + reg [2:0] cam_raw_3_bits_tag; // @[Reg.scala 27:20] + wire _T_241 = _GEN_256 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 367:67] + wire _T_242 = cam_data_reset & _T_241; // @[dec_decode_ctl.scala 367:45] + reg cam_raw_3_valid; // @[Reg.scala 27:20] + wire cam_data_reset_val_3 = _T_242 & cam_raw_3_valid; // @[dec_decode_ctl.scala 367:88] + wire cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[dec_decode_ctl.scala 371:39] + wire _T_108 = ~cam_3_valid; // @[dec_decode_ctl.scala 348:78] + wire _T_114 = _T_102 & cam_2_valid; // @[dec_decode_ctl.scala 348:126] + wire _T_117 = _T_114 & _T_108; // @[dec_decode_ctl.scala 348:126] + wire [3:0] _T_119 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 3'h0}; // @[dec_decode_ctl.scala 348:158] + wire _T_120 = _T_90 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[Mux.scala 27:72] + wire [1:0] _T_121 = _T_96 ? _T_98 : 2'h0; // @[Mux.scala 27:72] + wire [2:0] _T_122 = _T_105 ? _T_107 : 3'h0; // @[Mux.scala 27:72] + wire [3:0] _T_123 = _T_117 ? _T_119 : 4'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_260 = {{1'd0}, _T_120}; // @[Mux.scala 27:72] + wire [1:0] _T_124 = _GEN_260 | _T_121; // @[Mux.scala 27:72] + wire [2:0] _GEN_261 = {{1'd0}, _T_124}; // @[Mux.scala 27:72] + wire [2:0] _T_125 = _GEN_261 | _T_122; // @[Mux.scala 27:72] + wire [3:0] _GEN_262 = {{1'd0}, _T_125}; // @[Mux.scala 27:72] + wire [3:0] cam_wen = _GEN_262 | _T_123; // @[Mux.scala 27:72] + reg x_d_bits_i0load; // @[Reg.scala 27:20] + wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[dec_decode_ctl.scala 359:31] + reg [2:0] _T_815; // @[dec_decode_ctl.scala 764:80] + wire [3:0] i0_pipe_en = {io_dec_aln_dec_i0_decode_d,_T_815}; // @[Cat.scala 29:58] + wire _T_821 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 767:49] + wire i0_r_ctl_en = _T_821 | io_clk_override; // @[dec_decode_ctl.scala 767:53] + reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20] + reg r_d_bits_i0load; // @[Reg.scala 27:20] + wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[dec_decode_ctl.scala 364:56] + wire [2:0] _GEN_263 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_inv_tag_r}; // @[dec_decode_ctl.scala 366:66] + wire _T_130 = _GEN_263 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 366:66] + wire _T_131 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_130; // @[dec_decode_ctl.scala 366:45] + wire cam_inv_reset_val_0 = _T_131 & cam_0_valid; // @[dec_decode_ctl.scala 366:87] + reg [4:0] cam_raw_0_bits_rd; // @[Reg.scala 27:20] + wire _T_142 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 379:85] + wire _T_143 = i0_wen_r & _T_142; // @[dec_decode_ctl.scala 379:64] + reg cam_raw_0_bits_wb; // @[Reg.scala 27:20] + wire _T_145 = _T_143 & cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 379:105] + wire _T_146 = cam_inv_reset_val_0 | _T_145; // @[dec_decode_ctl.scala 379:44] + wire _GEN_110 = _T_146 ? 1'h0 : cam_0_valid; // @[dec_decode_ctl.scala 379:131] + wire [4:0] _GEN_111 = _T_146 ? 5'h0 : cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 379:131] + wire [2:0] _GEN_112 = _T_146 ? 3'h0 : cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 379:131] + wire _GEN_113 = _T_146 ? 1'h0 : cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 379:131] + wire _GEN_114 = cam_wen[0] | _GEN_110; // @[dec_decode_ctl.scala 374:28] + wire _GEN_115 = cam_wen[0] ? 1'h0 : _GEN_113; // @[dec_decode_ctl.scala 374:28] + wire [2:0] cam_in_0_bits_tag = cam_wen[0] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_112; // @[dec_decode_ctl.scala 374:28] + wire [4:0] cam_in_0_bits_rd = cam_wen[0] ? nonblock_load_rd : _GEN_111; // @[dec_decode_ctl.scala 374:28] + wire _T_149 = nonblock_load_valid_m_delay & _T_130; // @[dec_decode_ctl.scala 384:44] + wire _T_151 = _T_149 & cam_0_valid; // @[dec_decode_ctl.scala 384:113] + wire cam_in_0_bits_wb = _T_151 | _GEN_115; // @[dec_decode_ctl.scala 384:135] + wire cam_in_0_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_114; // @[dec_decode_ctl.scala 388:32] + wire [8:0] _T_154 = {cam_in_0_bits_wb,cam_in_0_bits_tag,cam_in_0_bits_rd}; // @[lib.scala 494:61] + wire [8:0] _T_156 = {cam_raw_0_bits_wb,cam_raw_0_bits_tag,cam_raw_0_bits_rd}; // @[lib.scala 494:74] + wire [8:0] _T_157 = _T_154 ^ _T_156; // @[lib.scala 494:68] + wire _T_158 = |_T_157; // @[lib.scala 494:82] + wire _T_159 = cam_in_0_valid ^ cam_raw_0_valid; // @[lib.scala 494:68] + wire _T_160 = |_T_159; // @[lib.scala 494:82] + wire _T_161 = _T_158 | _T_160; // @[lib.scala 494:97] + wire nonblock_load_write_0 = _T_133 & cam_raw_0_valid; // @[dec_decode_ctl.scala 393:71] + wire _T_166 = _GEN_263 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 366:66] + wire _T_167 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_166; // @[dec_decode_ctl.scala 366:45] + wire cam_inv_reset_val_1 = _T_167 & cam_1_valid; // @[dec_decode_ctl.scala 366:87] + reg [4:0] cam_raw_1_bits_rd; // @[Reg.scala 27:20] + wire _T_178 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 379:85] + wire _T_179 = i0_wen_r & _T_178; // @[dec_decode_ctl.scala 379:64] + reg cam_raw_1_bits_wb; // @[Reg.scala 27:20] + wire _T_181 = _T_179 & cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 379:105] + wire _T_182 = cam_inv_reset_val_1 | _T_181; // @[dec_decode_ctl.scala 379:44] + wire _GEN_125 = _T_182 ? 1'h0 : cam_1_valid; // @[dec_decode_ctl.scala 379:131] + wire [4:0] _GEN_126 = _T_182 ? 5'h0 : cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 379:131] + wire [2:0] _GEN_127 = _T_182 ? 3'h0 : cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 379:131] + wire _GEN_128 = _T_182 ? 1'h0 : cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 379:131] + wire _GEN_129 = cam_wen[1] | _GEN_125; // @[dec_decode_ctl.scala 374:28] + wire _GEN_130 = cam_wen[1] ? 1'h0 : _GEN_128; // @[dec_decode_ctl.scala 374:28] + wire [2:0] cam_in_1_bits_tag = cam_wen[1] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_127; // @[dec_decode_ctl.scala 374:28] + wire [4:0] cam_in_1_bits_rd = cam_wen[1] ? nonblock_load_rd : _GEN_126; // @[dec_decode_ctl.scala 374:28] + wire _T_185 = nonblock_load_valid_m_delay & _T_166; // @[dec_decode_ctl.scala 384:44] + wire _T_187 = _T_185 & cam_1_valid; // @[dec_decode_ctl.scala 384:113] + wire cam_in_1_bits_wb = _T_187 | _GEN_130; // @[dec_decode_ctl.scala 384:135] + wire cam_in_1_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_129; // @[dec_decode_ctl.scala 388:32] + wire [8:0] _T_190 = {cam_in_1_bits_wb,cam_in_1_bits_tag,cam_in_1_bits_rd}; // @[lib.scala 494:61] + wire [8:0] _T_192 = {cam_raw_1_bits_wb,cam_raw_1_bits_tag,cam_raw_1_bits_rd}; // @[lib.scala 494:74] + wire [8:0] _T_193 = _T_190 ^ _T_192; // @[lib.scala 494:68] + wire _T_194 = |_T_193; // @[lib.scala 494:82] + wire _T_195 = cam_in_1_valid ^ cam_raw_1_valid; // @[lib.scala 494:68] + wire _T_196 = |_T_195; // @[lib.scala 494:82] + wire _T_197 = _T_194 | _T_196; // @[lib.scala 494:97] + wire nonblock_load_write_1 = _T_169 & cam_raw_1_valid; // @[dec_decode_ctl.scala 393:71] + wire _T_202 = _GEN_263 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 366:66] + wire _T_203 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_202; // @[dec_decode_ctl.scala 366:45] + wire cam_inv_reset_val_2 = _T_203 & cam_2_valid; // @[dec_decode_ctl.scala 366:87] + reg [4:0] cam_raw_2_bits_rd; // @[Reg.scala 27:20] + wire _T_214 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 379:85] + wire _T_215 = i0_wen_r & _T_214; // @[dec_decode_ctl.scala 379:64] + reg cam_raw_2_bits_wb; // @[Reg.scala 27:20] + wire _T_217 = _T_215 & cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 379:105] + wire _T_218 = cam_inv_reset_val_2 | _T_217; // @[dec_decode_ctl.scala 379:44] + wire _GEN_140 = _T_218 ? 1'h0 : cam_2_valid; // @[dec_decode_ctl.scala 379:131] + wire [4:0] _GEN_141 = _T_218 ? 5'h0 : cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 379:131] + wire [2:0] _GEN_142 = _T_218 ? 3'h0 : cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 379:131] + wire _GEN_143 = _T_218 ? 1'h0 : cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 379:131] + wire _GEN_144 = cam_wen[2] | _GEN_140; // @[dec_decode_ctl.scala 374:28] + wire _GEN_145 = cam_wen[2] ? 1'h0 : _GEN_143; // @[dec_decode_ctl.scala 374:28] + wire [2:0] cam_in_2_bits_tag = cam_wen[2] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_142; // @[dec_decode_ctl.scala 374:28] + wire [4:0] cam_in_2_bits_rd = cam_wen[2] ? nonblock_load_rd : _GEN_141; // @[dec_decode_ctl.scala 374:28] + wire _T_221 = nonblock_load_valid_m_delay & _T_202; // @[dec_decode_ctl.scala 384:44] + wire _T_223 = _T_221 & cam_2_valid; // @[dec_decode_ctl.scala 384:113] + wire cam_in_2_bits_wb = _T_223 | _GEN_145; // @[dec_decode_ctl.scala 384:135] + wire cam_in_2_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_144; // @[dec_decode_ctl.scala 388:32] + wire [8:0] _T_226 = {cam_in_2_bits_wb,cam_in_2_bits_tag,cam_in_2_bits_rd}; // @[lib.scala 494:61] + wire [8:0] _T_228 = {cam_raw_2_bits_wb,cam_raw_2_bits_tag,cam_raw_2_bits_rd}; // @[lib.scala 494:74] + wire [8:0] _T_229 = _T_226 ^ _T_228; // @[lib.scala 494:68] + wire _T_230 = |_T_229; // @[lib.scala 494:82] + wire _T_231 = cam_in_2_valid ^ cam_raw_2_valid; // @[lib.scala 494:68] + wire _T_232 = |_T_231; // @[lib.scala 494:82] + wire _T_233 = _T_230 | _T_232; // @[lib.scala 494:97] + wire nonblock_load_write_2 = _T_205 & cam_raw_2_valid; // @[dec_decode_ctl.scala 393:71] + wire _T_238 = _GEN_263 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 366:66] + wire _T_239 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_238; // @[dec_decode_ctl.scala 366:45] + wire cam_inv_reset_val_3 = _T_239 & cam_3_valid; // @[dec_decode_ctl.scala 366:87] + reg [4:0] cam_raw_3_bits_rd; // @[Reg.scala 27:20] + wire _T_250 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 379:85] + wire _T_251 = i0_wen_r & _T_250; // @[dec_decode_ctl.scala 379:64] + reg cam_raw_3_bits_wb; // @[Reg.scala 27:20] + wire _T_253 = _T_251 & cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 379:105] + wire _T_254 = cam_inv_reset_val_3 | _T_253; // @[dec_decode_ctl.scala 379:44] + wire _GEN_155 = _T_254 ? 1'h0 : cam_3_valid; // @[dec_decode_ctl.scala 379:131] + wire [4:0] _GEN_156 = _T_254 ? 5'h0 : cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 379:131] + wire [2:0] _GEN_157 = _T_254 ? 3'h0 : cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 379:131] + wire _GEN_158 = _T_254 ? 1'h0 : cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 379:131] + wire _GEN_159 = cam_wen[3] | _GEN_155; // @[dec_decode_ctl.scala 374:28] + wire _GEN_160 = cam_wen[3] ? 1'h0 : _GEN_158; // @[dec_decode_ctl.scala 374:28] + wire [2:0] cam_in_3_bits_tag = cam_wen[3] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_157; // @[dec_decode_ctl.scala 374:28] + wire [4:0] cam_in_3_bits_rd = cam_wen[3] ? nonblock_load_rd : _GEN_156; // @[dec_decode_ctl.scala 374:28] + wire _T_257 = nonblock_load_valid_m_delay & _T_238; // @[dec_decode_ctl.scala 384:44] + wire _T_259 = _T_257 & cam_3_valid; // @[dec_decode_ctl.scala 384:113] + wire cam_in_3_bits_wb = _T_259 | _GEN_160; // @[dec_decode_ctl.scala 384:135] + wire cam_in_3_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_159; // @[dec_decode_ctl.scala 388:32] + wire [8:0] _T_262 = {cam_in_3_bits_wb,cam_in_3_bits_tag,cam_in_3_bits_rd}; // @[lib.scala 494:61] + wire [8:0] _T_264 = {cam_raw_3_bits_wb,cam_raw_3_bits_tag,cam_raw_3_bits_rd}; // @[lib.scala 494:74] + wire [8:0] _T_265 = _T_262 ^ _T_264; // @[lib.scala 494:68] + wire _T_266 = |_T_265; // @[lib.scala 494:82] + wire _T_267 = cam_in_3_valid ^ cam_raw_3_valid; // @[lib.scala 494:68] + wire _T_268 = |_T_267; // @[lib.scala 494:82] + wire _T_269 = _T_266 | _T_268; // @[lib.scala 494:97] + wire nonblock_load_write_3 = _T_241 & cam_raw_3_valid; // @[dec_decode_ctl.scala 393:71] + wire _T_274 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[dec_decode_ctl.scala 398:49] + wire nonblock_load_cancel = _T_274 & i0_wen_r; // @[dec_decode_ctl.scala 398:81] + wire _T_275 = nonblock_load_write_0 | nonblock_load_write_1; // @[dec_decode_ctl.scala 399:108] + wire _T_276 = _T_275 | nonblock_load_write_2; // @[dec_decode_ctl.scala 399:108] + wire _T_277 = _T_276 | nonblock_load_write_3; // @[dec_decode_ctl.scala 399:108] + wire _T_279 = io_dctl_busbuff_lsu_nonblock_load_data_valid & _T_277; // @[dec_decode_ctl.scala 399:77] + wire _T_280 = ~nonblock_load_cancel; // @[dec_decode_ctl.scala 399:122] + wire _T_282 = nonblock_load_rd == i0r_rs1; // @[dec_decode_ctl.scala 400:54] + wire _T_283 = _T_282 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 400:66] + wire _T_284 = _T_283 & io_decode_exu_dec_i0_rs1_en_d; // @[dec_decode_ctl.scala 400:110] + wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 677:16] + wire _T_285 = nonblock_load_rd == i0r_rs2; // @[dec_decode_ctl.scala 400:161] + wire _T_286 = _T_285 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 400:173] + wire _T_287 = _T_286 & io_decode_exu_dec_i0_rs2_en_d; // @[dec_decode_ctl.scala 400:217] + wire i0_nonblock_boundary_stall = _T_284 | _T_287; // @[dec_decode_ctl.scala 400:142] + wire [4:0] _T_289 = nonblock_load_write_0 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_290 = _T_289 & cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 404:88] + wire _T_291 = io_decode_exu_dec_i0_rs1_en_d & cam_0_valid; // @[dec_decode_ctl.scala 404:137] + wire _T_292 = cam_raw_0_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 404:170] + wire _T_293 = _T_291 & _T_292; // @[dec_decode_ctl.scala 404:152] + wire _T_294 = io_decode_exu_dec_i0_rs2_en_d & cam_0_valid; // @[dec_decode_ctl.scala 404:214] + wire _T_295 = cam_raw_0_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 404:247] + wire _T_296 = _T_294 & _T_295; // @[dec_decode_ctl.scala 404:229] + wire [4:0] _T_298 = nonblock_load_write_1 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_299 = _T_298 & cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 404:88] + wire _T_300 = io_decode_exu_dec_i0_rs1_en_d & cam_1_valid; // @[dec_decode_ctl.scala 404:137] + wire _T_301 = cam_raw_1_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 404:170] + wire _T_302 = _T_300 & _T_301; // @[dec_decode_ctl.scala 404:152] + wire _T_303 = io_decode_exu_dec_i0_rs2_en_d & cam_1_valid; // @[dec_decode_ctl.scala 404:214] + wire _T_304 = cam_raw_1_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 404:247] + wire _T_305 = _T_303 & _T_304; // @[dec_decode_ctl.scala 404:229] + wire [4:0] _T_307 = nonblock_load_write_2 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_308 = _T_307 & cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 404:88] + wire _T_309 = io_decode_exu_dec_i0_rs1_en_d & cam_2_valid; // @[dec_decode_ctl.scala 404:137] + wire _T_310 = cam_raw_2_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 404:170] + wire _T_311 = _T_309 & _T_310; // @[dec_decode_ctl.scala 404:152] + wire _T_312 = io_decode_exu_dec_i0_rs2_en_d & cam_2_valid; // @[dec_decode_ctl.scala 404:214] + wire _T_313 = cam_raw_2_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 404:247] + wire _T_314 = _T_312 & _T_313; // @[dec_decode_ctl.scala 404:229] + wire [4:0] _T_316 = nonblock_load_write_3 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_317 = _T_316 & cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 404:88] + wire _T_318 = io_decode_exu_dec_i0_rs1_en_d & cam_3_valid; // @[dec_decode_ctl.scala 404:137] + wire _T_319 = cam_raw_3_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 404:170] + wire _T_320 = _T_318 & _T_319; // @[dec_decode_ctl.scala 404:152] + wire _T_321 = io_decode_exu_dec_i0_rs2_en_d & cam_3_valid; // @[dec_decode_ctl.scala 404:214] + wire _T_322 = cam_raw_3_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 404:247] + wire _T_323 = _T_321 & _T_322; // @[dec_decode_ctl.scala 404:229] + wire [4:0] _T_324 = _T_290 | _T_299; // @[dec_decode_ctl.scala 405:69] + wire [4:0] _T_325 = _T_324 | _T_308; // @[dec_decode_ctl.scala 405:69] + wire _T_326 = _T_293 | _T_302; // @[dec_decode_ctl.scala 405:102] + wire _T_327 = _T_326 | _T_311; // @[dec_decode_ctl.scala 405:102] + wire ld_stall_1 = _T_327 | _T_320; // @[dec_decode_ctl.scala 405:102] + wire _T_328 = _T_296 | _T_305; // @[dec_decode_ctl.scala 405:134] + wire _T_329 = _T_328 | _T_314; // @[dec_decode_ctl.scala 405:134] + wire ld_stall_2 = _T_329 | _T_323; // @[dec_decode_ctl.scala 405:134] + wire _T_330 = ld_stall_1 | ld_stall_2; // @[dec_decode_ctl.scala 407:38] + wire i0_nonblock_load_stall = _T_330 | i0_nonblock_boundary_stall; // @[dec_decode_ctl.scala 407:51] + wire _T_332 = ~i0_predict_br; // @[dec_decode_ctl.scala 416:34] + wire i0_br_unpred = i0_dp_jal & _T_332; // @[dec_decode_ctl.scala 416:32] + wire [3:0] _T_334 = i0_legal_decode_d ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[dec_decode_ctl.scala 517:36] + wire _T_335 = csr_read & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 428:16] + wire _T_337 = ~csr_read; // @[dec_decode_ctl.scala 429:6] + wire _T_338 = _T_337 & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 429:16] + wire _T_340 = ~io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 430:18] + wire _T_341 = csr_read & _T_340; // @[dec_decode_ctl.scala 430:16] + wire _T_343 = i0_dp_zbb | i0_dp_zbs; // @[dec_decode_ctl.scala 431:16] + wire _T_344 = _T_343 | i0_dp_zbe; // @[dec_decode_ctl.scala 431:28] + wire _T_345 = _T_344 | i0_dp_zbc; // @[dec_decode_ctl.scala 431:40] + wire _T_346 = _T_345 | i0_dp_zbp; // @[dec_decode_ctl.scala 431:52] + wire _T_347 = _T_346 | i0_dp_zbr; // @[dec_decode_ctl.scala 431:65] + wire _T_348 = _T_347 | i0_dp_zbf; // @[dec_decode_ctl.scala 431:77] + wire _T_349 = _T_348 | i0_dp_zba; // @[dec_decode_ctl.scala 431:89] + wire [3:0] _T_350 = i0_dp_mul ? 4'h1 : 4'h0; // @[Mux.scala 98:16] + wire [3:0] _T_351 = i0_dp_load ? 4'h2 : _T_350; // @[Mux.scala 98:16] + wire [3:0] _T_352 = i0_dp_store ? 4'h3 : _T_351; // @[Mux.scala 98:16] + wire [3:0] _T_353 = i0_dp_pm_alu ? 4'h4 : _T_352; // @[Mux.scala 98:16] + wire [3:0] _T_354 = _T_349 ? 4'hf : _T_353; // @[Mux.scala 98:16] + wire [3:0] _T_355 = _T_341 ? 4'h5 : _T_354; // @[Mux.scala 98:16] + wire [3:0] _T_356 = _T_338 ? 4'h6 : _T_355; // @[Mux.scala 98:16] + wire [3:0] _T_357 = _T_335 ? 4'h7 : _T_356; // @[Mux.scala 98:16] + wire [3:0] _T_358 = i0_dp_ebreak ? 4'h8 : _T_357; // @[Mux.scala 98:16] + wire [3:0] _T_359 = i0_dp_ecall ? 4'h9 : _T_358; // @[Mux.scala 98:16] + wire [3:0] _T_360 = i0_dp_fence ? 4'ha : _T_359; // @[Mux.scala 98:16] + wire [3:0] _T_361 = i0_dp_fence_i ? 4'hb : _T_360; // @[Mux.scala 98:16] + wire [3:0] _T_362 = i0_dp_mret ? 4'hc : _T_361; // @[Mux.scala 98:16] + wire [3:0] _T_363 = i0_dp_condbr ? 4'hd : _T_362; // @[Mux.scala 98:16] + wire [3:0] _T_364 = i0_dp_jal ? 4'he : _T_363; // @[Mux.scala 98:16] + wire [3:0] d_t_pmu_i0_itype = _T_334 & _T_364; // @[dec_decode_ctl.scala 420:49] + reg lsu_idle; // @[dec_decode_ctl.scala 442:45] + wire _T_418 = ~i0_pcall_case; // @[dec_decode_ctl.scala 464:35] + wire _T_419 = i0_dp_jal & _T_418; // @[dec_decode_ctl.scala 464:32] + wire _T_420 = ~i0_pja_case; // @[dec_decode_ctl.scala 464:52] + wire _T_421 = _T_419 & _T_420; // @[dec_decode_ctl.scala 464:50] + wire _T_422 = ~i0_pret_case; // @[dec_decode_ctl.scala 464:67] + wire _T_425 = i0r_rs1 == 5'h2; // @[dec_decode_ctl.scala 508:41] + wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[dec_decode_ctl.scala 633:40] + wire _T_1018 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 901:43] + reg x_d_bits_i0v; // @[Reg.scala 27:20] + wire _T_992 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 881:59] + wire _T_993 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 881:91] + wire i0_rs1_depend_i0_x = _T_992 & _T_993; // @[dec_decode_ctl.scala 881:74] + wire _T_994 = io_decode_exu_dec_i0_rs1_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 882:59] + wire _T_995 = r_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 882:91] + wire i0_rs1_depend_i0_r = _T_994 & _T_995; // @[dec_decode_ctl.scala 882:74] + wire [1:0] _T_1007 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 888:63] + wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_1007; // @[dec_decode_ctl.scala 888:24] + wire _T_1020 = _T_1018 & i0_rs1_depth_d[0]; // @[dec_decode_ctl.scala 901:58] + reg i0_x_c_load; // @[Reg.scala 27:20] + reg i0_r_c_load; // @[Reg.scala 27:20] + wire _T_1003_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 887:61] + wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_1003_load; // @[dec_decode_ctl.scala 887:24] + wire load_ldst_bypass_d = _T_1020 & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 901:78] + wire _T_996 = io_decode_exu_dec_i0_rs2_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 884:59] + wire _T_997 = x_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 884:91] + wire i0_rs2_depend_i0_x = _T_996 & _T_997; // @[dec_decode_ctl.scala 884:74] + wire _T_998 = io_decode_exu_dec_i0_rs2_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 885:59] + wire _T_999 = r_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 885:91] + wire i0_rs2_depend_i0_r = _T_998 & _T_999; // @[dec_decode_ctl.scala 885:74] + wire [1:0] _T_1016 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 890:63] + wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_1016; // @[dec_decode_ctl.scala 890:24] + wire _T_1023 = i0_dp_store & i0_rs2_depth_d[0]; // @[dec_decode_ctl.scala 902:43] + wire _T_1012_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 889:61] + wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_1012_load; // @[dec_decode_ctl.scala 889:24] + wire store_data_bypass_d = _T_1023 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 902:63] + wire _T_435 = i0_dp_csr_clr | i0_dp_csr_set; // @[dec_decode_ctl.scala 525:42] + wire _T_436 = _T_435 | i0_csr_write; // @[dec_decode_ctl.scala 525:58] + wire [11:0] _T_440 = io_dec_csr_any_unq_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12] + reg r_d_bits_csrwen; // @[Reg.scala 27:20] + wire _T_443 = r_d_bits_csrwen & r_d_valid; // @[dec_decode_ctl.scala 530:53] + wire [11:0] _T_445 = _T_443 ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12] + reg [11:0] r_d_bits_csrwaddr; // @[Reg.scala 27:20] + wire _T_450 = r_d_bits_csrwaddr == 12'h300; // @[dec_decode_ctl.scala 537:50] + wire _T_451 = r_d_bits_csrwaddr == 12'h304; // @[dec_decode_ctl.scala 537:85] + wire _T_452 = _T_450 | _T_451; // @[dec_decode_ctl.scala 537:64] + wire _T_453 = _T_452 & r_d_bits_csrwen; // @[dec_decode_ctl.scala 537:100] + wire _T_454 = _T_453 & r_d_valid; // @[dec_decode_ctl.scala 537:118] + wire _T_455 = ~io_dec_tlu_i0_kill_writeb_wb; // @[dec_decode_ctl.scala 537:132] + reg csr_read_x; // @[dec_decode_ctl.scala 539:52] + reg csr_clr_x; // @[dec_decode_ctl.scala 540:51] + reg csr_set_x; // @[dec_decode_ctl.scala 541:51] + reg csr_write_x; // @[dec_decode_ctl.scala 542:53] + reg csr_imm_x; // @[dec_decode_ctl.scala 543:51] + wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[dec_decode_ctl.scala 769:50] + wire _T_459 = i0_x_data_en & any_csr_d; // @[dec_decode_ctl.scala 546:48] + reg [4:0] csrimm_x; // @[Reg.scala 27:20] + reg [31:0] csr_rddata_x; // @[Reg.scala 27:20] + wire [31:0] _T_493 = {27'h0,csrimm_x}; // @[Cat.scala 29:58] + wire _T_495 = ~csr_imm_x; // @[dec_decode_ctl.scala 551:5] + wire [31:0] _T_496 = csr_imm_x ? _T_493 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_497 = _T_495 ? io_decode_exu_exu_csr_rs1_x : 32'h0; // @[Mux.scala 27:72] + wire [31:0] csr_mask_x = _T_496 | _T_497; // @[Mux.scala 27:72] + wire [31:0] _T_499 = ~csr_mask_x; // @[dec_decode_ctl.scala 554:38] + wire [31:0] _T_500 = csr_rddata_x & _T_499; // @[dec_decode_ctl.scala 554:35] + wire [31:0] _T_501 = csr_rddata_x | csr_mask_x; // @[dec_decode_ctl.scala 555:35] + wire [31:0] _T_502 = csr_clr_x ? _T_500 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_503 = csr_set_x ? _T_501 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_504 = csr_write_x ? csr_mask_x : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_505 = _T_502 | _T_503; // @[Mux.scala 27:72] + wire [31:0] write_csr_data_x = _T_505 | _T_504; // @[Mux.scala 27:72] + wire _T_517 = ~tlu_wr_pause_r1; // @[dec_decode_ctl.scala 562:44] + wire _T_518 = ~tlu_wr_pause_r2; // @[dec_decode_ctl.scala 562:64] + wire _T_519 = _T_517 & _T_518; // @[dec_decode_ctl.scala 562:61] + wire [31:0] _T_522 = write_csr_data - 32'h1; // @[dec_decode_ctl.scala 565:59] + wire _T_524 = csr_clr_x | csr_set_x; // @[dec_decode_ctl.scala 567:34] + wire _T_525 = _T_524 | csr_write_x; // @[dec_decode_ctl.scala 567:46] + wire _T_526 = _T_525 & csr_read_x; // @[dec_decode_ctl.scala 567:61] + wire _T_527 = _T_526 | io_dec_tlu_wr_pause_r; // @[dec_decode_ctl.scala 567:75] + wire csr_data_wen = _T_527 | pause_stall; // @[dec_decode_ctl.scala 567:99] + reg r_d_bits_csrwonly; // @[Reg.scala 27:20] + wire _T_529 = r_d_bits_csrwonly & r_d_valid; // @[dec_decode_ctl.scala 574:50] + wire _T_881 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 822:42] + reg [31:0] i0_result_r_raw; // @[Reg.scala 27:20] + wire [31:0] i0_result_corr_r = _T_881 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 822:27] + reg x_d_bits_csrwonly; // @[Reg.scala 27:20] + wire _T_532 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[dec_decode_ctl.scala 576:43] + reg wbd_bits_csrwonly; // @[Reg.scala 27:20] + wire prior_csr_write = _T_532 | wbd_bits_csrwonly; // @[dec_decode_ctl.scala 576:63] + wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[1]; // @[dec_decode_ctl.scala 579:48] + wire debug_fence = debug_fence_raw | debug_fence_i; // @[dec_decode_ctl.scala 580:40] + wire _T_536 = i0_dp_presync | io_dec_tlu_presync_d; // @[dec_decode_ctl.scala 583:34] + wire _T_537 = _T_536 | debug_fence_i; // @[dec_decode_ctl.scala 583:57] + wire _T_538 = _T_537 | debug_fence_raw; // @[dec_decode_ctl.scala 583:73] + wire i0_presync = _T_538 | io_dec_tlu_pipelining_disable; // @[dec_decode_ctl.scala 583:91] + wire [31:0] _T_562 = {16'h0,io_dec_aln_ifu_i0_cinst}; // @[Cat.scala 29:58] + wire _T_564 = ~illegal_lockout; // @[dec_decode_ctl.scala 595:44] + wire illegal_inst_en = shift_illegal & _T_564; // @[dec_decode_ctl.scala 595:42] + reg [31:0] _T_565; // @[Reg.scala 27:20] + wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[dec_decode_ctl.scala 598:42] + wire _T_569 = i0_dp_csr_read & prior_csr_write; // @[dec_decode_ctl.scala 600:40] + wire _T_570 = _T_569 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 600:59] + wire _T_571 = _T_570 | pause_stall; // @[dec_decode_ctl.scala 600:92] + wire _T_572 = _T_571 | leak1_i0_stall; // @[dec_decode_ctl.scala 600:106] + wire _T_573 = _T_572 | io_dec_tlu_debug_stall; // @[dec_decode_ctl.scala 601:20] + wire _T_574 = _T_573 | postsync_stall; // @[dec_decode_ctl.scala 601:45] + wire prior_inflight = x_d_valid | r_d_valid; // @[dec_decode_ctl.scala 623:41] + wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[dec_decode_ctl.scala 624:31] + wire presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 626:37] + wire _T_575 = _T_574 | presync_stall; // @[dec_decode_ctl.scala 601:62] + wire _T_576 = i0_dp_fence | debug_fence; // @[dec_decode_ctl.scala 602:19] + wire _T_577 = ~lsu_idle; // @[dec_decode_ctl.scala 602:36] + wire _T_578 = _T_576 & _T_577; // @[dec_decode_ctl.scala 602:34] + wire _T_579 = _T_575 | _T_578; // @[dec_decode_ctl.scala 601:79] + wire _T_580 = _T_579 | i0_nonblock_load_stall; // @[dec_decode_ctl.scala 602:47] + wire _T_939 = io_decode_exu_dec_i0_rs1_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 850:60] + wire _T_940 = io_div_waddr_wb == i0r_rs1; // @[dec_decode_ctl.scala 850:99] + wire _T_941 = _T_939 & _T_940; // @[dec_decode_ctl.scala 850:80] + wire _T_942 = io_decode_exu_dec_i0_rs2_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 851:36] + wire _T_943 = io_div_waddr_wb == i0r_rs2; // @[dec_decode_ctl.scala 851:75] + wire _T_944 = _T_942 & _T_943; // @[dec_decode_ctl.scala 851:56] + wire i0_nonblock_div_stall = _T_941 | _T_944; // @[dec_decode_ctl.scala 850:113] + wire _T_582 = _T_580 | i0_nonblock_div_stall; // @[dec_decode_ctl.scala 603:21] + wire i0_block_raw_d = _T_582 | i0_div_prior_div_stall; // @[dec_decode_ctl.scala 603:45] + wire _T_583 = io_lsu_store_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 605:65] + wire i0_store_stall_d = i0_dp_store & _T_583; // @[dec_decode_ctl.scala 605:39] + wire _T_584 = io_lsu_load_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 606:63] + wire i0_load_stall_d = i0_dp_load & _T_584; // @[dec_decode_ctl.scala 606:38] + wire _T_585 = i0_block_raw_d | i0_store_stall_d; // @[dec_decode_ctl.scala 607:38] + wire i0_block_d = _T_585 | i0_load_stall_d; // @[dec_decode_ctl.scala 607:57] + wire _T_586 = ~i0_block_d; // @[dec_decode_ctl.scala 611:54] + wire _T_587 = io_dec_ib0_valid_d & _T_586; // @[dec_decode_ctl.scala 611:52] + wire _T_589 = _T_587 & _T_367; // @[dec_decode_ctl.scala 611:69] + wire _T_592 = ~i0_block_raw_d; // @[dec_decode_ctl.scala 612:46] + wire _T_593 = io_dec_ib0_valid_d & _T_592; // @[dec_decode_ctl.scala 612:44] + wire _T_595 = _T_593 & _T_367; // @[dec_decode_ctl.scala 612:61] + wire i0_exudecode_d = _T_595 & _T_567; // @[dec_decode_ctl.scala 612:89] + wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[dec_decode_ctl.scala 613:46] + wire _T_597 = ~io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 617:51] + wire _T_610 = i0_dp_condbr | i0_dp_jal; // @[dec_decode_ctl.scala 631:53] + wire d_t_icaf = i0_icaf_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 641:40] + wire d_t_icaf_second = io_dec_i0_icaf_second_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 642:58] + wire _T_619 = i0_dp_fence_i | debug_fence_i; // @[dec_decode_ctl.scala 645:44] + wire d_t_fence_i = _T_619 & i0_legal_decode_d; // @[dec_decode_ctl.scala 645:61] + wire [3:0] _T_624 = {io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d}; // @[Cat.scala 29:58] + wire [3:0] d_t_i0trigger = io_dec_i0_trigger_match_d & _T_624; // @[dec_decode_ctl.scala 652:56] + wire _T_818 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 766:49] + wire i0_x_ctl_en = _T_818 | io_clk_override; // @[dec_decode_ctl.scala 766:53] + reg x_t_legal; // @[Reg.scala 27:20] + reg x_t_icaf; // @[Reg.scala 27:20] + reg x_t_icaf_second; // @[Reg.scala 27:20] + reg [1:0] x_t_icaf_type; // @[Reg.scala 27:20] + reg x_t_fence_i; // @[Reg.scala 27:20] + reg [3:0] x_t_i0trigger; // @[Reg.scala 27:20] + reg [3:0] x_t_pmu_i0_itype; // @[Reg.scala 27:20] + reg x_t_pmu_i0_br_unpred; // @[Reg.scala 27:20] + wire [3:0] _T_632 = {io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb}; // @[Cat.scala 29:58] + wire [3:0] _T_633 = ~_T_632; // @[dec_decode_ctl.scala 658:39] + wire [3:0] x_t_in_i0trigger = x_t_i0trigger & _T_633; // @[dec_decode_ctl.scala 658:37] + reg r_t_legal; // @[Reg.scala 27:20] + reg r_t_icaf; // @[Reg.scala 27:20] + reg r_t_icaf_second; // @[Reg.scala 27:20] + reg [1:0] r_t_icaf_type; // @[Reg.scala 27:20] + reg r_t_fence_i; // @[Reg.scala 27:20] + reg [3:0] r_t_i0trigger; // @[Reg.scala 27:20] + reg [3:0] r_t_pmu_i0_itype; // @[Reg.scala 27:20] + reg r_t_pmu_i0_br_unpred; // @[Reg.scala 27:20] + reg r_d_bits_i0store; // @[Reg.scala 27:20] + wire _T_638 = r_d_bits_i0load | r_d_bits_i0store; // @[dec_decode_ctl.scala 664:61] + wire [3:0] _T_642 = {_T_638,_T_638,_T_638,_T_638}; // @[Cat.scala 29:58] + wire [3:0] _T_643 = _T_642 & lsu_trigger_match_r; // @[dec_decode_ctl.scala 664:82] + wire [3:0] _T_644 = _T_643 | r_t_i0trigger; // @[dec_decode_ctl.scala 664:105] + wire _T_657 = i0r_rs1 != 5'h0; // @[dec_decode_ctl.scala 680:60] + wire _T_659 = i0r_rs2 != 5'h0; // @[dec_decode_ctl.scala 681:60] + wire _T_661 = i0r_rd != 5'h0; // @[dec_decode_ctl.scala 682:48] + wire i0_rd_en_d = i0_dp_rd & _T_661; // @[dec_decode_ctl.scala 682:37] + wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[dec_decode_ctl.scala 686:38] + wire _T_662 = ~i0_dp_jal; // @[dec_decode_ctl.scala 687:27] + wire i0_uiimm20 = _T_662 & i0_dp_imm20; // @[dec_decode_ctl.scala 687:38] + wire [9:0] _T_673 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] + wire [18:0] _T_682 = {_T_673,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] + wire [31:0] _T_685 = {_T_682,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31:20]}; // @[Cat.scala 29:58] + wire [31:0] _T_714 = {27'h0,i0r_rs2}; // @[Cat.scala 29:58] + wire [31:0] _T_734 = {_T_673,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21],1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_748 = {io_dec_i0_instr_d[31:12],12'h0}; // @[Cat.scala 29:58] + wire _T_749 = i0_csr_write_only_d & i0_dp_csr_imm; // @[dec_decode_ctl.scala 698:26] + wire [31:0] _T_779 = {27'h0,i0r_rs1}; // @[Cat.scala 29:58] + wire [31:0] _T_780 = i0_dp_imm12 ? _T_685 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_781 = i0_dp_shimm5 ? _T_714 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_782 = i0_jalimm20 ? _T_734 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_783 = i0_uiimm20 ? _T_748 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_784 = _T_749 ? _T_779 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_785 = _T_780 | _T_781; // @[Mux.scala 27:72] + wire [31:0] _T_786 = _T_785 | _T_782; // @[Mux.scala 27:72] + wire [31:0] _T_787 = _T_786 | _T_783; // @[Mux.scala 27:72] + wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[dec_decode_ctl.scala 758:44] + wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[dec_decode_ctl.scala 759:44] + wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[dec_decode_ctl.scala 760:44] + reg i0_x_c_mul; // @[Reg.scala 27:20] + reg i0_x_c_alu; // @[Reg.scala 27:20] + reg i0_r_c_mul; // @[Reg.scala 27:20] + reg i0_r_c_alu; // @[Reg.scala 27:20] + wire _T_824 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 768:49] + wire i0_wb_ctl_en = _T_824 | io_clk_override; // @[dec_decode_ctl.scala 768:53] + wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[dec_decode_ctl.scala 770:50] + wire i0_wb_data_en = i0_pipe_en[1] | io_clk_override; // @[dec_decode_ctl.scala 771:50] + wire d_d_bits_i0v = i0_rd_en_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 777:50] + wire d_d_bits_i0store = i0_dp_store & i0_legal_decode_d; // @[dec_decode_ctl.scala 781:50] + wire d_d_bits_i0div = i0_dp_div & i0_legal_decode_d; // @[dec_decode_ctl.scala 782:50] + wire d_d_bits_csrwen = io_dec_csr_wen_unq_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 784:61] + wire d_d_bits_csrwonly = i0_csr_write_only_d & io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 785:58] + reg x_d_bits_i0store; // @[Reg.scala 27:20] + reg x_d_bits_csrwen; // @[Reg.scala 27:20] + reg [11:0] x_d_bits_csrwaddr; // @[Reg.scala 27:20] + wire _T_847 = x_d_bits_i0v & _T_857; // @[dec_decode_ctl.scala 791:47] + wire x_d_in_bits_i0v = _T_847 & _T_367; // @[dec_decode_ctl.scala 791:76] + wire _T_851 = x_d_valid & _T_857; // @[dec_decode_ctl.scala 792:33] + wire x_d_in_valid = _T_851 & _T_367; // @[dec_decode_ctl.scala 792:62] + wire _T_870 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 807:49] + wire _T_871 = i0_wen_r & _T_870; // @[dec_decode_ctl.scala 807:47] + wire _T_872 = ~i0_load_kill_wen_r; // @[dec_decode_ctl.scala 807:70] + wire _T_874 = x_d_bits_i0v | x_d_bits_csrwen; // @[dec_decode_ctl.scala 811:74] + wire _T_875 = _T_874 | debug_valid_x; // @[dec_decode_ctl.scala 811:92] + wire _T_876 = i0_r_data_en & _T_875; // @[dec_decode_ctl.scala 811:58] + wire _T_878 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 817:47] + wire _T_885 = io_decode_exu_i0_ap_predict_nt & _T_662; // @[dec_decode_ctl.scala 823:71] + wire [11:0] _T_898 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] + reg [11:0] last_br_immed_x; // @[Reg.scala 27:20] + wire trace_enable = ~io_dec_tlu_trace_disable; // @[dec_decode_ctl.scala 858:22] + reg [4:0] _T_947; // @[Reg.scala 27:20] + wire _T_948 = i0_x_data_en & trace_enable; // @[dec_decode_ctl.scala 862:50] + reg [31:0] i0_inst_x; // @[Reg.scala 27:20] + wire _T_950 = i0_r_data_en & trace_enable; // @[dec_decode_ctl.scala 863:50] + reg [31:0] i0_inst_r; // @[Reg.scala 27:20] + wire _T_952 = i0_wb_data_en & trace_enable; // @[dec_decode_ctl.scala 865:51] + reg [31:0] i0_inst_wb; // @[Reg.scala 27:20] + reg [30:0] i0_pc_wb; // @[Reg.scala 27:20] + reg [30:0] dec_i0_pc_r; // @[Reg.scala 27:20] + wire [31:0] _T_958 = {io_dec_alu_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58] + wire [12:0] _T_959 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58] + wire [12:0] _T_962 = _T_958[12:1] + _T_959[12:1]; // @[lib.scala 68:31] + wire [18:0] _T_965 = _T_958[31:13] + 19'h1; // @[lib.scala 69:27] + wire [18:0] _T_968 = _T_958[31:13] - 19'h1; // @[lib.scala 70:27] + wire _T_971 = ~_T_962[12]; // @[lib.scala 72:28] + wire _T_972 = _T_959[12] ^ _T_971; // @[lib.scala 72:26] + wire _T_975 = ~_T_959[12]; // @[lib.scala 73:20] + wire _T_977 = _T_975 & _T_962[12]; // @[lib.scala 73:26] + wire _T_981 = _T_959[12] & _T_971; // @[lib.scala 74:26] + wire [18:0] _T_983 = _T_972 ? _T_958[31:13] : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_984 = _T_977 ? _T_965 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_985 = _T_981 ? _T_968 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_986 = _T_983 | _T_984; // @[Mux.scala 27:72] + wire [18:0] _T_987 = _T_986 | _T_985; // @[Mux.scala 27:72] + wire [31:0] temp_pred_correct_npc_x = {_T_987,_T_962[11:0],1'h0}; // @[Cat.scala 29:58] + wire _T_1003_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 887:61] + wire _T_1003_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 887:61] + wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_1003_mul; // @[dec_decode_ctl.scala 887:24] + wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_1003_alu; // @[dec_decode_ctl.scala 887:24] + wire _T_1012_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 889:61] + wire _T_1012_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 889:61] + wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_1012_mul; // @[dec_decode_ctl.scala 889:24] + wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_1012_alu; // @[dec_decode_ctl.scala 889:24] + wire _T_1025 = io_decode_exu_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 907:73] + wire _T_1026 = io_dec_nonblock_load_waddr == i0r_rs1; // @[dec_decode_ctl.scala 907:130] + wire i0_rs1_nonblock_load_bypass_en_d = _T_1025 & _T_1026; // @[dec_decode_ctl.scala 907:100] + wire _T_1027 = io_decode_exu_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 909:73] + wire _T_1028 = io_dec_nonblock_load_waddr == i0r_rs2; // @[dec_decode_ctl.scala 909:130] + wire i0_rs2_nonblock_load_bypass_en_d = _T_1027 & _T_1028; // @[dec_decode_ctl.scala 909:100] + wire _T_1030 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[dec_decode_ctl.scala 912:66] + wire _T_1031 = i0_rs1_depth_d[0] & _T_1030; // @[dec_decode_ctl.scala 912:45] + wire _T_1033 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 912:108] + wire _T_1036 = _T_1030 | i0_rs1_class_d_load; // @[dec_decode_ctl.scala 912:196] + wire _T_1037 = i0_rs1_depth_d[1] & _T_1036; // @[dec_decode_ctl.scala 912:153] + wire [2:0] i0_rs1bypass = {_T_1031,_T_1033,_T_1037}; // @[Cat.scala 29:58] + wire _T_1041 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[dec_decode_ctl.scala 914:67] + wire _T_1042 = i0_rs2_depth_d[0] & _T_1041; // @[dec_decode_ctl.scala 914:45] + wire _T_1044 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 914:109] + wire _T_1047 = _T_1041 | i0_rs2_class_d_load; // @[dec_decode_ctl.scala 914:196] + wire _T_1048 = i0_rs2_depth_d[1] & _T_1047; // @[dec_decode_ctl.scala 914:153] + wire [2:0] i0_rs2bypass = {_T_1042,_T_1044,_T_1048}; // @[Cat.scala 29:58] + wire _T_1052 = ~i0_rs1bypass[0]; // @[dec_decode_ctl.scala 916:53] + wire _T_1054 = ~i0_rs1bypass[1]; // @[dec_decode_ctl.scala 916:72] + wire _T_1055 = _T_1052 & _T_1054; // @[dec_decode_ctl.scala 916:70] + wire _T_1057 = ~i0_rs1bypass[2]; // @[dec_decode_ctl.scala 916:91] + wire _T_1058 = _T_1055 & _T_1057; // @[dec_decode_ctl.scala 916:89] + wire _T_1059 = _T_1058 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 916:108] + wire [1:0] _T_1063 = {i0_rs1bypass[1],i0_rs1bypass[0]}; // @[Cat.scala 29:58] + wire [1:0] _T_1064 = {_T_1059,i0_rs1bypass[2]}; // @[Cat.scala 29:58] + wire _T_1067 = ~i0_rs2bypass[0]; // @[dec_decode_ctl.scala 917:53] + wire _T_1069 = ~i0_rs2bypass[1]; // @[dec_decode_ctl.scala 917:72] + wire _T_1070 = _T_1067 & _T_1069; // @[dec_decode_ctl.scala 917:70] + wire _T_1072 = ~i0_rs2bypass[2]; // @[dec_decode_ctl.scala 917:91] + wire _T_1073 = _T_1070 & _T_1072; // @[dec_decode_ctl.scala 917:89] + wire _T_1074 = _T_1073 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 917:108] + wire [1:0] _T_1078 = {i0_rs2bypass[1],i0_rs2bypass[0]}; // @[Cat.scala 29:58] + wire [1:0] _T_1079 = {_T_1074,i0_rs2bypass[2]}; // @[Cat.scala 29:58] + wire _T_1081 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 921:68] + wire _T_1082 = io_dec_ib0_valid_d & _T_1081; // @[dec_decode_ctl.scala 921:50] + wire _T_1083 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 921:89] + wire _T_1084 = _T_1082 & _T_1083; // @[dec_decode_ctl.scala 921:87] + wire _T_1086 = _T_1084 & _T_592; // @[dec_decode_ctl.scala 921:121] + wire _T_1088 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 923:6] + wire _T_1089 = _T_1088 & i0_dp_lsu; // @[dec_decode_ctl.scala 923:38] + wire _T_1090 = _T_1089 & i0_dp_load; // @[dec_decode_ctl.scala 923:50] + wire _T_1095 = _T_1089 & i0_dp_store; // @[dec_decode_ctl.scala 924:50] + wire [11:0] _T_1099 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58] + wire [11:0] _T_1100 = _T_1090 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72] + wire [11:0] _T_1101 = _T_1095 ? _T_1099 : 12'h0; // @[Mux.scala 27:72] + dec_dec_ctl i0_dec ( // @[dec_decode_ctl.scala 438:22] + .io_ins(i0_dec_io_ins), + .io_out_clz(i0_dec_io_out_clz), + .io_out_ctz(i0_dec_io_out_ctz), + .io_out_pcnt(i0_dec_io_out_pcnt), + .io_out_sext_b(i0_dec_io_out_sext_b), + .io_out_sext_h(i0_dec_io_out_sext_h), + .io_out_slo(i0_dec_io_out_slo), + .io_out_sro(i0_dec_io_out_sro), + .io_out_min(i0_dec_io_out_min), + .io_out_max(i0_dec_io_out_max), + .io_out_pack(i0_dec_io_out_pack), + .io_out_packu(i0_dec_io_out_packu), + .io_out_packh(i0_dec_io_out_packh), + .io_out_rol(i0_dec_io_out_rol), + .io_out_ror(i0_dec_io_out_ror), + .io_out_grev(i0_dec_io_out_grev), + .io_out_gorc(i0_dec_io_out_gorc), + .io_out_zbb(i0_dec_io_out_zbb), + .io_out_sbset(i0_dec_io_out_sbset), + .io_out_sbclr(i0_dec_io_out_sbclr), + .io_out_sbinv(i0_dec_io_out_sbinv), + .io_out_sbext(i0_dec_io_out_sbext), + .io_out_zbs(i0_dec_io_out_zbs), + .io_out_bext(i0_dec_io_out_bext), + .io_out_bdep(i0_dec_io_out_bdep), + .io_out_zbe(i0_dec_io_out_zbe), + .io_out_clmul(i0_dec_io_out_clmul), + .io_out_clmulh(i0_dec_io_out_clmulh), + .io_out_clmulr(i0_dec_io_out_clmulr), + .io_out_zbc(i0_dec_io_out_zbc), + .io_out_shfl(i0_dec_io_out_shfl), + .io_out_unshfl(i0_dec_io_out_unshfl), + .io_out_zbp(i0_dec_io_out_zbp), + .io_out_crc32_b(i0_dec_io_out_crc32_b), + .io_out_crc32_h(i0_dec_io_out_crc32_h), + .io_out_crc32_w(i0_dec_io_out_crc32_w), + .io_out_crc32c_b(i0_dec_io_out_crc32c_b), + .io_out_crc32c_h(i0_dec_io_out_crc32c_h), + .io_out_crc32c_w(i0_dec_io_out_crc32c_w), + .io_out_zbr(i0_dec_io_out_zbr), + .io_out_bfp(i0_dec_io_out_bfp), + .io_out_zbf(i0_dec_io_out_zbf), + .io_out_sh1add(i0_dec_io_out_sh1add), + .io_out_sh2add(i0_dec_io_out_sh2add), + .io_out_sh3add(i0_dec_io_out_sh3add), + .io_out_zba(i0_dec_io_out_zba), + .io_out_alu(i0_dec_io_out_alu), + .io_out_rs1(i0_dec_io_out_rs1), + .io_out_rs2(i0_dec_io_out_rs2), + .io_out_imm12(i0_dec_io_out_imm12), + .io_out_rd(i0_dec_io_out_rd), + .io_out_shimm5(i0_dec_io_out_shimm5), + .io_out_imm20(i0_dec_io_out_imm20), + .io_out_pc(i0_dec_io_out_pc), + .io_out_load(i0_dec_io_out_load), + .io_out_store(i0_dec_io_out_store), + .io_out_lsu(i0_dec_io_out_lsu), + .io_out_add(i0_dec_io_out_add), + .io_out_sub(i0_dec_io_out_sub), + .io_out_land(i0_dec_io_out_land), + .io_out_lor(i0_dec_io_out_lor), + .io_out_lxor(i0_dec_io_out_lxor), + .io_out_sll(i0_dec_io_out_sll), + .io_out_sra(i0_dec_io_out_sra), + .io_out_srl(i0_dec_io_out_srl), + .io_out_slt(i0_dec_io_out_slt), + .io_out_unsign(i0_dec_io_out_unsign), + .io_out_condbr(i0_dec_io_out_condbr), + .io_out_beq(i0_dec_io_out_beq), + .io_out_bne(i0_dec_io_out_bne), + .io_out_bge(i0_dec_io_out_bge), + .io_out_blt(i0_dec_io_out_blt), + .io_out_jal(i0_dec_io_out_jal), + .io_out_by(i0_dec_io_out_by), + .io_out_half(i0_dec_io_out_half), + .io_out_word(i0_dec_io_out_word), + .io_out_csr_read(i0_dec_io_out_csr_read), + .io_out_csr_clr(i0_dec_io_out_csr_clr), + .io_out_csr_set(i0_dec_io_out_csr_set), + .io_out_csr_write(i0_dec_io_out_csr_write), + .io_out_csr_imm(i0_dec_io_out_csr_imm), + .io_out_presync(i0_dec_io_out_presync), + .io_out_postsync(i0_dec_io_out_postsync), + .io_out_ebreak(i0_dec_io_out_ebreak), + .io_out_ecall(i0_dec_io_out_ecall), + .io_out_mret(i0_dec_io_out_mret), + .io_out_mul(i0_dec_io_out_mul), + .io_out_rs1_sign(i0_dec_io_out_rs1_sign), + .io_out_rs2_sign(i0_dec_io_out_rs2_sign), + .io_out_low(i0_dec_io_out_low), + .io_out_div(i0_dec_io_out_div), + .io_out_rem(i0_dec_io_out_rem), + .io_out_fence(i0_dec_io_out_fence), + .io_out_fence_i(i0_dec_io_out_fence_i), + .io_out_pm_alu(i0_dec_io_out_pm_alu), + .io_out_legal(i0_dec_io_out_legal) + ); + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en) + ); + rvclkhdr rvclkhdr_10 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en) + ); + assign io_decode_exu_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[dec_decode_ctl.scala 773:38] + assign io_decode_exu_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[dec_decode_ctl.scala 774:38] + assign io_decode_exu_i0_ap_clz = _T_80 ? 1'h0 : i0_dp_raw_clz; // @[dec_decode_ctl.scala 317:33] + assign io_decode_exu_i0_ap_ctz = _T_80 ? 1'h0 : i0_dp_raw_ctz; // @[dec_decode_ctl.scala 318:33] + assign io_decode_exu_i0_ap_pcnt = _T_80 ? 1'h0 : i0_dp_raw_pcnt; // @[dec_decode_ctl.scala 319:33] + assign io_decode_exu_i0_ap_sext_b = _T_80 ? 1'h0 : i0_dp_raw_sext_b; // @[dec_decode_ctl.scala 320:33] + assign io_decode_exu_i0_ap_sext_h = _T_80 ? 1'h0 : i0_dp_raw_sext_h; // @[dec_decode_ctl.scala 321:33] + assign io_decode_exu_i0_ap_slo = _T_80 ? 1'h0 : i0_dp_raw_slo; // @[dec_decode_ctl.scala 326:33] + assign io_decode_exu_i0_ap_sro = _T_80 ? 1'h0 : i0_dp_raw_sro; // @[dec_decode_ctl.scala 327:33] + assign io_decode_exu_i0_ap_min = _T_80 ? 1'h0 : i0_dp_raw_min; // @[dec_decode_ctl.scala 328:33] + assign io_decode_exu_i0_ap_max = _T_80 ? 1'h0 : i0_dp_raw_max; // @[dec_decode_ctl.scala 329:33] + assign io_decode_exu_i0_ap_pack = _T_80 ? 1'h0 : i0_dp_raw_pack; // @[dec_decode_ctl.scala 330:33] + assign io_decode_exu_i0_ap_packu = _T_80 ? 1'h0 : i0_dp_raw_packu; // @[dec_decode_ctl.scala 331:33] + assign io_decode_exu_i0_ap_packh = _T_80 ? 1'h0 : i0_dp_raw_packh; // @[dec_decode_ctl.scala 332:33] + assign io_decode_exu_i0_ap_rol = _T_80 ? 1'h0 : i0_dp_raw_rol; // @[dec_decode_ctl.scala 333:33] + assign io_decode_exu_i0_ap_ror = _T_80 ? 1'h0 : i0_dp_raw_ror; // @[dec_decode_ctl.scala 334:33] + assign io_decode_exu_i0_ap_grev = _T_80 ? 1'h0 : i0_dp_raw_grev; // @[dec_decode_ctl.scala 335:33] + assign io_decode_exu_i0_ap_gorc = _T_80 ? 1'h0 : i0_dp_raw_gorc; // @[dec_decode_ctl.scala 336:33] + assign io_decode_exu_i0_ap_zbb = _T_80 ? 1'h0 : i0_dp_raw_zbb; // @[dec_decode_ctl.scala 337:33] + assign io_decode_exu_i0_ap_sbset = _T_80 ? 1'h0 : i0_dp_raw_sbset; // @[dec_decode_ctl.scala 338:33] + assign io_decode_exu_i0_ap_sbclr = _T_80 ? 1'h0 : i0_dp_raw_sbclr; // @[dec_decode_ctl.scala 339:33] + assign io_decode_exu_i0_ap_sbinv = _T_80 ? 1'h0 : i0_dp_raw_sbinv; // @[dec_decode_ctl.scala 340:33] + assign io_decode_exu_i0_ap_sbext = _T_80 ? 1'h0 : i0_dp_raw_sbext; // @[dec_decode_ctl.scala 341:33] + assign io_decode_exu_i0_ap_sh1add = _T_80 ? 1'h0 : i0_dp_raw_sh1add; // @[dec_decode_ctl.scala 322:33] + assign io_decode_exu_i0_ap_sh2add = _T_80 ? 1'h0 : i0_dp_raw_sh2add; // @[dec_decode_ctl.scala 323:33] + assign io_decode_exu_i0_ap_sh3add = _T_80 ? 1'h0 : i0_dp_raw_sh3add; // @[dec_decode_ctl.scala 324:33] + assign io_decode_exu_i0_ap_zba = _T_80 ? 1'h0 : i0_dp_raw_zba; // @[dec_decode_ctl.scala 325:33] + assign io_decode_exu_i0_ap_land = _T_80 ? 1'h0 : i0_dp_raw_land; // @[dec_decode_ctl.scala 305:33] + assign io_decode_exu_i0_ap_lor = _T_80 | i0_dp_raw_lor; // @[dec_decode_ctl.scala 306:33] + assign io_decode_exu_i0_ap_lxor = _T_80 ? 1'h0 : i0_dp_raw_lxor; // @[dec_decode_ctl.scala 307:33] + assign io_decode_exu_i0_ap_sll = _T_80 ? 1'h0 : i0_dp_raw_sll; // @[dec_decode_ctl.scala 308:33] + assign io_decode_exu_i0_ap_srl = _T_80 ? 1'h0 : i0_dp_raw_srl; // @[dec_decode_ctl.scala 309:33] + assign io_decode_exu_i0_ap_sra = _T_80 ? 1'h0 : i0_dp_raw_sra; // @[dec_decode_ctl.scala 310:33] + assign io_decode_exu_i0_ap_beq = _T_80 ? 1'h0 : i0_dp_raw_beq; // @[dec_decode_ctl.scala 313:33] + assign io_decode_exu_i0_ap_bne = _T_80 ? 1'h0 : i0_dp_raw_bne; // @[dec_decode_ctl.scala 314:33] + assign io_decode_exu_i0_ap_blt = _T_80 ? 1'h0 : i0_dp_raw_blt; // @[dec_decode_ctl.scala 315:33] + assign io_decode_exu_i0_ap_bge = _T_80 ? 1'h0 : i0_dp_raw_bge; // @[dec_decode_ctl.scala 316:33] + assign io_decode_exu_i0_ap_add = _T_80 ? 1'h0 : i0_dp_raw_add; // @[dec_decode_ctl.scala 303:33] + assign io_decode_exu_i0_ap_sub = _T_80 ? 1'h0 : i0_dp_raw_sub; // @[dec_decode_ctl.scala 304:33] + assign io_decode_exu_i0_ap_slt = _T_80 ? 1'h0 : i0_dp_raw_slt; // @[dec_decode_ctl.scala 311:33] + assign io_decode_exu_i0_ap_unsign = _T_80 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 312:33] + assign io_decode_exu_i0_ap_jal = _T_421 & _T_422; // @[dec_decode_ctl.scala 344:33] + assign io_decode_exu_i0_ap_predict_t = _T_86 & i0_predict_br; // @[dec_decode_ctl.scala 300:37] + assign io_decode_exu_i0_ap_predict_nt = _T_87 & i0_predict_br; // @[dec_decode_ctl.scala 299:37] + assign io_decode_exu_i0_ap_csr_write = i0_csr_write & _T_433; // @[dec_decode_ctl.scala 342:33] + assign io_decode_exu_i0_ap_csr_imm = _T_80 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 343:33] + assign io_decode_exu_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[dec_decode_ctl.scala 232:57] + assign io_decode_exu_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 230:57] + assign io_decode_exu_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_bits_hist; // @[dec_decode_ctl.scala 231:57] + assign io_decode_exu_dec_i0_predict_p_d_bits_toffset = _T_399 ? i0_pcall_imm[11:0] : _T_408; // @[dec_decode_ctl.scala 244:58] + assign io_decode_exu_dec_i0_predict_p_d_bits_br_error = _T_71 & _T_50; // @[dec_decode_ctl.scala 239:58] + assign io_decode_exu_dec_i0_predict_p_d_bits_br_start_error = _T_74 & _T_50; // @[dec_decode_ctl.scala 240:58] + assign io_decode_exu_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 226:57] + assign io_decode_exu_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 227:57] + assign io_decode_exu_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_bits_way; // @[dec_decode_ctl.scala 246:58] + assign io_decode_exu_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 228:57] + assign io_decode_exu_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_bits_prett; // @[dec_decode_ctl.scala 229:57] + assign io_decode_exu_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[dec_decode_ctl.scala 245:58] + assign io_decode_exu_i0_predict_index_d = io_dec_i0_bp_index; // @[dec_decode_ctl.scala 241:58] + assign io_decode_exu_i0_predict_btag_d = io_dec_i0_bp_btag; // @[dec_decode_ctl.scala 242:58] + assign io_decode_exu_dec_i0_rs1_en_d = i0_dp_rs1 & _T_657; // @[dec_decode_ctl.scala 680:35] + assign io_decode_exu_dec_i0_branch_d = _T_610 | i0_br_error_all; // @[dec_decode_ctl.scala 631:37] + assign io_decode_exu_dec_i0_rs2_en_d = i0_dp_rs2 & _T_659; // @[dec_decode_ctl.scala 681:35] + assign io_decode_exu_dec_i0_immed_d = _T_787 | _T_784; // @[dec_decode_ctl.scala 693:32] + assign io_decode_exu_dec_i0_result_r = i0_result_r_raw; // @[dec_decode_ctl.scala 919:41] + assign io_decode_exu_dec_qual_lsu_d = _T_80 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 636:32] + assign io_decode_exu_dec_i0_select_pc_d = _T_80 ? 1'h0 : i0_dp_raw_pc; // @[dec_decode_ctl.scala 291:36] + assign io_decode_exu_dec_i0_rs1_bypass_en_d = {_T_1064,_T_1063}; // @[dec_decode_ctl.scala 916:45] + assign io_decode_exu_dec_i0_rs2_bypass_en_d = {_T_1079,_T_1078}; // @[dec_decode_ctl.scala 917:45] + assign io_decode_exu_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 471:32] + assign io_decode_exu_mul_p_bits_rs1_sign = _T_80 ? 1'h0 : i0_dp_raw_rs1_sign; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 472:37] + assign io_decode_exu_mul_p_bits_rs2_sign = _T_80 ? 1'h0 : i0_dp_raw_rs2_sign; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 473:37] + assign io_decode_exu_mul_p_bits_low = _T_80 ? 1'h0 : i0_dp_raw_low; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 474:37] + assign io_decode_exu_mul_p_bits_bext = _T_80 ? 1'h0 : i0_dp_raw_bext; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 475:37] + assign io_decode_exu_mul_p_bits_bdep = _T_80 ? 1'h0 : i0_dp_raw_bdep; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 476:37] + assign io_decode_exu_mul_p_bits_clmul = _T_80 ? 1'h0 : i0_dp_raw_clmul; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 477:37] + assign io_decode_exu_mul_p_bits_clmulh = _T_80 ? 1'h0 : i0_dp_raw_clmulh; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 478:37] + assign io_decode_exu_mul_p_bits_clmulr = _T_80 ? 1'h0 : i0_dp_raw_clmulr; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 479:37] + assign io_decode_exu_mul_p_bits_grev = _T_80 ? 1'h0 : i0_dp_raw_grev; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 480:37] + assign io_decode_exu_mul_p_bits_gorc = _T_80 ? 1'h0 : i0_dp_raw_gorc; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 481:37] + assign io_decode_exu_mul_p_bits_shfl = _T_80 ? 1'h0 : i0_dp_raw_shfl; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 482:37] + assign io_decode_exu_mul_p_bits_unshfl = _T_80 ? 1'h0 : i0_dp_raw_unshfl; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 483:37] + assign io_decode_exu_mul_p_bits_crc32_b = _T_80 ? 1'h0 : i0_dp_raw_crc32_b; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 484:37] + assign io_decode_exu_mul_p_bits_crc32_h = _T_80 ? 1'h0 : i0_dp_raw_crc32_h; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 485:37] + assign io_decode_exu_mul_p_bits_crc32_w = _T_80 ? 1'h0 : i0_dp_raw_crc32_w; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 486:37] + assign io_decode_exu_mul_p_bits_crc32c_b = _T_80 ? 1'h0 : i0_dp_raw_crc32c_b; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 487:37] + assign io_decode_exu_mul_p_bits_crc32c_h = _T_80 ? 1'h0 : i0_dp_raw_crc32c_h; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 488:37] + assign io_decode_exu_mul_p_bits_crc32c_w = _T_80 ? 1'h0 : i0_dp_raw_crc32c_w; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 489:37] + assign io_decode_exu_mul_p_bits_bfp = _T_80 ? 1'h0 : i0_dp_raw_bfp; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 490:37] + assign io_decode_exu_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[dec_decode_ctl.scala 877:36] + assign io_decode_exu_dec_extint_stall = _T_12; // @[dec_decode_ctl.scala 208:35] + assign io_dec_alu_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[dec_decode_ctl.scala 630:34] + assign io_dec_alu_dec_csr_ren_d = i0_dp_csr_read & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 516:29] + assign io_dec_alu_dec_i0_br_immed_d = _T_885 ? i0_br_offset : _T_898; // @[dec_decode_ctl.scala 823:32] + assign io_dec_div_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 467:29] + assign io_dec_div_div_p_bits_unsign = _T_80 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 468:34] + assign io_dec_div_div_p_bits_rem = _T_80 ? 1'h0 : i0_dp_raw_rem; // @[dec_decode_ctl.scala 469:34] + assign io_dec_div_dec_div_cancel = _T_927 | _T_932; // @[dec_decode_ctl.scala 842:37] + assign io_dec_aln_dec_i0_decode_d = _T_589 & _T_567; // @[dec_decode_ctl.scala 611:30 dec_decode_ctl.scala 674:30] + assign io_dec_i0_inst_wb = i0_inst_wb; // @[dec_decode_ctl.scala 868:21] + assign io_dec_i0_pc_wb = i0_pc_wb; // @[dec_decode_ctl.scala 869:19] + assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 683:19] + assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 684:19] + assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[dec_decode_ctl.scala 805:27] + assign io_dec_i0_wen_r = _T_871 & _T_872; // @[dec_decode_ctl.scala 807:32] + assign io_dec_i0_wdata_r = _T_881 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 808:26] + assign io_lsu_p_valid = io_decode_exu_dec_extint_stall | lsu_decode_d; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 498:24 dec_decode_ctl.scala 502:35] + assign io_lsu_p_bits_fast_int = io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 497:29] + assign io_lsu_p_bits_stack = io_decode_exu_dec_extint_stall ? 1'h0 : _T_425; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 508:29] + assign io_lsu_p_bits_by = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_by; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 505:40] + assign io_lsu_p_bits_half = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_half; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 506:40] + assign io_lsu_p_bits_word = io_decode_exu_dec_extint_stall | i0_dp_word; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 496:29 dec_decode_ctl.scala 507:40] + assign io_lsu_p_bits_load = io_decode_exu_dec_extint_stall | i0_dp_load; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 495:29 dec_decode_ctl.scala 503:40] + assign io_lsu_p_bits_store = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_store; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 504:40] + assign io_lsu_p_bits_unsign = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 512:40] + assign io_lsu_p_bits_store_data_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 510:40] + assign io_lsu_p_bits_load_ldst_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 509:40] + assign io_div_waddr_wb = _T_947; // @[dec_decode_ctl.scala 860:19] + assign io_dec_lsu_valid_raw_d = _T_1086 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 921:26] + assign io_dec_lsu_offset_d = _T_1100 | _T_1101; // @[dec_decode_ctl.scala 922:23] + assign io_dec_csr_wen_unq_d = _T_436 & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 525:24] + assign io_dec_csr_any_unq_d = any_csr_d & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 528:24] + assign io_dec_csr_rdaddr_d = _T_440 & io_dec_i0_instr_d[31:20]; // @[dec_decode_ctl.scala 529:24] + assign io_dec_csr_wen_r = _T_443 & _T_868; // @[dec_decode_ctl.scala 534:20] + assign io_dec_csr_wraddr_r = _T_445 & r_d_bits_csrwaddr; // @[dec_decode_ctl.scala 530:24] + assign io_dec_csr_wrdata_r = _T_529 ? i0_result_corr_r : write_csr_data; // @[dec_decode_ctl.scala 574:24] + assign io_dec_csr_stall_int_ff = _T_454 & _T_455; // @[dec_decode_ctl.scala 537:27] + assign io_dec_tlu_i0_valid_r = r_d_valid & _T_857; // @[dec_decode_ctl.scala 637:29] + assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_icaf_second = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_second; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_644; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 669:39 dec_decode_ctl.scala 670:39] + assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[dec_decode_ctl.scala 872:27] + assign io_dec_illegal_inst = _T_565; // @[dec_decode_ctl.scala 596:23] + assign io_dec_pmu_instr_decoded = io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 616:28] + assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_597; // @[dec_decode_ctl.scala 617:27] + assign io_dec_pmu_presync_stall = presync_stall & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 619:29] + assign io_dec_pmu_postsync_stall = postsync_stall & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 618:29] + assign io_dec_nonblock_load_wen = _T_279 & _T_280; // @[dec_decode_ctl.scala 399:28] + assign io_dec_nonblock_load_waddr = _T_325 | _T_317; // @[dec_decode_ctl.scala 396:29 dec_decode_ctl.scala 406:29] + assign io_dec_pause_state = pause_stall; // @[dec_decode_ctl.scala 560:22] + assign io_dec_pause_state_cg = pause_stall & _T_519; // @[dec_decode_ctl.scala 562:25] + assign io_dec_div_active = _T_42; // @[dec_decode_ctl.scala 217:35] + assign i0_dec_io_ins = io_dec_i0_instr_d; // @[dec_decode_ctl.scala 439:16] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = i0_x_data_en & any_csr_d; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = i0_x_data_en & any_csr_d; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = _T_527 | pause_stall; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = shift_illegal & _T_564; // @[lib.scala 407:17] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_4_io_en = i0_r_data_en & _T_875; // @[lib.scala 407:17] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_5_io_en = i0_pipe_en[3] | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_6_io_en = i0_legal_decode_d & i0_dp_div; // @[lib.scala 407:17] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_7_io_en = i0_x_data_en & trace_enable; // @[lib.scala 407:17] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_8_io_en = i0_r_data_en & trace_enable; // @[lib.scala 407:17] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_9_io_en = i0_wb_data_en & trace_enable; // @[lib.scala 407:17] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_10_io_en = i0_wb_data_en & trace_enable; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + leak1_i1_stall = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + leak1_i0_stall = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_12 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + pause_stall = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + write_csr_data = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + tlu_wr_pause_r1 = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + tlu_wr_pause_r2 = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + illegal_lockout = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + flush_final_r = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + postsync_stall = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + x_d_valid = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + lsu_trigger_match_r = _RAND_11[3:0]; + _RAND_12 = {1{`RANDOM}}; + lsu_pmu_misaligned_r = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + x_d_bits_i0div = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + x_d_bits_i0rd = _RAND_14[4:0]; + _RAND_15 = {1{`RANDOM}}; + r_d_bits_i0div = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + r_d_valid = _RAND_16[0:0]; + _RAND_17 = {1{`RANDOM}}; + r_d_bits_i0rd = _RAND_17[4:0]; + _RAND_18 = {1{`RANDOM}}; + r_d_bits_i0v = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + _T_42 = _RAND_19[0:0]; + _RAND_20 = {1{`RANDOM}}; + debug_valid_x = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + cam_raw_0_bits_tag = _RAND_21[2:0]; + _RAND_22 = {1{`RANDOM}}; + cam_raw_0_valid = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + cam_raw_1_bits_tag = _RAND_23[2:0]; + _RAND_24 = {1{`RANDOM}}; + cam_raw_1_valid = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + cam_raw_2_bits_tag = _RAND_25[2:0]; + _RAND_26 = {1{`RANDOM}}; + cam_raw_2_valid = _RAND_26[0:0]; + _RAND_27 = {1{`RANDOM}}; + cam_raw_3_bits_tag = _RAND_27[2:0]; + _RAND_28 = {1{`RANDOM}}; + cam_raw_3_valid = _RAND_28[0:0]; + _RAND_29 = {1{`RANDOM}}; + x_d_bits_i0load = _RAND_29[0:0]; + _RAND_30 = {1{`RANDOM}}; + _T_815 = _RAND_30[2:0]; + _RAND_31 = {1{`RANDOM}}; + nonblock_load_valid_m_delay = _RAND_31[0:0]; + _RAND_32 = {1{`RANDOM}}; + r_d_bits_i0load = _RAND_32[0:0]; + _RAND_33 = {1{`RANDOM}}; + cam_raw_0_bits_rd = _RAND_33[4:0]; + _RAND_34 = {1{`RANDOM}}; + cam_raw_0_bits_wb = _RAND_34[0:0]; + _RAND_35 = {1{`RANDOM}}; + cam_raw_1_bits_rd = _RAND_35[4:0]; + _RAND_36 = {1{`RANDOM}}; + cam_raw_1_bits_wb = _RAND_36[0:0]; + _RAND_37 = {1{`RANDOM}}; + cam_raw_2_bits_rd = _RAND_37[4:0]; + _RAND_38 = {1{`RANDOM}}; + cam_raw_2_bits_wb = _RAND_38[0:0]; + _RAND_39 = {1{`RANDOM}}; + cam_raw_3_bits_rd = _RAND_39[4:0]; + _RAND_40 = {1{`RANDOM}}; + cam_raw_3_bits_wb = _RAND_40[0:0]; + _RAND_41 = {1{`RANDOM}}; + lsu_idle = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + x_d_bits_i0v = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + i0_x_c_load = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + i0_r_c_load = _RAND_44[0:0]; + _RAND_45 = {1{`RANDOM}}; + r_d_bits_csrwen = _RAND_45[0:0]; + _RAND_46 = {1{`RANDOM}}; + r_d_bits_csrwaddr = _RAND_46[11:0]; + _RAND_47 = {1{`RANDOM}}; + csr_read_x = _RAND_47[0:0]; + _RAND_48 = {1{`RANDOM}}; + csr_clr_x = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + csr_set_x = _RAND_49[0:0]; + _RAND_50 = {1{`RANDOM}}; + csr_write_x = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + csr_imm_x = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + csrimm_x = _RAND_52[4:0]; + _RAND_53 = {1{`RANDOM}}; + csr_rddata_x = _RAND_53[31:0]; + _RAND_54 = {1{`RANDOM}}; + r_d_bits_csrwonly = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + i0_result_r_raw = _RAND_55[31:0]; + _RAND_56 = {1{`RANDOM}}; + x_d_bits_csrwonly = _RAND_56[0:0]; + _RAND_57 = {1{`RANDOM}}; + wbd_bits_csrwonly = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + _T_565 = _RAND_58[31:0]; + _RAND_59 = {1{`RANDOM}}; + x_t_legal = _RAND_59[0:0]; + _RAND_60 = {1{`RANDOM}}; + x_t_icaf = _RAND_60[0:0]; + _RAND_61 = {1{`RANDOM}}; + x_t_icaf_second = _RAND_61[0:0]; + _RAND_62 = {1{`RANDOM}}; + x_t_icaf_type = _RAND_62[1:0]; + _RAND_63 = {1{`RANDOM}}; + x_t_fence_i = _RAND_63[0:0]; + _RAND_64 = {1{`RANDOM}}; + x_t_i0trigger = _RAND_64[3:0]; + _RAND_65 = {1{`RANDOM}}; + x_t_pmu_i0_itype = _RAND_65[3:0]; + _RAND_66 = {1{`RANDOM}}; + x_t_pmu_i0_br_unpred = _RAND_66[0:0]; + _RAND_67 = {1{`RANDOM}}; + r_t_legal = _RAND_67[0:0]; + _RAND_68 = {1{`RANDOM}}; + r_t_icaf = _RAND_68[0:0]; + _RAND_69 = {1{`RANDOM}}; + r_t_icaf_second = _RAND_69[0:0]; + _RAND_70 = {1{`RANDOM}}; + r_t_icaf_type = _RAND_70[1:0]; + _RAND_71 = {1{`RANDOM}}; + r_t_fence_i = _RAND_71[0:0]; + _RAND_72 = {1{`RANDOM}}; + r_t_i0trigger = _RAND_72[3:0]; + _RAND_73 = {1{`RANDOM}}; + r_t_pmu_i0_itype = _RAND_73[3:0]; + _RAND_74 = {1{`RANDOM}}; + r_t_pmu_i0_br_unpred = _RAND_74[0:0]; + _RAND_75 = {1{`RANDOM}}; + r_d_bits_i0store = _RAND_75[0:0]; + _RAND_76 = {1{`RANDOM}}; + i0_x_c_mul = _RAND_76[0:0]; + _RAND_77 = {1{`RANDOM}}; + i0_x_c_alu = _RAND_77[0:0]; + _RAND_78 = {1{`RANDOM}}; + i0_r_c_mul = _RAND_78[0:0]; + _RAND_79 = {1{`RANDOM}}; + i0_r_c_alu = _RAND_79[0:0]; + _RAND_80 = {1{`RANDOM}}; + x_d_bits_i0store = _RAND_80[0:0]; + _RAND_81 = {1{`RANDOM}}; + x_d_bits_csrwen = _RAND_81[0:0]; + _RAND_82 = {1{`RANDOM}}; + x_d_bits_csrwaddr = _RAND_82[11:0]; + _RAND_83 = {1{`RANDOM}}; + last_br_immed_x = _RAND_83[11:0]; + _RAND_84 = {1{`RANDOM}}; + _T_947 = _RAND_84[4:0]; + _RAND_85 = {1{`RANDOM}}; + i0_inst_x = _RAND_85[31:0]; + _RAND_86 = {1{`RANDOM}}; + i0_inst_r = _RAND_86[31:0]; + _RAND_87 = {1{`RANDOM}}; + i0_inst_wb = _RAND_87[31:0]; + _RAND_88 = {1{`RANDOM}}; + i0_pc_wb = _RAND_88[30:0]; + _RAND_89 = {1{`RANDOM}}; + dec_i0_pc_r = _RAND_89[30:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + leak1_i1_stall = 1'h0; + end + if (reset) begin + leak1_i0_stall = 1'h0; + end + if (reset) begin + _T_12 = 1'h0; + end + if (reset) begin + pause_stall = 1'h0; + end + if (reset) begin + write_csr_data = 32'h0; + end + if (reset) begin + tlu_wr_pause_r1 = 1'h0; + end + if (reset) begin + tlu_wr_pause_r2 = 1'h0; + end + if (reset) begin + illegal_lockout = 1'h0; + end + if (reset) begin + flush_final_r = 1'h0; + end + if (reset) begin + postsync_stall = 1'h0; + end + if (reset) begin + x_d_valid = 1'h0; + end + if (reset) begin + lsu_trigger_match_r = 4'h0; + end + if (reset) begin + lsu_pmu_misaligned_r = 1'h0; + end + if (reset) begin + x_d_bits_i0div = 1'h0; + end + if (reset) begin + x_d_bits_i0rd = 5'h0; + end + if (reset) begin + r_d_bits_i0div = 1'h0; + end + if (reset) begin + r_d_valid = 1'h0; + end + if (reset) begin + r_d_bits_i0rd = 5'h0; + end + if (reset) begin + r_d_bits_i0v = 1'h0; + end + if (reset) begin + _T_42 = 1'h0; + end + if (reset) begin + debug_valid_x = 1'h0; + end + if (reset) begin + cam_raw_0_bits_tag = 3'h0; + end + if (reset) begin + cam_raw_0_valid = 1'h0; + end + if (reset) begin + cam_raw_1_bits_tag = 3'h0; + end + if (reset) begin + cam_raw_1_valid = 1'h0; + end + if (reset) begin + cam_raw_2_bits_tag = 3'h0; + end + if (reset) begin + cam_raw_2_valid = 1'h0; + end + if (reset) begin + cam_raw_3_bits_tag = 3'h0; + end + if (reset) begin + cam_raw_3_valid = 1'h0; + end + if (reset) begin + x_d_bits_i0load = 1'h0; + end + if (reset) begin + _T_815 = 3'h0; + end + if (reset) begin + nonblock_load_valid_m_delay = 1'h0; + end + if (reset) begin + r_d_bits_i0load = 1'h0; + end + if (reset) begin + cam_raw_0_bits_rd = 5'h0; + end + if (reset) begin + cam_raw_0_bits_wb = 1'h0; + end + if (reset) begin + cam_raw_1_bits_rd = 5'h0; + end + if (reset) begin + cam_raw_1_bits_wb = 1'h0; + end + if (reset) begin + cam_raw_2_bits_rd = 5'h0; + end + if (reset) begin + cam_raw_2_bits_wb = 1'h0; + end + if (reset) begin + cam_raw_3_bits_rd = 5'h0; + end + if (reset) begin + cam_raw_3_bits_wb = 1'h0; + end + if (reset) begin + lsu_idle = 1'h0; + end + if (reset) begin + x_d_bits_i0v = 1'h0; + end + if (reset) begin + i0_x_c_load = 1'h0; + end + if (reset) begin + i0_r_c_load = 1'h0; + end + if (reset) begin + r_d_bits_csrwen = 1'h0; + end + if (reset) begin + r_d_bits_csrwaddr = 12'h0; + end + if (reset) begin + csr_read_x = 1'h0; + end + if (reset) begin + csr_clr_x = 1'h0; + end + if (reset) begin + csr_set_x = 1'h0; + end + if (reset) begin + csr_write_x = 1'h0; + end + if (reset) begin + csr_imm_x = 1'h0; + end + if (reset) begin + csrimm_x = 5'h0; + end + if (reset) begin + csr_rddata_x = 32'h0; + end + if (reset) begin + r_d_bits_csrwonly = 1'h0; + end + if (reset) begin + i0_result_r_raw = 32'h0; + end + if (reset) begin + x_d_bits_csrwonly = 1'h0; + end + if (reset) begin + wbd_bits_csrwonly = 1'h0; + end + if (reset) begin + _T_565 = 32'h0; + end + if (reset) begin + x_t_legal = 1'h0; + end + if (reset) begin + x_t_icaf = 1'h0; + end + if (reset) begin + x_t_icaf_second = 1'h0; + end + if (reset) begin + x_t_icaf_type = 2'h0; + end + if (reset) begin + x_t_fence_i = 1'h0; + end + if (reset) begin + x_t_i0trigger = 4'h0; + end + if (reset) begin + x_t_pmu_i0_itype = 4'h0; + end + if (reset) begin + x_t_pmu_i0_br_unpred = 1'h0; + end + if (reset) begin + r_t_legal = 1'h0; + end + if (reset) begin + r_t_icaf = 1'h0; + end + if (reset) begin + r_t_icaf_second = 1'h0; + end + if (reset) begin + r_t_icaf_type = 2'h0; + end + if (reset) begin + r_t_fence_i = 1'h0; + end + if (reset) begin + r_t_i0trigger = 4'h0; + end + if (reset) begin + r_t_pmu_i0_itype = 4'h0; + end + if (reset) begin + r_t_pmu_i0_br_unpred = 1'h0; + end + if (reset) begin + r_d_bits_i0store = 1'h0; + end + if (reset) begin + i0_x_c_mul = 1'h0; + end + if (reset) begin + i0_x_c_alu = 1'h0; + end + if (reset) begin + i0_r_c_mul = 1'h0; + end + if (reset) begin + i0_r_c_alu = 1'h0; + end + if (reset) begin + x_d_bits_i0store = 1'h0; + end + if (reset) begin + x_d_bits_csrwen = 1'h0; + end + if (reset) begin + x_d_bits_csrwaddr = 12'h0; + end + if (reset) begin + last_br_immed_x = 12'h0; + end + if (reset) begin + _T_947 = 5'h0; + end + if (reset) begin + i0_inst_x = 32'h0; + end + if (reset) begin + i0_inst_r = 32'h0; + end + if (reset) begin + i0_inst_wb = 32'h0; + end + if (reset) begin + i0_pc_wb = 31'h0; + end + if (reset) begin + dec_i0_pc_r = 31'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + leak1_i1_stall <= 1'h0; + end else if (_T_3) begin + leak1_i1_stall <= leak1_i1_stall_in; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + leak1_i0_stall <= 1'h0; + end else if (_T_7) begin + leak1_i0_stall <= leak1_i0_stall_in; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_12 <= 1'h0; + end else if (_T_11) begin + _T_12 <= io_dec_tlu_flush_extint; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + pause_stall <= 1'h0; + end else if (_T_15) begin + pause_stall <= pause_state_in; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + write_csr_data <= 32'h0; + end else if (csr_data_wen) begin + if (pause_stall) begin + write_csr_data <= _T_522; + end else if (io_dec_tlu_wr_pause_r) begin + write_csr_data <= io_dec_csr_wrdata_r; + end else begin + write_csr_data <= write_csr_data_x; + end + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + tlu_wr_pause_r1 <= 1'h0; + end else if (_T_19) begin + tlu_wr_pause_r1 <= io_dec_tlu_wr_pause_r; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + tlu_wr_pause_r2 <= 1'h0; + end else if (_T_23) begin + tlu_wr_pause_r2 <= tlu_wr_pause_r1; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + illegal_lockout <= 1'h0; + end else if (_T_27) begin + illegal_lockout <= illegal_lockout_in; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + flush_final_r <= 1'h0; + end else if (_T_45) begin + flush_final_r <= io_exu_flush_final; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + postsync_stall <= 1'h0; + end else if (_T_31) begin + postsync_stall <= ps_stall_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_d_valid <= 1'h0; + end else if (i0_x_ctl_en) begin + x_d_valid <= io_dec_aln_dec_i0_decode_d; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + lsu_trigger_match_r <= 4'h0; + end else if (_T_34) begin + lsu_trigger_match_r <= io_lsu_trigger_match_m; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + lsu_pmu_misaligned_r <= 1'h0; + end else if (_T_37) begin + lsu_pmu_misaligned_r <= io_lsu_pmu_misaligned_m; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_d_bits_i0div <= 1'h0; + end else if (i0_x_ctl_en) begin + x_d_bits_i0div <= d_d_bits_i0div; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_d_bits_i0rd <= 5'h0; + end else if (i0_x_ctl_en) begin + x_d_bits_i0rd <= i0r_rd; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_d_bits_i0div <= 1'h0; + end else if (i0_r_ctl_en) begin + r_d_bits_i0div <= x_d_bits_i0div; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_d_valid <= 1'h0; + end else if (i0_r_ctl_en) begin + r_d_valid <= x_d_in_valid; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_d_bits_i0rd <= 5'h0; + end else if (i0_r_ctl_en) begin + r_d_bits_i0rd <= x_d_bits_i0rd; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_d_bits_i0v <= 1'h0; + end else if (i0_r_ctl_en) begin + r_d_bits_i0v <= x_d_in_bits_i0v; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_42 <= 1'h0; + end else if (_T_41) begin + _T_42 <= div_active_in; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + debug_valid_x <= 1'h0; + end else if (_T_48) begin + debug_valid_x <= io_dec_debug_valid_d; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_0_bits_tag <= 3'h0; + end else if (_T_161) begin + if (cam_wen[0]) begin + cam_raw_0_bits_tag <= {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m}; + end else if (_T_146) begin + cam_raw_0_bits_tag <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_0_valid <= 1'h0; + end else if (_T_161) begin + if (io_dec_tlu_force_halt) begin + cam_raw_0_valid <= 1'h0; + end else begin + cam_raw_0_valid <= _GEN_114; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_1_bits_tag <= 3'h0; + end else if (_T_197) begin + if (cam_wen[1]) begin + cam_raw_1_bits_tag <= {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m}; + end else if (_T_182) begin + cam_raw_1_bits_tag <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_1_valid <= 1'h0; + end else if (_T_197) begin + if (io_dec_tlu_force_halt) begin + cam_raw_1_valid <= 1'h0; + end else begin + cam_raw_1_valid <= _GEN_129; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_2_bits_tag <= 3'h0; + end else if (_T_233) begin + if (cam_wen[2]) begin + cam_raw_2_bits_tag <= {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m}; + end else if (_T_218) begin + cam_raw_2_bits_tag <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_2_valid <= 1'h0; + end else if (_T_233) begin + if (io_dec_tlu_force_halt) begin + cam_raw_2_valid <= 1'h0; + end else begin + cam_raw_2_valid <= _GEN_144; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_3_bits_tag <= 3'h0; + end else if (_T_269) begin + if (cam_wen[3]) begin + cam_raw_3_bits_tag <= {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m}; + end else if (_T_254) begin + cam_raw_3_bits_tag <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_3_valid <= 1'h0; + end else if (_T_269) begin + if (io_dec_tlu_force_halt) begin + cam_raw_3_valid <= 1'h0; + end else begin + cam_raw_3_valid <= _GEN_159; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_d_bits_i0load <= 1'h0; + end else if (i0_x_ctl_en) begin + x_d_bits_i0load <= i0_d_c_load; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_815 <= 3'h0; + end else begin + _T_815 <= i0_pipe_en[3:1]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + nonblock_load_valid_m_delay <= 1'h0; + end else if (i0_r_ctl_en) begin + nonblock_load_valid_m_delay <= io_dctl_busbuff_lsu_nonblock_load_valid_m; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_d_bits_i0load <= 1'h0; + end else if (i0_r_ctl_en) begin + r_d_bits_i0load <= x_d_bits_i0load; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_0_bits_rd <= 5'h0; + end else if (_T_161) begin + if (cam_wen[0]) begin + if (x_d_bits_i0load) begin + cam_raw_0_bits_rd <= x_d_bits_i0rd; + end else begin + cam_raw_0_bits_rd <= 5'h0; + end + end else if (_T_146) begin + cam_raw_0_bits_rd <= 5'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_0_bits_wb <= 1'h0; + end else if (_T_161) begin + cam_raw_0_bits_wb <= cam_in_0_bits_wb; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_1_bits_rd <= 5'h0; + end else if (_T_197) begin + if (cam_wen[1]) begin + if (x_d_bits_i0load) begin + cam_raw_1_bits_rd <= x_d_bits_i0rd; + end else begin + cam_raw_1_bits_rd <= 5'h0; + end + end else if (_T_182) begin + cam_raw_1_bits_rd <= 5'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_1_bits_wb <= 1'h0; + end else if (_T_197) begin + cam_raw_1_bits_wb <= cam_in_1_bits_wb; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_2_bits_rd <= 5'h0; + end else if (_T_233) begin + if (cam_wen[2]) begin + if (x_d_bits_i0load) begin + cam_raw_2_bits_rd <= x_d_bits_i0rd; + end else begin + cam_raw_2_bits_rd <= 5'h0; + end + end else if (_T_218) begin + cam_raw_2_bits_rd <= 5'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_2_bits_wb <= 1'h0; + end else if (_T_233) begin + cam_raw_2_bits_wb <= cam_in_2_bits_wb; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_3_bits_rd <= 5'h0; + end else if (_T_269) begin + if (cam_wen[3]) begin + if (x_d_bits_i0load) begin + cam_raw_3_bits_rd <= x_d_bits_i0rd; + end else begin + cam_raw_3_bits_rd <= 5'h0; + end + end else if (_T_254) begin + cam_raw_3_bits_rd <= 5'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_3_bits_wb <= 1'h0; + end else if (_T_269) begin + cam_raw_3_bits_wb <= cam_in_3_bits_wb; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + lsu_idle <= 1'h0; + end else begin + lsu_idle <= io_lsu_idle_any; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_d_bits_i0v <= 1'h0; + end else if (i0_x_ctl_en) begin + x_d_bits_i0v <= d_d_bits_i0v; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + i0_x_c_load <= 1'h0; + end else if (i0_x_ctl_en) begin + i0_x_c_load <= i0_d_c_load; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + i0_r_c_load <= 1'h0; + end else if (i0_r_ctl_en) begin + i0_r_c_load <= i0_x_c_load; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_d_bits_csrwen <= 1'h0; + end else if (i0_r_ctl_en) begin + r_d_bits_csrwen <= x_d_bits_csrwen; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_d_bits_csrwaddr <= 12'h0; + end else if (i0_r_ctl_en) begin + r_d_bits_csrwaddr <= x_d_bits_csrwaddr; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_read_x <= 1'h0; + end else begin + csr_read_x <= i0_dp_csr_read & i0_legal_decode_d; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_clr_x <= 1'h0; + end else begin + csr_clr_x <= i0_dp_csr_clr & i0_legal_decode_d; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_set_x <= 1'h0; + end else begin + csr_set_x <= i0_dp_csr_set & i0_legal_decode_d; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_write_x <= 1'h0; + end else begin + csr_write_x <= i0_csr_write & i0_legal_decode_d; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_imm_x <= 1'h0; + end else if (_T_80) begin + csr_imm_x <= 1'h0; + end else begin + csr_imm_x <= i0_dp_raw_csr_imm; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + csrimm_x <= 5'h0; + end else if (_T_459) begin + csrimm_x <= i0r_rs1; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + csr_rddata_x <= 32'h0; + end else if (_T_459) begin + csr_rddata_x <= io_dec_csr_rddata_d; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_d_bits_csrwonly <= 1'h0; + end else if (i0_r_ctl_en) begin + r_d_bits_csrwonly <= x_d_bits_csrwonly; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + i0_result_r_raw <= 32'h0; + end else if (_T_876) begin + if (_T_878) begin + i0_result_r_raw <= io_lsu_result_m; + end else begin + i0_result_r_raw <= io_decode_exu_exu_i0_result_x; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_d_bits_csrwonly <= 1'h0; + end else if (i0_x_ctl_en) begin + x_d_bits_csrwonly <= d_d_bits_csrwonly; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + wbd_bits_csrwonly <= 1'h0; + end else if (i0_wb_ctl_en) begin + wbd_bits_csrwonly <= r_d_bits_csrwonly; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_565 <= 32'h0; + end else if (illegal_inst_en) begin + if (io_dec_i0_pc4_d) begin + _T_565 <= io_dec_i0_instr_d; + end else begin + _T_565 <= _T_562; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_t_legal <= 1'h0; + end else if (i0_x_ctl_en) begin + x_t_legal <= i0_legal_decode_d; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_t_icaf <= 1'h0; + end else if (i0_x_ctl_en) begin + x_t_icaf <= d_t_icaf; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_t_icaf_second <= 1'h0; + end else if (i0_x_ctl_en) begin + x_t_icaf_second <= d_t_icaf_second; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_t_icaf_type <= 2'h0; + end else if (i0_x_ctl_en) begin + x_t_icaf_type <= io_dec_i0_icaf_type_d; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_t_fence_i <= 1'h0; + end else if (i0_x_ctl_en) begin + x_t_fence_i <= d_t_fence_i; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_t_i0trigger <= 4'h0; + end else if (i0_x_ctl_en) begin + x_t_i0trigger <= d_t_i0trigger; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_t_pmu_i0_itype <= 4'h0; + end else if (i0_x_ctl_en) begin + x_t_pmu_i0_itype <= d_t_pmu_i0_itype; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_t_pmu_i0_br_unpred <= 1'h0; + end else if (i0_x_ctl_en) begin + x_t_pmu_i0_br_unpred <= i0_br_unpred; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_t_legal <= 1'h0; + end else if (i0_x_ctl_en) begin + r_t_legal <= x_t_legal; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_t_icaf <= 1'h0; + end else if (i0_x_ctl_en) begin + r_t_icaf <= x_t_icaf; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_t_icaf_second <= 1'h0; + end else if (i0_x_ctl_en) begin + r_t_icaf_second <= x_t_icaf_second; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_t_icaf_type <= 2'h0; + end else if (i0_x_ctl_en) begin + r_t_icaf_type <= x_t_icaf_type; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_t_fence_i <= 1'h0; + end else if (i0_x_ctl_en) begin + r_t_fence_i <= x_t_fence_i; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_t_i0trigger <= 4'h0; + end else if (i0_x_ctl_en) begin + r_t_i0trigger <= x_t_in_i0trigger; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_t_pmu_i0_itype <= 4'h0; + end else if (i0_x_ctl_en) begin + r_t_pmu_i0_itype <= x_t_pmu_i0_itype; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_t_pmu_i0_br_unpred <= 1'h0; + end else if (i0_x_ctl_en) begin + r_t_pmu_i0_br_unpred <= x_t_pmu_i0_br_unpred; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_d_bits_i0store <= 1'h0; + end else if (i0_r_ctl_en) begin + r_d_bits_i0store <= x_d_bits_i0store; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + i0_x_c_mul <= 1'h0; + end else if (i0_x_ctl_en) begin + i0_x_c_mul <= i0_d_c_mul; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + i0_x_c_alu <= 1'h0; + end else if (i0_x_ctl_en) begin + i0_x_c_alu <= i0_d_c_alu; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + i0_r_c_mul <= 1'h0; + end else if (i0_r_ctl_en) begin + i0_r_c_mul <= i0_x_c_mul; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + i0_r_c_alu <= 1'h0; + end else if (i0_r_ctl_en) begin + i0_r_c_alu <= i0_x_c_alu; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_d_bits_i0store <= 1'h0; + end else if (i0_x_ctl_en) begin + x_d_bits_i0store <= d_d_bits_i0store; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_d_bits_csrwen <= 1'h0; + end else if (i0_x_ctl_en) begin + x_d_bits_csrwen <= d_d_bits_csrwen; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_d_bits_csrwaddr <= 12'h0; + end else if (i0_x_ctl_en) begin + if (d_d_bits_csrwen) begin + x_d_bits_csrwaddr <= io_dec_i0_instr_d[31:20]; + end else begin + x_d_bits_csrwaddr <= 12'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + last_br_immed_x <= 12'h0; + end else if (i0_x_data_en) begin + if (io_decode_exu_i0_ap_predict_nt) begin + last_br_immed_x <= _T_898; + end else if (_T_399) begin + last_br_immed_x <= i0_pcall_imm[11:0]; + end else begin + last_br_immed_x <= _T_408; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_947 <= 5'h0; + end else if (i0_div_decode_d) begin + _T_947 <= i0r_rd; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + i0_inst_x <= 32'h0; + end else if (_T_948) begin + if (io_dec_i0_pc4_d) begin + i0_inst_x <= io_dec_i0_instr_d; + end else begin + i0_inst_x <= _T_562; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + i0_inst_r <= 32'h0; + end else if (_T_950) begin + i0_inst_r <= i0_inst_x; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + i0_inst_wb <= 32'h0; + end else if (_T_952) begin + i0_inst_wb <= i0_inst_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + i0_pc_wb <= 31'h0; + end else if (_T_952) begin + i0_pc_wb <= io_dec_tlu_i0_pc_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + dec_i0_pc_r <= 31'h0; + end else if (i0_r_data_en) begin + dec_i0_pc_r <= io_dec_alu_exu_i0_pc_x; + end + end +endmodule +module dec_gpr_ctl( + input clock, + input reset, + input [4:0] io_raddr0, + input [4:0] io_raddr1, + input io_wen0, + input [4:0] io_waddr0, + input [31:0] io_wd0, + input io_wen1, + input [4:0] io_waddr1, + input [31:0] io_wd1, + input io_wen2, + input [4:0] io_waddr2, + input [31:0] io_wd2, + output [31:0] io_gpr_exu_gpr_i0_rs1_d, + output [31:0] io_gpr_exu_gpr_i0_rs2_d +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_4_io_en; // @[lib.scala 404:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_5_io_en; // @[lib.scala 404:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_6_io_en; // @[lib.scala 404:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_7_io_en; // @[lib.scala 404:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_8_io_en; // @[lib.scala 404:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_9_io_en; // @[lib.scala 404:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_10_io_en; // @[lib.scala 404:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_11_io_en; // @[lib.scala 404:23] + wire rvclkhdr_12_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_12_io_en; // @[lib.scala 404:23] + wire rvclkhdr_13_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_13_io_en; // @[lib.scala 404:23] + wire rvclkhdr_14_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_14_io_en; // @[lib.scala 404:23] + wire rvclkhdr_15_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_15_io_en; // @[lib.scala 404:23] + wire rvclkhdr_16_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_16_io_en; // @[lib.scala 404:23] + wire rvclkhdr_17_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_17_io_en; // @[lib.scala 404:23] + wire rvclkhdr_18_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_18_io_en; // @[lib.scala 404:23] + wire rvclkhdr_19_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_19_io_en; // @[lib.scala 404:23] + wire rvclkhdr_20_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_20_io_en; // @[lib.scala 404:23] + wire rvclkhdr_21_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_21_io_en; // @[lib.scala 404:23] + wire rvclkhdr_22_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_22_io_en; // @[lib.scala 404:23] + wire rvclkhdr_23_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_23_io_en; // @[lib.scala 404:23] + wire rvclkhdr_24_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_24_io_en; // @[lib.scala 404:23] + wire rvclkhdr_25_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_25_io_en; // @[lib.scala 404:23] + wire rvclkhdr_26_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_26_io_en; // @[lib.scala 404:23] + wire rvclkhdr_27_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_27_io_en; // @[lib.scala 404:23] + wire rvclkhdr_28_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_28_io_en; // @[lib.scala 404:23] + wire rvclkhdr_29_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_29_io_en; // @[lib.scala 404:23] + wire rvclkhdr_30_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_30_io_en; // @[lib.scala 404:23] + wire _T = io_waddr0 == 5'h1; // @[dec_gpr_ctl.scala 52:52] + wire w0v_1 = io_wen0 & _T; // @[dec_gpr_ctl.scala 52:40] + wire _T_2 = io_waddr1 == 5'h1; // @[dec_gpr_ctl.scala 53:52] + wire w1v_1 = io_wen1 & _T_2; // @[dec_gpr_ctl.scala 53:40] + wire _T_4 = io_waddr2 == 5'h1; // @[dec_gpr_ctl.scala 54:52] + wire w2v_1 = io_wen2 & _T_4; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_7 = w0v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_8 = _T_7 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_10 = w1v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_11 = _T_10 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_12 = _T_8 | _T_11; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_14 = w2v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_15 = _T_14 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_1 = _T_12 | _T_15; // @[dec_gpr_ctl.scala 55:88] + wire _T_17 = io_waddr0 == 5'h2; // @[dec_gpr_ctl.scala 52:52] + wire w0v_2 = io_wen0 & _T_17; // @[dec_gpr_ctl.scala 52:40] + wire _T_19 = io_waddr1 == 5'h2; // @[dec_gpr_ctl.scala 53:52] + wire w1v_2 = io_wen1 & _T_19; // @[dec_gpr_ctl.scala 53:40] + wire _T_21 = io_waddr2 == 5'h2; // @[dec_gpr_ctl.scala 54:52] + wire w2v_2 = io_wen2 & _T_21; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_24 = w0v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_25 = _T_24 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_27 = w1v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_28 = _T_27 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_29 = _T_25 | _T_28; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_31 = w2v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_32 = _T_31 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_2 = _T_29 | _T_32; // @[dec_gpr_ctl.scala 55:88] + wire _T_34 = io_waddr0 == 5'h3; // @[dec_gpr_ctl.scala 52:52] + wire w0v_3 = io_wen0 & _T_34; // @[dec_gpr_ctl.scala 52:40] + wire _T_36 = io_waddr1 == 5'h3; // @[dec_gpr_ctl.scala 53:52] + wire w1v_3 = io_wen1 & _T_36; // @[dec_gpr_ctl.scala 53:40] + wire _T_38 = io_waddr2 == 5'h3; // @[dec_gpr_ctl.scala 54:52] + wire w2v_3 = io_wen2 & _T_38; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_41 = w0v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_42 = _T_41 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_44 = w1v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_45 = _T_44 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_46 = _T_42 | _T_45; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_48 = w2v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_49 = _T_48 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_3 = _T_46 | _T_49; // @[dec_gpr_ctl.scala 55:88] + wire _T_51 = io_waddr0 == 5'h4; // @[dec_gpr_ctl.scala 52:52] + wire w0v_4 = io_wen0 & _T_51; // @[dec_gpr_ctl.scala 52:40] + wire _T_53 = io_waddr1 == 5'h4; // @[dec_gpr_ctl.scala 53:52] + wire w1v_4 = io_wen1 & _T_53; // @[dec_gpr_ctl.scala 53:40] + wire _T_55 = io_waddr2 == 5'h4; // @[dec_gpr_ctl.scala 54:52] + wire w2v_4 = io_wen2 & _T_55; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_58 = w0v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_59 = _T_58 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_61 = w1v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_62 = _T_61 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_63 = _T_59 | _T_62; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_65 = w2v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_66 = _T_65 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_4 = _T_63 | _T_66; // @[dec_gpr_ctl.scala 55:88] + wire _T_68 = io_waddr0 == 5'h5; // @[dec_gpr_ctl.scala 52:52] + wire w0v_5 = io_wen0 & _T_68; // @[dec_gpr_ctl.scala 52:40] + wire _T_70 = io_waddr1 == 5'h5; // @[dec_gpr_ctl.scala 53:52] + wire w1v_5 = io_wen1 & _T_70; // @[dec_gpr_ctl.scala 53:40] + wire _T_72 = io_waddr2 == 5'h5; // @[dec_gpr_ctl.scala 54:52] + wire w2v_5 = io_wen2 & _T_72; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_75 = w0v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_76 = _T_75 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_78 = w1v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_79 = _T_78 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_80 = _T_76 | _T_79; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_82 = w2v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_83 = _T_82 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_5 = _T_80 | _T_83; // @[dec_gpr_ctl.scala 55:88] + wire _T_85 = io_waddr0 == 5'h6; // @[dec_gpr_ctl.scala 52:52] + wire w0v_6 = io_wen0 & _T_85; // @[dec_gpr_ctl.scala 52:40] + wire _T_87 = io_waddr1 == 5'h6; // @[dec_gpr_ctl.scala 53:52] + wire w1v_6 = io_wen1 & _T_87; // @[dec_gpr_ctl.scala 53:40] + wire _T_89 = io_waddr2 == 5'h6; // @[dec_gpr_ctl.scala 54:52] + wire w2v_6 = io_wen2 & _T_89; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_92 = w0v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_93 = _T_92 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_95 = w1v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_96 = _T_95 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_97 = _T_93 | _T_96; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_99 = w2v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_100 = _T_99 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_6 = _T_97 | _T_100; // @[dec_gpr_ctl.scala 55:88] + wire _T_102 = io_waddr0 == 5'h7; // @[dec_gpr_ctl.scala 52:52] + wire w0v_7 = io_wen0 & _T_102; // @[dec_gpr_ctl.scala 52:40] + wire _T_104 = io_waddr1 == 5'h7; // @[dec_gpr_ctl.scala 53:52] + wire w1v_7 = io_wen1 & _T_104; // @[dec_gpr_ctl.scala 53:40] + wire _T_106 = io_waddr2 == 5'h7; // @[dec_gpr_ctl.scala 54:52] + wire w2v_7 = io_wen2 & _T_106; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_109 = w0v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_110 = _T_109 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_112 = w1v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_113 = _T_112 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_114 = _T_110 | _T_113; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_116 = w2v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_117 = _T_116 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_7 = _T_114 | _T_117; // @[dec_gpr_ctl.scala 55:88] + wire _T_119 = io_waddr0 == 5'h8; // @[dec_gpr_ctl.scala 52:52] + wire w0v_8 = io_wen0 & _T_119; // @[dec_gpr_ctl.scala 52:40] + wire _T_121 = io_waddr1 == 5'h8; // @[dec_gpr_ctl.scala 53:52] + wire w1v_8 = io_wen1 & _T_121; // @[dec_gpr_ctl.scala 53:40] + wire _T_123 = io_waddr2 == 5'h8; // @[dec_gpr_ctl.scala 54:52] + wire w2v_8 = io_wen2 & _T_123; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_126 = w0v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_127 = _T_126 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_129 = w1v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_130 = _T_129 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_131 = _T_127 | _T_130; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_133 = w2v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_134 = _T_133 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_8 = _T_131 | _T_134; // @[dec_gpr_ctl.scala 55:88] + wire _T_136 = io_waddr0 == 5'h9; // @[dec_gpr_ctl.scala 52:52] + wire w0v_9 = io_wen0 & _T_136; // @[dec_gpr_ctl.scala 52:40] + wire _T_138 = io_waddr1 == 5'h9; // @[dec_gpr_ctl.scala 53:52] + wire w1v_9 = io_wen1 & _T_138; // @[dec_gpr_ctl.scala 53:40] + wire _T_140 = io_waddr2 == 5'h9; // @[dec_gpr_ctl.scala 54:52] + wire w2v_9 = io_wen2 & _T_140; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_143 = w0v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_144 = _T_143 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_146 = w1v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_147 = _T_146 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_148 = _T_144 | _T_147; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_150 = w2v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_151 = _T_150 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_9 = _T_148 | _T_151; // @[dec_gpr_ctl.scala 55:88] + wire _T_153 = io_waddr0 == 5'ha; // @[dec_gpr_ctl.scala 52:52] + wire w0v_10 = io_wen0 & _T_153; // @[dec_gpr_ctl.scala 52:40] + wire _T_155 = io_waddr1 == 5'ha; // @[dec_gpr_ctl.scala 53:52] + wire w1v_10 = io_wen1 & _T_155; // @[dec_gpr_ctl.scala 53:40] + wire _T_157 = io_waddr2 == 5'ha; // @[dec_gpr_ctl.scala 54:52] + wire w2v_10 = io_wen2 & _T_157; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_160 = w0v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_161 = _T_160 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_163 = w1v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_164 = _T_163 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_165 = _T_161 | _T_164; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_167 = w2v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_168 = _T_167 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_10 = _T_165 | _T_168; // @[dec_gpr_ctl.scala 55:88] + wire _T_170 = io_waddr0 == 5'hb; // @[dec_gpr_ctl.scala 52:52] + wire w0v_11 = io_wen0 & _T_170; // @[dec_gpr_ctl.scala 52:40] + wire _T_172 = io_waddr1 == 5'hb; // @[dec_gpr_ctl.scala 53:52] + wire w1v_11 = io_wen1 & _T_172; // @[dec_gpr_ctl.scala 53:40] + wire _T_174 = io_waddr2 == 5'hb; // @[dec_gpr_ctl.scala 54:52] + wire w2v_11 = io_wen2 & _T_174; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_177 = w0v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_178 = _T_177 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_180 = w1v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_181 = _T_180 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_182 = _T_178 | _T_181; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_184 = w2v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_185 = _T_184 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_11 = _T_182 | _T_185; // @[dec_gpr_ctl.scala 55:88] + wire _T_187 = io_waddr0 == 5'hc; // @[dec_gpr_ctl.scala 52:52] + wire w0v_12 = io_wen0 & _T_187; // @[dec_gpr_ctl.scala 52:40] + wire _T_189 = io_waddr1 == 5'hc; // @[dec_gpr_ctl.scala 53:52] + wire w1v_12 = io_wen1 & _T_189; // @[dec_gpr_ctl.scala 53:40] + wire _T_191 = io_waddr2 == 5'hc; // @[dec_gpr_ctl.scala 54:52] + wire w2v_12 = io_wen2 & _T_191; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_194 = w0v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_195 = _T_194 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_197 = w1v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_198 = _T_197 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_199 = _T_195 | _T_198; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_201 = w2v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_202 = _T_201 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_12 = _T_199 | _T_202; // @[dec_gpr_ctl.scala 55:88] + wire _T_204 = io_waddr0 == 5'hd; // @[dec_gpr_ctl.scala 52:52] + wire w0v_13 = io_wen0 & _T_204; // @[dec_gpr_ctl.scala 52:40] + wire _T_206 = io_waddr1 == 5'hd; // @[dec_gpr_ctl.scala 53:52] + wire w1v_13 = io_wen1 & _T_206; // @[dec_gpr_ctl.scala 53:40] + wire _T_208 = io_waddr2 == 5'hd; // @[dec_gpr_ctl.scala 54:52] + wire w2v_13 = io_wen2 & _T_208; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_211 = w0v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_212 = _T_211 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_214 = w1v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_215 = _T_214 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_216 = _T_212 | _T_215; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_218 = w2v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_219 = _T_218 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_13 = _T_216 | _T_219; // @[dec_gpr_ctl.scala 55:88] + wire _T_221 = io_waddr0 == 5'he; // @[dec_gpr_ctl.scala 52:52] + wire w0v_14 = io_wen0 & _T_221; // @[dec_gpr_ctl.scala 52:40] + wire _T_223 = io_waddr1 == 5'he; // @[dec_gpr_ctl.scala 53:52] + wire w1v_14 = io_wen1 & _T_223; // @[dec_gpr_ctl.scala 53:40] + wire _T_225 = io_waddr2 == 5'he; // @[dec_gpr_ctl.scala 54:52] + wire w2v_14 = io_wen2 & _T_225; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_228 = w0v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_229 = _T_228 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_231 = w1v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_232 = _T_231 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_233 = _T_229 | _T_232; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_235 = w2v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_236 = _T_235 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_14 = _T_233 | _T_236; // @[dec_gpr_ctl.scala 55:88] + wire _T_238 = io_waddr0 == 5'hf; // @[dec_gpr_ctl.scala 52:52] + wire w0v_15 = io_wen0 & _T_238; // @[dec_gpr_ctl.scala 52:40] + wire _T_240 = io_waddr1 == 5'hf; // @[dec_gpr_ctl.scala 53:52] + wire w1v_15 = io_wen1 & _T_240; // @[dec_gpr_ctl.scala 53:40] + wire _T_242 = io_waddr2 == 5'hf; // @[dec_gpr_ctl.scala 54:52] + wire w2v_15 = io_wen2 & _T_242; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_245 = w0v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_246 = _T_245 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_248 = w1v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_249 = _T_248 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_250 = _T_246 | _T_249; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_252 = w2v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_253 = _T_252 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_15 = _T_250 | _T_253; // @[dec_gpr_ctl.scala 55:88] + wire _T_255 = io_waddr0 == 5'h10; // @[dec_gpr_ctl.scala 52:52] + wire w0v_16 = io_wen0 & _T_255; // @[dec_gpr_ctl.scala 52:40] + wire _T_257 = io_waddr1 == 5'h10; // @[dec_gpr_ctl.scala 53:52] + wire w1v_16 = io_wen1 & _T_257; // @[dec_gpr_ctl.scala 53:40] + wire _T_259 = io_waddr2 == 5'h10; // @[dec_gpr_ctl.scala 54:52] + wire w2v_16 = io_wen2 & _T_259; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_262 = w0v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_263 = _T_262 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_265 = w1v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_266 = _T_265 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_267 = _T_263 | _T_266; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_269 = w2v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_270 = _T_269 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_16 = _T_267 | _T_270; // @[dec_gpr_ctl.scala 55:88] + wire _T_272 = io_waddr0 == 5'h11; // @[dec_gpr_ctl.scala 52:52] + wire w0v_17 = io_wen0 & _T_272; // @[dec_gpr_ctl.scala 52:40] + wire _T_274 = io_waddr1 == 5'h11; // @[dec_gpr_ctl.scala 53:52] + wire w1v_17 = io_wen1 & _T_274; // @[dec_gpr_ctl.scala 53:40] + wire _T_276 = io_waddr2 == 5'h11; // @[dec_gpr_ctl.scala 54:52] + wire w2v_17 = io_wen2 & _T_276; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_279 = w0v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_280 = _T_279 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_282 = w1v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_283 = _T_282 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_284 = _T_280 | _T_283; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_286 = w2v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_287 = _T_286 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_17 = _T_284 | _T_287; // @[dec_gpr_ctl.scala 55:88] + wire _T_289 = io_waddr0 == 5'h12; // @[dec_gpr_ctl.scala 52:52] + wire w0v_18 = io_wen0 & _T_289; // @[dec_gpr_ctl.scala 52:40] + wire _T_291 = io_waddr1 == 5'h12; // @[dec_gpr_ctl.scala 53:52] + wire w1v_18 = io_wen1 & _T_291; // @[dec_gpr_ctl.scala 53:40] + wire _T_293 = io_waddr2 == 5'h12; // @[dec_gpr_ctl.scala 54:52] + wire w2v_18 = io_wen2 & _T_293; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_296 = w0v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_297 = _T_296 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_299 = w1v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_300 = _T_299 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_301 = _T_297 | _T_300; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_303 = w2v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_304 = _T_303 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_18 = _T_301 | _T_304; // @[dec_gpr_ctl.scala 55:88] + wire _T_306 = io_waddr0 == 5'h13; // @[dec_gpr_ctl.scala 52:52] + wire w0v_19 = io_wen0 & _T_306; // @[dec_gpr_ctl.scala 52:40] + wire _T_308 = io_waddr1 == 5'h13; // @[dec_gpr_ctl.scala 53:52] + wire w1v_19 = io_wen1 & _T_308; // @[dec_gpr_ctl.scala 53:40] + wire _T_310 = io_waddr2 == 5'h13; // @[dec_gpr_ctl.scala 54:52] + wire w2v_19 = io_wen2 & _T_310; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_313 = w0v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_314 = _T_313 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_316 = w1v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_317 = _T_316 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_318 = _T_314 | _T_317; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_320 = w2v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_321 = _T_320 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_19 = _T_318 | _T_321; // @[dec_gpr_ctl.scala 55:88] + wire _T_323 = io_waddr0 == 5'h14; // @[dec_gpr_ctl.scala 52:52] + wire w0v_20 = io_wen0 & _T_323; // @[dec_gpr_ctl.scala 52:40] + wire _T_325 = io_waddr1 == 5'h14; // @[dec_gpr_ctl.scala 53:52] + wire w1v_20 = io_wen1 & _T_325; // @[dec_gpr_ctl.scala 53:40] + wire _T_327 = io_waddr2 == 5'h14; // @[dec_gpr_ctl.scala 54:52] + wire w2v_20 = io_wen2 & _T_327; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_330 = w0v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_331 = _T_330 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_333 = w1v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_334 = _T_333 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_335 = _T_331 | _T_334; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_337 = w2v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_338 = _T_337 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_20 = _T_335 | _T_338; // @[dec_gpr_ctl.scala 55:88] + wire _T_340 = io_waddr0 == 5'h15; // @[dec_gpr_ctl.scala 52:52] + wire w0v_21 = io_wen0 & _T_340; // @[dec_gpr_ctl.scala 52:40] + wire _T_342 = io_waddr1 == 5'h15; // @[dec_gpr_ctl.scala 53:52] + wire w1v_21 = io_wen1 & _T_342; // @[dec_gpr_ctl.scala 53:40] + wire _T_344 = io_waddr2 == 5'h15; // @[dec_gpr_ctl.scala 54:52] + wire w2v_21 = io_wen2 & _T_344; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_347 = w0v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_348 = _T_347 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_350 = w1v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_351 = _T_350 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_352 = _T_348 | _T_351; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_354 = w2v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_355 = _T_354 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_21 = _T_352 | _T_355; // @[dec_gpr_ctl.scala 55:88] + wire _T_357 = io_waddr0 == 5'h16; // @[dec_gpr_ctl.scala 52:52] + wire w0v_22 = io_wen0 & _T_357; // @[dec_gpr_ctl.scala 52:40] + wire _T_359 = io_waddr1 == 5'h16; // @[dec_gpr_ctl.scala 53:52] + wire w1v_22 = io_wen1 & _T_359; // @[dec_gpr_ctl.scala 53:40] + wire _T_361 = io_waddr2 == 5'h16; // @[dec_gpr_ctl.scala 54:52] + wire w2v_22 = io_wen2 & _T_361; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_364 = w0v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_365 = _T_364 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_367 = w1v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_368 = _T_367 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_369 = _T_365 | _T_368; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_371 = w2v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_372 = _T_371 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_22 = _T_369 | _T_372; // @[dec_gpr_ctl.scala 55:88] + wire _T_374 = io_waddr0 == 5'h17; // @[dec_gpr_ctl.scala 52:52] + wire w0v_23 = io_wen0 & _T_374; // @[dec_gpr_ctl.scala 52:40] + wire _T_376 = io_waddr1 == 5'h17; // @[dec_gpr_ctl.scala 53:52] + wire w1v_23 = io_wen1 & _T_376; // @[dec_gpr_ctl.scala 53:40] + wire _T_378 = io_waddr2 == 5'h17; // @[dec_gpr_ctl.scala 54:52] + wire w2v_23 = io_wen2 & _T_378; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_381 = w0v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_382 = _T_381 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_384 = w1v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_385 = _T_384 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_386 = _T_382 | _T_385; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_388 = w2v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_389 = _T_388 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_23 = _T_386 | _T_389; // @[dec_gpr_ctl.scala 55:88] + wire _T_391 = io_waddr0 == 5'h18; // @[dec_gpr_ctl.scala 52:52] + wire w0v_24 = io_wen0 & _T_391; // @[dec_gpr_ctl.scala 52:40] + wire _T_393 = io_waddr1 == 5'h18; // @[dec_gpr_ctl.scala 53:52] + wire w1v_24 = io_wen1 & _T_393; // @[dec_gpr_ctl.scala 53:40] + wire _T_395 = io_waddr2 == 5'h18; // @[dec_gpr_ctl.scala 54:52] + wire w2v_24 = io_wen2 & _T_395; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_398 = w0v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_399 = _T_398 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_401 = w1v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_402 = _T_401 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_403 = _T_399 | _T_402; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_405 = w2v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_406 = _T_405 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_24 = _T_403 | _T_406; // @[dec_gpr_ctl.scala 55:88] + wire _T_408 = io_waddr0 == 5'h19; // @[dec_gpr_ctl.scala 52:52] + wire w0v_25 = io_wen0 & _T_408; // @[dec_gpr_ctl.scala 52:40] + wire _T_410 = io_waddr1 == 5'h19; // @[dec_gpr_ctl.scala 53:52] + wire w1v_25 = io_wen1 & _T_410; // @[dec_gpr_ctl.scala 53:40] + wire _T_412 = io_waddr2 == 5'h19; // @[dec_gpr_ctl.scala 54:52] + wire w2v_25 = io_wen2 & _T_412; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_415 = w0v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_416 = _T_415 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_418 = w1v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_419 = _T_418 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_420 = _T_416 | _T_419; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_422 = w2v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_423 = _T_422 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_25 = _T_420 | _T_423; // @[dec_gpr_ctl.scala 55:88] + wire _T_425 = io_waddr0 == 5'h1a; // @[dec_gpr_ctl.scala 52:52] + wire w0v_26 = io_wen0 & _T_425; // @[dec_gpr_ctl.scala 52:40] + wire _T_427 = io_waddr1 == 5'h1a; // @[dec_gpr_ctl.scala 53:52] + wire w1v_26 = io_wen1 & _T_427; // @[dec_gpr_ctl.scala 53:40] + wire _T_429 = io_waddr2 == 5'h1a; // @[dec_gpr_ctl.scala 54:52] + wire w2v_26 = io_wen2 & _T_429; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_432 = w0v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_433 = _T_432 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_435 = w1v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_436 = _T_435 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_437 = _T_433 | _T_436; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_439 = w2v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_440 = _T_439 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_26 = _T_437 | _T_440; // @[dec_gpr_ctl.scala 55:88] + wire _T_442 = io_waddr0 == 5'h1b; // @[dec_gpr_ctl.scala 52:52] + wire w0v_27 = io_wen0 & _T_442; // @[dec_gpr_ctl.scala 52:40] + wire _T_444 = io_waddr1 == 5'h1b; // @[dec_gpr_ctl.scala 53:52] + wire w1v_27 = io_wen1 & _T_444; // @[dec_gpr_ctl.scala 53:40] + wire _T_446 = io_waddr2 == 5'h1b; // @[dec_gpr_ctl.scala 54:52] + wire w2v_27 = io_wen2 & _T_446; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_449 = w0v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_450 = _T_449 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_452 = w1v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_453 = _T_452 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_454 = _T_450 | _T_453; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_456 = w2v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_457 = _T_456 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_27 = _T_454 | _T_457; // @[dec_gpr_ctl.scala 55:88] + wire _T_459 = io_waddr0 == 5'h1c; // @[dec_gpr_ctl.scala 52:52] + wire w0v_28 = io_wen0 & _T_459; // @[dec_gpr_ctl.scala 52:40] + wire _T_461 = io_waddr1 == 5'h1c; // @[dec_gpr_ctl.scala 53:52] + wire w1v_28 = io_wen1 & _T_461; // @[dec_gpr_ctl.scala 53:40] + wire _T_463 = io_waddr2 == 5'h1c; // @[dec_gpr_ctl.scala 54:52] + wire w2v_28 = io_wen2 & _T_463; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_466 = w0v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_467 = _T_466 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_469 = w1v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_470 = _T_469 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_471 = _T_467 | _T_470; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_473 = w2v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_474 = _T_473 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_28 = _T_471 | _T_474; // @[dec_gpr_ctl.scala 55:88] + wire _T_476 = io_waddr0 == 5'h1d; // @[dec_gpr_ctl.scala 52:52] + wire w0v_29 = io_wen0 & _T_476; // @[dec_gpr_ctl.scala 52:40] + wire _T_478 = io_waddr1 == 5'h1d; // @[dec_gpr_ctl.scala 53:52] + wire w1v_29 = io_wen1 & _T_478; // @[dec_gpr_ctl.scala 53:40] + wire _T_480 = io_waddr2 == 5'h1d; // @[dec_gpr_ctl.scala 54:52] + wire w2v_29 = io_wen2 & _T_480; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_483 = w0v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_484 = _T_483 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_486 = w1v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_487 = _T_486 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_488 = _T_484 | _T_487; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_490 = w2v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_491 = _T_490 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_29 = _T_488 | _T_491; // @[dec_gpr_ctl.scala 55:88] + wire _T_493 = io_waddr0 == 5'h1e; // @[dec_gpr_ctl.scala 52:52] + wire w0v_30 = io_wen0 & _T_493; // @[dec_gpr_ctl.scala 52:40] + wire _T_495 = io_waddr1 == 5'h1e; // @[dec_gpr_ctl.scala 53:52] + wire w1v_30 = io_wen1 & _T_495; // @[dec_gpr_ctl.scala 53:40] + wire _T_497 = io_waddr2 == 5'h1e; // @[dec_gpr_ctl.scala 54:52] + wire w2v_30 = io_wen2 & _T_497; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_500 = w0v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_501 = _T_500 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_503 = w1v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_504 = _T_503 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_505 = _T_501 | _T_504; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_507 = w2v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_508 = _T_507 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_30 = _T_505 | _T_508; // @[dec_gpr_ctl.scala 55:88] + wire _T_510 = io_waddr0 == 5'h1f; // @[dec_gpr_ctl.scala 52:52] + wire w0v_31 = io_wen0 & _T_510; // @[dec_gpr_ctl.scala 52:40] + wire _T_512 = io_waddr1 == 5'h1f; // @[dec_gpr_ctl.scala 53:52] + wire w1v_31 = io_wen1 & _T_512; // @[dec_gpr_ctl.scala 53:40] + wire _T_514 = io_waddr2 == 5'h1f; // @[dec_gpr_ctl.scala 54:52] + wire w2v_31 = io_wen2 & _T_514; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_517 = w0v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_518 = _T_517 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_520 = w1v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_521 = _T_520 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_522 = _T_518 | _T_521; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_524 = w2v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_525 = _T_524 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_31 = _T_522 | _T_525; // @[dec_gpr_ctl.scala 55:88] + wire [9:0] _T_535 = {w0v_9,w0v_8,w0v_7,w0v_6,w0v_5,w0v_4,w0v_3,w0v_2,w0v_1,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_544 = {w0v_18,w0v_17,w0v_16,w0v_15,w0v_14,w0v_13,w0v_12,w0v_11,w0v_10,_T_535}; // @[Cat.scala 29:58] + wire [27:0] _T_553 = {w0v_27,w0v_26,w0v_25,w0v_24,w0v_23,w0v_22,w0v_21,w0v_20,w0v_19,_T_544}; // @[Cat.scala 29:58] + wire [31:0] _T_557 = {w0v_31,w0v_30,w0v_29,w0v_28,_T_553}; // @[Cat.scala 29:58] + wire [9:0] _T_566 = {w1v_9,w1v_8,w1v_7,w1v_6,w1v_5,w1v_4,w1v_3,w1v_2,w1v_1,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_575 = {w1v_18,w1v_17,w1v_16,w1v_15,w1v_14,w1v_13,w1v_12,w1v_11,w1v_10,_T_566}; // @[Cat.scala 29:58] + wire [27:0] _T_584 = {w1v_27,w1v_26,w1v_25,w1v_24,w1v_23,w1v_22,w1v_21,w1v_20,w1v_19,_T_575}; // @[Cat.scala 29:58] + wire [31:0] _T_588 = {w1v_31,w1v_30,w1v_29,w1v_28,_T_584}; // @[Cat.scala 29:58] + wire [31:0] _T_589 = _T_557 | _T_588; // @[dec_gpr_ctl.scala 57:57] + wire [9:0] _T_598 = {w2v_9,w2v_8,w2v_7,w2v_6,w2v_5,w2v_4,w2v_3,w2v_2,w2v_1,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_607 = {w2v_18,w2v_17,w2v_16,w2v_15,w2v_14,w2v_13,w2v_12,w2v_11,w2v_10,_T_598}; // @[Cat.scala 29:58] + wire [27:0] _T_616 = {w2v_27,w2v_26,w2v_25,w2v_24,w2v_23,w2v_22,w2v_21,w2v_20,w2v_19,_T_607}; // @[Cat.scala 29:58] + wire [31:0] _T_620 = {w2v_31,w2v_30,w2v_29,w2v_28,_T_616}; // @[Cat.scala 29:58] + wire [31:0] gpr_wr_en = _T_589 | _T_620; // @[dec_gpr_ctl.scala 57:95] + reg [31:0] gpr_out_1; // @[Reg.scala 27:20] + reg [31:0] gpr_out_2; // @[Reg.scala 27:20] + reg [31:0] gpr_out_3; // @[Reg.scala 27:20] + reg [31:0] gpr_out_4; // @[Reg.scala 27:20] + reg [31:0] gpr_out_5; // @[Reg.scala 27:20] + reg [31:0] gpr_out_6; // @[Reg.scala 27:20] + reg [31:0] gpr_out_7; // @[Reg.scala 27:20] + reg [31:0] gpr_out_8; // @[Reg.scala 27:20] + reg [31:0] gpr_out_9; // @[Reg.scala 27:20] + reg [31:0] gpr_out_10; // @[Reg.scala 27:20] + reg [31:0] gpr_out_11; // @[Reg.scala 27:20] + reg [31:0] gpr_out_12; // @[Reg.scala 27:20] + reg [31:0] gpr_out_13; // @[Reg.scala 27:20] + reg [31:0] gpr_out_14; // @[Reg.scala 27:20] + reg [31:0] gpr_out_15; // @[Reg.scala 27:20] + reg [31:0] gpr_out_16; // @[Reg.scala 27:20] + reg [31:0] gpr_out_17; // @[Reg.scala 27:20] + reg [31:0] gpr_out_18; // @[Reg.scala 27:20] + reg [31:0] gpr_out_19; // @[Reg.scala 27:20] + reg [31:0] gpr_out_20; // @[Reg.scala 27:20] + reg [31:0] gpr_out_21; // @[Reg.scala 27:20] + reg [31:0] gpr_out_22; // @[Reg.scala 27:20] + reg [31:0] gpr_out_23; // @[Reg.scala 27:20] + reg [31:0] gpr_out_24; // @[Reg.scala 27:20] + reg [31:0] gpr_out_25; // @[Reg.scala 27:20] + reg [31:0] gpr_out_26; // @[Reg.scala 27:20] + reg [31:0] gpr_out_27; // @[Reg.scala 27:20] + reg [31:0] gpr_out_28; // @[Reg.scala 27:20] + reg [31:0] gpr_out_29; // @[Reg.scala 27:20] + reg [31:0] gpr_out_30; // @[Reg.scala 27:20] + reg [31:0] gpr_out_31; // @[Reg.scala 27:20] + wire _T_684 = io_raddr0 == 5'h1; // @[dec_gpr_ctl.scala 64:72] + wire _T_686 = io_raddr0 == 5'h2; // @[dec_gpr_ctl.scala 64:72] + wire _T_688 = io_raddr0 == 5'h3; // @[dec_gpr_ctl.scala 64:72] + wire _T_690 = io_raddr0 == 5'h4; // @[dec_gpr_ctl.scala 64:72] + wire _T_692 = io_raddr0 == 5'h5; // @[dec_gpr_ctl.scala 64:72] + wire _T_694 = io_raddr0 == 5'h6; // @[dec_gpr_ctl.scala 64:72] + wire _T_696 = io_raddr0 == 5'h7; // @[dec_gpr_ctl.scala 64:72] + wire _T_698 = io_raddr0 == 5'h8; // @[dec_gpr_ctl.scala 64:72] + wire _T_700 = io_raddr0 == 5'h9; // @[dec_gpr_ctl.scala 64:72] + wire _T_702 = io_raddr0 == 5'ha; // @[dec_gpr_ctl.scala 64:72] + wire _T_704 = io_raddr0 == 5'hb; // @[dec_gpr_ctl.scala 64:72] + wire _T_706 = io_raddr0 == 5'hc; // @[dec_gpr_ctl.scala 64:72] + wire _T_708 = io_raddr0 == 5'hd; // @[dec_gpr_ctl.scala 64:72] + wire _T_710 = io_raddr0 == 5'he; // @[dec_gpr_ctl.scala 64:72] + wire _T_712 = io_raddr0 == 5'hf; // @[dec_gpr_ctl.scala 64:72] + wire _T_714 = io_raddr0 == 5'h10; // @[dec_gpr_ctl.scala 64:72] + wire _T_716 = io_raddr0 == 5'h11; // @[dec_gpr_ctl.scala 64:72] + wire _T_718 = io_raddr0 == 5'h12; // @[dec_gpr_ctl.scala 64:72] + wire _T_720 = io_raddr0 == 5'h13; // @[dec_gpr_ctl.scala 64:72] + wire _T_722 = io_raddr0 == 5'h14; // @[dec_gpr_ctl.scala 64:72] + wire _T_724 = io_raddr0 == 5'h15; // @[dec_gpr_ctl.scala 64:72] + wire _T_726 = io_raddr0 == 5'h16; // @[dec_gpr_ctl.scala 64:72] + wire _T_728 = io_raddr0 == 5'h17; // @[dec_gpr_ctl.scala 64:72] + wire _T_730 = io_raddr0 == 5'h18; // @[dec_gpr_ctl.scala 64:72] + wire _T_732 = io_raddr0 == 5'h19; // @[dec_gpr_ctl.scala 64:72] + wire _T_734 = io_raddr0 == 5'h1a; // @[dec_gpr_ctl.scala 64:72] + wire _T_736 = io_raddr0 == 5'h1b; // @[dec_gpr_ctl.scala 64:72] + wire _T_738 = io_raddr0 == 5'h1c; // @[dec_gpr_ctl.scala 64:72] + wire _T_740 = io_raddr0 == 5'h1d; // @[dec_gpr_ctl.scala 64:72] + wire _T_742 = io_raddr0 == 5'h1e; // @[dec_gpr_ctl.scala 64:72] + wire _T_744 = io_raddr0 == 5'h1f; // @[dec_gpr_ctl.scala 64:72] + wire [31:0] _T_746 = _T_684 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_747 = _T_686 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_748 = _T_688 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_749 = _T_690 ? gpr_out_4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_750 = _T_692 ? gpr_out_5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_751 = _T_694 ? gpr_out_6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_752 = _T_696 ? gpr_out_7 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_753 = _T_698 ? gpr_out_8 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_754 = _T_700 ? gpr_out_9 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_755 = _T_702 ? gpr_out_10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_756 = _T_704 ? gpr_out_11 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_757 = _T_706 ? gpr_out_12 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_758 = _T_708 ? gpr_out_13 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_759 = _T_710 ? gpr_out_14 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_760 = _T_712 ? gpr_out_15 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_761 = _T_714 ? gpr_out_16 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_762 = _T_716 ? gpr_out_17 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_763 = _T_718 ? gpr_out_18 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_764 = _T_720 ? gpr_out_19 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_765 = _T_722 ? gpr_out_20 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_766 = _T_724 ? gpr_out_21 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_767 = _T_726 ? gpr_out_22 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_768 = _T_728 ? gpr_out_23 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_769 = _T_730 ? gpr_out_24 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_770 = _T_732 ? gpr_out_25 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_771 = _T_734 ? gpr_out_26 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_772 = _T_736 ? gpr_out_27 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_773 = _T_738 ? gpr_out_28 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_774 = _T_740 ? gpr_out_29 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_775 = _T_742 ? gpr_out_30 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_776 = _T_744 ? gpr_out_31 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_777 = _T_746 | _T_747; // @[Mux.scala 27:72] + wire [31:0] _T_778 = _T_777 | _T_748; // @[Mux.scala 27:72] + wire [31:0] _T_779 = _T_778 | _T_749; // @[Mux.scala 27:72] + wire [31:0] _T_780 = _T_779 | _T_750; // @[Mux.scala 27:72] + wire [31:0] _T_781 = _T_780 | _T_751; // @[Mux.scala 27:72] + wire [31:0] _T_782 = _T_781 | _T_752; // @[Mux.scala 27:72] + wire [31:0] _T_783 = _T_782 | _T_753; // @[Mux.scala 27:72] + wire [31:0] _T_784 = _T_783 | _T_754; // @[Mux.scala 27:72] + wire [31:0] _T_785 = _T_784 | _T_755; // @[Mux.scala 27:72] + wire [31:0] _T_786 = _T_785 | _T_756; // @[Mux.scala 27:72] + wire [31:0] _T_787 = _T_786 | _T_757; // @[Mux.scala 27:72] + wire [31:0] _T_788 = _T_787 | _T_758; // @[Mux.scala 27:72] + wire [31:0] _T_789 = _T_788 | _T_759; // @[Mux.scala 27:72] + wire [31:0] _T_790 = _T_789 | _T_760; // @[Mux.scala 27:72] + wire [31:0] _T_791 = _T_790 | _T_761; // @[Mux.scala 27:72] + wire [31:0] _T_792 = _T_791 | _T_762; // @[Mux.scala 27:72] + wire [31:0] _T_793 = _T_792 | _T_763; // @[Mux.scala 27:72] + wire [31:0] _T_794 = _T_793 | _T_764; // @[Mux.scala 27:72] + wire [31:0] _T_795 = _T_794 | _T_765; // @[Mux.scala 27:72] + wire [31:0] _T_796 = _T_795 | _T_766; // @[Mux.scala 27:72] + wire [31:0] _T_797 = _T_796 | _T_767; // @[Mux.scala 27:72] + wire [31:0] _T_798 = _T_797 | _T_768; // @[Mux.scala 27:72] + wire [31:0] _T_799 = _T_798 | _T_769; // @[Mux.scala 27:72] + wire [31:0] _T_800 = _T_799 | _T_770; // @[Mux.scala 27:72] + wire [31:0] _T_801 = _T_800 | _T_771; // @[Mux.scala 27:72] + wire [31:0] _T_802 = _T_801 | _T_772; // @[Mux.scala 27:72] + wire [31:0] _T_803 = _T_802 | _T_773; // @[Mux.scala 27:72] + wire [31:0] _T_804 = _T_803 | _T_774; // @[Mux.scala 27:72] + wire [31:0] _T_805 = _T_804 | _T_775; // @[Mux.scala 27:72] + wire _T_808 = io_raddr1 == 5'h1; // @[dec_gpr_ctl.scala 65:72] + wire _T_810 = io_raddr1 == 5'h2; // @[dec_gpr_ctl.scala 65:72] + wire _T_812 = io_raddr1 == 5'h3; // @[dec_gpr_ctl.scala 65:72] + wire _T_814 = io_raddr1 == 5'h4; // @[dec_gpr_ctl.scala 65:72] + wire _T_816 = io_raddr1 == 5'h5; // @[dec_gpr_ctl.scala 65:72] + wire _T_818 = io_raddr1 == 5'h6; // @[dec_gpr_ctl.scala 65:72] + wire _T_820 = io_raddr1 == 5'h7; // @[dec_gpr_ctl.scala 65:72] + wire _T_822 = io_raddr1 == 5'h8; // @[dec_gpr_ctl.scala 65:72] + wire _T_824 = io_raddr1 == 5'h9; // @[dec_gpr_ctl.scala 65:72] + wire _T_826 = io_raddr1 == 5'ha; // @[dec_gpr_ctl.scala 65:72] + wire _T_828 = io_raddr1 == 5'hb; // @[dec_gpr_ctl.scala 65:72] + wire _T_830 = io_raddr1 == 5'hc; // @[dec_gpr_ctl.scala 65:72] + wire _T_832 = io_raddr1 == 5'hd; // @[dec_gpr_ctl.scala 65:72] + wire _T_834 = io_raddr1 == 5'he; // @[dec_gpr_ctl.scala 65:72] + wire _T_836 = io_raddr1 == 5'hf; // @[dec_gpr_ctl.scala 65:72] + wire _T_838 = io_raddr1 == 5'h10; // @[dec_gpr_ctl.scala 65:72] + wire _T_840 = io_raddr1 == 5'h11; // @[dec_gpr_ctl.scala 65:72] + wire _T_842 = io_raddr1 == 5'h12; // @[dec_gpr_ctl.scala 65:72] + wire _T_844 = io_raddr1 == 5'h13; // @[dec_gpr_ctl.scala 65:72] + wire _T_846 = io_raddr1 == 5'h14; // @[dec_gpr_ctl.scala 65:72] + wire _T_848 = io_raddr1 == 5'h15; // @[dec_gpr_ctl.scala 65:72] + wire _T_850 = io_raddr1 == 5'h16; // @[dec_gpr_ctl.scala 65:72] + wire _T_852 = io_raddr1 == 5'h17; // @[dec_gpr_ctl.scala 65:72] + wire _T_854 = io_raddr1 == 5'h18; // @[dec_gpr_ctl.scala 65:72] + wire _T_856 = io_raddr1 == 5'h19; // @[dec_gpr_ctl.scala 65:72] + wire _T_858 = io_raddr1 == 5'h1a; // @[dec_gpr_ctl.scala 65:72] + wire _T_860 = io_raddr1 == 5'h1b; // @[dec_gpr_ctl.scala 65:72] + wire _T_862 = io_raddr1 == 5'h1c; // @[dec_gpr_ctl.scala 65:72] + wire _T_864 = io_raddr1 == 5'h1d; // @[dec_gpr_ctl.scala 65:72] + wire _T_866 = io_raddr1 == 5'h1e; // @[dec_gpr_ctl.scala 65:72] + wire _T_868 = io_raddr1 == 5'h1f; // @[dec_gpr_ctl.scala 65:72] + wire [31:0] _T_870 = _T_808 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_871 = _T_810 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_872 = _T_812 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_873 = _T_814 ? gpr_out_4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_874 = _T_816 ? gpr_out_5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_875 = _T_818 ? gpr_out_6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_876 = _T_820 ? gpr_out_7 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_877 = _T_822 ? gpr_out_8 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_878 = _T_824 ? gpr_out_9 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_879 = _T_826 ? gpr_out_10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_880 = _T_828 ? gpr_out_11 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_881 = _T_830 ? gpr_out_12 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_882 = _T_832 ? gpr_out_13 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_883 = _T_834 ? gpr_out_14 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_884 = _T_836 ? gpr_out_15 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_885 = _T_838 ? gpr_out_16 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_886 = _T_840 ? gpr_out_17 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_887 = _T_842 ? gpr_out_18 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_888 = _T_844 ? gpr_out_19 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_889 = _T_846 ? gpr_out_20 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_890 = _T_848 ? gpr_out_21 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_891 = _T_850 ? gpr_out_22 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_892 = _T_852 ? gpr_out_23 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_893 = _T_854 ? gpr_out_24 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_894 = _T_856 ? gpr_out_25 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_895 = _T_858 ? gpr_out_26 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_896 = _T_860 ? gpr_out_27 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_897 = _T_862 ? gpr_out_28 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_898 = _T_864 ? gpr_out_29 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_899 = _T_866 ? gpr_out_30 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_900 = _T_868 ? gpr_out_31 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_901 = _T_870 | _T_871; // @[Mux.scala 27:72] + wire [31:0] _T_902 = _T_901 | _T_872; // @[Mux.scala 27:72] + wire [31:0] _T_903 = _T_902 | _T_873; // @[Mux.scala 27:72] + wire [31:0] _T_904 = _T_903 | _T_874; // @[Mux.scala 27:72] + wire [31:0] _T_905 = _T_904 | _T_875; // @[Mux.scala 27:72] + wire [31:0] _T_906 = _T_905 | _T_876; // @[Mux.scala 27:72] + wire [31:0] _T_907 = _T_906 | _T_877; // @[Mux.scala 27:72] + wire [31:0] _T_908 = _T_907 | _T_878; // @[Mux.scala 27:72] + wire [31:0] _T_909 = _T_908 | _T_879; // @[Mux.scala 27:72] + wire [31:0] _T_910 = _T_909 | _T_880; // @[Mux.scala 27:72] + wire [31:0] _T_911 = _T_910 | _T_881; // @[Mux.scala 27:72] + wire [31:0] _T_912 = _T_911 | _T_882; // @[Mux.scala 27:72] + wire [31:0] _T_913 = _T_912 | _T_883; // @[Mux.scala 27:72] + wire [31:0] _T_914 = _T_913 | _T_884; // @[Mux.scala 27:72] + wire [31:0] _T_915 = _T_914 | _T_885; // @[Mux.scala 27:72] + wire [31:0] _T_916 = _T_915 | _T_886; // @[Mux.scala 27:72] + wire [31:0] _T_917 = _T_916 | _T_887; // @[Mux.scala 27:72] + wire [31:0] _T_918 = _T_917 | _T_888; // @[Mux.scala 27:72] + wire [31:0] _T_919 = _T_918 | _T_889; // @[Mux.scala 27:72] + wire [31:0] _T_920 = _T_919 | _T_890; // @[Mux.scala 27:72] + wire [31:0] _T_921 = _T_920 | _T_891; // @[Mux.scala 27:72] + wire [31:0] _T_922 = _T_921 | _T_892; // @[Mux.scala 27:72] + wire [31:0] _T_923 = _T_922 | _T_893; // @[Mux.scala 27:72] + wire [31:0] _T_924 = _T_923 | _T_894; // @[Mux.scala 27:72] + wire [31:0] _T_925 = _T_924 | _T_895; // @[Mux.scala 27:72] + wire [31:0] _T_926 = _T_925 | _T_896; // @[Mux.scala 27:72] + wire [31:0] _T_927 = _T_926 | _T_897; // @[Mux.scala 27:72] + wire [31:0] _T_928 = _T_927 | _T_898; // @[Mux.scala 27:72] + wire [31:0] _T_929 = _T_928 | _T_899; // @[Mux.scala 27:72] + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en) + ); + rvclkhdr rvclkhdr_10 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en) + ); + rvclkhdr rvclkhdr_11 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en) + ); + rvclkhdr rvclkhdr_12 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_12_io_clk), + .io_en(rvclkhdr_12_io_en) + ); + rvclkhdr rvclkhdr_13 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_13_io_clk), + .io_en(rvclkhdr_13_io_en) + ); + rvclkhdr rvclkhdr_14 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_14_io_clk), + .io_en(rvclkhdr_14_io_en) + ); + rvclkhdr rvclkhdr_15 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_15_io_clk), + .io_en(rvclkhdr_15_io_en) + ); + rvclkhdr rvclkhdr_16 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_16_io_clk), + .io_en(rvclkhdr_16_io_en) + ); + rvclkhdr rvclkhdr_17 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_17_io_clk), + .io_en(rvclkhdr_17_io_en) + ); + rvclkhdr rvclkhdr_18 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_18_io_clk), + .io_en(rvclkhdr_18_io_en) + ); + rvclkhdr rvclkhdr_19 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_19_io_clk), + .io_en(rvclkhdr_19_io_en) + ); + rvclkhdr rvclkhdr_20 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_20_io_clk), + .io_en(rvclkhdr_20_io_en) + ); + rvclkhdr rvclkhdr_21 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_21_io_clk), + .io_en(rvclkhdr_21_io_en) + ); + rvclkhdr rvclkhdr_22 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_22_io_clk), + .io_en(rvclkhdr_22_io_en) + ); + rvclkhdr rvclkhdr_23 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_23_io_clk), + .io_en(rvclkhdr_23_io_en) + ); + rvclkhdr rvclkhdr_24 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_24_io_clk), + .io_en(rvclkhdr_24_io_en) + ); + rvclkhdr rvclkhdr_25 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_25_io_clk), + .io_en(rvclkhdr_25_io_en) + ); + rvclkhdr rvclkhdr_26 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_26_io_clk), + .io_en(rvclkhdr_26_io_en) + ); + rvclkhdr rvclkhdr_27 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_27_io_clk), + .io_en(rvclkhdr_27_io_en) + ); + rvclkhdr rvclkhdr_28 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_28_io_clk), + .io_en(rvclkhdr_28_io_en) + ); + rvclkhdr rvclkhdr_29 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_29_io_clk), + .io_en(rvclkhdr_29_io_en) + ); + rvclkhdr rvclkhdr_30 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_30_io_clk), + .io_en(rvclkhdr_30_io_en) + ); + assign io_gpr_exu_gpr_i0_rs1_d = _T_805 | _T_776; // @[dec_gpr_ctl.scala 48:32 dec_gpr_ctl.scala 64:32] + assign io_gpr_exu_gpr_i0_rs2_d = _T_929 | _T_900; // @[dec_gpr_ctl.scala 49:32 dec_gpr_ctl.scala 65:32] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = gpr_wr_en[1]; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = gpr_wr_en[2]; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = gpr_wr_en[3]; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = gpr_wr_en[4]; // @[lib.scala 407:17] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_4_io_en = gpr_wr_en[5]; // @[lib.scala 407:17] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_5_io_en = gpr_wr_en[6]; // @[lib.scala 407:17] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_6_io_en = gpr_wr_en[7]; // @[lib.scala 407:17] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_7_io_en = gpr_wr_en[8]; // @[lib.scala 407:17] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_8_io_en = gpr_wr_en[9]; // @[lib.scala 407:17] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_9_io_en = gpr_wr_en[10]; // @[lib.scala 407:17] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_10_io_en = gpr_wr_en[11]; // @[lib.scala 407:17] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_11_io_en = gpr_wr_en[12]; // @[lib.scala 407:17] + assign rvclkhdr_12_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_12_io_en = gpr_wr_en[13]; // @[lib.scala 407:17] + assign rvclkhdr_13_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_13_io_en = gpr_wr_en[14]; // @[lib.scala 407:17] + assign rvclkhdr_14_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_14_io_en = gpr_wr_en[15]; // @[lib.scala 407:17] + assign rvclkhdr_15_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_15_io_en = gpr_wr_en[16]; // @[lib.scala 407:17] + assign rvclkhdr_16_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_16_io_en = gpr_wr_en[17]; // @[lib.scala 407:17] + assign rvclkhdr_17_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_17_io_en = gpr_wr_en[18]; // @[lib.scala 407:17] + assign rvclkhdr_18_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_18_io_en = gpr_wr_en[19]; // @[lib.scala 407:17] + assign rvclkhdr_19_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_19_io_en = gpr_wr_en[20]; // @[lib.scala 407:17] + assign rvclkhdr_20_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_20_io_en = gpr_wr_en[21]; // @[lib.scala 407:17] + assign rvclkhdr_21_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_21_io_en = gpr_wr_en[22]; // @[lib.scala 407:17] + assign rvclkhdr_22_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_22_io_en = gpr_wr_en[23]; // @[lib.scala 407:17] + assign rvclkhdr_23_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_23_io_en = gpr_wr_en[24]; // @[lib.scala 407:17] + assign rvclkhdr_24_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_24_io_en = gpr_wr_en[25]; // @[lib.scala 407:17] + assign rvclkhdr_25_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_25_io_en = gpr_wr_en[26]; // @[lib.scala 407:17] + assign rvclkhdr_26_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_26_io_en = gpr_wr_en[27]; // @[lib.scala 407:17] + assign rvclkhdr_27_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_27_io_en = gpr_wr_en[28]; // @[lib.scala 407:17] + assign rvclkhdr_28_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_28_io_en = gpr_wr_en[29]; // @[lib.scala 407:17] + assign rvclkhdr_29_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_29_io_en = gpr_wr_en[30]; // @[lib.scala 407:17] + assign rvclkhdr_30_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_30_io_en = gpr_wr_en[31]; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + gpr_out_1 = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + gpr_out_2 = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + gpr_out_3 = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + gpr_out_4 = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + gpr_out_5 = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + gpr_out_6 = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + gpr_out_7 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + gpr_out_8 = _RAND_7[31:0]; + _RAND_8 = {1{`RANDOM}}; + gpr_out_9 = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + gpr_out_10 = _RAND_9[31:0]; + _RAND_10 = {1{`RANDOM}}; + gpr_out_11 = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + gpr_out_12 = _RAND_11[31:0]; + _RAND_12 = {1{`RANDOM}}; + gpr_out_13 = _RAND_12[31:0]; + _RAND_13 = {1{`RANDOM}}; + gpr_out_14 = _RAND_13[31:0]; + _RAND_14 = {1{`RANDOM}}; + gpr_out_15 = _RAND_14[31:0]; + _RAND_15 = {1{`RANDOM}}; + gpr_out_16 = _RAND_15[31:0]; + _RAND_16 = {1{`RANDOM}}; + gpr_out_17 = _RAND_16[31:0]; + _RAND_17 = {1{`RANDOM}}; + gpr_out_18 = _RAND_17[31:0]; + _RAND_18 = {1{`RANDOM}}; + gpr_out_19 = _RAND_18[31:0]; + _RAND_19 = {1{`RANDOM}}; + gpr_out_20 = _RAND_19[31:0]; + _RAND_20 = {1{`RANDOM}}; + gpr_out_21 = _RAND_20[31:0]; + _RAND_21 = {1{`RANDOM}}; + gpr_out_22 = _RAND_21[31:0]; + _RAND_22 = {1{`RANDOM}}; + gpr_out_23 = _RAND_22[31:0]; + _RAND_23 = {1{`RANDOM}}; + gpr_out_24 = _RAND_23[31:0]; + _RAND_24 = {1{`RANDOM}}; + gpr_out_25 = _RAND_24[31:0]; + _RAND_25 = {1{`RANDOM}}; + gpr_out_26 = _RAND_25[31:0]; + _RAND_26 = {1{`RANDOM}}; + gpr_out_27 = _RAND_26[31:0]; + _RAND_27 = {1{`RANDOM}}; + gpr_out_28 = _RAND_27[31:0]; + _RAND_28 = {1{`RANDOM}}; + gpr_out_29 = _RAND_28[31:0]; + _RAND_29 = {1{`RANDOM}}; + gpr_out_30 = _RAND_29[31:0]; + _RAND_30 = {1{`RANDOM}}; + gpr_out_31 = _RAND_30[31:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + gpr_out_1 = 32'h0; + end + if (reset) begin + gpr_out_2 = 32'h0; + end + if (reset) begin + gpr_out_3 = 32'h0; + end + if (reset) begin + gpr_out_4 = 32'h0; + end + if (reset) begin + gpr_out_5 = 32'h0; + end + if (reset) begin + gpr_out_6 = 32'h0; + end + if (reset) begin + gpr_out_7 = 32'h0; + end + if (reset) begin + gpr_out_8 = 32'h0; + end + if (reset) begin + gpr_out_9 = 32'h0; + end + if (reset) begin + gpr_out_10 = 32'h0; + end + if (reset) begin + gpr_out_11 = 32'h0; + end + if (reset) begin + gpr_out_12 = 32'h0; + end + if (reset) begin + gpr_out_13 = 32'h0; + end + if (reset) begin + gpr_out_14 = 32'h0; + end + if (reset) begin + gpr_out_15 = 32'h0; + end + if (reset) begin + gpr_out_16 = 32'h0; + end + if (reset) begin + gpr_out_17 = 32'h0; + end + if (reset) begin + gpr_out_18 = 32'h0; + end + if (reset) begin + gpr_out_19 = 32'h0; + end + if (reset) begin + gpr_out_20 = 32'h0; + end + if (reset) begin + gpr_out_21 = 32'h0; + end + if (reset) begin + gpr_out_22 = 32'h0; + end + if (reset) begin + gpr_out_23 = 32'h0; + end + if (reset) begin + gpr_out_24 = 32'h0; + end + if (reset) begin + gpr_out_25 = 32'h0; + end + if (reset) begin + gpr_out_26 = 32'h0; + end + if (reset) begin + gpr_out_27 = 32'h0; + end + if (reset) begin + gpr_out_28 = 32'h0; + end + if (reset) begin + gpr_out_29 = 32'h0; + end + if (reset) begin + gpr_out_30 = 32'h0; + end + if (reset) begin + gpr_out_31 = 32'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_1 <= 32'h0; + end else if (gpr_wr_en[1]) begin + gpr_out_1 <= gpr_in_1; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_2 <= 32'h0; + end else if (gpr_wr_en[2]) begin + gpr_out_2 <= gpr_in_2; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_3 <= 32'h0; + end else if (gpr_wr_en[3]) begin + gpr_out_3 <= gpr_in_3; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_4 <= 32'h0; + end else if (gpr_wr_en[4]) begin + gpr_out_4 <= gpr_in_4; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_5 <= 32'h0; + end else if (gpr_wr_en[5]) begin + gpr_out_5 <= gpr_in_5; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_6 <= 32'h0; + end else if (gpr_wr_en[6]) begin + gpr_out_6 <= gpr_in_6; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_7 <= 32'h0; + end else if (gpr_wr_en[7]) begin + gpr_out_7 <= gpr_in_7; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_8 <= 32'h0; + end else if (gpr_wr_en[8]) begin + gpr_out_8 <= gpr_in_8; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_9 <= 32'h0; + end else if (gpr_wr_en[9]) begin + gpr_out_9 <= gpr_in_9; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_10 <= 32'h0; + end else if (gpr_wr_en[10]) begin + gpr_out_10 <= gpr_in_10; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_11 <= 32'h0; + end else if (gpr_wr_en[11]) begin + gpr_out_11 <= gpr_in_11; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_12 <= 32'h0; + end else if (gpr_wr_en[12]) begin + gpr_out_12 <= gpr_in_12; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_13 <= 32'h0; + end else if (gpr_wr_en[13]) begin + gpr_out_13 <= gpr_in_13; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_14 <= 32'h0; + end else if (gpr_wr_en[14]) begin + gpr_out_14 <= gpr_in_14; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_15 <= 32'h0; + end else if (gpr_wr_en[15]) begin + gpr_out_15 <= gpr_in_15; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_16 <= 32'h0; + end else if (gpr_wr_en[16]) begin + gpr_out_16 <= gpr_in_16; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_17 <= 32'h0; + end else if (gpr_wr_en[17]) begin + gpr_out_17 <= gpr_in_17; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_18 <= 32'h0; + end else if (gpr_wr_en[18]) begin + gpr_out_18 <= gpr_in_18; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_19 <= 32'h0; + end else if (gpr_wr_en[19]) begin + gpr_out_19 <= gpr_in_19; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_20 <= 32'h0; + end else if (gpr_wr_en[20]) begin + gpr_out_20 <= gpr_in_20; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_21 <= 32'h0; + end else if (gpr_wr_en[21]) begin + gpr_out_21 <= gpr_in_21; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_22 <= 32'h0; + end else if (gpr_wr_en[22]) begin + gpr_out_22 <= gpr_in_22; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_23 <= 32'h0; + end else if (gpr_wr_en[23]) begin + gpr_out_23 <= gpr_in_23; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_24 <= 32'h0; + end else if (gpr_wr_en[24]) begin + gpr_out_24 <= gpr_in_24; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_25 <= 32'h0; + end else if (gpr_wr_en[25]) begin + gpr_out_25 <= gpr_in_25; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_26 <= 32'h0; + end else if (gpr_wr_en[26]) begin + gpr_out_26 <= gpr_in_26; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_27 <= 32'h0; + end else if (gpr_wr_en[27]) begin + gpr_out_27 <= gpr_in_27; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_28 <= 32'h0; + end else if (gpr_wr_en[28]) begin + gpr_out_28 <= gpr_in_28; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_29 <= 32'h0; + end else if (gpr_wr_en[29]) begin + gpr_out_29 <= gpr_in_29; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_30 <= 32'h0; + end else if (gpr_wr_en[30]) begin + gpr_out_30 <= gpr_in_30; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_31 <= 32'h0; + end else if (gpr_wr_en[31]) begin + gpr_out_31 <= gpr_in_31; + end + end +endmodule +module int_exc( + input clock, + input reset, + output io_mhwakeup_ready, + output io_ext_int_ready, + output io_ce_int_ready, + output io_soft_int_ready, + output io_timer_int_ready, + output io_int_timer0_int_hold, + output io_int_timer1_int_hold, + output io_internal_dbg_halt_timers, + output io_take_ext_int_start, + input io_ext_int_freeze_d1, + input io_take_ext_int_start_d1, + input io_take_ext_int_start_d2, + input io_take_ext_int_start_d3, + output io_ext_int_freeze, + output io_take_ext_int, + output io_fast_int_meicpct, + output io_ignore_ext_int_due_to_lsu_stall, + output io_take_ce_int, + output io_take_soft_int, + output io_take_timer_int, + output io_take_int_timer0_int, + output io_take_int_timer1_int, + output io_take_reset, + output io_take_nmi, + output io_synchronous_flush_r, + output io_tlu_flush_lower_r, + output io_dec_tlu_flush_lower_wb, + output io_dec_tlu_flush_lower_r, + output [30:0] io_dec_tlu_flush_path_r, + output io_interrupt_valid_r_d1, + output io_i0_exception_valid_r_d1, + output io_exc_or_int_valid_r_d1, + output [4:0] io_exc_cause_wb, + output io_i0_valid_wb, + output io_trigger_hit_r_d1, + output io_take_nmi_r_d1, + output io_interrupt_valid_r, + output [4:0] io_exc_cause_r, + output io_i0_exception_valid_r, + output [30:0] io_tlu_flush_path_r_d1, + output io_exc_or_int_valid_r, + input io_dec_csr_stall_int_ff, + input io_mstatus_mie_ns, + input [5:0] io_mip, + input [5:0] io_mie_ns, + input io_mret_r, + input io_pmu_fw_tlu_halted_f, + input io_int_timer0_int_hold_f, + input io_int_timer1_int_hold_f, + input io_internal_dbg_halt_mode_f, + input io_dcsr_single_step_running, + input io_internal_dbg_halt_mode, + input io_dec_tlu_i0_valid_r, + input io_internal_pmu_fw_halt_mode, + input io_i_cpu_halt_req_d1, + input io_ebreak_to_debug_mode_r, + input [1:0] io_lsu_fir_error, + input io_csr_pkt_csr_meicpct, + input io_dec_csr_any_unq_d, + input io_lsu_fastint_stall_any, + input io_reset_delayed, + input io_mpc_reset_run_req, + input io_nmi_int_detected, + input io_dcsr_single_step_running_f, + input io_dcsr_single_step_done_f, + input [15:0] io_dcsr, + input [30:0] io_mtvec, + input io_tlu_i0_commit_cmt, + input io_i0_trigger_hit_r, + input io_pause_expired_r, + input [30:0] io_nmi_vec, + input io_lsu_i0_rfnpc_r, + input io_fence_i_r, + input io_iccm_repair_state_rfnpc, + input io_i_cpu_run_req_d1, + input io_rfpc_i0_r, + input io_lsu_exc_valid_r, + input io_trigger_hit_dmode_r, + input io_take_halt, + input [30:0] io_rst_vec, + input [30:0] io_lsu_fir_addr, + input [30:0] io_dec_tlu_i0_pc_r, + input [30:0] io_npc_r, + input [30:0] io_mepc, + input io_debug_resume_req_f, + input [30:0] io_dpc, + input [30:0] io_npc_r_d1, + input io_tlu_flush_lower_r_d1, + input io_dec_tlu_dbg_halted, + input io_ebreak_r, + input io_ecall_r, + input io_illegal_r, + input io_inst_acc_r, + input io_lsu_i0_exc_r, + input io_lsu_error_pkt_r_bits_inst_type, + input io_lsu_error_pkt_r_bits_exc_type, + input io_dec_tlu_wr_pause_r_d1 +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; +`endif // RANDOMIZE_REG_INIT + wire _T = ~io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 3017:48] + wire lsu_exc_ma_r = io_lsu_i0_exc_r & _T; // @[dec_tlu_ctl.scala 3017:46] + wire lsu_exc_acc_r = io_lsu_i0_exc_r & io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 3018:46] + wire lsu_exc_st_r = io_lsu_i0_exc_r & io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 3019:46] + wire _T_1 = io_ebreak_r | io_ecall_r; // @[dec_tlu_ctl.scala 3031:49] + wire _T_2 = _T_1 | io_illegal_r; // @[dec_tlu_ctl.scala 3031:62] + wire _T_3 = _T_2 | io_inst_acc_r; // @[dec_tlu_ctl.scala 3031:77] + wire _T_4 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 3031:96] + wire _T_5 = _T_3 & _T_4; // @[dec_tlu_ctl.scala 3031:94] + wire _T_6 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 3031:112] + wire [4:0] _T_9 = io_take_nmi ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_10 = ~_T_9; // @[dec_tlu_ctl.scala 3039:27] + wire _T_20 = io_ebreak_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 3049:31] + wire _T_22 = ~lsu_exc_st_r; // @[dec_tlu_ctl.scala 3050:33] + wire _T_23 = lsu_exc_ma_r & _T_22; // @[dec_tlu_ctl.scala 3050:31] + wire _T_26 = lsu_exc_acc_r & _T_22; // @[dec_tlu_ctl.scala 3051:32] + wire _T_28 = lsu_exc_ma_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 3052:31] + wire _T_30 = lsu_exc_acc_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 3053:32] + wire [4:0] _T_32 = io_take_ext_int ? 5'hb : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_33 = io_take_timer_int ? 5'h7 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_34 = io_take_soft_int ? 5'h3 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_35 = io_take_int_timer0_int ? 5'h1d : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_36 = io_take_int_timer1_int ? 5'h1c : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_37 = io_take_ce_int ? 5'h1e : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_38 = io_illegal_r ? 5'h2 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_39 = io_ecall_r ? 5'hb : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_40 = io_inst_acc_r ? 5'h1 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_41 = _T_20 ? 5'h3 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_42 = _T_23 ? 5'h4 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_43 = _T_26 ? 5'h5 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_44 = _T_28 ? 5'h6 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_45 = _T_30 ? 5'h7 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_46 = _T_32 | _T_33; // @[Mux.scala 27:72] + wire [4:0] _T_47 = _T_46 | _T_34; // @[Mux.scala 27:72] + wire [4:0] _T_48 = _T_47 | _T_35; // @[Mux.scala 27:72] + wire [4:0] _T_49 = _T_48 | _T_36; // @[Mux.scala 27:72] + wire [4:0] _T_50 = _T_49 | _T_37; // @[Mux.scala 27:72] + wire [4:0] _T_51 = _T_50 | _T_38; // @[Mux.scala 27:72] + wire [4:0] _T_52 = _T_51 | _T_39; // @[Mux.scala 27:72] + wire [4:0] _T_53 = _T_52 | _T_40; // @[Mux.scala 27:72] + wire [4:0] _T_54 = _T_53 | _T_41; // @[Mux.scala 27:72] + wire [4:0] _T_55 = _T_54 | _T_42; // @[Mux.scala 27:72] + wire [4:0] _T_56 = _T_55 | _T_43; // @[Mux.scala 27:72] + wire [4:0] _T_57 = _T_56 | _T_44; // @[Mux.scala 27:72] + wire [4:0] _T_58 = _T_57 | _T_45; // @[Mux.scala 27:72] + wire _T_61 = ~io_dec_csr_stall_int_ff; // @[dec_tlu_ctl.scala 3064:31] + wire _T_62 = _T_61 & io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 3064:56] + wire _T_64 = _T_62 & io_mip[2]; // @[dec_tlu_ctl.scala 3064:76] + wire _T_66 = _T_64 & io_mie_ns[2]; // @[dec_tlu_ctl.scala 3064:97] + wire _T_73 = ~io_ignore_ext_int_due_to_lsu_stall; // @[dec_tlu_ctl.scala 3065:121] + wire [5:0] _T_77 = {{5'd0}, io_mip[5]}; // @[dec_tlu_ctl.scala 3066:84] + wire _T_79 = _T_62 & _T_77[0]; // @[dec_tlu_ctl.scala 3066:76] + wire _T_85 = _T_62 & io_mip[0]; // @[dec_tlu_ctl.scala 3067:76] + wire _T_91 = _T_62 & io_mip[1]; // @[dec_tlu_ctl.scala 3068:76] + wire int_timer0_int_possible = io_mstatus_mie_ns & io_mie_ns[4]; // @[dec_tlu_ctl.scala 3071:57] + wire [5:0] _T_95 = {{4'd0}, io_mip[5:4]}; // @[dec_tlu_ctl.scala 3072:42] + wire int_timer0_int_ready = _T_95[0] & int_timer0_int_possible; // @[dec_tlu_ctl.scala 3072:55] + wire int_timer1_int_possible = io_mstatus_mie_ns & io_mie_ns[3]; // @[dec_tlu_ctl.scala 3073:57] + wire [5:0] _T_98 = {{3'd0}, io_mip[5:3]}; // @[dec_tlu_ctl.scala 3074:42] + wire int_timer1_int_ready = _T_98[0] & int_timer1_int_possible; // @[dec_tlu_ctl.scala 3074:55] + wire _T_100 = io_dec_csr_stall_int_ff | io_synchronous_flush_r; // @[dec_tlu_ctl.scala 3078:57] + wire _T_101 = _T_100 | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 3078:82] + wire int_timer_stalled = _T_101 | io_mret_r; // @[dec_tlu_ctl.scala 3078:109] + wire _T_102 = io_pmu_fw_tlu_halted_f | int_timer_stalled; // @[dec_tlu_ctl.scala 3080:83] + wire _T_103 = int_timer0_int_ready & _T_102; // @[dec_tlu_ctl.scala 3080:57] + wire _T_104 = int_timer0_int_possible & io_int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 3080:132] + wire _T_105 = ~io_interrupt_valid_r; // @[dec_tlu_ctl.scala 3080:161] + wire _T_106 = _T_104 & _T_105; // @[dec_tlu_ctl.scala 3080:159] + wire _T_107 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 3080:185] + wire _T_108 = _T_106 & _T_107; // @[dec_tlu_ctl.scala 3080:183] + wire _T_109 = ~io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 3080:210] + wire _T_110 = _T_108 & _T_109; // @[dec_tlu_ctl.scala 3080:208] + wire _T_113 = int_timer1_int_ready & _T_102; // @[dec_tlu_ctl.scala 3081:57] + wire _T_114 = int_timer1_int_possible & io_int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 3081:132] + wire _T_116 = _T_114 & _T_105; // @[dec_tlu_ctl.scala 3081:159] + wire _T_118 = _T_116 & _T_107; // @[dec_tlu_ctl.scala 3081:183] + wire _T_120 = _T_118 & _T_109; // @[dec_tlu_ctl.scala 3081:208] + wire _T_122 = ~io_dcsr_single_step_running; // @[dec_tlu_ctl.scala 3083:70] + wire _T_125 = _T_122 | io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 3085:92] + wire _T_126 = io_internal_dbg_halt_mode & _T_125; // @[dec_tlu_ctl.scala 3085:60] + wire _T_127 = _T_126 | io_internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 3085:118] + wire _T_128 = _T_127 | io_i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 3085:149] + wire _T_129 = _T_128 | io_take_nmi; // @[dec_tlu_ctl.scala 3085:172] + wire _T_130 = _T_129 | io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 3085:186] + wire _T_131 = _T_130 | io_synchronous_flush_r; // @[dec_tlu_ctl.scala 3085:214] + wire _T_132 = _T_131 | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 3085:240] + wire _T_133 = _T_132 | io_mret_r; // @[dec_tlu_ctl.scala 3085:267] + wire block_interrupts = _T_133 | io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 3085:279] + wire _T_134 = ~block_interrupts; // @[dec_tlu_ctl.scala 3093:61] + wire _T_136 = io_take_ext_int_start | io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 3094:60] + wire _T_137 = _T_136 | io_take_ext_int_start_d2; // @[dec_tlu_ctl.scala 3094:87] + wire _T_139 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 3095:81] + wire _T_140 = ~_T_139; // @[dec_tlu_ctl.scala 3095:63] + wire _T_141 = io_take_ext_int_start_d3 & _T_140; // @[dec_tlu_ctl.scala 3095:61] + wire _T_143 = ~io_ext_int_ready; // @[dec_tlu_ctl.scala 3110:46] + wire _T_144 = io_ce_int_ready & _T_143; // @[dec_tlu_ctl.scala 3110:44] + wire _T_148 = io_soft_int_ready & _T_143; // @[dec_tlu_ctl.scala 3111:47] + wire _T_149 = ~io_ce_int_ready; // @[dec_tlu_ctl.scala 3111:69] + wire _T_150 = _T_148 & _T_149; // @[dec_tlu_ctl.scala 3111:67] + wire _T_153 = ~io_soft_int_ready; // @[dec_tlu_ctl.scala 3112:51] + wire _T_154 = io_timer_int_ready & _T_153; // @[dec_tlu_ctl.scala 3112:49] + wire _T_156 = _T_154 & _T_143; // @[dec_tlu_ctl.scala 3112:70] + wire _T_158 = _T_156 & _T_149; // @[dec_tlu_ctl.scala 3112:90] + wire _T_161 = int_timer0_int_ready | io_int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 3113:57] + wire _T_162 = _T_161 & int_timer0_int_possible; // @[dec_tlu_ctl.scala 3113:85] + wire _T_164 = _T_162 & _T_61; // @[dec_tlu_ctl.scala 3113:111] + wire _T_165 = ~io_timer_int_ready; // @[dec_tlu_ctl.scala 3113:140] + wire _T_166 = _T_164 & _T_165; // @[dec_tlu_ctl.scala 3113:138] + wire _T_168 = _T_166 & _T_153; // @[dec_tlu_ctl.scala 3113:160] + wire _T_170 = _T_168 & _T_143; // @[dec_tlu_ctl.scala 3113:181] + wire _T_172 = _T_170 & _T_149; // @[dec_tlu_ctl.scala 3113:201] + wire _T_175 = int_timer1_int_ready | io_int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 3114:57] + wire _T_176 = _T_175 & int_timer1_int_possible; // @[dec_tlu_ctl.scala 3114:85] + wire _T_178 = _T_176 & _T_61; // @[dec_tlu_ctl.scala 3114:111] + wire _T_180 = ~_T_161; // @[dec_tlu_ctl.scala 3114:140] + wire _T_181 = _T_178 & _T_180; // @[dec_tlu_ctl.scala 3114:138] + wire _T_183 = _T_181 & _T_165; // @[dec_tlu_ctl.scala 3114:191] + wire _T_185 = _T_183 & _T_153; // @[dec_tlu_ctl.scala 3114:213] + wire _T_187 = _T_185 & _T_143; // @[dec_tlu_ctl.scala 3114:234] + wire _T_189 = _T_187 & _T_149; // @[dec_tlu_ctl.scala 3114:254] + wire _T_193 = ~io_internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 3116:46] + wire _T_194 = io_nmi_int_detected & _T_193; // @[dec_tlu_ctl.scala 3116:44] + wire _T_195 = ~io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 3116:79] + wire _T_197 = io_dcsr_single_step_running_f & io_dcsr[11]; // @[dec_tlu_ctl.scala 3116:139] + wire _T_198 = ~io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 3116:164] + wire _T_199 = _T_197 & _T_198; // @[dec_tlu_ctl.scala 3116:162] + wire _T_200 = ~io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 3116:189] + wire _T_201 = _T_199 & _T_200; // @[dec_tlu_ctl.scala 3116:187] + wire _T_202 = _T_195 | _T_201; // @[dec_tlu_ctl.scala 3116:106] + wire _T_203 = _T_194 & _T_202; // @[dec_tlu_ctl.scala 3116:76] + wire _T_204 = ~io_synchronous_flush_r; // @[dec_tlu_ctl.scala 3116:220] + wire _T_205 = _T_203 & _T_204; // @[dec_tlu_ctl.scala 3116:218] + wire _T_206 = ~io_mret_r; // @[dec_tlu_ctl.scala 3116:246] + wire _T_207 = _T_205 & _T_206; // @[dec_tlu_ctl.scala 3116:244] + wire _T_208 = ~io_take_reset; // @[dec_tlu_ctl.scala 3116:259] + wire _T_209 = _T_207 & _T_208; // @[dec_tlu_ctl.scala 3116:257] + wire _T_210 = ~io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 3116:276] + wire _T_211 = _T_209 & _T_210; // @[dec_tlu_ctl.scala 3116:274] + wire _T_212 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 3116:306] + wire _T_214 = io_take_ext_int_start_d3 & _T_139; // @[dec_tlu_ctl.scala 3116:356] + wire _T_215 = _T_212 | _T_214; // @[dec_tlu_ctl.scala 3116:328] + wire _T_217 = io_take_ext_int | io_take_timer_int; // @[dec_tlu_ctl.scala 3120:49] + wire _T_218 = _T_217 | io_take_soft_int; // @[dec_tlu_ctl.scala 3120:69] + wire _T_219 = _T_218 | io_take_nmi; // @[dec_tlu_ctl.scala 3120:88] + wire _T_220 = _T_219 | io_take_ce_int; // @[dec_tlu_ctl.scala 3120:102] + wire _T_221 = _T_220 | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 3120:119] + wire [30:0] _T_224 = {io_mtvec[30:1],1'h0}; // @[Cat.scala 29:58] + wire [30:0] _T_226 = {25'h0,io_exc_cause_r,1'h0}; // @[Cat.scala 29:58] + wire [30:0] vectored_path = _T_224 + _T_226; // @[dec_tlu_ctl.scala 3125:59] + wire [30:0] _T_233 = io_mtvec[0] ? vectored_path : _T_224; // @[dec_tlu_ctl.scala 3126:69] + wire [30:0] interrupt_path = io_take_nmi ? io_nmi_vec : _T_233; // @[dec_tlu_ctl.scala 3126:33] + wire _T_234 = io_lsu_i0_rfnpc_r | io_fence_i_r; // @[dec_tlu_ctl.scala 3127:44] + wire _T_235 = _T_234 | io_iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 3127:59] + wire _T_237 = io_i_cpu_run_req_d1 & _T_105; // @[dec_tlu_ctl.scala 3127:111] + wire _T_238 = _T_235 | _T_237; // @[dec_tlu_ctl.scala 3127:88] + wire _T_240 = io_rfpc_i0_r & _T_198; // @[dec_tlu_ctl.scala 3127:152] + wire sel_npc_r = _T_238 | _T_240; // @[dec_tlu_ctl.scala 3127:136] + wire _T_241 = io_i_cpu_run_req_d1 & io_pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 3128:51] + wire sel_npc_resume = _T_241 | io_pause_expired_r; // @[dec_tlu_ctl.scala 3128:77] + wire _T_244 = io_i0_exception_valid_r | io_rfpc_i0_r; // @[dec_tlu_ctl.scala 3130:60] + wire _T_245 = _T_244 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 3130:75] + wire _T_246 = _T_245 | io_fence_i_r; // @[dec_tlu_ctl.scala 3130:96] + wire _T_247 = _T_246 | io_lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 3130:111] + wire _T_248 = _T_247 | io_iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 3130:131] + wire _T_249 = _T_248 | io_debug_resume_req_f; // @[dec_tlu_ctl.scala 3130:161] + wire _T_250 = _T_249 | sel_npc_resume; // @[dec_tlu_ctl.scala 3130:186] + wire _T_251 = _T_250 | io_dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 3130:204] + wire _T_253 = io_interrupt_valid_r | io_mret_r; // @[dec_tlu_ctl.scala 3131:54] + wire _T_254 = _T_253 | io_synchronous_flush_r; // @[dec_tlu_ctl.scala 3131:66] + wire _T_255 = _T_254 | io_take_halt; // @[dec_tlu_ctl.scala 3131:91] + wire _T_256 = _T_255 | io_take_reset; // @[dec_tlu_ctl.scala 3131:106] + wire _T_260 = ~io_take_nmi; // @[dec_tlu_ctl.scala 3135:29] + wire _T_262 = _T_260 & sel_npc_r; // @[dec_tlu_ctl.scala 3135:36] + wire _T_265 = _T_260 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 3136:36] + wire _T_267 = _T_265 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 3136:57] + wire _T_268 = ~sel_npc_r; // @[dec_tlu_ctl.scala 3136:98] + wire _T_269 = _T_267 & _T_268; // @[dec_tlu_ctl.scala 3136:87] + wire _T_271 = ~_T_141; // @[dec_tlu_ctl.scala 3137:59] + wire _T_272 = io_interrupt_valid_r & _T_271; // @[dec_tlu_ctl.scala 3137:45] + wire _T_273 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 3138:43] + wire _T_274 = ~io_trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 3138:89] + wire _T_275 = io_i0_trigger_hit_r & _T_274; // @[dec_tlu_ctl.scala 3138:87] + wire _T_276 = _T_273 | _T_275; // @[dec_tlu_ctl.scala 3138:64] + wire _T_278 = _T_276 & _T_105; // @[dec_tlu_ctl.scala 3138:115] + wire _T_280 = _T_278 & _T_271; // @[dec_tlu_ctl.scala 3138:139] + wire _T_285 = _T_260 & io_mret_r; // @[dec_tlu_ctl.scala 3139:31] + wire _T_288 = _T_260 & io_debug_resume_req_f; // @[dec_tlu_ctl.scala 3140:31] + wire _T_291 = _T_260 & sel_npc_resume; // @[dec_tlu_ctl.scala 3141:31] + wire [30:0] _T_293 = _T_141 ? io_lsu_fir_addr : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_294 = _T_262 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_295 = _T_269 ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_296 = _T_272 ? interrupt_path : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_297 = _T_280 ? _T_224 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_298 = _T_285 ? io_mepc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_299 = _T_288 ? io_dpc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_300 = _T_291 ? io_npc_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_301 = _T_293 | _T_294; // @[Mux.scala 27:72] + wire [30:0] _T_302 = _T_301 | _T_295; // @[Mux.scala 27:72] + wire [30:0] _T_303 = _T_302 | _T_296; // @[Mux.scala 27:72] + wire [30:0] _T_304 = _T_303 | _T_297; // @[Mux.scala 27:72] + wire [30:0] _T_305 = _T_304 | _T_298; // @[Mux.scala 27:72] + wire [30:0] _T_306 = _T_305 | _T_299; // @[Mux.scala 27:72] + wire [30:0] _T_307 = _T_306 | _T_300; // @[Mux.scala 27:72] + reg [30:0] _T_311; // @[Reg.scala 27:20] + wire _T_312 = io_lsu_exc_valid_r | io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 3152:53] + wire _T_313 = _T_312 | io_interrupt_valid_r; // @[dec_tlu_ctl.scala 3152:79] + reg _T_320; // @[Reg.scala 27:20] + wire _T_318 = io_interrupt_valid_r ^ _T_320; // @[lib.scala 448:21] + wire _T_319 = |_T_318; // @[lib.scala 448:29] + reg _T_324; // @[Reg.scala 27:20] + wire _T_322 = io_i0_exception_valid_r ^ _T_324; // @[lib.scala 448:21] + wire _T_323 = |_T_322; // @[lib.scala 448:29] + reg _T_328; // @[Reg.scala 27:20] + wire _T_326 = io_exc_or_int_valid_r ^ _T_328; // @[lib.scala 448:21] + wire _T_327 = |_T_326; // @[lib.scala 448:29] + reg [4:0] _T_332; // @[Reg.scala 27:20] + wire [4:0] _T_330 = io_exc_cause_r ^ _T_332; // @[lib.scala 448:21] + wire _T_331 = |_T_330; // @[lib.scala 448:29] + wire _T_333 = ~io_illegal_r; // @[dec_tlu_ctl.scala 3158:104] + wire _T_334 = io_tlu_i0_commit_cmt & _T_333; // @[dec_tlu_ctl.scala 3158:102] + reg _T_338; // @[Reg.scala 27:20] + wire _T_336 = _T_334 ^ _T_338; // @[lib.scala 448:21] + wire _T_337 = |_T_336; // @[lib.scala 448:29] + reg _T_342; // @[Reg.scala 27:20] + wire _T_340 = io_i0_trigger_hit_r ^ _T_342; // @[lib.scala 448:21] + wire _T_341 = |_T_340; // @[lib.scala 448:29] + reg _T_346; // @[Reg.scala 27:20] + wire _T_344 = io_take_nmi ^ _T_346; // @[lib.scala 448:21] + wire _T_345 = |_T_344; // @[lib.scala 448:29] + assign io_mhwakeup_ready = _T_64 & io_mie_ns[2]; // @[dec_tlu_ctl.scala 3064:28] + assign io_ext_int_ready = _T_66 & _T_73; // @[dec_tlu_ctl.scala 3065:28] + assign io_ce_int_ready = _T_79 & io_mie_ns[5]; // @[dec_tlu_ctl.scala 3066:28] + assign io_soft_int_ready = _T_85 & io_mie_ns[0]; // @[dec_tlu_ctl.scala 3067:28] + assign io_timer_int_ready = _T_91 & io_mie_ns[1]; // @[dec_tlu_ctl.scala 3068:28] + assign io_int_timer0_int_hold = _T_103 | _T_110; // @[dec_tlu_ctl.scala 3080:32] + assign io_int_timer1_int_hold = _T_113 | _T_120; // @[dec_tlu_ctl.scala 3081:32] + assign io_internal_dbg_halt_timers = io_internal_dbg_halt_mode_f & _T_122; // @[dec_tlu_ctl.scala 3083:37] + assign io_take_ext_int_start = io_ext_int_ready & _T_134; // @[dec_tlu_ctl.scala 3093:39] + assign io_ext_int_freeze = _T_137 | io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 3094:35] + assign io_take_ext_int = io_take_ext_int_start_d3 & _T_140; // @[dec_tlu_ctl.scala 3095:33] + assign io_fast_int_meicpct = io_csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 3096:37] + assign io_ignore_ext_int_due_to_lsu_stall = io_lsu_fastint_stall_any; // @[dec_tlu_ctl.scala 3097:52] + assign io_take_ce_int = _T_144 & _T_134; // @[dec_tlu_ctl.scala 3110:25] + assign io_take_soft_int = _T_150 & _T_134; // @[dec_tlu_ctl.scala 3111:26] + assign io_take_timer_int = _T_158 & _T_134; // @[dec_tlu_ctl.scala 3112:27] + assign io_take_int_timer0_int = _T_172 & _T_134; // @[dec_tlu_ctl.scala 3113:32] + assign io_take_int_timer1_int = _T_189 & _T_134; // @[dec_tlu_ctl.scala 3114:32] + assign io_take_reset = io_reset_delayed & io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 3115:23] + assign io_take_nmi = _T_211 & _T_215; // @[dec_tlu_ctl.scala 3116:21] + assign io_synchronous_flush_r = _T_251 | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 3130:33] + assign io_tlu_flush_lower_r = _T_256 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 3131:30] + assign io_dec_tlu_flush_lower_wb = io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 3146:41] + assign io_dec_tlu_flush_lower_r = io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 3148:41] + assign io_dec_tlu_flush_path_r = io_take_reset ? io_rst_vec : _T_307; // @[dec_tlu_ctl.scala 3149:41] + assign io_interrupt_valid_r_d1 = _T_320; // @[dec_tlu_ctl.scala 3154:59] + assign io_i0_exception_valid_r_d1 = _T_324; // @[dec_tlu_ctl.scala 3155:51] + assign io_exc_or_int_valid_r_d1 = _T_328; // @[dec_tlu_ctl.scala 3156:53] + assign io_exc_cause_wb = _T_332; // @[dec_tlu_ctl.scala 3157:65] + assign io_i0_valid_wb = _T_338; // @[dec_tlu_ctl.scala 3158:71] + assign io_trigger_hit_r_d1 = _T_342; // @[dec_tlu_ctl.scala 3159:63] + assign io_take_nmi_r_d1 = _T_346; // @[dec_tlu_ctl.scala 3160:73] + assign io_interrupt_valid_r = _T_221 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 3120:30] + assign io_exc_cause_r = _T_10 & _T_58; // @[dec_tlu_ctl.scala 3039:24] + assign io_i0_exception_valid_r = _T_5 & _T_6; // @[dec_tlu_ctl.scala 3031:33] + assign io_tlu_flush_path_r_d1 = _T_311; // @[dec_tlu_ctl.scala 3144:31] + assign io_exc_or_int_valid_r = _T_313 | _T_275; // @[dec_tlu_ctl.scala 3152:31] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T_311 = _RAND_0[30:0]; + _RAND_1 = {1{`RANDOM}}; + _T_320 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_324 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + _T_328 = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + _T_332 = _RAND_4[4:0]; + _RAND_5 = {1{`RANDOM}}; + _T_338 = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + _T_342 = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + _T_346 = _RAND_7[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_311 = 31'h0; + end + if (reset) begin + _T_320 = 1'h0; + end + if (reset) begin + _T_324 = 1'h0; + end + if (reset) begin + _T_328 = 1'h0; + end + if (reset) begin + _T_332 = 5'h0; + end + if (reset) begin + _T_338 = 1'h0; + end + if (reset) begin + _T_342 = 1'h0; + end + if (reset) begin + _T_346 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_311 <= 31'h0; + end else if (io_tlu_flush_lower_r) begin + if (io_take_reset) begin + _T_311 <= io_rst_vec; + end else begin + _T_311 <= _T_307; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_320 <= 1'h0; + end else if (_T_319) begin + _T_320 <= io_interrupt_valid_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_324 <= 1'h0; + end else if (_T_323) begin + _T_324 <= io_i0_exception_valid_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_328 <= 1'h0; + end else if (_T_327) begin + _T_328 <= io_exc_or_int_valid_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_332 <= 5'h0; + end else if (_T_331) begin + _T_332 <= io_exc_cause_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_338 <= 1'h0; + end else if (_T_337) begin + _T_338 <= _T_334; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_342 <= 1'h0; + end else if (_T_341) begin + _T_342 <= io_i0_trigger_hit_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_346 <= 1'h0; + end else if (_T_345) begin + _T_346 <= io_take_nmi; + end + end +endmodule +module perf_mux_and_flops( + input reset, + output io_mhpmc_inc_r_0, + output io_mhpmc_inc_r_1, + output io_mhpmc_inc_r_2, + output io_mhpmc_inc_r_3, + input [6:0] io_mcountinhibit, + input [9:0] io_mhpme_vec_0, + input [9:0] io_mhpme_vec_1, + input [9:0] io_mhpme_vec_2, + input [9:0] io_mhpme_vec_3, + input io_ifu_pmu_ic_hit, + input io_ifu_pmu_ic_miss, + input io_tlu_i0_commit_cmt, + input io_illegal_r, + input io_exu_pmu_i0_pc4, + input io_ifu_pmu_instr_aligned, + input io_dec_pmu_instr_decoded, + input [3:0] io_dec_tlu_packet_r_pmu_i0_itype, + input io_dec_tlu_packet_r_pmu_i0_br_unpred, + input io_dec_tlu_packet_r_pmu_divide, + input io_dec_tlu_packet_r_pmu_lsu_misaligned, + input io_exu_pmu_i0_br_misp, + input io_dec_pmu_decode_stall, + input io_exu_pmu_i0_br_ataken, + input io_ifu_pmu_fetch_stall, + input io_dec_pmu_postsync_stall, + input io_dec_pmu_presync_stall, + input io_lsu_store_stall_any, + input io_dma_dccm_stall_any, + input io_dma_iccm_stall_any, + input io_i0_exception_valid_r, + input io_dec_tlu_pmu_fw_halted, + input io_dma_pmu_any_read, + input io_dma_pmu_any_write, + input io_dma_pmu_dccm_read, + input io_dma_pmu_dccm_write, + input io_lsu_pmu_load_external_r, + input io_lsu_pmu_store_external_r, + output [1:0] io_mstatus, + input [5:0] io_mie, + input io_ifu_pmu_bus_trxn, + input io_lsu_pmu_bus_trxn, + input io_lsu_pmu_bus_misaligned, + input io_ifu_pmu_bus_error, + input io_lsu_pmu_bus_error, + input io_ifu_pmu_bus_busy, + input io_lsu_pmu_bus_busy, + input io_i0_trigger_hit_r, + input io_lsu_exc_valid_r, + input io_take_timer_int, + input io_take_int_timer0_int, + input io_take_int_timer1_int, + input io_take_ext_int, + input io_tlu_flush_lower_r, + input io_dec_tlu_br0_error_r, + input io_rfpc_i0_r, + input io_dec_tlu_br0_start_error_r, + output io_mcyclel_cout_f, + output io_minstret_enable_f, + output io_minstretl_cout_f, + output [3:0] io_meicidpl, + output io_icache_rd_valid_f, + output io_icache_wr_valid_f, + output io_mhpmc_inc_r_d1_0, + output io_mhpmc_inc_r_d1_1, + output io_mhpmc_inc_r_d1_2, + output io_mhpmc_inc_r_d1_3, + output io_perfcnt_halted_d1, + output io_mdseac_locked_f, + output io_lsu_single_ecc_error_r_d1, + output io_lsu_i0_exc_r_d1, + output io_take_ext_int_start_d1, + output io_take_ext_int_start_d2, + output io_take_ext_int_start_d3, + output io_ext_int_freeze_d1, + output [5:0] io_mip, + input io_mdseac_locked_ns, + input io_lsu_single_ecc_error_r, + input io_lsu_i0_exc_r, + input io_take_ext_int_start, + input io_ext_int_freeze, + input [5:0] io_mip_ns, + input io_mcyclel_cout, + input io_wr_mcycleh_r, + input io_mcyclel_cout_in, + input io_minstret_enable, + input io_minstretl_cout_ns, + input [3:0] io_meicidpl_ns, + input io_icache_rd_valid, + input io_icache_wr_valid, + input io_perfcnt_halted, + input [1:0] io_mstatus_ns, + input io_free_l2clk +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; +`endif // RANDOMIZE_REG_INIT + wire [3:0] _T_1 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1; // @[dec_tlu_ctl.scala 2795:66] + wire _T_3 = ~io_mcountinhibit[3]; // @[dec_tlu_ctl.scala 2797:40] + wire _T_4 = io_mhpme_vec_0 == 10'h1; // @[dec_tlu_ctl.scala 2798:42] + wire _T_6 = io_mhpme_vec_0 == 10'h2; // @[dec_tlu_ctl.scala 2799:42] + wire _T_8 = io_mhpme_vec_0 == 10'h3; // @[dec_tlu_ctl.scala 2800:42] + wire _T_10 = io_mhpme_vec_0 == 10'h4; // @[dec_tlu_ctl.scala 2801:42] + wire _T_12 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2801:104] + wire _T_13 = io_tlu_i0_commit_cmt & _T_12; // @[dec_tlu_ctl.scala 2801:102] + wire _T_14 = io_mhpme_vec_0 == 10'h5; // @[dec_tlu_ctl.scala 2802:42] + wire _T_16 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2802:104] + wire _T_17 = io_tlu_i0_commit_cmt & _T_16; // @[dec_tlu_ctl.scala 2802:102] + wire _T_19 = _T_17 & _T_12; // @[dec_tlu_ctl.scala 2802:123] + wire _T_20 = io_mhpme_vec_0 == 10'h6; // @[dec_tlu_ctl.scala 2803:42] + wire _T_22 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2803:102] + wire _T_24 = _T_22 & _T_12; // @[dec_tlu_ctl.scala 2803:123] + wire _T_25 = io_mhpme_vec_0 == 10'h7; // @[dec_tlu_ctl.scala 2805:42] + wire _T_27 = io_mhpme_vec_0 == 10'h8; // @[dec_tlu_ctl.scala 2806:42] + wire _T_29 = io_mhpme_vec_0 == 10'h1e; // @[dec_tlu_ctl.scala 2807:42] + wire _T_31 = io_mhpme_vec_0 == 10'h9; // @[dec_tlu_ctl.scala 2808:42] + wire _T_33 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2808:99] + wire _T_34 = io_mhpme_vec_0 == 10'ha; // @[dec_tlu_ctl.scala 2809:42] + wire _T_36 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2809:113] + wire _T_38 = _T_36 & _T_12; // @[dec_tlu_ctl.scala 2809:136] + wire _T_39 = io_mhpme_vec_0 == 10'hb; // @[dec_tlu_ctl.scala 2810:42] + wire _T_41 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2810:99] + wire _T_42 = io_mhpme_vec_0 == 10'hc; // @[dec_tlu_ctl.scala 2811:42] + wire _T_44 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2811:99] + wire _T_45 = io_mhpme_vec_0 == 10'hd; // @[dec_tlu_ctl.scala 2812:42] + wire _T_48 = _T_41 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2812:108] + wire _T_49 = io_mhpme_vec_0 == 10'he; // @[dec_tlu_ctl.scala 2813:42] + wire _T_53 = _T_44 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2813:109] + wire _T_54 = io_mhpme_vec_0 == 10'hf; // @[dec_tlu_ctl.scala 2815:42] + wire _T_56 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2815:97] + wire _T_57 = io_mhpme_vec_0 == 10'h10; // @[dec_tlu_ctl.scala 2816:42] + wire _T_59 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2816:97] + wire _T_60 = io_mhpme_vec_0 == 10'h12; // @[dec_tlu_ctl.scala 2817:42] + wire _T_62 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2817:97] + wire _T_63 = io_mhpme_vec_0 == 10'h11; // @[dec_tlu_ctl.scala 2818:42] + wire _T_65 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2818:97] + wire _T_66 = io_mhpme_vec_0 == 10'h13; // @[dec_tlu_ctl.scala 2819:42] + wire _T_68 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2819:97] + wire _T_69 = io_mhpme_vec_0 == 10'h14; // @[dec_tlu_ctl.scala 2820:42] + wire _T_71 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2820:97] + wire _T_72 = io_mhpme_vec_0 == 10'h15; // @[dec_tlu_ctl.scala 2821:42] + wire _T_74 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2821:97] + wire _T_75 = io_mhpme_vec_0 == 10'h16; // @[dec_tlu_ctl.scala 2822:42] + wire _T_77 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2822:97] + wire _T_78 = io_mhpme_vec_0 == 10'h17; // @[dec_tlu_ctl.scala 2823:42] + wire _T_80 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2823:97] + wire _T_81 = io_mhpme_vec_0 == 10'h18; // @[dec_tlu_ctl.scala 2824:42] + wire _T_83 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2824:97] + wire _T_84 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2824:130] + wire _T_85 = _T_83 | _T_84; // @[dec_tlu_ctl.scala 2824:109] + wire _T_86 = io_mhpme_vec_0 == 10'h19; // @[dec_tlu_ctl.scala 2826:42] + wire _T_88 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2826:103] + wire _T_90 = _T_88 & _T_12; // @[dec_tlu_ctl.scala 2826:126] + wire _T_91 = io_mhpme_vec_0 == 10'h1a; // @[dec_tlu_ctl.scala 2827:42] + wire _T_93 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2827:105] + wire _T_95 = _T_93 & _T_12; // @[dec_tlu_ctl.scala 2827:128] + wire _T_96 = io_mhpme_vec_0 == 10'h1b; // @[dec_tlu_ctl.scala 2828:42] + wire _T_98 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2828:118] + wire _T_100 = _T_98 & _T_12; // @[dec_tlu_ctl.scala 2828:141] + wire _T_101 = io_mhpme_vec_0 == 10'h1c; // @[dec_tlu_ctl.scala 2829:42] + wire _T_105 = io_mhpme_vec_0 == 10'h1f; // @[dec_tlu_ctl.scala 2831:42] + wire _T_107 = io_mhpme_vec_0 == 10'h20; // @[dec_tlu_ctl.scala 2832:42] + wire _T_109 = io_mhpme_vec_0 == 10'h22; // @[dec_tlu_ctl.scala 2833:42] + wire _T_111 = io_mhpme_vec_0 == 10'h23; // @[dec_tlu_ctl.scala 2834:42] + wire _T_113 = io_mhpme_vec_0 == 10'h24; // @[dec_tlu_ctl.scala 2835:42] + wire _T_115 = io_mhpme_vec_0 == 10'h25; // @[dec_tlu_ctl.scala 2836:42] + wire _T_117 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2836:106] + wire _T_118 = _T_117 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2836:128] + wire _T_119 = io_mhpme_vec_0 == 10'h26; // @[dec_tlu_ctl.scala 2837:42] + wire _T_121 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2837:100] + wire _T_122 = _T_121 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2837:125] + wire _T_123 = io_mhpme_vec_0 == 10'h27; // @[dec_tlu_ctl.scala 2838:42] + wire _T_125 = io_mhpme_vec_0 == 10'h28; // @[dec_tlu_ctl.scala 2839:42] + wire _T_127 = io_mhpme_vec_0 == 10'h29; // @[dec_tlu_ctl.scala 2840:42] + wire _T_129 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2840:105] + wire _T_130 = _T_129 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2840:137] + wire _T_131 = io_mhpme_vec_0 == 10'h2a; // @[dec_tlu_ctl.scala 2842:42] + wire _T_133 = io_mhpme_vec_0 == 10'h2b; // @[dec_tlu_ctl.scala 2843:42] + wire _T_135 = io_mhpme_vec_0 == 10'h2c; // @[dec_tlu_ctl.scala 2844:42] + wire _T_137 = io_mhpme_vec_0 == 10'h2d; // @[dec_tlu_ctl.scala 2845:42] + wire _T_139 = io_mhpme_vec_0 == 10'h2e; // @[dec_tlu_ctl.scala 2846:42] + wire _T_141 = io_mhpme_vec_0 == 10'h2f; // @[dec_tlu_ctl.scala 2847:42] + wire _T_143 = io_mhpme_vec_0 == 10'h30; // @[dec_tlu_ctl.scala 2848:42] + wire _T_145 = io_mhpme_vec_0 == 10'h31; // @[dec_tlu_ctl.scala 2849:42] + wire _T_149 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2849:81] + wire _T_150 = io_mhpme_vec_0 == 10'h32; // @[dec_tlu_ctl.scala 2850:42] + wire [5:0] _T_157 = io_mip & io_mie; // @[dec_tlu_ctl.scala 2850:121] + wire _T_158 = |_T_157; // @[dec_tlu_ctl.scala 2850:136] + wire _T_159 = _T_149 & _T_158; // @[dec_tlu_ctl.scala 2850:106] + wire _T_160 = io_mhpme_vec_0 == 10'h36; // @[dec_tlu_ctl.scala 2851:42] + wire _T_162 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2851:99] + wire _T_163 = io_mhpme_vec_0 == 10'h37; // @[dec_tlu_ctl.scala 2852:42] + wire _T_165 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2852:102] + wire _T_167 = _T_165 & _T_12; // @[dec_tlu_ctl.scala 2852:131] + wire _T_168 = io_mhpme_vec_0 == 10'h38; // @[dec_tlu_ctl.scala 2853:42] + wire _T_170 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2853:102] + wire _T_172 = _T_170 & _T_12; // @[dec_tlu_ctl.scala 2853:132] + wire _T_173 = io_mhpme_vec_0 == 10'h200; // @[dec_tlu_ctl.scala 2855:42] + wire _T_175 = io_mhpme_vec_0 == 10'h201; // @[dec_tlu_ctl.scala 2856:42] + wire _T_177 = io_mhpme_vec_0 == 10'h202; // @[dec_tlu_ctl.scala 2857:42] + wire _T_179 = io_mhpme_vec_0 == 10'h203; // @[dec_tlu_ctl.scala 2858:42] + wire _T_181 = io_mhpme_vec_0 == 10'h204; // @[dec_tlu_ctl.scala 2859:42] + wire _T_184 = _T_6 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_185 = _T_8 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_186 = _T_10 & _T_13; // @[Mux.scala 27:72] + wire _T_187 = _T_14 & _T_19; // @[Mux.scala 27:72] + wire _T_188 = _T_20 & _T_24; // @[Mux.scala 27:72] + wire _T_189 = _T_25 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_190 = _T_27 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_191 = _T_29 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_192 = _T_31 & _T_33; // @[Mux.scala 27:72] + wire _T_193 = _T_34 & _T_38; // @[Mux.scala 27:72] + wire _T_194 = _T_39 & _T_41; // @[Mux.scala 27:72] + wire _T_195 = _T_42 & _T_44; // @[Mux.scala 27:72] + wire _T_196 = _T_45 & _T_48; // @[Mux.scala 27:72] + wire _T_197 = _T_49 & _T_53; // @[Mux.scala 27:72] + wire _T_198 = _T_54 & _T_56; // @[Mux.scala 27:72] + wire _T_199 = _T_57 & _T_59; // @[Mux.scala 27:72] + wire _T_200 = _T_60 & _T_62; // @[Mux.scala 27:72] + wire _T_201 = _T_63 & _T_65; // @[Mux.scala 27:72] + wire _T_202 = _T_66 & _T_68; // @[Mux.scala 27:72] + wire _T_203 = _T_69 & _T_71; // @[Mux.scala 27:72] + wire _T_204 = _T_72 & _T_74; // @[Mux.scala 27:72] + wire _T_205 = _T_75 & _T_77; // @[Mux.scala 27:72] + wire _T_206 = _T_78 & _T_80; // @[Mux.scala 27:72] + wire _T_207 = _T_81 & _T_85; // @[Mux.scala 27:72] + wire _T_208 = _T_86 & _T_90; // @[Mux.scala 27:72] + wire _T_209 = _T_91 & _T_95; // @[Mux.scala 27:72] + wire _T_210 = _T_96 & _T_100; // @[Mux.scala 27:72] + wire _T_211 = _T_101 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_213 = _T_105 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_214 = _T_107 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_215 = _T_109 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_216 = _T_111 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_217 = _T_113 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_218 = _T_115 & _T_118; // @[Mux.scala 27:72] + wire _T_219 = _T_119 & _T_122; // @[Mux.scala 27:72] + wire _T_220 = _T_123 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_221 = _T_125 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_222 = _T_127 & _T_130; // @[Mux.scala 27:72] + wire _T_223 = _T_131 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_224 = _T_133 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_225 = _T_135 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_226 = _T_137 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_227 = _T_139 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_228 = _T_141 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_229 = _T_143 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_230 = _T_145 & _T_149; // @[Mux.scala 27:72] + wire _T_231 = _T_150 & _T_159; // @[Mux.scala 27:72] + wire _T_232 = _T_160 & _T_162; // @[Mux.scala 27:72] + wire _T_233 = _T_163 & _T_167; // @[Mux.scala 27:72] + wire _T_234 = _T_168 & _T_172; // @[Mux.scala 27:72] + wire _T_235 = _T_173 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_236 = _T_175 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_237 = _T_177 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_238 = _T_179 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_239 = _T_181 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_240 = _T_4 | _T_184; // @[Mux.scala 27:72] + wire _T_241 = _T_240 | _T_185; // @[Mux.scala 27:72] + wire _T_242 = _T_241 | _T_186; // @[Mux.scala 27:72] + wire _T_243 = _T_242 | _T_187; // @[Mux.scala 27:72] + wire _T_244 = _T_243 | _T_188; // @[Mux.scala 27:72] + wire _T_245 = _T_244 | _T_189; // @[Mux.scala 27:72] + wire _T_246 = _T_245 | _T_190; // @[Mux.scala 27:72] + wire _T_247 = _T_246 | _T_191; // @[Mux.scala 27:72] + wire _T_248 = _T_247 | _T_192; // @[Mux.scala 27:72] + wire _T_249 = _T_248 | _T_193; // @[Mux.scala 27:72] + wire _T_250 = _T_249 | _T_194; // @[Mux.scala 27:72] + wire _T_251 = _T_250 | _T_195; // @[Mux.scala 27:72] + wire _T_252 = _T_251 | _T_196; // @[Mux.scala 27:72] + wire _T_253 = _T_252 | _T_197; // @[Mux.scala 27:72] + wire _T_254 = _T_253 | _T_198; // @[Mux.scala 27:72] + wire _T_255 = _T_254 | _T_199; // @[Mux.scala 27:72] + wire _T_256 = _T_255 | _T_200; // @[Mux.scala 27:72] + wire _T_257 = _T_256 | _T_201; // @[Mux.scala 27:72] + wire _T_258 = _T_257 | _T_202; // @[Mux.scala 27:72] + wire _T_259 = _T_258 | _T_203; // @[Mux.scala 27:72] + wire _T_260 = _T_259 | _T_204; // @[Mux.scala 27:72] + wire _T_261 = _T_260 | _T_205; // @[Mux.scala 27:72] + wire _T_262 = _T_261 | _T_206; // @[Mux.scala 27:72] + wire _T_263 = _T_262 | _T_207; // @[Mux.scala 27:72] + wire _T_264 = _T_263 | _T_208; // @[Mux.scala 27:72] + wire _T_265 = _T_264 | _T_209; // @[Mux.scala 27:72] + wire _T_266 = _T_265 | _T_210; // @[Mux.scala 27:72] + wire _T_267 = _T_266 | _T_211; // @[Mux.scala 27:72] + wire _T_268 = _T_267 | _T_191; // @[Mux.scala 27:72] + wire _T_269 = _T_268 | _T_213; // @[Mux.scala 27:72] + wire _T_270 = _T_269 | _T_214; // @[Mux.scala 27:72] + wire _T_271 = _T_270 | _T_215; // @[Mux.scala 27:72] + wire _T_272 = _T_271 | _T_216; // @[Mux.scala 27:72] + wire _T_273 = _T_272 | _T_217; // @[Mux.scala 27:72] + wire _T_274 = _T_273 | _T_218; // @[Mux.scala 27:72] + wire _T_275 = _T_274 | _T_219; // @[Mux.scala 27:72] + wire _T_276 = _T_275 | _T_220; // @[Mux.scala 27:72] + wire _T_277 = _T_276 | _T_221; // @[Mux.scala 27:72] + wire _T_278 = _T_277 | _T_222; // @[Mux.scala 27:72] + wire _T_279 = _T_278 | _T_223; // @[Mux.scala 27:72] + wire _T_280 = _T_279 | _T_224; // @[Mux.scala 27:72] + wire _T_281 = _T_280 | _T_225; // @[Mux.scala 27:72] + wire _T_282 = _T_281 | _T_226; // @[Mux.scala 27:72] + wire _T_283 = _T_282 | _T_227; // @[Mux.scala 27:72] + wire _T_284 = _T_283 | _T_228; // @[Mux.scala 27:72] + wire _T_285 = _T_284 | _T_229; // @[Mux.scala 27:72] + wire _T_286 = _T_285 | _T_230; // @[Mux.scala 27:72] + wire _T_287 = _T_286 | _T_231; // @[Mux.scala 27:72] + wire _T_288 = _T_287 | _T_232; // @[Mux.scala 27:72] + wire _T_289 = _T_288 | _T_233; // @[Mux.scala 27:72] + wire _T_290 = _T_289 | _T_234; // @[Mux.scala 27:72] + wire _T_291 = _T_290 | _T_235; // @[Mux.scala 27:72] + wire _T_292 = _T_291 | _T_236; // @[Mux.scala 27:72] + wire _T_293 = _T_292 | _T_237; // @[Mux.scala 27:72] + wire _T_294 = _T_293 | _T_238; // @[Mux.scala 27:72] + wire _T_295 = _T_294 | _T_239; // @[Mux.scala 27:72] + wire _T_299 = ~io_mcountinhibit[4]; // @[dec_tlu_ctl.scala 2797:40] + wire _T_300 = io_mhpme_vec_1 == 10'h1; // @[dec_tlu_ctl.scala 2798:42] + wire _T_302 = io_mhpme_vec_1 == 10'h2; // @[dec_tlu_ctl.scala 2799:42] + wire _T_304 = io_mhpme_vec_1 == 10'h3; // @[dec_tlu_ctl.scala 2800:42] + wire _T_306 = io_mhpme_vec_1 == 10'h4; // @[dec_tlu_ctl.scala 2801:42] + wire _T_310 = io_mhpme_vec_1 == 10'h5; // @[dec_tlu_ctl.scala 2802:42] + wire _T_316 = io_mhpme_vec_1 == 10'h6; // @[dec_tlu_ctl.scala 2803:42] + wire _T_321 = io_mhpme_vec_1 == 10'h7; // @[dec_tlu_ctl.scala 2805:42] + wire _T_323 = io_mhpme_vec_1 == 10'h8; // @[dec_tlu_ctl.scala 2806:42] + wire _T_325 = io_mhpme_vec_1 == 10'h1e; // @[dec_tlu_ctl.scala 2807:42] + wire _T_327 = io_mhpme_vec_1 == 10'h9; // @[dec_tlu_ctl.scala 2808:42] + wire _T_330 = io_mhpme_vec_1 == 10'ha; // @[dec_tlu_ctl.scala 2809:42] + wire _T_335 = io_mhpme_vec_1 == 10'hb; // @[dec_tlu_ctl.scala 2810:42] + wire _T_338 = io_mhpme_vec_1 == 10'hc; // @[dec_tlu_ctl.scala 2811:42] + wire _T_341 = io_mhpme_vec_1 == 10'hd; // @[dec_tlu_ctl.scala 2812:42] + wire _T_345 = io_mhpme_vec_1 == 10'he; // @[dec_tlu_ctl.scala 2813:42] + wire _T_350 = io_mhpme_vec_1 == 10'hf; // @[dec_tlu_ctl.scala 2815:42] + wire _T_353 = io_mhpme_vec_1 == 10'h10; // @[dec_tlu_ctl.scala 2816:42] + wire _T_356 = io_mhpme_vec_1 == 10'h12; // @[dec_tlu_ctl.scala 2817:42] + wire _T_359 = io_mhpme_vec_1 == 10'h11; // @[dec_tlu_ctl.scala 2818:42] + wire _T_362 = io_mhpme_vec_1 == 10'h13; // @[dec_tlu_ctl.scala 2819:42] + wire _T_365 = io_mhpme_vec_1 == 10'h14; // @[dec_tlu_ctl.scala 2820:42] + wire _T_368 = io_mhpme_vec_1 == 10'h15; // @[dec_tlu_ctl.scala 2821:42] + wire _T_371 = io_mhpme_vec_1 == 10'h16; // @[dec_tlu_ctl.scala 2822:42] + wire _T_374 = io_mhpme_vec_1 == 10'h17; // @[dec_tlu_ctl.scala 2823:42] + wire _T_377 = io_mhpme_vec_1 == 10'h18; // @[dec_tlu_ctl.scala 2824:42] + wire _T_382 = io_mhpme_vec_1 == 10'h19; // @[dec_tlu_ctl.scala 2826:42] + wire _T_387 = io_mhpme_vec_1 == 10'h1a; // @[dec_tlu_ctl.scala 2827:42] + wire _T_392 = io_mhpme_vec_1 == 10'h1b; // @[dec_tlu_ctl.scala 2828:42] + wire _T_397 = io_mhpme_vec_1 == 10'h1c; // @[dec_tlu_ctl.scala 2829:42] + wire _T_401 = io_mhpme_vec_1 == 10'h1f; // @[dec_tlu_ctl.scala 2831:42] + wire _T_403 = io_mhpme_vec_1 == 10'h20; // @[dec_tlu_ctl.scala 2832:42] + wire _T_405 = io_mhpme_vec_1 == 10'h22; // @[dec_tlu_ctl.scala 2833:42] + wire _T_407 = io_mhpme_vec_1 == 10'h23; // @[dec_tlu_ctl.scala 2834:42] + wire _T_409 = io_mhpme_vec_1 == 10'h24; // @[dec_tlu_ctl.scala 2835:42] + wire _T_411 = io_mhpme_vec_1 == 10'h25; // @[dec_tlu_ctl.scala 2836:42] + wire _T_415 = io_mhpme_vec_1 == 10'h26; // @[dec_tlu_ctl.scala 2837:42] + wire _T_419 = io_mhpme_vec_1 == 10'h27; // @[dec_tlu_ctl.scala 2838:42] + wire _T_421 = io_mhpme_vec_1 == 10'h28; // @[dec_tlu_ctl.scala 2839:42] + wire _T_423 = io_mhpme_vec_1 == 10'h29; // @[dec_tlu_ctl.scala 2840:42] + wire _T_427 = io_mhpme_vec_1 == 10'h2a; // @[dec_tlu_ctl.scala 2842:42] + wire _T_429 = io_mhpme_vec_1 == 10'h2b; // @[dec_tlu_ctl.scala 2843:42] + wire _T_431 = io_mhpme_vec_1 == 10'h2c; // @[dec_tlu_ctl.scala 2844:42] + wire _T_433 = io_mhpme_vec_1 == 10'h2d; // @[dec_tlu_ctl.scala 2845:42] + wire _T_435 = io_mhpme_vec_1 == 10'h2e; // @[dec_tlu_ctl.scala 2846:42] + wire _T_437 = io_mhpme_vec_1 == 10'h2f; // @[dec_tlu_ctl.scala 2847:42] + wire _T_439 = io_mhpme_vec_1 == 10'h30; // @[dec_tlu_ctl.scala 2848:42] + wire _T_441 = io_mhpme_vec_1 == 10'h31; // @[dec_tlu_ctl.scala 2849:42] + wire _T_446 = io_mhpme_vec_1 == 10'h32; // @[dec_tlu_ctl.scala 2850:42] + wire _T_456 = io_mhpme_vec_1 == 10'h36; // @[dec_tlu_ctl.scala 2851:42] + wire _T_459 = io_mhpme_vec_1 == 10'h37; // @[dec_tlu_ctl.scala 2852:42] + wire _T_464 = io_mhpme_vec_1 == 10'h38; // @[dec_tlu_ctl.scala 2853:42] + wire _T_469 = io_mhpme_vec_1 == 10'h200; // @[dec_tlu_ctl.scala 2855:42] + wire _T_471 = io_mhpme_vec_1 == 10'h201; // @[dec_tlu_ctl.scala 2856:42] + wire _T_473 = io_mhpme_vec_1 == 10'h202; // @[dec_tlu_ctl.scala 2857:42] + wire _T_475 = io_mhpme_vec_1 == 10'h203; // @[dec_tlu_ctl.scala 2858:42] + wire _T_477 = io_mhpme_vec_1 == 10'h204; // @[dec_tlu_ctl.scala 2859:42] + wire _T_480 = _T_302 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_481 = _T_304 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_482 = _T_306 & _T_13; // @[Mux.scala 27:72] + wire _T_483 = _T_310 & _T_19; // @[Mux.scala 27:72] + wire _T_484 = _T_316 & _T_24; // @[Mux.scala 27:72] + wire _T_485 = _T_321 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_486 = _T_323 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_487 = _T_325 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_488 = _T_327 & _T_33; // @[Mux.scala 27:72] + wire _T_489 = _T_330 & _T_38; // @[Mux.scala 27:72] + wire _T_490 = _T_335 & _T_41; // @[Mux.scala 27:72] + wire _T_491 = _T_338 & _T_44; // @[Mux.scala 27:72] + wire _T_492 = _T_341 & _T_48; // @[Mux.scala 27:72] + wire _T_493 = _T_345 & _T_53; // @[Mux.scala 27:72] + wire _T_494 = _T_350 & _T_56; // @[Mux.scala 27:72] + wire _T_495 = _T_353 & _T_59; // @[Mux.scala 27:72] + wire _T_496 = _T_356 & _T_62; // @[Mux.scala 27:72] + wire _T_497 = _T_359 & _T_65; // @[Mux.scala 27:72] + wire _T_498 = _T_362 & _T_68; // @[Mux.scala 27:72] + wire _T_499 = _T_365 & _T_71; // @[Mux.scala 27:72] + wire _T_500 = _T_368 & _T_74; // @[Mux.scala 27:72] + wire _T_501 = _T_371 & _T_77; // @[Mux.scala 27:72] + wire _T_502 = _T_374 & _T_80; // @[Mux.scala 27:72] + wire _T_503 = _T_377 & _T_85; // @[Mux.scala 27:72] + wire _T_504 = _T_382 & _T_90; // @[Mux.scala 27:72] + wire _T_505 = _T_387 & _T_95; // @[Mux.scala 27:72] + wire _T_506 = _T_392 & _T_100; // @[Mux.scala 27:72] + wire _T_507 = _T_397 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_509 = _T_401 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_510 = _T_403 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_511 = _T_405 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_512 = _T_407 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_513 = _T_409 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_514 = _T_411 & _T_118; // @[Mux.scala 27:72] + wire _T_515 = _T_415 & _T_122; // @[Mux.scala 27:72] + wire _T_516 = _T_419 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_517 = _T_421 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_518 = _T_423 & _T_130; // @[Mux.scala 27:72] + wire _T_519 = _T_427 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_520 = _T_429 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_521 = _T_431 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_522 = _T_433 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_523 = _T_435 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_524 = _T_437 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_525 = _T_439 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_526 = _T_441 & _T_149; // @[Mux.scala 27:72] + wire _T_527 = _T_446 & _T_159; // @[Mux.scala 27:72] + wire _T_528 = _T_456 & _T_162; // @[Mux.scala 27:72] + wire _T_529 = _T_459 & _T_167; // @[Mux.scala 27:72] + wire _T_530 = _T_464 & _T_172; // @[Mux.scala 27:72] + wire _T_531 = _T_469 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_532 = _T_471 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_533 = _T_473 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_534 = _T_475 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_535 = _T_477 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_536 = _T_300 | _T_480; // @[Mux.scala 27:72] + wire _T_537 = _T_536 | _T_481; // @[Mux.scala 27:72] + wire _T_538 = _T_537 | _T_482; // @[Mux.scala 27:72] + wire _T_539 = _T_538 | _T_483; // @[Mux.scala 27:72] + wire _T_540 = _T_539 | _T_484; // @[Mux.scala 27:72] + wire _T_541 = _T_540 | _T_485; // @[Mux.scala 27:72] + wire _T_542 = _T_541 | _T_486; // @[Mux.scala 27:72] + wire _T_543 = _T_542 | _T_487; // @[Mux.scala 27:72] + wire _T_544 = _T_543 | _T_488; // @[Mux.scala 27:72] + wire _T_545 = _T_544 | _T_489; // @[Mux.scala 27:72] + wire _T_546 = _T_545 | _T_490; // @[Mux.scala 27:72] + wire _T_547 = _T_546 | _T_491; // @[Mux.scala 27:72] + wire _T_548 = _T_547 | _T_492; // @[Mux.scala 27:72] + wire _T_549 = _T_548 | _T_493; // @[Mux.scala 27:72] + wire _T_550 = _T_549 | _T_494; // @[Mux.scala 27:72] + wire _T_551 = _T_550 | _T_495; // @[Mux.scala 27:72] + wire _T_552 = _T_551 | _T_496; // @[Mux.scala 27:72] + wire _T_553 = _T_552 | _T_497; // @[Mux.scala 27:72] + wire _T_554 = _T_553 | _T_498; // @[Mux.scala 27:72] + wire _T_555 = _T_554 | _T_499; // @[Mux.scala 27:72] + wire _T_556 = _T_555 | _T_500; // @[Mux.scala 27:72] + wire _T_557 = _T_556 | _T_501; // @[Mux.scala 27:72] + wire _T_558 = _T_557 | _T_502; // @[Mux.scala 27:72] + wire _T_559 = _T_558 | _T_503; // @[Mux.scala 27:72] + wire _T_560 = _T_559 | _T_504; // @[Mux.scala 27:72] + wire _T_561 = _T_560 | _T_505; // @[Mux.scala 27:72] + wire _T_562 = _T_561 | _T_506; // @[Mux.scala 27:72] + wire _T_563 = _T_562 | _T_507; // @[Mux.scala 27:72] + wire _T_564 = _T_563 | _T_487; // @[Mux.scala 27:72] + wire _T_565 = _T_564 | _T_509; // @[Mux.scala 27:72] + wire _T_566 = _T_565 | _T_510; // @[Mux.scala 27:72] + wire _T_567 = _T_566 | _T_511; // @[Mux.scala 27:72] + wire _T_568 = _T_567 | _T_512; // @[Mux.scala 27:72] + wire _T_569 = _T_568 | _T_513; // @[Mux.scala 27:72] + wire _T_570 = _T_569 | _T_514; // @[Mux.scala 27:72] + wire _T_571 = _T_570 | _T_515; // @[Mux.scala 27:72] + wire _T_572 = _T_571 | _T_516; // @[Mux.scala 27:72] + wire _T_573 = _T_572 | _T_517; // @[Mux.scala 27:72] + wire _T_574 = _T_573 | _T_518; // @[Mux.scala 27:72] + wire _T_575 = _T_574 | _T_519; // @[Mux.scala 27:72] + wire _T_576 = _T_575 | _T_520; // @[Mux.scala 27:72] + wire _T_577 = _T_576 | _T_521; // @[Mux.scala 27:72] + wire _T_578 = _T_577 | _T_522; // @[Mux.scala 27:72] + wire _T_579 = _T_578 | _T_523; // @[Mux.scala 27:72] + wire _T_580 = _T_579 | _T_524; // @[Mux.scala 27:72] + wire _T_581 = _T_580 | _T_525; // @[Mux.scala 27:72] + wire _T_582 = _T_581 | _T_526; // @[Mux.scala 27:72] + wire _T_583 = _T_582 | _T_527; // @[Mux.scala 27:72] + wire _T_584 = _T_583 | _T_528; // @[Mux.scala 27:72] + wire _T_585 = _T_584 | _T_529; // @[Mux.scala 27:72] + wire _T_586 = _T_585 | _T_530; // @[Mux.scala 27:72] + wire _T_587 = _T_586 | _T_531; // @[Mux.scala 27:72] + wire _T_588 = _T_587 | _T_532; // @[Mux.scala 27:72] + wire _T_589 = _T_588 | _T_533; // @[Mux.scala 27:72] + wire _T_590 = _T_589 | _T_534; // @[Mux.scala 27:72] + wire _T_591 = _T_590 | _T_535; // @[Mux.scala 27:72] + wire _T_595 = ~io_mcountinhibit[5]; // @[dec_tlu_ctl.scala 2797:40] + wire _T_596 = io_mhpme_vec_2 == 10'h1; // @[dec_tlu_ctl.scala 2798:42] + wire _T_598 = io_mhpme_vec_2 == 10'h2; // @[dec_tlu_ctl.scala 2799:42] + wire _T_600 = io_mhpme_vec_2 == 10'h3; // @[dec_tlu_ctl.scala 2800:42] + wire _T_602 = io_mhpme_vec_2 == 10'h4; // @[dec_tlu_ctl.scala 2801:42] + wire _T_606 = io_mhpme_vec_2 == 10'h5; // @[dec_tlu_ctl.scala 2802:42] + wire _T_612 = io_mhpme_vec_2 == 10'h6; // @[dec_tlu_ctl.scala 2803:42] + wire _T_617 = io_mhpme_vec_2 == 10'h7; // @[dec_tlu_ctl.scala 2805:42] + wire _T_619 = io_mhpme_vec_2 == 10'h8; // @[dec_tlu_ctl.scala 2806:42] + wire _T_621 = io_mhpme_vec_2 == 10'h1e; // @[dec_tlu_ctl.scala 2807:42] + wire _T_623 = io_mhpme_vec_2 == 10'h9; // @[dec_tlu_ctl.scala 2808:42] + wire _T_626 = io_mhpme_vec_2 == 10'ha; // @[dec_tlu_ctl.scala 2809:42] + wire _T_631 = io_mhpme_vec_2 == 10'hb; // @[dec_tlu_ctl.scala 2810:42] + wire _T_634 = io_mhpme_vec_2 == 10'hc; // @[dec_tlu_ctl.scala 2811:42] + wire _T_637 = io_mhpme_vec_2 == 10'hd; // @[dec_tlu_ctl.scala 2812:42] + wire _T_641 = io_mhpme_vec_2 == 10'he; // @[dec_tlu_ctl.scala 2813:42] + wire _T_646 = io_mhpme_vec_2 == 10'hf; // @[dec_tlu_ctl.scala 2815:42] + wire _T_649 = io_mhpme_vec_2 == 10'h10; // @[dec_tlu_ctl.scala 2816:42] + wire _T_652 = io_mhpme_vec_2 == 10'h12; // @[dec_tlu_ctl.scala 2817:42] + wire _T_655 = io_mhpme_vec_2 == 10'h11; // @[dec_tlu_ctl.scala 2818:42] + wire _T_658 = io_mhpme_vec_2 == 10'h13; // @[dec_tlu_ctl.scala 2819:42] + wire _T_661 = io_mhpme_vec_2 == 10'h14; // @[dec_tlu_ctl.scala 2820:42] + wire _T_664 = io_mhpme_vec_2 == 10'h15; // @[dec_tlu_ctl.scala 2821:42] + wire _T_667 = io_mhpme_vec_2 == 10'h16; // @[dec_tlu_ctl.scala 2822:42] + wire _T_670 = io_mhpme_vec_2 == 10'h17; // @[dec_tlu_ctl.scala 2823:42] + wire _T_673 = io_mhpme_vec_2 == 10'h18; // @[dec_tlu_ctl.scala 2824:42] + wire _T_678 = io_mhpme_vec_2 == 10'h19; // @[dec_tlu_ctl.scala 2826:42] + wire _T_683 = io_mhpme_vec_2 == 10'h1a; // @[dec_tlu_ctl.scala 2827:42] + wire _T_688 = io_mhpme_vec_2 == 10'h1b; // @[dec_tlu_ctl.scala 2828:42] + wire _T_693 = io_mhpme_vec_2 == 10'h1c; // @[dec_tlu_ctl.scala 2829:42] + wire _T_697 = io_mhpme_vec_2 == 10'h1f; // @[dec_tlu_ctl.scala 2831:42] + wire _T_699 = io_mhpme_vec_2 == 10'h20; // @[dec_tlu_ctl.scala 2832:42] + wire _T_701 = io_mhpme_vec_2 == 10'h22; // @[dec_tlu_ctl.scala 2833:42] + wire _T_703 = io_mhpme_vec_2 == 10'h23; // @[dec_tlu_ctl.scala 2834:42] + wire _T_705 = io_mhpme_vec_2 == 10'h24; // @[dec_tlu_ctl.scala 2835:42] + wire _T_707 = io_mhpme_vec_2 == 10'h25; // @[dec_tlu_ctl.scala 2836:42] + wire _T_711 = io_mhpme_vec_2 == 10'h26; // @[dec_tlu_ctl.scala 2837:42] + wire _T_715 = io_mhpme_vec_2 == 10'h27; // @[dec_tlu_ctl.scala 2838:42] + wire _T_717 = io_mhpme_vec_2 == 10'h28; // @[dec_tlu_ctl.scala 2839:42] + wire _T_719 = io_mhpme_vec_2 == 10'h29; // @[dec_tlu_ctl.scala 2840:42] + wire _T_723 = io_mhpme_vec_2 == 10'h2a; // @[dec_tlu_ctl.scala 2842:42] + wire _T_725 = io_mhpme_vec_2 == 10'h2b; // @[dec_tlu_ctl.scala 2843:42] + wire _T_727 = io_mhpme_vec_2 == 10'h2c; // @[dec_tlu_ctl.scala 2844:42] + wire _T_729 = io_mhpme_vec_2 == 10'h2d; // @[dec_tlu_ctl.scala 2845:42] + wire _T_731 = io_mhpme_vec_2 == 10'h2e; // @[dec_tlu_ctl.scala 2846:42] + wire _T_733 = io_mhpme_vec_2 == 10'h2f; // @[dec_tlu_ctl.scala 2847:42] + wire _T_735 = io_mhpme_vec_2 == 10'h30; // @[dec_tlu_ctl.scala 2848:42] + wire _T_737 = io_mhpme_vec_2 == 10'h31; // @[dec_tlu_ctl.scala 2849:42] + wire _T_742 = io_mhpme_vec_2 == 10'h32; // @[dec_tlu_ctl.scala 2850:42] + wire _T_752 = io_mhpme_vec_2 == 10'h36; // @[dec_tlu_ctl.scala 2851:42] + wire _T_755 = io_mhpme_vec_2 == 10'h37; // @[dec_tlu_ctl.scala 2852:42] + wire _T_760 = io_mhpme_vec_2 == 10'h38; // @[dec_tlu_ctl.scala 2853:42] + wire _T_765 = io_mhpme_vec_2 == 10'h200; // @[dec_tlu_ctl.scala 2855:42] + wire _T_767 = io_mhpme_vec_2 == 10'h201; // @[dec_tlu_ctl.scala 2856:42] + wire _T_769 = io_mhpme_vec_2 == 10'h202; // @[dec_tlu_ctl.scala 2857:42] + wire _T_771 = io_mhpme_vec_2 == 10'h203; // @[dec_tlu_ctl.scala 2858:42] + wire _T_773 = io_mhpme_vec_2 == 10'h204; // @[dec_tlu_ctl.scala 2859:42] + wire _T_776 = _T_598 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_777 = _T_600 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_778 = _T_602 & _T_13; // @[Mux.scala 27:72] + wire _T_779 = _T_606 & _T_19; // @[Mux.scala 27:72] + wire _T_780 = _T_612 & _T_24; // @[Mux.scala 27:72] + wire _T_781 = _T_617 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_782 = _T_619 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_783 = _T_621 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_784 = _T_623 & _T_33; // @[Mux.scala 27:72] + wire _T_785 = _T_626 & _T_38; // @[Mux.scala 27:72] + wire _T_786 = _T_631 & _T_41; // @[Mux.scala 27:72] + wire _T_787 = _T_634 & _T_44; // @[Mux.scala 27:72] + wire _T_788 = _T_637 & _T_48; // @[Mux.scala 27:72] + wire _T_789 = _T_641 & _T_53; // @[Mux.scala 27:72] + wire _T_790 = _T_646 & _T_56; // @[Mux.scala 27:72] + wire _T_791 = _T_649 & _T_59; // @[Mux.scala 27:72] + wire _T_792 = _T_652 & _T_62; // @[Mux.scala 27:72] + wire _T_793 = _T_655 & _T_65; // @[Mux.scala 27:72] + wire _T_794 = _T_658 & _T_68; // @[Mux.scala 27:72] + wire _T_795 = _T_661 & _T_71; // @[Mux.scala 27:72] + wire _T_796 = _T_664 & _T_74; // @[Mux.scala 27:72] + wire _T_797 = _T_667 & _T_77; // @[Mux.scala 27:72] + wire _T_798 = _T_670 & _T_80; // @[Mux.scala 27:72] + wire _T_799 = _T_673 & _T_85; // @[Mux.scala 27:72] + wire _T_800 = _T_678 & _T_90; // @[Mux.scala 27:72] + wire _T_801 = _T_683 & _T_95; // @[Mux.scala 27:72] + wire _T_802 = _T_688 & _T_100; // @[Mux.scala 27:72] + wire _T_803 = _T_693 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_805 = _T_697 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_806 = _T_699 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_807 = _T_701 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_808 = _T_703 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_809 = _T_705 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_810 = _T_707 & _T_118; // @[Mux.scala 27:72] + wire _T_811 = _T_711 & _T_122; // @[Mux.scala 27:72] + wire _T_812 = _T_715 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_813 = _T_717 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_814 = _T_719 & _T_130; // @[Mux.scala 27:72] + wire _T_815 = _T_723 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_816 = _T_725 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_817 = _T_727 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_818 = _T_729 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_819 = _T_731 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_820 = _T_733 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_821 = _T_735 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_822 = _T_737 & _T_149; // @[Mux.scala 27:72] + wire _T_823 = _T_742 & _T_159; // @[Mux.scala 27:72] + wire _T_824 = _T_752 & _T_162; // @[Mux.scala 27:72] + wire _T_825 = _T_755 & _T_167; // @[Mux.scala 27:72] + wire _T_826 = _T_760 & _T_172; // @[Mux.scala 27:72] + wire _T_827 = _T_765 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_828 = _T_767 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_829 = _T_769 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_830 = _T_771 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_831 = _T_773 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_832 = _T_596 | _T_776; // @[Mux.scala 27:72] + wire _T_833 = _T_832 | _T_777; // @[Mux.scala 27:72] + wire _T_834 = _T_833 | _T_778; // @[Mux.scala 27:72] + wire _T_835 = _T_834 | _T_779; // @[Mux.scala 27:72] + wire _T_836 = _T_835 | _T_780; // @[Mux.scala 27:72] + wire _T_837 = _T_836 | _T_781; // @[Mux.scala 27:72] + wire _T_838 = _T_837 | _T_782; // @[Mux.scala 27:72] + wire _T_839 = _T_838 | _T_783; // @[Mux.scala 27:72] + wire _T_840 = _T_839 | _T_784; // @[Mux.scala 27:72] + wire _T_841 = _T_840 | _T_785; // @[Mux.scala 27:72] + wire _T_842 = _T_841 | _T_786; // @[Mux.scala 27:72] + wire _T_843 = _T_842 | _T_787; // @[Mux.scala 27:72] + wire _T_844 = _T_843 | _T_788; // @[Mux.scala 27:72] + wire _T_845 = _T_844 | _T_789; // @[Mux.scala 27:72] + wire _T_846 = _T_845 | _T_790; // @[Mux.scala 27:72] + wire _T_847 = _T_846 | _T_791; // @[Mux.scala 27:72] + wire _T_848 = _T_847 | _T_792; // @[Mux.scala 27:72] + wire _T_849 = _T_848 | _T_793; // @[Mux.scala 27:72] + wire _T_850 = _T_849 | _T_794; // @[Mux.scala 27:72] + wire _T_851 = _T_850 | _T_795; // @[Mux.scala 27:72] + wire _T_852 = _T_851 | _T_796; // @[Mux.scala 27:72] + wire _T_853 = _T_852 | _T_797; // @[Mux.scala 27:72] + wire _T_854 = _T_853 | _T_798; // @[Mux.scala 27:72] + wire _T_855 = _T_854 | _T_799; // @[Mux.scala 27:72] + wire _T_856 = _T_855 | _T_800; // @[Mux.scala 27:72] + wire _T_857 = _T_856 | _T_801; // @[Mux.scala 27:72] + wire _T_858 = _T_857 | _T_802; // @[Mux.scala 27:72] + wire _T_859 = _T_858 | _T_803; // @[Mux.scala 27:72] + wire _T_860 = _T_859 | _T_783; // @[Mux.scala 27:72] + wire _T_861 = _T_860 | _T_805; // @[Mux.scala 27:72] + wire _T_862 = _T_861 | _T_806; // @[Mux.scala 27:72] + wire _T_863 = _T_862 | _T_807; // @[Mux.scala 27:72] + wire _T_864 = _T_863 | _T_808; // @[Mux.scala 27:72] + wire _T_865 = _T_864 | _T_809; // @[Mux.scala 27:72] + wire _T_866 = _T_865 | _T_810; // @[Mux.scala 27:72] + wire _T_867 = _T_866 | _T_811; // @[Mux.scala 27:72] + wire _T_868 = _T_867 | _T_812; // @[Mux.scala 27:72] + wire _T_869 = _T_868 | _T_813; // @[Mux.scala 27:72] + wire _T_870 = _T_869 | _T_814; // @[Mux.scala 27:72] + wire _T_871 = _T_870 | _T_815; // @[Mux.scala 27:72] + wire _T_872 = _T_871 | _T_816; // @[Mux.scala 27:72] + wire _T_873 = _T_872 | _T_817; // @[Mux.scala 27:72] + wire _T_874 = _T_873 | _T_818; // @[Mux.scala 27:72] + wire _T_875 = _T_874 | _T_819; // @[Mux.scala 27:72] + wire _T_876 = _T_875 | _T_820; // @[Mux.scala 27:72] + wire _T_877 = _T_876 | _T_821; // @[Mux.scala 27:72] + wire _T_878 = _T_877 | _T_822; // @[Mux.scala 27:72] + wire _T_879 = _T_878 | _T_823; // @[Mux.scala 27:72] + wire _T_880 = _T_879 | _T_824; // @[Mux.scala 27:72] + wire _T_881 = _T_880 | _T_825; // @[Mux.scala 27:72] + wire _T_882 = _T_881 | _T_826; // @[Mux.scala 27:72] + wire _T_883 = _T_882 | _T_827; // @[Mux.scala 27:72] + wire _T_884 = _T_883 | _T_828; // @[Mux.scala 27:72] + wire _T_885 = _T_884 | _T_829; // @[Mux.scala 27:72] + wire _T_886 = _T_885 | _T_830; // @[Mux.scala 27:72] + wire _T_887 = _T_886 | _T_831; // @[Mux.scala 27:72] + wire _T_891 = ~io_mcountinhibit[6]; // @[dec_tlu_ctl.scala 2797:40] + wire _T_892 = io_mhpme_vec_3 == 10'h1; // @[dec_tlu_ctl.scala 2798:42] + wire _T_894 = io_mhpme_vec_3 == 10'h2; // @[dec_tlu_ctl.scala 2799:42] + wire _T_896 = io_mhpme_vec_3 == 10'h3; // @[dec_tlu_ctl.scala 2800:42] + wire _T_898 = io_mhpme_vec_3 == 10'h4; // @[dec_tlu_ctl.scala 2801:42] + wire _T_902 = io_mhpme_vec_3 == 10'h5; // @[dec_tlu_ctl.scala 2802:42] + wire _T_908 = io_mhpme_vec_3 == 10'h6; // @[dec_tlu_ctl.scala 2803:42] + wire _T_913 = io_mhpme_vec_3 == 10'h7; // @[dec_tlu_ctl.scala 2805:42] + wire _T_915 = io_mhpme_vec_3 == 10'h8; // @[dec_tlu_ctl.scala 2806:42] + wire _T_917 = io_mhpme_vec_3 == 10'h1e; // @[dec_tlu_ctl.scala 2807:42] + wire _T_919 = io_mhpme_vec_3 == 10'h9; // @[dec_tlu_ctl.scala 2808:42] + wire _T_922 = io_mhpme_vec_3 == 10'ha; // @[dec_tlu_ctl.scala 2809:42] + wire _T_927 = io_mhpme_vec_3 == 10'hb; // @[dec_tlu_ctl.scala 2810:42] + wire _T_930 = io_mhpme_vec_3 == 10'hc; // @[dec_tlu_ctl.scala 2811:42] + wire _T_933 = io_mhpme_vec_3 == 10'hd; // @[dec_tlu_ctl.scala 2812:42] + wire _T_937 = io_mhpme_vec_3 == 10'he; // @[dec_tlu_ctl.scala 2813:42] + wire _T_942 = io_mhpme_vec_3 == 10'hf; // @[dec_tlu_ctl.scala 2815:42] + wire _T_945 = io_mhpme_vec_3 == 10'h10; // @[dec_tlu_ctl.scala 2816:42] + wire _T_948 = io_mhpme_vec_3 == 10'h12; // @[dec_tlu_ctl.scala 2817:42] + wire _T_951 = io_mhpme_vec_3 == 10'h11; // @[dec_tlu_ctl.scala 2818:42] + wire _T_954 = io_mhpme_vec_3 == 10'h13; // @[dec_tlu_ctl.scala 2819:42] + wire _T_957 = io_mhpme_vec_3 == 10'h14; // @[dec_tlu_ctl.scala 2820:42] + wire _T_960 = io_mhpme_vec_3 == 10'h15; // @[dec_tlu_ctl.scala 2821:42] + wire _T_963 = io_mhpme_vec_3 == 10'h16; // @[dec_tlu_ctl.scala 2822:42] + wire _T_966 = io_mhpme_vec_3 == 10'h17; // @[dec_tlu_ctl.scala 2823:42] + wire _T_969 = io_mhpme_vec_3 == 10'h18; // @[dec_tlu_ctl.scala 2824:42] + wire _T_974 = io_mhpme_vec_3 == 10'h19; // @[dec_tlu_ctl.scala 2826:42] + wire _T_979 = io_mhpme_vec_3 == 10'h1a; // @[dec_tlu_ctl.scala 2827:42] + wire _T_984 = io_mhpme_vec_3 == 10'h1b; // @[dec_tlu_ctl.scala 2828:42] + wire _T_989 = io_mhpme_vec_3 == 10'h1c; // @[dec_tlu_ctl.scala 2829:42] + wire _T_993 = io_mhpme_vec_3 == 10'h1f; // @[dec_tlu_ctl.scala 2831:42] + wire _T_995 = io_mhpme_vec_3 == 10'h20; // @[dec_tlu_ctl.scala 2832:42] + wire _T_997 = io_mhpme_vec_3 == 10'h22; // @[dec_tlu_ctl.scala 2833:42] + wire _T_999 = io_mhpme_vec_3 == 10'h23; // @[dec_tlu_ctl.scala 2834:42] + wire _T_1001 = io_mhpme_vec_3 == 10'h24; // @[dec_tlu_ctl.scala 2835:42] + wire _T_1003 = io_mhpme_vec_3 == 10'h25; // @[dec_tlu_ctl.scala 2836:42] + wire _T_1007 = io_mhpme_vec_3 == 10'h26; // @[dec_tlu_ctl.scala 2837:42] + wire _T_1011 = io_mhpme_vec_3 == 10'h27; // @[dec_tlu_ctl.scala 2838:42] + wire _T_1013 = io_mhpme_vec_3 == 10'h28; // @[dec_tlu_ctl.scala 2839:42] + wire _T_1015 = io_mhpme_vec_3 == 10'h29; // @[dec_tlu_ctl.scala 2840:42] + wire _T_1019 = io_mhpme_vec_3 == 10'h2a; // @[dec_tlu_ctl.scala 2842:42] + wire _T_1021 = io_mhpme_vec_3 == 10'h2b; // @[dec_tlu_ctl.scala 2843:42] + wire _T_1023 = io_mhpme_vec_3 == 10'h2c; // @[dec_tlu_ctl.scala 2844:42] + wire _T_1025 = io_mhpme_vec_3 == 10'h2d; // @[dec_tlu_ctl.scala 2845:42] + wire _T_1027 = io_mhpme_vec_3 == 10'h2e; // @[dec_tlu_ctl.scala 2846:42] + wire _T_1029 = io_mhpme_vec_3 == 10'h2f; // @[dec_tlu_ctl.scala 2847:42] + wire _T_1031 = io_mhpme_vec_3 == 10'h30; // @[dec_tlu_ctl.scala 2848:42] + wire _T_1033 = io_mhpme_vec_3 == 10'h31; // @[dec_tlu_ctl.scala 2849:42] + wire _T_1038 = io_mhpme_vec_3 == 10'h32; // @[dec_tlu_ctl.scala 2850:42] + wire _T_1048 = io_mhpme_vec_3 == 10'h36; // @[dec_tlu_ctl.scala 2851:42] + wire _T_1051 = io_mhpme_vec_3 == 10'h37; // @[dec_tlu_ctl.scala 2852:42] + wire _T_1056 = io_mhpme_vec_3 == 10'h38; // @[dec_tlu_ctl.scala 2853:42] + wire _T_1061 = io_mhpme_vec_3 == 10'h200; // @[dec_tlu_ctl.scala 2855:42] + wire _T_1063 = io_mhpme_vec_3 == 10'h201; // @[dec_tlu_ctl.scala 2856:42] + wire _T_1065 = io_mhpme_vec_3 == 10'h202; // @[dec_tlu_ctl.scala 2857:42] + wire _T_1067 = io_mhpme_vec_3 == 10'h203; // @[dec_tlu_ctl.scala 2858:42] + wire _T_1069 = io_mhpme_vec_3 == 10'h204; // @[dec_tlu_ctl.scala 2859:42] + wire _T_1072 = _T_894 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1073 = _T_896 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1074 = _T_898 & _T_13; // @[Mux.scala 27:72] + wire _T_1075 = _T_902 & _T_19; // @[Mux.scala 27:72] + wire _T_1076 = _T_908 & _T_24; // @[Mux.scala 27:72] + wire _T_1077 = _T_913 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1078 = _T_915 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1079 = _T_917 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1080 = _T_919 & _T_33; // @[Mux.scala 27:72] + wire _T_1081 = _T_922 & _T_38; // @[Mux.scala 27:72] + wire _T_1082 = _T_927 & _T_41; // @[Mux.scala 27:72] + wire _T_1083 = _T_930 & _T_44; // @[Mux.scala 27:72] + wire _T_1084 = _T_933 & _T_48; // @[Mux.scala 27:72] + wire _T_1085 = _T_937 & _T_53; // @[Mux.scala 27:72] + wire _T_1086 = _T_942 & _T_56; // @[Mux.scala 27:72] + wire _T_1087 = _T_945 & _T_59; // @[Mux.scala 27:72] + wire _T_1088 = _T_948 & _T_62; // @[Mux.scala 27:72] + wire _T_1089 = _T_951 & _T_65; // @[Mux.scala 27:72] + wire _T_1090 = _T_954 & _T_68; // @[Mux.scala 27:72] + wire _T_1091 = _T_957 & _T_71; // @[Mux.scala 27:72] + wire _T_1092 = _T_960 & _T_74; // @[Mux.scala 27:72] + wire _T_1093 = _T_963 & _T_77; // @[Mux.scala 27:72] + wire _T_1094 = _T_966 & _T_80; // @[Mux.scala 27:72] + wire _T_1095 = _T_969 & _T_85; // @[Mux.scala 27:72] + wire _T_1096 = _T_974 & _T_90; // @[Mux.scala 27:72] + wire _T_1097 = _T_979 & _T_95; // @[Mux.scala 27:72] + wire _T_1098 = _T_984 & _T_100; // @[Mux.scala 27:72] + wire _T_1099 = _T_989 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1101 = _T_993 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1102 = _T_995 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1103 = _T_997 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1104 = _T_999 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1105 = _T_1001 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1106 = _T_1003 & _T_118; // @[Mux.scala 27:72] + wire _T_1107 = _T_1007 & _T_122; // @[Mux.scala 27:72] + wire _T_1108 = _T_1011 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1109 = _T_1013 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1110 = _T_1015 & _T_130; // @[Mux.scala 27:72] + wire _T_1111 = _T_1019 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1112 = _T_1021 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1113 = _T_1023 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1114 = _T_1025 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1115 = _T_1027 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1116 = _T_1029 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1117 = _T_1031 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1118 = _T_1033 & _T_149; // @[Mux.scala 27:72] + wire _T_1119 = _T_1038 & _T_159; // @[Mux.scala 27:72] + wire _T_1120 = _T_1048 & _T_162; // @[Mux.scala 27:72] + wire _T_1121 = _T_1051 & _T_167; // @[Mux.scala 27:72] + wire _T_1122 = _T_1056 & _T_172; // @[Mux.scala 27:72] + wire _T_1123 = _T_1061 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1124 = _T_1063 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1125 = _T_1065 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1126 = _T_1067 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1127 = _T_1069 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1128 = _T_892 | _T_1072; // @[Mux.scala 27:72] + wire _T_1129 = _T_1128 | _T_1073; // @[Mux.scala 27:72] + wire _T_1130 = _T_1129 | _T_1074; // @[Mux.scala 27:72] + wire _T_1131 = _T_1130 | _T_1075; // @[Mux.scala 27:72] + wire _T_1132 = _T_1131 | _T_1076; // @[Mux.scala 27:72] + wire _T_1133 = _T_1132 | _T_1077; // @[Mux.scala 27:72] + wire _T_1134 = _T_1133 | _T_1078; // @[Mux.scala 27:72] + wire _T_1135 = _T_1134 | _T_1079; // @[Mux.scala 27:72] + wire _T_1136 = _T_1135 | _T_1080; // @[Mux.scala 27:72] + wire _T_1137 = _T_1136 | _T_1081; // @[Mux.scala 27:72] + wire _T_1138 = _T_1137 | _T_1082; // @[Mux.scala 27:72] + wire _T_1139 = _T_1138 | _T_1083; // @[Mux.scala 27:72] + wire _T_1140 = _T_1139 | _T_1084; // @[Mux.scala 27:72] + wire _T_1141 = _T_1140 | _T_1085; // @[Mux.scala 27:72] + wire _T_1142 = _T_1141 | _T_1086; // @[Mux.scala 27:72] + wire _T_1143 = _T_1142 | _T_1087; // @[Mux.scala 27:72] + wire _T_1144 = _T_1143 | _T_1088; // @[Mux.scala 27:72] + wire _T_1145 = _T_1144 | _T_1089; // @[Mux.scala 27:72] + wire _T_1146 = _T_1145 | _T_1090; // @[Mux.scala 27:72] + wire _T_1147 = _T_1146 | _T_1091; // @[Mux.scala 27:72] + wire _T_1148 = _T_1147 | _T_1092; // @[Mux.scala 27:72] + wire _T_1149 = _T_1148 | _T_1093; // @[Mux.scala 27:72] + wire _T_1150 = _T_1149 | _T_1094; // @[Mux.scala 27:72] + wire _T_1151 = _T_1150 | _T_1095; // @[Mux.scala 27:72] + wire _T_1152 = _T_1151 | _T_1096; // @[Mux.scala 27:72] + wire _T_1153 = _T_1152 | _T_1097; // @[Mux.scala 27:72] + wire _T_1154 = _T_1153 | _T_1098; // @[Mux.scala 27:72] + wire _T_1155 = _T_1154 | _T_1099; // @[Mux.scala 27:72] + wire _T_1156 = _T_1155 | _T_1079; // @[Mux.scala 27:72] + wire _T_1157 = _T_1156 | _T_1101; // @[Mux.scala 27:72] + wire _T_1158 = _T_1157 | _T_1102; // @[Mux.scala 27:72] + wire _T_1159 = _T_1158 | _T_1103; // @[Mux.scala 27:72] + wire _T_1160 = _T_1159 | _T_1104; // @[Mux.scala 27:72] + wire _T_1161 = _T_1160 | _T_1105; // @[Mux.scala 27:72] + wire _T_1162 = _T_1161 | _T_1106; // @[Mux.scala 27:72] + wire _T_1163 = _T_1162 | _T_1107; // @[Mux.scala 27:72] + wire _T_1164 = _T_1163 | _T_1108; // @[Mux.scala 27:72] + wire _T_1165 = _T_1164 | _T_1109; // @[Mux.scala 27:72] + wire _T_1166 = _T_1165 | _T_1110; // @[Mux.scala 27:72] + wire _T_1167 = _T_1166 | _T_1111; // @[Mux.scala 27:72] + wire _T_1168 = _T_1167 | _T_1112; // @[Mux.scala 27:72] + wire _T_1169 = _T_1168 | _T_1113; // @[Mux.scala 27:72] + wire _T_1170 = _T_1169 | _T_1114; // @[Mux.scala 27:72] + wire _T_1171 = _T_1170 | _T_1115; // @[Mux.scala 27:72] + wire _T_1172 = _T_1171 | _T_1116; // @[Mux.scala 27:72] + wire _T_1173 = _T_1172 | _T_1117; // @[Mux.scala 27:72] + wire _T_1174 = _T_1173 | _T_1118; // @[Mux.scala 27:72] + wire _T_1175 = _T_1174 | _T_1119; // @[Mux.scala 27:72] + wire _T_1176 = _T_1175 | _T_1120; // @[Mux.scala 27:72] + wire _T_1177 = _T_1176 | _T_1121; // @[Mux.scala 27:72] + wire _T_1178 = _T_1177 | _T_1122; // @[Mux.scala 27:72] + wire _T_1179 = _T_1178 | _T_1123; // @[Mux.scala 27:72] + wire _T_1180 = _T_1179 | _T_1124; // @[Mux.scala 27:72] + wire _T_1181 = _T_1180 | _T_1125; // @[Mux.scala 27:72] + wire _T_1182 = _T_1181 | _T_1126; // @[Mux.scala 27:72] + wire _T_1183 = _T_1182 | _T_1127; // @[Mux.scala 27:72] + reg _T_1189; // @[Reg.scala 27:20] + wire _T_1187 = io_mdseac_locked_ns ^ _T_1189; // @[lib.scala 470:21] + wire _T_1188 = |_T_1187; // @[lib.scala 470:29] + reg _T_1193; // @[Reg.scala 27:20] + wire _T_1191 = io_lsu_single_ecc_error_r ^ _T_1193; // @[lib.scala 470:21] + wire _T_1192 = |_T_1191; // @[lib.scala 470:29] + reg _T_1201; // @[Reg.scala 27:20] + wire _T_1199 = io_lsu_i0_exc_r ^ _T_1201; // @[lib.scala 470:21] + wire _T_1200 = |_T_1199; // @[lib.scala 470:29] + reg _T_1205; // @[Reg.scala 27:20] + wire _T_1203 = io_take_ext_int_start ^ _T_1205; // @[lib.scala 470:21] + wire _T_1204 = |_T_1203; // @[lib.scala 470:29] + reg _T_1209; // @[Reg.scala 27:20] + wire _T_1207 = io_take_ext_int_start_d1 ^ _T_1209; // @[lib.scala 470:21] + wire _T_1208 = |_T_1207; // @[lib.scala 470:29] + reg _T_1213; // @[Reg.scala 27:20] + wire _T_1211 = io_take_ext_int_start_d2 ^ _T_1213; // @[lib.scala 470:21] + wire _T_1212 = |_T_1211; // @[lib.scala 470:29] + reg _T_1217; // @[Reg.scala 27:20] + wire _T_1215 = io_ext_int_freeze ^ _T_1217; // @[lib.scala 470:21] + wire _T_1216 = |_T_1215; // @[lib.scala 470:29] + reg [5:0] _T_1221; // @[Reg.scala 27:20] + wire [5:0] _T_1219 = io_mip_ns ^ _T_1221; // @[lib.scala 448:21] + wire _T_1220 = |_T_1219; // @[lib.scala 448:29] + wire _T_1222 = ~io_wr_mcycleh_r; // @[dec_tlu_ctl.scala 2879:80] + wire _T_1223 = io_mcyclel_cout & _T_1222; // @[dec_tlu_ctl.scala 2879:78] + wire _T_1224 = _T_1223 & io_mcyclel_cout_in; // @[dec_tlu_ctl.scala 2879:97] + reg _T_1228; // @[Reg.scala 27:20] + wire _T_1226 = _T_1224 ^ _T_1228; // @[lib.scala 470:21] + wire _T_1227 = |_T_1226; // @[lib.scala 470:29] + reg _T_1232; // @[Reg.scala 27:20] + wire _T_1230 = io_minstret_enable ^ _T_1232; // @[lib.scala 470:21] + wire _T_1231 = |_T_1230; // @[lib.scala 470:29] + reg _T_1236; // @[Reg.scala 27:20] + wire _T_1234 = io_minstretl_cout_ns ^ _T_1236; // @[lib.scala 470:21] + wire _T_1235 = |_T_1234; // @[lib.scala 470:29] + reg [3:0] _T_1244; // @[Reg.scala 27:20] + wire [3:0] _T_1242 = io_meicidpl_ns ^ _T_1244; // @[lib.scala 448:21] + wire _T_1243 = |_T_1242; // @[lib.scala 448:29] + reg _T_1248; // @[Reg.scala 27:20] + wire _T_1246 = io_icache_rd_valid ^ _T_1248; // @[lib.scala 470:21] + wire _T_1247 = |_T_1246; // @[lib.scala 470:29] + reg _T_1252; // @[Reg.scala 27:20] + wire _T_1250 = io_icache_wr_valid ^ _T_1252; // @[lib.scala 470:21] + wire _T_1251 = |_T_1250; // @[lib.scala 470:29] + reg _T_1266_0; // @[Reg.scala 27:20] + wire _T_1254 = io_mhpmc_inc_r_0 ^ _T_1266_0; // @[lib.scala 518:68] + wire _T_1255 = |_T_1254; // @[lib.scala 518:82] + reg _T_1266_1; // @[Reg.scala 27:20] + wire _T_1256 = io_mhpmc_inc_r_1 ^ _T_1266_1; // @[lib.scala 518:68] + wire _T_1257 = |_T_1256; // @[lib.scala 518:82] + reg _T_1266_2; // @[Reg.scala 27:20] + wire _T_1258 = io_mhpmc_inc_r_2 ^ _T_1266_2; // @[lib.scala 518:68] + wire _T_1259 = |_T_1258; // @[lib.scala 518:82] + reg _T_1266_3; // @[Reg.scala 27:20] + wire _T_1260 = io_mhpmc_inc_r_3 ^ _T_1266_3; // @[lib.scala 518:68] + wire _T_1261 = |_T_1260; // @[lib.scala 518:82] + wire _T_1262 = _T_1255 | _T_1257; // @[lib.scala 518:97] + wire _T_1263 = _T_1262 | _T_1259; // @[lib.scala 518:97] + wire _T_1264 = _T_1263 | _T_1261; // @[lib.scala 518:97] + reg _T_1270; // @[Reg.scala 27:20] + wire _T_1268 = io_perfcnt_halted ^ _T_1270; // @[lib.scala 470:21] + wire _T_1269 = |_T_1268; // @[lib.scala 470:29] + reg [1:0] _T_1274; // @[Reg.scala 27:20] + wire [1:0] _T_1272 = io_mstatus_ns ^ _T_1274; // @[lib.scala 448:21] + wire _T_1273 = |_T_1272; // @[lib.scala 448:29] + assign io_mhpmc_inc_r_0 = _T_3 & _T_295; // @[dec_tlu_ctl.scala 2797:35] + assign io_mhpmc_inc_r_1 = _T_299 & _T_591; // @[dec_tlu_ctl.scala 2797:35] + assign io_mhpmc_inc_r_2 = _T_595 & _T_887; // @[dec_tlu_ctl.scala 2797:35] + assign io_mhpmc_inc_r_3 = _T_891 & _T_1183; // @[dec_tlu_ctl.scala 2797:35] + assign io_mstatus = _T_1274; // @[dec_tlu_ctl.scala 2888:52] + assign io_mcyclel_cout_f = _T_1228; // @[dec_tlu_ctl.scala 2879:52] + assign io_minstret_enable_f = _T_1232; // @[dec_tlu_ctl.scala 2880:52] + assign io_minstretl_cout_f = _T_1236; // @[dec_tlu_ctl.scala 2881:52] + assign io_meicidpl = _T_1244; // @[dec_tlu_ctl.scala 2883:52] + assign io_icache_rd_valid_f = _T_1248; // @[dec_tlu_ctl.scala 2884:52] + assign io_icache_wr_valid_f = _T_1252; // @[dec_tlu_ctl.scala 2885:52] + assign io_mhpmc_inc_r_d1_0 = _T_1266_0; // @[dec_tlu_ctl.scala 2886:52] + assign io_mhpmc_inc_r_d1_1 = _T_1266_1; // @[dec_tlu_ctl.scala 2886:52] + assign io_mhpmc_inc_r_d1_2 = _T_1266_2; // @[dec_tlu_ctl.scala 2886:52] + assign io_mhpmc_inc_r_d1_3 = _T_1266_3; // @[dec_tlu_ctl.scala 2886:52] + assign io_perfcnt_halted_d1 = _T_1270; // @[dec_tlu_ctl.scala 2887:52] + assign io_mdseac_locked_f = _T_1189; // @[dec_tlu_ctl.scala 2870:52] + assign io_lsu_single_ecc_error_r_d1 = _T_1193; // @[dec_tlu_ctl.scala 2871:52] + assign io_lsu_i0_exc_r_d1 = _T_1201; // @[dec_tlu_ctl.scala 2873:52] + assign io_take_ext_int_start_d1 = _T_1205; // @[dec_tlu_ctl.scala 2874:52] + assign io_take_ext_int_start_d2 = _T_1209; // @[dec_tlu_ctl.scala 2875:52] + assign io_take_ext_int_start_d3 = _T_1213; // @[dec_tlu_ctl.scala 2876:52] + assign io_ext_int_freeze_d1 = _T_1217; // @[dec_tlu_ctl.scala 2877:52] + assign io_mip = _T_1221; // @[dec_tlu_ctl.scala 2878:52] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T_1189 = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + _T_1193 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_1201 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + _T_1205 = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + _T_1209 = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + _T_1213 = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + _T_1217 = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + _T_1221 = _RAND_7[5:0]; + _RAND_8 = {1{`RANDOM}}; + _T_1228 = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + _T_1232 = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + _T_1236 = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + _T_1244 = _RAND_11[3:0]; + _RAND_12 = {1{`RANDOM}}; + _T_1248 = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + _T_1252 = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + _T_1266_0 = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + _T_1266_1 = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + _T_1266_2 = _RAND_16[0:0]; + _RAND_17 = {1{`RANDOM}}; + _T_1266_3 = _RAND_17[0:0]; + _RAND_18 = {1{`RANDOM}}; + _T_1270 = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + _T_1274 = _RAND_19[1:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_1189 = 1'h0; + end + if (reset) begin + _T_1193 = 1'h0; + end + if (reset) begin + _T_1201 = 1'h0; + end + if (reset) begin + _T_1205 = 1'h0; + end + if (reset) begin + _T_1209 = 1'h0; + end + if (reset) begin + _T_1213 = 1'h0; + end + if (reset) begin + _T_1217 = 1'h0; + end + if (reset) begin + _T_1221 = 6'h0; + end + if (reset) begin + _T_1228 = 1'h0; + end + if (reset) begin + _T_1232 = 1'h0; + end + if (reset) begin + _T_1236 = 1'h0; + end + if (reset) begin + _T_1244 = 4'h0; + end + if (reset) begin + _T_1248 = 1'h0; + end + if (reset) begin + _T_1252 = 1'h0; + end + if (reset) begin + _T_1266_0 = 1'h0; + end + if (reset) begin + _T_1266_1 = 1'h0; + end + if (reset) begin + _T_1266_2 = 1'h0; + end + if (reset) begin + _T_1266_3 = 1'h0; + end + if (reset) begin + _T_1270 = 1'h0; + end + if (reset) begin + _T_1274 = 2'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1189 <= 1'h0; + end else if (_T_1188) begin + _T_1189 <= io_mdseac_locked_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1193 <= 1'h0; + end else if (_T_1192) begin + _T_1193 <= io_lsu_single_ecc_error_r; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1201 <= 1'h0; + end else if (_T_1200) begin + _T_1201 <= io_lsu_i0_exc_r; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1205 <= 1'h0; + end else if (_T_1204) begin + _T_1205 <= io_take_ext_int_start; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1209 <= 1'h0; + end else if (_T_1208) begin + _T_1209 <= io_take_ext_int_start_d1; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1213 <= 1'h0; + end else if (_T_1212) begin + _T_1213 <= io_take_ext_int_start_d2; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1217 <= 1'h0; + end else if (_T_1216) begin + _T_1217 <= io_ext_int_freeze; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1221 <= 6'h0; + end else if (_T_1220) begin + _T_1221 <= io_mip_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1228 <= 1'h0; + end else if (_T_1227) begin + _T_1228 <= _T_1224; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1232 <= 1'h0; + end else if (_T_1231) begin + _T_1232 <= io_minstret_enable; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1236 <= 1'h0; + end else if (_T_1235) begin + _T_1236 <= io_minstretl_cout_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1244 <= 4'h0; + end else if (_T_1243) begin + _T_1244 <= io_meicidpl_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1248 <= 1'h0; + end else if (_T_1247) begin + _T_1248 <= io_icache_rd_valid; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1252 <= 1'h0; + end else if (_T_1251) begin + _T_1252 <= io_icache_wr_valid; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1266_0 <= 1'h0; + end else if (_T_1264) begin + _T_1266_0 <= io_mhpmc_inc_r_0; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1266_1 <= 1'h0; + end else if (_T_1264) begin + _T_1266_1 <= io_mhpmc_inc_r_1; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1266_2 <= 1'h0; + end else if (_T_1264) begin + _T_1266_2 <= io_mhpmc_inc_r_2; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1266_3 <= 1'h0; + end else if (_T_1264) begin + _T_1266_3 <= io_mhpmc_inc_r_3; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1270 <= 1'h0; + end else if (_T_1269) begin + _T_1270 <= io_perfcnt_halted; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1274 <= 2'h0; + end else if (_T_1273) begin + _T_1274 <= io_mstatus_ns; + end + end +endmodule +module perf_csr( + input clock, + input reset, + input io_free_l2clk, + input io_dec_tlu_dbg_halted, + input [15:0] io_dcsr, + input io_dec_tlu_pmu_fw_halted, + input [9:0] io_mhpme_vec_0, + input [9:0] io_mhpme_vec_1, + input [9:0] io_mhpme_vec_2, + input [9:0] io_mhpme_vec_3, + input io_dec_csr_wen_r_mod, + input [11:0] io_dec_csr_wraddr_r, + input [31:0] io_dec_csr_wrdata_r, + input io_mhpmc_inc_r_0, + input io_mhpmc_inc_r_1, + input io_mhpmc_inc_r_2, + input io_mhpmc_inc_r_3, + input io_mhpmc_inc_r_d1_0, + input io_mhpmc_inc_r_d1_1, + input io_mhpmc_inc_r_d1_2, + input io_mhpmc_inc_r_d1_3, + input io_perfcnt_halted_d1, + output [31:0] io_mhpmc3h, + output [31:0] io_mhpmc3, + output [31:0] io_mhpmc4h, + output [31:0] io_mhpmc4, + output [31:0] io_mhpmc5h, + output [31:0] io_mhpmc5, + output [31:0] io_mhpmc6h, + output [31:0] io_mhpmc6, + output [9:0] io_mhpme3, + output [9:0] io_mhpme4, + output [9:0] io_mhpme5, + output [9:0] io_mhpme6, + output io_dec_tlu_perfcnt0, + output io_dec_tlu_perfcnt1, + output io_dec_tlu_perfcnt2, + output io_dec_tlu_perfcnt3 +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_4_io_en; // @[lib.scala 404:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_5_io_en; // @[lib.scala 404:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_6_io_en; // @[lib.scala 404:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_7_io_en; // @[lib.scala 404:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_8_io_en; // @[lib.scala 404:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_9_io_en; // @[lib.scala 404:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_10_io_en; // @[lib.scala 404:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_11_io_en; // @[lib.scala 404:23] + wire _T_1 = io_dec_tlu_dbg_halted & io_dcsr[10]; // @[dec_tlu_ctl.scala 2578:54] + wire perfcnt_halted = _T_1 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2578:77] + wire _T_4 = ~_T_1; // @[dec_tlu_ctl.scala 2579:44] + wire [3:0] _T_6 = _T_4 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_13 = {io_mhpme_vec_3[9],io_mhpme_vec_2[9],io_mhpme_vec_1[9],io_mhpme_vec_0[9]}; // @[Cat.scala 29:58] + wire [3:0] perfcnt_during_sleep = _T_6 & _T_13; // @[dec_tlu_ctl.scala 2579:93] + wire _T_15 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2582:80] + wire _T_16 = io_perfcnt_halted_d1 & _T_15; // @[dec_tlu_ctl.scala 2582:78] + wire _T_17 = ~_T_16; // @[dec_tlu_ctl.scala 2582:55] + wire _T_20 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2583:80] + wire _T_21 = io_perfcnt_halted_d1 & _T_20; // @[dec_tlu_ctl.scala 2583:78] + wire _T_22 = ~_T_21; // @[dec_tlu_ctl.scala 2583:55] + wire _T_25 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2584:80] + wire _T_26 = io_perfcnt_halted_d1 & _T_25; // @[dec_tlu_ctl.scala 2584:78] + wire _T_27 = ~_T_26; // @[dec_tlu_ctl.scala 2584:55] + wire _T_30 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2585:80] + wire _T_31 = io_perfcnt_halted_d1 & _T_30; // @[dec_tlu_ctl.scala 2585:78] + wire _T_32 = ~_T_31; // @[dec_tlu_ctl.scala 2585:55] + wire _T_35 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2591:79] + wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_35; // @[dec_tlu_ctl.scala 2591:50] + wire _T_36 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2592:30] + wire _T_38 = _T_36 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2592:46] + wire _T_39 = |io_mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2592:96] + wire mhpmc3_wr_en1 = _T_38 & _T_39; // @[dec_tlu_ctl.scala 2592:73] + wire mhpmc3_wr_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[dec_tlu_ctl.scala 2593:43] + wire [63:0] _T_42 = {io_mhpmc3h,io_mhpmc3}; // @[Cat.scala 29:58] + wire [63:0] mhpmc3_incr = _T_42 + 64'h1; // @[dec_tlu_ctl.scala 2596:65] + reg [31:0] _T_48; // @[Reg.scala 27:20] + wire _T_50 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2601:80] + wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_50; // @[dec_tlu_ctl.scala 2601:51] + wire mhpmc3h_wr_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1; // @[dec_tlu_ctl.scala 2602:45] + reg [31:0] _T_54; // @[Reg.scala 27:20] + wire _T_56 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2612:79] + wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_56; // @[dec_tlu_ctl.scala 2612:50] + wire _T_59 = _T_36 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2613:46] + wire _T_60 = |io_mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2613:96] + wire mhpmc4_wr_en1 = _T_59 & _T_60; // @[dec_tlu_ctl.scala 2613:73] + wire mhpmc4_wr_en = mhpmc4_wr_en0 | mhpmc4_wr_en1; // @[dec_tlu_ctl.scala 2614:43] + wire [63:0] _T_63 = {io_mhpmc4h,io_mhpmc4}; // @[Cat.scala 29:58] + wire [63:0] mhpmc4_incr = _T_63 + 64'h1; // @[dec_tlu_ctl.scala 2618:65] + reg [31:0] _T_70; // @[Reg.scala 27:20] + wire _T_72 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2622:80] + wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_72; // @[dec_tlu_ctl.scala 2622:51] + wire mhpmc4h_wr_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1; // @[dec_tlu_ctl.scala 2623:45] + reg [31:0] _T_76; // @[Reg.scala 27:20] + wire _T_78 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2631:79] + wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_78; // @[dec_tlu_ctl.scala 2631:50] + wire _T_81 = _T_36 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2632:46] + wire _T_82 = |io_mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2632:96] + wire mhpmc5_wr_en1 = _T_81 & _T_82; // @[dec_tlu_ctl.scala 2632:73] + wire mhpmc5_wr_en = mhpmc5_wr_en0 | mhpmc5_wr_en1; // @[dec_tlu_ctl.scala 2633:43] + wire [63:0] _T_85 = {io_mhpmc5h,io_mhpmc5}; // @[Cat.scala 29:58] + wire [63:0] mhpmc5_incr = _T_85 + 64'h1; // @[dec_tlu_ctl.scala 2635:65] + reg [31:0] _T_91; // @[Reg.scala 27:20] + wire _T_93 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2640:80] + wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_93; // @[dec_tlu_ctl.scala 2640:51] + wire mhpmc5h_wr_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1; // @[dec_tlu_ctl.scala 2641:45] + reg [31:0] _T_97; // @[Reg.scala 27:20] + wire _T_99 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2651:79] + wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_99; // @[dec_tlu_ctl.scala 2651:50] + wire _T_102 = _T_36 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2652:46] + wire _T_103 = |io_mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2652:96] + wire mhpmc6_wr_en1 = _T_102 & _T_103; // @[dec_tlu_ctl.scala 2652:73] + wire mhpmc6_wr_en = mhpmc6_wr_en0 | mhpmc6_wr_en1; // @[dec_tlu_ctl.scala 2653:43] + wire [63:0] _T_106 = {io_mhpmc6h,io_mhpmc6}; // @[Cat.scala 29:58] + wire [63:0] mhpmc6_incr = _T_106 + 64'h1; // @[dec_tlu_ctl.scala 2655:65] + reg [31:0] _T_112; // @[Reg.scala 27:20] + wire _T_114 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2661:80] + wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_114; // @[dec_tlu_ctl.scala 2661:51] + wire mhpmc6h_wr_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[dec_tlu_ctl.scala 2662:45] + reg [31:0] _T_118; // @[Reg.scala 27:20] + wire _T_120 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2671:56] + wire _T_122 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2671:102] + wire _T_123 = _T_120 | _T_122; // @[dec_tlu_ctl.scala 2671:72] + wire _T_125 = io_dec_csr_wrdata_r[9:0] < 10'h200; // @[dec_tlu_ctl.scala 2672:44] + wire _T_127 = io_dec_csr_wrdata_r[9:0] > 10'h38; // @[dec_tlu_ctl.scala 2672:88] + wire _T_128 = _T_125 & _T_127; // @[dec_tlu_ctl.scala 2672:60] + wire _T_129 = _T_123 | _T_128; // @[dec_tlu_ctl.scala 2671:107] + wire _T_131 = io_dec_csr_wrdata_r[9:0] < 10'h36; // @[dec_tlu_ctl.scala 2673:44] + wire _T_133 = io_dec_csr_wrdata_r[9:0] > 10'h32; // @[dec_tlu_ctl.scala 2673:88] + wire _T_134 = _T_131 & _T_133; // @[dec_tlu_ctl.scala 2673:60] + wire _T_135 = _T_129 | _T_134; // @[dec_tlu_ctl.scala 2672:103] + wire _T_137 = io_dec_csr_wrdata_r[9:0] == 10'h1d; // @[dec_tlu_ctl.scala 2674:43] + wire _T_138 = _T_135 | _T_137; // @[dec_tlu_ctl.scala 2673:103] + wire _T_140 = io_dec_csr_wrdata_r[9:0] == 10'h21; // @[dec_tlu_ctl.scala 2674:87] + wire zero_event_r = _T_138 | _T_140; // @[dec_tlu_ctl.scala 2674:59] + wire _T_143 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2677:77] + wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_143; // @[dec_tlu_ctl.scala 2677:48] + reg [9:0] _T_145; // @[Reg.scala 27:20] + wire _T_147 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2684:77] + wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_147; // @[dec_tlu_ctl.scala 2684:48] + reg [9:0] _T_149; // @[Reg.scala 27:20] + wire _T_151 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2691:77] + wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_151; // @[dec_tlu_ctl.scala 2691:48] + reg [9:0] _T_153; // @[Reg.scala 27:20] + wire _T_155 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2698:77] + wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_155; // @[dec_tlu_ctl.scala 2698:48] + reg [9:0] _T_157; // @[Reg.scala 27:20] + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en) + ); + rvclkhdr rvclkhdr_10 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en) + ); + rvclkhdr rvclkhdr_11 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en) + ); + assign io_mhpmc3h = _T_54; // @[dec_tlu_ctl.scala 2605:20] + assign io_mhpmc3 = _T_48; // @[dec_tlu_ctl.scala 2599:19] + assign io_mhpmc4h = _T_76; // @[dec_tlu_ctl.scala 2625:20] + assign io_mhpmc4 = _T_70; // @[dec_tlu_ctl.scala 2620:19] + assign io_mhpmc5h = _T_97; // @[dec_tlu_ctl.scala 2644:20] + assign io_mhpmc5 = _T_91; // @[dec_tlu_ctl.scala 2638:19] + assign io_mhpmc6h = _T_118; // @[dec_tlu_ctl.scala 2665:20] + assign io_mhpmc6 = _T_112; // @[dec_tlu_ctl.scala 2659:19] + assign io_mhpme3 = _T_145; // @[dec_tlu_ctl.scala 2679:19] + assign io_mhpme4 = _T_149; // @[dec_tlu_ctl.scala 2685:19] + assign io_mhpme5 = _T_153; // @[dec_tlu_ctl.scala 2692:19] + assign io_mhpme6 = _T_157; // @[dec_tlu_ctl.scala 2699:19] + assign io_dec_tlu_perfcnt0 = io_mhpmc_inc_r_d1_0 & _T_17; // @[dec_tlu_ctl.scala 2582:29] + assign io_dec_tlu_perfcnt1 = io_mhpmc_inc_r_d1_1 & _T_22; // @[dec_tlu_ctl.scala 2583:29] + assign io_dec_tlu_perfcnt2 = io_mhpmc_inc_r_d1_2 & _T_27; // @[dec_tlu_ctl.scala 2584:29] + assign io_dec_tlu_perfcnt3 = io_mhpmc_inc_r_d1_3 & _T_32; // @[dec_tlu_ctl.scala 2585:29] + assign rvclkhdr_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = mhpmc4_wr_en0 | mhpmc4_wr_en1; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1; // @[lib.scala 407:17] + assign rvclkhdr_4_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_4_io_en = mhpmc5_wr_en0 | mhpmc5_wr_en1; // @[lib.scala 407:17] + assign rvclkhdr_5_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_5_io_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1; // @[lib.scala 407:17] + assign rvclkhdr_6_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_6_io_en = mhpmc6_wr_en0 | mhpmc6_wr_en1; // @[lib.scala 407:17] + assign rvclkhdr_7_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_7_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[lib.scala 407:17] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_8_io_en = io_dec_csr_wen_r_mod & _T_143; // @[lib.scala 407:17] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_9_io_en = io_dec_csr_wen_r_mod & _T_147; // @[lib.scala 407:17] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_151; // @[lib.scala 407:17] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_11_io_en = io_dec_csr_wen_r_mod & _T_155; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T_48 = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + _T_54 = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + _T_70 = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + _T_76 = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + _T_91 = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + _T_97 = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + _T_112 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + _T_118 = _RAND_7[31:0]; + _RAND_8 = {1{`RANDOM}}; + _T_145 = _RAND_8[9:0]; + _RAND_9 = {1{`RANDOM}}; + _T_149 = _RAND_9[9:0]; + _RAND_10 = {1{`RANDOM}}; + _T_153 = _RAND_10[9:0]; + _RAND_11 = {1{`RANDOM}}; + _T_157 = _RAND_11[9:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_48 = 32'h0; + end + if (reset) begin + _T_54 = 32'h0; + end + if (reset) begin + _T_70 = 32'h0; + end + if (reset) begin + _T_76 = 32'h0; + end + if (reset) begin + _T_91 = 32'h0; + end + if (reset) begin + _T_97 = 32'h0; + end + if (reset) begin + _T_112 = 32'h0; + end + if (reset) begin + _T_118 = 32'h0; + end + if (reset) begin + _T_145 = 10'h0; + end + if (reset) begin + _T_149 = 10'h0; + end + if (reset) begin + _T_153 = 10'h0; + end + if (reset) begin + _T_157 = 10'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_48 <= 32'h0; + end else if (mhpmc3_wr_en) begin + if (mhpmc3_wr_en0) begin + _T_48 <= io_dec_csr_wrdata_r; + end else begin + _T_48 <= mhpmc3_incr[31:0]; + end + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_54 <= 32'h0; + end else if (mhpmc3h_wr_en) begin + if (mhpmc3h_wr_en0) begin + _T_54 <= io_dec_csr_wrdata_r; + end else begin + _T_54 <= mhpmc3_incr[63:32]; + end + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_70 <= 32'h0; + end else if (mhpmc4_wr_en) begin + if (mhpmc4_wr_en0) begin + _T_70 <= io_dec_csr_wrdata_r; + end else begin + _T_70 <= mhpmc4_incr[31:0]; + end + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_76 <= 32'h0; + end else if (mhpmc4h_wr_en) begin + if (mhpmc4h_wr_en0) begin + _T_76 <= io_dec_csr_wrdata_r; + end else begin + _T_76 <= mhpmc4_incr[63:32]; + end + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_91 <= 32'h0; + end else if (mhpmc5_wr_en) begin + if (mhpmc5_wr_en0) begin + _T_91 <= io_dec_csr_wrdata_r; + end else begin + _T_91 <= mhpmc5_incr[31:0]; + end + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_97 <= 32'h0; + end else if (mhpmc5h_wr_en) begin + if (mhpmc5h_wr_en0) begin + _T_97 <= io_dec_csr_wrdata_r; + end else begin + _T_97 <= mhpmc5_incr[63:32]; + end + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_112 <= 32'h0; + end else if (mhpmc6_wr_en) begin + if (mhpmc6_wr_en0) begin + _T_112 <= io_dec_csr_wrdata_r; + end else begin + _T_112 <= mhpmc6_incr[31:0]; + end + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_118 <= 32'h0; + end else if (mhpmc6h_wr_en) begin + if (mhpmc6h_wr_en0) begin + _T_118 <= io_dec_csr_wrdata_r; + end else begin + _T_118 <= mhpmc6_incr[63:32]; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_145 <= 10'h0; + end else if (wr_mhpme3_r) begin + if (zero_event_r) begin + _T_145 <= 10'h0; + end else begin + _T_145 <= io_dec_csr_wrdata_r[9:0]; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_149 <= 10'h0; + end else if (wr_mhpme4_r) begin + if (zero_event_r) begin + _T_149 <= 10'h0; + end else begin + _T_149 <= io_dec_csr_wrdata_r[9:0]; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_153 <= 10'h0; + end else if (wr_mhpme5_r) begin + if (zero_event_r) begin + _T_153 <= 10'h0; + end else begin + _T_153 <= io_dec_csr_wrdata_r[9:0]; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_157 <= 10'h0; + end else if (wr_mhpme6_r) begin + if (zero_event_r) begin + _T_157 <= 10'h0; + end else begin + _T_157 <= io_dec_csr_wrdata_r[9:0]; + end + end + end +endmodule +module csr_tlu( + input clock, + input reset, + input io_free_l2clk, + input io_free_clk, + input [31:0] io_dec_csr_wrdata_r, + input [11:0] io_dec_csr_wraddr_r, + input [11:0] io_dec_csr_rdaddr_d, + input io_dec_csr_wen_unq_d, + input io_dec_i0_decode_d, + output [70:0] io_dec_tlu_ic_diag_pkt_icache_wrdata, + output [16:0] io_dec_tlu_ic_diag_pkt_icache_dicawics, + output io_dec_tlu_ic_diag_pkt_icache_rd_valid, + output io_dec_tlu_ic_diag_pkt_icache_wr_valid, + input io_ifu_ic_debug_rd_data_valid, + output io_trigger_pkt_any_0_select, + output io_trigger_pkt_any_0_match_pkt, + output io_trigger_pkt_any_0_store, + output io_trigger_pkt_any_0_load, + output io_trigger_pkt_any_0_execute, + output io_trigger_pkt_any_0_m, + output [31:0] io_trigger_pkt_any_0_tdata2, + output io_trigger_pkt_any_1_select, + output io_trigger_pkt_any_1_match_pkt, + output io_trigger_pkt_any_1_store, + output io_trigger_pkt_any_1_load, + output io_trigger_pkt_any_1_execute, + output io_trigger_pkt_any_1_m, + output [31:0] io_trigger_pkt_any_1_tdata2, + output io_trigger_pkt_any_2_select, + output io_trigger_pkt_any_2_match_pkt, + output io_trigger_pkt_any_2_store, + output io_trigger_pkt_any_2_load, + output io_trigger_pkt_any_2_execute, + output io_trigger_pkt_any_2_m, + output [31:0] io_trigger_pkt_any_2_tdata2, + output io_trigger_pkt_any_3_select, + output io_trigger_pkt_any_3_match_pkt, + output io_trigger_pkt_any_3_store, + output io_trigger_pkt_any_3_load, + output io_trigger_pkt_any_3_execute, + output io_trigger_pkt_any_3_m, + output [31:0] io_trigger_pkt_any_3_tdata2, + input io_ifu_pmu_bus_trxn, + input io_dma_iccm_stall_any, + input io_dma_dccm_stall_any, + input io_lsu_store_stall_any, + input io_dec_pmu_presync_stall, + input io_dec_pmu_postsync_stall, + input io_dec_pmu_decode_stall, + input io_ifu_pmu_fetch_stall, + input [1:0] io_dec_tlu_packet_r_icaf_type, + input [3:0] io_dec_tlu_packet_r_pmu_i0_itype, + input io_dec_tlu_packet_r_pmu_i0_br_unpred, + input io_dec_tlu_packet_r_pmu_divide, + input io_dec_tlu_packet_r_pmu_lsu_misaligned, + input io_exu_pmu_i0_br_ataken, + input io_exu_pmu_i0_br_misp, + input io_dec_pmu_instr_decoded, + input io_ifu_pmu_instr_aligned, + input io_exu_pmu_i0_pc4, + input io_ifu_pmu_ic_miss, + input io_ifu_pmu_ic_hit, + output io_dec_tlu_int_valid_wb1, + output io_dec_tlu_i0_exc_valid_wb1, + output io_dec_tlu_i0_valid_wb1, + input io_dec_csr_wen_r, + output [31:0] io_dec_tlu_mtval_wb1, + output [4:0] io_dec_tlu_exc_cause_wb1, + output io_dec_tlu_perfcnt0, + output io_dec_tlu_perfcnt1, + output io_dec_tlu_perfcnt2, + output io_dec_tlu_perfcnt3, + input io_dec_tlu_dbg_halted, + input io_dma_pmu_dccm_write, + input io_dma_pmu_dccm_read, + input io_dma_pmu_any_write, + input io_dma_pmu_any_read, + input io_lsu_pmu_bus_busy, + input [30:0] io_dec_tlu_i0_pc_r, + input io_dec_tlu_i0_valid_r, + input io_dec_csr_any_unq_d, + output io_dec_tlu_misc_clk_override, + output io_dec_tlu_dec_clk_override, + output io_dec_tlu_ifu_clk_override, + output io_dec_tlu_lsu_clk_override, + output io_dec_tlu_bus_clk_override, + output io_dec_tlu_pic_clk_override, + output io_dec_tlu_dccm_clk_override, + output io_dec_tlu_icm_clk_override, + output [31:0] io_dec_csr_rddata_d, + output io_dec_tlu_pipelining_disable, + output io_dec_tlu_wr_pause_r, + input io_ifu_pmu_bus_busy, + input io_lsu_pmu_bus_error, + input io_ifu_pmu_bus_error, + input io_lsu_pmu_bus_misaligned, + input io_lsu_pmu_bus_trxn, + input [70:0] io_ifu_ic_debug_rd_data, + output [3:0] io_dec_tlu_meipt, + input [3:0] io_pic_pl, + output [3:0] io_dec_tlu_meicurpl, + output [29:0] io_dec_tlu_meihap, + input [7:0] io_pic_claimid, + input io_iccm_dma_sb_error, + input [31:0] io_lsu_imprecise_error_addr_any, + input io_lsu_imprecise_error_load_any, + input io_lsu_imprecise_error_store_any, + output [31:0] io_dec_tlu_mrac_ff, + output io_dec_tlu_wb_coalescing_disable, + output io_dec_tlu_bpred_disable, + output io_dec_tlu_sideeffect_posted_disable, + output io_dec_tlu_core_ecc_disable, + output io_dec_tlu_external_ldfwd_disable, + output [2:0] io_dec_tlu_dma_qos_prty, + output io_dec_tlu_trace_disable, + input [31:0] io_dec_illegal_inst, + input [3:0] io_lsu_error_pkt_r_bits_mscause, + input io_mexintpend, + input [30:0] io_exu_npc_r, + input io_mpc_reset_run_req, + input [30:0] io_rst_vec, + input [27:0] io_core_id, + input [31:0] io_dec_timer_rddata_d, + input io_dec_timer_read_d, + output io_dec_csr_wen_r_mod, + input io_rfpc_i0_r, + input io_i0_trigger_hit_r, + output io_fw_halt_req, + output [1:0] io_mstatus, + input io_exc_or_int_valid_r, + input io_mret_r, + output io_mstatus_mie_ns, + input io_dcsr_single_step_running_f, + output [15:0] io_dcsr, + output [30:0] io_mtvec, + output [5:0] io_mip, + input io_dec_timer_t0_pulse, + input io_dec_timer_t1_pulse, + input io_timer_int_sync, + input io_soft_int_sync, + output [5:0] io_mie_ns, + input io_csr_wr_clk, + input io_ebreak_to_debug_mode_r, + input io_dec_tlu_pmu_fw_halted, + input [1:0] io_lsu_fir_error, + output [30:0] io_npc_r, + input io_tlu_flush_lower_r_d1, + input io_dec_tlu_flush_noredir_r_d1, + input [30:0] io_tlu_flush_path_r_d1, + output [30:0] io_npc_r_d1, + input io_reset_delayed, + output [30:0] io_mepc, + input io_interrupt_valid_r, + input io_i0_exception_valid_r, + input io_lsu_exc_valid_r, + input io_mepc_trigger_hit_sel_pc_r, + input io_lsu_single_ecc_error_r, + input io_e4e5_int_clk, + input io_lsu_i0_exc_r, + input io_inst_acc_r, + input io_inst_acc_second_r, + input io_take_nmi, + input [31:0] io_lsu_error_pkt_addr_r, + input [4:0] io_exc_cause_r, + input io_i0_valid_wb, + input io_interrupt_valid_r_d1, + input io_i0_exception_valid_r_d1, + input [4:0] io_exc_cause_wb, + input io_nmi_lsu_store_type, + input io_nmi_lsu_load_type, + input io_tlu_i0_commit_cmt, + input io_ebreak_r, + input io_ecall_r, + input io_illegal_r, + output io_mdseac_locked_ns, + output io_mdseac_locked_f, + input io_nmi_int_detected_f, + input io_internal_dbg_halt_mode_f2, + input io_ext_int_freeze, + output io_ext_int_freeze_d1, + output io_take_ext_int_start_d1, + output io_take_ext_int_start_d2, + output io_take_ext_int_start_d3, + input io_ic_perr_r, + input io_iccm_sbecc_r, + input io_ifu_miss_state_idle_f, + input io_lsu_idle_any_f, + input io_dbg_tlu_halted_f, + input io_dbg_tlu_halted, + input io_debug_halt_req_f, + output io_force_halt, + input io_take_ext_int_start, + input io_trigger_hit_dmode_r_d1, + input io_trigger_hit_r_d1, + input io_dcsr_single_step_done_f, + input io_ebreak_to_debug_mode_r_d1, + input io_debug_halt_req, + input io_allow_dbg_halt_csr_write, + input io_internal_dbg_halt_mode_f, + input io_enter_debug_halt_req, + input io_internal_dbg_halt_mode, + input io_request_debug_mode_done, + input io_request_debug_mode_r, + output [30:0] io_dpc, + input [3:0] io_update_hit_bit_r, + input io_take_timer_int, + input io_take_int_timer0_int, + input io_take_int_timer1_int, + input io_take_ext_int, + input io_tlu_flush_lower_r, + input io_dec_tlu_br0_error_r, + input io_dec_tlu_br0_start_error_r, + input io_lsu_pmu_load_external_r, + input io_lsu_pmu_store_external_r, + input io_csr_pkt_csr_misa, + input io_csr_pkt_csr_mvendorid, + input io_csr_pkt_csr_marchid, + input io_csr_pkt_csr_mimpid, + input io_csr_pkt_csr_mhartid, + input io_csr_pkt_csr_mstatus, + input io_csr_pkt_csr_mtvec, + input io_csr_pkt_csr_mip, + input io_csr_pkt_csr_mie, + input io_csr_pkt_csr_mcyclel, + input io_csr_pkt_csr_mcycleh, + input io_csr_pkt_csr_minstretl, + input io_csr_pkt_csr_minstreth, + input io_csr_pkt_csr_mscratch, + input io_csr_pkt_csr_mepc, + input io_csr_pkt_csr_mcause, + input io_csr_pkt_csr_mscause, + input io_csr_pkt_csr_mtval, + input io_csr_pkt_csr_mrac, + input io_csr_pkt_csr_mdseac, + input io_csr_pkt_csr_meihap, + input io_csr_pkt_csr_meivt, + input io_csr_pkt_csr_meipt, + input io_csr_pkt_csr_meicurpl, + input io_csr_pkt_csr_meicidpl, + input io_csr_pkt_csr_dcsr, + input io_csr_pkt_csr_mcgc, + input io_csr_pkt_csr_mfdc, + input io_csr_pkt_csr_dpc, + input io_csr_pkt_csr_mtsel, + input io_csr_pkt_csr_mtdata1, + input io_csr_pkt_csr_mtdata2, + input io_csr_pkt_csr_mhpmc3, + input io_csr_pkt_csr_mhpmc4, + input io_csr_pkt_csr_mhpmc5, + input io_csr_pkt_csr_mhpmc6, + input io_csr_pkt_csr_mhpmc3h, + input io_csr_pkt_csr_mhpmc4h, + input io_csr_pkt_csr_mhpmc5h, + input io_csr_pkt_csr_mhpmc6h, + input io_csr_pkt_csr_mhpme3, + input io_csr_pkt_csr_mhpme4, + input io_csr_pkt_csr_mhpme5, + input io_csr_pkt_csr_mhpme6, + input io_csr_pkt_csr_mcountinhibit, + input io_csr_pkt_csr_mpmc, + input io_csr_pkt_csr_micect, + input io_csr_pkt_csr_miccmect, + input io_csr_pkt_csr_mdccmect, + input io_csr_pkt_csr_mfdht, + input io_csr_pkt_csr_mfdhs, + input io_csr_pkt_csr_dicawics, + input io_csr_pkt_csr_dicad0h, + input io_csr_pkt_csr_dicad0, + input io_csr_pkt_csr_dicad1, + output [9:0] io_mtdata1_t_0, + output [9:0] io_mtdata1_t_1, + output [9:0] io_mtdata1_t_2, + output [9:0] io_mtdata1_t_3, + input [3:0] io_trigger_enabled +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; +`endif // RANDOMIZE_REG_INIT + wire perfmux_flop_reset; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 1455:34] + wire [6:0] perfmux_flop_io_mcountinhibit; // @[dec_tlu_ctl.scala 1455:34] + wire [9:0] perfmux_flop_io_mhpme_vec_0; // @[dec_tlu_ctl.scala 1455:34] + wire [9:0] perfmux_flop_io_mhpme_vec_1; // @[dec_tlu_ctl.scala 1455:34] + wire [9:0] perfmux_flop_io_mhpme_vec_2; // @[dec_tlu_ctl.scala 1455:34] + wire [9:0] perfmux_flop_io_mhpme_vec_3; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_illegal_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 1455:34] + wire [3:0] perfmux_flop_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dma_pmu_any_read; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dma_pmu_any_write; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 1455:34] + wire [1:0] perfmux_flop_io_mstatus; // @[dec_tlu_ctl.scala 1455:34] + wire [5:0] perfmux_flop_io_mie; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_take_timer_int; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_take_ext_int; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_tlu_br0_error_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mcyclel_cout_f; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_minstret_enable_f; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_minstretl_cout_f; // @[dec_tlu_ctl.scala 1455:34] + wire [3:0] perfmux_flop_io_meicidpl; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_icache_rd_valid_f; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_icache_wr_valid_f; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_perfcnt_halted_d1; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_take_ext_int_start_d2; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1455:34] + wire [5:0] perfmux_flop_io_mip; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mdseac_locked_ns; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_single_ecc_error_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_take_ext_int_start; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_ext_int_freeze; // @[dec_tlu_ctl.scala 1455:34] + wire [5:0] perfmux_flop_io_mip_ns; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mcyclel_cout; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_wr_mcycleh_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mcyclel_cout_in; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_minstret_enable; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_minstretl_cout_ns; // @[dec_tlu_ctl.scala 1455:34] + wire [3:0] perfmux_flop_io_meicidpl_ns; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_icache_rd_valid; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_icache_wr_valid; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_perfcnt_halted; // @[dec_tlu_ctl.scala 1455:34] + wire [1:0] perfmux_flop_io_mstatus_ns; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_free_l2clk; // @[dec_tlu_ctl.scala 1455:34] + wire perf_csrs_clock; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_reset; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_free_l2clk; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 1456:31] + wire [15:0] perf_csrs_io_dcsr; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 1456:31] + wire [9:0] perf_csrs_io_mhpme_vec_0; // @[dec_tlu_ctl.scala 1456:31] + wire [9:0] perf_csrs_io_mhpme_vec_1; // @[dec_tlu_ctl.scala 1456:31] + wire [9:0] perf_csrs_io_mhpme_vec_2; // @[dec_tlu_ctl.scala 1456:31] + wire [9:0] perf_csrs_io_mhpme_vec_3; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 1456:31] + wire [11:0] perf_csrs_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 1456:31] + wire [31:0] perf_csrs_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_perfcnt_halted_d1; // @[dec_tlu_ctl.scala 1456:31] + wire [31:0] perf_csrs_io_mhpmc3h; // @[dec_tlu_ctl.scala 1456:31] + wire [31:0] perf_csrs_io_mhpmc3; // @[dec_tlu_ctl.scala 1456:31] + wire [31:0] perf_csrs_io_mhpmc4h; // @[dec_tlu_ctl.scala 1456:31] + wire [31:0] perf_csrs_io_mhpmc4; // @[dec_tlu_ctl.scala 1456:31] + wire [31:0] perf_csrs_io_mhpmc5h; // @[dec_tlu_ctl.scala 1456:31] + wire [31:0] perf_csrs_io_mhpmc5; // @[dec_tlu_ctl.scala 1456:31] + wire [31:0] perf_csrs_io_mhpmc6h; // @[dec_tlu_ctl.scala 1456:31] + wire [31:0] perf_csrs_io_mhpmc6; // @[dec_tlu_ctl.scala 1456:31] + wire [9:0] perf_csrs_io_mhpme3; // @[dec_tlu_ctl.scala 1456:31] + wire [9:0] perf_csrs_io_mhpme4; // @[dec_tlu_ctl.scala 1456:31] + wire [9:0] perf_csrs_io_mhpme5; // @[dec_tlu_ctl.scala 1456:31] + wire [9:0] perf_csrs_io_mhpme6; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 1456:31] + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_4_io_en; // @[lib.scala 404:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_5_io_en; // @[lib.scala 404:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_6_io_en; // @[lib.scala 404:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_7_io_en; // @[lib.scala 404:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_8_io_en; // @[lib.scala 404:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_9_io_en; // @[lib.scala 404:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_10_io_en; // @[lib.scala 404:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_11_io_en; // @[lib.scala 404:23] + wire rvclkhdr_12_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_12_io_en; // @[lib.scala 404:23] + wire rvclkhdr_13_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_13_io_en; // @[lib.scala 404:23] + wire rvclkhdr_14_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_14_io_en; // @[lib.scala 404:23] + wire rvclkhdr_15_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_15_io_en; // @[lib.scala 404:23] + wire rvclkhdr_16_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_16_io_en; // @[lib.scala 404:23] + wire rvclkhdr_17_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_17_io_en; // @[lib.scala 404:23] + wire rvclkhdr_18_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_18_io_en; // @[lib.scala 404:23] + wire rvclkhdr_19_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_19_io_en; // @[lib.scala 404:23] + wire rvclkhdr_20_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_20_io_en; // @[lib.scala 404:23] + wire rvclkhdr_21_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_21_io_en; // @[lib.scala 404:23] + wire rvclkhdr_22_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_22_io_en; // @[lib.scala 404:23] + wire rvclkhdr_23_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_23_io_en; // @[lib.scala 404:23] + wire rvclkhdr_24_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_24_io_en; // @[lib.scala 404:23] + wire rvclkhdr_25_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_25_io_en; // @[lib.scala 404:23] + wire rvclkhdr_26_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_26_io_en; // @[lib.scala 404:23] + wire rvclkhdr_27_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_27_io_en; // @[lib.scala 404:23] + wire rvclkhdr_28_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_28_io_en; // @[lib.scala 404:23] + wire rvclkhdr_29_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_29_io_en; // @[lib.scala 404:23] + wire rvclkhdr_30_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_30_io_en; // @[lib.scala 404:23] + wire rvclkhdr_31_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_31_io_en; // @[lib.scala 404:23] + wire rvclkhdr_32_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_32_io_en; // @[lib.scala 404:23] + wire rvclkhdr_33_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_33_io_en; // @[lib.scala 404:23] + wire rvclkhdr_34_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_34_io_en; // @[lib.scala 404:23] + wire _T = ~io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 1472:52] + wire _T_1 = io_dec_csr_wen_r & _T; // @[dec_tlu_ctl.scala 1472:50] + wire _T_2 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1472:75] + wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[dec_tlu_ctl.scala 1473:78] + wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[dec_tlu_ctl.scala 1473:49] + wire _T_553 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1883:69] + wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_553; // @[dec_tlu_ctl.scala 1883:46] + wire _T_565 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1891:44] + reg mpmc_b; // @[dec_tlu_ctl.scala 1893:51] + wire mpmc = ~mpmc_b; // @[dec_tlu_ctl.scala 1896:17] + wire _T_566 = ~mpmc; // @[dec_tlu_ctl.scala 1891:69] + wire mpmc_b_ns = wr_mpmc_r ? _T_565 : _T_566; // @[dec_tlu_ctl.scala 1891:25] + wire _T_6 = ~mpmc_b_ns; // @[dec_tlu_ctl.scala 1476:35] + wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[dec_tlu_ctl.scala 1476:46] + wire _T_7 = ~wr_mstatus_r; // @[dec_tlu_ctl.scala 1479:18] + wire _T_8 = _T_7 & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1479:32] + wire [1:0] _T_12 = {io_mstatus[0],1'h0}; // @[Cat.scala 29:58] + wire _T_13 = wr_mstatus_r & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1480:31] + wire [1:0] _T_16 = {io_dec_csr_wrdata_r[3],1'h0}; // @[Cat.scala 29:58] + wire _T_17 = ~io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1481:30] + wire _T_18 = io_mret_r & _T_17; // @[dec_tlu_ctl.scala 1481:28] + wire [1:0] _T_21 = {1'h1,io_mstatus[1]}; // @[Cat.scala 29:58] + wire [1:0] _T_24 = {io_mstatus[1],1'h1}; // @[Cat.scala 29:58] + wire _T_26 = wr_mstatus_r & _T_17; // @[dec_tlu_ctl.scala 1483:31] + wire [1:0] _T_30 = {io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58] + wire _T_33 = _T_7 & _T_17; // @[dec_tlu_ctl.scala 1484:32] + wire _T_34 = ~io_mret_r; // @[dec_tlu_ctl.scala 1484:59] + wire _T_35 = _T_33 & _T_34; // @[dec_tlu_ctl.scala 1484:57] + wire _T_36 = ~set_mie_pmu_fw_halt; // @[dec_tlu_ctl.scala 1484:72] + wire _T_37 = _T_35 & _T_36; // @[dec_tlu_ctl.scala 1484:70] + wire [1:0] _T_39 = _T_8 ? _T_12 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_40 = _T_13 ? _T_16 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_41 = _T_18 ? _T_21 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_42 = set_mie_pmu_fw_halt ? _T_24 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_43 = _T_26 ? _T_30 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_44 = _T_37 ? io_mstatus : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_45 = _T_39 | _T_40; // @[Mux.scala 27:72] + wire [1:0] _T_46 = _T_45 | _T_41; // @[Mux.scala 27:72] + wire [1:0] _T_47 = _T_46 | _T_42; // @[Mux.scala 27:72] + wire [1:0] _T_48 = _T_47 | _T_43; // @[Mux.scala 27:72] + wire _T_52 = ~io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 1489:57] + wire _T_54 = _T_52 | io_dcsr[11]; // @[dec_tlu_ctl.scala 1489:88] + wire _T_57 = io_dec_csr_wraddr_r == 12'h305; // @[dec_tlu_ctl.scala 1500:76] + wire wr_mtvec_r = io_dec_csr_wen_r_mod & _T_57; // @[dec_tlu_ctl.scala 1500:47] + wire [30:0] mtvec_ns = {io_dec_csr_wrdata_r[31:2],io_dec_csr_wrdata_r[0]}; // @[Cat.scala 29:58] + reg [30:0] _T_61; // @[Reg.scala 27:20] + reg [31:0] mdccmect; // @[Reg.scala 27:20] + wire [62:0] _T_629 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1942:48] + wire [31:0] _T_631 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_43 = {{31'd0}, _T_631}; // @[dec_tlu_ctl.scala 1942:68] + wire [62:0] _T_632 = _T_629 & _GEN_43; // @[dec_tlu_ctl.scala 1942:68] + wire mdccme_ce_req = |_T_632; // @[dec_tlu_ctl.scala 1942:101] + reg [31:0] miccmect; // @[Reg.scala 27:20] + wire [62:0] _T_609 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1928:48] + wire [31:0] _T_611 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_44 = {{31'd0}, _T_611}; // @[dec_tlu_ctl.scala 1928:68] + wire [62:0] _T_612 = _T_609 & _GEN_44; // @[dec_tlu_ctl.scala 1928:68] + wire miccme_ce_req = |_T_612; // @[dec_tlu_ctl.scala 1928:101] + wire _T_62 = mdccme_ce_req | miccme_ce_req; // @[dec_tlu_ctl.scala 1514:37] + reg [31:0] micect; // @[Reg.scala 27:20] + wire [62:0] _T_587 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1913:46] + wire [31:0] _T_589 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_45 = {{31'd0}, _T_589}; // @[dec_tlu_ctl.scala 1913:64] + wire [62:0] _T_590 = _T_587 & _GEN_45; // @[dec_tlu_ctl.scala 1913:64] + wire mice_ce_req = |_T_590; // @[dec_tlu_ctl.scala 1913:95] + wire ce_int = _T_62 | mice_ce_req; // @[dec_tlu_ctl.scala 1514:53] + wire [2:0] _T_64 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58] + wire [2:0] _T_66 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58] + wire _T_68 = io_dec_csr_wraddr_r == 12'h304; // @[dec_tlu_ctl.scala 1530:74] + wire wr_mie_r = io_dec_csr_wen_r_mod & _T_68; // @[dec_tlu_ctl.scala 1530:45] + wire [5:0] _T_76 = {io_dec_csr_wrdata_r[30:28],io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58] + reg [5:0] mie; // @[dec_tlu_ctl.scala 1533:24] + wire kill_ebreak_count_r = io_ebreak_to_debug_mode_r & io_dcsr[10]; // @[dec_tlu_ctl.scala 1539:61] + wire _T_81 = io_dec_csr_wraddr_r == 12'hb00; // @[dec_tlu_ctl.scala 1541:78] + wire wr_mcyclel_r = io_dec_csr_wen_r_mod & _T_81; // @[dec_tlu_ctl.scala 1541:49] + wire _T_83 = io_dec_tlu_dbg_halted & io_dcsr[10]; // @[dec_tlu_ctl.scala 1543:78] + wire _T_84 = kill_ebreak_count_r | _T_83; // @[dec_tlu_ctl.scala 1543:53] + wire _T_85 = _T_84 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 1543:101] + reg [4:0] temp_ncount6_2; // @[Reg.scala 27:20] + wire [5:0] _T_1138 = {temp_ncount6_2,1'h0}; // @[Cat.scala 29:58] + reg temp_ncount0; // @[Reg.scala 27:20] + wire [6:0] mcountinhibit = {temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire _T_87 = _T_85 | mcountinhibit[0]; // @[dec_tlu_ctl.scala 1543:128] + wire mcyclel_cout_in = ~_T_87; // @[dec_tlu_ctl.scala 1543:31] + reg [23:0] _T_106; // @[Reg.scala 27:20] + reg [7:0] _T_110; // @[Reg.scala 27:20] + wire [31:0] mcyclel = {_T_106,_T_110}; // @[Cat.scala 29:58] + wire [8:0] mcyclel_inc1 = mcyclel[7:0] + 8'h1; // @[dec_tlu_ctl.scala 1548:38] + wire [23:0] _T_93 = {23'h0,mcyclel_inc1[8]}; // @[Cat.scala 29:58] + wire [24:0] mcyclel_inc2 = mcyclel[31:8] + _T_93; // @[dec_tlu_ctl.scala 1549:39] + wire [31:0] mcyclel_inc = {mcyclel_inc2[23:0],mcyclel_inc1[7:0]}; // @[Cat.scala 29:58] + wire [31:0] mcyclel_ns = wr_mcyclel_r ? io_dec_csr_wrdata_r : mcyclel_inc; // @[dec_tlu_ctl.scala 1551:29] + wire _T_102 = mcyclel_inc1[8] & mcyclel_cout_in; // @[dec_tlu_ctl.scala 1553:82] + wire _T_104 = wr_mcyclel_r | _T_102; // @[dec_tlu_ctl.scala 1553:63] + wire _T_108 = wr_mcyclel_r | mcyclel_cout_in; // @[dec_tlu_ctl.scala 1553:184] + wire _T_113 = io_dec_csr_wraddr_r == 12'hb80; // @[dec_tlu_ctl.scala 1560:78] + wire wr_mcycleh_r = io_dec_csr_wen_r_mod & _T_113; // @[dec_tlu_ctl.scala 1560:49] + wire [31:0] _T_114 = {31'h0,perfmux_flop_io_mcyclel_cout_f}; // @[Cat.scala 29:58] + reg [31:0] mcycleh; // @[Reg.scala 27:20] + wire [31:0] mcycleh_inc = mcycleh + _T_114; // @[dec_tlu_ctl.scala 1562:35] + wire _T_117 = wr_mcycleh_r | perfmux_flop_io_mcyclel_cout_f; // @[dec_tlu_ctl.scala 1565:53] + wire _T_120 = io_ebreak_r | io_ecall_r; // @[dec_tlu_ctl.scala 1579:81] + wire _T_121 = _T_120 | io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 1579:94] + wire _T_122 = _T_121 | io_illegal_r; // @[dec_tlu_ctl.scala 1579:122] + wire _T_124 = _T_122 | mcountinhibit[2]; // @[dec_tlu_ctl.scala 1579:137] + wire _T_125 = ~_T_124; // @[dec_tlu_ctl.scala 1579:67] + wire i0_valid_no_ebreak_ecall_r = io_dec_tlu_i0_valid_r & _T_125; // @[dec_tlu_ctl.scala 1579:65] + wire _T_128 = io_dec_csr_wraddr_r == 12'hb02; // @[dec_tlu_ctl.scala 1581:80] + wire wr_minstretl_r = io_dec_csr_wen_r_mod & _T_128; // @[dec_tlu_ctl.scala 1581:51] + reg [23:0] _T_150; // @[Reg.scala 27:20] + reg [7:0] _T_153; // @[Reg.scala 27:20] + wire [31:0] minstretl = {_T_150,_T_153}; // @[Cat.scala 29:58] + wire [8:0] minstretl_inc1 = minstretl[7:0] + 8'h1; // @[dec_tlu_ctl.scala 1585:42] + wire [23:0] _T_134 = {23'h0,minstretl_inc1[8]}; // @[Cat.scala 29:58] + wire [24:0] minstretl_inc2 = minstretl[31:8] + _T_134; // @[dec_tlu_ctl.scala 1586:43] + wire minstretl_cout = minstretl_inc2[24]; // @[dec_tlu_ctl.scala 1587:44] + wire [31:0] minstretl_inc = {minstretl_inc2[23:0],minstretl_inc1[7:0]}; // @[Cat.scala 29:58] + wire _T_138 = i0_valid_no_ebreak_ecall_r & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 1589:59] + wire minstret_enable = _T_138 | wr_minstretl_r; // @[dec_tlu_ctl.scala 1589:83] + wire _T_156 = io_dec_csr_wraddr_r == 12'hb82; // @[dec_tlu_ctl.scala 1605:78] + wire wr_minstreth_r = io_dec_csr_wen_r_mod & _T_156; // @[dec_tlu_ctl.scala 1605:49] + wire _T_139 = ~wr_minstreth_r; // @[dec_tlu_ctl.scala 1590:50] + wire _T_140 = minstretl_cout & _T_139; // @[dec_tlu_ctl.scala 1590:48] + wire _T_141 = _T_140 & i0_valid_no_ebreak_ecall_r; // @[dec_tlu_ctl.scala 1590:66] + wire _T_142 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 1590:97] + wire [31:0] minstretl_ns = wr_minstretl_r ? io_dec_csr_wrdata_r : minstretl_inc; // @[dec_tlu_ctl.scala 1593:31] + wire _T_147 = minstretl_inc1[8] & minstret_enable; // @[dec_tlu_ctl.scala 1595:88] + wire _T_148 = wr_minstretl_r | _T_147; // @[dec_tlu_ctl.scala 1595:67] + wire [31:0] _T_159 = {31'h0,perfmux_flop_io_minstretl_cout_f}; // @[Cat.scala 29:58] + reg [31:0] minstreth; // @[Reg.scala 27:20] + wire [31:0] minstreth_inc = minstreth + _T_159; // @[dec_tlu_ctl.scala 1609:39] + wire _T_162 = perfmux_flop_io_minstret_enable_f & perfmux_flop_io_minstretl_cout_f; // @[dec_tlu_ctl.scala 1612:79] + wire _T_163 = _T_162 | wr_minstreth_r; // @[dec_tlu_ctl.scala 1612:116] + wire _T_167 = io_dec_csr_wraddr_r == 12'h340; // @[dec_tlu_ctl.scala 1620:79] + wire wr_mscratch_r = io_dec_csr_wen_r_mod & _T_167; // @[dec_tlu_ctl.scala 1620:50] + reg [31:0] mscratch; // @[Reg.scala 27:20] + wire _T_171 = ~io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1631:54] + wire _T_172 = _T_142 & _T_171; // @[dec_tlu_ctl.scala 1631:52] + wire sel_exu_npc_r = _T_172 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1631:79] + wire _T_174 = _T_142 & io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1632:54] + wire _T_175 = ~io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 1632:82] + wire sel_flush_npc_r = _T_174 & _T_175; // @[dec_tlu_ctl.scala 1632:80] + wire _T_176 = ~sel_exu_npc_r; // @[dec_tlu_ctl.scala 1633:30] + wire _T_177 = ~sel_flush_npc_r; // @[dec_tlu_ctl.scala 1633:47] + wire sel_hold_npc_r = _T_176 & _T_177; // @[dec_tlu_ctl.scala 1633:45] + wire _T_179 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 1637:18] + wire _T_180 = _T_179 & io_reset_delayed; // @[dec_tlu_ctl.scala 1637:40] + wire [30:0] _T_184 = sel_exu_npc_r ? io_exu_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_185 = _T_180 ? io_rst_vec : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_186 = sel_flush_npc_r ? io_tlu_flush_path_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_187 = sel_hold_npc_r ? io_npc_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_188 = _T_184 | _T_185; // @[Mux.scala 27:72] + wire [30:0] _T_189 = _T_188 | _T_186; // @[Mux.scala 27:72] + wire _T_192 = sel_exu_npc_r | sel_flush_npc_r; // @[dec_tlu_ctl.scala 1641:58] + wire _T_193 = _T_192 | io_reset_delayed; // @[dec_tlu_ctl.scala 1641:76] + reg [30:0] _T_196; // @[Reg.scala 27:20] + wire pc0_valid_r = _T_142 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1644:51] + wire _T_199 = ~pc0_valid_r; // @[dec_tlu_ctl.scala 1648:17] + wire [30:0] _T_200 = pc0_valid_r ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] + reg [30:0] pc_r_d1; // @[Reg.scala 27:20] + wire [30:0] _T_201 = _T_199 ? pc_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] pc_r = _T_200 | _T_201; // @[Mux.scala 27:72] + wire _T_206 = io_dec_csr_wraddr_r == 12'h341; // @[dec_tlu_ctl.scala 1652:75] + wire wr_mepc_r = io_dec_csr_wen_r_mod & _T_206; // @[dec_tlu_ctl.scala 1652:46] + wire _T_207 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1655:42] + wire _T_208 = _T_207 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1655:63] + wire _T_212 = wr_mepc_r & _T_17; // @[dec_tlu_ctl.scala 1657:28] + wire _T_215 = ~wr_mepc_r; // @[dec_tlu_ctl.scala 1658:18] + wire _T_217 = _T_215 & _T_17; // @[dec_tlu_ctl.scala 1658:29] + wire [30:0] _T_219 = _T_208 ? pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_220 = io_interrupt_valid_r ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_221 = _T_212 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_222 = _T_217 ? io_mepc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_223 = _T_219 | _T_220; // @[Mux.scala 27:72] + wire [30:0] _T_224 = _T_223 | _T_221; // @[Mux.scala 27:72] + wire [30:0] mepc_ns = _T_224 | _T_222; // @[Mux.scala 27:72] + wire _T_228 = _T_208 | io_interrupt_valid_r; // @[dec_tlu_ctl.scala 1660:111] + wire _T_229 = _T_228 | wr_mepc_r; // @[dec_tlu_ctl.scala 1660:134] + reg [30:0] _T_231; // @[Reg.scala 27:20] + wire _T_233 = io_dec_csr_wraddr_r == 12'h342; // @[dec_tlu_ctl.scala 1668:77] + wire wr_mcause_r = io_dec_csr_wen_r_mod & _T_233; // @[dec_tlu_ctl.scala 1668:48] + wire _T_234 = io_exc_or_int_valid_r & io_take_nmi; // @[dec_tlu_ctl.scala 1669:58] + wire mcause_sel_nmi_store = _T_234 & io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 1669:72] + wire mcause_sel_nmi_load = _T_234 & io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 1670:71] + wire _T_237 = _T_234 & io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 1671:69] + wire _T_238 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 1671:115] + wire _T_239 = _T_237 & _T_238; // @[dec_tlu_ctl.scala 1671:96] + wire _T_240 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1671:121] + wire mcause_sel_nmi_ext = _T_239 & _T_240; // @[dec_tlu_ctl.scala 1671:119] + wire _T_241 = &io_lsu_fir_error; // @[dec_tlu_ctl.scala 1678:58] + wire _T_244 = ~io_lsu_fir_error[0]; // @[dec_tlu_ctl.scala 1678:87] + wire _T_245 = io_lsu_fir_error[1] & _T_244; // @[dec_tlu_ctl.scala 1678:85] + wire [31:0] _T_250 = {30'h3c000400,_T_241,_T_245}; // @[Cat.scala 29:58] + wire _T_251 = ~io_take_nmi; // @[dec_tlu_ctl.scala 1684:42] + wire _T_252 = io_exc_or_int_valid_r & _T_251; // @[dec_tlu_ctl.scala 1684:40] + wire [31:0] _T_255 = {io_interrupt_valid_r,26'h0,io_exc_cause_r}; // @[Cat.scala 29:58] + wire _T_257 = wr_mcause_r & _T_17; // @[dec_tlu_ctl.scala 1685:30] + wire _T_259 = ~wr_mcause_r; // @[dec_tlu_ctl.scala 1686:18] + wire _T_261 = _T_259 & _T_17; // @[dec_tlu_ctl.scala 1686:31] + wire [31:0] _T_263 = mcause_sel_nmi_store ? 32'hf0000000 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_264 = mcause_sel_nmi_load ? 32'hf0000001 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_265 = mcause_sel_nmi_ext ? _T_250 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_266 = _T_252 ? _T_255 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_267 = _T_257 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] + reg [31:0] mcause; // @[Reg.scala 27:20] + wire [31:0] _T_268 = _T_261 ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_269 = _T_263 | _T_264; // @[Mux.scala 27:72] + wire [31:0] _T_270 = _T_269 | _T_265; // @[Mux.scala 27:72] + wire [31:0] _T_271 = _T_270 | _T_266; // @[Mux.scala 27:72] + wire [31:0] _T_272 = _T_271 | _T_267; // @[Mux.scala 27:72] + wire [31:0] mcause_ns = _T_272 | _T_268; // @[Mux.scala 27:72] + wire _T_274 = io_exc_or_int_valid_r | wr_mcause_r; // @[dec_tlu_ctl.scala 1688:58] + wire _T_278 = io_dec_csr_wraddr_r == 12'h7ff; // @[dec_tlu_ctl.scala 1695:78] + wire wr_mscause_r = io_dec_csr_wen_r_mod & _T_278; // @[dec_tlu_ctl.scala 1695:49] + wire _T_279 = io_dec_tlu_packet_r_icaf_type == 2'h0; // @[dec_tlu_ctl.scala 1697:63] + wire [3:0] _T_280 = {2'h0,io_dec_tlu_packet_r_icaf_type}; // @[Cat.scala 29:58] + wire [3:0] ifu_mscause = _T_279 ? 4'h9 : _T_280; // @[dec_tlu_ctl.scala 1697:31] + wire [3:0] _T_285 = io_lsu_i0_exc_r ? io_lsu_error_pkt_r_bits_mscause : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_286 = io_i0_trigger_hit_r ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_287 = io_ebreak_r ? 4'h2 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_288 = io_inst_acc_r ? ifu_mscause : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_289 = _T_285 | _T_286; // @[Mux.scala 27:72] + wire [3:0] _T_290 = _T_289 | _T_287; // @[Mux.scala 27:72] + wire [3:0] mscause_type = _T_290 | _T_288; // @[Mux.scala 27:72] + wire _T_294 = wr_mscause_r & _T_17; // @[dec_tlu_ctl.scala 1708:31] + wire _T_297 = ~wr_mscause_r; // @[dec_tlu_ctl.scala 1709:18] + wire _T_299 = _T_297 & _T_17; // @[dec_tlu_ctl.scala 1709:32] + wire [3:0] _T_301 = io_exc_or_int_valid_r ? mscause_type : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_302 = _T_294 ? io_dec_csr_wrdata_r[3:0] : 4'h0; // @[Mux.scala 27:72] + reg [3:0] mscause; // @[dec_tlu_ctl.scala 1711:54] + wire [3:0] _T_303 = _T_299 ? mscause : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_304 = _T_301 | _T_302; // @[Mux.scala 27:72] + wire _T_308 = io_dec_csr_wraddr_r == 12'h343; // @[dec_tlu_ctl.scala 1718:76] + wire wr_mtval_r = io_dec_csr_wen_r_mod & _T_308; // @[dec_tlu_ctl.scala 1718:47] + wire _T_309 = ~io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1719:90] + wire _T_310 = io_inst_acc_r & _T_309; // @[dec_tlu_ctl.scala 1719:88] + wire _T_311 = io_ebreak_r | _T_310; // @[dec_tlu_ctl.scala 1719:71] + wire _T_312 = _T_311 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1719:113] + wire _T_313 = io_exc_or_int_valid_r & _T_312; // @[dec_tlu_ctl.scala 1719:56] + wire mtval_capture_pc_r = _T_313 & _T_251; // @[dec_tlu_ctl.scala 1719:145] + wire _T_315 = io_inst_acc_r & io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1720:79] + wire _T_316 = io_exc_or_int_valid_r & _T_315; // @[dec_tlu_ctl.scala 1720:62] + wire mtval_capture_pc_plus2_r = _T_316 & _T_251; // @[dec_tlu_ctl.scala 1720:103] + wire _T_318 = io_exc_or_int_valid_r & io_illegal_r; // @[dec_tlu_ctl.scala 1721:58] + wire mtval_capture_inst_r = _T_318 & _T_251; // @[dec_tlu_ctl.scala 1721:73] + wire _T_320 = io_exc_or_int_valid_r & io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1722:57] + wire mtval_capture_lsu_r = _T_320 & _T_251; // @[dec_tlu_ctl.scala 1722:78] + wire _T_322 = ~mtval_capture_pc_r; // @[dec_tlu_ctl.scala 1723:53] + wire _T_323 = io_exc_or_int_valid_r & _T_322; // @[dec_tlu_ctl.scala 1723:51] + wire _T_324 = ~mtval_capture_inst_r; // @[dec_tlu_ctl.scala 1723:75] + wire _T_325 = _T_323 & _T_324; // @[dec_tlu_ctl.scala 1723:73] + wire _T_326 = ~mtval_capture_lsu_r; // @[dec_tlu_ctl.scala 1723:99] + wire _T_327 = _T_325 & _T_326; // @[dec_tlu_ctl.scala 1723:97] + wire _T_328 = ~io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1723:122] + wire mtval_clear_r = _T_327 & _T_328; // @[dec_tlu_ctl.scala 1723:120] + wire [31:0] _T_330 = {pc_r,1'h0}; // @[Cat.scala 29:58] + wire [30:0] _T_333 = pc_r + 31'h1; // @[dec_tlu_ctl.scala 1728:96] + wire [31:0] _T_334 = {_T_333,1'h0}; // @[Cat.scala 29:58] + wire _T_337 = ~io_interrupt_valid_r; // @[dec_tlu_ctl.scala 1731:31] + wire _T_338 = wr_mtval_r & _T_337; // @[dec_tlu_ctl.scala 1731:29] + wire _T_341 = ~wr_mtval_r; // @[dec_tlu_ctl.scala 1732:33] + wire _T_342 = _T_251 & _T_341; // @[dec_tlu_ctl.scala 1732:31] + wire _T_344 = _T_342 & _T_322; // @[dec_tlu_ctl.scala 1732:45] + wire _T_346 = _T_344 & _T_324; // @[dec_tlu_ctl.scala 1732:67] + wire _T_347 = ~mtval_clear_r; // @[dec_tlu_ctl.scala 1732:93] + wire _T_348 = _T_346 & _T_347; // @[dec_tlu_ctl.scala 1732:91] + wire _T_350 = _T_348 & _T_326; // @[dec_tlu_ctl.scala 1732:108] + wire [31:0] _T_352 = mtval_capture_pc_r ? _T_330 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_353 = mtval_capture_pc_plus2_r ? _T_334 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_354 = mtval_capture_inst_r ? io_dec_illegal_inst : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_355 = mtval_capture_lsu_r ? io_lsu_error_pkt_addr_r : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_356 = _T_338 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] + reg [31:0] mtval; // @[Reg.scala 27:20] + wire [31:0] _T_357 = _T_350 ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_358 = _T_352 | _T_353; // @[Mux.scala 27:72] + wire [31:0] _T_359 = _T_358 | _T_354; // @[Mux.scala 27:72] + wire [31:0] _T_360 = _T_359 | _T_355; // @[Mux.scala 27:72] + wire [31:0] _T_361 = _T_360 | _T_356; // @[Mux.scala 27:72] + wire [31:0] mtval_ns = _T_361 | _T_357; // @[Mux.scala 27:72] + wire _T_363 = io_tlu_flush_lower_r | wr_mtval_r; // @[dec_tlu_ctl.scala 1734:55] + wire _T_367 = io_dec_csr_wraddr_r == 12'h7f8; // @[dec_tlu_ctl.scala 1752:75] + wire wr_mcgc_r = io_dec_csr_wen_r_mod & _T_367; // @[dec_tlu_ctl.scala 1752:46] + wire _T_370 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1753:42] + wire [9:0] _T_372 = {_T_370,io_dec_csr_wrdata_r[8:0]}; // @[Cat.scala 29:58] + reg [9:0] mcgc_int; // @[Reg.scala 27:20] + wire _T_376 = ~mcgc_int[9]; // @[dec_tlu_ctl.scala 1755:24] + wire [9:0] mcgc = {_T_376,mcgc_int[8:0]}; // @[Cat.scala 29:58] + wire _T_388 = io_dec_csr_wraddr_r == 12'h7f9; // @[dec_tlu_ctl.scala 1785:75] + wire wr_mfdc_r = io_dec_csr_wen_r_mod & _T_388; // @[dec_tlu_ctl.scala 1785:46] + reg [15:0] mfdc_int; // @[Reg.scala 27:20] + wire [2:0] _T_392 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1795:32] + wire _T_396 = ~io_dec_csr_wrdata_r[6]; // @[dec_tlu_ctl.scala 1795:111] + wire [15:0] mfdc_ns = {_T_392,io_dec_csr_wrdata_r[12],io_dec_csr_wrdata_r[11:7],_T_396,io_dec_csr_wrdata_r[5:0]}; // @[Cat.scala 29:58] + wire [2:0] _T_403 = ~mfdc_int[15:13]; // @[dec_tlu_ctl.scala 1796:32] + wire _T_407 = ~mfdc_int[6]; // @[dec_tlu_ctl.scala 1796:88] + wire [18:0] mfdc = {_T_403,3'h0,mfdc_int[12],mfdc_int[11:7],_T_407,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire _T_423 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1822:84] + wire _T_424 = io_dec_csr_wen_r_mod & _T_423; // @[dec_tlu_ctl.scala 1822:55] + wire _T_426 = _T_424 & _T_337; // @[dec_tlu_ctl.scala 1822:94] + wire _T_427 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1822:120] + wire _T_430 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1829:75] + wire wr_mrac_r = io_dec_csr_wen_r_mod & _T_430; // @[dec_tlu_ctl.scala 1829:46] + wire _T_434 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1832:78] + wire _T_435 = io_dec_csr_wrdata_r[30] & _T_434; // @[dec_tlu_ctl.scala 1832:76] + wire _T_439 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1833:68] + wire _T_440 = io_dec_csr_wrdata_r[28] & _T_439; // @[dec_tlu_ctl.scala 1833:66] + wire _T_444 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1834:68] + wire _T_445 = io_dec_csr_wrdata_r[26] & _T_444; // @[dec_tlu_ctl.scala 1834:66] + wire _T_449 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1835:68] + wire _T_450 = io_dec_csr_wrdata_r[24] & _T_449; // @[dec_tlu_ctl.scala 1835:66] + wire _T_454 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1836:68] + wire _T_455 = io_dec_csr_wrdata_r[22] & _T_454; // @[dec_tlu_ctl.scala 1836:66] + wire _T_459 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1837:68] + wire _T_460 = io_dec_csr_wrdata_r[20] & _T_459; // @[dec_tlu_ctl.scala 1837:66] + wire _T_464 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1838:68] + wire _T_465 = io_dec_csr_wrdata_r[18] & _T_464; // @[dec_tlu_ctl.scala 1838:66] + wire _T_469 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1839:68] + wire _T_470 = io_dec_csr_wrdata_r[16] & _T_469; // @[dec_tlu_ctl.scala 1839:66] + wire _T_474 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1840:68] + wire _T_475 = io_dec_csr_wrdata_r[14] & _T_474; // @[dec_tlu_ctl.scala 1840:66] + wire _T_479 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1841:68] + wire _T_480 = io_dec_csr_wrdata_r[12] & _T_479; // @[dec_tlu_ctl.scala 1841:66] + wire _T_484 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1842:68] + wire _T_485 = io_dec_csr_wrdata_r[10] & _T_484; // @[dec_tlu_ctl.scala 1842:66] + wire _T_490 = io_dec_csr_wrdata_r[8] & _T_370; // @[dec_tlu_ctl.scala 1843:65] + wire _T_494 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1844:68] + wire _T_495 = io_dec_csr_wrdata_r[6] & _T_494; // @[dec_tlu_ctl.scala 1844:65] + wire _T_499 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1845:68] + wire _T_500 = io_dec_csr_wrdata_r[4] & _T_499; // @[dec_tlu_ctl.scala 1845:65] + wire _T_504 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1846:68] + wire _T_505 = io_dec_csr_wrdata_r[2] & _T_504; // @[dec_tlu_ctl.scala 1846:65] + wire _T_510 = io_dec_csr_wrdata_r[0] & _T_565; // @[dec_tlu_ctl.scala 1847:65] + wire [7:0] _T_517 = {io_dec_csr_wrdata_r[7],_T_495,io_dec_csr_wrdata_r[5],_T_500,io_dec_csr_wrdata_r[3],_T_505,io_dec_csr_wrdata_r[1],_T_510}; // @[Cat.scala 29:58] + wire [15:0] _T_525 = {io_dec_csr_wrdata_r[15],_T_475,io_dec_csr_wrdata_r[13],_T_480,io_dec_csr_wrdata_r[11],_T_485,io_dec_csr_wrdata_r[9],_T_490,_T_517}; // @[Cat.scala 29:58] + wire [7:0] _T_532 = {io_dec_csr_wrdata_r[23],_T_455,io_dec_csr_wrdata_r[21],_T_460,io_dec_csr_wrdata_r[19],_T_465,io_dec_csr_wrdata_r[17],_T_470}; // @[Cat.scala 29:58] + wire [31:0] mrac_in = {io_dec_csr_wrdata_r[31],_T_435,io_dec_csr_wrdata_r[29],_T_440,io_dec_csr_wrdata_r[27],_T_445,io_dec_csr_wrdata_r[25],_T_450,_T_532,_T_525}; // @[Cat.scala 29:58] + reg [31:0] mrac; // @[Reg.scala 27:20] + wire _T_543 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1860:76] + wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_543; // @[dec_tlu_ctl.scala 1860:47] + wire _T_544 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1870:66] + wire _T_545 = io_mdseac_locked_f & _T_544; // @[dec_tlu_ctl.scala 1870:64] + wire _T_547 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1872:56] + wire _T_549 = _T_547 & _T_240; // @[dec_tlu_ctl.scala 1872:91] + wire _T_550 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1872:118] + wire mdseac_en = _T_549 & _T_550; // @[dec_tlu_ctl.scala 1872:116] + reg [31:0] mdseac; // @[Reg.scala 27:20] + wire _T_555 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1887:37] + wire _T_556 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1887:64] + wire _T_557 = _T_555 & _T_556; // @[dec_tlu_ctl.scala 1887:62] + wire _T_558 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1887:96] + wire _T_571 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1905:55] + wire [4:0] csr_sat = _T_571 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1905:26] + wire _T_573 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1907:71] + wire wr_micect_r = io_dec_csr_wen_r_mod & _T_573; // @[dec_tlu_ctl.scala 1907:48] + wire [26:0] _T_575 = {26'h0,io_ic_perr_r}; // @[Cat.scala 29:58] + wire [26:0] micect_inc = micect[26:0] + _T_575; // @[dec_tlu_ctl.scala 1908:36] + wire [31:0] _T_580 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_582 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] + wire _T_583 = wr_micect_r | io_ic_perr_r; // @[dec_tlu_ctl.scala 1911:49] + wire _T_593 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1922:83] + wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_593; // @[dec_tlu_ctl.scala 1922:54] + wire _T_595 = io_iccm_sbecc_r | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1923:74] + wire [26:0] _T_596 = {26'h0,_T_595}; // @[Cat.scala 29:58] + wire [26:0] miccmect_inc = miccmect[26:0] + _T_596; // @[dec_tlu_ctl.scala 1923:40] + wire [31:0] _T_603 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] + wire _T_604 = wr_miccmect_r | io_iccm_sbecc_r; // @[dec_tlu_ctl.scala 1926:55] + wire _T_605 = _T_604 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1926:73] + wire _T_615 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1937:83] + wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_615; // @[dec_tlu_ctl.scala 1937:54] + wire [26:0] _T_617 = {26'h0,perfmux_flop_io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] + wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_617; // @[dec_tlu_ctl.scala 1938:40] + wire [31:0] _T_624 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] + wire _T_625 = wr_mdccmect_r | perfmux_flop_io_lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 1941:56] + wire _T_635 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1952:76] + wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_635; // @[dec_tlu_ctl.scala 1952:47] + reg [5:0] mfdht; // @[Reg.scala 27:20] + wire _T_641 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1965:76] + wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_641; // @[dec_tlu_ctl.scala 1965:47] + wire _T_644 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1968:42] + wire _T_645 = io_dbg_tlu_halted & _T_644; // @[dec_tlu_ctl.scala 1968:40] + wire _T_647 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1968:77] + wire _T_648 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1968:97] + wire [1:0] _T_649 = {_T_647,_T_648}; // @[Cat.scala 29:58] + reg [1:0] mfdhs; // @[Reg.scala 27:20] + wire _T_651 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1970:76] + reg [31:0] force_halt_ctr_f; // @[Reg.scala 27:20] + wire [31:0] _T_656 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1972:81] + wire [62:0] _T_663 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1977:78] + wire [62:0] _GEN_46 = {{31'd0}, force_halt_ctr_f}; // @[dec_tlu_ctl.scala 1977:55] + wire [62:0] _T_664 = _GEN_46 & _T_663; // @[dec_tlu_ctl.scala 1977:55] + wire _T_665 = |_T_664; // @[dec_tlu_ctl.scala 1977:94] + wire _T_668 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1985:76] + wire wr_meivt_r = io_dec_csr_wen_r_mod & _T_668; // @[dec_tlu_ctl.scala 1985:47] + reg [21:0] meivt; // @[Reg.scala 27:20] + wire _T_686 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 2036:76] + wire _T_687 = io_dec_csr_wen_r_mod & _T_686; // @[dec_tlu_ctl.scala 2036:47] + wire wr_meicpct_r = _T_687 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 2036:90] + reg [7:0] meihap; // @[Reg.scala 27:20] + wire _T_674 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 2009:79] + wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_674; // @[dec_tlu_ctl.scala 2009:50] + reg [3:0] meicurpl; // @[dec_tlu_ctl.scala 2012:53] + wire _T_679 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 2024:80] + wire _T_680 = io_dec_csr_wen_r_mod & _T_679; // @[dec_tlu_ctl.scala 2024:51] + wire wr_meicidpl_r = _T_680 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 2024:95] + wire [3:0] _T_684 = wr_meicidpl_r ? io_dec_csr_wrdata_r[3:0] : perfmux_flop_io_meicidpl; // @[dec_tlu_ctl.scala 2027:20] + wire _T_690 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 2045:76] + wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_690; // @[dec_tlu_ctl.scala 2045:47] + reg [3:0] meipt; // @[dec_tlu_ctl.scala 2048:50] + wire _T_694 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2076:96] + wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_694; // @[dec_tlu_ctl.scala 2076:73] + wire _T_695 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2079:47] + wire _T_696 = io_dcsr_single_step_done_f & _T_695; // @[dec_tlu_ctl.scala 2079:45] + wire _T_697 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2079:79] + wire _T_698 = _T_696 & _T_697; // @[dec_tlu_ctl.scala 2079:77] + wire _T_699 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2079:114] + wire _T_700 = _T_698 & _T_699; // @[dec_tlu_ctl.scala 2079:112] + wire _T_703 = io_debug_halt_req & _T_695; // @[dec_tlu_ctl.scala 2080:36] + wire _T_705 = _T_703 & _T_697; // @[dec_tlu_ctl.scala 2080:68] + wire _T_708 = io_ebreak_to_debug_mode_r_d1 & _T_697; // @[dec_tlu_ctl.scala 2081:47] + wire [2:0] _T_711 = _T_700 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_712 = _T_705 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_713 = _T_708 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_714 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_715 = _T_711 | _T_712; // @[Mux.scala 27:72] + wire [2:0] _T_716 = _T_715 | _T_713; // @[Mux.scala 27:72] + wire [2:0] dcsr_cause = _T_716 | _T_714; // @[Mux.scala 27:72] + wire _T_718 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2084:53] + wire _T_720 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2084:105] + wire wr_dcsr_r = _T_718 & _T_720; // @[dec_tlu_ctl.scala 2084:76] + wire _T_722 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2090:82] + wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_722; // @[dec_tlu_ctl.scala 2090:66] + wire _T_723 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2091:66] + wire _T_724 = _T_723 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2091:85] + wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_724; // @[dec_tlu_ctl.scala 2091:63] + wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 2093:55] + wire [15:0] _T_730 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] + wire _T_736 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2095:158] + wire [15:0] _T_745 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_736,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] + wire [15:0] _T_750 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] + wire _T_752 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2098:61] + wire _T_753 = _T_752 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2098:73] + wire _T_754 = _T_753 | io_take_nmi; // @[dec_tlu_ctl.scala 2098:101] + reg [15:0] _T_756; // @[Reg.scala 27:20] + wire _T_759 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2106:104] + wire wr_dpc_r = _T_718 & _T_759; // @[dec_tlu_ctl.scala 2106:75] + wire _T_762 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2107:74] + wire dpc_capture_npc = _T_645 & _T_762; // @[dec_tlu_ctl.scala 2107:72] + wire _T_763 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2111:18] + wire _T_764 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2111:36] + wire _T_765 = _T_763 & _T_764; // @[dec_tlu_ctl.scala 2111:34] + wire _T_766 = _T_765 & wr_dpc_r; // @[dec_tlu_ctl.scala 2111:53] + wire _T_771 = _T_763 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2113:34] + wire [30:0] _T_773 = _T_766 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_774 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_775 = _T_771 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_776 = _T_773 | _T_774; // @[Mux.scala 27:72] + wire [30:0] dpc_ns = _T_776 | _T_775; // @[Mux.scala 27:72] + wire _T_778 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2115:43] + wire _T_779 = _T_778 | dpc_capture_npc; // @[dec_tlu_ctl.scala 2115:60] + reg [30:0] _T_781; // @[Reg.scala 27:20] + wire [16:0] dicawics_ns = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20],io_dec_csr_wrdata_r[16:3]}; // @[Cat.scala 29:58] + wire _T_788 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2130:109] + wire wr_dicawics_r = _T_718 & _T_788; // @[dec_tlu_ctl.scala 2130:80] + reg [16:0] dicawics; // @[Reg.scala 27:20] + wire _T_792 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2148:107] + wire wr_dicad0_r = _T_718 & _T_792; // @[dec_tlu_ctl.scala 2148:78] + wire _T_795 = wr_dicad0_r | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2151:53] + reg [31:0] dicad0; // @[Reg.scala 27:20] + wire _T_799 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2161:108] + wire wr_dicad0h_r = _T_718 & _T_799; // @[dec_tlu_ctl.scala 2161:79] + wire _T_802 = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2165:55] + reg [31:0] dicad0h; // @[Reg.scala 27:20] + wire _T_807 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2173:115] + wire _T_808 = _T_718 & _T_807; // @[dec_tlu_ctl.scala 2173:86] + wire _T_813 = _T_808 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2177:61] + reg [6:0] _T_815; // @[Reg.scala 27:20] + wire [31:0] dicad1 = {25'h0,_T_815}; // @[Cat.scala 29:58] + wire [38:0] _T_820 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] + wire _T_822 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2205:59] + wire _T_823 = _T_822 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2205:82] + wire _T_824 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2205:105] + wire _T_825 = _T_823 & _T_824; // @[dec_tlu_ctl.scala 2205:103] + wire _T_827 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2205:156] + wire _T_830 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2206:111] + wire _T_832 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2220:76] + wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_832; // @[dec_tlu_ctl.scala 2220:47] + reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2223:50] + wire tdata_load = io_dec_csr_wrdata_r[0] & _T_464; // @[dec_tlu_ctl.scala 2258:49] + wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_464; // @[dec_tlu_ctl.scala 2260:51] + wire _T_843 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2262:53] + wire tdata_action = _T_843 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2262:76] + wire _T_851 = io_mtdata1_t_3[9] & _T_444; // @[dec_tlu_ctl.scala 2266:91] + wire _T_852 = ~_T_851; // @[dec_tlu_ctl.scala 2266:58] + wire _T_853 = io_dec_csr_wrdata_r[11] & _T_852; // @[dec_tlu_ctl.scala 2266:56] + wire _T_858 = io_mtdata1_t_1[9] & _T_444; // @[dec_tlu_ctl.scala 2267:84] + wire _T_859 = ~_T_858; // @[dec_tlu_ctl.scala 2267:51] + wire _T_860 = io_dec_csr_wrdata_r[11] & _T_859; // @[dec_tlu_ctl.scala 2267:49] + wire _T_861 = mtsel[1] ? _T_853 : _T_860; // @[dec_tlu_ctl.scala 2266:20] + wire tdata_chain = mtsel[0] ? 1'h0 : _T_861; // @[dec_tlu_ctl.scala 2265:30] + wire _T_865 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2270:73] + wire _T_867 = _T_865 & io_mtdata1_t_2[5]; // @[dec_tlu_ctl.scala 2270:105] + wire _T_868 = io_dec_csr_wrdata_r[27] & _T_867; // @[dec_tlu_ctl.scala 2270:70] + wire _T_871 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2271:44] + wire _T_873 = _T_871 & io_mtdata1_t_0[5]; // @[dec_tlu_ctl.scala 2271:76] + wire _T_874 = io_dec_csr_wrdata_r[27] & _T_873; // @[dec_tlu_ctl.scala 2271:41] + wire tdata_kill_write = mtsel[1] ? _T_868 : _T_874; // @[dec_tlu_ctl.scala 2270:35] + wire [9:0] tdata_wrdata_r = {_T_843,io_dec_csr_wrdata_r[20:19],tdata_action,tdata_chain,io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] + wire _T_887 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2276:127] + wire _T_888 = io_dec_csr_wen_r_mod & _T_887; // @[dec_tlu_ctl.scala 2276:98] + wire _T_889 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2276:149] + wire _T_890 = _T_888 & _T_889; // @[dec_tlu_ctl.scala 2276:140] + wire _T_893 = _T_871 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2276:198] + wire wr_mtdata1_t_r_0 = _T_890 & _T_893; // @[dec_tlu_ctl.scala 2276:163] + wire _T_898 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2276:298] + wire _T_899 = _T_888 & _T_898; // @[dec_tlu_ctl.scala 2276:289] + wire _T_901 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2276:315] + wire _T_902 = _T_901 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2276:347] + wire _T_903 = _T_899 & _T_902; // @[dec_tlu_ctl.scala 2276:312] + wire _T_904 = ~tdata_kill_write; // @[dec_tlu_ctl.scala 2276:373] + wire wr_mtdata1_t_r_1 = _T_903 & _T_904; // @[dec_tlu_ctl.scala 2276:371] + wire _T_909 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2276:149] + wire _T_910 = _T_888 & _T_909; // @[dec_tlu_ctl.scala 2276:140] + wire _T_913 = _T_865 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2276:198] + wire wr_mtdata1_t_r_2 = _T_910 & _T_913; // @[dec_tlu_ctl.scala 2276:163] + wire _T_918 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2276:298] + wire _T_919 = _T_888 & _T_918; // @[dec_tlu_ctl.scala 2276:289] + wire _T_921 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2276:315] + wire _T_922 = _T_921 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2276:347] + wire _T_923 = _T_919 & _T_922; // @[dec_tlu_ctl.scala 2276:312] + wire wr_mtdata1_t_r_3 = _T_923 & _T_904; // @[dec_tlu_ctl.scala 2276:371] + wire _T_930 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2278:148] + wire [9:0] _T_933 = {io_mtdata1_t_0[9],_T_930,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] + wire _T_939 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2278:148] + wire [9:0] _T_942 = {io_mtdata1_t_1[9],_T_939,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] + wire _T_948 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2278:148] + wire [9:0] _T_951 = {io_mtdata1_t_2[9],_T_948,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] + wire _T_957 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2278:148] + wire [9:0] _T_960 = {io_mtdata1_t_3[9],_T_957,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] + wire _T_963 = io_trigger_enabled[0] | wr_mtdata1_t_r_0; // @[dec_tlu_ctl.scala 2282:95] + reg [9:0] _T_965; // @[Reg.scala 27:20] + wire _T_967 = io_trigger_enabled[1] | wr_mtdata1_t_r_1; // @[dec_tlu_ctl.scala 2282:95] + reg [9:0] _T_969; // @[Reg.scala 27:20] + wire _T_971 = io_trigger_enabled[2] | wr_mtdata1_t_r_2; // @[dec_tlu_ctl.scala 2282:95] + reg [9:0] _T_973; // @[Reg.scala 27:20] + wire _T_975 = io_trigger_enabled[3] | wr_mtdata1_t_r_3; // @[dec_tlu_ctl.scala 2282:95] + reg [9:0] _T_977; // @[Reg.scala 27:20] + wire [31:0] _T_992 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_1007 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_1022 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_1037 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_1038 = _T_889 ? _T_992 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1039 = _T_898 ? _T_1007 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1040 = _T_909 ? _T_1022 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1041 = _T_918 ? _T_1037 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1042 = _T_1038 | _T_1039; // @[Mux.scala 27:72] + wire [31:0] _T_1043 = _T_1042 | _T_1040; // @[Mux.scala 27:72] + wire [31:0] mtdata1_tsel_out = _T_1043 | _T_1041; // @[Mux.scala 27:72] + wire _T_1070 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2299:105] + wire _T_1071 = io_dec_csr_wen_r_mod & _T_1070; // @[dec_tlu_ctl.scala 2299:76] + wire _T_1073 = _T_1071 & _T_889; // @[dec_tlu_ctl.scala 2299:118] + wire wr_mtdata2_t_r_0 = _T_1073 & _T_893; // @[dec_tlu_ctl.scala 2299:141] + wire _T_1082 = _T_1071 & _T_898; // @[dec_tlu_ctl.scala 2299:118] + wire wr_mtdata2_t_r_1 = _T_1082 & _T_902; // @[dec_tlu_ctl.scala 2299:141] + wire _T_1091 = _T_1071 & _T_909; // @[dec_tlu_ctl.scala 2299:118] + wire wr_mtdata2_t_r_2 = _T_1091 & _T_913; // @[dec_tlu_ctl.scala 2299:141] + wire _T_1100 = _T_1071 & _T_918; // @[dec_tlu_ctl.scala 2299:118] + wire wr_mtdata2_t_r_3 = _T_1100 & _T_922; // @[dec_tlu_ctl.scala 2299:141] + reg [31:0] mtdata2_t_0; // @[Reg.scala 27:20] + reg [31:0] mtdata2_t_1; // @[Reg.scala 27:20] + reg [31:0] mtdata2_t_2; // @[Reg.scala 27:20] + reg [31:0] mtdata2_t_3; // @[Reg.scala 27:20] + wire [31:0] _T_1117 = _T_889 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1118 = _T_898 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1119 = _T_909 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1120 = _T_918 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1121 = _T_1117 | _T_1118; // @[Mux.scala 27:72] + wire [31:0] _T_1122 = _T_1121 | _T_1119; // @[Mux.scala 27:72] + wire [31:0] mtdata2_tsel_out = _T_1122 | _T_1120; // @[Mux.scala 27:72] + wire _T_1128 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2455:84] + wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_1128; // @[dec_tlu_ctl.scala 2455:55] + wire _T_1140 = ~io_dec_tlu_trace_disable; // @[dec_tlu_ctl.scala 2468:42] + wire _T_1143 = io_i0_exception_valid_r_d1 | perfmux_flop_io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2469:98] + wire _T_1144 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2469:158] + wire _T_1145 = io_trigger_hit_r_d1 & _T_1144; // @[dec_tlu_ctl.scala 2469:156] + wire _T_1146 = _T_1143 | _T_1145; // @[dec_tlu_ctl.scala 2469:133] + wire [4:0] _T_1150 = _T_1140 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] dec_tlu_exc_cause_wb1_raw = _T_1150 & io_exc_cause_wb; // @[dec_tlu_ctl.scala 2470:77] + wire dec_tlu_int_valid_wb1_raw = _T_1140 & io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2471:68] + reg [4:0] dec_tlu_exc_cause_wb2; // @[Reg.scala 27:20] + wire [4:0] _T_1152 = dec_tlu_exc_cause_wb1_raw ^ dec_tlu_exc_cause_wb2; // @[lib.scala 448:21] + wire _T_1153 = |_T_1152; // @[lib.scala 448:29] + reg dec_tlu_int_valid_wb2; // @[Reg.scala 27:20] + wire _T_1155 = dec_tlu_int_valid_wb1_raw ^ dec_tlu_int_valid_wb2; // @[lib.scala 470:21] + wire _T_1156 = |_T_1155; // @[lib.scala 470:29] + wire [31:0] _T_1164 = {io_core_id,4'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1173 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1178 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] + wire [31:0] _T_1191 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1204 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1216 = {io_mepc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1221 = {28'h0,mscause}; // @[Cat.scala 29:58] + wire [31:0] _T_1229 = {meivt,10'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1232 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1235 = {28'h0,meicurpl}; // @[Cat.scala 29:58] + wire [3:0] _T_1237 = perfmux_flop_io_meicidpl; // @[dec_tlu_ctl.scala 2509:97] + wire [31:0] _T_1238 = {28'h0,_T_1237}; // @[Cat.scala 29:58] + wire [31:0] _T_1241 = {28'h0,meipt}; // @[Cat.scala 29:58] + wire [31:0] _T_1244 = {22'h0,_T_376,mcgc_int[8:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_1247 = {13'h0,_T_403,3'h0,mfdc_int[12],mfdc_int[11:7],_T_407,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_1251 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] + wire [31:0] _T_1253 = {io_dpc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1269 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1272 = {30'h0,mtsel}; // @[Cat.scala 29:58] + wire [31:0] _T_1284 = perf_csrs_io_mhpmc3; // @[dec_tlu_ctl.scala 2525:77] + wire [31:0] _T_1286 = perf_csrs_io_mhpmc4; // @[dec_tlu_ctl.scala 2526:77] + wire [31:0] _T_1288 = perf_csrs_io_mhpmc5; // @[dec_tlu_ctl.scala 2527:77] + wire [31:0] _T_1290 = perf_csrs_io_mhpmc6; // @[dec_tlu_ctl.scala 2528:77] + wire [31:0] _T_1292 = perf_csrs_io_mhpmc3h; // @[dec_tlu_ctl.scala 2529:78] + wire [31:0] _T_1294 = perf_csrs_io_mhpmc4h; // @[dec_tlu_ctl.scala 2530:78] + wire [31:0] _T_1296 = perf_csrs_io_mhpmc5h; // @[dec_tlu_ctl.scala 2531:78] + wire [31:0] _T_1298 = perf_csrs_io_mhpmc6h; // @[dec_tlu_ctl.scala 2532:78] + wire [31:0] _T_1301 = {26'h0,mfdht}; // @[Cat.scala 29:58] + wire [31:0] _T_1304 = {30'h0,mfdhs}; // @[Cat.scala 29:58] + wire [9:0] _T_1306 = perf_csrs_io_mhpme3; // @[dec_tlu_ctl.scala 2535:92] + wire [31:0] _T_1307 = {22'h0,_T_1306}; // @[Cat.scala 29:58] + wire [9:0] _T_1309 = perf_csrs_io_mhpme4; // @[dec_tlu_ctl.scala 2536:92] + wire [31:0] _T_1310 = {22'h0,_T_1309}; // @[Cat.scala 29:58] + wire [9:0] _T_1312 = perf_csrs_io_mhpme5; // @[dec_tlu_ctl.scala 2537:91] + wire [31:0] _T_1313 = {22'h0,_T_1312}; // @[Cat.scala 29:58] + wire [9:0] _T_1315 = perf_csrs_io_mhpme6; // @[dec_tlu_ctl.scala 2538:91] + wire [31:0] _T_1316 = {22'h0,_T_1315}; // @[Cat.scala 29:58] + wire [31:0] _T_1319 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire [31:0] _T_1322 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1325 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1326 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1327 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1328 = io_csr_pkt_csr_mimpid ? 32'h3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1329 = io_csr_pkt_csr_mhartid ? _T_1164 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1330 = io_csr_pkt_csr_mstatus ? _T_1173 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1331 = io_csr_pkt_csr_mtvec ? _T_1178 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1332 = io_csr_pkt_csr_mip ? _T_1191 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1333 = io_csr_pkt_csr_mie ? _T_1204 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1334 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1335 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1336 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1337 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1338 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1339 = io_csr_pkt_csr_mepc ? _T_1216 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1340 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1341 = io_csr_pkt_csr_mscause ? _T_1221 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1342 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1343 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1344 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1345 = io_csr_pkt_csr_meivt ? _T_1229 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1346 = io_csr_pkt_csr_meihap ? _T_1232 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1347 = io_csr_pkt_csr_meicurpl ? _T_1235 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1348 = io_csr_pkt_csr_meicidpl ? _T_1238 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1349 = io_csr_pkt_csr_meipt ? _T_1241 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1350 = io_csr_pkt_csr_mcgc ? _T_1244 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1351 = io_csr_pkt_csr_mfdc ? _T_1247 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1352 = io_csr_pkt_csr_dcsr ? _T_1251 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1353 = io_csr_pkt_csr_dpc ? _T_1253 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1354 = io_csr_pkt_csr_dicad0 ? dicad0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1355 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1356 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1357 = io_csr_pkt_csr_dicawics ? _T_1269 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1358 = io_csr_pkt_csr_mtsel ? _T_1272 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1359 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1360 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1361 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1362 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1363 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1364 = io_csr_pkt_csr_mhpmc3 ? _T_1284 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1365 = io_csr_pkt_csr_mhpmc4 ? _T_1286 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1366 = io_csr_pkt_csr_mhpmc5 ? _T_1288 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1367 = io_csr_pkt_csr_mhpmc6 ? _T_1290 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1368 = io_csr_pkt_csr_mhpmc3h ? _T_1292 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1369 = io_csr_pkt_csr_mhpmc4h ? _T_1294 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1370 = io_csr_pkt_csr_mhpmc5h ? _T_1296 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1371 = io_csr_pkt_csr_mhpmc6h ? _T_1298 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1372 = io_csr_pkt_csr_mfdht ? _T_1301 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1373 = io_csr_pkt_csr_mfdhs ? _T_1304 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1374 = io_csr_pkt_csr_mhpme3 ? _T_1307 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1375 = io_csr_pkt_csr_mhpme4 ? _T_1310 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1376 = io_csr_pkt_csr_mhpme5 ? _T_1313 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1377 = io_csr_pkt_csr_mhpme6 ? _T_1316 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1378 = io_csr_pkt_csr_mcountinhibit ? _T_1319 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1379 = io_csr_pkt_csr_mpmc ? _T_1322 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1380 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1381 = _T_1325 | _T_1326; // @[Mux.scala 27:72] + wire [31:0] _T_1382 = _T_1381 | _T_1327; // @[Mux.scala 27:72] + wire [31:0] _T_1383 = _T_1382 | _T_1328; // @[Mux.scala 27:72] + wire [31:0] _T_1384 = _T_1383 | _T_1329; // @[Mux.scala 27:72] + wire [31:0] _T_1385 = _T_1384 | _T_1330; // @[Mux.scala 27:72] + wire [31:0] _T_1386 = _T_1385 | _T_1331; // @[Mux.scala 27:72] + wire [31:0] _T_1387 = _T_1386 | _T_1332; // @[Mux.scala 27:72] + wire [31:0] _T_1388 = _T_1387 | _T_1333; // @[Mux.scala 27:72] + wire [31:0] _T_1389 = _T_1388 | _T_1334; // @[Mux.scala 27:72] + wire [31:0] _T_1390 = _T_1389 | _T_1335; // @[Mux.scala 27:72] + wire [31:0] _T_1391 = _T_1390 | _T_1336; // @[Mux.scala 27:72] + wire [31:0] _T_1392 = _T_1391 | _T_1337; // @[Mux.scala 27:72] + wire [31:0] _T_1393 = _T_1392 | _T_1338; // @[Mux.scala 27:72] + wire [31:0] _T_1394 = _T_1393 | _T_1339; // @[Mux.scala 27:72] + wire [31:0] _T_1395 = _T_1394 | _T_1340; // @[Mux.scala 27:72] + wire [31:0] _T_1396 = _T_1395 | _T_1341; // @[Mux.scala 27:72] + wire [31:0] _T_1397 = _T_1396 | _T_1342; // @[Mux.scala 27:72] + wire [31:0] _T_1398 = _T_1397 | _T_1343; // @[Mux.scala 27:72] + wire [31:0] _T_1399 = _T_1398 | _T_1344; // @[Mux.scala 27:72] + wire [31:0] _T_1400 = _T_1399 | _T_1345; // @[Mux.scala 27:72] + wire [31:0] _T_1401 = _T_1400 | _T_1346; // @[Mux.scala 27:72] + wire [31:0] _T_1402 = _T_1401 | _T_1347; // @[Mux.scala 27:72] + wire [31:0] _T_1403 = _T_1402 | _T_1348; // @[Mux.scala 27:72] + wire [31:0] _T_1404 = _T_1403 | _T_1349; // @[Mux.scala 27:72] + wire [31:0] _T_1405 = _T_1404 | _T_1350; // @[Mux.scala 27:72] + wire [31:0] _T_1406 = _T_1405 | _T_1351; // @[Mux.scala 27:72] + wire [31:0] _T_1407 = _T_1406 | _T_1352; // @[Mux.scala 27:72] + wire [31:0] _T_1408 = _T_1407 | _T_1353; // @[Mux.scala 27:72] + wire [31:0] _T_1409 = _T_1408 | _T_1354; // @[Mux.scala 27:72] + wire [31:0] _T_1410 = _T_1409 | _T_1355; // @[Mux.scala 27:72] + wire [31:0] _T_1411 = _T_1410 | _T_1356; // @[Mux.scala 27:72] + wire [31:0] _T_1412 = _T_1411 | _T_1357; // @[Mux.scala 27:72] + wire [31:0] _T_1413 = _T_1412 | _T_1358; // @[Mux.scala 27:72] + wire [31:0] _T_1414 = _T_1413 | _T_1359; // @[Mux.scala 27:72] + wire [31:0] _T_1415 = _T_1414 | _T_1360; // @[Mux.scala 27:72] + wire [31:0] _T_1416 = _T_1415 | _T_1361; // @[Mux.scala 27:72] + wire [31:0] _T_1417 = _T_1416 | _T_1362; // @[Mux.scala 27:72] + wire [31:0] _T_1418 = _T_1417 | _T_1363; // @[Mux.scala 27:72] + wire [31:0] _T_1419 = _T_1418 | _T_1364; // @[Mux.scala 27:72] + wire [31:0] _T_1420 = _T_1419 | _T_1365; // @[Mux.scala 27:72] + wire [31:0] _T_1421 = _T_1420 | _T_1366; // @[Mux.scala 27:72] + wire [31:0] _T_1422 = _T_1421 | _T_1367; // @[Mux.scala 27:72] + wire [31:0] _T_1423 = _T_1422 | _T_1368; // @[Mux.scala 27:72] + wire [31:0] _T_1424 = _T_1423 | _T_1369; // @[Mux.scala 27:72] + wire [31:0] _T_1425 = _T_1424 | _T_1370; // @[Mux.scala 27:72] + wire [31:0] _T_1426 = _T_1425 | _T_1371; // @[Mux.scala 27:72] + wire [31:0] _T_1427 = _T_1426 | _T_1372; // @[Mux.scala 27:72] + wire [31:0] _T_1428 = _T_1427 | _T_1373; // @[Mux.scala 27:72] + wire [31:0] _T_1429 = _T_1428 | _T_1374; // @[Mux.scala 27:72] + wire [31:0] _T_1430 = _T_1429 | _T_1375; // @[Mux.scala 27:72] + wire [31:0] _T_1431 = _T_1430 | _T_1376; // @[Mux.scala 27:72] + wire [31:0] _T_1432 = _T_1431 | _T_1377; // @[Mux.scala 27:72] + wire [31:0] _T_1433 = _T_1432 | _T_1378; // @[Mux.scala 27:72] + wire [31:0] _T_1434 = _T_1433 | _T_1379; // @[Mux.scala 27:72] + perf_mux_and_flops perfmux_flop ( // @[dec_tlu_ctl.scala 1455:34] + .reset(perfmux_flop_reset), + .io_mhpmc_inc_r_0(perfmux_flop_io_mhpmc_inc_r_0), + .io_mhpmc_inc_r_1(perfmux_flop_io_mhpmc_inc_r_1), + .io_mhpmc_inc_r_2(perfmux_flop_io_mhpmc_inc_r_2), + .io_mhpmc_inc_r_3(perfmux_flop_io_mhpmc_inc_r_3), + .io_mcountinhibit(perfmux_flop_io_mcountinhibit), + .io_mhpme_vec_0(perfmux_flop_io_mhpme_vec_0), + .io_mhpme_vec_1(perfmux_flop_io_mhpme_vec_1), + .io_mhpme_vec_2(perfmux_flop_io_mhpme_vec_2), + .io_mhpme_vec_3(perfmux_flop_io_mhpme_vec_3), + .io_ifu_pmu_ic_hit(perfmux_flop_io_ifu_pmu_ic_hit), + .io_ifu_pmu_ic_miss(perfmux_flop_io_ifu_pmu_ic_miss), + .io_tlu_i0_commit_cmt(perfmux_flop_io_tlu_i0_commit_cmt), + .io_illegal_r(perfmux_flop_io_illegal_r), + .io_exu_pmu_i0_pc4(perfmux_flop_io_exu_pmu_i0_pc4), + .io_ifu_pmu_instr_aligned(perfmux_flop_io_ifu_pmu_instr_aligned), + .io_dec_pmu_instr_decoded(perfmux_flop_io_dec_pmu_instr_decoded), + .io_dec_tlu_packet_r_pmu_i0_itype(perfmux_flop_io_dec_tlu_packet_r_pmu_i0_itype), + .io_dec_tlu_packet_r_pmu_i0_br_unpred(perfmux_flop_io_dec_tlu_packet_r_pmu_i0_br_unpred), + .io_dec_tlu_packet_r_pmu_divide(perfmux_flop_io_dec_tlu_packet_r_pmu_divide), + .io_dec_tlu_packet_r_pmu_lsu_misaligned(perfmux_flop_io_dec_tlu_packet_r_pmu_lsu_misaligned), + .io_exu_pmu_i0_br_misp(perfmux_flop_io_exu_pmu_i0_br_misp), + .io_dec_pmu_decode_stall(perfmux_flop_io_dec_pmu_decode_stall), + .io_exu_pmu_i0_br_ataken(perfmux_flop_io_exu_pmu_i0_br_ataken), + .io_ifu_pmu_fetch_stall(perfmux_flop_io_ifu_pmu_fetch_stall), + .io_dec_pmu_postsync_stall(perfmux_flop_io_dec_pmu_postsync_stall), + .io_dec_pmu_presync_stall(perfmux_flop_io_dec_pmu_presync_stall), + .io_lsu_store_stall_any(perfmux_flop_io_lsu_store_stall_any), + .io_dma_dccm_stall_any(perfmux_flop_io_dma_dccm_stall_any), + .io_dma_iccm_stall_any(perfmux_flop_io_dma_iccm_stall_any), + .io_i0_exception_valid_r(perfmux_flop_io_i0_exception_valid_r), + .io_dec_tlu_pmu_fw_halted(perfmux_flop_io_dec_tlu_pmu_fw_halted), + .io_dma_pmu_any_read(perfmux_flop_io_dma_pmu_any_read), + .io_dma_pmu_any_write(perfmux_flop_io_dma_pmu_any_write), + .io_dma_pmu_dccm_read(perfmux_flop_io_dma_pmu_dccm_read), + .io_dma_pmu_dccm_write(perfmux_flop_io_dma_pmu_dccm_write), + .io_lsu_pmu_load_external_r(perfmux_flop_io_lsu_pmu_load_external_r), + .io_lsu_pmu_store_external_r(perfmux_flop_io_lsu_pmu_store_external_r), + .io_mstatus(perfmux_flop_io_mstatus), + .io_mie(perfmux_flop_io_mie), + .io_ifu_pmu_bus_trxn(perfmux_flop_io_ifu_pmu_bus_trxn), + .io_lsu_pmu_bus_trxn(perfmux_flop_io_lsu_pmu_bus_trxn), + .io_lsu_pmu_bus_misaligned(perfmux_flop_io_lsu_pmu_bus_misaligned), + .io_ifu_pmu_bus_error(perfmux_flop_io_ifu_pmu_bus_error), + .io_lsu_pmu_bus_error(perfmux_flop_io_lsu_pmu_bus_error), + .io_ifu_pmu_bus_busy(perfmux_flop_io_ifu_pmu_bus_busy), + .io_lsu_pmu_bus_busy(perfmux_flop_io_lsu_pmu_bus_busy), + .io_i0_trigger_hit_r(perfmux_flop_io_i0_trigger_hit_r), + .io_lsu_exc_valid_r(perfmux_flop_io_lsu_exc_valid_r), + .io_take_timer_int(perfmux_flop_io_take_timer_int), + .io_take_int_timer0_int(perfmux_flop_io_take_int_timer0_int), + .io_take_int_timer1_int(perfmux_flop_io_take_int_timer1_int), + .io_take_ext_int(perfmux_flop_io_take_ext_int), + .io_tlu_flush_lower_r(perfmux_flop_io_tlu_flush_lower_r), + .io_dec_tlu_br0_error_r(perfmux_flop_io_dec_tlu_br0_error_r), + .io_rfpc_i0_r(perfmux_flop_io_rfpc_i0_r), + .io_dec_tlu_br0_start_error_r(perfmux_flop_io_dec_tlu_br0_start_error_r), + .io_mcyclel_cout_f(perfmux_flop_io_mcyclel_cout_f), + .io_minstret_enable_f(perfmux_flop_io_minstret_enable_f), + .io_minstretl_cout_f(perfmux_flop_io_minstretl_cout_f), + .io_meicidpl(perfmux_flop_io_meicidpl), + .io_icache_rd_valid_f(perfmux_flop_io_icache_rd_valid_f), + .io_icache_wr_valid_f(perfmux_flop_io_icache_wr_valid_f), + .io_mhpmc_inc_r_d1_0(perfmux_flop_io_mhpmc_inc_r_d1_0), + .io_mhpmc_inc_r_d1_1(perfmux_flop_io_mhpmc_inc_r_d1_1), + .io_mhpmc_inc_r_d1_2(perfmux_flop_io_mhpmc_inc_r_d1_2), + .io_mhpmc_inc_r_d1_3(perfmux_flop_io_mhpmc_inc_r_d1_3), + .io_perfcnt_halted_d1(perfmux_flop_io_perfcnt_halted_d1), + .io_mdseac_locked_f(perfmux_flop_io_mdseac_locked_f), + .io_lsu_single_ecc_error_r_d1(perfmux_flop_io_lsu_single_ecc_error_r_d1), + .io_lsu_i0_exc_r_d1(perfmux_flop_io_lsu_i0_exc_r_d1), + .io_take_ext_int_start_d1(perfmux_flop_io_take_ext_int_start_d1), + .io_take_ext_int_start_d2(perfmux_flop_io_take_ext_int_start_d2), + .io_take_ext_int_start_d3(perfmux_flop_io_take_ext_int_start_d3), + .io_ext_int_freeze_d1(perfmux_flop_io_ext_int_freeze_d1), + .io_mip(perfmux_flop_io_mip), + .io_mdseac_locked_ns(perfmux_flop_io_mdseac_locked_ns), + .io_lsu_single_ecc_error_r(perfmux_flop_io_lsu_single_ecc_error_r), + .io_lsu_i0_exc_r(perfmux_flop_io_lsu_i0_exc_r), + .io_take_ext_int_start(perfmux_flop_io_take_ext_int_start), + .io_ext_int_freeze(perfmux_flop_io_ext_int_freeze), + .io_mip_ns(perfmux_flop_io_mip_ns), + .io_mcyclel_cout(perfmux_flop_io_mcyclel_cout), + .io_wr_mcycleh_r(perfmux_flop_io_wr_mcycleh_r), + .io_mcyclel_cout_in(perfmux_flop_io_mcyclel_cout_in), + .io_minstret_enable(perfmux_flop_io_minstret_enable), + .io_minstretl_cout_ns(perfmux_flop_io_minstretl_cout_ns), + .io_meicidpl_ns(perfmux_flop_io_meicidpl_ns), + .io_icache_rd_valid(perfmux_flop_io_icache_rd_valid), + .io_icache_wr_valid(perfmux_flop_io_icache_wr_valid), + .io_perfcnt_halted(perfmux_flop_io_perfcnt_halted), + .io_mstatus_ns(perfmux_flop_io_mstatus_ns), + .io_free_l2clk(perfmux_flop_io_free_l2clk) + ); + perf_csr perf_csrs ( // @[dec_tlu_ctl.scala 1456:31] + .clock(perf_csrs_clock), + .reset(perf_csrs_reset), + .io_free_l2clk(perf_csrs_io_free_l2clk), + .io_dec_tlu_dbg_halted(perf_csrs_io_dec_tlu_dbg_halted), + .io_dcsr(perf_csrs_io_dcsr), + .io_dec_tlu_pmu_fw_halted(perf_csrs_io_dec_tlu_pmu_fw_halted), + .io_mhpme_vec_0(perf_csrs_io_mhpme_vec_0), + .io_mhpme_vec_1(perf_csrs_io_mhpme_vec_1), + .io_mhpme_vec_2(perf_csrs_io_mhpme_vec_2), + .io_mhpme_vec_3(perf_csrs_io_mhpme_vec_3), + .io_dec_csr_wen_r_mod(perf_csrs_io_dec_csr_wen_r_mod), + .io_dec_csr_wraddr_r(perf_csrs_io_dec_csr_wraddr_r), + .io_dec_csr_wrdata_r(perf_csrs_io_dec_csr_wrdata_r), + .io_mhpmc_inc_r_0(perf_csrs_io_mhpmc_inc_r_0), + .io_mhpmc_inc_r_1(perf_csrs_io_mhpmc_inc_r_1), + .io_mhpmc_inc_r_2(perf_csrs_io_mhpmc_inc_r_2), + .io_mhpmc_inc_r_3(perf_csrs_io_mhpmc_inc_r_3), + .io_mhpmc_inc_r_d1_0(perf_csrs_io_mhpmc_inc_r_d1_0), + .io_mhpmc_inc_r_d1_1(perf_csrs_io_mhpmc_inc_r_d1_1), + .io_mhpmc_inc_r_d1_2(perf_csrs_io_mhpmc_inc_r_d1_2), + .io_mhpmc_inc_r_d1_3(perf_csrs_io_mhpmc_inc_r_d1_3), + .io_perfcnt_halted_d1(perf_csrs_io_perfcnt_halted_d1), + .io_mhpmc3h(perf_csrs_io_mhpmc3h), + .io_mhpmc3(perf_csrs_io_mhpmc3), + .io_mhpmc4h(perf_csrs_io_mhpmc4h), + .io_mhpmc4(perf_csrs_io_mhpmc4), + .io_mhpmc5h(perf_csrs_io_mhpmc5h), + .io_mhpmc5(perf_csrs_io_mhpmc5), + .io_mhpmc6h(perf_csrs_io_mhpmc6h), + .io_mhpmc6(perf_csrs_io_mhpmc6), + .io_mhpme3(perf_csrs_io_mhpme3), + .io_mhpme4(perf_csrs_io_mhpme4), + .io_mhpme5(perf_csrs_io_mhpme5), + .io_mhpme6(perf_csrs_io_mhpme6), + .io_dec_tlu_perfcnt0(perf_csrs_io_dec_tlu_perfcnt0), + .io_dec_tlu_perfcnt1(perf_csrs_io_dec_tlu_perfcnt1), + .io_dec_tlu_perfcnt2(perf_csrs_io_dec_tlu_perfcnt2), + .io_dec_tlu_perfcnt3(perf_csrs_io_dec_tlu_perfcnt3) + ); + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en) + ); + rvclkhdr rvclkhdr_10 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en) + ); + rvclkhdr rvclkhdr_11 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en) + ); + rvclkhdr rvclkhdr_12 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_12_io_clk), + .io_en(rvclkhdr_12_io_en) + ); + rvclkhdr rvclkhdr_13 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_13_io_clk), + .io_en(rvclkhdr_13_io_en) + ); + rvclkhdr rvclkhdr_14 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_14_io_clk), + .io_en(rvclkhdr_14_io_en) + ); + rvclkhdr rvclkhdr_15 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_15_io_clk), + .io_en(rvclkhdr_15_io_en) + ); + rvclkhdr rvclkhdr_16 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_16_io_clk), + .io_en(rvclkhdr_16_io_en) + ); + rvclkhdr rvclkhdr_17 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_17_io_clk), + .io_en(rvclkhdr_17_io_en) + ); + rvclkhdr rvclkhdr_18 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_18_io_clk), + .io_en(rvclkhdr_18_io_en) + ); + rvclkhdr rvclkhdr_19 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_19_io_clk), + .io_en(rvclkhdr_19_io_en) + ); + rvclkhdr rvclkhdr_20 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_20_io_clk), + .io_en(rvclkhdr_20_io_en) + ); + rvclkhdr rvclkhdr_21 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_21_io_clk), + .io_en(rvclkhdr_21_io_en) + ); + rvclkhdr rvclkhdr_22 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_22_io_clk), + .io_en(rvclkhdr_22_io_en) + ); + rvclkhdr rvclkhdr_23 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_23_io_clk), + .io_en(rvclkhdr_23_io_en) + ); + rvclkhdr rvclkhdr_24 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_24_io_clk), + .io_en(rvclkhdr_24_io_en) + ); + rvclkhdr rvclkhdr_25 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_25_io_clk), + .io_en(rvclkhdr_25_io_en) + ); + rvclkhdr rvclkhdr_26 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_26_io_clk), + .io_en(rvclkhdr_26_io_en) + ); + rvclkhdr rvclkhdr_27 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_27_io_clk), + .io_en(rvclkhdr_27_io_en) + ); + rvclkhdr rvclkhdr_28 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_28_io_clk), + .io_en(rvclkhdr_28_io_en) + ); + rvclkhdr rvclkhdr_29 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_29_io_clk), + .io_en(rvclkhdr_29_io_en) + ); + rvclkhdr rvclkhdr_30 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_30_io_clk), + .io_en(rvclkhdr_30_io_en) + ); + rvclkhdr rvclkhdr_31 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_31_io_clk), + .io_en(rvclkhdr_31_io_en) + ); + rvclkhdr rvclkhdr_32 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_32_io_clk), + .io_en(rvclkhdr_32_io_en) + ); + rvclkhdr rvclkhdr_33 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_33_io_clk), + .io_en(rvclkhdr_33_io_en) + ); + rvclkhdr rvclkhdr_34 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_34_io_clk), + .io_en(rvclkhdr_34_io_en) + ); + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_820,dicad0}; // @[dec_tlu_ctl.scala 2200:63] + assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2203:48] + assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = perfmux_flop_io_icache_rd_valid_f; // @[dec_tlu_ctl.scala 2211:48] + assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = perfmux_flop_io_icache_wr_valid_f; // @[dec_tlu_ctl.scala 2212:48] + assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[dec_tlu_ctl.scala 2287:48] + assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[dec_tlu_ctl.scala 2288:51] + assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[dec_tlu_ctl.scala 2289:48] + assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[dec_tlu_ctl.scala 2290:48] + assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[dec_tlu_ctl.scala 2291:48] + assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 2292:48] + assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[dec_tlu_ctl.scala 2305:59] + assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[dec_tlu_ctl.scala 2287:48] + assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[dec_tlu_ctl.scala 2288:51] + assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[dec_tlu_ctl.scala 2289:48] + assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[dec_tlu_ctl.scala 2290:48] + assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[dec_tlu_ctl.scala 2291:48] + assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 2292:48] + assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[dec_tlu_ctl.scala 2305:59] + assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[dec_tlu_ctl.scala 2287:48] + assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[dec_tlu_ctl.scala 2288:51] + assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[dec_tlu_ctl.scala 2289:48] + assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[dec_tlu_ctl.scala 2290:48] + assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[dec_tlu_ctl.scala 2291:48] + assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 2292:48] + assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[dec_tlu_ctl.scala 2305:59] + assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[dec_tlu_ctl.scala 2287:48] + assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[dec_tlu_ctl.scala 2288:51] + assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[dec_tlu_ctl.scala 2289:48] + assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[dec_tlu_ctl.scala 2290:48] + assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2291:48] + assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2292:48] + assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2305:59] + assign io_dec_tlu_int_valid_wb1 = dec_tlu_int_valid_wb2; // @[dec_tlu_ctl.scala 2478:34] + assign io_dec_tlu_i0_exc_valid_wb1 = _T_1140 & _T_1146; // @[dec_tlu_ctl.scala 2469:39] + assign io_dec_tlu_i0_valid_wb1 = _T_1140 & io_i0_valid_wb; // @[dec_tlu_ctl.scala 2468:39] + assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2479:31] + assign io_dec_tlu_exc_cause_wb1 = dec_tlu_int_valid_wb2 ? dec_tlu_exc_cause_wb2 : dec_tlu_exc_cause_wb1_raw; // @[dec_tlu_ctl.scala 2477:34] + assign io_dec_tlu_perfcnt0 = perf_csrs_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 2436:29] + assign io_dec_tlu_perfcnt1 = perf_csrs_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 2437:29] + assign io_dec_tlu_perfcnt2 = perf_csrs_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 2438:29] + assign io_dec_tlu_perfcnt3 = perf_csrs_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 2439:29] + assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1757:38] + assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1758:38] + assign io_dec_tlu_ifu_clk_override = mcgc[5]; // @[dec_tlu_ctl.scala 1759:38] + assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1760:38] + assign io_dec_tlu_bus_clk_override = mcgc[3]; // @[dec_tlu_ctl.scala 1761:38] + assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1762:38] + assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1763:38] + assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1764:38] + assign io_dec_csr_rddata_d = _T_1434 | _T_1380; // @[dec_tlu_ctl.scala 2485:28] + assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1813:46] + assign io_dec_tlu_wr_pause_r = _T_426 & _T_427; // @[dec_tlu_ctl.scala 1822:31] + assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 2050:26] + assign io_dec_tlu_meicurpl = meicurpl; // @[dec_tlu_ctl.scala 2014:29] + assign io_dec_tlu_meihap = {meivt,meihap}; // @[dec_tlu_ctl.scala 2000:27] + assign io_dec_tlu_mrac_ff = mrac; // @[dec_tlu_ctl.scala 1852:28] + assign io_dec_tlu_wb_coalescing_disable = mfdc[2]; // @[dec_tlu_ctl.scala 1812:46] + assign io_dec_tlu_bpred_disable = mfdc[3]; // @[dec_tlu_ctl.scala 1811:46] + assign io_dec_tlu_sideeffect_posted_disable = mfdc[6]; // @[dec_tlu_ctl.scala 1810:46] + assign io_dec_tlu_core_ecc_disable = mfdc[8]; // @[dec_tlu_ctl.scala 1809:46] + assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[dec_tlu_ctl.scala 1808:46] + assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[dec_tlu_ctl.scala 1806:46] + assign io_dec_tlu_trace_disable = mfdc[12]; // @[dec_tlu_ctl.scala 1807:46] + assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[dec_tlu_ctl.scala 1472:30] + assign io_fw_halt_req = _T_557 & _T_558; // @[dec_tlu_ctl.scala 1887:24] + assign io_mstatus = perfmux_flop_io_mstatus; // @[dec_tlu_ctl.scala 2348:26] + assign io_mstatus_mie_ns = io_mstatus[0] & _T_54; // @[dec_tlu_ctl.scala 1489:27] + assign io_dcsr = _T_756; // @[dec_tlu_ctl.scala 2098:17] + assign io_mtvec = _T_61; // @[dec_tlu_ctl.scala 1502:18] + assign io_mip = perfmux_flop_io_mip; // @[dec_tlu_ctl.scala 2349:18] + assign io_mie_ns = wr_mie_r ? _T_76 : mie; // @[dec_tlu_ctl.scala 1531:19] + assign io_npc_r = _T_189 | _T_187; // @[dec_tlu_ctl.scala 1635:18] + assign io_npc_r_d1 = _T_196; // @[dec_tlu_ctl.scala 1641:21] + assign io_mepc = _T_231; // @[dec_tlu_ctl.scala 1660:17] + assign io_mdseac_locked_ns = mdseac_en | _T_545; // @[dec_tlu_ctl.scala 1870:29] + assign io_mdseac_locked_f = perfmux_flop_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 2378:42] + assign io_ext_int_freeze_d1 = perfmux_flop_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 2385:42] + assign io_take_ext_int_start_d1 = perfmux_flop_io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 2382:42] + assign io_take_ext_int_start_d2 = perfmux_flop_io_take_ext_int_start_d2; // @[dec_tlu_ctl.scala 2383:42] + assign io_take_ext_int_start_d3 = perfmux_flop_io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 2384:42] + assign io_force_halt = mfdht[0] & _T_665; // @[dec_tlu_ctl.scala 1977:23] + assign io_dpc = _T_781; // @[dec_tlu_ctl.scala 2115:16] + assign io_mtdata1_t_0 = _T_965; // @[dec_tlu_ctl.scala 2282:47] + assign io_mtdata1_t_1 = _T_969; // @[dec_tlu_ctl.scala 2282:47] + assign io_mtdata1_t_2 = _T_973; // @[dec_tlu_ctl.scala 2282:47] + assign io_mtdata1_t_3 = _T_977; // @[dec_tlu_ctl.scala 2282:47] + assign perfmux_flop_reset = reset; + assign perfmux_flop_io_mcountinhibit = {_T_1138,temp_ncount0}; // @[dec_tlu_ctl.scala 2321:57] + assign perfmux_flop_io_mhpme_vec_0 = perf_csrs_io_mhpme3; // @[dec_tlu_ctl.scala 2322:57] + assign perfmux_flop_io_mhpme_vec_1 = perf_csrs_io_mhpme4; // @[dec_tlu_ctl.scala 2322:57] + assign perfmux_flop_io_mhpme_vec_2 = perf_csrs_io_mhpme5; // @[dec_tlu_ctl.scala 2322:57] + assign perfmux_flop_io_mhpme_vec_3 = perf_csrs_io_mhpme6; // @[dec_tlu_ctl.scala 2322:57] + assign perfmux_flop_io_ifu_pmu_ic_hit = io_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 2323:57] + assign perfmux_flop_io_ifu_pmu_ic_miss = io_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 2324:57] + assign perfmux_flop_io_tlu_i0_commit_cmt = io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2325:57] + assign perfmux_flop_io_illegal_r = io_illegal_r; // @[dec_tlu_ctl.scala 2326:57] + assign perfmux_flop_io_exu_pmu_i0_pc4 = io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2327:57] + assign perfmux_flop_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 2328:57] + assign perfmux_flop_io_dec_pmu_instr_decoded = io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 2329:57] + assign perfmux_flop_io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 2330:57] + assign perfmux_flop_io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 2330:57] + assign perfmux_flop_io_dec_tlu_packet_r_pmu_divide = io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 2330:57] + assign perfmux_flop_io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2330:57] + assign perfmux_flop_io_exu_pmu_i0_br_misp = io_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 2331:57] + assign perfmux_flop_io_dec_pmu_decode_stall = io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 2332:57] + assign perfmux_flop_io_exu_pmu_i0_br_ataken = io_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 2333:57] + assign perfmux_flop_io_ifu_pmu_fetch_stall = io_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 2334:57] + assign perfmux_flop_io_dec_pmu_postsync_stall = io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 2335:57] + assign perfmux_flop_io_dec_pmu_presync_stall = io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 2336:57] + assign perfmux_flop_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 2337:57] + assign perfmux_flop_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 2338:57] + assign perfmux_flop_io_dma_iccm_stall_any = io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 2339:57] + assign perfmux_flop_io_i0_exception_valid_r = io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 2340:57] + assign perfmux_flop_io_dec_tlu_pmu_fw_halted = io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2341:57] + assign perfmux_flop_io_dma_pmu_any_read = io_dma_pmu_any_read; // @[dec_tlu_ctl.scala 2342:57] + assign perfmux_flop_io_dma_pmu_any_write = io_dma_pmu_any_write; // @[dec_tlu_ctl.scala 2343:57] + assign perfmux_flop_io_dma_pmu_dccm_read = io_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 2344:57] + assign perfmux_flop_io_dma_pmu_dccm_write = io_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 2345:57] + assign perfmux_flop_io_lsu_pmu_load_external_r = io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2346:57] + assign perfmux_flop_io_lsu_pmu_store_external_r = io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2347:57] + assign perfmux_flop_io_mie = mie; // @[dec_tlu_ctl.scala 2350:57] + assign perfmux_flop_io_ifu_pmu_bus_trxn = io_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 2351:57] + assign perfmux_flop_io_lsu_pmu_bus_trxn = io_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 2352:57] + assign perfmux_flop_io_lsu_pmu_bus_misaligned = io_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 2353:57] + assign perfmux_flop_io_ifu_pmu_bus_error = io_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 2354:57] + assign perfmux_flop_io_lsu_pmu_bus_error = io_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 2355:57] + assign perfmux_flop_io_ifu_pmu_bus_busy = io_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 2356:57] + assign perfmux_flop_io_lsu_pmu_bus_busy = io_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 2357:57] + assign perfmux_flop_io_i0_trigger_hit_r = io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2358:57] + assign perfmux_flop_io_lsu_exc_valid_r = io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2359:57] + assign perfmux_flop_io_take_timer_int = io_take_timer_int; // @[dec_tlu_ctl.scala 2360:57] + assign perfmux_flop_io_take_int_timer0_int = io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2361:57] + assign perfmux_flop_io_take_int_timer1_int = io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2362:57] + assign perfmux_flop_io_take_ext_int = io_take_ext_int; // @[dec_tlu_ctl.scala 2363:57] + assign perfmux_flop_io_tlu_flush_lower_r = io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 2364:57] + assign perfmux_flop_io_dec_tlu_br0_error_r = io_dec_tlu_br0_error_r; // @[dec_tlu_ctl.scala 2365:57] + assign perfmux_flop_io_rfpc_i0_r = io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2366:57] + assign perfmux_flop_io_dec_tlu_br0_start_error_r = io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2367:57] + assign perfmux_flop_io_mdseac_locked_ns = io_mdseac_locked_ns; // @[dec_tlu_ctl.scala 2389:55] + assign perfmux_flop_io_lsu_single_ecc_error_r = io_lsu_single_ecc_error_r; // @[dec_tlu_ctl.scala 2390:55] + assign perfmux_flop_io_lsu_i0_exc_r = io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 2391:55] + assign perfmux_flop_io_take_ext_int_start = io_take_ext_int_start; // @[dec_tlu_ctl.scala 2392:55] + assign perfmux_flop_io_ext_int_freeze = io_ext_int_freeze; // @[dec_tlu_ctl.scala 2393:55] + assign perfmux_flop_io_mip_ns = {_T_66,_T_64}; // @[dec_tlu_ctl.scala 2394:55] + assign perfmux_flop_io_mcyclel_cout = mcyclel_inc2[24]; // @[dec_tlu_ctl.scala 2395:55] + assign perfmux_flop_io_wr_mcycleh_r = io_dec_csr_wen_r_mod & _T_113; // @[dec_tlu_ctl.scala 2396:55] + assign perfmux_flop_io_mcyclel_cout_in = ~_T_87; // @[dec_tlu_ctl.scala 2397:55] + assign perfmux_flop_io_minstret_enable = _T_138 | wr_minstretl_r; // @[dec_tlu_ctl.scala 2398:55] + assign perfmux_flop_io_minstretl_cout_ns = _T_141 & _T_142; // @[dec_tlu_ctl.scala 2399:55] + assign perfmux_flop_io_meicidpl_ns = wr_meicpct_r ? io_pic_pl : _T_684; // @[dec_tlu_ctl.scala 2401:55] + assign perfmux_flop_io_icache_rd_valid = _T_825 & _T_827; // @[dec_tlu_ctl.scala 2402:55] + assign perfmux_flop_io_icache_wr_valid = _T_718 & _T_830; // @[dec_tlu_ctl.scala 2403:55] + assign perfmux_flop_io_perfcnt_halted = _T_83 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2404:55] + assign perfmux_flop_io_mstatus_ns = _T_48 | _T_44; // @[dec_tlu_ctl.scala 2405:55] + assign perfmux_flop_io_free_l2clk = io_free_l2clk; // @[dec_tlu_ctl.scala 2407:56] + assign perf_csrs_clock = clock; + assign perf_csrs_reset = reset; + assign perf_csrs_io_free_l2clk = io_free_l2clk; // @[dec_tlu_ctl.scala 2411:50] + assign perf_csrs_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 2413:50] + assign perf_csrs_io_dcsr = io_dcsr; // @[dec_tlu_ctl.scala 2414:50] + assign perf_csrs_io_dec_tlu_pmu_fw_halted = io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2415:50] + assign perf_csrs_io_mhpme_vec_0 = perf_csrs_io_mhpme3; // @[dec_tlu_ctl.scala 2416:50] + assign perf_csrs_io_mhpme_vec_1 = perf_csrs_io_mhpme4; // @[dec_tlu_ctl.scala 2416:50] + assign perf_csrs_io_mhpme_vec_2 = perf_csrs_io_mhpme5; // @[dec_tlu_ctl.scala 2416:50] + assign perf_csrs_io_mhpme_vec_3 = perf_csrs_io_mhpme6; // @[dec_tlu_ctl.scala 2416:50] + assign perf_csrs_io_dec_csr_wen_r_mod = io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2417:50] + assign perf_csrs_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 2418:50] + assign perf_csrs_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 2419:50] + assign perf_csrs_io_mhpmc_inc_r_0 = perfmux_flop_io_mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2420:50] + assign perf_csrs_io_mhpmc_inc_r_1 = perfmux_flop_io_mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2420:50] + assign perf_csrs_io_mhpmc_inc_r_2 = perfmux_flop_io_mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2420:50] + assign perf_csrs_io_mhpmc_inc_r_3 = perfmux_flop_io_mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2420:50] + assign perf_csrs_io_mhpmc_inc_r_d1_0 = perfmux_flop_io_mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2421:50] + assign perf_csrs_io_mhpmc_inc_r_d1_1 = perfmux_flop_io_mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2421:50] + assign perf_csrs_io_mhpmc_inc_r_d1_2 = perfmux_flop_io_mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2421:50] + assign perf_csrs_io_mhpmc_inc_r_d1_3 = perfmux_flop_io_mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2421:50] + assign perf_csrs_io_perfcnt_halted_d1 = perfmux_flop_io_perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2422:50] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_57; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = wr_mcyclel_r | _T_102; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = wr_mcyclel_r | mcyclel_cout_in; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = wr_mcycleh_r | perfmux_flop_io_mcyclel_cout_f; // @[lib.scala 407:17] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_4_io_en = wr_minstretl_r | _T_147; // @[lib.scala 407:17] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_5_io_en = _T_138 | wr_minstretl_r; // @[lib.scala 407:17] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_6_io_en = _T_162 | wr_minstreth_r; // @[lib.scala 407:17] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_7_io_en = io_dec_csr_wen_r_mod & _T_167; // @[lib.scala 407:17] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_8_io_en = _T_228 | wr_mepc_r; // @[lib.scala 407:17] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_9_io_en = io_exc_or_int_valid_r | wr_mcause_r; // @[lib.scala 407:17] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_10_io_en = io_tlu_flush_lower_r | wr_mtval_r; // @[lib.scala 407:17] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_11_io_en = io_dec_csr_wen_r_mod & _T_367; // @[lib.scala 407:17] + assign rvclkhdr_12_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_12_io_en = io_dec_csr_wen_r_mod & _T_388; // @[lib.scala 407:17] + assign rvclkhdr_13_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_13_io_en = io_dec_csr_wen_r_mod & _T_430; // @[lib.scala 407:17] + assign rvclkhdr_14_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_14_io_en = _T_549 & _T_550; // @[lib.scala 407:17] + assign rvclkhdr_15_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_15_io_en = wr_micect_r | io_ic_perr_r; // @[lib.scala 407:17] + assign rvclkhdr_16_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_16_io_en = _T_604 | io_iccm_dma_sb_error; // @[lib.scala 407:17] + assign rvclkhdr_17_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_17_io_en = wr_mdccmect_r | perfmux_flop_io_lsu_single_ecc_error_r_d1; // @[lib.scala 407:17] + assign rvclkhdr_18_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_18_io_en = mfdht[0]; // @[lib.scala 407:17] + assign rvclkhdr_19_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_19_io_en = io_dec_csr_wen_r_mod & _T_668; // @[lib.scala 407:17] + assign rvclkhdr_20_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_20_io_en = _T_687 | io_take_ext_int_start; // @[lib.scala 407:17] + assign rvclkhdr_21_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_21_io_en = _T_753 | io_take_nmi; // @[lib.scala 407:17] + assign rvclkhdr_22_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_22_io_en = _T_778 | dpc_capture_npc; // @[lib.scala 407:17] + assign rvclkhdr_23_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_23_io_en = _T_718 & _T_788; // @[lib.scala 407:17] + assign rvclkhdr_24_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_24_io_en = wr_dicad0_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 407:17] + assign rvclkhdr_25_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_25_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 407:17] + assign rvclkhdr_26_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_26_io_en = _T_808 | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 407:17] + assign rvclkhdr_27_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_27_io_en = io_trigger_enabled[0] | wr_mtdata1_t_r_0; // @[lib.scala 407:17] + assign rvclkhdr_28_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_28_io_en = io_trigger_enabled[1] | wr_mtdata1_t_r_1; // @[lib.scala 407:17] + assign rvclkhdr_29_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_29_io_en = io_trigger_enabled[2] | wr_mtdata1_t_r_2; // @[lib.scala 407:17] + assign rvclkhdr_30_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_30_io_en = io_trigger_enabled[3] | wr_mtdata1_t_r_3; // @[lib.scala 407:17] + assign rvclkhdr_31_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_31_io_en = _T_1073 & _T_893; // @[lib.scala 407:17] + assign rvclkhdr_32_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_32_io_en = _T_1082 & _T_902; // @[lib.scala 407:17] + assign rvclkhdr_33_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_33_io_en = _T_1091 & _T_913; // @[lib.scala 407:17] + assign rvclkhdr_34_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_34_io_en = _T_1100 & _T_922; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + mpmc_b = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + _T_61 = _RAND_1[30:0]; + _RAND_2 = {1{`RANDOM}}; + mdccmect = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + miccmect = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + micect = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + mie = _RAND_5[5:0]; + _RAND_6 = {1{`RANDOM}}; + temp_ncount6_2 = _RAND_6[4:0]; + _RAND_7 = {1{`RANDOM}}; + temp_ncount0 = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + _T_106 = _RAND_8[23:0]; + _RAND_9 = {1{`RANDOM}}; + _T_110 = _RAND_9[7:0]; + _RAND_10 = {1{`RANDOM}}; + mcycleh = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + _T_150 = _RAND_11[23:0]; + _RAND_12 = {1{`RANDOM}}; + _T_153 = _RAND_12[7:0]; + _RAND_13 = {1{`RANDOM}}; + minstreth = _RAND_13[31:0]; + _RAND_14 = {1{`RANDOM}}; + mscratch = _RAND_14[31:0]; + _RAND_15 = {1{`RANDOM}}; + _T_196 = _RAND_15[30:0]; + _RAND_16 = {1{`RANDOM}}; + pc_r_d1 = _RAND_16[30:0]; + _RAND_17 = {1{`RANDOM}}; + _T_231 = _RAND_17[30:0]; + _RAND_18 = {1{`RANDOM}}; + mcause = _RAND_18[31:0]; + _RAND_19 = {1{`RANDOM}}; + mscause = _RAND_19[3:0]; + _RAND_20 = {1{`RANDOM}}; + mtval = _RAND_20[31:0]; + _RAND_21 = {1{`RANDOM}}; + mcgc_int = _RAND_21[9:0]; + _RAND_22 = {1{`RANDOM}}; + mfdc_int = _RAND_22[15:0]; + _RAND_23 = {1{`RANDOM}}; + mrac = _RAND_23[31:0]; + _RAND_24 = {1{`RANDOM}}; + mdseac = _RAND_24[31:0]; + _RAND_25 = {1{`RANDOM}}; + mfdht = _RAND_25[5:0]; + _RAND_26 = {1{`RANDOM}}; + mfdhs = _RAND_26[1:0]; + _RAND_27 = {1{`RANDOM}}; + force_halt_ctr_f = _RAND_27[31:0]; + _RAND_28 = {1{`RANDOM}}; + meivt = _RAND_28[21:0]; + _RAND_29 = {1{`RANDOM}}; + meihap = _RAND_29[7:0]; + _RAND_30 = {1{`RANDOM}}; + meicurpl = _RAND_30[3:0]; + _RAND_31 = {1{`RANDOM}}; + meipt = _RAND_31[3:0]; + _RAND_32 = {1{`RANDOM}}; + _T_756 = _RAND_32[15:0]; + _RAND_33 = {1{`RANDOM}}; + _T_781 = _RAND_33[30:0]; + _RAND_34 = {1{`RANDOM}}; + dicawics = _RAND_34[16:0]; + _RAND_35 = {1{`RANDOM}}; + dicad0 = _RAND_35[31:0]; + _RAND_36 = {1{`RANDOM}}; + dicad0h = _RAND_36[31:0]; + _RAND_37 = {1{`RANDOM}}; + _T_815 = _RAND_37[6:0]; + _RAND_38 = {1{`RANDOM}}; + mtsel = _RAND_38[1:0]; + _RAND_39 = {1{`RANDOM}}; + _T_965 = _RAND_39[9:0]; + _RAND_40 = {1{`RANDOM}}; + _T_969 = _RAND_40[9:0]; + _RAND_41 = {1{`RANDOM}}; + _T_973 = _RAND_41[9:0]; + _RAND_42 = {1{`RANDOM}}; + _T_977 = _RAND_42[9:0]; + _RAND_43 = {1{`RANDOM}}; + mtdata2_t_0 = _RAND_43[31:0]; + _RAND_44 = {1{`RANDOM}}; + mtdata2_t_1 = _RAND_44[31:0]; + _RAND_45 = {1{`RANDOM}}; + mtdata2_t_2 = _RAND_45[31:0]; + _RAND_46 = {1{`RANDOM}}; + mtdata2_t_3 = _RAND_46[31:0]; + _RAND_47 = {1{`RANDOM}}; + dec_tlu_exc_cause_wb2 = _RAND_47[4:0]; + _RAND_48 = {1{`RANDOM}}; + dec_tlu_int_valid_wb2 = _RAND_48[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + mpmc_b = 1'h0; + end + if (reset) begin + _T_61 = 31'h0; + end + if (reset) begin + mdccmect = 32'h0; + end + if (reset) begin + miccmect = 32'h0; + end + if (reset) begin + micect = 32'h0; + end + if (reset) begin + mie = 6'h0; + end + if (reset) begin + temp_ncount6_2 = 5'h0; + end + if (reset) begin + temp_ncount0 = 1'h0; + end + if (reset) begin + _T_106 = 24'h0; + end + if (reset) begin + _T_110 = 8'h0; + end + if (reset) begin + mcycleh = 32'h0; + end + if (reset) begin + _T_150 = 24'h0; + end + if (reset) begin + _T_153 = 8'h0; + end + if (reset) begin + minstreth = 32'h0; + end + if (reset) begin + mscratch = 32'h0; + end + if (reset) begin + _T_196 = 31'h0; + end + if (reset) begin + pc_r_d1 = 31'h0; + end + if (reset) begin + _T_231 = 31'h0; + end + if (reset) begin + mcause = 32'h0; + end + if (reset) begin + mscause = 4'h0; + end + if (reset) begin + mtval = 32'h0; + end + if (reset) begin + mcgc_int = 10'h0; + end + if (reset) begin + mfdc_int = 16'h0; + end + if (reset) begin + mrac = 32'h0; + end + if (reset) begin + mdseac = 32'h0; + end + if (reset) begin + mfdht = 6'h0; + end + if (reset) begin + mfdhs = 2'h0; + end + if (reset) begin + force_halt_ctr_f = 32'h0; + end + if (reset) begin + meivt = 22'h0; + end + if (reset) begin + meihap = 8'h0; + end + if (reset) begin + meicurpl = 4'h0; + end + if (reset) begin + meipt = 4'h0; + end + if (reset) begin + _T_756 = 16'h0; + end + if (reset) begin + _T_781 = 31'h0; + end + if (reset) begin + dicawics = 17'h0; + end + if (reset) begin + dicad0 = 32'h0; + end + if (reset) begin + dicad0h = 32'h0; + end + if (reset) begin + _T_815 = 7'h0; + end + if (reset) begin + mtsel = 2'h0; + end + if (reset) begin + _T_965 = 10'h0; + end + if (reset) begin + _T_969 = 10'h0; + end + if (reset) begin + _T_973 = 10'h0; + end + if (reset) begin + _T_977 = 10'h0; + end + if (reset) begin + mtdata2_t_0 = 32'h0; + end + if (reset) begin + mtdata2_t_1 = 32'h0; + end + if (reset) begin + mtdata2_t_2 = 32'h0; + end + if (reset) begin + mtdata2_t_3 = 32'h0; + end + if (reset) begin + dec_tlu_exc_cause_wb2 = 5'h0; + end + if (reset) begin + dec_tlu_int_valid_wb2 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mpmc_b <= 1'h0; + end else if (wr_mpmc_r) begin + mpmc_b <= _T_565; + end else begin + mpmc_b <= _T_566; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_61 <= 31'h0; + end else if (wr_mtvec_r) begin + _T_61 <= mtvec_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + mdccmect <= 32'h0; + end else if (_T_625) begin + if (wr_mdccmect_r) begin + mdccmect <= _T_580; + end else begin + mdccmect <= _T_624; + end + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + miccmect <= 32'h0; + end else if (_T_605) begin + if (wr_miccmect_r) begin + miccmect <= _T_580; + end else begin + miccmect <= _T_603; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + micect <= 32'h0; + end else if (_T_583) begin + if (wr_micect_r) begin + micect <= _T_580; + end else begin + micect <= _T_582; + end + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mie <= 6'h0; + end else begin + mie <= io_mie_ns; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + temp_ncount6_2 <= 5'h0; + end else if (wr_mcountinhibit_r) begin + temp_ncount6_2 <= io_dec_csr_wrdata_r[6:2]; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + temp_ncount0 <= 1'h0; + end else if (wr_mcountinhibit_r) begin + temp_ncount0 <= io_dec_csr_wrdata_r[0]; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_106 <= 24'h0; + end else if (_T_104) begin + _T_106 <= mcyclel_ns[31:8]; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_110 <= 8'h0; + end else if (_T_108) begin + _T_110 <= mcyclel_ns[7:0]; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + mcycleh <= 32'h0; + end else if (_T_117) begin + if (wr_mcycleh_r) begin + mcycleh <= io_dec_csr_wrdata_r; + end else begin + mcycleh <= mcycleh_inc; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_150 <= 24'h0; + end else if (_T_148) begin + _T_150 <= minstretl_ns[31:8]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_153 <= 8'h0; + end else if (minstret_enable) begin + _T_153 <= minstretl_ns[7:0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + minstreth <= 32'h0; + end else if (_T_163) begin + if (wr_minstreth_r) begin + minstreth <= io_dec_csr_wrdata_r; + end else begin + minstreth <= minstreth_inc; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mscratch <= 32'h0; + end else if (wr_mscratch_r) begin + mscratch <= io_dec_csr_wrdata_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_196 <= 31'h0; + end else if (_T_193) begin + _T_196 <= io_npc_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + pc_r_d1 <= 31'h0; + end else if (pc0_valid_r) begin + pc_r_d1 <= pc_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_231 <= 31'h0; + end else if (_T_229) begin + _T_231 <= mepc_ns; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mcause <= 32'h0; + end else if (_T_274) begin + mcause <= mcause_ns; + end + end + always @(posedge io_e4e5_int_clk or posedge reset) begin + if (reset) begin + mscause <= 4'h0; + end else begin + mscause <= _T_304 | _T_303; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mtval <= 32'h0; + end else if (_T_363) begin + mtval <= mtval_ns; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mcgc_int <= 10'h0; + end else if (wr_mcgc_r) begin + if (wr_mcgc_r) begin + mcgc_int <= _T_372; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mfdc_int <= 16'h0; + end else if (wr_mfdc_r) begin + mfdc_int <= mfdc_ns; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mrac <= 32'h0; + end else if (wr_mrac_r) begin + mrac <= mrac_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mdseac <= 32'h0; + end else if (mdseac_en) begin + mdseac <= io_lsu_imprecise_error_addr_any; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mfdht <= 6'h0; + end else if (wr_mfdht_r) begin + if (wr_mfdht_r) begin + mfdht <= io_dec_csr_wrdata_r[5:0]; + end + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mfdhs <= 2'h0; + end else if (_T_651) begin + if (wr_mfdhs_r) begin + mfdhs <= io_dec_csr_wrdata_r[1:0]; + end else if (_T_645) begin + mfdhs <= _T_649; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + force_halt_ctr_f <= 32'h0; + end else if (mfdht[0]) begin + if (io_debug_halt_req_f) begin + force_halt_ctr_f <= _T_656; + end else if (io_dbg_tlu_halted_f) begin + force_halt_ctr_f <= 32'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + meivt <= 22'h0; + end else if (wr_meivt_r) begin + meivt <= io_dec_csr_wrdata_r[31:10]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + meihap <= 8'h0; + end else if (wr_meicpct_r) begin + meihap <= io_pic_claimid; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + meicurpl <= 4'h0; + end else if (wr_meicurpl_r) begin + meicurpl <= io_dec_csr_wrdata_r[3:0]; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + meipt <= 4'h0; + end else if (wr_meipt_r) begin + meipt <= io_dec_csr_wrdata_r[3:0]; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_756 <= 16'h0; + end else if (_T_754) begin + if (enter_debug_halt_req_le) begin + _T_756 <= _T_730; + end else if (wr_dcsr_r) begin + _T_756 <= _T_745; + end else begin + _T_756 <= _T_750; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_781 <= 31'h0; + end else if (_T_779) begin + _T_781 <= dpc_ns; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + dicawics <= 17'h0; + end else if (wr_dicawics_r) begin + dicawics <= dicawics_ns; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + dicad0 <= 32'h0; + end else if (_T_795) begin + if (wr_dicad0_r) begin + dicad0 <= io_dec_csr_wrdata_r; + end else begin + dicad0 <= io_ifu_ic_debug_rd_data[31:0]; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + dicad0h <= 32'h0; + end else if (_T_802) begin + if (wr_dicad0h_r) begin + dicad0h <= io_dec_csr_wrdata_r; + end else begin + dicad0h <= io_ifu_ic_debug_rd_data[63:32]; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_815 <= 7'h0; + end else if (_T_813) begin + if (_T_808) begin + _T_815 <= io_dec_csr_wrdata_r[6:0]; + end else begin + _T_815 <= io_ifu_ic_debug_rd_data[70:64]; + end + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mtsel <= 2'h0; + end else if (wr_mtsel_r) begin + mtsel <= io_dec_csr_wrdata_r[1:0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_965 <= 10'h0; + end else if (_T_963) begin + if (wr_mtdata1_t_r_0) begin + _T_965 <= tdata_wrdata_r; + end else begin + _T_965 <= _T_933; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_969 <= 10'h0; + end else if (_T_967) begin + if (wr_mtdata1_t_r_1) begin + _T_969 <= tdata_wrdata_r; + end else begin + _T_969 <= _T_942; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_973 <= 10'h0; + end else if (_T_971) begin + if (wr_mtdata1_t_r_2) begin + _T_973 <= tdata_wrdata_r; + end else begin + _T_973 <= _T_951; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_977 <= 10'h0; + end else if (_T_975) begin + if (wr_mtdata1_t_r_3) begin + _T_977 <= tdata_wrdata_r; + end else begin + _T_977 <= _T_960; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mtdata2_t_0 <= 32'h0; + end else if (wr_mtdata2_t_r_0) begin + mtdata2_t_0 <= io_dec_csr_wrdata_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mtdata2_t_1 <= 32'h0; + end else if (wr_mtdata2_t_r_1) begin + mtdata2_t_1 <= io_dec_csr_wrdata_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mtdata2_t_2 <= 32'h0; + end else if (wr_mtdata2_t_r_2) begin + mtdata2_t_2 <= io_dec_csr_wrdata_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mtdata2_t_3 <= 32'h0; + end else if (wr_mtdata2_t_r_3) begin + mtdata2_t_3 <= io_dec_csr_wrdata_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + dec_tlu_exc_cause_wb2 <= 5'h0; + end else if (_T_1153) begin + dec_tlu_exc_cause_wb2 <= dec_tlu_exc_cause_wb1_raw; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + dec_tlu_int_valid_wb2 <= 1'h0; + end else if (_T_1156) begin + dec_tlu_int_valid_wb2 <= dec_tlu_int_valid_wb1_raw; + end + end +endmodule +module dec_timer_ctl( + input clock, + input reset, + input io_free_l2clk, + input io_csr_wr_clk, + input io_dec_csr_wen_r_mod, + input [11:0] io_dec_csr_wraddr_r, + input [31:0] io_dec_csr_wrdata_r, + input io_csr_mitctl0, + input io_csr_mitctl1, + input io_csr_mitb0, + input io_csr_mitb1, + input io_csr_mitcnt0, + input io_csr_mitcnt1, + input io_dec_pause_state, + input io_dec_tlu_pmu_fw_halted, + input io_internal_dbg_halt_timers, + output [31:0] io_dec_timer_rddata_d, + output io_dec_timer_read_d, + output io_dec_timer_t0_pulse, + output io_dec_timer_t1_pulse +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_4_io_en; // @[lib.scala 404:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_5_io_en; // @[lib.scala 404:23] + reg [23:0] _T_28; // @[Reg.scala 27:20] + reg [7:0] _T_33; // @[Reg.scala 27:20] + wire [31:0] mitcnt0 = {_T_28,_T_33}; // @[Cat.scala 29:58] + reg [31:0] mitb0_b; // @[Reg.scala 27:20] + wire [31:0] mitb0 = ~mitb0_b; // @[dec_tlu_ctl.scala 3335:22] + wire mit0_match_ns = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 3277:36] + reg [23:0] _T_67; // @[Reg.scala 27:20] + reg [7:0] _T_72; // @[Reg.scala 27:20] + wire [31:0] mitcnt1 = {_T_67,_T_72}; // @[Cat.scala 29:58] + reg [31:0] mitb1_b; // @[Reg.scala 27:20] + wire [31:0] mitb1 = ~mitb1_b; // @[dec_tlu_ctl.scala 3344:18] + wire mit1_match_ns = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 3278:36] + wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[dec_tlu_ctl.scala 3288:72] + wire wr_mitcnt0_r = io_dec_csr_wen_r_mod & _T; // @[dec_tlu_ctl.scala 3288:49] + reg [1:0] _T_90; // @[Reg.scala 27:20] + reg mitctl0_0_b; // @[Reg.scala 27:20] + wire _T_91 = ~mitctl0_0_b; // @[dec_tlu_ctl.scala 3360:107] + wire [2:0] mitctl0 = {_T_90,_T_91}; // @[Cat.scala 29:58] + wire _T_2 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 3290:56] + wire _T_4 = _T_2 | mitctl0[2]; // @[dec_tlu_ctl.scala 3290:76] + wire _T_5 = mitctl0[0] & _T_4; // @[dec_tlu_ctl.scala 3290:53] + wire _T_6 = ~io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 3290:112] + wire _T_8 = _T_6 | mitctl0[1]; // @[dec_tlu_ctl.scala 3290:138] + wire _T_9 = _T_5 & _T_8; // @[dec_tlu_ctl.scala 3290:109] + wire _T_10 = ~io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 3290:173] + wire mitcnt0_inc_ok = _T_9 & _T_10; // @[dec_tlu_ctl.scala 3290:171] + wire [7:0] _T_14 = mitcnt0[7:0] + 8'h1; // @[dec_tlu_ctl.scala 3293:38] + wire [8:0] mitcnt0_inc1 = {{1'd0}, _T_14}; // @[dec_tlu_ctl.scala 3293:22] + wire mitcnt0_inc_cout = mitcnt0_inc1[8]; // @[dec_tlu_ctl.scala 3294:44] + wire [23:0] _T_16 = {23'h0,mitcnt0_inc_cout}; // @[Cat.scala 29:58] + wire [23:0] mitcnt0_inc2 = mitcnt0[31:8] + _T_16; // @[dec_tlu_ctl.scala 3295:39] + wire [31:0] mitcnt0_inc = {mitcnt0_inc2,mitcnt0_inc1[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_22 = mit0_match_ns ? 32'h0 : mitcnt0_inc; // @[dec_tlu_ctl.scala 3298:69] + wire [31:0] mitcnt0_ns = wr_mitcnt0_r ? io_dec_csr_wrdata_r : _T_22; // @[dec_tlu_ctl.scala 3298:30] + wire _T_24 = mitcnt0_inc_ok & mitcnt0_inc_cout; // @[dec_tlu_ctl.scala 3301:87] + wire _T_25 = wr_mitcnt0_r | _T_24; // @[dec_tlu_ctl.scala 3301:69] + wire _T_26 = _T_25 | mit0_match_ns; // @[dec_tlu_ctl.scala 3301:107] + wire _T_30 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[dec_tlu_ctl.scala 3302:54] + wire _T_31 = _T_30 | mit0_match_ns; // @[dec_tlu_ctl.scala 3302:71] + wire _T_35 = io_dec_csr_wraddr_r == 12'h7d5; // @[dec_tlu_ctl.scala 3309:72] + wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_35; // @[dec_tlu_ctl.scala 3309:49] + reg [2:0] _T_101; // @[Reg.scala 27:20] + reg mitctl1_0_b; // @[Reg.scala 27:20] + wire _T_102 = ~mitctl1_0_b; // @[dec_tlu_ctl.scala 3374:92] + wire [3:0] mitctl1 = {_T_101,_T_102}; // @[Cat.scala 29:58] + wire _T_39 = _T_2 | mitctl1[2]; // @[dec_tlu_ctl.scala 3311:76] + wire _T_40 = mitctl1[0] & _T_39; // @[dec_tlu_ctl.scala 3311:53] + wire _T_43 = _T_6 | mitctl1[1]; // @[dec_tlu_ctl.scala 3311:138] + wire _T_44 = _T_40 & _T_43; // @[dec_tlu_ctl.scala 3311:109] + wire _T_46 = _T_44 & _T_10; // @[dec_tlu_ctl.scala 3311:171] + wire _T_48 = ~mitctl1[3]; // @[dec_tlu_ctl.scala 3311:205] + wire _T_49 = _T_48 | mit0_match_ns; // @[dec_tlu_ctl.scala 3311:217] + wire mitcnt1_inc_ok = _T_46 & _T_49; // @[dec_tlu_ctl.scala 3311:202] + wire [7:0] _T_53 = mitcnt1[7:0] + 8'h1; // @[dec_tlu_ctl.scala 3316:38] + wire [8:0] mitcnt1_inc1 = {{1'd0}, _T_53}; // @[dec_tlu_ctl.scala 3316:22] + wire mitcnt1_inc_cout = mitcnt1_inc1[8]; // @[dec_tlu_ctl.scala 3317:44] + wire [23:0] _T_55 = {23'h0,mitcnt1_inc_cout}; // @[Cat.scala 29:58] + wire [23:0] mitcnt1_inc2 = mitcnt1[31:8] + _T_55; // @[dec_tlu_ctl.scala 3318:39] + wire [31:0] mitcnt1_inc = {mitcnt1_inc2,mitcnt1_inc1[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_61 = mit1_match_ns ? 32'h0 : mitcnt1_inc; // @[dec_tlu_ctl.scala 3321:75] + wire [31:0] mitcnt1_ns = wr_mitcnt1_r ? io_dec_csr_wrdata_r : _T_61; // @[dec_tlu_ctl.scala 3321:29] + wire _T_63 = mitcnt1_inc_ok & mitcnt1_inc_cout; // @[dec_tlu_ctl.scala 3323:87] + wire _T_64 = wr_mitcnt1_r | _T_63; // @[dec_tlu_ctl.scala 3323:69] + wire _T_65 = _T_64 | mit1_match_ns; // @[dec_tlu_ctl.scala 3323:107] + wire _T_69 = wr_mitcnt1_r | mitcnt1_inc_ok; // @[dec_tlu_ctl.scala 3324:54] + wire _T_70 = _T_69 | mit1_match_ns; // @[dec_tlu_ctl.scala 3324:71] + wire _T_74 = io_dec_csr_wraddr_r == 12'h7d3; // @[dec_tlu_ctl.scala 3333:70] + wire wr_mitb0_r = io_dec_csr_wen_r_mod & _T_74; // @[dec_tlu_ctl.scala 3333:47] + wire [31:0] _T_75 = ~io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 3334:38] + wire _T_78 = io_dec_csr_wraddr_r == 12'h7d6; // @[dec_tlu_ctl.scala 3342:69] + wire wr_mitb1_r = io_dec_csr_wen_r_mod & _T_78; // @[dec_tlu_ctl.scala 3342:47] + wire _T_82 = io_dec_csr_wraddr_r == 12'h7d4; // @[dec_tlu_ctl.scala 3355:72] + wire wr_mitctl0_r = io_dec_csr_wen_r_mod & _T_82; // @[dec_tlu_ctl.scala 3355:49] + wire [2:0] mitctl0_ns = wr_mitctl0_r ? io_dec_csr_wrdata_r[2:0] : mitctl0; // @[dec_tlu_ctl.scala 3356:31] + wire mitctl0_0_b_ns = ~mitctl0_ns[0]; // @[dec_tlu_ctl.scala 3358:30] + wire _T_93 = io_dec_csr_wraddr_r == 12'h7d7; // @[dec_tlu_ctl.scala 3370:71] + wire wr_mitctl1_r = io_dec_csr_wen_r_mod & _T_93; // @[dec_tlu_ctl.scala 3370:49] + wire [3:0] mitctl1_ns = wr_mitctl1_r ? io_dec_csr_wrdata_r[3:0] : mitctl1; // @[dec_tlu_ctl.scala 3371:31] + wire mitctl1_0_b_ns = ~mitctl1_ns[0]; // @[dec_tlu_ctl.scala 3372:29] + wire _T_104 = io_csr_mitcnt1 | io_csr_mitcnt0; // @[dec_tlu_ctl.scala 3376:51] + wire _T_105 = _T_104 | io_csr_mitb1; // @[dec_tlu_ctl.scala 3376:68] + wire _T_106 = _T_105 | io_csr_mitb0; // @[dec_tlu_ctl.scala 3376:83] + wire _T_107 = _T_106 | io_csr_mitctl0; // @[dec_tlu_ctl.scala 3376:98] + wire [31:0] _T_116 = {29'h0,_T_90,_T_91}; // @[Cat.scala 29:58] + wire [31:0] _T_119 = {28'h0,_T_101,_T_102}; // @[Cat.scala 29:58] + wire [31:0] _T_120 = io_csr_mitcnt0 ? mitcnt0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_121 = io_csr_mitcnt1 ? mitcnt1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_122 = io_csr_mitb0 ? mitb0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_123 = io_csr_mitb1 ? mitb1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_124 = io_csr_mitctl0 ? _T_116 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_125 = io_csr_mitctl1 ? _T_119 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_126 = _T_120 | _T_121; // @[Mux.scala 27:72] + wire [31:0] _T_127 = _T_126 | _T_122; // @[Mux.scala 27:72] + wire [31:0] _T_128 = _T_127 | _T_123; // @[Mux.scala 27:72] + wire [31:0] _T_129 = _T_128 | _T_124; // @[Mux.scala 27:72] + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en) + ); + assign io_dec_timer_rddata_d = _T_129 | _T_125; // @[dec_tlu_ctl.scala 3377:33] + assign io_dec_timer_read_d = _T_107 | io_csr_mitctl1; // @[dec_tlu_ctl.scala 3376:33] + assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 3280:31] + assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 3281:31] + assign rvclkhdr_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_io_en = _T_25 | mit0_match_ns; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = _T_30 | mit0_match_ns; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = _T_64 | mit1_match_ns; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = _T_69 | mit1_match_ns; // @[lib.scala 407:17] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_4_io_en = io_dec_csr_wen_r_mod & _T_74; // @[lib.scala 407:17] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_5_io_en = io_dec_csr_wen_r_mod & _T_78; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T_28 = _RAND_0[23:0]; + _RAND_1 = {1{`RANDOM}}; + _T_33 = _RAND_1[7:0]; + _RAND_2 = {1{`RANDOM}}; + mitb0_b = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + _T_67 = _RAND_3[23:0]; + _RAND_4 = {1{`RANDOM}}; + _T_72 = _RAND_4[7:0]; + _RAND_5 = {1{`RANDOM}}; + mitb1_b = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + _T_90 = _RAND_6[1:0]; + _RAND_7 = {1{`RANDOM}}; + mitctl0_0_b = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + _T_101 = _RAND_8[2:0]; + _RAND_9 = {1{`RANDOM}}; + mitctl1_0_b = _RAND_9[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_28 = 24'h0; + end + if (reset) begin + _T_33 = 8'h0; + end + if (reset) begin + mitb0_b = 32'h0; + end + if (reset) begin + _T_67 = 24'h0; + end + if (reset) begin + _T_72 = 8'h0; + end + if (reset) begin + mitb1_b = 32'h0; + end + if (reset) begin + _T_90 = 2'h0; + end + if (reset) begin + mitctl0_0_b = 1'h0; + end + if (reset) begin + _T_101 = 3'h0; + end + if (reset) begin + mitctl1_0_b = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_28 <= 24'h0; + end else if (_T_26) begin + _T_28 <= mitcnt0_ns[31:8]; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_33 <= 8'h0; + end else if (_T_31) begin + _T_33 <= mitcnt0_ns[7:0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mitb0_b <= 32'h0; + end else if (wr_mitb0_r) begin + mitb0_b <= _T_75; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_67 <= 24'h0; + end else if (_T_65) begin + _T_67 <= mitcnt1_ns[31:8]; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_72 <= 8'h0; + end else if (_T_70) begin + _T_72 <= mitcnt1_ns[7:0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mitb1_b <= 32'h0; + end else if (wr_mitb1_r) begin + mitb1_b <= _T_75; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + _T_90 <= 2'h0; + end else if (wr_mitctl0_r) begin + _T_90 <= mitctl0_ns[2:1]; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mitctl0_0_b <= 1'h0; + end else if (wr_mitctl0_r) begin + mitctl0_0_b <= mitctl0_0_b_ns; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + _T_101 <= 3'h0; + end else if (wr_mitctl1_r) begin + _T_101 <= mitctl1_ns[3:1]; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mitctl1_0_b <= 1'h0; + end else if (wr_mitctl1_r) begin + mitctl1_0_b <= mitctl1_0_b_ns; + end + end +endmodule +module dec_decode_csr_read( + input [11:0] io_dec_csr_rdaddr_d, + output io_csr_pkt_csr_misa, + output io_csr_pkt_csr_mvendorid, + output io_csr_pkt_csr_marchid, + output io_csr_pkt_csr_mimpid, + output io_csr_pkt_csr_mhartid, + output io_csr_pkt_csr_mstatus, + output io_csr_pkt_csr_mtvec, + output io_csr_pkt_csr_mip, + output io_csr_pkt_csr_mie, + output io_csr_pkt_csr_mcyclel, + output io_csr_pkt_csr_mcycleh, + output io_csr_pkt_csr_minstretl, + output io_csr_pkt_csr_minstreth, + output io_csr_pkt_csr_mscratch, + output io_csr_pkt_csr_mepc, + output io_csr_pkt_csr_mcause, + output io_csr_pkt_csr_mscause, + output io_csr_pkt_csr_mtval, + output io_csr_pkt_csr_mrac, + output io_csr_pkt_csr_dmst, + output io_csr_pkt_csr_mdseac, + output io_csr_pkt_csr_meihap, + output io_csr_pkt_csr_meivt, + output io_csr_pkt_csr_meipt, + output io_csr_pkt_csr_meicurpl, + output io_csr_pkt_csr_meicidpl, + output io_csr_pkt_csr_dcsr, + output io_csr_pkt_csr_mcgc, + output io_csr_pkt_csr_mfdc, + output io_csr_pkt_csr_dpc, + output io_csr_pkt_csr_mtsel, + output io_csr_pkt_csr_mtdata1, + output io_csr_pkt_csr_mtdata2, + output io_csr_pkt_csr_mhpmc3, + output io_csr_pkt_csr_mhpmc4, + output io_csr_pkt_csr_mhpmc5, + output io_csr_pkt_csr_mhpmc6, + output io_csr_pkt_csr_mhpmc3h, + output io_csr_pkt_csr_mhpmc4h, + output io_csr_pkt_csr_mhpmc5h, + output io_csr_pkt_csr_mhpmc6h, + output io_csr_pkt_csr_mhpme3, + output io_csr_pkt_csr_mhpme4, + output io_csr_pkt_csr_mhpme5, + output io_csr_pkt_csr_mhpme6, + output io_csr_pkt_csr_mcountinhibit, + output io_csr_pkt_csr_mitctl0, + output io_csr_pkt_csr_mitctl1, + output io_csr_pkt_csr_mitb0, + output io_csr_pkt_csr_mitb1, + output io_csr_pkt_csr_mitcnt0, + output io_csr_pkt_csr_mitcnt1, + output io_csr_pkt_csr_mpmc, + output io_csr_pkt_csr_meicpct, + output io_csr_pkt_csr_micect, + output io_csr_pkt_csr_miccmect, + output io_csr_pkt_csr_mdccmect, + output io_csr_pkt_csr_mfdht, + output io_csr_pkt_csr_mfdhs, + output io_csr_pkt_csr_dicawics, + output io_csr_pkt_csr_dicad0h, + output io_csr_pkt_csr_dicad0, + output io_csr_pkt_csr_dicad1, + output io_csr_pkt_csr_dicago, + output io_csr_pkt_presync, + output io_csr_pkt_postsync, + output io_csr_pkt_legal +); + wire _T_1 = ~io_dec_csr_rdaddr_d[11]; // @[dec_tlu_ctl.scala 3173:129] + wire _T_3 = ~io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:129] + wire _T_5 = ~io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:129] + wire _T_7 = ~io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:129] + wire _T_9 = _T_1 & _T_3; // @[dec_tlu_ctl.scala 3173:198] + wire _T_10 = _T_9 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_11 = _T_10 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_15 = ~io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 3173:129] + wire _T_17 = ~io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:129] + wire _T_19 = io_dec_csr_rdaddr_d[10] & _T_15; // @[dec_tlu_ctl.scala 3173:198] + wire _T_20 = _T_19 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_27 = ~io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:165] + wire _T_29 = _T_19 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_36 = io_dec_csr_rdaddr_d[10] & _T_3; // @[dec_tlu_ctl.scala 3173:198] + wire _T_37 = _T_36 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_69 = _T_10 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_70 = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_75 = _T_15 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_94 = ~io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:129] + wire _T_96 = ~io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:129] + wire _T_101 = io_dec_csr_rdaddr_d[11] & _T_15; // @[dec_tlu_ctl.scala 3173:198] + wire _T_102 = _T_101 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_103 = _T_102 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_104 = _T_103 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_119 = io_dec_csr_rdaddr_d[7] & _T_3; // @[dec_tlu_ctl.scala 3173:198] + wire _T_120 = _T_119 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_121 = _T_120 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_122 = _T_121 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_123 = _T_122 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_138 = _T_15 & _T_3; // @[dec_tlu_ctl.scala 3173:198] + wire _T_139 = _T_138 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_140 = _T_139 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_141 = _T_140 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_142 = _T_141 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_145 = ~io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 3173:129] + wire _T_156 = _T_145 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_157 = _T_156 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_158 = _T_157 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_159 = _T_158 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_160 = _T_159 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_172 = _T_75 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_173 = _T_172 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_182 = _T_75 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_183 = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_191 = _T_75 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_196 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_217 = _T_1 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_218 = _T_217 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_219 = _T_218 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_220 = _T_219 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_230 = io_dec_csr_rdaddr_d[10] & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_231 = _T_230 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_232 = _T_231 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_240 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_241 = _T_240 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_258 = _T_145 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_259 = _T_258 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_260 = _T_259 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_261 = _T_260 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_268 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_269 = _T_268 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_281 = _T_268 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_291 = _T_36 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_292 = _T_291 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_299 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_300 = _T_299 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_310 = _T_300 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_311 = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_330 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_331 = _T_330 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_332 = _T_331 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_342 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_381 = _T_103 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_382 = _T_381 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_397 = _T_103 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_411 = _T_15 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_412 = _T_411 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_413 = _T_412 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_414 = _T_413 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_415 = _T_414 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_426 = io_dec_csr_rdaddr_d[7] & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_427 = _T_426 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_428 = _T_427 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_429 = _T_428 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_444 = _T_119 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_445 = _T_444 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_446 = _T_445 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_447 = _T_446 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_460 = _T_427 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_461 = _T_460 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_478 = _T_446 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_490 = _T_15 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_491 = _T_490 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_492 = _T_491 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_493 = _T_492 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_505 = io_dec_csr_rdaddr_d[5] & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_506 = _T_505 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_507 = _T_506 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_508 = _T_507 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_536 = _T_507 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_553 = _T_493 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_562 = io_dec_csr_rdaddr_d[6] & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_563 = _T_562 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_564 = _T_563 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_572 = io_dec_csr_rdaddr_d[6] & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_573 = _T_572 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_574 = _T_573 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_585 = _T_563 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_593 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_594 = _T_593 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_595 = _T_594 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_614 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_615 = _T_614 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_624 = io_dec_csr_rdaddr_d[6] & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_625 = _T_624 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_626 = _T_625 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_645 = _T_196 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_646 = _T_645 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_662 = _T_196 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_670 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_671 = _T_670 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_672 = _T_671 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_680 = _T_624 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_693 = _T_1 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_694 = _T_693 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_695 = _T_694 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_696 = _T_695 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_703 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_704 = _T_703 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_714 = _T_230 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_715 = _T_714 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_725 = _T_703 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_726 = _T_725 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_764 = _T_311 | _T_553; // @[dec_tlu_ctl.scala 3241:81] + wire _T_776 = _T_3 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_777 = _T_776 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_778 = _T_777 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_779 = _T_778 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_780 = _T_779 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_781 = _T_764 | _T_780; // @[dec_tlu_ctl.scala 3241:121] + wire _T_790 = io_dec_csr_rdaddr_d[11] & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_791 = _T_790 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_792 = _T_791 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_793 = _T_792 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_794 = _T_781 | _T_793; // @[dec_tlu_ctl.scala 3241:155] + wire _T_805 = _T_791 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_806 = _T_805 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_807 = _T_794 | _T_806; // @[dec_tlu_ctl.scala 3242:49] + wire _T_818 = io_dec_csr_rdaddr_d[7] & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_819 = _T_818 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_820 = _T_819 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_821 = _T_820 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_822 = _T_821 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_846 = _T_311 | _T_70; // @[dec_tlu_ctl.scala 3243:81] + wire _T_856 = _T_846 | _T_183; // @[dec_tlu_ctl.scala 3243:121] + wire _T_866 = _T_856 | _T_342; // @[dec_tlu_ctl.scala 3243:162] + wire _T_881 = _T_1 & _T_15; // @[dec_tlu_ctl.scala 3173:198] + wire _T_882 = _T_881 & _T_3; // @[dec_tlu_ctl.scala 3173:198] + wire _T_883 = _T_882 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_884 = _T_883 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_885 = _T_884 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_886 = _T_885 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_887 = _T_866 | _T_886; // @[dec_tlu_ctl.scala 3244:57] + wire _T_899 = _T_217 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_900 = _T_899 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_901 = _T_900 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_902 = _T_901 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_903 = _T_887 | _T_902; // @[dec_tlu_ctl.scala 3244:97] + wire _T_914 = _T_231 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_915 = _T_914 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_932 = _T_1 & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_933 = _T_932 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_934 = _T_933 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_935 = _T_934 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_936 = _T_935 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_937 = _T_936 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_938 = _T_937 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_939 = _T_938 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_940 = _T_939 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_941 = _T_940 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_960 = _T_1 & _T_145; // @[dec_tlu_ctl.scala 3173:198] + wire _T_961 = _T_960 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_962 = _T_961 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_963 = _T_962 & _T_15; // @[dec_tlu_ctl.scala 3173:198] + wire _T_964 = _T_963 & _T_3; // @[dec_tlu_ctl.scala 3173:198] + wire _T_965 = _T_964 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_966 = _T_965 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_967 = _T_966 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_968 = _T_967 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_969 = _T_941 | _T_968; // @[dec_tlu_ctl.scala 3246:81] + wire _T_990 = _T_964 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_991 = _T_990 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_992 = _T_991 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_993 = _T_969 | _T_992; // @[dec_tlu_ctl.scala 3246:129] + wire _T_1009 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1010 = _T_1009 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1011 = _T_1010 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1012 = _T_1011 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1013 = _T_1012 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1014 = _T_1013 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1015 = _T_1014 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1016 = _T_1015 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1017 = _T_1016 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1018 = _T_993 | _T_1017; // @[dec_tlu_ctl.scala 3247:73] + wire _T_1030 = io_dec_csr_rdaddr_d[11] & _T_145; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1031 = _T_1030 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1032 = _T_1031 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1033 = _T_1032 & _T_3; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1034 = _T_1033 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1035 = _T_1034 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1036 = _T_1018 | _T_1035; // @[dec_tlu_ctl.scala 3247:121] + wire _T_1055 = _T_936 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1056 = _T_1055 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1057 = _T_1056 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1058 = _T_1057 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1059 = _T_1058 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1060 = _T_1059 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1061 = _T_1036 | _T_1060; // @[dec_tlu_ctl.scala 3248:73] + wire _T_1082 = _T_1056 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1083 = _T_1082 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1084 = _T_1061 | _T_1083; // @[dec_tlu_ctl.scala 3248:121] + wire _T_1102 = _T_1010 & _T_15; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1103 = _T_1102 & _T_3; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1104 = _T_1103 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1105 = _T_1104 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1106 = _T_1105 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1107 = _T_1106 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1108 = _T_1107 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1109 = _T_1084 | _T_1108; // @[dec_tlu_ctl.scala 3249:73] + wire _T_1129 = _T_935 & _T_3; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1130 = _T_1129 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1131 = _T_1130 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1132 = _T_1131 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1133 = _T_1132 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1134 = _T_1109 | _T_1133; // @[dec_tlu_ctl.scala 3249:129] + wire _T_1153 = _T_990 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1154 = _T_1134 | _T_1153; // @[dec_tlu_ctl.scala 3250:73] + wire _T_1179 = _T_1106 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1180 = _T_1179 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1181 = _T_1180 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1182 = _T_1154 | _T_1181; // @[dec_tlu_ctl.scala 3250:129] + wire _T_1201 = _T_936 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1202 = _T_1201 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1203 = _T_1202 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1204 = _T_1203 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1205 = _T_1182 | _T_1204; // @[dec_tlu_ctl.scala 3251:65] + wire _T_1225 = _T_1201 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1226 = _T_1225 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1227 = _T_1226 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1228 = _T_1205 | _T_1227; // @[dec_tlu_ctl.scala 3251:121] + wire _T_1252 = _T_1107 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1253 = _T_1228 | _T_1252; // @[dec_tlu_ctl.scala 3252:73] + wire _T_1273 = _T_990 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1274 = _T_1273 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1275 = _T_1253 | _T_1274; // @[dec_tlu_ctl.scala 3252:129] + wire _T_1292 = _T_1032 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1293 = _T_1292 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1294 = _T_1293 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1295 = _T_1294 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1296 = _T_1295 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1297 = _T_1275 | _T_1296; // @[dec_tlu_ctl.scala 3253:73] + wire _T_1320 = _T_1295 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1321 = _T_1320 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1322 = _T_1297 | _T_1321; // @[dec_tlu_ctl.scala 3253:129] + wire _T_1338 = _T_1034 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1339 = _T_1322 | _T_1338; // @[dec_tlu_ctl.scala 3254:73] + wire _T_1361 = _T_1226 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1362 = _T_1339 | _T_1361; // @[dec_tlu_ctl.scala 3254:129] + wire _T_1383 = _T_1202 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1384 = _T_1362 | _T_1383; // @[dec_tlu_ctl.scala 3255:73] + wire _T_1407 = _T_1203 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1408 = _T_1384 | _T_1407; // @[dec_tlu_ctl.scala 3255:129] + wire _T_1432 = _T_1130 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1433 = _T_1432 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1434 = _T_1433 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1435 = _T_1434 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1436 = _T_1408 | _T_1435; // @[dec_tlu_ctl.scala 3256:73] + wire _T_1452 = _T_1034 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1453 = _T_1436 | _T_1452; // @[dec_tlu_ctl.scala 3256:121] + wire _T_1475 = _T_963 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1476 = _T_1475 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1477 = _T_1476 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1478 = _T_1477 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1479 = _T_1478 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1480 = _T_1453 | _T_1479; // @[dec_tlu_ctl.scala 3257:81] + wire _T_1503 = _T_963 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1504 = _T_1503 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1505 = _T_1504 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1506 = _T_1505 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1507 = _T_1506 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1508 = _T_1480 | _T_1507; // @[dec_tlu_ctl.scala 3257:129] + wire _T_1527 = _T_990 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1528 = _T_1508 | _T_1527; // @[dec_tlu_ctl.scala 3258:65] + wire _T_1544 = _T_1034 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1545 = _T_1528 | _T_1544; // @[dec_tlu_ctl.scala 3258:121] + wire _T_1564 = _T_990 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1565 = _T_1545 | _T_1564; // @[dec_tlu_ctl.scala 3259:81] + wire _T_1581 = _T_1034 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + assign io_csr_pkt_csr_misa = _T_11 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3175:57] + assign io_csr_pkt_csr_mvendorid = _T_20 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3176:57] + assign io_csr_pkt_csr_marchid = _T_29 & _T_27; // @[dec_tlu_ctl.scala 3177:57] + assign io_csr_pkt_csr_mimpid = _T_37 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3178:57] + assign io_csr_pkt_csr_mhartid = _T_19 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3179:57] + assign io_csr_pkt_csr_mstatus = _T_11 & _T_27; // @[dec_tlu_ctl.scala 3180:57] + assign io_csr_pkt_csr_mtvec = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3181:57] + assign io_csr_pkt_csr_mip = _T_75 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3182:65] + assign io_csr_pkt_csr_mie = _T_69 & _T_27; // @[dec_tlu_ctl.scala 3183:65] + assign io_csr_pkt_csr_mcyclel = _T_104 & _T_17; // @[dec_tlu_ctl.scala 3184:57] + assign io_csr_pkt_csr_mcycleh = _T_123 & _T_17; // @[dec_tlu_ctl.scala 3185:57] + assign io_csr_pkt_csr_minstretl = _T_142 & _T_27; // @[dec_tlu_ctl.scala 3186:57] + assign io_csr_pkt_csr_minstreth = _T_160 & _T_27; // @[dec_tlu_ctl.scala 3187:57] + assign io_csr_pkt_csr_mscratch = _T_173 & _T_27; // @[dec_tlu_ctl.scala 3188:57] + assign io_csr_pkt_csr_mepc = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3189:57] + assign io_csr_pkt_csr_mcause = _T_191 & _T_27; // @[dec_tlu_ctl.scala 3190:57] + assign io_csr_pkt_csr_mscause = _T_196 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3191:57] + assign io_csr_pkt_csr_mtval = _T_191 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3192:57] + assign io_csr_pkt_csr_mrac = _T_220 & _T_17; // @[dec_tlu_ctl.scala 3193:57] + assign io_csr_pkt_csr_dmst = _T_232 & _T_17; // @[dec_tlu_ctl.scala 3194:57] + assign io_csr_pkt_csr_mdseac = _T_241 & _T_96; // @[dec_tlu_ctl.scala 3195:57] + assign io_csr_pkt_csr_meihap = _T_240 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3196:57] + assign io_csr_pkt_csr_meivt = _T_261 & _T_27; // @[dec_tlu_ctl.scala 3197:57] + assign io_csr_pkt_csr_meipt = _T_269 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3198:57] + assign io_csr_pkt_csr_meicurpl = _T_268 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3199:57] + assign io_csr_pkt_csr_meicidpl = _T_281 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3200:57] + assign io_csr_pkt_csr_dcsr = _T_292 & _T_27; // @[dec_tlu_ctl.scala 3201:57] + assign io_csr_pkt_csr_mcgc = _T_300 & _T_27; // @[dec_tlu_ctl.scala 3202:57] + assign io_csr_pkt_csr_mfdc = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3203:57] + assign io_csr_pkt_csr_dpc = _T_292 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3204:65] + assign io_csr_pkt_csr_mtsel = _T_332 & _T_27; // @[dec_tlu_ctl.scala 3205:57] + assign io_csr_pkt_csr_mtdata1 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3206:57] + assign io_csr_pkt_csr_mtdata2 = _T_331 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3207:57] + assign io_csr_pkt_csr_mhpmc3 = _T_104 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3208:57] + assign io_csr_pkt_csr_mhpmc4 = _T_382 & _T_27; // @[dec_tlu_ctl.scala 3209:57] + assign io_csr_pkt_csr_mhpmc5 = _T_397 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3210:57] + assign io_csr_pkt_csr_mhpmc6 = _T_415 & _T_27; // @[dec_tlu_ctl.scala 3211:57] + assign io_csr_pkt_csr_mhpmc3h = _T_429 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3212:57] + assign io_csr_pkt_csr_mhpmc4h = _T_447 & _T_27; // @[dec_tlu_ctl.scala 3213:57] + assign io_csr_pkt_csr_mhpmc5h = _T_461 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3214:57] + assign io_csr_pkt_csr_mhpmc6h = _T_478 & _T_27; // @[dec_tlu_ctl.scala 3215:57] + assign io_csr_pkt_csr_mhpme3 = _T_493 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3216:57] + assign io_csr_pkt_csr_mhpme4 = _T_508 & _T_27; // @[dec_tlu_ctl.scala 3217:57] + assign io_csr_pkt_csr_mhpme5 = _T_508 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3218:57] + assign io_csr_pkt_csr_mhpme6 = _T_536 & _T_27; // @[dec_tlu_ctl.scala 3219:57] + assign io_csr_pkt_csr_mcountinhibit = _T_493 & _T_27; // @[dec_tlu_ctl.scala 3220:49] + assign io_csr_pkt_csr_mitctl0 = _T_564 & _T_27; // @[dec_tlu_ctl.scala 3221:57] + assign io_csr_pkt_csr_mitctl1 = _T_574 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3222:57] + assign io_csr_pkt_csr_mitb0 = _T_585 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3223:57] + assign io_csr_pkt_csr_mitb1 = _T_595 & _T_27; // @[dec_tlu_ctl.scala 3224:57] + assign io_csr_pkt_csr_mitcnt0 = _T_585 & _T_27; // @[dec_tlu_ctl.scala 3225:57] + assign io_csr_pkt_csr_mitcnt1 = _T_615 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3226:57] + assign io_csr_pkt_csr_mpmc = _T_626 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3227:57] + assign io_csr_pkt_csr_meicpct = _T_281 & _T_27; // @[dec_tlu_ctl.scala 3229:57] + assign io_csr_pkt_csr_micect = _T_646 & _T_27; // @[dec_tlu_ctl.scala 3231:57] + assign io_csr_pkt_csr_miccmect = _T_645 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3232:57] + assign io_csr_pkt_csr_mdccmect = _T_662 & _T_27; // @[dec_tlu_ctl.scala 3233:57] + assign io_csr_pkt_csr_mfdht = _T_672 & _T_27; // @[dec_tlu_ctl.scala 3234:57] + assign io_csr_pkt_csr_mfdhs = _T_680 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3235:57] + assign io_csr_pkt_csr_dicawics = _T_696 & _T_27; // @[dec_tlu_ctl.scala 3236:57] + assign io_csr_pkt_csr_dicad0h = _T_704 & _T_17; // @[dec_tlu_ctl.scala 3237:57] + assign io_csr_pkt_csr_dicad0 = _T_715 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3238:57] + assign io_csr_pkt_csr_dicad1 = _T_726 & _T_27; // @[dec_tlu_ctl.scala 3239:57] + assign io_csr_pkt_csr_dicago = _T_726 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3240:57] + assign io_csr_pkt_presync = _T_807 | _T_822; // @[dec_tlu_ctl.scala 3241:34] + assign io_csr_pkt_postsync = _T_903 | _T_915; // @[dec_tlu_ctl.scala 3243:30] + assign io_csr_pkt_legal = _T_1565 | _T_1581; // @[dec_tlu_ctl.scala 3246:26] +endmodule +module dec_tlu_ctl( + input clock, + input reset, + output [29:0] io_tlu_exu_dec_tlu_meihap, + output io_tlu_exu_dec_tlu_flush_lower_r, + output [30:0] io_tlu_exu_dec_tlu_flush_path_r, + input [1:0] io_tlu_exu_exu_i0_br_hist_r, + input io_tlu_exu_exu_i0_br_error_r, + input io_tlu_exu_exu_i0_br_start_error_r, + input io_tlu_exu_exu_i0_br_valid_r, + input io_tlu_exu_exu_i0_br_mp_r, + input io_tlu_exu_exu_i0_br_middle_r, + input io_tlu_exu_exu_pmu_i0_br_misp, + input io_tlu_exu_exu_pmu_i0_br_ataken, + input io_tlu_exu_exu_pmu_i0_pc4, + input [30:0] io_tlu_exu_exu_npc_r, + input io_tlu_dma_dma_pmu_dccm_read, + input io_tlu_dma_dma_pmu_dccm_write, + input io_tlu_dma_dma_pmu_any_read, + input io_tlu_dma_dma_pmu_any_write, + output [2:0] io_tlu_dma_dec_tlu_dma_qos_prty, + input io_tlu_dma_dma_dccm_stall_any, + input io_tlu_dma_dma_iccm_stall_any, + input io_free_clk, + input io_free_l2clk, + input [30:0] io_rst_vec, + input io_nmi_int, + input [30:0] io_nmi_vec, + input io_i_cpu_halt_req, + input io_i_cpu_run_req, + input io_lsu_fastint_stall_any, + input io_lsu_idle_any, + input io_dec_pmu_instr_decoded, + input io_dec_pmu_decode_stall, + input io_dec_pmu_presync_stall, + input io_dec_pmu_postsync_stall, + input io_lsu_store_stall_any, + input [30:0] io_lsu_fir_addr, + input [1:0] io_lsu_fir_error, + input io_iccm_dma_sb_error, + input io_lsu_error_pkt_r_valid, + input io_lsu_error_pkt_r_bits_single_ecc_error, + input io_lsu_error_pkt_r_bits_inst_type, + input io_lsu_error_pkt_r_bits_exc_type, + input [3:0] io_lsu_error_pkt_r_bits_mscause, + input [31:0] io_lsu_error_pkt_r_bits_addr, + input io_lsu_single_ecc_error_incr, + input io_dec_pause_state, + input io_dec_csr_wen_unq_d, + input io_dec_csr_any_unq_d, + input [11:0] io_dec_csr_rdaddr_d, + input io_dec_csr_wen_r, + input [11:0] io_dec_csr_wraddr_r, + input [31:0] io_dec_csr_wrdata_r, + input io_dec_csr_stall_int_ff, + input io_dec_tlu_i0_valid_r, + input [30:0] io_dec_tlu_i0_pc_r, + input io_dec_tlu_packet_r_legal, + input io_dec_tlu_packet_r_icaf, + input io_dec_tlu_packet_r_icaf_second, + input [1:0] io_dec_tlu_packet_r_icaf_type, + input io_dec_tlu_packet_r_fence_i, + input [3:0] io_dec_tlu_packet_r_i0trigger, + input [3:0] io_dec_tlu_packet_r_pmu_i0_itype, + input io_dec_tlu_packet_r_pmu_i0_br_unpred, + input io_dec_tlu_packet_r_pmu_divide, + input io_dec_tlu_packet_r_pmu_lsu_misaligned, + input [31:0] io_dec_illegal_inst, + input io_dec_i0_decode_d, + input io_exu_i0_br_way_r, + output io_dec_tlu_core_empty, + output io_dec_dbg_cmd_done, + output io_dec_dbg_cmd_fail, + output io_dec_tlu_dbg_halted, + output io_dec_tlu_debug_mode, + output io_dec_tlu_resume_ack, + output io_dec_tlu_debug_stall, + output io_dec_tlu_mpc_halted_only, + output io_dec_tlu_flush_extint, + input io_dbg_halt_req, + input io_dbg_resume_req, + input io_dec_div_active, + output io_trigger_pkt_any_0_select, + output io_trigger_pkt_any_0_match_pkt, + output io_trigger_pkt_any_0_store, + output io_trigger_pkt_any_0_load, + output io_trigger_pkt_any_0_execute, + output io_trigger_pkt_any_0_m, + output [31:0] io_trigger_pkt_any_0_tdata2, + output io_trigger_pkt_any_1_select, + output io_trigger_pkt_any_1_match_pkt, + output io_trigger_pkt_any_1_store, + output io_trigger_pkt_any_1_load, + output io_trigger_pkt_any_1_execute, + output io_trigger_pkt_any_1_m, + output [31:0] io_trigger_pkt_any_1_tdata2, + output io_trigger_pkt_any_2_select, + output io_trigger_pkt_any_2_match_pkt, + output io_trigger_pkt_any_2_store, + output io_trigger_pkt_any_2_load, + output io_trigger_pkt_any_2_execute, + output io_trigger_pkt_any_2_m, + output [31:0] io_trigger_pkt_any_2_tdata2, + output io_trigger_pkt_any_3_select, + output io_trigger_pkt_any_3_match_pkt, + output io_trigger_pkt_any_3_store, + output io_trigger_pkt_any_3_load, + output io_trigger_pkt_any_3_execute, + output io_trigger_pkt_any_3_m, + output [31:0] io_trigger_pkt_any_3_tdata2, + input io_timer_int, + input io_soft_int, + output io_o_cpu_halt_status, + output io_o_cpu_halt_ack, + output io_o_cpu_run_ack, + output io_o_debug_mode_status, + input [27:0] io_core_id, + input io_mpc_debug_halt_req, + input io_mpc_debug_run_req, + input io_mpc_reset_run_req, + output io_mpc_debug_halt_ack, + output io_mpc_debug_run_ack, + output io_debug_brkpt_status, + output [31:0] io_dec_csr_rddata_d, + output io_dec_csr_legal_d, + output io_dec_tlu_i0_kill_writeb_wb, + output io_dec_tlu_i0_kill_writeb_r, + output io_dec_tlu_wr_pause_r, + output io_dec_tlu_flush_pause_r, + output io_dec_tlu_presync_d, + output io_dec_tlu_postsync_d, + output io_dec_tlu_perfcnt0, + output io_dec_tlu_perfcnt1, + output io_dec_tlu_perfcnt2, + output io_dec_tlu_perfcnt3, + output io_dec_tlu_i0_exc_valid_wb1, + output io_dec_tlu_i0_valid_wb1, + output io_dec_tlu_int_valid_wb1, + output [4:0] io_dec_tlu_exc_cause_wb1, + output [31:0] io_dec_tlu_mtval_wb1, + output io_dec_tlu_pipelining_disable, + output io_dec_tlu_trace_disable, + output io_dec_tlu_misc_clk_override, + output io_dec_tlu_dec_clk_override, + output io_dec_tlu_ifu_clk_override, + output io_dec_tlu_lsu_clk_override, + output io_dec_tlu_bus_clk_override, + output io_dec_tlu_pic_clk_override, + output io_dec_tlu_dccm_clk_override, + output io_dec_tlu_icm_clk_override, + output io_dec_tlu_flush_lower_wb, + input io_ifu_pmu_instr_aligned, + output io_tlu_bp_dec_tlu_br0_r_pkt_valid, + output [1:0] io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist, + output io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error, + output io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error, + output io_tlu_bp_dec_tlu_br0_r_pkt_bits_way, + output io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle, + output io_tlu_bp_dec_tlu_flush_leak_one_wb, + output io_tlu_bp_dec_tlu_bpred_disable, + output io_tlu_ifc_dec_tlu_flush_noredir_wb, + output [31:0] io_tlu_ifc_dec_tlu_mrac_ff, + input io_tlu_ifc_ifu_pmu_fetch_stall, + output io_tlu_mem_dec_tlu_flush_err_wb, + output io_tlu_mem_dec_tlu_i0_commit_cmt, + output io_tlu_mem_dec_tlu_force_halt, + output io_tlu_mem_dec_tlu_fence_i_wb, + output [70:0] io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata, + output [16:0] io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics, + output io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid, + output io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid, + output io_tlu_mem_dec_tlu_core_ecc_disable, + input io_tlu_mem_ifu_pmu_ic_miss, + input io_tlu_mem_ifu_pmu_ic_hit, + input io_tlu_mem_ifu_pmu_bus_error, + input io_tlu_mem_ifu_pmu_bus_busy, + input io_tlu_mem_ifu_pmu_bus_trxn, + input io_tlu_mem_ifu_ic_error_start, + input io_tlu_mem_ifu_iccm_rd_ecc_single_err, + input [70:0] io_tlu_mem_ifu_ic_debug_rd_data, + input io_tlu_mem_ifu_ic_debug_rd_data_valid, + input io_tlu_mem_ifu_miss_state_idle, + input io_tlu_busbuff_lsu_pmu_bus_trxn, + input io_tlu_busbuff_lsu_pmu_bus_misaligned, + input io_tlu_busbuff_lsu_pmu_bus_error, + input io_tlu_busbuff_lsu_pmu_bus_busy, + output io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + output io_tlu_busbuff_dec_tlu_wb_coalescing_disable, + output io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, + input io_tlu_busbuff_lsu_imprecise_error_load_any, + input io_tlu_busbuff_lsu_imprecise_error_store_any, + input [31:0] io_tlu_busbuff_lsu_imprecise_error_addr_any, + input io_lsu_tlu_lsu_pmu_load_external_m, + input io_lsu_tlu_lsu_pmu_store_external_m, + input [7:0] io_dec_pic_pic_claimid, + input [3:0] io_dec_pic_pic_pl, + input io_dec_pic_mhwakeup, + output [3:0] io_dec_pic_dec_tlu_meicurpl, + output [3:0] io_dec_pic_dec_tlu_meipt, + input io_dec_pic_mexintpend +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; +`endif // RANDOMIZE_REG_INIT + wire int_exc_clock; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_reset; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_mhwakeup_ready; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_ext_int_ready; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_ce_int_ready; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_soft_int_ready; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_timer_int_ready; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_int_timer0_int_hold; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_int_timer1_int_hold; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_ext_int_start; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_ext_int_start_d2; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_ext_int_freeze; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_ext_int; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_fast_int_meicpct; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_ignore_ext_int_due_to_lsu_stall; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_ce_int; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_soft_int; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_timer_int; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_reset; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_nmi; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_synchronous_flush_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dec_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_dec_tlu_flush_path_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 282:29] + wire [4:0] int_exc_io_exc_cause_wb; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_i0_valid_wb; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_trigger_hit_r_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_nmi_r_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 282:29] + wire [4:0] int_exc_io_exc_cause_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dec_csr_stall_int_ff; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 282:29] + wire [5:0] int_exc_io_mip; // @[dec_tlu_ctl.scala 282:29] + wire [5:0] int_exc_io_mie_ns; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_mret_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dcsr_single_step_running; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 282:29] + wire [1:0] int_exc_io_lsu_fir_error; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_lsu_fastint_stall_any; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_reset_delayed; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_nmi_int_detected; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 282:29] + wire [15:0] int_exc_io_dcsr; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_mtvec; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_pause_expired_r; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_nmi_vec; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_fence_i_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_rfpc_i0_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_halt; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_rst_vec; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_lsu_fir_addr; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_npc_r; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_mepc; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_debug_resume_req_f; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_dpc; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_npc_r_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_ebreak_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_ecall_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_illegal_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_inst_acc_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 282:29] + wire csr_clock; // @[dec_tlu_ctl.scala 283:23] + wire csr_reset; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_free_l2clk; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_free_clk; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 283:23] + wire [11:0] csr_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 283:23] + wire [11:0] csr_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 283:23] + wire [70:0] csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 283:23] + wire [16:0] csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 283:23] + wire [1:0] csr_io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 283:23] + wire [3:0] csr_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 283:23] + wire [4:0] csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dma_pmu_any_write; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dma_pmu_any_read; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 283:23] + wire [30:0] csr_io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_ifu_clk_override; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 283:23] + wire [70:0] csr_io_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 283:23] + wire [3:0] csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 283:23] + wire [3:0] csr_io_pic_pl; // @[dec_tlu_ctl.scala 283:23] + wire [3:0] csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 283:23] + wire [29:0] csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 283:23] + wire [7:0] csr_io_pic_claimid; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 283:23] + wire [2:0] csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_trace_disable; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_dec_illegal_inst; // @[dec_tlu_ctl.scala 283:23] + wire [3:0] csr_io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_mexintpend; // @[dec_tlu_ctl.scala 283:23] + wire [30:0] csr_io_exu_npc_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 283:23] + wire [30:0] csr_io_rst_vec; // @[dec_tlu_ctl.scala 283:23] + wire [27:0] csr_io_core_id; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_rfpc_i0_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 283:23] + wire [1:0] csr_io_mstatus; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_mret_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 283:23] + wire [15:0] csr_io_dcsr; // @[dec_tlu_ctl.scala 283:23] + wire [30:0] csr_io_mtvec; // @[dec_tlu_ctl.scala 283:23] + wire [5:0] csr_io_mip; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_timer_int_sync; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_soft_int_sync; // @[dec_tlu_ctl.scala 283:23] + wire [5:0] csr_io_mie_ns; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_wr_clk; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 283:23] + wire [1:0] csr_io_lsu_fir_error; // @[dec_tlu_ctl.scala 283:23] + wire [30:0] csr_io_npc_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 283:23] + wire [30:0] csr_io_tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 283:23] + wire [30:0] csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_reset_delayed; // @[dec_tlu_ctl.scala 283:23] + wire [30:0] csr_io_mepc; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_single_ecc_error_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_e4e5_int_clk; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_inst_acc_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_inst_acc_second_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_take_nmi; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_lsu_error_pkt_addr_r; // @[dec_tlu_ctl.scala 283:23] + wire [4:0] csr_io_exc_cause_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_i0_valid_wb; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 283:23] + wire [4:0] csr_io_exc_cause_wb; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ebreak_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ecall_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_illegal_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_mdseac_locked_ns; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ext_int_freeze; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_take_ext_int_start_d2; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ic_perr_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_iccm_sbecc_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_debug_halt_req_f; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_force_halt; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_take_ext_int_start; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_hit_r_d1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_debug_halt_req; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_allow_dbg_halt_csr_write; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_enter_debug_halt_req; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_request_debug_mode_done; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_request_debug_mode_r; // @[dec_tlu_ctl.scala 283:23] + wire [30:0] csr_io_dpc; // @[dec_tlu_ctl.scala 283:23] + wire [3:0] csr_io_update_hit_bit_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_take_timer_int; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_take_ext_int; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_br0_error_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 283:23] + wire [9:0] csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 283:23] + wire [9:0] csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 283:23] + wire [9:0] csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 283:23] + wire [9:0] csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 283:23] + wire [3:0] csr_io_trigger_enabled; // @[dec_tlu_ctl.scala 283:23] + wire int_timers_clock; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_reset; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_free_l2clk; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_csr_wr_clk; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 284:30] + wire [11:0] int_timers_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 284:30] + wire [31:0] int_timers_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_csr_mitctl0; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_csr_mitctl1; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_csr_mitb0; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_csr_mitb1; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_csr_mitcnt0; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_csr_mitcnt1; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_dec_pause_state; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 284:30] + wire [31:0] int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 284:30] + wire [11:0] csr_read_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 1017:28] + reg dbg_halt_state_f; // @[Reg.scala 27:20] + wire _T = ~dbg_halt_state_f; // @[dec_tlu_ctl.scala 281:39] + reg mpc_halt_state_f; // @[Reg.scala 27:20] + wire _T_1 = _T & mpc_halt_state_f; // @[dec_tlu_ctl.scala 281:57] + wire [2:0] _T_3 = {io_i_cpu_run_req,io_mpc_debug_halt_req,io_mpc_debug_run_req}; // @[Cat.scala 29:58] + wire [3:0] _T_6 = {io_nmi_int,io_timer_int,io_soft_int,io_i_cpu_halt_req}; // @[Cat.scala 29:58] + reg [6:0] _T_8; // @[lib.scala 37:81] + reg [6:0] syncro_ff; // @[lib.scala 37:58] + wire nmi_int_sync = syncro_ff[6]; // @[dec_tlu_ctl.scala 311:75] + wire i_cpu_halt_req_sync = syncro_ff[3]; // @[dec_tlu_ctl.scala 314:59] + wire i_cpu_run_req_sync = syncro_ff[2]; // @[dec_tlu_ctl.scala 315:59] + wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[dec_tlu_ctl.scala 316:51] + wire mpc_debug_run_req_sync = syncro_ff[0]; // @[dec_tlu_ctl.scala 317:59] + wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 1010:37] + reg debug_mode_status; // @[Reg.scala 27:20] + reg i_cpu_run_req_d1_raw; // @[Reg.scala 27:20] + reg nmi_int_delayed; // @[Reg.scala 27:20] + wire _T_76 = ~nmi_int_delayed; // @[dec_tlu_ctl.scala 360:45] + wire _T_77 = nmi_int_sync & _T_76; // @[dec_tlu_ctl.scala 360:43] + wire mdseac_locked_f = csr_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 965:27] + wire _T_72 = ~mdseac_locked_f; // @[dec_tlu_ctl.scala 357:32] + wire _T_73 = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 357:96] + wire _T_74 = _T_72 & _T_73; // @[dec_tlu_ctl.scala 357:49] + reg nmi_int_detected_f; // @[Reg.scala 27:20] + wire _T_99 = ~nmi_int_detected_f; // @[dec_tlu_ctl.scala 365:25] + wire _T_100 = _T_99 & csr_io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 365:45] + wire _T_101 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 365:95] + wire nmi_fir_type = _T_100 & _T_101; // @[dec_tlu_ctl.scala 365:76] + wire _T_75 = ~nmi_fir_type; // @[dec_tlu_ctl.scala 357:146] + wire nmi_lsu_detected = _T_74 & _T_75; // @[dec_tlu_ctl.scala 357:144] + wire _T_78 = _T_77 | nmi_lsu_detected; // @[dec_tlu_ctl.scala 360:63] + wire take_nmi_r_d1 = int_exc_io_take_nmi_r_d1; // @[dec_tlu_ctl.scala 814:43] + wire _T_79 = ~take_nmi_r_d1; // @[dec_tlu_ctl.scala 360:106] + wire _T_80 = nmi_int_detected_f & _T_79; // @[dec_tlu_ctl.scala 360:104] + wire _T_81 = _T_78 | _T_80; // @[dec_tlu_ctl.scala 360:82] + wire nmi_int_detected = _T_81 | nmi_fir_type; // @[dec_tlu_ctl.scala 360:122] + wire timer_int_ready = int_exc_io_timer_int_ready; // @[dec_tlu_ctl.scala 784:43] + wire _T_576 = nmi_int_detected | timer_int_ready; // @[dec_tlu_ctl.scala 633:71] + wire soft_int_ready = int_exc_io_soft_int_ready; // @[dec_tlu_ctl.scala 783:43] + wire _T_577 = _T_576 | soft_int_ready; // @[dec_tlu_ctl.scala 633:89] + reg int_timer0_int_hold_f; // @[Reg.scala 27:20] + wire _T_578 = _T_577 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 633:106] + reg int_timer1_int_hold_f; // @[Reg.scala 27:20] + wire _T_579 = _T_578 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 633:130] + wire mhwakeup_ready = int_exc_io_mhwakeup_ready; // @[dec_tlu_ctl.scala 780:43] + wire _T_580 = io_dec_pic_mhwakeup & mhwakeup_ready; // @[dec_tlu_ctl.scala 633:177] + wire _T_581 = _T_579 | _T_580; // @[dec_tlu_ctl.scala 633:154] + wire _T_582 = _T_581 & io_o_cpu_halt_status; // @[dec_tlu_ctl.scala 633:196] + reg i_cpu_halt_req_d1; // @[Reg.scala 27:20] + wire _T_583 = ~i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 633:221] + wire _T_584 = _T_582 & _T_583; // @[dec_tlu_ctl.scala 633:219] + wire i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_584; // @[dec_tlu_ctl.scala 633:50] + wire interrupt_valid_r = int_exc_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 816:43] + wire interrupt_valid_r_d1 = int_exc_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 812:43] + reg reset_detect; // @[Reg.scala 27:20] + reg reset_detected; // @[Reg.scala 27:20] + wire reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 369:64] + wire _T_345 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 504:28] + reg dec_pause_state_f; // @[Reg.scala 27:20] + wire _T_346 = _T_345 & dec_pause_state_f; // @[dec_tlu_ctl.scala 504:48] + wire ext_int_ready = int_exc_io_ext_int_ready; // @[dec_tlu_ctl.scala 781:43] + wire ce_int_ready = int_exc_io_ce_int_ready; // @[dec_tlu_ctl.scala 782:43] + wire _T_347 = ext_int_ready | ce_int_ready; // @[dec_tlu_ctl.scala 504:86] + wire _T_348 = _T_347 | timer_int_ready; // @[dec_tlu_ctl.scala 504:101] + wire _T_349 = _T_348 | soft_int_ready; // @[dec_tlu_ctl.scala 504:119] + wire _T_350 = _T_349 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 504:136] + wire _T_351 = _T_350 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 504:160] + wire _T_352 = _T_351 | nmi_int_detected; // @[dec_tlu_ctl.scala 504:184] + wire _T_353 = _T_352 | csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 504:203] + wire _T_354 = ~_T_353; // @[dec_tlu_ctl.scala 504:70] + wire _T_355 = _T_346 & _T_354; // @[dec_tlu_ctl.scala 504:68] + wire _T_356 = ~interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 504:233] + wire _T_357 = _T_355 & _T_356; // @[dec_tlu_ctl.scala 504:231] + reg debug_halt_req_f; // @[Reg.scala 27:20] + wire _T_358 = ~debug_halt_req_f; // @[dec_tlu_ctl.scala 504:257] + wire _T_359 = _T_357 & _T_358; // @[dec_tlu_ctl.scala 504:255] + reg pmu_fw_halt_req_f; // @[Reg.scala 27:20] + wire _T_360 = ~pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 504:277] + wire _T_361 = _T_359 & _T_360; // @[dec_tlu_ctl.scala 504:275] + reg halt_taken_f; // @[Reg.scala 27:20] + wire _T_362 = ~halt_taken_f; // @[dec_tlu_ctl.scala 504:298] + reg ifu_ic_error_start_f; // @[Reg.scala 27:20] + wire _T_680 = ~csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 709:49] + wire _T_681 = ifu_ic_error_start_f & _T_680; // @[dec_tlu_ctl.scala 709:47] + wire _T_682 = ~debug_mode_status; // @[dec_tlu_ctl.scala 709:78] + reg debug_resume_req_f_raw; // @[Reg.scala 27:20] + wire _T_333 = ~io_dbg_halt_req; // @[dec_tlu_ctl.scala 489:56] + wire debug_resume_req_f = debug_resume_req_f_raw & _T_333; // @[dec_tlu_ctl.scala 489:54] + wire [15:0] dcsr = csr_io_dcsr; // @[dec_tlu_ctl.scala 1013:37] + wire _T_255 = debug_resume_req_f & dcsr[2]; // @[dec_tlu_ctl.scala 459:60] + reg dcsr_single_step_running_f; // @[Reg.scala 27:20] + reg dcsr_single_step_done_f; // @[Reg.scala 27:20] + wire _T_256 = ~dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 459:111] + wire _T_257 = dcsr_single_step_running_f & _T_256; // @[dec_tlu_ctl.scala 459:109] + wire dcsr_single_step_running = _T_255 | _T_257; // @[dec_tlu_ctl.scala 459:79] + wire _T_683 = _T_682 | dcsr_single_step_running; // @[dec_tlu_ctl.scala 709:104] + wire _T_684 = _T_681 & _T_683; // @[dec_tlu_ctl.scala 709:75] + reg internal_pmu_fw_halt_mode_f; // @[Reg.scala 27:20] + wire _T_685 = ~internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 709:134] + wire ic_perr_r = _T_684 & _T_685; // @[dec_tlu_ctl.scala 709:132] + reg ifu_iccm_rd_ecc_single_err_f; // @[Reg.scala 27:20] + wire _T_688 = ifu_iccm_rd_ecc_single_err_f & _T_680; // @[dec_tlu_ctl.scala 710:55] + wire _T_691 = _T_688 & _T_683; // @[dec_tlu_ctl.scala 710:83] + wire iccm_sbecc_r = _T_691 & _T_685; // @[dec_tlu_ctl.scala 710:140] + wire _T_23 = io_tlu_mem_ifu_ic_error_start ^ ifu_ic_error_start_f; // @[lib.scala 470:21] + wire _T_24 = |_T_23; // @[lib.scala 470:29] + wire _T_26 = io_tlu_mem_ifu_iccm_rd_ecc_single_err ^ ifu_iccm_rd_ecc_single_err_f; // @[lib.scala 470:21] + wire _T_27 = |_T_26; // @[lib.scala 470:29] + reg iccm_repair_state_d1; // @[Reg.scala 27:20] + wire _T_623 = ~io_tlu_exu_dec_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 666:72] + wire _T_624 = iccm_repair_state_d1 & _T_623; // @[dec_tlu_ctl.scala 666:70] + wire iccm_repair_state_ns = iccm_sbecc_r | _T_624; // @[dec_tlu_ctl.scala 666:46] + wire _T_29 = iccm_repair_state_ns ^ iccm_repair_state_d1; // @[lib.scala 448:21] + wire _T_30 = |_T_29; // @[lib.scala 448:29] + reg dbg_halt_req_held; // @[Reg.scala 27:20] + wire _T_184 = io_dbg_halt_req | dbg_halt_req_held; // @[dec_tlu_ctl.scala 418:48] + wire dbg_halt_req_final = _T_184 & _T_680; // @[dec_tlu_ctl.scala 418:69] + wire mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & _T_680; // @[dec_tlu_ctl.scala 376:67] + wire _T_187 = dbg_halt_req_final | mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 421:50] + wire _T_188 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 421:95] + wire _T_189 = reset_delayed & _T_188; // @[dec_tlu_ctl.scala 421:93] + wire _T_190 = _T_187 | _T_189; // @[dec_tlu_ctl.scala 421:76] + wire _T_192 = _T_190 & _T_682; // @[dec_tlu_ctl.scala 421:119] + wire debug_halt_req = _T_192 & _T_680; // @[dec_tlu_ctl.scala 421:147] + wire _T_231 = _T_682 & debug_halt_req; // @[dec_tlu_ctl.scala 441:63] + wire _T_232 = _T_231 | dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 441:81] + reg trigger_hit_dmode_r_d1; // @[Reg.scala 27:20] + wire _T_233 = _T_232 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 441:107] + reg ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 718:64] + wire enter_debug_halt_req = _T_233 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 441:132] + wire force_halt = csr_io_force_halt; // @[dec_tlu_ctl.scala 1007:37] + reg lsu_idle_any_f; // @[Reg.scala 27:20] + wire _T_220 = io_lsu_idle_any & lsu_idle_any_f; // @[dec_tlu_ctl.scala 435:53] + wire _T_221 = _T_220 & io_tlu_mem_ifu_miss_state_idle; // @[dec_tlu_ctl.scala 435:70] + reg ifu_miss_state_idle_f; // @[Reg.scala 27:20] + wire _T_222 = _T_221 & ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 435:103] + wire _T_223 = ~debug_halt_req; // @[dec_tlu_ctl.scala 435:129] + wire _T_224 = _T_222 & _T_223; // @[dec_tlu_ctl.scala 435:127] + reg debug_halt_req_d1; // @[Reg.scala 27:20] + wire _T_225 = ~debug_halt_req_d1; // @[dec_tlu_ctl.scala 435:147] + wire _T_226 = _T_224 & _T_225; // @[dec_tlu_ctl.scala 435:145] + wire _T_227 = ~io_dec_div_active; // @[dec_tlu_ctl.scala 435:168] + wire _T_228 = _T_226 & _T_227; // @[dec_tlu_ctl.scala 435:166] + wire core_empty = force_halt | _T_228; // @[dec_tlu_ctl.scala 435:34] + wire _T_241 = debug_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 452:48] + reg dec_tlu_flush_noredir_r_d1; // @[Reg.scala 27:20] + reg dec_tlu_flush_pause_r_d1; // @[Reg.scala 27:20] + wire _T_210 = ~dec_tlu_flush_pause_r_d1; // @[dec_tlu_ctl.scala 431:56] + wire _T_211 = dec_tlu_flush_noredir_r_d1 & _T_210; // @[dec_tlu_ctl.scala 431:54] + wire _T_212 = ~csr_io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 431:84] + wire _T_213 = _T_211 & _T_212; // @[dec_tlu_ctl.scala 431:82] + reg dbg_tlu_halted_f; // @[Reg.scala 27:20] + wire _T_214 = ~dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 431:133] + wire _T_215 = halt_taken_f & _T_214; // @[dec_tlu_ctl.scala 431:131] + reg pmu_fw_tlu_halted_f; // @[Reg.scala 27:20] + wire _T_216 = ~pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 431:153] + wire _T_217 = _T_215 & _T_216; // @[dec_tlu_ctl.scala 431:151] + wire _T_219 = _T_217 & _T_356; // @[dec_tlu_ctl.scala 431:174] + wire halt_taken = _T_213 | _T_219; // @[dec_tlu_ctl.scala 431:115] + wire _T_242 = _T_241 & halt_taken; // @[dec_tlu_ctl.scala 452:61] + wire _T_243 = ~debug_resume_req_f; // @[dec_tlu_ctl.scala 452:97] + wire _T_244 = dbg_tlu_halted_f & _T_243; // @[dec_tlu_ctl.scala 452:95] + wire dbg_tlu_halted = _T_242 | _T_244; // @[dec_tlu_ctl.scala 452:75] + wire _T_245 = ~dbg_tlu_halted; // @[dec_tlu_ctl.scala 454:73] + wire _T_246 = debug_halt_req_f & _T_245; // @[dec_tlu_ctl.scala 454:71] + wire debug_halt_req_ns = enter_debug_halt_req | _T_246; // @[dec_tlu_ctl.scala 454:51] + wire _T_235 = ~dcsr[2]; // @[dec_tlu_ctl.scala 444:106] + wire _T_236 = debug_resume_req_f & _T_235; // @[dec_tlu_ctl.scala 444:104] + wire _T_237 = ~_T_236; // @[dec_tlu_ctl.scala 444:83] + wire _T_238 = debug_mode_status & _T_237; // @[dec_tlu_ctl.scala 444:81] + wire internal_dbg_halt_mode = debug_halt_req_ns | _T_238; // @[dec_tlu_ctl.scala 444:53] + wire _T_37 = internal_dbg_halt_mode ^ debug_mode_status; // @[lib.scala 448:21] + wire _T_38 = |_T_37; // @[lib.scala 448:29] + reg lsu_pmu_load_external_r; // @[Reg.scala 27:20] + wire _T_40 = io_lsu_tlu_lsu_pmu_load_external_m ^ lsu_pmu_load_external_r; // @[lib.scala 470:21] + wire _T_41 = |_T_40; // @[lib.scala 470:29] + reg lsu_pmu_store_external_r; // @[Reg.scala 27:20] + wire _T_43 = io_lsu_tlu_lsu_pmu_store_external_m ^ lsu_pmu_store_external_r; // @[lib.scala 470:21] + wire _T_44 = |_T_43; // @[lib.scala 470:29] + wire tlu_flush_lower_r = int_exc_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 808:43] + reg tlu_flush_lower_r_d1; // @[Reg.scala 27:20] + wire _T_46 = tlu_flush_lower_r ^ tlu_flush_lower_r_d1; // @[lib.scala 448:21] + wire _T_47 = |_T_46; // @[lib.scala 448:29] + wire _T_611 = ~tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 663:49] + wire _T_612 = io_dec_tlu_i0_valid_r & _T_611; // @[dec_tlu_ctl.scala 663:47] + wire _T_613 = io_tlu_exu_exu_i0_br_error_r | io_tlu_exu_exu_i0_br_start_error_r; // @[dec_tlu_ctl.scala 663:103] + wire _T_614 = _T_612 & _T_613; // @[dec_tlu_ctl.scala 663:71] + wire _T_615 = ic_perr_r | iccm_sbecc_r; // @[dec_tlu_ctl.scala 663:156] + wire _T_617 = _T_615 & _T_680; // @[dec_tlu_ctl.scala 663:172] + wire _T_618 = _T_614 | _T_617; // @[dec_tlu_ctl.scala 663:142] + wire _T_431 = io_dec_tlu_flush_lower_wb | io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 545:64] + wire [3:0] _T_433 = _T_431 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_434 = ~_T_433; // @[dec_tlu_ctl.scala 545:29] + wire [3:0] _T_426 = io_dec_tlu_i0_valid_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_428 = _T_426 & io_dec_tlu_packet_r_i0trigger; // @[dec_tlu_ctl.scala 543:58] + wire [9:0] mtdata1_t_3 = csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 162:67 dec_tlu_ctl.scala 1016:39] + wire [9:0] mtdata1_t_2 = csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 162:67 dec_tlu_ctl.scala 1016:39] + wire [9:0] mtdata1_t_1 = csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 162:67 dec_tlu_ctl.scala 1016:39] + wire [9:0] mtdata1_t_0 = csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 162:67 dec_tlu_ctl.scala 1016:39] + wire [3:0] trigger_execute = {mtdata1_t_3[2],mtdata1_t_2[2],mtdata1_t_1[2],mtdata1_t_0[2]}; // @[Cat.scala 29:58] + wire [3:0] trigger_data = {mtdata1_t_3[7],mtdata1_t_2[7],mtdata1_t_1[7],mtdata1_t_0[7]}; // @[Cat.scala 29:58] + wire [3:0] _T_413 = trigger_execute & trigger_data; // @[dec_tlu_ctl.scala 535:62] + wire inst_acc_r_raw = io_dec_tlu_packet_r_icaf & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 712:54] + wire [3:0] _T_415 = inst_acc_r_raw ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_416 = _T_413 & _T_415; // @[dec_tlu_ctl.scala 535:77] + wire [3:0] _T_419 = _T_613 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_420 = _T_416 | _T_419; // @[dec_tlu_ctl.scala 535:103] + wire [3:0] i0_iside_trigger_has_pri_r = ~_T_420; // @[dec_tlu_ctl.scala 535:43] + wire [3:0] _T_429 = _T_428 & i0_iside_trigger_has_pri_r; // @[dec_tlu_ctl.scala 543:95] + wire [3:0] trigger_store = {mtdata1_t_3[1],mtdata1_t_2[1],mtdata1_t_1[1],mtdata1_t_0[1]}; // @[Cat.scala 29:58] + wire [3:0] _T_421 = trigger_store & trigger_data; // @[dec_tlu_ctl.scala 538:56] + wire [3:0] _T_423 = io_lsu_error_pkt_r_valid ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_424 = _T_421 & _T_423; // @[dec_tlu_ctl.scala 538:71] + wire [3:0] i0_lsu_trigger_has_pri_r = ~_T_424; // @[dec_tlu_ctl.scala 538:40] + wire [3:0] _T_430 = _T_429 & i0_lsu_trigger_has_pri_r; // @[dec_tlu_ctl.scala 543:124] + wire [1:0] mstatus = csr_io_mstatus; // @[dec_tlu_ctl.scala 1012:37] + wire _T_393 = mtdata1_t_3[6] | mstatus[0]; // @[dec_tlu_ctl.scala 529:70] + wire _T_395 = _T_393 & mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 529:94] + wire _T_398 = mtdata1_t_2[6] | mstatus[0]; // @[dec_tlu_ctl.scala 530:47] + wire _T_400 = _T_398 & mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 530:71] + wire [1:0] _T_412 = {_T_395,_T_400}; // @[Cat.scala 29:58] + wire _T_403 = mtdata1_t_1[6] | mstatus[0]; // @[dec_tlu_ctl.scala 531:47] + wire _T_405 = _T_403 & mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 531:71] + wire _T_408 = mtdata1_t_0[6] | mstatus[0]; // @[dec_tlu_ctl.scala 532:47] + wire _T_410 = _T_408 & mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 532:71] + wire [1:0] _T_411 = {_T_405,_T_410}; // @[Cat.scala 29:58] + wire [3:0] trigger_enabled = {_T_395,_T_400,_T_405,_T_410}; // @[Cat.scala 29:58] + wire [3:0] i0trigger_qual_r = _T_430 & trigger_enabled; // @[dec_tlu_ctl.scala 543:151] + wire [3:0] i0_trigger_r = _T_434 & i0trigger_qual_r; // @[dec_tlu_ctl.scala 545:90] + wire _T_437 = ~mtdata1_t_2[5]; // @[dec_tlu_ctl.scala 548:65] + wire _T_439 = _T_437 | i0_trigger_r[2]; // @[dec_tlu_ctl.scala 548:94] + wire _T_440 = i0_trigger_r[3] & _T_439; // @[dec_tlu_ctl.scala 548:62] + wire _T_445 = _T_437 | i0_trigger_r[3]; // @[dec_tlu_ctl.scala 549:65] + wire _T_446 = i0_trigger_r[2] & _T_445; // @[dec_tlu_ctl.scala 549:33] + wire _T_449 = ~mtdata1_t_0[5]; // @[dec_tlu_ctl.scala 550:36] + wire _T_451 = _T_449 | i0_trigger_r[0]; // @[dec_tlu_ctl.scala 550:65] + wire _T_452 = i0_trigger_r[1] & _T_451; // @[dec_tlu_ctl.scala 550:33] + wire _T_457 = _T_449 | i0_trigger_r[1]; // @[dec_tlu_ctl.scala 551:65] + wire _T_458 = i0_trigger_r[0] & _T_457; // @[dec_tlu_ctl.scala 551:33] + wire [3:0] i0_trigger_chain_masked_r = {_T_440,_T_446,_T_452,_T_458}; // @[Cat.scala 29:58] + wire i0_trigger_hit_raw_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 555:62] + wire _T_619 = ~i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 663:205] + wire _T_620 = _T_618 & _T_619; // @[dec_tlu_ctl.scala 663:202] + wire _T_592 = io_dec_tlu_i0_valid_r & _T_619; // @[dec_tlu_ctl.scala 651:52] + wire _T_593 = ~io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 651:75] + wire _T_594 = _T_593 & io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec_tlu_ctl.scala 651:110] + wire lsu_i0_rfnpc_r = _T_592 & _T_594; // @[dec_tlu_ctl.scala 651:72] + wire _T_621 = ~lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 663:226] + wire rfpc_i0_r = _T_620 & _T_621; // @[dec_tlu_ctl.scala 663:223] + wire _T_586 = ~io_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 642:62] + wire lsu_exc_valid_r_raw = io_lsu_error_pkt_r_valid & _T_586; // @[dec_tlu_ctl.scala 642:60] + wire _T_587 = io_lsu_error_pkt_r_valid & lsu_exc_valid_r_raw; // @[dec_tlu_ctl.scala 644:45] + wire _T_589 = _T_587 & _T_619; // @[dec_tlu_ctl.scala 644:67] + wire _T_590 = ~rfpc_i0_r; // @[dec_tlu_ctl.scala 644:89] + wire lsu_exc_valid_r = _T_589 & _T_590; // @[dec_tlu_ctl.scala 644:87] + wire _T_606 = rfpc_i0_r | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 657:43] + wire _T_696 = inst_acc_r_raw & _T_590; // @[dec_tlu_ctl.scala 713:38] + wire inst_acc_r = _T_696 & _T_619; // @[dec_tlu_ctl.scala 713:51] + wire _T_607 = _T_606 | inst_acc_r; // @[dec_tlu_ctl.scala 657:58] + wire _T_663 = ~io_dec_tlu_packet_r_legal; // @[dec_tlu_ctl.scala 705:23] + wire _T_664 = _T_663 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 705:52] + wire _T_666 = _T_664 & _T_619; // @[dec_tlu_ctl.scala 705:76] + wire illegal_r = _T_666 & _T_590; // @[dec_tlu_ctl.scala 705:96] + wire _T_608 = illegal_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 657:84] + wire _T_609 = _T_607 | _T_608; // @[dec_tlu_ctl.scala 657:71] + wire tlu_i0_kill_writeb_r = _T_609 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 657:109] + reg _T_52; // @[Reg.scala 27:20] + wire _T_50 = tlu_i0_kill_writeb_r ^ _T_52; // @[lib.scala 448:21] + wire _T_51 = |_T_50; // @[lib.scala 448:29] + reg internal_dbg_halt_mode_f2; // @[Reg.scala 27:20] + wire _T_53 = debug_mode_status ^ internal_dbg_halt_mode_f2; // @[lib.scala 448:21] + wire _T_54 = |_T_53; // @[lib.scala 448:29] + reg _T_59; // @[Reg.scala 27:20] + wire _T_57 = force_halt ^ _T_59; // @[lib.scala 448:21] + wire _T_58 = |_T_57; // @[lib.scala 448:29] + wire _T_60 = nmi_int_sync ^ nmi_int_delayed; // @[lib.scala 470:21] + wire _T_61 = |_T_60; // @[lib.scala 470:29] + wire _T_63 = nmi_int_detected ^ nmi_int_detected_f; // @[lib.scala 448:21] + wire _T_64 = |_T_63; // @[lib.scala 448:29] + wire _T_83 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 362:49] + wire _T_86 = ~_T_80; // @[dec_tlu_ctl.scala 362:98] + wire _T_87 = _T_83 & _T_86; // @[dec_tlu_ctl.scala 362:95] + reg nmi_lsu_load_type_f; // @[Reg.scala 27:20] + wire _T_89 = nmi_lsu_load_type_f & _T_79; // @[dec_tlu_ctl.scala 362:162] + wire nmi_lsu_load_type = _T_87 | _T_89; // @[dec_tlu_ctl.scala 362:138] + wire _T_66 = nmi_lsu_load_type ^ nmi_lsu_load_type_f; // @[lib.scala 448:21] + wire _T_67 = |_T_66; // @[lib.scala 448:29] + wire _T_91 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 363:49] + wire _T_95 = _T_91 & _T_86; // @[dec_tlu_ctl.scala 363:96] + reg nmi_lsu_store_type_f; // @[Reg.scala 27:20] + wire _T_97 = nmi_lsu_store_type_f & _T_79; // @[dec_tlu_ctl.scala 363:162] + wire nmi_lsu_store_type = _T_95 | _T_97; // @[dec_tlu_ctl.scala 363:138] + wire _T_69 = nmi_lsu_store_type ^ nmi_lsu_store_type_f; // @[lib.scala 448:21] + wire _T_70 = |_T_69; // @[lib.scala 448:29] + wire _T_103 = 1'h1 ^ reset_detect; // @[lib.scala 448:21] + wire _T_104 = |_T_103; // @[lib.scala 448:29] + wire _T_107 = |reset_delayed; // @[lib.scala 448:29] + reg mpc_debug_halt_req_sync_f; // @[Reg.scala 27:20] + wire _T_111 = mpc_debug_halt_req_sync ^ mpc_debug_halt_req_sync_f; // @[lib.scala 470:21] + wire _T_112 = |_T_111; // @[lib.scala 470:29] + reg mpc_debug_run_req_sync_f; // @[Reg.scala 27:20] + wire _T_114 = mpc_debug_run_req_sync ^ mpc_debug_run_req_sync_f; // @[lib.scala 470:21] + wire _T_115 = |_T_114; // @[lib.scala 470:29] + wire _T_144 = ~mpc_debug_halt_req_sync_f; // @[dec_tlu_ctl.scala 390:71] + wire mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & _T_144; // @[dec_tlu_ctl.scala 390:69] + wire _T_146 = mpc_halt_state_f | mpc_debug_halt_req_sync_pulse; // @[dec_tlu_ctl.scala 393:48] + wire _T_149 = _T_146 | _T_189; // @[dec_tlu_ctl.scala 393:80] + wire _T_150 = ~mpc_debug_run_req_sync; // @[dec_tlu_ctl.scala 393:125] + wire mpc_halt_state_ns = _T_149 & _T_150; // @[dec_tlu_ctl.scala 393:123] + wire _T_118 = mpc_halt_state_ns ^ mpc_halt_state_f; // @[lib.scala 448:21] + wire _T_119 = |_T_118; // @[lib.scala 448:29] + reg mpc_run_state_f; // @[Reg.scala 27:20] + wire _T_145 = ~mpc_debug_run_req_sync_f; // @[dec_tlu_ctl.scala 391:70] + wire mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & _T_145; // @[dec_tlu_ctl.scala 391:68] + reg mpc_debug_run_ack_f; // @[Reg.scala 27:20] + wire _T_152 = ~mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 394:80] + wire _T_153 = mpc_debug_run_req_sync_pulse & _T_152; // @[dec_tlu_ctl.scala 394:78] + wire _T_154 = mpc_run_state_f | _T_153; // @[dec_tlu_ctl.scala 394:46] + wire _T_155 = ~dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 394:133] + wire _T_156 = debug_mode_status & _T_155; // @[dec_tlu_ctl.scala 394:131] + wire mpc_run_state_ns = _T_154 & _T_156; // @[dec_tlu_ctl.scala 394:103] + wire _T_121 = mpc_run_state_ns ^ mpc_run_state_f; // @[lib.scala 448:21] + wire _T_122 = |_T_121; // @[lib.scala 448:29] + wire debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 404:59] + reg debug_brkpt_status_f; // @[Reg.scala 27:20] + wire _T_170 = debug_brkpt_valid | debug_brkpt_status_f; // @[dec_tlu_ctl.scala 405:53] + wire _T_172 = internal_dbg_halt_mode & _T_155; // @[dec_tlu_ctl.scala 405:103] + wire debug_brkpt_status_ns = _T_170 & _T_172; // @[dec_tlu_ctl.scala 405:77] + wire _T_124 = debug_brkpt_status_ns ^ debug_brkpt_status_f; // @[lib.scala 448:21] + wire _T_125 = |_T_124; // @[lib.scala 448:29] + wire _T_174 = mpc_halt_state_f & debug_mode_status; // @[dec_tlu_ctl.scala 408:51] + wire _T_175 = _T_174 & mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 408:78] + wire mpc_debug_halt_ack_ns = _T_175 & core_empty; // @[dec_tlu_ctl.scala 408:104] + reg mpc_debug_halt_ack_f; // @[Reg.scala 27:20] + wire _T_127 = mpc_debug_halt_ack_ns ^ mpc_debug_halt_ack_f; // @[lib.scala 448:21] + wire _T_128 = |_T_127; // @[lib.scala 448:29] + wire _T_158 = dbg_halt_req_final | dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 397:70] + wire _T_159 = _T_158 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 397:96] + wire _T_160 = _T_159 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 397:121] + wire _T_161 = dbg_halt_state_f | _T_160; // @[dec_tlu_ctl.scala 397:48] + wire _T_162 = ~io_dbg_resume_req; // @[dec_tlu_ctl.scala 397:153] + wire dbg_halt_state_ns = _T_161 & _T_162; // @[dec_tlu_ctl.scala 397:151] + wire _T_177 = ~dbg_halt_state_ns; // @[dec_tlu_ctl.scala 409:59] + wire _T_178 = mpc_debug_run_req_sync & _T_177; // @[dec_tlu_ctl.scala 409:57] + wire _T_179 = ~mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 409:80] + wire _T_180 = _T_178 & _T_179; // @[dec_tlu_ctl.scala 409:78] + wire _T_181 = mpc_debug_run_ack_f & mpc_debug_run_req_sync; // @[dec_tlu_ctl.scala 409:129] + wire mpc_debug_run_ack_ns = _T_180 | _T_181; // @[dec_tlu_ctl.scala 409:106] + wire _T_130 = mpc_debug_run_ack_ns ^ mpc_debug_run_ack_f; // @[lib.scala 448:21] + wire _T_131 = |_T_130; // @[lib.scala 448:29] + wire _T_134 = dbg_halt_state_ns ^ dbg_halt_state_f; // @[lib.scala 448:21] + wire _T_135 = |_T_134; // @[lib.scala 448:29] + reg dbg_run_state_f; // @[Reg.scala 27:20] + wire _T_164 = dbg_run_state_f | io_dbg_resume_req; // @[dec_tlu_ctl.scala 398:46] + wire dbg_run_state_ns = _T_164 & _T_156; // @[dec_tlu_ctl.scala 398:67] + wire _T_137 = dbg_run_state_ns ^ dbg_run_state_f; // @[lib.scala 448:21] + wire _T_138 = |_T_137; // @[lib.scala 448:29] + reg _T_143; // @[Reg.scala 27:20] + wire _T_141 = _T_1 ^ _T_143; // @[lib.scala 448:21] + wire _T_142 = |_T_141; // @[lib.scala 448:29] + wire dbg_halt_req_held_ns = _T_184 & csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 417:74] + wire _T_196 = mpc_run_state_ns & _T_177; // @[dec_tlu_ctl.scala 423:73] + wire _T_197 = ~mpc_halt_state_ns; // @[dec_tlu_ctl.scala 423:117] + wire _T_198 = dbg_run_state_ns & _T_197; // @[dec_tlu_ctl.scala 423:115] + wire _T_199 = _T_196 | _T_198; // @[dec_tlu_ctl.scala 423:95] + wire debug_resume_req = _T_243 & _T_199; // @[dec_tlu_ctl.scala 423:52] + wire _T_200 = debug_halt_req_f | pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 428:43] + wire synchronous_flush_r = int_exc_io_synchronous_flush_r; // @[dec_tlu_ctl.scala 807:43] + wire _T_201 = ~synchronous_flush_r; // @[dec_tlu_ctl.scala 428:66] + wire _T_202 = _T_200 & _T_201; // @[dec_tlu_ctl.scala 428:64] + wire _T_669 = io_dec_tlu_packet_r_pmu_i0_itype == 4'hc; // @[dec_tlu_ctl.scala 706:57] + wire _T_670 = _T_669 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 706:70] + wire _T_672 = _T_670 & _T_619; // @[dec_tlu_ctl.scala 706:94] + wire mret_r = _T_672 & _T_590; // @[dec_tlu_ctl.scala 706:114] + wire _T_203 = ~mret_r; // @[dec_tlu_ctl.scala 428:89] + wire _T_204 = _T_202 & _T_203; // @[dec_tlu_ctl.scala 428:87] + wire _T_206 = _T_204 & _T_362; // @[dec_tlu_ctl.scala 428:97] + wire _T_207 = ~dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 428:115] + wire _T_208 = _T_206 & _T_207; // @[dec_tlu_ctl.scala 428:113] + wire take_reset = int_exc_io_take_reset; // @[dec_tlu_ctl.scala 805:43] + wire _T_209 = ~take_reset; // @[dec_tlu_ctl.scala 428:145] + wire take_halt = _T_208 & _T_209; // @[dec_tlu_ctl.scala 428:143] + wire _T_248 = debug_resume_req_f & dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 455:49] + wire resume_ack_ns = _T_248 & dbg_run_state_ns; // @[dec_tlu_ctl.scala 455:68] + wire _T_249 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 457:61] + wire _T_250 = io_dec_tlu_i0_valid_r & _T_249; // @[dec_tlu_ctl.scala 457:59] + wire _T_252 = _T_250 & dcsr[2]; // @[dec_tlu_ctl.scala 457:84] + wire dcsr_single_step_done = _T_252 & _T_590; // @[dec_tlu_ctl.scala 457:102] + wire _T_463 = mtdata1_t_3[6] & mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 561:69] + wire _T_466 = mtdata1_t_2[6] & mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 562:46] + wire _T_469 = _T_466 & _T_437; // @[dec_tlu_ctl.scala 562:76] + wire _T_472 = mtdata1_t_1[6] & mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 563:46] + wire _T_475 = mtdata1_t_0[6] & mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 564:46] + wire _T_478 = _T_475 & _T_449; // @[dec_tlu_ctl.scala 564:76] + wire [3:0] trigger_action = {_T_463,_T_469,_T_472,_T_478}; // @[Cat.scala 29:58] + wire [3:0] _T_493 = i0_trigger_chain_masked_r & trigger_action; // @[dec_tlu_ctl.scala 570:62] + wire i0_trigger_action_r = |_T_493; // @[dec_tlu_ctl.scala 570:80] + wire trigger_hit_dmode_r = i0_trigger_hit_raw_r & i0_trigger_action_r; // @[dec_tlu_ctl.scala 572:50] + wire _T_699 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h8; // @[dec_tlu_ctl.scala 716:69] + wire _T_700 = _T_699 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 716:82] + wire _T_702 = _T_700 & _T_619; // @[dec_tlu_ctl.scala 716:106] + wire _T_704 = _T_702 & dcsr[15]; // @[dec_tlu_ctl.scala 716:126] + wire ebreak_to_debug_mode_r = _T_704 & _T_590; // @[dec_tlu_ctl.scala 716:147] + wire _T_258 = trigger_hit_dmode_r | ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 464:57] + reg request_debug_mode_r_d1; // @[Reg.scala 27:20] + wire _T_260 = request_debug_mode_r_d1 & _T_586; // @[dec_tlu_ctl.scala 464:110] + wire request_debug_mode_r = _T_258 | _T_260; // @[dec_tlu_ctl.scala 464:83] + reg request_debug_mode_done_f; // @[Reg.scala 27:20] + wire _T_261 = request_debug_mode_r_d1 | request_debug_mode_done_f; // @[dec_tlu_ctl.scala 466:64] + wire request_debug_mode_done = _T_261 & _T_214; // @[dec_tlu_ctl.scala 466:93] + wire _T_264 = io_tlu_ifc_dec_tlu_flush_noredir_wb ^ dec_tlu_flush_noredir_r_d1; // @[lib.scala 470:21] + wire _T_265 = |_T_264; // @[lib.scala 470:29] + wire _T_268 = halt_taken ^ halt_taken_f; // @[lib.scala 448:21] + wire _T_269 = |_T_268; // @[lib.scala 448:29] + wire _T_272 = io_lsu_idle_any ^ lsu_idle_any_f; // @[lib.scala 448:21] + wire _T_273 = |_T_272; // @[lib.scala 448:29] + wire _T_276 = io_tlu_mem_ifu_miss_state_idle ^ ifu_miss_state_idle_f; // @[lib.scala 470:21] + wire _T_277 = |_T_276; // @[lib.scala 470:29] + wire _T_280 = dbg_tlu_halted ^ dbg_tlu_halted_f; // @[lib.scala 448:21] + wire _T_281 = |_T_280; // @[lib.scala 448:29] + reg _T_286; // @[Reg.scala 27:20] + wire _T_284 = resume_ack_ns ^ _T_286; // @[lib.scala 448:21] + wire _T_285 = |_T_284; // @[lib.scala 448:29] + wire _T_288 = debug_halt_req_ns ^ debug_halt_req_f; // @[lib.scala 448:21] + wire _T_289 = |_T_288; // @[lib.scala 448:29] + wire _T_292 = debug_resume_req ^ debug_resume_req_f_raw; // @[lib.scala 448:21] + wire _T_293 = |_T_292; // @[lib.scala 448:29] + wire _T_296 = trigger_hit_dmode_r ^ trigger_hit_dmode_r_d1; // @[lib.scala 448:21] + wire _T_297 = |_T_296; // @[lib.scala 448:29] + wire _T_300 = dcsr_single_step_done ^ dcsr_single_step_done_f; // @[lib.scala 448:21] + wire _T_301 = |_T_300; // @[lib.scala 448:29] + wire _T_304 = debug_halt_req ^ debug_halt_req_d1; // @[lib.scala 448:21] + wire _T_305 = |_T_304; // @[lib.scala 448:29] + reg dec_tlu_wr_pause_r_d1; // @[Reg.scala 27:20] + wire _T_307 = io_dec_tlu_wr_pause_r ^ dec_tlu_wr_pause_r_d1; // @[lib.scala 448:21] + wire _T_308 = |_T_307; // @[lib.scala 448:29] + wire _T_310 = io_dec_pause_state ^ dec_pause_state_f; // @[lib.scala 448:21] + wire _T_311 = |_T_310; // @[lib.scala 448:29] + wire _T_314 = request_debug_mode_r ^ request_debug_mode_r_d1; // @[lib.scala 448:21] + wire _T_315 = |_T_314; // @[lib.scala 448:29] + wire _T_318 = request_debug_mode_done ^ request_debug_mode_done_f; // @[lib.scala 448:21] + wire _T_319 = |_T_318; // @[lib.scala 448:29] + wire _T_322 = dcsr_single_step_running ^ dcsr_single_step_running_f; // @[lib.scala 448:21] + wire _T_323 = |_T_322; // @[lib.scala 448:29] + wire _T_326 = io_dec_tlu_flush_pause_r ^ dec_tlu_flush_pause_r_d1; // @[lib.scala 448:21] + wire _T_327 = |_T_326; // @[lib.scala 448:29] + wire _T_330 = dbg_halt_req_held_ns ^ dbg_halt_req_held; // @[lib.scala 448:21] + wire _T_331 = |_T_330; // @[lib.scala 448:29] + wire _T_675 = io_dec_tlu_packet_r_fence_i & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 708:55] + wire _T_677 = _T_675 & _T_619; // @[dec_tlu_ctl.scala 708:79] + wire fence_i_r = _T_677 & _T_590; // @[dec_tlu_ctl.scala 708:100] + wire _T_335 = fence_i_r & internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 497:71] + wire _T_336 = take_halt | _T_335; // @[dec_tlu_ctl.scala 497:58] + wire _T_337 = _T_336 | io_dec_tlu_flush_pause_r; // @[dec_tlu_ctl.scala 497:97] + wire _T_338 = i0_trigger_hit_raw_r & trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 497:144] + wire _T_339 = _T_337 | _T_338; // @[dec_tlu_ctl.scala 497:124] + wire take_ext_int_start = int_exc_io_take_ext_int_start; // @[dec_tlu_ctl.scala 788:43] + wire _T_341 = ~interrupt_valid_r; // @[dec_tlu_ctl.scala 502:61] + wire _T_342 = dec_tlu_wr_pause_r_d1 & _T_341; // @[dec_tlu_ctl.scala 502:59] + wire _T_343 = ~take_ext_int_start; // @[dec_tlu_ctl.scala 502:82] + wire _T_365 = io_tlu_exu_dec_tlu_flush_lower_r & dcsr[2]; // @[dec_tlu_ctl.scala 506:82] + wire _T_366 = io_dec_tlu_resume_ack | dcsr_single_step_running; // @[dec_tlu_ctl.scala 506:125] + wire _T_367 = _T_365 & _T_366; // @[dec_tlu_ctl.scala 506:100] + wire _T_368 = ~io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec_tlu_ctl.scala 506:155] + wire _T_481 = |i0_trigger_r; // @[dec_tlu_ctl.scala 567:59] + wire _T_483 = _T_481 & _T_590; // @[dec_tlu_ctl.scala 567:63] + wire [3:0] _T_485 = _T_483 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_492 = {i0_trigger_chain_masked_r[3],i0_trigger_r[2],i0_trigger_chain_masked_r[1],i0_trigger_r[0]}; // @[Cat.scala 29:58] + wire _T_495 = ~trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 574:60] + wire _T_496 = ~io_dec_tlu_debug_mode; // @[dec_tlu_ctl.scala 601:62] + wire _T_497 = i_cpu_halt_req_sync & _T_496; // @[dec_tlu_ctl.scala 601:60] + wire i_cpu_halt_req_sync_qual = _T_497 & _T_680; // @[dec_tlu_ctl.scala 601:85] + wire _T_500 = i_cpu_run_req_sync & _T_496; // @[dec_tlu_ctl.scala 602:58] + wire _T_501 = _T_500 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 602:83] + wire i_cpu_run_req_sync_qual = _T_501 & _T_680; // @[dec_tlu_ctl.scala 602:105] + wire _T_503 = i_cpu_halt_req_sync_qual ^ i_cpu_halt_req_d1; // @[lib.scala 448:21] + wire _T_504 = |_T_503; // @[lib.scala 448:29] + wire _T_506 = i_cpu_run_req_sync_qual ^ i_cpu_run_req_d1_raw; // @[lib.scala 448:21] + wire _T_507 = |_T_506; // @[lib.scala 448:29] + wire _T_563 = ~i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 626:51] + wire _T_564 = pmu_fw_tlu_halted_f & _T_563; // @[dec_tlu_ctl.scala 626:49] + wire _T_566 = io_o_cpu_halt_status & _T_563; // @[dec_tlu_ctl.scala 626:94] + wire _T_568 = _T_566 & _T_682; // @[dec_tlu_ctl.scala 626:114] + wire cpu_halt_status = _T_564 | _T_568; // @[dec_tlu_ctl.scala 626:70] + reg _T_512; // @[Reg.scala 27:20] + wire _T_510 = cpu_halt_status ^ _T_512; // @[lib.scala 448:21] + wire _T_511 = |_T_510; // @[lib.scala 448:29] + wire _T_560 = i_cpu_halt_req_d1 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 625:44] + wire _T_561 = io_o_cpu_halt_ack & i_cpu_halt_req_sync; // @[dec_tlu_ctl.scala 625:88] + wire cpu_halt_ack = _T_560 | _T_561; // @[dec_tlu_ctl.scala 625:67] + reg _T_516; // @[Reg.scala 27:20] + wire _T_514 = cpu_halt_ack ^ _T_516; // @[lib.scala 448:21] + wire _T_515 = |_T_514; // @[lib.scala 448:29] + wire _T_571 = _T_216 & i_cpu_run_req_sync; // @[dec_tlu_ctl.scala 627:46] + wire _T_572 = io_o_cpu_halt_status & i_cpu_run_req_d1_raw; // @[dec_tlu_ctl.scala 627:92] + wire _T_573 = _T_571 | _T_572; // @[dec_tlu_ctl.scala 627:68] + wire _T_574 = io_o_cpu_run_ack & i_cpu_run_req_sync; // @[dec_tlu_ctl.scala 627:136] + wire cpu_run_ack = _T_573 | _T_574; // @[dec_tlu_ctl.scala 627:116] + reg _T_520; // @[Reg.scala 27:20] + wire _T_518 = cpu_run_ack ^ _T_520; // @[lib.scala 448:21] + wire _T_519 = |_T_518; // @[lib.scala 448:29] + wire ext_halt_pulse = i_cpu_halt_req_sync_qual & _T_583; // @[dec_tlu_ctl.scala 617:55] + wire fw_halt_req = csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 1011:37] + wire enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; // @[dec_tlu_ctl.scala 618:53] + wire _T_551 = pmu_fw_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 623:50] + wire _T_552 = _T_551 & halt_taken; // @[dec_tlu_ctl.scala 623:63] + wire _T_553 = ~enter_debug_halt_req; // @[dec_tlu_ctl.scala 623:78] + wire _T_554 = _T_552 & _T_553; // @[dec_tlu_ctl.scala 623:76] + wire _T_557 = _T_554 | _T_564; // @[dec_tlu_ctl.scala 623:101] + wire pmu_fw_tlu_halted = _T_557 & _T_358; // @[dec_tlu_ctl.scala 623:146] + wire _T_541 = ~pmu_fw_tlu_halted; // @[dec_tlu_ctl.scala 619:77] + wire _T_542 = pmu_fw_halt_req_f & _T_541; // @[dec_tlu_ctl.scala 619:75] + wire _T_543 = enter_pmu_fw_halt_req | _T_542; // @[dec_tlu_ctl.scala 619:54] + wire pmu_fw_halt_req_ns = _T_543 & _T_358; // @[dec_tlu_ctl.scala 619:98] + wire _T_547 = internal_pmu_fw_halt_mode_f & _T_563; // @[dec_tlu_ctl.scala 620:88] + wire _T_549 = _T_547 & _T_358; // @[dec_tlu_ctl.scala 620:108] + wire internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | _T_549; // @[dec_tlu_ctl.scala 620:57] + wire _T_521 = internal_pmu_fw_halt_mode ^ internal_pmu_fw_halt_mode_f; // @[lib.scala 448:21] + wire _T_522 = |_T_521; // @[lib.scala 448:29] + wire _T_525 = pmu_fw_halt_req_ns ^ pmu_fw_halt_req_f; // @[lib.scala 448:21] + wire _T_526 = |_T_525; // @[lib.scala 448:29] + wire _T_529 = pmu_fw_tlu_halted ^ pmu_fw_tlu_halted_f; // @[lib.scala 448:21] + wire _T_530 = |_T_529; // @[lib.scala 448:29] + wire int_timer0_int_hold = int_exc_io_int_timer0_int_hold; // @[dec_tlu_ctl.scala 785:43] + wire _T_533 = int_timer0_int_hold ^ int_timer0_int_hold_f; // @[lib.scala 448:21] + wire _T_534 = |_T_533; // @[lib.scala 448:29] + wire int_timer1_int_hold = int_exc_io_int_timer1_int_hold; // @[dec_tlu_ctl.scala 786:43] + wire _T_537 = int_timer1_int_hold ^ int_timer1_int_hold_f; // @[lib.scala 448:21] + wire _T_538 = |_T_537; // @[lib.scala 448:29] + wire _T_596 = io_dec_tlu_i0_valid_r & _T_590; // @[dec_tlu_ctl.scala 654:55] + wire _T_597 = ~lsu_exc_valid_r; // @[dec_tlu_ctl.scala 654:70] + wire _T_598 = _T_596 & _T_597; // @[dec_tlu_ctl.scala 654:68] + wire _T_599 = ~inst_acc_r; // @[dec_tlu_ctl.scala 654:87] + wire _T_600 = _T_598 & _T_599; // @[dec_tlu_ctl.scala 654:84] + wire _T_602 = _T_600 & _T_249; // @[dec_tlu_ctl.scala 654:99] + wire _T_603 = ~request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 654:126] + wire _T_604 = _T_602 & _T_603; // @[dec_tlu_ctl.scala 654:124] + wire tlu_i0_commit_cmt = _T_604 & _T_619; // @[dec_tlu_ctl.scala 654:151] + wire _T_626 = tlu_i0_commit_cmt & iccm_repair_state_d1; // @[dec_tlu_ctl.scala 672:57] + wire _T_653 = ~dcsr[15]; // @[dec_tlu_ctl.scala 703:116] + wire _T_654 = _T_702 & _T_653; // @[dec_tlu_ctl.scala 703:114] + wire ebreak_r = _T_654 & _T_590; // @[dec_tlu_ctl.scala 703:136] + wire _T_657 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h9; // @[dec_tlu_ctl.scala 704:57] + wire _T_658 = _T_657 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 704:70] + wire _T_660 = _T_658 & _T_619; // @[dec_tlu_ctl.scala 704:94] + wire ecall_r = _T_660 & _T_590; // @[dec_tlu_ctl.scala 704:114] + wire _T_627 = ebreak_r | ecall_r; // @[dec_tlu_ctl.scala 672:93] + wire _T_628 = _T_627 | mret_r; // @[dec_tlu_ctl.scala 672:103] + wire _T_629 = _T_628 | take_reset; // @[dec_tlu_ctl.scala 672:112] + wire _T_630 = _T_629 | illegal_r; // @[dec_tlu_ctl.scala 672:125] + wire _T_631 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 672:181] + wire _T_632 = dec_csr_wen_r_mod & _T_631; // @[dec_tlu_ctl.scala 672:158] + wire _T_633 = _T_630 | _T_632; // @[dec_tlu_ctl.scala 672:137] + wire _T_634 = ~_T_633; // @[dec_tlu_ctl.scala 672:82] + wire _T_635 = io_tlu_exu_exu_i0_br_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 679:69] + wire _T_638 = io_tlu_exu_exu_i0_br_start_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 680:81] + wire _T_641 = io_tlu_exu_exu_i0_br_valid_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 681:65] + wire _T_643 = _T_641 & _T_611; // @[dec_tlu_ctl.scala 681:89] + wire _T_644 = ~io_tlu_exu_exu_i0_br_mp_r; // @[dec_tlu_ctl.scala 681:116] + wire _T_645 = ~io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 681:145] + wire _T_646 = _T_644 | _T_645; // @[dec_tlu_ctl.scala 681:143] + wire csr_pkt_presync = csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_708 = csr_pkt_presync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1021:50] + wire _T_709 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 1021:75] + wire csr_pkt_postsync = csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_718 = csr_pkt_csr_dcsr | csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1026:63] + wire csr_pkt_csr_dmst = csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_719 = _T_718 | csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1026:81] + wire csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_720 = _T_719 | csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1026:100] + wire csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_721 = _T_720 | csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1026:123] + wire csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_722 = _T_721 | csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1026:144] + wire csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_723 = _T_722 | csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1026:166] + wire csr_pkt_csr_dicago = csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_724 = _T_723 | csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1026:187] + wire _T_725 = ~_T_724; // @[dec_tlu_ctl.scala 1026:44] + wire _T_726 = _T_725 | dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1026:209] + wire csr_pkt_legal = csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_727 = csr_pkt_legal & _T_726; // @[dec_tlu_ctl.scala 1026:41] + wire fast_int_meicpct = int_exc_io_fast_int_meicpct; // @[dec_tlu_ctl.scala 798:43] + wire _T_728 = ~fast_int_meicpct; // @[dec_tlu_ctl.scala 1026:231] + wire valid_csr = _T_727 & _T_728; // @[dec_tlu_ctl.scala 1026:229] + wire _T_731 = io_dec_csr_any_unq_d & valid_csr; // @[dec_tlu_ctl.scala 1028:54] + wire csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_732 = csr_pkt_csr_mvendorid | csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1028:115] + wire csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_733 = _T_732 | csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1028:137] + wire csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_734 = _T_733 | csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1028:158] + wire csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_735 = _T_734 | csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1028:180] + wire csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_736 = _T_735 | csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1028:201] + wire _T_737 = io_dec_csr_wen_unq_d & _T_736; // @[dec_tlu_ctl.scala 1028:90] + wire _T_738 = ~_T_737; // @[dec_tlu_ctl.scala 1028:67] + int_exc int_exc ( // @[dec_tlu_ctl.scala 282:29] + .clock(int_exc_clock), + .reset(int_exc_reset), + .io_mhwakeup_ready(int_exc_io_mhwakeup_ready), + .io_ext_int_ready(int_exc_io_ext_int_ready), + .io_ce_int_ready(int_exc_io_ce_int_ready), + .io_soft_int_ready(int_exc_io_soft_int_ready), + .io_timer_int_ready(int_exc_io_timer_int_ready), + .io_int_timer0_int_hold(int_exc_io_int_timer0_int_hold), + .io_int_timer1_int_hold(int_exc_io_int_timer1_int_hold), + .io_internal_dbg_halt_timers(int_exc_io_internal_dbg_halt_timers), + .io_take_ext_int_start(int_exc_io_take_ext_int_start), + .io_ext_int_freeze_d1(int_exc_io_ext_int_freeze_d1), + .io_take_ext_int_start_d1(int_exc_io_take_ext_int_start_d1), + .io_take_ext_int_start_d2(int_exc_io_take_ext_int_start_d2), + .io_take_ext_int_start_d3(int_exc_io_take_ext_int_start_d3), + .io_ext_int_freeze(int_exc_io_ext_int_freeze), + .io_take_ext_int(int_exc_io_take_ext_int), + .io_fast_int_meicpct(int_exc_io_fast_int_meicpct), + .io_ignore_ext_int_due_to_lsu_stall(int_exc_io_ignore_ext_int_due_to_lsu_stall), + .io_take_ce_int(int_exc_io_take_ce_int), + .io_take_soft_int(int_exc_io_take_soft_int), + .io_take_timer_int(int_exc_io_take_timer_int), + .io_take_int_timer0_int(int_exc_io_take_int_timer0_int), + .io_take_int_timer1_int(int_exc_io_take_int_timer1_int), + .io_take_reset(int_exc_io_take_reset), + .io_take_nmi(int_exc_io_take_nmi), + .io_synchronous_flush_r(int_exc_io_synchronous_flush_r), + .io_tlu_flush_lower_r(int_exc_io_tlu_flush_lower_r), + .io_dec_tlu_flush_lower_wb(int_exc_io_dec_tlu_flush_lower_wb), + .io_dec_tlu_flush_lower_r(int_exc_io_dec_tlu_flush_lower_r), + .io_dec_tlu_flush_path_r(int_exc_io_dec_tlu_flush_path_r), + .io_interrupt_valid_r_d1(int_exc_io_interrupt_valid_r_d1), + .io_i0_exception_valid_r_d1(int_exc_io_i0_exception_valid_r_d1), + .io_exc_or_int_valid_r_d1(int_exc_io_exc_or_int_valid_r_d1), + .io_exc_cause_wb(int_exc_io_exc_cause_wb), + .io_i0_valid_wb(int_exc_io_i0_valid_wb), + .io_trigger_hit_r_d1(int_exc_io_trigger_hit_r_d1), + .io_take_nmi_r_d1(int_exc_io_take_nmi_r_d1), + .io_interrupt_valid_r(int_exc_io_interrupt_valid_r), + .io_exc_cause_r(int_exc_io_exc_cause_r), + .io_i0_exception_valid_r(int_exc_io_i0_exception_valid_r), + .io_tlu_flush_path_r_d1(int_exc_io_tlu_flush_path_r_d1), + .io_exc_or_int_valid_r(int_exc_io_exc_or_int_valid_r), + .io_dec_csr_stall_int_ff(int_exc_io_dec_csr_stall_int_ff), + .io_mstatus_mie_ns(int_exc_io_mstatus_mie_ns), + .io_mip(int_exc_io_mip), + .io_mie_ns(int_exc_io_mie_ns), + .io_mret_r(int_exc_io_mret_r), + .io_pmu_fw_tlu_halted_f(int_exc_io_pmu_fw_tlu_halted_f), + .io_int_timer0_int_hold_f(int_exc_io_int_timer0_int_hold_f), + .io_int_timer1_int_hold_f(int_exc_io_int_timer1_int_hold_f), + .io_internal_dbg_halt_mode_f(int_exc_io_internal_dbg_halt_mode_f), + .io_dcsr_single_step_running(int_exc_io_dcsr_single_step_running), + .io_internal_dbg_halt_mode(int_exc_io_internal_dbg_halt_mode), + .io_dec_tlu_i0_valid_r(int_exc_io_dec_tlu_i0_valid_r), + .io_internal_pmu_fw_halt_mode(int_exc_io_internal_pmu_fw_halt_mode), + .io_i_cpu_halt_req_d1(int_exc_io_i_cpu_halt_req_d1), + .io_ebreak_to_debug_mode_r(int_exc_io_ebreak_to_debug_mode_r), + .io_lsu_fir_error(int_exc_io_lsu_fir_error), + .io_csr_pkt_csr_meicpct(int_exc_io_csr_pkt_csr_meicpct), + .io_dec_csr_any_unq_d(int_exc_io_dec_csr_any_unq_d), + .io_lsu_fastint_stall_any(int_exc_io_lsu_fastint_stall_any), + .io_reset_delayed(int_exc_io_reset_delayed), + .io_mpc_reset_run_req(int_exc_io_mpc_reset_run_req), + .io_nmi_int_detected(int_exc_io_nmi_int_detected), + .io_dcsr_single_step_running_f(int_exc_io_dcsr_single_step_running_f), + .io_dcsr_single_step_done_f(int_exc_io_dcsr_single_step_done_f), + .io_dcsr(int_exc_io_dcsr), + .io_mtvec(int_exc_io_mtvec), + .io_tlu_i0_commit_cmt(int_exc_io_tlu_i0_commit_cmt), + .io_i0_trigger_hit_r(int_exc_io_i0_trigger_hit_r), + .io_pause_expired_r(int_exc_io_pause_expired_r), + .io_nmi_vec(int_exc_io_nmi_vec), + .io_lsu_i0_rfnpc_r(int_exc_io_lsu_i0_rfnpc_r), + .io_fence_i_r(int_exc_io_fence_i_r), + .io_iccm_repair_state_rfnpc(int_exc_io_iccm_repair_state_rfnpc), + .io_i_cpu_run_req_d1(int_exc_io_i_cpu_run_req_d1), + .io_rfpc_i0_r(int_exc_io_rfpc_i0_r), + .io_lsu_exc_valid_r(int_exc_io_lsu_exc_valid_r), + .io_trigger_hit_dmode_r(int_exc_io_trigger_hit_dmode_r), + .io_take_halt(int_exc_io_take_halt), + .io_rst_vec(int_exc_io_rst_vec), + .io_lsu_fir_addr(int_exc_io_lsu_fir_addr), + .io_dec_tlu_i0_pc_r(int_exc_io_dec_tlu_i0_pc_r), + .io_npc_r(int_exc_io_npc_r), + .io_mepc(int_exc_io_mepc), + .io_debug_resume_req_f(int_exc_io_debug_resume_req_f), + .io_dpc(int_exc_io_dpc), + .io_npc_r_d1(int_exc_io_npc_r_d1), + .io_tlu_flush_lower_r_d1(int_exc_io_tlu_flush_lower_r_d1), + .io_dec_tlu_dbg_halted(int_exc_io_dec_tlu_dbg_halted), + .io_ebreak_r(int_exc_io_ebreak_r), + .io_ecall_r(int_exc_io_ecall_r), + .io_illegal_r(int_exc_io_illegal_r), + .io_inst_acc_r(int_exc_io_inst_acc_r), + .io_lsu_i0_exc_r(int_exc_io_lsu_i0_exc_r), + .io_lsu_error_pkt_r_bits_inst_type(int_exc_io_lsu_error_pkt_r_bits_inst_type), + .io_lsu_error_pkt_r_bits_exc_type(int_exc_io_lsu_error_pkt_r_bits_exc_type), + .io_dec_tlu_wr_pause_r_d1(int_exc_io_dec_tlu_wr_pause_r_d1) + ); + csr_tlu csr ( // @[dec_tlu_ctl.scala 283:23] + .clock(csr_clock), + .reset(csr_reset), + .io_free_l2clk(csr_io_free_l2clk), + .io_free_clk(csr_io_free_clk), + .io_dec_csr_wrdata_r(csr_io_dec_csr_wrdata_r), + .io_dec_csr_wraddr_r(csr_io_dec_csr_wraddr_r), + .io_dec_csr_rdaddr_d(csr_io_dec_csr_rdaddr_d), + .io_dec_csr_wen_unq_d(csr_io_dec_csr_wen_unq_d), + .io_dec_i0_decode_d(csr_io_dec_i0_decode_d), + .io_dec_tlu_ic_diag_pkt_icache_wrdata(csr_io_dec_tlu_ic_diag_pkt_icache_wrdata), + .io_dec_tlu_ic_diag_pkt_icache_dicawics(csr_io_dec_tlu_ic_diag_pkt_icache_dicawics), + .io_dec_tlu_ic_diag_pkt_icache_rd_valid(csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid), + .io_dec_tlu_ic_diag_pkt_icache_wr_valid(csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid), + .io_ifu_ic_debug_rd_data_valid(csr_io_ifu_ic_debug_rd_data_valid), + .io_trigger_pkt_any_0_select(csr_io_trigger_pkt_any_0_select), + .io_trigger_pkt_any_0_match_pkt(csr_io_trigger_pkt_any_0_match_pkt), + .io_trigger_pkt_any_0_store(csr_io_trigger_pkt_any_0_store), + .io_trigger_pkt_any_0_load(csr_io_trigger_pkt_any_0_load), + .io_trigger_pkt_any_0_execute(csr_io_trigger_pkt_any_0_execute), + .io_trigger_pkt_any_0_m(csr_io_trigger_pkt_any_0_m), + .io_trigger_pkt_any_0_tdata2(csr_io_trigger_pkt_any_0_tdata2), + .io_trigger_pkt_any_1_select(csr_io_trigger_pkt_any_1_select), + .io_trigger_pkt_any_1_match_pkt(csr_io_trigger_pkt_any_1_match_pkt), + .io_trigger_pkt_any_1_store(csr_io_trigger_pkt_any_1_store), + .io_trigger_pkt_any_1_load(csr_io_trigger_pkt_any_1_load), + .io_trigger_pkt_any_1_execute(csr_io_trigger_pkt_any_1_execute), + .io_trigger_pkt_any_1_m(csr_io_trigger_pkt_any_1_m), + .io_trigger_pkt_any_1_tdata2(csr_io_trigger_pkt_any_1_tdata2), + .io_trigger_pkt_any_2_select(csr_io_trigger_pkt_any_2_select), + .io_trigger_pkt_any_2_match_pkt(csr_io_trigger_pkt_any_2_match_pkt), + .io_trigger_pkt_any_2_store(csr_io_trigger_pkt_any_2_store), + .io_trigger_pkt_any_2_load(csr_io_trigger_pkt_any_2_load), + .io_trigger_pkt_any_2_execute(csr_io_trigger_pkt_any_2_execute), + .io_trigger_pkt_any_2_m(csr_io_trigger_pkt_any_2_m), + .io_trigger_pkt_any_2_tdata2(csr_io_trigger_pkt_any_2_tdata2), + .io_trigger_pkt_any_3_select(csr_io_trigger_pkt_any_3_select), + .io_trigger_pkt_any_3_match_pkt(csr_io_trigger_pkt_any_3_match_pkt), + .io_trigger_pkt_any_3_store(csr_io_trigger_pkt_any_3_store), + .io_trigger_pkt_any_3_load(csr_io_trigger_pkt_any_3_load), + .io_trigger_pkt_any_3_execute(csr_io_trigger_pkt_any_3_execute), + .io_trigger_pkt_any_3_m(csr_io_trigger_pkt_any_3_m), + .io_trigger_pkt_any_3_tdata2(csr_io_trigger_pkt_any_3_tdata2), + .io_ifu_pmu_bus_trxn(csr_io_ifu_pmu_bus_trxn), + .io_dma_iccm_stall_any(csr_io_dma_iccm_stall_any), + .io_dma_dccm_stall_any(csr_io_dma_dccm_stall_any), + .io_lsu_store_stall_any(csr_io_lsu_store_stall_any), + .io_dec_pmu_presync_stall(csr_io_dec_pmu_presync_stall), + .io_dec_pmu_postsync_stall(csr_io_dec_pmu_postsync_stall), + .io_dec_pmu_decode_stall(csr_io_dec_pmu_decode_stall), + .io_ifu_pmu_fetch_stall(csr_io_ifu_pmu_fetch_stall), + .io_dec_tlu_packet_r_icaf_type(csr_io_dec_tlu_packet_r_icaf_type), + .io_dec_tlu_packet_r_pmu_i0_itype(csr_io_dec_tlu_packet_r_pmu_i0_itype), + .io_dec_tlu_packet_r_pmu_i0_br_unpred(csr_io_dec_tlu_packet_r_pmu_i0_br_unpred), + .io_dec_tlu_packet_r_pmu_divide(csr_io_dec_tlu_packet_r_pmu_divide), + .io_dec_tlu_packet_r_pmu_lsu_misaligned(csr_io_dec_tlu_packet_r_pmu_lsu_misaligned), + .io_exu_pmu_i0_br_ataken(csr_io_exu_pmu_i0_br_ataken), + .io_exu_pmu_i0_br_misp(csr_io_exu_pmu_i0_br_misp), + .io_dec_pmu_instr_decoded(csr_io_dec_pmu_instr_decoded), + .io_ifu_pmu_instr_aligned(csr_io_ifu_pmu_instr_aligned), + .io_exu_pmu_i0_pc4(csr_io_exu_pmu_i0_pc4), + .io_ifu_pmu_ic_miss(csr_io_ifu_pmu_ic_miss), + .io_ifu_pmu_ic_hit(csr_io_ifu_pmu_ic_hit), + .io_dec_tlu_int_valid_wb1(csr_io_dec_tlu_int_valid_wb1), + .io_dec_tlu_i0_exc_valid_wb1(csr_io_dec_tlu_i0_exc_valid_wb1), + .io_dec_tlu_i0_valid_wb1(csr_io_dec_tlu_i0_valid_wb1), + .io_dec_csr_wen_r(csr_io_dec_csr_wen_r), + .io_dec_tlu_mtval_wb1(csr_io_dec_tlu_mtval_wb1), + .io_dec_tlu_exc_cause_wb1(csr_io_dec_tlu_exc_cause_wb1), + .io_dec_tlu_perfcnt0(csr_io_dec_tlu_perfcnt0), + .io_dec_tlu_perfcnt1(csr_io_dec_tlu_perfcnt1), + .io_dec_tlu_perfcnt2(csr_io_dec_tlu_perfcnt2), + .io_dec_tlu_perfcnt3(csr_io_dec_tlu_perfcnt3), + .io_dec_tlu_dbg_halted(csr_io_dec_tlu_dbg_halted), + .io_dma_pmu_dccm_write(csr_io_dma_pmu_dccm_write), + .io_dma_pmu_dccm_read(csr_io_dma_pmu_dccm_read), + .io_dma_pmu_any_write(csr_io_dma_pmu_any_write), + .io_dma_pmu_any_read(csr_io_dma_pmu_any_read), + .io_lsu_pmu_bus_busy(csr_io_lsu_pmu_bus_busy), + .io_dec_tlu_i0_pc_r(csr_io_dec_tlu_i0_pc_r), + .io_dec_tlu_i0_valid_r(csr_io_dec_tlu_i0_valid_r), + .io_dec_csr_any_unq_d(csr_io_dec_csr_any_unq_d), + .io_dec_tlu_misc_clk_override(csr_io_dec_tlu_misc_clk_override), + .io_dec_tlu_dec_clk_override(csr_io_dec_tlu_dec_clk_override), + .io_dec_tlu_ifu_clk_override(csr_io_dec_tlu_ifu_clk_override), + .io_dec_tlu_lsu_clk_override(csr_io_dec_tlu_lsu_clk_override), + .io_dec_tlu_bus_clk_override(csr_io_dec_tlu_bus_clk_override), + .io_dec_tlu_pic_clk_override(csr_io_dec_tlu_pic_clk_override), + .io_dec_tlu_dccm_clk_override(csr_io_dec_tlu_dccm_clk_override), + .io_dec_tlu_icm_clk_override(csr_io_dec_tlu_icm_clk_override), + .io_dec_csr_rddata_d(csr_io_dec_csr_rddata_d), + .io_dec_tlu_pipelining_disable(csr_io_dec_tlu_pipelining_disable), + .io_dec_tlu_wr_pause_r(csr_io_dec_tlu_wr_pause_r), + .io_ifu_pmu_bus_busy(csr_io_ifu_pmu_bus_busy), + .io_lsu_pmu_bus_error(csr_io_lsu_pmu_bus_error), + .io_ifu_pmu_bus_error(csr_io_ifu_pmu_bus_error), + .io_lsu_pmu_bus_misaligned(csr_io_lsu_pmu_bus_misaligned), + .io_lsu_pmu_bus_trxn(csr_io_lsu_pmu_bus_trxn), + .io_ifu_ic_debug_rd_data(csr_io_ifu_ic_debug_rd_data), + .io_dec_tlu_meipt(csr_io_dec_tlu_meipt), + .io_pic_pl(csr_io_pic_pl), + .io_dec_tlu_meicurpl(csr_io_dec_tlu_meicurpl), + .io_dec_tlu_meihap(csr_io_dec_tlu_meihap), + .io_pic_claimid(csr_io_pic_claimid), + .io_iccm_dma_sb_error(csr_io_iccm_dma_sb_error), + .io_lsu_imprecise_error_addr_any(csr_io_lsu_imprecise_error_addr_any), + .io_lsu_imprecise_error_load_any(csr_io_lsu_imprecise_error_load_any), + .io_lsu_imprecise_error_store_any(csr_io_lsu_imprecise_error_store_any), + .io_dec_tlu_mrac_ff(csr_io_dec_tlu_mrac_ff), + .io_dec_tlu_wb_coalescing_disable(csr_io_dec_tlu_wb_coalescing_disable), + .io_dec_tlu_bpred_disable(csr_io_dec_tlu_bpred_disable), + .io_dec_tlu_sideeffect_posted_disable(csr_io_dec_tlu_sideeffect_posted_disable), + .io_dec_tlu_core_ecc_disable(csr_io_dec_tlu_core_ecc_disable), + .io_dec_tlu_external_ldfwd_disable(csr_io_dec_tlu_external_ldfwd_disable), + .io_dec_tlu_dma_qos_prty(csr_io_dec_tlu_dma_qos_prty), + .io_dec_tlu_trace_disable(csr_io_dec_tlu_trace_disable), + .io_dec_illegal_inst(csr_io_dec_illegal_inst), + .io_lsu_error_pkt_r_bits_mscause(csr_io_lsu_error_pkt_r_bits_mscause), + .io_mexintpend(csr_io_mexintpend), + .io_exu_npc_r(csr_io_exu_npc_r), + .io_mpc_reset_run_req(csr_io_mpc_reset_run_req), + .io_rst_vec(csr_io_rst_vec), + .io_core_id(csr_io_core_id), + .io_dec_timer_rddata_d(csr_io_dec_timer_rddata_d), + .io_dec_timer_read_d(csr_io_dec_timer_read_d), + .io_dec_csr_wen_r_mod(csr_io_dec_csr_wen_r_mod), + .io_rfpc_i0_r(csr_io_rfpc_i0_r), + .io_i0_trigger_hit_r(csr_io_i0_trigger_hit_r), + .io_fw_halt_req(csr_io_fw_halt_req), + .io_mstatus(csr_io_mstatus), + .io_exc_or_int_valid_r(csr_io_exc_or_int_valid_r), + .io_mret_r(csr_io_mret_r), + .io_mstatus_mie_ns(csr_io_mstatus_mie_ns), + .io_dcsr_single_step_running_f(csr_io_dcsr_single_step_running_f), + .io_dcsr(csr_io_dcsr), + .io_mtvec(csr_io_mtvec), + .io_mip(csr_io_mip), + .io_dec_timer_t0_pulse(csr_io_dec_timer_t0_pulse), + .io_dec_timer_t1_pulse(csr_io_dec_timer_t1_pulse), + .io_timer_int_sync(csr_io_timer_int_sync), + .io_soft_int_sync(csr_io_soft_int_sync), + .io_mie_ns(csr_io_mie_ns), + .io_csr_wr_clk(csr_io_csr_wr_clk), + .io_ebreak_to_debug_mode_r(csr_io_ebreak_to_debug_mode_r), + .io_dec_tlu_pmu_fw_halted(csr_io_dec_tlu_pmu_fw_halted), + .io_lsu_fir_error(csr_io_lsu_fir_error), + .io_npc_r(csr_io_npc_r), + .io_tlu_flush_lower_r_d1(csr_io_tlu_flush_lower_r_d1), + .io_dec_tlu_flush_noredir_r_d1(csr_io_dec_tlu_flush_noredir_r_d1), + .io_tlu_flush_path_r_d1(csr_io_tlu_flush_path_r_d1), + .io_npc_r_d1(csr_io_npc_r_d1), + .io_reset_delayed(csr_io_reset_delayed), + .io_mepc(csr_io_mepc), + .io_interrupt_valid_r(csr_io_interrupt_valid_r), + .io_i0_exception_valid_r(csr_io_i0_exception_valid_r), + .io_lsu_exc_valid_r(csr_io_lsu_exc_valid_r), + .io_mepc_trigger_hit_sel_pc_r(csr_io_mepc_trigger_hit_sel_pc_r), + .io_lsu_single_ecc_error_r(csr_io_lsu_single_ecc_error_r), + .io_e4e5_int_clk(csr_io_e4e5_int_clk), + .io_lsu_i0_exc_r(csr_io_lsu_i0_exc_r), + .io_inst_acc_r(csr_io_inst_acc_r), + .io_inst_acc_second_r(csr_io_inst_acc_second_r), + .io_take_nmi(csr_io_take_nmi), + .io_lsu_error_pkt_addr_r(csr_io_lsu_error_pkt_addr_r), + .io_exc_cause_r(csr_io_exc_cause_r), + .io_i0_valid_wb(csr_io_i0_valid_wb), + .io_interrupt_valid_r_d1(csr_io_interrupt_valid_r_d1), + .io_i0_exception_valid_r_d1(csr_io_i0_exception_valid_r_d1), + .io_exc_cause_wb(csr_io_exc_cause_wb), + .io_nmi_lsu_store_type(csr_io_nmi_lsu_store_type), + .io_nmi_lsu_load_type(csr_io_nmi_lsu_load_type), + .io_tlu_i0_commit_cmt(csr_io_tlu_i0_commit_cmt), + .io_ebreak_r(csr_io_ebreak_r), + .io_ecall_r(csr_io_ecall_r), + .io_illegal_r(csr_io_illegal_r), + .io_mdseac_locked_ns(csr_io_mdseac_locked_ns), + .io_mdseac_locked_f(csr_io_mdseac_locked_f), + .io_nmi_int_detected_f(csr_io_nmi_int_detected_f), + .io_internal_dbg_halt_mode_f2(csr_io_internal_dbg_halt_mode_f2), + .io_ext_int_freeze(csr_io_ext_int_freeze), + .io_ext_int_freeze_d1(csr_io_ext_int_freeze_d1), + .io_take_ext_int_start_d1(csr_io_take_ext_int_start_d1), + .io_take_ext_int_start_d2(csr_io_take_ext_int_start_d2), + .io_take_ext_int_start_d3(csr_io_take_ext_int_start_d3), + .io_ic_perr_r(csr_io_ic_perr_r), + .io_iccm_sbecc_r(csr_io_iccm_sbecc_r), + .io_ifu_miss_state_idle_f(csr_io_ifu_miss_state_idle_f), + .io_lsu_idle_any_f(csr_io_lsu_idle_any_f), + .io_dbg_tlu_halted_f(csr_io_dbg_tlu_halted_f), + .io_dbg_tlu_halted(csr_io_dbg_tlu_halted), + .io_debug_halt_req_f(csr_io_debug_halt_req_f), + .io_force_halt(csr_io_force_halt), + .io_take_ext_int_start(csr_io_take_ext_int_start), + .io_trigger_hit_dmode_r_d1(csr_io_trigger_hit_dmode_r_d1), + .io_trigger_hit_r_d1(csr_io_trigger_hit_r_d1), + .io_dcsr_single_step_done_f(csr_io_dcsr_single_step_done_f), + .io_ebreak_to_debug_mode_r_d1(csr_io_ebreak_to_debug_mode_r_d1), + .io_debug_halt_req(csr_io_debug_halt_req), + .io_allow_dbg_halt_csr_write(csr_io_allow_dbg_halt_csr_write), + .io_internal_dbg_halt_mode_f(csr_io_internal_dbg_halt_mode_f), + .io_enter_debug_halt_req(csr_io_enter_debug_halt_req), + .io_internal_dbg_halt_mode(csr_io_internal_dbg_halt_mode), + .io_request_debug_mode_done(csr_io_request_debug_mode_done), + .io_request_debug_mode_r(csr_io_request_debug_mode_r), + .io_dpc(csr_io_dpc), + .io_update_hit_bit_r(csr_io_update_hit_bit_r), + .io_take_timer_int(csr_io_take_timer_int), + .io_take_int_timer0_int(csr_io_take_int_timer0_int), + .io_take_int_timer1_int(csr_io_take_int_timer1_int), + .io_take_ext_int(csr_io_take_ext_int), + .io_tlu_flush_lower_r(csr_io_tlu_flush_lower_r), + .io_dec_tlu_br0_error_r(csr_io_dec_tlu_br0_error_r), + .io_dec_tlu_br0_start_error_r(csr_io_dec_tlu_br0_start_error_r), + .io_lsu_pmu_load_external_r(csr_io_lsu_pmu_load_external_r), + .io_lsu_pmu_store_external_r(csr_io_lsu_pmu_store_external_r), + .io_csr_pkt_csr_misa(csr_io_csr_pkt_csr_misa), + .io_csr_pkt_csr_mvendorid(csr_io_csr_pkt_csr_mvendorid), + .io_csr_pkt_csr_marchid(csr_io_csr_pkt_csr_marchid), + .io_csr_pkt_csr_mimpid(csr_io_csr_pkt_csr_mimpid), + .io_csr_pkt_csr_mhartid(csr_io_csr_pkt_csr_mhartid), + .io_csr_pkt_csr_mstatus(csr_io_csr_pkt_csr_mstatus), + .io_csr_pkt_csr_mtvec(csr_io_csr_pkt_csr_mtvec), + .io_csr_pkt_csr_mip(csr_io_csr_pkt_csr_mip), + .io_csr_pkt_csr_mie(csr_io_csr_pkt_csr_mie), + .io_csr_pkt_csr_mcyclel(csr_io_csr_pkt_csr_mcyclel), + .io_csr_pkt_csr_mcycleh(csr_io_csr_pkt_csr_mcycleh), + .io_csr_pkt_csr_minstretl(csr_io_csr_pkt_csr_minstretl), + .io_csr_pkt_csr_minstreth(csr_io_csr_pkt_csr_minstreth), + .io_csr_pkt_csr_mscratch(csr_io_csr_pkt_csr_mscratch), + .io_csr_pkt_csr_mepc(csr_io_csr_pkt_csr_mepc), + .io_csr_pkt_csr_mcause(csr_io_csr_pkt_csr_mcause), + .io_csr_pkt_csr_mscause(csr_io_csr_pkt_csr_mscause), + .io_csr_pkt_csr_mtval(csr_io_csr_pkt_csr_mtval), + .io_csr_pkt_csr_mrac(csr_io_csr_pkt_csr_mrac), + .io_csr_pkt_csr_mdseac(csr_io_csr_pkt_csr_mdseac), + .io_csr_pkt_csr_meihap(csr_io_csr_pkt_csr_meihap), + .io_csr_pkt_csr_meivt(csr_io_csr_pkt_csr_meivt), + .io_csr_pkt_csr_meipt(csr_io_csr_pkt_csr_meipt), + .io_csr_pkt_csr_meicurpl(csr_io_csr_pkt_csr_meicurpl), + .io_csr_pkt_csr_meicidpl(csr_io_csr_pkt_csr_meicidpl), + .io_csr_pkt_csr_dcsr(csr_io_csr_pkt_csr_dcsr), + .io_csr_pkt_csr_mcgc(csr_io_csr_pkt_csr_mcgc), + .io_csr_pkt_csr_mfdc(csr_io_csr_pkt_csr_mfdc), + .io_csr_pkt_csr_dpc(csr_io_csr_pkt_csr_dpc), + .io_csr_pkt_csr_mtsel(csr_io_csr_pkt_csr_mtsel), + .io_csr_pkt_csr_mtdata1(csr_io_csr_pkt_csr_mtdata1), + .io_csr_pkt_csr_mtdata2(csr_io_csr_pkt_csr_mtdata2), + .io_csr_pkt_csr_mhpmc3(csr_io_csr_pkt_csr_mhpmc3), + .io_csr_pkt_csr_mhpmc4(csr_io_csr_pkt_csr_mhpmc4), + .io_csr_pkt_csr_mhpmc5(csr_io_csr_pkt_csr_mhpmc5), + .io_csr_pkt_csr_mhpmc6(csr_io_csr_pkt_csr_mhpmc6), + .io_csr_pkt_csr_mhpmc3h(csr_io_csr_pkt_csr_mhpmc3h), + .io_csr_pkt_csr_mhpmc4h(csr_io_csr_pkt_csr_mhpmc4h), + .io_csr_pkt_csr_mhpmc5h(csr_io_csr_pkt_csr_mhpmc5h), + .io_csr_pkt_csr_mhpmc6h(csr_io_csr_pkt_csr_mhpmc6h), + .io_csr_pkt_csr_mhpme3(csr_io_csr_pkt_csr_mhpme3), + .io_csr_pkt_csr_mhpme4(csr_io_csr_pkt_csr_mhpme4), + .io_csr_pkt_csr_mhpme5(csr_io_csr_pkt_csr_mhpme5), + .io_csr_pkt_csr_mhpme6(csr_io_csr_pkt_csr_mhpme6), + .io_csr_pkt_csr_mcountinhibit(csr_io_csr_pkt_csr_mcountinhibit), + .io_csr_pkt_csr_mpmc(csr_io_csr_pkt_csr_mpmc), + .io_csr_pkt_csr_micect(csr_io_csr_pkt_csr_micect), + .io_csr_pkt_csr_miccmect(csr_io_csr_pkt_csr_miccmect), + .io_csr_pkt_csr_mdccmect(csr_io_csr_pkt_csr_mdccmect), + .io_csr_pkt_csr_mfdht(csr_io_csr_pkt_csr_mfdht), + .io_csr_pkt_csr_mfdhs(csr_io_csr_pkt_csr_mfdhs), + .io_csr_pkt_csr_dicawics(csr_io_csr_pkt_csr_dicawics), + .io_csr_pkt_csr_dicad0h(csr_io_csr_pkt_csr_dicad0h), + .io_csr_pkt_csr_dicad0(csr_io_csr_pkt_csr_dicad0), + .io_csr_pkt_csr_dicad1(csr_io_csr_pkt_csr_dicad1), + .io_mtdata1_t_0(csr_io_mtdata1_t_0), + .io_mtdata1_t_1(csr_io_mtdata1_t_1), + .io_mtdata1_t_2(csr_io_mtdata1_t_2), + .io_mtdata1_t_3(csr_io_mtdata1_t_3), + .io_trigger_enabled(csr_io_trigger_enabled) + ); + dec_timer_ctl int_timers ( // @[dec_tlu_ctl.scala 284:30] + .clock(int_timers_clock), + .reset(int_timers_reset), + .io_free_l2clk(int_timers_io_free_l2clk), + .io_csr_wr_clk(int_timers_io_csr_wr_clk), + .io_dec_csr_wen_r_mod(int_timers_io_dec_csr_wen_r_mod), + .io_dec_csr_wraddr_r(int_timers_io_dec_csr_wraddr_r), + .io_dec_csr_wrdata_r(int_timers_io_dec_csr_wrdata_r), + .io_csr_mitctl0(int_timers_io_csr_mitctl0), + .io_csr_mitctl1(int_timers_io_csr_mitctl1), + .io_csr_mitb0(int_timers_io_csr_mitb0), + .io_csr_mitb1(int_timers_io_csr_mitb1), + .io_csr_mitcnt0(int_timers_io_csr_mitcnt0), + .io_csr_mitcnt1(int_timers_io_csr_mitcnt1), + .io_dec_pause_state(int_timers_io_dec_pause_state), + .io_dec_tlu_pmu_fw_halted(int_timers_io_dec_tlu_pmu_fw_halted), + .io_internal_dbg_halt_timers(int_timers_io_internal_dbg_halt_timers), + .io_dec_timer_rddata_d(int_timers_io_dec_timer_rddata_d), + .io_dec_timer_read_d(int_timers_io_dec_timer_read_d), + .io_dec_timer_t0_pulse(int_timers_io_dec_timer_t0_pulse), + .io_dec_timer_t1_pulse(int_timers_io_dec_timer_t1_pulse) + ); + dec_decode_csr_read csr_read ( // @[dec_tlu_ctl.scala 1017:28] + .io_dec_csr_rdaddr_d(csr_read_io_dec_csr_rdaddr_d), + .io_csr_pkt_csr_misa(csr_read_io_csr_pkt_csr_misa), + .io_csr_pkt_csr_mvendorid(csr_read_io_csr_pkt_csr_mvendorid), + .io_csr_pkt_csr_marchid(csr_read_io_csr_pkt_csr_marchid), + .io_csr_pkt_csr_mimpid(csr_read_io_csr_pkt_csr_mimpid), + .io_csr_pkt_csr_mhartid(csr_read_io_csr_pkt_csr_mhartid), + .io_csr_pkt_csr_mstatus(csr_read_io_csr_pkt_csr_mstatus), + .io_csr_pkt_csr_mtvec(csr_read_io_csr_pkt_csr_mtvec), + .io_csr_pkt_csr_mip(csr_read_io_csr_pkt_csr_mip), + .io_csr_pkt_csr_mie(csr_read_io_csr_pkt_csr_mie), + .io_csr_pkt_csr_mcyclel(csr_read_io_csr_pkt_csr_mcyclel), + .io_csr_pkt_csr_mcycleh(csr_read_io_csr_pkt_csr_mcycleh), + .io_csr_pkt_csr_minstretl(csr_read_io_csr_pkt_csr_minstretl), + .io_csr_pkt_csr_minstreth(csr_read_io_csr_pkt_csr_minstreth), + .io_csr_pkt_csr_mscratch(csr_read_io_csr_pkt_csr_mscratch), + .io_csr_pkt_csr_mepc(csr_read_io_csr_pkt_csr_mepc), + .io_csr_pkt_csr_mcause(csr_read_io_csr_pkt_csr_mcause), + .io_csr_pkt_csr_mscause(csr_read_io_csr_pkt_csr_mscause), + .io_csr_pkt_csr_mtval(csr_read_io_csr_pkt_csr_mtval), + .io_csr_pkt_csr_mrac(csr_read_io_csr_pkt_csr_mrac), + .io_csr_pkt_csr_dmst(csr_read_io_csr_pkt_csr_dmst), + .io_csr_pkt_csr_mdseac(csr_read_io_csr_pkt_csr_mdseac), + .io_csr_pkt_csr_meihap(csr_read_io_csr_pkt_csr_meihap), + .io_csr_pkt_csr_meivt(csr_read_io_csr_pkt_csr_meivt), + .io_csr_pkt_csr_meipt(csr_read_io_csr_pkt_csr_meipt), + .io_csr_pkt_csr_meicurpl(csr_read_io_csr_pkt_csr_meicurpl), + .io_csr_pkt_csr_meicidpl(csr_read_io_csr_pkt_csr_meicidpl), + .io_csr_pkt_csr_dcsr(csr_read_io_csr_pkt_csr_dcsr), + .io_csr_pkt_csr_mcgc(csr_read_io_csr_pkt_csr_mcgc), + .io_csr_pkt_csr_mfdc(csr_read_io_csr_pkt_csr_mfdc), + .io_csr_pkt_csr_dpc(csr_read_io_csr_pkt_csr_dpc), + .io_csr_pkt_csr_mtsel(csr_read_io_csr_pkt_csr_mtsel), + .io_csr_pkt_csr_mtdata1(csr_read_io_csr_pkt_csr_mtdata1), + .io_csr_pkt_csr_mtdata2(csr_read_io_csr_pkt_csr_mtdata2), + .io_csr_pkt_csr_mhpmc3(csr_read_io_csr_pkt_csr_mhpmc3), + .io_csr_pkt_csr_mhpmc4(csr_read_io_csr_pkt_csr_mhpmc4), + .io_csr_pkt_csr_mhpmc5(csr_read_io_csr_pkt_csr_mhpmc5), + .io_csr_pkt_csr_mhpmc6(csr_read_io_csr_pkt_csr_mhpmc6), + .io_csr_pkt_csr_mhpmc3h(csr_read_io_csr_pkt_csr_mhpmc3h), + .io_csr_pkt_csr_mhpmc4h(csr_read_io_csr_pkt_csr_mhpmc4h), + .io_csr_pkt_csr_mhpmc5h(csr_read_io_csr_pkt_csr_mhpmc5h), + .io_csr_pkt_csr_mhpmc6h(csr_read_io_csr_pkt_csr_mhpmc6h), + .io_csr_pkt_csr_mhpme3(csr_read_io_csr_pkt_csr_mhpme3), + .io_csr_pkt_csr_mhpme4(csr_read_io_csr_pkt_csr_mhpme4), + .io_csr_pkt_csr_mhpme5(csr_read_io_csr_pkt_csr_mhpme5), + .io_csr_pkt_csr_mhpme6(csr_read_io_csr_pkt_csr_mhpme6), + .io_csr_pkt_csr_mcountinhibit(csr_read_io_csr_pkt_csr_mcountinhibit), + .io_csr_pkt_csr_mitctl0(csr_read_io_csr_pkt_csr_mitctl0), + .io_csr_pkt_csr_mitctl1(csr_read_io_csr_pkt_csr_mitctl1), + .io_csr_pkt_csr_mitb0(csr_read_io_csr_pkt_csr_mitb0), + .io_csr_pkt_csr_mitb1(csr_read_io_csr_pkt_csr_mitb1), + .io_csr_pkt_csr_mitcnt0(csr_read_io_csr_pkt_csr_mitcnt0), + .io_csr_pkt_csr_mitcnt1(csr_read_io_csr_pkt_csr_mitcnt1), + .io_csr_pkt_csr_mpmc(csr_read_io_csr_pkt_csr_mpmc), + .io_csr_pkt_csr_meicpct(csr_read_io_csr_pkt_csr_meicpct), + .io_csr_pkt_csr_micect(csr_read_io_csr_pkt_csr_micect), + .io_csr_pkt_csr_miccmect(csr_read_io_csr_pkt_csr_miccmect), + .io_csr_pkt_csr_mdccmect(csr_read_io_csr_pkt_csr_mdccmect), + .io_csr_pkt_csr_mfdht(csr_read_io_csr_pkt_csr_mfdht), + .io_csr_pkt_csr_mfdhs(csr_read_io_csr_pkt_csr_mfdhs), + .io_csr_pkt_csr_dicawics(csr_read_io_csr_pkt_csr_dicawics), + .io_csr_pkt_csr_dicad0h(csr_read_io_csr_pkt_csr_dicad0h), + .io_csr_pkt_csr_dicad0(csr_read_io_csr_pkt_csr_dicad0), + .io_csr_pkt_csr_dicad1(csr_read_io_csr_pkt_csr_dicad1), + .io_csr_pkt_csr_dicago(csr_read_io_csr_pkt_csr_dicago), + .io_csr_pkt_presync(csr_read_io_csr_pkt_presync), + .io_csr_pkt_postsync(csr_read_io_csr_pkt_postsync), + .io_csr_pkt_legal(csr_read_io_csr_pkt_legal) + ); + assign io_tlu_exu_dec_tlu_meihap = csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 879:58] + assign io_tlu_exu_dec_tlu_flush_lower_r = int_exc_io_dec_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 810:54] + assign io_tlu_exu_dec_tlu_flush_path_r = int_exc_io_dec_tlu_flush_path_r; // @[dec_tlu_ctl.scala 811:54] + assign io_tlu_dma_dec_tlu_dma_qos_prty = csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 910:54] + assign io_dec_tlu_core_empty = force_halt | _T_228; // @[dec_tlu_ctl.scala 436:31] + assign io_dec_dbg_cmd_done = io_dec_tlu_i0_valid_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 510:29] + assign io_dec_dbg_cmd_fail = illegal_r & io_dec_dbg_cmd_done; // @[dec_tlu_ctl.scala 511:29] + assign io_dec_tlu_dbg_halted = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 492:41] + assign io_dec_tlu_debug_mode = debug_mode_status; // @[dec_tlu_ctl.scala 493:41] + assign io_dec_tlu_resume_ack = _T_286; // @[dec_tlu_ctl.scala 473:53] + assign io_dec_tlu_debug_stall = debug_halt_req_f; // @[dec_tlu_ctl.scala 491:41] + assign io_dec_tlu_mpc_halted_only = _T_143; // @[dec_tlu_ctl.scala 386:42] + assign io_dec_tlu_flush_extint = int_exc_io_take_ext_int_start; // @[dec_tlu_ctl.scala 499:33] + assign io_trigger_pkt_any_0_select = csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_0_match_pkt = csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_0_store = csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_0_load = csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_0_execute = csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_0_m = csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_0_tdata2 = csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_1_select = csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_1_match_pkt = csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_1_store = csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_1_load = csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_1_execute = csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_1_m = csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_1_tdata2 = csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_2_select = csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_2_match_pkt = csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_2_store = csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_2_load = csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_2_execute = csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_2_m = csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_2_tdata2 = csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_3_select = csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_3_match_pkt = csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_3_store = csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_3_load = csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_3_execute = csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_3_m = csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_3_tdata2 = csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 885:46] + assign io_o_cpu_halt_status = _T_512; // @[dec_tlu_ctl.scala 606:60] + assign io_o_cpu_halt_ack = _T_516; // @[dec_tlu_ctl.scala 607:68] + assign io_o_cpu_run_ack = _T_520; // @[dec_tlu_ctl.scala 608:68] + assign io_o_debug_mode_status = debug_mode_status; // @[dec_tlu_ctl.scala 630:32] + assign io_mpc_debug_halt_ack = mpc_debug_halt_ack_f; // @[dec_tlu_ctl.scala 412:31] + assign io_mpc_debug_run_ack = mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 413:31] + assign io_debug_brkpt_status = debug_brkpt_status_f; // @[dec_tlu_ctl.scala 414:31] + assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 901:46] + assign io_dec_csr_legal_d = _T_731 & _T_738; // @[dec_tlu_ctl.scala 1028:28] + assign io_dec_tlu_i0_kill_writeb_wb = _T_52; // @[dec_tlu_ctl.scala 343:41] + assign io_dec_tlu_i0_kill_writeb_r = _T_609 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 349:41] + assign io_dec_tlu_wr_pause_r = csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 903:46] + assign io_dec_tlu_flush_pause_r = _T_342 & _T_343; // @[dec_tlu_ctl.scala 502:34] + assign io_dec_tlu_presync_d = _T_708 & _T_709; // @[dec_tlu_ctl.scala 1021:31] + assign io_dec_tlu_postsync_d = csr_pkt_postsync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1022:31] + assign io_dec_tlu_perfcnt0 = csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 888:46] + assign io_dec_tlu_perfcnt1 = csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 889:46] + assign io_dec_tlu_perfcnt2 = csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 890:46] + assign io_dec_tlu_perfcnt3 = csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 891:46] + assign io_dec_tlu_i0_exc_valid_wb1 = csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 882:50] + assign io_dec_tlu_i0_valid_wb1 = csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 883:50] + assign io_dec_tlu_int_valid_wb1 = csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 881:50] + assign io_dec_tlu_exc_cause_wb1 = csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 887:46] + assign io_dec_tlu_mtval_wb1 = csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 886:46] + assign io_dec_tlu_pipelining_disable = csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 902:46] + assign io_dec_tlu_trace_disable = csr_io_dec_tlu_trace_disable; // @[dec_tlu_ctl.scala 911:49] + assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 892:46] + assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 894:46] + assign io_dec_tlu_ifu_clk_override = csr_io_dec_tlu_ifu_clk_override; // @[dec_tlu_ctl.scala 895:46] + assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 896:46] + assign io_dec_tlu_bus_clk_override = csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 897:46] + assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 898:46] + assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 899:46] + assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 900:46] + assign io_dec_tlu_flush_lower_wb = int_exc_io_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 809:46] + assign io_tlu_bp_dec_tlu_br0_r_pkt_valid = _T_643 & _T_646; // @[dec_tlu_ctl.scala 687:73] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist = io_tlu_exu_exu_i0_br_hist_r; // @[dec_tlu_ctl.scala 684:73] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error = _T_635 & _T_611; // @[dec_tlu_ctl.scala 685:73] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error = _T_638 & _T_611; // @[dec_tlu_ctl.scala 686:73] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[dec_tlu_ctl.scala 688:73] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle = io_tlu_exu_exu_i0_br_middle_r; // @[dec_tlu_ctl.scala 689:81] + assign io_tlu_bp_dec_tlu_flush_leak_one_wb = _T_367 & _T_368; // @[dec_tlu_ctl.scala 506:45] + assign io_tlu_bp_dec_tlu_bpred_disable = csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 906:53] + assign io_tlu_ifc_dec_tlu_flush_noredir_wb = _T_339 | take_ext_int_start; // @[dec_tlu_ctl.scala 497:45] + assign io_tlu_ifc_dec_tlu_mrac_ff = csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 904:54] + assign io_tlu_mem_dec_tlu_flush_err_wb = io_tlu_exu_dec_tlu_flush_lower_r & _T_615; // @[dec_tlu_ctl.scala 507:41] + assign io_tlu_mem_dec_tlu_i0_commit_cmt = _T_604 & _T_619; // @[dec_tlu_ctl.scala 658:42] + assign io_tlu_mem_dec_tlu_force_halt = _T_59; // @[dec_tlu_ctl.scala 345:41] + assign io_tlu_mem_dec_tlu_fence_i_wb = _T_677 & _T_590; // @[dec_tlu_ctl.scala 719:39] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata = csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 884:58] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics = csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 884:58] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid = csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 884:58] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid = csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 884:58] + assign io_tlu_mem_dec_tlu_core_ecc_disable = csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 908:54] + assign io_tlu_busbuff_dec_tlu_external_ldfwd_disable = csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 909:58] + assign io_tlu_busbuff_dec_tlu_wb_coalescing_disable = csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 905:58] + assign io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 907:58] + assign io_dec_pic_dec_tlu_meicurpl = csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 878:58] + assign io_dec_pic_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 880:58] + assign int_exc_clock = clock; + assign int_exc_reset = reset; + assign int_exc_io_ext_int_freeze_d1 = csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 789:42] + assign int_exc_io_take_ext_int_start_d1 = csr_io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 790:44] + assign int_exc_io_take_ext_int_start_d2 = csr_io_take_ext_int_start_d2; // @[dec_tlu_ctl.scala 791:44] + assign int_exc_io_take_ext_int_start_d3 = csr_io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 792:44] + assign int_exc_io_dec_csr_stall_int_ff = io_dec_csr_stall_int_ff; // @[dec_tlu_ctl.scala 724:49] + assign int_exc_io_mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 725:49] + assign int_exc_io_mip = csr_io_mip; // @[dec_tlu_ctl.scala 726:49] + assign int_exc_io_mie_ns = csr_io_mie_ns; // @[dec_tlu_ctl.scala 727:49] + assign int_exc_io_mret_r = _T_672 & _T_590; // @[dec_tlu_ctl.scala 728:49] + assign int_exc_io_pmu_fw_tlu_halted_f = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 729:49] + assign int_exc_io_int_timer0_int_hold_f = int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 730:49] + assign int_exc_io_int_timer1_int_hold_f = int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 731:49] + assign int_exc_io_internal_dbg_halt_mode_f = debug_mode_status; // @[dec_tlu_ctl.scala 732:49] + assign int_exc_io_dcsr_single_step_running = _T_255 | _T_257; // @[dec_tlu_ctl.scala 733:49] + assign int_exc_io_internal_dbg_halt_mode = debug_halt_req_ns | _T_238; // @[dec_tlu_ctl.scala 734:49] + assign int_exc_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 735:49] + assign int_exc_io_internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | _T_549; // @[dec_tlu_ctl.scala 736:49] + assign int_exc_io_i_cpu_halt_req_d1 = i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 737:49] + assign int_exc_io_ebreak_to_debug_mode_r = _T_704 & _T_590; // @[dec_tlu_ctl.scala 738:49] + assign int_exc_io_lsu_fir_error = io_lsu_fir_error; // @[dec_tlu_ctl.scala 739:49] + assign int_exc_io_csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 740:49] + assign int_exc_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 741:49] + assign int_exc_io_lsu_fastint_stall_any = io_lsu_fastint_stall_any; // @[dec_tlu_ctl.scala 742:49] + assign int_exc_io_reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 743:49] + assign int_exc_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 744:49] + assign int_exc_io_nmi_int_detected = _T_81 | nmi_fir_type; // @[dec_tlu_ctl.scala 745:49] + assign int_exc_io_dcsr_single_step_running_f = dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 746:49] + assign int_exc_io_dcsr_single_step_done_f = dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 747:49] + assign int_exc_io_dcsr = csr_io_dcsr; // @[dec_tlu_ctl.scala 748:49] + assign int_exc_io_mtvec = csr_io_mtvec; // @[dec_tlu_ctl.scala 749:49] + assign int_exc_io_tlu_i0_commit_cmt = _T_604 & _T_619; // @[dec_tlu_ctl.scala 750:49] + assign int_exc_io_i0_trigger_hit_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 751:49] + assign int_exc_io_pause_expired_r = _T_361 & _T_362; // @[dec_tlu_ctl.scala 752:49] + assign int_exc_io_nmi_vec = io_nmi_vec; // @[dec_tlu_ctl.scala 753:49] + assign int_exc_io_lsu_i0_rfnpc_r = _T_592 & _T_594; // @[dec_tlu_ctl.scala 754:49] + assign int_exc_io_fence_i_r = _T_677 & _T_590; // @[dec_tlu_ctl.scala 755:49] + assign int_exc_io_iccm_repair_state_rfnpc = _T_626 & _T_634; // @[dec_tlu_ctl.scala 756:49] + assign int_exc_io_i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_584; // @[dec_tlu_ctl.scala 757:49] + assign int_exc_io_rfpc_i0_r = _T_620 & _T_621; // @[dec_tlu_ctl.scala 758:49] + assign int_exc_io_lsu_exc_valid_r = _T_589 & _T_590; // @[dec_tlu_ctl.scala 759:49] + assign int_exc_io_trigger_hit_dmode_r = i0_trigger_hit_raw_r & i0_trigger_action_r; // @[dec_tlu_ctl.scala 760:49] + assign int_exc_io_take_halt = _T_208 & _T_209; // @[dec_tlu_ctl.scala 761:49] + assign int_exc_io_rst_vec = io_rst_vec; // @[dec_tlu_ctl.scala 762:49] + assign int_exc_io_lsu_fir_addr = io_lsu_fir_addr; // @[dec_tlu_ctl.scala 763:49] + assign int_exc_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 764:49] + assign int_exc_io_npc_r = csr_io_npc_r; // @[dec_tlu_ctl.scala 765:49] + assign int_exc_io_mepc = csr_io_mepc; // @[dec_tlu_ctl.scala 766:49] + assign int_exc_io_debug_resume_req_f = debug_resume_req_f_raw & _T_333; // @[dec_tlu_ctl.scala 767:49] + assign int_exc_io_dpc = csr_io_dpc; // @[dec_tlu_ctl.scala 768:49] + assign int_exc_io_npc_r_d1 = csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 769:49] + assign int_exc_io_tlu_flush_lower_r_d1 = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 770:49] + assign int_exc_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 771:49] + assign int_exc_io_ebreak_r = _T_654 & _T_590; // @[dec_tlu_ctl.scala 772:49] + assign int_exc_io_ecall_r = _T_660 & _T_590; // @[dec_tlu_ctl.scala 773:49] + assign int_exc_io_illegal_r = _T_666 & _T_590; // @[dec_tlu_ctl.scala 774:49] + assign int_exc_io_inst_acc_r = _T_696 & _T_619; // @[dec_tlu_ctl.scala 775:49] + assign int_exc_io_lsu_i0_exc_r = _T_589 & _T_590; // @[dec_tlu_ctl.scala 776:49] + assign int_exc_io_lsu_error_pkt_r_bits_inst_type = io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 777:49] + assign int_exc_io_lsu_error_pkt_r_bits_exc_type = io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 777:49] + assign int_exc_io_dec_tlu_wr_pause_r_d1 = dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 778:42] + assign csr_clock = clock; + assign csr_reset = reset; + assign csr_io_free_l2clk = io_free_l2clk; // @[dec_tlu_ctl.scala 822:50] + assign csr_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 821:50] + assign csr_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 824:50] + assign csr_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 825:50] + assign csr_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 826:50] + assign csr_io_dec_csr_wen_unq_d = io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 827:50] + assign csr_io_dec_i0_decode_d = io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 828:50] + assign csr_io_ifu_ic_debug_rd_data_valid = io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 829:50] + assign csr_io_ifu_pmu_bus_trxn = io_tlu_mem_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 830:50] + assign csr_io_dma_iccm_stall_any = io_tlu_dma_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 831:50] + assign csr_io_dma_dccm_stall_any = io_tlu_dma_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 832:50] + assign csr_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 833:50] + assign csr_io_dec_pmu_presync_stall = io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 834:50] + assign csr_io_dec_pmu_postsync_stall = io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 835:50] + assign csr_io_dec_pmu_decode_stall = io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 836:50] + assign csr_io_ifu_pmu_fetch_stall = io_tlu_ifc_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 837:50] + assign csr_io_dec_tlu_packet_r_icaf_type = io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 838:50] + assign csr_io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 838:50] + assign csr_io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 838:50] + assign csr_io_dec_tlu_packet_r_pmu_divide = io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 838:50] + assign csr_io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 838:50] + assign csr_io_exu_pmu_i0_br_ataken = io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 839:50] + assign csr_io_exu_pmu_i0_br_misp = io_tlu_exu_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 840:50] + assign csr_io_dec_pmu_instr_decoded = io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 841:50] + assign csr_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 842:50] + assign csr_io_exu_pmu_i0_pc4 = io_tlu_exu_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 843:50] + assign csr_io_ifu_pmu_ic_miss = io_tlu_mem_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 844:50] + assign csr_io_ifu_pmu_ic_hit = io_tlu_mem_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 845:50] + assign csr_io_dec_csr_wen_r = io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 846:50] + assign csr_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 847:50] + assign csr_io_dma_pmu_dccm_write = io_tlu_dma_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 848:50] + assign csr_io_dma_pmu_dccm_read = io_tlu_dma_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 849:50] + assign csr_io_dma_pmu_any_write = io_tlu_dma_dma_pmu_any_write; // @[dec_tlu_ctl.scala 850:50] + assign csr_io_dma_pmu_any_read = io_tlu_dma_dma_pmu_any_read; // @[dec_tlu_ctl.scala 851:50] + assign csr_io_lsu_pmu_bus_busy = io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 852:50] + assign csr_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 853:50] + assign csr_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 854:50] + assign csr_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 856:50] + assign csr_io_ifu_pmu_bus_busy = io_tlu_mem_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 857:50] + assign csr_io_lsu_pmu_bus_error = io_tlu_busbuff_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 858:50] + assign csr_io_ifu_pmu_bus_error = io_tlu_mem_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 859:50] + assign csr_io_lsu_pmu_bus_misaligned = io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 860:50] + assign csr_io_lsu_pmu_bus_trxn = io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 861:50] + assign csr_io_ifu_ic_debug_rd_data = io_tlu_mem_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 862:50] + assign csr_io_pic_pl = io_dec_pic_pic_pl; // @[dec_tlu_ctl.scala 863:50] + assign csr_io_pic_claimid = io_dec_pic_pic_claimid; // @[dec_tlu_ctl.scala 864:50] + assign csr_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 865:50] + assign csr_io_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 866:50] + assign csr_io_lsu_imprecise_error_load_any = io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 867:50] + assign csr_io_lsu_imprecise_error_store_any = io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 868:50] + assign csr_io_dec_illegal_inst = io_dec_illegal_inst; // @[dec_tlu_ctl.scala 869:50 dec_tlu_ctl.scala 912:50] + assign csr_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 870:50 dec_tlu_ctl.scala 913:50] + assign csr_io_mexintpend = io_dec_pic_mexintpend; // @[dec_tlu_ctl.scala 871:50 dec_tlu_ctl.scala 914:50] + assign csr_io_exu_npc_r = io_tlu_exu_exu_npc_r; // @[dec_tlu_ctl.scala 872:50 dec_tlu_ctl.scala 915:50] + assign csr_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 873:50 dec_tlu_ctl.scala 916:50] + assign csr_io_rst_vec = io_rst_vec; // @[dec_tlu_ctl.scala 874:50 dec_tlu_ctl.scala 917:50] + assign csr_io_core_id = io_core_id; // @[dec_tlu_ctl.scala 875:50 dec_tlu_ctl.scala 918:50] + assign csr_io_dec_timer_rddata_d = int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 876:50 dec_tlu_ctl.scala 919:50] + assign csr_io_dec_timer_read_d = int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 877:50 dec_tlu_ctl.scala 920:50] + assign csr_io_rfpc_i0_r = _T_620 & _T_621; // @[dec_tlu_ctl.scala 923:45] + assign csr_io_i0_trigger_hit_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 924:45] + assign csr_io_exc_or_int_valid_r = int_exc_io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 925:45] + assign csr_io_mret_r = _T_672 & _T_590; // @[dec_tlu_ctl.scala 926:45] + assign csr_io_dcsr_single_step_running_f = dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 927:45] + assign csr_io_dec_timer_t0_pulse = int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 928:45] + assign csr_io_dec_timer_t1_pulse = int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 929:45] + assign csr_io_timer_int_sync = syncro_ff[5]; // @[dec_tlu_ctl.scala 930:45] + assign csr_io_soft_int_sync = syncro_ff[4]; // @[dec_tlu_ctl.scala 931:45] + assign csr_io_csr_wr_clk = clock; // @[dec_tlu_ctl.scala 932:45] + assign csr_io_ebreak_to_debug_mode_r = _T_704 & _T_590; // @[dec_tlu_ctl.scala 933:45] + assign csr_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 934:45] + assign csr_io_lsu_fir_error = io_lsu_fir_error; // @[dec_tlu_ctl.scala 935:45] + assign csr_io_tlu_flush_lower_r_d1 = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 936:45] + assign csr_io_dec_tlu_flush_noredir_r_d1 = dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 937:45] + assign csr_io_tlu_flush_path_r_d1 = int_exc_io_tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 938:45] + assign csr_io_reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 939:45] + assign csr_io_interrupt_valid_r = int_exc_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 940:45] + assign csr_io_i0_exception_valid_r = int_exc_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 941:45] + assign csr_io_lsu_exc_valid_r = _T_589 & _T_590; // @[dec_tlu_ctl.scala 942:45] + assign csr_io_mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_495; // @[dec_tlu_ctl.scala 943:45] + assign csr_io_lsu_single_ecc_error_r = io_lsu_single_ecc_error_incr; // @[dec_tlu_ctl.scala 944:45] + assign csr_io_e4e5_int_clk = clock; // @[dec_tlu_ctl.scala 945:45] + assign csr_io_lsu_i0_exc_r = _T_589 & _T_590; // @[dec_tlu_ctl.scala 946:45] + assign csr_io_inst_acc_r = _T_696 & _T_619; // @[dec_tlu_ctl.scala 947:45] + assign csr_io_inst_acc_second_r = io_dec_tlu_packet_r_icaf_second; // @[dec_tlu_ctl.scala 948:45] + assign csr_io_take_nmi = int_exc_io_take_nmi; // @[dec_tlu_ctl.scala 949:45] + assign csr_io_lsu_error_pkt_addr_r = io_lsu_error_pkt_r_bits_addr; // @[dec_tlu_ctl.scala 950:45] + assign csr_io_exc_cause_r = int_exc_io_exc_cause_r; // @[dec_tlu_ctl.scala 951:45] + assign csr_io_i0_valid_wb = int_exc_io_i0_valid_wb; // @[dec_tlu_ctl.scala 952:45] + assign csr_io_interrupt_valid_r_d1 = int_exc_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 954:45] + assign csr_io_i0_exception_valid_r_d1 = int_exc_io_i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 956:45] + assign csr_io_exc_cause_wb = int_exc_io_exc_cause_wb; // @[dec_tlu_ctl.scala 958:45] + assign csr_io_nmi_lsu_store_type = _T_95 | _T_97; // @[dec_tlu_ctl.scala 959:45] + assign csr_io_nmi_lsu_load_type = _T_87 | _T_89; // @[dec_tlu_ctl.scala 960:45] + assign csr_io_tlu_i0_commit_cmt = _T_604 & _T_619; // @[dec_tlu_ctl.scala 961:45] + assign csr_io_ebreak_r = _T_654 & _T_590; // @[dec_tlu_ctl.scala 962:45] + assign csr_io_ecall_r = _T_660 & _T_590; // @[dec_tlu_ctl.scala 963:45] + assign csr_io_illegal_r = _T_666 & _T_590; // @[dec_tlu_ctl.scala 964:45] + assign csr_io_nmi_int_detected_f = nmi_int_detected_f; // @[dec_tlu_ctl.scala 966:45] + assign csr_io_internal_dbg_halt_mode_f2 = internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 967:45] + assign csr_io_ext_int_freeze = int_exc_io_ext_int_freeze; // @[dec_tlu_ctl.scala 820:32] + assign csr_io_ic_perr_r = _T_684 & _T_685; // @[dec_tlu_ctl.scala 969:45] + assign csr_io_iccm_sbecc_r = _T_691 & _T_685; // @[dec_tlu_ctl.scala 970:45] + assign csr_io_ifu_miss_state_idle_f = ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 972:45] + assign csr_io_lsu_idle_any_f = lsu_idle_any_f; // @[dec_tlu_ctl.scala 973:45] + assign csr_io_dbg_tlu_halted_f = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 974:45] + assign csr_io_dbg_tlu_halted = _T_242 | _T_244; // @[dec_tlu_ctl.scala 975:45] + assign csr_io_debug_halt_req_f = debug_halt_req_f; // @[dec_tlu_ctl.scala 976:59] + assign csr_io_take_ext_int_start = int_exc_io_take_ext_int_start; // @[dec_tlu_ctl.scala 977:55] + assign csr_io_trigger_hit_dmode_r_d1 = trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 978:43] + assign csr_io_trigger_hit_r_d1 = int_exc_io_trigger_hit_r_d1; // @[dec_tlu_ctl.scala 979:43] + assign csr_io_dcsr_single_step_done_f = dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 980:43] + assign csr_io_ebreak_to_debug_mode_r_d1 = ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 981:45] + assign csr_io_debug_halt_req = _T_192 & _T_680; // @[dec_tlu_ctl.scala 982:51] + assign csr_io_allow_dbg_halt_csr_write = debug_mode_status & _T_155; // @[dec_tlu_ctl.scala 983:45] + assign csr_io_internal_dbg_halt_mode_f = debug_mode_status; // @[dec_tlu_ctl.scala 984:45] + assign csr_io_enter_debug_halt_req = _T_233 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 985:45] + assign csr_io_internal_dbg_halt_mode = debug_halt_req_ns | _T_238; // @[dec_tlu_ctl.scala 986:45] + assign csr_io_request_debug_mode_done = _T_261 & _T_214; // @[dec_tlu_ctl.scala 987:45] + assign csr_io_request_debug_mode_r = _T_258 | _T_260; // @[dec_tlu_ctl.scala 988:45] + assign csr_io_update_hit_bit_r = _T_485 & _T_492; // @[dec_tlu_ctl.scala 989:45] + assign csr_io_take_timer_int = int_exc_io_take_timer_int; // @[dec_tlu_ctl.scala 990:45] + assign csr_io_take_int_timer0_int = int_exc_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 991:45] + assign csr_io_take_int_timer1_int = int_exc_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 992:45] + assign csr_io_take_ext_int = int_exc_io_take_ext_int; // @[dec_tlu_ctl.scala 993:45] + assign csr_io_tlu_flush_lower_r = int_exc_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 994:45] + assign csr_io_dec_tlu_br0_error_r = _T_635 & _T_611; // @[dec_tlu_ctl.scala 995:45] + assign csr_io_dec_tlu_br0_start_error_r = _T_638 & _T_611; // @[dec_tlu_ctl.scala 996:45] + assign csr_io_lsu_pmu_load_external_r = lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 997:45] + assign csr_io_lsu_pmu_store_external_r = lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 998:45] + assign csr_io_csr_pkt_csr_misa = csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mstatus = csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mtvec = csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mip = csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mie = csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mcyclel = csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mcycleh = csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_minstretl = csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_minstreth = csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mscratch = csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mepc = csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mcause = csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mscause = csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mtval = csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mrac = csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_meivt = csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_meipt = csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_meicurpl = csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_meicidpl = csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mcgc = csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mfdc = csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mtsel = csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mtdata1 = csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mtdata2 = csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpmc3 = csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpmc4 = csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpmc5 = csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpmc6 = csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpmc3h = csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpmc4h = csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpmc5h = csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpmc6h = csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpme3 = csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpme4 = csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpme5 = csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpme6 = csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mcountinhibit = csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mpmc = csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_micect = csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_miccmect = csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mdccmect = csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mfdht = csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mfdhs = csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_trigger_enabled = {_T_412,_T_411}; // @[dec_tlu_ctl.scala 999:45] + assign int_timers_clock = clock; + assign int_timers_reset = reset; + assign int_timers_io_free_l2clk = io_free_l2clk; // @[dec_tlu_ctl.scala 285:65] + assign int_timers_io_csr_wr_clk = clock; // @[dec_tlu_ctl.scala 321:52] + assign int_timers_io_dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 287:49] + assign int_timers_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 289:49] + assign int_timers_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 290:49] + assign int_timers_io_csr_mitctl0 = csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 291:57] + assign int_timers_io_csr_mitctl1 = csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 292:57] + assign int_timers_io_csr_mitb0 = csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 293:57] + assign int_timers_io_csr_mitb1 = csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 294:57] + assign int_timers_io_csr_mitcnt0 = csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 295:57] + assign int_timers_io_csr_mitcnt1 = csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 296:57] + assign int_timers_io_dec_pause_state = io_dec_pause_state; // @[dec_tlu_ctl.scala 297:49] + assign int_timers_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 298:49] + assign int_timers_io_internal_dbg_halt_timers = int_exc_io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 299:47] + assign csr_read_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1018:37] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + dbg_halt_state_f = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + mpc_halt_state_f = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_8 = _RAND_2[6:0]; + _RAND_3 = {1{`RANDOM}}; + syncro_ff = _RAND_3[6:0]; + _RAND_4 = {1{`RANDOM}}; + debug_mode_status = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + i_cpu_run_req_d1_raw = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + nmi_int_delayed = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + nmi_int_detected_f = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + int_timer0_int_hold_f = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + int_timer1_int_hold_f = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + i_cpu_halt_req_d1 = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + reset_detect = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + reset_detected = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + dec_pause_state_f = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + debug_halt_req_f = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + pmu_fw_halt_req_f = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + halt_taken_f = _RAND_16[0:0]; + _RAND_17 = {1{`RANDOM}}; + ifu_ic_error_start_f = _RAND_17[0:0]; + _RAND_18 = {1{`RANDOM}}; + debug_resume_req_f_raw = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + dcsr_single_step_running_f = _RAND_19[0:0]; + _RAND_20 = {1{`RANDOM}}; + dcsr_single_step_done_f = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + internal_pmu_fw_halt_mode_f = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + ifu_iccm_rd_ecc_single_err_f = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + iccm_repair_state_d1 = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + dbg_halt_req_held = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + trigger_hit_dmode_r_d1 = _RAND_25[0:0]; + _RAND_26 = {1{`RANDOM}}; + ebreak_to_debug_mode_r_d1 = _RAND_26[0:0]; + _RAND_27 = {1{`RANDOM}}; + lsu_idle_any_f = _RAND_27[0:0]; + _RAND_28 = {1{`RANDOM}}; + ifu_miss_state_idle_f = _RAND_28[0:0]; + _RAND_29 = {1{`RANDOM}}; + debug_halt_req_d1 = _RAND_29[0:0]; + _RAND_30 = {1{`RANDOM}}; + dec_tlu_flush_noredir_r_d1 = _RAND_30[0:0]; + _RAND_31 = {1{`RANDOM}}; + dec_tlu_flush_pause_r_d1 = _RAND_31[0:0]; + _RAND_32 = {1{`RANDOM}}; + dbg_tlu_halted_f = _RAND_32[0:0]; + _RAND_33 = {1{`RANDOM}}; + pmu_fw_tlu_halted_f = _RAND_33[0:0]; + _RAND_34 = {1{`RANDOM}}; + lsu_pmu_load_external_r = _RAND_34[0:0]; + _RAND_35 = {1{`RANDOM}}; + lsu_pmu_store_external_r = _RAND_35[0:0]; + _RAND_36 = {1{`RANDOM}}; + tlu_flush_lower_r_d1 = _RAND_36[0:0]; + _RAND_37 = {1{`RANDOM}}; + _T_52 = _RAND_37[0:0]; + _RAND_38 = {1{`RANDOM}}; + internal_dbg_halt_mode_f2 = _RAND_38[0:0]; + _RAND_39 = {1{`RANDOM}}; + _T_59 = _RAND_39[0:0]; + _RAND_40 = {1{`RANDOM}}; + nmi_lsu_load_type_f = _RAND_40[0:0]; + _RAND_41 = {1{`RANDOM}}; + nmi_lsu_store_type_f = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + mpc_debug_halt_req_sync_f = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + mpc_debug_run_req_sync_f = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + mpc_run_state_f = _RAND_44[0:0]; + _RAND_45 = {1{`RANDOM}}; + mpc_debug_run_ack_f = _RAND_45[0:0]; + _RAND_46 = {1{`RANDOM}}; + debug_brkpt_status_f = _RAND_46[0:0]; + _RAND_47 = {1{`RANDOM}}; + mpc_debug_halt_ack_f = _RAND_47[0:0]; + _RAND_48 = {1{`RANDOM}}; + dbg_run_state_f = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + _T_143 = _RAND_49[0:0]; + _RAND_50 = {1{`RANDOM}}; + request_debug_mode_r_d1 = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + request_debug_mode_done_f = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + _T_286 = _RAND_52[0:0]; + _RAND_53 = {1{`RANDOM}}; + dec_tlu_wr_pause_r_d1 = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + _T_512 = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + _T_516 = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + _T_520 = _RAND_56[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + dbg_halt_state_f = 1'h0; + end + if (reset) begin + mpc_halt_state_f = 1'h0; + end + if (reset) begin + _T_8 = 7'h0; + end + if (reset) begin + syncro_ff = 7'h0; + end + if (reset) begin + debug_mode_status = 1'h0; + end + if (reset) begin + i_cpu_run_req_d1_raw = 1'h0; + end + if (reset) begin + nmi_int_delayed = 1'h0; + end + if (reset) begin + nmi_int_detected_f = 1'h0; + end + if (reset) begin + int_timer0_int_hold_f = 1'h0; + end + if (reset) begin + int_timer1_int_hold_f = 1'h0; + end + if (reset) begin + i_cpu_halt_req_d1 = 1'h0; + end + if (reset) begin + reset_detect = 1'h0; + end + if (reset) begin + reset_detected = 1'h0; + end + if (reset) begin + dec_pause_state_f = 1'h0; + end + if (reset) begin + debug_halt_req_f = 1'h0; + end + if (reset) begin + pmu_fw_halt_req_f = 1'h0; + end + if (reset) begin + halt_taken_f = 1'h0; + end + if (reset) begin + ifu_ic_error_start_f = 1'h0; + end + if (reset) begin + debug_resume_req_f_raw = 1'h0; + end + if (reset) begin + dcsr_single_step_running_f = 1'h0; + end + if (reset) begin + dcsr_single_step_done_f = 1'h0; + end + if (reset) begin + internal_pmu_fw_halt_mode_f = 1'h0; + end + if (reset) begin + ifu_iccm_rd_ecc_single_err_f = 1'h0; + end + if (reset) begin + iccm_repair_state_d1 = 1'h0; + end + if (reset) begin + dbg_halt_req_held = 1'h0; + end + if (reset) begin + trigger_hit_dmode_r_d1 = 1'h0; + end + if (reset) begin + ebreak_to_debug_mode_r_d1 = 1'h0; + end + if (reset) begin + lsu_idle_any_f = 1'h0; + end + if (reset) begin + ifu_miss_state_idle_f = 1'h0; + end + if (reset) begin + debug_halt_req_d1 = 1'h0; + end + if (reset) begin + dec_tlu_flush_noredir_r_d1 = 1'h0; + end + if (reset) begin + dec_tlu_flush_pause_r_d1 = 1'h0; + end + if (reset) begin + dbg_tlu_halted_f = 1'h0; + end + if (reset) begin + pmu_fw_tlu_halted_f = 1'h0; + end + if (reset) begin + lsu_pmu_load_external_r = 1'h0; + end + if (reset) begin + lsu_pmu_store_external_r = 1'h0; + end + if (reset) begin + tlu_flush_lower_r_d1 = 1'h0; + end + if (reset) begin + _T_52 = 1'h0; + end + if (reset) begin + internal_dbg_halt_mode_f2 = 1'h0; + end + if (reset) begin + _T_59 = 1'h0; + end + if (reset) begin + nmi_lsu_load_type_f = 1'h0; + end + if (reset) begin + nmi_lsu_store_type_f = 1'h0; + end + if (reset) begin + mpc_debug_halt_req_sync_f = 1'h0; + end + if (reset) begin + mpc_debug_run_req_sync_f = 1'h0; + end + if (reset) begin + mpc_run_state_f = 1'h0; + end + if (reset) begin + mpc_debug_run_ack_f = 1'h0; + end + if (reset) begin + debug_brkpt_status_f = 1'h0; + end + if (reset) begin + mpc_debug_halt_ack_f = 1'h0; + end + if (reset) begin + dbg_run_state_f = 1'h0; + end + if (reset) begin + _T_143 = 1'h0; + end + if (reset) begin + request_debug_mode_r_d1 = 1'h0; + end + if (reset) begin + request_debug_mode_done_f = 1'h0; + end + if (reset) begin + _T_286 = 1'h0; + end + if (reset) begin + dec_tlu_wr_pause_r_d1 = 1'h0; + end + if (reset) begin + _T_512 = 1'h0; + end + if (reset) begin + _T_516 = 1'h0; + end + if (reset) begin + _T_520 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dbg_halt_state_f <= 1'h0; + end else if (_T_135) begin + dbg_halt_state_f <= dbg_halt_state_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + mpc_halt_state_f <= 1'h0; + end else if (_T_119) begin + mpc_halt_state_f <= mpc_halt_state_ns; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_8 <= 7'h0; + end else begin + _T_8 <= {_T_6,_T_3}; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + syncro_ff <= 7'h0; + end else begin + syncro_ff <= _T_8; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + debug_mode_status <= 1'h0; + end else if (_T_38) begin + debug_mode_status <= internal_dbg_halt_mode; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + i_cpu_run_req_d1_raw <= 1'h0; + end else if (_T_507) begin + i_cpu_run_req_d1_raw <= i_cpu_run_req_sync_qual; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + nmi_int_delayed <= 1'h0; + end else if (_T_61) begin + nmi_int_delayed <= nmi_int_sync; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + nmi_int_detected_f <= 1'h0; + end else if (_T_64) begin + nmi_int_detected_f <= nmi_int_detected; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + int_timer0_int_hold_f <= 1'h0; + end else if (_T_534) begin + int_timer0_int_hold_f <= int_timer0_int_hold; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + int_timer1_int_hold_f <= 1'h0; + end else if (_T_538) begin + int_timer1_int_hold_f <= int_timer1_int_hold; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + i_cpu_halt_req_d1 <= 1'h0; + end else if (_T_504) begin + i_cpu_halt_req_d1 <= i_cpu_halt_req_sync_qual; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + reset_detect <= 1'h0; + end else begin + reset_detect <= _T_104 | reset_detect; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + reset_detected <= 1'h0; + end else if (_T_107) begin + reset_detected <= reset_detect; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dec_pause_state_f <= 1'h0; + end else if (_T_311) begin + dec_pause_state_f <= io_dec_pause_state; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + debug_halt_req_f <= 1'h0; + end else if (_T_289) begin + debug_halt_req_f <= debug_halt_req_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + pmu_fw_halt_req_f <= 1'h0; + end else if (_T_526) begin + pmu_fw_halt_req_f <= pmu_fw_halt_req_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + halt_taken_f <= 1'h0; + end else if (_T_269) begin + halt_taken_f <= halt_taken; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + ifu_ic_error_start_f <= 1'h0; + end else if (_T_24) begin + ifu_ic_error_start_f <= io_tlu_mem_ifu_ic_error_start; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + debug_resume_req_f_raw <= 1'h0; + end else if (_T_293) begin + debug_resume_req_f_raw <= debug_resume_req; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dcsr_single_step_running_f <= 1'h0; + end else if (_T_323) begin + dcsr_single_step_running_f <= dcsr_single_step_running; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dcsr_single_step_done_f <= 1'h0; + end else if (_T_301) begin + dcsr_single_step_done_f <= dcsr_single_step_done; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + internal_pmu_fw_halt_mode_f <= 1'h0; + end else if (_T_522) begin + internal_pmu_fw_halt_mode_f <= internal_pmu_fw_halt_mode; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + ifu_iccm_rd_ecc_single_err_f <= 1'h0; + end else if (_T_27) begin + ifu_iccm_rd_ecc_single_err_f <= io_tlu_mem_ifu_iccm_rd_ecc_single_err; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + iccm_repair_state_d1 <= 1'h0; + end else if (_T_30) begin + iccm_repair_state_d1 <= iccm_repair_state_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dbg_halt_req_held <= 1'h0; + end else if (_T_331) begin + dbg_halt_req_held <= dbg_halt_req_held_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + trigger_hit_dmode_r_d1 <= 1'h0; + end else if (_T_297) begin + trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ebreak_to_debug_mode_r_d1 <= 1'h0; + end else begin + ebreak_to_debug_mode_r_d1 <= _T_704 & _T_590; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + lsu_idle_any_f <= 1'h0; + end else if (_T_273) begin + lsu_idle_any_f <= io_lsu_idle_any; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + ifu_miss_state_idle_f <= 1'h0; + end else if (_T_277) begin + ifu_miss_state_idle_f <= io_tlu_mem_ifu_miss_state_idle; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + debug_halt_req_d1 <= 1'h0; + end else if (_T_305) begin + debug_halt_req_d1 <= debug_halt_req; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dec_tlu_flush_noredir_r_d1 <= 1'h0; + end else if (_T_265) begin + dec_tlu_flush_noredir_r_d1 <= io_tlu_ifc_dec_tlu_flush_noredir_wb; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dec_tlu_flush_pause_r_d1 <= 1'h0; + end else if (_T_327) begin + dec_tlu_flush_pause_r_d1 <= io_dec_tlu_flush_pause_r; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dbg_tlu_halted_f <= 1'h0; + end else if (_T_281) begin + dbg_tlu_halted_f <= dbg_tlu_halted; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + pmu_fw_tlu_halted_f <= 1'h0; + end else if (_T_530) begin + pmu_fw_tlu_halted_f <= pmu_fw_tlu_halted; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + lsu_pmu_load_external_r <= 1'h0; + end else if (_T_41) begin + lsu_pmu_load_external_r <= io_lsu_tlu_lsu_pmu_load_external_m; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + lsu_pmu_store_external_r <= 1'h0; + end else if (_T_44) begin + lsu_pmu_store_external_r <= io_lsu_tlu_lsu_pmu_store_external_m; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + tlu_flush_lower_r_d1 <= 1'h0; + end else if (_T_47) begin + tlu_flush_lower_r_d1 <= tlu_flush_lower_r; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_52 <= 1'h0; + end else if (_T_51) begin + _T_52 <= tlu_i0_kill_writeb_r; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + internal_dbg_halt_mode_f2 <= 1'h0; + end else if (_T_54) begin + internal_dbg_halt_mode_f2 <= debug_mode_status; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_59 <= 1'h0; + end else if (_T_58) begin + _T_59 <= force_halt; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + nmi_lsu_load_type_f <= 1'h0; + end else if (_T_67) begin + nmi_lsu_load_type_f <= nmi_lsu_load_type; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + nmi_lsu_store_type_f <= 1'h0; + end else if (_T_70) begin + nmi_lsu_store_type_f <= nmi_lsu_store_type; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + mpc_debug_halt_req_sync_f <= 1'h0; + end else if (_T_112) begin + mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + mpc_debug_run_req_sync_f <= 1'h0; + end else if (_T_115) begin + mpc_debug_run_req_sync_f <= mpc_debug_run_req_sync; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + mpc_run_state_f <= 1'h0; + end else if (_T_122) begin + mpc_run_state_f <= mpc_run_state_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + mpc_debug_run_ack_f <= 1'h0; + end else if (_T_131) begin + mpc_debug_run_ack_f <= mpc_debug_run_ack_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + debug_brkpt_status_f <= 1'h0; + end else if (_T_125) begin + debug_brkpt_status_f <= debug_brkpt_status_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + mpc_debug_halt_ack_f <= 1'h0; + end else if (_T_128) begin + mpc_debug_halt_ack_f <= mpc_debug_halt_ack_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dbg_run_state_f <= 1'h0; + end else if (_T_138) begin + dbg_run_state_f <= dbg_run_state_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_143 <= 1'h0; + end else if (_T_142) begin + _T_143 <= _T_1; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + request_debug_mode_r_d1 <= 1'h0; + end else if (_T_315) begin + request_debug_mode_r_d1 <= request_debug_mode_r; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + request_debug_mode_done_f <= 1'h0; + end else if (_T_319) begin + request_debug_mode_done_f <= request_debug_mode_done; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_286 <= 1'h0; + end else if (_T_285) begin + _T_286 <= resume_ack_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dec_tlu_wr_pause_r_d1 <= 1'h0; + end else if (_T_308) begin + dec_tlu_wr_pause_r_d1 <= io_dec_tlu_wr_pause_r; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_512 <= 1'h0; + end else if (_T_511) begin + _T_512 <= cpu_halt_status; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_516 <= 1'h0; + end else if (_T_515) begin + _T_516 <= cpu_halt_ack; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_520 <= 1'h0; + end else if (_T_519) begin + _T_520 <= cpu_run_ack; + end + end +endmodule +module dec_trigger( + input io_trigger_pkt_any_0_select, + input io_trigger_pkt_any_0_match_pkt, + input io_trigger_pkt_any_0_execute, + input io_trigger_pkt_any_0_m, + input [31:0] io_trigger_pkt_any_0_tdata2, + input io_trigger_pkt_any_1_select, + input io_trigger_pkt_any_1_match_pkt, + input io_trigger_pkt_any_1_execute, + input io_trigger_pkt_any_1_m, + input [31:0] io_trigger_pkt_any_1_tdata2, + input io_trigger_pkt_any_2_select, + input io_trigger_pkt_any_2_match_pkt, + input io_trigger_pkt_any_2_execute, + input io_trigger_pkt_any_2_m, + input [31:0] io_trigger_pkt_any_2_tdata2, + input io_trigger_pkt_any_3_select, + input io_trigger_pkt_any_3_match_pkt, + input io_trigger_pkt_any_3_execute, + input io_trigger_pkt_any_3_m, + input [31:0] io_trigger_pkt_any_3_tdata2, + input [30:0] io_dec_i0_pc_d, + output [3:0] io_dec_i0_trigger_match_d +); + wire _T = ~io_trigger_pkt_any_0_select; // @[dec_trigger.scala 14:63] + wire _T_1 = _T & io_trigger_pkt_any_0_execute; // @[dec_trigger.scala 14:93] + wire [9:0] _T_11 = {_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58] + wire [18:0] _T_20 = {_T_11,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58] + wire [27:0] _T_29 = {_T_20,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58] + wire [31:0] _T_33 = {_T_29,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58] + wire [31:0] _T_35 = {io_dec_i0_pc_d,io_trigger_pkt_any_0_tdata2[0]}; // @[Cat.scala 29:58] + wire [31:0] dec_i0_match_data_0 = _T_33 & _T_35; // @[dec_trigger.scala 14:127] + wire _T_37 = ~io_trigger_pkt_any_1_select; // @[dec_trigger.scala 14:63] + wire _T_38 = _T_37 & io_trigger_pkt_any_1_execute; // @[dec_trigger.scala 14:93] + wire [9:0] _T_48 = {_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58] + wire [18:0] _T_57 = {_T_48,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58] + wire [27:0] _T_66 = {_T_57,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58] + wire [31:0] _T_70 = {_T_66,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58] + wire [31:0] _T_72 = {io_dec_i0_pc_d,io_trigger_pkt_any_1_tdata2[0]}; // @[Cat.scala 29:58] + wire [31:0] dec_i0_match_data_1 = _T_70 & _T_72; // @[dec_trigger.scala 14:127] + wire _T_74 = ~io_trigger_pkt_any_2_select; // @[dec_trigger.scala 14:63] + wire _T_75 = _T_74 & io_trigger_pkt_any_2_execute; // @[dec_trigger.scala 14:93] + wire [9:0] _T_85 = {_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58] + wire [18:0] _T_94 = {_T_85,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58] + wire [27:0] _T_103 = {_T_94,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58] + wire [31:0] _T_107 = {_T_103,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58] + wire [31:0] _T_109 = {io_dec_i0_pc_d,io_trigger_pkt_any_2_tdata2[0]}; // @[Cat.scala 29:58] + wire [31:0] dec_i0_match_data_2 = _T_107 & _T_109; // @[dec_trigger.scala 14:127] + wire _T_111 = ~io_trigger_pkt_any_3_select; // @[dec_trigger.scala 14:63] + wire _T_112 = _T_111 & io_trigger_pkt_any_3_execute; // @[dec_trigger.scala 14:93] + wire [9:0] _T_122 = {_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58] + wire [18:0] _T_131 = {_T_122,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58] + wire [27:0] _T_140 = {_T_131,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58] + wire [31:0] _T_144 = {_T_140,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58] + wire [31:0] _T_146 = {io_dec_i0_pc_d,io_trigger_pkt_any_3_tdata2[0]}; // @[Cat.scala 29:58] + wire [31:0] dec_i0_match_data_3 = _T_144 & _T_146; // @[dec_trigger.scala 14:127] + wire _T_148 = io_trigger_pkt_any_0_execute & io_trigger_pkt_any_0_m; // @[dec_trigger.scala 15:83] + wire _T_151 = &io_trigger_pkt_any_0_tdata2; // @[lib.scala 101:45] + wire _T_152 = ~_T_151; // @[lib.scala 101:39] + wire _T_153 = io_trigger_pkt_any_0_match_pkt & _T_152; // @[lib.scala 101:37] + wire _T_156 = io_trigger_pkt_any_0_tdata2[0] == dec_i0_match_data_0[0]; // @[lib.scala 102:52] + wire _T_157 = _T_153 | _T_156; // @[lib.scala 102:41] + wire _T_159 = &io_trigger_pkt_any_0_tdata2[0]; // @[lib.scala 104:36] + wire _T_160 = _T_159 & _T_153; // @[lib.scala 104:41] + wire _T_163 = io_trigger_pkt_any_0_tdata2[1] == dec_i0_match_data_0[1]; // @[lib.scala 104:78] + wire _T_164 = _T_160 | _T_163; // @[lib.scala 104:23] + wire _T_166 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_167 = _T_166 & _T_153; // @[lib.scala 104:41] + wire _T_170 = io_trigger_pkt_any_0_tdata2[2] == dec_i0_match_data_0[2]; // @[lib.scala 104:78] + wire _T_171 = _T_167 | _T_170; // @[lib.scala 104:23] + wire _T_173 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_174 = _T_173 & _T_153; // @[lib.scala 104:41] + wire _T_177 = io_trigger_pkt_any_0_tdata2[3] == dec_i0_match_data_0[3]; // @[lib.scala 104:78] + wire _T_178 = _T_174 | _T_177; // @[lib.scala 104:23] + wire _T_180 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_181 = _T_180 & _T_153; // @[lib.scala 104:41] + wire _T_184 = io_trigger_pkt_any_0_tdata2[4] == dec_i0_match_data_0[4]; // @[lib.scala 104:78] + wire _T_185 = _T_181 | _T_184; // @[lib.scala 104:23] + wire _T_187 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_188 = _T_187 & _T_153; // @[lib.scala 104:41] + wire _T_191 = io_trigger_pkt_any_0_tdata2[5] == dec_i0_match_data_0[5]; // @[lib.scala 104:78] + wire _T_192 = _T_188 | _T_191; // @[lib.scala 104:23] + wire _T_194 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_195 = _T_194 & _T_153; // @[lib.scala 104:41] + wire _T_198 = io_trigger_pkt_any_0_tdata2[6] == dec_i0_match_data_0[6]; // @[lib.scala 104:78] + wire _T_199 = _T_195 | _T_198; // @[lib.scala 104:23] + wire _T_201 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_202 = _T_201 & _T_153; // @[lib.scala 104:41] + wire _T_205 = io_trigger_pkt_any_0_tdata2[7] == dec_i0_match_data_0[7]; // @[lib.scala 104:78] + wire _T_206 = _T_202 | _T_205; // @[lib.scala 104:23] + wire _T_208 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_209 = _T_208 & _T_153; // @[lib.scala 104:41] + wire _T_212 = io_trigger_pkt_any_0_tdata2[8] == dec_i0_match_data_0[8]; // @[lib.scala 104:78] + wire _T_213 = _T_209 | _T_212; // @[lib.scala 104:23] + wire _T_215 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_216 = _T_215 & _T_153; // @[lib.scala 104:41] + wire _T_219 = io_trigger_pkt_any_0_tdata2[9] == dec_i0_match_data_0[9]; // @[lib.scala 104:78] + wire _T_220 = _T_216 | _T_219; // @[lib.scala 104:23] + wire _T_222 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_223 = _T_222 & _T_153; // @[lib.scala 104:41] + wire _T_226 = io_trigger_pkt_any_0_tdata2[10] == dec_i0_match_data_0[10]; // @[lib.scala 104:78] + wire _T_227 = _T_223 | _T_226; // @[lib.scala 104:23] + wire _T_229 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_230 = _T_229 & _T_153; // @[lib.scala 104:41] + wire _T_233 = io_trigger_pkt_any_0_tdata2[11] == dec_i0_match_data_0[11]; // @[lib.scala 104:78] + wire _T_234 = _T_230 | _T_233; // @[lib.scala 104:23] + wire _T_236 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_237 = _T_236 & _T_153; // @[lib.scala 104:41] + wire _T_240 = io_trigger_pkt_any_0_tdata2[12] == dec_i0_match_data_0[12]; // @[lib.scala 104:78] + wire _T_241 = _T_237 | _T_240; // @[lib.scala 104:23] + wire _T_243 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_244 = _T_243 & _T_153; // @[lib.scala 104:41] + wire _T_247 = io_trigger_pkt_any_0_tdata2[13] == dec_i0_match_data_0[13]; // @[lib.scala 104:78] + wire _T_248 = _T_244 | _T_247; // @[lib.scala 104:23] + wire _T_250 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_251 = _T_250 & _T_153; // @[lib.scala 104:41] + wire _T_254 = io_trigger_pkt_any_0_tdata2[14] == dec_i0_match_data_0[14]; // @[lib.scala 104:78] + wire _T_255 = _T_251 | _T_254; // @[lib.scala 104:23] + wire _T_257 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_258 = _T_257 & _T_153; // @[lib.scala 104:41] + wire _T_261 = io_trigger_pkt_any_0_tdata2[15] == dec_i0_match_data_0[15]; // @[lib.scala 104:78] + wire _T_262 = _T_258 | _T_261; // @[lib.scala 104:23] + wire _T_264 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_265 = _T_264 & _T_153; // @[lib.scala 104:41] + wire _T_268 = io_trigger_pkt_any_0_tdata2[16] == dec_i0_match_data_0[16]; // @[lib.scala 104:78] + wire _T_269 = _T_265 | _T_268; // @[lib.scala 104:23] + wire _T_271 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_272 = _T_271 & _T_153; // @[lib.scala 104:41] + wire _T_275 = io_trigger_pkt_any_0_tdata2[17] == dec_i0_match_data_0[17]; // @[lib.scala 104:78] + wire _T_276 = _T_272 | _T_275; // @[lib.scala 104:23] + wire _T_278 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_279 = _T_278 & _T_153; // @[lib.scala 104:41] + wire _T_282 = io_trigger_pkt_any_0_tdata2[18] == dec_i0_match_data_0[18]; // @[lib.scala 104:78] + wire _T_283 = _T_279 | _T_282; // @[lib.scala 104:23] + wire _T_285 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_286 = _T_285 & _T_153; // @[lib.scala 104:41] + wire _T_289 = io_trigger_pkt_any_0_tdata2[19] == dec_i0_match_data_0[19]; // @[lib.scala 104:78] + wire _T_290 = _T_286 | _T_289; // @[lib.scala 104:23] + wire _T_292 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_293 = _T_292 & _T_153; // @[lib.scala 104:41] + wire _T_296 = io_trigger_pkt_any_0_tdata2[20] == dec_i0_match_data_0[20]; // @[lib.scala 104:78] + wire _T_297 = _T_293 | _T_296; // @[lib.scala 104:23] + wire _T_299 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_300 = _T_299 & _T_153; // @[lib.scala 104:41] + wire _T_303 = io_trigger_pkt_any_0_tdata2[21] == dec_i0_match_data_0[21]; // @[lib.scala 104:78] + wire _T_304 = _T_300 | _T_303; // @[lib.scala 104:23] + wire _T_306 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_307 = _T_306 & _T_153; // @[lib.scala 104:41] + wire _T_310 = io_trigger_pkt_any_0_tdata2[22] == dec_i0_match_data_0[22]; // @[lib.scala 104:78] + wire _T_311 = _T_307 | _T_310; // @[lib.scala 104:23] + wire _T_313 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_314 = _T_313 & _T_153; // @[lib.scala 104:41] + wire _T_317 = io_trigger_pkt_any_0_tdata2[23] == dec_i0_match_data_0[23]; // @[lib.scala 104:78] + wire _T_318 = _T_314 | _T_317; // @[lib.scala 104:23] + wire _T_320 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_321 = _T_320 & _T_153; // @[lib.scala 104:41] + wire _T_324 = io_trigger_pkt_any_0_tdata2[24] == dec_i0_match_data_0[24]; // @[lib.scala 104:78] + wire _T_325 = _T_321 | _T_324; // @[lib.scala 104:23] + wire _T_327 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_328 = _T_327 & _T_153; // @[lib.scala 104:41] + wire _T_331 = io_trigger_pkt_any_0_tdata2[25] == dec_i0_match_data_0[25]; // @[lib.scala 104:78] + wire _T_332 = _T_328 | _T_331; // @[lib.scala 104:23] + wire _T_334 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_335 = _T_334 & _T_153; // @[lib.scala 104:41] + wire _T_338 = io_trigger_pkt_any_0_tdata2[26] == dec_i0_match_data_0[26]; // @[lib.scala 104:78] + wire _T_339 = _T_335 | _T_338; // @[lib.scala 104:23] + wire _T_341 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_342 = _T_341 & _T_153; // @[lib.scala 104:41] + wire _T_345 = io_trigger_pkt_any_0_tdata2[27] == dec_i0_match_data_0[27]; // @[lib.scala 104:78] + wire _T_346 = _T_342 | _T_345; // @[lib.scala 104:23] + wire _T_348 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_349 = _T_348 & _T_153; // @[lib.scala 104:41] + wire _T_352 = io_trigger_pkt_any_0_tdata2[28] == dec_i0_match_data_0[28]; // @[lib.scala 104:78] + wire _T_353 = _T_349 | _T_352; // @[lib.scala 104:23] + wire _T_355 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_356 = _T_355 & _T_153; // @[lib.scala 104:41] + wire _T_359 = io_trigger_pkt_any_0_tdata2[29] == dec_i0_match_data_0[29]; // @[lib.scala 104:78] + wire _T_360 = _T_356 | _T_359; // @[lib.scala 104:23] + wire _T_362 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_363 = _T_362 & _T_153; // @[lib.scala 104:41] + wire _T_366 = io_trigger_pkt_any_0_tdata2[30] == dec_i0_match_data_0[30]; // @[lib.scala 104:78] + wire _T_367 = _T_363 | _T_366; // @[lib.scala 104:23] + wire _T_369 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_370 = _T_369 & _T_153; // @[lib.scala 104:41] + wire _T_373 = io_trigger_pkt_any_0_tdata2[31] == dec_i0_match_data_0[31]; // @[lib.scala 104:78] + wire _T_374 = _T_370 | _T_373; // @[lib.scala 104:23] + wire [7:0] _T_381 = {_T_206,_T_199,_T_192,_T_185,_T_178,_T_171,_T_164,_T_157}; // @[lib.scala 105:14] + wire [15:0] _T_389 = {_T_262,_T_255,_T_248,_T_241,_T_234,_T_227,_T_220,_T_213,_T_381}; // @[lib.scala 105:14] + wire [7:0] _T_396 = {_T_318,_T_311,_T_304,_T_297,_T_290,_T_283,_T_276,_T_269}; // @[lib.scala 105:14] + wire [31:0] _T_405 = {_T_374,_T_367,_T_360,_T_353,_T_346,_T_339,_T_332,_T_325,_T_396,_T_389}; // @[lib.scala 105:14] + wire _T_406 = &_T_405; // @[lib.scala 105:25] + wire _T_407 = _T_148 & _T_406; // @[dec_trigger.scala 15:109] + wire _T_408 = io_trigger_pkt_any_1_execute & io_trigger_pkt_any_1_m; // @[dec_trigger.scala 15:83] + wire _T_411 = &io_trigger_pkt_any_1_tdata2; // @[lib.scala 101:45] + wire _T_412 = ~_T_411; // @[lib.scala 101:39] + wire _T_413 = io_trigger_pkt_any_1_match_pkt & _T_412; // @[lib.scala 101:37] + wire _T_416 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[lib.scala 102:52] + wire _T_417 = _T_413 | _T_416; // @[lib.scala 102:41] + wire _T_419 = &io_trigger_pkt_any_1_tdata2[0]; // @[lib.scala 104:36] + wire _T_420 = _T_419 & _T_413; // @[lib.scala 104:41] + wire _T_423 = io_trigger_pkt_any_1_tdata2[1] == dec_i0_match_data_1[1]; // @[lib.scala 104:78] + wire _T_424 = _T_420 | _T_423; // @[lib.scala 104:23] + wire _T_426 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_427 = _T_426 & _T_413; // @[lib.scala 104:41] + wire _T_430 = io_trigger_pkt_any_1_tdata2[2] == dec_i0_match_data_1[2]; // @[lib.scala 104:78] + wire _T_431 = _T_427 | _T_430; // @[lib.scala 104:23] + wire _T_433 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_434 = _T_433 & _T_413; // @[lib.scala 104:41] + wire _T_437 = io_trigger_pkt_any_1_tdata2[3] == dec_i0_match_data_1[3]; // @[lib.scala 104:78] + wire _T_438 = _T_434 | _T_437; // @[lib.scala 104:23] + wire _T_440 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_441 = _T_440 & _T_413; // @[lib.scala 104:41] + wire _T_444 = io_trigger_pkt_any_1_tdata2[4] == dec_i0_match_data_1[4]; // @[lib.scala 104:78] + wire _T_445 = _T_441 | _T_444; // @[lib.scala 104:23] + wire _T_447 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_448 = _T_447 & _T_413; // @[lib.scala 104:41] + wire _T_451 = io_trigger_pkt_any_1_tdata2[5] == dec_i0_match_data_1[5]; // @[lib.scala 104:78] + wire _T_452 = _T_448 | _T_451; // @[lib.scala 104:23] + wire _T_454 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_455 = _T_454 & _T_413; // @[lib.scala 104:41] + wire _T_458 = io_trigger_pkt_any_1_tdata2[6] == dec_i0_match_data_1[6]; // @[lib.scala 104:78] + wire _T_459 = _T_455 | _T_458; // @[lib.scala 104:23] + wire _T_461 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_462 = _T_461 & _T_413; // @[lib.scala 104:41] + wire _T_465 = io_trigger_pkt_any_1_tdata2[7] == dec_i0_match_data_1[7]; // @[lib.scala 104:78] + wire _T_466 = _T_462 | _T_465; // @[lib.scala 104:23] + wire _T_468 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_469 = _T_468 & _T_413; // @[lib.scala 104:41] + wire _T_472 = io_trigger_pkt_any_1_tdata2[8] == dec_i0_match_data_1[8]; // @[lib.scala 104:78] + wire _T_473 = _T_469 | _T_472; // @[lib.scala 104:23] + wire _T_475 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_476 = _T_475 & _T_413; // @[lib.scala 104:41] + wire _T_479 = io_trigger_pkt_any_1_tdata2[9] == dec_i0_match_data_1[9]; // @[lib.scala 104:78] + wire _T_480 = _T_476 | _T_479; // @[lib.scala 104:23] + wire _T_482 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_483 = _T_482 & _T_413; // @[lib.scala 104:41] + wire _T_486 = io_trigger_pkt_any_1_tdata2[10] == dec_i0_match_data_1[10]; // @[lib.scala 104:78] + wire _T_487 = _T_483 | _T_486; // @[lib.scala 104:23] + wire _T_489 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_490 = _T_489 & _T_413; // @[lib.scala 104:41] + wire _T_493 = io_trigger_pkt_any_1_tdata2[11] == dec_i0_match_data_1[11]; // @[lib.scala 104:78] + wire _T_494 = _T_490 | _T_493; // @[lib.scala 104:23] + wire _T_496 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_497 = _T_496 & _T_413; // @[lib.scala 104:41] + wire _T_500 = io_trigger_pkt_any_1_tdata2[12] == dec_i0_match_data_1[12]; // @[lib.scala 104:78] + wire _T_501 = _T_497 | _T_500; // @[lib.scala 104:23] + wire _T_503 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_504 = _T_503 & _T_413; // @[lib.scala 104:41] + wire _T_507 = io_trigger_pkt_any_1_tdata2[13] == dec_i0_match_data_1[13]; // @[lib.scala 104:78] + wire _T_508 = _T_504 | _T_507; // @[lib.scala 104:23] + wire _T_510 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_511 = _T_510 & _T_413; // @[lib.scala 104:41] + wire _T_514 = io_trigger_pkt_any_1_tdata2[14] == dec_i0_match_data_1[14]; // @[lib.scala 104:78] + wire _T_515 = _T_511 | _T_514; // @[lib.scala 104:23] + wire _T_517 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_518 = _T_517 & _T_413; // @[lib.scala 104:41] + wire _T_521 = io_trigger_pkt_any_1_tdata2[15] == dec_i0_match_data_1[15]; // @[lib.scala 104:78] + wire _T_522 = _T_518 | _T_521; // @[lib.scala 104:23] + wire _T_524 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_525 = _T_524 & _T_413; // @[lib.scala 104:41] + wire _T_528 = io_trigger_pkt_any_1_tdata2[16] == dec_i0_match_data_1[16]; // @[lib.scala 104:78] + wire _T_529 = _T_525 | _T_528; // @[lib.scala 104:23] + wire _T_531 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_532 = _T_531 & _T_413; // @[lib.scala 104:41] + wire _T_535 = io_trigger_pkt_any_1_tdata2[17] == dec_i0_match_data_1[17]; // @[lib.scala 104:78] + wire _T_536 = _T_532 | _T_535; // @[lib.scala 104:23] + wire _T_538 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_539 = _T_538 & _T_413; // @[lib.scala 104:41] + wire _T_542 = io_trigger_pkt_any_1_tdata2[18] == dec_i0_match_data_1[18]; // @[lib.scala 104:78] + wire _T_543 = _T_539 | _T_542; // @[lib.scala 104:23] + wire _T_545 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_546 = _T_545 & _T_413; // @[lib.scala 104:41] + wire _T_549 = io_trigger_pkt_any_1_tdata2[19] == dec_i0_match_data_1[19]; // @[lib.scala 104:78] + wire _T_550 = _T_546 | _T_549; // @[lib.scala 104:23] + wire _T_552 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_553 = _T_552 & _T_413; // @[lib.scala 104:41] + wire _T_556 = io_trigger_pkt_any_1_tdata2[20] == dec_i0_match_data_1[20]; // @[lib.scala 104:78] + wire _T_557 = _T_553 | _T_556; // @[lib.scala 104:23] + wire _T_559 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_560 = _T_559 & _T_413; // @[lib.scala 104:41] + wire _T_563 = io_trigger_pkt_any_1_tdata2[21] == dec_i0_match_data_1[21]; // @[lib.scala 104:78] + wire _T_564 = _T_560 | _T_563; // @[lib.scala 104:23] + wire _T_566 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_567 = _T_566 & _T_413; // @[lib.scala 104:41] + wire _T_570 = io_trigger_pkt_any_1_tdata2[22] == dec_i0_match_data_1[22]; // @[lib.scala 104:78] + wire _T_571 = _T_567 | _T_570; // @[lib.scala 104:23] + wire _T_573 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_574 = _T_573 & _T_413; // @[lib.scala 104:41] + wire _T_577 = io_trigger_pkt_any_1_tdata2[23] == dec_i0_match_data_1[23]; // @[lib.scala 104:78] + wire _T_578 = _T_574 | _T_577; // @[lib.scala 104:23] + wire _T_580 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_581 = _T_580 & _T_413; // @[lib.scala 104:41] + wire _T_584 = io_trigger_pkt_any_1_tdata2[24] == dec_i0_match_data_1[24]; // @[lib.scala 104:78] + wire _T_585 = _T_581 | _T_584; // @[lib.scala 104:23] + wire _T_587 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_588 = _T_587 & _T_413; // @[lib.scala 104:41] + wire _T_591 = io_trigger_pkt_any_1_tdata2[25] == dec_i0_match_data_1[25]; // @[lib.scala 104:78] + wire _T_592 = _T_588 | _T_591; // @[lib.scala 104:23] + wire _T_594 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_595 = _T_594 & _T_413; // @[lib.scala 104:41] + wire _T_598 = io_trigger_pkt_any_1_tdata2[26] == dec_i0_match_data_1[26]; // @[lib.scala 104:78] + wire _T_599 = _T_595 | _T_598; // @[lib.scala 104:23] + wire _T_601 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_602 = _T_601 & _T_413; // @[lib.scala 104:41] + wire _T_605 = io_trigger_pkt_any_1_tdata2[27] == dec_i0_match_data_1[27]; // @[lib.scala 104:78] + wire _T_606 = _T_602 | _T_605; // @[lib.scala 104:23] + wire _T_608 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_609 = _T_608 & _T_413; // @[lib.scala 104:41] + wire _T_612 = io_trigger_pkt_any_1_tdata2[28] == dec_i0_match_data_1[28]; // @[lib.scala 104:78] + wire _T_613 = _T_609 | _T_612; // @[lib.scala 104:23] + wire _T_615 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_616 = _T_615 & _T_413; // @[lib.scala 104:41] + wire _T_619 = io_trigger_pkt_any_1_tdata2[29] == dec_i0_match_data_1[29]; // @[lib.scala 104:78] + wire _T_620 = _T_616 | _T_619; // @[lib.scala 104:23] + wire _T_622 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_623 = _T_622 & _T_413; // @[lib.scala 104:41] + wire _T_626 = io_trigger_pkt_any_1_tdata2[30] == dec_i0_match_data_1[30]; // @[lib.scala 104:78] + wire _T_627 = _T_623 | _T_626; // @[lib.scala 104:23] + wire _T_629 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_630 = _T_629 & _T_413; // @[lib.scala 104:41] + wire _T_633 = io_trigger_pkt_any_1_tdata2[31] == dec_i0_match_data_1[31]; // @[lib.scala 104:78] + wire _T_634 = _T_630 | _T_633; // @[lib.scala 104:23] + wire [7:0] _T_641 = {_T_466,_T_459,_T_452,_T_445,_T_438,_T_431,_T_424,_T_417}; // @[lib.scala 105:14] + wire [15:0] _T_649 = {_T_522,_T_515,_T_508,_T_501,_T_494,_T_487,_T_480,_T_473,_T_641}; // @[lib.scala 105:14] + wire [7:0] _T_656 = {_T_578,_T_571,_T_564,_T_557,_T_550,_T_543,_T_536,_T_529}; // @[lib.scala 105:14] + wire [31:0] _T_665 = {_T_634,_T_627,_T_620,_T_613,_T_606,_T_599,_T_592,_T_585,_T_656,_T_649}; // @[lib.scala 105:14] + wire _T_666 = &_T_665; // @[lib.scala 105:25] + wire _T_667 = _T_408 & _T_666; // @[dec_trigger.scala 15:109] + wire _T_668 = io_trigger_pkt_any_2_execute & io_trigger_pkt_any_2_m; // @[dec_trigger.scala 15:83] + wire _T_671 = &io_trigger_pkt_any_2_tdata2; // @[lib.scala 101:45] + wire _T_672 = ~_T_671; // @[lib.scala 101:39] + wire _T_673 = io_trigger_pkt_any_2_match_pkt & _T_672; // @[lib.scala 101:37] + wire _T_676 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[lib.scala 102:52] + wire _T_677 = _T_673 | _T_676; // @[lib.scala 102:41] + wire _T_679 = &io_trigger_pkt_any_2_tdata2[0]; // @[lib.scala 104:36] + wire _T_680 = _T_679 & _T_673; // @[lib.scala 104:41] + wire _T_683 = io_trigger_pkt_any_2_tdata2[1] == dec_i0_match_data_2[1]; // @[lib.scala 104:78] + wire _T_684 = _T_680 | _T_683; // @[lib.scala 104:23] + wire _T_686 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_687 = _T_686 & _T_673; // @[lib.scala 104:41] + wire _T_690 = io_trigger_pkt_any_2_tdata2[2] == dec_i0_match_data_2[2]; // @[lib.scala 104:78] + wire _T_691 = _T_687 | _T_690; // @[lib.scala 104:23] + wire _T_693 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_694 = _T_693 & _T_673; // @[lib.scala 104:41] + wire _T_697 = io_trigger_pkt_any_2_tdata2[3] == dec_i0_match_data_2[3]; // @[lib.scala 104:78] + wire _T_698 = _T_694 | _T_697; // @[lib.scala 104:23] + wire _T_700 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_701 = _T_700 & _T_673; // @[lib.scala 104:41] + wire _T_704 = io_trigger_pkt_any_2_tdata2[4] == dec_i0_match_data_2[4]; // @[lib.scala 104:78] + wire _T_705 = _T_701 | _T_704; // @[lib.scala 104:23] + wire _T_707 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_708 = _T_707 & _T_673; // @[lib.scala 104:41] + wire _T_711 = io_trigger_pkt_any_2_tdata2[5] == dec_i0_match_data_2[5]; // @[lib.scala 104:78] + wire _T_712 = _T_708 | _T_711; // @[lib.scala 104:23] + wire _T_714 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_715 = _T_714 & _T_673; // @[lib.scala 104:41] + wire _T_718 = io_trigger_pkt_any_2_tdata2[6] == dec_i0_match_data_2[6]; // @[lib.scala 104:78] + wire _T_719 = _T_715 | _T_718; // @[lib.scala 104:23] + wire _T_721 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_722 = _T_721 & _T_673; // @[lib.scala 104:41] + wire _T_725 = io_trigger_pkt_any_2_tdata2[7] == dec_i0_match_data_2[7]; // @[lib.scala 104:78] + wire _T_726 = _T_722 | _T_725; // @[lib.scala 104:23] + wire _T_728 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_729 = _T_728 & _T_673; // @[lib.scala 104:41] + wire _T_732 = io_trigger_pkt_any_2_tdata2[8] == dec_i0_match_data_2[8]; // @[lib.scala 104:78] + wire _T_733 = _T_729 | _T_732; // @[lib.scala 104:23] + wire _T_735 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_736 = _T_735 & _T_673; // @[lib.scala 104:41] + wire _T_739 = io_trigger_pkt_any_2_tdata2[9] == dec_i0_match_data_2[9]; // @[lib.scala 104:78] + wire _T_740 = _T_736 | _T_739; // @[lib.scala 104:23] + wire _T_742 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_743 = _T_742 & _T_673; // @[lib.scala 104:41] + wire _T_746 = io_trigger_pkt_any_2_tdata2[10] == dec_i0_match_data_2[10]; // @[lib.scala 104:78] + wire _T_747 = _T_743 | _T_746; // @[lib.scala 104:23] + wire _T_749 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_750 = _T_749 & _T_673; // @[lib.scala 104:41] + wire _T_753 = io_trigger_pkt_any_2_tdata2[11] == dec_i0_match_data_2[11]; // @[lib.scala 104:78] + wire _T_754 = _T_750 | _T_753; // @[lib.scala 104:23] + wire _T_756 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_757 = _T_756 & _T_673; // @[lib.scala 104:41] + wire _T_760 = io_trigger_pkt_any_2_tdata2[12] == dec_i0_match_data_2[12]; // @[lib.scala 104:78] + wire _T_761 = _T_757 | _T_760; // @[lib.scala 104:23] + wire _T_763 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_764 = _T_763 & _T_673; // @[lib.scala 104:41] + wire _T_767 = io_trigger_pkt_any_2_tdata2[13] == dec_i0_match_data_2[13]; // @[lib.scala 104:78] + wire _T_768 = _T_764 | _T_767; // @[lib.scala 104:23] + wire _T_770 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_771 = _T_770 & _T_673; // @[lib.scala 104:41] + wire _T_774 = io_trigger_pkt_any_2_tdata2[14] == dec_i0_match_data_2[14]; // @[lib.scala 104:78] + wire _T_775 = _T_771 | _T_774; // @[lib.scala 104:23] + wire _T_777 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_778 = _T_777 & _T_673; // @[lib.scala 104:41] + wire _T_781 = io_trigger_pkt_any_2_tdata2[15] == dec_i0_match_data_2[15]; // @[lib.scala 104:78] + wire _T_782 = _T_778 | _T_781; // @[lib.scala 104:23] + wire _T_784 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_785 = _T_784 & _T_673; // @[lib.scala 104:41] + wire _T_788 = io_trigger_pkt_any_2_tdata2[16] == dec_i0_match_data_2[16]; // @[lib.scala 104:78] + wire _T_789 = _T_785 | _T_788; // @[lib.scala 104:23] + wire _T_791 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_792 = _T_791 & _T_673; // @[lib.scala 104:41] + wire _T_795 = io_trigger_pkt_any_2_tdata2[17] == dec_i0_match_data_2[17]; // @[lib.scala 104:78] + wire _T_796 = _T_792 | _T_795; // @[lib.scala 104:23] + wire _T_798 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_799 = _T_798 & _T_673; // @[lib.scala 104:41] + wire _T_802 = io_trigger_pkt_any_2_tdata2[18] == dec_i0_match_data_2[18]; // @[lib.scala 104:78] + wire _T_803 = _T_799 | _T_802; // @[lib.scala 104:23] + wire _T_805 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_806 = _T_805 & _T_673; // @[lib.scala 104:41] + wire _T_809 = io_trigger_pkt_any_2_tdata2[19] == dec_i0_match_data_2[19]; // @[lib.scala 104:78] + wire _T_810 = _T_806 | _T_809; // @[lib.scala 104:23] + wire _T_812 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_813 = _T_812 & _T_673; // @[lib.scala 104:41] + wire _T_816 = io_trigger_pkt_any_2_tdata2[20] == dec_i0_match_data_2[20]; // @[lib.scala 104:78] + wire _T_817 = _T_813 | _T_816; // @[lib.scala 104:23] + wire _T_819 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_820 = _T_819 & _T_673; // @[lib.scala 104:41] + wire _T_823 = io_trigger_pkt_any_2_tdata2[21] == dec_i0_match_data_2[21]; // @[lib.scala 104:78] + wire _T_824 = _T_820 | _T_823; // @[lib.scala 104:23] + wire _T_826 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_827 = _T_826 & _T_673; // @[lib.scala 104:41] + wire _T_830 = io_trigger_pkt_any_2_tdata2[22] == dec_i0_match_data_2[22]; // @[lib.scala 104:78] + wire _T_831 = _T_827 | _T_830; // @[lib.scala 104:23] + wire _T_833 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_834 = _T_833 & _T_673; // @[lib.scala 104:41] + wire _T_837 = io_trigger_pkt_any_2_tdata2[23] == dec_i0_match_data_2[23]; // @[lib.scala 104:78] + wire _T_838 = _T_834 | _T_837; // @[lib.scala 104:23] + wire _T_840 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_841 = _T_840 & _T_673; // @[lib.scala 104:41] + wire _T_844 = io_trigger_pkt_any_2_tdata2[24] == dec_i0_match_data_2[24]; // @[lib.scala 104:78] + wire _T_845 = _T_841 | _T_844; // @[lib.scala 104:23] + wire _T_847 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_848 = _T_847 & _T_673; // @[lib.scala 104:41] + wire _T_851 = io_trigger_pkt_any_2_tdata2[25] == dec_i0_match_data_2[25]; // @[lib.scala 104:78] + wire _T_852 = _T_848 | _T_851; // @[lib.scala 104:23] + wire _T_854 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_855 = _T_854 & _T_673; // @[lib.scala 104:41] + wire _T_858 = io_trigger_pkt_any_2_tdata2[26] == dec_i0_match_data_2[26]; // @[lib.scala 104:78] + wire _T_859 = _T_855 | _T_858; // @[lib.scala 104:23] + wire _T_861 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_862 = _T_861 & _T_673; // @[lib.scala 104:41] + wire _T_865 = io_trigger_pkt_any_2_tdata2[27] == dec_i0_match_data_2[27]; // @[lib.scala 104:78] + wire _T_866 = _T_862 | _T_865; // @[lib.scala 104:23] + wire _T_868 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_869 = _T_868 & _T_673; // @[lib.scala 104:41] + wire _T_872 = io_trigger_pkt_any_2_tdata2[28] == dec_i0_match_data_2[28]; // @[lib.scala 104:78] + wire _T_873 = _T_869 | _T_872; // @[lib.scala 104:23] + wire _T_875 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_876 = _T_875 & _T_673; // @[lib.scala 104:41] + wire _T_879 = io_trigger_pkt_any_2_tdata2[29] == dec_i0_match_data_2[29]; // @[lib.scala 104:78] + wire _T_880 = _T_876 | _T_879; // @[lib.scala 104:23] + wire _T_882 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_883 = _T_882 & _T_673; // @[lib.scala 104:41] + wire _T_886 = io_trigger_pkt_any_2_tdata2[30] == dec_i0_match_data_2[30]; // @[lib.scala 104:78] + wire _T_887 = _T_883 | _T_886; // @[lib.scala 104:23] + wire _T_889 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_890 = _T_889 & _T_673; // @[lib.scala 104:41] + wire _T_893 = io_trigger_pkt_any_2_tdata2[31] == dec_i0_match_data_2[31]; // @[lib.scala 104:78] + wire _T_894 = _T_890 | _T_893; // @[lib.scala 104:23] + wire [7:0] _T_901 = {_T_726,_T_719,_T_712,_T_705,_T_698,_T_691,_T_684,_T_677}; // @[lib.scala 105:14] + wire [15:0] _T_909 = {_T_782,_T_775,_T_768,_T_761,_T_754,_T_747,_T_740,_T_733,_T_901}; // @[lib.scala 105:14] + wire [7:0] _T_916 = {_T_838,_T_831,_T_824,_T_817,_T_810,_T_803,_T_796,_T_789}; // @[lib.scala 105:14] + wire [31:0] _T_925 = {_T_894,_T_887,_T_880,_T_873,_T_866,_T_859,_T_852,_T_845,_T_916,_T_909}; // @[lib.scala 105:14] + wire _T_926 = &_T_925; // @[lib.scala 105:25] + wire _T_927 = _T_668 & _T_926; // @[dec_trigger.scala 15:109] + wire _T_928 = io_trigger_pkt_any_3_execute & io_trigger_pkt_any_3_m; // @[dec_trigger.scala 15:83] + wire _T_931 = &io_trigger_pkt_any_3_tdata2; // @[lib.scala 101:45] + wire _T_932 = ~_T_931; // @[lib.scala 101:39] + wire _T_933 = io_trigger_pkt_any_3_match_pkt & _T_932; // @[lib.scala 101:37] + wire _T_936 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[lib.scala 102:52] + wire _T_937 = _T_933 | _T_936; // @[lib.scala 102:41] + wire _T_939 = &io_trigger_pkt_any_3_tdata2[0]; // @[lib.scala 104:36] + wire _T_940 = _T_939 & _T_933; // @[lib.scala 104:41] + wire _T_943 = io_trigger_pkt_any_3_tdata2[1] == dec_i0_match_data_3[1]; // @[lib.scala 104:78] + wire _T_944 = _T_940 | _T_943; // @[lib.scala 104:23] + wire _T_946 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_947 = _T_946 & _T_933; // @[lib.scala 104:41] + wire _T_950 = io_trigger_pkt_any_3_tdata2[2] == dec_i0_match_data_3[2]; // @[lib.scala 104:78] + wire _T_951 = _T_947 | _T_950; // @[lib.scala 104:23] + wire _T_953 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_954 = _T_953 & _T_933; // @[lib.scala 104:41] + wire _T_957 = io_trigger_pkt_any_3_tdata2[3] == dec_i0_match_data_3[3]; // @[lib.scala 104:78] + wire _T_958 = _T_954 | _T_957; // @[lib.scala 104:23] + wire _T_960 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_961 = _T_960 & _T_933; // @[lib.scala 104:41] + wire _T_964 = io_trigger_pkt_any_3_tdata2[4] == dec_i0_match_data_3[4]; // @[lib.scala 104:78] + wire _T_965 = _T_961 | _T_964; // @[lib.scala 104:23] + wire _T_967 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_968 = _T_967 & _T_933; // @[lib.scala 104:41] + wire _T_971 = io_trigger_pkt_any_3_tdata2[5] == dec_i0_match_data_3[5]; // @[lib.scala 104:78] + wire _T_972 = _T_968 | _T_971; // @[lib.scala 104:23] + wire _T_974 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_975 = _T_974 & _T_933; // @[lib.scala 104:41] + wire _T_978 = io_trigger_pkt_any_3_tdata2[6] == dec_i0_match_data_3[6]; // @[lib.scala 104:78] + wire _T_979 = _T_975 | _T_978; // @[lib.scala 104:23] + wire _T_981 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_982 = _T_981 & _T_933; // @[lib.scala 104:41] + wire _T_985 = io_trigger_pkt_any_3_tdata2[7] == dec_i0_match_data_3[7]; // @[lib.scala 104:78] + wire _T_986 = _T_982 | _T_985; // @[lib.scala 104:23] + wire _T_988 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_989 = _T_988 & _T_933; // @[lib.scala 104:41] + wire _T_992 = io_trigger_pkt_any_3_tdata2[8] == dec_i0_match_data_3[8]; // @[lib.scala 104:78] + wire _T_993 = _T_989 | _T_992; // @[lib.scala 104:23] + wire _T_995 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_996 = _T_995 & _T_933; // @[lib.scala 104:41] + wire _T_999 = io_trigger_pkt_any_3_tdata2[9] == dec_i0_match_data_3[9]; // @[lib.scala 104:78] + wire _T_1000 = _T_996 | _T_999; // @[lib.scala 104:23] + wire _T_1002 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_1003 = _T_1002 & _T_933; // @[lib.scala 104:41] + wire _T_1006 = io_trigger_pkt_any_3_tdata2[10] == dec_i0_match_data_3[10]; // @[lib.scala 104:78] + wire _T_1007 = _T_1003 | _T_1006; // @[lib.scala 104:23] + wire _T_1009 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_1010 = _T_1009 & _T_933; // @[lib.scala 104:41] + wire _T_1013 = io_trigger_pkt_any_3_tdata2[11] == dec_i0_match_data_3[11]; // @[lib.scala 104:78] + wire _T_1014 = _T_1010 | _T_1013; // @[lib.scala 104:23] + wire _T_1016 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_1017 = _T_1016 & _T_933; // @[lib.scala 104:41] + wire _T_1020 = io_trigger_pkt_any_3_tdata2[12] == dec_i0_match_data_3[12]; // @[lib.scala 104:78] + wire _T_1021 = _T_1017 | _T_1020; // @[lib.scala 104:23] + wire _T_1023 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_1024 = _T_1023 & _T_933; // @[lib.scala 104:41] + wire _T_1027 = io_trigger_pkt_any_3_tdata2[13] == dec_i0_match_data_3[13]; // @[lib.scala 104:78] + wire _T_1028 = _T_1024 | _T_1027; // @[lib.scala 104:23] + wire _T_1030 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_1031 = _T_1030 & _T_933; // @[lib.scala 104:41] + wire _T_1034 = io_trigger_pkt_any_3_tdata2[14] == dec_i0_match_data_3[14]; // @[lib.scala 104:78] + wire _T_1035 = _T_1031 | _T_1034; // @[lib.scala 104:23] + wire _T_1037 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_1038 = _T_1037 & _T_933; // @[lib.scala 104:41] + wire _T_1041 = io_trigger_pkt_any_3_tdata2[15] == dec_i0_match_data_3[15]; // @[lib.scala 104:78] + wire _T_1042 = _T_1038 | _T_1041; // @[lib.scala 104:23] + wire _T_1044 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_1045 = _T_1044 & _T_933; // @[lib.scala 104:41] + wire _T_1048 = io_trigger_pkt_any_3_tdata2[16] == dec_i0_match_data_3[16]; // @[lib.scala 104:78] + wire _T_1049 = _T_1045 | _T_1048; // @[lib.scala 104:23] + wire _T_1051 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_1052 = _T_1051 & _T_933; // @[lib.scala 104:41] + wire _T_1055 = io_trigger_pkt_any_3_tdata2[17] == dec_i0_match_data_3[17]; // @[lib.scala 104:78] + wire _T_1056 = _T_1052 | _T_1055; // @[lib.scala 104:23] + wire _T_1058 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_1059 = _T_1058 & _T_933; // @[lib.scala 104:41] + wire _T_1062 = io_trigger_pkt_any_3_tdata2[18] == dec_i0_match_data_3[18]; // @[lib.scala 104:78] + wire _T_1063 = _T_1059 | _T_1062; // @[lib.scala 104:23] + wire _T_1065 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_1066 = _T_1065 & _T_933; // @[lib.scala 104:41] + wire _T_1069 = io_trigger_pkt_any_3_tdata2[19] == dec_i0_match_data_3[19]; // @[lib.scala 104:78] + wire _T_1070 = _T_1066 | _T_1069; // @[lib.scala 104:23] + wire _T_1072 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_1073 = _T_1072 & _T_933; // @[lib.scala 104:41] + wire _T_1076 = io_trigger_pkt_any_3_tdata2[20] == dec_i0_match_data_3[20]; // @[lib.scala 104:78] + wire _T_1077 = _T_1073 | _T_1076; // @[lib.scala 104:23] + wire _T_1079 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_1080 = _T_1079 & _T_933; // @[lib.scala 104:41] + wire _T_1083 = io_trigger_pkt_any_3_tdata2[21] == dec_i0_match_data_3[21]; // @[lib.scala 104:78] + wire _T_1084 = _T_1080 | _T_1083; // @[lib.scala 104:23] + wire _T_1086 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_1087 = _T_1086 & _T_933; // @[lib.scala 104:41] + wire _T_1090 = io_trigger_pkt_any_3_tdata2[22] == dec_i0_match_data_3[22]; // @[lib.scala 104:78] + wire _T_1091 = _T_1087 | _T_1090; // @[lib.scala 104:23] + wire _T_1093 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_1094 = _T_1093 & _T_933; // @[lib.scala 104:41] + wire _T_1097 = io_trigger_pkt_any_3_tdata2[23] == dec_i0_match_data_3[23]; // @[lib.scala 104:78] + wire _T_1098 = _T_1094 | _T_1097; // @[lib.scala 104:23] + wire _T_1100 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_1101 = _T_1100 & _T_933; // @[lib.scala 104:41] + wire _T_1104 = io_trigger_pkt_any_3_tdata2[24] == dec_i0_match_data_3[24]; // @[lib.scala 104:78] + wire _T_1105 = _T_1101 | _T_1104; // @[lib.scala 104:23] + wire _T_1107 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_1108 = _T_1107 & _T_933; // @[lib.scala 104:41] + wire _T_1111 = io_trigger_pkt_any_3_tdata2[25] == dec_i0_match_data_3[25]; // @[lib.scala 104:78] + wire _T_1112 = _T_1108 | _T_1111; // @[lib.scala 104:23] + wire _T_1114 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_1115 = _T_1114 & _T_933; // @[lib.scala 104:41] + wire _T_1118 = io_trigger_pkt_any_3_tdata2[26] == dec_i0_match_data_3[26]; // @[lib.scala 104:78] + wire _T_1119 = _T_1115 | _T_1118; // @[lib.scala 104:23] + wire _T_1121 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_1122 = _T_1121 & _T_933; // @[lib.scala 104:41] + wire _T_1125 = io_trigger_pkt_any_3_tdata2[27] == dec_i0_match_data_3[27]; // @[lib.scala 104:78] + wire _T_1126 = _T_1122 | _T_1125; // @[lib.scala 104:23] + wire _T_1128 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_1129 = _T_1128 & _T_933; // @[lib.scala 104:41] + wire _T_1132 = io_trigger_pkt_any_3_tdata2[28] == dec_i0_match_data_3[28]; // @[lib.scala 104:78] + wire _T_1133 = _T_1129 | _T_1132; // @[lib.scala 104:23] + wire _T_1135 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_1136 = _T_1135 & _T_933; // @[lib.scala 104:41] + wire _T_1139 = io_trigger_pkt_any_3_tdata2[29] == dec_i0_match_data_3[29]; // @[lib.scala 104:78] + wire _T_1140 = _T_1136 | _T_1139; // @[lib.scala 104:23] + wire _T_1142 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_1143 = _T_1142 & _T_933; // @[lib.scala 104:41] + wire _T_1146 = io_trigger_pkt_any_3_tdata2[30] == dec_i0_match_data_3[30]; // @[lib.scala 104:78] + wire _T_1147 = _T_1143 | _T_1146; // @[lib.scala 104:23] + wire _T_1149 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_1150 = _T_1149 & _T_933; // @[lib.scala 104:41] + wire _T_1153 = io_trigger_pkt_any_3_tdata2[31] == dec_i0_match_data_3[31]; // @[lib.scala 104:78] + wire _T_1154 = _T_1150 | _T_1153; // @[lib.scala 104:23] + wire [7:0] _T_1161 = {_T_986,_T_979,_T_972,_T_965,_T_958,_T_951,_T_944,_T_937}; // @[lib.scala 105:14] + wire [15:0] _T_1169 = {_T_1042,_T_1035,_T_1028,_T_1021,_T_1014,_T_1007,_T_1000,_T_993,_T_1161}; // @[lib.scala 105:14] + wire [7:0] _T_1176 = {_T_1098,_T_1091,_T_1084,_T_1077,_T_1070,_T_1063,_T_1056,_T_1049}; // @[lib.scala 105:14] + wire [31:0] _T_1185 = {_T_1154,_T_1147,_T_1140,_T_1133,_T_1126,_T_1119,_T_1112,_T_1105,_T_1176,_T_1169}; // @[lib.scala 105:14] + wire _T_1186 = &_T_1185; // @[lib.scala 105:25] + wire _T_1187 = _T_928 & _T_1186; // @[dec_trigger.scala 15:109] + wire [2:0] _T_1189 = {_T_1187,_T_927,_T_667}; // @[Cat.scala 29:58] + assign io_dec_i0_trigger_match_d = {_T_1189,_T_407}; // @[dec_trigger.scala 15:29] +endmodule +module dec( + input clock, + input reset, + input io_free_clk, + input io_active_clk, + input io_free_l2clk, + input io_lsu_fastint_stall_any, + output io_dec_pause_state_cg, + output io_dec_tlu_core_empty, + input [30:0] io_rst_vec, + input [8:0] io_ifu_i0_fa_index, + output [8:0] io_dec_fa_error_index, + input io_nmi_int, + input [30:0] io_nmi_vec, + input [31:0] io_lsu_nonblock_load_data, + input io_i_cpu_halt_req, + input io_i_cpu_run_req, + output io_o_cpu_halt_status, + output io_o_cpu_halt_ack, + output io_o_cpu_run_ack, + output io_o_debug_mode_status, + input [27:0] io_core_id, + input io_mpc_debug_halt_req, + input io_mpc_debug_run_req, + input io_mpc_reset_run_req, + output io_mpc_debug_halt_ack, + output io_mpc_debug_run_ack, + output io_debug_brkpt_status, + input io_lsu_pmu_misaligned_m, + input [30:0] io_lsu_fir_addr, + input [1:0] io_lsu_fir_error, + input [3:0] io_lsu_trigger_match_m, + input io_lsu_idle_any, + input io_lsu_error_pkt_r_valid, + input io_lsu_error_pkt_r_bits_single_ecc_error, + input io_lsu_error_pkt_r_bits_inst_type, + input io_lsu_error_pkt_r_bits_exc_type, + input [3:0] io_lsu_error_pkt_r_bits_mscause, + input [31:0] io_lsu_error_pkt_r_bits_addr, + input io_lsu_single_ecc_error_incr, + input [31:0] io_exu_div_result, + input io_exu_div_wren, + input [31:0] io_lsu_result_m, + input [31:0] io_lsu_result_corr_r, + input io_lsu_load_stall_any, + input io_lsu_store_stall_any, + input io_iccm_dma_sb_error, + input io_exu_flush_final, + input io_timer_int, + input io_soft_int, + input io_dbg_halt_req, + input io_dbg_resume_req, + output io_dec_tlu_dbg_halted, + output io_dec_tlu_debug_mode, + output io_dec_tlu_resume_ack, + output io_dec_tlu_mpc_halted_only, + output [31:0] io_dec_dbg_rddata, + output [31:0] io_dec_csr_rddata_d, + output io_dec_dbg_cmd_done, + output io_dec_dbg_cmd_fail, + output io_trigger_pkt_any_0_select, + output io_trigger_pkt_any_0_match_pkt, + output io_trigger_pkt_any_0_store, + output io_trigger_pkt_any_0_load, + output io_trigger_pkt_any_0_execute, + output io_trigger_pkt_any_0_m, + output [31:0] io_trigger_pkt_any_0_tdata2, + output io_trigger_pkt_any_1_select, + output io_trigger_pkt_any_1_match_pkt, + output io_trigger_pkt_any_1_store, + output io_trigger_pkt_any_1_load, + output io_trigger_pkt_any_1_execute, + output io_trigger_pkt_any_1_m, + output [31:0] io_trigger_pkt_any_1_tdata2, + output io_trigger_pkt_any_2_select, + output io_trigger_pkt_any_2_match_pkt, + output io_trigger_pkt_any_2_store, + output io_trigger_pkt_any_2_load, + output io_trigger_pkt_any_2_execute, + output io_trigger_pkt_any_2_m, + output [31:0] io_trigger_pkt_any_2_tdata2, + output io_trigger_pkt_any_3_select, + output io_trigger_pkt_any_3_match_pkt, + output io_trigger_pkt_any_3_store, + output io_trigger_pkt_any_3_load, + output io_trigger_pkt_any_3_execute, + output io_trigger_pkt_any_3_m, + output [31:0] io_trigger_pkt_any_3_tdata2, + input io_exu_i0_br_way_r, + output io_lsu_p_valid, + output io_lsu_p_bits_fast_int, + output io_lsu_p_bits_stack, + output io_lsu_p_bits_by, + output io_lsu_p_bits_half, + output io_lsu_p_bits_word, + output io_lsu_p_bits_dword, + output io_lsu_p_bits_load, + output io_lsu_p_bits_store, + output io_lsu_p_bits_unsign, + output io_lsu_p_bits_dma, + output io_lsu_p_bits_store_data_bypass_d, + output io_lsu_p_bits_load_ldst_bypass_d, + output io_lsu_p_bits_store_data_bypass_m, + output [11:0] io_dec_lsu_offset_d, + output io_dec_tlu_i0_kill_writeb_r, + output io_dec_tlu_perfcnt0, + output io_dec_tlu_perfcnt1, + output io_dec_tlu_perfcnt2, + output io_dec_tlu_perfcnt3, + output io_dec_tlu_flush_lower_wb, + output io_dec_lsu_valid_raw_d, + output io_trace_rv_trace_pkt_rv_i_valid_ip, + output [31:0] io_trace_rv_trace_pkt_rv_i_insn_ip, + output [31:0] io_trace_rv_trace_pkt_rv_i_address_ip, + output io_trace_rv_trace_pkt_rv_i_exception_ip, + output [4:0] io_trace_rv_trace_pkt_rv_i_ecause_ip, + output io_trace_rv_trace_pkt_rv_i_interrupt_ip, + output [31:0] io_trace_rv_trace_pkt_rv_i_tval_ip, + output io_dec_tlu_misc_clk_override, + output io_dec_tlu_ifu_clk_override, + output io_dec_tlu_lsu_clk_override, + output io_dec_tlu_bus_clk_override, + output io_dec_tlu_pic_clk_override, + output io_dec_tlu_picio_clk_override, + output io_dec_tlu_dccm_clk_override, + output io_dec_tlu_icm_clk_override, + input io_scan_mode, + output io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d, + input [15:0] io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst, + input io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf, + input [1:0] io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type, + input io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_second, + input io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc, + input [7:0] io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index, + input [7:0] io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr, + input [4:0] io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag, + input io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid, + input [31:0] io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr, + input [30:0] io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc, + input io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4, + input io_ifu_dec_dec_aln_aln_ib_i0_brp_valid, + input [11:0] io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset, + input [1:0] io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist, + input io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error, + input io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error, + input io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_bank, + input [30:0] io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett, + input io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way, + input io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret, + input io_ifu_dec_dec_aln_ifu_pmu_instr_aligned, + output io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb, + output io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt, + output io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt, + output io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb, + output [70:0] io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata, + output [16:0] io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics, + output io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid, + output io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid, + output io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable, + input io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss, + input io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit, + input io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error, + input io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy, + input io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn, + input io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start, + input io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err, + input [70:0] io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data, + input io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid, + input io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle, + output io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb, + output [31:0] io_ifu_dec_dec_ifc_dec_tlu_mrac_ff, + input io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall, + output io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid, + output [1:0] io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist, + output io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error, + output io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error, + output io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way, + output io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle, + output io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb, + output io_ifu_dec_dec_bp_dec_tlu_bpred_disable, + output io_dec_exu_dec_alu_dec_i0_alu_decode_d, + output io_dec_exu_dec_alu_dec_csr_ren_d, + output [11:0] io_dec_exu_dec_alu_dec_i0_br_immed_d, + input [30:0] io_dec_exu_dec_alu_exu_i0_pc_x, + output io_dec_exu_dec_div_div_p_valid, + output io_dec_exu_dec_div_div_p_bits_unsign, + output io_dec_exu_dec_div_div_p_bits_rem, + output io_dec_exu_dec_div_dec_div_cancel, + output [1:0] io_dec_exu_decode_exu_dec_data_en, + output [1:0] io_dec_exu_decode_exu_dec_ctl_en, + output io_dec_exu_decode_exu_i0_ap_clz, + output io_dec_exu_decode_exu_i0_ap_ctz, + output io_dec_exu_decode_exu_i0_ap_pcnt, + output io_dec_exu_decode_exu_i0_ap_sext_b, + output io_dec_exu_decode_exu_i0_ap_sext_h, + output io_dec_exu_decode_exu_i0_ap_slo, + output io_dec_exu_decode_exu_i0_ap_sro, + output io_dec_exu_decode_exu_i0_ap_min, + output io_dec_exu_decode_exu_i0_ap_max, + output io_dec_exu_decode_exu_i0_ap_pack, + output io_dec_exu_decode_exu_i0_ap_packu, + output io_dec_exu_decode_exu_i0_ap_packh, + output io_dec_exu_decode_exu_i0_ap_rol, + output io_dec_exu_decode_exu_i0_ap_ror, + output io_dec_exu_decode_exu_i0_ap_grev, + output io_dec_exu_decode_exu_i0_ap_gorc, + output io_dec_exu_decode_exu_i0_ap_zbb, + output io_dec_exu_decode_exu_i0_ap_sbset, + output io_dec_exu_decode_exu_i0_ap_sbclr, + output io_dec_exu_decode_exu_i0_ap_sbinv, + output io_dec_exu_decode_exu_i0_ap_sbext, + output io_dec_exu_decode_exu_i0_ap_sh1add, + output io_dec_exu_decode_exu_i0_ap_sh2add, + output io_dec_exu_decode_exu_i0_ap_sh3add, + output io_dec_exu_decode_exu_i0_ap_zba, + output io_dec_exu_decode_exu_i0_ap_land, + output io_dec_exu_decode_exu_i0_ap_lor, + output io_dec_exu_decode_exu_i0_ap_lxor, + output io_dec_exu_decode_exu_i0_ap_sll, + output io_dec_exu_decode_exu_i0_ap_srl, + output io_dec_exu_decode_exu_i0_ap_sra, + output io_dec_exu_decode_exu_i0_ap_beq, + output io_dec_exu_decode_exu_i0_ap_bne, + output io_dec_exu_decode_exu_i0_ap_blt, + output io_dec_exu_decode_exu_i0_ap_bge, + output io_dec_exu_decode_exu_i0_ap_add, + output io_dec_exu_decode_exu_i0_ap_sub, + output io_dec_exu_decode_exu_i0_ap_slt, + output io_dec_exu_decode_exu_i0_ap_unsign, + output io_dec_exu_decode_exu_i0_ap_jal, + output io_dec_exu_decode_exu_i0_ap_predict_t, + output io_dec_exu_decode_exu_i0_ap_predict_nt, + output io_dec_exu_decode_exu_i0_ap_csr_write, + output io_dec_exu_decode_exu_i0_ap_csr_imm, + output io_dec_exu_decode_exu_dec_i0_predict_p_d_valid, + output io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_misp, + output io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_ataken, + output io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_boffset, + output io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4, + output [1:0] io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist, + output [11:0] io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset, + output io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error, + output io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error, + output io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall, + output io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja, + output io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way, + output io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret, + output [30:0] io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett, + output [7:0] io_dec_exu_decode_exu_i0_predict_fghr_d, + output [7:0] io_dec_exu_decode_exu_i0_predict_index_d, + output [4:0] io_dec_exu_decode_exu_i0_predict_btag_d, + output io_dec_exu_decode_exu_dec_i0_rs1_en_d, + output io_dec_exu_decode_exu_dec_i0_branch_d, + output io_dec_exu_decode_exu_dec_i0_rs2_en_d, + output [31:0] io_dec_exu_decode_exu_dec_i0_immed_d, + output [31:0] io_dec_exu_decode_exu_dec_i0_result_r, + output io_dec_exu_decode_exu_dec_qual_lsu_d, + output io_dec_exu_decode_exu_dec_i0_select_pc_d, + output [3:0] io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d, + output [3:0] io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d, + output io_dec_exu_decode_exu_mul_p_valid, + output io_dec_exu_decode_exu_mul_p_bits_rs1_sign, + output io_dec_exu_decode_exu_mul_p_bits_rs2_sign, + output io_dec_exu_decode_exu_mul_p_bits_low, + output io_dec_exu_decode_exu_mul_p_bits_bext, + output io_dec_exu_decode_exu_mul_p_bits_bdep, + output io_dec_exu_decode_exu_mul_p_bits_clmul, + output io_dec_exu_decode_exu_mul_p_bits_clmulh, + output io_dec_exu_decode_exu_mul_p_bits_clmulr, + output io_dec_exu_decode_exu_mul_p_bits_grev, + output io_dec_exu_decode_exu_mul_p_bits_gorc, + output io_dec_exu_decode_exu_mul_p_bits_shfl, + output io_dec_exu_decode_exu_mul_p_bits_unshfl, + output io_dec_exu_decode_exu_mul_p_bits_crc32_b, + output io_dec_exu_decode_exu_mul_p_bits_crc32_h, + output io_dec_exu_decode_exu_mul_p_bits_crc32_w, + output io_dec_exu_decode_exu_mul_p_bits_crc32c_b, + output io_dec_exu_decode_exu_mul_p_bits_crc32c_h, + output io_dec_exu_decode_exu_mul_p_bits_crc32c_w, + output io_dec_exu_decode_exu_mul_p_bits_bfp, + output [30:0] io_dec_exu_decode_exu_pred_correct_npc_x, + output io_dec_exu_decode_exu_dec_extint_stall, + input [31:0] io_dec_exu_decode_exu_exu_i0_result_x, + input [31:0] io_dec_exu_decode_exu_exu_csr_rs1_x, + output [29:0] io_dec_exu_tlu_exu_dec_tlu_meihap, + output io_dec_exu_tlu_exu_dec_tlu_flush_lower_r, + output [30:0] io_dec_exu_tlu_exu_dec_tlu_flush_path_r, + input [1:0] io_dec_exu_tlu_exu_exu_i0_br_hist_r, + input io_dec_exu_tlu_exu_exu_i0_br_error_r, + input io_dec_exu_tlu_exu_exu_i0_br_start_error_r, + input [7:0] io_dec_exu_tlu_exu_exu_i0_br_index_r, + input io_dec_exu_tlu_exu_exu_i0_br_valid_r, + input io_dec_exu_tlu_exu_exu_i0_br_mp_r, + input io_dec_exu_tlu_exu_exu_i0_br_middle_r, + input io_dec_exu_tlu_exu_exu_pmu_i0_br_misp, + input io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken, + input io_dec_exu_tlu_exu_exu_pmu_i0_pc4, + input [30:0] io_dec_exu_tlu_exu_exu_npc_r, + output [30:0] io_dec_exu_ib_exu_dec_i0_pc_d, + output io_dec_exu_ib_exu_dec_debug_wdata_rs1_d, + output [31:0] io_dec_exu_gpr_exu_gpr_i0_rs1_d, + output [31:0] io_dec_exu_gpr_exu_gpr_i0_rs2_d, + input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn, + input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned, + input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error, + input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy, + output io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable, + output io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable, + output io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable, + input io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any, + input io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any, + input [31:0] io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any, + input io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m, + input [1:0] io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m, + input io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r, + input [1:0] io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r, + input io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid, + input io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error, + input [1:0] io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag, + input io_lsu_tlu_lsu_pmu_load_external_m, + input io_lsu_tlu_lsu_pmu_store_external_m, + input io_dec_dbg_dbg_ib_dbg_cmd_valid, + input io_dec_dbg_dbg_ib_dbg_cmd_write, + input [1:0] io_dec_dbg_dbg_ib_dbg_cmd_type, + input [31:0] io_dec_dbg_dbg_ib_dbg_cmd_addr, + input [31:0] io_dec_dbg_dbg_dctl_dbg_cmd_wrdata, + input io_dec_dma_dctl_dma_dma_dccm_stall_any, + input io_dec_dma_tlu_dma_dma_pmu_dccm_read, + input io_dec_dma_tlu_dma_dma_pmu_dccm_write, + input io_dec_dma_tlu_dma_dma_pmu_any_read, + input io_dec_dma_tlu_dma_dma_pmu_any_write, + output [2:0] io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty, + input io_dec_dma_tlu_dma_dma_dccm_stall_any, + input io_dec_dma_tlu_dma_dma_iccm_stall_any, + input [7:0] io_dec_pic_pic_claimid, + input [3:0] io_dec_pic_pic_pl, + input io_dec_pic_mhwakeup, + output [3:0] io_dec_pic_dec_tlu_meicurpl, + output [3:0] io_dec_pic_dec_tlu_meipt, + input io_dec_pic_mexintpend +); + wire instbuff_io_ifu_ib_ifu_i0_icaf; // @[dec.scala 128:24] + wire [1:0] instbuff_io_ifu_ib_ifu_i0_icaf_type; // @[dec.scala 128:24] + wire instbuff_io_ifu_ib_ifu_i0_icaf_second; // @[dec.scala 128:24] + wire instbuff_io_ifu_ib_ifu_i0_dbecc; // @[dec.scala 128:24] + wire [7:0] instbuff_io_ifu_ib_ifu_i0_bp_index; // @[dec.scala 128:24] + wire [7:0] instbuff_io_ifu_ib_ifu_i0_bp_fghr; // @[dec.scala 128:24] + wire [4:0] instbuff_io_ifu_ib_ifu_i0_bp_btag; // @[dec.scala 128:24] + wire instbuff_io_ifu_ib_ifu_i0_valid; // @[dec.scala 128:24] + wire [31:0] instbuff_io_ifu_ib_ifu_i0_instr; // @[dec.scala 128:24] + wire [30:0] instbuff_io_ifu_ib_ifu_i0_pc; // @[dec.scala 128:24] + wire instbuff_io_ifu_ib_ifu_i0_pc4; // @[dec.scala 128:24] + wire instbuff_io_ifu_ib_i0_brp_valid; // @[dec.scala 128:24] + wire [11:0] instbuff_io_ifu_ib_i0_brp_bits_toffset; // @[dec.scala 128:24] + wire [1:0] instbuff_io_ifu_ib_i0_brp_bits_hist; // @[dec.scala 128:24] + wire instbuff_io_ifu_ib_i0_brp_bits_br_error; // @[dec.scala 128:24] + wire instbuff_io_ifu_ib_i0_brp_bits_br_start_error; // @[dec.scala 128:24] + wire [30:0] instbuff_io_ifu_ib_i0_brp_bits_prett; // @[dec.scala 128:24] + wire instbuff_io_ifu_ib_i0_brp_bits_way; // @[dec.scala 128:24] + wire instbuff_io_ifu_ib_i0_brp_bits_ret; // @[dec.scala 128:24] + wire [30:0] instbuff_io_ib_exu_dec_i0_pc_d; // @[dec.scala 128:24] + wire instbuff_io_ib_exu_dec_debug_wdata_rs1_d; // @[dec.scala 128:24] + wire instbuff_io_dbg_ib_dbg_cmd_valid; // @[dec.scala 128:24] + wire instbuff_io_dbg_ib_dbg_cmd_write; // @[dec.scala 128:24] + wire [1:0] instbuff_io_dbg_ib_dbg_cmd_type; // @[dec.scala 128:24] + wire [31:0] instbuff_io_dbg_ib_dbg_cmd_addr; // @[dec.scala 128:24] + wire instbuff_io_dec_ib0_valid_d; // @[dec.scala 128:24] + wire [1:0] instbuff_io_dec_i0_icaf_type_d; // @[dec.scala 128:24] + wire [31:0] instbuff_io_dec_i0_instr_d; // @[dec.scala 128:24] + wire instbuff_io_dec_i0_pc4_d; // @[dec.scala 128:24] + wire instbuff_io_dec_i0_brp_valid; // @[dec.scala 128:24] + wire [11:0] instbuff_io_dec_i0_brp_bits_toffset; // @[dec.scala 128:24] + wire [1:0] instbuff_io_dec_i0_brp_bits_hist; // @[dec.scala 128:24] + wire instbuff_io_dec_i0_brp_bits_br_error; // @[dec.scala 128:24] + wire instbuff_io_dec_i0_brp_bits_br_start_error; // @[dec.scala 128:24] + wire [30:0] instbuff_io_dec_i0_brp_bits_prett; // @[dec.scala 128:24] + wire instbuff_io_dec_i0_brp_bits_way; // @[dec.scala 128:24] + wire instbuff_io_dec_i0_brp_bits_ret; // @[dec.scala 128:24] + wire [7:0] instbuff_io_dec_i0_bp_index; // @[dec.scala 128:24] + wire [7:0] instbuff_io_dec_i0_bp_fghr; // @[dec.scala 128:24] + wire [4:0] instbuff_io_dec_i0_bp_btag; // @[dec.scala 128:24] + wire instbuff_io_dec_i0_icaf_d; // @[dec.scala 128:24] + wire instbuff_io_dec_i0_icaf_second_d; // @[dec.scala 128:24] + wire instbuff_io_dec_i0_dbecc_d; // @[dec.scala 128:24] + wire instbuff_io_dec_debug_fence_d; // @[dec.scala 128:24] + wire decode_clock; // @[dec.scala 129:22] + wire decode_reset; // @[dec.scala 129:22] + wire [1:0] decode_io_decode_exu_dec_data_en; // @[dec.scala 129:22] + wire [1:0] decode_io_decode_exu_dec_ctl_en; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_clz; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_ctz; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_pcnt; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_sext_b; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_sext_h; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_slo; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_sro; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_min; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_max; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_pack; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_packu; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_packh; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_rol; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_ror; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_grev; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_gorc; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_zbb; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_sbset; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_sbclr; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_sbinv; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_sbext; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_sh1add; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_sh2add; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_sh3add; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_zba; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_land; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_lor; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_lxor; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_sll; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_srl; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_sra; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_beq; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_bne; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_blt; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_bge; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_add; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_sub; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_slt; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_unsign; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_jal; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_predict_t; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_predict_nt; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_csr_write; // @[dec.scala 129:22] + wire decode_io_decode_exu_i0_ap_csr_imm; // @[dec.scala 129:22] + wire decode_io_decode_exu_dec_i0_predict_p_d_valid; // @[dec.scala 129:22] + wire decode_io_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[dec.scala 129:22] + wire [1:0] decode_io_decode_exu_dec_i0_predict_p_d_bits_hist; // @[dec.scala 129:22] + wire [11:0] decode_io_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[dec.scala 129:22] + wire decode_io_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[dec.scala 129:22] + wire decode_io_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[dec.scala 129:22] + wire decode_io_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[dec.scala 129:22] + wire decode_io_decode_exu_dec_i0_predict_p_d_bits_pja; // @[dec.scala 129:22] + wire decode_io_decode_exu_dec_i0_predict_p_d_bits_way; // @[dec.scala 129:22] + wire decode_io_decode_exu_dec_i0_predict_p_d_bits_pret; // @[dec.scala 129:22] + wire [30:0] decode_io_decode_exu_dec_i0_predict_p_d_bits_prett; // @[dec.scala 129:22] + wire [7:0] decode_io_decode_exu_i0_predict_fghr_d; // @[dec.scala 129:22] + wire [7:0] decode_io_decode_exu_i0_predict_index_d; // @[dec.scala 129:22] + wire [4:0] decode_io_decode_exu_i0_predict_btag_d; // @[dec.scala 129:22] + wire decode_io_decode_exu_dec_i0_rs1_en_d; // @[dec.scala 129:22] + wire decode_io_decode_exu_dec_i0_branch_d; // @[dec.scala 129:22] + wire decode_io_decode_exu_dec_i0_rs2_en_d; // @[dec.scala 129:22] + wire [31:0] decode_io_decode_exu_dec_i0_immed_d; // @[dec.scala 129:22] + wire [31:0] decode_io_decode_exu_dec_i0_result_r; // @[dec.scala 129:22] + wire decode_io_decode_exu_dec_qual_lsu_d; // @[dec.scala 129:22] + wire decode_io_decode_exu_dec_i0_select_pc_d; // @[dec.scala 129:22] + wire [3:0] decode_io_decode_exu_dec_i0_rs1_bypass_en_d; // @[dec.scala 129:22] + wire [3:0] decode_io_decode_exu_dec_i0_rs2_bypass_en_d; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_valid; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_bits_rs1_sign; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_bits_rs2_sign; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_bits_low; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_bits_bext; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_bits_bdep; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_bits_clmul; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_bits_clmulh; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_bits_clmulr; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_bits_grev; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_bits_gorc; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_bits_shfl; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_bits_unshfl; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_bits_crc32_b; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_bits_crc32_h; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_bits_crc32_w; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_bits_crc32c_b; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_bits_crc32c_h; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_bits_crc32c_w; // @[dec.scala 129:22] + wire decode_io_decode_exu_mul_p_bits_bfp; // @[dec.scala 129:22] + wire [30:0] decode_io_decode_exu_pred_correct_npc_x; // @[dec.scala 129:22] + wire decode_io_decode_exu_dec_extint_stall; // @[dec.scala 129:22] + wire [31:0] decode_io_decode_exu_exu_i0_result_x; // @[dec.scala 129:22] + wire [31:0] decode_io_decode_exu_exu_csr_rs1_x; // @[dec.scala 129:22] + wire decode_io_dec_alu_dec_i0_alu_decode_d; // @[dec.scala 129:22] + wire decode_io_dec_alu_dec_csr_ren_d; // @[dec.scala 129:22] + wire [11:0] decode_io_dec_alu_dec_i0_br_immed_d; // @[dec.scala 129:22] + wire [30:0] decode_io_dec_alu_exu_i0_pc_x; // @[dec.scala 129:22] + wire decode_io_dec_div_div_p_valid; // @[dec.scala 129:22] + wire decode_io_dec_div_div_p_bits_unsign; // @[dec.scala 129:22] + wire decode_io_dec_div_div_p_bits_rem; // @[dec.scala 129:22] + wire decode_io_dec_div_dec_div_cancel; // @[dec.scala 129:22] + wire decode_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec.scala 129:22] + wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[dec.scala 129:22] + wire decode_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[dec.scala 129:22] + wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[dec.scala 129:22] + wire decode_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[dec.scala 129:22] + wire decode_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec.scala 129:22] + wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[dec.scala 129:22] + wire decode_io_dctl_dma_dma_dccm_stall_any; // @[dec.scala 129:22] + wire decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 129:22] + wire [15:0] decode_io_dec_aln_ifu_i0_cinst; // @[dec.scala 129:22] + wire [31:0] decode_io_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 129:22] + wire decode_io_dec_tlu_trace_disable; // @[dec.scala 129:22] + wire decode_io_dec_debug_valid_d; // @[dec.scala 129:22] + wire decode_io_dec_tlu_flush_extint; // @[dec.scala 129:22] + wire decode_io_dec_tlu_force_halt; // @[dec.scala 129:22] + wire [31:0] decode_io_dec_i0_inst_wb; // @[dec.scala 129:22] + wire [30:0] decode_io_dec_i0_pc_wb; // @[dec.scala 129:22] + wire [3:0] decode_io_dec_i0_trigger_match_d; // @[dec.scala 129:22] + wire decode_io_dec_tlu_wr_pause_r; // @[dec.scala 129:22] + wire decode_io_dec_tlu_pipelining_disable; // @[dec.scala 129:22] + wire [3:0] decode_io_lsu_trigger_match_m; // @[dec.scala 129:22] + wire decode_io_lsu_pmu_misaligned_m; // @[dec.scala 129:22] + wire decode_io_dec_tlu_debug_stall; // @[dec.scala 129:22] + wire decode_io_dec_tlu_flush_leak_one_r; // @[dec.scala 129:22] + wire decode_io_dec_debug_fence_d; // @[dec.scala 129:22] + wire decode_io_dec_i0_icaf_d; // @[dec.scala 129:22] + wire decode_io_dec_i0_icaf_second_d; // @[dec.scala 129:22] + wire [1:0] decode_io_dec_i0_icaf_type_d; // @[dec.scala 129:22] + wire decode_io_dec_i0_dbecc_d; // @[dec.scala 129:22] + wire decode_io_dec_i0_brp_valid; // @[dec.scala 129:22] + wire [11:0] decode_io_dec_i0_brp_bits_toffset; // @[dec.scala 129:22] + wire [1:0] decode_io_dec_i0_brp_bits_hist; // @[dec.scala 129:22] + wire decode_io_dec_i0_brp_bits_br_error; // @[dec.scala 129:22] + wire decode_io_dec_i0_brp_bits_br_start_error; // @[dec.scala 129:22] + wire [30:0] decode_io_dec_i0_brp_bits_prett; // @[dec.scala 129:22] + wire decode_io_dec_i0_brp_bits_way; // @[dec.scala 129:22] + wire decode_io_dec_i0_brp_bits_ret; // @[dec.scala 129:22] + wire [7:0] decode_io_dec_i0_bp_index; // @[dec.scala 129:22] + wire [7:0] decode_io_dec_i0_bp_fghr; // @[dec.scala 129:22] + wire [4:0] decode_io_dec_i0_bp_btag; // @[dec.scala 129:22] + wire decode_io_lsu_idle_any; // @[dec.scala 129:22] + wire decode_io_lsu_load_stall_any; // @[dec.scala 129:22] + wire decode_io_lsu_store_stall_any; // @[dec.scala 129:22] + wire decode_io_exu_div_wren; // @[dec.scala 129:22] + wire decode_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 129:22] + wire decode_io_dec_tlu_flush_lower_wb; // @[dec.scala 129:22] + wire decode_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 129:22] + wire decode_io_dec_tlu_flush_lower_r; // @[dec.scala 129:22] + wire decode_io_dec_tlu_flush_pause_r; // @[dec.scala 129:22] + wire decode_io_dec_tlu_presync_d; // @[dec.scala 129:22] + wire decode_io_dec_tlu_postsync_d; // @[dec.scala 129:22] + wire decode_io_dec_i0_pc4_d; // @[dec.scala 129:22] + wire [31:0] decode_io_dec_csr_rddata_d; // @[dec.scala 129:22] + wire decode_io_dec_csr_legal_d; // @[dec.scala 129:22] + wire [31:0] decode_io_lsu_result_m; // @[dec.scala 129:22] + wire [31:0] decode_io_lsu_result_corr_r; // @[dec.scala 129:22] + wire decode_io_exu_flush_final; // @[dec.scala 129:22] + wire [31:0] decode_io_dec_i0_instr_d; // @[dec.scala 129:22] + wire decode_io_dec_ib0_valid_d; // @[dec.scala 129:22] + wire decode_io_active_clk; // @[dec.scala 129:22] + wire decode_io_free_l2clk; // @[dec.scala 129:22] + wire decode_io_clk_override; // @[dec.scala 129:22] + wire [4:0] decode_io_dec_i0_rs1_d; // @[dec.scala 129:22] + wire [4:0] decode_io_dec_i0_rs2_d; // @[dec.scala 129:22] + wire [4:0] decode_io_dec_i0_waddr_r; // @[dec.scala 129:22] + wire decode_io_dec_i0_wen_r; // @[dec.scala 129:22] + wire [31:0] decode_io_dec_i0_wdata_r; // @[dec.scala 129:22] + wire decode_io_lsu_p_valid; // @[dec.scala 129:22] + wire decode_io_lsu_p_bits_fast_int; // @[dec.scala 129:22] + wire decode_io_lsu_p_bits_stack; // @[dec.scala 129:22] + wire decode_io_lsu_p_bits_by; // @[dec.scala 129:22] + wire decode_io_lsu_p_bits_half; // @[dec.scala 129:22] + wire decode_io_lsu_p_bits_word; // @[dec.scala 129:22] + wire decode_io_lsu_p_bits_load; // @[dec.scala 129:22] + wire decode_io_lsu_p_bits_store; // @[dec.scala 129:22] + wire decode_io_lsu_p_bits_unsign; // @[dec.scala 129:22] + wire decode_io_lsu_p_bits_store_data_bypass_d; // @[dec.scala 129:22] + wire decode_io_lsu_p_bits_load_ldst_bypass_d; // @[dec.scala 129:22] + wire [4:0] decode_io_div_waddr_wb; // @[dec.scala 129:22] + wire decode_io_dec_lsu_valid_raw_d; // @[dec.scala 129:22] + wire [11:0] decode_io_dec_lsu_offset_d; // @[dec.scala 129:22] + wire decode_io_dec_csr_wen_unq_d; // @[dec.scala 129:22] + wire decode_io_dec_csr_any_unq_d; // @[dec.scala 129:22] + wire [11:0] decode_io_dec_csr_rdaddr_d; // @[dec.scala 129:22] + wire decode_io_dec_csr_wen_r; // @[dec.scala 129:22] + wire [11:0] decode_io_dec_csr_wraddr_r; // @[dec.scala 129:22] + wire [31:0] decode_io_dec_csr_wrdata_r; // @[dec.scala 129:22] + wire decode_io_dec_csr_stall_int_ff; // @[dec.scala 129:22] + wire decode_io_dec_tlu_i0_valid_r; // @[dec.scala 129:22] + wire decode_io_dec_tlu_packet_r_legal; // @[dec.scala 129:22] + wire decode_io_dec_tlu_packet_r_icaf; // @[dec.scala 129:22] + wire decode_io_dec_tlu_packet_r_icaf_second; // @[dec.scala 129:22] + wire [1:0] decode_io_dec_tlu_packet_r_icaf_type; // @[dec.scala 129:22] + wire decode_io_dec_tlu_packet_r_fence_i; // @[dec.scala 129:22] + wire [3:0] decode_io_dec_tlu_packet_r_i0trigger; // @[dec.scala 129:22] + wire [3:0] decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec.scala 129:22] + wire decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec.scala 129:22] + wire decode_io_dec_tlu_packet_r_pmu_divide; // @[dec.scala 129:22] + wire decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec.scala 129:22] + wire [30:0] decode_io_dec_tlu_i0_pc_r; // @[dec.scala 129:22] + wire [31:0] decode_io_dec_illegal_inst; // @[dec.scala 129:22] + wire decode_io_dec_pmu_instr_decoded; // @[dec.scala 129:22] + wire decode_io_dec_pmu_decode_stall; // @[dec.scala 129:22] + wire decode_io_dec_pmu_presync_stall; // @[dec.scala 129:22] + wire decode_io_dec_pmu_postsync_stall; // @[dec.scala 129:22] + wire decode_io_dec_nonblock_load_wen; // @[dec.scala 129:22] + wire [4:0] decode_io_dec_nonblock_load_waddr; // @[dec.scala 129:22] + wire decode_io_dec_pause_state; // @[dec.scala 129:22] + wire decode_io_dec_pause_state_cg; // @[dec.scala 129:22] + wire decode_io_dec_div_active; // @[dec.scala 129:22] + wire gpr_clock; // @[dec.scala 130:19] + wire gpr_reset; // @[dec.scala 130:19] + wire [4:0] gpr_io_raddr0; // @[dec.scala 130:19] + wire [4:0] gpr_io_raddr1; // @[dec.scala 130:19] + wire gpr_io_wen0; // @[dec.scala 130:19] + wire [4:0] gpr_io_waddr0; // @[dec.scala 130:19] + wire [31:0] gpr_io_wd0; // @[dec.scala 130:19] + wire gpr_io_wen1; // @[dec.scala 130:19] + wire [4:0] gpr_io_waddr1; // @[dec.scala 130:19] + wire [31:0] gpr_io_wd1; // @[dec.scala 130:19] + wire gpr_io_wen2; // @[dec.scala 130:19] + wire [4:0] gpr_io_waddr2; // @[dec.scala 130:19] + wire [31:0] gpr_io_wd2; // @[dec.scala 130:19] + wire [31:0] gpr_io_gpr_exu_gpr_i0_rs1_d; // @[dec.scala 130:19] + wire [31:0] gpr_io_gpr_exu_gpr_i0_rs2_d; // @[dec.scala 130:19] + wire tlu_clock; // @[dec.scala 131:19] + wire tlu_reset; // @[dec.scala 131:19] + wire [29:0] tlu_io_tlu_exu_dec_tlu_meihap; // @[dec.scala 131:19] + wire tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 131:19] + wire [30:0] tlu_io_tlu_exu_dec_tlu_flush_path_r; // @[dec.scala 131:19] + wire [1:0] tlu_io_tlu_exu_exu_i0_br_hist_r; // @[dec.scala 131:19] + wire tlu_io_tlu_exu_exu_i0_br_error_r; // @[dec.scala 131:19] + wire tlu_io_tlu_exu_exu_i0_br_start_error_r; // @[dec.scala 131:19] + wire tlu_io_tlu_exu_exu_i0_br_valid_r; // @[dec.scala 131:19] + wire tlu_io_tlu_exu_exu_i0_br_mp_r; // @[dec.scala 131:19] + wire tlu_io_tlu_exu_exu_i0_br_middle_r; // @[dec.scala 131:19] + wire tlu_io_tlu_exu_exu_pmu_i0_br_misp; // @[dec.scala 131:19] + wire tlu_io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec.scala 131:19] + wire tlu_io_tlu_exu_exu_pmu_i0_pc4; // @[dec.scala 131:19] + wire [30:0] tlu_io_tlu_exu_exu_npc_r; // @[dec.scala 131:19] + wire tlu_io_tlu_dma_dma_pmu_dccm_read; // @[dec.scala 131:19] + wire tlu_io_tlu_dma_dma_pmu_dccm_write; // @[dec.scala 131:19] + wire tlu_io_tlu_dma_dma_pmu_any_read; // @[dec.scala 131:19] + wire tlu_io_tlu_dma_dma_pmu_any_write; // @[dec.scala 131:19] + wire [2:0] tlu_io_tlu_dma_dec_tlu_dma_qos_prty; // @[dec.scala 131:19] + wire tlu_io_tlu_dma_dma_dccm_stall_any; // @[dec.scala 131:19] + wire tlu_io_tlu_dma_dma_iccm_stall_any; // @[dec.scala 131:19] + wire tlu_io_free_clk; // @[dec.scala 131:19] + wire tlu_io_free_l2clk; // @[dec.scala 131:19] + wire [30:0] tlu_io_rst_vec; // @[dec.scala 131:19] + wire tlu_io_nmi_int; // @[dec.scala 131:19] + wire [30:0] tlu_io_nmi_vec; // @[dec.scala 131:19] + wire tlu_io_i_cpu_halt_req; // @[dec.scala 131:19] + wire tlu_io_i_cpu_run_req; // @[dec.scala 131:19] + wire tlu_io_lsu_fastint_stall_any; // @[dec.scala 131:19] + wire tlu_io_lsu_idle_any; // @[dec.scala 131:19] + wire tlu_io_dec_pmu_instr_decoded; // @[dec.scala 131:19] + wire tlu_io_dec_pmu_decode_stall; // @[dec.scala 131:19] + wire tlu_io_dec_pmu_presync_stall; // @[dec.scala 131:19] + wire tlu_io_dec_pmu_postsync_stall; // @[dec.scala 131:19] + wire tlu_io_lsu_store_stall_any; // @[dec.scala 131:19] + wire [30:0] tlu_io_lsu_fir_addr; // @[dec.scala 131:19] + wire [1:0] tlu_io_lsu_fir_error; // @[dec.scala 131:19] + wire tlu_io_iccm_dma_sb_error; // @[dec.scala 131:19] + wire tlu_io_lsu_error_pkt_r_valid; // @[dec.scala 131:19] + wire tlu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec.scala 131:19] + wire tlu_io_lsu_error_pkt_r_bits_inst_type; // @[dec.scala 131:19] + wire tlu_io_lsu_error_pkt_r_bits_exc_type; // @[dec.scala 131:19] + wire [3:0] tlu_io_lsu_error_pkt_r_bits_mscause; // @[dec.scala 131:19] + wire [31:0] tlu_io_lsu_error_pkt_r_bits_addr; // @[dec.scala 131:19] + wire tlu_io_lsu_single_ecc_error_incr; // @[dec.scala 131:19] + wire tlu_io_dec_pause_state; // @[dec.scala 131:19] + wire tlu_io_dec_csr_wen_unq_d; // @[dec.scala 131:19] + wire tlu_io_dec_csr_any_unq_d; // @[dec.scala 131:19] + wire [11:0] tlu_io_dec_csr_rdaddr_d; // @[dec.scala 131:19] + wire tlu_io_dec_csr_wen_r; // @[dec.scala 131:19] + wire [11:0] tlu_io_dec_csr_wraddr_r; // @[dec.scala 131:19] + wire [31:0] tlu_io_dec_csr_wrdata_r; // @[dec.scala 131:19] + wire tlu_io_dec_csr_stall_int_ff; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_i0_valid_r; // @[dec.scala 131:19] + wire [30:0] tlu_io_dec_tlu_i0_pc_r; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_packet_r_legal; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_packet_r_icaf; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_packet_r_icaf_second; // @[dec.scala 131:19] + wire [1:0] tlu_io_dec_tlu_packet_r_icaf_type; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_packet_r_fence_i; // @[dec.scala 131:19] + wire [3:0] tlu_io_dec_tlu_packet_r_i0trigger; // @[dec.scala 131:19] + wire [3:0] tlu_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_packet_r_pmu_divide; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec.scala 131:19] + wire [31:0] tlu_io_dec_illegal_inst; // @[dec.scala 131:19] + wire tlu_io_dec_i0_decode_d; // @[dec.scala 131:19] + wire tlu_io_exu_i0_br_way_r; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_core_empty; // @[dec.scala 131:19] + wire tlu_io_dec_dbg_cmd_done; // @[dec.scala 131:19] + wire tlu_io_dec_dbg_cmd_fail; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_dbg_halted; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_debug_mode; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_resume_ack; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_debug_stall; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_mpc_halted_only; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_flush_extint; // @[dec.scala 131:19] + wire tlu_io_dbg_halt_req; // @[dec.scala 131:19] + wire tlu_io_dbg_resume_req; // @[dec.scala 131:19] + wire tlu_io_dec_div_active; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_0_select; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_0_store; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_0_load; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_0_execute; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_0_m; // @[dec.scala 131:19] + wire [31:0] tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_1_select; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_1_store; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_1_load; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_1_execute; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_1_m; // @[dec.scala 131:19] + wire [31:0] tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_2_select; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_2_store; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_2_load; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_2_execute; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_2_m; // @[dec.scala 131:19] + wire [31:0] tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_3_select; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_3_store; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_3_load; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_3_execute; // @[dec.scala 131:19] + wire tlu_io_trigger_pkt_any_3_m; // @[dec.scala 131:19] + wire [31:0] tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 131:19] + wire tlu_io_timer_int; // @[dec.scala 131:19] + wire tlu_io_soft_int; // @[dec.scala 131:19] + wire tlu_io_o_cpu_halt_status; // @[dec.scala 131:19] + wire tlu_io_o_cpu_halt_ack; // @[dec.scala 131:19] + wire tlu_io_o_cpu_run_ack; // @[dec.scala 131:19] + wire tlu_io_o_debug_mode_status; // @[dec.scala 131:19] + wire [27:0] tlu_io_core_id; // @[dec.scala 131:19] + wire tlu_io_mpc_debug_halt_req; // @[dec.scala 131:19] + wire tlu_io_mpc_debug_run_req; // @[dec.scala 131:19] + wire tlu_io_mpc_reset_run_req; // @[dec.scala 131:19] + wire tlu_io_mpc_debug_halt_ack; // @[dec.scala 131:19] + wire tlu_io_mpc_debug_run_ack; // @[dec.scala 131:19] + wire tlu_io_debug_brkpt_status; // @[dec.scala 131:19] + wire [31:0] tlu_io_dec_csr_rddata_d; // @[dec.scala 131:19] + wire tlu_io_dec_csr_legal_d; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_wr_pause_r; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_flush_pause_r; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_presync_d; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_postsync_d; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_perfcnt0; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_perfcnt1; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_perfcnt2; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_perfcnt3; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_i0_exc_valid_wb1; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_i0_valid_wb1; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_int_valid_wb1; // @[dec.scala 131:19] + wire [4:0] tlu_io_dec_tlu_exc_cause_wb1; // @[dec.scala 131:19] + wire [31:0] tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_pipelining_disable; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_trace_disable; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_ifu_clk_override; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 131:19] + wire tlu_io_dec_tlu_flush_lower_wb; // @[dec.scala 131:19] + wire tlu_io_ifu_pmu_instr_aligned; // @[dec.scala 131:19] + wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_valid; // @[dec.scala 131:19] + wire [1:0] tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist; // @[dec.scala 131:19] + wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[dec.scala 131:19] + wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[dec.scala 131:19] + wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_way; // @[dec.scala 131:19] + wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle; // @[dec.scala 131:19] + wire tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 131:19] + wire tlu_io_tlu_bp_dec_tlu_bpred_disable; // @[dec.scala 131:19] + wire tlu_io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec.scala 131:19] + wire [31:0] tlu_io_tlu_ifc_dec_tlu_mrac_ff; // @[dec.scala 131:19] + wire tlu_io_tlu_ifc_ifu_pmu_fetch_stall; // @[dec.scala 131:19] + wire tlu_io_tlu_mem_dec_tlu_flush_err_wb; // @[dec.scala 131:19] + wire tlu_io_tlu_mem_dec_tlu_i0_commit_cmt; // @[dec.scala 131:19] + wire tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 131:19] + wire tlu_io_tlu_mem_dec_tlu_fence_i_wb; // @[dec.scala 131:19] + wire [70:0] tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec.scala 131:19] + wire [16:0] tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec.scala 131:19] + wire tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec.scala 131:19] + wire tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec.scala 131:19] + wire tlu_io_tlu_mem_dec_tlu_core_ecc_disable; // @[dec.scala 131:19] + wire tlu_io_tlu_mem_ifu_pmu_ic_miss; // @[dec.scala 131:19] + wire tlu_io_tlu_mem_ifu_pmu_ic_hit; // @[dec.scala 131:19] + wire tlu_io_tlu_mem_ifu_pmu_bus_error; // @[dec.scala 131:19] + wire tlu_io_tlu_mem_ifu_pmu_bus_busy; // @[dec.scala 131:19] + wire tlu_io_tlu_mem_ifu_pmu_bus_trxn; // @[dec.scala 131:19] + wire tlu_io_tlu_mem_ifu_ic_error_start; // @[dec.scala 131:19] + wire tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err; // @[dec.scala 131:19] + wire [70:0] tlu_io_tlu_mem_ifu_ic_debug_rd_data; // @[dec.scala 131:19] + wire tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec.scala 131:19] + wire tlu_io_tlu_mem_ifu_miss_state_idle; // @[dec.scala 131:19] + wire tlu_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec.scala 131:19] + wire tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec.scala 131:19] + wire tlu_io_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 131:19] + wire tlu_io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 131:19] + wire tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 131:19] + wire tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 131:19] + wire tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 131:19] + wire tlu_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec.scala 131:19] + wire tlu_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec.scala 131:19] + wire [31:0] tlu_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec.scala 131:19] + wire tlu_io_lsu_tlu_lsu_pmu_load_external_m; // @[dec.scala 131:19] + wire tlu_io_lsu_tlu_lsu_pmu_store_external_m; // @[dec.scala 131:19] + wire [7:0] tlu_io_dec_pic_pic_claimid; // @[dec.scala 131:19] + wire [3:0] tlu_io_dec_pic_pic_pl; // @[dec.scala 131:19] + wire tlu_io_dec_pic_mhwakeup; // @[dec.scala 131:19] + wire [3:0] tlu_io_dec_pic_dec_tlu_meicurpl; // @[dec.scala 131:19] + wire [3:0] tlu_io_dec_pic_dec_tlu_meipt; // @[dec.scala 131:19] + wire tlu_io_dec_pic_mexintpend; // @[dec.scala 131:19] + wire dec_trigger_io_trigger_pkt_any_0_select; // @[dec.scala 132:27] + wire dec_trigger_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 132:27] + wire dec_trigger_io_trigger_pkt_any_0_execute; // @[dec.scala 132:27] + wire dec_trigger_io_trigger_pkt_any_0_m; // @[dec.scala 132:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_0_tdata2; // @[dec.scala 132:27] + wire dec_trigger_io_trigger_pkt_any_1_select; // @[dec.scala 132:27] + wire dec_trigger_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 132:27] + wire dec_trigger_io_trigger_pkt_any_1_execute; // @[dec.scala 132:27] + wire dec_trigger_io_trigger_pkt_any_1_m; // @[dec.scala 132:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_1_tdata2; // @[dec.scala 132:27] + wire dec_trigger_io_trigger_pkt_any_2_select; // @[dec.scala 132:27] + wire dec_trigger_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 132:27] + wire dec_trigger_io_trigger_pkt_any_2_execute; // @[dec.scala 132:27] + wire dec_trigger_io_trigger_pkt_any_2_m; // @[dec.scala 132:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_2_tdata2; // @[dec.scala 132:27] + wire dec_trigger_io_trigger_pkt_any_3_select; // @[dec.scala 132:27] + wire dec_trigger_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 132:27] + wire dec_trigger_io_trigger_pkt_any_3_execute; // @[dec.scala 132:27] + wire dec_trigger_io_trigger_pkt_any_3_m; // @[dec.scala 132:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_3_tdata2; // @[dec.scala 132:27] + wire [30:0] dec_trigger_io_dec_i0_pc_d; // @[dec.scala 132:27] + wire [3:0] dec_trigger_io_dec_i0_trigger_match_d; // @[dec.scala 132:27] + wire _T_1 = tlu_io_dec_tlu_int_valid_wb1 | tlu_io_dec_tlu_i0_valid_wb1; // @[dec.scala 312:71] + dec_ib_ctl instbuff ( // @[dec.scala 128:24] + .io_ifu_ib_ifu_i0_icaf(instbuff_io_ifu_ib_ifu_i0_icaf), + .io_ifu_ib_ifu_i0_icaf_type(instbuff_io_ifu_ib_ifu_i0_icaf_type), + .io_ifu_ib_ifu_i0_icaf_second(instbuff_io_ifu_ib_ifu_i0_icaf_second), + .io_ifu_ib_ifu_i0_dbecc(instbuff_io_ifu_ib_ifu_i0_dbecc), + .io_ifu_ib_ifu_i0_bp_index(instbuff_io_ifu_ib_ifu_i0_bp_index), + .io_ifu_ib_ifu_i0_bp_fghr(instbuff_io_ifu_ib_ifu_i0_bp_fghr), + .io_ifu_ib_ifu_i0_bp_btag(instbuff_io_ifu_ib_ifu_i0_bp_btag), + .io_ifu_ib_ifu_i0_valid(instbuff_io_ifu_ib_ifu_i0_valid), + .io_ifu_ib_ifu_i0_instr(instbuff_io_ifu_ib_ifu_i0_instr), + .io_ifu_ib_ifu_i0_pc(instbuff_io_ifu_ib_ifu_i0_pc), + .io_ifu_ib_ifu_i0_pc4(instbuff_io_ifu_ib_ifu_i0_pc4), + .io_ifu_ib_i0_brp_valid(instbuff_io_ifu_ib_i0_brp_valid), + .io_ifu_ib_i0_brp_bits_toffset(instbuff_io_ifu_ib_i0_brp_bits_toffset), + .io_ifu_ib_i0_brp_bits_hist(instbuff_io_ifu_ib_i0_brp_bits_hist), + .io_ifu_ib_i0_brp_bits_br_error(instbuff_io_ifu_ib_i0_brp_bits_br_error), + .io_ifu_ib_i0_brp_bits_br_start_error(instbuff_io_ifu_ib_i0_brp_bits_br_start_error), + .io_ifu_ib_i0_brp_bits_prett(instbuff_io_ifu_ib_i0_brp_bits_prett), + .io_ifu_ib_i0_brp_bits_way(instbuff_io_ifu_ib_i0_brp_bits_way), + .io_ifu_ib_i0_brp_bits_ret(instbuff_io_ifu_ib_i0_brp_bits_ret), + .io_ib_exu_dec_i0_pc_d(instbuff_io_ib_exu_dec_i0_pc_d), + .io_ib_exu_dec_debug_wdata_rs1_d(instbuff_io_ib_exu_dec_debug_wdata_rs1_d), + .io_dbg_ib_dbg_cmd_valid(instbuff_io_dbg_ib_dbg_cmd_valid), + .io_dbg_ib_dbg_cmd_write(instbuff_io_dbg_ib_dbg_cmd_write), + .io_dbg_ib_dbg_cmd_type(instbuff_io_dbg_ib_dbg_cmd_type), + .io_dbg_ib_dbg_cmd_addr(instbuff_io_dbg_ib_dbg_cmd_addr), + .io_dec_ib0_valid_d(instbuff_io_dec_ib0_valid_d), + .io_dec_i0_icaf_type_d(instbuff_io_dec_i0_icaf_type_d), + .io_dec_i0_instr_d(instbuff_io_dec_i0_instr_d), + .io_dec_i0_pc4_d(instbuff_io_dec_i0_pc4_d), + .io_dec_i0_brp_valid(instbuff_io_dec_i0_brp_valid), + .io_dec_i0_brp_bits_toffset(instbuff_io_dec_i0_brp_bits_toffset), + .io_dec_i0_brp_bits_hist(instbuff_io_dec_i0_brp_bits_hist), + .io_dec_i0_brp_bits_br_error(instbuff_io_dec_i0_brp_bits_br_error), + .io_dec_i0_brp_bits_br_start_error(instbuff_io_dec_i0_brp_bits_br_start_error), + .io_dec_i0_brp_bits_prett(instbuff_io_dec_i0_brp_bits_prett), + .io_dec_i0_brp_bits_way(instbuff_io_dec_i0_brp_bits_way), + .io_dec_i0_brp_bits_ret(instbuff_io_dec_i0_brp_bits_ret), + .io_dec_i0_bp_index(instbuff_io_dec_i0_bp_index), + .io_dec_i0_bp_fghr(instbuff_io_dec_i0_bp_fghr), + .io_dec_i0_bp_btag(instbuff_io_dec_i0_bp_btag), + .io_dec_i0_icaf_d(instbuff_io_dec_i0_icaf_d), + .io_dec_i0_icaf_second_d(instbuff_io_dec_i0_icaf_second_d), + .io_dec_i0_dbecc_d(instbuff_io_dec_i0_dbecc_d), + .io_dec_debug_fence_d(instbuff_io_dec_debug_fence_d) + ); + dec_decode_ctl decode ( // @[dec.scala 129:22] + .clock(decode_clock), + .reset(decode_reset), + .io_decode_exu_dec_data_en(decode_io_decode_exu_dec_data_en), + .io_decode_exu_dec_ctl_en(decode_io_decode_exu_dec_ctl_en), + .io_decode_exu_i0_ap_clz(decode_io_decode_exu_i0_ap_clz), + .io_decode_exu_i0_ap_ctz(decode_io_decode_exu_i0_ap_ctz), + .io_decode_exu_i0_ap_pcnt(decode_io_decode_exu_i0_ap_pcnt), + .io_decode_exu_i0_ap_sext_b(decode_io_decode_exu_i0_ap_sext_b), + .io_decode_exu_i0_ap_sext_h(decode_io_decode_exu_i0_ap_sext_h), + .io_decode_exu_i0_ap_slo(decode_io_decode_exu_i0_ap_slo), + .io_decode_exu_i0_ap_sro(decode_io_decode_exu_i0_ap_sro), + .io_decode_exu_i0_ap_min(decode_io_decode_exu_i0_ap_min), + .io_decode_exu_i0_ap_max(decode_io_decode_exu_i0_ap_max), + .io_decode_exu_i0_ap_pack(decode_io_decode_exu_i0_ap_pack), + .io_decode_exu_i0_ap_packu(decode_io_decode_exu_i0_ap_packu), + .io_decode_exu_i0_ap_packh(decode_io_decode_exu_i0_ap_packh), + .io_decode_exu_i0_ap_rol(decode_io_decode_exu_i0_ap_rol), + .io_decode_exu_i0_ap_ror(decode_io_decode_exu_i0_ap_ror), + .io_decode_exu_i0_ap_grev(decode_io_decode_exu_i0_ap_grev), + .io_decode_exu_i0_ap_gorc(decode_io_decode_exu_i0_ap_gorc), + .io_decode_exu_i0_ap_zbb(decode_io_decode_exu_i0_ap_zbb), + .io_decode_exu_i0_ap_sbset(decode_io_decode_exu_i0_ap_sbset), + .io_decode_exu_i0_ap_sbclr(decode_io_decode_exu_i0_ap_sbclr), + .io_decode_exu_i0_ap_sbinv(decode_io_decode_exu_i0_ap_sbinv), + .io_decode_exu_i0_ap_sbext(decode_io_decode_exu_i0_ap_sbext), + .io_decode_exu_i0_ap_sh1add(decode_io_decode_exu_i0_ap_sh1add), + .io_decode_exu_i0_ap_sh2add(decode_io_decode_exu_i0_ap_sh2add), + .io_decode_exu_i0_ap_sh3add(decode_io_decode_exu_i0_ap_sh3add), + .io_decode_exu_i0_ap_zba(decode_io_decode_exu_i0_ap_zba), + .io_decode_exu_i0_ap_land(decode_io_decode_exu_i0_ap_land), + .io_decode_exu_i0_ap_lor(decode_io_decode_exu_i0_ap_lor), + .io_decode_exu_i0_ap_lxor(decode_io_decode_exu_i0_ap_lxor), + .io_decode_exu_i0_ap_sll(decode_io_decode_exu_i0_ap_sll), + .io_decode_exu_i0_ap_srl(decode_io_decode_exu_i0_ap_srl), + .io_decode_exu_i0_ap_sra(decode_io_decode_exu_i0_ap_sra), + .io_decode_exu_i0_ap_beq(decode_io_decode_exu_i0_ap_beq), + .io_decode_exu_i0_ap_bne(decode_io_decode_exu_i0_ap_bne), + .io_decode_exu_i0_ap_blt(decode_io_decode_exu_i0_ap_blt), + .io_decode_exu_i0_ap_bge(decode_io_decode_exu_i0_ap_bge), + .io_decode_exu_i0_ap_add(decode_io_decode_exu_i0_ap_add), + .io_decode_exu_i0_ap_sub(decode_io_decode_exu_i0_ap_sub), + .io_decode_exu_i0_ap_slt(decode_io_decode_exu_i0_ap_slt), + .io_decode_exu_i0_ap_unsign(decode_io_decode_exu_i0_ap_unsign), + .io_decode_exu_i0_ap_jal(decode_io_decode_exu_i0_ap_jal), + .io_decode_exu_i0_ap_predict_t(decode_io_decode_exu_i0_ap_predict_t), + .io_decode_exu_i0_ap_predict_nt(decode_io_decode_exu_i0_ap_predict_nt), + .io_decode_exu_i0_ap_csr_write(decode_io_decode_exu_i0_ap_csr_write), + .io_decode_exu_i0_ap_csr_imm(decode_io_decode_exu_i0_ap_csr_imm), + .io_decode_exu_dec_i0_predict_p_d_valid(decode_io_decode_exu_dec_i0_predict_p_d_valid), + .io_decode_exu_dec_i0_predict_p_d_bits_pc4(decode_io_decode_exu_dec_i0_predict_p_d_bits_pc4), + .io_decode_exu_dec_i0_predict_p_d_bits_hist(decode_io_decode_exu_dec_i0_predict_p_d_bits_hist), + .io_decode_exu_dec_i0_predict_p_d_bits_toffset(decode_io_decode_exu_dec_i0_predict_p_d_bits_toffset), + .io_decode_exu_dec_i0_predict_p_d_bits_br_error(decode_io_decode_exu_dec_i0_predict_p_d_bits_br_error), + .io_decode_exu_dec_i0_predict_p_d_bits_br_start_error(decode_io_decode_exu_dec_i0_predict_p_d_bits_br_start_error), + .io_decode_exu_dec_i0_predict_p_d_bits_pcall(decode_io_decode_exu_dec_i0_predict_p_d_bits_pcall), + .io_decode_exu_dec_i0_predict_p_d_bits_pja(decode_io_decode_exu_dec_i0_predict_p_d_bits_pja), + .io_decode_exu_dec_i0_predict_p_d_bits_way(decode_io_decode_exu_dec_i0_predict_p_d_bits_way), + .io_decode_exu_dec_i0_predict_p_d_bits_pret(decode_io_decode_exu_dec_i0_predict_p_d_bits_pret), + .io_decode_exu_dec_i0_predict_p_d_bits_prett(decode_io_decode_exu_dec_i0_predict_p_d_bits_prett), + .io_decode_exu_i0_predict_fghr_d(decode_io_decode_exu_i0_predict_fghr_d), + .io_decode_exu_i0_predict_index_d(decode_io_decode_exu_i0_predict_index_d), + .io_decode_exu_i0_predict_btag_d(decode_io_decode_exu_i0_predict_btag_d), + .io_decode_exu_dec_i0_rs1_en_d(decode_io_decode_exu_dec_i0_rs1_en_d), + .io_decode_exu_dec_i0_branch_d(decode_io_decode_exu_dec_i0_branch_d), + .io_decode_exu_dec_i0_rs2_en_d(decode_io_decode_exu_dec_i0_rs2_en_d), + .io_decode_exu_dec_i0_immed_d(decode_io_decode_exu_dec_i0_immed_d), + .io_decode_exu_dec_i0_result_r(decode_io_decode_exu_dec_i0_result_r), + .io_decode_exu_dec_qual_lsu_d(decode_io_decode_exu_dec_qual_lsu_d), + .io_decode_exu_dec_i0_select_pc_d(decode_io_decode_exu_dec_i0_select_pc_d), + .io_decode_exu_dec_i0_rs1_bypass_en_d(decode_io_decode_exu_dec_i0_rs1_bypass_en_d), + .io_decode_exu_dec_i0_rs2_bypass_en_d(decode_io_decode_exu_dec_i0_rs2_bypass_en_d), + .io_decode_exu_mul_p_valid(decode_io_decode_exu_mul_p_valid), + .io_decode_exu_mul_p_bits_rs1_sign(decode_io_decode_exu_mul_p_bits_rs1_sign), + .io_decode_exu_mul_p_bits_rs2_sign(decode_io_decode_exu_mul_p_bits_rs2_sign), + .io_decode_exu_mul_p_bits_low(decode_io_decode_exu_mul_p_bits_low), + .io_decode_exu_mul_p_bits_bext(decode_io_decode_exu_mul_p_bits_bext), + .io_decode_exu_mul_p_bits_bdep(decode_io_decode_exu_mul_p_bits_bdep), + .io_decode_exu_mul_p_bits_clmul(decode_io_decode_exu_mul_p_bits_clmul), + .io_decode_exu_mul_p_bits_clmulh(decode_io_decode_exu_mul_p_bits_clmulh), + .io_decode_exu_mul_p_bits_clmulr(decode_io_decode_exu_mul_p_bits_clmulr), + .io_decode_exu_mul_p_bits_grev(decode_io_decode_exu_mul_p_bits_grev), + .io_decode_exu_mul_p_bits_gorc(decode_io_decode_exu_mul_p_bits_gorc), + .io_decode_exu_mul_p_bits_shfl(decode_io_decode_exu_mul_p_bits_shfl), + .io_decode_exu_mul_p_bits_unshfl(decode_io_decode_exu_mul_p_bits_unshfl), + .io_decode_exu_mul_p_bits_crc32_b(decode_io_decode_exu_mul_p_bits_crc32_b), + .io_decode_exu_mul_p_bits_crc32_h(decode_io_decode_exu_mul_p_bits_crc32_h), + .io_decode_exu_mul_p_bits_crc32_w(decode_io_decode_exu_mul_p_bits_crc32_w), + .io_decode_exu_mul_p_bits_crc32c_b(decode_io_decode_exu_mul_p_bits_crc32c_b), + .io_decode_exu_mul_p_bits_crc32c_h(decode_io_decode_exu_mul_p_bits_crc32c_h), + .io_decode_exu_mul_p_bits_crc32c_w(decode_io_decode_exu_mul_p_bits_crc32c_w), + .io_decode_exu_mul_p_bits_bfp(decode_io_decode_exu_mul_p_bits_bfp), + .io_decode_exu_pred_correct_npc_x(decode_io_decode_exu_pred_correct_npc_x), + .io_decode_exu_dec_extint_stall(decode_io_decode_exu_dec_extint_stall), + .io_decode_exu_exu_i0_result_x(decode_io_decode_exu_exu_i0_result_x), + .io_decode_exu_exu_csr_rs1_x(decode_io_decode_exu_exu_csr_rs1_x), + .io_dec_alu_dec_i0_alu_decode_d(decode_io_dec_alu_dec_i0_alu_decode_d), + .io_dec_alu_dec_csr_ren_d(decode_io_dec_alu_dec_csr_ren_d), + .io_dec_alu_dec_i0_br_immed_d(decode_io_dec_alu_dec_i0_br_immed_d), + .io_dec_alu_exu_i0_pc_x(decode_io_dec_alu_exu_i0_pc_x), + .io_dec_div_div_p_valid(decode_io_dec_div_div_p_valid), + .io_dec_div_div_p_bits_unsign(decode_io_dec_div_div_p_bits_unsign), + .io_dec_div_div_p_bits_rem(decode_io_dec_div_div_p_bits_rem), + .io_dec_div_dec_div_cancel(decode_io_dec_div_dec_div_cancel), + .io_dctl_busbuff_lsu_nonblock_load_valid_m(decode_io_dctl_busbuff_lsu_nonblock_load_valid_m), + .io_dctl_busbuff_lsu_nonblock_load_tag_m(decode_io_dctl_busbuff_lsu_nonblock_load_tag_m), + .io_dctl_busbuff_lsu_nonblock_load_inv_r(decode_io_dctl_busbuff_lsu_nonblock_load_inv_r), + .io_dctl_busbuff_lsu_nonblock_load_inv_tag_r(decode_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r), + .io_dctl_busbuff_lsu_nonblock_load_data_valid(decode_io_dctl_busbuff_lsu_nonblock_load_data_valid), + .io_dctl_busbuff_lsu_nonblock_load_data_error(decode_io_dctl_busbuff_lsu_nonblock_load_data_error), + .io_dctl_busbuff_lsu_nonblock_load_data_tag(decode_io_dctl_busbuff_lsu_nonblock_load_data_tag), + .io_dctl_dma_dma_dccm_stall_any(decode_io_dctl_dma_dma_dccm_stall_any), + .io_dec_aln_dec_i0_decode_d(decode_io_dec_aln_dec_i0_decode_d), + .io_dec_aln_ifu_i0_cinst(decode_io_dec_aln_ifu_i0_cinst), + .io_dbg_dctl_dbg_cmd_wrdata(decode_io_dbg_dctl_dbg_cmd_wrdata), + .io_dec_tlu_trace_disable(decode_io_dec_tlu_trace_disable), + .io_dec_debug_valid_d(decode_io_dec_debug_valid_d), + .io_dec_tlu_flush_extint(decode_io_dec_tlu_flush_extint), + .io_dec_tlu_force_halt(decode_io_dec_tlu_force_halt), + .io_dec_i0_inst_wb(decode_io_dec_i0_inst_wb), + .io_dec_i0_pc_wb(decode_io_dec_i0_pc_wb), + .io_dec_i0_trigger_match_d(decode_io_dec_i0_trigger_match_d), + .io_dec_tlu_wr_pause_r(decode_io_dec_tlu_wr_pause_r), + .io_dec_tlu_pipelining_disable(decode_io_dec_tlu_pipelining_disable), + .io_lsu_trigger_match_m(decode_io_lsu_trigger_match_m), + .io_lsu_pmu_misaligned_m(decode_io_lsu_pmu_misaligned_m), + .io_dec_tlu_debug_stall(decode_io_dec_tlu_debug_stall), + .io_dec_tlu_flush_leak_one_r(decode_io_dec_tlu_flush_leak_one_r), + .io_dec_debug_fence_d(decode_io_dec_debug_fence_d), + .io_dec_i0_icaf_d(decode_io_dec_i0_icaf_d), + .io_dec_i0_icaf_second_d(decode_io_dec_i0_icaf_second_d), + .io_dec_i0_icaf_type_d(decode_io_dec_i0_icaf_type_d), + .io_dec_i0_dbecc_d(decode_io_dec_i0_dbecc_d), + .io_dec_i0_brp_valid(decode_io_dec_i0_brp_valid), + .io_dec_i0_brp_bits_toffset(decode_io_dec_i0_brp_bits_toffset), + .io_dec_i0_brp_bits_hist(decode_io_dec_i0_brp_bits_hist), + .io_dec_i0_brp_bits_br_error(decode_io_dec_i0_brp_bits_br_error), + .io_dec_i0_brp_bits_br_start_error(decode_io_dec_i0_brp_bits_br_start_error), + .io_dec_i0_brp_bits_prett(decode_io_dec_i0_brp_bits_prett), + .io_dec_i0_brp_bits_way(decode_io_dec_i0_brp_bits_way), + .io_dec_i0_brp_bits_ret(decode_io_dec_i0_brp_bits_ret), + .io_dec_i0_bp_index(decode_io_dec_i0_bp_index), + .io_dec_i0_bp_fghr(decode_io_dec_i0_bp_fghr), + .io_dec_i0_bp_btag(decode_io_dec_i0_bp_btag), + .io_lsu_idle_any(decode_io_lsu_idle_any), + .io_lsu_load_stall_any(decode_io_lsu_load_stall_any), + .io_lsu_store_stall_any(decode_io_lsu_store_stall_any), + .io_exu_div_wren(decode_io_exu_div_wren), + .io_dec_tlu_i0_kill_writeb_wb(decode_io_dec_tlu_i0_kill_writeb_wb), + .io_dec_tlu_flush_lower_wb(decode_io_dec_tlu_flush_lower_wb), + .io_dec_tlu_i0_kill_writeb_r(decode_io_dec_tlu_i0_kill_writeb_r), + .io_dec_tlu_flush_lower_r(decode_io_dec_tlu_flush_lower_r), + .io_dec_tlu_flush_pause_r(decode_io_dec_tlu_flush_pause_r), + .io_dec_tlu_presync_d(decode_io_dec_tlu_presync_d), + .io_dec_tlu_postsync_d(decode_io_dec_tlu_postsync_d), + .io_dec_i0_pc4_d(decode_io_dec_i0_pc4_d), + .io_dec_csr_rddata_d(decode_io_dec_csr_rddata_d), + .io_dec_csr_legal_d(decode_io_dec_csr_legal_d), + .io_lsu_result_m(decode_io_lsu_result_m), + .io_lsu_result_corr_r(decode_io_lsu_result_corr_r), + .io_exu_flush_final(decode_io_exu_flush_final), + .io_dec_i0_instr_d(decode_io_dec_i0_instr_d), + .io_dec_ib0_valid_d(decode_io_dec_ib0_valid_d), + .io_active_clk(decode_io_active_clk), + .io_free_l2clk(decode_io_free_l2clk), + .io_clk_override(decode_io_clk_override), + .io_dec_i0_rs1_d(decode_io_dec_i0_rs1_d), + .io_dec_i0_rs2_d(decode_io_dec_i0_rs2_d), + .io_dec_i0_waddr_r(decode_io_dec_i0_waddr_r), + .io_dec_i0_wen_r(decode_io_dec_i0_wen_r), + .io_dec_i0_wdata_r(decode_io_dec_i0_wdata_r), + .io_lsu_p_valid(decode_io_lsu_p_valid), + .io_lsu_p_bits_fast_int(decode_io_lsu_p_bits_fast_int), + .io_lsu_p_bits_stack(decode_io_lsu_p_bits_stack), + .io_lsu_p_bits_by(decode_io_lsu_p_bits_by), + .io_lsu_p_bits_half(decode_io_lsu_p_bits_half), + .io_lsu_p_bits_word(decode_io_lsu_p_bits_word), + .io_lsu_p_bits_load(decode_io_lsu_p_bits_load), + .io_lsu_p_bits_store(decode_io_lsu_p_bits_store), + .io_lsu_p_bits_unsign(decode_io_lsu_p_bits_unsign), + .io_lsu_p_bits_store_data_bypass_d(decode_io_lsu_p_bits_store_data_bypass_d), + .io_lsu_p_bits_load_ldst_bypass_d(decode_io_lsu_p_bits_load_ldst_bypass_d), + .io_div_waddr_wb(decode_io_div_waddr_wb), + .io_dec_lsu_valid_raw_d(decode_io_dec_lsu_valid_raw_d), + .io_dec_lsu_offset_d(decode_io_dec_lsu_offset_d), + .io_dec_csr_wen_unq_d(decode_io_dec_csr_wen_unq_d), + .io_dec_csr_any_unq_d(decode_io_dec_csr_any_unq_d), + .io_dec_csr_rdaddr_d(decode_io_dec_csr_rdaddr_d), + .io_dec_csr_wen_r(decode_io_dec_csr_wen_r), + .io_dec_csr_wraddr_r(decode_io_dec_csr_wraddr_r), + .io_dec_csr_wrdata_r(decode_io_dec_csr_wrdata_r), + .io_dec_csr_stall_int_ff(decode_io_dec_csr_stall_int_ff), + .io_dec_tlu_i0_valid_r(decode_io_dec_tlu_i0_valid_r), + .io_dec_tlu_packet_r_legal(decode_io_dec_tlu_packet_r_legal), + .io_dec_tlu_packet_r_icaf(decode_io_dec_tlu_packet_r_icaf), + .io_dec_tlu_packet_r_icaf_second(decode_io_dec_tlu_packet_r_icaf_second), + .io_dec_tlu_packet_r_icaf_type(decode_io_dec_tlu_packet_r_icaf_type), + .io_dec_tlu_packet_r_fence_i(decode_io_dec_tlu_packet_r_fence_i), + .io_dec_tlu_packet_r_i0trigger(decode_io_dec_tlu_packet_r_i0trigger), + .io_dec_tlu_packet_r_pmu_i0_itype(decode_io_dec_tlu_packet_r_pmu_i0_itype), + .io_dec_tlu_packet_r_pmu_i0_br_unpred(decode_io_dec_tlu_packet_r_pmu_i0_br_unpred), + .io_dec_tlu_packet_r_pmu_divide(decode_io_dec_tlu_packet_r_pmu_divide), + .io_dec_tlu_packet_r_pmu_lsu_misaligned(decode_io_dec_tlu_packet_r_pmu_lsu_misaligned), + .io_dec_tlu_i0_pc_r(decode_io_dec_tlu_i0_pc_r), + .io_dec_illegal_inst(decode_io_dec_illegal_inst), + .io_dec_pmu_instr_decoded(decode_io_dec_pmu_instr_decoded), + .io_dec_pmu_decode_stall(decode_io_dec_pmu_decode_stall), + .io_dec_pmu_presync_stall(decode_io_dec_pmu_presync_stall), + .io_dec_pmu_postsync_stall(decode_io_dec_pmu_postsync_stall), + .io_dec_nonblock_load_wen(decode_io_dec_nonblock_load_wen), + .io_dec_nonblock_load_waddr(decode_io_dec_nonblock_load_waddr), + .io_dec_pause_state(decode_io_dec_pause_state), + .io_dec_pause_state_cg(decode_io_dec_pause_state_cg), + .io_dec_div_active(decode_io_dec_div_active) + ); + dec_gpr_ctl gpr ( // @[dec.scala 130:19] + .clock(gpr_clock), + .reset(gpr_reset), + .io_raddr0(gpr_io_raddr0), + .io_raddr1(gpr_io_raddr1), + .io_wen0(gpr_io_wen0), + .io_waddr0(gpr_io_waddr0), + .io_wd0(gpr_io_wd0), + .io_wen1(gpr_io_wen1), + .io_waddr1(gpr_io_waddr1), + .io_wd1(gpr_io_wd1), + .io_wen2(gpr_io_wen2), + .io_waddr2(gpr_io_waddr2), + .io_wd2(gpr_io_wd2), + .io_gpr_exu_gpr_i0_rs1_d(gpr_io_gpr_exu_gpr_i0_rs1_d), + .io_gpr_exu_gpr_i0_rs2_d(gpr_io_gpr_exu_gpr_i0_rs2_d) + ); + dec_tlu_ctl tlu ( // @[dec.scala 131:19] + .clock(tlu_clock), + .reset(tlu_reset), + .io_tlu_exu_dec_tlu_meihap(tlu_io_tlu_exu_dec_tlu_meihap), + .io_tlu_exu_dec_tlu_flush_lower_r(tlu_io_tlu_exu_dec_tlu_flush_lower_r), + .io_tlu_exu_dec_tlu_flush_path_r(tlu_io_tlu_exu_dec_tlu_flush_path_r), + .io_tlu_exu_exu_i0_br_hist_r(tlu_io_tlu_exu_exu_i0_br_hist_r), + .io_tlu_exu_exu_i0_br_error_r(tlu_io_tlu_exu_exu_i0_br_error_r), + .io_tlu_exu_exu_i0_br_start_error_r(tlu_io_tlu_exu_exu_i0_br_start_error_r), + .io_tlu_exu_exu_i0_br_valid_r(tlu_io_tlu_exu_exu_i0_br_valid_r), + .io_tlu_exu_exu_i0_br_mp_r(tlu_io_tlu_exu_exu_i0_br_mp_r), + .io_tlu_exu_exu_i0_br_middle_r(tlu_io_tlu_exu_exu_i0_br_middle_r), + .io_tlu_exu_exu_pmu_i0_br_misp(tlu_io_tlu_exu_exu_pmu_i0_br_misp), + .io_tlu_exu_exu_pmu_i0_br_ataken(tlu_io_tlu_exu_exu_pmu_i0_br_ataken), + .io_tlu_exu_exu_pmu_i0_pc4(tlu_io_tlu_exu_exu_pmu_i0_pc4), + .io_tlu_exu_exu_npc_r(tlu_io_tlu_exu_exu_npc_r), + .io_tlu_dma_dma_pmu_dccm_read(tlu_io_tlu_dma_dma_pmu_dccm_read), + .io_tlu_dma_dma_pmu_dccm_write(tlu_io_tlu_dma_dma_pmu_dccm_write), + .io_tlu_dma_dma_pmu_any_read(tlu_io_tlu_dma_dma_pmu_any_read), + .io_tlu_dma_dma_pmu_any_write(tlu_io_tlu_dma_dma_pmu_any_write), + .io_tlu_dma_dec_tlu_dma_qos_prty(tlu_io_tlu_dma_dec_tlu_dma_qos_prty), + .io_tlu_dma_dma_dccm_stall_any(tlu_io_tlu_dma_dma_dccm_stall_any), + .io_tlu_dma_dma_iccm_stall_any(tlu_io_tlu_dma_dma_iccm_stall_any), + .io_free_clk(tlu_io_free_clk), + .io_free_l2clk(tlu_io_free_l2clk), + .io_rst_vec(tlu_io_rst_vec), + .io_nmi_int(tlu_io_nmi_int), + .io_nmi_vec(tlu_io_nmi_vec), + .io_i_cpu_halt_req(tlu_io_i_cpu_halt_req), + .io_i_cpu_run_req(tlu_io_i_cpu_run_req), + .io_lsu_fastint_stall_any(tlu_io_lsu_fastint_stall_any), + .io_lsu_idle_any(tlu_io_lsu_idle_any), + .io_dec_pmu_instr_decoded(tlu_io_dec_pmu_instr_decoded), + .io_dec_pmu_decode_stall(tlu_io_dec_pmu_decode_stall), + .io_dec_pmu_presync_stall(tlu_io_dec_pmu_presync_stall), + .io_dec_pmu_postsync_stall(tlu_io_dec_pmu_postsync_stall), + .io_lsu_store_stall_any(tlu_io_lsu_store_stall_any), + .io_lsu_fir_addr(tlu_io_lsu_fir_addr), + .io_lsu_fir_error(tlu_io_lsu_fir_error), + .io_iccm_dma_sb_error(tlu_io_iccm_dma_sb_error), + .io_lsu_error_pkt_r_valid(tlu_io_lsu_error_pkt_r_valid), + .io_lsu_error_pkt_r_bits_single_ecc_error(tlu_io_lsu_error_pkt_r_bits_single_ecc_error), + .io_lsu_error_pkt_r_bits_inst_type(tlu_io_lsu_error_pkt_r_bits_inst_type), + .io_lsu_error_pkt_r_bits_exc_type(tlu_io_lsu_error_pkt_r_bits_exc_type), + .io_lsu_error_pkt_r_bits_mscause(tlu_io_lsu_error_pkt_r_bits_mscause), + .io_lsu_error_pkt_r_bits_addr(tlu_io_lsu_error_pkt_r_bits_addr), + .io_lsu_single_ecc_error_incr(tlu_io_lsu_single_ecc_error_incr), + .io_dec_pause_state(tlu_io_dec_pause_state), + .io_dec_csr_wen_unq_d(tlu_io_dec_csr_wen_unq_d), + .io_dec_csr_any_unq_d(tlu_io_dec_csr_any_unq_d), + .io_dec_csr_rdaddr_d(tlu_io_dec_csr_rdaddr_d), + .io_dec_csr_wen_r(tlu_io_dec_csr_wen_r), + .io_dec_csr_wraddr_r(tlu_io_dec_csr_wraddr_r), + .io_dec_csr_wrdata_r(tlu_io_dec_csr_wrdata_r), + .io_dec_csr_stall_int_ff(tlu_io_dec_csr_stall_int_ff), + .io_dec_tlu_i0_valid_r(tlu_io_dec_tlu_i0_valid_r), + .io_dec_tlu_i0_pc_r(tlu_io_dec_tlu_i0_pc_r), + .io_dec_tlu_packet_r_legal(tlu_io_dec_tlu_packet_r_legal), + .io_dec_tlu_packet_r_icaf(tlu_io_dec_tlu_packet_r_icaf), + .io_dec_tlu_packet_r_icaf_second(tlu_io_dec_tlu_packet_r_icaf_second), + .io_dec_tlu_packet_r_icaf_type(tlu_io_dec_tlu_packet_r_icaf_type), + .io_dec_tlu_packet_r_fence_i(tlu_io_dec_tlu_packet_r_fence_i), + .io_dec_tlu_packet_r_i0trigger(tlu_io_dec_tlu_packet_r_i0trigger), + .io_dec_tlu_packet_r_pmu_i0_itype(tlu_io_dec_tlu_packet_r_pmu_i0_itype), + .io_dec_tlu_packet_r_pmu_i0_br_unpred(tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred), + .io_dec_tlu_packet_r_pmu_divide(tlu_io_dec_tlu_packet_r_pmu_divide), + .io_dec_tlu_packet_r_pmu_lsu_misaligned(tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned), + .io_dec_illegal_inst(tlu_io_dec_illegal_inst), + .io_dec_i0_decode_d(tlu_io_dec_i0_decode_d), + .io_exu_i0_br_way_r(tlu_io_exu_i0_br_way_r), + .io_dec_tlu_core_empty(tlu_io_dec_tlu_core_empty), + .io_dec_dbg_cmd_done(tlu_io_dec_dbg_cmd_done), + .io_dec_dbg_cmd_fail(tlu_io_dec_dbg_cmd_fail), + .io_dec_tlu_dbg_halted(tlu_io_dec_tlu_dbg_halted), + .io_dec_tlu_debug_mode(tlu_io_dec_tlu_debug_mode), + .io_dec_tlu_resume_ack(tlu_io_dec_tlu_resume_ack), + .io_dec_tlu_debug_stall(tlu_io_dec_tlu_debug_stall), + .io_dec_tlu_mpc_halted_only(tlu_io_dec_tlu_mpc_halted_only), + .io_dec_tlu_flush_extint(tlu_io_dec_tlu_flush_extint), + .io_dbg_halt_req(tlu_io_dbg_halt_req), + .io_dbg_resume_req(tlu_io_dbg_resume_req), + .io_dec_div_active(tlu_io_dec_div_active), + .io_trigger_pkt_any_0_select(tlu_io_trigger_pkt_any_0_select), + .io_trigger_pkt_any_0_match_pkt(tlu_io_trigger_pkt_any_0_match_pkt), + .io_trigger_pkt_any_0_store(tlu_io_trigger_pkt_any_0_store), + .io_trigger_pkt_any_0_load(tlu_io_trigger_pkt_any_0_load), + .io_trigger_pkt_any_0_execute(tlu_io_trigger_pkt_any_0_execute), + .io_trigger_pkt_any_0_m(tlu_io_trigger_pkt_any_0_m), + .io_trigger_pkt_any_0_tdata2(tlu_io_trigger_pkt_any_0_tdata2), + .io_trigger_pkt_any_1_select(tlu_io_trigger_pkt_any_1_select), + .io_trigger_pkt_any_1_match_pkt(tlu_io_trigger_pkt_any_1_match_pkt), + .io_trigger_pkt_any_1_store(tlu_io_trigger_pkt_any_1_store), + .io_trigger_pkt_any_1_load(tlu_io_trigger_pkt_any_1_load), + .io_trigger_pkt_any_1_execute(tlu_io_trigger_pkt_any_1_execute), + .io_trigger_pkt_any_1_m(tlu_io_trigger_pkt_any_1_m), + .io_trigger_pkt_any_1_tdata2(tlu_io_trigger_pkt_any_1_tdata2), + .io_trigger_pkt_any_2_select(tlu_io_trigger_pkt_any_2_select), + .io_trigger_pkt_any_2_match_pkt(tlu_io_trigger_pkt_any_2_match_pkt), + .io_trigger_pkt_any_2_store(tlu_io_trigger_pkt_any_2_store), + .io_trigger_pkt_any_2_load(tlu_io_trigger_pkt_any_2_load), + .io_trigger_pkt_any_2_execute(tlu_io_trigger_pkt_any_2_execute), + .io_trigger_pkt_any_2_m(tlu_io_trigger_pkt_any_2_m), + .io_trigger_pkt_any_2_tdata2(tlu_io_trigger_pkt_any_2_tdata2), + .io_trigger_pkt_any_3_select(tlu_io_trigger_pkt_any_3_select), + .io_trigger_pkt_any_3_match_pkt(tlu_io_trigger_pkt_any_3_match_pkt), + .io_trigger_pkt_any_3_store(tlu_io_trigger_pkt_any_3_store), + .io_trigger_pkt_any_3_load(tlu_io_trigger_pkt_any_3_load), + .io_trigger_pkt_any_3_execute(tlu_io_trigger_pkt_any_3_execute), + .io_trigger_pkt_any_3_m(tlu_io_trigger_pkt_any_3_m), + .io_trigger_pkt_any_3_tdata2(tlu_io_trigger_pkt_any_3_tdata2), + .io_timer_int(tlu_io_timer_int), + .io_soft_int(tlu_io_soft_int), + .io_o_cpu_halt_status(tlu_io_o_cpu_halt_status), + .io_o_cpu_halt_ack(tlu_io_o_cpu_halt_ack), + .io_o_cpu_run_ack(tlu_io_o_cpu_run_ack), + .io_o_debug_mode_status(tlu_io_o_debug_mode_status), + .io_core_id(tlu_io_core_id), + .io_mpc_debug_halt_req(tlu_io_mpc_debug_halt_req), + .io_mpc_debug_run_req(tlu_io_mpc_debug_run_req), + .io_mpc_reset_run_req(tlu_io_mpc_reset_run_req), + .io_mpc_debug_halt_ack(tlu_io_mpc_debug_halt_ack), + .io_mpc_debug_run_ack(tlu_io_mpc_debug_run_ack), + .io_debug_brkpt_status(tlu_io_debug_brkpt_status), + .io_dec_csr_rddata_d(tlu_io_dec_csr_rddata_d), + .io_dec_csr_legal_d(tlu_io_dec_csr_legal_d), + .io_dec_tlu_i0_kill_writeb_wb(tlu_io_dec_tlu_i0_kill_writeb_wb), + .io_dec_tlu_i0_kill_writeb_r(tlu_io_dec_tlu_i0_kill_writeb_r), + .io_dec_tlu_wr_pause_r(tlu_io_dec_tlu_wr_pause_r), + .io_dec_tlu_flush_pause_r(tlu_io_dec_tlu_flush_pause_r), + .io_dec_tlu_presync_d(tlu_io_dec_tlu_presync_d), + .io_dec_tlu_postsync_d(tlu_io_dec_tlu_postsync_d), + .io_dec_tlu_perfcnt0(tlu_io_dec_tlu_perfcnt0), + .io_dec_tlu_perfcnt1(tlu_io_dec_tlu_perfcnt1), + .io_dec_tlu_perfcnt2(tlu_io_dec_tlu_perfcnt2), + .io_dec_tlu_perfcnt3(tlu_io_dec_tlu_perfcnt3), + .io_dec_tlu_i0_exc_valid_wb1(tlu_io_dec_tlu_i0_exc_valid_wb1), + .io_dec_tlu_i0_valid_wb1(tlu_io_dec_tlu_i0_valid_wb1), + .io_dec_tlu_int_valid_wb1(tlu_io_dec_tlu_int_valid_wb1), + .io_dec_tlu_exc_cause_wb1(tlu_io_dec_tlu_exc_cause_wb1), + .io_dec_tlu_mtval_wb1(tlu_io_dec_tlu_mtval_wb1), + .io_dec_tlu_pipelining_disable(tlu_io_dec_tlu_pipelining_disable), + .io_dec_tlu_trace_disable(tlu_io_dec_tlu_trace_disable), + .io_dec_tlu_misc_clk_override(tlu_io_dec_tlu_misc_clk_override), + .io_dec_tlu_dec_clk_override(tlu_io_dec_tlu_dec_clk_override), + .io_dec_tlu_ifu_clk_override(tlu_io_dec_tlu_ifu_clk_override), + .io_dec_tlu_lsu_clk_override(tlu_io_dec_tlu_lsu_clk_override), + .io_dec_tlu_bus_clk_override(tlu_io_dec_tlu_bus_clk_override), + .io_dec_tlu_pic_clk_override(tlu_io_dec_tlu_pic_clk_override), + .io_dec_tlu_dccm_clk_override(tlu_io_dec_tlu_dccm_clk_override), + .io_dec_tlu_icm_clk_override(tlu_io_dec_tlu_icm_clk_override), + .io_dec_tlu_flush_lower_wb(tlu_io_dec_tlu_flush_lower_wb), + .io_ifu_pmu_instr_aligned(tlu_io_ifu_pmu_instr_aligned), + .io_tlu_bp_dec_tlu_br0_r_pkt_valid(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_valid), + .io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist), + .io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error), + .io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error), + .io_tlu_bp_dec_tlu_br0_r_pkt_bits_way(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_way), + .io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle), + .io_tlu_bp_dec_tlu_flush_leak_one_wb(tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb), + .io_tlu_bp_dec_tlu_bpred_disable(tlu_io_tlu_bp_dec_tlu_bpred_disable), + .io_tlu_ifc_dec_tlu_flush_noredir_wb(tlu_io_tlu_ifc_dec_tlu_flush_noredir_wb), + .io_tlu_ifc_dec_tlu_mrac_ff(tlu_io_tlu_ifc_dec_tlu_mrac_ff), + .io_tlu_ifc_ifu_pmu_fetch_stall(tlu_io_tlu_ifc_ifu_pmu_fetch_stall), + .io_tlu_mem_dec_tlu_flush_err_wb(tlu_io_tlu_mem_dec_tlu_flush_err_wb), + .io_tlu_mem_dec_tlu_i0_commit_cmt(tlu_io_tlu_mem_dec_tlu_i0_commit_cmt), + .io_tlu_mem_dec_tlu_force_halt(tlu_io_tlu_mem_dec_tlu_force_halt), + .io_tlu_mem_dec_tlu_fence_i_wb(tlu_io_tlu_mem_dec_tlu_fence_i_wb), + .io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata(tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata), + .io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics(tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics), + .io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid(tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid), + .io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid(tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid), + .io_tlu_mem_dec_tlu_core_ecc_disable(tlu_io_tlu_mem_dec_tlu_core_ecc_disable), + .io_tlu_mem_ifu_pmu_ic_miss(tlu_io_tlu_mem_ifu_pmu_ic_miss), + .io_tlu_mem_ifu_pmu_ic_hit(tlu_io_tlu_mem_ifu_pmu_ic_hit), + .io_tlu_mem_ifu_pmu_bus_error(tlu_io_tlu_mem_ifu_pmu_bus_error), + .io_tlu_mem_ifu_pmu_bus_busy(tlu_io_tlu_mem_ifu_pmu_bus_busy), + .io_tlu_mem_ifu_pmu_bus_trxn(tlu_io_tlu_mem_ifu_pmu_bus_trxn), + .io_tlu_mem_ifu_ic_error_start(tlu_io_tlu_mem_ifu_ic_error_start), + .io_tlu_mem_ifu_iccm_rd_ecc_single_err(tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err), + .io_tlu_mem_ifu_ic_debug_rd_data(tlu_io_tlu_mem_ifu_ic_debug_rd_data), + .io_tlu_mem_ifu_ic_debug_rd_data_valid(tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid), + .io_tlu_mem_ifu_miss_state_idle(tlu_io_tlu_mem_ifu_miss_state_idle), + .io_tlu_busbuff_lsu_pmu_bus_trxn(tlu_io_tlu_busbuff_lsu_pmu_bus_trxn), + .io_tlu_busbuff_lsu_pmu_bus_misaligned(tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned), + .io_tlu_busbuff_lsu_pmu_bus_error(tlu_io_tlu_busbuff_lsu_pmu_bus_error), + .io_tlu_busbuff_lsu_pmu_bus_busy(tlu_io_tlu_busbuff_lsu_pmu_bus_busy), + .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), + .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), + .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), + .io_tlu_busbuff_lsu_imprecise_error_load_any(tlu_io_tlu_busbuff_lsu_imprecise_error_load_any), + .io_tlu_busbuff_lsu_imprecise_error_store_any(tlu_io_tlu_busbuff_lsu_imprecise_error_store_any), + .io_tlu_busbuff_lsu_imprecise_error_addr_any(tlu_io_tlu_busbuff_lsu_imprecise_error_addr_any), + .io_lsu_tlu_lsu_pmu_load_external_m(tlu_io_lsu_tlu_lsu_pmu_load_external_m), + .io_lsu_tlu_lsu_pmu_store_external_m(tlu_io_lsu_tlu_lsu_pmu_store_external_m), + .io_dec_pic_pic_claimid(tlu_io_dec_pic_pic_claimid), + .io_dec_pic_pic_pl(tlu_io_dec_pic_pic_pl), + .io_dec_pic_mhwakeup(tlu_io_dec_pic_mhwakeup), + .io_dec_pic_dec_tlu_meicurpl(tlu_io_dec_pic_dec_tlu_meicurpl), + .io_dec_pic_dec_tlu_meipt(tlu_io_dec_pic_dec_tlu_meipt), + .io_dec_pic_mexintpend(tlu_io_dec_pic_mexintpend) + ); + dec_trigger dec_trigger ( // @[dec.scala 132:27] + .io_trigger_pkt_any_0_select(dec_trigger_io_trigger_pkt_any_0_select), + .io_trigger_pkt_any_0_match_pkt(dec_trigger_io_trigger_pkt_any_0_match_pkt), + .io_trigger_pkt_any_0_execute(dec_trigger_io_trigger_pkt_any_0_execute), + .io_trigger_pkt_any_0_m(dec_trigger_io_trigger_pkt_any_0_m), + .io_trigger_pkt_any_0_tdata2(dec_trigger_io_trigger_pkt_any_0_tdata2), + .io_trigger_pkt_any_1_select(dec_trigger_io_trigger_pkt_any_1_select), + .io_trigger_pkt_any_1_match_pkt(dec_trigger_io_trigger_pkt_any_1_match_pkt), + .io_trigger_pkt_any_1_execute(dec_trigger_io_trigger_pkt_any_1_execute), + .io_trigger_pkt_any_1_m(dec_trigger_io_trigger_pkt_any_1_m), + .io_trigger_pkt_any_1_tdata2(dec_trigger_io_trigger_pkt_any_1_tdata2), + .io_trigger_pkt_any_2_select(dec_trigger_io_trigger_pkt_any_2_select), + .io_trigger_pkt_any_2_match_pkt(dec_trigger_io_trigger_pkt_any_2_match_pkt), + .io_trigger_pkt_any_2_execute(dec_trigger_io_trigger_pkt_any_2_execute), + .io_trigger_pkt_any_2_m(dec_trigger_io_trigger_pkt_any_2_m), + .io_trigger_pkt_any_2_tdata2(dec_trigger_io_trigger_pkt_any_2_tdata2), + .io_trigger_pkt_any_3_select(dec_trigger_io_trigger_pkt_any_3_select), + .io_trigger_pkt_any_3_match_pkt(dec_trigger_io_trigger_pkt_any_3_match_pkt), + .io_trigger_pkt_any_3_execute(dec_trigger_io_trigger_pkt_any_3_execute), + .io_trigger_pkt_any_3_m(dec_trigger_io_trigger_pkt_any_3_m), + .io_trigger_pkt_any_3_tdata2(dec_trigger_io_trigger_pkt_any_3_tdata2), + .io_dec_i0_pc_d(dec_trigger_io_dec_i0_pc_d), + .io_dec_i0_trigger_match_d(dec_trigger_io_dec_i0_trigger_match_d) + ); + assign io_dec_pause_state_cg = decode_io_dec_pause_state_cg; // @[dec.scala 202:48] + assign io_dec_tlu_core_empty = tlu_io_dec_tlu_core_empty; // @[dec.scala 304:36] + assign io_dec_fa_error_index = 9'h0; // @[dec.scala 204:48] + assign io_o_cpu_halt_status = tlu_io_o_cpu_halt_status; // @[dec.scala 279:29] + assign io_o_cpu_halt_ack = tlu_io_o_cpu_halt_ack; // @[dec.scala 280:29] + assign io_o_cpu_run_ack = tlu_io_o_cpu_run_ack; // @[dec.scala 281:29] + assign io_o_debug_mode_status = tlu_io_o_debug_mode_status; // @[dec.scala 282:29] + assign io_mpc_debug_halt_ack = tlu_io_mpc_debug_halt_ack; // @[dec.scala 283:29] + assign io_mpc_debug_run_ack = tlu_io_mpc_debug_run_ack; // @[dec.scala 284:29] + assign io_debug_brkpt_status = tlu_io_debug_brkpt_status; // @[dec.scala 285:29] + assign io_dec_tlu_dbg_halted = tlu_io_dec_tlu_dbg_halted; // @[dec.scala 274:28] + assign io_dec_tlu_debug_mode = tlu_io_dec_tlu_debug_mode; // @[dec.scala 275:28] + assign io_dec_tlu_resume_ack = tlu_io_dec_tlu_resume_ack; // @[dec.scala 276:28] + assign io_dec_tlu_mpc_halted_only = tlu_io_dec_tlu_mpc_halted_only; // @[dec.scala 277:51] + assign io_dec_dbg_rddata = decode_io_dec_i0_wdata_r; // @[dec.scala 320:21] + assign io_dec_csr_rddata_d = tlu_io_dec_csr_rddata_d; // @[dec.scala 305:36] + assign io_dec_dbg_cmd_done = tlu_io_dec_dbg_cmd_done; // @[dec.scala 272:28] + assign io_dec_dbg_cmd_fail = tlu_io_dec_dbg_cmd_fail; // @[dec.scala 273:28] + assign io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[dec.scala 278:29] + assign io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 278:29] + assign io_trigger_pkt_any_0_store = tlu_io_trigger_pkt_any_0_store; // @[dec.scala 278:29] + assign io_trigger_pkt_any_0_load = tlu_io_trigger_pkt_any_0_load; // @[dec.scala 278:29] + assign io_trigger_pkt_any_0_execute = tlu_io_trigger_pkt_any_0_execute; // @[dec.scala 278:29] + assign io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[dec.scala 278:29] + assign io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 278:29] + assign io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[dec.scala 278:29] + assign io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 278:29] + assign io_trigger_pkt_any_1_store = tlu_io_trigger_pkt_any_1_store; // @[dec.scala 278:29] + assign io_trigger_pkt_any_1_load = tlu_io_trigger_pkt_any_1_load; // @[dec.scala 278:29] + assign io_trigger_pkt_any_1_execute = tlu_io_trigger_pkt_any_1_execute; // @[dec.scala 278:29] + assign io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[dec.scala 278:29] + assign io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 278:29] + assign io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[dec.scala 278:29] + assign io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 278:29] + assign io_trigger_pkt_any_2_store = tlu_io_trigger_pkt_any_2_store; // @[dec.scala 278:29] + assign io_trigger_pkt_any_2_load = tlu_io_trigger_pkt_any_2_load; // @[dec.scala 278:29] + assign io_trigger_pkt_any_2_execute = tlu_io_trigger_pkt_any_2_execute; // @[dec.scala 278:29] + assign io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[dec.scala 278:29] + assign io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 278:29] + assign io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[dec.scala 278:29] + assign io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 278:29] + assign io_trigger_pkt_any_3_store = tlu_io_trigger_pkt_any_3_store; // @[dec.scala 278:29] + assign io_trigger_pkt_any_3_load = tlu_io_trigger_pkt_any_3_load; // @[dec.scala 278:29] + assign io_trigger_pkt_any_3_execute = tlu_io_trigger_pkt_any_3_execute; // @[dec.scala 278:29] + assign io_trigger_pkt_any_3_m = tlu_io_trigger_pkt_any_3_m; // @[dec.scala 278:29] + assign io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 278:29] + assign io_lsu_p_valid = decode_io_lsu_p_valid; // @[dec.scala 199:48] + assign io_lsu_p_bits_fast_int = decode_io_lsu_p_bits_fast_int; // @[dec.scala 199:48] + assign io_lsu_p_bits_stack = decode_io_lsu_p_bits_stack; // @[dec.scala 199:48] + assign io_lsu_p_bits_by = decode_io_lsu_p_bits_by; // @[dec.scala 199:48] + assign io_lsu_p_bits_half = decode_io_lsu_p_bits_half; // @[dec.scala 199:48] + assign io_lsu_p_bits_word = decode_io_lsu_p_bits_word; // @[dec.scala 199:48] + assign io_lsu_p_bits_dword = 1'h0; // @[dec.scala 199:48] + assign io_lsu_p_bits_load = decode_io_lsu_p_bits_load; // @[dec.scala 199:48] + assign io_lsu_p_bits_store = decode_io_lsu_p_bits_store; // @[dec.scala 199:48] + assign io_lsu_p_bits_unsign = decode_io_lsu_p_bits_unsign; // @[dec.scala 199:48] + assign io_lsu_p_bits_dma = 1'h0; // @[dec.scala 199:48] + assign io_lsu_p_bits_store_data_bypass_d = decode_io_lsu_p_bits_store_data_bypass_d; // @[dec.scala 199:48] + assign io_lsu_p_bits_load_ldst_bypass_d = decode_io_lsu_p_bits_load_ldst_bypass_d; // @[dec.scala 199:48] + assign io_lsu_p_bits_store_data_bypass_m = 1'h0; // @[dec.scala 199:48] + assign io_dec_lsu_offset_d = decode_io_dec_lsu_offset_d; // @[dec.scala 201:48] + assign io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 286:34] + assign io_dec_tlu_perfcnt0 = tlu_io_dec_tlu_perfcnt0; // @[dec.scala 287:29] + assign io_dec_tlu_perfcnt1 = tlu_io_dec_tlu_perfcnt1; // @[dec.scala 288:29] + assign io_dec_tlu_perfcnt2 = tlu_io_dec_tlu_perfcnt2; // @[dec.scala 289:29] + assign io_dec_tlu_perfcnt3 = tlu_io_dec_tlu_perfcnt3; // @[dec.scala 290:29] + assign io_dec_tlu_flush_lower_wb = tlu_io_dec_tlu_flush_lower_wb; // @[dec.scala 306:36] + assign io_dec_lsu_valid_raw_d = decode_io_dec_lsu_valid_raw_d; // @[dec.scala 200:48] + assign io_trace_rv_trace_pkt_rv_i_valid_ip = _T_1 | tlu_io_dec_tlu_i0_exc_valid_wb1; // @[dec.scala 312:39] + assign io_trace_rv_trace_pkt_rv_i_insn_ip = decode_io_dec_i0_inst_wb; // @[dec.scala 310:38] + assign io_trace_rv_trace_pkt_rv_i_address_ip = {decode_io_dec_i0_pc_wb,1'h0}; // @[dec.scala 311:41] + assign io_trace_rv_trace_pkt_rv_i_exception_ip = tlu_io_dec_tlu_int_valid_wb1 | tlu_io_dec_tlu_i0_exc_valid_wb1; // @[dec.scala 313:43] + assign io_trace_rv_trace_pkt_rv_i_ecause_ip = tlu_io_dec_tlu_exc_cause_wb1; // @[dec.scala 314:40] + assign io_trace_rv_trace_pkt_rv_i_interrupt_ip = tlu_io_dec_tlu_int_valid_wb1; // @[dec.scala 315:43] + assign io_trace_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 316:38] + assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 296:35] + assign io_dec_tlu_ifu_clk_override = tlu_io_dec_tlu_ifu_clk_override; // @[dec.scala 297:36] + assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 298:36] + assign io_dec_tlu_bus_clk_override = tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 299:36] + assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 300:36] + assign io_dec_tlu_picio_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 303:36] + assign io_dec_tlu_dccm_clk_override = tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 301:36] + assign io_dec_tlu_icm_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 302:36] + assign io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d = decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 145:21] + assign io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = tlu_io_tlu_mem_dec_tlu_flush_err_wb; // @[dec.scala 220:18] + assign io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = tlu_io_tlu_mem_dec_tlu_i0_commit_cmt; // @[dec.scala 220:18] + assign io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 220:18] + assign io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = tlu_io_tlu_mem_dec_tlu_fence_i_wb; // @[dec.scala 220:18] + assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec.scala 220:18] + assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec.scala 220:18] + assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec.scala 220:18] + assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec.scala 220:18] + assign io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = tlu_io_tlu_mem_dec_tlu_core_ecc_disable; // @[dec.scala 220:18] + assign io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = tlu_io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec.scala 221:18] + assign io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = tlu_io_tlu_ifc_dec_tlu_mrac_ff; // @[dec.scala 221:18] + assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_valid; // @[dec.scala 222:18] + assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist; // @[dec.scala 222:18] + assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[dec.scala 222:18] + assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[dec.scala 222:18] + assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_way; // @[dec.scala 222:18] + assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle; // @[dec.scala 222:18] + assign io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 222:18] + assign io_ifu_dec_dec_bp_dec_tlu_bpred_disable = tlu_io_tlu_bp_dec_tlu_bpred_disable; // @[dec.scala 222:18] + assign io_dec_exu_dec_alu_dec_i0_alu_decode_d = decode_io_dec_alu_dec_i0_alu_decode_d; // @[dec.scala 148:20] + assign io_dec_exu_dec_alu_dec_csr_ren_d = decode_io_dec_alu_dec_csr_ren_d; // @[dec.scala 148:20] + assign io_dec_exu_dec_alu_dec_i0_br_immed_d = decode_io_dec_alu_dec_i0_br_immed_d; // @[dec.scala 148:20] + assign io_dec_exu_dec_div_div_p_valid = decode_io_dec_div_div_p_valid; // @[dec.scala 149:20] + assign io_dec_exu_dec_div_div_p_bits_unsign = decode_io_dec_div_div_p_bits_unsign; // @[dec.scala 149:20] + assign io_dec_exu_dec_div_div_p_bits_rem = decode_io_dec_div_div_p_bits_rem; // @[dec.scala 149:20] + assign io_dec_exu_dec_div_dec_div_cancel = decode_io_dec_div_dec_div_cancel; // @[dec.scala 149:20] + assign io_dec_exu_decode_exu_dec_data_en = decode_io_decode_exu_dec_data_en; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_ctl_en = decode_io_decode_exu_dec_ctl_en; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_clz = decode_io_decode_exu_i0_ap_clz; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_ctz = decode_io_decode_exu_i0_ap_ctz; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_pcnt = decode_io_decode_exu_i0_ap_pcnt; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_sext_b = decode_io_decode_exu_i0_ap_sext_b; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_sext_h = decode_io_decode_exu_i0_ap_sext_h; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_slo = decode_io_decode_exu_i0_ap_slo; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_sro = decode_io_decode_exu_i0_ap_sro; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_min = decode_io_decode_exu_i0_ap_min; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_max = decode_io_decode_exu_i0_ap_max; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_pack = decode_io_decode_exu_i0_ap_pack; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_packu = decode_io_decode_exu_i0_ap_packu; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_packh = decode_io_decode_exu_i0_ap_packh; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_rol = decode_io_decode_exu_i0_ap_rol; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_ror = decode_io_decode_exu_i0_ap_ror; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_grev = decode_io_decode_exu_i0_ap_grev; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_gorc = decode_io_decode_exu_i0_ap_gorc; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_zbb = decode_io_decode_exu_i0_ap_zbb; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_sbset = decode_io_decode_exu_i0_ap_sbset; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_sbclr = decode_io_decode_exu_i0_ap_sbclr; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_sbinv = decode_io_decode_exu_i0_ap_sbinv; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_sbext = decode_io_decode_exu_i0_ap_sbext; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_sh1add = decode_io_decode_exu_i0_ap_sh1add; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_sh2add = decode_io_decode_exu_i0_ap_sh2add; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_sh3add = decode_io_decode_exu_i0_ap_sh3add; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_zba = decode_io_decode_exu_i0_ap_zba; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_land = decode_io_decode_exu_i0_ap_land; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_lor = decode_io_decode_exu_i0_ap_lor; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_lxor = decode_io_decode_exu_i0_ap_lxor; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_sll = decode_io_decode_exu_i0_ap_sll; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_srl = decode_io_decode_exu_i0_ap_srl; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_sra = decode_io_decode_exu_i0_ap_sra; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_beq = decode_io_decode_exu_i0_ap_beq; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_bne = decode_io_decode_exu_i0_ap_bne; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_blt = decode_io_decode_exu_i0_ap_blt; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_bge = decode_io_decode_exu_i0_ap_bge; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_add = decode_io_decode_exu_i0_ap_add; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_sub = decode_io_decode_exu_i0_ap_sub; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_slt = decode_io_decode_exu_i0_ap_slt; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_unsign = decode_io_decode_exu_i0_ap_unsign; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_jal = decode_io_decode_exu_i0_ap_jal; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_predict_t = decode_io_decode_exu_i0_ap_predict_t; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_predict_nt = decode_io_decode_exu_i0_ap_predict_nt; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_csr_write = decode_io_decode_exu_i0_ap_csr_write; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_ap_csr_imm = decode_io_decode_exu_i0_ap_csr_imm; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = decode_io_decode_exu_dec_i0_predict_p_d_valid; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_misp = 1'h0; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_ataken = 1'h0; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_boffset = 1'h0; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = decode_io_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = decode_io_decode_exu_dec_i0_predict_p_d_bits_hist; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = decode_io_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = decode_io_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = decode_io_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = decode_io_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = decode_io_decode_exu_dec_i0_predict_p_d_bits_pja; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = decode_io_decode_exu_dec_i0_predict_p_d_bits_way; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = decode_io_decode_exu_dec_i0_predict_p_d_bits_pret; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = decode_io_decode_exu_dec_i0_predict_p_d_bits_prett; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_predict_fghr_d = decode_io_decode_exu_i0_predict_fghr_d; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_predict_index_d = decode_io_decode_exu_i0_predict_index_d; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_i0_predict_btag_d = decode_io_decode_exu_i0_predict_btag_d; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_rs1_en_d = decode_io_decode_exu_dec_i0_rs1_en_d; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_branch_d = decode_io_decode_exu_dec_i0_branch_d; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_rs2_en_d = decode_io_decode_exu_dec_i0_rs2_en_d; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_immed_d = decode_io_decode_exu_dec_i0_immed_d; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_result_r = decode_io_decode_exu_dec_i0_result_r; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_qual_lsu_d = decode_io_decode_exu_dec_qual_lsu_d; // @[dec.scala 147:23 dec.scala 203:48] + assign io_dec_exu_decode_exu_dec_i0_select_pc_d = decode_io_decode_exu_dec_i0_select_pc_d; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = decode_io_decode_exu_dec_i0_rs1_bypass_en_d; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = decode_io_decode_exu_dec_i0_rs2_bypass_en_d; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_valid = decode_io_decode_exu_mul_p_valid; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_bits_rs1_sign = decode_io_decode_exu_mul_p_bits_rs1_sign; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_bits_rs2_sign = decode_io_decode_exu_mul_p_bits_rs2_sign; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_bits_low = decode_io_decode_exu_mul_p_bits_low; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_bits_bext = decode_io_decode_exu_mul_p_bits_bext; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_bits_bdep = decode_io_decode_exu_mul_p_bits_bdep; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_bits_clmul = decode_io_decode_exu_mul_p_bits_clmul; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_bits_clmulh = decode_io_decode_exu_mul_p_bits_clmulh; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_bits_clmulr = decode_io_decode_exu_mul_p_bits_clmulr; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_bits_grev = decode_io_decode_exu_mul_p_bits_grev; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_bits_gorc = decode_io_decode_exu_mul_p_bits_gorc; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_bits_shfl = decode_io_decode_exu_mul_p_bits_shfl; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_bits_unshfl = decode_io_decode_exu_mul_p_bits_unshfl; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_bits_crc32_b = decode_io_decode_exu_mul_p_bits_crc32_b; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_bits_crc32_h = decode_io_decode_exu_mul_p_bits_crc32_h; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_bits_crc32_w = decode_io_decode_exu_mul_p_bits_crc32_w; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_bits_crc32c_b = decode_io_decode_exu_mul_p_bits_crc32c_b; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_bits_crc32c_h = decode_io_decode_exu_mul_p_bits_crc32c_h; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_bits_crc32c_w = decode_io_decode_exu_mul_p_bits_crc32c_w; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_mul_p_bits_bfp = decode_io_decode_exu_mul_p_bits_bfp; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_pred_correct_npc_x = decode_io_decode_exu_pred_correct_npc_x; // @[dec.scala 147:23] + assign io_dec_exu_decode_exu_dec_extint_stall = decode_io_decode_exu_dec_extint_stall; // @[dec.scala 147:23] + assign io_dec_exu_tlu_exu_dec_tlu_meihap = tlu_io_tlu_exu_dec_tlu_meihap; // @[dec.scala 223:18] + assign io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 223:18] + assign io_dec_exu_tlu_exu_dec_tlu_flush_path_r = tlu_io_tlu_exu_dec_tlu_flush_path_r; // @[dec.scala 223:18] + assign io_dec_exu_ib_exu_dec_i0_pc_d = instbuff_io_ib_exu_dec_i0_pc_d; // @[dec.scala 137:22] + assign io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = instbuff_io_ib_exu_dec_debug_wdata_rs1_d; // @[dec.scala 137:22] + assign io_dec_exu_gpr_exu_gpr_i0_rs1_d = gpr_io_gpr_exu_gpr_i0_rs1_d; // @[dec.scala 218:22] + assign io_dec_exu_gpr_exu_gpr_i0_rs2_d = gpr_io_gpr_exu_gpr_i0_rs2_d; // @[dec.scala 218:22] + assign io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 240:26] + assign io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 240:26] + assign io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 240:26] + assign io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = tlu_io_tlu_dma_dec_tlu_dma_qos_prty; // @[dec.scala 224:18] + assign io_dec_pic_dec_tlu_meicurpl = tlu_io_dec_pic_dec_tlu_meicurpl; // @[dec.scala 242:14] + assign io_dec_pic_dec_tlu_meipt = tlu_io_dec_pic_dec_tlu_meipt; // @[dec.scala 242:14] + assign instbuff_io_ifu_ib_ifu_i0_icaf = io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[dec.scala 136:22] + assign instbuff_io_ifu_ib_ifu_i0_icaf_type = io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[dec.scala 136:22] + assign instbuff_io_ifu_ib_ifu_i0_icaf_second = io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_second; // @[dec.scala 136:22] + assign instbuff_io_ifu_ib_ifu_i0_dbecc = io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[dec.scala 136:22] + assign instbuff_io_ifu_ib_ifu_i0_bp_index = io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[dec.scala 136:22] + assign instbuff_io_ifu_ib_ifu_i0_bp_fghr = io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[dec.scala 136:22] + assign instbuff_io_ifu_ib_ifu_i0_bp_btag = io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[dec.scala 136:22] + assign instbuff_io_ifu_ib_ifu_i0_valid = io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[dec.scala 136:22] + assign instbuff_io_ifu_ib_ifu_i0_instr = io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[dec.scala 136:22] + assign instbuff_io_ifu_ib_ifu_i0_pc = io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[dec.scala 136:22] + assign instbuff_io_ifu_ib_ifu_i0_pc4 = io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[dec.scala 136:22] + assign instbuff_io_ifu_ib_i0_brp_valid = io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[dec.scala 136:22] + assign instbuff_io_ifu_ib_i0_brp_bits_toffset = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[dec.scala 136:22] + assign instbuff_io_ifu_ib_i0_brp_bits_hist = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[dec.scala 136:22] + assign instbuff_io_ifu_ib_i0_brp_bits_br_error = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[dec.scala 136:22] + assign instbuff_io_ifu_ib_i0_brp_bits_br_start_error = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[dec.scala 136:22] + assign instbuff_io_ifu_ib_i0_brp_bits_prett = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[dec.scala 136:22] + assign instbuff_io_ifu_ib_i0_brp_bits_way = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[dec.scala 136:22] + assign instbuff_io_ifu_ib_i0_brp_bits_ret = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[dec.scala 136:22] + assign instbuff_io_dbg_ib_dbg_cmd_valid = io_dec_dbg_dbg_ib_dbg_cmd_valid; // @[dec.scala 138:22] + assign instbuff_io_dbg_ib_dbg_cmd_write = io_dec_dbg_dbg_ib_dbg_cmd_write; // @[dec.scala 138:22] + assign instbuff_io_dbg_ib_dbg_cmd_type = io_dec_dbg_dbg_ib_dbg_cmd_type; // @[dec.scala 138:22] + assign instbuff_io_dbg_ib_dbg_cmd_addr = io_dec_dbg_dbg_ib_dbg_cmd_addr; // @[dec.scala 138:22] + assign decode_clock = clock; + assign decode_reset = reset; + assign decode_io_decode_exu_exu_i0_result_x = io_dec_exu_decode_exu_exu_i0_result_x; // @[dec.scala 147:23] + assign decode_io_decode_exu_exu_csr_rs1_x = io_dec_exu_decode_exu_exu_csr_rs1_x; // @[dec.scala 147:23] + assign decode_io_dec_alu_exu_i0_pc_x = io_dec_exu_dec_alu_exu_i0_pc_x; // @[dec.scala 148:20] + assign decode_io_dctl_busbuff_lsu_nonblock_load_valid_m = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec.scala 155:26] + assign decode_io_dctl_busbuff_lsu_nonblock_load_tag_m = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[dec.scala 155:26] + assign decode_io_dctl_busbuff_lsu_nonblock_load_inv_r = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[dec.scala 155:26] + assign decode_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[dec.scala 155:26] + assign decode_io_dctl_busbuff_lsu_nonblock_load_data_valid = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[dec.scala 155:26] + assign decode_io_dctl_busbuff_lsu_nonblock_load_data_error = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec.scala 155:26] + assign decode_io_dctl_busbuff_lsu_nonblock_load_data_tag = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[dec.scala 155:26] + assign decode_io_dctl_dma_dma_dccm_stall_any = io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[dec.scala 150:22] + assign decode_io_dec_aln_ifu_i0_cinst = io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[dec.scala 145:21] + assign decode_io_dbg_dctl_dbg_cmd_wrdata = io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 165:22] + assign decode_io_dec_tlu_trace_disable = tlu_io_dec_tlu_trace_disable; // @[dec.scala 151:48] + assign decode_io_dec_debug_valid_d = instbuff_io_dec_debug_fence_d; // @[dec.scala 152:48] + assign decode_io_dec_tlu_flush_extint = tlu_io_dec_tlu_flush_extint; // @[dec.scala 153:48] + assign decode_io_dec_tlu_force_halt = tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 154:48] + assign decode_io_dec_i0_trigger_match_d = dec_trigger_io_dec_i0_trigger_match_d; // @[dec.scala 156:48] + assign decode_io_dec_tlu_wr_pause_r = tlu_io_dec_tlu_wr_pause_r; // @[dec.scala 157:48] + assign decode_io_dec_tlu_pipelining_disable = tlu_io_dec_tlu_pipelining_disable; // @[dec.scala 158:48] + assign decode_io_lsu_trigger_match_m = io_lsu_trigger_match_m; // @[dec.scala 159:48] + assign decode_io_lsu_pmu_misaligned_m = io_lsu_pmu_misaligned_m; // @[dec.scala 160:48] + assign decode_io_dec_tlu_debug_stall = tlu_io_dec_tlu_debug_stall; // @[dec.scala 161:48] + assign decode_io_dec_tlu_flush_leak_one_r = tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 163:48] + assign decode_io_dec_debug_fence_d = instbuff_io_dec_debug_fence_d; // @[dec.scala 164:48] + assign decode_io_dec_i0_icaf_d = instbuff_io_dec_i0_icaf_d; // @[dec.scala 166:48] + assign decode_io_dec_i0_icaf_second_d = instbuff_io_dec_i0_icaf_second_d; // @[dec.scala 167:48] + assign decode_io_dec_i0_icaf_type_d = instbuff_io_dec_i0_icaf_type_d; // @[dec.scala 168:48] + assign decode_io_dec_i0_dbecc_d = instbuff_io_dec_i0_dbecc_d; // @[dec.scala 169:48] + assign decode_io_dec_i0_brp_valid = instbuff_io_dec_i0_brp_valid; // @[dec.scala 170:48] + assign decode_io_dec_i0_brp_bits_toffset = instbuff_io_dec_i0_brp_bits_toffset; // @[dec.scala 170:48] + assign decode_io_dec_i0_brp_bits_hist = instbuff_io_dec_i0_brp_bits_hist; // @[dec.scala 170:48] + assign decode_io_dec_i0_brp_bits_br_error = instbuff_io_dec_i0_brp_bits_br_error; // @[dec.scala 170:48] + assign decode_io_dec_i0_brp_bits_br_start_error = instbuff_io_dec_i0_brp_bits_br_start_error; // @[dec.scala 170:48] + assign decode_io_dec_i0_brp_bits_prett = instbuff_io_dec_i0_brp_bits_prett; // @[dec.scala 170:48] + assign decode_io_dec_i0_brp_bits_way = instbuff_io_dec_i0_brp_bits_way; // @[dec.scala 170:48] + assign decode_io_dec_i0_brp_bits_ret = instbuff_io_dec_i0_brp_bits_ret; // @[dec.scala 170:48] + assign decode_io_dec_i0_bp_index = instbuff_io_dec_i0_bp_index; // @[dec.scala 171:48] + assign decode_io_dec_i0_bp_fghr = instbuff_io_dec_i0_bp_fghr; // @[dec.scala 172:48] + assign decode_io_dec_i0_bp_btag = instbuff_io_dec_i0_bp_btag; // @[dec.scala 173:48] + assign decode_io_lsu_idle_any = io_lsu_idle_any; // @[dec.scala 174:48] + assign decode_io_lsu_load_stall_any = io_lsu_load_stall_any; // @[dec.scala 175:48] + assign decode_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec.scala 176:48] + assign decode_io_exu_div_wren = io_exu_div_wren; // @[dec.scala 177:48] + assign decode_io_dec_tlu_i0_kill_writeb_wb = tlu_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 178:48] + assign decode_io_dec_tlu_flush_lower_wb = tlu_io_dec_tlu_flush_lower_wb; // @[dec.scala 179:48] + assign decode_io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 180:48] + assign decode_io_dec_tlu_flush_lower_r = tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 181:48] + assign decode_io_dec_tlu_flush_pause_r = tlu_io_dec_tlu_flush_pause_r; // @[dec.scala 182:48] + assign decode_io_dec_tlu_presync_d = tlu_io_dec_tlu_presync_d; // @[dec.scala 183:48] + assign decode_io_dec_tlu_postsync_d = tlu_io_dec_tlu_postsync_d; // @[dec.scala 184:48] + assign decode_io_dec_i0_pc4_d = instbuff_io_dec_i0_pc4_d; // @[dec.scala 185:48] + assign decode_io_dec_csr_rddata_d = tlu_io_dec_csr_rddata_d; // @[dec.scala 186:48] + assign decode_io_dec_csr_legal_d = tlu_io_dec_csr_legal_d; // @[dec.scala 187:48] + assign decode_io_lsu_result_m = io_lsu_result_m; // @[dec.scala 188:48] + assign decode_io_lsu_result_corr_r = io_lsu_result_corr_r; // @[dec.scala 189:48] + assign decode_io_exu_flush_final = io_exu_flush_final; // @[dec.scala 190:48] + assign decode_io_dec_i0_instr_d = instbuff_io_dec_i0_instr_d; // @[dec.scala 191:48] + assign decode_io_dec_ib0_valid_d = instbuff_io_dec_ib0_valid_d; // @[dec.scala 192:48] + assign decode_io_active_clk = io_active_clk; // @[dec.scala 194:48] + assign decode_io_free_l2clk = io_free_l2clk; // @[dec.scala 193:48] + assign decode_io_clk_override = tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 195:48] + assign gpr_clock = clock; + assign gpr_reset = reset; + assign gpr_io_raddr0 = decode_io_dec_i0_rs1_d; // @[dec.scala 206:23] + assign gpr_io_raddr1 = decode_io_dec_i0_rs2_d; // @[dec.scala 207:23] + assign gpr_io_wen0 = decode_io_dec_i0_wen_r; // @[dec.scala 208:23] + assign gpr_io_waddr0 = decode_io_dec_i0_waddr_r; // @[dec.scala 209:23] + assign gpr_io_wd0 = decode_io_dec_i0_wdata_r; // @[dec.scala 210:23] + assign gpr_io_wen1 = decode_io_dec_nonblock_load_wen; // @[dec.scala 211:23] + assign gpr_io_waddr1 = decode_io_dec_nonblock_load_waddr; // @[dec.scala 212:23] + assign gpr_io_wd1 = io_lsu_nonblock_load_data; // @[dec.scala 213:23] + assign gpr_io_wen2 = io_exu_div_wren; // @[dec.scala 214:23] + assign gpr_io_waddr2 = decode_io_div_waddr_wb; // @[dec.scala 215:23] + assign gpr_io_wd2 = io_exu_div_result; // @[dec.scala 216:23] + assign tlu_clock = clock; + assign tlu_reset = reset; + assign tlu_io_tlu_exu_exu_i0_br_hist_r = io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[dec.scala 223:18] + assign tlu_io_tlu_exu_exu_i0_br_error_r = io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[dec.scala 223:18] + assign tlu_io_tlu_exu_exu_i0_br_start_error_r = io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[dec.scala 223:18] + assign tlu_io_tlu_exu_exu_i0_br_valid_r = io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[dec.scala 223:18] + assign tlu_io_tlu_exu_exu_i0_br_mp_r = io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[dec.scala 223:18] + assign tlu_io_tlu_exu_exu_i0_br_middle_r = io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[dec.scala 223:18] + assign tlu_io_tlu_exu_exu_pmu_i0_br_misp = io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[dec.scala 223:18] + assign tlu_io_tlu_exu_exu_pmu_i0_br_ataken = io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[dec.scala 223:18] + assign tlu_io_tlu_exu_exu_pmu_i0_pc4 = io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[dec.scala 223:18] + assign tlu_io_tlu_exu_exu_npc_r = io_dec_exu_tlu_exu_exu_npc_r; // @[dec.scala 223:18] + assign tlu_io_tlu_dma_dma_pmu_dccm_read = io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[dec.scala 224:18] + assign tlu_io_tlu_dma_dma_pmu_dccm_write = io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[dec.scala 224:18] + assign tlu_io_tlu_dma_dma_pmu_any_read = io_dec_dma_tlu_dma_dma_pmu_any_read; // @[dec.scala 224:18] + assign tlu_io_tlu_dma_dma_pmu_any_write = io_dec_dma_tlu_dma_dma_pmu_any_write; // @[dec.scala 224:18] + assign tlu_io_tlu_dma_dma_dccm_stall_any = io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[dec.scala 224:18] + assign tlu_io_tlu_dma_dma_iccm_stall_any = io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[dec.scala 224:18] + assign tlu_io_free_clk = io_free_clk; // @[dec.scala 226:45] + assign tlu_io_free_l2clk = io_free_l2clk; // @[dec.scala 225:45] + assign tlu_io_rst_vec = io_rst_vec; // @[dec.scala 228:45] + assign tlu_io_nmi_int = io_nmi_int; // @[dec.scala 229:45] + assign tlu_io_nmi_vec = io_nmi_vec; // @[dec.scala 230:45] + assign tlu_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[dec.scala 231:45] + assign tlu_io_i_cpu_run_req = io_i_cpu_run_req; // @[dec.scala 232:45] + assign tlu_io_lsu_fastint_stall_any = io_lsu_fastint_stall_any; // @[dec.scala 233:45] + assign tlu_io_lsu_idle_any = io_lsu_idle_any; // @[dec.scala 264:45] + assign tlu_io_dec_pmu_instr_decoded = decode_io_dec_pmu_instr_decoded; // @[dec.scala 235:45] + assign tlu_io_dec_pmu_decode_stall = decode_io_dec_pmu_decode_stall; // @[dec.scala 236:45] + assign tlu_io_dec_pmu_presync_stall = decode_io_dec_pmu_presync_stall; // @[dec.scala 237:45] + assign tlu_io_dec_pmu_postsync_stall = decode_io_dec_pmu_postsync_stall; // @[dec.scala 238:45] + assign tlu_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec.scala 239:45] + assign tlu_io_lsu_fir_addr = io_lsu_fir_addr; // @[dec.scala 243:45] + assign tlu_io_lsu_fir_error = io_lsu_fir_error; // @[dec.scala 244:45] + assign tlu_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[dec.scala 245:45] + assign tlu_io_lsu_error_pkt_r_valid = io_lsu_error_pkt_r_valid; // @[dec.scala 246:45] + assign tlu_io_lsu_error_pkt_r_bits_single_ecc_error = io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec.scala 246:45] + assign tlu_io_lsu_error_pkt_r_bits_inst_type = io_lsu_error_pkt_r_bits_inst_type; // @[dec.scala 246:45] + assign tlu_io_lsu_error_pkt_r_bits_exc_type = io_lsu_error_pkt_r_bits_exc_type; // @[dec.scala 246:45] + assign tlu_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[dec.scala 246:45] + assign tlu_io_lsu_error_pkt_r_bits_addr = io_lsu_error_pkt_r_bits_addr; // @[dec.scala 246:45] + assign tlu_io_lsu_single_ecc_error_incr = io_lsu_single_ecc_error_incr; // @[dec.scala 247:45] + assign tlu_io_dec_pause_state = decode_io_dec_pause_state; // @[dec.scala 248:45] + assign tlu_io_dec_csr_wen_unq_d = decode_io_dec_csr_wen_unq_d; // @[dec.scala 249:45] + assign tlu_io_dec_csr_any_unq_d = decode_io_dec_csr_any_unq_d; // @[dec.scala 250:45] + assign tlu_io_dec_csr_rdaddr_d = decode_io_dec_csr_rdaddr_d; // @[dec.scala 251:45] + assign tlu_io_dec_csr_wen_r = decode_io_dec_csr_wen_r; // @[dec.scala 252:45] + assign tlu_io_dec_csr_wraddr_r = decode_io_dec_csr_wraddr_r; // @[dec.scala 253:45] + assign tlu_io_dec_csr_wrdata_r = decode_io_dec_csr_wrdata_r; // @[dec.scala 254:45] + assign tlu_io_dec_csr_stall_int_ff = decode_io_dec_csr_stall_int_ff; // @[dec.scala 255:45] + assign tlu_io_dec_tlu_i0_valid_r = decode_io_dec_tlu_i0_valid_r; // @[dec.scala 256:45] + assign tlu_io_dec_tlu_i0_pc_r = decode_io_dec_tlu_i0_pc_r; // @[dec.scala 257:45] + assign tlu_io_dec_tlu_packet_r_legal = decode_io_dec_tlu_packet_r_legal; // @[dec.scala 258:45] + assign tlu_io_dec_tlu_packet_r_icaf = decode_io_dec_tlu_packet_r_icaf; // @[dec.scala 258:45] + assign tlu_io_dec_tlu_packet_r_icaf_second = decode_io_dec_tlu_packet_r_icaf_second; // @[dec.scala 258:45] + assign tlu_io_dec_tlu_packet_r_icaf_type = decode_io_dec_tlu_packet_r_icaf_type; // @[dec.scala 258:45] + assign tlu_io_dec_tlu_packet_r_fence_i = decode_io_dec_tlu_packet_r_fence_i; // @[dec.scala 258:45] + assign tlu_io_dec_tlu_packet_r_i0trigger = decode_io_dec_tlu_packet_r_i0trigger; // @[dec.scala 258:45] + assign tlu_io_dec_tlu_packet_r_pmu_i0_itype = decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec.scala 258:45] + assign tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred = decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec.scala 258:45] + assign tlu_io_dec_tlu_packet_r_pmu_divide = decode_io_dec_tlu_packet_r_pmu_divide; // @[dec.scala 258:45] + assign tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned = decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec.scala 258:45] + assign tlu_io_dec_illegal_inst = decode_io_dec_illegal_inst; // @[dec.scala 259:45] + assign tlu_io_dec_i0_decode_d = decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 260:45] + assign tlu_io_exu_i0_br_way_r = io_exu_i0_br_way_r; // @[dec.scala 261:45] + assign tlu_io_dbg_halt_req = io_dbg_halt_req; // @[dec.scala 262:45] + assign tlu_io_dbg_resume_req = io_dbg_resume_req; // @[dec.scala 263:45] + assign tlu_io_dec_div_active = decode_io_dec_div_active; // @[dec.scala 265:45] + assign tlu_io_timer_int = io_timer_int; // @[dec.scala 266:45] + assign tlu_io_soft_int = io_soft_int; // @[dec.scala 267:45] + assign tlu_io_core_id = io_core_id; // @[dec.scala 268:45] + assign tlu_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[dec.scala 269:45] + assign tlu_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[dec.scala 270:45] + assign tlu_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec.scala 271:45] + assign tlu_io_ifu_pmu_instr_aligned = io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[dec.scala 234:45] + assign tlu_io_tlu_ifc_ifu_pmu_fetch_stall = io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[dec.scala 221:18] + assign tlu_io_tlu_mem_ifu_pmu_ic_miss = io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[dec.scala 220:18] + assign tlu_io_tlu_mem_ifu_pmu_ic_hit = io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[dec.scala 220:18] + assign tlu_io_tlu_mem_ifu_pmu_bus_error = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[dec.scala 220:18] + assign tlu_io_tlu_mem_ifu_pmu_bus_busy = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[dec.scala 220:18] + assign tlu_io_tlu_mem_ifu_pmu_bus_trxn = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[dec.scala 220:18] + assign tlu_io_tlu_mem_ifu_ic_error_start = io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[dec.scala 220:18] + assign tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err = io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[dec.scala 220:18] + assign tlu_io_tlu_mem_ifu_ic_debug_rd_data = io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[dec.scala 220:18] + assign tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid = io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[dec.scala 220:18] + assign tlu_io_tlu_mem_ifu_miss_state_idle = io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[dec.scala 220:18] + assign tlu_io_tlu_busbuff_lsu_pmu_bus_trxn = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec.scala 240:26] + assign tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec.scala 240:26] + assign tlu_io_tlu_busbuff_lsu_pmu_bus_error = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 240:26] + assign tlu_io_tlu_busbuff_lsu_pmu_bus_busy = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 240:26] + assign tlu_io_tlu_busbuff_lsu_imprecise_error_load_any = io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec.scala 240:26] + assign tlu_io_tlu_busbuff_lsu_imprecise_error_store_any = io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec.scala 240:26] + assign tlu_io_tlu_busbuff_lsu_imprecise_error_addr_any = io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec.scala 240:26] + assign tlu_io_lsu_tlu_lsu_pmu_load_external_m = io_lsu_tlu_lsu_pmu_load_external_m; // @[dec.scala 241:14] + assign tlu_io_lsu_tlu_lsu_pmu_store_external_m = io_lsu_tlu_lsu_pmu_store_external_m; // @[dec.scala 241:14] + assign tlu_io_dec_pic_pic_claimid = io_dec_pic_pic_claimid; // @[dec.scala 242:14] + assign tlu_io_dec_pic_pic_pl = io_dec_pic_pic_pl; // @[dec.scala 242:14] + assign tlu_io_dec_pic_mhwakeup = io_dec_pic_mhwakeup; // @[dec.scala 242:14] + assign tlu_io_dec_pic_mexintpend = io_dec_pic_mexintpend; // @[dec.scala 242:14] + assign dec_trigger_io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[dec.scala 141:34] + assign dec_trigger_io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 141:34] + assign dec_trigger_io_trigger_pkt_any_0_execute = tlu_io_trigger_pkt_any_0_execute; // @[dec.scala 141:34] + assign dec_trigger_io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[dec.scala 141:34] + assign dec_trigger_io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 141:34] + assign dec_trigger_io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[dec.scala 141:34] + assign dec_trigger_io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 141:34] + assign dec_trigger_io_trigger_pkt_any_1_execute = tlu_io_trigger_pkt_any_1_execute; // @[dec.scala 141:34] + assign dec_trigger_io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[dec.scala 141:34] + assign dec_trigger_io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 141:34] + assign dec_trigger_io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[dec.scala 141:34] + assign dec_trigger_io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 141:34] + assign dec_trigger_io_trigger_pkt_any_2_execute = tlu_io_trigger_pkt_any_2_execute; // @[dec.scala 141:34] + assign dec_trigger_io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[dec.scala 141:34] + assign dec_trigger_io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 141:34] + assign dec_trigger_io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[dec.scala 141:34] + assign dec_trigger_io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 141:34] + assign dec_trigger_io_trigger_pkt_any_3_execute = tlu_io_trigger_pkt_any_3_execute; // @[dec.scala 141:34] + assign dec_trigger_io_trigger_pkt_any_3_m = tlu_io_trigger_pkt_any_3_m; // @[dec.scala 141:34] + assign dec_trigger_io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 141:34] + assign dec_trigger_io_dec_i0_pc_d = instbuff_io_ib_exu_dec_i0_pc_d; // @[dec.scala 140:30] +endmodule diff --git a/dec_dec_ctl.anno.json b/dec_dec_ctl.anno.json new file mode 100644 index 00000000..5675a682 --- /dev/null +++ b/dec_dec_ctl.anno.json @@ -0,0 +1,683 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_unshfl", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_packh", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_crc32_w", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_rd", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_crc32_b", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_zba", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_presync", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_rs1_sign", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_ror", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_rs2", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_pc", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_load", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_csr_clr", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_grev", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_alu", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_mul", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_min", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_zbp", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_clmulr", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_imm12", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_gorc", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_pcnt", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_beq", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_sra", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_ebreak", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_by", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + 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"class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_sh3add", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_postsync", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_clz", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_sro", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_imm20", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_clmul", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_rs2_sign", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_bdep", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_dec_ctl|dec_dec_ctl>io_out_shimm5", + "sources":[ + "~dec_dec_ctl|dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"dec_dec_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/dec_dec_ctl.fir b/dec_dec_ctl.fir new file mode 100644 index 00000000..8b5880b5 --- /dev/null +++ b/dec_dec_ctl.fir @@ -0,0 +1,4526 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit dec_dec_ctl : + module dec_dec_ctl : + input clock : Clock + input reset : UInt<1> + output io : {flip ins : UInt<32>, out : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, zbs : UInt<1>, bext : UInt<1>, bdep : UInt<1>, zbe : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, zbc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, zbp : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, zbr : UInt<1>, bfp : UInt<1>, zbf : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>}} + + node _T = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_3 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_4 = eq(_T_3, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_5 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_6 = eq(_T_5, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_7 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_8 = eq(_T_7, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_9 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_10 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_11 = eq(_T_10, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_12 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_13 = and(_T, _T_1) @[dec_dec_ctl.scala 17:17] + node _T_14 = and(_T_13, _T_2) @[dec_dec_ctl.scala 17:17] + node _T_15 = and(_T_14, _T_4) @[dec_dec_ctl.scala 17:17] + node _T_16 = and(_T_15, _T_6) @[dec_dec_ctl.scala 17:17] + node _T_17 = and(_T_16, _T_8) @[dec_dec_ctl.scala 17:17] + node _T_18 = and(_T_17, _T_9) @[dec_dec_ctl.scala 17:17] + node _T_19 = and(_T_18, _T_11) @[dec_dec_ctl.scala 17:17] + node _T_20 = and(_T_19, _T_12) @[dec_dec_ctl.scala 17:17] + node _T_21 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_22 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_23 = eq(_T_22, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_24 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_25 = eq(_T_24, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_26 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_27 = and(_T_21, _T_23) @[dec_dec_ctl.scala 17:17] + node _T_28 = and(_T_27, _T_25) @[dec_dec_ctl.scala 17:17] + node _T_29 = and(_T_28, _T_26) @[dec_dec_ctl.scala 17:17] + node _T_30 = or(_T_20, _T_29) @[dec_dec_ctl.scala 20:62] + node _T_31 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_32 = eq(_T_31, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_33 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_34 = eq(_T_33, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_35 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_36 = eq(_T_35, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_37 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_38 = and(_T_32, _T_34) @[dec_dec_ctl.scala 17:17] + node _T_39 = and(_T_38, _T_36) @[dec_dec_ctl.scala 17:17] + node _T_40 = and(_T_39, _T_37) @[dec_dec_ctl.scala 17:17] + node _T_41 = or(_T_30, _T_40) @[dec_dec_ctl.scala 20:92] + node _T_42 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_43 = eq(_T_42, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_44 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_45 = eq(_T_44, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_46 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_47 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_48 = and(_T_43, _T_45) @[dec_dec_ctl.scala 17:17] + node _T_49 = and(_T_48, _T_46) @[dec_dec_ctl.scala 17:17] + node _T_50 = and(_T_49, _T_47) @[dec_dec_ctl.scala 17:17] + node _T_51 = or(_T_41, _T_50) @[dec_dec_ctl.scala 21:34] + node _T_52 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_53 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_54 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_55 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_56 = and(_T_52, _T_53) @[dec_dec_ctl.scala 17:17] + node _T_57 = and(_T_56, _T_54) @[dec_dec_ctl.scala 17:17] + node _T_58 = and(_T_57, _T_55) @[dec_dec_ctl.scala 17:17] + node _T_59 = or(_T_51, _T_58) @[dec_dec_ctl.scala 21:66] + node _T_60 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_61 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_62 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_63 = eq(_T_62, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_64 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_65 = and(_T_60, _T_61) @[dec_dec_ctl.scala 17:17] + node _T_66 = and(_T_65, _T_63) @[dec_dec_ctl.scala 17:17] + node _T_67 = and(_T_66, _T_64) @[dec_dec_ctl.scala 17:17] + node _T_68 = or(_T_59, _T_67) @[dec_dec_ctl.scala 21:94] + node _T_69 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_70 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_71 = eq(_T_70, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_72 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_73 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_74 = and(_T_69, _T_71) @[dec_dec_ctl.scala 17:17] + node _T_75 = and(_T_74, _T_72) @[dec_dec_ctl.scala 17:17] + node _T_76 = and(_T_75, _T_73) @[dec_dec_ctl.scala 17:17] + node _T_77 = or(_T_68, _T_76) @[dec_dec_ctl.scala 22:32] + node _T_78 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_79 = eq(_T_78, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_80 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_81 = eq(_T_80, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_82 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_83 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_84 = and(_T_79, _T_81) @[dec_dec_ctl.scala 17:17] + node _T_85 = and(_T_84, _T_82) @[dec_dec_ctl.scala 17:17] + node _T_86 = and(_T_85, _T_83) @[dec_dec_ctl.scala 17:17] + node _T_87 = or(_T_77, _T_86) @[dec_dec_ctl.scala 22:60] + node _T_88 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_89 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_90 = eq(_T_89, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_91 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_93 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_94 = and(_T_88, _T_90) @[dec_dec_ctl.scala 17:17] + node _T_95 = and(_T_94, _T_92) @[dec_dec_ctl.scala 17:17] + node _T_96 = and(_T_95, _T_93) @[dec_dec_ctl.scala 17:17] + node _T_97 = or(_T_87, _T_96) @[dec_dec_ctl.scala 22:90] + node _T_98 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_99 = eq(_T_98, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_100 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_101 = eq(_T_100, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_102 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_104 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_105 = and(_T_99, _T_101) @[dec_dec_ctl.scala 17:17] + node _T_106 = and(_T_105, _T_103) @[dec_dec_ctl.scala 17:17] + node _T_107 = and(_T_106, _T_104) @[dec_dec_ctl.scala 17:17] + node _T_108 = or(_T_97, _T_107) @[dec_dec_ctl.scala 23:33] + node _T_109 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_110 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_111 = eq(_T_110, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_112 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_113 = and(_T_109, _T_111) @[dec_dec_ctl.scala 17:17] + node _T_114 = and(_T_113, _T_112) @[dec_dec_ctl.scala 17:17] + node _T_115 = or(_T_108, _T_114) @[dec_dec_ctl.scala 23:64] + node _T_116 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_117 = eq(_T_116, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_118 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_119 = eq(_T_118, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_120 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_121 = and(_T_117, _T_119) @[dec_dec_ctl.scala 17:17] + node _T_122 = and(_T_121, _T_120) @[dec_dec_ctl.scala 17:17] + node _T_123 = or(_T_115, _T_122) @[dec_dec_ctl.scala 23:89] + node _T_124 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_125 = or(_T_123, _T_124) @[dec_dec_ctl.scala 24:29] + node _T_126 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_127 = or(_T_125, _T_126) @[dec_dec_ctl.scala 24:48] + node _T_128 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_129 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_130 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_131 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_132 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_133 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_134 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_135 = eq(_T_134, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_136 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_137 = and(_T_128, _T_129) @[dec_dec_ctl.scala 17:17] + node _T_138 = and(_T_137, _T_130) @[dec_dec_ctl.scala 17:17] + node _T_139 = and(_T_138, _T_131) @[dec_dec_ctl.scala 17:17] + node _T_140 = and(_T_139, _T_132) @[dec_dec_ctl.scala 17:17] + node _T_141 = and(_T_140, _T_133) @[dec_dec_ctl.scala 17:17] + node _T_142 = and(_T_141, _T_135) @[dec_dec_ctl.scala 17:17] + node _T_143 = and(_T_142, _T_136) @[dec_dec_ctl.scala 17:17] + node _T_144 = or(_T_127, _T_143) @[dec_dec_ctl.scala 24:67] + node _T_145 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_147 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_148 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_149 = eq(_T_148, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_150 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_152 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_153 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_154 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_155 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_156 = eq(_T_155, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_157 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_158 = and(_T_146, _T_147) @[dec_dec_ctl.scala 17:17] + node _T_159 = and(_T_158, _T_149) @[dec_dec_ctl.scala 17:17] + node _T_160 = and(_T_159, _T_151) @[dec_dec_ctl.scala 17:17] + node _T_161 = and(_T_160, _T_152) @[dec_dec_ctl.scala 17:17] + node _T_162 = and(_T_161, _T_153) @[dec_dec_ctl.scala 17:17] + node _T_163 = and(_T_162, _T_154) @[dec_dec_ctl.scala 17:17] + node _T_164 = and(_T_163, _T_156) @[dec_dec_ctl.scala 17:17] + node _T_165 = and(_T_164, _T_157) @[dec_dec_ctl.scala 17:17] + node _T_166 = or(_T_144, _T_165) @[dec_dec_ctl.scala 24:107] + node _T_167 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_169 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_170 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_172 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_173 = eq(_T_172, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_174 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_175 = eq(_T_174, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_176 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_177 = eq(_T_176, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_178 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_180 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_181 = and(_T_168, _T_169) @[dec_dec_ctl.scala 17:17] + node _T_182 = and(_T_181, _T_171) @[dec_dec_ctl.scala 17:17] + node _T_183 = and(_T_182, _T_173) @[dec_dec_ctl.scala 17:17] + node _T_184 = and(_T_183, _T_175) @[dec_dec_ctl.scala 17:17] + node _T_185 = and(_T_184, _T_177) @[dec_dec_ctl.scala 17:17] + node _T_186 = and(_T_185, _T_179) @[dec_dec_ctl.scala 17:17] + node _T_187 = and(_T_186, _T_180) @[dec_dec_ctl.scala 17:17] + node _T_188 = or(_T_166, _T_187) @[dec_dec_ctl.scala 25:49] + io.out.alu <= _T_188 @[dec_dec_ctl.scala 20:14] + node _T_189 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_190 = eq(_T_189, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_191 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_192 = eq(_T_191, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_193 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_194 = eq(_T_193, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_195 = and(_T_190, _T_192) @[dec_dec_ctl.scala 17:17] + node _T_196 = and(_T_195, _T_194) @[dec_dec_ctl.scala 17:17] + node _T_197 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_198 = eq(_T_197, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_199 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34] + node _T_200 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_201 = eq(_T_200, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_202 = and(_T_198, _T_199) @[dec_dec_ctl.scala 17:17] + node _T_203 = and(_T_202, _T_201) @[dec_dec_ctl.scala 17:17] + node _T_204 = or(_T_196, _T_203) @[dec_dec_ctl.scala 27:43] + node _T_205 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34] + node _T_206 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_207 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_208 = eq(_T_207, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_209 = and(_T_205, _T_206) @[dec_dec_ctl.scala 17:17] + node _T_210 = and(_T_209, _T_208) @[dec_dec_ctl.scala 17:17] + node _T_211 = or(_T_204, _T_210) @[dec_dec_ctl.scala 27:70] + node _T_212 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_213 = eq(_T_212, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_214 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34] + node _T_215 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_217 = and(_T_213, _T_214) @[dec_dec_ctl.scala 17:17] + node _T_218 = and(_T_217, _T_216) @[dec_dec_ctl.scala 17:17] + node _T_219 = or(_T_211, _T_218) @[dec_dec_ctl.scala 27:96] + node _T_220 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34] + node _T_221 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_222 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_223 = eq(_T_222, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_224 = and(_T_220, _T_221) @[dec_dec_ctl.scala 17:17] + node _T_225 = and(_T_224, _T_223) @[dec_dec_ctl.scala 17:17] + node _T_226 = or(_T_219, _T_225) @[dec_dec_ctl.scala 28:30] + node _T_227 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_228 = eq(_T_227, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_229 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34] + node _T_230 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_231 = eq(_T_230, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_232 = and(_T_228, _T_229) @[dec_dec_ctl.scala 17:17] + node _T_233 = and(_T_232, _T_231) @[dec_dec_ctl.scala 17:17] + node _T_234 = or(_T_226, _T_233) @[dec_dec_ctl.scala 28:57] + node _T_235 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34] + node _T_236 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_237 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_238 = eq(_T_237, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_239 = and(_T_235, _T_236) @[dec_dec_ctl.scala 17:17] + node _T_240 = and(_T_239, _T_238) @[dec_dec_ctl.scala 17:17] + node _T_241 = or(_T_234, _T_240) @[dec_dec_ctl.scala 28:83] + node _T_242 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_243 = eq(_T_242, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_244 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34] + node _T_245 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_246 = eq(_T_245, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_247 = and(_T_243, _T_244) @[dec_dec_ctl.scala 17:17] + node _T_248 = and(_T_247, _T_246) @[dec_dec_ctl.scala 17:17] + node _T_249 = or(_T_241, _T_248) @[dec_dec_ctl.scala 28:109] + node _T_250 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34] + node _T_251 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_252 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_254 = and(_T_250, _T_251) @[dec_dec_ctl.scala 17:17] + node _T_255 = and(_T_254, _T_253) @[dec_dec_ctl.scala 17:17] + node _T_256 = or(_T_249, _T_255) @[dec_dec_ctl.scala 29:29] + node _T_257 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_258 = eq(_T_257, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_259 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34] + node _T_260 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_261 = eq(_T_260, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_262 = and(_T_258, _T_259) @[dec_dec_ctl.scala 17:17] + node _T_263 = and(_T_262, _T_261) @[dec_dec_ctl.scala 17:17] + node _T_264 = or(_T_256, _T_263) @[dec_dec_ctl.scala 29:55] + node _T_265 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34] + node _T_266 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_267 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_268 = eq(_T_267, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_269 = and(_T_265, _T_266) @[dec_dec_ctl.scala 17:17] + node _T_270 = and(_T_269, _T_268) @[dec_dec_ctl.scala 17:17] + node _T_271 = or(_T_264, _T_270) @[dec_dec_ctl.scala 29:81] + node _T_272 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_274 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_275 = eq(_T_274, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_276 = and(_T_273, _T_275) @[dec_dec_ctl.scala 17:17] + node _T_277 = or(_T_271, _T_276) @[dec_dec_ctl.scala 30:29] + node _T_278 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_279 = eq(_T_278, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_280 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_281 = eq(_T_280, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_282 = and(_T_279, _T_281) @[dec_dec_ctl.scala 17:17] + node _T_283 = or(_T_277, _T_282) @[dec_dec_ctl.scala 30:52] + io.out.rs1 <= _T_283 @[dec_dec_ctl.scala 27:14] + node _T_284 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_285 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_286 = eq(_T_285, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_287 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_288 = eq(_T_287, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_289 = and(_T_284, _T_286) @[dec_dec_ctl.scala 17:17] + node _T_290 = and(_T_289, _T_288) @[dec_dec_ctl.scala 17:17] + node _T_291 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_292 = eq(_T_291, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_293 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_294 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_295 = eq(_T_294, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_296 = and(_T_292, _T_293) @[dec_dec_ctl.scala 17:17] + node _T_297 = and(_T_296, _T_295) @[dec_dec_ctl.scala 17:17] + node _T_298 = or(_T_290, _T_297) @[dec_dec_ctl.scala 32:40] + io.out.rs2 <= _T_298 @[dec_dec_ctl.scala 32:14] + node _T_299 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_300 = eq(_T_299, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_301 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_302 = eq(_T_301, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_303 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_304 = and(_T_300, _T_302) @[dec_dec_ctl.scala 17:17] + node _T_305 = and(_T_304, _T_303) @[dec_dec_ctl.scala 17:17] + node _T_306 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_307 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_308 = eq(_T_307, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_309 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_310 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_311 = eq(_T_310, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_312 = and(_T_306, _T_308) @[dec_dec_ctl.scala 17:17] + node _T_313 = and(_T_312, _T_309) @[dec_dec_ctl.scala 17:17] + node _T_314 = and(_T_313, _T_311) @[dec_dec_ctl.scala 17:17] + node _T_315 = or(_T_305, _T_314) @[dec_dec_ctl.scala 34:42] + node _T_316 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_317 = eq(_T_316, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_318 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_319 = eq(_T_318, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_320 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_321 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_322 = and(_T_317, _T_319) @[dec_dec_ctl.scala 17:17] + node _T_323 = and(_T_322, _T_320) @[dec_dec_ctl.scala 17:17] + node _T_324 = and(_T_323, _T_321) @[dec_dec_ctl.scala 17:17] + node _T_325 = or(_T_315, _T_324) @[dec_dec_ctl.scala 34:70] + node _T_326 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_328 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_330 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_331 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_332 = eq(_T_331, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_333 = and(_T_327, _T_329) @[dec_dec_ctl.scala 17:17] + node _T_334 = and(_T_333, _T_330) @[dec_dec_ctl.scala 17:17] + node _T_335 = and(_T_334, _T_332) @[dec_dec_ctl.scala 17:17] + node _T_336 = or(_T_325, _T_335) @[dec_dec_ctl.scala 34:99] + io.out.imm12 <= _T_336 @[dec_dec_ctl.scala 34:16] + node _T_337 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_339 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_340 = eq(_T_339, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_341 = and(_T_338, _T_340) @[dec_dec_ctl.scala 17:17] + node _T_342 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_343 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_344 = and(_T_342, _T_343) @[dec_dec_ctl.scala 17:17] + node _T_345 = or(_T_341, _T_344) @[dec_dec_ctl.scala 36:37] + node _T_346 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_347 = or(_T_345, _T_346) @[dec_dec_ctl.scala 36:58] + io.out.rd <= _T_347 @[dec_dec_ctl.scala 36:13] + node _T_348 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_349 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_350 = eq(_T_349, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_351 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_352 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_354 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_355 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_356 = eq(_T_355, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_357 = and(_T_348, _T_350) @[dec_dec_ctl.scala 17:17] + node _T_358 = and(_T_357, _T_351) @[dec_dec_ctl.scala 17:17] + node _T_359 = and(_T_358, _T_353) @[dec_dec_ctl.scala 17:17] + node _T_360 = and(_T_359, _T_354) @[dec_dec_ctl.scala 17:17] + node _T_361 = and(_T_360, _T_356) @[dec_dec_ctl.scala 17:17] + node _T_362 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_363 = eq(_T_362, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_364 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_365 = eq(_T_364, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_366 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_367 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_369 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_370 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_371 = eq(_T_370, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_372 = and(_T_363, _T_365) @[dec_dec_ctl.scala 17:17] + node _T_373 = and(_T_372, _T_366) @[dec_dec_ctl.scala 17:17] + node _T_374 = and(_T_373, _T_368) @[dec_dec_ctl.scala 17:17] + node _T_375 = and(_T_374, _T_369) @[dec_dec_ctl.scala 17:17] + node _T_376 = and(_T_375, _T_371) @[dec_dec_ctl.scala 17:17] + node _T_377 = or(_T_361, _T_376) @[dec_dec_ctl.scala 38:53] + node _T_378 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_379 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_380 = eq(_T_379, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_381 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_382 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_383 = eq(_T_382, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_384 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_385 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_387 = and(_T_378, _T_380) @[dec_dec_ctl.scala 17:17] + node _T_388 = and(_T_387, _T_381) @[dec_dec_ctl.scala 17:17] + node _T_389 = and(_T_388, _T_383) @[dec_dec_ctl.scala 17:17] + node _T_390 = and(_T_389, _T_384) @[dec_dec_ctl.scala 17:17] + node _T_391 = and(_T_390, _T_386) @[dec_dec_ctl.scala 17:17] + node _T_392 = or(_T_377, _T_391) @[dec_dec_ctl.scala 38:89] + io.out.shimm5 <= _T_392 @[dec_dec_ctl.scala 38:17] + node _T_393 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_394 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_395 = and(_T_393, _T_394) @[dec_dec_ctl.scala 17:17] + node _T_396 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_397 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_398 = and(_T_396, _T_397) @[dec_dec_ctl.scala 17:17] + node _T_399 = or(_T_395, _T_398) @[dec_dec_ctl.scala 40:38] + io.out.imm20 <= _T_399 @[dec_dec_ctl.scala 40:16] + node _T_400 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_401 = eq(_T_400, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_402 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_403 = eq(_T_402, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_404 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_405 = and(_T_401, _T_403) @[dec_dec_ctl.scala 17:17] + node _T_406 = and(_T_405, _T_404) @[dec_dec_ctl.scala 17:17] + node _T_407 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_408 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_409 = and(_T_407, _T_408) @[dec_dec_ctl.scala 17:17] + node _T_410 = or(_T_406, _T_409) @[dec_dec_ctl.scala 42:39] + io.out.pc <= _T_410 @[dec_dec_ctl.scala 42:13] + node _T_411 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_412 = eq(_T_411, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_413 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_414 = eq(_T_413, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_415 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_416 = eq(_T_415, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_417 = and(_T_412, _T_414) @[dec_dec_ctl.scala 17:17] + node _T_418 = and(_T_417, _T_416) @[dec_dec_ctl.scala 17:17] + io.out.load <= _T_418 @[dec_dec_ctl.scala 44:15] + node _T_419 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_420 = eq(_T_419, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_421 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_422 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_424 = and(_T_420, _T_421) @[dec_dec_ctl.scala 17:17] + node _T_425 = and(_T_424, _T_423) @[dec_dec_ctl.scala 17:17] + io.out.store <= _T_425 @[dec_dec_ctl.scala 46:16] + node _T_426 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_427 = eq(_T_426, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_428 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_429 = eq(_T_428, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_430 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_431 = eq(_T_430, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_432 = and(_T_427, _T_429) @[dec_dec_ctl.scala 17:17] + node _T_433 = and(_T_432, _T_431) @[dec_dec_ctl.scala 17:17] + io.out.lsu <= _T_433 @[dec_dec_ctl.scala 48:14] + node _T_434 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_436 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_438 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_439 = eq(_T_438, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_440 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_441 = eq(_T_440, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_442 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_443 = and(_T_435, _T_437) @[dec_dec_ctl.scala 17:17] + node _T_444 = and(_T_443, _T_439) @[dec_dec_ctl.scala 17:17] + node _T_445 = and(_T_444, _T_441) @[dec_dec_ctl.scala 17:17] + node _T_446 = and(_T_445, _T_442) @[dec_dec_ctl.scala 17:17] + node _T_447 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_448 = eq(_T_447, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_449 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_450 = eq(_T_449, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_451 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_452 = and(_T_448, _T_450) @[dec_dec_ctl.scala 17:17] + node _T_453 = and(_T_452, _T_451) @[dec_dec_ctl.scala 17:17] + node _T_454 = or(_T_446, _T_453) @[dec_dec_ctl.scala 50:49] + node _T_455 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_457 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_458 = eq(_T_457, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_459 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_460 = eq(_T_459, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_461 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_462 = eq(_T_461, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_463 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_464 = eq(_T_463, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_465 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_466 = eq(_T_465, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_467 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_468 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_470 = and(_T_456, _T_458) @[dec_dec_ctl.scala 17:17] + node _T_471 = and(_T_470, _T_460) @[dec_dec_ctl.scala 17:17] + node _T_472 = and(_T_471, _T_462) @[dec_dec_ctl.scala 17:17] + node _T_473 = and(_T_472, _T_464) @[dec_dec_ctl.scala 17:17] + node _T_474 = and(_T_473, _T_466) @[dec_dec_ctl.scala 17:17] + node _T_475 = and(_T_474, _T_467) @[dec_dec_ctl.scala 17:17] + node _T_476 = and(_T_475, _T_469) @[dec_dec_ctl.scala 17:17] + node _T_477 = or(_T_454, _T_476) @[dec_dec_ctl.scala 50:74] + io.out.add <= _T_477 @[dec_dec_ctl.scala 50:14] + node _T_478 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_479 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_480 = eq(_T_479, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_481 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_482 = eq(_T_481, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_483 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_485 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_486 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_487 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_489 = and(_T_478, _T_480) @[dec_dec_ctl.scala 17:17] + node _T_490 = and(_T_489, _T_482) @[dec_dec_ctl.scala 17:17] + node _T_491 = and(_T_490, _T_484) @[dec_dec_ctl.scala 17:17] + node _T_492 = and(_T_491, _T_485) @[dec_dec_ctl.scala 17:17] + node _T_493 = and(_T_492, _T_486) @[dec_dec_ctl.scala 17:17] + node _T_494 = and(_T_493, _T_488) @[dec_dec_ctl.scala 17:17] + node _T_495 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_496 = eq(_T_495, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_497 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_498 = eq(_T_497, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_499 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_500 = eq(_T_499, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_501 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_502 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_503 = eq(_T_502, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_504 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_505 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_506 = eq(_T_505, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_507 = and(_T_496, _T_498) @[dec_dec_ctl.scala 17:17] + node _T_508 = and(_T_507, _T_500) @[dec_dec_ctl.scala 17:17] + node _T_509 = and(_T_508, _T_501) @[dec_dec_ctl.scala 17:17] + node _T_510 = and(_T_509, _T_503) @[dec_dec_ctl.scala 17:17] + node _T_511 = and(_T_510, _T_504) @[dec_dec_ctl.scala 17:17] + node _T_512 = and(_T_511, _T_506) @[dec_dec_ctl.scala 17:17] + node _T_513 = or(_T_494, _T_512) @[dec_dec_ctl.scala 52:53] + node _T_514 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_515 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_516 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_517 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_518 = eq(_T_517, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_519 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_520 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_521 = eq(_T_520, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_522 = and(_T_514, _T_515) @[dec_dec_ctl.scala 17:17] + node _T_523 = and(_T_522, _T_516) @[dec_dec_ctl.scala 17:17] + node _T_524 = and(_T_523, _T_518) @[dec_dec_ctl.scala 17:17] + node _T_525 = and(_T_524, _T_519) @[dec_dec_ctl.scala 17:17] + node _T_526 = and(_T_525, _T_521) @[dec_dec_ctl.scala 17:17] + node _T_527 = or(_T_513, _T_526) @[dec_dec_ctl.scala 52:93] + node _T_528 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_529 = eq(_T_528, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_530 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_531 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_533 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_534 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_536 = and(_T_529, _T_530) @[dec_dec_ctl.scala 17:17] + node _T_537 = and(_T_536, _T_532) @[dec_dec_ctl.scala 17:17] + node _T_538 = and(_T_537, _T_533) @[dec_dec_ctl.scala 17:17] + node _T_539 = and(_T_538, _T_535) @[dec_dec_ctl.scala 17:17] + node _T_540 = or(_T_527, _T_539) @[dec_dec_ctl.scala 53:37] + node _T_541 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_542 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_543 = eq(_T_542, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_544 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_545 = eq(_T_544, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_546 = and(_T_541, _T_543) @[dec_dec_ctl.scala 17:17] + node _T_547 = and(_T_546, _T_545) @[dec_dec_ctl.scala 17:17] + node _T_548 = or(_T_540, _T_547) @[dec_dec_ctl.scala 53:69] + io.out.sub <= _T_548 @[dec_dec_ctl.scala 52:14] + node _T_549 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_550 = eq(_T_549, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_551 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_552 = eq(_T_551, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_553 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_554 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_555 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_556 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_557 = eq(_T_556, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_558 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_560 = and(_T_550, _T_552) @[dec_dec_ctl.scala 17:17] + node _T_561 = and(_T_560, _T_553) @[dec_dec_ctl.scala 17:17] + node _T_562 = and(_T_561, _T_554) @[dec_dec_ctl.scala 17:17] + node _T_563 = and(_T_562, _T_555) @[dec_dec_ctl.scala 17:17] + node _T_564 = and(_T_563, _T_557) @[dec_dec_ctl.scala 17:17] + node _T_565 = and(_T_564, _T_559) @[dec_dec_ctl.scala 17:17] + node _T_566 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_567 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_568 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_569 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_570 = eq(_T_569, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_571 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_572 = eq(_T_571, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_573 = and(_T_566, _T_567) @[dec_dec_ctl.scala 17:17] + node _T_574 = and(_T_573, _T_568) @[dec_dec_ctl.scala 17:17] + node _T_575 = and(_T_574, _T_570) @[dec_dec_ctl.scala 17:17] + node _T_576 = and(_T_575, _T_572) @[dec_dec_ctl.scala 17:17] + node _T_577 = or(_T_565, _T_576) @[dec_dec_ctl.scala 55:56] + io.out.land <= _T_577 @[dec_dec_ctl.scala 55:15] + node _T_578 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_579 = eq(_T_578, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_580 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_581 = and(_T_579, _T_580) @[dec_dec_ctl.scala 17:17] + node _T_582 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_583 = eq(_T_582, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_584 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_585 = eq(_T_584, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_586 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_587 = eq(_T_586, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_588 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_589 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_590 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_591 = eq(_T_590, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_592 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_593 = eq(_T_592, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_594 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_595 = eq(_T_594, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_596 = and(_T_583, _T_585) @[dec_dec_ctl.scala 17:17] + node _T_597 = and(_T_596, _T_587) @[dec_dec_ctl.scala 17:17] + node _T_598 = and(_T_597, _T_588) @[dec_dec_ctl.scala 17:17] + node _T_599 = and(_T_598, _T_589) @[dec_dec_ctl.scala 17:17] + node _T_600 = and(_T_599, _T_591) @[dec_dec_ctl.scala 17:17] + node _T_601 = and(_T_600, _T_593) @[dec_dec_ctl.scala 17:17] + node _T_602 = and(_T_601, _T_595) @[dec_dec_ctl.scala 17:17] + node _T_603 = or(_T_581, _T_602) @[dec_dec_ctl.scala 57:37] + node _T_604 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_605 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_606 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_607 = and(_T_604, _T_605) @[dec_dec_ctl.scala 17:17] + node _T_608 = and(_T_607, _T_606) @[dec_dec_ctl.scala 17:17] + node _T_609 = or(_T_603, _T_608) @[dec_dec_ctl.scala 57:82] + node _T_610 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_611 = eq(_T_610, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_612 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_613 = eq(_T_612, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_614 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_615 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_616 = and(_T_611, _T_613) @[dec_dec_ctl.scala 17:17] + node _T_617 = and(_T_616, _T_614) @[dec_dec_ctl.scala 17:17] + node _T_618 = and(_T_617, _T_615) @[dec_dec_ctl.scala 17:17] + node _T_619 = or(_T_609, _T_618) @[dec_dec_ctl.scala 57:105] + node _T_620 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_621 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_622 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_623 = eq(_T_622, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_624 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_625 = eq(_T_624, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_626 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_627 = eq(_T_626, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_628 = and(_T_620, _T_621) @[dec_dec_ctl.scala 17:17] + node _T_629 = and(_T_628, _T_623) @[dec_dec_ctl.scala 17:17] + node _T_630 = and(_T_629, _T_625) @[dec_dec_ctl.scala 17:17] + node _T_631 = and(_T_630, _T_627) @[dec_dec_ctl.scala 17:17] + node _T_632 = or(_T_619, _T_631) @[dec_dec_ctl.scala 58:32] + io.out.lor <= _T_632 @[dec_dec_ctl.scala 57:14] + node _T_633 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_634 = eq(_T_633, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_635 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_636 = eq(_T_635, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_637 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_638 = eq(_T_637, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_639 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_640 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_641 = eq(_T_640, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_642 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_643 = eq(_T_642, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_644 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_645 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_646 = eq(_T_645, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_647 = and(_T_634, _T_636) @[dec_dec_ctl.scala 17:17] + node _T_648 = and(_T_647, _T_638) @[dec_dec_ctl.scala 17:17] + node _T_649 = and(_T_648, _T_639) @[dec_dec_ctl.scala 17:17] + node _T_650 = and(_T_649, _T_641) @[dec_dec_ctl.scala 17:17] + node _T_651 = and(_T_650, _T_643) @[dec_dec_ctl.scala 17:17] + node _T_652 = and(_T_651, _T_644) @[dec_dec_ctl.scala 17:17] + node _T_653 = and(_T_652, _T_646) @[dec_dec_ctl.scala 17:17] + node _T_654 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_655 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_656 = eq(_T_655, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_657 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_658 = eq(_T_657, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_659 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_660 = eq(_T_659, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_661 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_662 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_663 = eq(_T_662, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_664 = and(_T_654, _T_656) @[dec_dec_ctl.scala 17:17] + node _T_665 = and(_T_664, _T_658) @[dec_dec_ctl.scala 17:17] + node _T_666 = and(_T_665, _T_660) @[dec_dec_ctl.scala 17:17] + node _T_667 = and(_T_666, _T_661) @[dec_dec_ctl.scala 17:17] + node _T_668 = and(_T_667, _T_663) @[dec_dec_ctl.scala 17:17] + node _T_669 = or(_T_653, _T_668) @[dec_dec_ctl.scala 60:61] + io.out.lxor <= _T_669 @[dec_dec_ctl.scala 60:15] + node _T_670 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_671 = eq(_T_670, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_672 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_673 = eq(_T_672, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_674 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_675 = eq(_T_674, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_676 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_677 = eq(_T_676, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_678 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_679 = eq(_T_678, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_680 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_681 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_682 = eq(_T_681, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_683 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_684 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_685 = eq(_T_684, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_686 = and(_T_671, _T_673) @[dec_dec_ctl.scala 17:17] + node _T_687 = and(_T_686, _T_675) @[dec_dec_ctl.scala 17:17] + node _T_688 = and(_T_687, _T_677) @[dec_dec_ctl.scala 17:17] + node _T_689 = and(_T_688, _T_679) @[dec_dec_ctl.scala 17:17] + node _T_690 = and(_T_689, _T_680) @[dec_dec_ctl.scala 17:17] + node _T_691 = and(_T_690, _T_682) @[dec_dec_ctl.scala 17:17] + node _T_692 = and(_T_691, _T_683) @[dec_dec_ctl.scala 17:17] + node _T_693 = and(_T_692, _T_685) @[dec_dec_ctl.scala 17:17] + io.out.sll <= _T_693 @[dec_dec_ctl.scala 62:14] + node _T_694 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_695 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_696 = eq(_T_695, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_697 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_698 = eq(_T_697, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_699 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_700 = eq(_T_699, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_701 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_702 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_703 = eq(_T_702, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_704 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_705 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_706 = eq(_T_705, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_707 = and(_T_694, _T_696) @[dec_dec_ctl.scala 17:17] + node _T_708 = and(_T_707, _T_698) @[dec_dec_ctl.scala 17:17] + node _T_709 = and(_T_708, _T_700) @[dec_dec_ctl.scala 17:17] + node _T_710 = and(_T_709, _T_701) @[dec_dec_ctl.scala 17:17] + node _T_711 = and(_T_710, _T_703) @[dec_dec_ctl.scala 17:17] + node _T_712 = and(_T_711, _T_704) @[dec_dec_ctl.scala 17:17] + node _T_713 = and(_T_712, _T_706) @[dec_dec_ctl.scala 17:17] + io.out.sra <= _T_713 @[dec_dec_ctl.scala 64:14] + node _T_714 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_715 = eq(_T_714, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_716 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_717 = eq(_T_716, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_718 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_719 = eq(_T_718, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_720 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_721 = eq(_T_720, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_722 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_723 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_724 = eq(_T_723, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_725 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_726 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_727 = eq(_T_726, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_728 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_729 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_730 = eq(_T_729, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_731 = and(_T_715, _T_717) @[dec_dec_ctl.scala 17:17] + node _T_732 = and(_T_731, _T_719) @[dec_dec_ctl.scala 17:17] + node _T_733 = and(_T_732, _T_721) @[dec_dec_ctl.scala 17:17] + node _T_734 = and(_T_733, _T_722) @[dec_dec_ctl.scala 17:17] + node _T_735 = and(_T_734, _T_724) @[dec_dec_ctl.scala 17:17] + node _T_736 = and(_T_735, _T_725) @[dec_dec_ctl.scala 17:17] + node _T_737 = and(_T_736, _T_727) @[dec_dec_ctl.scala 17:17] + node _T_738 = and(_T_737, _T_728) @[dec_dec_ctl.scala 17:17] + node _T_739 = and(_T_738, _T_730) @[dec_dec_ctl.scala 17:17] + io.out.srl <= _T_739 @[dec_dec_ctl.scala 66:14] + node _T_740 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_741 = eq(_T_740, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_742 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_743 = eq(_T_742, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_744 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_745 = eq(_T_744, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_746 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_747 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_748 = eq(_T_747, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_749 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_750 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_751 = eq(_T_750, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_752 = and(_T_741, _T_743) @[dec_dec_ctl.scala 17:17] + node _T_753 = and(_T_752, _T_745) @[dec_dec_ctl.scala 17:17] + node _T_754 = and(_T_753, _T_746) @[dec_dec_ctl.scala 17:17] + node _T_755 = and(_T_754, _T_748) @[dec_dec_ctl.scala 17:17] + node _T_756 = and(_T_755, _T_749) @[dec_dec_ctl.scala 17:17] + node _T_757 = and(_T_756, _T_751) @[dec_dec_ctl.scala 17:17] + node _T_758 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_759 = eq(_T_758, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_760 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_761 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_762 = eq(_T_761, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_763 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_764 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_765 = eq(_T_764, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_766 = and(_T_759, _T_760) @[dec_dec_ctl.scala 17:17] + node _T_767 = and(_T_766, _T_762) @[dec_dec_ctl.scala 17:17] + node _T_768 = and(_T_767, _T_763) @[dec_dec_ctl.scala 17:17] + node _T_769 = and(_T_768, _T_765) @[dec_dec_ctl.scala 17:17] + node _T_770 = or(_T_757, _T_769) @[dec_dec_ctl.scala 68:55] + io.out.slt <= _T_770 @[dec_dec_ctl.scala 68:14] + node _T_771 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_773 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_774 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_775 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_776 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_778 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_779 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_780 = eq(_T_779, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_781 = and(_T_772, _T_773) @[dec_dec_ctl.scala 17:17] + node _T_782 = and(_T_781, _T_774) @[dec_dec_ctl.scala 17:17] + node _T_783 = and(_T_782, _T_775) @[dec_dec_ctl.scala 17:17] + node _T_784 = and(_T_783, _T_777) @[dec_dec_ctl.scala 17:17] + node _T_785 = and(_T_784, _T_778) @[dec_dec_ctl.scala 17:17] + node _T_786 = and(_T_785, _T_780) @[dec_dec_ctl.scala 17:17] + node _T_787 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_788 = eq(_T_787, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_789 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_790 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_791 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_792 = eq(_T_791, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_793 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_794 = eq(_T_793, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_795 = and(_T_788, _T_789) @[dec_dec_ctl.scala 17:17] + node _T_796 = and(_T_795, _T_790) @[dec_dec_ctl.scala 17:17] + node _T_797 = and(_T_796, _T_792) @[dec_dec_ctl.scala 17:17] + node _T_798 = and(_T_797, _T_794) @[dec_dec_ctl.scala 17:17] + node _T_799 = or(_T_786, _T_798) @[dec_dec_ctl.scala 70:56] + node _T_800 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_801 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_802 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_803 = eq(_T_802, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_804 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_805 = eq(_T_804, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_806 = and(_T_800, _T_801) @[dec_dec_ctl.scala 17:17] + node _T_807 = and(_T_806, _T_803) @[dec_dec_ctl.scala 17:17] + node _T_808 = and(_T_807, _T_805) @[dec_dec_ctl.scala 17:17] + node _T_809 = or(_T_799, _T_808) @[dec_dec_ctl.scala 70:89] + node _T_810 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_811 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_813 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_814 = eq(_T_813, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_815 = and(_T_810, _T_812) @[dec_dec_ctl.scala 17:17] + node _T_816 = and(_T_815, _T_814) @[dec_dec_ctl.scala 17:17] + node _T_817 = or(_T_809, _T_816) @[dec_dec_ctl.scala 71:31] + node _T_818 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_819 = eq(_T_818, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_820 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_821 = eq(_T_820, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_822 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_823 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_824 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_825 = eq(_T_824, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_826 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_827 = eq(_T_826, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_828 = and(_T_819, _T_821) @[dec_dec_ctl.scala 17:17] + node _T_829 = and(_T_828, _T_822) @[dec_dec_ctl.scala 17:17] + node _T_830 = and(_T_829, _T_823) @[dec_dec_ctl.scala 17:17] + node _T_831 = and(_T_830, _T_825) @[dec_dec_ctl.scala 17:17] + node _T_832 = and(_T_831, _T_827) @[dec_dec_ctl.scala 17:17] + node _T_833 = or(_T_817, _T_832) @[dec_dec_ctl.scala 71:57] + node _T_834 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_835 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_836 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_837 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_838 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_840 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_841 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_842 = eq(_T_841, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_843 = and(_T_834, _T_835) @[dec_dec_ctl.scala 17:17] + node _T_844 = and(_T_843, _T_836) @[dec_dec_ctl.scala 17:17] + node _T_845 = and(_T_844, _T_837) @[dec_dec_ctl.scala 17:17] + node _T_846 = and(_T_845, _T_839) @[dec_dec_ctl.scala 17:17] + node _T_847 = and(_T_846, _T_840) @[dec_dec_ctl.scala 17:17] + node _T_848 = and(_T_847, _T_842) @[dec_dec_ctl.scala 17:17] + node _T_849 = or(_T_833, _T_848) @[dec_dec_ctl.scala 71:94] + io.out.unsign <= _T_849 @[dec_dec_ctl.scala 70:17] + node _T_850 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_851 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_852 = eq(_T_851, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_853 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_854 = eq(_T_853, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_855 = and(_T_850, _T_852) @[dec_dec_ctl.scala 17:17] + node _T_856 = and(_T_855, _T_854) @[dec_dec_ctl.scala 17:17] + io.out.condbr <= _T_856 @[dec_dec_ctl.scala 74:17] + node _T_857 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_858 = eq(_T_857, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_859 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_860 = eq(_T_859, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_861 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_862 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_863 = eq(_T_862, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_864 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_865 = eq(_T_864, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_866 = and(_T_858, _T_860) @[dec_dec_ctl.scala 17:17] + node _T_867 = and(_T_866, _T_861) @[dec_dec_ctl.scala 17:17] + node _T_868 = and(_T_867, _T_863) @[dec_dec_ctl.scala 17:17] + node _T_869 = and(_T_868, _T_865) @[dec_dec_ctl.scala 17:17] + io.out.beq <= _T_869 @[dec_dec_ctl.scala 76:14] + node _T_870 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_871 = eq(_T_870, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_872 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_873 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_874 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_875 = eq(_T_874, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_876 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_877 = eq(_T_876, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_878 = and(_T_871, _T_872) @[dec_dec_ctl.scala 17:17] + node _T_879 = and(_T_878, _T_873) @[dec_dec_ctl.scala 17:17] + node _T_880 = and(_T_879, _T_875) @[dec_dec_ctl.scala 17:17] + node _T_881 = and(_T_880, _T_877) @[dec_dec_ctl.scala 17:17] + io.out.bne <= _T_881 @[dec_dec_ctl.scala 78:14] + node _T_882 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_883 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_884 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_885 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_886 = eq(_T_885, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_887 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_888 = eq(_T_887, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_889 = and(_T_882, _T_883) @[dec_dec_ctl.scala 17:17] + node _T_890 = and(_T_889, _T_884) @[dec_dec_ctl.scala 17:17] + node _T_891 = and(_T_890, _T_886) @[dec_dec_ctl.scala 17:17] + node _T_892 = and(_T_891, _T_888) @[dec_dec_ctl.scala 17:17] + io.out.bge <= _T_892 @[dec_dec_ctl.scala 80:14] + node _T_893 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_894 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_896 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_897 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_898 = eq(_T_897, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_899 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_900 = eq(_T_899, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_901 = and(_T_893, _T_895) @[dec_dec_ctl.scala 17:17] + node _T_902 = and(_T_901, _T_896) @[dec_dec_ctl.scala 17:17] + node _T_903 = and(_T_902, _T_898) @[dec_dec_ctl.scala 17:17] + node _T_904 = and(_T_903, _T_900) @[dec_dec_ctl.scala 17:17] + io.out.blt <= _T_904 @[dec_dec_ctl.scala 82:14] + node _T_905 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_906 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_907 = and(_T_905, _T_906) @[dec_dec_ctl.scala 17:17] + io.out.jal <= _T_907 @[dec_dec_ctl.scala 84:14] + node _T_908 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_909 = eq(_T_908, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_910 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_911 = eq(_T_910, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_912 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_913 = eq(_T_912, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_914 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_915 = eq(_T_914, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_916 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_917 = eq(_T_916, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_918 = and(_T_909, _T_911) @[dec_dec_ctl.scala 17:17] + node _T_919 = and(_T_918, _T_913) @[dec_dec_ctl.scala 17:17] + node _T_920 = and(_T_919, _T_915) @[dec_dec_ctl.scala 17:17] + node _T_921 = and(_T_920, _T_917) @[dec_dec_ctl.scala 17:17] + io.out.by <= _T_921 @[dec_dec_ctl.scala 86:13] + node _T_922 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_923 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_924 = eq(_T_923, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_925 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_926 = eq(_T_925, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_927 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_928 = eq(_T_927, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_929 = and(_T_922, _T_924) @[dec_dec_ctl.scala 17:17] + node _T_930 = and(_T_929, _T_926) @[dec_dec_ctl.scala 17:17] + node _T_931 = and(_T_930, _T_928) @[dec_dec_ctl.scala 17:17] + io.out.half <= _T_931 @[dec_dec_ctl.scala 88:15] + node _T_932 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_933 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_934 = eq(_T_933, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_935 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_936 = eq(_T_935, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_937 = and(_T_932, _T_934) @[dec_dec_ctl.scala 17:17] + node _T_938 = and(_T_937, _T_936) @[dec_dec_ctl.scala 17:17] + io.out.word <= _T_938 @[dec_dec_ctl.scala 90:15] + node _T_939 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_940 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_941 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_942 = and(_T_939, _T_940) @[dec_dec_ctl.scala 17:17] + node _T_943 = and(_T_942, _T_941) @[dec_dec_ctl.scala 17:17] + node _T_944 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34] + node _T_945 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_946 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_947 = and(_T_944, _T_945) @[dec_dec_ctl.scala 17:17] + node _T_948 = and(_T_947, _T_946) @[dec_dec_ctl.scala 17:17] + node _T_949 = or(_T_943, _T_948) @[dec_dec_ctl.scala 92:44] + node _T_950 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34] + node _T_951 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_952 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_953 = and(_T_950, _T_951) @[dec_dec_ctl.scala 17:17] + node _T_954 = and(_T_953, _T_952) @[dec_dec_ctl.scala 17:17] + node _T_955 = or(_T_949, _T_954) @[dec_dec_ctl.scala 92:67] + node _T_956 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34] + node _T_957 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_958 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_959 = and(_T_956, _T_957) @[dec_dec_ctl.scala 17:17] + node _T_960 = and(_T_959, _T_958) @[dec_dec_ctl.scala 17:17] + node _T_961 = or(_T_955, _T_960) @[dec_dec_ctl.scala 92:90] + node _T_962 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34] + node _T_963 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_964 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_965 = and(_T_962, _T_963) @[dec_dec_ctl.scala 17:17] + node _T_966 = and(_T_965, _T_964) @[dec_dec_ctl.scala 17:17] + node _T_967 = or(_T_961, _T_966) @[dec_dec_ctl.scala 93:26] + node _T_968 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34] + node _T_969 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_970 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_971 = and(_T_968, _T_969) @[dec_dec_ctl.scala 17:17] + node _T_972 = and(_T_971, _T_970) @[dec_dec_ctl.scala 17:17] + node _T_973 = or(_T_967, _T_972) @[dec_dec_ctl.scala 93:50] + io.out.csr_read <= _T_973 @[dec_dec_ctl.scala 92:19] + node _T_974 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34] + node _T_975 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_976 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_977 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_978 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_979 = and(_T_974, _T_975) @[dec_dec_ctl.scala 17:17] + node _T_980 = and(_T_979, _T_976) @[dec_dec_ctl.scala 17:17] + node _T_981 = and(_T_980, _T_977) @[dec_dec_ctl.scala 17:17] + node _T_982 = and(_T_981, _T_978) @[dec_dec_ctl.scala 17:17] + node _T_983 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34] + node _T_984 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_985 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_986 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_987 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_988 = and(_T_983, _T_984) @[dec_dec_ctl.scala 17:17] + node _T_989 = and(_T_988, _T_985) @[dec_dec_ctl.scala 17:17] + node _T_990 = and(_T_989, _T_986) @[dec_dec_ctl.scala 17:17] + node _T_991 = and(_T_990, _T_987) @[dec_dec_ctl.scala 17:17] + node _T_992 = or(_T_982, _T_991) @[dec_dec_ctl.scala 95:49] + node _T_993 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34] + node _T_994 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_995 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_996 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_997 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_998 = and(_T_993, _T_994) @[dec_dec_ctl.scala 17:17] + node _T_999 = and(_T_998, _T_995) @[dec_dec_ctl.scala 17:17] + node _T_1000 = and(_T_999, _T_996) @[dec_dec_ctl.scala 17:17] + node _T_1001 = and(_T_1000, _T_997) @[dec_dec_ctl.scala 17:17] + node _T_1002 = or(_T_992, _T_1001) @[dec_dec_ctl.scala 95:79] + node _T_1003 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34] + node _T_1004 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1005 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1006 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1007 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1008 = and(_T_1003, _T_1004) @[dec_dec_ctl.scala 17:17] + node _T_1009 = and(_T_1008, _T_1005) @[dec_dec_ctl.scala 17:17] + node _T_1010 = and(_T_1009, _T_1006) @[dec_dec_ctl.scala 17:17] + node _T_1011 = and(_T_1010, _T_1007) @[dec_dec_ctl.scala 17:17] + node _T_1012 = or(_T_1002, _T_1011) @[dec_dec_ctl.scala 96:33] + node _T_1013 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34] + node _T_1014 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1015 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1016 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1017 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1018 = and(_T_1013, _T_1014) @[dec_dec_ctl.scala 17:17] + node _T_1019 = and(_T_1018, _T_1015) @[dec_dec_ctl.scala 17:17] + node _T_1020 = and(_T_1019, _T_1016) @[dec_dec_ctl.scala 17:17] + node _T_1021 = and(_T_1020, _T_1017) @[dec_dec_ctl.scala 17:17] + node _T_1022 = or(_T_1012, _T_1021) @[dec_dec_ctl.scala 96:63] + io.out.csr_clr <= _T_1022 @[dec_dec_ctl.scala 95:18] + node _T_1023 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34] + node _T_1024 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1026 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1027 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1028 = and(_T_1023, _T_1025) @[dec_dec_ctl.scala 17:17] + node _T_1029 = and(_T_1028, _T_1026) @[dec_dec_ctl.scala 17:17] + node _T_1030 = and(_T_1029, _T_1027) @[dec_dec_ctl.scala 17:17] + node _T_1031 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34] + node _T_1032 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1033 = eq(_T_1032, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1034 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1035 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1036 = and(_T_1031, _T_1033) @[dec_dec_ctl.scala 17:17] + node _T_1037 = and(_T_1036, _T_1034) @[dec_dec_ctl.scala 17:17] + node _T_1038 = and(_T_1037, _T_1035) @[dec_dec_ctl.scala 17:17] + node _T_1039 = or(_T_1030, _T_1038) @[dec_dec_ctl.scala 98:47] + node _T_1040 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34] + node _T_1041 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1042 = eq(_T_1041, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1043 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1044 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1045 = and(_T_1040, _T_1042) @[dec_dec_ctl.scala 17:17] + node _T_1046 = and(_T_1045, _T_1043) @[dec_dec_ctl.scala 17:17] + node _T_1047 = and(_T_1046, _T_1044) @[dec_dec_ctl.scala 17:17] + node _T_1048 = or(_T_1039, _T_1047) @[dec_dec_ctl.scala 98:75] + node _T_1049 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34] + node _T_1050 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1051 = eq(_T_1050, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1052 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1053 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1054 = and(_T_1049, _T_1051) @[dec_dec_ctl.scala 17:17] + node _T_1055 = and(_T_1054, _T_1052) @[dec_dec_ctl.scala 17:17] + node _T_1056 = and(_T_1055, _T_1053) @[dec_dec_ctl.scala 17:17] + node _T_1057 = or(_T_1048, _T_1056) @[dec_dec_ctl.scala 98:103] + node _T_1058 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34] + node _T_1059 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1060 = eq(_T_1059, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1061 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1062 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1063 = and(_T_1058, _T_1060) @[dec_dec_ctl.scala 17:17] + node _T_1064 = and(_T_1063, _T_1061) @[dec_dec_ctl.scala 17:17] + node _T_1065 = and(_T_1064, _T_1062) @[dec_dec_ctl.scala 17:17] + node _T_1066 = or(_T_1057, _T_1065) @[dec_dec_ctl.scala 99:31] + io.out.csr_set <= _T_1066 @[dec_dec_ctl.scala 98:18] + node _T_1067 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1068 = eq(_T_1067, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1069 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1070 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1071 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1072 = and(_T_1068, _T_1069) @[dec_dec_ctl.scala 17:17] + node _T_1073 = and(_T_1072, _T_1070) @[dec_dec_ctl.scala 17:17] + node _T_1074 = and(_T_1073, _T_1071) @[dec_dec_ctl.scala 17:17] + io.out.csr_write <= _T_1074 @[dec_dec_ctl.scala 101:20] + node _T_1075 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1076 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1077 = eq(_T_1076, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1078 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1079 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1080 = and(_T_1075, _T_1077) @[dec_dec_ctl.scala 17:17] + node _T_1081 = and(_T_1080, _T_1078) @[dec_dec_ctl.scala 17:17] + node _T_1082 = and(_T_1081, _T_1079) @[dec_dec_ctl.scala 17:17] + node _T_1083 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34] + node _T_1084 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1085 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1086 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1087 = and(_T_1083, _T_1084) @[dec_dec_ctl.scala 17:17] + node _T_1088 = and(_T_1087, _T_1085) @[dec_dec_ctl.scala 17:17] + node _T_1089 = and(_T_1088, _T_1086) @[dec_dec_ctl.scala 17:17] + node _T_1090 = or(_T_1082, _T_1089) @[dec_dec_ctl.scala 103:47] + node _T_1091 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34] + node _T_1092 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1093 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1094 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1095 = and(_T_1091, _T_1092) @[dec_dec_ctl.scala 17:17] + node _T_1096 = and(_T_1095, _T_1093) @[dec_dec_ctl.scala 17:17] + node _T_1097 = and(_T_1096, _T_1094) @[dec_dec_ctl.scala 17:17] + node _T_1098 = or(_T_1090, _T_1097) @[dec_dec_ctl.scala 103:74] + node _T_1099 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34] + node _T_1100 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1101 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1102 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1103 = and(_T_1099, _T_1100) @[dec_dec_ctl.scala 17:17] + node _T_1104 = and(_T_1103, _T_1101) @[dec_dec_ctl.scala 17:17] + node _T_1105 = and(_T_1104, _T_1102) @[dec_dec_ctl.scala 17:17] + node _T_1106 = or(_T_1098, _T_1105) @[dec_dec_ctl.scala 103:101] + node _T_1107 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34] + node _T_1108 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1109 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1110 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1111 = and(_T_1107, _T_1108) @[dec_dec_ctl.scala 17:17] + node _T_1112 = and(_T_1111, _T_1109) @[dec_dec_ctl.scala 17:17] + node _T_1113 = and(_T_1112, _T_1110) @[dec_dec_ctl.scala 17:17] + node _T_1114 = or(_T_1106, _T_1113) @[dec_dec_ctl.scala 104:30] + node _T_1115 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34] + node _T_1116 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1117 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1118 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1119 = and(_T_1115, _T_1116) @[dec_dec_ctl.scala 17:17] + node _T_1120 = and(_T_1119, _T_1117) @[dec_dec_ctl.scala 17:17] + node _T_1121 = and(_T_1120, _T_1118) @[dec_dec_ctl.scala 17:17] + node _T_1122 = or(_T_1114, _T_1121) @[dec_dec_ctl.scala 104:57] + io.out.csr_imm <= _T_1122 @[dec_dec_ctl.scala 103:18] + node _T_1123 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1124 = eq(_T_1123, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1125 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_1126 = and(_T_1124, _T_1125) @[dec_dec_ctl.scala 17:17] + node _T_1127 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1129 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34] + node _T_1130 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1131 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1132 = and(_T_1128, _T_1129) @[dec_dec_ctl.scala 17:17] + node _T_1133 = and(_T_1132, _T_1130) @[dec_dec_ctl.scala 17:17] + node _T_1134 = and(_T_1133, _T_1131) @[dec_dec_ctl.scala 17:17] + node _T_1135 = or(_T_1126, _T_1134) @[dec_dec_ctl.scala 106:41] + node _T_1136 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1137 = eq(_T_1136, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1138 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34] + node _T_1139 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1140 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1141 = and(_T_1137, _T_1138) @[dec_dec_ctl.scala 17:17] + node _T_1142 = and(_T_1141, _T_1139) @[dec_dec_ctl.scala 17:17] + node _T_1143 = and(_T_1142, _T_1140) @[dec_dec_ctl.scala 17:17] + node _T_1144 = or(_T_1135, _T_1143) @[dec_dec_ctl.scala 106:68] + node _T_1145 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1146 = eq(_T_1145, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1147 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34] + node _T_1148 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1149 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1150 = and(_T_1146, _T_1147) @[dec_dec_ctl.scala 17:17] + node _T_1151 = and(_T_1150, _T_1148) @[dec_dec_ctl.scala 17:17] + node _T_1152 = and(_T_1151, _T_1149) @[dec_dec_ctl.scala 17:17] + node _T_1153 = or(_T_1144, _T_1152) @[dec_dec_ctl.scala 106:95] + node _T_1154 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1155 = eq(_T_1154, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1156 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34] + node _T_1157 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1158 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1159 = and(_T_1155, _T_1156) @[dec_dec_ctl.scala 17:17] + node _T_1160 = and(_T_1159, _T_1157) @[dec_dec_ctl.scala 17:17] + node _T_1161 = and(_T_1160, _T_1158) @[dec_dec_ctl.scala 17:17] + node _T_1162 = or(_T_1153, _T_1161) @[dec_dec_ctl.scala 107:30] + node _T_1163 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1164 = eq(_T_1163, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1165 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34] + node _T_1166 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1167 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1168 = and(_T_1164, _T_1165) @[dec_dec_ctl.scala 17:17] + node _T_1169 = and(_T_1168, _T_1166) @[dec_dec_ctl.scala 17:17] + node _T_1170 = and(_T_1169, _T_1167) @[dec_dec_ctl.scala 17:17] + node _T_1171 = or(_T_1162, _T_1170) @[dec_dec_ctl.scala 107:58] + node _T_1172 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34] + node _T_1173 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1174 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1175 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1176 = and(_T_1172, _T_1173) @[dec_dec_ctl.scala 17:17] + node _T_1177 = and(_T_1176, _T_1174) @[dec_dec_ctl.scala 17:17] + node _T_1178 = and(_T_1177, _T_1175) @[dec_dec_ctl.scala 17:17] + node _T_1179 = or(_T_1171, _T_1178) @[dec_dec_ctl.scala 107:86] + node _T_1180 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34] + node _T_1181 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1182 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1183 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1184 = and(_T_1180, _T_1181) @[dec_dec_ctl.scala 17:17] + node _T_1185 = and(_T_1184, _T_1182) @[dec_dec_ctl.scala 17:17] + node _T_1186 = and(_T_1185, _T_1183) @[dec_dec_ctl.scala 17:17] + node _T_1187 = or(_T_1179, _T_1186) @[dec_dec_ctl.scala 108:30] + node _T_1188 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34] + node _T_1189 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1190 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1191 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1192 = and(_T_1188, _T_1189) @[dec_dec_ctl.scala 17:17] + node _T_1193 = and(_T_1192, _T_1190) @[dec_dec_ctl.scala 17:17] + node _T_1194 = and(_T_1193, _T_1191) @[dec_dec_ctl.scala 17:17] + node _T_1195 = or(_T_1187, _T_1194) @[dec_dec_ctl.scala 108:57] + node _T_1196 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34] + node _T_1197 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1198 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1199 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1200 = and(_T_1196, _T_1197) @[dec_dec_ctl.scala 17:17] + node _T_1201 = and(_T_1200, _T_1198) @[dec_dec_ctl.scala 17:17] + node _T_1202 = and(_T_1201, _T_1199) @[dec_dec_ctl.scala 17:17] + node _T_1203 = or(_T_1195, _T_1202) @[dec_dec_ctl.scala 108:84] + node _T_1204 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34] + node _T_1205 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1206 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1207 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1208 = and(_T_1204, _T_1205) @[dec_dec_ctl.scala 17:17] + node _T_1209 = and(_T_1208, _T_1206) @[dec_dec_ctl.scala 17:17] + node _T_1210 = and(_T_1209, _T_1207) @[dec_dec_ctl.scala 17:17] + node _T_1211 = or(_T_1203, _T_1210) @[dec_dec_ctl.scala 109:30] + io.out.presync <= _T_1211 @[dec_dec_ctl.scala 106:18] + node _T_1212 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1213 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1215 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_1216 = and(_T_1212, _T_1214) @[dec_dec_ctl.scala 17:17] + node _T_1217 = and(_T_1216, _T_1215) @[dec_dec_ctl.scala 17:17] + node _T_1218 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_1219 = eq(_T_1218, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1220 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1221 = eq(_T_1220, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1222 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1223 = eq(_T_1222, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1224 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1225 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1226 = and(_T_1219, _T_1221) @[dec_dec_ctl.scala 17:17] + node _T_1227 = and(_T_1226, _T_1223) @[dec_dec_ctl.scala 17:17] + node _T_1228 = and(_T_1227, _T_1224) @[dec_dec_ctl.scala 17:17] + node _T_1229 = and(_T_1228, _T_1225) @[dec_dec_ctl.scala 17:17] + node _T_1230 = or(_T_1217, _T_1229) @[dec_dec_ctl.scala 111:45] + node _T_1231 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1233 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34] + node _T_1234 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1235 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1236 = and(_T_1232, _T_1233) @[dec_dec_ctl.scala 17:17] + node _T_1237 = and(_T_1236, _T_1234) @[dec_dec_ctl.scala 17:17] + node _T_1238 = and(_T_1237, _T_1235) @[dec_dec_ctl.scala 17:17] + node _T_1239 = or(_T_1230, _T_1238) @[dec_dec_ctl.scala 111:78] + node _T_1240 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1241 = eq(_T_1240, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1242 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34] + node _T_1243 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1244 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1245 = and(_T_1241, _T_1242) @[dec_dec_ctl.scala 17:17] + node _T_1246 = and(_T_1245, _T_1243) @[dec_dec_ctl.scala 17:17] + node _T_1247 = and(_T_1246, _T_1244) @[dec_dec_ctl.scala 17:17] + node _T_1248 = or(_T_1239, _T_1247) @[dec_dec_ctl.scala 112:30] + node _T_1249 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1250 = eq(_T_1249, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1251 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34] + node _T_1252 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1253 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1254 = and(_T_1250, _T_1251) @[dec_dec_ctl.scala 17:17] + node _T_1255 = and(_T_1254, _T_1252) @[dec_dec_ctl.scala 17:17] + node _T_1256 = and(_T_1255, _T_1253) @[dec_dec_ctl.scala 17:17] + node _T_1257 = or(_T_1248, _T_1256) @[dec_dec_ctl.scala 112:57] + node _T_1258 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1259 = eq(_T_1258, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1260 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34] + node _T_1261 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1262 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1263 = and(_T_1259, _T_1260) @[dec_dec_ctl.scala 17:17] + node _T_1264 = and(_T_1263, _T_1261) @[dec_dec_ctl.scala 17:17] + node _T_1265 = and(_T_1264, _T_1262) @[dec_dec_ctl.scala 17:17] + node _T_1266 = or(_T_1257, _T_1265) @[dec_dec_ctl.scala 112:84] + node _T_1267 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1268 = eq(_T_1267, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1269 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34] + node _T_1270 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1271 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1272 = and(_T_1268, _T_1269) @[dec_dec_ctl.scala 17:17] + node _T_1273 = and(_T_1272, _T_1270) @[dec_dec_ctl.scala 17:17] + node _T_1274 = and(_T_1273, _T_1271) @[dec_dec_ctl.scala 17:17] + node _T_1275 = or(_T_1266, _T_1274) @[dec_dec_ctl.scala 112:112] + node _T_1276 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34] + node _T_1277 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1278 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1279 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1280 = and(_T_1276, _T_1277) @[dec_dec_ctl.scala 17:17] + node _T_1281 = and(_T_1280, _T_1278) @[dec_dec_ctl.scala 17:17] + node _T_1282 = and(_T_1281, _T_1279) @[dec_dec_ctl.scala 17:17] + node _T_1283 = or(_T_1275, _T_1282) @[dec_dec_ctl.scala 113:31] + node _T_1284 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34] + node _T_1285 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1286 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1287 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1288 = and(_T_1284, _T_1285) @[dec_dec_ctl.scala 17:17] + node _T_1289 = and(_T_1288, _T_1286) @[dec_dec_ctl.scala 17:17] + node _T_1290 = and(_T_1289, _T_1287) @[dec_dec_ctl.scala 17:17] + node _T_1291 = or(_T_1283, _T_1290) @[dec_dec_ctl.scala 113:58] + node _T_1292 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34] + node _T_1293 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1294 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1295 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1296 = and(_T_1292, _T_1293) @[dec_dec_ctl.scala 17:17] + node _T_1297 = and(_T_1296, _T_1294) @[dec_dec_ctl.scala 17:17] + node _T_1298 = and(_T_1297, _T_1295) @[dec_dec_ctl.scala 17:17] + node _T_1299 = or(_T_1291, _T_1298) @[dec_dec_ctl.scala 113:85] + node _T_1300 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34] + node _T_1301 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1302 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1303 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1304 = and(_T_1300, _T_1301) @[dec_dec_ctl.scala 17:17] + node _T_1305 = and(_T_1304, _T_1302) @[dec_dec_ctl.scala 17:17] + node _T_1306 = and(_T_1305, _T_1303) @[dec_dec_ctl.scala 17:17] + node _T_1307 = or(_T_1299, _T_1306) @[dec_dec_ctl.scala 113:112] + node _T_1308 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34] + node _T_1309 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1310 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1311 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1312 = and(_T_1308, _T_1309) @[dec_dec_ctl.scala 17:17] + node _T_1313 = and(_T_1312, _T_1310) @[dec_dec_ctl.scala 17:17] + node _T_1314 = and(_T_1313, _T_1311) @[dec_dec_ctl.scala 17:17] + node _T_1315 = or(_T_1307, _T_1314) @[dec_dec_ctl.scala 114:30] + io.out.postsync <= _T_1315 @[dec_dec_ctl.scala 111:19] + node _T_1316 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_1317 = eq(_T_1316, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1318 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_1319 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1320 = eq(_T_1319, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1321 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1322 = eq(_T_1321, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1323 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1324 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1325 = and(_T_1317, _T_1318) @[dec_dec_ctl.scala 17:17] + node _T_1326 = and(_T_1325, _T_1320) @[dec_dec_ctl.scala 17:17] + node _T_1327 = and(_T_1326, _T_1322) @[dec_dec_ctl.scala 17:17] + node _T_1328 = and(_T_1327, _T_1323) @[dec_dec_ctl.scala 17:17] + node _T_1329 = and(_T_1328, _T_1324) @[dec_dec_ctl.scala 17:17] + io.out.ebreak <= _T_1329 @[dec_dec_ctl.scala 116:17] + node _T_1330 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_1331 = eq(_T_1330, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1332 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1334 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1336 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1337 = eq(_T_1336, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1338 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1339 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1340 = and(_T_1331, _T_1333) @[dec_dec_ctl.scala 17:17] + node _T_1341 = and(_T_1340, _T_1335) @[dec_dec_ctl.scala 17:17] + node _T_1342 = and(_T_1341, _T_1337) @[dec_dec_ctl.scala 17:17] + node _T_1343 = and(_T_1342, _T_1338) @[dec_dec_ctl.scala 17:17] + node _T_1344 = and(_T_1343, _T_1339) @[dec_dec_ctl.scala 17:17] + io.out.ecall <= _T_1344 @[dec_dec_ctl.scala 118:16] + node _T_1345 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1346 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1347 = eq(_T_1346, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1348 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1349 = eq(_T_1348, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1350 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1351 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1352 = and(_T_1345, _T_1347) @[dec_dec_ctl.scala 17:17] + node _T_1353 = and(_T_1352, _T_1349) @[dec_dec_ctl.scala 17:17] + node _T_1354 = and(_T_1353, _T_1350) @[dec_dec_ctl.scala 17:17] + node _T_1355 = and(_T_1354, _T_1351) @[dec_dec_ctl.scala 17:17] + io.out.mret <= _T_1355 @[dec_dec_ctl.scala 120:15] + node _T_1356 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_1357 = eq(_T_1356, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1358 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1359 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_1360 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_1361 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1362 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1363 = eq(_T_1362, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1364 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1365 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1366 = eq(_T_1365, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1367 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1368 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1369 = eq(_T_1368, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1370 = and(_T_1357, _T_1358) @[dec_dec_ctl.scala 17:17] + node _T_1371 = and(_T_1370, _T_1359) @[dec_dec_ctl.scala 17:17] + node _T_1372 = and(_T_1371, _T_1360) @[dec_dec_ctl.scala 17:17] + node _T_1373 = and(_T_1372, _T_1361) @[dec_dec_ctl.scala 17:17] + node _T_1374 = and(_T_1373, _T_1363) @[dec_dec_ctl.scala 17:17] + node _T_1375 = and(_T_1374, _T_1364) @[dec_dec_ctl.scala 17:17] + node _T_1376 = and(_T_1375, _T_1366) @[dec_dec_ctl.scala 17:17] + node _T_1377 = and(_T_1376, _T_1367) @[dec_dec_ctl.scala 17:17] + node _T_1378 = and(_T_1377, _T_1369) @[dec_dec_ctl.scala 17:17] + node _T_1379 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1380 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1381 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_1382 = eq(_T_1381, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1383 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_1384 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1385 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1386 = eq(_T_1385, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1387 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1388 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1389 = eq(_T_1388, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1390 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1391 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1392 = eq(_T_1391, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1393 = and(_T_1379, _T_1380) @[dec_dec_ctl.scala 17:17] + node _T_1394 = and(_T_1393, _T_1382) @[dec_dec_ctl.scala 17:17] + node _T_1395 = and(_T_1394, _T_1383) @[dec_dec_ctl.scala 17:17] + node _T_1396 = and(_T_1395, _T_1384) @[dec_dec_ctl.scala 17:17] + node _T_1397 = and(_T_1396, _T_1386) @[dec_dec_ctl.scala 17:17] + node _T_1398 = and(_T_1397, _T_1387) @[dec_dec_ctl.scala 17:17] + node _T_1399 = and(_T_1398, _T_1389) @[dec_dec_ctl.scala 17:17] + node _T_1400 = and(_T_1399, _T_1390) @[dec_dec_ctl.scala 17:17] + node _T_1401 = and(_T_1400, _T_1392) @[dec_dec_ctl.scala 17:17] + node _T_1402 = or(_T_1378, _T_1401) @[dec_dec_ctl.scala 122:63] + node _T_1403 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1404 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1405 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_1406 = eq(_T_1405, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1407 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_1408 = eq(_T_1407, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1409 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1410 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1411 = eq(_T_1410, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1412 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1413 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1414 = eq(_T_1413, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1415 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1416 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1417 = eq(_T_1416, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1418 = and(_T_1403, _T_1404) @[dec_dec_ctl.scala 17:17] + node _T_1419 = and(_T_1418, _T_1406) @[dec_dec_ctl.scala 17:17] + node _T_1420 = and(_T_1419, _T_1408) @[dec_dec_ctl.scala 17:17] + node _T_1421 = and(_T_1420, _T_1409) @[dec_dec_ctl.scala 17:17] + node _T_1422 = and(_T_1421, _T_1411) @[dec_dec_ctl.scala 17:17] + node _T_1423 = and(_T_1422, _T_1412) @[dec_dec_ctl.scala 17:17] + node _T_1424 = and(_T_1423, _T_1414) @[dec_dec_ctl.scala 17:17] + node _T_1425 = and(_T_1424, _T_1415) @[dec_dec_ctl.scala 17:17] + node _T_1426 = and(_T_1425, _T_1417) @[dec_dec_ctl.scala 17:17] + node _T_1427 = or(_T_1402, _T_1426) @[dec_dec_ctl.scala 122:111] + node _T_1428 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1429 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_1430 = eq(_T_1429, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1431 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1432 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1434 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1435 = eq(_T_1434, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1436 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1437 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1438 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1440 = and(_T_1428, _T_1430) @[dec_dec_ctl.scala 17:17] + node _T_1441 = and(_T_1440, _T_1431) @[dec_dec_ctl.scala 17:17] + node _T_1442 = and(_T_1441, _T_1433) @[dec_dec_ctl.scala 17:17] + node _T_1443 = and(_T_1442, _T_1435) @[dec_dec_ctl.scala 17:17] + node _T_1444 = and(_T_1443, _T_1436) @[dec_dec_ctl.scala 17:17] + node _T_1445 = and(_T_1444, _T_1437) @[dec_dec_ctl.scala 17:17] + node _T_1446 = and(_T_1445, _T_1439) @[dec_dec_ctl.scala 17:17] + node _T_1447 = or(_T_1427, _T_1446) @[dec_dec_ctl.scala 123:52] + node _T_1448 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1449 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1450 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1451 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1452 = eq(_T_1451, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1453 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1454 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1455 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1456 = eq(_T_1455, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1457 = and(_T_1448, _T_1449) @[dec_dec_ctl.scala 17:17] + node _T_1458 = and(_T_1457, _T_1450) @[dec_dec_ctl.scala 17:17] + node _T_1459 = and(_T_1458, _T_1452) @[dec_dec_ctl.scala 17:17] + node _T_1460 = and(_T_1459, _T_1453) @[dec_dec_ctl.scala 17:17] + node _T_1461 = and(_T_1460, _T_1454) @[dec_dec_ctl.scala 17:17] + node _T_1462 = and(_T_1461, _T_1456) @[dec_dec_ctl.scala 17:17] + node _T_1463 = or(_T_1447, _T_1462) @[dec_dec_ctl.scala 123:93] + node _T_1464 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1465 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1466 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_1467 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1469 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1470 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1471 = eq(_T_1470, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1472 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1473 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1474 = eq(_T_1473, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1475 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1476 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1477 = eq(_T_1476, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1478 = and(_T_1464, _T_1465) @[dec_dec_ctl.scala 17:17] + node _T_1479 = and(_T_1478, _T_1466) @[dec_dec_ctl.scala 17:17] + node _T_1480 = and(_T_1479, _T_1468) @[dec_dec_ctl.scala 17:17] + node _T_1481 = and(_T_1480, _T_1469) @[dec_dec_ctl.scala 17:17] + node _T_1482 = and(_T_1481, _T_1471) @[dec_dec_ctl.scala 17:17] + node _T_1483 = and(_T_1482, _T_1472) @[dec_dec_ctl.scala 17:17] + node _T_1484 = and(_T_1483, _T_1474) @[dec_dec_ctl.scala 17:17] + node _T_1485 = and(_T_1484, _T_1475) @[dec_dec_ctl.scala 17:17] + node _T_1486 = and(_T_1485, _T_1477) @[dec_dec_ctl.scala 17:17] + node _T_1487 = or(_T_1463, _T_1486) @[dec_dec_ctl.scala 124:39] + node _T_1488 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1489 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1490 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1492 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_1493 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1494 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1495 = eq(_T_1494, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1496 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1497 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1498 = eq(_T_1497, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1499 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1500 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1501 = eq(_T_1500, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1502 = and(_T_1488, _T_1489) @[dec_dec_ctl.scala 17:17] + node _T_1503 = and(_T_1502, _T_1491) @[dec_dec_ctl.scala 17:17] + node _T_1504 = and(_T_1503, _T_1492) @[dec_dec_ctl.scala 17:17] + node _T_1505 = and(_T_1504, _T_1493) @[dec_dec_ctl.scala 17:17] + node _T_1506 = and(_T_1505, _T_1495) @[dec_dec_ctl.scala 17:17] + node _T_1507 = and(_T_1506, _T_1496) @[dec_dec_ctl.scala 17:17] + node _T_1508 = and(_T_1507, _T_1498) @[dec_dec_ctl.scala 17:17] + node _T_1509 = and(_T_1508, _T_1499) @[dec_dec_ctl.scala 17:17] + node _T_1510 = and(_T_1509, _T_1501) @[dec_dec_ctl.scala 17:17] + node _T_1511 = or(_T_1487, _T_1510) @[dec_dec_ctl.scala 124:87] + node _T_1512 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1513 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1514 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1516 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_1517 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1518 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1520 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1521 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1522 = eq(_T_1521, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1523 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1524 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1525 = eq(_T_1524, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1526 = and(_T_1512, _T_1513) @[dec_dec_ctl.scala 17:17] + node _T_1527 = and(_T_1526, _T_1515) @[dec_dec_ctl.scala 17:17] + node _T_1528 = and(_T_1527, _T_1516) @[dec_dec_ctl.scala 17:17] + node _T_1529 = and(_T_1528, _T_1517) @[dec_dec_ctl.scala 17:17] + node _T_1530 = and(_T_1529, _T_1519) @[dec_dec_ctl.scala 17:17] + node _T_1531 = and(_T_1530, _T_1520) @[dec_dec_ctl.scala 17:17] + node _T_1532 = and(_T_1531, _T_1522) @[dec_dec_ctl.scala 17:17] + node _T_1533 = and(_T_1532, _T_1523) @[dec_dec_ctl.scala 17:17] + node _T_1534 = and(_T_1533, _T_1525) @[dec_dec_ctl.scala 17:17] + node _T_1535 = or(_T_1511, _T_1534) @[dec_dec_ctl.scala 125:51] + node _T_1536 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1537 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1538 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1539 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_1540 = eq(_T_1539, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1541 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1542 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1543 = eq(_T_1542, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1544 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1545 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1546 = eq(_T_1545, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1547 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1548 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1549 = eq(_T_1548, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1550 = and(_T_1536, _T_1537) @[dec_dec_ctl.scala 17:17] + node _T_1551 = and(_T_1550, _T_1538) @[dec_dec_ctl.scala 17:17] + node _T_1552 = and(_T_1551, _T_1540) @[dec_dec_ctl.scala 17:17] + node _T_1553 = and(_T_1552, _T_1541) @[dec_dec_ctl.scala 17:17] + node _T_1554 = and(_T_1553, _T_1543) @[dec_dec_ctl.scala 17:17] + node _T_1555 = and(_T_1554, _T_1544) @[dec_dec_ctl.scala 17:17] + node _T_1556 = and(_T_1555, _T_1546) @[dec_dec_ctl.scala 17:17] + node _T_1557 = and(_T_1556, _T_1547) @[dec_dec_ctl.scala 17:17] + node _T_1558 = and(_T_1557, _T_1549) @[dec_dec_ctl.scala 17:17] + node _T_1559 = or(_T_1535, _T_1558) @[dec_dec_ctl.scala 125:99] + node _T_1560 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_1561 = eq(_T_1560, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1562 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1563 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_1564 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1565 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1566 = eq(_T_1565, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1567 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1568 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1569 = eq(_T_1568, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1570 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1571 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1573 = and(_T_1561, _T_1562) @[dec_dec_ctl.scala 17:17] + node _T_1574 = and(_T_1573, _T_1563) @[dec_dec_ctl.scala 17:17] + node _T_1575 = and(_T_1574, _T_1564) @[dec_dec_ctl.scala 17:17] + node _T_1576 = and(_T_1575, _T_1566) @[dec_dec_ctl.scala 17:17] + node _T_1577 = and(_T_1576, _T_1567) @[dec_dec_ctl.scala 17:17] + node _T_1578 = and(_T_1577, _T_1569) @[dec_dec_ctl.scala 17:17] + node _T_1579 = and(_T_1578, _T_1570) @[dec_dec_ctl.scala 17:17] + node _T_1580 = and(_T_1579, _T_1572) @[dec_dec_ctl.scala 17:17] + node _T_1581 = or(_T_1559, _T_1580) @[dec_dec_ctl.scala 126:51] + node _T_1582 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_1583 = eq(_T_1582, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1584 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_1585 = eq(_T_1584, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1586 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1587 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_1588 = eq(_T_1587, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1589 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1590 = eq(_T_1589, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1591 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1592 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1593 = eq(_T_1592, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1594 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1595 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1596 = eq(_T_1595, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1597 = and(_T_1583, _T_1585) @[dec_dec_ctl.scala 17:17] + node _T_1598 = and(_T_1597, _T_1586) @[dec_dec_ctl.scala 17:17] + node _T_1599 = and(_T_1598, _T_1588) @[dec_dec_ctl.scala 17:17] + node _T_1600 = and(_T_1599, _T_1590) @[dec_dec_ctl.scala 17:17] + node _T_1601 = and(_T_1600, _T_1591) @[dec_dec_ctl.scala 17:17] + node _T_1602 = and(_T_1601, _T_1593) @[dec_dec_ctl.scala 17:17] + node _T_1603 = and(_T_1602, _T_1594) @[dec_dec_ctl.scala 17:17] + node _T_1604 = and(_T_1603, _T_1596) @[dec_dec_ctl.scala 17:17] + node _T_1605 = or(_T_1581, _T_1604) @[dec_dec_ctl.scala 126:96] + node _T_1606 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1607 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1608 = eq(_T_1607, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1609 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1610 = eq(_T_1609, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1611 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1612 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1613 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1614 = eq(_T_1613, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1615 = and(_T_1606, _T_1608) @[dec_dec_ctl.scala 17:17] + node _T_1616 = and(_T_1615, _T_1610) @[dec_dec_ctl.scala 17:17] + node _T_1617 = and(_T_1616, _T_1611) @[dec_dec_ctl.scala 17:17] + node _T_1618 = and(_T_1617, _T_1612) @[dec_dec_ctl.scala 17:17] + node _T_1619 = and(_T_1618, _T_1614) @[dec_dec_ctl.scala 17:17] + node _T_1620 = or(_T_1605, _T_1619) @[dec_dec_ctl.scala 127:50] + node _T_1621 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1622 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1623 = eq(_T_1622, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1624 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_1625 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1626 = eq(_T_1625, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1627 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1628 = eq(_T_1627, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1629 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1630 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1631 = eq(_T_1630, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1632 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1633 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1634 = eq(_T_1633, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1635 = and(_T_1621, _T_1623) @[dec_dec_ctl.scala 17:17] + node _T_1636 = and(_T_1635, _T_1624) @[dec_dec_ctl.scala 17:17] + node _T_1637 = and(_T_1636, _T_1626) @[dec_dec_ctl.scala 17:17] + node _T_1638 = and(_T_1637, _T_1628) @[dec_dec_ctl.scala 17:17] + node _T_1639 = and(_T_1638, _T_1629) @[dec_dec_ctl.scala 17:17] + node _T_1640 = and(_T_1639, _T_1631) @[dec_dec_ctl.scala 17:17] + node _T_1641 = and(_T_1640, _T_1632) @[dec_dec_ctl.scala 17:17] + node _T_1642 = and(_T_1641, _T_1634) @[dec_dec_ctl.scala 17:17] + node _T_1643 = or(_T_1620, _T_1642) @[dec_dec_ctl.scala 127:84] + node _T_1644 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1645 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1646 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1647 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1648 = eq(_T_1647, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1649 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1650 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1651 = eq(_T_1650, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1652 = and(_T_1644, _T_1645) @[dec_dec_ctl.scala 17:17] + node _T_1653 = and(_T_1652, _T_1646) @[dec_dec_ctl.scala 17:17] + node _T_1654 = and(_T_1653, _T_1648) @[dec_dec_ctl.scala 17:17] + node _T_1655 = and(_T_1654, _T_1649) @[dec_dec_ctl.scala 17:17] + node _T_1656 = and(_T_1655, _T_1651) @[dec_dec_ctl.scala 17:17] + node _T_1657 = or(_T_1643, _T_1656) @[dec_dec_ctl.scala 128:49] + io.out.mul <= _T_1657 @[dec_dec_ctl.scala 122:14] + node _T_1658 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1659 = eq(_T_1658, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1660 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1661 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1662 = eq(_T_1661, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1663 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1664 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1665 = eq(_T_1664, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1666 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1667 = eq(_T_1666, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1668 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1669 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1670 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1671 = eq(_T_1670, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1672 = and(_T_1659, _T_1660) @[dec_dec_ctl.scala 17:17] + node _T_1673 = and(_T_1672, _T_1662) @[dec_dec_ctl.scala 17:17] + node _T_1674 = and(_T_1673, _T_1663) @[dec_dec_ctl.scala 17:17] + node _T_1675 = and(_T_1674, _T_1665) @[dec_dec_ctl.scala 17:17] + node _T_1676 = and(_T_1675, _T_1667) @[dec_dec_ctl.scala 17:17] + node _T_1677 = and(_T_1676, _T_1668) @[dec_dec_ctl.scala 17:17] + node _T_1678 = and(_T_1677, _T_1669) @[dec_dec_ctl.scala 17:17] + node _T_1679 = and(_T_1678, _T_1671) @[dec_dec_ctl.scala 17:17] + node _T_1680 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1681 = eq(_T_1680, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1682 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1683 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1684 = eq(_T_1683, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1685 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1686 = eq(_T_1685, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1687 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1688 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1689 = eq(_T_1688, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1690 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1691 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1692 = eq(_T_1691, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1693 = and(_T_1681, _T_1682) @[dec_dec_ctl.scala 17:17] + node _T_1694 = and(_T_1693, _T_1684) @[dec_dec_ctl.scala 17:17] + node _T_1695 = and(_T_1694, _T_1686) @[dec_dec_ctl.scala 17:17] + node _T_1696 = and(_T_1695, _T_1687) @[dec_dec_ctl.scala 17:17] + node _T_1697 = and(_T_1696, _T_1689) @[dec_dec_ctl.scala 17:17] + node _T_1698 = and(_T_1697, _T_1690) @[dec_dec_ctl.scala 17:17] + node _T_1699 = and(_T_1698, _T_1692) @[dec_dec_ctl.scala 17:17] + node _T_1700 = or(_T_1679, _T_1699) @[dec_dec_ctl.scala 130:65] + io.out.rs1_sign <= _T_1700 @[dec_dec_ctl.scala 130:19] + node _T_1701 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1702 = eq(_T_1701, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1703 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1704 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1705 = eq(_T_1704, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1706 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1707 = eq(_T_1706, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1708 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1709 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1710 = eq(_T_1709, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1711 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1712 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1713 = eq(_T_1712, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1714 = and(_T_1702, _T_1703) @[dec_dec_ctl.scala 17:17] + node _T_1715 = and(_T_1714, _T_1705) @[dec_dec_ctl.scala 17:17] + node _T_1716 = and(_T_1715, _T_1707) @[dec_dec_ctl.scala 17:17] + node _T_1717 = and(_T_1716, _T_1708) @[dec_dec_ctl.scala 17:17] + node _T_1718 = and(_T_1717, _T_1710) @[dec_dec_ctl.scala 17:17] + node _T_1719 = and(_T_1718, _T_1711) @[dec_dec_ctl.scala 17:17] + node _T_1720 = and(_T_1719, _T_1713) @[dec_dec_ctl.scala 17:17] + io.out.rs2_sign <= _T_1720 @[dec_dec_ctl.scala 132:19] + node _T_1721 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1722 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1723 = eq(_T_1722, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1724 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1725 = eq(_T_1724, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1726 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1727 = eq(_T_1726, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1728 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1729 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1730 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1731 = eq(_T_1730, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1732 = and(_T_1721, _T_1723) @[dec_dec_ctl.scala 17:17] + node _T_1733 = and(_T_1732, _T_1725) @[dec_dec_ctl.scala 17:17] + node _T_1734 = and(_T_1733, _T_1727) @[dec_dec_ctl.scala 17:17] + node _T_1735 = and(_T_1734, _T_1728) @[dec_dec_ctl.scala 17:17] + node _T_1736 = and(_T_1735, _T_1729) @[dec_dec_ctl.scala 17:17] + node _T_1737 = and(_T_1736, _T_1731) @[dec_dec_ctl.scala 17:17] + io.out.low <= _T_1737 @[dec_dec_ctl.scala 134:14] + node _T_1738 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1739 = eq(_T_1738, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1740 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1741 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1742 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1743 = eq(_T_1742, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1744 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1745 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1746 = eq(_T_1745, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1747 = and(_T_1739, _T_1740) @[dec_dec_ctl.scala 17:17] + node _T_1748 = and(_T_1747, _T_1741) @[dec_dec_ctl.scala 17:17] + node _T_1749 = and(_T_1748, _T_1743) @[dec_dec_ctl.scala 17:17] + node _T_1750 = and(_T_1749, _T_1744) @[dec_dec_ctl.scala 17:17] + node _T_1751 = and(_T_1750, _T_1746) @[dec_dec_ctl.scala 17:17] + io.out.div <= _T_1751 @[dec_dec_ctl.scala 136:14] + node _T_1752 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1753 = eq(_T_1752, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1754 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1755 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1756 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1757 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1758 = eq(_T_1757, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1759 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1760 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1761 = eq(_T_1760, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1762 = and(_T_1753, _T_1754) @[dec_dec_ctl.scala 17:17] + node _T_1763 = and(_T_1762, _T_1755) @[dec_dec_ctl.scala 17:17] + node _T_1764 = and(_T_1763, _T_1756) @[dec_dec_ctl.scala 17:17] + node _T_1765 = and(_T_1764, _T_1758) @[dec_dec_ctl.scala 17:17] + node _T_1766 = and(_T_1765, _T_1759) @[dec_dec_ctl.scala 17:17] + node _T_1767 = and(_T_1766, _T_1761) @[dec_dec_ctl.scala 17:17] + io.out.rem <= _T_1767 @[dec_dec_ctl.scala 138:14] + node _T_1768 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1769 = eq(_T_1768, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1770 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_1771 = and(_T_1769, _T_1770) @[dec_dec_ctl.scala 17:17] + io.out.fence <= _T_1771 @[dec_dec_ctl.scala 140:16] + node _T_1772 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1773 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1774 = eq(_T_1773, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1775 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_1776 = and(_T_1772, _T_1774) @[dec_dec_ctl.scala 17:17] + node _T_1777 = and(_T_1776, _T_1775) @[dec_dec_ctl.scala 17:17] + io.out.fence_i <= _T_1777 @[dec_dec_ctl.scala 142:18] + node _T_1778 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1779 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1780 = eq(_T_1779, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1781 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_1782 = eq(_T_1781, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1783 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_1784 = eq(_T_1783, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1785 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_1786 = eq(_T_1785, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1787 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_1788 = eq(_T_1787, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1789 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1790 = eq(_T_1789, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1791 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1792 = eq(_T_1791, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1793 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1794 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1795 = eq(_T_1794, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1796 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1797 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1798 = eq(_T_1797, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1799 = and(_T_1778, _T_1780) @[dec_dec_ctl.scala 17:17] + node _T_1800 = and(_T_1799, _T_1782) @[dec_dec_ctl.scala 17:17] + node _T_1801 = and(_T_1800, _T_1784) @[dec_dec_ctl.scala 17:17] + node _T_1802 = and(_T_1801, _T_1786) @[dec_dec_ctl.scala 17:17] + node _T_1803 = and(_T_1802, _T_1788) @[dec_dec_ctl.scala 17:17] + node _T_1804 = and(_T_1803, _T_1790) @[dec_dec_ctl.scala 17:17] + node _T_1805 = and(_T_1804, _T_1792) @[dec_dec_ctl.scala 17:17] + node _T_1806 = and(_T_1805, _T_1793) @[dec_dec_ctl.scala 17:17] + node _T_1807 = and(_T_1806, _T_1795) @[dec_dec_ctl.scala 17:17] + node _T_1808 = and(_T_1807, _T_1796) @[dec_dec_ctl.scala 17:17] + node _T_1809 = and(_T_1808, _T_1798) @[dec_dec_ctl.scala 17:17] + io.out.clz <= _T_1809 @[dec_dec_ctl.scala 144:14] + node _T_1810 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1811 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1812 = eq(_T_1811, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1813 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_1814 = eq(_T_1813, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1815 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_1816 = eq(_T_1815, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1817 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_1818 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1819 = eq(_T_1818, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1820 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1821 = eq(_T_1820, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1822 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1823 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1824 = eq(_T_1823, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1825 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1826 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1827 = eq(_T_1826, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1828 = and(_T_1810, _T_1812) @[dec_dec_ctl.scala 17:17] + node _T_1829 = and(_T_1828, _T_1814) @[dec_dec_ctl.scala 17:17] + node _T_1830 = and(_T_1829, _T_1816) @[dec_dec_ctl.scala 17:17] + node _T_1831 = and(_T_1830, _T_1817) @[dec_dec_ctl.scala 17:17] + node _T_1832 = and(_T_1831, _T_1819) @[dec_dec_ctl.scala 17:17] + node _T_1833 = and(_T_1832, _T_1821) @[dec_dec_ctl.scala 17:17] + node _T_1834 = and(_T_1833, _T_1822) @[dec_dec_ctl.scala 17:17] + node _T_1835 = and(_T_1834, _T_1824) @[dec_dec_ctl.scala 17:17] + node _T_1836 = and(_T_1835, _T_1825) @[dec_dec_ctl.scala 17:17] + node _T_1837 = and(_T_1836, _T_1827) @[dec_dec_ctl.scala 17:17] + io.out.ctz <= _T_1837 @[dec_dec_ctl.scala 146:14] + node _T_1838 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1839 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1840 = eq(_T_1839, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1841 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_1842 = eq(_T_1841, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1843 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_1844 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1845 = eq(_T_1844, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1846 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1847 = eq(_T_1846, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1848 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1849 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1850 = eq(_T_1849, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1851 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1852 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1853 = eq(_T_1852, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1854 = and(_T_1838, _T_1840) @[dec_dec_ctl.scala 17:17] + node _T_1855 = and(_T_1854, _T_1842) @[dec_dec_ctl.scala 17:17] + node _T_1856 = and(_T_1855, _T_1843) @[dec_dec_ctl.scala 17:17] + node _T_1857 = and(_T_1856, _T_1845) @[dec_dec_ctl.scala 17:17] + node _T_1858 = and(_T_1857, _T_1847) @[dec_dec_ctl.scala 17:17] + node _T_1859 = and(_T_1858, _T_1848) @[dec_dec_ctl.scala 17:17] + node _T_1860 = and(_T_1859, _T_1850) @[dec_dec_ctl.scala 17:17] + node _T_1861 = and(_T_1860, _T_1851) @[dec_dec_ctl.scala 17:17] + node _T_1862 = and(_T_1861, _T_1853) @[dec_dec_ctl.scala 17:17] + io.out.pcnt <= _T_1862 @[dec_dec_ctl.scala 148:15] + node _T_1863 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1864 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1865 = eq(_T_1864, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1866 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_1867 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_1868 = eq(_T_1867, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1869 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1870 = eq(_T_1869, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1871 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1872 = eq(_T_1871, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1873 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1874 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1875 = eq(_T_1874, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1876 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1877 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1878 = eq(_T_1877, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1879 = and(_T_1863, _T_1865) @[dec_dec_ctl.scala 17:17] + node _T_1880 = and(_T_1879, _T_1866) @[dec_dec_ctl.scala 17:17] + node _T_1881 = and(_T_1880, _T_1868) @[dec_dec_ctl.scala 17:17] + node _T_1882 = and(_T_1881, _T_1870) @[dec_dec_ctl.scala 17:17] + node _T_1883 = and(_T_1882, _T_1872) @[dec_dec_ctl.scala 17:17] + node _T_1884 = and(_T_1883, _T_1873) @[dec_dec_ctl.scala 17:17] + node _T_1885 = and(_T_1884, _T_1875) @[dec_dec_ctl.scala 17:17] + node _T_1886 = and(_T_1885, _T_1876) @[dec_dec_ctl.scala 17:17] + node _T_1887 = and(_T_1886, _T_1878) @[dec_dec_ctl.scala 17:17] + io.out.sext_b <= _T_1887 @[dec_dec_ctl.scala 150:17] + node _T_1888 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1889 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1890 = eq(_T_1889, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1891 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_1892 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_1893 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1895 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1896 = eq(_T_1895, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1897 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1898 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1899 = eq(_T_1898, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1900 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1901 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1902 = eq(_T_1901, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1903 = and(_T_1888, _T_1890) @[dec_dec_ctl.scala 17:17] + node _T_1904 = and(_T_1903, _T_1891) @[dec_dec_ctl.scala 17:17] + node _T_1905 = and(_T_1904, _T_1892) @[dec_dec_ctl.scala 17:17] + node _T_1906 = and(_T_1905, _T_1894) @[dec_dec_ctl.scala 17:17] + node _T_1907 = and(_T_1906, _T_1896) @[dec_dec_ctl.scala 17:17] + node _T_1908 = and(_T_1907, _T_1897) @[dec_dec_ctl.scala 17:17] + node _T_1909 = and(_T_1908, _T_1899) @[dec_dec_ctl.scala 17:17] + node _T_1910 = and(_T_1909, _T_1900) @[dec_dec_ctl.scala 17:17] + node _T_1911 = and(_T_1910, _T_1902) @[dec_dec_ctl.scala 17:17] + io.out.sext_h <= _T_1911 @[dec_dec_ctl.scala 152:17] + node _T_1912 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1914 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1915 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1916 = eq(_T_1915, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1917 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1918 = eq(_T_1917, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1919 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1920 = eq(_T_1919, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1921 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1922 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1923 = eq(_T_1922, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1924 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1925 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1926 = eq(_T_1925, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1927 = and(_T_1913, _T_1914) @[dec_dec_ctl.scala 17:17] + node _T_1928 = and(_T_1927, _T_1916) @[dec_dec_ctl.scala 17:17] + node _T_1929 = and(_T_1928, _T_1918) @[dec_dec_ctl.scala 17:17] + node _T_1930 = and(_T_1929, _T_1920) @[dec_dec_ctl.scala 17:17] + node _T_1931 = and(_T_1930, _T_1921) @[dec_dec_ctl.scala 17:17] + node _T_1932 = and(_T_1931, _T_1923) @[dec_dec_ctl.scala 17:17] + node _T_1933 = and(_T_1932, _T_1924) @[dec_dec_ctl.scala 17:17] + node _T_1934 = and(_T_1933, _T_1926) @[dec_dec_ctl.scala 17:17] + io.out.slo <= _T_1934 @[dec_dec_ctl.scala 154:14] + node _T_1935 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_1936 = eq(_T_1935, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1937 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1938 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1939 = eq(_T_1938, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1940 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1941 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1942 = eq(_T_1941, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1943 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1944 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1945 = eq(_T_1944, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1946 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1947 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1948 = eq(_T_1947, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1949 = and(_T_1936, _T_1937) @[dec_dec_ctl.scala 17:17] + node _T_1950 = and(_T_1949, _T_1939) @[dec_dec_ctl.scala 17:17] + node _T_1951 = and(_T_1950, _T_1940) @[dec_dec_ctl.scala 17:17] + node _T_1952 = and(_T_1951, _T_1942) @[dec_dec_ctl.scala 17:17] + node _T_1953 = and(_T_1952, _T_1943) @[dec_dec_ctl.scala 17:17] + node _T_1954 = and(_T_1953, _T_1945) @[dec_dec_ctl.scala 17:17] + node _T_1955 = and(_T_1954, _T_1946) @[dec_dec_ctl.scala 17:17] + node _T_1956 = and(_T_1955, _T_1948) @[dec_dec_ctl.scala 17:17] + io.out.sro <= _T_1956 @[dec_dec_ctl.scala 156:14] + node _T_1957 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1958 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1959 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1960 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1961 = eq(_T_1960, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1962 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1963 = eq(_T_1962, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1964 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1965 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1966 = eq(_T_1965, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1967 = and(_T_1957, _T_1958) @[dec_dec_ctl.scala 17:17] + node _T_1968 = and(_T_1967, _T_1959) @[dec_dec_ctl.scala 17:17] + node _T_1969 = and(_T_1968, _T_1961) @[dec_dec_ctl.scala 17:17] + node _T_1970 = and(_T_1969, _T_1963) @[dec_dec_ctl.scala 17:17] + node _T_1971 = and(_T_1970, _T_1964) @[dec_dec_ctl.scala 17:17] + node _T_1972 = and(_T_1971, _T_1966) @[dec_dec_ctl.scala 17:17] + io.out.min <= _T_1972 @[dec_dec_ctl.scala 158:14] + node _T_1973 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1974 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1975 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1976 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1977 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1978 = eq(_T_1977, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1979 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1980 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1981 = eq(_T_1980, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1982 = and(_T_1973, _T_1974) @[dec_dec_ctl.scala 17:17] + node _T_1983 = and(_T_1982, _T_1975) @[dec_dec_ctl.scala 17:17] + node _T_1984 = and(_T_1983, _T_1976) @[dec_dec_ctl.scala 17:17] + node _T_1985 = and(_T_1984, _T_1978) @[dec_dec_ctl.scala 17:17] + node _T_1986 = and(_T_1985, _T_1979) @[dec_dec_ctl.scala 17:17] + node _T_1987 = and(_T_1986, _T_1981) @[dec_dec_ctl.scala 17:17] + io.out.max <= _T_1987 @[dec_dec_ctl.scala 160:14] + node _T_1988 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_1989 = eq(_T_1988, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1990 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1991 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_1992 = eq(_T_1991, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1993 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1994 = eq(_T_1993, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1995 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1996 = eq(_T_1995, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1997 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1998 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1999 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2000 = eq(_T_1999, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2001 = and(_T_1989, _T_1990) @[dec_dec_ctl.scala 17:17] + node _T_2002 = and(_T_2001, _T_1992) @[dec_dec_ctl.scala 17:17] + node _T_2003 = and(_T_2002, _T_1994) @[dec_dec_ctl.scala 17:17] + node _T_2004 = and(_T_2003, _T_1996) @[dec_dec_ctl.scala 17:17] + node _T_2005 = and(_T_2004, _T_1997) @[dec_dec_ctl.scala 17:17] + node _T_2006 = and(_T_2005, _T_1998) @[dec_dec_ctl.scala 17:17] + node _T_2007 = and(_T_2006, _T_2000) @[dec_dec_ctl.scala 17:17] + io.out.pack <= _T_2007 @[dec_dec_ctl.scala 162:15] + node _T_2008 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2009 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2010 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2011 = eq(_T_2010, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2012 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2013 = eq(_T_2012, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2014 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2015 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2016 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2017 = eq(_T_2016, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2018 = and(_T_2008, _T_2009) @[dec_dec_ctl.scala 17:17] + node _T_2019 = and(_T_2018, _T_2011) @[dec_dec_ctl.scala 17:17] + node _T_2020 = and(_T_2019, _T_2013) @[dec_dec_ctl.scala 17:17] + node _T_2021 = and(_T_2020, _T_2014) @[dec_dec_ctl.scala 17:17] + node _T_2022 = and(_T_2021, _T_2015) @[dec_dec_ctl.scala 17:17] + node _T_2023 = and(_T_2022, _T_2017) @[dec_dec_ctl.scala 17:17] + io.out.packu <= _T_2023 @[dec_dec_ctl.scala 164:16] + node _T_2024 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2025 = eq(_T_2024, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2026 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2027 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2028 = eq(_T_2027, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2029 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2030 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2031 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2032 = eq(_T_2031, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2033 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2034 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2035 = eq(_T_2034, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2036 = and(_T_2025, _T_2026) @[dec_dec_ctl.scala 17:17] + node _T_2037 = and(_T_2036, _T_2028) @[dec_dec_ctl.scala 17:17] + node _T_2038 = and(_T_2037, _T_2029) @[dec_dec_ctl.scala 17:17] + node _T_2039 = and(_T_2038, _T_2030) @[dec_dec_ctl.scala 17:17] + node _T_2040 = and(_T_2039, _T_2032) @[dec_dec_ctl.scala 17:17] + node _T_2041 = and(_T_2040, _T_2033) @[dec_dec_ctl.scala 17:17] + node _T_2042 = and(_T_2041, _T_2035) @[dec_dec_ctl.scala 17:17] + io.out.packh <= _T_2042 @[dec_dec_ctl.scala 166:16] + node _T_2043 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2044 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2045 = eq(_T_2044, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2046 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2047 = eq(_T_2046, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2048 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2049 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2050 = eq(_T_2049, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2051 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2052 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2053 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2054 = eq(_T_2053, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2055 = and(_T_2043, _T_2045) @[dec_dec_ctl.scala 17:17] + node _T_2056 = and(_T_2055, _T_2047) @[dec_dec_ctl.scala 17:17] + node _T_2057 = and(_T_2056, _T_2048) @[dec_dec_ctl.scala 17:17] + node _T_2058 = and(_T_2057, _T_2050) @[dec_dec_ctl.scala 17:17] + node _T_2059 = and(_T_2058, _T_2051) @[dec_dec_ctl.scala 17:17] + node _T_2060 = and(_T_2059, _T_2052) @[dec_dec_ctl.scala 17:17] + node _T_2061 = and(_T_2060, _T_2054) @[dec_dec_ctl.scala 17:17] + io.out.rol <= _T_2061 @[dec_dec_ctl.scala 168:14] + node _T_2062 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2063 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2064 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2065 = eq(_T_2064, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2066 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2067 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2068 = eq(_T_2067, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2069 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2070 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2071 = eq(_T_2070, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2072 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2073 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2074 = eq(_T_2073, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2075 = and(_T_2062, _T_2063) @[dec_dec_ctl.scala 17:17] + node _T_2076 = and(_T_2075, _T_2065) @[dec_dec_ctl.scala 17:17] + node _T_2077 = and(_T_2076, _T_2066) @[dec_dec_ctl.scala 17:17] + node _T_2078 = and(_T_2077, _T_2068) @[dec_dec_ctl.scala 17:17] + node _T_2079 = and(_T_2078, _T_2069) @[dec_dec_ctl.scala 17:17] + node _T_2080 = and(_T_2079, _T_2071) @[dec_dec_ctl.scala 17:17] + node _T_2081 = and(_T_2080, _T_2072) @[dec_dec_ctl.scala 17:17] + node _T_2082 = and(_T_2081, _T_2074) @[dec_dec_ctl.scala 17:17] + io.out.ror <= _T_2082 @[dec_dec_ctl.scala 170:14] + node _T_2083 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2084 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2085 = eq(_T_2084, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2086 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_2087 = eq(_T_2086, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2088 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2089 = eq(_T_2088, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2090 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2091 = eq(_T_2090, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2092 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2093 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2094 = eq(_T_2093, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2095 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2096 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2097 = eq(_T_2096, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2098 = and(_T_2083, _T_2085) @[dec_dec_ctl.scala 17:17] + node _T_2099 = and(_T_2098, _T_2087) @[dec_dec_ctl.scala 17:17] + node _T_2100 = and(_T_2099, _T_2089) @[dec_dec_ctl.scala 17:17] + node _T_2101 = and(_T_2100, _T_2091) @[dec_dec_ctl.scala 17:17] + node _T_2102 = and(_T_2101, _T_2092) @[dec_dec_ctl.scala 17:17] + node _T_2103 = and(_T_2102, _T_2094) @[dec_dec_ctl.scala 17:17] + node _T_2104 = and(_T_2103, _T_2095) @[dec_dec_ctl.scala 17:17] + node _T_2105 = and(_T_2104, _T_2097) @[dec_dec_ctl.scala 17:17] + node _T_2106 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2107 = eq(_T_2106, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2108 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2109 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2110 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2111 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2112 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2113 = eq(_T_2112, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2114 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2115 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2116 = eq(_T_2115, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2117 = and(_T_2107, _T_2108) @[dec_dec_ctl.scala 17:17] + node _T_2118 = and(_T_2117, _T_2109) @[dec_dec_ctl.scala 17:17] + node _T_2119 = and(_T_2118, _T_2110) @[dec_dec_ctl.scala 17:17] + node _T_2120 = and(_T_2119, _T_2111) @[dec_dec_ctl.scala 17:17] + node _T_2121 = and(_T_2120, _T_2113) @[dec_dec_ctl.scala 17:17] + node _T_2122 = and(_T_2121, _T_2114) @[dec_dec_ctl.scala 17:17] + node _T_2123 = and(_T_2122, _T_2116) @[dec_dec_ctl.scala 17:17] + node _T_2124 = or(_T_2105, _T_2123) @[dec_dec_ctl.scala 172:62] + node _T_2125 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2126 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2127 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2128 = eq(_T_2127, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2129 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2130 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2131 = eq(_T_2130, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2132 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2133 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2134 = eq(_T_2133, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2135 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2136 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2137 = eq(_T_2136, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2138 = and(_T_2125, _T_2126) @[dec_dec_ctl.scala 17:17] + node _T_2139 = and(_T_2138, _T_2128) @[dec_dec_ctl.scala 17:17] + node _T_2140 = and(_T_2139, _T_2129) @[dec_dec_ctl.scala 17:17] + node _T_2141 = and(_T_2140, _T_2131) @[dec_dec_ctl.scala 17:17] + node _T_2142 = and(_T_2141, _T_2132) @[dec_dec_ctl.scala 17:17] + node _T_2143 = and(_T_2142, _T_2134) @[dec_dec_ctl.scala 17:17] + node _T_2144 = and(_T_2143, _T_2135) @[dec_dec_ctl.scala 17:17] + node _T_2145 = and(_T_2144, _T_2137) @[dec_dec_ctl.scala 17:17] + node _T_2146 = or(_T_2124, _T_2145) @[dec_dec_ctl.scala 172:103] + node _T_2147 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2148 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2149 = eq(_T_2148, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2150 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2151 = eq(_T_2150, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2152 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2153 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2154 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2155 = eq(_T_2154, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2156 = and(_T_2147, _T_2149) @[dec_dec_ctl.scala 17:17] + node _T_2157 = and(_T_2156, _T_2151) @[dec_dec_ctl.scala 17:17] + node _T_2158 = and(_T_2157, _T_2152) @[dec_dec_ctl.scala 17:17] + node _T_2159 = and(_T_2158, _T_2153) @[dec_dec_ctl.scala 17:17] + node _T_2160 = and(_T_2159, _T_2155) @[dec_dec_ctl.scala 17:17] + node _T_2161 = or(_T_2146, _T_2160) @[dec_dec_ctl.scala 173:48] + node _T_2162 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2163 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2164 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2165 = eq(_T_2164, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2166 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2167 = eq(_T_2166, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2168 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2169 = eq(_T_2168, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2170 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2171 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2172 = eq(_T_2171, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2173 = and(_T_2162, _T_2163) @[dec_dec_ctl.scala 17:17] + node _T_2174 = and(_T_2173, _T_2165) @[dec_dec_ctl.scala 17:17] + node _T_2175 = and(_T_2174, _T_2167) @[dec_dec_ctl.scala 17:17] + node _T_2176 = and(_T_2175, _T_2169) @[dec_dec_ctl.scala 17:17] + node _T_2177 = and(_T_2176, _T_2170) @[dec_dec_ctl.scala 17:17] + node _T_2178 = and(_T_2177, _T_2172) @[dec_dec_ctl.scala 17:17] + node _T_2179 = or(_T_2161, _T_2178) @[dec_dec_ctl.scala 173:83] + node _T_2180 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2181 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2182 = eq(_T_2181, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2183 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2184 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2185 = eq(_T_2184, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2186 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2187 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2188 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2189 = eq(_T_2188, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2190 = and(_T_2180, _T_2182) @[dec_dec_ctl.scala 17:17] + node _T_2191 = and(_T_2190, _T_2183) @[dec_dec_ctl.scala 17:17] + node _T_2192 = and(_T_2191, _T_2185) @[dec_dec_ctl.scala 17:17] + node _T_2193 = and(_T_2192, _T_2186) @[dec_dec_ctl.scala 17:17] + node _T_2194 = and(_T_2193, _T_2187) @[dec_dec_ctl.scala 17:17] + node _T_2195 = and(_T_2194, _T_2189) @[dec_dec_ctl.scala 17:17] + node _T_2196 = or(_T_2179, _T_2195) @[dec_dec_ctl.scala 174:42] + node _T_2197 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2198 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2199 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2200 = eq(_T_2199, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2201 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2202 = eq(_T_2201, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2203 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2204 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2205 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2206 = eq(_T_2205, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2207 = and(_T_2197, _T_2198) @[dec_dec_ctl.scala 17:17] + node _T_2208 = and(_T_2207, _T_2200) @[dec_dec_ctl.scala 17:17] + node _T_2209 = and(_T_2208, _T_2202) @[dec_dec_ctl.scala 17:17] + node _T_2210 = and(_T_2209, _T_2203) @[dec_dec_ctl.scala 17:17] + node _T_2211 = and(_T_2210, _T_2204) @[dec_dec_ctl.scala 17:17] + node _T_2212 = and(_T_2211, _T_2206) @[dec_dec_ctl.scala 17:17] + node _T_2213 = or(_T_2196, _T_2212) @[dec_dec_ctl.scala 174:79] + node _T_2214 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2215 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2216 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2217 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_2218 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_2219 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_2220 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_2221 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2222 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2223 = eq(_T_2222, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2224 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2225 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2226 = eq(_T_2225, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2227 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2228 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2229 = eq(_T_2228, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2230 = and(_T_2214, _T_2215) @[dec_dec_ctl.scala 17:17] + node _T_2231 = and(_T_2230, _T_2216) @[dec_dec_ctl.scala 17:17] + node _T_2232 = and(_T_2231, _T_2217) @[dec_dec_ctl.scala 17:17] + node _T_2233 = and(_T_2232, _T_2218) @[dec_dec_ctl.scala 17:17] + node _T_2234 = and(_T_2233, _T_2219) @[dec_dec_ctl.scala 17:17] + node _T_2235 = and(_T_2234, _T_2220) @[dec_dec_ctl.scala 17:17] + node _T_2236 = and(_T_2235, _T_2221) @[dec_dec_ctl.scala 17:17] + node _T_2237 = and(_T_2236, _T_2223) @[dec_dec_ctl.scala 17:17] + node _T_2238 = and(_T_2237, _T_2224) @[dec_dec_ctl.scala 17:17] + node _T_2239 = and(_T_2238, _T_2226) @[dec_dec_ctl.scala 17:17] + node _T_2240 = and(_T_2239, _T_2227) @[dec_dec_ctl.scala 17:17] + node _T_2241 = and(_T_2240, _T_2229) @[dec_dec_ctl.scala 17:17] + node _T_2242 = or(_T_2213, _T_2241) @[dec_dec_ctl.scala 175:40] + node _T_2243 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2244 = eq(_T_2243, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2245 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2246 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2247 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_2248 = eq(_T_2247, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2249 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_2250 = eq(_T_2249, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2251 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_2252 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_2253 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_2254 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2255 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2256 = eq(_T_2255, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2257 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2258 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2259 = eq(_T_2258, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2260 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2261 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2262 = eq(_T_2261, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2263 = and(_T_2244, _T_2245) @[dec_dec_ctl.scala 17:17] + node _T_2264 = and(_T_2263, _T_2246) @[dec_dec_ctl.scala 17:17] + node _T_2265 = and(_T_2264, _T_2248) @[dec_dec_ctl.scala 17:17] + node _T_2266 = and(_T_2265, _T_2250) @[dec_dec_ctl.scala 17:17] + node _T_2267 = and(_T_2266, _T_2251) @[dec_dec_ctl.scala 17:17] + node _T_2268 = and(_T_2267, _T_2252) @[dec_dec_ctl.scala 17:17] + node _T_2269 = and(_T_2268, _T_2253) @[dec_dec_ctl.scala 17:17] + node _T_2270 = and(_T_2269, _T_2254) @[dec_dec_ctl.scala 17:17] + node _T_2271 = and(_T_2270, _T_2256) @[dec_dec_ctl.scala 17:17] + node _T_2272 = and(_T_2271, _T_2257) @[dec_dec_ctl.scala 17:17] + node _T_2273 = and(_T_2272, _T_2259) @[dec_dec_ctl.scala 17:17] + node _T_2274 = and(_T_2273, _T_2260) @[dec_dec_ctl.scala 17:17] + node _T_2275 = and(_T_2274, _T_2262) @[dec_dec_ctl.scala 17:17] + node _T_2276 = or(_T_2242, _T_2275) @[dec_dec_ctl.scala 175:96] + node _T_2277 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2278 = eq(_T_2277, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2279 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2280 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2281 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_2282 = eq(_T_2281, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2283 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_2284 = eq(_T_2283, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2285 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_2286 = eq(_T_2285, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2287 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_2288 = eq(_T_2287, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2289 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2290 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2291 = eq(_T_2290, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2292 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2293 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2294 = eq(_T_2293, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2295 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2296 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2297 = eq(_T_2296, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2298 = and(_T_2278, _T_2279) @[dec_dec_ctl.scala 17:17] + node _T_2299 = and(_T_2298, _T_2280) @[dec_dec_ctl.scala 17:17] + node _T_2300 = and(_T_2299, _T_2282) @[dec_dec_ctl.scala 17:17] + node _T_2301 = and(_T_2300, _T_2284) @[dec_dec_ctl.scala 17:17] + node _T_2302 = and(_T_2301, _T_2286) @[dec_dec_ctl.scala 17:17] + node _T_2303 = and(_T_2302, _T_2288) @[dec_dec_ctl.scala 17:17] + node _T_2304 = and(_T_2303, _T_2289) @[dec_dec_ctl.scala 17:17] + node _T_2305 = and(_T_2304, _T_2291) @[dec_dec_ctl.scala 17:17] + node _T_2306 = and(_T_2305, _T_2292) @[dec_dec_ctl.scala 17:17] + node _T_2307 = and(_T_2306, _T_2294) @[dec_dec_ctl.scala 17:17] + node _T_2308 = and(_T_2307, _T_2295) @[dec_dec_ctl.scala 17:17] + node _T_2309 = and(_T_2308, _T_2297) @[dec_dec_ctl.scala 17:17] + node _T_2310 = or(_T_2276, _T_2309) @[dec_dec_ctl.scala 176:65] + node _T_2311 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2312 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2313 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2314 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_2315 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_2316 = eq(_T_2315, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2317 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_2318 = eq(_T_2317, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2319 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_2320 = eq(_T_2319, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2321 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2322 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2323 = eq(_T_2322, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2324 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2325 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2326 = eq(_T_2325, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2327 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2328 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2329 = eq(_T_2328, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2330 = and(_T_2311, _T_2312) @[dec_dec_ctl.scala 17:17] + node _T_2331 = and(_T_2330, _T_2313) @[dec_dec_ctl.scala 17:17] + node _T_2332 = and(_T_2331, _T_2314) @[dec_dec_ctl.scala 17:17] + node _T_2333 = and(_T_2332, _T_2316) @[dec_dec_ctl.scala 17:17] + node _T_2334 = and(_T_2333, _T_2318) @[dec_dec_ctl.scala 17:17] + node _T_2335 = and(_T_2334, _T_2320) @[dec_dec_ctl.scala 17:17] + node _T_2336 = and(_T_2335, _T_2321) @[dec_dec_ctl.scala 17:17] + node _T_2337 = and(_T_2336, _T_2323) @[dec_dec_ctl.scala 17:17] + node _T_2338 = and(_T_2337, _T_2324) @[dec_dec_ctl.scala 17:17] + node _T_2339 = and(_T_2338, _T_2326) @[dec_dec_ctl.scala 17:17] + node _T_2340 = and(_T_2339, _T_2327) @[dec_dec_ctl.scala 17:17] + node _T_2341 = and(_T_2340, _T_2329) @[dec_dec_ctl.scala 17:17] + node _T_2342 = or(_T_2310, _T_2341) @[dec_dec_ctl.scala 177:64] + node _T_2343 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2344 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_2345 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2346 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2347 = eq(_T_2346, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2348 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2349 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2350 = eq(_T_2349, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2351 = and(_T_2343, _T_2344) @[dec_dec_ctl.scala 17:17] + node _T_2352 = and(_T_2351, _T_2345) @[dec_dec_ctl.scala 17:17] + node _T_2353 = and(_T_2352, _T_2347) @[dec_dec_ctl.scala 17:17] + node _T_2354 = and(_T_2353, _T_2348) @[dec_dec_ctl.scala 17:17] + node _T_2355 = and(_T_2354, _T_2350) @[dec_dec_ctl.scala 17:17] + node _T_2356 = or(_T_2342, _T_2355) @[dec_dec_ctl.scala 178:62] + io.out.zbb <= _T_2356 @[dec_dec_ctl.scala 172:14] + node _T_2357 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2358 = eq(_T_2357, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2359 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2360 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2361 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2362 = eq(_T_2361, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2363 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2364 = eq(_T_2363, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2365 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2366 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2367 = eq(_T_2366, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2368 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2369 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2370 = eq(_T_2369, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2371 = and(_T_2358, _T_2359) @[dec_dec_ctl.scala 17:17] + node _T_2372 = and(_T_2371, _T_2360) @[dec_dec_ctl.scala 17:17] + node _T_2373 = and(_T_2372, _T_2362) @[dec_dec_ctl.scala 17:17] + node _T_2374 = and(_T_2373, _T_2364) @[dec_dec_ctl.scala 17:17] + node _T_2375 = and(_T_2374, _T_2365) @[dec_dec_ctl.scala 17:17] + node _T_2376 = and(_T_2375, _T_2367) @[dec_dec_ctl.scala 17:17] + node _T_2377 = and(_T_2376, _T_2368) @[dec_dec_ctl.scala 17:17] + node _T_2378 = and(_T_2377, _T_2370) @[dec_dec_ctl.scala 17:17] + io.out.sbset <= _T_2378 @[dec_dec_ctl.scala 180:16] + node _T_2379 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2380 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2381 = eq(_T_2380, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2382 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2383 = eq(_T_2382, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2384 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2385 = eq(_T_2384, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2386 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2387 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2388 = eq(_T_2387, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2389 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2390 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2391 = eq(_T_2390, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2392 = and(_T_2379, _T_2381) @[dec_dec_ctl.scala 17:17] + node _T_2393 = and(_T_2392, _T_2383) @[dec_dec_ctl.scala 17:17] + node _T_2394 = and(_T_2393, _T_2385) @[dec_dec_ctl.scala 17:17] + node _T_2395 = and(_T_2394, _T_2386) @[dec_dec_ctl.scala 17:17] + node _T_2396 = and(_T_2395, _T_2388) @[dec_dec_ctl.scala 17:17] + node _T_2397 = and(_T_2396, _T_2389) @[dec_dec_ctl.scala 17:17] + node _T_2398 = and(_T_2397, _T_2391) @[dec_dec_ctl.scala 17:17] + io.out.sbclr <= _T_2398 @[dec_dec_ctl.scala 182:16] + node _T_2399 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2400 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2401 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2402 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2403 = eq(_T_2402, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2404 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2405 = eq(_T_2404, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2406 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2407 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2408 = eq(_T_2407, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2409 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2410 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2411 = eq(_T_2410, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2412 = and(_T_2399, _T_2400) @[dec_dec_ctl.scala 17:17] + node _T_2413 = and(_T_2412, _T_2401) @[dec_dec_ctl.scala 17:17] + node _T_2414 = and(_T_2413, _T_2403) @[dec_dec_ctl.scala 17:17] + node _T_2415 = and(_T_2414, _T_2405) @[dec_dec_ctl.scala 17:17] + node _T_2416 = and(_T_2415, _T_2406) @[dec_dec_ctl.scala 17:17] + node _T_2417 = and(_T_2416, _T_2408) @[dec_dec_ctl.scala 17:17] + node _T_2418 = and(_T_2417, _T_2409) @[dec_dec_ctl.scala 17:17] + node _T_2419 = and(_T_2418, _T_2411) @[dec_dec_ctl.scala 17:17] + io.out.sbinv <= _T_2419 @[dec_dec_ctl.scala 184:16] + node _T_2420 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2421 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2422 = eq(_T_2421, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2423 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2424 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2425 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2426 = eq(_T_2425, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2427 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2428 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2429 = eq(_T_2428, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2430 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2431 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2432 = eq(_T_2431, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2433 = and(_T_2420, _T_2422) @[dec_dec_ctl.scala 17:17] + node _T_2434 = and(_T_2433, _T_2423) @[dec_dec_ctl.scala 17:17] + node _T_2435 = and(_T_2434, _T_2424) @[dec_dec_ctl.scala 17:17] + node _T_2436 = and(_T_2435, _T_2426) @[dec_dec_ctl.scala 17:17] + node _T_2437 = and(_T_2436, _T_2427) @[dec_dec_ctl.scala 17:17] + node _T_2438 = and(_T_2437, _T_2429) @[dec_dec_ctl.scala 17:17] + node _T_2439 = and(_T_2438, _T_2430) @[dec_dec_ctl.scala 17:17] + node _T_2440 = and(_T_2439, _T_2432) @[dec_dec_ctl.scala 17:17] + io.out.sbext <= _T_2440 @[dec_dec_ctl.scala 186:16] + node _T_2441 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2442 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2443 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2444 = eq(_T_2443, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2445 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2446 = eq(_T_2445, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2447 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2448 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2449 = eq(_T_2448, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2450 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2451 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2452 = eq(_T_2451, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2453 = and(_T_2441, _T_2442) @[dec_dec_ctl.scala 17:17] + node _T_2454 = and(_T_2453, _T_2444) @[dec_dec_ctl.scala 17:17] + node _T_2455 = and(_T_2454, _T_2446) @[dec_dec_ctl.scala 17:17] + node _T_2456 = and(_T_2455, _T_2447) @[dec_dec_ctl.scala 17:17] + node _T_2457 = and(_T_2456, _T_2449) @[dec_dec_ctl.scala 17:17] + node _T_2458 = and(_T_2457, _T_2450) @[dec_dec_ctl.scala 17:17] + node _T_2459 = and(_T_2458, _T_2452) @[dec_dec_ctl.scala 17:17] + node _T_2460 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2461 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2462 = eq(_T_2461, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2463 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2464 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2465 = eq(_T_2464, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2466 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2467 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2468 = eq(_T_2467, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2469 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2470 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2471 = eq(_T_2470, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2472 = and(_T_2460, _T_2462) @[dec_dec_ctl.scala 17:17] + node _T_2473 = and(_T_2472, _T_2463) @[dec_dec_ctl.scala 17:17] + node _T_2474 = and(_T_2473, _T_2465) @[dec_dec_ctl.scala 17:17] + node _T_2475 = and(_T_2474, _T_2466) @[dec_dec_ctl.scala 17:17] + node _T_2476 = and(_T_2475, _T_2468) @[dec_dec_ctl.scala 17:17] + node _T_2477 = and(_T_2476, _T_2469) @[dec_dec_ctl.scala 17:17] + node _T_2478 = and(_T_2477, _T_2471) @[dec_dec_ctl.scala 17:17] + node _T_2479 = or(_T_2459, _T_2478) @[dec_dec_ctl.scala 188:57] + io.out.zbs <= _T_2479 @[dec_dec_ctl.scala 188:14] + node _T_2480 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2481 = eq(_T_2480, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2482 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2483 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2484 = eq(_T_2483, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2485 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2486 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2487 = eq(_T_2486, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2488 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2489 = eq(_T_2488, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2490 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2491 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2492 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2493 = eq(_T_2492, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2494 = and(_T_2481, _T_2482) @[dec_dec_ctl.scala 17:17] + node _T_2495 = and(_T_2494, _T_2484) @[dec_dec_ctl.scala 17:17] + node _T_2496 = and(_T_2495, _T_2485) @[dec_dec_ctl.scala 17:17] + node _T_2497 = and(_T_2496, _T_2487) @[dec_dec_ctl.scala 17:17] + node _T_2498 = and(_T_2497, _T_2489) @[dec_dec_ctl.scala 17:17] + node _T_2499 = and(_T_2498, _T_2490) @[dec_dec_ctl.scala 17:17] + node _T_2500 = and(_T_2499, _T_2491) @[dec_dec_ctl.scala 17:17] + node _T_2501 = and(_T_2500, _T_2493) @[dec_dec_ctl.scala 17:17] + io.out.bext <= _T_2501 @[dec_dec_ctl.scala 190:15] + node _T_2502 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2503 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2504 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2505 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2506 = eq(_T_2505, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2507 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2508 = eq(_T_2507, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2509 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2510 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2511 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2512 = eq(_T_2511, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2513 = and(_T_2502, _T_2503) @[dec_dec_ctl.scala 17:17] + node _T_2514 = and(_T_2513, _T_2504) @[dec_dec_ctl.scala 17:17] + node _T_2515 = and(_T_2514, _T_2506) @[dec_dec_ctl.scala 17:17] + node _T_2516 = and(_T_2515, _T_2508) @[dec_dec_ctl.scala 17:17] + node _T_2517 = and(_T_2516, _T_2509) @[dec_dec_ctl.scala 17:17] + node _T_2518 = and(_T_2517, _T_2510) @[dec_dec_ctl.scala 17:17] + node _T_2519 = and(_T_2518, _T_2512) @[dec_dec_ctl.scala 17:17] + io.out.bdep <= _T_2519 @[dec_dec_ctl.scala 192:15] + node _T_2520 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2521 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2522 = eq(_T_2521, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2523 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2524 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2525 = eq(_T_2524, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2526 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2527 = eq(_T_2526, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2528 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2529 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2530 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2531 = eq(_T_2530, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2532 = and(_T_2520, _T_2522) @[dec_dec_ctl.scala 17:17] + node _T_2533 = and(_T_2532, _T_2523) @[dec_dec_ctl.scala 17:17] + node _T_2534 = and(_T_2533, _T_2525) @[dec_dec_ctl.scala 17:17] + node _T_2535 = and(_T_2534, _T_2527) @[dec_dec_ctl.scala 17:17] + node _T_2536 = and(_T_2535, _T_2528) @[dec_dec_ctl.scala 17:17] + node _T_2537 = and(_T_2536, _T_2529) @[dec_dec_ctl.scala 17:17] + node _T_2538 = and(_T_2537, _T_2531) @[dec_dec_ctl.scala 17:17] + io.out.zbe <= _T_2538 @[dec_dec_ctl.scala 194:14] + node _T_2539 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2540 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_2541 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2542 = eq(_T_2541, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2543 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2544 = eq(_T_2543, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2545 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2546 = eq(_T_2545, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2547 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2548 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2549 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2550 = eq(_T_2549, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2551 = and(_T_2539, _T_2540) @[dec_dec_ctl.scala 17:17] + node _T_2552 = and(_T_2551, _T_2542) @[dec_dec_ctl.scala 17:17] + node _T_2553 = and(_T_2552, _T_2544) @[dec_dec_ctl.scala 17:17] + node _T_2554 = and(_T_2553, _T_2546) @[dec_dec_ctl.scala 17:17] + node _T_2555 = and(_T_2554, _T_2547) @[dec_dec_ctl.scala 17:17] + node _T_2556 = and(_T_2555, _T_2548) @[dec_dec_ctl.scala 17:17] + node _T_2557 = and(_T_2556, _T_2550) @[dec_dec_ctl.scala 17:17] + io.out.clmul <= _T_2557 @[dec_dec_ctl.scala 196:16] + node _T_2558 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2559 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2560 = eq(_T_2559, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2561 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2562 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2563 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2564 = eq(_T_2563, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2565 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2566 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2567 = eq(_T_2566, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2568 = and(_T_2558, _T_2560) @[dec_dec_ctl.scala 17:17] + node _T_2569 = and(_T_2568, _T_2561) @[dec_dec_ctl.scala 17:17] + node _T_2570 = and(_T_2569, _T_2562) @[dec_dec_ctl.scala 17:17] + node _T_2571 = and(_T_2570, _T_2564) @[dec_dec_ctl.scala 17:17] + node _T_2572 = and(_T_2571, _T_2565) @[dec_dec_ctl.scala 17:17] + node _T_2573 = and(_T_2572, _T_2567) @[dec_dec_ctl.scala 17:17] + io.out.clmulh <= _T_2573 @[dec_dec_ctl.scala 198:17] + node _T_2574 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2575 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2576 = eq(_T_2575, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2577 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2578 = eq(_T_2577, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2579 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2580 = eq(_T_2579, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2581 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2582 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2583 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2584 = eq(_T_2583, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2585 = and(_T_2574, _T_2576) @[dec_dec_ctl.scala 17:17] + node _T_2586 = and(_T_2585, _T_2578) @[dec_dec_ctl.scala 17:17] + node _T_2587 = and(_T_2586, _T_2580) @[dec_dec_ctl.scala 17:17] + node _T_2588 = and(_T_2587, _T_2581) @[dec_dec_ctl.scala 17:17] + node _T_2589 = and(_T_2588, _T_2582) @[dec_dec_ctl.scala 17:17] + node _T_2590 = and(_T_2589, _T_2584) @[dec_dec_ctl.scala 17:17] + io.out.clmulr <= _T_2590 @[dec_dec_ctl.scala 200:17] + node _T_2591 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2592 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_2593 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2594 = eq(_T_2593, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2595 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2596 = eq(_T_2595, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2597 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2598 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2599 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2600 = eq(_T_2599, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2601 = and(_T_2591, _T_2592) @[dec_dec_ctl.scala 17:17] + node _T_2602 = and(_T_2601, _T_2594) @[dec_dec_ctl.scala 17:17] + node _T_2603 = and(_T_2602, _T_2596) @[dec_dec_ctl.scala 17:17] + node _T_2604 = and(_T_2603, _T_2597) @[dec_dec_ctl.scala 17:17] + node _T_2605 = and(_T_2604, _T_2598) @[dec_dec_ctl.scala 17:17] + node _T_2606 = and(_T_2605, _T_2600) @[dec_dec_ctl.scala 17:17] + io.out.zbc <= _T_2606 @[dec_dec_ctl.scala 202:14] + node _T_2607 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2608 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2609 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2610 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2611 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2612 = eq(_T_2611, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2613 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2614 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2615 = eq(_T_2614, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2616 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2617 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2618 = eq(_T_2617, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2619 = and(_T_2607, _T_2608) @[dec_dec_ctl.scala 17:17] + node _T_2620 = and(_T_2619, _T_2609) @[dec_dec_ctl.scala 17:17] + node _T_2621 = and(_T_2620, _T_2610) @[dec_dec_ctl.scala 17:17] + node _T_2622 = and(_T_2621, _T_2612) @[dec_dec_ctl.scala 17:17] + node _T_2623 = and(_T_2622, _T_2613) @[dec_dec_ctl.scala 17:17] + node _T_2624 = and(_T_2623, _T_2615) @[dec_dec_ctl.scala 17:17] + node _T_2625 = and(_T_2624, _T_2616) @[dec_dec_ctl.scala 17:17] + node _T_2626 = and(_T_2625, _T_2618) @[dec_dec_ctl.scala 17:17] + io.out.grev <= _T_2626 @[dec_dec_ctl.scala 204:15] + node _T_2627 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2628 = eq(_T_2627, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2629 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2630 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2631 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2632 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2633 = eq(_T_2632, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2634 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2635 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2636 = eq(_T_2635, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2637 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2638 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2639 = eq(_T_2638, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2640 = and(_T_2628, _T_2629) @[dec_dec_ctl.scala 17:17] + node _T_2641 = and(_T_2640, _T_2630) @[dec_dec_ctl.scala 17:17] + node _T_2642 = and(_T_2641, _T_2631) @[dec_dec_ctl.scala 17:17] + node _T_2643 = and(_T_2642, _T_2633) @[dec_dec_ctl.scala 17:17] + node _T_2644 = and(_T_2643, _T_2634) @[dec_dec_ctl.scala 17:17] + node _T_2645 = and(_T_2644, _T_2636) @[dec_dec_ctl.scala 17:17] + node _T_2646 = and(_T_2645, _T_2637) @[dec_dec_ctl.scala 17:17] + node _T_2647 = and(_T_2646, _T_2639) @[dec_dec_ctl.scala 17:17] + io.out.gorc <= _T_2647 @[dec_dec_ctl.scala 206:15] + node _T_2648 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2649 = eq(_T_2648, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2650 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2651 = eq(_T_2650, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2652 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2653 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2654 = eq(_T_2653, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2655 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2656 = eq(_T_2655, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2657 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2658 = eq(_T_2657, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2659 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2660 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2661 = eq(_T_2660, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2662 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2663 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2664 = eq(_T_2663, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2665 = and(_T_2649, _T_2651) @[dec_dec_ctl.scala 17:17] + node _T_2666 = and(_T_2665, _T_2652) @[dec_dec_ctl.scala 17:17] + node _T_2667 = and(_T_2666, _T_2654) @[dec_dec_ctl.scala 17:17] + node _T_2668 = and(_T_2667, _T_2656) @[dec_dec_ctl.scala 17:17] + node _T_2669 = and(_T_2668, _T_2658) @[dec_dec_ctl.scala 17:17] + node _T_2670 = and(_T_2669, _T_2659) @[dec_dec_ctl.scala 17:17] + node _T_2671 = and(_T_2670, _T_2661) @[dec_dec_ctl.scala 17:17] + node _T_2672 = and(_T_2671, _T_2662) @[dec_dec_ctl.scala 17:17] + node _T_2673 = and(_T_2672, _T_2664) @[dec_dec_ctl.scala 17:17] + io.out.shfl <= _T_2673 @[dec_dec_ctl.scala 208:15] + node _T_2674 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2675 = eq(_T_2674, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2676 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2677 = eq(_T_2676, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2678 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2679 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2680 = eq(_T_2679, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2681 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2682 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2683 = eq(_T_2682, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2684 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2685 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2686 = eq(_T_2685, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2687 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2688 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2689 = eq(_T_2688, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2690 = and(_T_2675, _T_2677) @[dec_dec_ctl.scala 17:17] + node _T_2691 = and(_T_2690, _T_2678) @[dec_dec_ctl.scala 17:17] + node _T_2692 = and(_T_2691, _T_2680) @[dec_dec_ctl.scala 17:17] + node _T_2693 = and(_T_2692, _T_2681) @[dec_dec_ctl.scala 17:17] + node _T_2694 = and(_T_2693, _T_2683) @[dec_dec_ctl.scala 17:17] + node _T_2695 = and(_T_2694, _T_2684) @[dec_dec_ctl.scala 17:17] + node _T_2696 = and(_T_2695, _T_2686) @[dec_dec_ctl.scala 17:17] + node _T_2697 = and(_T_2696, _T_2687) @[dec_dec_ctl.scala 17:17] + node _T_2698 = and(_T_2697, _T_2689) @[dec_dec_ctl.scala 17:17] + io.out.unshfl <= _T_2698 @[dec_dec_ctl.scala 210:17] + node _T_2699 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2700 = eq(_T_2699, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2701 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2702 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2703 = eq(_T_2702, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2704 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2705 = eq(_T_2704, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2706 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2707 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2708 = eq(_T_2707, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2709 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2710 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2711 = eq(_T_2710, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2712 = and(_T_2700, _T_2701) @[dec_dec_ctl.scala 17:17] + node _T_2713 = and(_T_2712, _T_2703) @[dec_dec_ctl.scala 17:17] + node _T_2714 = and(_T_2713, _T_2705) @[dec_dec_ctl.scala 17:17] + node _T_2715 = and(_T_2714, _T_2706) @[dec_dec_ctl.scala 17:17] + node _T_2716 = and(_T_2715, _T_2708) @[dec_dec_ctl.scala 17:17] + node _T_2717 = and(_T_2716, _T_2709) @[dec_dec_ctl.scala 17:17] + node _T_2718 = and(_T_2717, _T_2711) @[dec_dec_ctl.scala 17:17] + node _T_2719 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2720 = eq(_T_2719, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2721 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2722 = eq(_T_2721, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2723 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2724 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2725 = eq(_T_2724, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2726 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2727 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2728 = eq(_T_2727, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2729 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2730 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2731 = eq(_T_2730, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2732 = and(_T_2720, _T_2722) @[dec_dec_ctl.scala 17:17] + node _T_2733 = and(_T_2732, _T_2723) @[dec_dec_ctl.scala 17:17] + node _T_2734 = and(_T_2733, _T_2725) @[dec_dec_ctl.scala 17:17] + node _T_2735 = and(_T_2734, _T_2726) @[dec_dec_ctl.scala 17:17] + node _T_2736 = and(_T_2735, _T_2728) @[dec_dec_ctl.scala 17:17] + node _T_2737 = and(_T_2736, _T_2729) @[dec_dec_ctl.scala 17:17] + node _T_2738 = and(_T_2737, _T_2731) @[dec_dec_ctl.scala 17:17] + node _T_2739 = or(_T_2718, _T_2738) @[dec_dec_ctl.scala 212:58] + node _T_2740 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2741 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2742 = eq(_T_2741, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2743 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2744 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2745 = eq(_T_2744, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2746 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2747 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2748 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2749 = eq(_T_2748, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2750 = and(_T_2740, _T_2742) @[dec_dec_ctl.scala 17:17] + node _T_2751 = and(_T_2750, _T_2743) @[dec_dec_ctl.scala 17:17] + node _T_2752 = and(_T_2751, _T_2745) @[dec_dec_ctl.scala 17:17] + node _T_2753 = and(_T_2752, _T_2746) @[dec_dec_ctl.scala 17:17] + node _T_2754 = and(_T_2753, _T_2747) @[dec_dec_ctl.scala 17:17] + node _T_2755 = and(_T_2754, _T_2749) @[dec_dec_ctl.scala 17:17] + node _T_2756 = or(_T_2739, _T_2755) @[dec_dec_ctl.scala 212:101] + node _T_2757 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2758 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2759 = eq(_T_2758, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2760 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2761 = eq(_T_2760, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2762 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2763 = eq(_T_2762, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2764 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2765 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2766 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2767 = eq(_T_2766, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2768 = and(_T_2757, _T_2759) @[dec_dec_ctl.scala 17:17] + node _T_2769 = and(_T_2768, _T_2761) @[dec_dec_ctl.scala 17:17] + node _T_2770 = and(_T_2769, _T_2763) @[dec_dec_ctl.scala 17:17] + node _T_2771 = and(_T_2770, _T_2764) @[dec_dec_ctl.scala 17:17] + node _T_2772 = and(_T_2771, _T_2765) @[dec_dec_ctl.scala 17:17] + node _T_2773 = and(_T_2772, _T_2767) @[dec_dec_ctl.scala 17:17] + node _T_2774 = or(_T_2756, _T_2773) @[dec_dec_ctl.scala 213:40] + node _T_2775 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2776 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2777 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2778 = eq(_T_2777, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2779 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2780 = eq(_T_2779, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2781 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2782 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2783 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2784 = eq(_T_2783, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2785 = and(_T_2775, _T_2776) @[dec_dec_ctl.scala 17:17] + node _T_2786 = and(_T_2785, _T_2778) @[dec_dec_ctl.scala 17:17] + node _T_2787 = and(_T_2786, _T_2780) @[dec_dec_ctl.scala 17:17] + node _T_2788 = and(_T_2787, _T_2781) @[dec_dec_ctl.scala 17:17] + node _T_2789 = and(_T_2788, _T_2782) @[dec_dec_ctl.scala 17:17] + node _T_2790 = and(_T_2789, _T_2784) @[dec_dec_ctl.scala 17:17] + node _T_2791 = or(_T_2774, _T_2790) @[dec_dec_ctl.scala 213:79] + node _T_2792 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2793 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2794 = eq(_T_2793, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2795 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2796 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2797 = eq(_T_2796, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2798 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2799 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2800 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2801 = eq(_T_2800, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2802 = and(_T_2792, _T_2794) @[dec_dec_ctl.scala 17:17] + node _T_2803 = and(_T_2802, _T_2795) @[dec_dec_ctl.scala 17:17] + node _T_2804 = and(_T_2803, _T_2797) @[dec_dec_ctl.scala 17:17] + node _T_2805 = and(_T_2804, _T_2798) @[dec_dec_ctl.scala 17:17] + node _T_2806 = and(_T_2805, _T_2799) @[dec_dec_ctl.scala 17:17] + node _T_2807 = and(_T_2806, _T_2801) @[dec_dec_ctl.scala 17:17] + node _T_2808 = or(_T_2791, _T_2807) @[dec_dec_ctl.scala 214:41] + node _T_2809 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2810 = eq(_T_2809, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2811 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2812 = eq(_T_2811, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2813 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2814 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2815 = eq(_T_2814, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2816 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2817 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2818 = eq(_T_2817, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2819 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2820 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2821 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2822 = eq(_T_2821, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2823 = and(_T_2810, _T_2812) @[dec_dec_ctl.scala 17:17] + node _T_2824 = and(_T_2823, _T_2813) @[dec_dec_ctl.scala 17:17] + node _T_2825 = and(_T_2824, _T_2815) @[dec_dec_ctl.scala 17:17] + node _T_2826 = and(_T_2825, _T_2816) @[dec_dec_ctl.scala 17:17] + node _T_2827 = and(_T_2826, _T_2818) @[dec_dec_ctl.scala 17:17] + node _T_2828 = and(_T_2827, _T_2819) @[dec_dec_ctl.scala 17:17] + node _T_2829 = and(_T_2828, _T_2820) @[dec_dec_ctl.scala 17:17] + node _T_2830 = and(_T_2829, _T_2822) @[dec_dec_ctl.scala 17:17] + node _T_2831 = or(_T_2808, _T_2830) @[dec_dec_ctl.scala 214:78] + node _T_2832 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2833 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2834 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2835 = eq(_T_2834, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2836 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2837 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2838 = eq(_T_2837, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2839 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2840 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2841 = eq(_T_2840, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2842 = and(_T_2832, _T_2833) @[dec_dec_ctl.scala 17:17] + node _T_2843 = and(_T_2842, _T_2835) @[dec_dec_ctl.scala 17:17] + node _T_2844 = and(_T_2843, _T_2836) @[dec_dec_ctl.scala 17:17] + node _T_2845 = and(_T_2844, _T_2838) @[dec_dec_ctl.scala 17:17] + node _T_2846 = and(_T_2845, _T_2839) @[dec_dec_ctl.scala 17:17] + node _T_2847 = and(_T_2846, _T_2841) @[dec_dec_ctl.scala 17:17] + node _T_2848 = or(_T_2831, _T_2847) @[dec_dec_ctl.scala 215:48] + io.out.zbp <= _T_2848 @[dec_dec_ctl.scala 212:14] + node _T_2849 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2850 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2851 = eq(_T_2850, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2852 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2853 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_2854 = eq(_T_2853, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2855 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_2856 = eq(_T_2855, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2857 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_2858 = eq(_T_2857, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2859 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2860 = eq(_T_2859, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2861 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2862 = eq(_T_2861, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2863 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2864 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2865 = eq(_T_2864, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2866 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2867 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2868 = eq(_T_2867, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2869 = and(_T_2849, _T_2851) @[dec_dec_ctl.scala 17:17] + node _T_2870 = and(_T_2869, _T_2852) @[dec_dec_ctl.scala 17:17] + node _T_2871 = and(_T_2870, _T_2854) @[dec_dec_ctl.scala 17:17] + node _T_2872 = and(_T_2871, _T_2856) @[dec_dec_ctl.scala 17:17] + node _T_2873 = and(_T_2872, _T_2858) @[dec_dec_ctl.scala 17:17] + node _T_2874 = and(_T_2873, _T_2860) @[dec_dec_ctl.scala 17:17] + node _T_2875 = and(_T_2874, _T_2862) @[dec_dec_ctl.scala 17:17] + node _T_2876 = and(_T_2875, _T_2863) @[dec_dec_ctl.scala 17:17] + node _T_2877 = and(_T_2876, _T_2865) @[dec_dec_ctl.scala 17:17] + node _T_2878 = and(_T_2877, _T_2866) @[dec_dec_ctl.scala 17:17] + node _T_2879 = and(_T_2878, _T_2868) @[dec_dec_ctl.scala 17:17] + io.out.crc32_b <= _T_2879 @[dec_dec_ctl.scala 217:18] + node _T_2880 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2881 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2882 = eq(_T_2881, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2883 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2884 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_2885 = eq(_T_2884, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2886 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_2887 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2888 = eq(_T_2887, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2889 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2890 = eq(_T_2889, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2891 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2892 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2893 = eq(_T_2892, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2894 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2895 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2896 = eq(_T_2895, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2897 = and(_T_2880, _T_2882) @[dec_dec_ctl.scala 17:17] + node _T_2898 = and(_T_2897, _T_2883) @[dec_dec_ctl.scala 17:17] + node _T_2899 = and(_T_2898, _T_2885) @[dec_dec_ctl.scala 17:17] + node _T_2900 = and(_T_2899, _T_2886) @[dec_dec_ctl.scala 17:17] + node _T_2901 = and(_T_2900, _T_2888) @[dec_dec_ctl.scala 17:17] + node _T_2902 = and(_T_2901, _T_2890) @[dec_dec_ctl.scala 17:17] + node _T_2903 = and(_T_2902, _T_2891) @[dec_dec_ctl.scala 17:17] + node _T_2904 = and(_T_2903, _T_2893) @[dec_dec_ctl.scala 17:17] + node _T_2905 = and(_T_2904, _T_2894) @[dec_dec_ctl.scala 17:17] + node _T_2906 = and(_T_2905, _T_2896) @[dec_dec_ctl.scala 17:17] + io.out.crc32_h <= _T_2906 @[dec_dec_ctl.scala 219:18] + node _T_2907 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2908 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2909 = eq(_T_2908, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2910 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2911 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_2912 = eq(_T_2911, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2913 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_2914 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2915 = eq(_T_2914, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2916 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2917 = eq(_T_2916, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2918 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2919 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2920 = eq(_T_2919, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2921 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2922 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2923 = eq(_T_2922, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2924 = and(_T_2907, _T_2909) @[dec_dec_ctl.scala 17:17] + node _T_2925 = and(_T_2924, _T_2910) @[dec_dec_ctl.scala 17:17] + node _T_2926 = and(_T_2925, _T_2912) @[dec_dec_ctl.scala 17:17] + node _T_2927 = and(_T_2926, _T_2913) @[dec_dec_ctl.scala 17:17] + node _T_2928 = and(_T_2927, _T_2915) @[dec_dec_ctl.scala 17:17] + node _T_2929 = and(_T_2928, _T_2917) @[dec_dec_ctl.scala 17:17] + node _T_2930 = and(_T_2929, _T_2918) @[dec_dec_ctl.scala 17:17] + node _T_2931 = and(_T_2930, _T_2920) @[dec_dec_ctl.scala 17:17] + node _T_2932 = and(_T_2931, _T_2921) @[dec_dec_ctl.scala 17:17] + node _T_2933 = and(_T_2932, _T_2923) @[dec_dec_ctl.scala 17:17] + io.out.crc32_w <= _T_2933 @[dec_dec_ctl.scala 221:18] + node _T_2934 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2935 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2936 = eq(_T_2935, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2937 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_2938 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_2939 = eq(_T_2938, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2940 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_2941 = eq(_T_2940, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2942 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2943 = eq(_T_2942, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2944 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2945 = eq(_T_2944, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2946 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2947 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2948 = eq(_T_2947, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2949 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2950 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2951 = eq(_T_2950, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2952 = and(_T_2934, _T_2936) @[dec_dec_ctl.scala 17:17] + node _T_2953 = and(_T_2952, _T_2937) @[dec_dec_ctl.scala 17:17] + node _T_2954 = and(_T_2953, _T_2939) @[dec_dec_ctl.scala 17:17] + node _T_2955 = and(_T_2954, _T_2941) @[dec_dec_ctl.scala 17:17] + node _T_2956 = and(_T_2955, _T_2943) @[dec_dec_ctl.scala 17:17] + node _T_2957 = and(_T_2956, _T_2945) @[dec_dec_ctl.scala 17:17] + node _T_2958 = and(_T_2957, _T_2946) @[dec_dec_ctl.scala 17:17] + node _T_2959 = and(_T_2958, _T_2948) @[dec_dec_ctl.scala 17:17] + node _T_2960 = and(_T_2959, _T_2949) @[dec_dec_ctl.scala 17:17] + node _T_2961 = and(_T_2960, _T_2951) @[dec_dec_ctl.scala 17:17] + io.out.crc32c_b <= _T_2961 @[dec_dec_ctl.scala 223:19] + node _T_2962 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2963 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2964 = eq(_T_2963, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2965 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_2966 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_2967 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2968 = eq(_T_2967, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2969 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2970 = eq(_T_2969, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2971 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2972 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2973 = eq(_T_2972, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2974 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2975 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2976 = eq(_T_2975, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2977 = and(_T_2962, _T_2964) @[dec_dec_ctl.scala 17:17] + node _T_2978 = and(_T_2977, _T_2965) @[dec_dec_ctl.scala 17:17] + node _T_2979 = and(_T_2978, _T_2966) @[dec_dec_ctl.scala 17:17] + node _T_2980 = and(_T_2979, _T_2968) @[dec_dec_ctl.scala 17:17] + node _T_2981 = and(_T_2980, _T_2970) @[dec_dec_ctl.scala 17:17] + node _T_2982 = and(_T_2981, _T_2971) @[dec_dec_ctl.scala 17:17] + node _T_2983 = and(_T_2982, _T_2973) @[dec_dec_ctl.scala 17:17] + node _T_2984 = and(_T_2983, _T_2974) @[dec_dec_ctl.scala 17:17] + node _T_2985 = and(_T_2984, _T_2976) @[dec_dec_ctl.scala 17:17] + io.out.crc32c_h <= _T_2985 @[dec_dec_ctl.scala 225:19] + node _T_2986 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2987 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2988 = eq(_T_2987, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2989 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_2990 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_2991 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2992 = eq(_T_2991, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2993 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2994 = eq(_T_2993, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2995 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2996 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2997 = eq(_T_2996, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2998 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2999 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3000 = eq(_T_2999, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3001 = and(_T_2986, _T_2988) @[dec_dec_ctl.scala 17:17] + node _T_3002 = and(_T_3001, _T_2989) @[dec_dec_ctl.scala 17:17] + node _T_3003 = and(_T_3002, _T_2990) @[dec_dec_ctl.scala 17:17] + node _T_3004 = and(_T_3003, _T_2992) @[dec_dec_ctl.scala 17:17] + node _T_3005 = and(_T_3004, _T_2994) @[dec_dec_ctl.scala 17:17] + node _T_3006 = and(_T_3005, _T_2995) @[dec_dec_ctl.scala 17:17] + node _T_3007 = and(_T_3006, _T_2997) @[dec_dec_ctl.scala 17:17] + node _T_3008 = and(_T_3007, _T_2998) @[dec_dec_ctl.scala 17:17] + node _T_3009 = and(_T_3008, _T_3000) @[dec_dec_ctl.scala 17:17] + io.out.crc32c_w <= _T_3009 @[dec_dec_ctl.scala 227:19] + node _T_3010 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_3011 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3012 = eq(_T_3011, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3013 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_3014 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3015 = eq(_T_3014, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3016 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3017 = eq(_T_3016, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3018 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_3019 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3020 = eq(_T_3019, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3021 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3022 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3023 = eq(_T_3022, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3024 = and(_T_3010, _T_3012) @[dec_dec_ctl.scala 17:17] + node _T_3025 = and(_T_3024, _T_3013) @[dec_dec_ctl.scala 17:17] + node _T_3026 = and(_T_3025, _T_3015) @[dec_dec_ctl.scala 17:17] + node _T_3027 = and(_T_3026, _T_3017) @[dec_dec_ctl.scala 17:17] + node _T_3028 = and(_T_3027, _T_3018) @[dec_dec_ctl.scala 17:17] + node _T_3029 = and(_T_3028, _T_3020) @[dec_dec_ctl.scala 17:17] + node _T_3030 = and(_T_3029, _T_3021) @[dec_dec_ctl.scala 17:17] + node _T_3031 = and(_T_3030, _T_3023) @[dec_dec_ctl.scala 17:17] + io.out.zbr <= _T_3031 @[dec_dec_ctl.scala 229:14] + node _T_3032 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_3033 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_3034 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_3035 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_3036 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3037 = eq(_T_3036, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3038 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3039 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3040 = eq(_T_3039, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3041 = and(_T_3032, _T_3033) @[dec_dec_ctl.scala 17:17] + node _T_3042 = and(_T_3041, _T_3034) @[dec_dec_ctl.scala 17:17] + node _T_3043 = and(_T_3042, _T_3035) @[dec_dec_ctl.scala 17:17] + node _T_3044 = and(_T_3043, _T_3037) @[dec_dec_ctl.scala 17:17] + node _T_3045 = and(_T_3044, _T_3038) @[dec_dec_ctl.scala 17:17] + node _T_3046 = and(_T_3045, _T_3040) @[dec_dec_ctl.scala 17:17] + io.out.bfp <= _T_3046 @[dec_dec_ctl.scala 231:14] + node _T_3047 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_3048 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_3049 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_3050 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_3051 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3052 = eq(_T_3051, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3053 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3054 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3055 = eq(_T_3054, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3056 = and(_T_3047, _T_3048) @[dec_dec_ctl.scala 17:17] + node _T_3057 = and(_T_3056, _T_3049) @[dec_dec_ctl.scala 17:17] + node _T_3058 = and(_T_3057, _T_3050) @[dec_dec_ctl.scala 17:17] + node _T_3059 = and(_T_3058, _T_3052) @[dec_dec_ctl.scala 17:17] + node _T_3060 = and(_T_3059, _T_3053) @[dec_dec_ctl.scala 17:17] + node _T_3061 = and(_T_3060, _T_3055) @[dec_dec_ctl.scala 17:17] + io.out.zbf <= _T_3061 @[dec_dec_ctl.scala 233:14] + node _T_3062 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3063 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3064 = eq(_T_3063, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3065 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3066 = eq(_T_3065, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3067 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3068 = eq(_T_3067, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3069 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3070 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3071 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3072 = eq(_T_3071, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3073 = and(_T_3062, _T_3064) @[dec_dec_ctl.scala 17:17] + node _T_3074 = and(_T_3073, _T_3066) @[dec_dec_ctl.scala 17:17] + node _T_3075 = and(_T_3074, _T_3068) @[dec_dec_ctl.scala 17:17] + node _T_3076 = and(_T_3075, _T_3069) @[dec_dec_ctl.scala 17:17] + node _T_3077 = and(_T_3076, _T_3070) @[dec_dec_ctl.scala 17:17] + node _T_3078 = and(_T_3077, _T_3072) @[dec_dec_ctl.scala 17:17] + io.out.sh1add <= _T_3078 @[dec_dec_ctl.scala 235:17] + node _T_3079 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3080 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_3081 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3082 = eq(_T_3081, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3083 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3084 = eq(_T_3083, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3085 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3086 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3087 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3088 = eq(_T_3087, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3089 = and(_T_3079, _T_3080) @[dec_dec_ctl.scala 17:17] + node _T_3090 = and(_T_3089, _T_3082) @[dec_dec_ctl.scala 17:17] + node _T_3091 = and(_T_3090, _T_3084) @[dec_dec_ctl.scala 17:17] + node _T_3092 = and(_T_3091, _T_3085) @[dec_dec_ctl.scala 17:17] + node _T_3093 = and(_T_3092, _T_3086) @[dec_dec_ctl.scala 17:17] + node _T_3094 = and(_T_3093, _T_3088) @[dec_dec_ctl.scala 17:17] + io.out.sh2add <= _T_3094 @[dec_dec_ctl.scala 237:17] + node _T_3095 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3096 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_3097 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_3098 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3099 = eq(_T_3098, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3100 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3101 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3102 = eq(_T_3101, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3103 = and(_T_3095, _T_3096) @[dec_dec_ctl.scala 17:17] + node _T_3104 = and(_T_3103, _T_3097) @[dec_dec_ctl.scala 17:17] + node _T_3105 = and(_T_3104, _T_3099) @[dec_dec_ctl.scala 17:17] + node _T_3106 = and(_T_3105, _T_3100) @[dec_dec_ctl.scala 17:17] + node _T_3107 = and(_T_3106, _T_3102) @[dec_dec_ctl.scala 17:17] + io.out.sh3add <= _T_3107 @[dec_dec_ctl.scala 239:17] + node _T_3108 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3109 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3110 = eq(_T_3109, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3111 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3112 = eq(_T_3111, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3113 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3114 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3115 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3116 = eq(_T_3115, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3117 = and(_T_3108, _T_3110) @[dec_dec_ctl.scala 17:17] + node _T_3118 = and(_T_3117, _T_3112) @[dec_dec_ctl.scala 17:17] + node _T_3119 = and(_T_3118, _T_3113) @[dec_dec_ctl.scala 17:17] + node _T_3120 = and(_T_3119, _T_3114) @[dec_dec_ctl.scala 17:17] + node _T_3121 = and(_T_3120, _T_3116) @[dec_dec_ctl.scala 17:17] + io.out.zba <= _T_3121 @[dec_dec_ctl.scala 241:14] + node _T_3122 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:34] + node _T_3123 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_3124 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3125 = eq(_T_3124, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3126 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3127 = eq(_T_3126, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3128 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3129 = and(_T_3122, _T_3123) @[dec_dec_ctl.scala 17:17] + node _T_3130 = and(_T_3129, _T_3125) @[dec_dec_ctl.scala 17:17] + node _T_3131 = and(_T_3130, _T_3127) @[dec_dec_ctl.scala 17:17] + node _T_3132 = and(_T_3131, _T_3128) @[dec_dec_ctl.scala 17:17] + node _T_3133 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3134 = eq(_T_3133, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3135 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3136 = eq(_T_3135, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3137 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3138 = eq(_T_3137, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3139 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3140 = eq(_T_3139, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3141 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3142 = eq(_T_3141, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3143 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3144 = and(_T_3134, _T_3136) @[dec_dec_ctl.scala 17:17] + node _T_3145 = and(_T_3144, _T_3138) @[dec_dec_ctl.scala 17:17] + node _T_3146 = and(_T_3145, _T_3140) @[dec_dec_ctl.scala 17:17] + node _T_3147 = and(_T_3146, _T_3142) @[dec_dec_ctl.scala 17:17] + node _T_3148 = and(_T_3147, _T_3143) @[dec_dec_ctl.scala 17:17] + node _T_3149 = or(_T_3132, _T_3148) @[dec_dec_ctl.scala 243:51] + node _T_3150 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3151 = eq(_T_3150, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3152 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3153 = eq(_T_3152, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3154 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3155 = eq(_T_3154, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3156 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3157 = eq(_T_3156, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3158 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_3159 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3160 = eq(_T_3159, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3161 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3162 = and(_T_3151, _T_3153) @[dec_dec_ctl.scala 17:17] + node _T_3163 = and(_T_3162, _T_3155) @[dec_dec_ctl.scala 17:17] + node _T_3164 = and(_T_3163, _T_3157) @[dec_dec_ctl.scala 17:17] + node _T_3165 = and(_T_3164, _T_3158) @[dec_dec_ctl.scala 17:17] + node _T_3166 = and(_T_3165, _T_3160) @[dec_dec_ctl.scala 17:17] + node _T_3167 = and(_T_3166, _T_3161) @[dec_dec_ctl.scala 17:17] + node _T_3168 = or(_T_3149, _T_3167) @[dec_dec_ctl.scala 243:89] + node _T_3169 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3170 = eq(_T_3169, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3171 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3172 = eq(_T_3171, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3173 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3174 = eq(_T_3173, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3175 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3176 = eq(_T_3175, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3177 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3178 = eq(_T_3177, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3179 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3180 = and(_T_3170, _T_3172) @[dec_dec_ctl.scala 17:17] + node _T_3181 = and(_T_3180, _T_3174) @[dec_dec_ctl.scala 17:17] + node _T_3182 = and(_T_3181, _T_3176) @[dec_dec_ctl.scala 17:17] + node _T_3183 = and(_T_3182, _T_3178) @[dec_dec_ctl.scala 17:17] + node _T_3184 = and(_T_3183, _T_3179) @[dec_dec_ctl.scala 17:17] + node _T_3185 = or(_T_3168, _T_3184) @[dec_dec_ctl.scala 244:44] + node _T_3186 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_3187 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3188 = eq(_T_3187, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3189 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3190 = and(_T_3186, _T_3188) @[dec_dec_ctl.scala 17:17] + node _T_3191 = and(_T_3190, _T_3189) @[dec_dec_ctl.scala 17:17] + node _T_3192 = or(_T_3185, _T_3191) @[dec_dec_ctl.scala 244:82] + node _T_3193 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3194 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_3195 = and(_T_3193, _T_3194) @[dec_dec_ctl.scala 17:17] + node _T_3196 = or(_T_3192, _T_3195) @[dec_dec_ctl.scala 245:28] + node _T_3197 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3198 = eq(_T_3197, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3199 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3200 = eq(_T_3199, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3201 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3202 = and(_T_3198, _T_3200) @[dec_dec_ctl.scala 17:17] + node _T_3203 = and(_T_3202, _T_3201) @[dec_dec_ctl.scala 17:17] + node _T_3204 = or(_T_3196, _T_3203) @[dec_dec_ctl.scala 245:49] + io.out.pm_alu <= _T_3204 @[dec_dec_ctl.scala 243:17] + node _T_3205 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3206 = eq(_T_3205, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3207 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3208 = eq(_T_3207, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3209 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3210 = eq(_T_3209, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3211 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:34] + node _T_3212 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3213 = eq(_T_3212, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3214 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3215 = eq(_T_3214, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3216 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3217 = eq(_T_3216, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3218 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_3219 = eq(_T_3218, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3220 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_3221 = eq(_T_3220, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3222 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_3223 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_3224 = eq(_T_3223, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3225 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_3226 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53] + node _T_3227 = eq(_T_3226, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3228 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53] + node _T_3229 = eq(_T_3228, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3230 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53] + node _T_3231 = eq(_T_3230, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3232 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53] + node _T_3233 = eq(_T_3232, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3234 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53] + node _T_3235 = eq(_T_3234, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3236 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3237 = eq(_T_3236, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3238 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53] + node _T_3239 = eq(_T_3238, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3240 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53] + node _T_3241 = eq(_T_3240, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3242 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53] + node _T_3243 = eq(_T_3242, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3244 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53] + node _T_3245 = eq(_T_3244, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3246 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53] + node _T_3247 = eq(_T_3246, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3248 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_3249 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3250 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3251 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3252 = eq(_T_3251, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3253 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3254 = eq(_T_3253, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3255 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3256 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3257 = and(_T_3206, _T_3208) @[dec_dec_ctl.scala 17:17] + node _T_3258 = and(_T_3257, _T_3210) @[dec_dec_ctl.scala 17:17] + node _T_3259 = and(_T_3258, _T_3211) @[dec_dec_ctl.scala 17:17] + node _T_3260 = and(_T_3259, _T_3213) @[dec_dec_ctl.scala 17:17] + node _T_3261 = and(_T_3260, _T_3215) @[dec_dec_ctl.scala 17:17] + node _T_3262 = and(_T_3261, _T_3217) @[dec_dec_ctl.scala 17:17] + node _T_3263 = and(_T_3262, _T_3219) @[dec_dec_ctl.scala 17:17] + node _T_3264 = and(_T_3263, _T_3221) @[dec_dec_ctl.scala 17:17] + node _T_3265 = and(_T_3264, _T_3222) @[dec_dec_ctl.scala 17:17] + node _T_3266 = and(_T_3265, _T_3224) @[dec_dec_ctl.scala 17:17] + node _T_3267 = and(_T_3266, _T_3225) @[dec_dec_ctl.scala 17:17] + node _T_3268 = and(_T_3267, _T_3227) @[dec_dec_ctl.scala 17:17] + node _T_3269 = and(_T_3268, _T_3229) @[dec_dec_ctl.scala 17:17] + node _T_3270 = and(_T_3269, _T_3231) @[dec_dec_ctl.scala 17:17] + node _T_3271 = and(_T_3270, _T_3233) @[dec_dec_ctl.scala 17:17] + node _T_3272 = and(_T_3271, _T_3235) @[dec_dec_ctl.scala 17:17] + node _T_3273 = and(_T_3272, _T_3237) @[dec_dec_ctl.scala 17:17] + node _T_3274 = and(_T_3273, _T_3239) @[dec_dec_ctl.scala 17:17] + node _T_3275 = and(_T_3274, _T_3241) @[dec_dec_ctl.scala 17:17] + node _T_3276 = and(_T_3275, _T_3243) @[dec_dec_ctl.scala 17:17] + node _T_3277 = and(_T_3276, _T_3245) @[dec_dec_ctl.scala 17:17] + node _T_3278 = and(_T_3277, _T_3247) @[dec_dec_ctl.scala 17:17] + node _T_3279 = and(_T_3278, _T_3248) @[dec_dec_ctl.scala 17:17] + node _T_3280 = and(_T_3279, _T_3249) @[dec_dec_ctl.scala 17:17] + node _T_3281 = and(_T_3280, _T_3250) @[dec_dec_ctl.scala 17:17] + node _T_3282 = and(_T_3281, _T_3252) @[dec_dec_ctl.scala 17:17] + node _T_3283 = and(_T_3282, _T_3254) @[dec_dec_ctl.scala 17:17] + node _T_3284 = and(_T_3283, _T_3255) @[dec_dec_ctl.scala 17:17] + node _T_3285 = and(_T_3284, _T_3256) @[dec_dec_ctl.scala 17:17] + node _T_3286 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3287 = eq(_T_3286, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3288 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3289 = eq(_T_3288, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3290 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3291 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:34] + node _T_3292 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3293 = eq(_T_3292, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3294 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3295 = eq(_T_3294, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3296 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3297 = eq(_T_3296, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3298 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_3299 = eq(_T_3298, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3300 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_3301 = eq(_T_3300, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3302 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_3303 = eq(_T_3302, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3304 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_3305 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_3306 = eq(_T_3305, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3307 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53] + node _T_3308 = eq(_T_3307, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3309 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53] + node _T_3310 = eq(_T_3309, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3311 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53] + node _T_3312 = eq(_T_3311, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3313 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53] + node _T_3314 = eq(_T_3313, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3315 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53] + node _T_3316 = eq(_T_3315, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3317 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3318 = eq(_T_3317, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3319 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53] + node _T_3320 = eq(_T_3319, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3321 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53] + node _T_3322 = eq(_T_3321, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3323 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53] + node _T_3324 = eq(_T_3323, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3325 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53] + node _T_3326 = eq(_T_3325, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3327 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53] + node _T_3328 = eq(_T_3327, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3329 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_3330 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3331 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3332 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3333 = eq(_T_3332, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3334 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3335 = eq(_T_3334, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3336 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3337 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3338 = and(_T_3287, _T_3289) @[dec_dec_ctl.scala 17:17] + node _T_3339 = and(_T_3338, _T_3290) @[dec_dec_ctl.scala 17:17] + node _T_3340 = and(_T_3339, _T_3291) @[dec_dec_ctl.scala 17:17] + node _T_3341 = and(_T_3340, _T_3293) @[dec_dec_ctl.scala 17:17] + node _T_3342 = and(_T_3341, _T_3295) @[dec_dec_ctl.scala 17:17] + node _T_3343 = and(_T_3342, _T_3297) @[dec_dec_ctl.scala 17:17] + node _T_3344 = and(_T_3343, _T_3299) @[dec_dec_ctl.scala 17:17] + node _T_3345 = and(_T_3344, _T_3301) @[dec_dec_ctl.scala 17:17] + node _T_3346 = and(_T_3345, _T_3303) @[dec_dec_ctl.scala 17:17] + node _T_3347 = and(_T_3346, _T_3304) @[dec_dec_ctl.scala 17:17] + node _T_3348 = and(_T_3347, _T_3306) @[dec_dec_ctl.scala 17:17] + node _T_3349 = and(_T_3348, _T_3308) @[dec_dec_ctl.scala 17:17] + node _T_3350 = and(_T_3349, _T_3310) @[dec_dec_ctl.scala 17:17] + node _T_3351 = and(_T_3350, _T_3312) @[dec_dec_ctl.scala 17:17] + node _T_3352 = and(_T_3351, _T_3314) @[dec_dec_ctl.scala 17:17] + node _T_3353 = and(_T_3352, _T_3316) @[dec_dec_ctl.scala 17:17] + node _T_3354 = and(_T_3353, _T_3318) @[dec_dec_ctl.scala 17:17] + node _T_3355 = and(_T_3354, _T_3320) @[dec_dec_ctl.scala 17:17] + node _T_3356 = and(_T_3355, _T_3322) @[dec_dec_ctl.scala 17:17] + node _T_3357 = and(_T_3356, _T_3324) @[dec_dec_ctl.scala 17:17] + node _T_3358 = and(_T_3357, _T_3326) @[dec_dec_ctl.scala 17:17] + node _T_3359 = and(_T_3358, _T_3328) @[dec_dec_ctl.scala 17:17] + node _T_3360 = and(_T_3359, _T_3329) @[dec_dec_ctl.scala 17:17] + node _T_3361 = and(_T_3360, _T_3330) @[dec_dec_ctl.scala 17:17] + node _T_3362 = and(_T_3361, _T_3331) @[dec_dec_ctl.scala 17:17] + node _T_3363 = and(_T_3362, _T_3333) @[dec_dec_ctl.scala 17:17] + node _T_3364 = and(_T_3363, _T_3335) @[dec_dec_ctl.scala 17:17] + node _T_3365 = and(_T_3364, _T_3336) @[dec_dec_ctl.scala 17:17] + node _T_3366 = and(_T_3365, _T_3337) @[dec_dec_ctl.scala 17:17] + node _T_3367 = or(_T_3285, _T_3366) @[dec_dec_ctl.scala 248:136] + node _T_3368 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3369 = eq(_T_3368, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3370 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3371 = eq(_T_3370, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3372 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3373 = eq(_T_3372, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3374 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3375 = eq(_T_3374, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3376 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3377 = eq(_T_3376, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3378 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3379 = eq(_T_3378, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3380 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3381 = eq(_T_3380, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3382 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_3383 = eq(_T_3382, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3384 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_3385 = eq(_T_3384, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3386 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_3387 = eq(_T_3386, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3388 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_3389 = eq(_T_3388, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3390 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53] + node _T_3391 = eq(_T_3390, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3392 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53] + node _T_3393 = eq(_T_3392, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3394 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53] + node _T_3395 = eq(_T_3394, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3396 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53] + node _T_3397 = eq(_T_3396, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3398 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53] + node _T_3399 = eq(_T_3398, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3400 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3401 = eq(_T_3400, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3402 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53] + node _T_3403 = eq(_T_3402, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3404 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53] + node _T_3405 = eq(_T_3404, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3406 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53] + node _T_3407 = eq(_T_3406, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3408 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53] + node _T_3409 = eq(_T_3408, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3410 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53] + node _T_3411 = eq(_T_3410, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3412 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3413 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3414 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3415 = eq(_T_3414, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3416 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3417 = eq(_T_3416, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3418 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3419 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3420 = and(_T_3369, _T_3371) @[dec_dec_ctl.scala 17:17] + node _T_3421 = and(_T_3420, _T_3373) @[dec_dec_ctl.scala 17:17] + node _T_3422 = and(_T_3421, _T_3375) @[dec_dec_ctl.scala 17:17] + node _T_3423 = and(_T_3422, _T_3377) @[dec_dec_ctl.scala 17:17] + node _T_3424 = and(_T_3423, _T_3379) @[dec_dec_ctl.scala 17:17] + node _T_3425 = and(_T_3424, _T_3381) @[dec_dec_ctl.scala 17:17] + node _T_3426 = and(_T_3425, _T_3383) @[dec_dec_ctl.scala 17:17] + node _T_3427 = and(_T_3426, _T_3385) @[dec_dec_ctl.scala 17:17] + node _T_3428 = and(_T_3427, _T_3387) @[dec_dec_ctl.scala 17:17] + node _T_3429 = and(_T_3428, _T_3389) @[dec_dec_ctl.scala 17:17] + node _T_3430 = and(_T_3429, _T_3391) @[dec_dec_ctl.scala 17:17] + node _T_3431 = and(_T_3430, _T_3393) @[dec_dec_ctl.scala 17:17] + node _T_3432 = and(_T_3431, _T_3395) @[dec_dec_ctl.scala 17:17] + node _T_3433 = and(_T_3432, _T_3397) @[dec_dec_ctl.scala 17:17] + node _T_3434 = and(_T_3433, _T_3399) @[dec_dec_ctl.scala 17:17] + node _T_3435 = and(_T_3434, _T_3401) @[dec_dec_ctl.scala 17:17] + node _T_3436 = and(_T_3435, _T_3403) @[dec_dec_ctl.scala 17:17] + node _T_3437 = and(_T_3436, _T_3405) @[dec_dec_ctl.scala 17:17] + node _T_3438 = and(_T_3437, _T_3407) @[dec_dec_ctl.scala 17:17] + node _T_3439 = and(_T_3438, _T_3409) @[dec_dec_ctl.scala 17:17] + node _T_3440 = and(_T_3439, _T_3411) @[dec_dec_ctl.scala 17:17] + node _T_3441 = and(_T_3440, _T_3412) @[dec_dec_ctl.scala 17:17] + node _T_3442 = and(_T_3441, _T_3413) @[dec_dec_ctl.scala 17:17] + node _T_3443 = and(_T_3442, _T_3415) @[dec_dec_ctl.scala 17:17] + node _T_3444 = and(_T_3443, _T_3417) @[dec_dec_ctl.scala 17:17] + node _T_3445 = and(_T_3444, _T_3418) @[dec_dec_ctl.scala 17:17] + node _T_3446 = and(_T_3445, _T_3419) @[dec_dec_ctl.scala 17:17] + node _T_3447 = or(_T_3367, _T_3446) @[dec_dec_ctl.scala 249:122] + node _T_3448 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3449 = eq(_T_3448, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3450 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3451 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3452 = eq(_T_3451, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3453 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3454 = eq(_T_3453, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3455 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3456 = eq(_T_3455, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3457 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_3458 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_3459 = eq(_T_3458, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3460 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_3461 = eq(_T_3460, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3462 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3463 = eq(_T_3462, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3464 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3465 = eq(_T_3464, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3466 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3467 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3468 = eq(_T_3467, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3469 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3470 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3471 = and(_T_3449, _T_3450) @[dec_dec_ctl.scala 17:17] + node _T_3472 = and(_T_3471, _T_3452) @[dec_dec_ctl.scala 17:17] + node _T_3473 = and(_T_3472, _T_3454) @[dec_dec_ctl.scala 17:17] + node _T_3474 = and(_T_3473, _T_3456) @[dec_dec_ctl.scala 17:17] + node _T_3475 = and(_T_3474, _T_3457) @[dec_dec_ctl.scala 17:17] + node _T_3476 = and(_T_3475, _T_3459) @[dec_dec_ctl.scala 17:17] + node _T_3477 = and(_T_3476, _T_3461) @[dec_dec_ctl.scala 17:17] + node _T_3478 = and(_T_3477, _T_3463) @[dec_dec_ctl.scala 17:17] + node _T_3479 = and(_T_3478, _T_3465) @[dec_dec_ctl.scala 17:17] + node _T_3480 = and(_T_3479, _T_3466) @[dec_dec_ctl.scala 17:17] + node _T_3481 = and(_T_3480, _T_3468) @[dec_dec_ctl.scala 17:17] + node _T_3482 = and(_T_3481, _T_3469) @[dec_dec_ctl.scala 17:17] + node _T_3483 = and(_T_3482, _T_3470) @[dec_dec_ctl.scala 17:17] + node _T_3484 = or(_T_3447, _T_3483) @[dec_dec_ctl.scala 250:119] + node _T_3485 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3486 = eq(_T_3485, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3487 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3488 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3489 = eq(_T_3488, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3490 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3491 = eq(_T_3490, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3492 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3493 = eq(_T_3492, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3494 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_3495 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_3496 = eq(_T_3495, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3497 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_3498 = eq(_T_3497, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3499 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3500 = eq(_T_3499, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3501 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3502 = eq(_T_3501, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3503 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3504 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3505 = eq(_T_3504, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3506 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3507 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3508 = and(_T_3486, _T_3487) @[dec_dec_ctl.scala 17:17] + node _T_3509 = and(_T_3508, _T_3489) @[dec_dec_ctl.scala 17:17] + node _T_3510 = and(_T_3509, _T_3491) @[dec_dec_ctl.scala 17:17] + node _T_3511 = and(_T_3510, _T_3493) @[dec_dec_ctl.scala 17:17] + node _T_3512 = and(_T_3511, _T_3494) @[dec_dec_ctl.scala 17:17] + node _T_3513 = and(_T_3512, _T_3496) @[dec_dec_ctl.scala 17:17] + node _T_3514 = and(_T_3513, _T_3498) @[dec_dec_ctl.scala 17:17] + node _T_3515 = and(_T_3514, _T_3500) @[dec_dec_ctl.scala 17:17] + node _T_3516 = and(_T_3515, _T_3502) @[dec_dec_ctl.scala 17:17] + node _T_3517 = and(_T_3516, _T_3503) @[dec_dec_ctl.scala 17:17] + node _T_3518 = and(_T_3517, _T_3505) @[dec_dec_ctl.scala 17:17] + node _T_3519 = and(_T_3518, _T_3506) @[dec_dec_ctl.scala 17:17] + node _T_3520 = and(_T_3519, _T_3507) @[dec_dec_ctl.scala 17:17] + node _T_3521 = or(_T_3484, _T_3520) @[dec_dec_ctl.scala 251:65] + node _T_3522 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3523 = eq(_T_3522, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3524 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3525 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3526 = eq(_T_3525, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3527 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3528 = eq(_T_3527, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3529 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3530 = eq(_T_3529, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3531 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_3532 = eq(_T_3531, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3533 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_3534 = eq(_T_3533, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3535 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_3536 = eq(_T_3535, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3537 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3538 = eq(_T_3537, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3539 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3540 = eq(_T_3539, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3541 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3542 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3543 = eq(_T_3542, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3544 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3545 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3546 = and(_T_3523, _T_3524) @[dec_dec_ctl.scala 17:17] + node _T_3547 = and(_T_3546, _T_3526) @[dec_dec_ctl.scala 17:17] + node _T_3548 = and(_T_3547, _T_3528) @[dec_dec_ctl.scala 17:17] + node _T_3549 = and(_T_3548, _T_3530) @[dec_dec_ctl.scala 17:17] + node _T_3550 = and(_T_3549, _T_3532) @[dec_dec_ctl.scala 17:17] + node _T_3551 = and(_T_3550, _T_3534) @[dec_dec_ctl.scala 17:17] + node _T_3552 = and(_T_3551, _T_3536) @[dec_dec_ctl.scala 17:17] + node _T_3553 = and(_T_3552, _T_3538) @[dec_dec_ctl.scala 17:17] + node _T_3554 = and(_T_3553, _T_3540) @[dec_dec_ctl.scala 17:17] + node _T_3555 = and(_T_3554, _T_3541) @[dec_dec_ctl.scala 17:17] + node _T_3556 = and(_T_3555, _T_3543) @[dec_dec_ctl.scala 17:17] + node _T_3557 = and(_T_3556, _T_3544) @[dec_dec_ctl.scala 17:17] + node _T_3558 = and(_T_3557, _T_3545) @[dec_dec_ctl.scala 17:17] + node _T_3559 = or(_T_3521, _T_3558) @[dec_dec_ctl.scala 251:127] + node _T_3560 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3561 = eq(_T_3560, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3562 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3563 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3564 = eq(_T_3563, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3565 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3566 = eq(_T_3565, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3567 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3568 = eq(_T_3567, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3569 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_3570 = eq(_T_3569, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3571 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_3572 = eq(_T_3571, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3573 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_3574 = eq(_T_3573, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3575 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3576 = eq(_T_3575, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3577 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3578 = eq(_T_3577, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3579 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3580 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3581 = eq(_T_3580, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3582 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3583 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3584 = and(_T_3561, _T_3562) @[dec_dec_ctl.scala 17:17] + node _T_3585 = and(_T_3584, _T_3564) @[dec_dec_ctl.scala 17:17] + node _T_3586 = and(_T_3585, _T_3566) @[dec_dec_ctl.scala 17:17] + node _T_3587 = and(_T_3586, _T_3568) @[dec_dec_ctl.scala 17:17] + node _T_3588 = and(_T_3587, _T_3570) @[dec_dec_ctl.scala 17:17] + node _T_3589 = and(_T_3588, _T_3572) @[dec_dec_ctl.scala 17:17] + node _T_3590 = and(_T_3589, _T_3574) @[dec_dec_ctl.scala 17:17] + node _T_3591 = and(_T_3590, _T_3576) @[dec_dec_ctl.scala 17:17] + node _T_3592 = and(_T_3591, _T_3578) @[dec_dec_ctl.scala 17:17] + node _T_3593 = and(_T_3592, _T_3579) @[dec_dec_ctl.scala 17:17] + node _T_3594 = and(_T_3593, _T_3581) @[dec_dec_ctl.scala 17:17] + node _T_3595 = and(_T_3594, _T_3582) @[dec_dec_ctl.scala 17:17] + node _T_3596 = and(_T_3595, _T_3583) @[dec_dec_ctl.scala 17:17] + node _T_3597 = or(_T_3559, _T_3596) @[dec_dec_ctl.scala 252:66] + node _T_3598 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3599 = eq(_T_3598, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3600 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3601 = eq(_T_3600, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3602 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3603 = eq(_T_3602, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3604 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3605 = eq(_T_3604, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3606 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3607 = eq(_T_3606, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3608 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_3609 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_3610 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3611 = eq(_T_3610, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3612 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3613 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3614 = eq(_T_3613, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3615 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3616 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3617 = and(_T_3599, _T_3601) @[dec_dec_ctl.scala 17:17] + node _T_3618 = and(_T_3617, _T_3603) @[dec_dec_ctl.scala 17:17] + node _T_3619 = and(_T_3618, _T_3605) @[dec_dec_ctl.scala 17:17] + node _T_3620 = and(_T_3619, _T_3607) @[dec_dec_ctl.scala 17:17] + node _T_3621 = and(_T_3620, _T_3608) @[dec_dec_ctl.scala 17:17] + node _T_3622 = and(_T_3621, _T_3609) @[dec_dec_ctl.scala 17:17] + node _T_3623 = and(_T_3622, _T_3611) @[dec_dec_ctl.scala 17:17] + node _T_3624 = and(_T_3623, _T_3612) @[dec_dec_ctl.scala 17:17] + node _T_3625 = and(_T_3624, _T_3614) @[dec_dec_ctl.scala 17:17] + node _T_3626 = and(_T_3625, _T_3615) @[dec_dec_ctl.scala 17:17] + node _T_3627 = and(_T_3626, _T_3616) @[dec_dec_ctl.scala 17:17] + node _T_3628 = or(_T_3597, _T_3627) @[dec_dec_ctl.scala 252:129] + node _T_3629 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3630 = eq(_T_3629, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3631 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3632 = eq(_T_3631, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3633 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3634 = eq(_T_3633, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3635 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3636 = eq(_T_3635, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3637 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3638 = eq(_T_3637, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3639 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_3640 = eq(_T_3639, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3641 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3642 = eq(_T_3641, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3643 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3644 = eq(_T_3643, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3645 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3646 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3647 = eq(_T_3646, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3648 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3649 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3650 = and(_T_3630, _T_3632) @[dec_dec_ctl.scala 17:17] + node _T_3651 = and(_T_3650, _T_3634) @[dec_dec_ctl.scala 17:17] + node _T_3652 = and(_T_3651, _T_3636) @[dec_dec_ctl.scala 17:17] + node _T_3653 = and(_T_3652, _T_3638) @[dec_dec_ctl.scala 17:17] + node _T_3654 = and(_T_3653, _T_3640) @[dec_dec_ctl.scala 17:17] + node _T_3655 = and(_T_3654, _T_3642) @[dec_dec_ctl.scala 17:17] + node _T_3656 = and(_T_3655, _T_3644) @[dec_dec_ctl.scala 17:17] + node _T_3657 = and(_T_3656, _T_3645) @[dec_dec_ctl.scala 17:17] + node _T_3658 = and(_T_3657, _T_3647) @[dec_dec_ctl.scala 17:17] + node _T_3659 = and(_T_3658, _T_3648) @[dec_dec_ctl.scala 17:17] + node _T_3660 = and(_T_3659, _T_3649) @[dec_dec_ctl.scala 17:17] + node _T_3661 = or(_T_3628, _T_3660) @[dec_dec_ctl.scala 253:58] + node _T_3662 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3663 = eq(_T_3662, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3664 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3665 = eq(_T_3664, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3666 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3667 = eq(_T_3666, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3668 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3669 = eq(_T_3668, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3670 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3671 = eq(_T_3670, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3672 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3673 = eq(_T_3672, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3674 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_3675 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3676 = eq(_T_3675, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3677 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3678 = eq(_T_3677, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3679 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3680 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3681 = eq(_T_3680, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3682 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3683 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3684 = and(_T_3663, _T_3665) @[dec_dec_ctl.scala 17:17] + node _T_3685 = and(_T_3684, _T_3667) @[dec_dec_ctl.scala 17:17] + node _T_3686 = and(_T_3685, _T_3669) @[dec_dec_ctl.scala 17:17] + node _T_3687 = and(_T_3686, _T_3671) @[dec_dec_ctl.scala 17:17] + node _T_3688 = and(_T_3687, _T_3673) @[dec_dec_ctl.scala 17:17] + node _T_3689 = and(_T_3688, _T_3674) @[dec_dec_ctl.scala 17:17] + node _T_3690 = and(_T_3689, _T_3676) @[dec_dec_ctl.scala 17:17] + node _T_3691 = and(_T_3690, _T_3678) @[dec_dec_ctl.scala 17:17] + node _T_3692 = and(_T_3691, _T_3679) @[dec_dec_ctl.scala 17:17] + node _T_3693 = and(_T_3692, _T_3681) @[dec_dec_ctl.scala 17:17] + node _T_3694 = and(_T_3693, _T_3682) @[dec_dec_ctl.scala 17:17] + node _T_3695 = and(_T_3694, _T_3683) @[dec_dec_ctl.scala 17:17] + node _T_3696 = or(_T_3661, _T_3695) @[dec_dec_ctl.scala 253:114] + node _T_3697 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3698 = eq(_T_3697, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3699 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3700 = eq(_T_3699, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3701 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3702 = eq(_T_3701, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3703 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3704 = eq(_T_3703, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3705 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3706 = eq(_T_3705, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3707 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3708 = eq(_T_3707, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3709 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_3710 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3711 = eq(_T_3710, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3712 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3713 = eq(_T_3712, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3714 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3715 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3716 = eq(_T_3715, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3717 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3718 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3719 = and(_T_3698, _T_3700) @[dec_dec_ctl.scala 17:17] + node _T_3720 = and(_T_3719, _T_3702) @[dec_dec_ctl.scala 17:17] + node _T_3721 = and(_T_3720, _T_3704) @[dec_dec_ctl.scala 17:17] + node _T_3722 = and(_T_3721, _T_3706) @[dec_dec_ctl.scala 17:17] + node _T_3723 = and(_T_3722, _T_3708) @[dec_dec_ctl.scala 17:17] + node _T_3724 = and(_T_3723, _T_3709) @[dec_dec_ctl.scala 17:17] + node _T_3725 = and(_T_3724, _T_3711) @[dec_dec_ctl.scala 17:17] + node _T_3726 = and(_T_3725, _T_3713) @[dec_dec_ctl.scala 17:17] + node _T_3727 = and(_T_3726, _T_3714) @[dec_dec_ctl.scala 17:17] + node _T_3728 = and(_T_3727, _T_3716) @[dec_dec_ctl.scala 17:17] + node _T_3729 = and(_T_3728, _T_3717) @[dec_dec_ctl.scala 17:17] + node _T_3730 = and(_T_3729, _T_3718) @[dec_dec_ctl.scala 17:17] + node _T_3731 = or(_T_3696, _T_3730) @[dec_dec_ctl.scala 254:63] + node _T_3732 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3733 = eq(_T_3732, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3734 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3735 = eq(_T_3734, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3736 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3737 = eq(_T_3736, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3738 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3739 = eq(_T_3738, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3740 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3741 = eq(_T_3740, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3742 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3743 = eq(_T_3742, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3744 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3745 = eq(_T_3744, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3746 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3747 = eq(_T_3746, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3748 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3749 = eq(_T_3748, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3750 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3751 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3752 = eq(_T_3751, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3753 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3754 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3755 = and(_T_3733, _T_3735) @[dec_dec_ctl.scala 17:17] + node _T_3756 = and(_T_3755, _T_3737) @[dec_dec_ctl.scala 17:17] + node _T_3757 = and(_T_3756, _T_3739) @[dec_dec_ctl.scala 17:17] + node _T_3758 = and(_T_3757, _T_3741) @[dec_dec_ctl.scala 17:17] + node _T_3759 = and(_T_3758, _T_3743) @[dec_dec_ctl.scala 17:17] + node _T_3760 = and(_T_3759, _T_3745) @[dec_dec_ctl.scala 17:17] + node _T_3761 = and(_T_3760, _T_3747) @[dec_dec_ctl.scala 17:17] + node _T_3762 = and(_T_3761, _T_3749) @[dec_dec_ctl.scala 17:17] + node _T_3763 = and(_T_3762, _T_3750) @[dec_dec_ctl.scala 17:17] + node _T_3764 = and(_T_3763, _T_3752) @[dec_dec_ctl.scala 17:17] + node _T_3765 = and(_T_3764, _T_3753) @[dec_dec_ctl.scala 17:17] + node _T_3766 = and(_T_3765, _T_3754) @[dec_dec_ctl.scala 17:17] + node _T_3767 = or(_T_3731, _T_3766) @[dec_dec_ctl.scala 254:123] + node _T_3768 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3769 = eq(_T_3768, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3770 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3771 = eq(_T_3770, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3772 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3773 = eq(_T_3772, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3774 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3775 = eq(_T_3774, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3776 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3777 = eq(_T_3776, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3778 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_3779 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3780 = eq(_T_3779, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3781 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3782 = eq(_T_3781, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3783 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3784 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3785 = eq(_T_3784, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3786 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3787 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3788 = and(_T_3769, _T_3771) @[dec_dec_ctl.scala 17:17] + node _T_3789 = and(_T_3788, _T_3773) @[dec_dec_ctl.scala 17:17] + node _T_3790 = and(_T_3789, _T_3775) @[dec_dec_ctl.scala 17:17] + node _T_3791 = and(_T_3790, _T_3777) @[dec_dec_ctl.scala 17:17] + node _T_3792 = and(_T_3791, _T_3778) @[dec_dec_ctl.scala 17:17] + node _T_3793 = and(_T_3792, _T_3780) @[dec_dec_ctl.scala 17:17] + node _T_3794 = and(_T_3793, _T_3782) @[dec_dec_ctl.scala 17:17] + node _T_3795 = and(_T_3794, _T_3783) @[dec_dec_ctl.scala 17:17] + node _T_3796 = and(_T_3795, _T_3785) @[dec_dec_ctl.scala 17:17] + node _T_3797 = and(_T_3796, _T_3786) @[dec_dec_ctl.scala 17:17] + node _T_3798 = and(_T_3797, _T_3787) @[dec_dec_ctl.scala 17:17] + node _T_3799 = or(_T_3767, _T_3798) @[dec_dec_ctl.scala 255:64] + node _T_3800 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3801 = eq(_T_3800, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3802 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3803 = eq(_T_3802, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3804 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3805 = eq(_T_3804, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3806 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3807 = eq(_T_3806, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3808 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3809 = eq(_T_3808, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3810 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3811 = eq(_T_3810, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3812 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_3813 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3814 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3815 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3816 = eq(_T_3815, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3817 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3818 = eq(_T_3817, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3819 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3820 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3821 = and(_T_3801, _T_3803) @[dec_dec_ctl.scala 17:17] + node _T_3822 = and(_T_3821, _T_3805) @[dec_dec_ctl.scala 17:17] + node _T_3823 = and(_T_3822, _T_3807) @[dec_dec_ctl.scala 17:17] + node _T_3824 = and(_T_3823, _T_3809) @[dec_dec_ctl.scala 17:17] + node _T_3825 = and(_T_3824, _T_3811) @[dec_dec_ctl.scala 17:17] + node _T_3826 = and(_T_3825, _T_3812) @[dec_dec_ctl.scala 17:17] + node _T_3827 = and(_T_3826, _T_3813) @[dec_dec_ctl.scala 17:17] + node _T_3828 = and(_T_3827, _T_3814) @[dec_dec_ctl.scala 17:17] + node _T_3829 = and(_T_3828, _T_3816) @[dec_dec_ctl.scala 17:17] + node _T_3830 = and(_T_3829, _T_3818) @[dec_dec_ctl.scala 17:17] + node _T_3831 = and(_T_3830, _T_3819) @[dec_dec_ctl.scala 17:17] + node _T_3832 = and(_T_3831, _T_3820) @[dec_dec_ctl.scala 17:17] + node _T_3833 = or(_T_3799, _T_3832) @[dec_dec_ctl.scala 255:119] + node _T_3834 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3835 = eq(_T_3834, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3836 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3837 = eq(_T_3836, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3838 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3839 = eq(_T_3838, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3840 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3841 = eq(_T_3840, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3842 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3843 = eq(_T_3842, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3844 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_3845 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3846 = eq(_T_3845, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3847 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3848 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3849 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3850 = eq(_T_3849, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3851 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3852 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3853 = and(_T_3835, _T_3837) @[dec_dec_ctl.scala 17:17] + node _T_3854 = and(_T_3853, _T_3839) @[dec_dec_ctl.scala 17:17] + node _T_3855 = and(_T_3854, _T_3841) @[dec_dec_ctl.scala 17:17] + node _T_3856 = and(_T_3855, _T_3843) @[dec_dec_ctl.scala 17:17] + node _T_3857 = and(_T_3856, _T_3844) @[dec_dec_ctl.scala 17:17] + node _T_3858 = and(_T_3857, _T_3846) @[dec_dec_ctl.scala 17:17] + node _T_3859 = and(_T_3858, _T_3847) @[dec_dec_ctl.scala 17:17] + node _T_3860 = and(_T_3859, _T_3848) @[dec_dec_ctl.scala 17:17] + node _T_3861 = and(_T_3860, _T_3850) @[dec_dec_ctl.scala 17:17] + node _T_3862 = and(_T_3861, _T_3851) @[dec_dec_ctl.scala 17:17] + node _T_3863 = and(_T_3862, _T_3852) @[dec_dec_ctl.scala 17:17] + node _T_3864 = or(_T_3833, _T_3863) @[dec_dec_ctl.scala 256:61] + node _T_3865 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3866 = eq(_T_3865, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3867 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_3868 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3869 = eq(_T_3868, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3870 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_3871 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3872 = eq(_T_3871, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3873 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3874 = eq(_T_3873, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3875 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3876 = eq(_T_3875, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3877 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_3878 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3879 = eq(_T_3878, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3880 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3881 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3882 = eq(_T_3881, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3883 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3884 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3885 = and(_T_3866, _T_3867) @[dec_dec_ctl.scala 17:17] + node _T_3886 = and(_T_3885, _T_3869) @[dec_dec_ctl.scala 17:17] + node _T_3887 = and(_T_3886, _T_3870) @[dec_dec_ctl.scala 17:17] + node _T_3888 = and(_T_3887, _T_3872) @[dec_dec_ctl.scala 17:17] + node _T_3889 = and(_T_3888, _T_3874) @[dec_dec_ctl.scala 17:17] + node _T_3890 = and(_T_3889, _T_3876) @[dec_dec_ctl.scala 17:17] + node _T_3891 = and(_T_3890, _T_3877) @[dec_dec_ctl.scala 17:17] + node _T_3892 = and(_T_3891, _T_3879) @[dec_dec_ctl.scala 17:17] + node _T_3893 = and(_T_3892, _T_3880) @[dec_dec_ctl.scala 17:17] + node _T_3894 = and(_T_3893, _T_3882) @[dec_dec_ctl.scala 17:17] + node _T_3895 = and(_T_3894, _T_3883) @[dec_dec_ctl.scala 17:17] + node _T_3896 = and(_T_3895, _T_3884) @[dec_dec_ctl.scala 17:17] + node _T_3897 = or(_T_3864, _T_3896) @[dec_dec_ctl.scala 256:115] + node _T_3898 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3899 = eq(_T_3898, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3900 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3901 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3902 = eq(_T_3901, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3903 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_3904 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3905 = eq(_T_3904, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3906 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3907 = eq(_T_3906, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3908 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3909 = eq(_T_3908, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3910 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3911 = eq(_T_3910, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3912 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3913 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3914 = eq(_T_3913, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3915 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3916 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3917 = and(_T_3899, _T_3900) @[dec_dec_ctl.scala 17:17] + node _T_3918 = and(_T_3917, _T_3902) @[dec_dec_ctl.scala 17:17] + node _T_3919 = and(_T_3918, _T_3903) @[dec_dec_ctl.scala 17:17] + node _T_3920 = and(_T_3919, _T_3905) @[dec_dec_ctl.scala 17:17] + node _T_3921 = and(_T_3920, _T_3907) @[dec_dec_ctl.scala 17:17] + node _T_3922 = and(_T_3921, _T_3909) @[dec_dec_ctl.scala 17:17] + node _T_3923 = and(_T_3922, _T_3911) @[dec_dec_ctl.scala 17:17] + node _T_3924 = and(_T_3923, _T_3912) @[dec_dec_ctl.scala 17:17] + node _T_3925 = and(_T_3924, _T_3914) @[dec_dec_ctl.scala 17:17] + node _T_3926 = and(_T_3925, _T_3915) @[dec_dec_ctl.scala 17:17] + node _T_3927 = and(_T_3926, _T_3916) @[dec_dec_ctl.scala 17:17] + node _T_3928 = or(_T_3897, _T_3927) @[dec_dec_ctl.scala 257:61] + node _T_3929 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3930 = eq(_T_3929, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3931 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3932 = eq(_T_3931, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3933 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3934 = eq(_T_3933, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3935 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3936 = eq(_T_3935, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3937 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3938 = eq(_T_3937, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3939 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3940 = eq(_T_3939, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3941 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3942 = eq(_T_3941, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3943 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3944 = eq(_T_3943, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3945 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3946 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3947 = eq(_T_3946, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3948 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3949 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3950 = and(_T_3930, _T_3932) @[dec_dec_ctl.scala 17:17] + node _T_3951 = and(_T_3950, _T_3934) @[dec_dec_ctl.scala 17:17] + node _T_3952 = and(_T_3951, _T_3936) @[dec_dec_ctl.scala 17:17] + node _T_3953 = and(_T_3952, _T_3938) @[dec_dec_ctl.scala 17:17] + node _T_3954 = and(_T_3953, _T_3940) @[dec_dec_ctl.scala 17:17] + node _T_3955 = and(_T_3954, _T_3942) @[dec_dec_ctl.scala 17:17] + node _T_3956 = and(_T_3955, _T_3944) @[dec_dec_ctl.scala 17:17] + node _T_3957 = and(_T_3956, _T_3945) @[dec_dec_ctl.scala 17:17] + node _T_3958 = and(_T_3957, _T_3947) @[dec_dec_ctl.scala 17:17] + node _T_3959 = and(_T_3958, _T_3948) @[dec_dec_ctl.scala 17:17] + node _T_3960 = and(_T_3959, _T_3949) @[dec_dec_ctl.scala 17:17] + node _T_3961 = or(_T_3928, _T_3960) @[dec_dec_ctl.scala 257:116] + node _T_3962 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3963 = eq(_T_3962, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3964 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3965 = eq(_T_3964, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3966 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3967 = eq(_T_3966, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3968 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3969 = eq(_T_3968, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3970 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3971 = eq(_T_3970, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3972 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3973 = eq(_T_3972, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3974 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3975 = eq(_T_3974, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3976 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3977 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3978 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3979 = eq(_T_3978, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3980 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3981 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3982 = and(_T_3963, _T_3965) @[dec_dec_ctl.scala 17:17] + node _T_3983 = and(_T_3982, _T_3967) @[dec_dec_ctl.scala 17:17] + node _T_3984 = and(_T_3983, _T_3969) @[dec_dec_ctl.scala 17:17] + node _T_3985 = and(_T_3984, _T_3971) @[dec_dec_ctl.scala 17:17] + node _T_3986 = and(_T_3985, _T_3973) @[dec_dec_ctl.scala 17:17] + node _T_3987 = and(_T_3986, _T_3975) @[dec_dec_ctl.scala 17:17] + node _T_3988 = and(_T_3987, _T_3976) @[dec_dec_ctl.scala 17:17] + node _T_3989 = and(_T_3988, _T_3977) @[dec_dec_ctl.scala 17:17] + node _T_3990 = and(_T_3989, _T_3979) @[dec_dec_ctl.scala 17:17] + node _T_3991 = and(_T_3990, _T_3980) @[dec_dec_ctl.scala 17:17] + node _T_3992 = and(_T_3991, _T_3981) @[dec_dec_ctl.scala 17:17] + node _T_3993 = or(_T_3961, _T_3992) @[dec_dec_ctl.scala 258:59] + node _T_3994 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3995 = eq(_T_3994, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3996 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3997 = eq(_T_3996, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3998 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3999 = eq(_T_3998, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4000 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_4001 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4002 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4003 = eq(_T_4002, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4004 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4005 = eq(_T_4004, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4006 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4007 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4008 = and(_T_3995, _T_3997) @[dec_dec_ctl.scala 17:17] + node _T_4009 = and(_T_4008, _T_3999) @[dec_dec_ctl.scala 17:17] + node _T_4010 = and(_T_4009, _T_4000) @[dec_dec_ctl.scala 17:17] + node _T_4011 = and(_T_4010, _T_4001) @[dec_dec_ctl.scala 17:17] + node _T_4012 = and(_T_4011, _T_4003) @[dec_dec_ctl.scala 17:17] + node _T_4013 = and(_T_4012, _T_4005) @[dec_dec_ctl.scala 17:17] + node _T_4014 = and(_T_4013, _T_4006) @[dec_dec_ctl.scala 17:17] + node _T_4015 = and(_T_4014, _T_4007) @[dec_dec_ctl.scala 17:17] + node _T_4016 = or(_T_3993, _T_4015) @[dec_dec_ctl.scala 258:114] + node _T_4017 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_4018 = eq(_T_4017, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4019 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_4020 = eq(_T_4019, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4021 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_4022 = eq(_T_4021, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4023 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_4024 = eq(_T_4023, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4025 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_4026 = eq(_T_4025, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4027 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_4028 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4029 = eq(_T_4028, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4030 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4031 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_4032 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4033 = eq(_T_4032, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4034 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4035 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4036 = and(_T_4018, _T_4020) @[dec_dec_ctl.scala 17:17] + node _T_4037 = and(_T_4036, _T_4022) @[dec_dec_ctl.scala 17:17] + node _T_4038 = and(_T_4037, _T_4024) @[dec_dec_ctl.scala 17:17] + node _T_4039 = and(_T_4038, _T_4026) @[dec_dec_ctl.scala 17:17] + node _T_4040 = and(_T_4039, _T_4027) @[dec_dec_ctl.scala 17:17] + node _T_4041 = and(_T_4040, _T_4029) @[dec_dec_ctl.scala 17:17] + node _T_4042 = and(_T_4041, _T_4030) @[dec_dec_ctl.scala 17:17] + node _T_4043 = and(_T_4042, _T_4031) @[dec_dec_ctl.scala 17:17] + node _T_4044 = and(_T_4043, _T_4033) @[dec_dec_ctl.scala 17:17] + node _T_4045 = and(_T_4044, _T_4034) @[dec_dec_ctl.scala 17:17] + node _T_4046 = and(_T_4045, _T_4035) @[dec_dec_ctl.scala 17:17] + node _T_4047 = or(_T_4016, _T_4046) @[dec_dec_ctl.scala 259:46] + node _T_4048 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_4049 = eq(_T_4048, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4050 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_4051 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_4052 = eq(_T_4051, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4053 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_4054 = eq(_T_4053, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4055 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_4056 = eq(_T_4055, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4057 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_4058 = eq(_T_4057, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4059 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_4060 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4061 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_4062 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4063 = eq(_T_4062, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4064 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4065 = eq(_T_4064, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4066 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4067 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4068 = and(_T_4049, _T_4050) @[dec_dec_ctl.scala 17:17] + node _T_4069 = and(_T_4068, _T_4052) @[dec_dec_ctl.scala 17:17] + node _T_4070 = and(_T_4069, _T_4054) @[dec_dec_ctl.scala 17:17] + node _T_4071 = and(_T_4070, _T_4056) @[dec_dec_ctl.scala 17:17] + node _T_4072 = and(_T_4071, _T_4058) @[dec_dec_ctl.scala 17:17] + node _T_4073 = and(_T_4072, _T_4059) @[dec_dec_ctl.scala 17:17] + node _T_4074 = and(_T_4073, _T_4060) @[dec_dec_ctl.scala 17:17] + node _T_4075 = and(_T_4074, _T_4061) @[dec_dec_ctl.scala 17:17] + node _T_4076 = and(_T_4075, _T_4063) @[dec_dec_ctl.scala 17:17] + node _T_4077 = and(_T_4076, _T_4065) @[dec_dec_ctl.scala 17:17] + node _T_4078 = and(_T_4077, _T_4066) @[dec_dec_ctl.scala 17:17] + node _T_4079 = and(_T_4078, _T_4067) @[dec_dec_ctl.scala 17:17] + node _T_4080 = or(_T_4047, _T_4079) @[dec_dec_ctl.scala 259:100] + node _T_4081 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_4082 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_4083 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4084 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4085 = eq(_T_4084, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4086 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4087 = eq(_T_4086, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4088 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4089 = eq(_T_4088, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4090 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4091 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4092 = and(_T_4081, _T_4082) @[dec_dec_ctl.scala 17:17] + node _T_4093 = and(_T_4092, _T_4083) @[dec_dec_ctl.scala 17:17] + node _T_4094 = and(_T_4093, _T_4085) @[dec_dec_ctl.scala 17:17] + node _T_4095 = and(_T_4094, _T_4087) @[dec_dec_ctl.scala 17:17] + node _T_4096 = and(_T_4095, _T_4089) @[dec_dec_ctl.scala 17:17] + node _T_4097 = and(_T_4096, _T_4090) @[dec_dec_ctl.scala 17:17] + node _T_4098 = and(_T_4097, _T_4091) @[dec_dec_ctl.scala 17:17] + node _T_4099 = or(_T_4080, _T_4098) @[dec_dec_ctl.scala 260:60] + node _T_4100 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_4101 = eq(_T_4100, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4102 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_4103 = eq(_T_4102, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4104 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4105 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4106 = eq(_T_4105, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4107 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4108 = eq(_T_4107, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4109 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4110 = eq(_T_4109, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4111 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4112 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4113 = and(_T_4101, _T_4103) @[dec_dec_ctl.scala 17:17] + node _T_4114 = and(_T_4113, _T_4104) @[dec_dec_ctl.scala 17:17] + node _T_4115 = and(_T_4114, _T_4106) @[dec_dec_ctl.scala 17:17] + node _T_4116 = and(_T_4115, _T_4108) @[dec_dec_ctl.scala 17:17] + node _T_4117 = and(_T_4116, _T_4110) @[dec_dec_ctl.scala 17:17] + node _T_4118 = and(_T_4117, _T_4111) @[dec_dec_ctl.scala 17:17] + node _T_4119 = and(_T_4118, _T_4112) @[dec_dec_ctl.scala 17:17] + node _T_4120 = or(_T_4099, _T_4119) @[dec_dec_ctl.scala 260:97] + node _T_4121 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_4122 = eq(_T_4121, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4123 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4124 = eq(_T_4123, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4125 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_4126 = eq(_T_4125, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4127 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_4128 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4129 = eq(_T_4128, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4130 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4131 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4132 = and(_T_4122, _T_4124) @[dec_dec_ctl.scala 17:17] + node _T_4133 = and(_T_4132, _T_4126) @[dec_dec_ctl.scala 17:17] + node _T_4134 = and(_T_4133, _T_4127) @[dec_dec_ctl.scala 17:17] + node _T_4135 = and(_T_4134, _T_4129) @[dec_dec_ctl.scala 17:17] + node _T_4136 = and(_T_4135, _T_4130) @[dec_dec_ctl.scala 17:17] + node _T_4137 = and(_T_4136, _T_4131) @[dec_dec_ctl.scala 17:17] + node _T_4138 = or(_T_4120, _T_4137) @[dec_dec_ctl.scala 261:43] + node _T_4139 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_4140 = eq(_T_4139, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4141 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_4142 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_4143 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4144 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4145 = eq(_T_4144, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4146 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4147 = eq(_T_4146, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4148 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4149 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4150 = and(_T_4140, _T_4141) @[dec_dec_ctl.scala 17:17] + node _T_4151 = and(_T_4150, _T_4142) @[dec_dec_ctl.scala 17:17] + node _T_4152 = and(_T_4151, _T_4143) @[dec_dec_ctl.scala 17:17] + node _T_4153 = and(_T_4152, _T_4145) @[dec_dec_ctl.scala 17:17] + node _T_4154 = and(_T_4153, _T_4147) @[dec_dec_ctl.scala 17:17] + node _T_4155 = and(_T_4154, _T_4148) @[dec_dec_ctl.scala 17:17] + node _T_4156 = and(_T_4155, _T_4149) @[dec_dec_ctl.scala 17:17] + node _T_4157 = or(_T_4138, _T_4156) @[dec_dec_ctl.scala 261:79] + node _T_4158 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_4159 = eq(_T_4158, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4160 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_4161 = eq(_T_4160, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4162 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_4163 = eq(_T_4162, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4164 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_4165 = eq(_T_4164, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4166 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_4167 = eq(_T_4166, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4168 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_4169 = eq(_T_4168, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4170 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_4171 = eq(_T_4170, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4172 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_4173 = eq(_T_4172, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4174 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_4175 = eq(_T_4174, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4176 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_4177 = eq(_T_4176, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4178 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_4179 = eq(_T_4178, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4180 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_4181 = eq(_T_4180, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4182 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53] + node _T_4183 = eq(_T_4182, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4184 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53] + node _T_4185 = eq(_T_4184, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4186 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53] + node _T_4187 = eq(_T_4186, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4188 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53] + node _T_4189 = eq(_T_4188, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4190 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53] + node _T_4191 = eq(_T_4190, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4192 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_4193 = eq(_T_4192, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4194 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_4195 = eq(_T_4194, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4196 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53] + node _T_4197 = eq(_T_4196, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4198 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53] + node _T_4199 = eq(_T_4198, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4200 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53] + node _T_4201 = eq(_T_4200, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4202 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53] + node _T_4203 = eq(_T_4202, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4204 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53] + node _T_4205 = eq(_T_4204, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4206 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4207 = eq(_T_4206, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4208 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_4209 = eq(_T_4208, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4210 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4211 = eq(_T_4210, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4212 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_4213 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_4214 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4215 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4216 = and(_T_4159, _T_4161) @[dec_dec_ctl.scala 17:17] + node _T_4217 = and(_T_4216, _T_4163) @[dec_dec_ctl.scala 17:17] + node _T_4218 = and(_T_4217, _T_4165) @[dec_dec_ctl.scala 17:17] + node _T_4219 = and(_T_4218, _T_4167) @[dec_dec_ctl.scala 17:17] + node _T_4220 = and(_T_4219, _T_4169) @[dec_dec_ctl.scala 17:17] + node _T_4221 = and(_T_4220, _T_4171) @[dec_dec_ctl.scala 17:17] + node _T_4222 = and(_T_4221, _T_4173) @[dec_dec_ctl.scala 17:17] + node _T_4223 = and(_T_4222, _T_4175) @[dec_dec_ctl.scala 17:17] + node _T_4224 = and(_T_4223, _T_4177) @[dec_dec_ctl.scala 17:17] + node _T_4225 = and(_T_4224, _T_4179) @[dec_dec_ctl.scala 17:17] + node _T_4226 = and(_T_4225, _T_4181) @[dec_dec_ctl.scala 17:17] + node _T_4227 = and(_T_4226, _T_4183) @[dec_dec_ctl.scala 17:17] + node _T_4228 = and(_T_4227, _T_4185) @[dec_dec_ctl.scala 17:17] + node _T_4229 = and(_T_4228, _T_4187) @[dec_dec_ctl.scala 17:17] + node _T_4230 = and(_T_4229, _T_4189) @[dec_dec_ctl.scala 17:17] + node _T_4231 = and(_T_4230, _T_4191) @[dec_dec_ctl.scala 17:17] + node _T_4232 = and(_T_4231, _T_4193) @[dec_dec_ctl.scala 17:17] + node _T_4233 = and(_T_4232, _T_4195) @[dec_dec_ctl.scala 17:17] + node _T_4234 = and(_T_4233, _T_4197) @[dec_dec_ctl.scala 17:17] + node _T_4235 = and(_T_4234, _T_4199) @[dec_dec_ctl.scala 17:17] + node _T_4236 = and(_T_4235, _T_4201) @[dec_dec_ctl.scala 17:17] + node _T_4237 = and(_T_4236, _T_4203) @[dec_dec_ctl.scala 17:17] + node _T_4238 = and(_T_4237, _T_4205) @[dec_dec_ctl.scala 17:17] + node _T_4239 = and(_T_4238, _T_4207) @[dec_dec_ctl.scala 17:17] + node _T_4240 = and(_T_4239, _T_4209) @[dec_dec_ctl.scala 17:17] + node _T_4241 = and(_T_4240, _T_4211) @[dec_dec_ctl.scala 17:17] + node _T_4242 = and(_T_4241, _T_4212) @[dec_dec_ctl.scala 17:17] + node _T_4243 = and(_T_4242, _T_4213) @[dec_dec_ctl.scala 17:17] + node _T_4244 = and(_T_4243, _T_4214) @[dec_dec_ctl.scala 17:17] + node _T_4245 = and(_T_4244, _T_4215) @[dec_dec_ctl.scala 17:17] + node _T_4246 = or(_T_4157, _T_4245) @[dec_dec_ctl.scala 261:117] + node _T_4247 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_4248 = eq(_T_4247, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4249 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_4250 = eq(_T_4249, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4251 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_4252 = eq(_T_4251, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4253 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_4254 = eq(_T_4253, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4255 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53] + node _T_4256 = eq(_T_4255, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4257 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53] + node _T_4258 = eq(_T_4257, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4259 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53] + node _T_4260 = eq(_T_4259, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4261 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53] + node _T_4262 = eq(_T_4261, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4263 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53] + node _T_4264 = eq(_T_4263, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4265 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_4266 = eq(_T_4265, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4267 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_4268 = eq(_T_4267, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4269 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_4270 = eq(_T_4269, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4271 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53] + node _T_4272 = eq(_T_4271, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4273 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53] + node _T_4274 = eq(_T_4273, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4275 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53] + node _T_4276 = eq(_T_4275, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4277 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53] + node _T_4278 = eq(_T_4277, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4279 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53] + node _T_4280 = eq(_T_4279, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4281 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4282 = eq(_T_4281, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4283 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_4284 = eq(_T_4283, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4285 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4286 = eq(_T_4285, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4287 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_4288 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_4289 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4290 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4291 = and(_T_4248, _T_4250) @[dec_dec_ctl.scala 17:17] + node _T_4292 = and(_T_4291, _T_4252) @[dec_dec_ctl.scala 17:17] + node _T_4293 = and(_T_4292, _T_4254) @[dec_dec_ctl.scala 17:17] + node _T_4294 = and(_T_4293, _T_4256) @[dec_dec_ctl.scala 17:17] + node _T_4295 = and(_T_4294, _T_4258) @[dec_dec_ctl.scala 17:17] + node _T_4296 = and(_T_4295, _T_4260) @[dec_dec_ctl.scala 17:17] + node _T_4297 = and(_T_4296, _T_4262) @[dec_dec_ctl.scala 17:17] + node _T_4298 = and(_T_4297, _T_4264) @[dec_dec_ctl.scala 17:17] + node _T_4299 = and(_T_4298, _T_4266) @[dec_dec_ctl.scala 17:17] + node _T_4300 = and(_T_4299, _T_4268) @[dec_dec_ctl.scala 17:17] + node _T_4301 = and(_T_4300, _T_4270) @[dec_dec_ctl.scala 17:17] + node _T_4302 = and(_T_4301, _T_4272) @[dec_dec_ctl.scala 17:17] + node _T_4303 = and(_T_4302, _T_4274) @[dec_dec_ctl.scala 17:17] + node _T_4304 = and(_T_4303, _T_4276) @[dec_dec_ctl.scala 17:17] + node _T_4305 = and(_T_4304, _T_4278) @[dec_dec_ctl.scala 17:17] + node _T_4306 = and(_T_4305, _T_4280) @[dec_dec_ctl.scala 17:17] + node _T_4307 = and(_T_4306, _T_4282) @[dec_dec_ctl.scala 17:17] + node _T_4308 = and(_T_4307, _T_4284) @[dec_dec_ctl.scala 17:17] + node _T_4309 = and(_T_4308, _T_4286) @[dec_dec_ctl.scala 17:17] + node _T_4310 = and(_T_4309, _T_4287) @[dec_dec_ctl.scala 17:17] + node _T_4311 = and(_T_4310, _T_4288) @[dec_dec_ctl.scala 17:17] + node _T_4312 = and(_T_4311, _T_4289) @[dec_dec_ctl.scala 17:17] + node _T_4313 = and(_T_4312, _T_4290) @[dec_dec_ctl.scala 17:17] + node _T_4314 = or(_T_4246, _T_4313) @[dec_dec_ctl.scala 262:130] + node _T_4315 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_4316 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_4317 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4318 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_4319 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4320 = eq(_T_4319, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4321 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4322 = eq(_T_4321, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4323 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4324 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4325 = and(_T_4315, _T_4316) @[dec_dec_ctl.scala 17:17] + node _T_4326 = and(_T_4325, _T_4317) @[dec_dec_ctl.scala 17:17] + node _T_4327 = and(_T_4326, _T_4318) @[dec_dec_ctl.scala 17:17] + node _T_4328 = and(_T_4327, _T_4320) @[dec_dec_ctl.scala 17:17] + node _T_4329 = and(_T_4328, _T_4322) @[dec_dec_ctl.scala 17:17] + node _T_4330 = and(_T_4329, _T_4323) @[dec_dec_ctl.scala 17:17] + node _T_4331 = and(_T_4330, _T_4324) @[dec_dec_ctl.scala 17:17] + node _T_4332 = or(_T_4314, _T_4331) @[dec_dec_ctl.scala 263:102] + node _T_4333 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_4334 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4335 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4336 = eq(_T_4335, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4337 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_4338 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_4339 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4340 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4341 = and(_T_4333, _T_4334) @[dec_dec_ctl.scala 17:17] + node _T_4342 = and(_T_4341, _T_4336) @[dec_dec_ctl.scala 17:17] + node _T_4343 = and(_T_4342, _T_4337) @[dec_dec_ctl.scala 17:17] + node _T_4344 = and(_T_4343, _T_4338) @[dec_dec_ctl.scala 17:17] + node _T_4345 = and(_T_4344, _T_4339) @[dec_dec_ctl.scala 17:17] + node _T_4346 = and(_T_4345, _T_4340) @[dec_dec_ctl.scala 17:17] + node _T_4347 = or(_T_4332, _T_4346) @[dec_dec_ctl.scala 264:39] + node _T_4348 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_4349 = eq(_T_4348, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4350 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_4351 = eq(_T_4350, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4352 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4353 = eq(_T_4352, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4354 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4355 = eq(_T_4354, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4356 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4357 = eq(_T_4356, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4358 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4359 = eq(_T_4358, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4360 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4361 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4362 = and(_T_4349, _T_4351) @[dec_dec_ctl.scala 17:17] + node _T_4363 = and(_T_4362, _T_4353) @[dec_dec_ctl.scala 17:17] + node _T_4364 = and(_T_4363, _T_4355) @[dec_dec_ctl.scala 17:17] + node _T_4365 = and(_T_4364, _T_4357) @[dec_dec_ctl.scala 17:17] + node _T_4366 = and(_T_4365, _T_4359) @[dec_dec_ctl.scala 17:17] + node _T_4367 = and(_T_4366, _T_4360) @[dec_dec_ctl.scala 17:17] + node _T_4368 = and(_T_4367, _T_4361) @[dec_dec_ctl.scala 17:17] + node _T_4369 = or(_T_4347, _T_4368) @[dec_dec_ctl.scala 264:71] + node _T_4370 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_4371 = eq(_T_4370, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4372 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4373 = eq(_T_4372, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4374 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_4375 = eq(_T_4374, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4376 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4377 = eq(_T_4376, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4378 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4379 = eq(_T_4378, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4380 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4381 = eq(_T_4380, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4382 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4383 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4384 = and(_T_4371, _T_4373) @[dec_dec_ctl.scala 17:17] + node _T_4385 = and(_T_4384, _T_4375) @[dec_dec_ctl.scala 17:17] + node _T_4386 = and(_T_4385, _T_4377) @[dec_dec_ctl.scala 17:17] + node _T_4387 = and(_T_4386, _T_4379) @[dec_dec_ctl.scala 17:17] + node _T_4388 = and(_T_4387, _T_4381) @[dec_dec_ctl.scala 17:17] + node _T_4389 = and(_T_4388, _T_4382) @[dec_dec_ctl.scala 17:17] + node _T_4390 = and(_T_4389, _T_4383) @[dec_dec_ctl.scala 17:17] + node _T_4391 = or(_T_4369, _T_4390) @[dec_dec_ctl.scala 264:112] + node _T_4392 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_4393 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4394 = eq(_T_4393, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4395 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_4396 = eq(_T_4395, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4397 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_4398 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4399 = eq(_T_4398, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4400 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4401 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4402 = and(_T_4392, _T_4394) @[dec_dec_ctl.scala 17:17] + node _T_4403 = and(_T_4402, _T_4396) @[dec_dec_ctl.scala 17:17] + node _T_4404 = and(_T_4403, _T_4397) @[dec_dec_ctl.scala 17:17] + node _T_4405 = and(_T_4404, _T_4399) @[dec_dec_ctl.scala 17:17] + node _T_4406 = and(_T_4405, _T_4400) @[dec_dec_ctl.scala 17:17] + node _T_4407 = and(_T_4406, _T_4401) @[dec_dec_ctl.scala 17:17] + node _T_4408 = or(_T_4391, _T_4407) @[dec_dec_ctl.scala 265:43] + node _T_4409 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4410 = eq(_T_4409, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4411 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_4412 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4413 = eq(_T_4412, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4414 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_4415 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4416 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4417 = and(_T_4410, _T_4411) @[dec_dec_ctl.scala 17:17] + node _T_4418 = and(_T_4417, _T_4413) @[dec_dec_ctl.scala 17:17] + node _T_4419 = and(_T_4418, _T_4414) @[dec_dec_ctl.scala 17:17] + node _T_4420 = and(_T_4419, _T_4415) @[dec_dec_ctl.scala 17:17] + node _T_4421 = and(_T_4420, _T_4416) @[dec_dec_ctl.scala 17:17] + node _T_4422 = or(_T_4408, _T_4421) @[dec_dec_ctl.scala 265:78] + io.out.legal <= _T_4422 @[dec_dec_ctl.scala 248:16] + diff --git a/dec_dec_ctl.v b/dec_dec_ctl.v new file mode 100644 index 00000000..0d0dc7a3 --- /dev/null +++ b/dec_dec_ctl.v @@ -0,0 +1,1496 @@ +module dec_dec_ctl( + input clock, + input reset, + input [31:0] io_ins, + output io_out_clz, + output io_out_ctz, + output io_out_pcnt, + output io_out_sext_b, + output io_out_sext_h, + output io_out_slo, + output io_out_sro, + output io_out_min, + output io_out_max, + output io_out_pack, + output io_out_packu, + output io_out_packh, + output io_out_rol, + output io_out_ror, + output io_out_grev, + output io_out_gorc, + output io_out_zbb, + output io_out_sbset, + output io_out_sbclr, + output io_out_sbinv, + output io_out_sbext, + output io_out_zbs, + output io_out_bext, + output io_out_bdep, + output io_out_zbe, + output io_out_clmul, + output io_out_clmulh, + output io_out_clmulr, + output io_out_zbc, + output io_out_shfl, + output io_out_unshfl, + output io_out_zbp, + output io_out_crc32_b, + output io_out_crc32_h, + output io_out_crc32_w, + output io_out_crc32c_b, + output io_out_crc32c_h, + output io_out_crc32c_w, + output io_out_zbr, + output io_out_bfp, + output io_out_zbf, + output io_out_sh1add, + output io_out_sh2add, + output io_out_sh3add, + output io_out_zba, + output io_out_alu, + output io_out_rs1, + output io_out_rs2, + output io_out_imm12, + output io_out_rd, + output io_out_shimm5, + output io_out_imm20, + output io_out_pc, + output io_out_load, + output io_out_store, + output io_out_lsu, + output io_out_add, + output io_out_sub, + output io_out_land, + output io_out_lor, + output io_out_lxor, + output io_out_sll, + output io_out_sra, + output io_out_srl, + output io_out_slt, + output io_out_unsign, + output io_out_condbr, + output io_out_beq, + output io_out_bne, + output io_out_bge, + output io_out_blt, + output io_out_jal, + output io_out_by, + output io_out_half, + output io_out_word, + output io_out_csr_read, + output io_out_csr_clr, + output io_out_csr_set, + output io_out_csr_write, + output io_out_csr_imm, + output io_out_presync, + output io_out_postsync, + output io_out_ebreak, + output io_out_ecall, + output io_out_mret, + output io_out_mul, + output io_out_rs1_sign, + output io_out_rs2_sign, + output io_out_low, + output io_out_div, + output io_out_rem, + output io_out_fence, + output io_out_fence_i, + output io_out_pm_alu, + output io_out_legal +); + wire _T_4 = ~io_ins[22]; // @[dec_dec_ctl.scala 15:46] + wire _T_6 = ~io_ins[21]; // @[dec_dec_ctl.scala 15:46] + wire _T_8 = ~io_ins[20]; // @[dec_dec_ctl.scala 15:46] + wire _T_11 = ~io_ins[5]; // @[dec_dec_ctl.scala 15:46] + wire _T_13 = io_ins[30] & io_ins[24]; // @[dec_dec_ctl.scala 17:17] + wire _T_14 = _T_13 & io_ins[23]; // @[dec_dec_ctl.scala 17:17] + wire _T_15 = _T_14 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_16 = _T_15 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_17 = _T_16 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_18 = _T_17 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_19 = _T_18 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_20 = _T_19 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_23 = ~io_ins[27]; // @[dec_dec_ctl.scala 15:46] + wire _T_25 = ~io_ins[24]; // @[dec_dec_ctl.scala 15:46] + wire _T_27 = io_ins[29] & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_28 = _T_27 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_29 = _T_28 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_30 = _T_20 | _T_29; // @[dec_dec_ctl.scala 20:62] + wire _T_32 = ~io_ins[25]; // @[dec_dec_ctl.scala 15:46] + wire _T_34 = ~io_ins[13]; // @[dec_dec_ctl.scala 15:46] + wire _T_36 = ~io_ins[12]; // @[dec_dec_ctl.scala 15:46] + wire _T_38 = _T_32 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_39 = _T_38 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_40 = _T_39 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_41 = _T_30 | _T_40; // @[dec_dec_ctl.scala 20:92] + wire _T_43 = ~io_ins[30]; // @[dec_dec_ctl.scala 15:46] + wire _T_48 = _T_43 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_49 = _T_48 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_50 = _T_49 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_51 = _T_41 | _T_50; // @[dec_dec_ctl.scala 21:34] + wire _T_56 = io_ins[27] & io_ins[25]; // @[dec_dec_ctl.scala 17:17] + wire _T_57 = _T_56 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_58 = _T_57 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_59 = _T_51 | _T_58; // @[dec_dec_ctl.scala 21:66] + wire _T_63 = ~io_ins[14]; // @[dec_dec_ctl.scala 15:46] + wire _T_65 = io_ins[29] & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_66 = _T_65 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_67 = _T_66 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_68 = _T_59 | _T_67; // @[dec_dec_ctl.scala 21:94] + wire _T_74 = io_ins[29] & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_75 = _T_74 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_76 = _T_75 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_77 = _T_68 | _T_76; // @[dec_dec_ctl.scala 22:32] + wire _T_84 = _T_23 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_85 = _T_84 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_86 = _T_85 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_87 = _T_77 | _T_86; // @[dec_dec_ctl.scala 22:60] + wire _T_90 = ~io_ins[29]; // @[dec_dec_ctl.scala 15:46] + wire _T_94 = io_ins[30] & _T_90; // @[dec_dec_ctl.scala 17:17] + wire _T_95 = _T_94 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_96 = _T_95 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_97 = _T_87 | _T_96; // @[dec_dec_ctl.scala 22:90] + wire _T_105 = _T_43 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_106 = _T_105 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_107 = _T_106 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_108 = _T_97 | _T_107; // @[dec_dec_ctl.scala 23:33] + wire _T_113 = io_ins[13] & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_114 = _T_113 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_115 = _T_108 | _T_114; // @[dec_dec_ctl.scala 23:64] + wire _T_121 = _T_36 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_122 = _T_121 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_123 = _T_115 | _T_122; // @[dec_dec_ctl.scala 23:89] + wire _T_125 = _T_123 | io_ins[2]; // @[dec_dec_ctl.scala 24:29] + wire _T_127 = _T_125 | io_ins[6]; // @[dec_dec_ctl.scala 24:48] + wire _T_139 = _T_14 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_140 = _T_139 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_141 = _T_140 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_142 = _T_141 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_143 = _T_142 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_144 = _T_127 | _T_143; // @[dec_dec_ctl.scala 24:67] + wire _T_151 = ~io_ins[23]; // @[dec_dec_ctl.scala 15:46] + wire _T_158 = _T_43 & io_ins[29]; // @[dec_dec_ctl.scala 17:17] + wire _T_159 = _T_158 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_160 = _T_159 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_161 = _T_160 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_162 = _T_161 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_163 = _T_162 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_164 = _T_163 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_165 = _T_164 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_166 = _T_144 | _T_165; // @[dec_dec_ctl.scala 24:107] + wire _T_181 = _T_43 & io_ins[24]; // @[dec_dec_ctl.scala 17:17] + wire _T_182 = _T_181 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_183 = _T_182 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_184 = _T_183 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_185 = _T_184 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_186 = _T_185 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_187 = _T_186 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_194 = ~io_ins[2]; // @[dec_dec_ctl.scala 15:46] + wire _T_195 = _T_63 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_196 = _T_195 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_202 = _T_34 & io_ins[11]; // @[dec_dec_ctl.scala 17:17] + wire _T_203 = _T_202 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_204 = _T_196 | _T_203; // @[dec_dec_ctl.scala 27:43] + wire _T_209 = io_ins[19] & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_210 = _T_209 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_211 = _T_204 | _T_210; // @[dec_dec_ctl.scala 27:70] + wire _T_217 = _T_34 & io_ins[10]; // @[dec_dec_ctl.scala 17:17] + wire _T_218 = _T_217 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_219 = _T_211 | _T_218; // @[dec_dec_ctl.scala 27:96] + wire _T_224 = io_ins[18] & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_225 = _T_224 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_226 = _T_219 | _T_225; // @[dec_dec_ctl.scala 28:30] + wire _T_232 = _T_34 & io_ins[9]; // @[dec_dec_ctl.scala 17:17] + wire _T_233 = _T_232 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_234 = _T_226 | _T_233; // @[dec_dec_ctl.scala 28:57] + wire _T_239 = io_ins[17] & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_240 = _T_239 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_241 = _T_234 | _T_240; // @[dec_dec_ctl.scala 28:83] + wire _T_247 = _T_34 & io_ins[8]; // @[dec_dec_ctl.scala 17:17] + wire _T_248 = _T_247 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_249 = _T_241 | _T_248; // @[dec_dec_ctl.scala 28:109] + wire _T_254 = io_ins[16] & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_255 = _T_254 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_256 = _T_249 | _T_255; // @[dec_dec_ctl.scala 29:29] + wire _T_262 = _T_34 & io_ins[7]; // @[dec_dec_ctl.scala 17:17] + wire _T_263 = _T_262 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_264 = _T_256 | _T_263; // @[dec_dec_ctl.scala 29:55] + wire _T_269 = io_ins[15] & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_270 = _T_269 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_271 = _T_264 | _T_270; // @[dec_dec_ctl.scala 29:81] + wire _T_273 = ~io_ins[4]; // @[dec_dec_ctl.scala 15:46] + wire _T_275 = ~io_ins[3]; // @[dec_dec_ctl.scala 15:46] + wire _T_276 = _T_273 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_277 = _T_271 | _T_276; // @[dec_dec_ctl.scala 30:29] + wire _T_279 = ~io_ins[6]; // @[dec_dec_ctl.scala 15:46] + wire _T_282 = _T_279 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_289 = io_ins[5] & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_290 = _T_289 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_296 = _T_279 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_297 = _T_296 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_305 = _T_276 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_314 = _T_114 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_315 = _T_305 | _T_314; // @[dec_dec_ctl.scala 34:42] + wire _T_322 = _T_34 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_323 = _T_322 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_324 = _T_323 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_325 = _T_315 | _T_324; // @[dec_dec_ctl.scala 34:70] + wire _T_335 = _T_122 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_341 = _T_11 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_344 = io_ins[5] & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_345 = _T_341 | _T_344; // @[dec_dec_ctl.scala 36:37] + wire _T_357 = io_ins[27] & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_358 = _T_357 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_359 = _T_358 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_360 = _T_359 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_361 = _T_360 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_372 = _T_43 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_373 = _T_372 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_374 = _T_373 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_375 = _T_374 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_376 = _T_375 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_377 = _T_361 | _T_376; // @[dec_dec_ctl.scala 38:53] + wire _T_387 = io_ins[14] & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_388 = _T_387 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_389 = _T_388 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_390 = _T_389 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_391 = _T_390 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_395 = io_ins[5] & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_398 = io_ins[4] & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_405 = _T_11 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_406 = _T_405 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_417 = _T_11 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_432 = _T_279 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_444 = _T_195 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_445 = _T_444 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_446 = _T_445 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_454 = _T_446 | _T_406; // @[dec_dec_ctl.scala 50:49] + wire _T_471 = _T_48 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_472 = _T_471 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_473 = _T_472 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_474 = _T_473 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_475 = _T_474 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_476 = _T_475 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_489 = io_ins[30] & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_490 = _T_489 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_491 = _T_490 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_492 = _T_491 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_493 = _T_492 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_494 = _T_493 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_507 = _T_90 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_508 = _T_507 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_509 = _T_508 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_510 = _T_509 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_511 = _T_510 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_512 = _T_511 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_513 = _T_494 | _T_512; // @[dec_dec_ctl.scala 52:53] + wire _T_524 = _T_57 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_525 = _T_524 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_526 = _T_525 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_527 = _T_513 | _T_526; // @[dec_dec_ctl.scala 52:93] + wire _T_536 = _T_63 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_537 = _T_536 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_538 = _T_537 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_539 = _T_538 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_540 = _T_527 | _T_539; // @[dec_dec_ctl.scala 53:37] + wire _T_546 = io_ins[6] & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_547 = _T_546 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_562 = _T_85 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_563 = _T_562 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_564 = _T_563 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_565 = _T_564 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_573 = io_ins[14] & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_574 = _T_573 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_575 = _T_574 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_576 = _T_575 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_581 = _T_279 & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_596 = _T_90 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_597 = _T_596 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_598 = _T_597 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_599 = _T_598 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_600 = _T_599 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_601 = _T_600 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_602 = _T_601 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_603 = _T_581 | _T_602; // @[dec_dec_ctl.scala 57:37] + wire _T_607 = io_ins[5] & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_608 = _T_607 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_609 = _T_603 | _T_608; // @[dec_dec_ctl.scala 57:82] + wire _T_619 = _T_609 | _T_324; // @[dec_dec_ctl.scala 57:105] + wire _T_629 = _T_573 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_630 = _T_629 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_631 = _T_630 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_650 = _T_598 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_651 = _T_650 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_652 = _T_651 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_653 = _T_652 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_665 = _T_387 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_666 = _T_665 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_667 = _T_666 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_668 = _T_667 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_688 = _T_597 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_689 = _T_688 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_690 = _T_689 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_691 = _T_690 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_692 = _T_691 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_708 = _T_94 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_709 = _T_708 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_710 = _T_709 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_711 = _T_710 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_712 = _T_711 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_731 = _T_43 & _T_90; // @[dec_dec_ctl.scala 17:17] + wire _T_732 = _T_731 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_733 = _T_732 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_734 = _T_733 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_735 = _T_734 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_736 = _T_735 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_737 = _T_736 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_738 = _T_737 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_781 = _T_23 & io_ins[25]; // @[dec_dec_ctl.scala 17:17] + wire _T_782 = _T_781 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_783 = _T_782 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_784 = _T_783 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_785 = _T_784 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_786 = _T_785 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_796 = _T_536 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_797 = _T_796 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_798 = _T_797 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_799 = _T_786 | _T_798; // @[dec_dec_ctl.scala 70:56] + wire _T_806 = io_ins[13] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_807 = _T_806 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_808 = _T_807 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_809 = _T_799 | _T_808; // @[dec_dec_ctl.scala 70:89] + wire _T_815 = io_ins[14] & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_816 = _T_815 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_817 = _T_809 | _T_816; // @[dec_dec_ctl.scala 71:31] + wire _T_828 = _T_32 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_829 = _T_828 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_830 = _T_829 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_831 = _T_830 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_832 = _T_831 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_833 = _T_817 | _T_832; // @[dec_dec_ctl.scala 71:57] + wire _T_845 = _T_57 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_846 = _T_845 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_847 = _T_846 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_848 = _T_847 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_866 = _T_63 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_867 = _T_866 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_868 = _T_867 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_878 = _T_63 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_879 = _T_878 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_880 = _T_879 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_889 = io_ins[14] & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_890 = _T_889 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_891 = _T_890 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_901 = io_ins[14] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_902 = _T_901 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_903 = _T_902 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_919 = _T_322 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_920 = _T_919 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_929 = io_ins[12] & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_930 = _T_929 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_937 = io_ins[13] & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_943 = _T_806 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_947 = io_ins[7] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_948 = _T_947 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_949 = _T_943 | _T_948; // @[dec_dec_ctl.scala 92:44] + wire _T_953 = io_ins[8] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_954 = _T_953 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_955 = _T_949 | _T_954; // @[dec_dec_ctl.scala 92:67] + wire _T_959 = io_ins[9] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_960 = _T_959 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_961 = _T_955 | _T_960; // @[dec_dec_ctl.scala 92:90] + wire _T_965 = io_ins[10] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_966 = _T_965 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_967 = _T_961 | _T_966; // @[dec_dec_ctl.scala 93:26] + wire _T_971 = io_ins[11] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_972 = _T_971 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_980 = _T_269 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_981 = _T_980 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_982 = _T_981 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_989 = _T_254 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_990 = _T_989 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_991 = _T_990 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_992 = _T_982 | _T_991; // @[dec_dec_ctl.scala 95:49] + wire _T_999 = _T_239 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1000 = _T_999 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1001 = _T_1000 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1002 = _T_992 | _T_1001; // @[dec_dec_ctl.scala 95:79] + wire _T_1009 = _T_224 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1010 = _T_1009 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1011 = _T_1010 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1012 = _T_1002 | _T_1011; // @[dec_dec_ctl.scala 96:33] + wire _T_1019 = _T_209 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1020 = _T_1019 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1021 = _T_1020 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1028 = io_ins[15] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1029 = _T_1028 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1030 = _T_1029 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1036 = io_ins[16] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1037 = _T_1036 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1038 = _T_1037 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1039 = _T_1030 | _T_1038; // @[dec_dec_ctl.scala 98:47] + wire _T_1045 = io_ins[17] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1046 = _T_1045 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1047 = _T_1046 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1048 = _T_1039 | _T_1047; // @[dec_dec_ctl.scala 98:75] + wire _T_1054 = io_ins[18] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1055 = _T_1054 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1056 = _T_1055 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1057 = _T_1048 | _T_1056; // @[dec_dec_ctl.scala 98:103] + wire _T_1063 = io_ins[19] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1064 = _T_1063 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1065 = _T_1064 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1072 = _T_34 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1073 = _T_1072 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1081 = _T_387 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1082 = _T_1081 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1087 = io_ins[15] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1088 = _T_1087 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1089 = _T_1088 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1090 = _T_1082 | _T_1089; // @[dec_dec_ctl.scala 103:47] + wire _T_1095 = io_ins[16] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1096 = _T_1095 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1097 = _T_1096 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1098 = _T_1090 | _T_1097; // @[dec_dec_ctl.scala 103:74] + wire _T_1103 = io_ins[17] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1104 = _T_1103 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1105 = _T_1104 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1106 = _T_1098 | _T_1105; // @[dec_dec_ctl.scala 103:101] + wire _T_1111 = io_ins[18] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1112 = _T_1111 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1113 = _T_1112 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1114 = _T_1106 | _T_1113; // @[dec_dec_ctl.scala 104:30] + wire _T_1119 = io_ins[19] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1120 = _T_1119 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1121 = _T_1120 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1126 = _T_11 & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_1133 = _T_262 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1134 = _T_1133 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1135 = _T_1126 | _T_1134; // @[dec_dec_ctl.scala 106:41] + wire _T_1142 = _T_247 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1143 = _T_1142 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1144 = _T_1135 | _T_1143; // @[dec_dec_ctl.scala 106:68] + wire _T_1151 = _T_232 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1152 = _T_1151 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1153 = _T_1144 | _T_1152; // @[dec_dec_ctl.scala 106:95] + wire _T_1160 = _T_217 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1161 = _T_1160 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1162 = _T_1153 | _T_1161; // @[dec_dec_ctl.scala 107:30] + wire _T_1169 = _T_202 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1170 = _T_1169 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1171 = _T_1162 | _T_1170; // @[dec_dec_ctl.scala 107:58] + wire _T_1177 = _T_269 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1178 = _T_1177 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1179 = _T_1171 | _T_1178; // @[dec_dec_ctl.scala 107:86] + wire _T_1185 = _T_254 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1186 = _T_1185 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1187 = _T_1179 | _T_1186; // @[dec_dec_ctl.scala 108:30] + wire _T_1193 = _T_239 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1194 = _T_1193 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1195 = _T_1187 | _T_1194; // @[dec_dec_ctl.scala 108:57] + wire _T_1201 = _T_224 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1202 = _T_1201 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1203 = _T_1195 | _T_1202; // @[dec_dec_ctl.scala 108:84] + wire _T_1209 = _T_209 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1210 = _T_1209 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1216 = io_ins[12] & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1217 = _T_1216 & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_1226 = _T_4 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1227 = _T_1226 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1228 = _T_1227 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1229 = _T_1228 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1230 = _T_1217 | _T_1229; // @[dec_dec_ctl.scala 111:45] + wire _T_1239 = _T_1230 | _T_1134; // @[dec_dec_ctl.scala 111:78] + wire _T_1248 = _T_1239 | _T_1143; // @[dec_dec_ctl.scala 112:30] + wire _T_1257 = _T_1248 | _T_1152; // @[dec_dec_ctl.scala 112:57] + wire _T_1266 = _T_1257 | _T_1161; // @[dec_dec_ctl.scala 112:84] + wire _T_1275 = _T_1266 | _T_1170; // @[dec_dec_ctl.scala 112:112] + wire _T_1283 = _T_1275 | _T_1178; // @[dec_dec_ctl.scala 113:31] + wire _T_1291 = _T_1283 | _T_1186; // @[dec_dec_ctl.scala 113:58] + wire _T_1299 = _T_1291 | _T_1194; // @[dec_dec_ctl.scala 113:85] + wire _T_1307 = _T_1299 | _T_1202; // @[dec_dec_ctl.scala 113:112] + wire _T_1325 = _T_4 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_1326 = _T_1325 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1327 = _T_1326 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1328 = _T_1327 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1340 = _T_6 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_1341 = _T_1340 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1342 = _T_1341 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1343 = _T_1342 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1352 = io_ins[29] & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1353 = _T_1352 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1354 = _T_1353 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1370 = _T_43 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_1371 = _T_1370 & io_ins[24]; // @[dec_dec_ctl.scala 17:17] + wire _T_1372 = _T_1371 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_1373 = _T_1372 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1374 = _T_1373 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1375 = _T_1374 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1376 = _T_1375 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1377 = _T_1376 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1378 = _T_1377 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1394 = _T_65 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_1395 = _T_1394 & io_ins[23]; // @[dec_dec_ctl.scala 17:17] + wire _T_1396 = _T_1395 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1397 = _T_1396 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1398 = _T_1397 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1399 = _T_1398 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1400 = _T_1399 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1401 = _T_1400 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1402 = _T_1378 | _T_1401; // @[dec_dec_ctl.scala 122:63] + wire _T_1420 = _T_1394 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_1421 = _T_1420 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1422 = _T_1421 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1423 = _T_1422 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1424 = _T_1423 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1425 = _T_1424 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1426 = _T_1425 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1427 = _T_1402 | _T_1426; // @[dec_dec_ctl.scala 122:111] + wire _T_1440 = io_ins[27] & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_1441 = _T_1440 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_1442 = _T_1441 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1443 = _T_1442 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1444 = _T_1443 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1445 = _T_1444 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1446 = _T_1445 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1447 = _T_1427 | _T_1446; // @[dec_dec_ctl.scala 123:52] + wire _T_1457 = io_ins[30] & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_1458 = _T_1457 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_1459 = _T_1458 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1460 = _T_1459 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1461 = _T_1460 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1462 = _T_1461 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1463 = _T_1447 | _T_1462; // @[dec_dec_ctl.scala 123:93] + wire _T_1479 = _T_65 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_1480 = _T_1479 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_1481 = _T_1480 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1482 = _T_1481 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1483 = _T_1482 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1484 = _T_1483 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1485 = _T_1484 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1486 = _T_1485 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1487 = _T_1463 | _T_1486; // @[dec_dec_ctl.scala 124:39] + wire _T_1503 = _T_65 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_1504 = _T_1503 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_1505 = _T_1504 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1506 = _T_1505 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1507 = _T_1506 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1508 = _T_1507 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1509 = _T_1508 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1510 = _T_1509 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1511 = _T_1487 | _T_1510; // @[dec_dec_ctl.scala 124:87] + wire _T_1527 = _T_65 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_1528 = _T_1527 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_1529 = _T_1528 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1530 = _T_1529 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1531 = _T_1530 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1532 = _T_1531 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1533 = _T_1532 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1534 = _T_1533 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1535 = _T_1511 | _T_1534; // @[dec_dec_ctl.scala 125:51] + wire _T_1550 = io_ins[30] & io_ins[29]; // @[dec_dec_ctl.scala 17:17] + wire _T_1551 = _T_1550 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_1552 = _T_1551 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_1553 = _T_1552 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1554 = _T_1553 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1555 = _T_1554 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1556 = _T_1555 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1557 = _T_1556 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1558 = _T_1557 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1559 = _T_1535 | _T_1558; // @[dec_dec_ctl.scala 125:99] + wire _T_1574 = _T_1370 & io_ins[23]; // @[dec_dec_ctl.scala 17:17] + wire _T_1575 = _T_1574 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1576 = _T_1575 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1577 = _T_1576 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1578 = _T_1577 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1579 = _T_1578 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1580 = _T_1579 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1581 = _T_1559 | _T_1580; // @[dec_dec_ctl.scala 126:51] + wire _T_1598 = _T_731 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_1599 = _T_1598 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_1600 = _T_1599 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1601 = _T_1600 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1602 = _T_1601 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1603 = _T_1602 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1604 = _T_1603 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1605 = _T_1581 | _T_1604; // @[dec_dec_ctl.scala 126:96] + wire _T_1615 = io_ins[25] & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1616 = _T_1615 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1617 = _T_1616 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1618 = _T_1617 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1619 = _T_1618 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1620 = _T_1605 | _T_1619; // @[dec_dec_ctl.scala 127:50] + wire _T_1635 = io_ins[30] & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_1636 = _T_1635 & io_ins[24]; // @[dec_dec_ctl.scala 17:17] + wire _T_1637 = _T_1636 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1638 = _T_1637 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1639 = _T_1638 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1640 = _T_1639 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1641 = _T_1640 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1642 = _T_1641 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1643 = _T_1620 | _T_1642; // @[dec_dec_ctl.scala 127:84] + wire _T_1653 = _T_65 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1654 = _T_1653 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1655 = _T_1654 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1656 = _T_1655 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1673 = _T_781 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1674 = _T_1673 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_1675 = _T_1674 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1676 = _T_1675 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1677 = _T_1676 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1678 = _T_1677 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1679 = _T_1678 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1695 = _T_1673 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1696 = _T_1695 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1697 = _T_1696 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1698 = _T_1697 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1699 = _T_1698 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1733 = _T_1615 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1734 = _T_1733 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1735 = _T_1734 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1736 = _T_1735 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1749 = _T_782 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1750 = _T_1749 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1764 = _T_782 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_1765 = _T_1764 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1766 = _T_1765 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1800 = _T_1635 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_1801 = _T_1800 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_1802 = _T_1801 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_1803 = _T_1802 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_1804 = _T_1803 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1805 = _T_1804 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1806 = _T_1805 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1807 = _T_1806 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1808 = _T_1807 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1831 = _T_1801 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_1832 = _T_1831 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1833 = _T_1832 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1834 = _T_1833 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1835 = _T_1834 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1836 = _T_1835 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1856 = _T_1800 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_1857 = _T_1856 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1858 = _T_1857 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1859 = _T_1858 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1860 = _T_1859 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1861 = _T_1860 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1880 = _T_1635 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_1881 = _T_1880 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_1882 = _T_1881 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1883 = _T_1882 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1884 = _T_1883 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1885 = _T_1884 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1886 = _T_1885 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1905 = _T_1880 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_1906 = _T_1905 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1907 = _T_1906 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1908 = _T_1907 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1909 = _T_1908 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1910 = _T_1909 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1928 = _T_158 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_1929 = _T_1928 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1930 = _T_1929 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1931 = _T_1930 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1932 = _T_1931 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1933 = _T_1932 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1951 = _T_1928 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1952 = _T_1951 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1953 = _T_1952 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1954 = _T_1953 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1955 = _T_1954 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1969 = _T_57 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1970 = _T_1969 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1971 = _T_1970 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1984 = _T_57 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1985 = _T_1984 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1986 = _T_1985 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2002 = _T_1370 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_2003 = _T_2002 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2004 = _T_2003 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2005 = _T_2004 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2006 = _T_2005 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2019 = _T_1457 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2020 = _T_2019 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2021 = _T_2020 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2022 = _T_2021 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2038 = _T_2002 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_2039 = _T_2038 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2040 = _T_2039 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2041 = _T_2040 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2056 = _T_1635 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2057 = _T_2056 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2058 = _T_2057 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2059 = _T_2058 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2060 = _T_2059 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2076 = _T_1550 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_2077 = _T_2076 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2078 = _T_2077 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2079 = _T_2078 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2080 = _T_2079 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2081 = _T_2080 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2100 = _T_1800 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2101 = _T_2100 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2102 = _T_2101 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2103 = _T_2102 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2104 = _T_2103 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2105 = _T_2104 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2118 = _T_1370 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2119 = _T_2118 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_2120 = _T_2119 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2121 = _T_2120 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2122 = _T_2121 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2123 = _T_2122 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2124 = _T_2105 | _T_2123; // @[dec_dec_ctl.scala 172:62] + wire _T_2143 = _T_2079 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2144 = _T_2143 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2145 = _T_2144 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2146 = _T_2124 | _T_2145; // @[dec_dec_ctl.scala 172:103] + wire _T_2157 = _T_357 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2158 = _T_2157 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2159 = _T_2158 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2160 = _T_2159 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2161 = _T_2146 | _T_2160; // @[dec_dec_ctl.scala 173:48] + wire _T_2173 = io_ins[30] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2174 = _T_2173 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2175 = _T_2174 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2176 = _T_2175 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2177 = _T_2176 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2178 = _T_2177 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2179 = _T_2161 | _T_2178; // @[dec_dec_ctl.scala 173:83] + wire _T_2191 = _T_1635 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_2192 = _T_2191 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2193 = _T_2192 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2194 = _T_2193 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2195 = _T_2194 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2196 = _T_2179 | _T_2195; // @[dec_dec_ctl.scala 174:42] + wire _T_2209 = _T_2076 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2210 = _T_2209 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2211 = _T_2210 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2212 = _T_2211 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2213 = _T_2196 | _T_2212; // @[dec_dec_ctl.scala 174:79] + wire _T_2231 = _T_1550 & io_ins[24]; // @[dec_dec_ctl.scala 17:17] + wire _T_2232 = _T_2231 & io_ins[23]; // @[dec_dec_ctl.scala 17:17] + wire _T_2233 = _T_2232 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_2234 = _T_2233 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_2235 = _T_2234 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_2236 = _T_2235 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2237 = _T_2236 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2238 = _T_2237 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2239 = _T_2238 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2240 = _T_2239 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2241 = _T_2240 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2242 = _T_2213 | _T_2241; // @[dec_dec_ctl.scala 175:40] + wire _T_2264 = _T_158 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_2265 = _T_2264 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_2266 = _T_2265 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_2267 = _T_2266 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_2268 = _T_2267 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_2269 = _T_2268 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_2270 = _T_2269 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2271 = _T_2270 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2272 = _T_2271 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2273 = _T_2272 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2274 = _T_2273 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2275 = _T_2274 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2276 = _T_2242 | _T_2275; // @[dec_dec_ctl.scala 175:96] + wire _T_2300 = _T_1371 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_2301 = _T_2300 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_2302 = _T_2301 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_2303 = _T_2302 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_2304 = _T_2303 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2305 = _T_2304 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2306 = _T_2305 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2307 = _T_2306 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2308 = _T_2307 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2309 = _T_2308 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2310 = _T_2276 | _T_2309; // @[dec_dec_ctl.scala 176:65] + wire _T_2333 = _T_2232 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_2334 = _T_2333 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_2335 = _T_2334 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_2336 = _T_2335 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2337 = _T_2336 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2338 = _T_2337 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2339 = _T_2338 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2340 = _T_2339 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2341 = _T_2340 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2342 = _T_2310 | _T_2341; // @[dec_dec_ctl.scala 177:64] + wire _T_2373 = _T_2264 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2374 = _T_2373 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2375 = _T_2374 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2376 = _T_2375 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2377 = _T_2376 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2393 = _T_94 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2394 = _T_2393 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2395 = _T_2394 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2396 = _T_2395 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2397 = _T_2396 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2414 = _T_1551 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2415 = _T_2414 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2416 = _T_2415 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2417 = _T_2416 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2418 = _T_2417 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2434 = _T_94 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_2435 = _T_2434 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2436 = _T_2435 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2437 = _T_2436 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2438 = _T_2437 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2439 = _T_2438 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2455 = _T_66 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2456 = _T_2455 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2457 = _T_2456 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2458 = _T_2457 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2459 = _T_2458 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2474 = _T_2434 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2475 = _T_2474 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2476 = _T_2475 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2477 = _T_2476 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2478 = _T_2477 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2497 = _T_2038 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2498 = _T_2497 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2499 = _T_2498 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2500 = _T_2499 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2515 = _T_1458 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2516 = _T_2515 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2517 = _T_2516 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2518 = _T_2517 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2552 = _T_56 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2553 = _T_2552 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2554 = _T_2553 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2555 = _T_2554 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2556 = _T_2555 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2568 = io_ins[27] & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2569 = _T_2568 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_2570 = _T_2569 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2571 = _T_2570 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2572 = _T_2571 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2586 = _T_2568 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2587 = _T_2586 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2588 = _T_2587 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2589 = _T_2588 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2603 = _T_2552 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2604 = _T_2603 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2605 = _T_2604 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2621 = _T_1551 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2622 = _T_2621 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2623 = _T_2622 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2624 = _T_2623 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2625 = _T_2624 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2642 = _T_2264 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2643 = _T_2642 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2644 = _T_2643 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2645 = _T_2644 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2646 = _T_2645 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2668 = _T_1599 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2669 = _T_2668 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2670 = _T_2669 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2671 = _T_2670 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2672 = _T_2671 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2693 = _T_1599 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2694 = _T_2693 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2695 = _T_2694 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2696 = _T_2695 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2697 = _T_2696 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2714 = _T_1928 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2715 = _T_2714 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2716 = _T_2715 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2717 = _T_2716 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2718 = _T_2717 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2734 = _T_1598 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2735 = _T_2734 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2736 = _T_2735 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2737 = _T_2736 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2738 = _T_2737 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2739 = _T_2718 | _T_2738; // @[dec_dec_ctl.scala 212:58] + wire _T_2756 = _T_2739 | _T_2195; // @[dec_dec_ctl.scala 212:101] + wire _T_2769 = _T_1440 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2770 = _T_2769 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2771 = _T_2770 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2772 = _T_2771 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2773 = _T_2772 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2774 = _T_2756 | _T_2773; // @[dec_dec_ctl.scala 213:40] + wire _T_2788 = _T_2175 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2789 = _T_2788 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2790 = _T_2789 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2791 = _T_2774 | _T_2790; // @[dec_dec_ctl.scala 213:79] + wire _T_2803 = _T_27 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2804 = _T_2803 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2805 = _T_2804 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2806 = _T_2805 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2807 = _T_2806 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2808 = _T_2791 | _T_2807; // @[dec_dec_ctl.scala 214:41] + wire _T_2826 = _T_1599 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2827 = _T_2826 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2828 = _T_2827 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2829 = _T_2828 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2830 = _T_2829 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2831 = _T_2808 | _T_2830; // @[dec_dec_ctl.scala 214:78] + wire _T_2842 = io_ins[29] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2843 = _T_2842 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2844 = _T_2843 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2845 = _T_2844 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2846 = _T_2845 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2847 = _T_2846 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2871 = _T_1636 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_2872 = _T_2871 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_2873 = _T_2872 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_2874 = _T_2873 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2875 = _T_2874 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2876 = _T_2875 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2877 = _T_2876 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2878 = _T_2877 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2900 = _T_2871 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_2901 = _T_2900 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2902 = _T_2901 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2903 = _T_2902 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2904 = _T_2903 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2905 = _T_2904 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2927 = _T_2871 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_2928 = _T_2927 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2929 = _T_2928 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2930 = _T_2929 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2931 = _T_2930 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2932 = _T_2931 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2953 = _T_1635 & io_ins[23]; // @[dec_dec_ctl.scala 17:17] + wire _T_2954 = _T_2953 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_2955 = _T_2954 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_2956 = _T_2955 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2957 = _T_2956 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2958 = _T_2957 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2959 = _T_2958 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2960 = _T_2959 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2979 = _T_2953 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_2980 = _T_2979 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2981 = _T_2980 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2982 = _T_2981 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2983 = _T_2982 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2984 = _T_2983 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3003 = _T_2953 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_3004 = _T_3003 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_3005 = _T_3004 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_3006 = _T_3005 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_3007 = _T_3006 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3008 = _T_3007 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3043 = _T_1458 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_3044 = _T_3043 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3045 = _T_3044 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3074 = _T_74 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3075 = _T_3074 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3076 = _T_3075 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3077 = _T_3076 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3091 = _T_2843 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3092 = _T_3091 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3093 = _T_3092 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3104 = _T_2842 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_3105 = _T_3104 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3106 = _T_3105 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3117 = io_ins[29] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3118 = _T_3117 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3119 = _T_3118 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3120 = _T_3119 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3129 = io_ins[28] & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_3130 = _T_3129 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_3131 = _T_3130 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3132 = _T_3131 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3147 = _T_733 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3148 = _T_3147 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3149 = _T_3132 | _T_3148; // @[dec_dec_ctl.scala 243:51] + wire _T_3164 = _T_597 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_3165 = _T_3164 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_3166 = _T_3165 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3167 = _T_3166 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3168 = _T_3149 | _T_3167; // @[dec_dec_ctl.scala 243:89] + wire _T_3183 = _T_688 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3184 = _T_3183 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3185 = _T_3168 | _T_3184; // @[dec_dec_ctl.scala 244:44] + wire _T_3192 = _T_3185 | _T_114; // @[dec_dec_ctl.scala 244:82] + wire _T_3196 = _T_3192 | _T_398; // @[dec_dec_ctl.scala 245:28] + wire _T_3206 = ~io_ins[31]; // @[dec_dec_ctl.scala 15:46] + wire _T_3215 = ~io_ins[26]; // @[dec_dec_ctl.scala 15:46] + wire _T_3227 = ~io_ins[19]; // @[dec_dec_ctl.scala 15:46] + wire _T_3229 = ~io_ins[18]; // @[dec_dec_ctl.scala 15:46] + wire _T_3231 = ~io_ins[17]; // @[dec_dec_ctl.scala 15:46] + wire _T_3233 = ~io_ins[16]; // @[dec_dec_ctl.scala 15:46] + wire _T_3235 = ~io_ins[15]; // @[dec_dec_ctl.scala 15:46] + wire _T_3239 = ~io_ins[11]; // @[dec_dec_ctl.scala 15:46] + wire _T_3241 = ~io_ins[10]; // @[dec_dec_ctl.scala 15:46] + wire _T_3243 = ~io_ins[9]; // @[dec_dec_ctl.scala 15:46] + wire _T_3245 = ~io_ins[8]; // @[dec_dec_ctl.scala 15:46] + wire _T_3247 = ~io_ins[7]; // @[dec_dec_ctl.scala 15:46] + wire _T_3257 = _T_3206 & _T_43; // @[dec_dec_ctl.scala 17:17] + wire _T_3258 = _T_3257 & _T_90; // @[dec_dec_ctl.scala 17:17] + wire _T_3259 = _T_3258 & io_ins[28]; // @[dec_dec_ctl.scala 17:17] + wire _T_3260 = _T_3259 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_3261 = _T_3260 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3262 = _T_3261 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3263 = _T_3262 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_3264 = _T_3263 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_3265 = _T_3264 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_3266 = _T_3265 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_3267 = _T_3266 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_3268 = _T_3267 & _T_3227; // @[dec_dec_ctl.scala 17:17] + wire _T_3269 = _T_3268 & _T_3229; // @[dec_dec_ctl.scala 17:17] + wire _T_3270 = _T_3269 & _T_3231; // @[dec_dec_ctl.scala 17:17] + wire _T_3271 = _T_3270 & _T_3233; // @[dec_dec_ctl.scala 17:17] + wire _T_3272 = _T_3271 & _T_3235; // @[dec_dec_ctl.scala 17:17] + wire _T_3273 = _T_3272 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_3274 = _T_3273 & _T_3239; // @[dec_dec_ctl.scala 17:17] + wire _T_3275 = _T_3274 & _T_3241; // @[dec_dec_ctl.scala 17:17] + wire _T_3276 = _T_3275 & _T_3243; // @[dec_dec_ctl.scala 17:17] + wire _T_3277 = _T_3276 & _T_3245; // @[dec_dec_ctl.scala 17:17] + wire _T_3278 = _T_3277 & _T_3247; // @[dec_dec_ctl.scala 17:17] + wire _T_3279 = _T_3278 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_3280 = _T_3279 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3281 = _T_3280 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3282 = _T_3281 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3283 = _T_3282 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_3284 = _T_3283 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3285 = _T_3284 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3339 = _T_3257 & io_ins[29]; // @[dec_dec_ctl.scala 17:17] + wire _T_3340 = _T_3339 & io_ins[28]; // @[dec_dec_ctl.scala 17:17] + wire _T_3341 = _T_3340 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_3342 = _T_3341 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3343 = _T_3342 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3344 = _T_3343 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_3345 = _T_3344 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_3346 = _T_3345 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_3347 = _T_3346 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_3348 = _T_3347 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_3349 = _T_3348 & _T_3227; // @[dec_dec_ctl.scala 17:17] + wire _T_3350 = _T_3349 & _T_3229; // @[dec_dec_ctl.scala 17:17] + wire _T_3351 = _T_3350 & _T_3231; // @[dec_dec_ctl.scala 17:17] + wire _T_3352 = _T_3351 & _T_3233; // @[dec_dec_ctl.scala 17:17] + wire _T_3353 = _T_3352 & _T_3235; // @[dec_dec_ctl.scala 17:17] + wire _T_3354 = _T_3353 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_3355 = _T_3354 & _T_3239; // @[dec_dec_ctl.scala 17:17] + wire _T_3356 = _T_3355 & _T_3241; // @[dec_dec_ctl.scala 17:17] + wire _T_3357 = _T_3356 & _T_3243; // @[dec_dec_ctl.scala 17:17] + wire _T_3358 = _T_3357 & _T_3245; // @[dec_dec_ctl.scala 17:17] + wire _T_3359 = _T_3358 & _T_3247; // @[dec_dec_ctl.scala 17:17] + wire _T_3360 = _T_3359 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_3361 = _T_3360 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3362 = _T_3361 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3363 = _T_3362 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3364 = _T_3363 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_3365 = _T_3364 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3366 = _T_3365 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3367 = _T_3285 | _T_3366; // @[dec_dec_ctl.scala 248:136] + wire _T_3375 = ~io_ins[28]; // @[dec_dec_ctl.scala 15:46] + wire _T_3422 = _T_3258 & _T_3375; // @[dec_dec_ctl.scala 17:17] + wire _T_3423 = _T_3422 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_3424 = _T_3423 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3425 = _T_3424 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3426 = _T_3425 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_3427 = _T_3426 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_3428 = _T_3427 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_3429 = _T_3428 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_3430 = _T_3429 & _T_3227; // @[dec_dec_ctl.scala 17:17] + wire _T_3431 = _T_3430 & _T_3229; // @[dec_dec_ctl.scala 17:17] + wire _T_3432 = _T_3431 & _T_3231; // @[dec_dec_ctl.scala 17:17] + wire _T_3433 = _T_3432 & _T_3233; // @[dec_dec_ctl.scala 17:17] + wire _T_3434 = _T_3433 & _T_3235; // @[dec_dec_ctl.scala 17:17] + wire _T_3435 = _T_3434 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_3436 = _T_3435 & _T_3239; // @[dec_dec_ctl.scala 17:17] + wire _T_3437 = _T_3436 & _T_3241; // @[dec_dec_ctl.scala 17:17] + wire _T_3438 = _T_3437 & _T_3243; // @[dec_dec_ctl.scala 17:17] + wire _T_3439 = _T_3438 & _T_3245; // @[dec_dec_ctl.scala 17:17] + wire _T_3440 = _T_3439 & _T_3247; // @[dec_dec_ctl.scala 17:17] + wire _T_3441 = _T_3440 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3442 = _T_3441 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3443 = _T_3442 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3444 = _T_3443 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_3445 = _T_3444 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3446 = _T_3445 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3447 = _T_3367 | _T_3446; // @[dec_dec_ctl.scala 249:122] + wire _T_3471 = _T_3206 & io_ins[29]; // @[dec_dec_ctl.scala 17:17] + wire _T_3472 = _T_3471 & _T_3375; // @[dec_dec_ctl.scala 17:17] + wire _T_3473 = _T_3472 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3474 = _T_3473 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3475 = _T_3474 & io_ins[24]; // @[dec_dec_ctl.scala 17:17] + wire _T_3476 = _T_3475 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_3477 = _T_3476 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_3478 = _T_3477 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3479 = _T_3478 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3480 = _T_3479 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3481 = _T_3480 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3482 = _T_3481 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3483 = _T_3482 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3484 = _T_3447 | _T_3483; // @[dec_dec_ctl.scala 250:119] + wire _T_3514 = _T_3476 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_3515 = _T_3514 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3516 = _T_3515 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3517 = _T_3516 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3518 = _T_3517 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3519 = _T_3518 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3520 = _T_3519 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3521 = _T_3484 | _T_3520; // @[dec_dec_ctl.scala 251:65] + wire _T_3550 = _T_3474 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_3551 = _T_3550 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_3552 = _T_3551 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_3553 = _T_3552 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3554 = _T_3553 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3555 = _T_3554 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3556 = _T_3555 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3557 = _T_3556 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3558 = _T_3557 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3559 = _T_3521 | _T_3558; // @[dec_dec_ctl.scala 251:127] + wire _T_3588 = _T_3474 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_3589 = _T_3588 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_3590 = _T_3589 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_3591 = _T_3590 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3592 = _T_3591 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3593 = _T_3592 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3594 = _T_3593 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3595 = _T_3594 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3596 = _T_3595 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3597 = _T_3559 | _T_3596; // @[dec_dec_ctl.scala 252:66] + wire _T_3620 = _T_3422 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3621 = _T_3620 & io_ins[25]; // @[dec_dec_ctl.scala 17:17] + wire _T_3622 = _T_3621 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_3623 = _T_3622 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3624 = _T_3623 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3625 = _T_3624 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3626 = _T_3625 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3627 = _T_3626 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3628 = _T_3597 | _T_3627; // @[dec_dec_ctl.scala 252:129] + wire _T_3651 = _T_3257 & _T_3375; // @[dec_dec_ctl.scala 17:17] + wire _T_3652 = _T_3651 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3653 = _T_3652 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3654 = _T_3653 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_3655 = _T_3654 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3656 = _T_3655 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3657 = _T_3656 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3658 = _T_3657 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3659 = _T_3658 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3660 = _T_3659 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3661 = _T_3628 | _T_3660; // @[dec_dec_ctl.scala 253:58] + wire _T_3686 = _T_3651 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_3687 = _T_3686 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3688 = _T_3687 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3689 = _T_3688 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_3690 = _T_3689 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3691 = _T_3690 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3692 = _T_3691 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3693 = _T_3692 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3694 = _T_3693 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3695 = _T_3694 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3696 = _T_3661 | _T_3695; // @[dec_dec_ctl.scala 253:114] + wire _T_3724 = _T_3688 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_3725 = _T_3724 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3726 = _T_3725 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3727 = _T_3726 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3728 = _T_3727 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3729 = _T_3728 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3730 = _T_3729 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3731 = _T_3696 | _T_3730; // @[dec_dec_ctl.scala 254:63] + wire _T_3755 = _T_3206 & _T_90; // @[dec_dec_ctl.scala 17:17] + wire _T_3756 = _T_3755 & _T_3375; // @[dec_dec_ctl.scala 17:17] + wire _T_3757 = _T_3756 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_3758 = _T_3757 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3759 = _T_3758 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3760 = _T_3759 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_3761 = _T_3760 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3762 = _T_3761 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3763 = _T_3762 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3764 = _T_3763 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3765 = _T_3764 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3766 = _T_3765 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3767 = _T_3731 | _T_3766; // @[dec_dec_ctl.scala 254:123] + wire _T_3788 = _T_3206 & _T_3375; // @[dec_dec_ctl.scala 17:17] + wire _T_3789 = _T_3788 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_3790 = _T_3789 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3791 = _T_3790 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3792 = _T_3791 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_3793 = _T_3792 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3794 = _T_3793 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3795 = _T_3794 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3796 = _T_3795 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3797 = _T_3796 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3798 = _T_3797 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3799 = _T_3767 | _T_3798; // @[dec_dec_ctl.scala 255:64] + wire _T_3825 = _T_3620 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_3826 = _T_3825 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_3827 = _T_3826 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3828 = _T_3827 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3829 = _T_3828 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3830 = _T_3829 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_3831 = _T_3830 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3832 = _T_3831 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3833 = _T_3799 | _T_3832; // @[dec_dec_ctl.scala 255:119] + wire _T_3857 = _T_3620 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_3858 = _T_3857 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3859 = _T_3858 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3860 = _T_3859 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3861 = _T_3860 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3862 = _T_3861 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3863 = _T_3862 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3864 = _T_3833 | _T_3863; // @[dec_dec_ctl.scala 256:61] + wire _T_3885 = _T_3206 & io_ins[30]; // @[dec_dec_ctl.scala 17:17] + wire _T_3886 = _T_3885 & _T_3375; // @[dec_dec_ctl.scala 17:17] + wire _T_3887 = _T_3886 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_3888 = _T_3887 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3889 = _T_3888 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3890 = _T_3889 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_3891 = _T_3890 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_3892 = _T_3891 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3893 = _T_3892 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3894 = _T_3893 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3895 = _T_3894 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3896 = _T_3895 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3897 = _T_3864 | _T_3896; // @[dec_dec_ctl.scala 256:115] + wire _T_3919 = _T_3472 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_3920 = _T_3919 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3921 = _T_3920 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3922 = _T_3921 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3923 = _T_3922 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3924 = _T_3923 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3925 = _T_3924 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3926 = _T_3925 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3927 = _T_3926 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3928 = _T_3897 | _T_3927; // @[dec_dec_ctl.scala 257:61] + wire _T_3955 = _T_3688 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3956 = _T_3955 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3957 = _T_3956 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3958 = _T_3957 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3959 = _T_3958 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3960 = _T_3959 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3961 = _T_3928 | _T_3960; // @[dec_dec_ctl.scala 257:116] + wire _T_3987 = _T_3424 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3988 = _T_3987 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3989 = _T_3988 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3990 = _T_3989 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3991 = _T_3990 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3992 = _T_3991 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3993 = _T_3961 | _T_3992; // @[dec_dec_ctl.scala 258:59] + wire _T_4010 = _T_444 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_4011 = _T_4010 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4012 = _T_4011 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4013 = _T_4012 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4014 = _T_4013 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4015 = _T_4014 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4016 = _T_3993 | _T_4015; // @[dec_dec_ctl.scala 258:114] + wire _T_4038 = _T_3756 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_4039 = _T_4038 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_4040 = _T_4039 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_4041 = _T_4040 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_4042 = _T_4041 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4043 = _T_4042 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_4044 = _T_4043 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4045 = _T_4044 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4046 = _T_4045 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4047 = _T_4016 | _T_4046; // @[dec_dec_ctl.scala 259:46] + wire _T_4072 = _T_3474 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_4073 = _T_4072 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_4074 = _T_4073 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4075 = _T_4074 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_4076 = _T_4075 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4077 = _T_4076 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4078 = _T_4077 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4079 = _T_4078 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4080 = _T_4047 | _T_4079; // @[dec_dec_ctl.scala 259:100] + wire _T_4092 = io_ins[14] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_4093 = _T_4092 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4094 = _T_4093 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4095 = _T_4094 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4096 = _T_4095 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4097 = _T_4096 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4098 = _T_4097 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4099 = _T_4080 | _T_4098; // @[dec_dec_ctl.scala 260:60] + wire _T_4114 = _T_195 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4115 = _T_4114 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4116 = _T_4115 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4117 = _T_4116 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4118 = _T_4117 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4119 = _T_4118 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4120 = _T_4099 | _T_4119; // @[dec_dec_ctl.scala 260:97] + wire _T_4132 = _T_36 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_4133 = _T_4132 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_4134 = _T_4133 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_4135 = _T_4134 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4136 = _T_4135 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4137 = _T_4136 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4138 = _T_4120 | _T_4137; // @[dec_dec_ctl.scala 261:43] + wire _T_4152 = _T_1073 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4153 = _T_4152 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4154 = _T_4153 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4155 = _T_4154 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4156 = _T_4155 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4157 = _T_4138 | _T_4156; // @[dec_dec_ctl.scala 261:79] + wire _T_4226 = _T_3429 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_4227 = _T_4226 & _T_3227; // @[dec_dec_ctl.scala 17:17] + wire _T_4228 = _T_4227 & _T_3229; // @[dec_dec_ctl.scala 17:17] + wire _T_4229 = _T_4228 & _T_3231; // @[dec_dec_ctl.scala 17:17] + wire _T_4230 = _T_4229 & _T_3233; // @[dec_dec_ctl.scala 17:17] + wire _T_4231 = _T_4230 & _T_3235; // @[dec_dec_ctl.scala 17:17] + wire _T_4232 = _T_4231 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_4233 = _T_4232 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_4234 = _T_4233 & _T_3239; // @[dec_dec_ctl.scala 17:17] + wire _T_4235 = _T_4234 & _T_3241; // @[dec_dec_ctl.scala 17:17] + wire _T_4236 = _T_4235 & _T_3243; // @[dec_dec_ctl.scala 17:17] + wire _T_4237 = _T_4236 & _T_3245; // @[dec_dec_ctl.scala 17:17] + wire _T_4238 = _T_4237 & _T_3247; // @[dec_dec_ctl.scala 17:17] + wire _T_4239 = _T_4238 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_4240 = _T_4239 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_4241 = _T_4240 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4242 = _T_4241 & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_4243 = _T_4242 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_4244 = _T_4243 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4245 = _T_4244 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4246 = _T_4157 | _T_4245; // @[dec_dec_ctl.scala 261:117] + wire _T_4294 = _T_3422 & _T_3227; // @[dec_dec_ctl.scala 17:17] + wire _T_4295 = _T_4294 & _T_3229; // @[dec_dec_ctl.scala 17:17] + wire _T_4296 = _T_4295 & _T_3231; // @[dec_dec_ctl.scala 17:17] + wire _T_4297 = _T_4296 & _T_3233; // @[dec_dec_ctl.scala 17:17] + wire _T_4298 = _T_4297 & _T_3235; // @[dec_dec_ctl.scala 17:17] + wire _T_4299 = _T_4298 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_4300 = _T_4299 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_4301 = _T_4300 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_4302 = _T_4301 & _T_3239; // @[dec_dec_ctl.scala 17:17] + wire _T_4303 = _T_4302 & _T_3241; // @[dec_dec_ctl.scala 17:17] + wire _T_4304 = _T_4303 & _T_3243; // @[dec_dec_ctl.scala 17:17] + wire _T_4305 = _T_4304 & _T_3245; // @[dec_dec_ctl.scala 17:17] + wire _T_4306 = _T_4305 & _T_3247; // @[dec_dec_ctl.scala 17:17] + wire _T_4307 = _T_4306 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_4308 = _T_4307 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_4309 = _T_4308 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4310 = _T_4309 & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_4311 = _T_4310 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_4312 = _T_4311 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4313 = _T_4312 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4314 = _T_4246 | _T_4313; // @[dec_dec_ctl.scala 262:130] + wire _T_4326 = _T_806 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4327 = _T_4326 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_4328 = _T_4327 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4329 = _T_4328 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4330 = _T_4329 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4331 = _T_4330 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4332 = _T_4314 | _T_4331; // @[dec_dec_ctl.scala 263:102] + wire _T_4341 = io_ins[6] & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4342 = _T_4341 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4343 = _T_4342 & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_4344 = _T_4343 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_4345 = _T_4344 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4346 = _T_4345 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4347 = _T_4332 | _T_4346; // @[dec_dec_ctl.scala 264:39] + wire _T_4363 = _T_866 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_4364 = _T_4363 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4365 = _T_4364 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4366 = _T_4365 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4367 = _T_4366 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4368 = _T_4367 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4369 = _T_4347 | _T_4368; // @[dec_dec_ctl.scala 264:71] + wire _T_4384 = _T_34 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_4385 = _T_4384 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_4386 = _T_4385 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4387 = _T_4386 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4388 = _T_4387 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4389 = _T_4388 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4390 = _T_4389 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4391 = _T_4369 | _T_4390; // @[dec_dec_ctl.scala 264:112] + wire _T_4403 = _T_937 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_4404 = _T_4403 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_4405 = _T_4404 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4406 = _T_4405 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4407 = _T_4406 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4408 = _T_4391 | _T_4407; // @[dec_dec_ctl.scala 265:43] + wire _T_4417 = _T_279 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_4418 = _T_4417 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4419 = _T_4418 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_4420 = _T_4419 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4421 = _T_4420 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + assign io_out_clz = _T_1808 & _T_194; // @[dec_dec_ctl.scala 144:14] + assign io_out_ctz = _T_1836 & _T_194; // @[dec_dec_ctl.scala 146:14] + assign io_out_pcnt = _T_1861 & _T_194; // @[dec_dec_ctl.scala 148:15] + assign io_out_sext_b = _T_1886 & _T_194; // @[dec_dec_ctl.scala 150:17] + assign io_out_sext_h = _T_1910 & _T_194; // @[dec_dec_ctl.scala 152:17] + assign io_out_slo = _T_1933 & _T_194; // @[dec_dec_ctl.scala 154:14] + assign io_out_sro = _T_1955 & _T_194; // @[dec_dec_ctl.scala 156:14] + assign io_out_min = _T_1971 & _T_194; // @[dec_dec_ctl.scala 158:14] + assign io_out_max = _T_1986 & _T_194; // @[dec_dec_ctl.scala 160:14] + assign io_out_pack = _T_2006 & _T_194; // @[dec_dec_ctl.scala 162:15] + assign io_out_packu = _T_2022 & _T_194; // @[dec_dec_ctl.scala 164:16] + assign io_out_packh = _T_2041 & _T_194; // @[dec_dec_ctl.scala 166:16] + assign io_out_rol = _T_2060 & _T_194; // @[dec_dec_ctl.scala 168:14] + assign io_out_ror = _T_2081 & _T_194; // @[dec_dec_ctl.scala 170:14] + assign io_out_grev = _T_2625 & _T_194; // @[dec_dec_ctl.scala 204:15] + assign io_out_gorc = _T_2646 & _T_194; // @[dec_dec_ctl.scala 206:15] + assign io_out_zbb = _T_2342 | _T_526; // @[dec_dec_ctl.scala 172:14] + assign io_out_sbset = _T_2377 & _T_194; // @[dec_dec_ctl.scala 180:16] + assign io_out_sbclr = _T_2397 & _T_194; // @[dec_dec_ctl.scala 182:16] + assign io_out_sbinv = _T_2418 & _T_194; // @[dec_dec_ctl.scala 184:16] + assign io_out_sbext = _T_2439 & _T_194; // @[dec_dec_ctl.scala 186:16] + assign io_out_zbs = _T_2459 | _T_2478; // @[dec_dec_ctl.scala 188:14] + assign io_out_bext = _T_2500 & _T_194; // @[dec_dec_ctl.scala 190:15] + assign io_out_bdep = _T_2518 & _T_194; // @[dec_dec_ctl.scala 192:15] + assign io_out_zbe = _T_1445 & _T_194; // @[dec_dec_ctl.scala 194:14] + assign io_out_clmul = _T_2556 & _T_194; // @[dec_dec_ctl.scala 196:16] + assign io_out_clmulh = _T_2572 & _T_194; // @[dec_dec_ctl.scala 198:17] + assign io_out_clmulr = _T_2589 & _T_194; // @[dec_dec_ctl.scala 200:17] + assign io_out_zbc = _T_2605 & _T_194; // @[dec_dec_ctl.scala 202:14] + assign io_out_shfl = _T_2672 & _T_194; // @[dec_dec_ctl.scala 208:15] + assign io_out_unshfl = _T_2697 & _T_194; // @[dec_dec_ctl.scala 210:17] + assign io_out_zbp = _T_2831 | _T_2847; // @[dec_dec_ctl.scala 212:14] + assign io_out_crc32_b = _T_2878 & _T_194; // @[dec_dec_ctl.scala 217:18] + assign io_out_crc32_h = _T_2905 & _T_194; // @[dec_dec_ctl.scala 219:18] + assign io_out_crc32_w = _T_2932 & _T_194; // @[dec_dec_ctl.scala 221:18] + assign io_out_crc32c_b = _T_2960 & _T_194; // @[dec_dec_ctl.scala 223:19] + assign io_out_crc32c_h = _T_2984 & _T_194; // @[dec_dec_ctl.scala 225:19] + assign io_out_crc32c_w = _T_3008 & _T_194; // @[dec_dec_ctl.scala 227:19] + assign io_out_zbr = _T_1641 & _T_194; // @[dec_dec_ctl.scala 229:14] + assign io_out_bfp = _T_3045 & _T_194; // @[dec_dec_ctl.scala 231:14] + assign io_out_zbf = _T_3045 & _T_194; // @[dec_dec_ctl.scala 233:14] + assign io_out_sh1add = _T_3077 & _T_194; // @[dec_dec_ctl.scala 235:17] + assign io_out_sh2add = _T_3093 & _T_194; // @[dec_dec_ctl.scala 237:17] + assign io_out_sh3add = _T_3106 & _T_194; // @[dec_dec_ctl.scala 239:17] + assign io_out_zba = _T_3120 & _T_194; // @[dec_dec_ctl.scala 241:14] + assign io_out_alu = _T_166 | _T_187; // @[dec_dec_ctl.scala 20:14] + assign io_out_rs1 = _T_277 | _T_282; // @[dec_dec_ctl.scala 27:14] + assign io_out_rs2 = _T_290 | _T_297; // @[dec_dec_ctl.scala 32:14] + assign io_out_imm12 = _T_325 | _T_335; // @[dec_dec_ctl.scala 34:16] + assign io_out_rd = _T_345 | io_ins[4]; // @[dec_dec_ctl.scala 36:13] + assign io_out_shimm5 = _T_377 | _T_391; // @[dec_dec_ctl.scala 38:17] + assign io_out_imm20 = _T_395 | _T_398; // @[dec_dec_ctl.scala 40:16] + assign io_out_pc = _T_406 | _T_395; // @[dec_dec_ctl.scala 42:13] + assign io_out_load = _T_417 & _T_194; // @[dec_dec_ctl.scala 44:15] + assign io_out_store = _T_296 & _T_273; // @[dec_dec_ctl.scala 46:16] + assign io_out_lsu = _T_432 & _T_194; // @[dec_dec_ctl.scala 48:14] + assign io_out_add = _T_454 | _T_476; // @[dec_dec_ctl.scala 50:14] + assign io_out_sub = _T_540 | _T_547; // @[dec_dec_ctl.scala 52:14] + assign io_out_land = _T_565 | _T_576; // @[dec_dec_ctl.scala 55:15] + assign io_out_lor = _T_619 | _T_631; // @[dec_dec_ctl.scala 57:14] + assign io_out_lxor = _T_653 | _T_668; // @[dec_dec_ctl.scala 60:15] + assign io_out_sll = _T_692 & _T_194; // @[dec_dec_ctl.scala 62:14] + assign io_out_sra = _T_712 & _T_194; // @[dec_dec_ctl.scala 64:14] + assign io_out_srl = _T_738 & _T_194; // @[dec_dec_ctl.scala 66:14] + assign io_out_slt = _T_512 | _T_539; // @[dec_dec_ctl.scala 68:14] + assign io_out_unsign = _T_833 | _T_848; // @[dec_dec_ctl.scala 70:17] + assign io_out_condbr = _T_546 & _T_194; // @[dec_dec_ctl.scala 74:17] + assign io_out_beq = _T_868 & _T_194; // @[dec_dec_ctl.scala 76:14] + assign io_out_bne = _T_880 & _T_194; // @[dec_dec_ctl.scala 78:14] + assign io_out_bge = _T_891 & _T_194; // @[dec_dec_ctl.scala 80:14] + assign io_out_blt = _T_903 & _T_194; // @[dec_dec_ctl.scala 82:14] + assign io_out_jal = io_ins[6] & io_ins[2]; // @[dec_dec_ctl.scala 84:14] + assign io_out_by = _T_920 & _T_194; // @[dec_dec_ctl.scala 86:13] + assign io_out_half = _T_930 & _T_194; // @[dec_dec_ctl.scala 88:15] + assign io_out_word = _T_937 & _T_273; // @[dec_dec_ctl.scala 90:15] + assign io_out_csr_read = _T_967 | _T_972; // @[dec_dec_ctl.scala 92:19] + assign io_out_csr_clr = _T_1012 | _T_1021; // @[dec_dec_ctl.scala 95:18] + assign io_out_csr_set = _T_1057 | _T_1065; // @[dec_dec_ctl.scala 98:18] + assign io_out_csr_write = _T_1073 & io_ins[4]; // @[dec_dec_ctl.scala 101:20] + assign io_out_csr_imm = _T_1114 | _T_1121; // @[dec_dec_ctl.scala 103:18] + assign io_out_presync = _T_1203 | _T_1210; // @[dec_dec_ctl.scala 106:18] + assign io_out_postsync = _T_1307 | _T_1210; // @[dec_dec_ctl.scala 111:19] + assign io_out_ebreak = _T_1328 & io_ins[4]; // @[dec_dec_ctl.scala 116:17] + assign io_out_ecall = _T_1343 & io_ins[4]; // @[dec_dec_ctl.scala 118:16] + assign io_out_mret = _T_1354 & io_ins[4]; // @[dec_dec_ctl.scala 120:15] + assign io_out_mul = _T_1643 | _T_1656; // @[dec_dec_ctl.scala 122:14] + assign io_out_rs1_sign = _T_1679 | _T_1699; // @[dec_dec_ctl.scala 130:19] + assign io_out_rs2_sign = _T_1698 & _T_194; // @[dec_dec_ctl.scala 132:19] + assign io_out_low = _T_1736 & _T_194; // @[dec_dec_ctl.scala 134:14] + assign io_out_div = _T_1750 & _T_194; // @[dec_dec_ctl.scala 136:14] + assign io_out_rem = _T_1766 & _T_194; // @[dec_dec_ctl.scala 138:14] + assign io_out_fence = _T_11 & io_ins[3]; // @[dec_dec_ctl.scala 140:16] + assign io_out_fence_i = _T_1216 & io_ins[3]; // @[dec_dec_ctl.scala 142:18] + assign io_out_pm_alu = _T_3196 | _T_122; // @[dec_dec_ctl.scala 243:17] + assign io_out_legal = _T_4408 | _T_4421; // @[dec_dec_ctl.scala 248:16] +endmodule diff --git a/dec_decode_ctl.anno.json b/dec_decode_ctl.anno.json new file mode 100644 index 00000000..1919af8c --- /dev/null +++ b/dec_decode_ctl.anno.json @@ -0,0 +1,2118 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_decode_exu_mul_p_bits_clmulr", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_instr_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_start_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + 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"~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_decode_exu_i0_ap_sh3add", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_instr_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_start_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_dec_csr_rdaddr_d", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_instr_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_csr_any_unq_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_ib0_valid_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_debug_fence_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_start_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_lsu_p_bits_store_data_bypass_m", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_decode_exu_dec_extint_stall" + ] + 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"~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_decode_exu_mul_p_bits_unshfl", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_instr_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_start_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + 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"~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_instr_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_start_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_decode_exu_mul_p_valid", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_dec_csr_legal_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_ib0_valid_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_tlu_flush_lower_r", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + 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"~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_dec_tlu_packet_r_icaf_type", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_dec_tlu_flush_lower_wb" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_decode_exu_mul_p_bits_crc32c_h", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_instr_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_start_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + 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"~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_decode_exu_dec_i0_rs1_en_d", + "~dec_decode_ctl|dec_decode_ctl>io_div_waddr_wb", + "~dec_decode_ctl|dec_decode_ctl>io_decode_exu_dec_i0_rs2_en_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist", + "~dec_decode_ctl|dec_decode_ctl>io_dec_tlu_debug_stall", + "~dec_decode_ctl|dec_decode_ctl>io_dec_tlu_pipelining_disable", + "~dec_decode_ctl|dec_decode_ctl>io_dctl_busbuff_lsu_nonblock_load_valid_m", + "~dec_decode_ctl|dec_decode_ctl>io_decode_exu_dec_extint_stall", + "~dec_decode_ctl|dec_decode_ctl>io_dbg_dctl_dbg_cmd_wrdata", + "~dec_decode_ctl|dec_decode_ctl>io_dec_tlu_presync_d", + "~dec_decode_ctl|dec_decode_ctl>io_dctl_busbuff_lsu_nonblock_load_data_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dctl_busbuff_lsu_nonblock_load_data_error", + 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"~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_decode_exu_i0_ap_sbext", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_instr_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_start_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_decode_exu_i0_ap_predict_t", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_instr_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_start_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_decode_exu_i0_ap_land", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_instr_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_start_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + 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"~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_dec_alu_dec_i0_alu_decode_d", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_dec_csr_legal_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_ib0_valid_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_tlu_flush_lower_r", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_instr_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_div_active", + "~dec_decode_ctl|dec_decode_ctl>io_dec_debug_fence_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_start_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + 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"~dec_decode_ctl|dec_decode_ctl>io_dctl_busbuff_lsu_nonblock_load_data_tag" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_decode_exu_dec_data_en", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_clk_override", + "~dec_decode_ctl|dec_decode_ctl>io_dec_aln_dec_i0_decode_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_ib0_valid_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_tlu_flush_lower_r", + "~dec_decode_ctl|dec_decode_ctl>io_lsu_load_stall_any", + "~dec_decode_ctl|dec_decode_ctl>io_dctl_dma_dma_dccm_stall_any", + "~dec_decode_ctl|dec_decode_ctl>io_dec_div_active", + "~dec_decode_ctl|dec_decode_ctl>io_lsu_store_stall_any", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_instr_d", + "~dec_decode_ctl|dec_decode_ctl>io_decode_exu_dec_i0_rs1_en_d", + "~dec_decode_ctl|dec_decode_ctl>io_div_waddr_wb", + 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"~dec_decode_ctl|dec_decode_ctl>io_dctl_busbuff_lsu_nonblock_load_data_error", + "~dec_decode_ctl|dec_decode_ctl>io_dctl_busbuff_lsu_nonblock_load_data_tag" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_dec_tlu_packet_r_pmu_lsu_misaligned", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_dec_tlu_flush_lower_wb" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_dec_lsu_offset_d", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_instr_d", + "~dec_decode_ctl|dec_decode_ctl>io_decode_exu_dec_extint_stall", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_start_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_lsu_p_bits_store_data_bypass_d", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_decode_exu_dec_extint_stall", + "~dec_decode_ctl|dec_decode_ctl>io_decode_exu_dec_i0_rs2_en_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_instr_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_start_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + 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"~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_decode_exu_i0_ap_sh2add", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_instr_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_start_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_decode_exu_i0_ap_sh1add", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_instr_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_start_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_decode_exu_dec_i0_predict_p_d_bits_pcall", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_instr_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_start_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_decode_exu_i0_ap_ror", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_instr_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_start_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_decode_exu_mul_p_bits_crc32_h", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_instr_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_start_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_decode_ctl|dec_decode_ctl>io_dec_csr_wen_unq_d", + "sources":[ + "~dec_decode_ctl|dec_decode_ctl>io_dec_ib0_valid_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_debug_fence_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_icaf_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_dbecc_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_instr_d", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_start_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_br_error", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_ret", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_toffset", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_valid", + "~dec_decode_ctl|dec_decode_ctl>io_dec_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"dec_decode_ctl.gated_latch", + "resourceId":"/vsrc/gated_latch.sv" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"dec_decode_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/dec_decode_ctl.fir b/dec_decode_ctl.fir new file mode 100644 index 00000000..6f5fea39 --- /dev/null +++ b/dec_decode_ctl.fir @@ -0,0 +1,7729 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit dec_decode_ctl : + module dec_dec_ctl : + input clock : Clock + input reset : Reset + output io : {flip ins : UInt<32>, out : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, zbs : UInt<1>, bext : UInt<1>, bdep : UInt<1>, zbe : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, zbc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, zbp : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, zbr : UInt<1>, bfp : UInt<1>, zbf : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>}} + + node _T = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_3 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_4 = eq(_T_3, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_5 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_6 = eq(_T_5, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_7 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_8 = eq(_T_7, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_9 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_10 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_11 = eq(_T_10, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_12 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_13 = and(_T, _T_1) @[dec_dec_ctl.scala 17:17] + node _T_14 = and(_T_13, _T_2) @[dec_dec_ctl.scala 17:17] + node _T_15 = and(_T_14, _T_4) @[dec_dec_ctl.scala 17:17] + node _T_16 = and(_T_15, _T_6) @[dec_dec_ctl.scala 17:17] + node _T_17 = and(_T_16, _T_8) @[dec_dec_ctl.scala 17:17] + node _T_18 = and(_T_17, _T_9) @[dec_dec_ctl.scala 17:17] + node _T_19 = and(_T_18, _T_11) @[dec_dec_ctl.scala 17:17] + node _T_20 = and(_T_19, _T_12) @[dec_dec_ctl.scala 17:17] + node _T_21 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_22 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_23 = eq(_T_22, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_24 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_25 = eq(_T_24, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_26 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_27 = and(_T_21, _T_23) @[dec_dec_ctl.scala 17:17] + node _T_28 = and(_T_27, _T_25) @[dec_dec_ctl.scala 17:17] + node _T_29 = and(_T_28, _T_26) @[dec_dec_ctl.scala 17:17] + node _T_30 = or(_T_20, _T_29) @[dec_dec_ctl.scala 20:62] + node _T_31 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_32 = eq(_T_31, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_33 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_34 = eq(_T_33, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_35 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_36 = eq(_T_35, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_37 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_38 = and(_T_32, _T_34) @[dec_dec_ctl.scala 17:17] + node _T_39 = and(_T_38, _T_36) @[dec_dec_ctl.scala 17:17] + node _T_40 = and(_T_39, _T_37) @[dec_dec_ctl.scala 17:17] + node _T_41 = or(_T_30, _T_40) @[dec_dec_ctl.scala 20:92] + node _T_42 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_43 = eq(_T_42, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_44 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_45 = eq(_T_44, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_46 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_47 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_48 = and(_T_43, _T_45) @[dec_dec_ctl.scala 17:17] + node _T_49 = and(_T_48, _T_46) @[dec_dec_ctl.scala 17:17] + node _T_50 = and(_T_49, _T_47) @[dec_dec_ctl.scala 17:17] + node _T_51 = or(_T_41, _T_50) @[dec_dec_ctl.scala 21:34] + node _T_52 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_53 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_54 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_55 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_56 = and(_T_52, _T_53) @[dec_dec_ctl.scala 17:17] + node _T_57 = and(_T_56, _T_54) @[dec_dec_ctl.scala 17:17] + node _T_58 = and(_T_57, _T_55) @[dec_dec_ctl.scala 17:17] + node _T_59 = or(_T_51, _T_58) @[dec_dec_ctl.scala 21:66] + node _T_60 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_61 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_62 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_63 = eq(_T_62, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_64 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_65 = and(_T_60, _T_61) @[dec_dec_ctl.scala 17:17] + node _T_66 = and(_T_65, _T_63) @[dec_dec_ctl.scala 17:17] + node _T_67 = and(_T_66, _T_64) @[dec_dec_ctl.scala 17:17] + node _T_68 = or(_T_59, _T_67) @[dec_dec_ctl.scala 21:94] + node _T_69 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_70 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_71 = eq(_T_70, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_72 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_73 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_74 = and(_T_69, _T_71) @[dec_dec_ctl.scala 17:17] + node _T_75 = and(_T_74, _T_72) @[dec_dec_ctl.scala 17:17] + node _T_76 = and(_T_75, _T_73) @[dec_dec_ctl.scala 17:17] + node _T_77 = or(_T_68, _T_76) @[dec_dec_ctl.scala 22:32] + node _T_78 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_79 = eq(_T_78, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_80 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_81 = eq(_T_80, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_82 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_83 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_84 = and(_T_79, _T_81) @[dec_dec_ctl.scala 17:17] + node _T_85 = and(_T_84, _T_82) @[dec_dec_ctl.scala 17:17] + node _T_86 = and(_T_85, _T_83) @[dec_dec_ctl.scala 17:17] + node _T_87 = or(_T_77, _T_86) @[dec_dec_ctl.scala 22:60] + node _T_88 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_89 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_90 = eq(_T_89, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_91 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_93 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_94 = and(_T_88, _T_90) @[dec_dec_ctl.scala 17:17] + node _T_95 = and(_T_94, _T_92) @[dec_dec_ctl.scala 17:17] + node _T_96 = and(_T_95, _T_93) @[dec_dec_ctl.scala 17:17] + node _T_97 = or(_T_87, _T_96) @[dec_dec_ctl.scala 22:90] + node _T_98 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_99 = eq(_T_98, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_100 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_101 = eq(_T_100, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_102 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_104 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_105 = and(_T_99, _T_101) @[dec_dec_ctl.scala 17:17] + node _T_106 = and(_T_105, _T_103) @[dec_dec_ctl.scala 17:17] + node _T_107 = and(_T_106, _T_104) @[dec_dec_ctl.scala 17:17] + node _T_108 = or(_T_97, _T_107) @[dec_dec_ctl.scala 23:33] + node _T_109 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_110 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_111 = eq(_T_110, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_112 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_113 = and(_T_109, _T_111) @[dec_dec_ctl.scala 17:17] + node _T_114 = and(_T_113, _T_112) @[dec_dec_ctl.scala 17:17] + node _T_115 = or(_T_108, _T_114) @[dec_dec_ctl.scala 23:64] + node _T_116 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_117 = eq(_T_116, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_118 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_119 = eq(_T_118, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_120 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_121 = and(_T_117, _T_119) @[dec_dec_ctl.scala 17:17] + node _T_122 = and(_T_121, _T_120) @[dec_dec_ctl.scala 17:17] + node _T_123 = or(_T_115, _T_122) @[dec_dec_ctl.scala 23:89] + node _T_124 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_125 = or(_T_123, _T_124) @[dec_dec_ctl.scala 24:29] + node _T_126 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_127 = or(_T_125, _T_126) @[dec_dec_ctl.scala 24:48] + node _T_128 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_129 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_130 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_131 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_132 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_133 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_134 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_135 = eq(_T_134, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_136 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_137 = and(_T_128, _T_129) @[dec_dec_ctl.scala 17:17] + node _T_138 = and(_T_137, _T_130) @[dec_dec_ctl.scala 17:17] + node _T_139 = and(_T_138, _T_131) @[dec_dec_ctl.scala 17:17] + node _T_140 = and(_T_139, _T_132) @[dec_dec_ctl.scala 17:17] + node _T_141 = and(_T_140, _T_133) @[dec_dec_ctl.scala 17:17] + node _T_142 = and(_T_141, _T_135) @[dec_dec_ctl.scala 17:17] + node _T_143 = and(_T_142, _T_136) @[dec_dec_ctl.scala 17:17] + node _T_144 = or(_T_127, _T_143) @[dec_dec_ctl.scala 24:67] + node _T_145 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_147 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_148 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_149 = eq(_T_148, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_150 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_152 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_153 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_154 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_155 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_156 = eq(_T_155, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_157 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_158 = and(_T_146, _T_147) @[dec_dec_ctl.scala 17:17] + node _T_159 = and(_T_158, _T_149) @[dec_dec_ctl.scala 17:17] + node _T_160 = and(_T_159, _T_151) @[dec_dec_ctl.scala 17:17] + node _T_161 = and(_T_160, _T_152) @[dec_dec_ctl.scala 17:17] + node _T_162 = and(_T_161, _T_153) @[dec_dec_ctl.scala 17:17] + node _T_163 = and(_T_162, _T_154) @[dec_dec_ctl.scala 17:17] + node _T_164 = and(_T_163, _T_156) @[dec_dec_ctl.scala 17:17] + node _T_165 = and(_T_164, _T_157) @[dec_dec_ctl.scala 17:17] + node _T_166 = or(_T_144, _T_165) @[dec_dec_ctl.scala 24:107] + node _T_167 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_169 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_170 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_172 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_173 = eq(_T_172, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_174 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_175 = eq(_T_174, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_176 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_177 = eq(_T_176, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_178 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_180 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_181 = and(_T_168, _T_169) @[dec_dec_ctl.scala 17:17] + node _T_182 = and(_T_181, _T_171) @[dec_dec_ctl.scala 17:17] + node _T_183 = and(_T_182, _T_173) @[dec_dec_ctl.scala 17:17] + node _T_184 = and(_T_183, _T_175) @[dec_dec_ctl.scala 17:17] + node _T_185 = and(_T_184, _T_177) @[dec_dec_ctl.scala 17:17] + node _T_186 = and(_T_185, _T_179) @[dec_dec_ctl.scala 17:17] + node _T_187 = and(_T_186, _T_180) @[dec_dec_ctl.scala 17:17] + node _T_188 = or(_T_166, _T_187) @[dec_dec_ctl.scala 25:49] + io.out.alu <= _T_188 @[dec_dec_ctl.scala 20:14] + node _T_189 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_190 = eq(_T_189, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_191 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_192 = eq(_T_191, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_193 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_194 = eq(_T_193, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_195 = and(_T_190, _T_192) @[dec_dec_ctl.scala 17:17] + node _T_196 = and(_T_195, _T_194) @[dec_dec_ctl.scala 17:17] + node _T_197 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_198 = eq(_T_197, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_199 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34] + node _T_200 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_201 = eq(_T_200, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_202 = and(_T_198, _T_199) @[dec_dec_ctl.scala 17:17] + node _T_203 = and(_T_202, _T_201) @[dec_dec_ctl.scala 17:17] + node _T_204 = or(_T_196, _T_203) @[dec_dec_ctl.scala 27:43] + node _T_205 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34] + node _T_206 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_207 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_208 = eq(_T_207, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_209 = and(_T_205, _T_206) @[dec_dec_ctl.scala 17:17] + node _T_210 = and(_T_209, _T_208) @[dec_dec_ctl.scala 17:17] + node _T_211 = or(_T_204, _T_210) @[dec_dec_ctl.scala 27:70] + node _T_212 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_213 = eq(_T_212, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_214 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34] + node _T_215 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_217 = and(_T_213, _T_214) @[dec_dec_ctl.scala 17:17] + node _T_218 = and(_T_217, _T_216) @[dec_dec_ctl.scala 17:17] + node _T_219 = or(_T_211, _T_218) @[dec_dec_ctl.scala 27:96] + node _T_220 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34] + node _T_221 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_222 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_223 = eq(_T_222, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_224 = and(_T_220, _T_221) @[dec_dec_ctl.scala 17:17] + node _T_225 = and(_T_224, _T_223) @[dec_dec_ctl.scala 17:17] + node _T_226 = or(_T_219, _T_225) @[dec_dec_ctl.scala 28:30] + node _T_227 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_228 = eq(_T_227, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_229 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34] + node _T_230 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_231 = eq(_T_230, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_232 = and(_T_228, _T_229) @[dec_dec_ctl.scala 17:17] + node _T_233 = and(_T_232, _T_231) @[dec_dec_ctl.scala 17:17] + node _T_234 = or(_T_226, _T_233) @[dec_dec_ctl.scala 28:57] + node _T_235 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34] + node _T_236 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_237 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_238 = eq(_T_237, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_239 = and(_T_235, _T_236) @[dec_dec_ctl.scala 17:17] + node _T_240 = and(_T_239, _T_238) @[dec_dec_ctl.scala 17:17] + node _T_241 = or(_T_234, _T_240) @[dec_dec_ctl.scala 28:83] + node _T_242 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_243 = eq(_T_242, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_244 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34] + node _T_245 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_246 = eq(_T_245, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_247 = and(_T_243, _T_244) @[dec_dec_ctl.scala 17:17] + node _T_248 = and(_T_247, _T_246) @[dec_dec_ctl.scala 17:17] + node _T_249 = or(_T_241, _T_248) @[dec_dec_ctl.scala 28:109] + node _T_250 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34] + node _T_251 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_252 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_254 = and(_T_250, _T_251) @[dec_dec_ctl.scala 17:17] + node _T_255 = and(_T_254, _T_253) @[dec_dec_ctl.scala 17:17] + node _T_256 = or(_T_249, _T_255) @[dec_dec_ctl.scala 29:29] + node _T_257 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_258 = eq(_T_257, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_259 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34] + node _T_260 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_261 = eq(_T_260, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_262 = and(_T_258, _T_259) @[dec_dec_ctl.scala 17:17] + node _T_263 = and(_T_262, _T_261) @[dec_dec_ctl.scala 17:17] + node _T_264 = or(_T_256, _T_263) @[dec_dec_ctl.scala 29:55] + node _T_265 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34] + node _T_266 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_267 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_268 = eq(_T_267, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_269 = and(_T_265, _T_266) @[dec_dec_ctl.scala 17:17] + node _T_270 = and(_T_269, _T_268) @[dec_dec_ctl.scala 17:17] + node _T_271 = or(_T_264, _T_270) @[dec_dec_ctl.scala 29:81] + node _T_272 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_274 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_275 = eq(_T_274, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_276 = and(_T_273, _T_275) @[dec_dec_ctl.scala 17:17] + node _T_277 = or(_T_271, _T_276) @[dec_dec_ctl.scala 30:29] + node _T_278 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_279 = eq(_T_278, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_280 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_281 = eq(_T_280, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_282 = and(_T_279, _T_281) @[dec_dec_ctl.scala 17:17] + node _T_283 = or(_T_277, _T_282) @[dec_dec_ctl.scala 30:52] + io.out.rs1 <= _T_283 @[dec_dec_ctl.scala 27:14] + node _T_284 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_285 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_286 = eq(_T_285, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_287 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_288 = eq(_T_287, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_289 = and(_T_284, _T_286) @[dec_dec_ctl.scala 17:17] + node _T_290 = and(_T_289, _T_288) @[dec_dec_ctl.scala 17:17] + node _T_291 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_292 = eq(_T_291, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_293 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_294 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_295 = eq(_T_294, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_296 = and(_T_292, _T_293) @[dec_dec_ctl.scala 17:17] + node _T_297 = and(_T_296, _T_295) @[dec_dec_ctl.scala 17:17] + node _T_298 = or(_T_290, _T_297) @[dec_dec_ctl.scala 32:40] + io.out.rs2 <= _T_298 @[dec_dec_ctl.scala 32:14] + node _T_299 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_300 = eq(_T_299, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_301 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_302 = eq(_T_301, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_303 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_304 = and(_T_300, _T_302) @[dec_dec_ctl.scala 17:17] + node _T_305 = and(_T_304, _T_303) @[dec_dec_ctl.scala 17:17] + node _T_306 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_307 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_308 = eq(_T_307, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_309 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_310 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_311 = eq(_T_310, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_312 = and(_T_306, _T_308) @[dec_dec_ctl.scala 17:17] + node _T_313 = and(_T_312, _T_309) @[dec_dec_ctl.scala 17:17] + node _T_314 = and(_T_313, _T_311) @[dec_dec_ctl.scala 17:17] + node _T_315 = or(_T_305, _T_314) @[dec_dec_ctl.scala 34:42] + node _T_316 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_317 = eq(_T_316, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_318 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_319 = eq(_T_318, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_320 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_321 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_322 = and(_T_317, _T_319) @[dec_dec_ctl.scala 17:17] + node _T_323 = and(_T_322, _T_320) @[dec_dec_ctl.scala 17:17] + node _T_324 = and(_T_323, _T_321) @[dec_dec_ctl.scala 17:17] + node _T_325 = or(_T_315, _T_324) @[dec_dec_ctl.scala 34:70] + node _T_326 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_328 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_330 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_331 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_332 = eq(_T_331, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_333 = and(_T_327, _T_329) @[dec_dec_ctl.scala 17:17] + node _T_334 = and(_T_333, _T_330) @[dec_dec_ctl.scala 17:17] + node _T_335 = and(_T_334, _T_332) @[dec_dec_ctl.scala 17:17] + node _T_336 = or(_T_325, _T_335) @[dec_dec_ctl.scala 34:99] + io.out.imm12 <= _T_336 @[dec_dec_ctl.scala 34:16] + node _T_337 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_339 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_340 = eq(_T_339, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_341 = and(_T_338, _T_340) @[dec_dec_ctl.scala 17:17] + node _T_342 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_343 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_344 = and(_T_342, _T_343) @[dec_dec_ctl.scala 17:17] + node _T_345 = or(_T_341, _T_344) @[dec_dec_ctl.scala 36:37] + node _T_346 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_347 = or(_T_345, _T_346) @[dec_dec_ctl.scala 36:58] + io.out.rd <= _T_347 @[dec_dec_ctl.scala 36:13] + node _T_348 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_349 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_350 = eq(_T_349, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_351 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_352 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_354 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_355 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_356 = eq(_T_355, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_357 = and(_T_348, _T_350) @[dec_dec_ctl.scala 17:17] + node _T_358 = and(_T_357, _T_351) @[dec_dec_ctl.scala 17:17] + node _T_359 = and(_T_358, _T_353) @[dec_dec_ctl.scala 17:17] + node _T_360 = and(_T_359, _T_354) @[dec_dec_ctl.scala 17:17] + node _T_361 = and(_T_360, _T_356) @[dec_dec_ctl.scala 17:17] + node _T_362 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_363 = eq(_T_362, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_364 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_365 = eq(_T_364, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_366 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_367 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_369 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_370 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_371 = eq(_T_370, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_372 = and(_T_363, _T_365) @[dec_dec_ctl.scala 17:17] + node _T_373 = and(_T_372, _T_366) @[dec_dec_ctl.scala 17:17] + node _T_374 = and(_T_373, _T_368) @[dec_dec_ctl.scala 17:17] + node _T_375 = and(_T_374, _T_369) @[dec_dec_ctl.scala 17:17] + node _T_376 = and(_T_375, _T_371) @[dec_dec_ctl.scala 17:17] + node _T_377 = or(_T_361, _T_376) @[dec_dec_ctl.scala 38:53] + node _T_378 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_379 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_380 = eq(_T_379, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_381 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_382 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_383 = eq(_T_382, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_384 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_385 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_387 = and(_T_378, _T_380) @[dec_dec_ctl.scala 17:17] + node _T_388 = and(_T_387, _T_381) @[dec_dec_ctl.scala 17:17] + node _T_389 = and(_T_388, _T_383) @[dec_dec_ctl.scala 17:17] + node _T_390 = and(_T_389, _T_384) @[dec_dec_ctl.scala 17:17] + node _T_391 = and(_T_390, _T_386) @[dec_dec_ctl.scala 17:17] + node _T_392 = or(_T_377, _T_391) @[dec_dec_ctl.scala 38:89] + io.out.shimm5 <= _T_392 @[dec_dec_ctl.scala 38:17] + node _T_393 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_394 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_395 = and(_T_393, _T_394) @[dec_dec_ctl.scala 17:17] + node _T_396 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_397 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_398 = and(_T_396, _T_397) @[dec_dec_ctl.scala 17:17] + node _T_399 = or(_T_395, _T_398) @[dec_dec_ctl.scala 40:38] + io.out.imm20 <= _T_399 @[dec_dec_ctl.scala 40:16] + node _T_400 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_401 = eq(_T_400, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_402 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_403 = eq(_T_402, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_404 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_405 = and(_T_401, _T_403) @[dec_dec_ctl.scala 17:17] + node _T_406 = and(_T_405, _T_404) @[dec_dec_ctl.scala 17:17] + node _T_407 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_408 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_409 = and(_T_407, _T_408) @[dec_dec_ctl.scala 17:17] + node _T_410 = or(_T_406, _T_409) @[dec_dec_ctl.scala 42:39] + io.out.pc <= _T_410 @[dec_dec_ctl.scala 42:13] + node _T_411 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_412 = eq(_T_411, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_413 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_414 = eq(_T_413, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_415 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_416 = eq(_T_415, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_417 = and(_T_412, _T_414) @[dec_dec_ctl.scala 17:17] + node _T_418 = and(_T_417, _T_416) @[dec_dec_ctl.scala 17:17] + io.out.load <= _T_418 @[dec_dec_ctl.scala 44:15] + node _T_419 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_420 = eq(_T_419, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_421 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_422 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_424 = and(_T_420, _T_421) @[dec_dec_ctl.scala 17:17] + node _T_425 = and(_T_424, _T_423) @[dec_dec_ctl.scala 17:17] + io.out.store <= _T_425 @[dec_dec_ctl.scala 46:16] + node _T_426 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_427 = eq(_T_426, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_428 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_429 = eq(_T_428, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_430 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_431 = eq(_T_430, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_432 = and(_T_427, _T_429) @[dec_dec_ctl.scala 17:17] + node _T_433 = and(_T_432, _T_431) @[dec_dec_ctl.scala 17:17] + io.out.lsu <= _T_433 @[dec_dec_ctl.scala 48:14] + node _T_434 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_436 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_438 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_439 = eq(_T_438, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_440 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_441 = eq(_T_440, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_442 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_443 = and(_T_435, _T_437) @[dec_dec_ctl.scala 17:17] + node _T_444 = and(_T_443, _T_439) @[dec_dec_ctl.scala 17:17] + node _T_445 = and(_T_444, _T_441) @[dec_dec_ctl.scala 17:17] + node _T_446 = and(_T_445, _T_442) @[dec_dec_ctl.scala 17:17] + node _T_447 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_448 = eq(_T_447, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_449 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_450 = eq(_T_449, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_451 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_452 = and(_T_448, _T_450) @[dec_dec_ctl.scala 17:17] + node _T_453 = and(_T_452, _T_451) @[dec_dec_ctl.scala 17:17] + node _T_454 = or(_T_446, _T_453) @[dec_dec_ctl.scala 50:49] + node _T_455 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_457 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_458 = eq(_T_457, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_459 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_460 = eq(_T_459, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_461 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_462 = eq(_T_461, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_463 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_464 = eq(_T_463, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_465 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_466 = eq(_T_465, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_467 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_468 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_470 = and(_T_456, _T_458) @[dec_dec_ctl.scala 17:17] + node _T_471 = and(_T_470, _T_460) @[dec_dec_ctl.scala 17:17] + node _T_472 = and(_T_471, _T_462) @[dec_dec_ctl.scala 17:17] + node _T_473 = and(_T_472, _T_464) @[dec_dec_ctl.scala 17:17] + node _T_474 = and(_T_473, _T_466) @[dec_dec_ctl.scala 17:17] + node _T_475 = and(_T_474, _T_467) @[dec_dec_ctl.scala 17:17] + node _T_476 = and(_T_475, _T_469) @[dec_dec_ctl.scala 17:17] + node _T_477 = or(_T_454, _T_476) @[dec_dec_ctl.scala 50:74] + io.out.add <= _T_477 @[dec_dec_ctl.scala 50:14] + node _T_478 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_479 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_480 = eq(_T_479, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_481 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_482 = eq(_T_481, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_483 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_485 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_486 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_487 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_489 = and(_T_478, _T_480) @[dec_dec_ctl.scala 17:17] + node _T_490 = and(_T_489, _T_482) @[dec_dec_ctl.scala 17:17] + node _T_491 = and(_T_490, _T_484) @[dec_dec_ctl.scala 17:17] + node _T_492 = and(_T_491, _T_485) @[dec_dec_ctl.scala 17:17] + node _T_493 = and(_T_492, _T_486) @[dec_dec_ctl.scala 17:17] + node _T_494 = and(_T_493, _T_488) @[dec_dec_ctl.scala 17:17] + node _T_495 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_496 = eq(_T_495, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_497 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_498 = eq(_T_497, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_499 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_500 = eq(_T_499, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_501 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_502 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_503 = eq(_T_502, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_504 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_505 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_506 = eq(_T_505, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_507 = and(_T_496, _T_498) @[dec_dec_ctl.scala 17:17] + node _T_508 = and(_T_507, _T_500) @[dec_dec_ctl.scala 17:17] + node _T_509 = and(_T_508, _T_501) @[dec_dec_ctl.scala 17:17] + node _T_510 = and(_T_509, _T_503) @[dec_dec_ctl.scala 17:17] + node _T_511 = and(_T_510, _T_504) @[dec_dec_ctl.scala 17:17] + node _T_512 = and(_T_511, _T_506) @[dec_dec_ctl.scala 17:17] + node _T_513 = or(_T_494, _T_512) @[dec_dec_ctl.scala 52:53] + node _T_514 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_515 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_516 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_517 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_518 = eq(_T_517, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_519 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_520 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_521 = eq(_T_520, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_522 = and(_T_514, _T_515) @[dec_dec_ctl.scala 17:17] + node _T_523 = and(_T_522, _T_516) @[dec_dec_ctl.scala 17:17] + node _T_524 = and(_T_523, _T_518) @[dec_dec_ctl.scala 17:17] + node _T_525 = and(_T_524, _T_519) @[dec_dec_ctl.scala 17:17] + node _T_526 = and(_T_525, _T_521) @[dec_dec_ctl.scala 17:17] + node _T_527 = or(_T_513, _T_526) @[dec_dec_ctl.scala 52:93] + node _T_528 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_529 = eq(_T_528, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_530 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_531 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_533 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_534 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_536 = and(_T_529, _T_530) @[dec_dec_ctl.scala 17:17] + node _T_537 = and(_T_536, _T_532) @[dec_dec_ctl.scala 17:17] + node _T_538 = and(_T_537, _T_533) @[dec_dec_ctl.scala 17:17] + node _T_539 = and(_T_538, _T_535) @[dec_dec_ctl.scala 17:17] + node _T_540 = or(_T_527, _T_539) @[dec_dec_ctl.scala 53:37] + node _T_541 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_542 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_543 = eq(_T_542, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_544 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_545 = eq(_T_544, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_546 = and(_T_541, _T_543) @[dec_dec_ctl.scala 17:17] + node _T_547 = and(_T_546, _T_545) @[dec_dec_ctl.scala 17:17] + node _T_548 = or(_T_540, _T_547) @[dec_dec_ctl.scala 53:69] + io.out.sub <= _T_548 @[dec_dec_ctl.scala 52:14] + node _T_549 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_550 = eq(_T_549, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_551 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_552 = eq(_T_551, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_553 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_554 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_555 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_556 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_557 = eq(_T_556, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_558 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_560 = and(_T_550, _T_552) @[dec_dec_ctl.scala 17:17] + node _T_561 = and(_T_560, _T_553) @[dec_dec_ctl.scala 17:17] + node _T_562 = and(_T_561, _T_554) @[dec_dec_ctl.scala 17:17] + node _T_563 = and(_T_562, _T_555) @[dec_dec_ctl.scala 17:17] + node _T_564 = and(_T_563, _T_557) @[dec_dec_ctl.scala 17:17] + node _T_565 = and(_T_564, _T_559) @[dec_dec_ctl.scala 17:17] + node _T_566 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_567 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_568 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_569 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_570 = eq(_T_569, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_571 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_572 = eq(_T_571, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_573 = and(_T_566, _T_567) @[dec_dec_ctl.scala 17:17] + node _T_574 = and(_T_573, _T_568) @[dec_dec_ctl.scala 17:17] + node _T_575 = and(_T_574, _T_570) @[dec_dec_ctl.scala 17:17] + node _T_576 = and(_T_575, _T_572) @[dec_dec_ctl.scala 17:17] + node _T_577 = or(_T_565, _T_576) @[dec_dec_ctl.scala 55:56] + io.out.land <= _T_577 @[dec_dec_ctl.scala 55:15] + node _T_578 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_579 = eq(_T_578, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_580 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_581 = and(_T_579, _T_580) @[dec_dec_ctl.scala 17:17] + node _T_582 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_583 = eq(_T_582, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_584 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_585 = eq(_T_584, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_586 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_587 = eq(_T_586, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_588 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_589 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_590 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_591 = eq(_T_590, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_592 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_593 = eq(_T_592, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_594 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_595 = eq(_T_594, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_596 = and(_T_583, _T_585) @[dec_dec_ctl.scala 17:17] + node _T_597 = and(_T_596, _T_587) @[dec_dec_ctl.scala 17:17] + node _T_598 = and(_T_597, _T_588) @[dec_dec_ctl.scala 17:17] + node _T_599 = and(_T_598, _T_589) @[dec_dec_ctl.scala 17:17] + node _T_600 = and(_T_599, _T_591) @[dec_dec_ctl.scala 17:17] + node _T_601 = and(_T_600, _T_593) @[dec_dec_ctl.scala 17:17] + node _T_602 = and(_T_601, _T_595) @[dec_dec_ctl.scala 17:17] + node _T_603 = or(_T_581, _T_602) @[dec_dec_ctl.scala 57:37] + node _T_604 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_605 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_606 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_607 = and(_T_604, _T_605) @[dec_dec_ctl.scala 17:17] + node _T_608 = and(_T_607, _T_606) @[dec_dec_ctl.scala 17:17] + node _T_609 = or(_T_603, _T_608) @[dec_dec_ctl.scala 57:82] + node _T_610 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_611 = eq(_T_610, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_612 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_613 = eq(_T_612, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_614 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_615 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_616 = and(_T_611, _T_613) @[dec_dec_ctl.scala 17:17] + node _T_617 = and(_T_616, _T_614) @[dec_dec_ctl.scala 17:17] + node _T_618 = and(_T_617, _T_615) @[dec_dec_ctl.scala 17:17] + node _T_619 = or(_T_609, _T_618) @[dec_dec_ctl.scala 57:105] + node _T_620 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_621 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_622 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_623 = eq(_T_622, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_624 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_625 = eq(_T_624, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_626 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_627 = eq(_T_626, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_628 = and(_T_620, _T_621) @[dec_dec_ctl.scala 17:17] + node _T_629 = and(_T_628, _T_623) @[dec_dec_ctl.scala 17:17] + node _T_630 = and(_T_629, _T_625) @[dec_dec_ctl.scala 17:17] + node _T_631 = and(_T_630, _T_627) @[dec_dec_ctl.scala 17:17] + node _T_632 = or(_T_619, _T_631) @[dec_dec_ctl.scala 58:32] + io.out.lor <= _T_632 @[dec_dec_ctl.scala 57:14] + node _T_633 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_634 = eq(_T_633, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_635 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_636 = eq(_T_635, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_637 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_638 = eq(_T_637, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_639 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_640 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_641 = eq(_T_640, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_642 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_643 = eq(_T_642, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_644 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_645 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_646 = eq(_T_645, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_647 = and(_T_634, _T_636) @[dec_dec_ctl.scala 17:17] + node _T_648 = and(_T_647, _T_638) @[dec_dec_ctl.scala 17:17] + node _T_649 = and(_T_648, _T_639) @[dec_dec_ctl.scala 17:17] + node _T_650 = and(_T_649, _T_641) @[dec_dec_ctl.scala 17:17] + node _T_651 = and(_T_650, _T_643) @[dec_dec_ctl.scala 17:17] + node _T_652 = and(_T_651, _T_644) @[dec_dec_ctl.scala 17:17] + node _T_653 = and(_T_652, _T_646) @[dec_dec_ctl.scala 17:17] + node _T_654 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_655 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_656 = eq(_T_655, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_657 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_658 = eq(_T_657, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_659 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_660 = eq(_T_659, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_661 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_662 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_663 = eq(_T_662, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_664 = and(_T_654, _T_656) @[dec_dec_ctl.scala 17:17] + node _T_665 = and(_T_664, _T_658) @[dec_dec_ctl.scala 17:17] + node _T_666 = and(_T_665, _T_660) @[dec_dec_ctl.scala 17:17] + node _T_667 = and(_T_666, _T_661) @[dec_dec_ctl.scala 17:17] + node _T_668 = and(_T_667, _T_663) @[dec_dec_ctl.scala 17:17] + node _T_669 = or(_T_653, _T_668) @[dec_dec_ctl.scala 60:61] + io.out.lxor <= _T_669 @[dec_dec_ctl.scala 60:15] + node _T_670 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_671 = eq(_T_670, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_672 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_673 = eq(_T_672, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_674 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_675 = eq(_T_674, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_676 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_677 = eq(_T_676, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_678 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_679 = eq(_T_678, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_680 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_681 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_682 = eq(_T_681, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_683 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_684 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_685 = eq(_T_684, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_686 = and(_T_671, _T_673) @[dec_dec_ctl.scala 17:17] + node _T_687 = and(_T_686, _T_675) @[dec_dec_ctl.scala 17:17] + node _T_688 = and(_T_687, _T_677) @[dec_dec_ctl.scala 17:17] + node _T_689 = and(_T_688, _T_679) @[dec_dec_ctl.scala 17:17] + node _T_690 = and(_T_689, _T_680) @[dec_dec_ctl.scala 17:17] + node _T_691 = and(_T_690, _T_682) @[dec_dec_ctl.scala 17:17] + node _T_692 = and(_T_691, _T_683) @[dec_dec_ctl.scala 17:17] + node _T_693 = and(_T_692, _T_685) @[dec_dec_ctl.scala 17:17] + io.out.sll <= _T_693 @[dec_dec_ctl.scala 62:14] + node _T_694 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_695 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_696 = eq(_T_695, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_697 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_698 = eq(_T_697, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_699 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_700 = eq(_T_699, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_701 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_702 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_703 = eq(_T_702, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_704 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_705 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_706 = eq(_T_705, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_707 = and(_T_694, _T_696) @[dec_dec_ctl.scala 17:17] + node _T_708 = and(_T_707, _T_698) @[dec_dec_ctl.scala 17:17] + node _T_709 = and(_T_708, _T_700) @[dec_dec_ctl.scala 17:17] + node _T_710 = and(_T_709, _T_701) @[dec_dec_ctl.scala 17:17] + node _T_711 = and(_T_710, _T_703) @[dec_dec_ctl.scala 17:17] + node _T_712 = and(_T_711, _T_704) @[dec_dec_ctl.scala 17:17] + node _T_713 = and(_T_712, _T_706) @[dec_dec_ctl.scala 17:17] + io.out.sra <= _T_713 @[dec_dec_ctl.scala 64:14] + node _T_714 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_715 = eq(_T_714, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_716 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_717 = eq(_T_716, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_718 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_719 = eq(_T_718, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_720 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_721 = eq(_T_720, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_722 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_723 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_724 = eq(_T_723, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_725 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_726 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_727 = eq(_T_726, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_728 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_729 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_730 = eq(_T_729, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_731 = and(_T_715, _T_717) @[dec_dec_ctl.scala 17:17] + node _T_732 = and(_T_731, _T_719) @[dec_dec_ctl.scala 17:17] + node _T_733 = and(_T_732, _T_721) @[dec_dec_ctl.scala 17:17] + node _T_734 = and(_T_733, _T_722) @[dec_dec_ctl.scala 17:17] + node _T_735 = and(_T_734, _T_724) @[dec_dec_ctl.scala 17:17] + node _T_736 = and(_T_735, _T_725) @[dec_dec_ctl.scala 17:17] + node _T_737 = and(_T_736, _T_727) @[dec_dec_ctl.scala 17:17] + node _T_738 = and(_T_737, _T_728) @[dec_dec_ctl.scala 17:17] + node _T_739 = and(_T_738, _T_730) @[dec_dec_ctl.scala 17:17] + io.out.srl <= _T_739 @[dec_dec_ctl.scala 66:14] + node _T_740 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_741 = eq(_T_740, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_742 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_743 = eq(_T_742, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_744 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_745 = eq(_T_744, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_746 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_747 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_748 = eq(_T_747, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_749 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_750 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_751 = eq(_T_750, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_752 = and(_T_741, _T_743) @[dec_dec_ctl.scala 17:17] + node _T_753 = and(_T_752, _T_745) @[dec_dec_ctl.scala 17:17] + node _T_754 = and(_T_753, _T_746) @[dec_dec_ctl.scala 17:17] + node _T_755 = and(_T_754, _T_748) @[dec_dec_ctl.scala 17:17] + node _T_756 = and(_T_755, _T_749) @[dec_dec_ctl.scala 17:17] + node _T_757 = and(_T_756, _T_751) @[dec_dec_ctl.scala 17:17] + node _T_758 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_759 = eq(_T_758, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_760 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_761 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_762 = eq(_T_761, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_763 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_764 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_765 = eq(_T_764, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_766 = and(_T_759, _T_760) @[dec_dec_ctl.scala 17:17] + node _T_767 = and(_T_766, _T_762) @[dec_dec_ctl.scala 17:17] + node _T_768 = and(_T_767, _T_763) @[dec_dec_ctl.scala 17:17] + node _T_769 = and(_T_768, _T_765) @[dec_dec_ctl.scala 17:17] + node _T_770 = or(_T_757, _T_769) @[dec_dec_ctl.scala 68:55] + io.out.slt <= _T_770 @[dec_dec_ctl.scala 68:14] + node _T_771 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_773 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_774 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_775 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_776 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_778 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_779 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_780 = eq(_T_779, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_781 = and(_T_772, _T_773) @[dec_dec_ctl.scala 17:17] + node _T_782 = and(_T_781, _T_774) @[dec_dec_ctl.scala 17:17] + node _T_783 = and(_T_782, _T_775) @[dec_dec_ctl.scala 17:17] + node _T_784 = and(_T_783, _T_777) @[dec_dec_ctl.scala 17:17] + node _T_785 = and(_T_784, _T_778) @[dec_dec_ctl.scala 17:17] + node _T_786 = and(_T_785, _T_780) @[dec_dec_ctl.scala 17:17] + node _T_787 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_788 = eq(_T_787, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_789 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_790 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_791 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_792 = eq(_T_791, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_793 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_794 = eq(_T_793, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_795 = and(_T_788, _T_789) @[dec_dec_ctl.scala 17:17] + node _T_796 = and(_T_795, _T_790) @[dec_dec_ctl.scala 17:17] + node _T_797 = and(_T_796, _T_792) @[dec_dec_ctl.scala 17:17] + node _T_798 = and(_T_797, _T_794) @[dec_dec_ctl.scala 17:17] + node _T_799 = or(_T_786, _T_798) @[dec_dec_ctl.scala 70:56] + node _T_800 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_801 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_802 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_803 = eq(_T_802, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_804 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_805 = eq(_T_804, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_806 = and(_T_800, _T_801) @[dec_dec_ctl.scala 17:17] + node _T_807 = and(_T_806, _T_803) @[dec_dec_ctl.scala 17:17] + node _T_808 = and(_T_807, _T_805) @[dec_dec_ctl.scala 17:17] + node _T_809 = or(_T_799, _T_808) @[dec_dec_ctl.scala 70:89] + node _T_810 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_811 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_813 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_814 = eq(_T_813, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_815 = and(_T_810, _T_812) @[dec_dec_ctl.scala 17:17] + node _T_816 = and(_T_815, _T_814) @[dec_dec_ctl.scala 17:17] + node _T_817 = or(_T_809, _T_816) @[dec_dec_ctl.scala 71:31] + node _T_818 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_819 = eq(_T_818, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_820 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_821 = eq(_T_820, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_822 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_823 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_824 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_825 = eq(_T_824, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_826 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_827 = eq(_T_826, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_828 = and(_T_819, _T_821) @[dec_dec_ctl.scala 17:17] + node _T_829 = and(_T_828, _T_822) @[dec_dec_ctl.scala 17:17] + node _T_830 = and(_T_829, _T_823) @[dec_dec_ctl.scala 17:17] + node _T_831 = and(_T_830, _T_825) @[dec_dec_ctl.scala 17:17] + node _T_832 = and(_T_831, _T_827) @[dec_dec_ctl.scala 17:17] + node _T_833 = or(_T_817, _T_832) @[dec_dec_ctl.scala 71:57] + node _T_834 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_835 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_836 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_837 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_838 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_840 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_841 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_842 = eq(_T_841, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_843 = and(_T_834, _T_835) @[dec_dec_ctl.scala 17:17] + node _T_844 = and(_T_843, _T_836) @[dec_dec_ctl.scala 17:17] + node _T_845 = and(_T_844, _T_837) @[dec_dec_ctl.scala 17:17] + node _T_846 = and(_T_845, _T_839) @[dec_dec_ctl.scala 17:17] + node _T_847 = and(_T_846, _T_840) @[dec_dec_ctl.scala 17:17] + node _T_848 = and(_T_847, _T_842) @[dec_dec_ctl.scala 17:17] + node _T_849 = or(_T_833, _T_848) @[dec_dec_ctl.scala 71:94] + io.out.unsign <= _T_849 @[dec_dec_ctl.scala 70:17] + node _T_850 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_851 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_852 = eq(_T_851, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_853 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_854 = eq(_T_853, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_855 = and(_T_850, _T_852) @[dec_dec_ctl.scala 17:17] + node _T_856 = and(_T_855, _T_854) @[dec_dec_ctl.scala 17:17] + io.out.condbr <= _T_856 @[dec_dec_ctl.scala 74:17] + node _T_857 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_858 = eq(_T_857, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_859 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_860 = eq(_T_859, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_861 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_862 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_863 = eq(_T_862, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_864 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_865 = eq(_T_864, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_866 = and(_T_858, _T_860) @[dec_dec_ctl.scala 17:17] + node _T_867 = and(_T_866, _T_861) @[dec_dec_ctl.scala 17:17] + node _T_868 = and(_T_867, _T_863) @[dec_dec_ctl.scala 17:17] + node _T_869 = and(_T_868, _T_865) @[dec_dec_ctl.scala 17:17] + io.out.beq <= _T_869 @[dec_dec_ctl.scala 76:14] + node _T_870 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_871 = eq(_T_870, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_872 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_873 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_874 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_875 = eq(_T_874, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_876 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_877 = eq(_T_876, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_878 = and(_T_871, _T_872) @[dec_dec_ctl.scala 17:17] + node _T_879 = and(_T_878, _T_873) @[dec_dec_ctl.scala 17:17] + node _T_880 = and(_T_879, _T_875) @[dec_dec_ctl.scala 17:17] + node _T_881 = and(_T_880, _T_877) @[dec_dec_ctl.scala 17:17] + io.out.bne <= _T_881 @[dec_dec_ctl.scala 78:14] + node _T_882 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_883 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_884 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_885 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_886 = eq(_T_885, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_887 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_888 = eq(_T_887, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_889 = and(_T_882, _T_883) @[dec_dec_ctl.scala 17:17] + node _T_890 = and(_T_889, _T_884) @[dec_dec_ctl.scala 17:17] + node _T_891 = and(_T_890, _T_886) @[dec_dec_ctl.scala 17:17] + node _T_892 = and(_T_891, _T_888) @[dec_dec_ctl.scala 17:17] + io.out.bge <= _T_892 @[dec_dec_ctl.scala 80:14] + node _T_893 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_894 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_896 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_897 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_898 = eq(_T_897, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_899 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_900 = eq(_T_899, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_901 = and(_T_893, _T_895) @[dec_dec_ctl.scala 17:17] + node _T_902 = and(_T_901, _T_896) @[dec_dec_ctl.scala 17:17] + node _T_903 = and(_T_902, _T_898) @[dec_dec_ctl.scala 17:17] + node _T_904 = and(_T_903, _T_900) @[dec_dec_ctl.scala 17:17] + io.out.blt <= _T_904 @[dec_dec_ctl.scala 82:14] + node _T_905 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_906 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_907 = and(_T_905, _T_906) @[dec_dec_ctl.scala 17:17] + io.out.jal <= _T_907 @[dec_dec_ctl.scala 84:14] + node _T_908 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_909 = eq(_T_908, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_910 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_911 = eq(_T_910, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_912 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_913 = eq(_T_912, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_914 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_915 = eq(_T_914, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_916 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_917 = eq(_T_916, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_918 = and(_T_909, _T_911) @[dec_dec_ctl.scala 17:17] + node _T_919 = and(_T_918, _T_913) @[dec_dec_ctl.scala 17:17] + node _T_920 = and(_T_919, _T_915) @[dec_dec_ctl.scala 17:17] + node _T_921 = and(_T_920, _T_917) @[dec_dec_ctl.scala 17:17] + io.out.by <= _T_921 @[dec_dec_ctl.scala 86:13] + node _T_922 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_923 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_924 = eq(_T_923, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_925 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_926 = eq(_T_925, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_927 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_928 = eq(_T_927, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_929 = and(_T_922, _T_924) @[dec_dec_ctl.scala 17:17] + node _T_930 = and(_T_929, _T_926) @[dec_dec_ctl.scala 17:17] + node _T_931 = and(_T_930, _T_928) @[dec_dec_ctl.scala 17:17] + io.out.half <= _T_931 @[dec_dec_ctl.scala 88:15] + node _T_932 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_933 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_934 = eq(_T_933, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_935 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_936 = eq(_T_935, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_937 = and(_T_932, _T_934) @[dec_dec_ctl.scala 17:17] + node _T_938 = and(_T_937, _T_936) @[dec_dec_ctl.scala 17:17] + io.out.word <= _T_938 @[dec_dec_ctl.scala 90:15] + node _T_939 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_940 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_941 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_942 = and(_T_939, _T_940) @[dec_dec_ctl.scala 17:17] + node _T_943 = and(_T_942, _T_941) @[dec_dec_ctl.scala 17:17] + node _T_944 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34] + node _T_945 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_946 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_947 = and(_T_944, _T_945) @[dec_dec_ctl.scala 17:17] + node _T_948 = and(_T_947, _T_946) @[dec_dec_ctl.scala 17:17] + node _T_949 = or(_T_943, _T_948) @[dec_dec_ctl.scala 92:44] + node _T_950 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34] + node _T_951 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_952 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_953 = and(_T_950, _T_951) @[dec_dec_ctl.scala 17:17] + node _T_954 = and(_T_953, _T_952) @[dec_dec_ctl.scala 17:17] + node _T_955 = or(_T_949, _T_954) @[dec_dec_ctl.scala 92:67] + node _T_956 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34] + node _T_957 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_958 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_959 = and(_T_956, _T_957) @[dec_dec_ctl.scala 17:17] + node _T_960 = and(_T_959, _T_958) @[dec_dec_ctl.scala 17:17] + node _T_961 = or(_T_955, _T_960) @[dec_dec_ctl.scala 92:90] + node _T_962 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34] + node _T_963 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_964 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_965 = and(_T_962, _T_963) @[dec_dec_ctl.scala 17:17] + node _T_966 = and(_T_965, _T_964) @[dec_dec_ctl.scala 17:17] + node _T_967 = or(_T_961, _T_966) @[dec_dec_ctl.scala 93:26] + node _T_968 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34] + node _T_969 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_970 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_971 = and(_T_968, _T_969) @[dec_dec_ctl.scala 17:17] + node _T_972 = and(_T_971, _T_970) @[dec_dec_ctl.scala 17:17] + node _T_973 = or(_T_967, _T_972) @[dec_dec_ctl.scala 93:50] + io.out.csr_read <= _T_973 @[dec_dec_ctl.scala 92:19] + node _T_974 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34] + node _T_975 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_976 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_977 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_978 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_979 = and(_T_974, _T_975) @[dec_dec_ctl.scala 17:17] + node _T_980 = and(_T_979, _T_976) @[dec_dec_ctl.scala 17:17] + node _T_981 = and(_T_980, _T_977) @[dec_dec_ctl.scala 17:17] + node _T_982 = and(_T_981, _T_978) @[dec_dec_ctl.scala 17:17] + node _T_983 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34] + node _T_984 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_985 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_986 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_987 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_988 = and(_T_983, _T_984) @[dec_dec_ctl.scala 17:17] + node _T_989 = and(_T_988, _T_985) @[dec_dec_ctl.scala 17:17] + node _T_990 = and(_T_989, _T_986) @[dec_dec_ctl.scala 17:17] + node _T_991 = and(_T_990, _T_987) @[dec_dec_ctl.scala 17:17] + node _T_992 = or(_T_982, _T_991) @[dec_dec_ctl.scala 95:49] + node _T_993 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34] + node _T_994 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_995 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_996 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_997 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_998 = and(_T_993, _T_994) @[dec_dec_ctl.scala 17:17] + node _T_999 = and(_T_998, _T_995) @[dec_dec_ctl.scala 17:17] + node _T_1000 = and(_T_999, _T_996) @[dec_dec_ctl.scala 17:17] + node _T_1001 = and(_T_1000, _T_997) @[dec_dec_ctl.scala 17:17] + node _T_1002 = or(_T_992, _T_1001) @[dec_dec_ctl.scala 95:79] + node _T_1003 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34] + node _T_1004 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1005 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1006 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1007 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1008 = and(_T_1003, _T_1004) @[dec_dec_ctl.scala 17:17] + node _T_1009 = and(_T_1008, _T_1005) @[dec_dec_ctl.scala 17:17] + node _T_1010 = and(_T_1009, _T_1006) @[dec_dec_ctl.scala 17:17] + node _T_1011 = and(_T_1010, _T_1007) @[dec_dec_ctl.scala 17:17] + node _T_1012 = or(_T_1002, _T_1011) @[dec_dec_ctl.scala 96:33] + node _T_1013 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34] + node _T_1014 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1015 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1016 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1017 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1018 = and(_T_1013, _T_1014) @[dec_dec_ctl.scala 17:17] + node _T_1019 = and(_T_1018, _T_1015) @[dec_dec_ctl.scala 17:17] + node _T_1020 = and(_T_1019, _T_1016) @[dec_dec_ctl.scala 17:17] + node _T_1021 = and(_T_1020, _T_1017) @[dec_dec_ctl.scala 17:17] + node _T_1022 = or(_T_1012, _T_1021) @[dec_dec_ctl.scala 96:63] + io.out.csr_clr <= _T_1022 @[dec_dec_ctl.scala 95:18] + node _T_1023 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34] + node _T_1024 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1026 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1027 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1028 = and(_T_1023, _T_1025) @[dec_dec_ctl.scala 17:17] + node _T_1029 = and(_T_1028, _T_1026) @[dec_dec_ctl.scala 17:17] + node _T_1030 = and(_T_1029, _T_1027) @[dec_dec_ctl.scala 17:17] + node _T_1031 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34] + node _T_1032 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1033 = eq(_T_1032, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1034 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1035 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1036 = and(_T_1031, _T_1033) @[dec_dec_ctl.scala 17:17] + node _T_1037 = and(_T_1036, _T_1034) @[dec_dec_ctl.scala 17:17] + node _T_1038 = and(_T_1037, _T_1035) @[dec_dec_ctl.scala 17:17] + node _T_1039 = or(_T_1030, _T_1038) @[dec_dec_ctl.scala 98:47] + node _T_1040 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34] + node _T_1041 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1042 = eq(_T_1041, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1043 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1044 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1045 = and(_T_1040, _T_1042) @[dec_dec_ctl.scala 17:17] + node _T_1046 = and(_T_1045, _T_1043) @[dec_dec_ctl.scala 17:17] + node _T_1047 = and(_T_1046, _T_1044) @[dec_dec_ctl.scala 17:17] + node _T_1048 = or(_T_1039, _T_1047) @[dec_dec_ctl.scala 98:75] + node _T_1049 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34] + node _T_1050 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1051 = eq(_T_1050, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1052 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1053 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1054 = and(_T_1049, _T_1051) @[dec_dec_ctl.scala 17:17] + node _T_1055 = and(_T_1054, _T_1052) @[dec_dec_ctl.scala 17:17] + node _T_1056 = and(_T_1055, _T_1053) @[dec_dec_ctl.scala 17:17] + node _T_1057 = or(_T_1048, _T_1056) @[dec_dec_ctl.scala 98:103] + node _T_1058 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34] + node _T_1059 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1060 = eq(_T_1059, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1061 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1062 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1063 = and(_T_1058, _T_1060) @[dec_dec_ctl.scala 17:17] + node _T_1064 = and(_T_1063, _T_1061) @[dec_dec_ctl.scala 17:17] + node _T_1065 = and(_T_1064, _T_1062) @[dec_dec_ctl.scala 17:17] + node _T_1066 = or(_T_1057, _T_1065) @[dec_dec_ctl.scala 99:31] + io.out.csr_set <= _T_1066 @[dec_dec_ctl.scala 98:18] + node _T_1067 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1068 = eq(_T_1067, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1069 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1070 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1071 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1072 = and(_T_1068, _T_1069) @[dec_dec_ctl.scala 17:17] + node _T_1073 = and(_T_1072, _T_1070) @[dec_dec_ctl.scala 17:17] + node _T_1074 = and(_T_1073, _T_1071) @[dec_dec_ctl.scala 17:17] + io.out.csr_write <= _T_1074 @[dec_dec_ctl.scala 101:20] + node _T_1075 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1076 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1077 = eq(_T_1076, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1078 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1079 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1080 = and(_T_1075, _T_1077) @[dec_dec_ctl.scala 17:17] + node _T_1081 = and(_T_1080, _T_1078) @[dec_dec_ctl.scala 17:17] + node _T_1082 = and(_T_1081, _T_1079) @[dec_dec_ctl.scala 17:17] + node _T_1083 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34] + node _T_1084 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1085 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1086 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1087 = and(_T_1083, _T_1084) @[dec_dec_ctl.scala 17:17] + node _T_1088 = and(_T_1087, _T_1085) @[dec_dec_ctl.scala 17:17] + node _T_1089 = and(_T_1088, _T_1086) @[dec_dec_ctl.scala 17:17] + node _T_1090 = or(_T_1082, _T_1089) @[dec_dec_ctl.scala 103:47] + node _T_1091 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34] + node _T_1092 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1093 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1094 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1095 = and(_T_1091, _T_1092) @[dec_dec_ctl.scala 17:17] + node _T_1096 = and(_T_1095, _T_1093) @[dec_dec_ctl.scala 17:17] + node _T_1097 = and(_T_1096, _T_1094) @[dec_dec_ctl.scala 17:17] + node _T_1098 = or(_T_1090, _T_1097) @[dec_dec_ctl.scala 103:74] + node _T_1099 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34] + node _T_1100 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1101 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1102 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1103 = and(_T_1099, _T_1100) @[dec_dec_ctl.scala 17:17] + node _T_1104 = and(_T_1103, _T_1101) @[dec_dec_ctl.scala 17:17] + node _T_1105 = and(_T_1104, _T_1102) @[dec_dec_ctl.scala 17:17] + node _T_1106 = or(_T_1098, _T_1105) @[dec_dec_ctl.scala 103:101] + node _T_1107 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34] + node _T_1108 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1109 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1110 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1111 = and(_T_1107, _T_1108) @[dec_dec_ctl.scala 17:17] + node _T_1112 = and(_T_1111, _T_1109) @[dec_dec_ctl.scala 17:17] + node _T_1113 = and(_T_1112, _T_1110) @[dec_dec_ctl.scala 17:17] + node _T_1114 = or(_T_1106, _T_1113) @[dec_dec_ctl.scala 104:30] + node _T_1115 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34] + node _T_1116 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1117 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1118 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1119 = and(_T_1115, _T_1116) @[dec_dec_ctl.scala 17:17] + node _T_1120 = and(_T_1119, _T_1117) @[dec_dec_ctl.scala 17:17] + node _T_1121 = and(_T_1120, _T_1118) @[dec_dec_ctl.scala 17:17] + node _T_1122 = or(_T_1114, _T_1121) @[dec_dec_ctl.scala 104:57] + io.out.csr_imm <= _T_1122 @[dec_dec_ctl.scala 103:18] + node _T_1123 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1124 = eq(_T_1123, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1125 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_1126 = and(_T_1124, _T_1125) @[dec_dec_ctl.scala 17:17] + node _T_1127 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1129 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34] + node _T_1130 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1131 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1132 = and(_T_1128, _T_1129) @[dec_dec_ctl.scala 17:17] + node _T_1133 = and(_T_1132, _T_1130) @[dec_dec_ctl.scala 17:17] + node _T_1134 = and(_T_1133, _T_1131) @[dec_dec_ctl.scala 17:17] + node _T_1135 = or(_T_1126, _T_1134) @[dec_dec_ctl.scala 106:41] + node _T_1136 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1137 = eq(_T_1136, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1138 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34] + node _T_1139 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1140 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1141 = and(_T_1137, _T_1138) @[dec_dec_ctl.scala 17:17] + node _T_1142 = and(_T_1141, _T_1139) @[dec_dec_ctl.scala 17:17] + node _T_1143 = and(_T_1142, _T_1140) @[dec_dec_ctl.scala 17:17] + node _T_1144 = or(_T_1135, _T_1143) @[dec_dec_ctl.scala 106:68] + node _T_1145 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1146 = eq(_T_1145, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1147 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34] + node _T_1148 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1149 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1150 = and(_T_1146, _T_1147) @[dec_dec_ctl.scala 17:17] + node _T_1151 = and(_T_1150, _T_1148) @[dec_dec_ctl.scala 17:17] + node _T_1152 = and(_T_1151, _T_1149) @[dec_dec_ctl.scala 17:17] + node _T_1153 = or(_T_1144, _T_1152) @[dec_dec_ctl.scala 106:95] + node _T_1154 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1155 = eq(_T_1154, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1156 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34] + node _T_1157 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1158 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1159 = and(_T_1155, _T_1156) @[dec_dec_ctl.scala 17:17] + node _T_1160 = and(_T_1159, _T_1157) @[dec_dec_ctl.scala 17:17] + node _T_1161 = and(_T_1160, _T_1158) @[dec_dec_ctl.scala 17:17] + node _T_1162 = or(_T_1153, _T_1161) @[dec_dec_ctl.scala 107:30] + node _T_1163 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1164 = eq(_T_1163, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1165 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34] + node _T_1166 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1167 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1168 = and(_T_1164, _T_1165) @[dec_dec_ctl.scala 17:17] + node _T_1169 = and(_T_1168, _T_1166) @[dec_dec_ctl.scala 17:17] + node _T_1170 = and(_T_1169, _T_1167) @[dec_dec_ctl.scala 17:17] + node _T_1171 = or(_T_1162, _T_1170) @[dec_dec_ctl.scala 107:58] + node _T_1172 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34] + node _T_1173 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1174 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1175 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1176 = and(_T_1172, _T_1173) @[dec_dec_ctl.scala 17:17] + node _T_1177 = and(_T_1176, _T_1174) @[dec_dec_ctl.scala 17:17] + node _T_1178 = and(_T_1177, _T_1175) @[dec_dec_ctl.scala 17:17] + node _T_1179 = or(_T_1171, _T_1178) @[dec_dec_ctl.scala 107:86] + node _T_1180 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34] + node _T_1181 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1182 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1183 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1184 = and(_T_1180, _T_1181) @[dec_dec_ctl.scala 17:17] + node _T_1185 = and(_T_1184, _T_1182) @[dec_dec_ctl.scala 17:17] + node _T_1186 = and(_T_1185, _T_1183) @[dec_dec_ctl.scala 17:17] + node _T_1187 = or(_T_1179, _T_1186) @[dec_dec_ctl.scala 108:30] + node _T_1188 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34] + node _T_1189 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1190 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1191 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1192 = and(_T_1188, _T_1189) @[dec_dec_ctl.scala 17:17] + node _T_1193 = and(_T_1192, _T_1190) @[dec_dec_ctl.scala 17:17] + node _T_1194 = and(_T_1193, _T_1191) @[dec_dec_ctl.scala 17:17] + node _T_1195 = or(_T_1187, _T_1194) @[dec_dec_ctl.scala 108:57] + node _T_1196 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34] + node _T_1197 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1198 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1199 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1200 = and(_T_1196, _T_1197) @[dec_dec_ctl.scala 17:17] + node _T_1201 = and(_T_1200, _T_1198) @[dec_dec_ctl.scala 17:17] + node _T_1202 = and(_T_1201, _T_1199) @[dec_dec_ctl.scala 17:17] + node _T_1203 = or(_T_1195, _T_1202) @[dec_dec_ctl.scala 108:84] + node _T_1204 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34] + node _T_1205 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1206 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1207 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1208 = and(_T_1204, _T_1205) @[dec_dec_ctl.scala 17:17] + node _T_1209 = and(_T_1208, _T_1206) @[dec_dec_ctl.scala 17:17] + node _T_1210 = and(_T_1209, _T_1207) @[dec_dec_ctl.scala 17:17] + node _T_1211 = or(_T_1203, _T_1210) @[dec_dec_ctl.scala 109:30] + io.out.presync <= _T_1211 @[dec_dec_ctl.scala 106:18] + node _T_1212 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1213 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1215 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_1216 = and(_T_1212, _T_1214) @[dec_dec_ctl.scala 17:17] + node _T_1217 = and(_T_1216, _T_1215) @[dec_dec_ctl.scala 17:17] + node _T_1218 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_1219 = eq(_T_1218, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1220 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1221 = eq(_T_1220, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1222 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1223 = eq(_T_1222, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1224 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1225 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1226 = and(_T_1219, _T_1221) @[dec_dec_ctl.scala 17:17] + node _T_1227 = and(_T_1226, _T_1223) @[dec_dec_ctl.scala 17:17] + node _T_1228 = and(_T_1227, _T_1224) @[dec_dec_ctl.scala 17:17] + node _T_1229 = and(_T_1228, _T_1225) @[dec_dec_ctl.scala 17:17] + node _T_1230 = or(_T_1217, _T_1229) @[dec_dec_ctl.scala 111:45] + node _T_1231 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1233 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34] + node _T_1234 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1235 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1236 = and(_T_1232, _T_1233) @[dec_dec_ctl.scala 17:17] + node _T_1237 = and(_T_1236, _T_1234) @[dec_dec_ctl.scala 17:17] + node _T_1238 = and(_T_1237, _T_1235) @[dec_dec_ctl.scala 17:17] + node _T_1239 = or(_T_1230, _T_1238) @[dec_dec_ctl.scala 111:78] + node _T_1240 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1241 = eq(_T_1240, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1242 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34] + node _T_1243 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1244 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1245 = and(_T_1241, _T_1242) @[dec_dec_ctl.scala 17:17] + node _T_1246 = and(_T_1245, _T_1243) @[dec_dec_ctl.scala 17:17] + node _T_1247 = and(_T_1246, _T_1244) @[dec_dec_ctl.scala 17:17] + node _T_1248 = or(_T_1239, _T_1247) @[dec_dec_ctl.scala 112:30] + node _T_1249 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1250 = eq(_T_1249, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1251 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34] + node _T_1252 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1253 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1254 = and(_T_1250, _T_1251) @[dec_dec_ctl.scala 17:17] + node _T_1255 = and(_T_1254, _T_1252) @[dec_dec_ctl.scala 17:17] + node _T_1256 = and(_T_1255, _T_1253) @[dec_dec_ctl.scala 17:17] + node _T_1257 = or(_T_1248, _T_1256) @[dec_dec_ctl.scala 112:57] + node _T_1258 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1259 = eq(_T_1258, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1260 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34] + node _T_1261 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1262 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1263 = and(_T_1259, _T_1260) @[dec_dec_ctl.scala 17:17] + node _T_1264 = and(_T_1263, _T_1261) @[dec_dec_ctl.scala 17:17] + node _T_1265 = and(_T_1264, _T_1262) @[dec_dec_ctl.scala 17:17] + node _T_1266 = or(_T_1257, _T_1265) @[dec_dec_ctl.scala 112:84] + node _T_1267 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1268 = eq(_T_1267, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1269 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34] + node _T_1270 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1271 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1272 = and(_T_1268, _T_1269) @[dec_dec_ctl.scala 17:17] + node _T_1273 = and(_T_1272, _T_1270) @[dec_dec_ctl.scala 17:17] + node _T_1274 = and(_T_1273, _T_1271) @[dec_dec_ctl.scala 17:17] + node _T_1275 = or(_T_1266, _T_1274) @[dec_dec_ctl.scala 112:112] + node _T_1276 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34] + node _T_1277 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1278 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1279 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1280 = and(_T_1276, _T_1277) @[dec_dec_ctl.scala 17:17] + node _T_1281 = and(_T_1280, _T_1278) @[dec_dec_ctl.scala 17:17] + node _T_1282 = and(_T_1281, _T_1279) @[dec_dec_ctl.scala 17:17] + node _T_1283 = or(_T_1275, _T_1282) @[dec_dec_ctl.scala 113:31] + node _T_1284 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34] + node _T_1285 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1286 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1287 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1288 = and(_T_1284, _T_1285) @[dec_dec_ctl.scala 17:17] + node _T_1289 = and(_T_1288, _T_1286) @[dec_dec_ctl.scala 17:17] + node _T_1290 = and(_T_1289, _T_1287) @[dec_dec_ctl.scala 17:17] + node _T_1291 = or(_T_1283, _T_1290) @[dec_dec_ctl.scala 113:58] + node _T_1292 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34] + node _T_1293 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1294 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1295 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1296 = and(_T_1292, _T_1293) @[dec_dec_ctl.scala 17:17] + node _T_1297 = and(_T_1296, _T_1294) @[dec_dec_ctl.scala 17:17] + node _T_1298 = and(_T_1297, _T_1295) @[dec_dec_ctl.scala 17:17] + node _T_1299 = or(_T_1291, _T_1298) @[dec_dec_ctl.scala 113:85] + node _T_1300 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34] + node _T_1301 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1302 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1303 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1304 = and(_T_1300, _T_1301) @[dec_dec_ctl.scala 17:17] + node _T_1305 = and(_T_1304, _T_1302) @[dec_dec_ctl.scala 17:17] + node _T_1306 = and(_T_1305, _T_1303) @[dec_dec_ctl.scala 17:17] + node _T_1307 = or(_T_1299, _T_1306) @[dec_dec_ctl.scala 113:112] + node _T_1308 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34] + node _T_1309 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1310 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1311 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1312 = and(_T_1308, _T_1309) @[dec_dec_ctl.scala 17:17] + node _T_1313 = and(_T_1312, _T_1310) @[dec_dec_ctl.scala 17:17] + node _T_1314 = and(_T_1313, _T_1311) @[dec_dec_ctl.scala 17:17] + node _T_1315 = or(_T_1307, _T_1314) @[dec_dec_ctl.scala 114:30] + io.out.postsync <= _T_1315 @[dec_dec_ctl.scala 111:19] + node _T_1316 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_1317 = eq(_T_1316, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1318 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_1319 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1320 = eq(_T_1319, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1321 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1322 = eq(_T_1321, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1323 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1324 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1325 = and(_T_1317, _T_1318) @[dec_dec_ctl.scala 17:17] + node _T_1326 = and(_T_1325, _T_1320) @[dec_dec_ctl.scala 17:17] + node _T_1327 = and(_T_1326, _T_1322) @[dec_dec_ctl.scala 17:17] + node _T_1328 = and(_T_1327, _T_1323) @[dec_dec_ctl.scala 17:17] + node _T_1329 = and(_T_1328, _T_1324) @[dec_dec_ctl.scala 17:17] + io.out.ebreak <= _T_1329 @[dec_dec_ctl.scala 116:17] + node _T_1330 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_1331 = eq(_T_1330, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1332 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1334 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1336 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1337 = eq(_T_1336, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1338 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1339 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1340 = and(_T_1331, _T_1333) @[dec_dec_ctl.scala 17:17] + node _T_1341 = and(_T_1340, _T_1335) @[dec_dec_ctl.scala 17:17] + node _T_1342 = and(_T_1341, _T_1337) @[dec_dec_ctl.scala 17:17] + node _T_1343 = and(_T_1342, _T_1338) @[dec_dec_ctl.scala 17:17] + node _T_1344 = and(_T_1343, _T_1339) @[dec_dec_ctl.scala 17:17] + io.out.ecall <= _T_1344 @[dec_dec_ctl.scala 118:16] + node _T_1345 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1346 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1347 = eq(_T_1346, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1348 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1349 = eq(_T_1348, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1350 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_1351 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1352 = and(_T_1345, _T_1347) @[dec_dec_ctl.scala 17:17] + node _T_1353 = and(_T_1352, _T_1349) @[dec_dec_ctl.scala 17:17] + node _T_1354 = and(_T_1353, _T_1350) @[dec_dec_ctl.scala 17:17] + node _T_1355 = and(_T_1354, _T_1351) @[dec_dec_ctl.scala 17:17] + io.out.mret <= _T_1355 @[dec_dec_ctl.scala 120:15] + node _T_1356 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_1357 = eq(_T_1356, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1358 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1359 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_1360 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_1361 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1362 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1363 = eq(_T_1362, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1364 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1365 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1366 = eq(_T_1365, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1367 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1368 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1369 = eq(_T_1368, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1370 = and(_T_1357, _T_1358) @[dec_dec_ctl.scala 17:17] + node _T_1371 = and(_T_1370, _T_1359) @[dec_dec_ctl.scala 17:17] + node _T_1372 = and(_T_1371, _T_1360) @[dec_dec_ctl.scala 17:17] + node _T_1373 = and(_T_1372, _T_1361) @[dec_dec_ctl.scala 17:17] + node _T_1374 = and(_T_1373, _T_1363) @[dec_dec_ctl.scala 17:17] + node _T_1375 = and(_T_1374, _T_1364) @[dec_dec_ctl.scala 17:17] + node _T_1376 = and(_T_1375, _T_1366) @[dec_dec_ctl.scala 17:17] + node _T_1377 = and(_T_1376, _T_1367) @[dec_dec_ctl.scala 17:17] + node _T_1378 = and(_T_1377, _T_1369) @[dec_dec_ctl.scala 17:17] + node _T_1379 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1380 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1381 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_1382 = eq(_T_1381, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1383 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_1384 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1385 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1386 = eq(_T_1385, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1387 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1388 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1389 = eq(_T_1388, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1390 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1391 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1392 = eq(_T_1391, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1393 = and(_T_1379, _T_1380) @[dec_dec_ctl.scala 17:17] + node _T_1394 = and(_T_1393, _T_1382) @[dec_dec_ctl.scala 17:17] + node _T_1395 = and(_T_1394, _T_1383) @[dec_dec_ctl.scala 17:17] + node _T_1396 = and(_T_1395, _T_1384) @[dec_dec_ctl.scala 17:17] + node _T_1397 = and(_T_1396, _T_1386) @[dec_dec_ctl.scala 17:17] + node _T_1398 = and(_T_1397, _T_1387) @[dec_dec_ctl.scala 17:17] + node _T_1399 = and(_T_1398, _T_1389) @[dec_dec_ctl.scala 17:17] + node _T_1400 = and(_T_1399, _T_1390) @[dec_dec_ctl.scala 17:17] + node _T_1401 = and(_T_1400, _T_1392) @[dec_dec_ctl.scala 17:17] + node _T_1402 = or(_T_1378, _T_1401) @[dec_dec_ctl.scala 122:63] + node _T_1403 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1404 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1405 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_1406 = eq(_T_1405, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1407 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_1408 = eq(_T_1407, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1409 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1410 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1411 = eq(_T_1410, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1412 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1413 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1414 = eq(_T_1413, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1415 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1416 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1417 = eq(_T_1416, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1418 = and(_T_1403, _T_1404) @[dec_dec_ctl.scala 17:17] + node _T_1419 = and(_T_1418, _T_1406) @[dec_dec_ctl.scala 17:17] + node _T_1420 = and(_T_1419, _T_1408) @[dec_dec_ctl.scala 17:17] + node _T_1421 = and(_T_1420, _T_1409) @[dec_dec_ctl.scala 17:17] + node _T_1422 = and(_T_1421, _T_1411) @[dec_dec_ctl.scala 17:17] + node _T_1423 = and(_T_1422, _T_1412) @[dec_dec_ctl.scala 17:17] + node _T_1424 = and(_T_1423, _T_1414) @[dec_dec_ctl.scala 17:17] + node _T_1425 = and(_T_1424, _T_1415) @[dec_dec_ctl.scala 17:17] + node _T_1426 = and(_T_1425, _T_1417) @[dec_dec_ctl.scala 17:17] + node _T_1427 = or(_T_1402, _T_1426) @[dec_dec_ctl.scala 122:111] + node _T_1428 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1429 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_1430 = eq(_T_1429, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1431 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1432 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1434 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1435 = eq(_T_1434, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1436 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1437 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1438 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1440 = and(_T_1428, _T_1430) @[dec_dec_ctl.scala 17:17] + node _T_1441 = and(_T_1440, _T_1431) @[dec_dec_ctl.scala 17:17] + node _T_1442 = and(_T_1441, _T_1433) @[dec_dec_ctl.scala 17:17] + node _T_1443 = and(_T_1442, _T_1435) @[dec_dec_ctl.scala 17:17] + node _T_1444 = and(_T_1443, _T_1436) @[dec_dec_ctl.scala 17:17] + node _T_1445 = and(_T_1444, _T_1437) @[dec_dec_ctl.scala 17:17] + node _T_1446 = and(_T_1445, _T_1439) @[dec_dec_ctl.scala 17:17] + node _T_1447 = or(_T_1427, _T_1446) @[dec_dec_ctl.scala 123:52] + node _T_1448 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1449 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1450 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1451 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1452 = eq(_T_1451, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1453 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1454 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1455 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1456 = eq(_T_1455, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1457 = and(_T_1448, _T_1449) @[dec_dec_ctl.scala 17:17] + node _T_1458 = and(_T_1457, _T_1450) @[dec_dec_ctl.scala 17:17] + node _T_1459 = and(_T_1458, _T_1452) @[dec_dec_ctl.scala 17:17] + node _T_1460 = and(_T_1459, _T_1453) @[dec_dec_ctl.scala 17:17] + node _T_1461 = and(_T_1460, _T_1454) @[dec_dec_ctl.scala 17:17] + node _T_1462 = and(_T_1461, _T_1456) @[dec_dec_ctl.scala 17:17] + node _T_1463 = or(_T_1447, _T_1462) @[dec_dec_ctl.scala 123:93] + node _T_1464 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1465 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1466 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_1467 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1469 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1470 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1471 = eq(_T_1470, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1472 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1473 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1474 = eq(_T_1473, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1475 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1476 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1477 = eq(_T_1476, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1478 = and(_T_1464, _T_1465) @[dec_dec_ctl.scala 17:17] + node _T_1479 = and(_T_1478, _T_1466) @[dec_dec_ctl.scala 17:17] + node _T_1480 = and(_T_1479, _T_1468) @[dec_dec_ctl.scala 17:17] + node _T_1481 = and(_T_1480, _T_1469) @[dec_dec_ctl.scala 17:17] + node _T_1482 = and(_T_1481, _T_1471) @[dec_dec_ctl.scala 17:17] + node _T_1483 = and(_T_1482, _T_1472) @[dec_dec_ctl.scala 17:17] + node _T_1484 = and(_T_1483, _T_1474) @[dec_dec_ctl.scala 17:17] + node _T_1485 = and(_T_1484, _T_1475) @[dec_dec_ctl.scala 17:17] + node _T_1486 = and(_T_1485, _T_1477) @[dec_dec_ctl.scala 17:17] + node _T_1487 = or(_T_1463, _T_1486) @[dec_dec_ctl.scala 124:39] + node _T_1488 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1489 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1490 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1492 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_1493 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1494 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1495 = eq(_T_1494, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1496 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1497 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1498 = eq(_T_1497, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1499 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1500 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1501 = eq(_T_1500, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1502 = and(_T_1488, _T_1489) @[dec_dec_ctl.scala 17:17] + node _T_1503 = and(_T_1502, _T_1491) @[dec_dec_ctl.scala 17:17] + node _T_1504 = and(_T_1503, _T_1492) @[dec_dec_ctl.scala 17:17] + node _T_1505 = and(_T_1504, _T_1493) @[dec_dec_ctl.scala 17:17] + node _T_1506 = and(_T_1505, _T_1495) @[dec_dec_ctl.scala 17:17] + node _T_1507 = and(_T_1506, _T_1496) @[dec_dec_ctl.scala 17:17] + node _T_1508 = and(_T_1507, _T_1498) @[dec_dec_ctl.scala 17:17] + node _T_1509 = and(_T_1508, _T_1499) @[dec_dec_ctl.scala 17:17] + node _T_1510 = and(_T_1509, _T_1501) @[dec_dec_ctl.scala 17:17] + node _T_1511 = or(_T_1487, _T_1510) @[dec_dec_ctl.scala 124:87] + node _T_1512 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1513 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1514 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1516 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_1517 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1518 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1520 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1521 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1522 = eq(_T_1521, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1523 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1524 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1525 = eq(_T_1524, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1526 = and(_T_1512, _T_1513) @[dec_dec_ctl.scala 17:17] + node _T_1527 = and(_T_1526, _T_1515) @[dec_dec_ctl.scala 17:17] + node _T_1528 = and(_T_1527, _T_1516) @[dec_dec_ctl.scala 17:17] + node _T_1529 = and(_T_1528, _T_1517) @[dec_dec_ctl.scala 17:17] + node _T_1530 = and(_T_1529, _T_1519) @[dec_dec_ctl.scala 17:17] + node _T_1531 = and(_T_1530, _T_1520) @[dec_dec_ctl.scala 17:17] + node _T_1532 = and(_T_1531, _T_1522) @[dec_dec_ctl.scala 17:17] + node _T_1533 = and(_T_1532, _T_1523) @[dec_dec_ctl.scala 17:17] + node _T_1534 = and(_T_1533, _T_1525) @[dec_dec_ctl.scala 17:17] + node _T_1535 = or(_T_1511, _T_1534) @[dec_dec_ctl.scala 125:51] + node _T_1536 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1537 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1538 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1539 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_1540 = eq(_T_1539, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1541 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1542 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1543 = eq(_T_1542, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1544 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1545 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1546 = eq(_T_1545, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1547 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1548 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1549 = eq(_T_1548, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1550 = and(_T_1536, _T_1537) @[dec_dec_ctl.scala 17:17] + node _T_1551 = and(_T_1550, _T_1538) @[dec_dec_ctl.scala 17:17] + node _T_1552 = and(_T_1551, _T_1540) @[dec_dec_ctl.scala 17:17] + node _T_1553 = and(_T_1552, _T_1541) @[dec_dec_ctl.scala 17:17] + node _T_1554 = and(_T_1553, _T_1543) @[dec_dec_ctl.scala 17:17] + node _T_1555 = and(_T_1554, _T_1544) @[dec_dec_ctl.scala 17:17] + node _T_1556 = and(_T_1555, _T_1546) @[dec_dec_ctl.scala 17:17] + node _T_1557 = and(_T_1556, _T_1547) @[dec_dec_ctl.scala 17:17] + node _T_1558 = and(_T_1557, _T_1549) @[dec_dec_ctl.scala 17:17] + node _T_1559 = or(_T_1535, _T_1558) @[dec_dec_ctl.scala 125:99] + node _T_1560 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_1561 = eq(_T_1560, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1562 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1563 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_1564 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1565 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1566 = eq(_T_1565, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1567 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1568 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1569 = eq(_T_1568, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1570 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1571 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1573 = and(_T_1561, _T_1562) @[dec_dec_ctl.scala 17:17] + node _T_1574 = and(_T_1573, _T_1563) @[dec_dec_ctl.scala 17:17] + node _T_1575 = and(_T_1574, _T_1564) @[dec_dec_ctl.scala 17:17] + node _T_1576 = and(_T_1575, _T_1566) @[dec_dec_ctl.scala 17:17] + node _T_1577 = and(_T_1576, _T_1567) @[dec_dec_ctl.scala 17:17] + node _T_1578 = and(_T_1577, _T_1569) @[dec_dec_ctl.scala 17:17] + node _T_1579 = and(_T_1578, _T_1570) @[dec_dec_ctl.scala 17:17] + node _T_1580 = and(_T_1579, _T_1572) @[dec_dec_ctl.scala 17:17] + node _T_1581 = or(_T_1559, _T_1580) @[dec_dec_ctl.scala 126:51] + node _T_1582 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_1583 = eq(_T_1582, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1584 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_1585 = eq(_T_1584, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1586 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1587 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_1588 = eq(_T_1587, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1589 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1590 = eq(_T_1589, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1591 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1592 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1593 = eq(_T_1592, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1594 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1595 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1596 = eq(_T_1595, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1597 = and(_T_1583, _T_1585) @[dec_dec_ctl.scala 17:17] + node _T_1598 = and(_T_1597, _T_1586) @[dec_dec_ctl.scala 17:17] + node _T_1599 = and(_T_1598, _T_1588) @[dec_dec_ctl.scala 17:17] + node _T_1600 = and(_T_1599, _T_1590) @[dec_dec_ctl.scala 17:17] + node _T_1601 = and(_T_1600, _T_1591) @[dec_dec_ctl.scala 17:17] + node _T_1602 = and(_T_1601, _T_1593) @[dec_dec_ctl.scala 17:17] + node _T_1603 = and(_T_1602, _T_1594) @[dec_dec_ctl.scala 17:17] + node _T_1604 = and(_T_1603, _T_1596) @[dec_dec_ctl.scala 17:17] + node _T_1605 = or(_T_1581, _T_1604) @[dec_dec_ctl.scala 126:96] + node _T_1606 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1607 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1608 = eq(_T_1607, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1609 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1610 = eq(_T_1609, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1611 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1612 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1613 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1614 = eq(_T_1613, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1615 = and(_T_1606, _T_1608) @[dec_dec_ctl.scala 17:17] + node _T_1616 = and(_T_1615, _T_1610) @[dec_dec_ctl.scala 17:17] + node _T_1617 = and(_T_1616, _T_1611) @[dec_dec_ctl.scala 17:17] + node _T_1618 = and(_T_1617, _T_1612) @[dec_dec_ctl.scala 17:17] + node _T_1619 = and(_T_1618, _T_1614) @[dec_dec_ctl.scala 17:17] + node _T_1620 = or(_T_1605, _T_1619) @[dec_dec_ctl.scala 127:50] + node _T_1621 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1622 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1623 = eq(_T_1622, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1624 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_1625 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1626 = eq(_T_1625, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1627 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1628 = eq(_T_1627, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1629 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1630 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1631 = eq(_T_1630, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1632 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1633 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1634 = eq(_T_1633, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1635 = and(_T_1621, _T_1623) @[dec_dec_ctl.scala 17:17] + node _T_1636 = and(_T_1635, _T_1624) @[dec_dec_ctl.scala 17:17] + node _T_1637 = and(_T_1636, _T_1626) @[dec_dec_ctl.scala 17:17] + node _T_1638 = and(_T_1637, _T_1628) @[dec_dec_ctl.scala 17:17] + node _T_1639 = and(_T_1638, _T_1629) @[dec_dec_ctl.scala 17:17] + node _T_1640 = and(_T_1639, _T_1631) @[dec_dec_ctl.scala 17:17] + node _T_1641 = and(_T_1640, _T_1632) @[dec_dec_ctl.scala 17:17] + node _T_1642 = and(_T_1641, _T_1634) @[dec_dec_ctl.scala 17:17] + node _T_1643 = or(_T_1620, _T_1642) @[dec_dec_ctl.scala 127:84] + node _T_1644 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1645 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1646 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1647 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1648 = eq(_T_1647, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1649 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1650 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1651 = eq(_T_1650, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1652 = and(_T_1644, _T_1645) @[dec_dec_ctl.scala 17:17] + node _T_1653 = and(_T_1652, _T_1646) @[dec_dec_ctl.scala 17:17] + node _T_1654 = and(_T_1653, _T_1648) @[dec_dec_ctl.scala 17:17] + node _T_1655 = and(_T_1654, _T_1649) @[dec_dec_ctl.scala 17:17] + node _T_1656 = and(_T_1655, _T_1651) @[dec_dec_ctl.scala 17:17] + node _T_1657 = or(_T_1643, _T_1656) @[dec_dec_ctl.scala 128:49] + io.out.mul <= _T_1657 @[dec_dec_ctl.scala 122:14] + node _T_1658 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1659 = eq(_T_1658, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1660 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1661 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1662 = eq(_T_1661, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1663 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1664 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1665 = eq(_T_1664, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1666 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1667 = eq(_T_1666, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1668 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1669 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1670 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1671 = eq(_T_1670, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1672 = and(_T_1659, _T_1660) @[dec_dec_ctl.scala 17:17] + node _T_1673 = and(_T_1672, _T_1662) @[dec_dec_ctl.scala 17:17] + node _T_1674 = and(_T_1673, _T_1663) @[dec_dec_ctl.scala 17:17] + node _T_1675 = and(_T_1674, _T_1665) @[dec_dec_ctl.scala 17:17] + node _T_1676 = and(_T_1675, _T_1667) @[dec_dec_ctl.scala 17:17] + node _T_1677 = and(_T_1676, _T_1668) @[dec_dec_ctl.scala 17:17] + node _T_1678 = and(_T_1677, _T_1669) @[dec_dec_ctl.scala 17:17] + node _T_1679 = and(_T_1678, _T_1671) @[dec_dec_ctl.scala 17:17] + node _T_1680 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1681 = eq(_T_1680, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1682 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1683 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1684 = eq(_T_1683, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1685 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1686 = eq(_T_1685, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1687 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1688 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1689 = eq(_T_1688, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1690 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1691 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1692 = eq(_T_1691, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1693 = and(_T_1681, _T_1682) @[dec_dec_ctl.scala 17:17] + node _T_1694 = and(_T_1693, _T_1684) @[dec_dec_ctl.scala 17:17] + node _T_1695 = and(_T_1694, _T_1686) @[dec_dec_ctl.scala 17:17] + node _T_1696 = and(_T_1695, _T_1687) @[dec_dec_ctl.scala 17:17] + node _T_1697 = and(_T_1696, _T_1689) @[dec_dec_ctl.scala 17:17] + node _T_1698 = and(_T_1697, _T_1690) @[dec_dec_ctl.scala 17:17] + node _T_1699 = and(_T_1698, _T_1692) @[dec_dec_ctl.scala 17:17] + node _T_1700 = or(_T_1679, _T_1699) @[dec_dec_ctl.scala 130:65] + io.out.rs1_sign <= _T_1700 @[dec_dec_ctl.scala 130:19] + node _T_1701 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1702 = eq(_T_1701, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1703 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1704 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1705 = eq(_T_1704, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1706 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1707 = eq(_T_1706, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1708 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1709 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1710 = eq(_T_1709, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1711 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1712 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1713 = eq(_T_1712, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1714 = and(_T_1702, _T_1703) @[dec_dec_ctl.scala 17:17] + node _T_1715 = and(_T_1714, _T_1705) @[dec_dec_ctl.scala 17:17] + node _T_1716 = and(_T_1715, _T_1707) @[dec_dec_ctl.scala 17:17] + node _T_1717 = and(_T_1716, _T_1708) @[dec_dec_ctl.scala 17:17] + node _T_1718 = and(_T_1717, _T_1710) @[dec_dec_ctl.scala 17:17] + node _T_1719 = and(_T_1718, _T_1711) @[dec_dec_ctl.scala 17:17] + node _T_1720 = and(_T_1719, _T_1713) @[dec_dec_ctl.scala 17:17] + io.out.rs2_sign <= _T_1720 @[dec_dec_ctl.scala 132:19] + node _T_1721 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1722 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1723 = eq(_T_1722, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1724 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1725 = eq(_T_1724, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1726 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1727 = eq(_T_1726, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1728 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1729 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1730 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1731 = eq(_T_1730, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1732 = and(_T_1721, _T_1723) @[dec_dec_ctl.scala 17:17] + node _T_1733 = and(_T_1732, _T_1725) @[dec_dec_ctl.scala 17:17] + node _T_1734 = and(_T_1733, _T_1727) @[dec_dec_ctl.scala 17:17] + node _T_1735 = and(_T_1734, _T_1728) @[dec_dec_ctl.scala 17:17] + node _T_1736 = and(_T_1735, _T_1729) @[dec_dec_ctl.scala 17:17] + node _T_1737 = and(_T_1736, _T_1731) @[dec_dec_ctl.scala 17:17] + io.out.low <= _T_1737 @[dec_dec_ctl.scala 134:14] + node _T_1738 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1739 = eq(_T_1738, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1740 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1741 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1742 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1743 = eq(_T_1742, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1744 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1745 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1746 = eq(_T_1745, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1747 = and(_T_1739, _T_1740) @[dec_dec_ctl.scala 17:17] + node _T_1748 = and(_T_1747, _T_1741) @[dec_dec_ctl.scala 17:17] + node _T_1749 = and(_T_1748, _T_1743) @[dec_dec_ctl.scala 17:17] + node _T_1750 = and(_T_1749, _T_1744) @[dec_dec_ctl.scala 17:17] + node _T_1751 = and(_T_1750, _T_1746) @[dec_dec_ctl.scala 17:17] + io.out.div <= _T_1751 @[dec_dec_ctl.scala 136:14] + node _T_1752 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1753 = eq(_T_1752, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1754 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1755 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1756 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_1757 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1758 = eq(_T_1757, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1759 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1760 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1761 = eq(_T_1760, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1762 = and(_T_1753, _T_1754) @[dec_dec_ctl.scala 17:17] + node _T_1763 = and(_T_1762, _T_1755) @[dec_dec_ctl.scala 17:17] + node _T_1764 = and(_T_1763, _T_1756) @[dec_dec_ctl.scala 17:17] + node _T_1765 = and(_T_1764, _T_1758) @[dec_dec_ctl.scala 17:17] + node _T_1766 = and(_T_1765, _T_1759) @[dec_dec_ctl.scala 17:17] + node _T_1767 = and(_T_1766, _T_1761) @[dec_dec_ctl.scala 17:17] + io.out.rem <= _T_1767 @[dec_dec_ctl.scala 138:14] + node _T_1768 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1769 = eq(_T_1768, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1770 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_1771 = and(_T_1769, _T_1770) @[dec_dec_ctl.scala 17:17] + io.out.fence <= _T_1771 @[dec_dec_ctl.scala 140:16] + node _T_1772 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1773 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1774 = eq(_T_1773, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1775 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_1776 = and(_T_1772, _T_1774) @[dec_dec_ctl.scala 17:17] + node _T_1777 = and(_T_1776, _T_1775) @[dec_dec_ctl.scala 17:17] + io.out.fence_i <= _T_1777 @[dec_dec_ctl.scala 142:18] + node _T_1778 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1779 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1780 = eq(_T_1779, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1781 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_1782 = eq(_T_1781, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1783 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_1784 = eq(_T_1783, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1785 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_1786 = eq(_T_1785, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1787 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_1788 = eq(_T_1787, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1789 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1790 = eq(_T_1789, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1791 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1792 = eq(_T_1791, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1793 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1794 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1795 = eq(_T_1794, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1796 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1797 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1798 = eq(_T_1797, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1799 = and(_T_1778, _T_1780) @[dec_dec_ctl.scala 17:17] + node _T_1800 = and(_T_1799, _T_1782) @[dec_dec_ctl.scala 17:17] + node _T_1801 = and(_T_1800, _T_1784) @[dec_dec_ctl.scala 17:17] + node _T_1802 = and(_T_1801, _T_1786) @[dec_dec_ctl.scala 17:17] + node _T_1803 = and(_T_1802, _T_1788) @[dec_dec_ctl.scala 17:17] + node _T_1804 = and(_T_1803, _T_1790) @[dec_dec_ctl.scala 17:17] + node _T_1805 = and(_T_1804, _T_1792) @[dec_dec_ctl.scala 17:17] + node _T_1806 = and(_T_1805, _T_1793) @[dec_dec_ctl.scala 17:17] + node _T_1807 = and(_T_1806, _T_1795) @[dec_dec_ctl.scala 17:17] + node _T_1808 = and(_T_1807, _T_1796) @[dec_dec_ctl.scala 17:17] + node _T_1809 = and(_T_1808, _T_1798) @[dec_dec_ctl.scala 17:17] + io.out.clz <= _T_1809 @[dec_dec_ctl.scala 144:14] + node _T_1810 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1811 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1812 = eq(_T_1811, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1813 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_1814 = eq(_T_1813, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1815 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_1816 = eq(_T_1815, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1817 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_1818 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1819 = eq(_T_1818, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1820 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1821 = eq(_T_1820, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1822 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1823 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1824 = eq(_T_1823, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1825 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1826 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1827 = eq(_T_1826, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1828 = and(_T_1810, _T_1812) @[dec_dec_ctl.scala 17:17] + node _T_1829 = and(_T_1828, _T_1814) @[dec_dec_ctl.scala 17:17] + node _T_1830 = and(_T_1829, _T_1816) @[dec_dec_ctl.scala 17:17] + node _T_1831 = and(_T_1830, _T_1817) @[dec_dec_ctl.scala 17:17] + node _T_1832 = and(_T_1831, _T_1819) @[dec_dec_ctl.scala 17:17] + node _T_1833 = and(_T_1832, _T_1821) @[dec_dec_ctl.scala 17:17] + node _T_1834 = and(_T_1833, _T_1822) @[dec_dec_ctl.scala 17:17] + node _T_1835 = and(_T_1834, _T_1824) @[dec_dec_ctl.scala 17:17] + node _T_1836 = and(_T_1835, _T_1825) @[dec_dec_ctl.scala 17:17] + node _T_1837 = and(_T_1836, _T_1827) @[dec_dec_ctl.scala 17:17] + io.out.ctz <= _T_1837 @[dec_dec_ctl.scala 146:14] + node _T_1838 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1839 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1840 = eq(_T_1839, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1841 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_1842 = eq(_T_1841, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1843 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_1844 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1845 = eq(_T_1844, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1846 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1847 = eq(_T_1846, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1848 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1849 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1850 = eq(_T_1849, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1851 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1852 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1853 = eq(_T_1852, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1854 = and(_T_1838, _T_1840) @[dec_dec_ctl.scala 17:17] + node _T_1855 = and(_T_1854, _T_1842) @[dec_dec_ctl.scala 17:17] + node _T_1856 = and(_T_1855, _T_1843) @[dec_dec_ctl.scala 17:17] + node _T_1857 = and(_T_1856, _T_1845) @[dec_dec_ctl.scala 17:17] + node _T_1858 = and(_T_1857, _T_1847) @[dec_dec_ctl.scala 17:17] + node _T_1859 = and(_T_1858, _T_1848) @[dec_dec_ctl.scala 17:17] + node _T_1860 = and(_T_1859, _T_1850) @[dec_dec_ctl.scala 17:17] + node _T_1861 = and(_T_1860, _T_1851) @[dec_dec_ctl.scala 17:17] + node _T_1862 = and(_T_1861, _T_1853) @[dec_dec_ctl.scala 17:17] + io.out.pcnt <= _T_1862 @[dec_dec_ctl.scala 148:15] + node _T_1863 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1864 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1865 = eq(_T_1864, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1866 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_1867 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_1868 = eq(_T_1867, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1869 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1870 = eq(_T_1869, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1871 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1872 = eq(_T_1871, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1873 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1874 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1875 = eq(_T_1874, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1876 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1877 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1878 = eq(_T_1877, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1879 = and(_T_1863, _T_1865) @[dec_dec_ctl.scala 17:17] + node _T_1880 = and(_T_1879, _T_1866) @[dec_dec_ctl.scala 17:17] + node _T_1881 = and(_T_1880, _T_1868) @[dec_dec_ctl.scala 17:17] + node _T_1882 = and(_T_1881, _T_1870) @[dec_dec_ctl.scala 17:17] + node _T_1883 = and(_T_1882, _T_1872) @[dec_dec_ctl.scala 17:17] + node _T_1884 = and(_T_1883, _T_1873) @[dec_dec_ctl.scala 17:17] + node _T_1885 = and(_T_1884, _T_1875) @[dec_dec_ctl.scala 17:17] + node _T_1886 = and(_T_1885, _T_1876) @[dec_dec_ctl.scala 17:17] + node _T_1887 = and(_T_1886, _T_1878) @[dec_dec_ctl.scala 17:17] + io.out.sext_b <= _T_1887 @[dec_dec_ctl.scala 150:17] + node _T_1888 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_1889 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1890 = eq(_T_1889, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1891 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_1892 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_1893 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1895 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1896 = eq(_T_1895, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1897 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1898 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_1899 = eq(_T_1898, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1900 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1901 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1902 = eq(_T_1901, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1903 = and(_T_1888, _T_1890) @[dec_dec_ctl.scala 17:17] + node _T_1904 = and(_T_1903, _T_1891) @[dec_dec_ctl.scala 17:17] + node _T_1905 = and(_T_1904, _T_1892) @[dec_dec_ctl.scala 17:17] + node _T_1906 = and(_T_1905, _T_1894) @[dec_dec_ctl.scala 17:17] + node _T_1907 = and(_T_1906, _T_1896) @[dec_dec_ctl.scala 17:17] + node _T_1908 = and(_T_1907, _T_1897) @[dec_dec_ctl.scala 17:17] + node _T_1909 = and(_T_1908, _T_1899) @[dec_dec_ctl.scala 17:17] + node _T_1910 = and(_T_1909, _T_1900) @[dec_dec_ctl.scala 17:17] + node _T_1911 = and(_T_1910, _T_1902) @[dec_dec_ctl.scala 17:17] + io.out.sext_h <= _T_1911 @[dec_dec_ctl.scala 152:17] + node _T_1912 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1914 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1915 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1916 = eq(_T_1915, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1917 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_1918 = eq(_T_1917, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1919 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1920 = eq(_T_1919, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1921 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1922 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1923 = eq(_T_1922, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1924 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1925 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1926 = eq(_T_1925, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1927 = and(_T_1913, _T_1914) @[dec_dec_ctl.scala 17:17] + node _T_1928 = and(_T_1927, _T_1916) @[dec_dec_ctl.scala 17:17] + node _T_1929 = and(_T_1928, _T_1918) @[dec_dec_ctl.scala 17:17] + node _T_1930 = and(_T_1929, _T_1920) @[dec_dec_ctl.scala 17:17] + node _T_1931 = and(_T_1930, _T_1921) @[dec_dec_ctl.scala 17:17] + node _T_1932 = and(_T_1931, _T_1923) @[dec_dec_ctl.scala 17:17] + node _T_1933 = and(_T_1932, _T_1924) @[dec_dec_ctl.scala 17:17] + node _T_1934 = and(_T_1933, _T_1926) @[dec_dec_ctl.scala 17:17] + io.out.slo <= _T_1934 @[dec_dec_ctl.scala 154:14] + node _T_1935 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_1936 = eq(_T_1935, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1937 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_1938 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_1939 = eq(_T_1938, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1940 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1941 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1942 = eq(_T_1941, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1943 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1944 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1945 = eq(_T_1944, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1946 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1947 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1948 = eq(_T_1947, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1949 = and(_T_1936, _T_1937) @[dec_dec_ctl.scala 17:17] + node _T_1950 = and(_T_1949, _T_1939) @[dec_dec_ctl.scala 17:17] + node _T_1951 = and(_T_1950, _T_1940) @[dec_dec_ctl.scala 17:17] + node _T_1952 = and(_T_1951, _T_1942) @[dec_dec_ctl.scala 17:17] + node _T_1953 = and(_T_1952, _T_1943) @[dec_dec_ctl.scala 17:17] + node _T_1954 = and(_T_1953, _T_1945) @[dec_dec_ctl.scala 17:17] + node _T_1955 = and(_T_1954, _T_1946) @[dec_dec_ctl.scala 17:17] + node _T_1956 = and(_T_1955, _T_1948) @[dec_dec_ctl.scala 17:17] + io.out.sro <= _T_1956 @[dec_dec_ctl.scala 156:14] + node _T_1957 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1958 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1959 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1960 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1961 = eq(_T_1960, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1962 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1963 = eq(_T_1962, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1964 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1965 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1966 = eq(_T_1965, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1967 = and(_T_1957, _T_1958) @[dec_dec_ctl.scala 17:17] + node _T_1968 = and(_T_1967, _T_1959) @[dec_dec_ctl.scala 17:17] + node _T_1969 = and(_T_1968, _T_1961) @[dec_dec_ctl.scala 17:17] + node _T_1970 = and(_T_1969, _T_1963) @[dec_dec_ctl.scala 17:17] + node _T_1971 = and(_T_1970, _T_1964) @[dec_dec_ctl.scala 17:17] + node _T_1972 = and(_T_1971, _T_1966) @[dec_dec_ctl.scala 17:17] + io.out.min <= _T_1972 @[dec_dec_ctl.scala 158:14] + node _T_1973 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1974 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_1975 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_1976 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_1977 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_1978 = eq(_T_1977, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1979 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1980 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_1981 = eq(_T_1980, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1982 = and(_T_1973, _T_1974) @[dec_dec_ctl.scala 17:17] + node _T_1983 = and(_T_1982, _T_1975) @[dec_dec_ctl.scala 17:17] + node _T_1984 = and(_T_1983, _T_1976) @[dec_dec_ctl.scala 17:17] + node _T_1985 = and(_T_1984, _T_1978) @[dec_dec_ctl.scala 17:17] + node _T_1986 = and(_T_1985, _T_1979) @[dec_dec_ctl.scala 17:17] + node _T_1987 = and(_T_1986, _T_1981) @[dec_dec_ctl.scala 17:17] + io.out.max <= _T_1987 @[dec_dec_ctl.scala 160:14] + node _T_1988 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_1989 = eq(_T_1988, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1990 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_1991 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_1992 = eq(_T_1991, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1993 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_1994 = eq(_T_1993, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1995 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_1996 = eq(_T_1995, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_1997 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_1998 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_1999 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2000 = eq(_T_1999, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2001 = and(_T_1989, _T_1990) @[dec_dec_ctl.scala 17:17] + node _T_2002 = and(_T_2001, _T_1992) @[dec_dec_ctl.scala 17:17] + node _T_2003 = and(_T_2002, _T_1994) @[dec_dec_ctl.scala 17:17] + node _T_2004 = and(_T_2003, _T_1996) @[dec_dec_ctl.scala 17:17] + node _T_2005 = and(_T_2004, _T_1997) @[dec_dec_ctl.scala 17:17] + node _T_2006 = and(_T_2005, _T_1998) @[dec_dec_ctl.scala 17:17] + node _T_2007 = and(_T_2006, _T_2000) @[dec_dec_ctl.scala 17:17] + io.out.pack <= _T_2007 @[dec_dec_ctl.scala 162:15] + node _T_2008 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2009 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2010 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2011 = eq(_T_2010, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2012 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2013 = eq(_T_2012, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2014 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2015 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2016 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2017 = eq(_T_2016, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2018 = and(_T_2008, _T_2009) @[dec_dec_ctl.scala 17:17] + node _T_2019 = and(_T_2018, _T_2011) @[dec_dec_ctl.scala 17:17] + node _T_2020 = and(_T_2019, _T_2013) @[dec_dec_ctl.scala 17:17] + node _T_2021 = and(_T_2020, _T_2014) @[dec_dec_ctl.scala 17:17] + node _T_2022 = and(_T_2021, _T_2015) @[dec_dec_ctl.scala 17:17] + node _T_2023 = and(_T_2022, _T_2017) @[dec_dec_ctl.scala 17:17] + io.out.packu <= _T_2023 @[dec_dec_ctl.scala 164:16] + node _T_2024 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2025 = eq(_T_2024, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2026 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2027 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2028 = eq(_T_2027, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2029 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2030 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2031 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2032 = eq(_T_2031, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2033 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2034 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2035 = eq(_T_2034, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2036 = and(_T_2025, _T_2026) @[dec_dec_ctl.scala 17:17] + node _T_2037 = and(_T_2036, _T_2028) @[dec_dec_ctl.scala 17:17] + node _T_2038 = and(_T_2037, _T_2029) @[dec_dec_ctl.scala 17:17] + node _T_2039 = and(_T_2038, _T_2030) @[dec_dec_ctl.scala 17:17] + node _T_2040 = and(_T_2039, _T_2032) @[dec_dec_ctl.scala 17:17] + node _T_2041 = and(_T_2040, _T_2033) @[dec_dec_ctl.scala 17:17] + node _T_2042 = and(_T_2041, _T_2035) @[dec_dec_ctl.scala 17:17] + io.out.packh <= _T_2042 @[dec_dec_ctl.scala 166:16] + node _T_2043 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2044 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2045 = eq(_T_2044, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2046 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2047 = eq(_T_2046, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2048 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2049 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2050 = eq(_T_2049, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2051 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2052 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2053 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2054 = eq(_T_2053, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2055 = and(_T_2043, _T_2045) @[dec_dec_ctl.scala 17:17] + node _T_2056 = and(_T_2055, _T_2047) @[dec_dec_ctl.scala 17:17] + node _T_2057 = and(_T_2056, _T_2048) @[dec_dec_ctl.scala 17:17] + node _T_2058 = and(_T_2057, _T_2050) @[dec_dec_ctl.scala 17:17] + node _T_2059 = and(_T_2058, _T_2051) @[dec_dec_ctl.scala 17:17] + node _T_2060 = and(_T_2059, _T_2052) @[dec_dec_ctl.scala 17:17] + node _T_2061 = and(_T_2060, _T_2054) @[dec_dec_ctl.scala 17:17] + io.out.rol <= _T_2061 @[dec_dec_ctl.scala 168:14] + node _T_2062 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2063 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2064 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2065 = eq(_T_2064, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2066 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2067 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2068 = eq(_T_2067, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2069 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2070 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2071 = eq(_T_2070, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2072 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2073 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2074 = eq(_T_2073, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2075 = and(_T_2062, _T_2063) @[dec_dec_ctl.scala 17:17] + node _T_2076 = and(_T_2075, _T_2065) @[dec_dec_ctl.scala 17:17] + node _T_2077 = and(_T_2076, _T_2066) @[dec_dec_ctl.scala 17:17] + node _T_2078 = and(_T_2077, _T_2068) @[dec_dec_ctl.scala 17:17] + node _T_2079 = and(_T_2078, _T_2069) @[dec_dec_ctl.scala 17:17] + node _T_2080 = and(_T_2079, _T_2071) @[dec_dec_ctl.scala 17:17] + node _T_2081 = and(_T_2080, _T_2072) @[dec_dec_ctl.scala 17:17] + node _T_2082 = and(_T_2081, _T_2074) @[dec_dec_ctl.scala 17:17] + io.out.ror <= _T_2082 @[dec_dec_ctl.scala 170:14] + node _T_2083 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2084 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2085 = eq(_T_2084, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2086 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_2087 = eq(_T_2086, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2088 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2089 = eq(_T_2088, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2090 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2091 = eq(_T_2090, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2092 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2093 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2094 = eq(_T_2093, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2095 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2096 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2097 = eq(_T_2096, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2098 = and(_T_2083, _T_2085) @[dec_dec_ctl.scala 17:17] + node _T_2099 = and(_T_2098, _T_2087) @[dec_dec_ctl.scala 17:17] + node _T_2100 = and(_T_2099, _T_2089) @[dec_dec_ctl.scala 17:17] + node _T_2101 = and(_T_2100, _T_2091) @[dec_dec_ctl.scala 17:17] + node _T_2102 = and(_T_2101, _T_2092) @[dec_dec_ctl.scala 17:17] + node _T_2103 = and(_T_2102, _T_2094) @[dec_dec_ctl.scala 17:17] + node _T_2104 = and(_T_2103, _T_2095) @[dec_dec_ctl.scala 17:17] + node _T_2105 = and(_T_2104, _T_2097) @[dec_dec_ctl.scala 17:17] + node _T_2106 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2107 = eq(_T_2106, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2108 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2109 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2110 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2111 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2112 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2113 = eq(_T_2112, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2114 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2115 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2116 = eq(_T_2115, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2117 = and(_T_2107, _T_2108) @[dec_dec_ctl.scala 17:17] + node _T_2118 = and(_T_2117, _T_2109) @[dec_dec_ctl.scala 17:17] + node _T_2119 = and(_T_2118, _T_2110) @[dec_dec_ctl.scala 17:17] + node _T_2120 = and(_T_2119, _T_2111) @[dec_dec_ctl.scala 17:17] + node _T_2121 = and(_T_2120, _T_2113) @[dec_dec_ctl.scala 17:17] + node _T_2122 = and(_T_2121, _T_2114) @[dec_dec_ctl.scala 17:17] + node _T_2123 = and(_T_2122, _T_2116) @[dec_dec_ctl.scala 17:17] + node _T_2124 = or(_T_2105, _T_2123) @[dec_dec_ctl.scala 172:62] + node _T_2125 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2126 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2127 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2128 = eq(_T_2127, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2129 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2130 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2131 = eq(_T_2130, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2132 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2133 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2134 = eq(_T_2133, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2135 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2136 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2137 = eq(_T_2136, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2138 = and(_T_2125, _T_2126) @[dec_dec_ctl.scala 17:17] + node _T_2139 = and(_T_2138, _T_2128) @[dec_dec_ctl.scala 17:17] + node _T_2140 = and(_T_2139, _T_2129) @[dec_dec_ctl.scala 17:17] + node _T_2141 = and(_T_2140, _T_2131) @[dec_dec_ctl.scala 17:17] + node _T_2142 = and(_T_2141, _T_2132) @[dec_dec_ctl.scala 17:17] + node _T_2143 = and(_T_2142, _T_2134) @[dec_dec_ctl.scala 17:17] + node _T_2144 = and(_T_2143, _T_2135) @[dec_dec_ctl.scala 17:17] + node _T_2145 = and(_T_2144, _T_2137) @[dec_dec_ctl.scala 17:17] + node _T_2146 = or(_T_2124, _T_2145) @[dec_dec_ctl.scala 172:103] + node _T_2147 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2148 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2149 = eq(_T_2148, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2150 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2151 = eq(_T_2150, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2152 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2153 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2154 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2155 = eq(_T_2154, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2156 = and(_T_2147, _T_2149) @[dec_dec_ctl.scala 17:17] + node _T_2157 = and(_T_2156, _T_2151) @[dec_dec_ctl.scala 17:17] + node _T_2158 = and(_T_2157, _T_2152) @[dec_dec_ctl.scala 17:17] + node _T_2159 = and(_T_2158, _T_2153) @[dec_dec_ctl.scala 17:17] + node _T_2160 = and(_T_2159, _T_2155) @[dec_dec_ctl.scala 17:17] + node _T_2161 = or(_T_2146, _T_2160) @[dec_dec_ctl.scala 173:48] + node _T_2162 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2163 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2164 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2165 = eq(_T_2164, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2166 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2167 = eq(_T_2166, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2168 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2169 = eq(_T_2168, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2170 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2171 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2172 = eq(_T_2171, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2173 = and(_T_2162, _T_2163) @[dec_dec_ctl.scala 17:17] + node _T_2174 = and(_T_2173, _T_2165) @[dec_dec_ctl.scala 17:17] + node _T_2175 = and(_T_2174, _T_2167) @[dec_dec_ctl.scala 17:17] + node _T_2176 = and(_T_2175, _T_2169) @[dec_dec_ctl.scala 17:17] + node _T_2177 = and(_T_2176, _T_2170) @[dec_dec_ctl.scala 17:17] + node _T_2178 = and(_T_2177, _T_2172) @[dec_dec_ctl.scala 17:17] + node _T_2179 = or(_T_2161, _T_2178) @[dec_dec_ctl.scala 173:83] + node _T_2180 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2181 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2182 = eq(_T_2181, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2183 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2184 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2185 = eq(_T_2184, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2186 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2187 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2188 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2189 = eq(_T_2188, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2190 = and(_T_2180, _T_2182) @[dec_dec_ctl.scala 17:17] + node _T_2191 = and(_T_2190, _T_2183) @[dec_dec_ctl.scala 17:17] + node _T_2192 = and(_T_2191, _T_2185) @[dec_dec_ctl.scala 17:17] + node _T_2193 = and(_T_2192, _T_2186) @[dec_dec_ctl.scala 17:17] + node _T_2194 = and(_T_2193, _T_2187) @[dec_dec_ctl.scala 17:17] + node _T_2195 = and(_T_2194, _T_2189) @[dec_dec_ctl.scala 17:17] + node _T_2196 = or(_T_2179, _T_2195) @[dec_dec_ctl.scala 174:42] + node _T_2197 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2198 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2199 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2200 = eq(_T_2199, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2201 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2202 = eq(_T_2201, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2203 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2204 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2205 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2206 = eq(_T_2205, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2207 = and(_T_2197, _T_2198) @[dec_dec_ctl.scala 17:17] + node _T_2208 = and(_T_2207, _T_2200) @[dec_dec_ctl.scala 17:17] + node _T_2209 = and(_T_2208, _T_2202) @[dec_dec_ctl.scala 17:17] + node _T_2210 = and(_T_2209, _T_2203) @[dec_dec_ctl.scala 17:17] + node _T_2211 = and(_T_2210, _T_2204) @[dec_dec_ctl.scala 17:17] + node _T_2212 = and(_T_2211, _T_2206) @[dec_dec_ctl.scala 17:17] + node _T_2213 = or(_T_2196, _T_2212) @[dec_dec_ctl.scala 174:79] + node _T_2214 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2215 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2216 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2217 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_2218 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_2219 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_2220 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_2221 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2222 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2223 = eq(_T_2222, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2224 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2225 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2226 = eq(_T_2225, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2227 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2228 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2229 = eq(_T_2228, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2230 = and(_T_2214, _T_2215) @[dec_dec_ctl.scala 17:17] + node _T_2231 = and(_T_2230, _T_2216) @[dec_dec_ctl.scala 17:17] + node _T_2232 = and(_T_2231, _T_2217) @[dec_dec_ctl.scala 17:17] + node _T_2233 = and(_T_2232, _T_2218) @[dec_dec_ctl.scala 17:17] + node _T_2234 = and(_T_2233, _T_2219) @[dec_dec_ctl.scala 17:17] + node _T_2235 = and(_T_2234, _T_2220) @[dec_dec_ctl.scala 17:17] + node _T_2236 = and(_T_2235, _T_2221) @[dec_dec_ctl.scala 17:17] + node _T_2237 = and(_T_2236, _T_2223) @[dec_dec_ctl.scala 17:17] + node _T_2238 = and(_T_2237, _T_2224) @[dec_dec_ctl.scala 17:17] + node _T_2239 = and(_T_2238, _T_2226) @[dec_dec_ctl.scala 17:17] + node _T_2240 = and(_T_2239, _T_2227) @[dec_dec_ctl.scala 17:17] + node _T_2241 = and(_T_2240, _T_2229) @[dec_dec_ctl.scala 17:17] + node _T_2242 = or(_T_2213, _T_2241) @[dec_dec_ctl.scala 175:40] + node _T_2243 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2244 = eq(_T_2243, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2245 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2246 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2247 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_2248 = eq(_T_2247, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2249 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_2250 = eq(_T_2249, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2251 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_2252 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_2253 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_2254 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2255 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2256 = eq(_T_2255, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2257 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2258 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2259 = eq(_T_2258, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2260 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2261 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2262 = eq(_T_2261, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2263 = and(_T_2244, _T_2245) @[dec_dec_ctl.scala 17:17] + node _T_2264 = and(_T_2263, _T_2246) @[dec_dec_ctl.scala 17:17] + node _T_2265 = and(_T_2264, _T_2248) @[dec_dec_ctl.scala 17:17] + node _T_2266 = and(_T_2265, _T_2250) @[dec_dec_ctl.scala 17:17] + node _T_2267 = and(_T_2266, _T_2251) @[dec_dec_ctl.scala 17:17] + node _T_2268 = and(_T_2267, _T_2252) @[dec_dec_ctl.scala 17:17] + node _T_2269 = and(_T_2268, _T_2253) @[dec_dec_ctl.scala 17:17] + node _T_2270 = and(_T_2269, _T_2254) @[dec_dec_ctl.scala 17:17] + node _T_2271 = and(_T_2270, _T_2256) @[dec_dec_ctl.scala 17:17] + node _T_2272 = and(_T_2271, _T_2257) @[dec_dec_ctl.scala 17:17] + node _T_2273 = and(_T_2272, _T_2259) @[dec_dec_ctl.scala 17:17] + node _T_2274 = and(_T_2273, _T_2260) @[dec_dec_ctl.scala 17:17] + node _T_2275 = and(_T_2274, _T_2262) @[dec_dec_ctl.scala 17:17] + node _T_2276 = or(_T_2242, _T_2275) @[dec_dec_ctl.scala 175:96] + node _T_2277 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2278 = eq(_T_2277, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2279 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2280 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2281 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_2282 = eq(_T_2281, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2283 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_2284 = eq(_T_2283, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2285 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_2286 = eq(_T_2285, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2287 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_2288 = eq(_T_2287, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2289 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2290 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2291 = eq(_T_2290, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2292 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2293 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2294 = eq(_T_2293, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2295 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2296 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2297 = eq(_T_2296, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2298 = and(_T_2278, _T_2279) @[dec_dec_ctl.scala 17:17] + node _T_2299 = and(_T_2298, _T_2280) @[dec_dec_ctl.scala 17:17] + node _T_2300 = and(_T_2299, _T_2282) @[dec_dec_ctl.scala 17:17] + node _T_2301 = and(_T_2300, _T_2284) @[dec_dec_ctl.scala 17:17] + node _T_2302 = and(_T_2301, _T_2286) @[dec_dec_ctl.scala 17:17] + node _T_2303 = and(_T_2302, _T_2288) @[dec_dec_ctl.scala 17:17] + node _T_2304 = and(_T_2303, _T_2289) @[dec_dec_ctl.scala 17:17] + node _T_2305 = and(_T_2304, _T_2291) @[dec_dec_ctl.scala 17:17] + node _T_2306 = and(_T_2305, _T_2292) @[dec_dec_ctl.scala 17:17] + node _T_2307 = and(_T_2306, _T_2294) @[dec_dec_ctl.scala 17:17] + node _T_2308 = and(_T_2307, _T_2295) @[dec_dec_ctl.scala 17:17] + node _T_2309 = and(_T_2308, _T_2297) @[dec_dec_ctl.scala 17:17] + node _T_2310 = or(_T_2276, _T_2309) @[dec_dec_ctl.scala 176:65] + node _T_2311 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2312 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2313 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2314 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_2315 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_2316 = eq(_T_2315, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2317 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_2318 = eq(_T_2317, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2319 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_2320 = eq(_T_2319, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2321 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2322 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2323 = eq(_T_2322, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2324 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2325 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2326 = eq(_T_2325, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2327 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2328 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2329 = eq(_T_2328, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2330 = and(_T_2311, _T_2312) @[dec_dec_ctl.scala 17:17] + node _T_2331 = and(_T_2330, _T_2313) @[dec_dec_ctl.scala 17:17] + node _T_2332 = and(_T_2331, _T_2314) @[dec_dec_ctl.scala 17:17] + node _T_2333 = and(_T_2332, _T_2316) @[dec_dec_ctl.scala 17:17] + node _T_2334 = and(_T_2333, _T_2318) @[dec_dec_ctl.scala 17:17] + node _T_2335 = and(_T_2334, _T_2320) @[dec_dec_ctl.scala 17:17] + node _T_2336 = and(_T_2335, _T_2321) @[dec_dec_ctl.scala 17:17] + node _T_2337 = and(_T_2336, _T_2323) @[dec_dec_ctl.scala 17:17] + node _T_2338 = and(_T_2337, _T_2324) @[dec_dec_ctl.scala 17:17] + node _T_2339 = and(_T_2338, _T_2326) @[dec_dec_ctl.scala 17:17] + node _T_2340 = and(_T_2339, _T_2327) @[dec_dec_ctl.scala 17:17] + node _T_2341 = and(_T_2340, _T_2329) @[dec_dec_ctl.scala 17:17] + node _T_2342 = or(_T_2310, _T_2341) @[dec_dec_ctl.scala 177:64] + node _T_2343 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2344 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_2345 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2346 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2347 = eq(_T_2346, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2348 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2349 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2350 = eq(_T_2349, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2351 = and(_T_2343, _T_2344) @[dec_dec_ctl.scala 17:17] + node _T_2352 = and(_T_2351, _T_2345) @[dec_dec_ctl.scala 17:17] + node _T_2353 = and(_T_2352, _T_2347) @[dec_dec_ctl.scala 17:17] + node _T_2354 = and(_T_2353, _T_2348) @[dec_dec_ctl.scala 17:17] + node _T_2355 = and(_T_2354, _T_2350) @[dec_dec_ctl.scala 17:17] + node _T_2356 = or(_T_2342, _T_2355) @[dec_dec_ctl.scala 178:62] + io.out.zbb <= _T_2356 @[dec_dec_ctl.scala 172:14] + node _T_2357 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2358 = eq(_T_2357, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2359 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2360 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2361 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2362 = eq(_T_2361, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2363 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2364 = eq(_T_2363, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2365 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2366 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2367 = eq(_T_2366, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2368 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2369 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2370 = eq(_T_2369, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2371 = and(_T_2358, _T_2359) @[dec_dec_ctl.scala 17:17] + node _T_2372 = and(_T_2371, _T_2360) @[dec_dec_ctl.scala 17:17] + node _T_2373 = and(_T_2372, _T_2362) @[dec_dec_ctl.scala 17:17] + node _T_2374 = and(_T_2373, _T_2364) @[dec_dec_ctl.scala 17:17] + node _T_2375 = and(_T_2374, _T_2365) @[dec_dec_ctl.scala 17:17] + node _T_2376 = and(_T_2375, _T_2367) @[dec_dec_ctl.scala 17:17] + node _T_2377 = and(_T_2376, _T_2368) @[dec_dec_ctl.scala 17:17] + node _T_2378 = and(_T_2377, _T_2370) @[dec_dec_ctl.scala 17:17] + io.out.sbset <= _T_2378 @[dec_dec_ctl.scala 180:16] + node _T_2379 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2380 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2381 = eq(_T_2380, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2382 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2383 = eq(_T_2382, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2384 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2385 = eq(_T_2384, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2386 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2387 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2388 = eq(_T_2387, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2389 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2390 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2391 = eq(_T_2390, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2392 = and(_T_2379, _T_2381) @[dec_dec_ctl.scala 17:17] + node _T_2393 = and(_T_2392, _T_2383) @[dec_dec_ctl.scala 17:17] + node _T_2394 = and(_T_2393, _T_2385) @[dec_dec_ctl.scala 17:17] + node _T_2395 = and(_T_2394, _T_2386) @[dec_dec_ctl.scala 17:17] + node _T_2396 = and(_T_2395, _T_2388) @[dec_dec_ctl.scala 17:17] + node _T_2397 = and(_T_2396, _T_2389) @[dec_dec_ctl.scala 17:17] + node _T_2398 = and(_T_2397, _T_2391) @[dec_dec_ctl.scala 17:17] + io.out.sbclr <= _T_2398 @[dec_dec_ctl.scala 182:16] + node _T_2399 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2400 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2401 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2402 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2403 = eq(_T_2402, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2404 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2405 = eq(_T_2404, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2406 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2407 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2408 = eq(_T_2407, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2409 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2410 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2411 = eq(_T_2410, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2412 = and(_T_2399, _T_2400) @[dec_dec_ctl.scala 17:17] + node _T_2413 = and(_T_2412, _T_2401) @[dec_dec_ctl.scala 17:17] + node _T_2414 = and(_T_2413, _T_2403) @[dec_dec_ctl.scala 17:17] + node _T_2415 = and(_T_2414, _T_2405) @[dec_dec_ctl.scala 17:17] + node _T_2416 = and(_T_2415, _T_2406) @[dec_dec_ctl.scala 17:17] + node _T_2417 = and(_T_2416, _T_2408) @[dec_dec_ctl.scala 17:17] + node _T_2418 = and(_T_2417, _T_2409) @[dec_dec_ctl.scala 17:17] + node _T_2419 = and(_T_2418, _T_2411) @[dec_dec_ctl.scala 17:17] + io.out.sbinv <= _T_2419 @[dec_dec_ctl.scala 184:16] + node _T_2420 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2421 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2422 = eq(_T_2421, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2423 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2424 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2425 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2426 = eq(_T_2425, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2427 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2428 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2429 = eq(_T_2428, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2430 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2431 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2432 = eq(_T_2431, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2433 = and(_T_2420, _T_2422) @[dec_dec_ctl.scala 17:17] + node _T_2434 = and(_T_2433, _T_2423) @[dec_dec_ctl.scala 17:17] + node _T_2435 = and(_T_2434, _T_2424) @[dec_dec_ctl.scala 17:17] + node _T_2436 = and(_T_2435, _T_2426) @[dec_dec_ctl.scala 17:17] + node _T_2437 = and(_T_2436, _T_2427) @[dec_dec_ctl.scala 17:17] + node _T_2438 = and(_T_2437, _T_2429) @[dec_dec_ctl.scala 17:17] + node _T_2439 = and(_T_2438, _T_2430) @[dec_dec_ctl.scala 17:17] + node _T_2440 = and(_T_2439, _T_2432) @[dec_dec_ctl.scala 17:17] + io.out.sbext <= _T_2440 @[dec_dec_ctl.scala 186:16] + node _T_2441 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2442 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2443 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2444 = eq(_T_2443, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2445 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2446 = eq(_T_2445, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2447 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2448 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2449 = eq(_T_2448, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2450 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2451 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2452 = eq(_T_2451, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2453 = and(_T_2441, _T_2442) @[dec_dec_ctl.scala 17:17] + node _T_2454 = and(_T_2453, _T_2444) @[dec_dec_ctl.scala 17:17] + node _T_2455 = and(_T_2454, _T_2446) @[dec_dec_ctl.scala 17:17] + node _T_2456 = and(_T_2455, _T_2447) @[dec_dec_ctl.scala 17:17] + node _T_2457 = and(_T_2456, _T_2449) @[dec_dec_ctl.scala 17:17] + node _T_2458 = and(_T_2457, _T_2450) @[dec_dec_ctl.scala 17:17] + node _T_2459 = and(_T_2458, _T_2452) @[dec_dec_ctl.scala 17:17] + node _T_2460 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2461 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2462 = eq(_T_2461, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2463 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2464 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2465 = eq(_T_2464, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2466 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2467 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2468 = eq(_T_2467, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2469 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2470 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2471 = eq(_T_2470, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2472 = and(_T_2460, _T_2462) @[dec_dec_ctl.scala 17:17] + node _T_2473 = and(_T_2472, _T_2463) @[dec_dec_ctl.scala 17:17] + node _T_2474 = and(_T_2473, _T_2465) @[dec_dec_ctl.scala 17:17] + node _T_2475 = and(_T_2474, _T_2466) @[dec_dec_ctl.scala 17:17] + node _T_2476 = and(_T_2475, _T_2468) @[dec_dec_ctl.scala 17:17] + node _T_2477 = and(_T_2476, _T_2469) @[dec_dec_ctl.scala 17:17] + node _T_2478 = and(_T_2477, _T_2471) @[dec_dec_ctl.scala 17:17] + node _T_2479 = or(_T_2459, _T_2478) @[dec_dec_ctl.scala 188:57] + io.out.zbs <= _T_2479 @[dec_dec_ctl.scala 188:14] + node _T_2480 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2481 = eq(_T_2480, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2482 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2483 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2484 = eq(_T_2483, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2485 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2486 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2487 = eq(_T_2486, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2488 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2489 = eq(_T_2488, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2490 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2491 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2492 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2493 = eq(_T_2492, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2494 = and(_T_2481, _T_2482) @[dec_dec_ctl.scala 17:17] + node _T_2495 = and(_T_2494, _T_2484) @[dec_dec_ctl.scala 17:17] + node _T_2496 = and(_T_2495, _T_2485) @[dec_dec_ctl.scala 17:17] + node _T_2497 = and(_T_2496, _T_2487) @[dec_dec_ctl.scala 17:17] + node _T_2498 = and(_T_2497, _T_2489) @[dec_dec_ctl.scala 17:17] + node _T_2499 = and(_T_2498, _T_2490) @[dec_dec_ctl.scala 17:17] + node _T_2500 = and(_T_2499, _T_2491) @[dec_dec_ctl.scala 17:17] + node _T_2501 = and(_T_2500, _T_2493) @[dec_dec_ctl.scala 17:17] + io.out.bext <= _T_2501 @[dec_dec_ctl.scala 190:15] + node _T_2502 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2503 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2504 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2505 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2506 = eq(_T_2505, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2507 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2508 = eq(_T_2507, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2509 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2510 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2511 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2512 = eq(_T_2511, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2513 = and(_T_2502, _T_2503) @[dec_dec_ctl.scala 17:17] + node _T_2514 = and(_T_2513, _T_2504) @[dec_dec_ctl.scala 17:17] + node _T_2515 = and(_T_2514, _T_2506) @[dec_dec_ctl.scala 17:17] + node _T_2516 = and(_T_2515, _T_2508) @[dec_dec_ctl.scala 17:17] + node _T_2517 = and(_T_2516, _T_2509) @[dec_dec_ctl.scala 17:17] + node _T_2518 = and(_T_2517, _T_2510) @[dec_dec_ctl.scala 17:17] + node _T_2519 = and(_T_2518, _T_2512) @[dec_dec_ctl.scala 17:17] + io.out.bdep <= _T_2519 @[dec_dec_ctl.scala 192:15] + node _T_2520 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2521 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2522 = eq(_T_2521, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2523 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2524 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2525 = eq(_T_2524, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2526 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2527 = eq(_T_2526, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2528 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2529 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2530 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2531 = eq(_T_2530, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2532 = and(_T_2520, _T_2522) @[dec_dec_ctl.scala 17:17] + node _T_2533 = and(_T_2532, _T_2523) @[dec_dec_ctl.scala 17:17] + node _T_2534 = and(_T_2533, _T_2525) @[dec_dec_ctl.scala 17:17] + node _T_2535 = and(_T_2534, _T_2527) @[dec_dec_ctl.scala 17:17] + node _T_2536 = and(_T_2535, _T_2528) @[dec_dec_ctl.scala 17:17] + node _T_2537 = and(_T_2536, _T_2529) @[dec_dec_ctl.scala 17:17] + node _T_2538 = and(_T_2537, _T_2531) @[dec_dec_ctl.scala 17:17] + io.out.zbe <= _T_2538 @[dec_dec_ctl.scala 194:14] + node _T_2539 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2540 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_2541 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2542 = eq(_T_2541, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2543 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2544 = eq(_T_2543, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2545 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2546 = eq(_T_2545, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2547 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2548 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2549 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2550 = eq(_T_2549, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2551 = and(_T_2539, _T_2540) @[dec_dec_ctl.scala 17:17] + node _T_2552 = and(_T_2551, _T_2542) @[dec_dec_ctl.scala 17:17] + node _T_2553 = and(_T_2552, _T_2544) @[dec_dec_ctl.scala 17:17] + node _T_2554 = and(_T_2553, _T_2546) @[dec_dec_ctl.scala 17:17] + node _T_2555 = and(_T_2554, _T_2547) @[dec_dec_ctl.scala 17:17] + node _T_2556 = and(_T_2555, _T_2548) @[dec_dec_ctl.scala 17:17] + node _T_2557 = and(_T_2556, _T_2550) @[dec_dec_ctl.scala 17:17] + io.out.clmul <= _T_2557 @[dec_dec_ctl.scala 196:16] + node _T_2558 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2559 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2560 = eq(_T_2559, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2561 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2562 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2563 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2564 = eq(_T_2563, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2565 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2566 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2567 = eq(_T_2566, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2568 = and(_T_2558, _T_2560) @[dec_dec_ctl.scala 17:17] + node _T_2569 = and(_T_2568, _T_2561) @[dec_dec_ctl.scala 17:17] + node _T_2570 = and(_T_2569, _T_2562) @[dec_dec_ctl.scala 17:17] + node _T_2571 = and(_T_2570, _T_2564) @[dec_dec_ctl.scala 17:17] + node _T_2572 = and(_T_2571, _T_2565) @[dec_dec_ctl.scala 17:17] + node _T_2573 = and(_T_2572, _T_2567) @[dec_dec_ctl.scala 17:17] + io.out.clmulh <= _T_2573 @[dec_dec_ctl.scala 198:17] + node _T_2574 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2575 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2576 = eq(_T_2575, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2577 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2578 = eq(_T_2577, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2579 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2580 = eq(_T_2579, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2581 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2582 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2583 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2584 = eq(_T_2583, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2585 = and(_T_2574, _T_2576) @[dec_dec_ctl.scala 17:17] + node _T_2586 = and(_T_2585, _T_2578) @[dec_dec_ctl.scala 17:17] + node _T_2587 = and(_T_2586, _T_2580) @[dec_dec_ctl.scala 17:17] + node _T_2588 = and(_T_2587, _T_2581) @[dec_dec_ctl.scala 17:17] + node _T_2589 = and(_T_2588, _T_2582) @[dec_dec_ctl.scala 17:17] + node _T_2590 = and(_T_2589, _T_2584) @[dec_dec_ctl.scala 17:17] + io.out.clmulr <= _T_2590 @[dec_dec_ctl.scala 200:17] + node _T_2591 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2592 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_2593 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2594 = eq(_T_2593, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2595 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2596 = eq(_T_2595, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2597 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2598 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2599 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2600 = eq(_T_2599, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2601 = and(_T_2591, _T_2592) @[dec_dec_ctl.scala 17:17] + node _T_2602 = and(_T_2601, _T_2594) @[dec_dec_ctl.scala 17:17] + node _T_2603 = and(_T_2602, _T_2596) @[dec_dec_ctl.scala 17:17] + node _T_2604 = and(_T_2603, _T_2597) @[dec_dec_ctl.scala 17:17] + node _T_2605 = and(_T_2604, _T_2598) @[dec_dec_ctl.scala 17:17] + node _T_2606 = and(_T_2605, _T_2600) @[dec_dec_ctl.scala 17:17] + io.out.zbc <= _T_2606 @[dec_dec_ctl.scala 202:14] + node _T_2607 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2608 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2609 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2610 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2611 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2612 = eq(_T_2611, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2613 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2614 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2615 = eq(_T_2614, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2616 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2617 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2618 = eq(_T_2617, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2619 = and(_T_2607, _T_2608) @[dec_dec_ctl.scala 17:17] + node _T_2620 = and(_T_2619, _T_2609) @[dec_dec_ctl.scala 17:17] + node _T_2621 = and(_T_2620, _T_2610) @[dec_dec_ctl.scala 17:17] + node _T_2622 = and(_T_2621, _T_2612) @[dec_dec_ctl.scala 17:17] + node _T_2623 = and(_T_2622, _T_2613) @[dec_dec_ctl.scala 17:17] + node _T_2624 = and(_T_2623, _T_2615) @[dec_dec_ctl.scala 17:17] + node _T_2625 = and(_T_2624, _T_2616) @[dec_dec_ctl.scala 17:17] + node _T_2626 = and(_T_2625, _T_2618) @[dec_dec_ctl.scala 17:17] + io.out.grev <= _T_2626 @[dec_dec_ctl.scala 204:15] + node _T_2627 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2628 = eq(_T_2627, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2629 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2630 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2631 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2632 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2633 = eq(_T_2632, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2634 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2635 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2636 = eq(_T_2635, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2637 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2638 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2639 = eq(_T_2638, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2640 = and(_T_2628, _T_2629) @[dec_dec_ctl.scala 17:17] + node _T_2641 = and(_T_2640, _T_2630) @[dec_dec_ctl.scala 17:17] + node _T_2642 = and(_T_2641, _T_2631) @[dec_dec_ctl.scala 17:17] + node _T_2643 = and(_T_2642, _T_2633) @[dec_dec_ctl.scala 17:17] + node _T_2644 = and(_T_2643, _T_2634) @[dec_dec_ctl.scala 17:17] + node _T_2645 = and(_T_2644, _T_2636) @[dec_dec_ctl.scala 17:17] + node _T_2646 = and(_T_2645, _T_2637) @[dec_dec_ctl.scala 17:17] + node _T_2647 = and(_T_2646, _T_2639) @[dec_dec_ctl.scala 17:17] + io.out.gorc <= _T_2647 @[dec_dec_ctl.scala 206:15] + node _T_2648 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2649 = eq(_T_2648, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2650 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2651 = eq(_T_2650, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2652 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2653 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2654 = eq(_T_2653, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2655 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2656 = eq(_T_2655, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2657 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2658 = eq(_T_2657, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2659 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2660 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2661 = eq(_T_2660, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2662 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2663 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2664 = eq(_T_2663, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2665 = and(_T_2649, _T_2651) @[dec_dec_ctl.scala 17:17] + node _T_2666 = and(_T_2665, _T_2652) @[dec_dec_ctl.scala 17:17] + node _T_2667 = and(_T_2666, _T_2654) @[dec_dec_ctl.scala 17:17] + node _T_2668 = and(_T_2667, _T_2656) @[dec_dec_ctl.scala 17:17] + node _T_2669 = and(_T_2668, _T_2658) @[dec_dec_ctl.scala 17:17] + node _T_2670 = and(_T_2669, _T_2659) @[dec_dec_ctl.scala 17:17] + node _T_2671 = and(_T_2670, _T_2661) @[dec_dec_ctl.scala 17:17] + node _T_2672 = and(_T_2671, _T_2662) @[dec_dec_ctl.scala 17:17] + node _T_2673 = and(_T_2672, _T_2664) @[dec_dec_ctl.scala 17:17] + io.out.shfl <= _T_2673 @[dec_dec_ctl.scala 208:15] + node _T_2674 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2675 = eq(_T_2674, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2676 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2677 = eq(_T_2676, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2678 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2679 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2680 = eq(_T_2679, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2681 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2682 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2683 = eq(_T_2682, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2684 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2685 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2686 = eq(_T_2685, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2687 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2688 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2689 = eq(_T_2688, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2690 = and(_T_2675, _T_2677) @[dec_dec_ctl.scala 17:17] + node _T_2691 = and(_T_2690, _T_2678) @[dec_dec_ctl.scala 17:17] + node _T_2692 = and(_T_2691, _T_2680) @[dec_dec_ctl.scala 17:17] + node _T_2693 = and(_T_2692, _T_2681) @[dec_dec_ctl.scala 17:17] + node _T_2694 = and(_T_2693, _T_2683) @[dec_dec_ctl.scala 17:17] + node _T_2695 = and(_T_2694, _T_2684) @[dec_dec_ctl.scala 17:17] + node _T_2696 = and(_T_2695, _T_2686) @[dec_dec_ctl.scala 17:17] + node _T_2697 = and(_T_2696, _T_2687) @[dec_dec_ctl.scala 17:17] + node _T_2698 = and(_T_2697, _T_2689) @[dec_dec_ctl.scala 17:17] + io.out.unshfl <= _T_2698 @[dec_dec_ctl.scala 210:17] + node _T_2699 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2700 = eq(_T_2699, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2701 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2702 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2703 = eq(_T_2702, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2704 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2705 = eq(_T_2704, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2706 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2707 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2708 = eq(_T_2707, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2709 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2710 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2711 = eq(_T_2710, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2712 = and(_T_2700, _T_2701) @[dec_dec_ctl.scala 17:17] + node _T_2713 = and(_T_2712, _T_2703) @[dec_dec_ctl.scala 17:17] + node _T_2714 = and(_T_2713, _T_2705) @[dec_dec_ctl.scala 17:17] + node _T_2715 = and(_T_2714, _T_2706) @[dec_dec_ctl.scala 17:17] + node _T_2716 = and(_T_2715, _T_2708) @[dec_dec_ctl.scala 17:17] + node _T_2717 = and(_T_2716, _T_2709) @[dec_dec_ctl.scala 17:17] + node _T_2718 = and(_T_2717, _T_2711) @[dec_dec_ctl.scala 17:17] + node _T_2719 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2720 = eq(_T_2719, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2721 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2722 = eq(_T_2721, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2723 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2724 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2725 = eq(_T_2724, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2726 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2727 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2728 = eq(_T_2727, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2729 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2730 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2731 = eq(_T_2730, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2732 = and(_T_2720, _T_2722) @[dec_dec_ctl.scala 17:17] + node _T_2733 = and(_T_2732, _T_2723) @[dec_dec_ctl.scala 17:17] + node _T_2734 = and(_T_2733, _T_2725) @[dec_dec_ctl.scala 17:17] + node _T_2735 = and(_T_2734, _T_2726) @[dec_dec_ctl.scala 17:17] + node _T_2736 = and(_T_2735, _T_2728) @[dec_dec_ctl.scala 17:17] + node _T_2737 = and(_T_2736, _T_2729) @[dec_dec_ctl.scala 17:17] + node _T_2738 = and(_T_2737, _T_2731) @[dec_dec_ctl.scala 17:17] + node _T_2739 = or(_T_2718, _T_2738) @[dec_dec_ctl.scala 212:58] + node _T_2740 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2741 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2742 = eq(_T_2741, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2743 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_2744 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2745 = eq(_T_2744, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2746 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2747 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2748 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2749 = eq(_T_2748, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2750 = and(_T_2740, _T_2742) @[dec_dec_ctl.scala 17:17] + node _T_2751 = and(_T_2750, _T_2743) @[dec_dec_ctl.scala 17:17] + node _T_2752 = and(_T_2751, _T_2745) @[dec_dec_ctl.scala 17:17] + node _T_2753 = and(_T_2752, _T_2746) @[dec_dec_ctl.scala 17:17] + node _T_2754 = and(_T_2753, _T_2747) @[dec_dec_ctl.scala 17:17] + node _T_2755 = and(_T_2754, _T_2749) @[dec_dec_ctl.scala 17:17] + node _T_2756 = or(_T_2739, _T_2755) @[dec_dec_ctl.scala 212:101] + node _T_2757 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2758 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2759 = eq(_T_2758, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2760 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2761 = eq(_T_2760, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2762 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2763 = eq(_T_2762, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2764 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2765 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2766 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2767 = eq(_T_2766, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2768 = and(_T_2757, _T_2759) @[dec_dec_ctl.scala 17:17] + node _T_2769 = and(_T_2768, _T_2761) @[dec_dec_ctl.scala 17:17] + node _T_2770 = and(_T_2769, _T_2763) @[dec_dec_ctl.scala 17:17] + node _T_2771 = and(_T_2770, _T_2764) @[dec_dec_ctl.scala 17:17] + node _T_2772 = and(_T_2771, _T_2765) @[dec_dec_ctl.scala 17:17] + node _T_2773 = and(_T_2772, _T_2767) @[dec_dec_ctl.scala 17:17] + node _T_2774 = or(_T_2756, _T_2773) @[dec_dec_ctl.scala 213:40] + node _T_2775 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2776 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2777 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2778 = eq(_T_2777, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2779 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_2780 = eq(_T_2779, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2781 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2782 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2783 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2784 = eq(_T_2783, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2785 = and(_T_2775, _T_2776) @[dec_dec_ctl.scala 17:17] + node _T_2786 = and(_T_2785, _T_2778) @[dec_dec_ctl.scala 17:17] + node _T_2787 = and(_T_2786, _T_2780) @[dec_dec_ctl.scala 17:17] + node _T_2788 = and(_T_2787, _T_2781) @[dec_dec_ctl.scala 17:17] + node _T_2789 = and(_T_2788, _T_2782) @[dec_dec_ctl.scala 17:17] + node _T_2790 = and(_T_2789, _T_2784) @[dec_dec_ctl.scala 17:17] + node _T_2791 = or(_T_2774, _T_2790) @[dec_dec_ctl.scala 213:79] + node _T_2792 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2793 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2794 = eq(_T_2793, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2795 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2796 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2797 = eq(_T_2796, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2798 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2799 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2800 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2801 = eq(_T_2800, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2802 = and(_T_2792, _T_2794) @[dec_dec_ctl.scala 17:17] + node _T_2803 = and(_T_2802, _T_2795) @[dec_dec_ctl.scala 17:17] + node _T_2804 = and(_T_2803, _T_2797) @[dec_dec_ctl.scala 17:17] + node _T_2805 = and(_T_2804, _T_2798) @[dec_dec_ctl.scala 17:17] + node _T_2806 = and(_T_2805, _T_2799) @[dec_dec_ctl.scala 17:17] + node _T_2807 = and(_T_2806, _T_2801) @[dec_dec_ctl.scala 17:17] + node _T_2808 = or(_T_2791, _T_2807) @[dec_dec_ctl.scala 214:41] + node _T_2809 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_2810 = eq(_T_2809, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2811 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_2812 = eq(_T_2811, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2813 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_2814 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_2815 = eq(_T_2814, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2816 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2817 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2818 = eq(_T_2817, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2819 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_2820 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2821 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2822 = eq(_T_2821, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2823 = and(_T_2810, _T_2812) @[dec_dec_ctl.scala 17:17] + node _T_2824 = and(_T_2823, _T_2813) @[dec_dec_ctl.scala 17:17] + node _T_2825 = and(_T_2824, _T_2815) @[dec_dec_ctl.scala 17:17] + node _T_2826 = and(_T_2825, _T_2816) @[dec_dec_ctl.scala 17:17] + node _T_2827 = and(_T_2826, _T_2818) @[dec_dec_ctl.scala 17:17] + node _T_2828 = and(_T_2827, _T_2819) @[dec_dec_ctl.scala 17:17] + node _T_2829 = and(_T_2828, _T_2820) @[dec_dec_ctl.scala 17:17] + node _T_2830 = and(_T_2829, _T_2822) @[dec_dec_ctl.scala 17:17] + node _T_2831 = or(_T_2808, _T_2830) @[dec_dec_ctl.scala 214:78] + node _T_2832 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_2833 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_2834 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2835 = eq(_T_2834, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2836 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2837 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_2838 = eq(_T_2837, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2839 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2840 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2841 = eq(_T_2840, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2842 = and(_T_2832, _T_2833) @[dec_dec_ctl.scala 17:17] + node _T_2843 = and(_T_2842, _T_2835) @[dec_dec_ctl.scala 17:17] + node _T_2844 = and(_T_2843, _T_2836) @[dec_dec_ctl.scala 17:17] + node _T_2845 = and(_T_2844, _T_2838) @[dec_dec_ctl.scala 17:17] + node _T_2846 = and(_T_2845, _T_2839) @[dec_dec_ctl.scala 17:17] + node _T_2847 = and(_T_2846, _T_2841) @[dec_dec_ctl.scala 17:17] + node _T_2848 = or(_T_2831, _T_2847) @[dec_dec_ctl.scala 215:48] + io.out.zbp <= _T_2848 @[dec_dec_ctl.scala 212:14] + node _T_2849 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2850 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2851 = eq(_T_2850, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2852 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2853 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_2854 = eq(_T_2853, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2855 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_2856 = eq(_T_2855, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2857 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_2858 = eq(_T_2857, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2859 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2860 = eq(_T_2859, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2861 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2862 = eq(_T_2861, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2863 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2864 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2865 = eq(_T_2864, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2866 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2867 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2868 = eq(_T_2867, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2869 = and(_T_2849, _T_2851) @[dec_dec_ctl.scala 17:17] + node _T_2870 = and(_T_2869, _T_2852) @[dec_dec_ctl.scala 17:17] + node _T_2871 = and(_T_2870, _T_2854) @[dec_dec_ctl.scala 17:17] + node _T_2872 = and(_T_2871, _T_2856) @[dec_dec_ctl.scala 17:17] + node _T_2873 = and(_T_2872, _T_2858) @[dec_dec_ctl.scala 17:17] + node _T_2874 = and(_T_2873, _T_2860) @[dec_dec_ctl.scala 17:17] + node _T_2875 = and(_T_2874, _T_2862) @[dec_dec_ctl.scala 17:17] + node _T_2876 = and(_T_2875, _T_2863) @[dec_dec_ctl.scala 17:17] + node _T_2877 = and(_T_2876, _T_2865) @[dec_dec_ctl.scala 17:17] + node _T_2878 = and(_T_2877, _T_2866) @[dec_dec_ctl.scala 17:17] + node _T_2879 = and(_T_2878, _T_2868) @[dec_dec_ctl.scala 17:17] + io.out.crc32_b <= _T_2879 @[dec_dec_ctl.scala 217:18] + node _T_2880 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2881 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2882 = eq(_T_2881, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2883 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2884 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_2885 = eq(_T_2884, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2886 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_2887 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2888 = eq(_T_2887, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2889 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2890 = eq(_T_2889, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2891 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2892 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2893 = eq(_T_2892, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2894 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2895 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2896 = eq(_T_2895, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2897 = and(_T_2880, _T_2882) @[dec_dec_ctl.scala 17:17] + node _T_2898 = and(_T_2897, _T_2883) @[dec_dec_ctl.scala 17:17] + node _T_2899 = and(_T_2898, _T_2885) @[dec_dec_ctl.scala 17:17] + node _T_2900 = and(_T_2899, _T_2886) @[dec_dec_ctl.scala 17:17] + node _T_2901 = and(_T_2900, _T_2888) @[dec_dec_ctl.scala 17:17] + node _T_2902 = and(_T_2901, _T_2890) @[dec_dec_ctl.scala 17:17] + node _T_2903 = and(_T_2902, _T_2891) @[dec_dec_ctl.scala 17:17] + node _T_2904 = and(_T_2903, _T_2893) @[dec_dec_ctl.scala 17:17] + node _T_2905 = and(_T_2904, _T_2894) @[dec_dec_ctl.scala 17:17] + node _T_2906 = and(_T_2905, _T_2896) @[dec_dec_ctl.scala 17:17] + io.out.crc32_h <= _T_2906 @[dec_dec_ctl.scala 219:18] + node _T_2907 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2908 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2909 = eq(_T_2908, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2910 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_2911 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_2912 = eq(_T_2911, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2913 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_2914 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2915 = eq(_T_2914, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2916 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2917 = eq(_T_2916, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2918 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2919 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2920 = eq(_T_2919, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2921 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2922 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2923 = eq(_T_2922, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2924 = and(_T_2907, _T_2909) @[dec_dec_ctl.scala 17:17] + node _T_2925 = and(_T_2924, _T_2910) @[dec_dec_ctl.scala 17:17] + node _T_2926 = and(_T_2925, _T_2912) @[dec_dec_ctl.scala 17:17] + node _T_2927 = and(_T_2926, _T_2913) @[dec_dec_ctl.scala 17:17] + node _T_2928 = and(_T_2927, _T_2915) @[dec_dec_ctl.scala 17:17] + node _T_2929 = and(_T_2928, _T_2917) @[dec_dec_ctl.scala 17:17] + node _T_2930 = and(_T_2929, _T_2918) @[dec_dec_ctl.scala 17:17] + node _T_2931 = and(_T_2930, _T_2920) @[dec_dec_ctl.scala 17:17] + node _T_2932 = and(_T_2931, _T_2921) @[dec_dec_ctl.scala 17:17] + node _T_2933 = and(_T_2932, _T_2923) @[dec_dec_ctl.scala 17:17] + io.out.crc32_w <= _T_2933 @[dec_dec_ctl.scala 221:18] + node _T_2934 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2935 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2936 = eq(_T_2935, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2937 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_2938 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_2939 = eq(_T_2938, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2940 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_2941 = eq(_T_2940, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2942 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2943 = eq(_T_2942, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2944 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2945 = eq(_T_2944, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2946 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2947 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2948 = eq(_T_2947, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2949 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2950 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2951 = eq(_T_2950, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2952 = and(_T_2934, _T_2936) @[dec_dec_ctl.scala 17:17] + node _T_2953 = and(_T_2952, _T_2937) @[dec_dec_ctl.scala 17:17] + node _T_2954 = and(_T_2953, _T_2939) @[dec_dec_ctl.scala 17:17] + node _T_2955 = and(_T_2954, _T_2941) @[dec_dec_ctl.scala 17:17] + node _T_2956 = and(_T_2955, _T_2943) @[dec_dec_ctl.scala 17:17] + node _T_2957 = and(_T_2956, _T_2945) @[dec_dec_ctl.scala 17:17] + node _T_2958 = and(_T_2957, _T_2946) @[dec_dec_ctl.scala 17:17] + node _T_2959 = and(_T_2958, _T_2948) @[dec_dec_ctl.scala 17:17] + node _T_2960 = and(_T_2959, _T_2949) @[dec_dec_ctl.scala 17:17] + node _T_2961 = and(_T_2960, _T_2951) @[dec_dec_ctl.scala 17:17] + io.out.crc32c_b <= _T_2961 @[dec_dec_ctl.scala 223:19] + node _T_2962 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2963 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2964 = eq(_T_2963, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2965 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_2966 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_2967 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2968 = eq(_T_2967, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2969 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2970 = eq(_T_2969, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2971 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2972 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2973 = eq(_T_2972, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2974 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2975 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_2976 = eq(_T_2975, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2977 = and(_T_2962, _T_2964) @[dec_dec_ctl.scala 17:17] + node _T_2978 = and(_T_2977, _T_2965) @[dec_dec_ctl.scala 17:17] + node _T_2979 = and(_T_2978, _T_2966) @[dec_dec_ctl.scala 17:17] + node _T_2980 = and(_T_2979, _T_2968) @[dec_dec_ctl.scala 17:17] + node _T_2981 = and(_T_2980, _T_2970) @[dec_dec_ctl.scala 17:17] + node _T_2982 = and(_T_2981, _T_2971) @[dec_dec_ctl.scala 17:17] + node _T_2983 = and(_T_2982, _T_2973) @[dec_dec_ctl.scala 17:17] + node _T_2984 = and(_T_2983, _T_2974) @[dec_dec_ctl.scala 17:17] + node _T_2985 = and(_T_2984, _T_2976) @[dec_dec_ctl.scala 17:17] + io.out.crc32c_h <= _T_2985 @[dec_dec_ctl.scala 225:19] + node _T_2986 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_2987 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_2988 = eq(_T_2987, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2989 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34] + node _T_2990 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_2991 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_2992 = eq(_T_2991, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2993 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_2994 = eq(_T_2993, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2995 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_2996 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_2997 = eq(_T_2996, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_2998 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_2999 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3000 = eq(_T_2999, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3001 = and(_T_2986, _T_2988) @[dec_dec_ctl.scala 17:17] + node _T_3002 = and(_T_3001, _T_2989) @[dec_dec_ctl.scala 17:17] + node _T_3003 = and(_T_3002, _T_2990) @[dec_dec_ctl.scala 17:17] + node _T_3004 = and(_T_3003, _T_2992) @[dec_dec_ctl.scala 17:17] + node _T_3005 = and(_T_3004, _T_2994) @[dec_dec_ctl.scala 17:17] + node _T_3006 = and(_T_3005, _T_2995) @[dec_dec_ctl.scala 17:17] + node _T_3007 = and(_T_3006, _T_2997) @[dec_dec_ctl.scala 17:17] + node _T_3008 = and(_T_3007, _T_2998) @[dec_dec_ctl.scala 17:17] + node _T_3009 = and(_T_3008, _T_3000) @[dec_dec_ctl.scala 17:17] + io.out.crc32c_w <= _T_3009 @[dec_dec_ctl.scala 227:19] + node _T_3010 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_3011 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3012 = eq(_T_3011, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3013 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_3014 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3015 = eq(_T_3014, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3016 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3017 = eq(_T_3016, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3018 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_3019 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3020 = eq(_T_3019, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3021 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3022 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3023 = eq(_T_3022, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3024 = and(_T_3010, _T_3012) @[dec_dec_ctl.scala 17:17] + node _T_3025 = and(_T_3024, _T_3013) @[dec_dec_ctl.scala 17:17] + node _T_3026 = and(_T_3025, _T_3015) @[dec_dec_ctl.scala 17:17] + node _T_3027 = and(_T_3026, _T_3017) @[dec_dec_ctl.scala 17:17] + node _T_3028 = and(_T_3027, _T_3018) @[dec_dec_ctl.scala 17:17] + node _T_3029 = and(_T_3028, _T_3020) @[dec_dec_ctl.scala 17:17] + node _T_3030 = and(_T_3029, _T_3021) @[dec_dec_ctl.scala 17:17] + node _T_3031 = and(_T_3030, _T_3023) @[dec_dec_ctl.scala 17:17] + io.out.zbr <= _T_3031 @[dec_dec_ctl.scala 229:14] + node _T_3032 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_3033 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_3034 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_3035 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_3036 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3037 = eq(_T_3036, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3038 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3039 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3040 = eq(_T_3039, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3041 = and(_T_3032, _T_3033) @[dec_dec_ctl.scala 17:17] + node _T_3042 = and(_T_3041, _T_3034) @[dec_dec_ctl.scala 17:17] + node _T_3043 = and(_T_3042, _T_3035) @[dec_dec_ctl.scala 17:17] + node _T_3044 = and(_T_3043, _T_3037) @[dec_dec_ctl.scala 17:17] + node _T_3045 = and(_T_3044, _T_3038) @[dec_dec_ctl.scala 17:17] + node _T_3046 = and(_T_3045, _T_3040) @[dec_dec_ctl.scala 17:17] + io.out.bfp <= _T_3046 @[dec_dec_ctl.scala 231:14] + node _T_3047 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_3048 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_3049 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_3050 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_3051 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3052 = eq(_T_3051, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3053 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3054 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3055 = eq(_T_3054, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3056 = and(_T_3047, _T_3048) @[dec_dec_ctl.scala 17:17] + node _T_3057 = and(_T_3056, _T_3049) @[dec_dec_ctl.scala 17:17] + node _T_3058 = and(_T_3057, _T_3050) @[dec_dec_ctl.scala 17:17] + node _T_3059 = and(_T_3058, _T_3052) @[dec_dec_ctl.scala 17:17] + node _T_3060 = and(_T_3059, _T_3053) @[dec_dec_ctl.scala 17:17] + node _T_3061 = and(_T_3060, _T_3055) @[dec_dec_ctl.scala 17:17] + io.out.zbf <= _T_3061 @[dec_dec_ctl.scala 233:14] + node _T_3062 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3063 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3064 = eq(_T_3063, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3065 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3066 = eq(_T_3065, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3067 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3068 = eq(_T_3067, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3069 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3070 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3071 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3072 = eq(_T_3071, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3073 = and(_T_3062, _T_3064) @[dec_dec_ctl.scala 17:17] + node _T_3074 = and(_T_3073, _T_3066) @[dec_dec_ctl.scala 17:17] + node _T_3075 = and(_T_3074, _T_3068) @[dec_dec_ctl.scala 17:17] + node _T_3076 = and(_T_3075, _T_3069) @[dec_dec_ctl.scala 17:17] + node _T_3077 = and(_T_3076, _T_3070) @[dec_dec_ctl.scala 17:17] + node _T_3078 = and(_T_3077, _T_3072) @[dec_dec_ctl.scala 17:17] + io.out.sh1add <= _T_3078 @[dec_dec_ctl.scala 235:17] + node _T_3079 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3080 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_3081 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3082 = eq(_T_3081, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3083 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3084 = eq(_T_3083, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3085 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3086 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3087 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3088 = eq(_T_3087, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3089 = and(_T_3079, _T_3080) @[dec_dec_ctl.scala 17:17] + node _T_3090 = and(_T_3089, _T_3082) @[dec_dec_ctl.scala 17:17] + node _T_3091 = and(_T_3090, _T_3084) @[dec_dec_ctl.scala 17:17] + node _T_3092 = and(_T_3091, _T_3085) @[dec_dec_ctl.scala 17:17] + node _T_3093 = and(_T_3092, _T_3086) @[dec_dec_ctl.scala 17:17] + node _T_3094 = and(_T_3093, _T_3088) @[dec_dec_ctl.scala 17:17] + io.out.sh2add <= _T_3094 @[dec_dec_ctl.scala 237:17] + node _T_3095 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3096 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_3097 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_3098 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3099 = eq(_T_3098, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3100 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3101 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3102 = eq(_T_3101, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3103 = and(_T_3095, _T_3096) @[dec_dec_ctl.scala 17:17] + node _T_3104 = and(_T_3103, _T_3097) @[dec_dec_ctl.scala 17:17] + node _T_3105 = and(_T_3104, _T_3099) @[dec_dec_ctl.scala 17:17] + node _T_3106 = and(_T_3105, _T_3100) @[dec_dec_ctl.scala 17:17] + node _T_3107 = and(_T_3106, _T_3102) @[dec_dec_ctl.scala 17:17] + io.out.sh3add <= _T_3107 @[dec_dec_ctl.scala 239:17] + node _T_3108 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3109 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3110 = eq(_T_3109, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3111 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3112 = eq(_T_3111, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3113 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3114 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3115 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3116 = eq(_T_3115, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3117 = and(_T_3108, _T_3110) @[dec_dec_ctl.scala 17:17] + node _T_3118 = and(_T_3117, _T_3112) @[dec_dec_ctl.scala 17:17] + node _T_3119 = and(_T_3118, _T_3113) @[dec_dec_ctl.scala 17:17] + node _T_3120 = and(_T_3119, _T_3114) @[dec_dec_ctl.scala 17:17] + node _T_3121 = and(_T_3120, _T_3116) @[dec_dec_ctl.scala 17:17] + io.out.zba <= _T_3121 @[dec_dec_ctl.scala 241:14] + node _T_3122 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:34] + node _T_3123 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_3124 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3125 = eq(_T_3124, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3126 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3127 = eq(_T_3126, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3128 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3129 = and(_T_3122, _T_3123) @[dec_dec_ctl.scala 17:17] + node _T_3130 = and(_T_3129, _T_3125) @[dec_dec_ctl.scala 17:17] + node _T_3131 = and(_T_3130, _T_3127) @[dec_dec_ctl.scala 17:17] + node _T_3132 = and(_T_3131, _T_3128) @[dec_dec_ctl.scala 17:17] + node _T_3133 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3134 = eq(_T_3133, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3135 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3136 = eq(_T_3135, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3137 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3138 = eq(_T_3137, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3139 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3140 = eq(_T_3139, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3141 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3142 = eq(_T_3141, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3143 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3144 = and(_T_3134, _T_3136) @[dec_dec_ctl.scala 17:17] + node _T_3145 = and(_T_3144, _T_3138) @[dec_dec_ctl.scala 17:17] + node _T_3146 = and(_T_3145, _T_3140) @[dec_dec_ctl.scala 17:17] + node _T_3147 = and(_T_3146, _T_3142) @[dec_dec_ctl.scala 17:17] + node _T_3148 = and(_T_3147, _T_3143) @[dec_dec_ctl.scala 17:17] + node _T_3149 = or(_T_3132, _T_3148) @[dec_dec_ctl.scala 243:51] + node _T_3150 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3151 = eq(_T_3150, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3152 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3153 = eq(_T_3152, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3154 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3155 = eq(_T_3154, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3156 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3157 = eq(_T_3156, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3158 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_3159 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3160 = eq(_T_3159, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3161 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3162 = and(_T_3151, _T_3153) @[dec_dec_ctl.scala 17:17] + node _T_3163 = and(_T_3162, _T_3155) @[dec_dec_ctl.scala 17:17] + node _T_3164 = and(_T_3163, _T_3157) @[dec_dec_ctl.scala 17:17] + node _T_3165 = and(_T_3164, _T_3158) @[dec_dec_ctl.scala 17:17] + node _T_3166 = and(_T_3165, _T_3160) @[dec_dec_ctl.scala 17:17] + node _T_3167 = and(_T_3166, _T_3161) @[dec_dec_ctl.scala 17:17] + node _T_3168 = or(_T_3149, _T_3167) @[dec_dec_ctl.scala 243:89] + node _T_3169 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3170 = eq(_T_3169, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3171 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3172 = eq(_T_3171, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3173 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3174 = eq(_T_3173, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3175 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3176 = eq(_T_3175, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3177 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3178 = eq(_T_3177, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3179 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3180 = and(_T_3170, _T_3172) @[dec_dec_ctl.scala 17:17] + node _T_3181 = and(_T_3180, _T_3174) @[dec_dec_ctl.scala 17:17] + node _T_3182 = and(_T_3181, _T_3176) @[dec_dec_ctl.scala 17:17] + node _T_3183 = and(_T_3182, _T_3178) @[dec_dec_ctl.scala 17:17] + node _T_3184 = and(_T_3183, _T_3179) @[dec_dec_ctl.scala 17:17] + node _T_3185 = or(_T_3168, _T_3184) @[dec_dec_ctl.scala 244:44] + node _T_3186 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_3187 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3188 = eq(_T_3187, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3189 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3190 = and(_T_3186, _T_3188) @[dec_dec_ctl.scala 17:17] + node _T_3191 = and(_T_3190, _T_3189) @[dec_dec_ctl.scala 17:17] + node _T_3192 = or(_T_3185, _T_3191) @[dec_dec_ctl.scala 244:82] + node _T_3193 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3194 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_3195 = and(_T_3193, _T_3194) @[dec_dec_ctl.scala 17:17] + node _T_3196 = or(_T_3192, _T_3195) @[dec_dec_ctl.scala 245:28] + node _T_3197 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3198 = eq(_T_3197, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3199 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3200 = eq(_T_3199, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3201 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3202 = and(_T_3198, _T_3200) @[dec_dec_ctl.scala 17:17] + node _T_3203 = and(_T_3202, _T_3201) @[dec_dec_ctl.scala 17:17] + node _T_3204 = or(_T_3196, _T_3203) @[dec_dec_ctl.scala 245:49] + io.out.pm_alu <= _T_3204 @[dec_dec_ctl.scala 243:17] + node _T_3205 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3206 = eq(_T_3205, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3207 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3208 = eq(_T_3207, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3209 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3210 = eq(_T_3209, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3211 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:34] + node _T_3212 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3213 = eq(_T_3212, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3214 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3215 = eq(_T_3214, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3216 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3217 = eq(_T_3216, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3218 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_3219 = eq(_T_3218, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3220 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_3221 = eq(_T_3220, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3222 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34] + node _T_3223 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_3224 = eq(_T_3223, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3225 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34] + node _T_3226 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53] + node _T_3227 = eq(_T_3226, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3228 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53] + node _T_3229 = eq(_T_3228, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3230 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53] + node _T_3231 = eq(_T_3230, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3232 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53] + node _T_3233 = eq(_T_3232, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3234 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53] + node _T_3235 = eq(_T_3234, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3236 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3237 = eq(_T_3236, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3238 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53] + node _T_3239 = eq(_T_3238, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3240 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53] + node _T_3241 = eq(_T_3240, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3242 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53] + node _T_3243 = eq(_T_3242, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3244 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53] + node _T_3245 = eq(_T_3244, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3246 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53] + node _T_3247 = eq(_T_3246, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3248 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_3249 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3250 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3251 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3252 = eq(_T_3251, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3253 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3254 = eq(_T_3253, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3255 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3256 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3257 = and(_T_3206, _T_3208) @[dec_dec_ctl.scala 17:17] + node _T_3258 = and(_T_3257, _T_3210) @[dec_dec_ctl.scala 17:17] + node _T_3259 = and(_T_3258, _T_3211) @[dec_dec_ctl.scala 17:17] + node _T_3260 = and(_T_3259, _T_3213) @[dec_dec_ctl.scala 17:17] + node _T_3261 = and(_T_3260, _T_3215) @[dec_dec_ctl.scala 17:17] + node _T_3262 = and(_T_3261, _T_3217) @[dec_dec_ctl.scala 17:17] + node _T_3263 = and(_T_3262, _T_3219) @[dec_dec_ctl.scala 17:17] + node _T_3264 = and(_T_3263, _T_3221) @[dec_dec_ctl.scala 17:17] + node _T_3265 = and(_T_3264, _T_3222) @[dec_dec_ctl.scala 17:17] + node _T_3266 = and(_T_3265, _T_3224) @[dec_dec_ctl.scala 17:17] + node _T_3267 = and(_T_3266, _T_3225) @[dec_dec_ctl.scala 17:17] + node _T_3268 = and(_T_3267, _T_3227) @[dec_dec_ctl.scala 17:17] + node _T_3269 = and(_T_3268, _T_3229) @[dec_dec_ctl.scala 17:17] + node _T_3270 = and(_T_3269, _T_3231) @[dec_dec_ctl.scala 17:17] + node _T_3271 = and(_T_3270, _T_3233) @[dec_dec_ctl.scala 17:17] + node _T_3272 = and(_T_3271, _T_3235) @[dec_dec_ctl.scala 17:17] + node _T_3273 = and(_T_3272, _T_3237) @[dec_dec_ctl.scala 17:17] + node _T_3274 = and(_T_3273, _T_3239) @[dec_dec_ctl.scala 17:17] + node _T_3275 = and(_T_3274, _T_3241) @[dec_dec_ctl.scala 17:17] + node _T_3276 = and(_T_3275, _T_3243) @[dec_dec_ctl.scala 17:17] + node _T_3277 = and(_T_3276, _T_3245) @[dec_dec_ctl.scala 17:17] + node _T_3278 = and(_T_3277, _T_3247) @[dec_dec_ctl.scala 17:17] + node _T_3279 = and(_T_3278, _T_3248) @[dec_dec_ctl.scala 17:17] + node _T_3280 = and(_T_3279, _T_3249) @[dec_dec_ctl.scala 17:17] + node _T_3281 = and(_T_3280, _T_3250) @[dec_dec_ctl.scala 17:17] + node _T_3282 = and(_T_3281, _T_3252) @[dec_dec_ctl.scala 17:17] + node _T_3283 = and(_T_3282, _T_3254) @[dec_dec_ctl.scala 17:17] + node _T_3284 = and(_T_3283, _T_3255) @[dec_dec_ctl.scala 17:17] + node _T_3285 = and(_T_3284, _T_3256) @[dec_dec_ctl.scala 17:17] + node _T_3286 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3287 = eq(_T_3286, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3288 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3289 = eq(_T_3288, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3290 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3291 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:34] + node _T_3292 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3293 = eq(_T_3292, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3294 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3295 = eq(_T_3294, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3296 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3297 = eq(_T_3296, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3298 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_3299 = eq(_T_3298, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3300 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_3301 = eq(_T_3300, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3302 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_3303 = eq(_T_3302, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3304 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34] + node _T_3305 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_3306 = eq(_T_3305, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3307 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53] + node _T_3308 = eq(_T_3307, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3309 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53] + node _T_3310 = eq(_T_3309, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3311 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53] + node _T_3312 = eq(_T_3311, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3313 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53] + node _T_3314 = eq(_T_3313, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3315 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53] + node _T_3316 = eq(_T_3315, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3317 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3318 = eq(_T_3317, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3319 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53] + node _T_3320 = eq(_T_3319, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3321 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53] + node _T_3322 = eq(_T_3321, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3323 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53] + node _T_3324 = eq(_T_3323, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3325 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53] + node _T_3326 = eq(_T_3325, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3327 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53] + node _T_3328 = eq(_T_3327, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3329 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_3330 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3331 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3332 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3333 = eq(_T_3332, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3334 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3335 = eq(_T_3334, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3336 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3337 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3338 = and(_T_3287, _T_3289) @[dec_dec_ctl.scala 17:17] + node _T_3339 = and(_T_3338, _T_3290) @[dec_dec_ctl.scala 17:17] + node _T_3340 = and(_T_3339, _T_3291) @[dec_dec_ctl.scala 17:17] + node _T_3341 = and(_T_3340, _T_3293) @[dec_dec_ctl.scala 17:17] + node _T_3342 = and(_T_3341, _T_3295) @[dec_dec_ctl.scala 17:17] + node _T_3343 = and(_T_3342, _T_3297) @[dec_dec_ctl.scala 17:17] + node _T_3344 = and(_T_3343, _T_3299) @[dec_dec_ctl.scala 17:17] + node _T_3345 = and(_T_3344, _T_3301) @[dec_dec_ctl.scala 17:17] + node _T_3346 = and(_T_3345, _T_3303) @[dec_dec_ctl.scala 17:17] + node _T_3347 = and(_T_3346, _T_3304) @[dec_dec_ctl.scala 17:17] + node _T_3348 = and(_T_3347, _T_3306) @[dec_dec_ctl.scala 17:17] + node _T_3349 = and(_T_3348, _T_3308) @[dec_dec_ctl.scala 17:17] + node _T_3350 = and(_T_3349, _T_3310) @[dec_dec_ctl.scala 17:17] + node _T_3351 = and(_T_3350, _T_3312) @[dec_dec_ctl.scala 17:17] + node _T_3352 = and(_T_3351, _T_3314) @[dec_dec_ctl.scala 17:17] + node _T_3353 = and(_T_3352, _T_3316) @[dec_dec_ctl.scala 17:17] + node _T_3354 = and(_T_3353, _T_3318) @[dec_dec_ctl.scala 17:17] + node _T_3355 = and(_T_3354, _T_3320) @[dec_dec_ctl.scala 17:17] + node _T_3356 = and(_T_3355, _T_3322) @[dec_dec_ctl.scala 17:17] + node _T_3357 = and(_T_3356, _T_3324) @[dec_dec_ctl.scala 17:17] + node _T_3358 = and(_T_3357, _T_3326) @[dec_dec_ctl.scala 17:17] + node _T_3359 = and(_T_3358, _T_3328) @[dec_dec_ctl.scala 17:17] + node _T_3360 = and(_T_3359, _T_3329) @[dec_dec_ctl.scala 17:17] + node _T_3361 = and(_T_3360, _T_3330) @[dec_dec_ctl.scala 17:17] + node _T_3362 = and(_T_3361, _T_3331) @[dec_dec_ctl.scala 17:17] + node _T_3363 = and(_T_3362, _T_3333) @[dec_dec_ctl.scala 17:17] + node _T_3364 = and(_T_3363, _T_3335) @[dec_dec_ctl.scala 17:17] + node _T_3365 = and(_T_3364, _T_3336) @[dec_dec_ctl.scala 17:17] + node _T_3366 = and(_T_3365, _T_3337) @[dec_dec_ctl.scala 17:17] + node _T_3367 = or(_T_3285, _T_3366) @[dec_dec_ctl.scala 248:136] + node _T_3368 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3369 = eq(_T_3368, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3370 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3371 = eq(_T_3370, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3372 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3373 = eq(_T_3372, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3374 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3375 = eq(_T_3374, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3376 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3377 = eq(_T_3376, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3378 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3379 = eq(_T_3378, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3380 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3381 = eq(_T_3380, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3382 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_3383 = eq(_T_3382, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3384 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_3385 = eq(_T_3384, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3386 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_3387 = eq(_T_3386, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3388 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_3389 = eq(_T_3388, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3390 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53] + node _T_3391 = eq(_T_3390, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3392 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53] + node _T_3393 = eq(_T_3392, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3394 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53] + node _T_3395 = eq(_T_3394, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3396 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53] + node _T_3397 = eq(_T_3396, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3398 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53] + node _T_3399 = eq(_T_3398, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3400 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3401 = eq(_T_3400, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3402 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53] + node _T_3403 = eq(_T_3402, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3404 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53] + node _T_3405 = eq(_T_3404, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3406 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53] + node _T_3407 = eq(_T_3406, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3408 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53] + node _T_3409 = eq(_T_3408, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3410 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53] + node _T_3411 = eq(_T_3410, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3412 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3413 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3414 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3415 = eq(_T_3414, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3416 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3417 = eq(_T_3416, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3418 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3419 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3420 = and(_T_3369, _T_3371) @[dec_dec_ctl.scala 17:17] + node _T_3421 = and(_T_3420, _T_3373) @[dec_dec_ctl.scala 17:17] + node _T_3422 = and(_T_3421, _T_3375) @[dec_dec_ctl.scala 17:17] + node _T_3423 = and(_T_3422, _T_3377) @[dec_dec_ctl.scala 17:17] + node _T_3424 = and(_T_3423, _T_3379) @[dec_dec_ctl.scala 17:17] + node _T_3425 = and(_T_3424, _T_3381) @[dec_dec_ctl.scala 17:17] + node _T_3426 = and(_T_3425, _T_3383) @[dec_dec_ctl.scala 17:17] + node _T_3427 = and(_T_3426, _T_3385) @[dec_dec_ctl.scala 17:17] + node _T_3428 = and(_T_3427, _T_3387) @[dec_dec_ctl.scala 17:17] + node _T_3429 = and(_T_3428, _T_3389) @[dec_dec_ctl.scala 17:17] + node _T_3430 = and(_T_3429, _T_3391) @[dec_dec_ctl.scala 17:17] + node _T_3431 = and(_T_3430, _T_3393) @[dec_dec_ctl.scala 17:17] + node _T_3432 = and(_T_3431, _T_3395) @[dec_dec_ctl.scala 17:17] + node _T_3433 = and(_T_3432, _T_3397) @[dec_dec_ctl.scala 17:17] + node _T_3434 = and(_T_3433, _T_3399) @[dec_dec_ctl.scala 17:17] + node _T_3435 = and(_T_3434, _T_3401) @[dec_dec_ctl.scala 17:17] + node _T_3436 = and(_T_3435, _T_3403) @[dec_dec_ctl.scala 17:17] + node _T_3437 = and(_T_3436, _T_3405) @[dec_dec_ctl.scala 17:17] + node _T_3438 = and(_T_3437, _T_3407) @[dec_dec_ctl.scala 17:17] + node _T_3439 = and(_T_3438, _T_3409) @[dec_dec_ctl.scala 17:17] + node _T_3440 = and(_T_3439, _T_3411) @[dec_dec_ctl.scala 17:17] + node _T_3441 = and(_T_3440, _T_3412) @[dec_dec_ctl.scala 17:17] + node _T_3442 = and(_T_3441, _T_3413) @[dec_dec_ctl.scala 17:17] + node _T_3443 = and(_T_3442, _T_3415) @[dec_dec_ctl.scala 17:17] + node _T_3444 = and(_T_3443, _T_3417) @[dec_dec_ctl.scala 17:17] + node _T_3445 = and(_T_3444, _T_3418) @[dec_dec_ctl.scala 17:17] + node _T_3446 = and(_T_3445, _T_3419) @[dec_dec_ctl.scala 17:17] + node _T_3447 = or(_T_3367, _T_3446) @[dec_dec_ctl.scala 249:122] + node _T_3448 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3449 = eq(_T_3448, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3450 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3451 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3452 = eq(_T_3451, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3453 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3454 = eq(_T_3453, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3455 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3456 = eq(_T_3455, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3457 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_3458 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_3459 = eq(_T_3458, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3460 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_3461 = eq(_T_3460, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3462 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3463 = eq(_T_3462, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3464 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3465 = eq(_T_3464, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3466 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3467 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3468 = eq(_T_3467, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3469 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3470 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3471 = and(_T_3449, _T_3450) @[dec_dec_ctl.scala 17:17] + node _T_3472 = and(_T_3471, _T_3452) @[dec_dec_ctl.scala 17:17] + node _T_3473 = and(_T_3472, _T_3454) @[dec_dec_ctl.scala 17:17] + node _T_3474 = and(_T_3473, _T_3456) @[dec_dec_ctl.scala 17:17] + node _T_3475 = and(_T_3474, _T_3457) @[dec_dec_ctl.scala 17:17] + node _T_3476 = and(_T_3475, _T_3459) @[dec_dec_ctl.scala 17:17] + node _T_3477 = and(_T_3476, _T_3461) @[dec_dec_ctl.scala 17:17] + node _T_3478 = and(_T_3477, _T_3463) @[dec_dec_ctl.scala 17:17] + node _T_3479 = and(_T_3478, _T_3465) @[dec_dec_ctl.scala 17:17] + node _T_3480 = and(_T_3479, _T_3466) @[dec_dec_ctl.scala 17:17] + node _T_3481 = and(_T_3480, _T_3468) @[dec_dec_ctl.scala 17:17] + node _T_3482 = and(_T_3481, _T_3469) @[dec_dec_ctl.scala 17:17] + node _T_3483 = and(_T_3482, _T_3470) @[dec_dec_ctl.scala 17:17] + node _T_3484 = or(_T_3447, _T_3483) @[dec_dec_ctl.scala 250:119] + node _T_3485 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3486 = eq(_T_3485, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3487 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3488 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3489 = eq(_T_3488, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3490 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3491 = eq(_T_3490, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3492 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3493 = eq(_T_3492, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3494 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34] + node _T_3495 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_3496 = eq(_T_3495, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3497 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_3498 = eq(_T_3497, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3499 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3500 = eq(_T_3499, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3501 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3502 = eq(_T_3501, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3503 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3504 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3505 = eq(_T_3504, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3506 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3507 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3508 = and(_T_3486, _T_3487) @[dec_dec_ctl.scala 17:17] + node _T_3509 = and(_T_3508, _T_3489) @[dec_dec_ctl.scala 17:17] + node _T_3510 = and(_T_3509, _T_3491) @[dec_dec_ctl.scala 17:17] + node _T_3511 = and(_T_3510, _T_3493) @[dec_dec_ctl.scala 17:17] + node _T_3512 = and(_T_3511, _T_3494) @[dec_dec_ctl.scala 17:17] + node _T_3513 = and(_T_3512, _T_3496) @[dec_dec_ctl.scala 17:17] + node _T_3514 = and(_T_3513, _T_3498) @[dec_dec_ctl.scala 17:17] + node _T_3515 = and(_T_3514, _T_3500) @[dec_dec_ctl.scala 17:17] + node _T_3516 = and(_T_3515, _T_3502) @[dec_dec_ctl.scala 17:17] + node _T_3517 = and(_T_3516, _T_3503) @[dec_dec_ctl.scala 17:17] + node _T_3518 = and(_T_3517, _T_3505) @[dec_dec_ctl.scala 17:17] + node _T_3519 = and(_T_3518, _T_3506) @[dec_dec_ctl.scala 17:17] + node _T_3520 = and(_T_3519, _T_3507) @[dec_dec_ctl.scala 17:17] + node _T_3521 = or(_T_3484, _T_3520) @[dec_dec_ctl.scala 251:65] + node _T_3522 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3523 = eq(_T_3522, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3524 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3525 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3526 = eq(_T_3525, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3527 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3528 = eq(_T_3527, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3529 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3530 = eq(_T_3529, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3531 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_3532 = eq(_T_3531, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3533 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_3534 = eq(_T_3533, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3535 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_3536 = eq(_T_3535, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3537 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3538 = eq(_T_3537, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3539 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3540 = eq(_T_3539, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3541 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3542 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3543 = eq(_T_3542, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3544 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3545 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3546 = and(_T_3523, _T_3524) @[dec_dec_ctl.scala 17:17] + node _T_3547 = and(_T_3546, _T_3526) @[dec_dec_ctl.scala 17:17] + node _T_3548 = and(_T_3547, _T_3528) @[dec_dec_ctl.scala 17:17] + node _T_3549 = and(_T_3548, _T_3530) @[dec_dec_ctl.scala 17:17] + node _T_3550 = and(_T_3549, _T_3532) @[dec_dec_ctl.scala 17:17] + node _T_3551 = and(_T_3550, _T_3534) @[dec_dec_ctl.scala 17:17] + node _T_3552 = and(_T_3551, _T_3536) @[dec_dec_ctl.scala 17:17] + node _T_3553 = and(_T_3552, _T_3538) @[dec_dec_ctl.scala 17:17] + node _T_3554 = and(_T_3553, _T_3540) @[dec_dec_ctl.scala 17:17] + node _T_3555 = and(_T_3554, _T_3541) @[dec_dec_ctl.scala 17:17] + node _T_3556 = and(_T_3555, _T_3543) @[dec_dec_ctl.scala 17:17] + node _T_3557 = and(_T_3556, _T_3544) @[dec_dec_ctl.scala 17:17] + node _T_3558 = and(_T_3557, _T_3545) @[dec_dec_ctl.scala 17:17] + node _T_3559 = or(_T_3521, _T_3558) @[dec_dec_ctl.scala 251:127] + node _T_3560 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3561 = eq(_T_3560, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3562 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3563 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3564 = eq(_T_3563, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3565 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3566 = eq(_T_3565, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3567 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3568 = eq(_T_3567, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3569 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_3570 = eq(_T_3569, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3571 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_3572 = eq(_T_3571, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3573 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_3574 = eq(_T_3573, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3575 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3576 = eq(_T_3575, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3577 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3578 = eq(_T_3577, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3579 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3580 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3581 = eq(_T_3580, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3582 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3583 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3584 = and(_T_3561, _T_3562) @[dec_dec_ctl.scala 17:17] + node _T_3585 = and(_T_3584, _T_3564) @[dec_dec_ctl.scala 17:17] + node _T_3586 = and(_T_3585, _T_3566) @[dec_dec_ctl.scala 17:17] + node _T_3587 = and(_T_3586, _T_3568) @[dec_dec_ctl.scala 17:17] + node _T_3588 = and(_T_3587, _T_3570) @[dec_dec_ctl.scala 17:17] + node _T_3589 = and(_T_3588, _T_3572) @[dec_dec_ctl.scala 17:17] + node _T_3590 = and(_T_3589, _T_3574) @[dec_dec_ctl.scala 17:17] + node _T_3591 = and(_T_3590, _T_3576) @[dec_dec_ctl.scala 17:17] + node _T_3592 = and(_T_3591, _T_3578) @[dec_dec_ctl.scala 17:17] + node _T_3593 = and(_T_3592, _T_3579) @[dec_dec_ctl.scala 17:17] + node _T_3594 = and(_T_3593, _T_3581) @[dec_dec_ctl.scala 17:17] + node _T_3595 = and(_T_3594, _T_3582) @[dec_dec_ctl.scala 17:17] + node _T_3596 = and(_T_3595, _T_3583) @[dec_dec_ctl.scala 17:17] + node _T_3597 = or(_T_3559, _T_3596) @[dec_dec_ctl.scala 252:66] + node _T_3598 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3599 = eq(_T_3598, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3600 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3601 = eq(_T_3600, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3602 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3603 = eq(_T_3602, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3604 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3605 = eq(_T_3604, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3606 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3607 = eq(_T_3606, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3608 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34] + node _T_3609 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_3610 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3611 = eq(_T_3610, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3612 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3613 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3614 = eq(_T_3613, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3615 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3616 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3617 = and(_T_3599, _T_3601) @[dec_dec_ctl.scala 17:17] + node _T_3618 = and(_T_3617, _T_3603) @[dec_dec_ctl.scala 17:17] + node _T_3619 = and(_T_3618, _T_3605) @[dec_dec_ctl.scala 17:17] + node _T_3620 = and(_T_3619, _T_3607) @[dec_dec_ctl.scala 17:17] + node _T_3621 = and(_T_3620, _T_3608) @[dec_dec_ctl.scala 17:17] + node _T_3622 = and(_T_3621, _T_3609) @[dec_dec_ctl.scala 17:17] + node _T_3623 = and(_T_3622, _T_3611) @[dec_dec_ctl.scala 17:17] + node _T_3624 = and(_T_3623, _T_3612) @[dec_dec_ctl.scala 17:17] + node _T_3625 = and(_T_3624, _T_3614) @[dec_dec_ctl.scala 17:17] + node _T_3626 = and(_T_3625, _T_3615) @[dec_dec_ctl.scala 17:17] + node _T_3627 = and(_T_3626, _T_3616) @[dec_dec_ctl.scala 17:17] + node _T_3628 = or(_T_3597, _T_3627) @[dec_dec_ctl.scala 252:129] + node _T_3629 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3630 = eq(_T_3629, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3631 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3632 = eq(_T_3631, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3633 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3634 = eq(_T_3633, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3635 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3636 = eq(_T_3635, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3637 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3638 = eq(_T_3637, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3639 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_3640 = eq(_T_3639, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3641 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3642 = eq(_T_3641, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3643 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3644 = eq(_T_3643, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3645 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3646 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3647 = eq(_T_3646, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3648 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3649 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3650 = and(_T_3630, _T_3632) @[dec_dec_ctl.scala 17:17] + node _T_3651 = and(_T_3650, _T_3634) @[dec_dec_ctl.scala 17:17] + node _T_3652 = and(_T_3651, _T_3636) @[dec_dec_ctl.scala 17:17] + node _T_3653 = and(_T_3652, _T_3638) @[dec_dec_ctl.scala 17:17] + node _T_3654 = and(_T_3653, _T_3640) @[dec_dec_ctl.scala 17:17] + node _T_3655 = and(_T_3654, _T_3642) @[dec_dec_ctl.scala 17:17] + node _T_3656 = and(_T_3655, _T_3644) @[dec_dec_ctl.scala 17:17] + node _T_3657 = and(_T_3656, _T_3645) @[dec_dec_ctl.scala 17:17] + node _T_3658 = and(_T_3657, _T_3647) @[dec_dec_ctl.scala 17:17] + node _T_3659 = and(_T_3658, _T_3648) @[dec_dec_ctl.scala 17:17] + node _T_3660 = and(_T_3659, _T_3649) @[dec_dec_ctl.scala 17:17] + node _T_3661 = or(_T_3628, _T_3660) @[dec_dec_ctl.scala 253:58] + node _T_3662 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3663 = eq(_T_3662, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3664 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3665 = eq(_T_3664, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3666 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3667 = eq(_T_3666, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3668 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3669 = eq(_T_3668, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3670 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3671 = eq(_T_3670, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3672 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3673 = eq(_T_3672, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3674 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_3675 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3676 = eq(_T_3675, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3677 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3678 = eq(_T_3677, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3679 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3680 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3681 = eq(_T_3680, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3682 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3683 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3684 = and(_T_3663, _T_3665) @[dec_dec_ctl.scala 17:17] + node _T_3685 = and(_T_3684, _T_3667) @[dec_dec_ctl.scala 17:17] + node _T_3686 = and(_T_3685, _T_3669) @[dec_dec_ctl.scala 17:17] + node _T_3687 = and(_T_3686, _T_3671) @[dec_dec_ctl.scala 17:17] + node _T_3688 = and(_T_3687, _T_3673) @[dec_dec_ctl.scala 17:17] + node _T_3689 = and(_T_3688, _T_3674) @[dec_dec_ctl.scala 17:17] + node _T_3690 = and(_T_3689, _T_3676) @[dec_dec_ctl.scala 17:17] + node _T_3691 = and(_T_3690, _T_3678) @[dec_dec_ctl.scala 17:17] + node _T_3692 = and(_T_3691, _T_3679) @[dec_dec_ctl.scala 17:17] + node _T_3693 = and(_T_3692, _T_3681) @[dec_dec_ctl.scala 17:17] + node _T_3694 = and(_T_3693, _T_3682) @[dec_dec_ctl.scala 17:17] + node _T_3695 = and(_T_3694, _T_3683) @[dec_dec_ctl.scala 17:17] + node _T_3696 = or(_T_3661, _T_3695) @[dec_dec_ctl.scala 253:114] + node _T_3697 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3698 = eq(_T_3697, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3699 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3700 = eq(_T_3699, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3701 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3702 = eq(_T_3701, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3703 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3704 = eq(_T_3703, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3705 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3706 = eq(_T_3705, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3707 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3708 = eq(_T_3707, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3709 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_3710 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3711 = eq(_T_3710, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3712 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3713 = eq(_T_3712, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3714 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3715 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3716 = eq(_T_3715, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3717 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3718 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3719 = and(_T_3698, _T_3700) @[dec_dec_ctl.scala 17:17] + node _T_3720 = and(_T_3719, _T_3702) @[dec_dec_ctl.scala 17:17] + node _T_3721 = and(_T_3720, _T_3704) @[dec_dec_ctl.scala 17:17] + node _T_3722 = and(_T_3721, _T_3706) @[dec_dec_ctl.scala 17:17] + node _T_3723 = and(_T_3722, _T_3708) @[dec_dec_ctl.scala 17:17] + node _T_3724 = and(_T_3723, _T_3709) @[dec_dec_ctl.scala 17:17] + node _T_3725 = and(_T_3724, _T_3711) @[dec_dec_ctl.scala 17:17] + node _T_3726 = and(_T_3725, _T_3713) @[dec_dec_ctl.scala 17:17] + node _T_3727 = and(_T_3726, _T_3714) @[dec_dec_ctl.scala 17:17] + node _T_3728 = and(_T_3727, _T_3716) @[dec_dec_ctl.scala 17:17] + node _T_3729 = and(_T_3728, _T_3717) @[dec_dec_ctl.scala 17:17] + node _T_3730 = and(_T_3729, _T_3718) @[dec_dec_ctl.scala 17:17] + node _T_3731 = or(_T_3696, _T_3730) @[dec_dec_ctl.scala 254:63] + node _T_3732 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3733 = eq(_T_3732, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3734 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3735 = eq(_T_3734, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3736 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3737 = eq(_T_3736, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3738 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3739 = eq(_T_3738, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3740 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3741 = eq(_T_3740, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3742 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3743 = eq(_T_3742, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3744 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3745 = eq(_T_3744, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3746 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3747 = eq(_T_3746, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3748 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3749 = eq(_T_3748, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3750 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3751 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3752 = eq(_T_3751, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3753 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3754 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3755 = and(_T_3733, _T_3735) @[dec_dec_ctl.scala 17:17] + node _T_3756 = and(_T_3755, _T_3737) @[dec_dec_ctl.scala 17:17] + node _T_3757 = and(_T_3756, _T_3739) @[dec_dec_ctl.scala 17:17] + node _T_3758 = and(_T_3757, _T_3741) @[dec_dec_ctl.scala 17:17] + node _T_3759 = and(_T_3758, _T_3743) @[dec_dec_ctl.scala 17:17] + node _T_3760 = and(_T_3759, _T_3745) @[dec_dec_ctl.scala 17:17] + node _T_3761 = and(_T_3760, _T_3747) @[dec_dec_ctl.scala 17:17] + node _T_3762 = and(_T_3761, _T_3749) @[dec_dec_ctl.scala 17:17] + node _T_3763 = and(_T_3762, _T_3750) @[dec_dec_ctl.scala 17:17] + node _T_3764 = and(_T_3763, _T_3752) @[dec_dec_ctl.scala 17:17] + node _T_3765 = and(_T_3764, _T_3753) @[dec_dec_ctl.scala 17:17] + node _T_3766 = and(_T_3765, _T_3754) @[dec_dec_ctl.scala 17:17] + node _T_3767 = or(_T_3731, _T_3766) @[dec_dec_ctl.scala 254:123] + node _T_3768 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3769 = eq(_T_3768, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3770 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3771 = eq(_T_3770, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3772 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3773 = eq(_T_3772, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3774 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3775 = eq(_T_3774, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3776 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3777 = eq(_T_3776, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3778 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_3779 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3780 = eq(_T_3779, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3781 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3782 = eq(_T_3781, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3783 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3784 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3785 = eq(_T_3784, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3786 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3787 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3788 = and(_T_3769, _T_3771) @[dec_dec_ctl.scala 17:17] + node _T_3789 = and(_T_3788, _T_3773) @[dec_dec_ctl.scala 17:17] + node _T_3790 = and(_T_3789, _T_3775) @[dec_dec_ctl.scala 17:17] + node _T_3791 = and(_T_3790, _T_3777) @[dec_dec_ctl.scala 17:17] + node _T_3792 = and(_T_3791, _T_3778) @[dec_dec_ctl.scala 17:17] + node _T_3793 = and(_T_3792, _T_3780) @[dec_dec_ctl.scala 17:17] + node _T_3794 = and(_T_3793, _T_3782) @[dec_dec_ctl.scala 17:17] + node _T_3795 = and(_T_3794, _T_3783) @[dec_dec_ctl.scala 17:17] + node _T_3796 = and(_T_3795, _T_3785) @[dec_dec_ctl.scala 17:17] + node _T_3797 = and(_T_3796, _T_3786) @[dec_dec_ctl.scala 17:17] + node _T_3798 = and(_T_3797, _T_3787) @[dec_dec_ctl.scala 17:17] + node _T_3799 = or(_T_3767, _T_3798) @[dec_dec_ctl.scala 255:64] + node _T_3800 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3801 = eq(_T_3800, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3802 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3803 = eq(_T_3802, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3804 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3805 = eq(_T_3804, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3806 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3807 = eq(_T_3806, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3808 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3809 = eq(_T_3808, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3810 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3811 = eq(_T_3810, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3812 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_3813 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3814 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3815 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3816 = eq(_T_3815, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3817 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_3818 = eq(_T_3817, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3819 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3820 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3821 = and(_T_3801, _T_3803) @[dec_dec_ctl.scala 17:17] + node _T_3822 = and(_T_3821, _T_3805) @[dec_dec_ctl.scala 17:17] + node _T_3823 = and(_T_3822, _T_3807) @[dec_dec_ctl.scala 17:17] + node _T_3824 = and(_T_3823, _T_3809) @[dec_dec_ctl.scala 17:17] + node _T_3825 = and(_T_3824, _T_3811) @[dec_dec_ctl.scala 17:17] + node _T_3826 = and(_T_3825, _T_3812) @[dec_dec_ctl.scala 17:17] + node _T_3827 = and(_T_3826, _T_3813) @[dec_dec_ctl.scala 17:17] + node _T_3828 = and(_T_3827, _T_3814) @[dec_dec_ctl.scala 17:17] + node _T_3829 = and(_T_3828, _T_3816) @[dec_dec_ctl.scala 17:17] + node _T_3830 = and(_T_3829, _T_3818) @[dec_dec_ctl.scala 17:17] + node _T_3831 = and(_T_3830, _T_3819) @[dec_dec_ctl.scala 17:17] + node _T_3832 = and(_T_3831, _T_3820) @[dec_dec_ctl.scala 17:17] + node _T_3833 = or(_T_3799, _T_3832) @[dec_dec_ctl.scala 255:119] + node _T_3834 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3835 = eq(_T_3834, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3836 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3837 = eq(_T_3836, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3838 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3839 = eq(_T_3838, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3840 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3841 = eq(_T_3840, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3842 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3843 = eq(_T_3842, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3844 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_3845 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3846 = eq(_T_3845, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3847 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3848 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3849 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3850 = eq(_T_3849, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3851 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3852 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3853 = and(_T_3835, _T_3837) @[dec_dec_ctl.scala 17:17] + node _T_3854 = and(_T_3853, _T_3839) @[dec_dec_ctl.scala 17:17] + node _T_3855 = and(_T_3854, _T_3841) @[dec_dec_ctl.scala 17:17] + node _T_3856 = and(_T_3855, _T_3843) @[dec_dec_ctl.scala 17:17] + node _T_3857 = and(_T_3856, _T_3844) @[dec_dec_ctl.scala 17:17] + node _T_3858 = and(_T_3857, _T_3846) @[dec_dec_ctl.scala 17:17] + node _T_3859 = and(_T_3858, _T_3847) @[dec_dec_ctl.scala 17:17] + node _T_3860 = and(_T_3859, _T_3848) @[dec_dec_ctl.scala 17:17] + node _T_3861 = and(_T_3860, _T_3850) @[dec_dec_ctl.scala 17:17] + node _T_3862 = and(_T_3861, _T_3851) @[dec_dec_ctl.scala 17:17] + node _T_3863 = and(_T_3862, _T_3852) @[dec_dec_ctl.scala 17:17] + node _T_3864 = or(_T_3833, _T_3863) @[dec_dec_ctl.scala 256:61] + node _T_3865 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3866 = eq(_T_3865, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3867 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34] + node _T_3868 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3869 = eq(_T_3868, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3870 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_3871 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3872 = eq(_T_3871, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3873 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3874 = eq(_T_3873, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3875 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3876 = eq(_T_3875, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3877 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_3878 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3879 = eq(_T_3878, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3880 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3881 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3882 = eq(_T_3881, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3883 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3884 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3885 = and(_T_3866, _T_3867) @[dec_dec_ctl.scala 17:17] + node _T_3886 = and(_T_3885, _T_3869) @[dec_dec_ctl.scala 17:17] + node _T_3887 = and(_T_3886, _T_3870) @[dec_dec_ctl.scala 17:17] + node _T_3888 = and(_T_3887, _T_3872) @[dec_dec_ctl.scala 17:17] + node _T_3889 = and(_T_3888, _T_3874) @[dec_dec_ctl.scala 17:17] + node _T_3890 = and(_T_3889, _T_3876) @[dec_dec_ctl.scala 17:17] + node _T_3891 = and(_T_3890, _T_3877) @[dec_dec_ctl.scala 17:17] + node _T_3892 = and(_T_3891, _T_3879) @[dec_dec_ctl.scala 17:17] + node _T_3893 = and(_T_3892, _T_3880) @[dec_dec_ctl.scala 17:17] + node _T_3894 = and(_T_3893, _T_3882) @[dec_dec_ctl.scala 17:17] + node _T_3895 = and(_T_3894, _T_3883) @[dec_dec_ctl.scala 17:17] + node _T_3896 = and(_T_3895, _T_3884) @[dec_dec_ctl.scala 17:17] + node _T_3897 = or(_T_3864, _T_3896) @[dec_dec_ctl.scala 256:115] + node _T_3898 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3899 = eq(_T_3898, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3900 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_3901 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3902 = eq(_T_3901, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3903 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34] + node _T_3904 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3905 = eq(_T_3904, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3906 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3907 = eq(_T_3906, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3908 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3909 = eq(_T_3908, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3910 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3911 = eq(_T_3910, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3912 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3913 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3914 = eq(_T_3913, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3915 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3916 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3917 = and(_T_3899, _T_3900) @[dec_dec_ctl.scala 17:17] + node _T_3918 = and(_T_3917, _T_3902) @[dec_dec_ctl.scala 17:17] + node _T_3919 = and(_T_3918, _T_3903) @[dec_dec_ctl.scala 17:17] + node _T_3920 = and(_T_3919, _T_3905) @[dec_dec_ctl.scala 17:17] + node _T_3921 = and(_T_3920, _T_3907) @[dec_dec_ctl.scala 17:17] + node _T_3922 = and(_T_3921, _T_3909) @[dec_dec_ctl.scala 17:17] + node _T_3923 = and(_T_3922, _T_3911) @[dec_dec_ctl.scala 17:17] + node _T_3924 = and(_T_3923, _T_3912) @[dec_dec_ctl.scala 17:17] + node _T_3925 = and(_T_3924, _T_3914) @[dec_dec_ctl.scala 17:17] + node _T_3926 = and(_T_3925, _T_3915) @[dec_dec_ctl.scala 17:17] + node _T_3927 = and(_T_3926, _T_3916) @[dec_dec_ctl.scala 17:17] + node _T_3928 = or(_T_3897, _T_3927) @[dec_dec_ctl.scala 257:61] + node _T_3929 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3930 = eq(_T_3929, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3931 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3932 = eq(_T_3931, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3933 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3934 = eq(_T_3933, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3935 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3936 = eq(_T_3935, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3937 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3938 = eq(_T_3937, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3939 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_3940 = eq(_T_3939, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3941 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3942 = eq(_T_3941, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3943 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_3944 = eq(_T_3943, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3945 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3946 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3947 = eq(_T_3946, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3948 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3949 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3950 = and(_T_3930, _T_3932) @[dec_dec_ctl.scala 17:17] + node _T_3951 = and(_T_3950, _T_3934) @[dec_dec_ctl.scala 17:17] + node _T_3952 = and(_T_3951, _T_3936) @[dec_dec_ctl.scala 17:17] + node _T_3953 = and(_T_3952, _T_3938) @[dec_dec_ctl.scala 17:17] + node _T_3954 = and(_T_3953, _T_3940) @[dec_dec_ctl.scala 17:17] + node _T_3955 = and(_T_3954, _T_3942) @[dec_dec_ctl.scala 17:17] + node _T_3956 = and(_T_3955, _T_3944) @[dec_dec_ctl.scala 17:17] + node _T_3957 = and(_T_3956, _T_3945) @[dec_dec_ctl.scala 17:17] + node _T_3958 = and(_T_3957, _T_3947) @[dec_dec_ctl.scala 17:17] + node _T_3959 = and(_T_3958, _T_3948) @[dec_dec_ctl.scala 17:17] + node _T_3960 = and(_T_3959, _T_3949) @[dec_dec_ctl.scala 17:17] + node _T_3961 = or(_T_3928, _T_3960) @[dec_dec_ctl.scala 257:116] + node _T_3962 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_3963 = eq(_T_3962, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3964 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_3965 = eq(_T_3964, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3966 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_3967 = eq(_T_3966, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3968 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_3969 = eq(_T_3968, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3970 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_3971 = eq(_T_3970, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3972 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_3973 = eq(_T_3972, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3974 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_3975 = eq(_T_3974, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3976 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_3977 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_3978 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_3979 = eq(_T_3978, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3980 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_3981 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_3982 = and(_T_3963, _T_3965) @[dec_dec_ctl.scala 17:17] + node _T_3983 = and(_T_3982, _T_3967) @[dec_dec_ctl.scala 17:17] + node _T_3984 = and(_T_3983, _T_3969) @[dec_dec_ctl.scala 17:17] + node _T_3985 = and(_T_3984, _T_3971) @[dec_dec_ctl.scala 17:17] + node _T_3986 = and(_T_3985, _T_3973) @[dec_dec_ctl.scala 17:17] + node _T_3987 = and(_T_3986, _T_3975) @[dec_dec_ctl.scala 17:17] + node _T_3988 = and(_T_3987, _T_3976) @[dec_dec_ctl.scala 17:17] + node _T_3989 = and(_T_3988, _T_3977) @[dec_dec_ctl.scala 17:17] + node _T_3990 = and(_T_3989, _T_3979) @[dec_dec_ctl.scala 17:17] + node _T_3991 = and(_T_3990, _T_3980) @[dec_dec_ctl.scala 17:17] + node _T_3992 = and(_T_3991, _T_3981) @[dec_dec_ctl.scala 17:17] + node _T_3993 = or(_T_3961, _T_3992) @[dec_dec_ctl.scala 258:59] + node _T_3994 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_3995 = eq(_T_3994, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3996 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_3997 = eq(_T_3996, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_3998 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_3999 = eq(_T_3998, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4000 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_4001 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4002 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4003 = eq(_T_4002, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4004 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4005 = eq(_T_4004, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4006 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4007 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4008 = and(_T_3995, _T_3997) @[dec_dec_ctl.scala 17:17] + node _T_4009 = and(_T_4008, _T_3999) @[dec_dec_ctl.scala 17:17] + node _T_4010 = and(_T_4009, _T_4000) @[dec_dec_ctl.scala 17:17] + node _T_4011 = and(_T_4010, _T_4001) @[dec_dec_ctl.scala 17:17] + node _T_4012 = and(_T_4011, _T_4003) @[dec_dec_ctl.scala 17:17] + node _T_4013 = and(_T_4012, _T_4005) @[dec_dec_ctl.scala 17:17] + node _T_4014 = and(_T_4013, _T_4006) @[dec_dec_ctl.scala 17:17] + node _T_4015 = and(_T_4014, _T_4007) @[dec_dec_ctl.scala 17:17] + node _T_4016 = or(_T_3993, _T_4015) @[dec_dec_ctl.scala 258:114] + node _T_4017 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_4018 = eq(_T_4017, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4019 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_4020 = eq(_T_4019, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4021 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_4022 = eq(_T_4021, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4023 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_4024 = eq(_T_4023, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4025 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_4026 = eq(_T_4025, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4027 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_4028 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4029 = eq(_T_4028, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4030 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4031 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_4032 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4033 = eq(_T_4032, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4034 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4035 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4036 = and(_T_4018, _T_4020) @[dec_dec_ctl.scala 17:17] + node _T_4037 = and(_T_4036, _T_4022) @[dec_dec_ctl.scala 17:17] + node _T_4038 = and(_T_4037, _T_4024) @[dec_dec_ctl.scala 17:17] + node _T_4039 = and(_T_4038, _T_4026) @[dec_dec_ctl.scala 17:17] + node _T_4040 = and(_T_4039, _T_4027) @[dec_dec_ctl.scala 17:17] + node _T_4041 = and(_T_4040, _T_4029) @[dec_dec_ctl.scala 17:17] + node _T_4042 = and(_T_4041, _T_4030) @[dec_dec_ctl.scala 17:17] + node _T_4043 = and(_T_4042, _T_4031) @[dec_dec_ctl.scala 17:17] + node _T_4044 = and(_T_4043, _T_4033) @[dec_dec_ctl.scala 17:17] + node _T_4045 = and(_T_4044, _T_4034) @[dec_dec_ctl.scala 17:17] + node _T_4046 = and(_T_4045, _T_4035) @[dec_dec_ctl.scala 17:17] + node _T_4047 = or(_T_4016, _T_4046) @[dec_dec_ctl.scala 259:46] + node _T_4048 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_4049 = eq(_T_4048, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4050 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34] + node _T_4051 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_4052 = eq(_T_4051, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4053 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_4054 = eq(_T_4053, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4055 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_4056 = eq(_T_4055, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4057 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_4058 = eq(_T_4057, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4059 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_4060 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4061 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_4062 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4063 = eq(_T_4062, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4064 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4065 = eq(_T_4064, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4066 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4067 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4068 = and(_T_4049, _T_4050) @[dec_dec_ctl.scala 17:17] + node _T_4069 = and(_T_4068, _T_4052) @[dec_dec_ctl.scala 17:17] + node _T_4070 = and(_T_4069, _T_4054) @[dec_dec_ctl.scala 17:17] + node _T_4071 = and(_T_4070, _T_4056) @[dec_dec_ctl.scala 17:17] + node _T_4072 = and(_T_4071, _T_4058) @[dec_dec_ctl.scala 17:17] + node _T_4073 = and(_T_4072, _T_4059) @[dec_dec_ctl.scala 17:17] + node _T_4074 = and(_T_4073, _T_4060) @[dec_dec_ctl.scala 17:17] + node _T_4075 = and(_T_4074, _T_4061) @[dec_dec_ctl.scala 17:17] + node _T_4076 = and(_T_4075, _T_4063) @[dec_dec_ctl.scala 17:17] + node _T_4077 = and(_T_4076, _T_4065) @[dec_dec_ctl.scala 17:17] + node _T_4078 = and(_T_4077, _T_4066) @[dec_dec_ctl.scala 17:17] + node _T_4079 = and(_T_4078, _T_4067) @[dec_dec_ctl.scala 17:17] + node _T_4080 = or(_T_4047, _T_4079) @[dec_dec_ctl.scala 259:100] + node _T_4081 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34] + node _T_4082 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_4083 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4084 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4085 = eq(_T_4084, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4086 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4087 = eq(_T_4086, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4088 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4089 = eq(_T_4088, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4090 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4091 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4092 = and(_T_4081, _T_4082) @[dec_dec_ctl.scala 17:17] + node _T_4093 = and(_T_4092, _T_4083) @[dec_dec_ctl.scala 17:17] + node _T_4094 = and(_T_4093, _T_4085) @[dec_dec_ctl.scala 17:17] + node _T_4095 = and(_T_4094, _T_4087) @[dec_dec_ctl.scala 17:17] + node _T_4096 = and(_T_4095, _T_4089) @[dec_dec_ctl.scala 17:17] + node _T_4097 = and(_T_4096, _T_4090) @[dec_dec_ctl.scala 17:17] + node _T_4098 = and(_T_4097, _T_4091) @[dec_dec_ctl.scala 17:17] + node _T_4099 = or(_T_4080, _T_4098) @[dec_dec_ctl.scala 260:60] + node _T_4100 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_4101 = eq(_T_4100, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4102 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_4103 = eq(_T_4102, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4104 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4105 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4106 = eq(_T_4105, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4107 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4108 = eq(_T_4107, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4109 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4110 = eq(_T_4109, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4111 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4112 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4113 = and(_T_4101, _T_4103) @[dec_dec_ctl.scala 17:17] + node _T_4114 = and(_T_4113, _T_4104) @[dec_dec_ctl.scala 17:17] + node _T_4115 = and(_T_4114, _T_4106) @[dec_dec_ctl.scala 17:17] + node _T_4116 = and(_T_4115, _T_4108) @[dec_dec_ctl.scala 17:17] + node _T_4117 = and(_T_4116, _T_4110) @[dec_dec_ctl.scala 17:17] + node _T_4118 = and(_T_4117, _T_4111) @[dec_dec_ctl.scala 17:17] + node _T_4119 = and(_T_4118, _T_4112) @[dec_dec_ctl.scala 17:17] + node _T_4120 = or(_T_4099, _T_4119) @[dec_dec_ctl.scala 260:97] + node _T_4121 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_4122 = eq(_T_4121, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4123 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4124 = eq(_T_4123, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4125 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_4126 = eq(_T_4125, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4127 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_4128 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4129 = eq(_T_4128, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4130 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4131 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4132 = and(_T_4122, _T_4124) @[dec_dec_ctl.scala 17:17] + node _T_4133 = and(_T_4132, _T_4126) @[dec_dec_ctl.scala 17:17] + node _T_4134 = and(_T_4133, _T_4127) @[dec_dec_ctl.scala 17:17] + node _T_4135 = and(_T_4134, _T_4129) @[dec_dec_ctl.scala 17:17] + node _T_4136 = and(_T_4135, _T_4130) @[dec_dec_ctl.scala 17:17] + node _T_4137 = and(_T_4136, _T_4131) @[dec_dec_ctl.scala 17:17] + node _T_4138 = or(_T_4120, _T_4137) @[dec_dec_ctl.scala 261:43] + node _T_4139 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_4140 = eq(_T_4139, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4141 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34] + node _T_4142 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_4143 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4144 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4145 = eq(_T_4144, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4146 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4147 = eq(_T_4146, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4148 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4149 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4150 = and(_T_4140, _T_4141) @[dec_dec_ctl.scala 17:17] + node _T_4151 = and(_T_4150, _T_4142) @[dec_dec_ctl.scala 17:17] + node _T_4152 = and(_T_4151, _T_4143) @[dec_dec_ctl.scala 17:17] + node _T_4153 = and(_T_4152, _T_4145) @[dec_dec_ctl.scala 17:17] + node _T_4154 = and(_T_4153, _T_4147) @[dec_dec_ctl.scala 17:17] + node _T_4155 = and(_T_4154, _T_4148) @[dec_dec_ctl.scala 17:17] + node _T_4156 = and(_T_4155, _T_4149) @[dec_dec_ctl.scala 17:17] + node _T_4157 = or(_T_4138, _T_4156) @[dec_dec_ctl.scala 261:79] + node _T_4158 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_4159 = eq(_T_4158, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4160 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_4161 = eq(_T_4160, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4162 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_4163 = eq(_T_4162, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4164 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_4165 = eq(_T_4164, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4166 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53] + node _T_4167 = eq(_T_4166, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4168 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53] + node _T_4169 = eq(_T_4168, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4170 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53] + node _T_4171 = eq(_T_4170, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4172 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53] + node _T_4173 = eq(_T_4172, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4174 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53] + node _T_4175 = eq(_T_4174, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4176 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53] + node _T_4177 = eq(_T_4176, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4178 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53] + node _T_4179 = eq(_T_4178, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4180 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53] + node _T_4181 = eq(_T_4180, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4182 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53] + node _T_4183 = eq(_T_4182, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4184 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53] + node _T_4185 = eq(_T_4184, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4186 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53] + node _T_4187 = eq(_T_4186, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4188 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53] + node _T_4189 = eq(_T_4188, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4190 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53] + node _T_4191 = eq(_T_4190, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4192 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_4193 = eq(_T_4192, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4194 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_4195 = eq(_T_4194, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4196 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53] + node _T_4197 = eq(_T_4196, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4198 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53] + node _T_4199 = eq(_T_4198, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4200 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53] + node _T_4201 = eq(_T_4200, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4202 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53] + node _T_4203 = eq(_T_4202, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4204 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53] + node _T_4205 = eq(_T_4204, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4206 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4207 = eq(_T_4206, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4208 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_4209 = eq(_T_4208, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4210 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4211 = eq(_T_4210, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4212 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_4213 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_4214 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4215 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4216 = and(_T_4159, _T_4161) @[dec_dec_ctl.scala 17:17] + node _T_4217 = and(_T_4216, _T_4163) @[dec_dec_ctl.scala 17:17] + node _T_4218 = and(_T_4217, _T_4165) @[dec_dec_ctl.scala 17:17] + node _T_4219 = and(_T_4218, _T_4167) @[dec_dec_ctl.scala 17:17] + node _T_4220 = and(_T_4219, _T_4169) @[dec_dec_ctl.scala 17:17] + node _T_4221 = and(_T_4220, _T_4171) @[dec_dec_ctl.scala 17:17] + node _T_4222 = and(_T_4221, _T_4173) @[dec_dec_ctl.scala 17:17] + node _T_4223 = and(_T_4222, _T_4175) @[dec_dec_ctl.scala 17:17] + node _T_4224 = and(_T_4223, _T_4177) @[dec_dec_ctl.scala 17:17] + node _T_4225 = and(_T_4224, _T_4179) @[dec_dec_ctl.scala 17:17] + node _T_4226 = and(_T_4225, _T_4181) @[dec_dec_ctl.scala 17:17] + node _T_4227 = and(_T_4226, _T_4183) @[dec_dec_ctl.scala 17:17] + node _T_4228 = and(_T_4227, _T_4185) @[dec_dec_ctl.scala 17:17] + node _T_4229 = and(_T_4228, _T_4187) @[dec_dec_ctl.scala 17:17] + node _T_4230 = and(_T_4229, _T_4189) @[dec_dec_ctl.scala 17:17] + node _T_4231 = and(_T_4230, _T_4191) @[dec_dec_ctl.scala 17:17] + node _T_4232 = and(_T_4231, _T_4193) @[dec_dec_ctl.scala 17:17] + node _T_4233 = and(_T_4232, _T_4195) @[dec_dec_ctl.scala 17:17] + node _T_4234 = and(_T_4233, _T_4197) @[dec_dec_ctl.scala 17:17] + node _T_4235 = and(_T_4234, _T_4199) @[dec_dec_ctl.scala 17:17] + node _T_4236 = and(_T_4235, _T_4201) @[dec_dec_ctl.scala 17:17] + node _T_4237 = and(_T_4236, _T_4203) @[dec_dec_ctl.scala 17:17] + node _T_4238 = and(_T_4237, _T_4205) @[dec_dec_ctl.scala 17:17] + node _T_4239 = and(_T_4238, _T_4207) @[dec_dec_ctl.scala 17:17] + node _T_4240 = and(_T_4239, _T_4209) @[dec_dec_ctl.scala 17:17] + node _T_4241 = and(_T_4240, _T_4211) @[dec_dec_ctl.scala 17:17] + node _T_4242 = and(_T_4241, _T_4212) @[dec_dec_ctl.scala 17:17] + node _T_4243 = and(_T_4242, _T_4213) @[dec_dec_ctl.scala 17:17] + node _T_4244 = and(_T_4243, _T_4214) @[dec_dec_ctl.scala 17:17] + node _T_4245 = and(_T_4244, _T_4215) @[dec_dec_ctl.scala 17:17] + node _T_4246 = or(_T_4157, _T_4245) @[dec_dec_ctl.scala 261:117] + node _T_4247 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53] + node _T_4248 = eq(_T_4247, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4249 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53] + node _T_4250 = eq(_T_4249, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4251 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53] + node _T_4252 = eq(_T_4251, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4253 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53] + node _T_4254 = eq(_T_4253, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4255 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53] + node _T_4256 = eq(_T_4255, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4257 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53] + node _T_4258 = eq(_T_4257, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4259 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53] + node _T_4260 = eq(_T_4259, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4261 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53] + node _T_4262 = eq(_T_4261, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4263 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53] + node _T_4264 = eq(_T_4263, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4265 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_4266 = eq(_T_4265, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4267 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_4268 = eq(_T_4267, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4269 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_4270 = eq(_T_4269, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4271 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53] + node _T_4272 = eq(_T_4271, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4273 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53] + node _T_4274 = eq(_T_4273, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4275 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53] + node _T_4276 = eq(_T_4275, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4277 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53] + node _T_4278 = eq(_T_4277, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4279 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53] + node _T_4280 = eq(_T_4279, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4281 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4282 = eq(_T_4281, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4283 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_4284 = eq(_T_4283, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4285 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4286 = eq(_T_4285, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4287 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_4288 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_4289 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4290 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4291 = and(_T_4248, _T_4250) @[dec_dec_ctl.scala 17:17] + node _T_4292 = and(_T_4291, _T_4252) @[dec_dec_ctl.scala 17:17] + node _T_4293 = and(_T_4292, _T_4254) @[dec_dec_ctl.scala 17:17] + node _T_4294 = and(_T_4293, _T_4256) @[dec_dec_ctl.scala 17:17] + node _T_4295 = and(_T_4294, _T_4258) @[dec_dec_ctl.scala 17:17] + node _T_4296 = and(_T_4295, _T_4260) @[dec_dec_ctl.scala 17:17] + node _T_4297 = and(_T_4296, _T_4262) @[dec_dec_ctl.scala 17:17] + node _T_4298 = and(_T_4297, _T_4264) @[dec_dec_ctl.scala 17:17] + node _T_4299 = and(_T_4298, _T_4266) @[dec_dec_ctl.scala 17:17] + node _T_4300 = and(_T_4299, _T_4268) @[dec_dec_ctl.scala 17:17] + node _T_4301 = and(_T_4300, _T_4270) @[dec_dec_ctl.scala 17:17] + node _T_4302 = and(_T_4301, _T_4272) @[dec_dec_ctl.scala 17:17] + node _T_4303 = and(_T_4302, _T_4274) @[dec_dec_ctl.scala 17:17] + node _T_4304 = and(_T_4303, _T_4276) @[dec_dec_ctl.scala 17:17] + node _T_4305 = and(_T_4304, _T_4278) @[dec_dec_ctl.scala 17:17] + node _T_4306 = and(_T_4305, _T_4280) @[dec_dec_ctl.scala 17:17] + node _T_4307 = and(_T_4306, _T_4282) @[dec_dec_ctl.scala 17:17] + node _T_4308 = and(_T_4307, _T_4284) @[dec_dec_ctl.scala 17:17] + node _T_4309 = and(_T_4308, _T_4286) @[dec_dec_ctl.scala 17:17] + node _T_4310 = and(_T_4309, _T_4287) @[dec_dec_ctl.scala 17:17] + node _T_4311 = and(_T_4310, _T_4288) @[dec_dec_ctl.scala 17:17] + node _T_4312 = and(_T_4311, _T_4289) @[dec_dec_ctl.scala 17:17] + node _T_4313 = and(_T_4312, _T_4290) @[dec_dec_ctl.scala 17:17] + node _T_4314 = or(_T_4246, _T_4313) @[dec_dec_ctl.scala 262:130] + node _T_4315 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_4316 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_4317 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4318 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_4319 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4320 = eq(_T_4319, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4321 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4322 = eq(_T_4321, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4323 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4324 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4325 = and(_T_4315, _T_4316) @[dec_dec_ctl.scala 17:17] + node _T_4326 = and(_T_4325, _T_4317) @[dec_dec_ctl.scala 17:17] + node _T_4327 = and(_T_4326, _T_4318) @[dec_dec_ctl.scala 17:17] + node _T_4328 = and(_T_4327, _T_4320) @[dec_dec_ctl.scala 17:17] + node _T_4329 = and(_T_4328, _T_4322) @[dec_dec_ctl.scala 17:17] + node _T_4330 = and(_T_4329, _T_4323) @[dec_dec_ctl.scala 17:17] + node _T_4331 = and(_T_4330, _T_4324) @[dec_dec_ctl.scala 17:17] + node _T_4332 = or(_T_4314, _T_4331) @[dec_dec_ctl.scala 263:102] + node _T_4333 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34] + node _T_4334 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34] + node _T_4335 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4336 = eq(_T_4335, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4337 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34] + node _T_4338 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_4339 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4340 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4341 = and(_T_4333, _T_4334) @[dec_dec_ctl.scala 17:17] + node _T_4342 = and(_T_4341, _T_4336) @[dec_dec_ctl.scala 17:17] + node _T_4343 = and(_T_4342, _T_4337) @[dec_dec_ctl.scala 17:17] + node _T_4344 = and(_T_4343, _T_4338) @[dec_dec_ctl.scala 17:17] + node _T_4345 = and(_T_4344, _T_4339) @[dec_dec_ctl.scala 17:17] + node _T_4346 = and(_T_4345, _T_4340) @[dec_dec_ctl.scala 17:17] + node _T_4347 = or(_T_4332, _T_4346) @[dec_dec_ctl.scala 264:39] + node _T_4348 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53] + node _T_4349 = eq(_T_4348, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4350 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53] + node _T_4351 = eq(_T_4350, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4352 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4353 = eq(_T_4352, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4354 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4355 = eq(_T_4354, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4356 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4357 = eq(_T_4356, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4358 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4359 = eq(_T_4358, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4360 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4361 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4362 = and(_T_4349, _T_4351) @[dec_dec_ctl.scala 17:17] + node _T_4363 = and(_T_4362, _T_4353) @[dec_dec_ctl.scala 17:17] + node _T_4364 = and(_T_4363, _T_4355) @[dec_dec_ctl.scala 17:17] + node _T_4365 = and(_T_4364, _T_4357) @[dec_dec_ctl.scala 17:17] + node _T_4366 = and(_T_4365, _T_4359) @[dec_dec_ctl.scala 17:17] + node _T_4367 = and(_T_4366, _T_4360) @[dec_dec_ctl.scala 17:17] + node _T_4368 = and(_T_4367, _T_4361) @[dec_dec_ctl.scala 17:17] + node _T_4369 = or(_T_4347, _T_4368) @[dec_dec_ctl.scala 264:71] + node _T_4370 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53] + node _T_4371 = eq(_T_4370, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4372 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4373 = eq(_T_4372, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4374 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_4375 = eq(_T_4374, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4376 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53] + node _T_4377 = eq(_T_4376, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4378 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4379 = eq(_T_4378, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4380 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53] + node _T_4381 = eq(_T_4380, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4382 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4383 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4384 = and(_T_4371, _T_4373) @[dec_dec_ctl.scala 17:17] + node _T_4385 = and(_T_4384, _T_4375) @[dec_dec_ctl.scala 17:17] + node _T_4386 = and(_T_4385, _T_4377) @[dec_dec_ctl.scala 17:17] + node _T_4387 = and(_T_4386, _T_4379) @[dec_dec_ctl.scala 17:17] + node _T_4388 = and(_T_4387, _T_4381) @[dec_dec_ctl.scala 17:17] + node _T_4389 = and(_T_4388, _T_4382) @[dec_dec_ctl.scala 17:17] + node _T_4390 = and(_T_4389, _T_4383) @[dec_dec_ctl.scala 17:17] + node _T_4391 = or(_T_4369, _T_4390) @[dec_dec_ctl.scala 264:112] + node _T_4392 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34] + node _T_4393 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4394 = eq(_T_4393, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4395 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53] + node _T_4396 = eq(_T_4395, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4397 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_4398 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4399 = eq(_T_4398, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4400 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4401 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4402 = and(_T_4392, _T_4394) @[dec_dec_ctl.scala 17:17] + node _T_4403 = and(_T_4402, _T_4396) @[dec_dec_ctl.scala 17:17] + node _T_4404 = and(_T_4403, _T_4397) @[dec_dec_ctl.scala 17:17] + node _T_4405 = and(_T_4404, _T_4399) @[dec_dec_ctl.scala 17:17] + node _T_4406 = and(_T_4405, _T_4400) @[dec_dec_ctl.scala 17:17] + node _T_4407 = and(_T_4406, _T_4401) @[dec_dec_ctl.scala 17:17] + node _T_4408 = or(_T_4391, _T_4407) @[dec_dec_ctl.scala 265:43] + node _T_4409 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53] + node _T_4410 = eq(_T_4409, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4411 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34] + node _T_4412 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53] + node _T_4413 = eq(_T_4412, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46] + node _T_4414 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34] + node _T_4415 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34] + node _T_4416 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34] + node _T_4417 = and(_T_4410, _T_4411) @[dec_dec_ctl.scala 17:17] + node _T_4418 = and(_T_4417, _T_4413) @[dec_dec_ctl.scala 17:17] + node _T_4419 = and(_T_4418, _T_4414) @[dec_dec_ctl.scala 17:17] + node _T_4420 = and(_T_4419, _T_4415) @[dec_dec_ctl.scala 17:17] + node _T_4421 = and(_T_4420, _T_4416) @[dec_dec_ctl.scala 17:17] + node _T_4422 = or(_T_4408, _T_4421) @[dec_dec_ctl.scala 265:78] + io.out.legal <= _T_4422 @[dec_dec_ctl.scala 248:16] + + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_10 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module dec_decode_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_branch_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_result_r : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<4>, flip dec_i0_rs2_bypass_en_d : UInt<4>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, flip dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, flip dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, flip dec_aln : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}, flip dec_tlu_trace_disable : UInt<1>, flip dec_debug_valid_d : UInt<1>, flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_i0_inst_wb : UInt<32>, dec_i0_pc_wb : UInt<31>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_second_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_bp_fa_index : UInt<9>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip active_clk : Clock, flip free_l2clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, dec_qual_lsu_d : UInt<1>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, div_waddr_wb : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, dec_fa_error_index : UInt<9>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>} + + wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[dec_decode_ctl.scala 117:40] + _T.bits.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.crc32c_w <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.crc32c_h <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.crc32c_b <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.crc32_w <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.crc32_h <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.crc32_b <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.unshfl <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.shfl <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.gorc <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.grev <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.clmulr <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.clmulh <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.clmul <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.bdep <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.bext <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.low <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.bits.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + _T.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 117:40] + io.decode_exu.mul_p.bits.bfp <= _T.bits.bfp @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.crc32c_w <= _T.bits.crc32c_w @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.crc32c_h <= _T.bits.crc32c_h @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.crc32c_b <= _T.bits.crc32c_b @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.crc32_w <= _T.bits.crc32_w @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.crc32_h <= _T.bits.crc32_h @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.crc32_b <= _T.bits.crc32_b @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.unshfl <= _T.bits.unshfl @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.shfl <= _T.bits.shfl @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.gorc <= _T.bits.gorc @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.grev <= _T.bits.grev @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.clmulr <= _T.bits.clmulr @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.clmulh <= _T.bits.clmulh @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.clmul <= _T.bits.clmul @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.bdep <= _T.bits.bdep @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.bext <= _T.bits.bext @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.low <= _T.bits.low @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.rs2_sign <= _T.bits.rs2_sign @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.bits.rs1_sign <= _T.bits.rs1_sign @[dec_decode_ctl.scala 117:25] + io.decode_exu.mul_p.valid <= _T.valid @[dec_decode_ctl.scala 117:25] + wire leak1_i1_stall_in : UInt<1> + leak1_i1_stall_in <= UInt<1>("h00") + wire leak1_i0_stall_in : UInt<1> + leak1_i0_stall_in <= UInt<1>("h00") + wire i0r : {rs1 : UInt<5>, rs2 : UInt<5>, rd : UInt<5>} @[dec_decode_ctl.scala 121:37] + wire d_t : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 122:37] + wire x_t : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 123:37] + wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 124:37] + wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 125:37] + wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 126:37] + wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 127:37] + wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 128:37] + wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 129:37] + wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 130:37] + wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 131:37] + wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 132:37] + wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 133:37] + wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 134:37] + wire i0_rs1_depth_d : UInt<2> + i0_rs1_depth_d <= UInt<1>("h00") + wire i0_rs2_depth_d : UInt<2> + i0_rs2_depth_d <= UInt<1>("h00") + wire cam_wen : UInt<4> + cam_wen <= UInt<1>("h00") + wire cam : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 138:37] + wire cam_write : UInt<1> + cam_write <= UInt<1>("h00") + wire cam_inv_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 140:37] + wire cam_data_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 141:37] + wire nonblock_load_write : UInt<1>[4] @[dec_decode_ctl.scala 142:37] + wire cam_raw : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 143:37] + wire cam_in : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 144:37] + wire i0_dp : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, zbs : UInt<1>, bext : UInt<1>, bdep : UInt<1>, zbe : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, zbc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, zbp : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, zbr : UInt<1>, bfp : UInt<1>, zbf : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 145:37] + wire i0_dp_raw : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, zbs : UInt<1>, bext : UInt<1>, bdep : UInt<1>, zbe : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, zbc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, zbp : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, zbr : UInt<1>, bfp : UInt<1>, zbf : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 146:37] + wire i0_rs1bypass : UInt<3> + i0_rs1bypass <= UInt<1>("h00") + wire i0_rs2bypass : UInt<3> + i0_rs2bypass <= UInt<1>("h00") + wire illegal_lockout : UInt<1> + illegal_lockout <= UInt<1>("h00") + wire postsync_stall : UInt<1> + postsync_stall <= UInt<1>("h00") + wire ps_stall_in : UInt<1> + ps_stall_in <= UInt<1>("h00") + wire i0_pipe_en : UInt<4> + i0_pipe_en <= UInt<1>("h00") + wire i0_load_block_d : UInt<1> + i0_load_block_d <= UInt<1>("h00") + wire load_ldst_bypass_d : UInt<1> + load_ldst_bypass_d <= UInt<1>("h00") + wire store_data_bypass_d : UInt<1> + store_data_bypass_d <= UInt<1>("h00") + wire store_data_bypass_m : UInt<1> + store_data_bypass_m <= UInt<1>("h00") + wire tlu_wr_pause_r1 : UInt<1> + tlu_wr_pause_r1 <= UInt<1>("h00") + wire tlu_wr_pause_r2 : UInt<1> + tlu_wr_pause_r2 <= UInt<1>("h00") + wire leak1_i1_stall : UInt<1> + leak1_i1_stall <= UInt<1>("h00") + wire leak1_i0_stall : UInt<1> + leak1_i0_stall <= UInt<1>("h00") + wire pause_stall : UInt<1> + pause_stall <= UInt<1>("h00") + wire flush_final_r : UInt<1> + flush_final_r <= UInt<1>("h00") + wire illegal_lockout_in : UInt<1> + illegal_lockout_in <= UInt<1>("h00") + wire lsu_idle : UInt<1> + lsu_idle <= UInt<1>("h00") + wire pause_state_in : UInt<1> + pause_state_in <= UInt<1>("h00") + wire leak1_mode : UInt<1> + leak1_mode <= UInt<1>("h00") + wire i0_pcall : UInt<1> + i0_pcall <= UInt<1>("h00") + wire i0_pja : UInt<1> + i0_pja <= UInt<1>("h00") + wire i0_pret : UInt<1> + i0_pret <= UInt<1>("h00") + wire i0_legal_decode_d : UInt<1> + i0_legal_decode_d <= UInt<1>("h00") + wire i0_pcall_raw : UInt<1> + i0_pcall_raw <= UInt<1>("h00") + wire i0_pja_raw : UInt<1> + i0_pja_raw <= UInt<1>("h00") + wire i0_pret_raw : UInt<1> + i0_pret_raw <= UInt<1>("h00") + wire i0_br_offset : UInt<12> + i0_br_offset <= UInt<1>("h00") + wire i0_csr_write_only_d : UInt<1> + i0_csr_write_only_d <= UInt<1>("h00") + wire i0_jal : UInt<1> + i0_jal <= UInt<1>("h00") + wire i0_wen_r : UInt<1> + i0_wen_r <= UInt<1>("h00") + wire i0_x_ctl_en : UInt<1> + i0_x_ctl_en <= UInt<1>("h00") + wire i0_r_ctl_en : UInt<1> + i0_r_ctl_en <= UInt<1>("h00") + wire i0_wb_ctl_en : UInt<1> + i0_wb_ctl_en <= UInt<1>("h00") + wire i0_x_data_en : UInt<1> + i0_x_data_en <= UInt<1>("h00") + wire i0_r_data_en : UInt<1> + i0_r_data_en <= UInt<1>("h00") + wire i0_wb_data_en : UInt<1> + i0_wb_data_en <= UInt<1>("h00") + wire i0_wb1_data_en : UInt<1> + i0_wb1_data_en <= UInt<1>("h00") + wire i0_nonblock_load_stall : UInt<1> + i0_nonblock_load_stall <= UInt<1>("h00") + wire csr_read : UInt<1> + csr_read <= UInt<1>("h00") + wire lsu_decode_d : UInt<1> + lsu_decode_d <= UInt<1>("h00") + wire mul_decode_d : UInt<1> + mul_decode_d <= UInt<1>("h00") + wire div_decode_d : UInt<1> + div_decode_d <= UInt<1>("h00") + wire write_csr_data : UInt<32> + write_csr_data <= UInt<1>("h00") + wire i0_result_corr_r : UInt<32> + i0_result_corr_r <= UInt<1>("h00") + wire presync_stall : UInt<1> + presync_stall <= UInt<1>("h00") + wire i0_nonblock_div_stall : UInt<1> + i0_nonblock_div_stall <= UInt<1>("h00") + wire debug_fence : UInt<1> + debug_fence <= UInt<1>("h00") + wire i0_immed_d : UInt<32> + i0_immed_d <= UInt<1>("h00") + wire i0_result_x : UInt<32> + i0_result_x <= UInt<1>("h00") + wire i0_result_r : UInt<32> + i0_result_r <= UInt<1>("h00") + wire i0_br_error_all : UInt<1> + i0_br_error_all <= UInt<1>("h00") + wire i0_brp_valid : UInt<1> + i0_brp_valid <= UInt<1>("h00") + wire btb_error_found_f : UInt<1> + btb_error_found_f <= UInt<1>("h00") + wire fa_error_index_ns : UInt<1> + fa_error_index_ns <= UInt<1>("h00") + wire btb_error_found : UInt<1> + btb_error_found <= UInt<1>("h00") + wire div_active_in : UInt<1> + div_active_in <= UInt<1>("h00") + wire _T_1 : UInt + _T_1 <= UInt<1>("h00") + node _T_2 = xor(leak1_i1_stall_in, _T_1) @[lib.scala 448:21] + node _T_3 = orr(_T_2) @[lib.scala 448:29] + reg _T_4 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3 : @[Reg.scala 28:19] + _T_4 <= leak1_i1_stall_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1 <= _T_4 @[lib.scala 451:16] + leak1_i1_stall <= _T_1 @[dec_decode_ctl.scala 206:35] + wire _T_5 : UInt + _T_5 <= UInt<1>("h00") + node _T_6 = xor(leak1_i0_stall_in, _T_5) @[lib.scala 448:21] + node _T_7 = orr(_T_6) @[lib.scala 448:29] + reg _T_8 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7 : @[Reg.scala 28:19] + _T_8 <= leak1_i0_stall_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_5 <= _T_8 @[lib.scala 451:16] + leak1_i0_stall <= _T_5 @[dec_decode_ctl.scala 207:35] + wire _T_9 : UInt<1> + _T_9 <= UInt<1>("h00") + node _T_10 = xor(io.dec_tlu_flush_extint, _T_9) @[lib.scala 470:21] + node _T_11 = orr(_T_10) @[lib.scala 470:29] + reg _T_12 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_11 : @[Reg.scala 28:19] + _T_12 <= io.dec_tlu_flush_extint @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_9 <= _T_12 @[lib.scala 473:16] + io.decode_exu.dec_extint_stall <= _T_9 @[dec_decode_ctl.scala 208:35] + wire _T_13 : UInt<1> + _T_13 <= UInt<1>("h00") + node _T_14 = xor(pause_state_in, _T_13) @[lib.scala 470:21] + node _T_15 = orr(_T_14) @[lib.scala 470:29] + reg _T_16 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_15 : @[Reg.scala 28:19] + _T_16 <= pause_state_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_13 <= _T_16 @[lib.scala 473:16] + pause_stall <= _T_13 @[dec_decode_ctl.scala 209:35] + wire _T_17 : UInt<1> + _T_17 <= UInt<1>("h00") + node _T_18 = xor(io.dec_tlu_wr_pause_r, _T_17) @[lib.scala 470:21] + node _T_19 = orr(_T_18) @[lib.scala 470:29] + reg _T_20 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_19 : @[Reg.scala 28:19] + _T_20 <= io.dec_tlu_wr_pause_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_17 <= _T_20 @[lib.scala 473:16] + tlu_wr_pause_r1 <= _T_17 @[dec_decode_ctl.scala 210:35] + wire _T_21 : UInt + _T_21 <= UInt<1>("h00") + node _T_22 = xor(tlu_wr_pause_r1, _T_21) @[lib.scala 448:21] + node _T_23 = orr(_T_22) @[lib.scala 448:29] + reg _T_24 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_23 : @[Reg.scala 28:19] + _T_24 <= tlu_wr_pause_r1 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_21 <= _T_24 @[lib.scala 451:16] + tlu_wr_pause_r2 <= _T_21 @[dec_decode_ctl.scala 211:35] + wire _T_25 : UInt + _T_25 <= UInt<1>("h00") + node _T_26 = xor(illegal_lockout_in, _T_25) @[lib.scala 448:21] + node _T_27 = orr(_T_26) @[lib.scala 448:29] + reg _T_28 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_27 : @[Reg.scala 28:19] + _T_28 <= illegal_lockout_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_25 <= _T_28 @[lib.scala 451:16] + illegal_lockout <= _T_25 @[dec_decode_ctl.scala 212:35] + wire _T_29 : UInt + _T_29 <= UInt<1>("h00") + node _T_30 = xor(ps_stall_in, _T_29) @[lib.scala 448:21] + node _T_31 = orr(_T_30) @[lib.scala 448:29] + reg _T_32 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_31 : @[Reg.scala 28:19] + _T_32 <= ps_stall_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_29 <= _T_32 @[lib.scala 451:16] + postsync_stall <= _T_29 @[dec_decode_ctl.scala 213:35] + wire lsu_trigger_match_r : UInt + lsu_trigger_match_r <= UInt<1>("h00") + node _T_33 = xor(io.lsu_trigger_match_m, lsu_trigger_match_r) @[lib.scala 448:21] + node _T_34 = orr(_T_33) @[lib.scala 448:29] + reg _T_35 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_34 : @[Reg.scala 28:19] + _T_35 <= io.lsu_trigger_match_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + lsu_trigger_match_r <= _T_35 @[lib.scala 451:16] + wire lsu_pmu_misaligned_r : UInt<1> + lsu_pmu_misaligned_r <= UInt<1>("h00") + node _T_36 = xor(io.lsu_pmu_misaligned_m, lsu_pmu_misaligned_r) @[lib.scala 470:21] + node _T_37 = orr(_T_36) @[lib.scala 470:29] + reg _T_38 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_37 : @[Reg.scala 28:19] + _T_38 <= io.lsu_pmu_misaligned_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + lsu_pmu_misaligned_r <= _T_38 @[lib.scala 473:16] + wire _T_39 : UInt<1> + _T_39 <= UInt<1>("h00") + node _T_40 = xor(div_active_in, _T_39) @[lib.scala 470:21] + node _T_41 = orr(_T_40) @[lib.scala 470:29] + reg _T_42 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_41 : @[Reg.scala 28:19] + _T_42 <= div_active_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_39 <= _T_42 @[lib.scala 473:16] + io.dec_div_active <= _T_39 @[dec_decode_ctl.scala 217:35] + wire _T_43 : UInt<1> + _T_43 <= UInt<1>("h00") + node _T_44 = xor(io.exu_flush_final, _T_43) @[lib.scala 470:21] + node _T_45 = orr(_T_44) @[lib.scala 470:29] + reg _T_46 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_45 : @[Reg.scala 28:19] + _T_46 <= io.exu_flush_final @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_43 <= _T_46 @[lib.scala 473:16] + flush_final_r <= _T_43 @[dec_decode_ctl.scala 218:35] + wire debug_valid_x : UInt<1> + debug_valid_x <= UInt<1>("h00") + node _T_47 = xor(io.dec_debug_valid_d, debug_valid_x) @[lib.scala 470:21] + node _T_48 = orr(_T_47) @[lib.scala 470:29] + reg _T_49 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_48 : @[Reg.scala 28:19] + _T_49 <= io.dec_debug_valid_d @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + debug_valid_x <= _T_49 @[lib.scala 473:16] + node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[dec_decode_ctl.scala 220:43] + node _T_50 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 222:82] + node _T_51 = and(io.dec_i0_brp.valid, _T_50) @[dec_decode_ctl.scala 222:80] + node _T_52 = eq(i0_icaf_d, UInt<1>("h00")) @[dec_decode_ctl.scala 222:96] + node _T_53 = and(_T_51, _T_52) @[dec_decode_ctl.scala 222:94] + i0_brp_valid <= _T_53 @[dec_decode_ctl.scala 222:57] + io.decode_exu.dec_i0_predict_p_d.bits.misp <= UInt<1>("h00") @[dec_decode_ctl.scala 223:57] + io.decode_exu.dec_i0_predict_p_d.bits.ataken <= UInt<1>("h00") @[dec_decode_ctl.scala 224:57] + io.decode_exu.dec_i0_predict_p_d.bits.boffset <= UInt<1>("h00") @[dec_decode_ctl.scala 225:57] + io.decode_exu.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[dec_decode_ctl.scala 226:57] + io.decode_exu.dec_i0_predict_p_d.bits.pja <= i0_pja @[dec_decode_ctl.scala 227:57] + io.decode_exu.dec_i0_predict_p_d.bits.pret <= i0_pret @[dec_decode_ctl.scala 228:57] + io.decode_exu.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[dec_decode_ctl.scala 229:57] + io.decode_exu.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[dec_decode_ctl.scala 230:57] + io.decode_exu.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[dec_decode_ctl.scala 231:57] + node _T_54 = and(i0_brp_valid, i0_legal_decode_d) @[dec_decode_ctl.scala 232:73] + io.decode_exu.dec_i0_predict_p_d.valid <= _T_54 @[dec_decode_ctl.scala 232:57] + node _T_55 = or(i0_dp_raw.condbr, i0_pcall_raw) @[dec_decode_ctl.scala 233:94] + node _T_56 = or(_T_55, i0_pja_raw) @[dec_decode_ctl.scala 233:109] + node _T_57 = or(_T_56, i0_pret_raw) @[dec_decode_ctl.scala 233:122] + node _T_58 = eq(_T_57, UInt<1>("h00")) @[dec_decode_ctl.scala 233:75] + node _T_59 = and(i0_brp_valid, _T_58) @[dec_decode_ctl.scala 233:73] + node _T_60 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 236:99] + node _T_61 = and(i0_brp_valid, _T_60) @[dec_decode_ctl.scala 236:74] + node _T_62 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[dec_decode_ctl.scala 236:133] + node _T_63 = and(_T_61, _T_62) @[dec_decode_ctl.scala 236:103] + node _T_64 = eq(i0_pret_raw, UInt<1>("h00")) @[dec_decode_ctl.scala 236:153] + node _T_65 = and(_T_63, _T_64) @[dec_decode_ctl.scala 236:151] + node _T_66 = xor(io.dec_i0_brp.bits.ret, i0_pret_raw) @[dec_decode_ctl.scala 237:100] + node _T_67 = and(i0_brp_valid, _T_66) @[dec_decode_ctl.scala 237:74] + node _T_68 = or(io.dec_i0_brp.bits.br_error, _T_59) @[dec_decode_ctl.scala 238:89] + node _T_69 = or(_T_68, _T_65) @[dec_decode_ctl.scala 238:106] + node _T_70 = or(_T_69, _T_67) @[dec_decode_ctl.scala 238:128] + node _T_71 = and(_T_70, i0_legal_decode_d) @[dec_decode_ctl.scala 239:74] + node _T_72 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 239:96] + node _T_73 = and(_T_71, _T_72) @[dec_decode_ctl.scala 239:94] + io.decode_exu.dec_i0_predict_p_d.bits.br_error <= _T_73 @[dec_decode_ctl.scala 239:58] + node _T_74 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[dec_decode_ctl.scala 240:96] + node _T_75 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 240:118] + node _T_76 = and(_T_74, _T_75) @[dec_decode_ctl.scala 240:116] + io.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= _T_76 @[dec_decode_ctl.scala 240:58] + io.decode_exu.i0_predict_index_d <= io.dec_i0_bp_index @[dec_decode_ctl.scala 241:58] + io.decode_exu.i0_predict_btag_d <= io.dec_i0_bp_btag @[dec_decode_ctl.scala 242:58] + node _T_77 = or(_T_70, io.dec_i0_brp.bits.br_start_error) @[dec_decode_ctl.scala 243:74] + node _T_78 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 243:113] + node _T_79 = and(_T_77, _T_78) @[dec_decode_ctl.scala 243:111] + i0_br_error_all <= _T_79 @[dec_decode_ctl.scala 243:58] + io.decode_exu.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[dec_decode_ctl.scala 244:58] + io.decode_exu.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[dec_decode_ctl.scala 245:58] + io.decode_exu.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[dec_decode_ctl.scala 246:58] + io.dec_fa_error_index <= UInt<1>("h00") @[dec_decode_ctl.scala 255:29] + i0_dp.legal <= i0_dp_raw.legal @[dec_decode_ctl.scala 279:23] + i0_dp.pm_alu <= i0_dp_raw.pm_alu @[dec_decode_ctl.scala 279:23] + i0_dp.fence_i <= i0_dp_raw.fence_i @[dec_decode_ctl.scala 279:23] + i0_dp.fence <= i0_dp_raw.fence @[dec_decode_ctl.scala 279:23] + i0_dp.rem <= i0_dp_raw.rem @[dec_decode_ctl.scala 279:23] + i0_dp.div <= i0_dp_raw.div @[dec_decode_ctl.scala 279:23] + i0_dp.low <= i0_dp_raw.low @[dec_decode_ctl.scala 279:23] + i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[dec_decode_ctl.scala 279:23] + i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[dec_decode_ctl.scala 279:23] + i0_dp.mul <= i0_dp_raw.mul @[dec_decode_ctl.scala 279:23] + i0_dp.mret <= i0_dp_raw.mret @[dec_decode_ctl.scala 279:23] + i0_dp.ecall <= i0_dp_raw.ecall @[dec_decode_ctl.scala 279:23] + i0_dp.ebreak <= i0_dp_raw.ebreak @[dec_decode_ctl.scala 279:23] + i0_dp.postsync <= i0_dp_raw.postsync @[dec_decode_ctl.scala 279:23] + i0_dp.presync <= i0_dp_raw.presync @[dec_decode_ctl.scala 279:23] + i0_dp.csr_imm <= i0_dp_raw.csr_imm @[dec_decode_ctl.scala 279:23] + i0_dp.csr_write <= i0_dp_raw.csr_write @[dec_decode_ctl.scala 279:23] + i0_dp.csr_set <= i0_dp_raw.csr_set @[dec_decode_ctl.scala 279:23] + i0_dp.csr_clr <= i0_dp_raw.csr_clr @[dec_decode_ctl.scala 279:23] + i0_dp.csr_read <= i0_dp_raw.csr_read @[dec_decode_ctl.scala 279:23] + i0_dp.word <= i0_dp_raw.word @[dec_decode_ctl.scala 279:23] + i0_dp.half <= i0_dp_raw.half @[dec_decode_ctl.scala 279:23] + i0_dp.by <= i0_dp_raw.by @[dec_decode_ctl.scala 279:23] + i0_dp.jal <= i0_dp_raw.jal @[dec_decode_ctl.scala 279:23] + i0_dp.blt <= i0_dp_raw.blt @[dec_decode_ctl.scala 279:23] + i0_dp.bge <= i0_dp_raw.bge @[dec_decode_ctl.scala 279:23] + i0_dp.bne <= i0_dp_raw.bne @[dec_decode_ctl.scala 279:23] + i0_dp.beq <= i0_dp_raw.beq @[dec_decode_ctl.scala 279:23] + i0_dp.condbr <= i0_dp_raw.condbr @[dec_decode_ctl.scala 279:23] + i0_dp.unsign <= i0_dp_raw.unsign @[dec_decode_ctl.scala 279:23] + i0_dp.slt <= i0_dp_raw.slt @[dec_decode_ctl.scala 279:23] + i0_dp.srl <= i0_dp_raw.srl @[dec_decode_ctl.scala 279:23] + i0_dp.sra <= i0_dp_raw.sra @[dec_decode_ctl.scala 279:23] + i0_dp.sll <= i0_dp_raw.sll @[dec_decode_ctl.scala 279:23] + i0_dp.lxor <= i0_dp_raw.lxor @[dec_decode_ctl.scala 279:23] + i0_dp.lor <= i0_dp_raw.lor @[dec_decode_ctl.scala 279:23] + i0_dp.land <= i0_dp_raw.land @[dec_decode_ctl.scala 279:23] + i0_dp.sub <= i0_dp_raw.sub @[dec_decode_ctl.scala 279:23] + i0_dp.add <= i0_dp_raw.add @[dec_decode_ctl.scala 279:23] + i0_dp.lsu <= i0_dp_raw.lsu @[dec_decode_ctl.scala 279:23] + i0_dp.store <= i0_dp_raw.store @[dec_decode_ctl.scala 279:23] + i0_dp.load <= i0_dp_raw.load @[dec_decode_ctl.scala 279:23] + i0_dp.pc <= i0_dp_raw.pc @[dec_decode_ctl.scala 279:23] + i0_dp.imm20 <= i0_dp_raw.imm20 @[dec_decode_ctl.scala 279:23] + i0_dp.shimm5 <= i0_dp_raw.shimm5 @[dec_decode_ctl.scala 279:23] + i0_dp.rd <= i0_dp_raw.rd @[dec_decode_ctl.scala 279:23] + i0_dp.imm12 <= i0_dp_raw.imm12 @[dec_decode_ctl.scala 279:23] + i0_dp.rs2 <= i0_dp_raw.rs2 @[dec_decode_ctl.scala 279:23] + i0_dp.rs1 <= i0_dp_raw.rs1 @[dec_decode_ctl.scala 279:23] + i0_dp.alu <= i0_dp_raw.alu @[dec_decode_ctl.scala 279:23] + i0_dp.zba <= i0_dp_raw.zba @[dec_decode_ctl.scala 279:23] + i0_dp.sh3add <= i0_dp_raw.sh3add @[dec_decode_ctl.scala 279:23] + i0_dp.sh2add <= i0_dp_raw.sh2add @[dec_decode_ctl.scala 279:23] + i0_dp.sh1add <= i0_dp_raw.sh1add @[dec_decode_ctl.scala 279:23] + i0_dp.zbf <= i0_dp_raw.zbf @[dec_decode_ctl.scala 279:23] + i0_dp.bfp <= i0_dp_raw.bfp @[dec_decode_ctl.scala 279:23] + i0_dp.zbr <= i0_dp_raw.zbr @[dec_decode_ctl.scala 279:23] + i0_dp.crc32c_w <= i0_dp_raw.crc32c_w @[dec_decode_ctl.scala 279:23] + i0_dp.crc32c_h <= i0_dp_raw.crc32c_h @[dec_decode_ctl.scala 279:23] + i0_dp.crc32c_b <= i0_dp_raw.crc32c_b @[dec_decode_ctl.scala 279:23] + i0_dp.crc32_w <= i0_dp_raw.crc32_w @[dec_decode_ctl.scala 279:23] + i0_dp.crc32_h <= i0_dp_raw.crc32_h @[dec_decode_ctl.scala 279:23] + i0_dp.crc32_b <= i0_dp_raw.crc32_b @[dec_decode_ctl.scala 279:23] + i0_dp.zbp <= i0_dp_raw.zbp @[dec_decode_ctl.scala 279:23] + i0_dp.unshfl <= i0_dp_raw.unshfl @[dec_decode_ctl.scala 279:23] + i0_dp.shfl <= i0_dp_raw.shfl @[dec_decode_ctl.scala 279:23] + i0_dp.zbc <= i0_dp_raw.zbc @[dec_decode_ctl.scala 279:23] + i0_dp.clmulr <= i0_dp_raw.clmulr @[dec_decode_ctl.scala 279:23] + i0_dp.clmulh <= i0_dp_raw.clmulh @[dec_decode_ctl.scala 279:23] + i0_dp.clmul <= i0_dp_raw.clmul @[dec_decode_ctl.scala 279:23] + i0_dp.zbe <= i0_dp_raw.zbe @[dec_decode_ctl.scala 279:23] + i0_dp.bdep <= i0_dp_raw.bdep @[dec_decode_ctl.scala 279:23] + i0_dp.bext <= i0_dp_raw.bext @[dec_decode_ctl.scala 279:23] + i0_dp.zbs <= i0_dp_raw.zbs @[dec_decode_ctl.scala 279:23] + i0_dp.sbext <= i0_dp_raw.sbext @[dec_decode_ctl.scala 279:23] + i0_dp.sbinv <= i0_dp_raw.sbinv @[dec_decode_ctl.scala 279:23] + i0_dp.sbclr <= i0_dp_raw.sbclr @[dec_decode_ctl.scala 279:23] + i0_dp.sbset <= i0_dp_raw.sbset @[dec_decode_ctl.scala 279:23] + i0_dp.zbb <= i0_dp_raw.zbb @[dec_decode_ctl.scala 279:23] + i0_dp.gorc <= i0_dp_raw.gorc @[dec_decode_ctl.scala 279:23] + i0_dp.grev <= i0_dp_raw.grev @[dec_decode_ctl.scala 279:23] + i0_dp.ror <= i0_dp_raw.ror @[dec_decode_ctl.scala 279:23] + i0_dp.rol <= i0_dp_raw.rol @[dec_decode_ctl.scala 279:23] + i0_dp.packh <= i0_dp_raw.packh @[dec_decode_ctl.scala 279:23] + i0_dp.packu <= i0_dp_raw.packu @[dec_decode_ctl.scala 279:23] + i0_dp.pack <= i0_dp_raw.pack @[dec_decode_ctl.scala 279:23] + i0_dp.max <= i0_dp_raw.max @[dec_decode_ctl.scala 279:23] + i0_dp.min <= i0_dp_raw.min @[dec_decode_ctl.scala 279:23] + i0_dp.sro <= i0_dp_raw.sro @[dec_decode_ctl.scala 279:23] + i0_dp.slo <= i0_dp_raw.slo @[dec_decode_ctl.scala 279:23] + i0_dp.sext_h <= i0_dp_raw.sext_h @[dec_decode_ctl.scala 279:23] + i0_dp.sext_b <= i0_dp_raw.sext_b @[dec_decode_ctl.scala 279:23] + i0_dp.pcnt <= i0_dp_raw.pcnt @[dec_decode_ctl.scala 279:23] + i0_dp.ctz <= i0_dp_raw.ctz @[dec_decode_ctl.scala 279:23] + i0_dp.clz <= i0_dp_raw.clz @[dec_decode_ctl.scala 279:23] + node _T_80 = or(i0_br_error_all, i0_icaf_d) @[dec_decode_ctl.scala 280:25] + node _T_81 = bits(_T_80, 0, 0) @[dec_decode_ctl.scala 280:43] + when _T_81 : @[dec_decode_ctl.scala 280:50] + wire _T_82 : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, zbs : UInt<1>, bext : UInt<1>, bdep : UInt<1>, zbe : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, zbc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, zbp : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, zbr : UInt<1>, bfp : UInt<1>, zbf : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 281:38] + _T_82.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.pm_alu <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.fence <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.rem <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.div <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.low <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.mret <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.ecall <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.ebreak <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.postsync <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.presync <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.csr_imm <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.csr_write <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.csr_set <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.csr_clr <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.csr_read <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.word <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.half <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.by <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.jal <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.blt <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.bge <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.bne <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.beq <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.condbr <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.slt <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.srl <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sra <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sll <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.lxor <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.lor <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.land <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sub <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.add <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.lsu <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.store <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.load <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.pc <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.imm20 <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.shimm5 <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.rd <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.imm12 <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.rs2 <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.rs1 <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.zba <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sh3add <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sh2add <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sh1add <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.zbf <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.zbr <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.crc32c_w <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.crc32c_h <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.crc32c_b <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.crc32_w <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.crc32_h <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.crc32_b <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.zbp <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.unshfl <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.shfl <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.zbc <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.clmulr <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.clmulh <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.clmul <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.zbe <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.bdep <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.bext <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.zbs <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sbext <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sbinv <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sbclr <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sbset <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.zbb <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.gorc <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.grev <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.ror <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.rol <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.packh <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.packu <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.pack <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.max <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.min <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sro <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.slo <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sext_h <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.sext_b <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.pcnt <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.ctz <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + _T_82.clz <= UInt<1>("h00") @[dec_decode_ctl.scala 281:38] + i0_dp.legal <= _T_82.legal @[dec_decode_ctl.scala 281:23] + i0_dp.pm_alu <= _T_82.pm_alu @[dec_decode_ctl.scala 281:23] + i0_dp.fence_i <= _T_82.fence_i @[dec_decode_ctl.scala 281:23] + i0_dp.fence <= _T_82.fence @[dec_decode_ctl.scala 281:23] + i0_dp.rem <= _T_82.rem @[dec_decode_ctl.scala 281:23] + i0_dp.div <= _T_82.div @[dec_decode_ctl.scala 281:23] + i0_dp.low <= _T_82.low @[dec_decode_ctl.scala 281:23] + i0_dp.rs2_sign <= _T_82.rs2_sign @[dec_decode_ctl.scala 281:23] + i0_dp.rs1_sign <= _T_82.rs1_sign @[dec_decode_ctl.scala 281:23] + i0_dp.mul <= _T_82.mul @[dec_decode_ctl.scala 281:23] + i0_dp.mret <= _T_82.mret @[dec_decode_ctl.scala 281:23] + i0_dp.ecall <= _T_82.ecall @[dec_decode_ctl.scala 281:23] + i0_dp.ebreak <= _T_82.ebreak @[dec_decode_ctl.scala 281:23] + i0_dp.postsync <= _T_82.postsync @[dec_decode_ctl.scala 281:23] + i0_dp.presync <= _T_82.presync @[dec_decode_ctl.scala 281:23] + i0_dp.csr_imm <= _T_82.csr_imm @[dec_decode_ctl.scala 281:23] + i0_dp.csr_write <= _T_82.csr_write @[dec_decode_ctl.scala 281:23] + i0_dp.csr_set <= _T_82.csr_set @[dec_decode_ctl.scala 281:23] + i0_dp.csr_clr <= _T_82.csr_clr @[dec_decode_ctl.scala 281:23] + i0_dp.csr_read <= _T_82.csr_read @[dec_decode_ctl.scala 281:23] + i0_dp.word <= _T_82.word @[dec_decode_ctl.scala 281:23] + i0_dp.half <= _T_82.half @[dec_decode_ctl.scala 281:23] + i0_dp.by <= _T_82.by @[dec_decode_ctl.scala 281:23] + i0_dp.jal <= _T_82.jal @[dec_decode_ctl.scala 281:23] + i0_dp.blt <= _T_82.blt @[dec_decode_ctl.scala 281:23] + i0_dp.bge <= _T_82.bge @[dec_decode_ctl.scala 281:23] + i0_dp.bne <= _T_82.bne @[dec_decode_ctl.scala 281:23] + i0_dp.beq <= _T_82.beq @[dec_decode_ctl.scala 281:23] + i0_dp.condbr <= _T_82.condbr @[dec_decode_ctl.scala 281:23] + i0_dp.unsign <= _T_82.unsign @[dec_decode_ctl.scala 281:23] + i0_dp.slt <= _T_82.slt @[dec_decode_ctl.scala 281:23] + i0_dp.srl <= _T_82.srl @[dec_decode_ctl.scala 281:23] + i0_dp.sra <= _T_82.sra @[dec_decode_ctl.scala 281:23] + i0_dp.sll <= _T_82.sll @[dec_decode_ctl.scala 281:23] + i0_dp.lxor <= _T_82.lxor @[dec_decode_ctl.scala 281:23] + i0_dp.lor <= _T_82.lor @[dec_decode_ctl.scala 281:23] + i0_dp.land <= _T_82.land @[dec_decode_ctl.scala 281:23] + i0_dp.sub <= _T_82.sub @[dec_decode_ctl.scala 281:23] + i0_dp.add <= _T_82.add @[dec_decode_ctl.scala 281:23] + i0_dp.lsu <= _T_82.lsu @[dec_decode_ctl.scala 281:23] + i0_dp.store <= _T_82.store @[dec_decode_ctl.scala 281:23] + i0_dp.load <= _T_82.load @[dec_decode_ctl.scala 281:23] + i0_dp.pc <= _T_82.pc @[dec_decode_ctl.scala 281:23] + i0_dp.imm20 <= _T_82.imm20 @[dec_decode_ctl.scala 281:23] + i0_dp.shimm5 <= _T_82.shimm5 @[dec_decode_ctl.scala 281:23] + i0_dp.rd <= _T_82.rd @[dec_decode_ctl.scala 281:23] + i0_dp.imm12 <= _T_82.imm12 @[dec_decode_ctl.scala 281:23] + i0_dp.rs2 <= _T_82.rs2 @[dec_decode_ctl.scala 281:23] + i0_dp.rs1 <= _T_82.rs1 @[dec_decode_ctl.scala 281:23] + i0_dp.alu <= _T_82.alu @[dec_decode_ctl.scala 281:23] + i0_dp.zba <= _T_82.zba @[dec_decode_ctl.scala 281:23] + i0_dp.sh3add <= _T_82.sh3add @[dec_decode_ctl.scala 281:23] + i0_dp.sh2add <= _T_82.sh2add @[dec_decode_ctl.scala 281:23] + i0_dp.sh1add <= _T_82.sh1add @[dec_decode_ctl.scala 281:23] + i0_dp.zbf <= _T_82.zbf @[dec_decode_ctl.scala 281:23] + i0_dp.bfp <= _T_82.bfp @[dec_decode_ctl.scala 281:23] + i0_dp.zbr <= _T_82.zbr @[dec_decode_ctl.scala 281:23] + i0_dp.crc32c_w <= _T_82.crc32c_w @[dec_decode_ctl.scala 281:23] + i0_dp.crc32c_h <= _T_82.crc32c_h @[dec_decode_ctl.scala 281:23] + i0_dp.crc32c_b <= _T_82.crc32c_b @[dec_decode_ctl.scala 281:23] + i0_dp.crc32_w <= _T_82.crc32_w @[dec_decode_ctl.scala 281:23] + i0_dp.crc32_h <= _T_82.crc32_h @[dec_decode_ctl.scala 281:23] + i0_dp.crc32_b <= _T_82.crc32_b @[dec_decode_ctl.scala 281:23] + i0_dp.zbp <= _T_82.zbp @[dec_decode_ctl.scala 281:23] + i0_dp.unshfl <= _T_82.unshfl @[dec_decode_ctl.scala 281:23] + i0_dp.shfl <= _T_82.shfl @[dec_decode_ctl.scala 281:23] + i0_dp.zbc <= _T_82.zbc @[dec_decode_ctl.scala 281:23] + i0_dp.clmulr <= _T_82.clmulr @[dec_decode_ctl.scala 281:23] + i0_dp.clmulh <= _T_82.clmulh @[dec_decode_ctl.scala 281:23] + i0_dp.clmul <= _T_82.clmul @[dec_decode_ctl.scala 281:23] + i0_dp.zbe <= _T_82.zbe @[dec_decode_ctl.scala 281:23] + i0_dp.bdep <= _T_82.bdep @[dec_decode_ctl.scala 281:23] + i0_dp.bext <= _T_82.bext @[dec_decode_ctl.scala 281:23] + i0_dp.zbs <= _T_82.zbs @[dec_decode_ctl.scala 281:23] + i0_dp.sbext <= _T_82.sbext @[dec_decode_ctl.scala 281:23] + i0_dp.sbinv <= _T_82.sbinv @[dec_decode_ctl.scala 281:23] + i0_dp.sbclr <= _T_82.sbclr @[dec_decode_ctl.scala 281:23] + i0_dp.sbset <= _T_82.sbset @[dec_decode_ctl.scala 281:23] + i0_dp.zbb <= _T_82.zbb @[dec_decode_ctl.scala 281:23] + i0_dp.gorc <= _T_82.gorc @[dec_decode_ctl.scala 281:23] + i0_dp.grev <= _T_82.grev @[dec_decode_ctl.scala 281:23] + i0_dp.ror <= _T_82.ror @[dec_decode_ctl.scala 281:23] + i0_dp.rol <= _T_82.rol @[dec_decode_ctl.scala 281:23] + i0_dp.packh <= _T_82.packh @[dec_decode_ctl.scala 281:23] + i0_dp.packu <= _T_82.packu @[dec_decode_ctl.scala 281:23] + i0_dp.pack <= _T_82.pack @[dec_decode_ctl.scala 281:23] + i0_dp.max <= _T_82.max @[dec_decode_ctl.scala 281:23] + i0_dp.min <= _T_82.min @[dec_decode_ctl.scala 281:23] + i0_dp.sro <= _T_82.sro @[dec_decode_ctl.scala 281:23] + i0_dp.slo <= _T_82.slo @[dec_decode_ctl.scala 281:23] + i0_dp.sext_h <= _T_82.sext_h @[dec_decode_ctl.scala 281:23] + i0_dp.sext_b <= _T_82.sext_b @[dec_decode_ctl.scala 281:23] + i0_dp.pcnt <= _T_82.pcnt @[dec_decode_ctl.scala 281:23] + i0_dp.ctz <= _T_82.ctz @[dec_decode_ctl.scala 281:23] + i0_dp.clz <= _T_82.clz @[dec_decode_ctl.scala 281:23] + i0_dp.alu <= UInt<1>("h01") @[dec_decode_ctl.scala 282:23] + i0_dp.rs1 <= UInt<1>("h01") @[dec_decode_ctl.scala 283:23] + i0_dp.rs2 <= UInt<1>("h01") @[dec_decode_ctl.scala 284:23] + i0_dp.lor <= UInt<1>("h01") @[dec_decode_ctl.scala 285:23] + i0_dp.legal <= UInt<1>("h01") @[dec_decode_ctl.scala 286:23] + i0_dp.postsync <= UInt<1>("h01") @[dec_decode_ctl.scala 287:23] + skip @[dec_decode_ctl.scala 280:50] + io.decode_exu.dec_i0_select_pc_d <= i0_dp.pc @[dec_decode_ctl.scala 291:36] + node _T_83 = or(i0_dp.condbr, i0_pcall) @[dec_decode_ctl.scala 294:54] + node _T_84 = or(_T_83, i0_pja) @[dec_decode_ctl.scala 294:65] + node i0_predict_br = or(_T_84, i0_pret) @[dec_decode_ctl.scala 294:74] + node _T_85 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 295:65] + node _T_86 = and(_T_85, i0_brp_valid) @[dec_decode_ctl.scala 295:69] + node _T_87 = eq(_T_86, UInt<1>("h00")) @[dec_decode_ctl.scala 295:40] + node i0_predict_nt = and(_T_87, i0_predict_br) @[dec_decode_ctl.scala 295:85] + node _T_88 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 296:65] + node _T_89 = and(_T_88, i0_brp_valid) @[dec_decode_ctl.scala 296:69] + node i0_predict_t = and(_T_89, i0_predict_br) @[dec_decode_ctl.scala 296:85] + node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[dec_decode_ctl.scala 297:40] + io.decode_exu.i0_ap.predict_nt <= i0_predict_nt @[dec_decode_ctl.scala 299:37] + io.decode_exu.i0_ap.predict_t <= i0_predict_t @[dec_decode_ctl.scala 300:37] + io.decode_exu.i0_ap.add <= i0_dp.add @[dec_decode_ctl.scala 303:33] + io.decode_exu.i0_ap.sub <= i0_dp.sub @[dec_decode_ctl.scala 304:33] + io.decode_exu.i0_ap.land <= i0_dp.land @[dec_decode_ctl.scala 305:33] + io.decode_exu.i0_ap.lor <= i0_dp.lor @[dec_decode_ctl.scala 306:33] + io.decode_exu.i0_ap.lxor <= i0_dp.lxor @[dec_decode_ctl.scala 307:33] + io.decode_exu.i0_ap.sll <= i0_dp.sll @[dec_decode_ctl.scala 308:33] + io.decode_exu.i0_ap.srl <= i0_dp.srl @[dec_decode_ctl.scala 309:33] + io.decode_exu.i0_ap.sra <= i0_dp.sra @[dec_decode_ctl.scala 310:33] + io.decode_exu.i0_ap.slt <= i0_dp.slt @[dec_decode_ctl.scala 311:33] + io.decode_exu.i0_ap.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 312:33] + io.decode_exu.i0_ap.beq <= i0_dp.beq @[dec_decode_ctl.scala 313:33] + io.decode_exu.i0_ap.bne <= i0_dp.bne @[dec_decode_ctl.scala 314:33] + io.decode_exu.i0_ap.blt <= i0_dp.blt @[dec_decode_ctl.scala 315:33] + io.decode_exu.i0_ap.bge <= i0_dp.bge @[dec_decode_ctl.scala 316:33] + io.decode_exu.i0_ap.clz <= i0_dp.clz @[dec_decode_ctl.scala 317:33] + io.decode_exu.i0_ap.ctz <= i0_dp.ctz @[dec_decode_ctl.scala 318:33] + io.decode_exu.i0_ap.pcnt <= i0_dp.pcnt @[dec_decode_ctl.scala 319:33] + io.decode_exu.i0_ap.sext_b <= i0_dp.sext_b @[dec_decode_ctl.scala 320:33] + io.decode_exu.i0_ap.sext_h <= i0_dp.sext_h @[dec_decode_ctl.scala 321:33] + io.decode_exu.i0_ap.sh1add <= i0_dp.sh1add @[dec_decode_ctl.scala 322:33] + io.decode_exu.i0_ap.sh2add <= i0_dp.sh2add @[dec_decode_ctl.scala 323:33] + io.decode_exu.i0_ap.sh3add <= i0_dp.sh3add @[dec_decode_ctl.scala 324:33] + io.decode_exu.i0_ap.zba <= i0_dp.zba @[dec_decode_ctl.scala 325:33] + io.decode_exu.i0_ap.slo <= i0_dp.slo @[dec_decode_ctl.scala 326:33] + io.decode_exu.i0_ap.sro <= i0_dp.sro @[dec_decode_ctl.scala 327:33] + io.decode_exu.i0_ap.min <= i0_dp.min @[dec_decode_ctl.scala 328:33] + io.decode_exu.i0_ap.max <= i0_dp.max @[dec_decode_ctl.scala 329:33] + io.decode_exu.i0_ap.pack <= i0_dp.pack @[dec_decode_ctl.scala 330:33] + io.decode_exu.i0_ap.packu <= i0_dp.packu @[dec_decode_ctl.scala 331:33] + io.decode_exu.i0_ap.packh <= i0_dp.packh @[dec_decode_ctl.scala 332:33] + io.decode_exu.i0_ap.rol <= i0_dp.rol @[dec_decode_ctl.scala 333:33] + io.decode_exu.i0_ap.ror <= i0_dp.ror @[dec_decode_ctl.scala 334:33] + io.decode_exu.i0_ap.grev <= i0_dp.grev @[dec_decode_ctl.scala 335:33] + io.decode_exu.i0_ap.gorc <= i0_dp.gorc @[dec_decode_ctl.scala 336:33] + io.decode_exu.i0_ap.zbb <= i0_dp.zbb @[dec_decode_ctl.scala 337:33] + io.decode_exu.i0_ap.sbset <= i0_dp.sbset @[dec_decode_ctl.scala 338:33] + io.decode_exu.i0_ap.sbclr <= i0_dp.sbclr @[dec_decode_ctl.scala 339:33] + io.decode_exu.i0_ap.sbinv <= i0_dp.sbinv @[dec_decode_ctl.scala 340:33] + io.decode_exu.i0_ap.sbext <= i0_dp.sbext @[dec_decode_ctl.scala 341:33] + io.decode_exu.i0_ap.csr_write <= i0_csr_write_only_d @[dec_decode_ctl.scala 342:33] + io.decode_exu.i0_ap.csr_imm <= i0_dp.csr_imm @[dec_decode_ctl.scala 343:33] + io.decode_exu.i0_ap.jal <= i0_jal @[dec_decode_ctl.scala 344:33] + node _T_90 = eq(cam[0].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 348:78] + node _T_91 = bits(_T_90, 0, 0) @[dec_decode_ctl.scala 348:137] + node _T_92 = shl(cam_write, 0) @[dec_decode_ctl.scala 348:158] + node _T_93 = eq(cam[1].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 348:78] + node _T_94 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 348:120] + node _T_95 = bits(_T_93, 0, 0) @[dec_decode_ctl.scala 348:129] + node _T_96 = and(_T_94, _T_95) @[dec_decode_ctl.scala 348:126] + node _T_97 = bits(_T_96, 0, 0) @[dec_decode_ctl.scala 348:137] + node _T_98 = shl(cam_write, 1) @[dec_decode_ctl.scala 348:158] + node _T_99 = eq(cam[2].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 348:78] + node _T_100 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 348:120] + node _T_101 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 348:129] + node _T_102 = and(_T_100, _T_101) @[dec_decode_ctl.scala 348:126] + node _T_103 = bits(_T_102, 0, 0) @[dec_decode_ctl.scala 348:120] + node _T_104 = bits(_T_99, 0, 0) @[dec_decode_ctl.scala 348:129] + node _T_105 = and(_T_103, _T_104) @[dec_decode_ctl.scala 348:126] + node _T_106 = bits(_T_105, 0, 0) @[dec_decode_ctl.scala 348:137] + node _T_107 = shl(cam_write, 2) @[dec_decode_ctl.scala 348:158] + node _T_108 = eq(cam[3].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 348:78] + node _T_109 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 348:120] + node _T_110 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 348:129] + node _T_111 = and(_T_109, _T_110) @[dec_decode_ctl.scala 348:126] + node _T_112 = bits(_T_111, 0, 0) @[dec_decode_ctl.scala 348:120] + node _T_113 = bits(cam[2].valid, 0, 0) @[dec_decode_ctl.scala 348:129] + node _T_114 = and(_T_112, _T_113) @[dec_decode_ctl.scala 348:126] + node _T_115 = bits(_T_114, 0, 0) @[dec_decode_ctl.scala 348:120] + node _T_116 = bits(_T_108, 0, 0) @[dec_decode_ctl.scala 348:129] + node _T_117 = and(_T_115, _T_116) @[dec_decode_ctl.scala 348:126] + node _T_118 = bits(_T_117, 0, 0) @[dec_decode_ctl.scala 348:137] + node _T_119 = shl(cam_write, 3) @[dec_decode_ctl.scala 348:158] + node _T_120 = mux(_T_91, _T_92, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_121 = mux(_T_97, _T_98, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_122 = mux(_T_106, _T_107, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_123 = mux(_T_118, _T_119, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_124 = or(_T_120, _T_121) @[Mux.scala 27:72] + node _T_125 = or(_T_124, _T_122) @[Mux.scala 27:72] + node _T_126 = or(_T_125, _T_123) @[Mux.scala 27:72] + wire _T_127 : UInt<4> @[Mux.scala 27:72] + _T_127 <= _T_126 @[Mux.scala 27:72] + cam_wen <= _T_127 @[dec_decode_ctl.scala 348:11] + cam_write <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[dec_decode_ctl.scala 350:25] + node cam_write_tag = bits(io.dctl_busbuff.lsu_nonblock_load_tag_m, 1, 0) @[dec_decode_ctl.scala 351:67] + node cam_data_reset = or(io.dctl_busbuff.lsu_nonblock_load_data_valid, io.dctl_busbuff.lsu_nonblock_load_data_error) @[dec_decode_ctl.scala 356:76] + node _T_128 = bits(x_d.bits.i0load, 0, 0) @[dec_decode_ctl.scala 359:48] + node nonblock_load_rd = mux(_T_128, x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 359:31] + node _T_129 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 363:129] + reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_129 : @[Reg.scala 28:19] + nonblock_load_valid_m_delay <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[dec_decode_ctl.scala 364:56] + node _T_130 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 366:66] + node _T_131 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_130) @[dec_decode_ctl.scala 366:45] + node _T_132 = and(_T_131, cam[0].valid) @[dec_decode_ctl.scala 366:87] + cam_inv_reset_val[0] <= _T_132 @[dec_decode_ctl.scala 366:26] + node _T_133 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[0].bits.tag) @[dec_decode_ctl.scala 367:67] + node _T_134 = and(cam_data_reset, _T_133) @[dec_decode_ctl.scala 367:45] + node _T_135 = and(_T_134, cam_raw[0].valid) @[dec_decode_ctl.scala 367:88] + cam_data_reset_val[0] <= _T_135 @[dec_decode_ctl.scala 367:27] + wire _T_136 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 368:28] + _T_136.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 368:28] + _T_136.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 368:28] + _T_136.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28] + _T_136.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28] + cam_in[0].bits.rd <= _T_136.bits.rd @[dec_decode_ctl.scala 368:14] + cam_in[0].bits.tag <= _T_136.bits.tag @[dec_decode_ctl.scala 368:14] + cam_in[0].bits.wb <= _T_136.bits.wb @[dec_decode_ctl.scala 368:14] + cam_in[0].valid <= _T_136.valid @[dec_decode_ctl.scala 368:14] + cam[0].bits.rd <= cam_raw[0].bits.rd @[dec_decode_ctl.scala 369:11] + cam[0].bits.tag <= cam_raw[0].bits.tag @[dec_decode_ctl.scala 369:11] + cam[0].bits.wb <= cam_raw[0].bits.wb @[dec_decode_ctl.scala 369:11] + cam[0].valid <= cam_raw[0].valid @[dec_decode_ctl.scala 369:11] + node _T_137 = bits(cam_data_reset_val[0], 0, 0) @[dec_decode_ctl.scala 371:32] + when _T_137 : @[dec_decode_ctl.scala 371:39] + cam[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 372:20] + skip @[dec_decode_ctl.scala 371:39] + node _T_138 = bits(cam_wen, 0, 0) @[dec_decode_ctl.scala 374:17] + node _T_139 = bits(_T_138, 0, 0) @[dec_decode_ctl.scala 374:21] + when _T_139 : @[dec_decode_ctl.scala 374:28] + cam_in[0].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 375:27] + cam_in[0].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 376:32] + cam_in[0].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 377:32] + cam_in[0].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 378:32] + skip @[dec_decode_ctl.scala 374:28] + else : @[dec_decode_ctl.scala 379:131] + node _T_140 = bits(cam_inv_reset_val[0], 0, 0) @[dec_decode_ctl.scala 379:37] + node _T_141 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 379:57] + node _T_142 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[dec_decode_ctl.scala 379:85] + node _T_143 = and(_T_141, _T_142) @[dec_decode_ctl.scala 379:64] + node _T_144 = bits(cam[0].bits.wb, 0, 0) @[dec_decode_ctl.scala 379:123] + node _T_145 = and(_T_143, _T_144) @[dec_decode_ctl.scala 379:105] + node _T_146 = or(_T_140, _T_145) @[dec_decode_ctl.scala 379:44] + when _T_146 : @[dec_decode_ctl.scala 379:131] + cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 380:23] + skip @[dec_decode_ctl.scala 379:131] + else : @[dec_decode_ctl.scala 381:16] + cam_in[0].bits.rd <= cam[0].bits.rd @[dec_decode_ctl.scala 382:22] + cam_in[0].bits.tag <= cam[0].bits.tag @[dec_decode_ctl.scala 382:22] + cam_in[0].bits.wb <= cam[0].bits.wb @[dec_decode_ctl.scala 382:22] + cam_in[0].valid <= cam[0].valid @[dec_decode_ctl.scala 382:22] + skip @[dec_decode_ctl.scala 381:16] + node _T_147 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 384:37] + node _T_148 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 384:92] + node _T_149 = and(_T_147, _T_148) @[dec_decode_ctl.scala 384:44] + node _T_150 = eq(cam[0].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 384:128] + node _T_151 = and(_T_149, _T_150) @[dec_decode_ctl.scala 384:113] + when _T_151 : @[dec_decode_ctl.scala 384:135] + cam_in[0].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 385:25] + skip @[dec_decode_ctl.scala 384:135] + when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 388:32] + cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 389:23] + skip @[dec_decode_ctl.scala 388:32] + wire _T_152 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} + _T_152.bits.rd <= cam_in[0].bits.rd + _T_152.bits.tag <= cam_in[0].bits.tag + _T_152.bits.wb <= cam_in[0].bits.wb + _T_152.valid <= cam_in[0].valid + node _T_153 = cat(cam_in[0].bits.wb, cam_in[0].bits.tag) @[lib.scala 494:61] + node _T_154 = cat(_T_153, cam_in[0].bits.rd) @[lib.scala 494:61] + node _T_155 = cat(_T_152.bits.wb, _T_152.bits.tag) @[lib.scala 494:74] + node _T_156 = cat(_T_155, _T_152.bits.rd) @[lib.scala 494:74] + node _T_157 = xor(_T_154, _T_156) @[lib.scala 494:68] + node _T_158 = orr(_T_157) @[lib.scala 494:82] + node _T_159 = xor(cam_in[0].valid, _T_152.valid) @[lib.scala 494:68] + node _T_160 = orr(_T_159) @[lib.scala 494:82] + node _T_161 = or(_T_158, _T_160) @[lib.scala 494:97] + wire _T_162 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[lib.scala 497:46] + _T_162.bits.rd <= UInt<5>("h00") @[lib.scala 497:46] + _T_162.bits.tag <= UInt<3>("h00") @[lib.scala 497:46] + _T_162.bits.wb <= UInt<1>("h00") @[lib.scala 497:46] + _T_162.valid <= UInt<1>("h00") @[lib.scala 497:46] + reg _T_163 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, clock with : (reset => (reset, _T_162)) @[Reg.scala 27:20] + when _T_161 : @[Reg.scala 28:19] + _T_163.bits.rd <= cam_in[0].bits.rd @[Reg.scala 28:23] + _T_163.bits.tag <= cam_in[0].bits.tag @[Reg.scala 28:23] + _T_163.bits.wb <= cam_in[0].bits.wb @[Reg.scala 28:23] + _T_163.valid <= cam_in[0].valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_152.bits.rd <= _T_163.bits.rd @[lib.scala 497:16] + _T_152.bits.tag <= _T_163.bits.tag @[lib.scala 497:16] + _T_152.bits.wb <= _T_163.bits.wb @[lib.scala 497:16] + _T_152.valid <= _T_163.valid @[lib.scala 497:16] + cam_raw[0].bits.rd <= _T_152.bits.rd @[dec_decode_ctl.scala 392:15] + cam_raw[0].bits.tag <= _T_152.bits.tag @[dec_decode_ctl.scala 392:15] + cam_raw[0].bits.wb <= _T_152.bits.wb @[dec_decode_ctl.scala 392:15] + cam_raw[0].valid <= _T_152.valid @[dec_decode_ctl.scala 392:15] + node _T_164 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[dec_decode_ctl.scala 393:46] + node _T_165 = and(_T_164, cam_raw[0].valid) @[dec_decode_ctl.scala 393:71] + nonblock_load_write[0] <= _T_165 @[dec_decode_ctl.scala 393:28] + node _T_166 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 366:66] + node _T_167 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_166) @[dec_decode_ctl.scala 366:45] + node _T_168 = and(_T_167, cam[1].valid) @[dec_decode_ctl.scala 366:87] + cam_inv_reset_val[1] <= _T_168 @[dec_decode_ctl.scala 366:26] + node _T_169 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[1].bits.tag) @[dec_decode_ctl.scala 367:67] + node _T_170 = and(cam_data_reset, _T_169) @[dec_decode_ctl.scala 367:45] + node _T_171 = and(_T_170, cam_raw[1].valid) @[dec_decode_ctl.scala 367:88] + cam_data_reset_val[1] <= _T_171 @[dec_decode_ctl.scala 367:27] + wire _T_172 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 368:28] + _T_172.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 368:28] + _T_172.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 368:28] + _T_172.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28] + _T_172.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28] + cam_in[1].bits.rd <= _T_172.bits.rd @[dec_decode_ctl.scala 368:14] + cam_in[1].bits.tag <= _T_172.bits.tag @[dec_decode_ctl.scala 368:14] + cam_in[1].bits.wb <= _T_172.bits.wb @[dec_decode_ctl.scala 368:14] + cam_in[1].valid <= _T_172.valid @[dec_decode_ctl.scala 368:14] + cam[1].bits.rd <= cam_raw[1].bits.rd @[dec_decode_ctl.scala 369:11] + cam[1].bits.tag <= cam_raw[1].bits.tag @[dec_decode_ctl.scala 369:11] + cam[1].bits.wb <= cam_raw[1].bits.wb @[dec_decode_ctl.scala 369:11] + cam[1].valid <= cam_raw[1].valid @[dec_decode_ctl.scala 369:11] + node _T_173 = bits(cam_data_reset_val[1], 0, 0) @[dec_decode_ctl.scala 371:32] + when _T_173 : @[dec_decode_ctl.scala 371:39] + cam[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 372:20] + skip @[dec_decode_ctl.scala 371:39] + node _T_174 = bits(cam_wen, 1, 1) @[dec_decode_ctl.scala 374:17] + node _T_175 = bits(_T_174, 0, 0) @[dec_decode_ctl.scala 374:21] + when _T_175 : @[dec_decode_ctl.scala 374:28] + cam_in[1].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 375:27] + cam_in[1].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 376:32] + cam_in[1].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 377:32] + cam_in[1].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 378:32] + skip @[dec_decode_ctl.scala 374:28] + else : @[dec_decode_ctl.scala 379:131] + node _T_176 = bits(cam_inv_reset_val[1], 0, 0) @[dec_decode_ctl.scala 379:37] + node _T_177 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 379:57] + node _T_178 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[dec_decode_ctl.scala 379:85] + node _T_179 = and(_T_177, _T_178) @[dec_decode_ctl.scala 379:64] + node _T_180 = bits(cam[1].bits.wb, 0, 0) @[dec_decode_ctl.scala 379:123] + node _T_181 = and(_T_179, _T_180) @[dec_decode_ctl.scala 379:105] + node _T_182 = or(_T_176, _T_181) @[dec_decode_ctl.scala 379:44] + when _T_182 : @[dec_decode_ctl.scala 379:131] + cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 380:23] + skip @[dec_decode_ctl.scala 379:131] + else : @[dec_decode_ctl.scala 381:16] + cam_in[1].bits.rd <= cam[1].bits.rd @[dec_decode_ctl.scala 382:22] + cam_in[1].bits.tag <= cam[1].bits.tag @[dec_decode_ctl.scala 382:22] + cam_in[1].bits.wb <= cam[1].bits.wb @[dec_decode_ctl.scala 382:22] + cam_in[1].valid <= cam[1].valid @[dec_decode_ctl.scala 382:22] + skip @[dec_decode_ctl.scala 381:16] + node _T_183 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 384:37] + node _T_184 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 384:92] + node _T_185 = and(_T_183, _T_184) @[dec_decode_ctl.scala 384:44] + node _T_186 = eq(cam[1].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 384:128] + node _T_187 = and(_T_185, _T_186) @[dec_decode_ctl.scala 384:113] + when _T_187 : @[dec_decode_ctl.scala 384:135] + cam_in[1].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 385:25] + skip @[dec_decode_ctl.scala 384:135] + when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 388:32] + cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 389:23] + skip @[dec_decode_ctl.scala 388:32] + wire _T_188 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} + _T_188.bits.rd <= cam_in[1].bits.rd + _T_188.bits.tag <= cam_in[1].bits.tag + _T_188.bits.wb <= cam_in[1].bits.wb + _T_188.valid <= cam_in[1].valid + node _T_189 = cat(cam_in[1].bits.wb, cam_in[1].bits.tag) @[lib.scala 494:61] + node _T_190 = cat(_T_189, cam_in[1].bits.rd) @[lib.scala 494:61] + node _T_191 = cat(_T_188.bits.wb, _T_188.bits.tag) @[lib.scala 494:74] + node _T_192 = cat(_T_191, _T_188.bits.rd) @[lib.scala 494:74] + node _T_193 = xor(_T_190, _T_192) @[lib.scala 494:68] + node _T_194 = orr(_T_193) @[lib.scala 494:82] + node _T_195 = xor(cam_in[1].valid, _T_188.valid) @[lib.scala 494:68] + node _T_196 = orr(_T_195) @[lib.scala 494:82] + node _T_197 = or(_T_194, _T_196) @[lib.scala 494:97] + wire _T_198 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[lib.scala 497:46] + _T_198.bits.rd <= UInt<5>("h00") @[lib.scala 497:46] + _T_198.bits.tag <= UInt<3>("h00") @[lib.scala 497:46] + _T_198.bits.wb <= UInt<1>("h00") @[lib.scala 497:46] + _T_198.valid <= UInt<1>("h00") @[lib.scala 497:46] + reg _T_199 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, clock with : (reset => (reset, _T_198)) @[Reg.scala 27:20] + when _T_197 : @[Reg.scala 28:19] + _T_199.bits.rd <= cam_in[1].bits.rd @[Reg.scala 28:23] + _T_199.bits.tag <= cam_in[1].bits.tag @[Reg.scala 28:23] + _T_199.bits.wb <= cam_in[1].bits.wb @[Reg.scala 28:23] + _T_199.valid <= cam_in[1].valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_188.bits.rd <= _T_199.bits.rd @[lib.scala 497:16] + _T_188.bits.tag <= _T_199.bits.tag @[lib.scala 497:16] + _T_188.bits.wb <= _T_199.bits.wb @[lib.scala 497:16] + _T_188.valid <= _T_199.valid @[lib.scala 497:16] + cam_raw[1].bits.rd <= _T_188.bits.rd @[dec_decode_ctl.scala 392:15] + cam_raw[1].bits.tag <= _T_188.bits.tag @[dec_decode_ctl.scala 392:15] + cam_raw[1].bits.wb <= _T_188.bits.wb @[dec_decode_ctl.scala 392:15] + cam_raw[1].valid <= _T_188.valid @[dec_decode_ctl.scala 392:15] + node _T_200 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[dec_decode_ctl.scala 393:46] + node _T_201 = and(_T_200, cam_raw[1].valid) @[dec_decode_ctl.scala 393:71] + nonblock_load_write[1] <= _T_201 @[dec_decode_ctl.scala 393:28] + node _T_202 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 366:66] + node _T_203 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_202) @[dec_decode_ctl.scala 366:45] + node _T_204 = and(_T_203, cam[2].valid) @[dec_decode_ctl.scala 366:87] + cam_inv_reset_val[2] <= _T_204 @[dec_decode_ctl.scala 366:26] + node _T_205 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[2].bits.tag) @[dec_decode_ctl.scala 367:67] + node _T_206 = and(cam_data_reset, _T_205) @[dec_decode_ctl.scala 367:45] + node _T_207 = and(_T_206, cam_raw[2].valid) @[dec_decode_ctl.scala 367:88] + cam_data_reset_val[2] <= _T_207 @[dec_decode_ctl.scala 367:27] + wire _T_208 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 368:28] + _T_208.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 368:28] + _T_208.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 368:28] + _T_208.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28] + _T_208.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28] + cam_in[2].bits.rd <= _T_208.bits.rd @[dec_decode_ctl.scala 368:14] + cam_in[2].bits.tag <= _T_208.bits.tag @[dec_decode_ctl.scala 368:14] + cam_in[2].bits.wb <= _T_208.bits.wb @[dec_decode_ctl.scala 368:14] + cam_in[2].valid <= _T_208.valid @[dec_decode_ctl.scala 368:14] + cam[2].bits.rd <= cam_raw[2].bits.rd @[dec_decode_ctl.scala 369:11] + cam[2].bits.tag <= cam_raw[2].bits.tag @[dec_decode_ctl.scala 369:11] + cam[2].bits.wb <= cam_raw[2].bits.wb @[dec_decode_ctl.scala 369:11] + cam[2].valid <= cam_raw[2].valid @[dec_decode_ctl.scala 369:11] + node _T_209 = bits(cam_data_reset_val[2], 0, 0) @[dec_decode_ctl.scala 371:32] + when _T_209 : @[dec_decode_ctl.scala 371:39] + cam[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 372:20] + skip @[dec_decode_ctl.scala 371:39] + node _T_210 = bits(cam_wen, 2, 2) @[dec_decode_ctl.scala 374:17] + node _T_211 = bits(_T_210, 0, 0) @[dec_decode_ctl.scala 374:21] + when _T_211 : @[dec_decode_ctl.scala 374:28] + cam_in[2].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 375:27] + cam_in[2].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 376:32] + cam_in[2].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 377:32] + cam_in[2].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 378:32] + skip @[dec_decode_ctl.scala 374:28] + else : @[dec_decode_ctl.scala 379:131] + node _T_212 = bits(cam_inv_reset_val[2], 0, 0) @[dec_decode_ctl.scala 379:37] + node _T_213 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 379:57] + node _T_214 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[dec_decode_ctl.scala 379:85] + node _T_215 = and(_T_213, _T_214) @[dec_decode_ctl.scala 379:64] + node _T_216 = bits(cam[2].bits.wb, 0, 0) @[dec_decode_ctl.scala 379:123] + node _T_217 = and(_T_215, _T_216) @[dec_decode_ctl.scala 379:105] + node _T_218 = or(_T_212, _T_217) @[dec_decode_ctl.scala 379:44] + when _T_218 : @[dec_decode_ctl.scala 379:131] + cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 380:23] + skip @[dec_decode_ctl.scala 379:131] + else : @[dec_decode_ctl.scala 381:16] + cam_in[2].bits.rd <= cam[2].bits.rd @[dec_decode_ctl.scala 382:22] + cam_in[2].bits.tag <= cam[2].bits.tag @[dec_decode_ctl.scala 382:22] + cam_in[2].bits.wb <= cam[2].bits.wb @[dec_decode_ctl.scala 382:22] + cam_in[2].valid <= cam[2].valid @[dec_decode_ctl.scala 382:22] + skip @[dec_decode_ctl.scala 381:16] + node _T_219 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 384:37] + node _T_220 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 384:92] + node _T_221 = and(_T_219, _T_220) @[dec_decode_ctl.scala 384:44] + node _T_222 = eq(cam[2].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 384:128] + node _T_223 = and(_T_221, _T_222) @[dec_decode_ctl.scala 384:113] + when _T_223 : @[dec_decode_ctl.scala 384:135] + cam_in[2].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 385:25] + skip @[dec_decode_ctl.scala 384:135] + when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 388:32] + cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 389:23] + skip @[dec_decode_ctl.scala 388:32] + wire _T_224 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} + _T_224.bits.rd <= cam_in[2].bits.rd + _T_224.bits.tag <= cam_in[2].bits.tag + _T_224.bits.wb <= cam_in[2].bits.wb + _T_224.valid <= cam_in[2].valid + node _T_225 = cat(cam_in[2].bits.wb, cam_in[2].bits.tag) @[lib.scala 494:61] + node _T_226 = cat(_T_225, cam_in[2].bits.rd) @[lib.scala 494:61] + node _T_227 = cat(_T_224.bits.wb, _T_224.bits.tag) @[lib.scala 494:74] + node _T_228 = cat(_T_227, _T_224.bits.rd) @[lib.scala 494:74] + node _T_229 = xor(_T_226, _T_228) @[lib.scala 494:68] + node _T_230 = orr(_T_229) @[lib.scala 494:82] + node _T_231 = xor(cam_in[2].valid, _T_224.valid) @[lib.scala 494:68] + node _T_232 = orr(_T_231) @[lib.scala 494:82] + node _T_233 = or(_T_230, _T_232) @[lib.scala 494:97] + wire _T_234 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[lib.scala 497:46] + _T_234.bits.rd <= UInt<5>("h00") @[lib.scala 497:46] + _T_234.bits.tag <= UInt<3>("h00") @[lib.scala 497:46] + _T_234.bits.wb <= UInt<1>("h00") @[lib.scala 497:46] + _T_234.valid <= UInt<1>("h00") @[lib.scala 497:46] + reg _T_235 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, clock with : (reset => (reset, _T_234)) @[Reg.scala 27:20] + when _T_233 : @[Reg.scala 28:19] + _T_235.bits.rd <= cam_in[2].bits.rd @[Reg.scala 28:23] + _T_235.bits.tag <= cam_in[2].bits.tag @[Reg.scala 28:23] + _T_235.bits.wb <= cam_in[2].bits.wb @[Reg.scala 28:23] + _T_235.valid <= cam_in[2].valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_224.bits.rd <= _T_235.bits.rd @[lib.scala 497:16] + _T_224.bits.tag <= _T_235.bits.tag @[lib.scala 497:16] + _T_224.bits.wb <= _T_235.bits.wb @[lib.scala 497:16] + _T_224.valid <= _T_235.valid @[lib.scala 497:16] + cam_raw[2].bits.rd <= _T_224.bits.rd @[dec_decode_ctl.scala 392:15] + cam_raw[2].bits.tag <= _T_224.bits.tag @[dec_decode_ctl.scala 392:15] + cam_raw[2].bits.wb <= _T_224.bits.wb @[dec_decode_ctl.scala 392:15] + cam_raw[2].valid <= _T_224.valid @[dec_decode_ctl.scala 392:15] + node _T_236 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[dec_decode_ctl.scala 393:46] + node _T_237 = and(_T_236, cam_raw[2].valid) @[dec_decode_ctl.scala 393:71] + nonblock_load_write[2] <= _T_237 @[dec_decode_ctl.scala 393:28] + node _T_238 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 366:66] + node _T_239 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_238) @[dec_decode_ctl.scala 366:45] + node _T_240 = and(_T_239, cam[3].valid) @[dec_decode_ctl.scala 366:87] + cam_inv_reset_val[3] <= _T_240 @[dec_decode_ctl.scala 366:26] + node _T_241 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[3].bits.tag) @[dec_decode_ctl.scala 367:67] + node _T_242 = and(cam_data_reset, _T_241) @[dec_decode_ctl.scala 367:45] + node _T_243 = and(_T_242, cam_raw[3].valid) @[dec_decode_ctl.scala 367:88] + cam_data_reset_val[3] <= _T_243 @[dec_decode_ctl.scala 367:27] + wire _T_244 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 368:28] + _T_244.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 368:28] + _T_244.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 368:28] + _T_244.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28] + _T_244.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 368:28] + cam_in[3].bits.rd <= _T_244.bits.rd @[dec_decode_ctl.scala 368:14] + cam_in[3].bits.tag <= _T_244.bits.tag @[dec_decode_ctl.scala 368:14] + cam_in[3].bits.wb <= _T_244.bits.wb @[dec_decode_ctl.scala 368:14] + cam_in[3].valid <= _T_244.valid @[dec_decode_ctl.scala 368:14] + cam[3].bits.rd <= cam_raw[3].bits.rd @[dec_decode_ctl.scala 369:11] + cam[3].bits.tag <= cam_raw[3].bits.tag @[dec_decode_ctl.scala 369:11] + cam[3].bits.wb <= cam_raw[3].bits.wb @[dec_decode_ctl.scala 369:11] + cam[3].valid <= cam_raw[3].valid @[dec_decode_ctl.scala 369:11] + node _T_245 = bits(cam_data_reset_val[3], 0, 0) @[dec_decode_ctl.scala 371:32] + when _T_245 : @[dec_decode_ctl.scala 371:39] + cam[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 372:20] + skip @[dec_decode_ctl.scala 371:39] + node _T_246 = bits(cam_wen, 3, 3) @[dec_decode_ctl.scala 374:17] + node _T_247 = bits(_T_246, 0, 0) @[dec_decode_ctl.scala 374:21] + when _T_247 : @[dec_decode_ctl.scala 374:28] + cam_in[3].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 375:27] + cam_in[3].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 376:32] + cam_in[3].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 377:32] + cam_in[3].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 378:32] + skip @[dec_decode_ctl.scala 374:28] + else : @[dec_decode_ctl.scala 379:131] + node _T_248 = bits(cam_inv_reset_val[3], 0, 0) @[dec_decode_ctl.scala 379:37] + node _T_249 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 379:57] + node _T_250 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[dec_decode_ctl.scala 379:85] + node _T_251 = and(_T_249, _T_250) @[dec_decode_ctl.scala 379:64] + node _T_252 = bits(cam[3].bits.wb, 0, 0) @[dec_decode_ctl.scala 379:123] + node _T_253 = and(_T_251, _T_252) @[dec_decode_ctl.scala 379:105] + node _T_254 = or(_T_248, _T_253) @[dec_decode_ctl.scala 379:44] + when _T_254 : @[dec_decode_ctl.scala 379:131] + cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 380:23] + skip @[dec_decode_ctl.scala 379:131] + else : @[dec_decode_ctl.scala 381:16] + cam_in[3].bits.rd <= cam[3].bits.rd @[dec_decode_ctl.scala 382:22] + cam_in[3].bits.tag <= cam[3].bits.tag @[dec_decode_ctl.scala 382:22] + cam_in[3].bits.wb <= cam[3].bits.wb @[dec_decode_ctl.scala 382:22] + cam_in[3].valid <= cam[3].valid @[dec_decode_ctl.scala 382:22] + skip @[dec_decode_ctl.scala 381:16] + node _T_255 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 384:37] + node _T_256 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 384:92] + node _T_257 = and(_T_255, _T_256) @[dec_decode_ctl.scala 384:44] + node _T_258 = eq(cam[3].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 384:128] + node _T_259 = and(_T_257, _T_258) @[dec_decode_ctl.scala 384:113] + when _T_259 : @[dec_decode_ctl.scala 384:135] + cam_in[3].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 385:25] + skip @[dec_decode_ctl.scala 384:135] + when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 388:32] + cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 389:23] + skip @[dec_decode_ctl.scala 388:32] + wire _T_260 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} + _T_260.bits.rd <= cam_in[3].bits.rd + _T_260.bits.tag <= cam_in[3].bits.tag + _T_260.bits.wb <= cam_in[3].bits.wb + _T_260.valid <= cam_in[3].valid + node _T_261 = cat(cam_in[3].bits.wb, cam_in[3].bits.tag) @[lib.scala 494:61] + node _T_262 = cat(_T_261, cam_in[3].bits.rd) @[lib.scala 494:61] + node _T_263 = cat(_T_260.bits.wb, _T_260.bits.tag) @[lib.scala 494:74] + node _T_264 = cat(_T_263, _T_260.bits.rd) @[lib.scala 494:74] + node _T_265 = xor(_T_262, _T_264) @[lib.scala 494:68] + node _T_266 = orr(_T_265) @[lib.scala 494:82] + node _T_267 = xor(cam_in[3].valid, _T_260.valid) @[lib.scala 494:68] + node _T_268 = orr(_T_267) @[lib.scala 494:82] + node _T_269 = or(_T_266, _T_268) @[lib.scala 494:97] + wire _T_270 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[lib.scala 497:46] + _T_270.bits.rd <= UInt<5>("h00") @[lib.scala 497:46] + _T_270.bits.tag <= UInt<3>("h00") @[lib.scala 497:46] + _T_270.bits.wb <= UInt<1>("h00") @[lib.scala 497:46] + _T_270.valid <= UInt<1>("h00") @[lib.scala 497:46] + reg _T_271 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, clock with : (reset => (reset, _T_270)) @[Reg.scala 27:20] + when _T_269 : @[Reg.scala 28:19] + _T_271.bits.rd <= cam_in[3].bits.rd @[Reg.scala 28:23] + _T_271.bits.tag <= cam_in[3].bits.tag @[Reg.scala 28:23] + _T_271.bits.wb <= cam_in[3].bits.wb @[Reg.scala 28:23] + _T_271.valid <= cam_in[3].valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_260.bits.rd <= _T_271.bits.rd @[lib.scala 497:16] + _T_260.bits.tag <= _T_271.bits.tag @[lib.scala 497:16] + _T_260.bits.wb <= _T_271.bits.wb @[lib.scala 497:16] + _T_260.valid <= _T_271.valid @[lib.scala 497:16] + cam_raw[3].bits.rd <= _T_260.bits.rd @[dec_decode_ctl.scala 392:15] + cam_raw[3].bits.tag <= _T_260.bits.tag @[dec_decode_ctl.scala 392:15] + cam_raw[3].bits.wb <= _T_260.bits.wb @[dec_decode_ctl.scala 392:15] + cam_raw[3].valid <= _T_260.valid @[dec_decode_ctl.scala 392:15] + node _T_272 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[dec_decode_ctl.scala 393:46] + node _T_273 = and(_T_272, cam_raw[3].valid) @[dec_decode_ctl.scala 393:71] + nonblock_load_write[3] <= _T_273 @[dec_decode_ctl.scala 393:28] + io.dec_nonblock_load_waddr <= UInt<5>("h00") @[dec_decode_ctl.scala 396:29] + node _T_274 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[dec_decode_ctl.scala 398:49] + node nonblock_load_cancel = and(_T_274, i0_wen_r) @[dec_decode_ctl.scala 398:81] + node _T_275 = or(nonblock_load_write[0], nonblock_load_write[1]) @[dec_decode_ctl.scala 399:108] + node _T_276 = or(_T_275, nonblock_load_write[2]) @[dec_decode_ctl.scala 399:108] + node _T_277 = or(_T_276, nonblock_load_write[3]) @[dec_decode_ctl.scala 399:108] + node _T_278 = bits(_T_277, 0, 0) @[dec_decode_ctl.scala 399:112] + node _T_279 = and(io.dctl_busbuff.lsu_nonblock_load_data_valid, _T_278) @[dec_decode_ctl.scala 399:77] + node _T_280 = eq(nonblock_load_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 399:122] + node _T_281 = and(_T_279, _T_280) @[dec_decode_ctl.scala 399:119] + io.dec_nonblock_load_wen <= _T_281 @[dec_decode_ctl.scala 399:28] + node _T_282 = eq(nonblock_load_rd, i0r.rs1) @[dec_decode_ctl.scala 400:54] + node _T_283 = and(_T_282, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 400:66] + node _T_284 = and(_T_283, io.decode_exu.dec_i0_rs1_en_d) @[dec_decode_ctl.scala 400:110] + node _T_285 = eq(nonblock_load_rd, i0r.rs2) @[dec_decode_ctl.scala 400:161] + node _T_286 = and(_T_285, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 400:173] + node _T_287 = and(_T_286, io.decode_exu.dec_i0_rs2_en_d) @[dec_decode_ctl.scala 400:217] + node i0_nonblock_boundary_stall = or(_T_284, _T_287) @[dec_decode_ctl.scala 400:142] + i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[dec_decode_ctl.scala 402:26] + node _T_288 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15] + node _T_289 = mux(_T_288, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_290 = and(_T_289, cam[0].bits.rd) @[dec_decode_ctl.scala 404:88] + node _T_291 = and(io.decode_exu.dec_i0_rs1_en_d, cam[0].valid) @[dec_decode_ctl.scala 404:137] + node _T_292 = eq(cam[0].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 404:170] + node _T_293 = and(_T_291, _T_292) @[dec_decode_ctl.scala 404:152] + node _T_294 = and(io.decode_exu.dec_i0_rs2_en_d, cam[0].valid) @[dec_decode_ctl.scala 404:214] + node _T_295 = eq(cam[0].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 404:247] + node _T_296 = and(_T_294, _T_295) @[dec_decode_ctl.scala 404:229] + node _T_297 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15] + node _T_298 = mux(_T_297, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_299 = and(_T_298, cam[1].bits.rd) @[dec_decode_ctl.scala 404:88] + node _T_300 = and(io.decode_exu.dec_i0_rs1_en_d, cam[1].valid) @[dec_decode_ctl.scala 404:137] + node _T_301 = eq(cam[1].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 404:170] + node _T_302 = and(_T_300, _T_301) @[dec_decode_ctl.scala 404:152] + node _T_303 = and(io.decode_exu.dec_i0_rs2_en_d, cam[1].valid) @[dec_decode_ctl.scala 404:214] + node _T_304 = eq(cam[1].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 404:247] + node _T_305 = and(_T_303, _T_304) @[dec_decode_ctl.scala 404:229] + node _T_306 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15] + node _T_307 = mux(_T_306, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_308 = and(_T_307, cam[2].bits.rd) @[dec_decode_ctl.scala 404:88] + node _T_309 = and(io.decode_exu.dec_i0_rs1_en_d, cam[2].valid) @[dec_decode_ctl.scala 404:137] + node _T_310 = eq(cam[2].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 404:170] + node _T_311 = and(_T_309, _T_310) @[dec_decode_ctl.scala 404:152] + node _T_312 = and(io.decode_exu.dec_i0_rs2_en_d, cam[2].valid) @[dec_decode_ctl.scala 404:214] + node _T_313 = eq(cam[2].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 404:247] + node _T_314 = and(_T_312, _T_313) @[dec_decode_ctl.scala 404:229] + node _T_315 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15] + node _T_316 = mux(_T_315, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_317 = and(_T_316, cam[3].bits.rd) @[dec_decode_ctl.scala 404:88] + node _T_318 = and(io.decode_exu.dec_i0_rs1_en_d, cam[3].valid) @[dec_decode_ctl.scala 404:137] + node _T_319 = eq(cam[3].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 404:170] + node _T_320 = and(_T_318, _T_319) @[dec_decode_ctl.scala 404:152] + node _T_321 = and(io.decode_exu.dec_i0_rs2_en_d, cam[3].valid) @[dec_decode_ctl.scala 404:214] + node _T_322 = eq(cam[3].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 404:247] + node _T_323 = and(_T_321, _T_322) @[dec_decode_ctl.scala 404:229] + node _T_324 = or(_T_290, _T_299) @[dec_decode_ctl.scala 405:69] + node _T_325 = or(_T_324, _T_308) @[dec_decode_ctl.scala 405:69] + node waddr = or(_T_325, _T_317) @[dec_decode_ctl.scala 405:69] + node _T_326 = or(_T_293, _T_302) @[dec_decode_ctl.scala 405:102] + node _T_327 = or(_T_326, _T_311) @[dec_decode_ctl.scala 405:102] + node ld_stall_1 = or(_T_327, _T_320) @[dec_decode_ctl.scala 405:102] + node _T_328 = or(_T_296, _T_305) @[dec_decode_ctl.scala 405:134] + node _T_329 = or(_T_328, _T_314) @[dec_decode_ctl.scala 405:134] + node ld_stall_2 = or(_T_329, _T_323) @[dec_decode_ctl.scala 405:134] + io.dec_nonblock_load_waddr <= waddr @[dec_decode_ctl.scala 406:29] + node _T_330 = or(ld_stall_1, ld_stall_2) @[dec_decode_ctl.scala 407:38] + node _T_331 = or(_T_330, i0_nonblock_boundary_stall) @[dec_decode_ctl.scala 407:51] + i0_nonblock_load_stall <= _T_331 @[dec_decode_ctl.scala 407:25] + node _T_332 = eq(i0_predict_br, UInt<1>("h00")) @[dec_decode_ctl.scala 416:34] + node i0_br_unpred = and(i0_dp.jal, _T_332) @[dec_decode_ctl.scala 416:32] + node _T_333 = bits(i0_legal_decode_d, 0, 0) @[Bitwise.scala 72:15] + node _T_334 = mux(_T_333, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_335 = and(csr_read, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 428:16] + node _T_336 = bits(_T_335, 0, 0) @[dec_decode_ctl.scala 428:30] + node _T_337 = eq(csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 429:6] + node _T_338 = and(_T_337, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 429:16] + node _T_339 = bits(_T_338, 0, 0) @[dec_decode_ctl.scala 429:30] + node _T_340 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[dec_decode_ctl.scala 430:18] + node _T_341 = and(csr_read, _T_340) @[dec_decode_ctl.scala 430:16] + node _T_342 = bits(_T_341, 0, 0) @[dec_decode_ctl.scala 430:30] + node _T_343 = or(i0_dp.zbb, i0_dp.zbs) @[dec_decode_ctl.scala 431:16] + node _T_344 = or(_T_343, i0_dp.zbe) @[dec_decode_ctl.scala 431:28] + node _T_345 = or(_T_344, i0_dp.zbc) @[dec_decode_ctl.scala 431:40] + node _T_346 = or(_T_345, i0_dp.zbp) @[dec_decode_ctl.scala 431:52] + node _T_347 = or(_T_346, i0_dp.zbr) @[dec_decode_ctl.scala 431:65] + node _T_348 = or(_T_347, i0_dp.zbf) @[dec_decode_ctl.scala 431:77] + node _T_349 = or(_T_348, i0_dp.zba) @[dec_decode_ctl.scala 431:89] + node _T_350 = mux(i0_dp.mul, UInt<4>("h01"), UInt<4>("h00")) @[Mux.scala 98:16] + node _T_351 = mux(i0_dp.load, UInt<4>("h02"), _T_350) @[Mux.scala 98:16] + node _T_352 = mux(i0_dp.store, UInt<4>("h03"), _T_351) @[Mux.scala 98:16] + node _T_353 = mux(i0_dp.pm_alu, UInt<4>("h04"), _T_352) @[Mux.scala 98:16] + node _T_354 = mux(_T_349, UInt<4>("h0f"), _T_353) @[Mux.scala 98:16] + node _T_355 = mux(_T_342, UInt<4>("h05"), _T_354) @[Mux.scala 98:16] + node _T_356 = mux(_T_339, UInt<4>("h06"), _T_355) @[Mux.scala 98:16] + node _T_357 = mux(_T_336, UInt<4>("h07"), _T_356) @[Mux.scala 98:16] + node _T_358 = mux(i0_dp.ebreak, UInt<4>("h08"), _T_357) @[Mux.scala 98:16] + node _T_359 = mux(i0_dp.ecall, UInt<4>("h09"), _T_358) @[Mux.scala 98:16] + node _T_360 = mux(i0_dp.fence, UInt<4>("h0a"), _T_359) @[Mux.scala 98:16] + node _T_361 = mux(i0_dp.fence_i, UInt<4>("h0b"), _T_360) @[Mux.scala 98:16] + node _T_362 = mux(i0_dp.mret, UInt<4>("h0c"), _T_361) @[Mux.scala 98:16] + node _T_363 = mux(i0_dp.condbr, UInt<4>("h0d"), _T_362) @[Mux.scala 98:16] + node _T_364 = mux(i0_dp.jal, UInt<4>("h0e"), _T_363) @[Mux.scala 98:16] + node _T_365 = and(_T_334, _T_364) @[dec_decode_ctl.scala 420:49] + d_t.pmu_i0_itype <= _T_365 @[dec_decode_ctl.scala 420:21] + inst i0_dec of dec_dec_ctl @[dec_decode_ctl.scala 438:22] + i0_dec.clock <= clock + i0_dec.reset <= reset + i0_dec.io.ins <= io.dec_i0_instr_d @[dec_decode_ctl.scala 439:16] + i0_dp_raw.legal <= i0_dec.io.out.legal @[dec_decode_ctl.scala 440:12] + i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[dec_decode_ctl.scala 440:12] + i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[dec_decode_ctl.scala 440:12] + i0_dp_raw.fence <= i0_dec.io.out.fence @[dec_decode_ctl.scala 440:12] + i0_dp_raw.rem <= i0_dec.io.out.rem @[dec_decode_ctl.scala 440:12] + i0_dp_raw.div <= i0_dec.io.out.div @[dec_decode_ctl.scala 440:12] + i0_dp_raw.low <= i0_dec.io.out.low @[dec_decode_ctl.scala 440:12] + i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[dec_decode_ctl.scala 440:12] + i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[dec_decode_ctl.scala 440:12] + i0_dp_raw.mul <= i0_dec.io.out.mul @[dec_decode_ctl.scala 440:12] + i0_dp_raw.mret <= i0_dec.io.out.mret @[dec_decode_ctl.scala 440:12] + i0_dp_raw.ecall <= i0_dec.io.out.ecall @[dec_decode_ctl.scala 440:12] + i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[dec_decode_ctl.scala 440:12] + i0_dp_raw.postsync <= i0_dec.io.out.postsync @[dec_decode_ctl.scala 440:12] + i0_dp_raw.presync <= i0_dec.io.out.presync @[dec_decode_ctl.scala 440:12] + i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[dec_decode_ctl.scala 440:12] + i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[dec_decode_ctl.scala 440:12] + i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[dec_decode_ctl.scala 440:12] + i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[dec_decode_ctl.scala 440:12] + i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[dec_decode_ctl.scala 440:12] + i0_dp_raw.word <= i0_dec.io.out.word @[dec_decode_ctl.scala 440:12] + i0_dp_raw.half <= i0_dec.io.out.half @[dec_decode_ctl.scala 440:12] + i0_dp_raw.by <= i0_dec.io.out.by @[dec_decode_ctl.scala 440:12] + i0_dp_raw.jal <= i0_dec.io.out.jal @[dec_decode_ctl.scala 440:12] + i0_dp_raw.blt <= i0_dec.io.out.blt @[dec_decode_ctl.scala 440:12] + i0_dp_raw.bge <= i0_dec.io.out.bge @[dec_decode_ctl.scala 440:12] + i0_dp_raw.bne <= i0_dec.io.out.bne @[dec_decode_ctl.scala 440:12] + i0_dp_raw.beq <= i0_dec.io.out.beq @[dec_decode_ctl.scala 440:12] + i0_dp_raw.condbr <= i0_dec.io.out.condbr @[dec_decode_ctl.scala 440:12] + i0_dp_raw.unsign <= i0_dec.io.out.unsign @[dec_decode_ctl.scala 440:12] + i0_dp_raw.slt <= i0_dec.io.out.slt @[dec_decode_ctl.scala 440:12] + i0_dp_raw.srl <= i0_dec.io.out.srl @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sra <= i0_dec.io.out.sra @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sll <= i0_dec.io.out.sll @[dec_decode_ctl.scala 440:12] + i0_dp_raw.lxor <= i0_dec.io.out.lxor @[dec_decode_ctl.scala 440:12] + i0_dp_raw.lor <= i0_dec.io.out.lor @[dec_decode_ctl.scala 440:12] + i0_dp_raw.land <= i0_dec.io.out.land @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sub <= i0_dec.io.out.sub @[dec_decode_ctl.scala 440:12] + i0_dp_raw.add <= i0_dec.io.out.add @[dec_decode_ctl.scala 440:12] + i0_dp_raw.lsu <= i0_dec.io.out.lsu @[dec_decode_ctl.scala 440:12] + i0_dp_raw.store <= i0_dec.io.out.store @[dec_decode_ctl.scala 440:12] + i0_dp_raw.load <= i0_dec.io.out.load @[dec_decode_ctl.scala 440:12] + i0_dp_raw.pc <= i0_dec.io.out.pc @[dec_decode_ctl.scala 440:12] + i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[dec_decode_ctl.scala 440:12] + i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[dec_decode_ctl.scala 440:12] + i0_dp_raw.rd <= i0_dec.io.out.rd @[dec_decode_ctl.scala 440:12] + i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[dec_decode_ctl.scala 440:12] + i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[dec_decode_ctl.scala 440:12] + i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[dec_decode_ctl.scala 440:12] + i0_dp_raw.alu <= i0_dec.io.out.alu @[dec_decode_ctl.scala 440:12] + i0_dp_raw.zba <= i0_dec.io.out.zba @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sh3add <= i0_dec.io.out.sh3add @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sh2add <= i0_dec.io.out.sh2add @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sh1add <= i0_dec.io.out.sh1add @[dec_decode_ctl.scala 440:12] + i0_dp_raw.zbf <= i0_dec.io.out.zbf @[dec_decode_ctl.scala 440:12] + i0_dp_raw.bfp <= i0_dec.io.out.bfp @[dec_decode_ctl.scala 440:12] + i0_dp_raw.zbr <= i0_dec.io.out.zbr @[dec_decode_ctl.scala 440:12] + i0_dp_raw.crc32c_w <= i0_dec.io.out.crc32c_w @[dec_decode_ctl.scala 440:12] + i0_dp_raw.crc32c_h <= i0_dec.io.out.crc32c_h @[dec_decode_ctl.scala 440:12] + i0_dp_raw.crc32c_b <= i0_dec.io.out.crc32c_b @[dec_decode_ctl.scala 440:12] + i0_dp_raw.crc32_w <= i0_dec.io.out.crc32_w @[dec_decode_ctl.scala 440:12] + i0_dp_raw.crc32_h <= i0_dec.io.out.crc32_h @[dec_decode_ctl.scala 440:12] + i0_dp_raw.crc32_b <= i0_dec.io.out.crc32_b @[dec_decode_ctl.scala 440:12] + i0_dp_raw.zbp <= i0_dec.io.out.zbp @[dec_decode_ctl.scala 440:12] + i0_dp_raw.unshfl <= i0_dec.io.out.unshfl @[dec_decode_ctl.scala 440:12] + i0_dp_raw.shfl <= i0_dec.io.out.shfl @[dec_decode_ctl.scala 440:12] + i0_dp_raw.zbc <= i0_dec.io.out.zbc @[dec_decode_ctl.scala 440:12] + i0_dp_raw.clmulr <= i0_dec.io.out.clmulr @[dec_decode_ctl.scala 440:12] + i0_dp_raw.clmulh <= i0_dec.io.out.clmulh @[dec_decode_ctl.scala 440:12] + i0_dp_raw.clmul <= i0_dec.io.out.clmul @[dec_decode_ctl.scala 440:12] + i0_dp_raw.zbe <= i0_dec.io.out.zbe @[dec_decode_ctl.scala 440:12] + i0_dp_raw.bdep <= i0_dec.io.out.bdep @[dec_decode_ctl.scala 440:12] + i0_dp_raw.bext <= i0_dec.io.out.bext @[dec_decode_ctl.scala 440:12] + i0_dp_raw.zbs <= i0_dec.io.out.zbs @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sbext <= i0_dec.io.out.sbext @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sbinv <= i0_dec.io.out.sbinv @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sbclr <= i0_dec.io.out.sbclr @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sbset <= i0_dec.io.out.sbset @[dec_decode_ctl.scala 440:12] + i0_dp_raw.zbb <= i0_dec.io.out.zbb @[dec_decode_ctl.scala 440:12] + i0_dp_raw.gorc <= i0_dec.io.out.gorc @[dec_decode_ctl.scala 440:12] + i0_dp_raw.grev <= i0_dec.io.out.grev @[dec_decode_ctl.scala 440:12] + i0_dp_raw.ror <= i0_dec.io.out.ror @[dec_decode_ctl.scala 440:12] + i0_dp_raw.rol <= i0_dec.io.out.rol @[dec_decode_ctl.scala 440:12] + i0_dp_raw.packh <= i0_dec.io.out.packh @[dec_decode_ctl.scala 440:12] + i0_dp_raw.packu <= i0_dec.io.out.packu @[dec_decode_ctl.scala 440:12] + i0_dp_raw.pack <= i0_dec.io.out.pack @[dec_decode_ctl.scala 440:12] + i0_dp_raw.max <= i0_dec.io.out.max @[dec_decode_ctl.scala 440:12] + i0_dp_raw.min <= i0_dec.io.out.min @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sro <= i0_dec.io.out.sro @[dec_decode_ctl.scala 440:12] + i0_dp_raw.slo <= i0_dec.io.out.slo @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sext_h <= i0_dec.io.out.sext_h @[dec_decode_ctl.scala 440:12] + i0_dp_raw.sext_b <= i0_dec.io.out.sext_b @[dec_decode_ctl.scala 440:12] + i0_dp_raw.pcnt <= i0_dec.io.out.pcnt @[dec_decode_ctl.scala 440:12] + i0_dp_raw.ctz <= i0_dec.io.out.ctz @[dec_decode_ctl.scala 440:12] + i0_dp_raw.clz <= i0_dec.io.out.clz @[dec_decode_ctl.scala 440:12] + reg _T_366 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 442:45] + _T_366 <= io.lsu_idle_any @[dec_decode_ctl.scala 442:45] + lsu_idle <= _T_366 @[dec_decode_ctl.scala 442:11] + node _T_367 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 445:73] + node _T_368 = and(leak1_i1_stall, _T_367) @[dec_decode_ctl.scala 445:71] + node _T_369 = or(io.dec_tlu_flush_leak_one_r, _T_368) @[dec_decode_ctl.scala 445:53] + leak1_i1_stall_in <= _T_369 @[dec_decode_ctl.scala 445:21] + leak1_mode <= leak1_i1_stall @[dec_decode_ctl.scala 446:14] + node _T_370 = and(io.dec_aln.dec_i0_decode_d, leak1_i1_stall) @[dec_decode_ctl.scala 447:53] + node _T_371 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 447:91] + node _T_372 = and(leak1_i0_stall, _T_371) @[dec_decode_ctl.scala 447:89] + node _T_373 = or(_T_370, _T_372) @[dec_decode_ctl.scala 447:71] + leak1_i0_stall_in <= _T_373 @[dec_decode_ctl.scala 447:21] + node _T_374 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 451:29] + node _T_375 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 451:36] + node _T_376 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 451:46] + node _T_377 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 451:53] + node _T_378 = cat(_T_376, _T_377) @[Cat.scala 29:58] + node _T_379 = cat(_T_374, _T_375) @[Cat.scala 29:58] + node i0_pcall_imm = cat(_T_379, _T_378) @[Cat.scala 29:58] + node _T_380 = bits(i0_pcall_imm, 11, 11) @[dec_decode_ctl.scala 452:46] + node _T_381 = bits(_T_380, 0, 0) @[dec_decode_ctl.scala 452:51] + node _T_382 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 452:71] + node _T_383 = eq(_T_382, UInt<8>("h0ff")) @[dec_decode_ctl.scala 452:79] + node _T_384 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 452:104] + node _T_385 = eq(_T_384, UInt<8>("h00")) @[dec_decode_ctl.scala 452:112] + node i0_pcall_12b_offset = mux(_T_381, _T_383, _T_385) @[dec_decode_ctl.scala 452:33] + node _T_386 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 453:47] + node _T_387 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 453:76] + node _T_388 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 453:98] + node _T_389 = or(_T_387, _T_388) @[dec_decode_ctl.scala 453:89] + node i0_pcall_case = and(_T_386, _T_389) @[dec_decode_ctl.scala 453:65] + node _T_390 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 454:47] + node _T_391 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 454:76] + node _T_392 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 454:98] + node _T_393 = or(_T_391, _T_392) @[dec_decode_ctl.scala 454:89] + node _T_394 = eq(_T_393, UInt<1>("h00")) @[dec_decode_ctl.scala 454:67] + node i0_pja_case = and(_T_390, _T_394) @[dec_decode_ctl.scala 454:65] + node _T_395 = and(i0_dp_raw.jal, i0_pcall_case) @[dec_decode_ctl.scala 455:38] + i0_pcall_raw <= _T_395 @[dec_decode_ctl.scala 455:20] + node _T_396 = and(i0_dp.jal, i0_pcall_case) @[dec_decode_ctl.scala 456:38] + i0_pcall <= _T_396 @[dec_decode_ctl.scala 456:20] + node _T_397 = and(i0_dp_raw.jal, i0_pja_case) @[dec_decode_ctl.scala 457:38] + i0_pja_raw <= _T_397 @[dec_decode_ctl.scala 457:20] + node _T_398 = and(i0_dp.jal, i0_pja_case) @[dec_decode_ctl.scala 458:38] + i0_pja <= _T_398 @[dec_decode_ctl.scala 458:20] + node _T_399 = or(i0_pcall_raw, i0_pja_raw) @[dec_decode_ctl.scala 459:41] + node _T_400 = bits(_T_399, 0, 0) @[dec_decode_ctl.scala 459:55] + node _T_401 = bits(i0_pcall_imm, 11, 0) @[dec_decode_ctl.scala 459:75] + node _T_402 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 459:90] + node _T_403 = bits(io.dec_i0_instr_d, 7, 7) @[dec_decode_ctl.scala 459:97] + node _T_404 = bits(io.dec_i0_instr_d, 30, 25) @[dec_decode_ctl.scala 459:103] + node _T_405 = bits(io.dec_i0_instr_d, 11, 8) @[dec_decode_ctl.scala 459:113] + node _T_406 = cat(_T_404, _T_405) @[Cat.scala 29:58] + node _T_407 = cat(_T_402, _T_403) @[Cat.scala 29:58] + node _T_408 = cat(_T_407, _T_406) @[Cat.scala 29:58] + node _T_409 = mux(_T_400, _T_401, _T_408) @[dec_decode_ctl.scala 459:26] + i0_br_offset <= _T_409 @[dec_decode_ctl.scala 459:20] + node _T_410 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[dec_decode_ctl.scala 461:37] + node _T_411 = eq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 461:65] + node _T_412 = and(_T_410, _T_411) @[dec_decode_ctl.scala 461:55] + node _T_413 = eq(i0r.rs1, UInt<5>("h01")) @[dec_decode_ctl.scala 461:89] + node _T_414 = eq(i0r.rs1, UInt<5>("h05")) @[dec_decode_ctl.scala 461:111] + node _T_415 = or(_T_413, _T_414) @[dec_decode_ctl.scala 461:101] + node i0_pret_case = and(_T_412, _T_415) @[dec_decode_ctl.scala 461:79] + node _T_416 = and(i0_dp_raw.jal, i0_pret_case) @[dec_decode_ctl.scala 462:32] + i0_pret_raw <= _T_416 @[dec_decode_ctl.scala 462:15] + node _T_417 = and(i0_dp.jal, i0_pret_case) @[dec_decode_ctl.scala 463:32] + i0_pret <= _T_417 @[dec_decode_ctl.scala 463:15] + node _T_418 = eq(i0_pcall_case, UInt<1>("h00")) @[dec_decode_ctl.scala 464:35] + node _T_419 = and(i0_dp.jal, _T_418) @[dec_decode_ctl.scala 464:32] + node _T_420 = eq(i0_pja_case, UInt<1>("h00")) @[dec_decode_ctl.scala 464:52] + node _T_421 = and(_T_419, _T_420) @[dec_decode_ctl.scala 464:50] + node _T_422 = eq(i0_pret_case, UInt<1>("h00")) @[dec_decode_ctl.scala 464:67] + node _T_423 = and(_T_421, _T_422) @[dec_decode_ctl.scala 464:65] + i0_jal <= _T_423 @[dec_decode_ctl.scala 464:15] + io.dec_div.div_p.valid <= div_decode_d @[dec_decode_ctl.scala 467:29] + io.dec_div.div_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 468:34] + io.dec_div.div_p.bits.rem <= i0_dp.rem @[dec_decode_ctl.scala 469:34] + io.decode_exu.mul_p.valid <= mul_decode_d @[dec_decode_ctl.scala 471:32] + io.decode_exu.mul_p.bits.rs1_sign <= i0_dp.rs1_sign @[dec_decode_ctl.scala 472:37] + io.decode_exu.mul_p.bits.rs2_sign <= i0_dp.rs2_sign @[dec_decode_ctl.scala 473:37] + io.decode_exu.mul_p.bits.low <= i0_dp.low @[dec_decode_ctl.scala 474:37] + io.decode_exu.mul_p.bits.bext <= i0_dp.bext @[dec_decode_ctl.scala 475:37] + io.decode_exu.mul_p.bits.bdep <= i0_dp.bdep @[dec_decode_ctl.scala 476:37] + io.decode_exu.mul_p.bits.clmul <= i0_dp.clmul @[dec_decode_ctl.scala 477:37] + io.decode_exu.mul_p.bits.clmulh <= i0_dp.clmulh @[dec_decode_ctl.scala 478:37] + io.decode_exu.mul_p.bits.clmulr <= i0_dp.clmulr @[dec_decode_ctl.scala 479:37] + io.decode_exu.mul_p.bits.grev <= i0_dp.grev @[dec_decode_ctl.scala 480:37] + io.decode_exu.mul_p.bits.gorc <= i0_dp.gorc @[dec_decode_ctl.scala 481:37] + io.decode_exu.mul_p.bits.shfl <= i0_dp.shfl @[dec_decode_ctl.scala 482:37] + io.decode_exu.mul_p.bits.unshfl <= i0_dp.unshfl @[dec_decode_ctl.scala 483:37] + io.decode_exu.mul_p.bits.crc32_b <= i0_dp.crc32_b @[dec_decode_ctl.scala 484:37] + io.decode_exu.mul_p.bits.crc32_h <= i0_dp.crc32_h @[dec_decode_ctl.scala 485:37] + io.decode_exu.mul_p.bits.crc32_w <= i0_dp.crc32_w @[dec_decode_ctl.scala 486:37] + io.decode_exu.mul_p.bits.crc32c_b <= i0_dp.crc32c_b @[dec_decode_ctl.scala 487:37] + io.decode_exu.mul_p.bits.crc32c_h <= i0_dp.crc32c_h @[dec_decode_ctl.scala 488:37] + io.decode_exu.mul_p.bits.crc32c_w <= i0_dp.crc32c_w @[dec_decode_ctl.scala 489:37] + io.decode_exu.mul_p.bits.bfp <= i0_dp.bfp @[dec_decode_ctl.scala 490:37] + wire _T_424 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[dec_decode_ctl.scala 493:27] + _T_424.bits.store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.load_ldst_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.store_data_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.dma <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.store <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.load <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.dword <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.word <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.half <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.by <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.stack <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.bits.fast_int <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + _T_424.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 493:27] + io.lsu_p.bits.store_data_bypass_m <= _T_424.bits.store_data_bypass_m @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.load_ldst_bypass_d <= _T_424.bits.load_ldst_bypass_d @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.store_data_bypass_d <= _T_424.bits.store_data_bypass_d @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.dma <= _T_424.bits.dma @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.unsign <= _T_424.bits.unsign @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.store <= _T_424.bits.store @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.load <= _T_424.bits.load @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.dword <= _T_424.bits.dword @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.word <= _T_424.bits.word @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.half <= _T_424.bits.half @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.by <= _T_424.bits.by @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.stack <= _T_424.bits.stack @[dec_decode_ctl.scala 493:12] + io.lsu_p.bits.fast_int <= _T_424.bits.fast_int @[dec_decode_ctl.scala 493:12] + io.lsu_p.valid <= _T_424.valid @[dec_decode_ctl.scala 493:12] + when io.decode_exu.dec_extint_stall : @[dec_decode_ctl.scala 494:40] + io.lsu_p.bits.load <= UInt<1>("h01") @[dec_decode_ctl.scala 495:29] + io.lsu_p.bits.word <= UInt<1>("h01") @[dec_decode_ctl.scala 496:29] + io.lsu_p.bits.fast_int <= UInt<1>("h01") @[dec_decode_ctl.scala 497:29] + io.lsu_p.valid <= UInt<1>("h01") @[dec_decode_ctl.scala 498:24] + skip @[dec_decode_ctl.scala 494:40] + else : @[dec_decode_ctl.scala 501:15] + io.lsu_p.valid <= lsu_decode_d @[dec_decode_ctl.scala 502:35] + io.lsu_p.bits.load <= i0_dp.load @[dec_decode_ctl.scala 503:40] + io.lsu_p.bits.store <= i0_dp.store @[dec_decode_ctl.scala 504:40] + io.lsu_p.bits.by <= i0_dp.by @[dec_decode_ctl.scala 505:40] + io.lsu_p.bits.half <= i0_dp.half @[dec_decode_ctl.scala 506:40] + io.lsu_p.bits.word <= i0_dp.word @[dec_decode_ctl.scala 507:40] + node _T_425 = eq(i0r.rs1, UInt<5>("h02")) @[dec_decode_ctl.scala 508:41] + io.lsu_p.bits.stack <= _T_425 @[dec_decode_ctl.scala 508:29] + io.lsu_p.bits.load_ldst_bypass_d <= load_ldst_bypass_d @[dec_decode_ctl.scala 509:40] + io.lsu_p.bits.store_data_bypass_d <= store_data_bypass_d @[dec_decode_ctl.scala 510:40] + io.lsu_p.bits.store_data_bypass_m <= store_data_bypass_m @[dec_decode_ctl.scala 511:40] + io.lsu_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 512:40] + skip @[dec_decode_ctl.scala 501:15] + node _T_426 = and(i0_dp.csr_read, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 516:47] + io.dec_alu.dec_csr_ren_d <= _T_426 @[dec_decode_ctl.scala 516:29] + node _T_427 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 517:56] + node _T_428 = and(i0_dp.csr_read, _T_427) @[dec_decode_ctl.scala 517:36] + csr_read <= _T_428 @[dec_decode_ctl.scala 517:18] + node _T_429 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[dec_decode_ctl.scala 519:42] + node i0_csr_write = and(i0_dp.csr_write, _T_429) @[dec_decode_ctl.scala 519:40] + node _T_430 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 520:61] + node csr_clr_d = and(i0_dp.csr_clr, _T_430) @[dec_decode_ctl.scala 520:41] + node _T_431 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 521:59] + node csr_set_d = and(i0_dp.csr_set, _T_431) @[dec_decode_ctl.scala 521:39] + node _T_432 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 522:59] + node csr_write_d = and(i0_csr_write, _T_432) @[dec_decode_ctl.scala 522:39] + node _T_433 = eq(i0_dp.csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 524:41] + node _T_434 = and(i0_csr_write, _T_433) @[dec_decode_ctl.scala 524:39] + i0_csr_write_only_d <= _T_434 @[dec_decode_ctl.scala 524:23] + node _T_435 = or(i0_dp.csr_clr, i0_dp.csr_set) @[dec_decode_ctl.scala 525:42] + node _T_436 = or(_T_435, i0_csr_write) @[dec_decode_ctl.scala 525:58] + node _T_437 = and(_T_436, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 525:74] + io.dec_csr_wen_unq_d <= _T_437 @[dec_decode_ctl.scala 525:24] + node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[dec_decode_ctl.scala 527:34] + node _T_438 = and(any_csr_d, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 528:37] + io.dec_csr_any_unq_d <= _T_438 @[dec_decode_ctl.scala 528:24] + node _T_439 = bits(io.dec_csr_any_unq_d, 0, 0) @[Bitwise.scala 72:15] + node _T_440 = mux(_T_439, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] + node _T_441 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 529:62] + node _T_442 = and(_T_440, _T_441) @[dec_decode_ctl.scala 529:58] + io.dec_csr_rdaddr_d <= _T_442 @[dec_decode_ctl.scala 529:24] + node _T_443 = and(r_d.bits.csrwen, r_d.valid) @[dec_decode_ctl.scala 530:53] + node _T_444 = bits(_T_443, 0, 0) @[Bitwise.scala 72:15] + node _T_445 = mux(_T_444, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] + node _T_446 = and(_T_445, r_d.bits.csrwaddr) @[dec_decode_ctl.scala 530:67] + io.dec_csr_wraddr_r <= _T_446 @[dec_decode_ctl.scala 530:24] + node _T_447 = and(r_d.bits.csrwen, r_d.valid) @[dec_decode_ctl.scala 534:39] + node _T_448 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 534:53] + node _T_449 = and(_T_447, _T_448) @[dec_decode_ctl.scala 534:51] + io.dec_csr_wen_r <= _T_449 @[dec_decode_ctl.scala 534:20] + node _T_450 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[dec_decode_ctl.scala 537:50] + node _T_451 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[dec_decode_ctl.scala 537:85] + node _T_452 = or(_T_450, _T_451) @[dec_decode_ctl.scala 537:64] + node _T_453 = and(_T_452, r_d.bits.csrwen) @[dec_decode_ctl.scala 537:100] + node _T_454 = and(_T_453, r_d.valid) @[dec_decode_ctl.scala 537:118] + node _T_455 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 537:132] + node _T_456 = and(_T_454, _T_455) @[dec_decode_ctl.scala 537:130] + io.dec_csr_stall_int_ff <= _T_456 @[dec_decode_ctl.scala 537:27] + reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 539:52] + csr_read_x <= csr_read @[dec_decode_ctl.scala 539:52] + reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 540:51] + csr_clr_x <= csr_clr_d @[dec_decode_ctl.scala 540:51] + reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 541:51] + csr_set_x <= csr_set_d @[dec_decode_ctl.scala 541:51] + reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 542:53] + csr_write_x <= csr_write_d @[dec_decode_ctl.scala 542:53] + reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 543:51] + csr_imm_x <= i0_dp.csr_imm @[dec_decode_ctl.scala 543:51] + node _T_457 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 546:27] + node _T_458 = bits(any_csr_d, 0, 0) @[dec_decode_ctl.scala 546:60] + node _T_459 = and(i0_x_data_en, _T_458) @[dec_decode_ctl.scala 546:48] + node _T_460 = bits(_T_459, 0, 0) @[lib.scala 8:44] + inst rvclkhdr of rvclkhdr @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= _T_460 @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg csrimm_x : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_460 : @[Reg.scala 28:19] + csrimm_x <= _T_457 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_461 = bits(any_csr_d, 0, 0) @[dec_decode_ctl.scala 547:74] + node _T_462 = and(i0_x_data_en, _T_461) @[dec_decode_ctl.scala 547:62] + node _T_463 = bits(_T_462, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_463 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg csr_rddata_x : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_463 : @[Reg.scala 28:19] + csr_rddata_x <= io.dec_csr_rddata_d @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_464 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 550:15] + wire _T_465 : UInt<1>[27] @[lib.scala 12:48] + _T_465[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[9] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[10] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[11] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[12] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[13] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[14] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[15] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[16] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[17] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[18] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[19] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[20] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[21] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[22] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[23] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[24] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[25] <= UInt<1>("h00") @[lib.scala 12:48] + _T_465[26] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_466 = cat(_T_465[0], _T_465[1]) @[Cat.scala 29:58] + node _T_467 = cat(_T_466, _T_465[2]) @[Cat.scala 29:58] + node _T_468 = cat(_T_467, _T_465[3]) @[Cat.scala 29:58] + node _T_469 = cat(_T_468, _T_465[4]) @[Cat.scala 29:58] + node _T_470 = cat(_T_469, _T_465[5]) @[Cat.scala 29:58] + node _T_471 = cat(_T_470, _T_465[6]) @[Cat.scala 29:58] + node _T_472 = cat(_T_471, _T_465[7]) @[Cat.scala 29:58] + node _T_473 = cat(_T_472, _T_465[8]) @[Cat.scala 29:58] + node _T_474 = cat(_T_473, _T_465[9]) @[Cat.scala 29:58] + node _T_475 = cat(_T_474, _T_465[10]) @[Cat.scala 29:58] + node _T_476 = cat(_T_475, _T_465[11]) @[Cat.scala 29:58] + node _T_477 = cat(_T_476, _T_465[12]) @[Cat.scala 29:58] + node _T_478 = cat(_T_477, _T_465[13]) @[Cat.scala 29:58] + node _T_479 = cat(_T_478, _T_465[14]) @[Cat.scala 29:58] + node _T_480 = cat(_T_479, _T_465[15]) @[Cat.scala 29:58] + node _T_481 = cat(_T_480, _T_465[16]) @[Cat.scala 29:58] + node _T_482 = cat(_T_481, _T_465[17]) @[Cat.scala 29:58] + node _T_483 = cat(_T_482, _T_465[18]) @[Cat.scala 29:58] + node _T_484 = cat(_T_483, _T_465[19]) @[Cat.scala 29:58] + node _T_485 = cat(_T_484, _T_465[20]) @[Cat.scala 29:58] + node _T_486 = cat(_T_485, _T_465[21]) @[Cat.scala 29:58] + node _T_487 = cat(_T_486, _T_465[22]) @[Cat.scala 29:58] + node _T_488 = cat(_T_487, _T_465[23]) @[Cat.scala 29:58] + node _T_489 = cat(_T_488, _T_465[24]) @[Cat.scala 29:58] + node _T_490 = cat(_T_489, _T_465[25]) @[Cat.scala 29:58] + node _T_491 = cat(_T_490, _T_465[26]) @[Cat.scala 29:58] + node _T_492 = bits(csrimm_x, 4, 0) @[dec_decode_ctl.scala 550:53] + node _T_493 = cat(_T_491, _T_492) @[Cat.scala 29:58] + node _T_494 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 551:16] + node _T_495 = eq(_T_494, UInt<1>("h00")) @[dec_decode_ctl.scala 551:5] + node _T_496 = mux(_T_464, _T_493, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_497 = mux(_T_495, io.decode_exu.exu_csr_rs1_x, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_498 = or(_T_496, _T_497) @[Mux.scala 27:72] + wire csr_mask_x : UInt<32> @[Mux.scala 27:72] + csr_mask_x <= _T_498 @[Mux.scala 27:72] + node _T_499 = not(csr_mask_x) @[dec_decode_ctl.scala 554:38] + node _T_500 = and(csr_rddata_x, _T_499) @[dec_decode_ctl.scala 554:35] + node _T_501 = or(csr_rddata_x, csr_mask_x) @[dec_decode_ctl.scala 555:35] + node _T_502 = mux(csr_clr_x, _T_500, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_503 = mux(csr_set_x, _T_501, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_504 = mux(csr_write_x, csr_mask_x, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_505 = or(_T_502, _T_503) @[Mux.scala 27:72] + node _T_506 = or(_T_505, _T_504) @[Mux.scala 27:72] + wire write_csr_data_x : UInt @[Mux.scala 27:72] + write_csr_data_x <= _T_506 @[Mux.scala 27:72] + node _T_507 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[dec_decode_ctl.scala 558:49] + node _T_508 = and(io.dec_tlu_flush_lower_r, _T_507) @[dec_decode_ctl.scala 558:47] + node _T_509 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] + node _T_510 = bits(write_csr_data, 0, 0) @[dec_decode_ctl.scala 558:145] + node _T_511 = cat(_T_509, _T_510) @[Cat.scala 29:58] + node _T_512 = eq(write_csr_data, _T_511) @[dec_decode_ctl.scala 558:109] + node _T_513 = and(pause_stall, _T_512) @[dec_decode_ctl.scala 558:91] + node clear_pause = or(_T_508, _T_513) @[dec_decode_ctl.scala 558:76] + node _T_514 = or(io.dec_tlu_wr_pause_r, pause_stall) @[dec_decode_ctl.scala 559:44] + node _T_515 = eq(clear_pause, UInt<1>("h00")) @[dec_decode_ctl.scala 559:61] + node _T_516 = and(_T_514, _T_515) @[dec_decode_ctl.scala 559:59] + pause_state_in <= _T_516 @[dec_decode_ctl.scala 559:18] + io.dec_pause_state <= pause_stall @[dec_decode_ctl.scala 560:22] + node _T_517 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[dec_decode_ctl.scala 562:44] + node _T_518 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[dec_decode_ctl.scala 562:64] + node _T_519 = and(_T_517, _T_518) @[dec_decode_ctl.scala 562:61] + node _T_520 = and(pause_stall, _T_519) @[dec_decode_ctl.scala 562:41] + io.dec_pause_state_cg <= _T_520 @[dec_decode_ctl.scala 562:25] + node _T_521 = sub(write_csr_data, UInt<32>("h01")) @[dec_decode_ctl.scala 565:59] + node _T_522 = tail(_T_521, 1) @[dec_decode_ctl.scala 565:59] + node _T_523 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[dec_decode_ctl.scala 566:8] + node write_csr_data_in = mux(pause_stall, _T_522, _T_523) @[dec_decode_ctl.scala 565:30] + node _T_524 = or(csr_clr_x, csr_set_x) @[dec_decode_ctl.scala 567:34] + node _T_525 = or(_T_524, csr_write_x) @[dec_decode_ctl.scala 567:46] + node _T_526 = and(_T_525, csr_read_x) @[dec_decode_ctl.scala 567:61] + node _T_527 = or(_T_526, io.dec_tlu_wr_pause_r) @[dec_decode_ctl.scala 567:75] + node csr_data_wen = or(_T_527, pause_stall) @[dec_decode_ctl.scala 567:99] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_2.io.en <= csr_data_wen @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_528 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when csr_data_wen : @[Reg.scala 28:19] + _T_528 <= write_csr_data_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + write_csr_data <= _T_528 @[dec_decode_ctl.scala 568:18] + node _T_529 = and(r_d.bits.csrwonly, r_d.valid) @[dec_decode_ctl.scala 574:50] + node _T_530 = bits(_T_529, 0, 0) @[dec_decode_ctl.scala 574:63] + node _T_531 = mux(_T_530, i0_result_corr_r, write_csr_data) @[dec_decode_ctl.scala 574:30] + io.dec_csr_wrdata_r <= _T_531 @[dec_decode_ctl.scala 574:24] + node _T_532 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[dec_decode_ctl.scala 576:43] + node prior_csr_write = or(_T_532, wbd.bits.csrwonly) @[dec_decode_ctl.scala 576:63] + node _T_533 = bits(io.dbg_dctl.dbg_cmd_wrdata, 0, 0) @[dec_decode_ctl.scala 578:76] + node debug_fence_i = and(io.dec_debug_fence_d, _T_533) @[dec_decode_ctl.scala 578:48] + node _T_534 = bits(io.dbg_dctl.dbg_cmd_wrdata, 1, 1) @[dec_decode_ctl.scala 579:76] + node debug_fence_raw = and(io.dec_debug_fence_d, _T_534) @[dec_decode_ctl.scala 579:48] + node _T_535 = or(debug_fence_raw, debug_fence_i) @[dec_decode_ctl.scala 580:40] + debug_fence <= _T_535 @[dec_decode_ctl.scala 580:21] + node _T_536 = or(i0_dp.presync, io.dec_tlu_presync_d) @[dec_decode_ctl.scala 583:34] + node _T_537 = or(_T_536, debug_fence_i) @[dec_decode_ctl.scala 583:57] + node _T_538 = or(_T_537, debug_fence_raw) @[dec_decode_ctl.scala 583:73] + node i0_presync = or(_T_538, io.dec_tlu_pipelining_disable) @[dec_decode_ctl.scala 583:91] + node _T_539 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[dec_decode_ctl.scala 586:36] + node _T_540 = or(_T_539, debug_fence_i) @[dec_decode_ctl.scala 586:60] + node _T_541 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 586:104] + node _T_542 = eq(_T_541, UInt<11>("h07c2")) @[dec_decode_ctl.scala 586:112] + node _T_543 = and(i0_csr_write_only_d, _T_542) @[dec_decode_ctl.scala 586:99] + node i0_postsync = or(_T_540, _T_543) @[dec_decode_ctl.scala 586:76] + node _T_544 = eq(any_csr_d, UInt<1>("h00")) @[dec_decode_ctl.scala 590:40] + node _T_545 = or(_T_544, io.dec_csr_legal_d) @[dec_decode_ctl.scala 590:51] + node i0_legal = and(i0_dp.legal, _T_545) @[dec_decode_ctl.scala 590:37] + wire _T_546 : UInt<1>[16] @[lib.scala 12:48] + _T_546[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[9] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[10] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[11] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[12] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[13] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[14] <= UInt<1>("h00") @[lib.scala 12:48] + _T_546[15] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_547 = cat(_T_546[0], _T_546[1]) @[Cat.scala 29:58] + node _T_548 = cat(_T_547, _T_546[2]) @[Cat.scala 29:58] + node _T_549 = cat(_T_548, _T_546[3]) @[Cat.scala 29:58] + node _T_550 = cat(_T_549, _T_546[4]) @[Cat.scala 29:58] + node _T_551 = cat(_T_550, _T_546[5]) @[Cat.scala 29:58] + node _T_552 = cat(_T_551, _T_546[6]) @[Cat.scala 29:58] + node _T_553 = cat(_T_552, _T_546[7]) @[Cat.scala 29:58] + node _T_554 = cat(_T_553, _T_546[8]) @[Cat.scala 29:58] + node _T_555 = cat(_T_554, _T_546[9]) @[Cat.scala 29:58] + node _T_556 = cat(_T_555, _T_546[10]) @[Cat.scala 29:58] + node _T_557 = cat(_T_556, _T_546[11]) @[Cat.scala 29:58] + node _T_558 = cat(_T_557, _T_546[12]) @[Cat.scala 29:58] + node _T_559 = cat(_T_558, _T_546[13]) @[Cat.scala 29:58] + node _T_560 = cat(_T_559, _T_546[14]) @[Cat.scala 29:58] + node _T_561 = cat(_T_560, _T_546[15]) @[Cat.scala 29:58] + node _T_562 = cat(_T_561, io.dec_aln.ifu_i0_cinst) @[Cat.scala 29:58] + node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_562) @[dec_decode_ctl.scala 591:27] + node _T_563 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 594:57] + node shift_illegal = and(io.dec_aln.dec_i0_decode_d, _T_563) @[dec_decode_ctl.scala 594:55] + node _T_564 = eq(illegal_lockout, UInt<1>("h00")) @[dec_decode_ctl.scala 595:44] + node illegal_inst_en = and(shift_illegal, _T_564) @[dec_decode_ctl.scala 595:42] + inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= illegal_inst_en @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_565 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when illegal_inst_en : @[Reg.scala 28:19] + _T_565 <= i0_inst_d @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.dec_illegal_inst <= _T_565 @[dec_decode_ctl.scala 596:23] + node _T_566 = or(shift_illegal, illegal_lockout) @[dec_decode_ctl.scala 597:40] + node _T_567 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 597:61] + node _T_568 = and(_T_566, _T_567) @[dec_decode_ctl.scala 597:59] + illegal_lockout_in <= _T_568 @[dec_decode_ctl.scala 597:22] + node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[dec_decode_ctl.scala 598:42] + node _T_569 = and(i0_dp.csr_read, prior_csr_write) @[dec_decode_ctl.scala 600:40] + node _T_570 = or(_T_569, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 600:59] + node _T_571 = or(_T_570, pause_stall) @[dec_decode_ctl.scala 600:92] + node _T_572 = or(_T_571, leak1_i0_stall) @[dec_decode_ctl.scala 600:106] + node _T_573 = or(_T_572, io.dec_tlu_debug_stall) @[dec_decode_ctl.scala 601:20] + node _T_574 = or(_T_573, postsync_stall) @[dec_decode_ctl.scala 601:45] + node _T_575 = or(_T_574, presync_stall) @[dec_decode_ctl.scala 601:62] + node _T_576 = or(i0_dp.fence, debug_fence) @[dec_decode_ctl.scala 602:19] + node _T_577 = eq(lsu_idle, UInt<1>("h00")) @[dec_decode_ctl.scala 602:36] + node _T_578 = and(_T_576, _T_577) @[dec_decode_ctl.scala 602:34] + node _T_579 = or(_T_575, _T_578) @[dec_decode_ctl.scala 601:79] + node _T_580 = or(_T_579, i0_nonblock_load_stall) @[dec_decode_ctl.scala 602:47] + node _T_581 = or(_T_580, i0_load_block_d) @[dec_decode_ctl.scala 602:72] + node _T_582 = or(_T_581, i0_nonblock_div_stall) @[dec_decode_ctl.scala 603:21] + node i0_block_raw_d = or(_T_582, i0_div_prior_div_stall) @[dec_decode_ctl.scala 603:45] + node _T_583 = or(io.lsu_store_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 605:65] + node i0_store_stall_d = and(i0_dp.store, _T_583) @[dec_decode_ctl.scala 605:39] + node _T_584 = or(io.lsu_load_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 606:63] + node i0_load_stall_d = and(i0_dp.load, _T_584) @[dec_decode_ctl.scala 606:38] + node _T_585 = or(i0_block_raw_d, i0_store_stall_d) @[dec_decode_ctl.scala 607:38] + node i0_block_d = or(_T_585, i0_load_stall_d) @[dec_decode_ctl.scala 607:57] + node _T_586 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 611:54] + node _T_587 = and(io.dec_ib0_valid_d, _T_586) @[dec_decode_ctl.scala 611:52] + node _T_588 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 611:71] + node _T_589 = and(_T_587, _T_588) @[dec_decode_ctl.scala 611:69] + node _T_590 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 611:99] + node _T_591 = and(_T_589, _T_590) @[dec_decode_ctl.scala 611:97] + io.dec_aln.dec_i0_decode_d <= _T_591 @[dec_decode_ctl.scala 611:30] + node _T_592 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 612:46] + node _T_593 = and(io.dec_ib0_valid_d, _T_592) @[dec_decode_ctl.scala 612:44] + node _T_594 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 612:63] + node _T_595 = and(_T_593, _T_594) @[dec_decode_ctl.scala 612:61] + node _T_596 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 612:91] + node i0_exudecode_d = and(_T_595, _T_596) @[dec_decode_ctl.scala 612:89] + node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[dec_decode_ctl.scala 613:46] + io.dec_pmu_instr_decoded <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 616:28] + node _T_597 = eq(io.dec_aln.dec_i0_decode_d, UInt<1>("h00")) @[dec_decode_ctl.scala 617:51] + node _T_598 = and(io.dec_ib0_valid_d, _T_597) @[dec_decode_ctl.scala 617:49] + io.dec_pmu_decode_stall <= _T_598 @[dec_decode_ctl.scala 617:27] + node _T_599 = bits(postsync_stall, 0, 0) @[dec_decode_ctl.scala 618:47] + node _T_600 = and(_T_599, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 618:54] + io.dec_pmu_postsync_stall <= _T_600 @[dec_decode_ctl.scala 618:29] + node _T_601 = bits(presync_stall, 0, 0) @[dec_decode_ctl.scala 619:46] + node _T_602 = and(_T_601, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 619:53] + io.dec_pmu_presync_stall <= _T_602 @[dec_decode_ctl.scala 619:29] + node prior_inflight = or(x_d.valid, r_d.valid) @[dec_decode_ctl.scala 623:41] + node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[dec_decode_ctl.scala 624:31] + node _T_603 = and(i0_presync, prior_inflight_eff) @[dec_decode_ctl.scala 626:37] + presync_stall <= _T_603 @[dec_decode_ctl.scala 626:22] + node _T_604 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 628:64] + node _T_605 = or(i0_postsync, _T_604) @[dec_decode_ctl.scala 628:62] + node _T_606 = and(io.dec_aln.dec_i0_decode_d, _T_605) @[dec_decode_ctl.scala 628:47] + node _T_607 = and(postsync_stall, x_d.valid) @[dec_decode_ctl.scala 628:96] + node _T_608 = or(_T_606, _T_607) @[dec_decode_ctl.scala 628:77] + ps_stall_in <= _T_608 @[dec_decode_ctl.scala 628:15] + node _T_609 = and(i0_exulegal_decode_d, i0_dp.alu) @[dec_decode_ctl.scala 630:58] + io.dec_alu.dec_i0_alu_decode_d <= _T_609 @[dec_decode_ctl.scala 630:34] + node _T_610 = or(i0_dp.condbr, i0_dp.jal) @[dec_decode_ctl.scala 631:53] + node _T_611 = or(_T_610, i0_br_error_all) @[dec_decode_ctl.scala 631:65] + io.decode_exu.dec_i0_branch_d <= _T_611 @[dec_decode_ctl.scala 631:37] + node _T_612 = and(i0_legal_decode_d, i0_dp.lsu) @[dec_decode_ctl.scala 633:40] + lsu_decode_d <= _T_612 @[dec_decode_ctl.scala 633:16] + node _T_613 = and(i0_exulegal_decode_d, i0_dp.mul) @[dec_decode_ctl.scala 634:40] + mul_decode_d <= _T_613 @[dec_decode_ctl.scala 634:16] + node _T_614 = and(i0_exulegal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 635:40] + div_decode_d <= _T_614 @[dec_decode_ctl.scala 635:16] + io.dec_qual_lsu_d <= i0_dp.lsu @[dec_decode_ctl.scala 636:21] + node _T_615 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 637:45] + node _T_616 = and(r_d.valid, _T_615) @[dec_decode_ctl.scala 637:43] + io.dec_tlu_i0_valid_r <= _T_616 @[dec_decode_ctl.scala 637:29] + d_t.legal <= i0_legal_decode_d @[dec_decode_ctl.scala 640:26] + node _T_617 = and(i0_icaf_d, i0_legal_decode_d) @[dec_decode_ctl.scala 641:40] + d_t.icaf <= _T_617 @[dec_decode_ctl.scala 641:26] + node _T_618 = and(io.dec_i0_icaf_second_d, i0_legal_decode_d) @[dec_decode_ctl.scala 642:58] + d_t.icaf_second <= _T_618 @[dec_decode_ctl.scala 642:30] + d_t.icaf_type <= io.dec_i0_icaf_type_d @[dec_decode_ctl.scala 643:26] + node _T_619 = or(i0_dp.fence_i, debug_fence_i) @[dec_decode_ctl.scala 645:44] + node _T_620 = and(_T_619, i0_legal_decode_d) @[dec_decode_ctl.scala 645:61] + d_t.fence_i <= _T_620 @[dec_decode_ctl.scala 645:26] + d_t.pmu_i0_br_unpred <= i0_br_unpred @[dec_decode_ctl.scala 648:26] + d_t.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 649:26] + d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 650:26] + wire _T_621 : UInt<1>[4] @[lib.scala 12:48] + _T_621[0] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48] + _T_621[1] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48] + _T_621[2] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48] + _T_621[3] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48] + node _T_622 = cat(_T_621[0], _T_621[1]) @[Cat.scala 29:58] + node _T_623 = cat(_T_622, _T_621[2]) @[Cat.scala 29:58] + node _T_624 = cat(_T_623, _T_621[3]) @[Cat.scala 29:58] + node _T_625 = and(io.dec_i0_trigger_match_d, _T_624) @[dec_decode_ctl.scala 652:56] + d_t.i0trigger <= _T_625 @[dec_decode_ctl.scala 652:26] + node _T_626 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 655:60] + wire _T_627 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[lib.scala 630:37] + _T_627.pmu_lsu_misaligned <= UInt<1>("h00") @[lib.scala 630:37] + _T_627.pmu_divide <= UInt<1>("h00") @[lib.scala 630:37] + _T_627.pmu_i0_br_unpred <= UInt<1>("h00") @[lib.scala 630:37] + _T_627.pmu_i0_itype <= UInt<4>("h00") @[lib.scala 630:37] + _T_627.i0trigger <= UInt<4>("h00") @[lib.scala 630:37] + _T_627.fence_i <= UInt<1>("h00") @[lib.scala 630:37] + _T_627.icaf_type <= UInt<2>("h00") @[lib.scala 630:37] + _T_627.icaf_second <= UInt<1>("h00") @[lib.scala 630:37] + _T_627.icaf <= UInt<1>("h00") @[lib.scala 630:37] + _T_627.legal <= UInt<1>("h00") @[lib.scala 630:37] + reg _T_628 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, clock with : (reset => (reset, _T_627)) @[Reg.scala 27:20] + when _T_626 : @[Reg.scala 28:19] + _T_628.pmu_lsu_misaligned <= d_t.pmu_lsu_misaligned @[Reg.scala 28:23] + _T_628.pmu_divide <= d_t.pmu_divide @[Reg.scala 28:23] + _T_628.pmu_i0_br_unpred <= d_t.pmu_i0_br_unpred @[Reg.scala 28:23] + _T_628.pmu_i0_itype <= d_t.pmu_i0_itype @[Reg.scala 28:23] + _T_628.i0trigger <= d_t.i0trigger @[Reg.scala 28:23] + _T_628.fence_i <= d_t.fence_i @[Reg.scala 28:23] + _T_628.icaf_type <= d_t.icaf_type @[Reg.scala 28:23] + _T_628.icaf_second <= d_t.icaf_second @[Reg.scala 28:23] + _T_628.icaf <= d_t.icaf @[Reg.scala 28:23] + _T_628.legal <= d_t.legal @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + x_t.pmu_lsu_misaligned <= _T_628.pmu_lsu_misaligned @[dec_decode_ctl.scala 655:7] + x_t.pmu_divide <= _T_628.pmu_divide @[dec_decode_ctl.scala 655:7] + x_t.pmu_i0_br_unpred <= _T_628.pmu_i0_br_unpred @[dec_decode_ctl.scala 655:7] + x_t.pmu_i0_itype <= _T_628.pmu_i0_itype @[dec_decode_ctl.scala 655:7] + x_t.i0trigger <= _T_628.i0trigger @[dec_decode_ctl.scala 655:7] + x_t.fence_i <= _T_628.fence_i @[dec_decode_ctl.scala 655:7] + x_t.icaf_type <= _T_628.icaf_type @[dec_decode_ctl.scala 655:7] + x_t.icaf_second <= _T_628.icaf_second @[dec_decode_ctl.scala 655:7] + x_t.icaf <= _T_628.icaf @[dec_decode_ctl.scala 655:7] + x_t.legal <= _T_628.legal @[dec_decode_ctl.scala 655:7] + x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 657:10] + x_t_in.pmu_divide <= x_t.pmu_divide @[dec_decode_ctl.scala 657:10] + x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 657:10] + x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[dec_decode_ctl.scala 657:10] + x_t_in.i0trigger <= x_t.i0trigger @[dec_decode_ctl.scala 657:10] + x_t_in.fence_i <= x_t.fence_i @[dec_decode_ctl.scala 657:10] + x_t_in.icaf_type <= x_t.icaf_type @[dec_decode_ctl.scala 657:10] + x_t_in.icaf_second <= x_t.icaf_second @[dec_decode_ctl.scala 657:10] + x_t_in.icaf <= x_t.icaf @[dec_decode_ctl.scala 657:10] + x_t_in.legal <= x_t.legal @[dec_decode_ctl.scala 657:10] + wire _T_629 : UInt<1>[4] @[lib.scala 12:48] + _T_629[0] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] + _T_629[1] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] + _T_629[2] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] + _T_629[3] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] + node _T_630 = cat(_T_629[0], _T_629[1]) @[Cat.scala 29:58] + node _T_631 = cat(_T_630, _T_629[2]) @[Cat.scala 29:58] + node _T_632 = cat(_T_631, _T_629[3]) @[Cat.scala 29:58] + node _T_633 = not(_T_632) @[dec_decode_ctl.scala 658:39] + node _T_634 = and(x_t.i0trigger, _T_633) @[dec_decode_ctl.scala 658:37] + x_t_in.i0trigger <= _T_634 @[dec_decode_ctl.scala 658:20] + node _T_635 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 660:63] + wire _T_636 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[lib.scala 630:37] + _T_636.pmu_lsu_misaligned <= UInt<1>("h00") @[lib.scala 630:37] + _T_636.pmu_divide <= UInt<1>("h00") @[lib.scala 630:37] + _T_636.pmu_i0_br_unpred <= UInt<1>("h00") @[lib.scala 630:37] + _T_636.pmu_i0_itype <= UInt<4>("h00") @[lib.scala 630:37] + _T_636.i0trigger <= UInt<4>("h00") @[lib.scala 630:37] + _T_636.fence_i <= UInt<1>("h00") @[lib.scala 630:37] + _T_636.icaf_type <= UInt<2>("h00") @[lib.scala 630:37] + _T_636.icaf_second <= UInt<1>("h00") @[lib.scala 630:37] + _T_636.icaf <= UInt<1>("h00") @[lib.scala 630:37] + _T_636.legal <= UInt<1>("h00") @[lib.scala 630:37] + reg _T_637 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, clock with : (reset => (reset, _T_636)) @[Reg.scala 27:20] + when _T_635 : @[Reg.scala 28:19] + _T_637.pmu_lsu_misaligned <= x_t_in.pmu_lsu_misaligned @[Reg.scala 28:23] + _T_637.pmu_divide <= x_t_in.pmu_divide @[Reg.scala 28:23] + _T_637.pmu_i0_br_unpred <= x_t_in.pmu_i0_br_unpred @[Reg.scala 28:23] + _T_637.pmu_i0_itype <= x_t_in.pmu_i0_itype @[Reg.scala 28:23] + _T_637.i0trigger <= x_t_in.i0trigger @[Reg.scala 28:23] + _T_637.fence_i <= x_t_in.fence_i @[Reg.scala 28:23] + _T_637.icaf_type <= x_t_in.icaf_type @[Reg.scala 28:23] + _T_637.icaf_second <= x_t_in.icaf_second @[Reg.scala 28:23] + _T_637.icaf <= x_t_in.icaf @[Reg.scala 28:23] + _T_637.legal <= x_t_in.legal @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + r_t.pmu_lsu_misaligned <= _T_637.pmu_lsu_misaligned @[dec_decode_ctl.scala 660:7] + r_t.pmu_divide <= _T_637.pmu_divide @[dec_decode_ctl.scala 660:7] + r_t.pmu_i0_br_unpred <= _T_637.pmu_i0_br_unpred @[dec_decode_ctl.scala 660:7] + r_t.pmu_i0_itype <= _T_637.pmu_i0_itype @[dec_decode_ctl.scala 660:7] + r_t.i0trigger <= _T_637.i0trigger @[dec_decode_ctl.scala 660:7] + r_t.fence_i <= _T_637.fence_i @[dec_decode_ctl.scala 660:7] + r_t.icaf_type <= _T_637.icaf_type @[dec_decode_ctl.scala 660:7] + r_t.icaf_second <= _T_637.icaf_second @[dec_decode_ctl.scala 660:7] + r_t.icaf <= _T_637.icaf @[dec_decode_ctl.scala 660:7] + r_t.legal <= _T_637.legal @[dec_decode_ctl.scala 660:7] + r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 662:10] + r_t_in.pmu_divide <= r_t.pmu_divide @[dec_decode_ctl.scala 662:10] + r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 662:10] + r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[dec_decode_ctl.scala 662:10] + r_t_in.i0trigger <= r_t.i0trigger @[dec_decode_ctl.scala 662:10] + r_t_in.fence_i <= r_t.fence_i @[dec_decode_ctl.scala 662:10] + r_t_in.icaf_type <= r_t.icaf_type @[dec_decode_ctl.scala 662:10] + r_t_in.icaf_second <= r_t.icaf_second @[dec_decode_ctl.scala 662:10] + r_t_in.icaf <= r_t.icaf @[dec_decode_ctl.scala 662:10] + r_t_in.legal <= r_t.legal @[dec_decode_ctl.scala 662:10] + node _T_638 = or(r_d.bits.i0load, r_d.bits.i0store) @[dec_decode_ctl.scala 664:61] + wire _T_639 : UInt<1>[4] @[lib.scala 12:48] + _T_639[0] <= _T_638 @[lib.scala 12:48] + _T_639[1] <= _T_638 @[lib.scala 12:48] + _T_639[2] <= _T_638 @[lib.scala 12:48] + _T_639[3] <= _T_638 @[lib.scala 12:48] + node _T_640 = cat(_T_639[0], _T_639[1]) @[Cat.scala 29:58] + node _T_641 = cat(_T_640, _T_639[2]) @[Cat.scala 29:58] + node _T_642 = cat(_T_641, _T_639[3]) @[Cat.scala 29:58] + node _T_643 = and(_T_642, lsu_trigger_match_r) @[dec_decode_ctl.scala 664:82] + node _T_644 = or(_T_643, r_t.i0trigger) @[dec_decode_ctl.scala 664:105] + r_t_in.i0trigger <= _T_644 @[dec_decode_ctl.scala 664:33] + r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[dec_decode_ctl.scala 665:33] + node _T_645 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[dec_decode_ctl.scala 667:35] + when _T_645 : @[dec_decode_ctl.scala 667:43] + wire _T_646 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 667:66] + _T_646.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + _T_646.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + _T_646.pmu_i0_br_unpred <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + _T_646.pmu_i0_itype <= UInt<4>("h00") @[dec_decode_ctl.scala 667:66] + _T_646.i0trigger <= UInt<4>("h00") @[dec_decode_ctl.scala 667:66] + _T_646.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + _T_646.icaf_type <= UInt<2>("h00") @[dec_decode_ctl.scala 667:66] + _T_646.icaf_second <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + _T_646.icaf <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + _T_646.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66] + r_t_in.pmu_lsu_misaligned <= _T_646.pmu_lsu_misaligned @[dec_decode_ctl.scala 667:51] + r_t_in.pmu_divide <= _T_646.pmu_divide @[dec_decode_ctl.scala 667:51] + r_t_in.pmu_i0_br_unpred <= _T_646.pmu_i0_br_unpred @[dec_decode_ctl.scala 667:51] + r_t_in.pmu_i0_itype <= _T_646.pmu_i0_itype @[dec_decode_ctl.scala 667:51] + r_t_in.i0trigger <= _T_646.i0trigger @[dec_decode_ctl.scala 667:51] + r_t_in.fence_i <= _T_646.fence_i @[dec_decode_ctl.scala 667:51] + r_t_in.icaf_type <= _T_646.icaf_type @[dec_decode_ctl.scala 667:51] + r_t_in.icaf_second <= _T_646.icaf_second @[dec_decode_ctl.scala 667:51] + r_t_in.icaf <= _T_646.icaf @[dec_decode_ctl.scala 667:51] + r_t_in.legal <= _T_646.legal @[dec_decode_ctl.scala 667:51] + skip @[dec_decode_ctl.scala 667:43] + io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.icaf_second <= r_t_in.icaf_second @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[dec_decode_ctl.scala 669:39] + io.dec_tlu_packet_r.legal <= r_t_in.legal @[dec_decode_ctl.scala 669:39] + node _T_647 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 670:58] + io.dec_tlu_packet_r.pmu_divide <= _T_647 @[dec_decode_ctl.scala 670:39] + node _T_648 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 674:54] + node _T_649 = and(io.dec_ib0_valid_d, _T_648) @[dec_decode_ctl.scala 674:52] + node _T_650 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 674:68] + node _T_651 = and(_T_649, _T_650) @[dec_decode_ctl.scala 674:66] + node _T_652 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 674:96] + node _T_653 = and(_T_651, _T_652) @[dec_decode_ctl.scala 674:94] + io.dec_aln.dec_i0_decode_d <= _T_653 @[dec_decode_ctl.scala 674:30] + node _T_654 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 676:16] + i0r.rs1 <= _T_654 @[dec_decode_ctl.scala 676:11] + node _T_655 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 677:16] + i0r.rs2 <= _T_655 @[dec_decode_ctl.scala 677:11] + node _T_656 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 678:16] + i0r.rd <= _T_656 @[dec_decode_ctl.scala 678:11] + node _T_657 = neq(i0r.rs1, UInt<5>("h00")) @[dec_decode_ctl.scala 680:60] + node _T_658 = and(i0_dp.rs1, _T_657) @[dec_decode_ctl.scala 680:49] + io.decode_exu.dec_i0_rs1_en_d <= _T_658 @[dec_decode_ctl.scala 680:35] + node _T_659 = neq(i0r.rs2, UInt<5>("h00")) @[dec_decode_ctl.scala 681:60] + node _T_660 = and(i0_dp.rs2, _T_659) @[dec_decode_ctl.scala 681:49] + io.decode_exu.dec_i0_rs2_en_d <= _T_660 @[dec_decode_ctl.scala 681:35] + node _T_661 = neq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 682:48] + node i0_rd_en_d = and(i0_dp.rd, _T_661) @[dec_decode_ctl.scala 682:37] + io.dec_i0_rs1_d <= i0r.rs1 @[dec_decode_ctl.scala 683:19] + io.dec_i0_rs2_d <= i0r.rs2 @[dec_decode_ctl.scala 684:19] + node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[dec_decode_ctl.scala 686:38] + node _T_662 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 687:27] + node i0_uiimm20 = and(_T_662, i0_dp.imm20) @[dec_decode_ctl.scala 687:38] + node _T_663 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 694:38] + wire _T_664 : UInt<1>[20] @[lib.scala 12:48] + _T_664[0] <= _T_663 @[lib.scala 12:48] + _T_664[1] <= _T_663 @[lib.scala 12:48] + _T_664[2] <= _T_663 @[lib.scala 12:48] + _T_664[3] <= _T_663 @[lib.scala 12:48] + _T_664[4] <= _T_663 @[lib.scala 12:48] + _T_664[5] <= _T_663 @[lib.scala 12:48] + _T_664[6] <= _T_663 @[lib.scala 12:48] + _T_664[7] <= _T_663 @[lib.scala 12:48] + _T_664[8] <= _T_663 @[lib.scala 12:48] + _T_664[9] <= _T_663 @[lib.scala 12:48] + _T_664[10] <= _T_663 @[lib.scala 12:48] + _T_664[11] <= _T_663 @[lib.scala 12:48] + _T_664[12] <= _T_663 @[lib.scala 12:48] + _T_664[13] <= _T_663 @[lib.scala 12:48] + _T_664[14] <= _T_663 @[lib.scala 12:48] + _T_664[15] <= _T_663 @[lib.scala 12:48] + _T_664[16] <= _T_663 @[lib.scala 12:48] + _T_664[17] <= _T_663 @[lib.scala 12:48] + _T_664[18] <= _T_663 @[lib.scala 12:48] + _T_664[19] <= _T_663 @[lib.scala 12:48] + node _T_665 = cat(_T_664[0], _T_664[1]) @[Cat.scala 29:58] + node _T_666 = cat(_T_665, _T_664[2]) @[Cat.scala 29:58] + node _T_667 = cat(_T_666, _T_664[3]) @[Cat.scala 29:58] + node _T_668 = cat(_T_667, _T_664[4]) @[Cat.scala 29:58] + node _T_669 = cat(_T_668, _T_664[5]) @[Cat.scala 29:58] + node _T_670 = cat(_T_669, _T_664[6]) @[Cat.scala 29:58] + node _T_671 = cat(_T_670, _T_664[7]) @[Cat.scala 29:58] + node _T_672 = cat(_T_671, _T_664[8]) @[Cat.scala 29:58] + node _T_673 = cat(_T_672, _T_664[9]) @[Cat.scala 29:58] + node _T_674 = cat(_T_673, _T_664[10]) @[Cat.scala 29:58] + node _T_675 = cat(_T_674, _T_664[11]) @[Cat.scala 29:58] + node _T_676 = cat(_T_675, _T_664[12]) @[Cat.scala 29:58] + node _T_677 = cat(_T_676, _T_664[13]) @[Cat.scala 29:58] + node _T_678 = cat(_T_677, _T_664[14]) @[Cat.scala 29:58] + node _T_679 = cat(_T_678, _T_664[15]) @[Cat.scala 29:58] + node _T_680 = cat(_T_679, _T_664[16]) @[Cat.scala 29:58] + node _T_681 = cat(_T_680, _T_664[17]) @[Cat.scala 29:58] + node _T_682 = cat(_T_681, _T_664[18]) @[Cat.scala 29:58] + node _T_683 = cat(_T_682, _T_664[19]) @[Cat.scala 29:58] + node _T_684 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 694:46] + node _T_685 = cat(_T_683, _T_684) @[Cat.scala 29:58] + wire _T_686 : UInt<1>[27] @[lib.scala 12:48] + _T_686[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[9] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[10] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[11] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[12] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[13] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[14] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[15] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[16] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[17] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[18] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[19] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[20] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[21] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[22] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[23] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[24] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[25] <= UInt<1>("h00") @[lib.scala 12:48] + _T_686[26] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_687 = cat(_T_686[0], _T_686[1]) @[Cat.scala 29:58] + node _T_688 = cat(_T_687, _T_686[2]) @[Cat.scala 29:58] + node _T_689 = cat(_T_688, _T_686[3]) @[Cat.scala 29:58] + node _T_690 = cat(_T_689, _T_686[4]) @[Cat.scala 29:58] + node _T_691 = cat(_T_690, _T_686[5]) @[Cat.scala 29:58] + node _T_692 = cat(_T_691, _T_686[6]) @[Cat.scala 29:58] + node _T_693 = cat(_T_692, _T_686[7]) @[Cat.scala 29:58] + node _T_694 = cat(_T_693, _T_686[8]) @[Cat.scala 29:58] + node _T_695 = cat(_T_694, _T_686[9]) @[Cat.scala 29:58] + node _T_696 = cat(_T_695, _T_686[10]) @[Cat.scala 29:58] + node _T_697 = cat(_T_696, _T_686[11]) @[Cat.scala 29:58] + node _T_698 = cat(_T_697, _T_686[12]) @[Cat.scala 29:58] + node _T_699 = cat(_T_698, _T_686[13]) @[Cat.scala 29:58] + node _T_700 = cat(_T_699, _T_686[14]) @[Cat.scala 29:58] + node _T_701 = cat(_T_700, _T_686[15]) @[Cat.scala 29:58] + node _T_702 = cat(_T_701, _T_686[16]) @[Cat.scala 29:58] + node _T_703 = cat(_T_702, _T_686[17]) @[Cat.scala 29:58] + node _T_704 = cat(_T_703, _T_686[18]) @[Cat.scala 29:58] + node _T_705 = cat(_T_704, _T_686[19]) @[Cat.scala 29:58] + node _T_706 = cat(_T_705, _T_686[20]) @[Cat.scala 29:58] + node _T_707 = cat(_T_706, _T_686[21]) @[Cat.scala 29:58] + node _T_708 = cat(_T_707, _T_686[22]) @[Cat.scala 29:58] + node _T_709 = cat(_T_708, _T_686[23]) @[Cat.scala 29:58] + node _T_710 = cat(_T_709, _T_686[24]) @[Cat.scala 29:58] + node _T_711 = cat(_T_710, _T_686[25]) @[Cat.scala 29:58] + node _T_712 = cat(_T_711, _T_686[26]) @[Cat.scala 29:58] + node _T_713 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 695:43] + node _T_714 = cat(_T_712, _T_713) @[Cat.scala 29:58] + node _T_715 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 696:38] + wire _T_716 : UInt<1>[12] @[lib.scala 12:48] + _T_716[0] <= _T_715 @[lib.scala 12:48] + _T_716[1] <= _T_715 @[lib.scala 12:48] + _T_716[2] <= _T_715 @[lib.scala 12:48] + _T_716[3] <= _T_715 @[lib.scala 12:48] + _T_716[4] <= _T_715 @[lib.scala 12:48] + _T_716[5] <= _T_715 @[lib.scala 12:48] + _T_716[6] <= _T_715 @[lib.scala 12:48] + _T_716[7] <= _T_715 @[lib.scala 12:48] + _T_716[8] <= _T_715 @[lib.scala 12:48] + _T_716[9] <= _T_715 @[lib.scala 12:48] + _T_716[10] <= _T_715 @[lib.scala 12:48] + _T_716[11] <= _T_715 @[lib.scala 12:48] + node _T_717 = cat(_T_716[0], _T_716[1]) @[Cat.scala 29:58] + node _T_718 = cat(_T_717, _T_716[2]) @[Cat.scala 29:58] + node _T_719 = cat(_T_718, _T_716[3]) @[Cat.scala 29:58] + node _T_720 = cat(_T_719, _T_716[4]) @[Cat.scala 29:58] + node _T_721 = cat(_T_720, _T_716[5]) @[Cat.scala 29:58] + node _T_722 = cat(_T_721, _T_716[6]) @[Cat.scala 29:58] + node _T_723 = cat(_T_722, _T_716[7]) @[Cat.scala 29:58] + node _T_724 = cat(_T_723, _T_716[8]) @[Cat.scala 29:58] + node _T_725 = cat(_T_724, _T_716[9]) @[Cat.scala 29:58] + node _T_726 = cat(_T_725, _T_716[10]) @[Cat.scala 29:58] + node _T_727 = cat(_T_726, _T_716[11]) @[Cat.scala 29:58] + node _T_728 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 696:46] + node _T_729 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 696:56] + node _T_730 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 696:63] + node _T_731 = cat(_T_730, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_732 = cat(_T_727, _T_728) @[Cat.scala 29:58] + node _T_733 = cat(_T_732, _T_729) @[Cat.scala 29:58] + node _T_734 = cat(_T_733, _T_731) @[Cat.scala 29:58] + node _T_735 = bits(io.dec_i0_instr_d, 31, 12) @[dec_decode_ctl.scala 697:30] + wire _T_736 : UInt<1>[12] @[lib.scala 12:48] + _T_736[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[9] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[10] <= UInt<1>("h00") @[lib.scala 12:48] + _T_736[11] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_737 = cat(_T_736[0], _T_736[1]) @[Cat.scala 29:58] + node _T_738 = cat(_T_737, _T_736[2]) @[Cat.scala 29:58] + node _T_739 = cat(_T_738, _T_736[3]) @[Cat.scala 29:58] + node _T_740 = cat(_T_739, _T_736[4]) @[Cat.scala 29:58] + node _T_741 = cat(_T_740, _T_736[5]) @[Cat.scala 29:58] + node _T_742 = cat(_T_741, _T_736[6]) @[Cat.scala 29:58] + node _T_743 = cat(_T_742, _T_736[7]) @[Cat.scala 29:58] + node _T_744 = cat(_T_743, _T_736[8]) @[Cat.scala 29:58] + node _T_745 = cat(_T_744, _T_736[9]) @[Cat.scala 29:58] + node _T_746 = cat(_T_745, _T_736[10]) @[Cat.scala 29:58] + node _T_747 = cat(_T_746, _T_736[11]) @[Cat.scala 29:58] + node _T_748 = cat(_T_735, _T_747) @[Cat.scala 29:58] + node _T_749 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[dec_decode_ctl.scala 698:26] + node _T_750 = bits(_T_749, 0, 0) @[dec_decode_ctl.scala 698:43] + wire _T_751 : UInt<1>[27] @[lib.scala 12:48] + _T_751[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[9] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[10] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[11] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[12] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[13] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[14] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[15] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[16] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[17] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[18] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[19] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[20] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[21] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[22] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[23] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[24] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[25] <= UInt<1>("h00") @[lib.scala 12:48] + _T_751[26] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_752 = cat(_T_751[0], _T_751[1]) @[Cat.scala 29:58] + node _T_753 = cat(_T_752, _T_751[2]) @[Cat.scala 29:58] + node _T_754 = cat(_T_753, _T_751[3]) @[Cat.scala 29:58] + node _T_755 = cat(_T_754, _T_751[4]) @[Cat.scala 29:58] + node _T_756 = cat(_T_755, _T_751[5]) @[Cat.scala 29:58] + node _T_757 = cat(_T_756, _T_751[6]) @[Cat.scala 29:58] + node _T_758 = cat(_T_757, _T_751[7]) @[Cat.scala 29:58] + node _T_759 = cat(_T_758, _T_751[8]) @[Cat.scala 29:58] + node _T_760 = cat(_T_759, _T_751[9]) @[Cat.scala 29:58] + node _T_761 = cat(_T_760, _T_751[10]) @[Cat.scala 29:58] + node _T_762 = cat(_T_761, _T_751[11]) @[Cat.scala 29:58] + node _T_763 = cat(_T_762, _T_751[12]) @[Cat.scala 29:58] + node _T_764 = cat(_T_763, _T_751[13]) @[Cat.scala 29:58] + node _T_765 = cat(_T_764, _T_751[14]) @[Cat.scala 29:58] + node _T_766 = cat(_T_765, _T_751[15]) @[Cat.scala 29:58] + node _T_767 = cat(_T_766, _T_751[16]) @[Cat.scala 29:58] + node _T_768 = cat(_T_767, _T_751[17]) @[Cat.scala 29:58] + node _T_769 = cat(_T_768, _T_751[18]) @[Cat.scala 29:58] + node _T_770 = cat(_T_769, _T_751[19]) @[Cat.scala 29:58] + node _T_771 = cat(_T_770, _T_751[20]) @[Cat.scala 29:58] + node _T_772 = cat(_T_771, _T_751[21]) @[Cat.scala 29:58] + node _T_773 = cat(_T_772, _T_751[22]) @[Cat.scala 29:58] + node _T_774 = cat(_T_773, _T_751[23]) @[Cat.scala 29:58] + node _T_775 = cat(_T_774, _T_751[24]) @[Cat.scala 29:58] + node _T_776 = cat(_T_775, _T_751[25]) @[Cat.scala 29:58] + node _T_777 = cat(_T_776, _T_751[26]) @[Cat.scala 29:58] + node _T_778 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 698:72] + node _T_779 = cat(_T_777, _T_778) @[Cat.scala 29:58] + node _T_780 = mux(i0_dp.imm12, _T_685, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_781 = mux(i0_dp.shimm5, _T_714, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_782 = mux(i0_jalimm20, _T_734, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_783 = mux(i0_uiimm20, _T_748, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_784 = mux(_T_750, _T_779, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_785 = or(_T_780, _T_781) @[Mux.scala 27:72] + node _T_786 = or(_T_785, _T_782) @[Mux.scala 27:72] + node _T_787 = or(_T_786, _T_783) @[Mux.scala 27:72] + node _T_788 = or(_T_787, _T_784) @[Mux.scala 27:72] + wire _T_789 : UInt<32> @[Mux.scala 27:72] + _T_789 <= _T_788 @[Mux.scala 27:72] + io.decode_exu.dec_i0_immed_d <= _T_789 @[dec_decode_ctl.scala 693:32] + wire bitmanip_zbb_legal : UInt<1> + bitmanip_zbb_legal <= UInt<1>("h00") + wire bitmanip_zbs_legal : UInt<1> + bitmanip_zbs_legal <= UInt<1>("h00") + wire bitmanip_zbe_legal : UInt<1> + bitmanip_zbe_legal <= UInt<1>("h00") + wire bitmanip_zbc_legal : UInt<1> + bitmanip_zbc_legal <= UInt<1>("h00") + wire bitmanip_zbp_legal : UInt<1> + bitmanip_zbp_legal <= UInt<1>("h00") + wire bitmanip_zbr_legal : UInt<1> + bitmanip_zbr_legal <= UInt<1>("h00") + wire bitmanip_zbf_legal : UInt<1> + bitmanip_zbf_legal <= UInt<1>("h00") + wire bitmanip_zba_legal : UInt<1> + bitmanip_zba_legal <= UInt<1>("h00") + wire bitmanip_zbb_zbp_legal : UInt<1> + bitmanip_zbb_zbp_legal <= UInt<1>("h00") + wire bitmanip_legal : UInt<1> + bitmanip_legal <= UInt<1>("h00") + bitmanip_zbb_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 711:29] + bitmanip_zbs_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 716:29] + node _T_790 = eq(i0_dp.zbe, UInt<1>("h00")) @[dec_decode_ctl.scala 723:32] + bitmanip_zbe_legal <= _T_790 @[dec_decode_ctl.scala 723:29] + node _T_791 = eq(i0_dp.zbc, UInt<1>("h00")) @[dec_decode_ctl.scala 728:32] + bitmanip_zbc_legal <= _T_791 @[dec_decode_ctl.scala 728:29] + node _T_792 = eq(i0_dp.zbb, UInt<1>("h00")) @[dec_decode_ctl.scala 733:46] + node _T_793 = and(i0_dp.zbp, _T_792) @[dec_decode_ctl.scala 733:44] + node _T_794 = eq(_T_793, UInt<1>("h00")) @[dec_decode_ctl.scala 733:32] + bitmanip_zbp_legal <= _T_794 @[dec_decode_ctl.scala 733:29] + node _T_795 = eq(i0_dp.zbr, UInt<1>("h00")) @[dec_decode_ctl.scala 738:32] + bitmanip_zbr_legal <= _T_795 @[dec_decode_ctl.scala 738:29] + node _T_796 = eq(i0_dp.zbf, UInt<1>("h00")) @[dec_decode_ctl.scala 743:32] + bitmanip_zbf_legal <= _T_796 @[dec_decode_ctl.scala 743:29] + node _T_797 = eq(i0_dp.zba, UInt<1>("h00")) @[dec_decode_ctl.scala 748:32] + bitmanip_zba_legal <= _T_797 @[dec_decode_ctl.scala 748:29] + bitmanip_zbb_zbp_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 751:29] + node _T_798 = and(bitmanip_zbb_legal, bitmanip_zbs_legal) @[dec_decode_ctl.scala 755:41] + node _T_799 = and(_T_798, bitmanip_zbe_legal) @[dec_decode_ctl.scala 755:62] + node _T_800 = and(_T_799, bitmanip_zbc_legal) @[dec_decode_ctl.scala 755:83] + node _T_801 = and(_T_800, bitmanip_zbp_legal) @[dec_decode_ctl.scala 755:104] + node _T_802 = and(_T_801, bitmanip_zbr_legal) @[dec_decode_ctl.scala 755:125] + node _T_803 = and(_T_802, bitmanip_zbf_legal) @[dec_decode_ctl.scala 755:146] + node _T_804 = and(_T_803, bitmanip_zba_legal) @[dec_decode_ctl.scala 755:167] + node _T_805 = and(_T_804, bitmanip_zbb_zbp_legal) @[dec_decode_ctl.scala 755:188] + bitmanip_legal <= _T_805 @[dec_decode_ctl.scala 755:18] + node _T_806 = and(io.dec_aln.dec_i0_decode_d, i0_legal) @[dec_decode_ctl.scala 756:54] + i0_legal_decode_d <= _T_806 @[dec_decode_ctl.scala 756:24] + node _T_807 = and(i0_dp.mul, i0_legal_decode_d) @[dec_decode_ctl.scala 758:44] + i0_d_c.mul <= _T_807 @[dec_decode_ctl.scala 758:29] + node _T_808 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 759:44] + i0_d_c.load <= _T_808 @[dec_decode_ctl.scala 759:29] + node _T_809 = and(i0_dp.alu, i0_legal_decode_d) @[dec_decode_ctl.scala 760:44] + i0_d_c.alu <= _T_809 @[dec_decode_ctl.scala 760:29] + wire _T_810 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 762:70] + _T_810.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 762:70] + _T_810.load <= UInt<1>("h00") @[dec_decode_ctl.scala 762:70] + _T_810.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 762:70] + node _T_811 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 762:92] + reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_810)) @[Reg.scala 27:20] + when _T_811 : @[Reg.scala 28:19] + i0_x_c.alu <= i0_d_c.alu @[Reg.scala 28:23] + i0_x_c.load <= i0_d_c.load @[Reg.scala 28:23] + i0_x_c.mul <= i0_d_c.mul @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wire _T_812 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 763:70] + _T_812.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 763:70] + _T_812.load <= UInt<1>("h00") @[dec_decode_ctl.scala 763:70] + _T_812.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 763:70] + node _T_813 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 763:92] + reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_812)) @[Reg.scala 27:20] + when _T_813 : @[Reg.scala 28:19] + i0_r_c.alu <= i0_x_c.alu @[Reg.scala 28:23] + i0_r_c.load <= i0_x_c.load @[Reg.scala 28:23] + i0_r_c.mul <= i0_x_c.mul @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_814 = bits(i0_pipe_en, 3, 1) @[dec_decode_ctl.scala 764:91] + reg _T_815 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 764:80] + _T_815 <= _T_814 @[dec_decode_ctl.scala 764:80] + node _T_816 = cat(io.dec_aln.dec_i0_decode_d, _T_815) @[Cat.scala 29:58] + i0_pipe_en <= _T_816 @[dec_decode_ctl.scala 764:14] + node _T_817 = bits(i0_pipe_en, 3, 2) @[dec_decode_ctl.scala 766:43] + node _T_818 = orr(_T_817) @[dec_decode_ctl.scala 766:49] + node _T_819 = or(_T_818, io.clk_override) @[dec_decode_ctl.scala 766:53] + i0_x_ctl_en <= _T_819 @[dec_decode_ctl.scala 766:29] + node _T_820 = bits(i0_pipe_en, 2, 1) @[dec_decode_ctl.scala 767:43] + node _T_821 = orr(_T_820) @[dec_decode_ctl.scala 767:49] + node _T_822 = or(_T_821, io.clk_override) @[dec_decode_ctl.scala 767:53] + i0_r_ctl_en <= _T_822 @[dec_decode_ctl.scala 767:29] + node _T_823 = bits(i0_pipe_en, 1, 0) @[dec_decode_ctl.scala 768:43] + node _T_824 = orr(_T_823) @[dec_decode_ctl.scala 768:49] + node _T_825 = or(_T_824, io.clk_override) @[dec_decode_ctl.scala 768:53] + i0_wb_ctl_en <= _T_825 @[dec_decode_ctl.scala 768:29] + node _T_826 = bits(i0_pipe_en, 3, 3) @[dec_decode_ctl.scala 769:44] + node _T_827 = or(_T_826, io.clk_override) @[dec_decode_ctl.scala 769:50] + i0_x_data_en <= _T_827 @[dec_decode_ctl.scala 769:29] + node _T_828 = bits(i0_pipe_en, 2, 2) @[dec_decode_ctl.scala 770:44] + node _T_829 = or(_T_828, io.clk_override) @[dec_decode_ctl.scala 770:50] + i0_r_data_en <= _T_829 @[dec_decode_ctl.scala 770:29] + node _T_830 = bits(i0_pipe_en, 1, 1) @[dec_decode_ctl.scala 771:44] + node _T_831 = or(_T_830, io.clk_override) @[dec_decode_ctl.scala 771:50] + i0_wb_data_en <= _T_831 @[dec_decode_ctl.scala 771:29] + node _T_832 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58] + io.decode_exu.dec_data_en <= _T_832 @[dec_decode_ctl.scala 773:38] + node _T_833 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58] + io.decode_exu.dec_ctl_en <= _T_833 @[dec_decode_ctl.scala 774:38] + d_d.bits.i0rd <= i0r.rd @[dec_decode_ctl.scala 776:34] + node _T_834 = and(i0_rd_en_d, i0_legal_decode_d) @[dec_decode_ctl.scala 777:50] + d_d.bits.i0v <= _T_834 @[dec_decode_ctl.scala 777:34] + d_d.valid <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 778:27] + node _T_835 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 780:50] + d_d.bits.i0load <= _T_835 @[dec_decode_ctl.scala 780:34] + node _T_836 = and(i0_dp.store, i0_legal_decode_d) @[dec_decode_ctl.scala 781:50] + d_d.bits.i0store <= _T_836 @[dec_decode_ctl.scala 781:34] + node _T_837 = and(i0_dp.div, i0_legal_decode_d) @[dec_decode_ctl.scala 782:50] + d_d.bits.i0div <= _T_837 @[dec_decode_ctl.scala 782:34] + node _T_838 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[dec_decode_ctl.scala 784:61] + d_d.bits.csrwen <= _T_838 @[dec_decode_ctl.scala 784:34] + node _T_839 = and(i0_csr_write_only_d, io.dec_aln.dec_i0_decode_d) @[dec_decode_ctl.scala 785:58] + d_d.bits.csrwonly <= _T_839 @[dec_decode_ctl.scala 785:34] + node _T_840 = bits(d_d.bits.csrwen, 0, 0) @[lib.scala 8:44] + node _T_841 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 786:61] + node _T_842 = mux(_T_840, _T_841, UInt<1>("h00")) @[dec_decode_ctl.scala 786:41] + d_d.bits.csrwaddr <= _T_842 @[dec_decode_ctl.scala 786:34] + node _T_843 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 788:63] + wire _T_844 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 630:37] + _T_844.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 630:37] + _T_844.bits.csrwonly <= UInt<1>("h00") @[lib.scala 630:37] + _T_844.bits.csrwen <= UInt<1>("h00") @[lib.scala 630:37] + _T_844.bits.i0v <= UInt<1>("h00") @[lib.scala 630:37] + _T_844.bits.i0div <= UInt<1>("h00") @[lib.scala 630:37] + _T_844.bits.i0store <= UInt<1>("h00") @[lib.scala 630:37] + _T_844.bits.i0load <= UInt<1>("h00") @[lib.scala 630:37] + _T_844.bits.i0rd <= UInt<5>("h00") @[lib.scala 630:37] + _T_844.valid <= UInt<1>("h00") @[lib.scala 630:37] + reg _T_845 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, clock with : (reset => (reset, _T_844)) @[Reg.scala 27:20] + when _T_843 : @[Reg.scala 28:19] + _T_845.bits.csrwaddr <= d_d.bits.csrwaddr @[Reg.scala 28:23] + _T_845.bits.csrwonly <= d_d.bits.csrwonly @[Reg.scala 28:23] + _T_845.bits.csrwen <= d_d.bits.csrwen @[Reg.scala 28:23] + _T_845.bits.i0v <= d_d.bits.i0v @[Reg.scala 28:23] + _T_845.bits.i0div <= d_d.bits.i0div @[Reg.scala 28:23] + _T_845.bits.i0store <= d_d.bits.i0store @[Reg.scala 28:23] + _T_845.bits.i0load <= d_d.bits.i0load @[Reg.scala 28:23] + _T_845.bits.i0rd <= d_d.bits.i0rd @[Reg.scala 28:23] + _T_845.valid <= d_d.valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + x_d.bits.csrwaddr <= _T_845.bits.csrwaddr @[dec_decode_ctl.scala 788:7] + x_d.bits.csrwonly <= _T_845.bits.csrwonly @[dec_decode_ctl.scala 788:7] + x_d.bits.csrwen <= _T_845.bits.csrwen @[dec_decode_ctl.scala 788:7] + x_d.bits.i0v <= _T_845.bits.i0v @[dec_decode_ctl.scala 788:7] + x_d.bits.i0div <= _T_845.bits.i0div @[dec_decode_ctl.scala 788:7] + x_d.bits.i0store <= _T_845.bits.i0store @[dec_decode_ctl.scala 788:7] + x_d.bits.i0load <= _T_845.bits.i0load @[dec_decode_ctl.scala 788:7] + x_d.bits.i0rd <= _T_845.bits.i0rd @[dec_decode_ctl.scala 788:7] + x_d.valid <= _T_845.valid @[dec_decode_ctl.scala 788:7] + wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 789:20] + x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[dec_decode_ctl.scala 790:10] + x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[dec_decode_ctl.scala 790:10] + x_d_in.bits.csrwen <= x_d.bits.csrwen @[dec_decode_ctl.scala 790:10] + x_d_in.bits.i0v <= x_d.bits.i0v @[dec_decode_ctl.scala 790:10] + x_d_in.bits.i0div <= x_d.bits.i0div @[dec_decode_ctl.scala 790:10] + x_d_in.bits.i0store <= x_d.bits.i0store @[dec_decode_ctl.scala 790:10] + x_d_in.bits.i0load <= x_d.bits.i0load @[dec_decode_ctl.scala 790:10] + x_d_in.bits.i0rd <= x_d.bits.i0rd @[dec_decode_ctl.scala 790:10] + x_d_in.valid <= x_d.valid @[dec_decode_ctl.scala 790:10] + node _T_846 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 791:49] + node _T_847 = and(x_d.bits.i0v, _T_846) @[dec_decode_ctl.scala 791:47] + node _T_848 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 791:78] + node _T_849 = and(_T_847, _T_848) @[dec_decode_ctl.scala 791:76] + x_d_in.bits.i0v <= _T_849 @[dec_decode_ctl.scala 791:27] + node _T_850 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 792:35] + node _T_851 = and(x_d.valid, _T_850) @[dec_decode_ctl.scala 792:33] + node _T_852 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 792:64] + node _T_853 = and(_T_851, _T_852) @[dec_decode_ctl.scala 792:62] + x_d_in.valid <= _T_853 @[dec_decode_ctl.scala 792:20] + node _T_854 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 794:65] + wire _T_855 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 630:37] + _T_855.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 630:37] + _T_855.bits.csrwonly <= UInt<1>("h00") @[lib.scala 630:37] + _T_855.bits.csrwen <= UInt<1>("h00") @[lib.scala 630:37] + _T_855.bits.i0v <= UInt<1>("h00") @[lib.scala 630:37] + _T_855.bits.i0div <= UInt<1>("h00") @[lib.scala 630:37] + _T_855.bits.i0store <= UInt<1>("h00") @[lib.scala 630:37] + _T_855.bits.i0load <= UInt<1>("h00") @[lib.scala 630:37] + _T_855.bits.i0rd <= UInt<5>("h00") @[lib.scala 630:37] + _T_855.valid <= UInt<1>("h00") @[lib.scala 630:37] + reg _T_856 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, clock with : (reset => (reset, _T_855)) @[Reg.scala 27:20] + when _T_854 : @[Reg.scala 28:19] + _T_856.bits.csrwaddr <= x_d_in.bits.csrwaddr @[Reg.scala 28:23] + _T_856.bits.csrwonly <= x_d_in.bits.csrwonly @[Reg.scala 28:23] + _T_856.bits.csrwen <= x_d_in.bits.csrwen @[Reg.scala 28:23] + _T_856.bits.i0v <= x_d_in.bits.i0v @[Reg.scala 28:23] + _T_856.bits.i0div <= x_d_in.bits.i0div @[Reg.scala 28:23] + _T_856.bits.i0store <= x_d_in.bits.i0store @[Reg.scala 28:23] + _T_856.bits.i0load <= x_d_in.bits.i0load @[Reg.scala 28:23] + _T_856.bits.i0rd <= x_d_in.bits.i0rd @[Reg.scala 28:23] + _T_856.valid <= x_d_in.valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + r_d.bits.csrwaddr <= _T_856.bits.csrwaddr @[dec_decode_ctl.scala 794:7] + r_d.bits.csrwonly <= _T_856.bits.csrwonly @[dec_decode_ctl.scala 794:7] + r_d.bits.csrwen <= _T_856.bits.csrwen @[dec_decode_ctl.scala 794:7] + r_d.bits.i0v <= _T_856.bits.i0v @[dec_decode_ctl.scala 794:7] + r_d.bits.i0div <= _T_856.bits.i0div @[dec_decode_ctl.scala 794:7] + r_d.bits.i0store <= _T_856.bits.i0store @[dec_decode_ctl.scala 794:7] + r_d.bits.i0load <= _T_856.bits.i0load @[dec_decode_ctl.scala 794:7] + r_d.bits.i0rd <= _T_856.bits.i0rd @[dec_decode_ctl.scala 794:7] + r_d.valid <= _T_856.valid @[dec_decode_ctl.scala 794:7] + r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 795:10] + r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[dec_decode_ctl.scala 795:10] + r_d_in.bits.csrwen <= r_d.bits.csrwen @[dec_decode_ctl.scala 795:10] + r_d_in.bits.i0v <= r_d.bits.i0v @[dec_decode_ctl.scala 795:10] + r_d_in.bits.i0div <= r_d.bits.i0div @[dec_decode_ctl.scala 795:10] + r_d_in.bits.i0store <= r_d.bits.i0store @[dec_decode_ctl.scala 795:10] + r_d_in.bits.i0load <= r_d.bits.i0load @[dec_decode_ctl.scala 795:10] + r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 795:10] + r_d_in.valid <= r_d.valid @[dec_decode_ctl.scala 795:10] + r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 796:22] + node _T_857 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 798:51] + node _T_858 = and(r_d.bits.i0v, _T_857) @[dec_decode_ctl.scala 798:49] + r_d_in.bits.i0v <= _T_858 @[dec_decode_ctl.scala 798:27] + node _T_859 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 799:37] + node _T_860 = and(r_d.valid, _T_859) @[dec_decode_ctl.scala 799:35] + r_d_in.valid <= _T_860 @[dec_decode_ctl.scala 799:20] + node _T_861 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 800:51] + node _T_862 = and(r_d.bits.i0load, _T_861) @[dec_decode_ctl.scala 800:49] + r_d_in.bits.i0load <= _T_862 @[dec_decode_ctl.scala 800:27] + node _T_863 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 801:51] + node _T_864 = and(r_d.bits.i0store, _T_863) @[dec_decode_ctl.scala 801:49] + r_d_in.bits.i0store <= _T_864 @[dec_decode_ctl.scala 801:27] + node _T_865 = bits(i0_wb_ctl_en, 0, 0) @[dec_decode_ctl.scala 803:66] + wire _T_866 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 630:37] + _T_866.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 630:37] + _T_866.bits.csrwonly <= UInt<1>("h00") @[lib.scala 630:37] + _T_866.bits.csrwen <= UInt<1>("h00") @[lib.scala 630:37] + _T_866.bits.i0v <= UInt<1>("h00") @[lib.scala 630:37] + _T_866.bits.i0div <= UInt<1>("h00") @[lib.scala 630:37] + _T_866.bits.i0store <= UInt<1>("h00") @[lib.scala 630:37] + _T_866.bits.i0load <= UInt<1>("h00") @[lib.scala 630:37] + _T_866.bits.i0rd <= UInt<5>("h00") @[lib.scala 630:37] + _T_866.valid <= UInt<1>("h00") @[lib.scala 630:37] + reg _T_867 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, clock with : (reset => (reset, _T_866)) @[Reg.scala 27:20] + when _T_865 : @[Reg.scala 28:19] + _T_867.bits.csrwaddr <= r_d_in.bits.csrwaddr @[Reg.scala 28:23] + _T_867.bits.csrwonly <= r_d_in.bits.csrwonly @[Reg.scala 28:23] + _T_867.bits.csrwen <= r_d_in.bits.csrwen @[Reg.scala 28:23] + _T_867.bits.i0v <= r_d_in.bits.i0v @[Reg.scala 28:23] + _T_867.bits.i0div <= r_d_in.bits.i0div @[Reg.scala 28:23] + _T_867.bits.i0store <= r_d_in.bits.i0store @[Reg.scala 28:23] + _T_867.bits.i0load <= r_d_in.bits.i0load @[Reg.scala 28:23] + _T_867.bits.i0rd <= r_d_in.bits.i0rd @[Reg.scala 28:23] + _T_867.valid <= r_d_in.valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wbd.bits.csrwaddr <= _T_867.bits.csrwaddr @[dec_decode_ctl.scala 803:7] + wbd.bits.csrwonly <= _T_867.bits.csrwonly @[dec_decode_ctl.scala 803:7] + wbd.bits.csrwen <= _T_867.bits.csrwen @[dec_decode_ctl.scala 803:7] + wbd.bits.i0v <= _T_867.bits.i0v @[dec_decode_ctl.scala 803:7] + wbd.bits.i0div <= _T_867.bits.i0div @[dec_decode_ctl.scala 803:7] + wbd.bits.i0store <= _T_867.bits.i0store @[dec_decode_ctl.scala 803:7] + wbd.bits.i0load <= _T_867.bits.i0load @[dec_decode_ctl.scala 803:7] + wbd.bits.i0rd <= _T_867.bits.i0rd @[dec_decode_ctl.scala 803:7] + wbd.valid <= _T_867.valid @[dec_decode_ctl.scala 803:7] + io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[dec_decode_ctl.scala 805:27] + node _T_868 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 806:47] + node _T_869 = and(r_d_in.bits.i0v, _T_868) @[dec_decode_ctl.scala 806:45] + i0_wen_r <= _T_869 @[dec_decode_ctl.scala 806:25] + node _T_870 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[dec_decode_ctl.scala 807:49] + node _T_871 = and(i0_wen_r, _T_870) @[dec_decode_ctl.scala 807:47] + node _T_872 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[dec_decode_ctl.scala 807:70] + node _T_873 = and(_T_871, _T_872) @[dec_decode_ctl.scala 807:68] + io.dec_i0_wen_r <= _T_873 @[dec_decode_ctl.scala 807:32] + io.dec_i0_wdata_r <= i0_result_corr_r @[dec_decode_ctl.scala 808:26] + node _T_874 = or(x_d.bits.i0v, x_d.bits.csrwen) @[dec_decode_ctl.scala 811:74] + node _T_875 = or(_T_874, debug_valid_x) @[dec_decode_ctl.scala 811:92] + node _T_876 = and(i0_r_data_en, _T_875) @[dec_decode_ctl.scala 811:58] + node _T_877 = eq(_T_876, UInt<1>("h01")) @[dec_decode_ctl.scala 811:110] + inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 404:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_4.io.en <= _T_877 @[lib.scala 407:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg i0_result_r_raw : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_877 : @[Reg.scala 28:19] + i0_result_r_raw <= i0_result_x @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_878 = and(x_d.bits.i0v, x_d.bits.i0load) @[dec_decode_ctl.scala 817:47] + node _T_879 = bits(_T_878, 0, 0) @[dec_decode_ctl.scala 817:66] + node _T_880 = mux(_T_879, io.lsu_result_m, io.decode_exu.exu_i0_result_x) @[dec_decode_ctl.scala 817:32] + i0_result_x <= _T_880 @[dec_decode_ctl.scala 817:26] + i0_result_r <= i0_result_r_raw @[dec_decode_ctl.scala 818:26] + node _T_881 = and(r_d.bits.i0v, r_d.bits.i0load) @[dec_decode_ctl.scala 822:42] + node _T_882 = bits(_T_881, 0, 0) @[dec_decode_ctl.scala 822:61] + node _T_883 = mux(_T_882, io.lsu_result_corr_r, i0_result_r_raw) @[dec_decode_ctl.scala 822:27] + i0_result_corr_r <= _T_883 @[dec_decode_ctl.scala 822:21] + node _T_884 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 823:73] + node _T_885 = and(io.decode_exu.i0_ap.predict_nt, _T_884) @[dec_decode_ctl.scala 823:71] + node _T_886 = bits(_T_885, 0, 0) @[dec_decode_ctl.scala 823:85] + wire _T_887 : UInt<1>[10] @[lib.scala 12:48] + _T_887[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_887[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_887[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_887[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_887[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_887[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_887[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_887[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_887[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_887[9] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_888 = cat(_T_887[0], _T_887[1]) @[Cat.scala 29:58] + node _T_889 = cat(_T_888, _T_887[2]) @[Cat.scala 29:58] + node _T_890 = cat(_T_889, _T_887[3]) @[Cat.scala 29:58] + node _T_891 = cat(_T_890, _T_887[4]) @[Cat.scala 29:58] + node _T_892 = cat(_T_891, _T_887[5]) @[Cat.scala 29:58] + node _T_893 = cat(_T_892, _T_887[6]) @[Cat.scala 29:58] + node _T_894 = cat(_T_893, _T_887[7]) @[Cat.scala 29:58] + node _T_895 = cat(_T_894, _T_887[8]) @[Cat.scala 29:58] + node _T_896 = cat(_T_895, _T_887[9]) @[Cat.scala 29:58] + node _T_897 = cat(_T_896, io.dec_i0_pc4_d) @[Cat.scala 29:58] + node _T_898 = cat(_T_897, i0_ap_pc2) @[Cat.scala 29:58] + node _T_899 = mux(_T_886, i0_br_offset, _T_898) @[dec_decode_ctl.scala 823:38] + io.dec_alu.dec_i0_br_immed_d <= _T_899 @[dec_decode_ctl.scala 823:32] + wire last_br_immed_d : UInt<12> + last_br_immed_d <= UInt<1>("h00") + node _T_900 = bits(io.decode_exu.i0_ap.predict_nt, 0, 0) @[dec_decode_ctl.scala 825:59] + wire _T_901 : UInt<1>[10] @[lib.scala 12:48] + _T_901[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_901[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_901[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_901[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_901[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_901[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_901[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_901[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_901[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_901[9] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_902 = cat(_T_901[0], _T_901[1]) @[Cat.scala 29:58] + node _T_903 = cat(_T_902, _T_901[2]) @[Cat.scala 29:58] + node _T_904 = cat(_T_903, _T_901[3]) @[Cat.scala 29:58] + node _T_905 = cat(_T_904, _T_901[4]) @[Cat.scala 29:58] + node _T_906 = cat(_T_905, _T_901[5]) @[Cat.scala 29:58] + node _T_907 = cat(_T_906, _T_901[6]) @[Cat.scala 29:58] + node _T_908 = cat(_T_907, _T_901[7]) @[Cat.scala 29:58] + node _T_909 = cat(_T_908, _T_901[8]) @[Cat.scala 29:58] + node _T_910 = cat(_T_909, _T_901[9]) @[Cat.scala 29:58] + node _T_911 = cat(_T_910, io.dec_i0_pc4_d) @[Cat.scala 29:58] + node _T_912 = cat(_T_911, i0_ap_pc2) @[Cat.scala 29:58] + node _T_913 = mux(_T_900, _T_912, i0_br_offset) @[dec_decode_ctl.scala 825:25] + last_br_immed_d <= _T_913 @[dec_decode_ctl.scala 825:19] + wire last_br_immed_x : UInt<12> + last_br_immed_x <= UInt<1>("h00") + node _T_914 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 827:58] + inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 404:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_5.io.en <= _T_914 @[lib.scala 407:17] + rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_915 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_914 : @[Reg.scala 28:19] + _T_915 <= last_br_immed_d @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + last_br_immed_x <= _T_915 @[dec_decode_ctl.scala 827:19] + node _T_916 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 831:45] + node _T_917 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 831:76] + node div_e1_to_r = or(_T_916, _T_917) @[dec_decode_ctl.scala 831:58] + node _T_918 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 833:48] + node _T_919 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 833:77] + node _T_920 = and(_T_918, _T_919) @[dec_decode_ctl.scala 833:60] + node _T_921 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 834:21] + node _T_922 = and(_T_921, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 834:33] + node _T_923 = or(_T_920, _T_922) @[dec_decode_ctl.scala 833:94] + node _T_924 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 835:21] + node _T_925 = and(_T_924, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 835:33] + node _T_926 = and(_T_925, io.dec_tlu_i0_kill_writeb_r) @[dec_decode_ctl.scala 835:60] + node div_flush = or(_T_923, _T_926) @[dec_decode_ctl.scala 834:62] + node _T_927 = and(io.dec_div_active, div_flush) @[dec_decode_ctl.scala 839:51] + node _T_928 = eq(div_e1_to_r, UInt<1>("h00")) @[dec_decode_ctl.scala 840:26] + node _T_929 = and(io.dec_div_active, _T_928) @[dec_decode_ctl.scala 840:24] + node _T_930 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[dec_decode_ctl.scala 840:56] + node _T_931 = and(_T_929, _T_930) @[dec_decode_ctl.scala 840:39] + node _T_932 = and(_T_931, i0_wen_r) @[dec_decode_ctl.scala 840:77] + node nonblock_div_cancel = or(_T_927, _T_932) @[dec_decode_ctl.scala 839:65] + node _T_933 = bits(nonblock_div_cancel, 0, 0) @[dec_decode_ctl.scala 842:61] + io.dec_div.dec_div_cancel <= _T_933 @[dec_decode_ctl.scala 842:37] + node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 843:55] + node _T_934 = eq(io.exu_div_wren, UInt<1>("h00")) @[dec_decode_ctl.scala 845:59] + node _T_935 = and(io.dec_div_active, _T_934) @[dec_decode_ctl.scala 845:57] + node _T_936 = eq(nonblock_div_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 845:78] + node _T_937 = and(_T_935, _T_936) @[dec_decode_ctl.scala 845:76] + node _T_938 = or(i0_div_decode_d, _T_937) @[dec_decode_ctl.scala 845:36] + div_active_in <= _T_938 @[dec_decode_ctl.scala 845:17] + node _T_939 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_div_active) @[dec_decode_ctl.scala 850:60] + node _T_940 = eq(io.div_waddr_wb, i0r.rs1) @[dec_decode_ctl.scala 850:99] + node _T_941 = and(_T_939, _T_940) @[dec_decode_ctl.scala 850:80] + node _T_942 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_div_active) @[dec_decode_ctl.scala 851:36] + node _T_943 = eq(io.div_waddr_wb, i0r.rs2) @[dec_decode_ctl.scala 851:75] + node _T_944 = and(_T_942, _T_943) @[dec_decode_ctl.scala 851:56] + node _T_945 = or(_T_941, _T_944) @[dec_decode_ctl.scala 850:113] + i0_nonblock_div_stall <= _T_945 @[dec_decode_ctl.scala 850:26] + node trace_enable = not(io.dec_tlu_trace_disable) @[dec_decode_ctl.scala 858:22] + node _T_946 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 860:58] + inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 404:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_6.io.en <= _T_946 @[lib.scala 407:17] + rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_947 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_946 : @[Reg.scala 28:19] + _T_947 <= i0r.rd @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.div_waddr_wb <= _T_947 @[dec_decode_ctl.scala 860:19] + node _T_948 = and(i0_x_data_en, trace_enable) @[dec_decode_ctl.scala 862:50] + node _T_949 = bits(_T_948, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 404:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_7.io.en <= _T_949 @[lib.scala 407:17] + rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg i0_inst_x : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_949 : @[Reg.scala 28:19] + i0_inst_x <= i0_inst_d @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_950 = and(i0_r_data_en, trace_enable) @[dec_decode_ctl.scala 863:50] + node _T_951 = bits(_T_950, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 404:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_8.io.en <= _T_951 @[lib.scala 407:17] + rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg i0_inst_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_951 : @[Reg.scala 28:19] + i0_inst_r <= i0_inst_x @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_952 = and(i0_wb_data_en, trace_enable) @[dec_decode_ctl.scala 865:51] + node _T_953 = bits(_T_952, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 404:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_9.io.en <= _T_953 @[lib.scala 407:17] + rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg i0_inst_wb : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_953 : @[Reg.scala 28:19] + i0_inst_wb <= i0_inst_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_954 = and(i0_wb_data_en, trace_enable) @[dec_decode_ctl.scala 866:54] + node _T_955 = bits(_T_954, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 404:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_10.io.en <= _T_955 @[lib.scala 407:17] + rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg i0_pc_wb : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_955 : @[Reg.scala 28:19] + i0_pc_wb <= io.dec_tlu_i0_pc_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.dec_i0_inst_wb <= i0_inst_wb @[dec_decode_ctl.scala 868:21] + io.dec_i0_pc_wb <= i0_pc_wb @[dec_decode_ctl.scala 869:19] + node _T_956 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 870:67] + wire _T_957 : UInt<31> @[lib.scala 648:38] + _T_957 <= UInt<1>("h00") @[lib.scala 648:38] + reg dec_i0_pc_r : UInt, clock with : (reset => (reset, _T_957)) @[Reg.scala 27:20] + when _T_956 : @[Reg.scala 28:19] + dec_i0_pc_r <= io.dec_alu.exu_i0_pc_x @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[dec_decode_ctl.scala 872:27] + node _T_958 = cat(io.dec_alu.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_959 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_960 = bits(_T_958, 12, 1) @[lib.scala 68:24] + node _T_961 = bits(_T_959, 12, 1) @[lib.scala 68:40] + node _T_962 = add(_T_960, _T_961) @[lib.scala 68:31] + node _T_963 = bits(_T_958, 31, 13) @[lib.scala 69:20] + node _T_964 = add(_T_963, UInt<1>("h01")) @[lib.scala 69:27] + node _T_965 = tail(_T_964, 1) @[lib.scala 69:27] + node _T_966 = bits(_T_958, 31, 13) @[lib.scala 70:20] + node _T_967 = sub(_T_966, UInt<1>("h01")) @[lib.scala 70:27] + node _T_968 = tail(_T_967, 1) @[lib.scala 70:27] + node _T_969 = bits(_T_959, 12, 12) @[lib.scala 71:22] + node _T_970 = bits(_T_962, 12, 12) @[lib.scala 72:39] + node _T_971 = eq(_T_970, UInt<1>("h00")) @[lib.scala 72:28] + node _T_972 = xor(_T_969, _T_971) @[lib.scala 72:26] + node _T_973 = bits(_T_972, 0, 0) @[lib.scala 72:64] + node _T_974 = bits(_T_958, 31, 13) @[lib.scala 72:76] + node _T_975 = eq(_T_969, UInt<1>("h00")) @[lib.scala 73:20] + node _T_976 = bits(_T_962, 12, 12) @[lib.scala 73:39] + node _T_977 = and(_T_975, _T_976) @[lib.scala 73:26] + node _T_978 = bits(_T_977, 0, 0) @[lib.scala 73:64] + node _T_979 = bits(_T_962, 12, 12) @[lib.scala 74:39] + node _T_980 = eq(_T_979, UInt<1>("h00")) @[lib.scala 74:28] + node _T_981 = and(_T_969, _T_980) @[lib.scala 74:26] + node _T_982 = bits(_T_981, 0, 0) @[lib.scala 74:64] + node _T_983 = mux(_T_973, _T_974, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_984 = mux(_T_978, _T_965, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_985 = mux(_T_982, _T_968, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_986 = or(_T_983, _T_984) @[Mux.scala 27:72] + node _T_987 = or(_T_986, _T_985) @[Mux.scala 27:72] + wire _T_988 : UInt<19> @[Mux.scala 27:72] + _T_988 <= _T_987 @[Mux.scala 27:72] + node _T_989 = bits(_T_962, 11, 0) @[lib.scala 74:94] + node _T_990 = cat(_T_988, _T_989) @[Cat.scala 29:58] + node temp_pred_correct_npc_x = cat(_T_990, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_991 = bits(temp_pred_correct_npc_x, 31, 1) @[dec_decode_ctl.scala 877:62] + io.decode_exu.pred_correct_npc_x <= _T_991 @[dec_decode_ctl.scala 877:36] + node _T_992 = and(io.decode_exu.dec_i0_rs1_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 881:59] + node _T_993 = eq(x_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 881:91] + node i0_rs1_depend_i0_x = and(_T_992, _T_993) @[dec_decode_ctl.scala 881:74] + node _T_994 = and(io.decode_exu.dec_i0_rs1_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 882:59] + node _T_995 = eq(r_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 882:91] + node i0_rs1_depend_i0_r = and(_T_994, _T_995) @[dec_decode_ctl.scala 882:74] + node _T_996 = and(io.decode_exu.dec_i0_rs2_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 884:59] + node _T_997 = eq(x_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 884:91] + node i0_rs2_depend_i0_x = and(_T_996, _T_997) @[dec_decode_ctl.scala 884:74] + node _T_998 = and(io.decode_exu.dec_i0_rs2_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 885:59] + node _T_999 = eq(r_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 885:91] + node i0_rs2_depend_i0_r = and(_T_998, _T_999) @[dec_decode_ctl.scala 885:74] + node _T_1000 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 887:44] + node _T_1001 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 887:81] + wire _T_1002 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 887:109] + _T_1002.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 887:109] + _T_1002.load <= UInt<1>("h00") @[dec_decode_ctl.scala 887:109] + _T_1002.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 887:109] + node _T_1003 = mux(_T_1001, i0_r_c, _T_1002) @[dec_decode_ctl.scala 887:61] + node _T_1004 = mux(_T_1000, i0_x_c, _T_1003) @[dec_decode_ctl.scala 887:24] + i0_rs1_class_d.alu <= _T_1004.alu @[dec_decode_ctl.scala 887:18] + i0_rs1_class_d.load <= _T_1004.load @[dec_decode_ctl.scala 887:18] + i0_rs1_class_d.mul <= _T_1004.mul @[dec_decode_ctl.scala 887:18] + node _T_1005 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 888:44] + node _T_1006 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 888:83] + node _T_1007 = mux(_T_1006, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 888:63] + node _T_1008 = mux(_T_1005, UInt<2>("h01"), _T_1007) @[dec_decode_ctl.scala 888:24] + i0_rs1_depth_d <= _T_1008 @[dec_decode_ctl.scala 888:18] + node _T_1009 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 889:44] + node _T_1010 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 889:81] + wire _T_1011 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 889:109] + _T_1011.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109] + _T_1011.load <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109] + _T_1011.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109] + node _T_1012 = mux(_T_1010, i0_r_c, _T_1011) @[dec_decode_ctl.scala 889:61] + node _T_1013 = mux(_T_1009, i0_x_c, _T_1012) @[dec_decode_ctl.scala 889:24] + i0_rs2_class_d.alu <= _T_1013.alu @[dec_decode_ctl.scala 889:18] + i0_rs2_class_d.load <= _T_1013.load @[dec_decode_ctl.scala 889:18] + i0_rs2_class_d.mul <= _T_1013.mul @[dec_decode_ctl.scala 889:18] + node _T_1014 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 890:44] + node _T_1015 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 890:83] + node _T_1016 = mux(_T_1015, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 890:63] + node _T_1017 = mux(_T_1014, UInt<2>("h01"), _T_1016) @[dec_decode_ctl.scala 890:24] + i0_rs2_depth_d <= _T_1017 @[dec_decode_ctl.scala 890:18] + i0_load_block_d <= UInt<1>("h00") @[dec_decode_ctl.scala 900:21] + node _T_1018 = or(i0_dp.load, i0_dp.store) @[dec_decode_ctl.scala 901:43] + node _T_1019 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 901:74] + node _T_1020 = and(_T_1018, _T_1019) @[dec_decode_ctl.scala 901:58] + node _T_1021 = and(_T_1020, i0_rs1_class_d.load) @[dec_decode_ctl.scala 901:78] + load_ldst_bypass_d <= _T_1021 @[dec_decode_ctl.scala 901:27] + node _T_1022 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 902:59] + node _T_1023 = and(i0_dp.store, _T_1022) @[dec_decode_ctl.scala 902:43] + node _T_1024 = and(_T_1023, i0_rs2_class_d.load) @[dec_decode_ctl.scala 902:63] + store_data_bypass_d <= _T_1024 @[dec_decode_ctl.scala 902:25] + store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 903:25] + node _T_1025 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 907:73] + node _T_1026 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[dec_decode_ctl.scala 907:130] + node i0_rs1_nonblock_load_bypass_en_d = and(_T_1025, _T_1026) @[dec_decode_ctl.scala 907:100] + node _T_1027 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 909:73] + node _T_1028 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[dec_decode_ctl.scala 909:130] + node i0_rs2_nonblock_load_bypass_en_d = and(_T_1027, _T_1028) @[dec_decode_ctl.scala 909:100] + node _T_1029 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 912:41] + node _T_1030 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 912:66] + node _T_1031 = and(_T_1029, _T_1030) @[dec_decode_ctl.scala 912:45] + node _T_1032 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 912:104] + node _T_1033 = and(_T_1032, i0_rs1_class_d.load) @[dec_decode_ctl.scala 912:108] + node _T_1034 = bits(i0_rs1_depth_d, 1, 1) @[dec_decode_ctl.scala 912:149] + node _T_1035 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 912:175] + node _T_1036 = or(_T_1035, i0_rs1_class_d.load) @[dec_decode_ctl.scala 912:196] + node _T_1037 = and(_T_1034, _T_1036) @[dec_decode_ctl.scala 912:153] + node _T_1038 = cat(_T_1031, _T_1033) @[Cat.scala 29:58] + node _T_1039 = cat(_T_1038, _T_1037) @[Cat.scala 29:58] + i0_rs1bypass <= _T_1039 @[dec_decode_ctl.scala 912:18] + node _T_1040 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 914:41] + node _T_1041 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 914:67] + node _T_1042 = and(_T_1040, _T_1041) @[dec_decode_ctl.scala 914:45] + node _T_1043 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 914:105] + node _T_1044 = and(_T_1043, i0_rs2_class_d.load) @[dec_decode_ctl.scala 914:109] + node _T_1045 = bits(i0_rs2_depth_d, 1, 1) @[dec_decode_ctl.scala 914:149] + node _T_1046 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 914:175] + node _T_1047 = or(_T_1046, i0_rs2_class_d.load) @[dec_decode_ctl.scala 914:196] + node _T_1048 = and(_T_1045, _T_1047) @[dec_decode_ctl.scala 914:153] + node _T_1049 = cat(_T_1042, _T_1044) @[Cat.scala 29:58] + node _T_1050 = cat(_T_1049, _T_1048) @[Cat.scala 29:58] + i0_rs2bypass <= _T_1050 @[dec_decode_ctl.scala 914:18] + node _T_1051 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 916:66] + node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[dec_decode_ctl.scala 916:53] + node _T_1053 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 916:85] + node _T_1054 = eq(_T_1053, UInt<1>("h00")) @[dec_decode_ctl.scala 916:72] + node _T_1055 = and(_T_1052, _T_1054) @[dec_decode_ctl.scala 916:70] + node _T_1056 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 916:104] + node _T_1057 = eq(_T_1056, UInt<1>("h00")) @[dec_decode_ctl.scala 916:91] + node _T_1058 = and(_T_1055, _T_1057) @[dec_decode_ctl.scala 916:89] + node _T_1059 = and(_T_1058, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 916:108] + node _T_1060 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 916:155] + node _T_1061 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 916:171] + node _T_1062 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 916:187] + node _T_1063 = cat(_T_1061, _T_1062) @[Cat.scala 29:58] + node _T_1064 = cat(_T_1059, _T_1060) @[Cat.scala 29:58] + node _T_1065 = cat(_T_1064, _T_1063) @[Cat.scala 29:58] + io.decode_exu.dec_i0_rs1_bypass_en_d <= _T_1065 @[dec_decode_ctl.scala 916:45] + node _T_1066 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 917:66] + node _T_1067 = eq(_T_1066, UInt<1>("h00")) @[dec_decode_ctl.scala 917:53] + node _T_1068 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 917:85] + node _T_1069 = eq(_T_1068, UInt<1>("h00")) @[dec_decode_ctl.scala 917:72] + node _T_1070 = and(_T_1067, _T_1069) @[dec_decode_ctl.scala 917:70] + node _T_1071 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 917:104] + node _T_1072 = eq(_T_1071, UInt<1>("h00")) @[dec_decode_ctl.scala 917:91] + node _T_1073 = and(_T_1070, _T_1072) @[dec_decode_ctl.scala 917:89] + node _T_1074 = and(_T_1073, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 917:108] + node _T_1075 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 917:155] + node _T_1076 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 917:171] + node _T_1077 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 917:187] + node _T_1078 = cat(_T_1076, _T_1077) @[Cat.scala 29:58] + node _T_1079 = cat(_T_1074, _T_1075) @[Cat.scala 29:58] + node _T_1080 = cat(_T_1079, _T_1078) @[Cat.scala 29:58] + io.decode_exu.dec_i0_rs2_bypass_en_d <= _T_1080 @[dec_decode_ctl.scala 917:45] + io.decode_exu.dec_i0_result_r <= i0_result_r @[dec_decode_ctl.scala 919:41] + node _T_1081 = or(i0_dp_raw.load, i0_dp_raw.store) @[dec_decode_ctl.scala 921:68] + node _T_1082 = and(io.dec_ib0_valid_d, _T_1081) @[dec_decode_ctl.scala 921:50] + node _T_1083 = eq(io.dctl_dma.dma_dccm_stall_any, UInt<1>("h00")) @[dec_decode_ctl.scala 921:89] + node _T_1084 = and(_T_1082, _T_1083) @[dec_decode_ctl.scala 921:87] + node _T_1085 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 921:123] + node _T_1086 = and(_T_1084, _T_1085) @[dec_decode_ctl.scala 921:121] + node _T_1087 = or(_T_1086, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 921:140] + io.dec_lsu_valid_raw_d <= _T_1087 @[dec_decode_ctl.scala 921:26] + node _T_1088 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 923:6] + node _T_1089 = and(_T_1088, i0_dp.lsu) @[dec_decode_ctl.scala 923:38] + node _T_1090 = and(_T_1089, i0_dp.load) @[dec_decode_ctl.scala 923:50] + node _T_1091 = bits(_T_1090, 0, 0) @[dec_decode_ctl.scala 923:64] + node _T_1092 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 923:81] + node _T_1093 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 924:6] + node _T_1094 = and(_T_1093, i0_dp.lsu) @[dec_decode_ctl.scala 924:38] + node _T_1095 = and(_T_1094, i0_dp.store) @[dec_decode_ctl.scala 924:50] + node _T_1096 = bits(_T_1095, 0, 0) @[dec_decode_ctl.scala 924:65] + node _T_1097 = bits(io.dec_i0_instr_d, 31, 25) @[dec_decode_ctl.scala 924:85] + node _T_1098 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 924:95] + node _T_1099 = cat(_T_1097, _T_1098) @[Cat.scala 29:58] + node _T_1100 = mux(_T_1091, _T_1092, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1101 = mux(_T_1096, _T_1099, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1102 = or(_T_1100, _T_1101) @[Mux.scala 27:72] + wire _T_1103 : UInt<12> @[Mux.scala 27:72] + _T_1103 <= _T_1102 @[Mux.scala 27:72] + io.dec_lsu_offset_d <= _T_1103 @[dec_decode_ctl.scala 922:23] + diff --git a/dec_decode_ctl.v b/dec_decode_ctl.v new file mode 100644 index 00000000..13c6c223 --- /dev/null +++ b/dec_decode_ctl.v @@ -0,0 +1,4365 @@ +module dec_dec_ctl( + input [31:0] io_ins, + output io_out_clz, + output io_out_ctz, + output io_out_pcnt, + output io_out_sext_b, + output io_out_sext_h, + output io_out_slo, + output io_out_sro, + output io_out_min, + output io_out_max, + output io_out_pack, + output io_out_packu, + output io_out_packh, + output io_out_rol, + output io_out_ror, + output io_out_grev, + output io_out_gorc, + output io_out_zbb, + output io_out_sbset, + output io_out_sbclr, + output io_out_sbinv, + output io_out_sbext, + output io_out_zbs, + output io_out_bext, + output io_out_bdep, + output io_out_zbe, + output io_out_clmul, + output io_out_clmulh, + output io_out_clmulr, + output io_out_zbc, + output io_out_shfl, + output io_out_unshfl, + output io_out_zbp, + output io_out_crc32_b, + output io_out_crc32_h, + output io_out_crc32_w, + output io_out_crc32c_b, + output io_out_crc32c_h, + output io_out_crc32c_w, + output io_out_zbr, + output io_out_bfp, + output io_out_zbf, + output io_out_sh1add, + output io_out_sh2add, + output io_out_sh3add, + output io_out_zba, + output io_out_alu, + output io_out_rs1, + output io_out_rs2, + output io_out_imm12, + output io_out_rd, + output io_out_shimm5, + output io_out_imm20, + output io_out_pc, + output io_out_load, + output io_out_store, + output io_out_lsu, + output io_out_add, + output io_out_sub, + output io_out_land, + output io_out_lor, + output io_out_lxor, + output io_out_sll, + output io_out_sra, + output io_out_srl, + output io_out_slt, + output io_out_unsign, + output io_out_condbr, + output io_out_beq, + output io_out_bne, + output io_out_bge, + output io_out_blt, + output io_out_jal, + output io_out_by, + output io_out_half, + output io_out_word, + output io_out_csr_read, + output io_out_csr_clr, + output io_out_csr_set, + output io_out_csr_write, + output io_out_csr_imm, + output io_out_presync, + output io_out_postsync, + output io_out_ebreak, + output io_out_ecall, + output io_out_mret, + output io_out_mul, + output io_out_rs1_sign, + output io_out_rs2_sign, + output io_out_low, + output io_out_div, + output io_out_rem, + output io_out_fence, + output io_out_fence_i, + output io_out_pm_alu, + output io_out_legal +); + wire _T_4 = ~io_ins[22]; // @[dec_dec_ctl.scala 15:46] + wire _T_6 = ~io_ins[21]; // @[dec_dec_ctl.scala 15:46] + wire _T_8 = ~io_ins[20]; // @[dec_dec_ctl.scala 15:46] + wire _T_11 = ~io_ins[5]; // @[dec_dec_ctl.scala 15:46] + wire _T_13 = io_ins[30] & io_ins[24]; // @[dec_dec_ctl.scala 17:17] + wire _T_14 = _T_13 & io_ins[23]; // @[dec_dec_ctl.scala 17:17] + wire _T_15 = _T_14 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_16 = _T_15 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_17 = _T_16 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_18 = _T_17 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_19 = _T_18 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_20 = _T_19 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_23 = ~io_ins[27]; // @[dec_dec_ctl.scala 15:46] + wire _T_25 = ~io_ins[24]; // @[dec_dec_ctl.scala 15:46] + wire _T_27 = io_ins[29] & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_28 = _T_27 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_29 = _T_28 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_30 = _T_20 | _T_29; // @[dec_dec_ctl.scala 20:62] + wire _T_32 = ~io_ins[25]; // @[dec_dec_ctl.scala 15:46] + wire _T_34 = ~io_ins[13]; // @[dec_dec_ctl.scala 15:46] + wire _T_36 = ~io_ins[12]; // @[dec_dec_ctl.scala 15:46] + wire _T_38 = _T_32 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_39 = _T_38 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_40 = _T_39 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_41 = _T_30 | _T_40; // @[dec_dec_ctl.scala 20:92] + wire _T_43 = ~io_ins[30]; // @[dec_dec_ctl.scala 15:46] + wire _T_48 = _T_43 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_49 = _T_48 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_50 = _T_49 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_51 = _T_41 | _T_50; // @[dec_dec_ctl.scala 21:34] + wire _T_56 = io_ins[27] & io_ins[25]; // @[dec_dec_ctl.scala 17:17] + wire _T_57 = _T_56 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_58 = _T_57 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_59 = _T_51 | _T_58; // @[dec_dec_ctl.scala 21:66] + wire _T_63 = ~io_ins[14]; // @[dec_dec_ctl.scala 15:46] + wire _T_65 = io_ins[29] & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_66 = _T_65 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_67 = _T_66 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_68 = _T_59 | _T_67; // @[dec_dec_ctl.scala 21:94] + wire _T_74 = io_ins[29] & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_75 = _T_74 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_76 = _T_75 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_77 = _T_68 | _T_76; // @[dec_dec_ctl.scala 22:32] + wire _T_84 = _T_23 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_85 = _T_84 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_86 = _T_85 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_87 = _T_77 | _T_86; // @[dec_dec_ctl.scala 22:60] + wire _T_90 = ~io_ins[29]; // @[dec_dec_ctl.scala 15:46] + wire _T_94 = io_ins[30] & _T_90; // @[dec_dec_ctl.scala 17:17] + wire _T_95 = _T_94 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_96 = _T_95 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_97 = _T_87 | _T_96; // @[dec_dec_ctl.scala 22:90] + wire _T_105 = _T_43 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_106 = _T_105 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_107 = _T_106 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_108 = _T_97 | _T_107; // @[dec_dec_ctl.scala 23:33] + wire _T_113 = io_ins[13] & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_114 = _T_113 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_115 = _T_108 | _T_114; // @[dec_dec_ctl.scala 23:64] + wire _T_121 = _T_36 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_122 = _T_121 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_123 = _T_115 | _T_122; // @[dec_dec_ctl.scala 23:89] + wire _T_125 = _T_123 | io_ins[2]; // @[dec_dec_ctl.scala 24:29] + wire _T_127 = _T_125 | io_ins[6]; // @[dec_dec_ctl.scala 24:48] + wire _T_139 = _T_14 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_140 = _T_139 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_141 = _T_140 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_142 = _T_141 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_143 = _T_142 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_144 = _T_127 | _T_143; // @[dec_dec_ctl.scala 24:67] + wire _T_151 = ~io_ins[23]; // @[dec_dec_ctl.scala 15:46] + wire _T_158 = _T_43 & io_ins[29]; // @[dec_dec_ctl.scala 17:17] + wire _T_159 = _T_158 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_160 = _T_159 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_161 = _T_160 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_162 = _T_161 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_163 = _T_162 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_164 = _T_163 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_165 = _T_164 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_166 = _T_144 | _T_165; // @[dec_dec_ctl.scala 24:107] + wire _T_181 = _T_43 & io_ins[24]; // @[dec_dec_ctl.scala 17:17] + wire _T_182 = _T_181 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_183 = _T_182 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_184 = _T_183 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_185 = _T_184 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_186 = _T_185 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_187 = _T_186 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_194 = ~io_ins[2]; // @[dec_dec_ctl.scala 15:46] + wire _T_195 = _T_63 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_196 = _T_195 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_202 = _T_34 & io_ins[11]; // @[dec_dec_ctl.scala 17:17] + wire _T_203 = _T_202 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_204 = _T_196 | _T_203; // @[dec_dec_ctl.scala 27:43] + wire _T_209 = io_ins[19] & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_210 = _T_209 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_211 = _T_204 | _T_210; // @[dec_dec_ctl.scala 27:70] + wire _T_217 = _T_34 & io_ins[10]; // @[dec_dec_ctl.scala 17:17] + wire _T_218 = _T_217 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_219 = _T_211 | _T_218; // @[dec_dec_ctl.scala 27:96] + wire _T_224 = io_ins[18] & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_225 = _T_224 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_226 = _T_219 | _T_225; // @[dec_dec_ctl.scala 28:30] + wire _T_232 = _T_34 & io_ins[9]; // @[dec_dec_ctl.scala 17:17] + wire _T_233 = _T_232 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_234 = _T_226 | _T_233; // @[dec_dec_ctl.scala 28:57] + wire _T_239 = io_ins[17] & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_240 = _T_239 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_241 = _T_234 | _T_240; // @[dec_dec_ctl.scala 28:83] + wire _T_247 = _T_34 & io_ins[8]; // @[dec_dec_ctl.scala 17:17] + wire _T_248 = _T_247 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_249 = _T_241 | _T_248; // @[dec_dec_ctl.scala 28:109] + wire _T_254 = io_ins[16] & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_255 = _T_254 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_256 = _T_249 | _T_255; // @[dec_dec_ctl.scala 29:29] + wire _T_262 = _T_34 & io_ins[7]; // @[dec_dec_ctl.scala 17:17] + wire _T_263 = _T_262 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_264 = _T_256 | _T_263; // @[dec_dec_ctl.scala 29:55] + wire _T_269 = io_ins[15] & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_270 = _T_269 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_271 = _T_264 | _T_270; // @[dec_dec_ctl.scala 29:81] + wire _T_273 = ~io_ins[4]; // @[dec_dec_ctl.scala 15:46] + wire _T_275 = ~io_ins[3]; // @[dec_dec_ctl.scala 15:46] + wire _T_276 = _T_273 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_277 = _T_271 | _T_276; // @[dec_dec_ctl.scala 30:29] + wire _T_279 = ~io_ins[6]; // @[dec_dec_ctl.scala 15:46] + wire _T_282 = _T_279 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_289 = io_ins[5] & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_290 = _T_289 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_296 = _T_279 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_297 = _T_296 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_305 = _T_276 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_314 = _T_114 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_315 = _T_305 | _T_314; // @[dec_dec_ctl.scala 34:42] + wire _T_322 = _T_34 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_323 = _T_322 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_324 = _T_323 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_325 = _T_315 | _T_324; // @[dec_dec_ctl.scala 34:70] + wire _T_335 = _T_122 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_341 = _T_11 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_344 = io_ins[5] & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_345 = _T_341 | _T_344; // @[dec_dec_ctl.scala 36:37] + wire _T_357 = io_ins[27] & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_358 = _T_357 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_359 = _T_358 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_360 = _T_359 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_361 = _T_360 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_372 = _T_43 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_373 = _T_372 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_374 = _T_373 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_375 = _T_374 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_376 = _T_375 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_377 = _T_361 | _T_376; // @[dec_dec_ctl.scala 38:53] + wire _T_387 = io_ins[14] & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_388 = _T_387 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_389 = _T_388 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_390 = _T_389 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_391 = _T_390 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_395 = io_ins[5] & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_398 = io_ins[4] & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_405 = _T_11 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_406 = _T_405 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_417 = _T_11 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_432 = _T_279 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_444 = _T_195 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_445 = _T_444 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_446 = _T_445 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_454 = _T_446 | _T_406; // @[dec_dec_ctl.scala 50:49] + wire _T_471 = _T_48 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_472 = _T_471 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_473 = _T_472 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_474 = _T_473 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_475 = _T_474 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_476 = _T_475 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_489 = io_ins[30] & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_490 = _T_489 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_491 = _T_490 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_492 = _T_491 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_493 = _T_492 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_494 = _T_493 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_507 = _T_90 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_508 = _T_507 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_509 = _T_508 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_510 = _T_509 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_511 = _T_510 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_512 = _T_511 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_513 = _T_494 | _T_512; // @[dec_dec_ctl.scala 52:53] + wire _T_524 = _T_57 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_525 = _T_524 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_526 = _T_525 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_527 = _T_513 | _T_526; // @[dec_dec_ctl.scala 52:93] + wire _T_536 = _T_63 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_537 = _T_536 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_538 = _T_537 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_539 = _T_538 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_540 = _T_527 | _T_539; // @[dec_dec_ctl.scala 53:37] + wire _T_546 = io_ins[6] & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_547 = _T_546 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_562 = _T_85 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_563 = _T_562 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_564 = _T_563 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_565 = _T_564 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_573 = io_ins[14] & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_574 = _T_573 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_575 = _T_574 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_576 = _T_575 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_581 = _T_279 & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_596 = _T_90 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_597 = _T_596 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_598 = _T_597 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_599 = _T_598 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_600 = _T_599 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_601 = _T_600 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_602 = _T_601 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_603 = _T_581 | _T_602; // @[dec_dec_ctl.scala 57:37] + wire _T_607 = io_ins[5] & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_608 = _T_607 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_609 = _T_603 | _T_608; // @[dec_dec_ctl.scala 57:82] + wire _T_619 = _T_609 | _T_324; // @[dec_dec_ctl.scala 57:105] + wire _T_629 = _T_573 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_630 = _T_629 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_631 = _T_630 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_650 = _T_598 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_651 = _T_650 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_652 = _T_651 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_653 = _T_652 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_665 = _T_387 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_666 = _T_665 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_667 = _T_666 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_668 = _T_667 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_688 = _T_597 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_689 = _T_688 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_690 = _T_689 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_691 = _T_690 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_692 = _T_691 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_708 = _T_94 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_709 = _T_708 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_710 = _T_709 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_711 = _T_710 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_712 = _T_711 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_731 = _T_43 & _T_90; // @[dec_dec_ctl.scala 17:17] + wire _T_732 = _T_731 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_733 = _T_732 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_734 = _T_733 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_735 = _T_734 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_736 = _T_735 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_737 = _T_736 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_738 = _T_737 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_781 = _T_23 & io_ins[25]; // @[dec_dec_ctl.scala 17:17] + wire _T_782 = _T_781 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_783 = _T_782 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_784 = _T_783 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_785 = _T_784 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_786 = _T_785 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_796 = _T_536 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_797 = _T_796 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_798 = _T_797 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_799 = _T_786 | _T_798; // @[dec_dec_ctl.scala 70:56] + wire _T_806 = io_ins[13] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_807 = _T_806 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_808 = _T_807 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_809 = _T_799 | _T_808; // @[dec_dec_ctl.scala 70:89] + wire _T_815 = io_ins[14] & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_816 = _T_815 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_817 = _T_809 | _T_816; // @[dec_dec_ctl.scala 71:31] + wire _T_828 = _T_32 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_829 = _T_828 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_830 = _T_829 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_831 = _T_830 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_832 = _T_831 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_833 = _T_817 | _T_832; // @[dec_dec_ctl.scala 71:57] + wire _T_845 = _T_57 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_846 = _T_845 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_847 = _T_846 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_848 = _T_847 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_866 = _T_63 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_867 = _T_866 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_868 = _T_867 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_878 = _T_63 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_879 = _T_878 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_880 = _T_879 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_889 = io_ins[14] & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_890 = _T_889 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_891 = _T_890 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_901 = io_ins[14] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_902 = _T_901 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_903 = _T_902 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_919 = _T_322 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_920 = _T_919 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_929 = io_ins[12] & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_930 = _T_929 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_937 = io_ins[13] & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_943 = _T_806 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_947 = io_ins[7] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_948 = _T_947 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_949 = _T_943 | _T_948; // @[dec_dec_ctl.scala 92:44] + wire _T_953 = io_ins[8] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_954 = _T_953 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_955 = _T_949 | _T_954; // @[dec_dec_ctl.scala 92:67] + wire _T_959 = io_ins[9] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_960 = _T_959 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_961 = _T_955 | _T_960; // @[dec_dec_ctl.scala 92:90] + wire _T_965 = io_ins[10] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_966 = _T_965 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_967 = _T_961 | _T_966; // @[dec_dec_ctl.scala 93:26] + wire _T_971 = io_ins[11] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_972 = _T_971 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_980 = _T_269 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_981 = _T_980 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_982 = _T_981 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_989 = _T_254 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_990 = _T_989 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_991 = _T_990 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_992 = _T_982 | _T_991; // @[dec_dec_ctl.scala 95:49] + wire _T_999 = _T_239 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1000 = _T_999 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1001 = _T_1000 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1002 = _T_992 | _T_1001; // @[dec_dec_ctl.scala 95:79] + wire _T_1009 = _T_224 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1010 = _T_1009 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1011 = _T_1010 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1012 = _T_1002 | _T_1011; // @[dec_dec_ctl.scala 96:33] + wire _T_1019 = _T_209 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1020 = _T_1019 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1021 = _T_1020 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1028 = io_ins[15] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1029 = _T_1028 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1030 = _T_1029 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1036 = io_ins[16] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1037 = _T_1036 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1038 = _T_1037 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1039 = _T_1030 | _T_1038; // @[dec_dec_ctl.scala 98:47] + wire _T_1045 = io_ins[17] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1046 = _T_1045 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1047 = _T_1046 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1048 = _T_1039 | _T_1047; // @[dec_dec_ctl.scala 98:75] + wire _T_1054 = io_ins[18] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1055 = _T_1054 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1056 = _T_1055 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1057 = _T_1048 | _T_1056; // @[dec_dec_ctl.scala 98:103] + wire _T_1063 = io_ins[19] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1064 = _T_1063 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1065 = _T_1064 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1072 = _T_34 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1073 = _T_1072 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1081 = _T_387 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1082 = _T_1081 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1087 = io_ins[15] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1088 = _T_1087 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1089 = _T_1088 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1090 = _T_1082 | _T_1089; // @[dec_dec_ctl.scala 103:47] + wire _T_1095 = io_ins[16] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1096 = _T_1095 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1097 = _T_1096 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1098 = _T_1090 | _T_1097; // @[dec_dec_ctl.scala 103:74] + wire _T_1103 = io_ins[17] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1104 = _T_1103 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1105 = _T_1104 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1106 = _T_1098 | _T_1105; // @[dec_dec_ctl.scala 103:101] + wire _T_1111 = io_ins[18] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1112 = _T_1111 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1113 = _T_1112 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1114 = _T_1106 | _T_1113; // @[dec_dec_ctl.scala 104:30] + wire _T_1119 = io_ins[19] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1120 = _T_1119 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1121 = _T_1120 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1126 = _T_11 & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_1133 = _T_262 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1134 = _T_1133 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1135 = _T_1126 | _T_1134; // @[dec_dec_ctl.scala 106:41] + wire _T_1142 = _T_247 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1143 = _T_1142 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1144 = _T_1135 | _T_1143; // @[dec_dec_ctl.scala 106:68] + wire _T_1151 = _T_232 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1152 = _T_1151 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1153 = _T_1144 | _T_1152; // @[dec_dec_ctl.scala 106:95] + wire _T_1160 = _T_217 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1161 = _T_1160 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1162 = _T_1153 | _T_1161; // @[dec_dec_ctl.scala 107:30] + wire _T_1169 = _T_202 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1170 = _T_1169 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1171 = _T_1162 | _T_1170; // @[dec_dec_ctl.scala 107:58] + wire _T_1177 = _T_269 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1178 = _T_1177 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1179 = _T_1171 | _T_1178; // @[dec_dec_ctl.scala 107:86] + wire _T_1185 = _T_254 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1186 = _T_1185 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1187 = _T_1179 | _T_1186; // @[dec_dec_ctl.scala 108:30] + wire _T_1193 = _T_239 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1194 = _T_1193 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1195 = _T_1187 | _T_1194; // @[dec_dec_ctl.scala 108:57] + wire _T_1201 = _T_224 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1202 = _T_1201 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1203 = _T_1195 | _T_1202; // @[dec_dec_ctl.scala 108:84] + wire _T_1209 = _T_209 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1210 = _T_1209 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1216 = io_ins[12] & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1217 = _T_1216 & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_1226 = _T_4 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1227 = _T_1226 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1228 = _T_1227 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1229 = _T_1228 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1230 = _T_1217 | _T_1229; // @[dec_dec_ctl.scala 111:45] + wire _T_1239 = _T_1230 | _T_1134; // @[dec_dec_ctl.scala 111:78] + wire _T_1248 = _T_1239 | _T_1143; // @[dec_dec_ctl.scala 112:30] + wire _T_1257 = _T_1248 | _T_1152; // @[dec_dec_ctl.scala 112:57] + wire _T_1266 = _T_1257 | _T_1161; // @[dec_dec_ctl.scala 112:84] + wire _T_1275 = _T_1266 | _T_1170; // @[dec_dec_ctl.scala 112:112] + wire _T_1283 = _T_1275 | _T_1178; // @[dec_dec_ctl.scala 113:31] + wire _T_1291 = _T_1283 | _T_1186; // @[dec_dec_ctl.scala 113:58] + wire _T_1299 = _T_1291 | _T_1194; // @[dec_dec_ctl.scala 113:85] + wire _T_1307 = _T_1299 | _T_1202; // @[dec_dec_ctl.scala 113:112] + wire _T_1325 = _T_4 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_1326 = _T_1325 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1327 = _T_1326 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1328 = _T_1327 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1340 = _T_6 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_1341 = _T_1340 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1342 = _T_1341 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1343 = _T_1342 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1352 = io_ins[29] & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1353 = _T_1352 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1354 = _T_1353 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_1370 = _T_43 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_1371 = _T_1370 & io_ins[24]; // @[dec_dec_ctl.scala 17:17] + wire _T_1372 = _T_1371 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_1373 = _T_1372 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1374 = _T_1373 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1375 = _T_1374 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1376 = _T_1375 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1377 = _T_1376 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1378 = _T_1377 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1394 = _T_65 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_1395 = _T_1394 & io_ins[23]; // @[dec_dec_ctl.scala 17:17] + wire _T_1396 = _T_1395 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1397 = _T_1396 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1398 = _T_1397 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1399 = _T_1398 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1400 = _T_1399 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1401 = _T_1400 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1402 = _T_1378 | _T_1401; // @[dec_dec_ctl.scala 122:63] + wire _T_1420 = _T_1394 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_1421 = _T_1420 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1422 = _T_1421 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1423 = _T_1422 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1424 = _T_1423 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1425 = _T_1424 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1426 = _T_1425 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1427 = _T_1402 | _T_1426; // @[dec_dec_ctl.scala 122:111] + wire _T_1440 = io_ins[27] & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_1441 = _T_1440 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_1442 = _T_1441 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1443 = _T_1442 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1444 = _T_1443 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1445 = _T_1444 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1446 = _T_1445 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1447 = _T_1427 | _T_1446; // @[dec_dec_ctl.scala 123:52] + wire _T_1457 = io_ins[30] & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_1458 = _T_1457 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_1459 = _T_1458 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1460 = _T_1459 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1461 = _T_1460 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1462 = _T_1461 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1463 = _T_1447 | _T_1462; // @[dec_dec_ctl.scala 123:93] + wire _T_1479 = _T_65 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_1480 = _T_1479 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_1481 = _T_1480 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1482 = _T_1481 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1483 = _T_1482 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1484 = _T_1483 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1485 = _T_1484 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1486 = _T_1485 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1487 = _T_1463 | _T_1486; // @[dec_dec_ctl.scala 124:39] + wire _T_1503 = _T_65 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_1504 = _T_1503 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_1505 = _T_1504 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1506 = _T_1505 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1507 = _T_1506 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1508 = _T_1507 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1509 = _T_1508 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1510 = _T_1509 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1511 = _T_1487 | _T_1510; // @[dec_dec_ctl.scala 124:87] + wire _T_1527 = _T_65 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_1528 = _T_1527 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_1529 = _T_1528 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1530 = _T_1529 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1531 = _T_1530 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1532 = _T_1531 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1533 = _T_1532 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1534 = _T_1533 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1535 = _T_1511 | _T_1534; // @[dec_dec_ctl.scala 125:51] + wire _T_1550 = io_ins[30] & io_ins[29]; // @[dec_dec_ctl.scala 17:17] + wire _T_1551 = _T_1550 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_1552 = _T_1551 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_1553 = _T_1552 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1554 = _T_1553 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1555 = _T_1554 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1556 = _T_1555 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1557 = _T_1556 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1558 = _T_1557 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1559 = _T_1535 | _T_1558; // @[dec_dec_ctl.scala 125:99] + wire _T_1574 = _T_1370 & io_ins[23]; // @[dec_dec_ctl.scala 17:17] + wire _T_1575 = _T_1574 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1576 = _T_1575 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1577 = _T_1576 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1578 = _T_1577 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1579 = _T_1578 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1580 = _T_1579 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1581 = _T_1559 | _T_1580; // @[dec_dec_ctl.scala 126:51] + wire _T_1598 = _T_731 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_1599 = _T_1598 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_1600 = _T_1599 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1601 = _T_1600 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1602 = _T_1601 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1603 = _T_1602 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1604 = _T_1603 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1605 = _T_1581 | _T_1604; // @[dec_dec_ctl.scala 126:96] + wire _T_1615 = io_ins[25] & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1616 = _T_1615 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1617 = _T_1616 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1618 = _T_1617 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1619 = _T_1618 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1620 = _T_1605 | _T_1619; // @[dec_dec_ctl.scala 127:50] + wire _T_1635 = io_ins[30] & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_1636 = _T_1635 & io_ins[24]; // @[dec_dec_ctl.scala 17:17] + wire _T_1637 = _T_1636 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1638 = _T_1637 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1639 = _T_1638 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1640 = _T_1639 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1641 = _T_1640 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1642 = _T_1641 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1643 = _T_1620 | _T_1642; // @[dec_dec_ctl.scala 127:84] + wire _T_1653 = _T_65 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1654 = _T_1653 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1655 = _T_1654 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1656 = _T_1655 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1673 = _T_781 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1674 = _T_1673 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_1675 = _T_1674 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1676 = _T_1675 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1677 = _T_1676 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1678 = _T_1677 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1679 = _T_1678 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1695 = _T_1673 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1696 = _T_1695 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1697 = _T_1696 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1698 = _T_1697 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1699 = _T_1698 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_1733 = _T_1615 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1734 = _T_1733 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1735 = _T_1734 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1736 = _T_1735 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1749 = _T_782 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1750 = _T_1749 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1764 = _T_782 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_1765 = _T_1764 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1766 = _T_1765 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1800 = _T_1635 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_1801 = _T_1800 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_1802 = _T_1801 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_1803 = _T_1802 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_1804 = _T_1803 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1805 = _T_1804 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1806 = _T_1805 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1807 = _T_1806 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1808 = _T_1807 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1831 = _T_1801 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_1832 = _T_1831 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1833 = _T_1832 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1834 = _T_1833 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1835 = _T_1834 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1836 = _T_1835 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1856 = _T_1800 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_1857 = _T_1856 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1858 = _T_1857 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1859 = _T_1858 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1860 = _T_1859 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1861 = _T_1860 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1880 = _T_1635 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_1881 = _T_1880 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_1882 = _T_1881 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1883 = _T_1882 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1884 = _T_1883 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1885 = _T_1884 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1886 = _T_1885 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1905 = _T_1880 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_1906 = _T_1905 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1907 = _T_1906 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1908 = _T_1907 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1909 = _T_1908 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_1910 = _T_1909 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1928 = _T_158 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_1929 = _T_1928 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_1930 = _T_1929 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1931 = _T_1930 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1932 = _T_1931 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1933 = _T_1932 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1951 = _T_1928 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_1952 = _T_1951 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_1953 = _T_1952 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1954 = _T_1953 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1955 = _T_1954 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_1969 = _T_57 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_1970 = _T_1969 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1971 = _T_1970 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_1984 = _T_57 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_1985 = _T_1984 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_1986 = _T_1985 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2002 = _T_1370 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_2003 = _T_2002 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2004 = _T_2003 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2005 = _T_2004 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2006 = _T_2005 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2019 = _T_1457 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2020 = _T_2019 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2021 = _T_2020 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2022 = _T_2021 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2038 = _T_2002 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_2039 = _T_2038 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2040 = _T_2039 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2041 = _T_2040 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2056 = _T_1635 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2057 = _T_2056 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2058 = _T_2057 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2059 = _T_2058 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2060 = _T_2059 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2076 = _T_1550 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_2077 = _T_2076 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2078 = _T_2077 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2079 = _T_2078 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2080 = _T_2079 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2081 = _T_2080 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2100 = _T_1800 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2101 = _T_2100 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2102 = _T_2101 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2103 = _T_2102 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2104 = _T_2103 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2105 = _T_2104 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2118 = _T_1370 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2119 = _T_2118 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_2120 = _T_2119 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2121 = _T_2120 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2122 = _T_2121 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2123 = _T_2122 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2124 = _T_2105 | _T_2123; // @[dec_dec_ctl.scala 172:62] + wire _T_2143 = _T_2079 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2144 = _T_2143 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2145 = _T_2144 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2146 = _T_2124 | _T_2145; // @[dec_dec_ctl.scala 172:103] + wire _T_2157 = _T_357 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2158 = _T_2157 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2159 = _T_2158 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2160 = _T_2159 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2161 = _T_2146 | _T_2160; // @[dec_dec_ctl.scala 173:48] + wire _T_2173 = io_ins[30] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2174 = _T_2173 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2175 = _T_2174 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2176 = _T_2175 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2177 = _T_2176 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2178 = _T_2177 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2179 = _T_2161 | _T_2178; // @[dec_dec_ctl.scala 173:83] + wire _T_2191 = _T_1635 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_2192 = _T_2191 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2193 = _T_2192 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2194 = _T_2193 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2195 = _T_2194 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2196 = _T_2179 | _T_2195; // @[dec_dec_ctl.scala 174:42] + wire _T_2209 = _T_2076 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2210 = _T_2209 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2211 = _T_2210 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2212 = _T_2211 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2213 = _T_2196 | _T_2212; // @[dec_dec_ctl.scala 174:79] + wire _T_2231 = _T_1550 & io_ins[24]; // @[dec_dec_ctl.scala 17:17] + wire _T_2232 = _T_2231 & io_ins[23]; // @[dec_dec_ctl.scala 17:17] + wire _T_2233 = _T_2232 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_2234 = _T_2233 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_2235 = _T_2234 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_2236 = _T_2235 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2237 = _T_2236 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2238 = _T_2237 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2239 = _T_2238 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2240 = _T_2239 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2241 = _T_2240 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2242 = _T_2213 | _T_2241; // @[dec_dec_ctl.scala 175:40] + wire _T_2264 = _T_158 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_2265 = _T_2264 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_2266 = _T_2265 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_2267 = _T_2266 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_2268 = _T_2267 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_2269 = _T_2268 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_2270 = _T_2269 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2271 = _T_2270 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2272 = _T_2271 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2273 = _T_2272 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2274 = _T_2273 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2275 = _T_2274 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2276 = _T_2242 | _T_2275; // @[dec_dec_ctl.scala 175:96] + wire _T_2300 = _T_1371 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_2301 = _T_2300 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_2302 = _T_2301 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_2303 = _T_2302 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_2304 = _T_2303 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2305 = _T_2304 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2306 = _T_2305 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2307 = _T_2306 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2308 = _T_2307 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2309 = _T_2308 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2310 = _T_2276 | _T_2309; // @[dec_dec_ctl.scala 176:65] + wire _T_2333 = _T_2232 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_2334 = _T_2333 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_2335 = _T_2334 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_2336 = _T_2335 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2337 = _T_2336 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2338 = _T_2337 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2339 = _T_2338 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2340 = _T_2339 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2341 = _T_2340 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2342 = _T_2310 | _T_2341; // @[dec_dec_ctl.scala 177:64] + wire _T_2373 = _T_2264 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2374 = _T_2373 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2375 = _T_2374 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2376 = _T_2375 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2377 = _T_2376 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2393 = _T_94 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2394 = _T_2393 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2395 = _T_2394 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2396 = _T_2395 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2397 = _T_2396 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2414 = _T_1551 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2415 = _T_2414 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2416 = _T_2415 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2417 = _T_2416 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2418 = _T_2417 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2434 = _T_94 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_2435 = _T_2434 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2436 = _T_2435 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2437 = _T_2436 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2438 = _T_2437 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2439 = _T_2438 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2455 = _T_66 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2456 = _T_2455 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2457 = _T_2456 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2458 = _T_2457 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2459 = _T_2458 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2474 = _T_2434 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2475 = _T_2474 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2476 = _T_2475 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2477 = _T_2476 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2478 = _T_2477 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2497 = _T_2038 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2498 = _T_2497 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2499 = _T_2498 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2500 = _T_2499 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2515 = _T_1458 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2516 = _T_2515 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2517 = _T_2516 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2518 = _T_2517 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2552 = _T_56 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2553 = _T_2552 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2554 = _T_2553 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2555 = _T_2554 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2556 = _T_2555 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2568 = io_ins[27] & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2569 = _T_2568 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_2570 = _T_2569 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2571 = _T_2570 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2572 = _T_2571 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2586 = _T_2568 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2587 = _T_2586 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2588 = _T_2587 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2589 = _T_2588 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2603 = _T_2552 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2604 = _T_2603 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2605 = _T_2604 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2621 = _T_1551 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2622 = _T_2621 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2623 = _T_2622 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2624 = _T_2623 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2625 = _T_2624 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2642 = _T_2264 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2643 = _T_2642 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2644 = _T_2643 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2645 = _T_2644 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2646 = _T_2645 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2668 = _T_1599 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2669 = _T_2668 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2670 = _T_2669 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2671 = _T_2670 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2672 = _T_2671 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2693 = _T_1599 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2694 = _T_2693 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2695 = _T_2694 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2696 = _T_2695 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2697 = _T_2696 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2714 = _T_1928 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2715 = _T_2714 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2716 = _T_2715 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2717 = _T_2716 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2718 = _T_2717 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2734 = _T_1598 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2735 = _T_2734 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2736 = _T_2735 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2737 = _T_2736 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2738 = _T_2737 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2739 = _T_2718 | _T_2738; // @[dec_dec_ctl.scala 212:58] + wire _T_2756 = _T_2739 | _T_2195; // @[dec_dec_ctl.scala 212:101] + wire _T_2769 = _T_1440 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2770 = _T_2769 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_2771 = _T_2770 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2772 = _T_2771 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2773 = _T_2772 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2774 = _T_2756 | _T_2773; // @[dec_dec_ctl.scala 213:40] + wire _T_2788 = _T_2175 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2789 = _T_2788 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2790 = _T_2789 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2791 = _T_2774 | _T_2790; // @[dec_dec_ctl.scala 213:79] + wire _T_2803 = _T_27 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2804 = _T_2803 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2805 = _T_2804 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2806 = _T_2805 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2807 = _T_2806 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2808 = _T_2791 | _T_2807; // @[dec_dec_ctl.scala 214:41] + wire _T_2826 = _T_1599 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2827 = _T_2826 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2828 = _T_2827 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_2829 = _T_2828 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2830 = _T_2829 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2831 = _T_2808 | _T_2830; // @[dec_dec_ctl.scala 214:78] + wire _T_2842 = io_ins[29] & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_2843 = _T_2842 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2844 = _T_2843 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2845 = _T_2844 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_2846 = _T_2845 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2847 = _T_2846 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_2871 = _T_1636 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_2872 = _T_2871 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_2873 = _T_2872 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_2874 = _T_2873 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2875 = _T_2874 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2876 = _T_2875 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2877 = _T_2876 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2878 = _T_2877 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2900 = _T_2871 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_2901 = _T_2900 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2902 = _T_2901 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2903 = _T_2902 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2904 = _T_2903 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2905 = _T_2904 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2927 = _T_2871 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_2928 = _T_2927 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2929 = _T_2928 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2930 = _T_2929 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2931 = _T_2930 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2932 = _T_2931 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2953 = _T_1635 & io_ins[23]; // @[dec_dec_ctl.scala 17:17] + wire _T_2954 = _T_2953 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_2955 = _T_2954 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_2956 = _T_2955 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2957 = _T_2956 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2958 = _T_2957 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2959 = _T_2958 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2960 = _T_2959 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_2979 = _T_2953 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_2980 = _T_2979 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_2981 = _T_2980 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_2982 = _T_2981 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_2983 = _T_2982 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_2984 = _T_2983 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3003 = _T_2953 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_3004 = _T_3003 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_3005 = _T_3004 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_3006 = _T_3005 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_3007 = _T_3006 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3008 = _T_3007 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3043 = _T_1458 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_3044 = _T_3043 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3045 = _T_3044 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3074 = _T_74 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3075 = _T_3074 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3076 = _T_3075 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3077 = _T_3076 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3091 = _T_2843 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3092 = _T_3091 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3093 = _T_3092 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3104 = _T_2842 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_3105 = _T_3104 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3106 = _T_3105 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3117 = io_ins[29] & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3118 = _T_3117 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3119 = _T_3118 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3120 = _T_3119 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3129 = io_ins[28] & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_3130 = _T_3129 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_3131 = _T_3130 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3132 = _T_3131 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3147 = _T_733 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3148 = _T_3147 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3149 = _T_3132 | _T_3148; // @[dec_dec_ctl.scala 243:51] + wire _T_3164 = _T_597 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_3165 = _T_3164 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_3166 = _T_3165 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3167 = _T_3166 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3168 = _T_3149 | _T_3167; // @[dec_dec_ctl.scala 243:89] + wire _T_3183 = _T_688 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3184 = _T_3183 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3185 = _T_3168 | _T_3184; // @[dec_dec_ctl.scala 244:44] + wire _T_3192 = _T_3185 | _T_114; // @[dec_dec_ctl.scala 244:82] + wire _T_3196 = _T_3192 | _T_398; // @[dec_dec_ctl.scala 245:28] + wire _T_3206 = ~io_ins[31]; // @[dec_dec_ctl.scala 15:46] + wire _T_3215 = ~io_ins[26]; // @[dec_dec_ctl.scala 15:46] + wire _T_3227 = ~io_ins[19]; // @[dec_dec_ctl.scala 15:46] + wire _T_3229 = ~io_ins[18]; // @[dec_dec_ctl.scala 15:46] + wire _T_3231 = ~io_ins[17]; // @[dec_dec_ctl.scala 15:46] + wire _T_3233 = ~io_ins[16]; // @[dec_dec_ctl.scala 15:46] + wire _T_3235 = ~io_ins[15]; // @[dec_dec_ctl.scala 15:46] + wire _T_3239 = ~io_ins[11]; // @[dec_dec_ctl.scala 15:46] + wire _T_3241 = ~io_ins[10]; // @[dec_dec_ctl.scala 15:46] + wire _T_3243 = ~io_ins[9]; // @[dec_dec_ctl.scala 15:46] + wire _T_3245 = ~io_ins[8]; // @[dec_dec_ctl.scala 15:46] + wire _T_3247 = ~io_ins[7]; // @[dec_dec_ctl.scala 15:46] + wire _T_3257 = _T_3206 & _T_43; // @[dec_dec_ctl.scala 17:17] + wire _T_3258 = _T_3257 & _T_90; // @[dec_dec_ctl.scala 17:17] + wire _T_3259 = _T_3258 & io_ins[28]; // @[dec_dec_ctl.scala 17:17] + wire _T_3260 = _T_3259 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_3261 = _T_3260 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3262 = _T_3261 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3263 = _T_3262 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_3264 = _T_3263 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_3265 = _T_3264 & io_ins[22]; // @[dec_dec_ctl.scala 17:17] + wire _T_3266 = _T_3265 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_3267 = _T_3266 & io_ins[20]; // @[dec_dec_ctl.scala 17:17] + wire _T_3268 = _T_3267 & _T_3227; // @[dec_dec_ctl.scala 17:17] + wire _T_3269 = _T_3268 & _T_3229; // @[dec_dec_ctl.scala 17:17] + wire _T_3270 = _T_3269 & _T_3231; // @[dec_dec_ctl.scala 17:17] + wire _T_3271 = _T_3270 & _T_3233; // @[dec_dec_ctl.scala 17:17] + wire _T_3272 = _T_3271 & _T_3235; // @[dec_dec_ctl.scala 17:17] + wire _T_3273 = _T_3272 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_3274 = _T_3273 & _T_3239; // @[dec_dec_ctl.scala 17:17] + wire _T_3275 = _T_3274 & _T_3241; // @[dec_dec_ctl.scala 17:17] + wire _T_3276 = _T_3275 & _T_3243; // @[dec_dec_ctl.scala 17:17] + wire _T_3277 = _T_3276 & _T_3245; // @[dec_dec_ctl.scala 17:17] + wire _T_3278 = _T_3277 & _T_3247; // @[dec_dec_ctl.scala 17:17] + wire _T_3279 = _T_3278 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_3280 = _T_3279 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3281 = _T_3280 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3282 = _T_3281 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3283 = _T_3282 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_3284 = _T_3283 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3285 = _T_3284 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3339 = _T_3257 & io_ins[29]; // @[dec_dec_ctl.scala 17:17] + wire _T_3340 = _T_3339 & io_ins[28]; // @[dec_dec_ctl.scala 17:17] + wire _T_3341 = _T_3340 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_3342 = _T_3341 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3343 = _T_3342 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3344 = _T_3343 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_3345 = _T_3344 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_3346 = _T_3345 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_3347 = _T_3346 & io_ins[21]; // @[dec_dec_ctl.scala 17:17] + wire _T_3348 = _T_3347 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_3349 = _T_3348 & _T_3227; // @[dec_dec_ctl.scala 17:17] + wire _T_3350 = _T_3349 & _T_3229; // @[dec_dec_ctl.scala 17:17] + wire _T_3351 = _T_3350 & _T_3231; // @[dec_dec_ctl.scala 17:17] + wire _T_3352 = _T_3351 & _T_3233; // @[dec_dec_ctl.scala 17:17] + wire _T_3353 = _T_3352 & _T_3235; // @[dec_dec_ctl.scala 17:17] + wire _T_3354 = _T_3353 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_3355 = _T_3354 & _T_3239; // @[dec_dec_ctl.scala 17:17] + wire _T_3356 = _T_3355 & _T_3241; // @[dec_dec_ctl.scala 17:17] + wire _T_3357 = _T_3356 & _T_3243; // @[dec_dec_ctl.scala 17:17] + wire _T_3358 = _T_3357 & _T_3245; // @[dec_dec_ctl.scala 17:17] + wire _T_3359 = _T_3358 & _T_3247; // @[dec_dec_ctl.scala 17:17] + wire _T_3360 = _T_3359 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_3361 = _T_3360 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3362 = _T_3361 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3363 = _T_3362 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3364 = _T_3363 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_3365 = _T_3364 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3366 = _T_3365 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3367 = _T_3285 | _T_3366; // @[dec_dec_ctl.scala 248:136] + wire _T_3375 = ~io_ins[28]; // @[dec_dec_ctl.scala 15:46] + wire _T_3422 = _T_3258 & _T_3375; // @[dec_dec_ctl.scala 17:17] + wire _T_3423 = _T_3422 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_3424 = _T_3423 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3425 = _T_3424 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3426 = _T_3425 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_3427 = _T_3426 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_3428 = _T_3427 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_3429 = _T_3428 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_3430 = _T_3429 & _T_3227; // @[dec_dec_ctl.scala 17:17] + wire _T_3431 = _T_3430 & _T_3229; // @[dec_dec_ctl.scala 17:17] + wire _T_3432 = _T_3431 & _T_3231; // @[dec_dec_ctl.scala 17:17] + wire _T_3433 = _T_3432 & _T_3233; // @[dec_dec_ctl.scala 17:17] + wire _T_3434 = _T_3433 & _T_3235; // @[dec_dec_ctl.scala 17:17] + wire _T_3435 = _T_3434 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_3436 = _T_3435 & _T_3239; // @[dec_dec_ctl.scala 17:17] + wire _T_3437 = _T_3436 & _T_3241; // @[dec_dec_ctl.scala 17:17] + wire _T_3438 = _T_3437 & _T_3243; // @[dec_dec_ctl.scala 17:17] + wire _T_3439 = _T_3438 & _T_3245; // @[dec_dec_ctl.scala 17:17] + wire _T_3440 = _T_3439 & _T_3247; // @[dec_dec_ctl.scala 17:17] + wire _T_3441 = _T_3440 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3442 = _T_3441 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3443 = _T_3442 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3444 = _T_3443 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_3445 = _T_3444 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3446 = _T_3445 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3447 = _T_3367 | _T_3446; // @[dec_dec_ctl.scala 249:122] + wire _T_3471 = _T_3206 & io_ins[29]; // @[dec_dec_ctl.scala 17:17] + wire _T_3472 = _T_3471 & _T_3375; // @[dec_dec_ctl.scala 17:17] + wire _T_3473 = _T_3472 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3474 = _T_3473 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3475 = _T_3474 & io_ins[24]; // @[dec_dec_ctl.scala 17:17] + wire _T_3476 = _T_3475 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_3477 = _T_3476 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_3478 = _T_3477 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3479 = _T_3478 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3480 = _T_3479 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3481 = _T_3480 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3482 = _T_3481 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3483 = _T_3482 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3484 = _T_3447 | _T_3483; // @[dec_dec_ctl.scala 250:119] + wire _T_3514 = _T_3476 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_3515 = _T_3514 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3516 = _T_3515 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3517 = _T_3516 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3518 = _T_3517 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3519 = _T_3518 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3520 = _T_3519 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3521 = _T_3484 | _T_3520; // @[dec_dec_ctl.scala 251:65] + wire _T_3550 = _T_3474 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_3551 = _T_3550 & _T_4; // @[dec_dec_ctl.scala 17:17] + wire _T_3552 = _T_3551 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_3553 = _T_3552 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3554 = _T_3553 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3555 = _T_3554 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3556 = _T_3555 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3557 = _T_3556 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3558 = _T_3557 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3559 = _T_3521 | _T_3558; // @[dec_dec_ctl.scala 251:127] + wire _T_3588 = _T_3474 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_3589 = _T_3588 & _T_151; // @[dec_dec_ctl.scala 17:17] + wire _T_3590 = _T_3589 & _T_6; // @[dec_dec_ctl.scala 17:17] + wire _T_3591 = _T_3590 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3592 = _T_3591 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3593 = _T_3592 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3594 = _T_3593 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3595 = _T_3594 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3596 = _T_3595 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3597 = _T_3559 | _T_3596; // @[dec_dec_ctl.scala 252:66] + wire _T_3620 = _T_3422 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3621 = _T_3620 & io_ins[25]; // @[dec_dec_ctl.scala 17:17] + wire _T_3622 = _T_3621 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_3623 = _T_3622 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3624 = _T_3623 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3625 = _T_3624 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3626 = _T_3625 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3627 = _T_3626 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3628 = _T_3597 | _T_3627; // @[dec_dec_ctl.scala 252:129] + wire _T_3651 = _T_3257 & _T_3375; // @[dec_dec_ctl.scala 17:17] + wire _T_3652 = _T_3651 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3653 = _T_3652 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3654 = _T_3653 & _T_25; // @[dec_dec_ctl.scala 17:17] + wire _T_3655 = _T_3654 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3656 = _T_3655 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3657 = _T_3656 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3658 = _T_3657 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3659 = _T_3658 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3660 = _T_3659 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3661 = _T_3628 | _T_3660; // @[dec_dec_ctl.scala 253:58] + wire _T_3686 = _T_3651 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_3687 = _T_3686 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3688 = _T_3687 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3689 = _T_3688 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_3690 = _T_3689 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3691 = _T_3690 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3692 = _T_3691 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3693 = _T_3692 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3694 = _T_3693 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3695 = _T_3694 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3696 = _T_3661 | _T_3695; // @[dec_dec_ctl.scala 253:114] + wire _T_3724 = _T_3688 & io_ins[13]; // @[dec_dec_ctl.scala 17:17] + wire _T_3725 = _T_3724 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3726 = _T_3725 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3727 = _T_3726 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3728 = _T_3727 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3729 = _T_3728 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3730 = _T_3729 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3731 = _T_3696 | _T_3730; // @[dec_dec_ctl.scala 254:63] + wire _T_3755 = _T_3206 & _T_90; // @[dec_dec_ctl.scala 17:17] + wire _T_3756 = _T_3755 & _T_3375; // @[dec_dec_ctl.scala 17:17] + wire _T_3757 = _T_3756 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_3758 = _T_3757 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3759 = _T_3758 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3760 = _T_3759 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_3761 = _T_3760 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_3762 = _T_3761 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3763 = _T_3762 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3764 = _T_3763 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3765 = _T_3764 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3766 = _T_3765 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3767 = _T_3731 | _T_3766; // @[dec_dec_ctl.scala 254:123] + wire _T_3788 = _T_3206 & _T_3375; // @[dec_dec_ctl.scala 17:17] + wire _T_3789 = _T_3788 & _T_23; // @[dec_dec_ctl.scala 17:17] + wire _T_3790 = _T_3789 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3791 = _T_3790 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3792 = _T_3791 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_3793 = _T_3792 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3794 = _T_3793 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3795 = _T_3794 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3796 = _T_3795 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3797 = _T_3796 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3798 = _T_3797 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3799 = _T_3767 | _T_3798; // @[dec_dec_ctl.scala 255:64] + wire _T_3825 = _T_3620 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_3826 = _T_3825 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_3827 = _T_3826 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3828 = _T_3827 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3829 = _T_3828 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3830 = _T_3829 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_3831 = _T_3830 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3832 = _T_3831 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3833 = _T_3799 | _T_3832; // @[dec_dec_ctl.scala 255:119] + wire _T_3857 = _T_3620 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_3858 = _T_3857 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3859 = _T_3858 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3860 = _T_3859 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3861 = _T_3860 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3862 = _T_3861 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3863 = _T_3862 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3864 = _T_3833 | _T_3863; // @[dec_dec_ctl.scala 256:61] + wire _T_3885 = _T_3206 & io_ins[30]; // @[dec_dec_ctl.scala 17:17] + wire _T_3886 = _T_3885 & _T_3375; // @[dec_dec_ctl.scala 17:17] + wire _T_3887 = _T_3886 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_3888 = _T_3887 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3889 = _T_3888 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3890 = _T_3889 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_3891 = _T_3890 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_3892 = _T_3891 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3893 = _T_3892 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3894 = _T_3893 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3895 = _T_3894 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3896 = _T_3895 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3897 = _T_3864 | _T_3896; // @[dec_dec_ctl.scala 256:115] + wire _T_3919 = _T_3472 & io_ins[27]; // @[dec_dec_ctl.scala 17:17] + wire _T_3920 = _T_3919 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_3921 = _T_3920 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_3922 = _T_3921 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3923 = _T_3922 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3924 = _T_3923 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3925 = _T_3924 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3926 = _T_3925 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3927 = _T_3926 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3928 = _T_3897 | _T_3927; // @[dec_dec_ctl.scala 257:61] + wire _T_3955 = _T_3688 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3956 = _T_3955 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_3957 = _T_3956 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3958 = _T_3957 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3959 = _T_3958 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3960 = _T_3959 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3961 = _T_3928 | _T_3960; // @[dec_dec_ctl.scala 257:116] + wire _T_3987 = _T_3424 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_3988 = _T_3987 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_3989 = _T_3988 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_3990 = _T_3989 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_3991 = _T_3990 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_3992 = _T_3991 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_3993 = _T_3961 | _T_3992; // @[dec_dec_ctl.scala 258:59] + wire _T_4010 = _T_444 & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_4011 = _T_4010 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4012 = _T_4011 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4013 = _T_4012 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4014 = _T_4013 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4015 = _T_4014 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4016 = _T_3993 | _T_4015; // @[dec_dec_ctl.scala 258:114] + wire _T_4038 = _T_3756 & _T_3215; // @[dec_dec_ctl.scala 17:17] + wire _T_4039 = _T_4038 & _T_32; // @[dec_dec_ctl.scala 17:17] + wire _T_4040 = _T_4039 & io_ins[14]; // @[dec_dec_ctl.scala 17:17] + wire _T_4041 = _T_4040 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_4042 = _T_4041 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4043 = _T_4042 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_4044 = _T_4043 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4045 = _T_4044 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4046 = _T_4045 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4047 = _T_4016 | _T_4046; // @[dec_dec_ctl.scala 259:46] + wire _T_4072 = _T_3474 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_4073 = _T_4072 & io_ins[12]; // @[dec_dec_ctl.scala 17:17] + wire _T_4074 = _T_4073 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4075 = _T_4074 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_4076 = _T_4075 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4077 = _T_4076 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4078 = _T_4077 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4079 = _T_4078 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4080 = _T_4047 | _T_4079; // @[dec_dec_ctl.scala 259:100] + wire _T_4092 = io_ins[14] & io_ins[6]; // @[dec_dec_ctl.scala 17:17] + wire _T_4093 = _T_4092 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4094 = _T_4093 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4095 = _T_4094 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4096 = _T_4095 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4097 = _T_4096 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4098 = _T_4097 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4099 = _T_4080 | _T_4098; // @[dec_dec_ctl.scala 260:60] + wire _T_4114 = _T_195 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4115 = _T_4114 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4116 = _T_4115 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4117 = _T_4116 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4118 = _T_4117 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4119 = _T_4118 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4120 = _T_4099 | _T_4119; // @[dec_dec_ctl.scala 260:97] + wire _T_4132 = _T_36 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_4133 = _T_4132 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_4134 = _T_4133 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_4135 = _T_4134 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4136 = _T_4135 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4137 = _T_4136 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4138 = _T_4120 | _T_4137; // @[dec_dec_ctl.scala 261:43] + wire _T_4152 = _T_1073 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4153 = _T_4152 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4154 = _T_4153 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4155 = _T_4154 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4156 = _T_4155 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4157 = _T_4138 | _T_4156; // @[dec_dec_ctl.scala 261:79] + wire _T_4226 = _T_3429 & _T_8; // @[dec_dec_ctl.scala 17:17] + wire _T_4227 = _T_4226 & _T_3227; // @[dec_dec_ctl.scala 17:17] + wire _T_4228 = _T_4227 & _T_3229; // @[dec_dec_ctl.scala 17:17] + wire _T_4229 = _T_4228 & _T_3231; // @[dec_dec_ctl.scala 17:17] + wire _T_4230 = _T_4229 & _T_3233; // @[dec_dec_ctl.scala 17:17] + wire _T_4231 = _T_4230 & _T_3235; // @[dec_dec_ctl.scala 17:17] + wire _T_4232 = _T_4231 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_4233 = _T_4232 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_4234 = _T_4233 & _T_3239; // @[dec_dec_ctl.scala 17:17] + wire _T_4235 = _T_4234 & _T_3241; // @[dec_dec_ctl.scala 17:17] + wire _T_4236 = _T_4235 & _T_3243; // @[dec_dec_ctl.scala 17:17] + wire _T_4237 = _T_4236 & _T_3245; // @[dec_dec_ctl.scala 17:17] + wire _T_4238 = _T_4237 & _T_3247; // @[dec_dec_ctl.scala 17:17] + wire _T_4239 = _T_4238 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_4240 = _T_4239 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_4241 = _T_4240 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4242 = _T_4241 & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_4243 = _T_4242 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_4244 = _T_4243 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4245 = _T_4244 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4246 = _T_4157 | _T_4245; // @[dec_dec_ctl.scala 261:117] + wire _T_4294 = _T_3422 & _T_3227; // @[dec_dec_ctl.scala 17:17] + wire _T_4295 = _T_4294 & _T_3229; // @[dec_dec_ctl.scala 17:17] + wire _T_4296 = _T_4295 & _T_3231; // @[dec_dec_ctl.scala 17:17] + wire _T_4297 = _T_4296 & _T_3233; // @[dec_dec_ctl.scala 17:17] + wire _T_4298 = _T_4297 & _T_3235; // @[dec_dec_ctl.scala 17:17] + wire _T_4299 = _T_4298 & _T_63; // @[dec_dec_ctl.scala 17:17] + wire _T_4300 = _T_4299 & _T_34; // @[dec_dec_ctl.scala 17:17] + wire _T_4301 = _T_4300 & _T_36; // @[dec_dec_ctl.scala 17:17] + wire _T_4302 = _T_4301 & _T_3239; // @[dec_dec_ctl.scala 17:17] + wire _T_4303 = _T_4302 & _T_3241; // @[dec_dec_ctl.scala 17:17] + wire _T_4304 = _T_4303 & _T_3243; // @[dec_dec_ctl.scala 17:17] + wire _T_4305 = _T_4304 & _T_3245; // @[dec_dec_ctl.scala 17:17] + wire _T_4306 = _T_4305 & _T_3247; // @[dec_dec_ctl.scala 17:17] + wire _T_4307 = _T_4306 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_4308 = _T_4307 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_4309 = _T_4308 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4310 = _T_4309 & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_4311 = _T_4310 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_4312 = _T_4311 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4313 = _T_4312 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4314 = _T_4246 | _T_4313; // @[dec_dec_ctl.scala 262:130] + wire _T_4326 = _T_806 & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4327 = _T_4326 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_4328 = _T_4327 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4329 = _T_4328 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4330 = _T_4329 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4331 = _T_4330 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4332 = _T_4314 | _T_4331; // @[dec_dec_ctl.scala 263:102] + wire _T_4341 = io_ins[6] & io_ins[5]; // @[dec_dec_ctl.scala 17:17] + wire _T_4342 = _T_4341 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4343 = _T_4342 & io_ins[3]; // @[dec_dec_ctl.scala 17:17] + wire _T_4344 = _T_4343 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_4345 = _T_4344 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4346 = _T_4345 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4347 = _T_4332 | _T_4346; // @[dec_dec_ctl.scala 264:39] + wire _T_4363 = _T_866 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_4364 = _T_4363 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4365 = _T_4364 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4366 = _T_4365 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4367 = _T_4366 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4368 = _T_4367 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4369 = _T_4347 | _T_4368; // @[dec_dec_ctl.scala 264:71] + wire _T_4384 = _T_34 & _T_279; // @[dec_dec_ctl.scala 17:17] + wire _T_4385 = _T_4384 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_4386 = _T_4385 & _T_273; // @[dec_dec_ctl.scala 17:17] + wire _T_4387 = _T_4386 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4388 = _T_4387 & _T_194; // @[dec_dec_ctl.scala 17:17] + wire _T_4389 = _T_4388 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4390 = _T_4389 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4391 = _T_4369 | _T_4390; // @[dec_dec_ctl.scala 264:112] + wire _T_4403 = _T_937 & _T_11; // @[dec_dec_ctl.scala 17:17] + wire _T_4404 = _T_4403 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_4405 = _T_4404 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4406 = _T_4405 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4407 = _T_4406 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + wire _T_4408 = _T_4391 | _T_4407; // @[dec_dec_ctl.scala 265:43] + wire _T_4417 = _T_279 & io_ins[4]; // @[dec_dec_ctl.scala 17:17] + wire _T_4418 = _T_4417 & _T_275; // @[dec_dec_ctl.scala 17:17] + wire _T_4419 = _T_4418 & io_ins[2]; // @[dec_dec_ctl.scala 17:17] + wire _T_4420 = _T_4419 & io_ins[1]; // @[dec_dec_ctl.scala 17:17] + wire _T_4421 = _T_4420 & io_ins[0]; // @[dec_dec_ctl.scala 17:17] + assign io_out_clz = _T_1808 & _T_194; // @[dec_dec_ctl.scala 144:14] + assign io_out_ctz = _T_1836 & _T_194; // @[dec_dec_ctl.scala 146:14] + assign io_out_pcnt = _T_1861 & _T_194; // @[dec_dec_ctl.scala 148:15] + assign io_out_sext_b = _T_1886 & _T_194; // @[dec_dec_ctl.scala 150:17] + assign io_out_sext_h = _T_1910 & _T_194; // @[dec_dec_ctl.scala 152:17] + assign io_out_slo = _T_1933 & _T_194; // @[dec_dec_ctl.scala 154:14] + assign io_out_sro = _T_1955 & _T_194; // @[dec_dec_ctl.scala 156:14] + assign io_out_min = _T_1971 & _T_194; // @[dec_dec_ctl.scala 158:14] + assign io_out_max = _T_1986 & _T_194; // @[dec_dec_ctl.scala 160:14] + assign io_out_pack = _T_2006 & _T_194; // @[dec_dec_ctl.scala 162:15] + assign io_out_packu = _T_2022 & _T_194; // @[dec_dec_ctl.scala 164:16] + assign io_out_packh = _T_2041 & _T_194; // @[dec_dec_ctl.scala 166:16] + assign io_out_rol = _T_2060 & _T_194; // @[dec_dec_ctl.scala 168:14] + assign io_out_ror = _T_2081 & _T_194; // @[dec_dec_ctl.scala 170:14] + assign io_out_grev = _T_2625 & _T_194; // @[dec_dec_ctl.scala 204:15] + assign io_out_gorc = _T_2646 & _T_194; // @[dec_dec_ctl.scala 206:15] + assign io_out_zbb = _T_2342 | _T_526; // @[dec_dec_ctl.scala 172:14] + assign io_out_sbset = _T_2377 & _T_194; // @[dec_dec_ctl.scala 180:16] + assign io_out_sbclr = _T_2397 & _T_194; // @[dec_dec_ctl.scala 182:16] + assign io_out_sbinv = _T_2418 & _T_194; // @[dec_dec_ctl.scala 184:16] + assign io_out_sbext = _T_2439 & _T_194; // @[dec_dec_ctl.scala 186:16] + assign io_out_zbs = _T_2459 | _T_2478; // @[dec_dec_ctl.scala 188:14] + assign io_out_bext = _T_2500 & _T_194; // @[dec_dec_ctl.scala 190:15] + assign io_out_bdep = _T_2518 & _T_194; // @[dec_dec_ctl.scala 192:15] + assign io_out_zbe = _T_1445 & _T_194; // @[dec_dec_ctl.scala 194:14] + assign io_out_clmul = _T_2556 & _T_194; // @[dec_dec_ctl.scala 196:16] + assign io_out_clmulh = _T_2572 & _T_194; // @[dec_dec_ctl.scala 198:17] + assign io_out_clmulr = _T_2589 & _T_194; // @[dec_dec_ctl.scala 200:17] + assign io_out_zbc = _T_2605 & _T_194; // @[dec_dec_ctl.scala 202:14] + assign io_out_shfl = _T_2672 & _T_194; // @[dec_dec_ctl.scala 208:15] + assign io_out_unshfl = _T_2697 & _T_194; // @[dec_dec_ctl.scala 210:17] + assign io_out_zbp = _T_2831 | _T_2847; // @[dec_dec_ctl.scala 212:14] + assign io_out_crc32_b = _T_2878 & _T_194; // @[dec_dec_ctl.scala 217:18] + assign io_out_crc32_h = _T_2905 & _T_194; // @[dec_dec_ctl.scala 219:18] + assign io_out_crc32_w = _T_2932 & _T_194; // @[dec_dec_ctl.scala 221:18] + assign io_out_crc32c_b = _T_2960 & _T_194; // @[dec_dec_ctl.scala 223:19] + assign io_out_crc32c_h = _T_2984 & _T_194; // @[dec_dec_ctl.scala 225:19] + assign io_out_crc32c_w = _T_3008 & _T_194; // @[dec_dec_ctl.scala 227:19] + assign io_out_zbr = _T_1641 & _T_194; // @[dec_dec_ctl.scala 229:14] + assign io_out_bfp = _T_3045 & _T_194; // @[dec_dec_ctl.scala 231:14] + assign io_out_zbf = _T_3045 & _T_194; // @[dec_dec_ctl.scala 233:14] + assign io_out_sh1add = _T_3077 & _T_194; // @[dec_dec_ctl.scala 235:17] + assign io_out_sh2add = _T_3093 & _T_194; // @[dec_dec_ctl.scala 237:17] + assign io_out_sh3add = _T_3106 & _T_194; // @[dec_dec_ctl.scala 239:17] + assign io_out_zba = _T_3120 & _T_194; // @[dec_dec_ctl.scala 241:14] + assign io_out_alu = _T_166 | _T_187; // @[dec_dec_ctl.scala 20:14] + assign io_out_rs1 = _T_277 | _T_282; // @[dec_dec_ctl.scala 27:14] + assign io_out_rs2 = _T_290 | _T_297; // @[dec_dec_ctl.scala 32:14] + assign io_out_imm12 = _T_325 | _T_335; // @[dec_dec_ctl.scala 34:16] + assign io_out_rd = _T_345 | io_ins[4]; // @[dec_dec_ctl.scala 36:13] + assign io_out_shimm5 = _T_377 | _T_391; // @[dec_dec_ctl.scala 38:17] + assign io_out_imm20 = _T_395 | _T_398; // @[dec_dec_ctl.scala 40:16] + assign io_out_pc = _T_406 | _T_395; // @[dec_dec_ctl.scala 42:13] + assign io_out_load = _T_417 & _T_194; // @[dec_dec_ctl.scala 44:15] + assign io_out_store = _T_296 & _T_273; // @[dec_dec_ctl.scala 46:16] + assign io_out_lsu = _T_432 & _T_194; // @[dec_dec_ctl.scala 48:14] + assign io_out_add = _T_454 | _T_476; // @[dec_dec_ctl.scala 50:14] + assign io_out_sub = _T_540 | _T_547; // @[dec_dec_ctl.scala 52:14] + assign io_out_land = _T_565 | _T_576; // @[dec_dec_ctl.scala 55:15] + assign io_out_lor = _T_619 | _T_631; // @[dec_dec_ctl.scala 57:14] + assign io_out_lxor = _T_653 | _T_668; // @[dec_dec_ctl.scala 60:15] + assign io_out_sll = _T_692 & _T_194; // @[dec_dec_ctl.scala 62:14] + assign io_out_sra = _T_712 & _T_194; // @[dec_dec_ctl.scala 64:14] + assign io_out_srl = _T_738 & _T_194; // @[dec_dec_ctl.scala 66:14] + assign io_out_slt = _T_512 | _T_539; // @[dec_dec_ctl.scala 68:14] + assign io_out_unsign = _T_833 | _T_848; // @[dec_dec_ctl.scala 70:17] + assign io_out_condbr = _T_546 & _T_194; // @[dec_dec_ctl.scala 74:17] + assign io_out_beq = _T_868 & _T_194; // @[dec_dec_ctl.scala 76:14] + assign io_out_bne = _T_880 & _T_194; // @[dec_dec_ctl.scala 78:14] + assign io_out_bge = _T_891 & _T_194; // @[dec_dec_ctl.scala 80:14] + assign io_out_blt = _T_903 & _T_194; // @[dec_dec_ctl.scala 82:14] + assign io_out_jal = io_ins[6] & io_ins[2]; // @[dec_dec_ctl.scala 84:14] + assign io_out_by = _T_920 & _T_194; // @[dec_dec_ctl.scala 86:13] + assign io_out_half = _T_930 & _T_194; // @[dec_dec_ctl.scala 88:15] + assign io_out_word = _T_937 & _T_273; // @[dec_dec_ctl.scala 90:15] + assign io_out_csr_read = _T_967 | _T_972; // @[dec_dec_ctl.scala 92:19] + assign io_out_csr_clr = _T_1012 | _T_1021; // @[dec_dec_ctl.scala 95:18] + assign io_out_csr_set = _T_1057 | _T_1065; // @[dec_dec_ctl.scala 98:18] + assign io_out_csr_write = _T_1073 & io_ins[4]; // @[dec_dec_ctl.scala 101:20] + assign io_out_csr_imm = _T_1114 | _T_1121; // @[dec_dec_ctl.scala 103:18] + assign io_out_presync = _T_1203 | _T_1210; // @[dec_dec_ctl.scala 106:18] + assign io_out_postsync = _T_1307 | _T_1210; // @[dec_dec_ctl.scala 111:19] + assign io_out_ebreak = _T_1328 & io_ins[4]; // @[dec_dec_ctl.scala 116:17] + assign io_out_ecall = _T_1343 & io_ins[4]; // @[dec_dec_ctl.scala 118:16] + assign io_out_mret = _T_1354 & io_ins[4]; // @[dec_dec_ctl.scala 120:15] + assign io_out_mul = _T_1643 | _T_1656; // @[dec_dec_ctl.scala 122:14] + assign io_out_rs1_sign = _T_1679 | _T_1699; // @[dec_dec_ctl.scala 130:19] + assign io_out_rs2_sign = _T_1698 & _T_194; // @[dec_dec_ctl.scala 132:19] + assign io_out_low = _T_1736 & _T_194; // @[dec_dec_ctl.scala 134:14] + assign io_out_div = _T_1750 & _T_194; // @[dec_dec_ctl.scala 136:14] + assign io_out_rem = _T_1766 & _T_194; // @[dec_dec_ctl.scala 138:14] + assign io_out_fence = _T_11 & io_ins[3]; // @[dec_dec_ctl.scala 140:16] + assign io_out_fence_i = _T_1216 & io_ins[3]; // @[dec_dec_ctl.scala 142:18] + assign io_out_pm_alu = _T_3196 | _T_122; // @[dec_dec_ctl.scala 243:17] + assign io_out_legal = _T_4408 | _T_4421; // @[dec_dec_ctl.scala 248:16] +endmodule +module rvclkhdr( + input io_clk, + input io_en +); + wire clkhdr_Q; // @[lib.scala 334:26] + wire clkhdr_CK; // @[lib.scala 334:26] + wire clkhdr_EN; // @[lib.scala 334:26] + wire clkhdr_SE; // @[lib.scala 334:26] + gated_latch clkhdr ( // @[lib.scala 334:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign clkhdr_CK = io_clk; // @[lib.scala 336:18] + assign clkhdr_EN = io_en; // @[lib.scala 337:18] + assign clkhdr_SE = 1'h0; // @[lib.scala 338:18] +endmodule +module dec_decode_ctl( + input clock, + input reset, + output [1:0] io_decode_exu_dec_data_en, + output [1:0] io_decode_exu_dec_ctl_en, + output io_decode_exu_i0_ap_clz, + output io_decode_exu_i0_ap_ctz, + output io_decode_exu_i0_ap_pcnt, + output io_decode_exu_i0_ap_sext_b, + output io_decode_exu_i0_ap_sext_h, + output io_decode_exu_i0_ap_slo, + output io_decode_exu_i0_ap_sro, + output io_decode_exu_i0_ap_min, + output io_decode_exu_i0_ap_max, + output io_decode_exu_i0_ap_pack, + output io_decode_exu_i0_ap_packu, + output io_decode_exu_i0_ap_packh, + output io_decode_exu_i0_ap_rol, + output io_decode_exu_i0_ap_ror, + output io_decode_exu_i0_ap_grev, + output io_decode_exu_i0_ap_gorc, + output io_decode_exu_i0_ap_zbb, + output io_decode_exu_i0_ap_sbset, + output io_decode_exu_i0_ap_sbclr, + output io_decode_exu_i0_ap_sbinv, + output io_decode_exu_i0_ap_sbext, + output io_decode_exu_i0_ap_sh1add, + output io_decode_exu_i0_ap_sh2add, + output io_decode_exu_i0_ap_sh3add, + output io_decode_exu_i0_ap_zba, + output io_decode_exu_i0_ap_land, + output io_decode_exu_i0_ap_lor, + output io_decode_exu_i0_ap_lxor, + output io_decode_exu_i0_ap_sll, + output io_decode_exu_i0_ap_srl, + output io_decode_exu_i0_ap_sra, + output io_decode_exu_i0_ap_beq, + output io_decode_exu_i0_ap_bne, + output io_decode_exu_i0_ap_blt, + output io_decode_exu_i0_ap_bge, + output io_decode_exu_i0_ap_add, + output io_decode_exu_i0_ap_sub, + output io_decode_exu_i0_ap_slt, + output io_decode_exu_i0_ap_unsign, + output io_decode_exu_i0_ap_jal, + output io_decode_exu_i0_ap_predict_t, + output io_decode_exu_i0_ap_predict_nt, + output io_decode_exu_i0_ap_csr_write, + output io_decode_exu_i0_ap_csr_imm, + output io_decode_exu_dec_i0_predict_p_d_valid, + output io_decode_exu_dec_i0_predict_p_d_bits_misp, + output io_decode_exu_dec_i0_predict_p_d_bits_ataken, + output io_decode_exu_dec_i0_predict_p_d_bits_boffset, + output io_decode_exu_dec_i0_predict_p_d_bits_pc4, + output [1:0] io_decode_exu_dec_i0_predict_p_d_bits_hist, + output [11:0] io_decode_exu_dec_i0_predict_p_d_bits_toffset, + output io_decode_exu_dec_i0_predict_p_d_bits_br_error, + output io_decode_exu_dec_i0_predict_p_d_bits_br_start_error, + output io_decode_exu_dec_i0_predict_p_d_bits_pcall, + output io_decode_exu_dec_i0_predict_p_d_bits_pja, + output io_decode_exu_dec_i0_predict_p_d_bits_way, + output io_decode_exu_dec_i0_predict_p_d_bits_pret, + output [30:0] io_decode_exu_dec_i0_predict_p_d_bits_prett, + output [7:0] io_decode_exu_i0_predict_fghr_d, + output [7:0] io_decode_exu_i0_predict_index_d, + output [4:0] io_decode_exu_i0_predict_btag_d, + output io_decode_exu_dec_i0_rs1_en_d, + output io_decode_exu_dec_i0_branch_d, + output io_decode_exu_dec_i0_rs2_en_d, + output [31:0] io_decode_exu_dec_i0_immed_d, + output [31:0] io_decode_exu_dec_i0_result_r, + output io_decode_exu_dec_i0_select_pc_d, + output [3:0] io_decode_exu_dec_i0_rs1_bypass_en_d, + output [3:0] io_decode_exu_dec_i0_rs2_bypass_en_d, + output io_decode_exu_mul_p_valid, + output io_decode_exu_mul_p_bits_rs1_sign, + output io_decode_exu_mul_p_bits_rs2_sign, + output io_decode_exu_mul_p_bits_low, + output io_decode_exu_mul_p_bits_bext, + output io_decode_exu_mul_p_bits_bdep, + output io_decode_exu_mul_p_bits_clmul, + output io_decode_exu_mul_p_bits_clmulh, + output io_decode_exu_mul_p_bits_clmulr, + output io_decode_exu_mul_p_bits_grev, + output io_decode_exu_mul_p_bits_gorc, + output io_decode_exu_mul_p_bits_shfl, + output io_decode_exu_mul_p_bits_unshfl, + output io_decode_exu_mul_p_bits_crc32_b, + output io_decode_exu_mul_p_bits_crc32_h, + output io_decode_exu_mul_p_bits_crc32_w, + output io_decode_exu_mul_p_bits_crc32c_b, + output io_decode_exu_mul_p_bits_crc32c_h, + output io_decode_exu_mul_p_bits_crc32c_w, + output io_decode_exu_mul_p_bits_bfp, + output [30:0] io_decode_exu_pred_correct_npc_x, + output io_decode_exu_dec_extint_stall, + input [31:0] io_decode_exu_exu_i0_result_x, + input [31:0] io_decode_exu_exu_csr_rs1_x, + output io_dec_alu_dec_i0_alu_decode_d, + output io_dec_alu_dec_csr_ren_d, + output [11:0] io_dec_alu_dec_i0_br_immed_d, + input [30:0] io_dec_alu_exu_i0_pc_x, + output io_dec_div_div_p_valid, + output io_dec_div_div_p_bits_unsign, + output io_dec_div_div_p_bits_rem, + output io_dec_div_dec_div_cancel, + input io_dctl_busbuff_lsu_nonblock_load_valid_m, + input [1:0] io_dctl_busbuff_lsu_nonblock_load_tag_m, + input io_dctl_busbuff_lsu_nonblock_load_inv_r, + input [1:0] io_dctl_busbuff_lsu_nonblock_load_inv_tag_r, + input io_dctl_busbuff_lsu_nonblock_load_data_valid, + input io_dctl_busbuff_lsu_nonblock_load_data_error, + input [1:0] io_dctl_busbuff_lsu_nonblock_load_data_tag, + input [31:0] io_dctl_busbuff_lsu_nonblock_load_data, + input io_dctl_dma_dma_dccm_stall_any, + output io_dec_aln_dec_i0_decode_d, + input [15:0] io_dec_aln_ifu_i0_cinst, + input [31:0] io_dbg_dctl_dbg_cmd_wrdata, + input io_dec_tlu_trace_disable, + input io_dec_debug_valid_d, + input io_dec_tlu_flush_extint, + input io_dec_tlu_force_halt, + output [31:0] io_dec_i0_inst_wb, + output [30:0] io_dec_i0_pc_wb, + input [3:0] io_dec_i0_trigger_match_d, + input io_dec_tlu_wr_pause_r, + input io_dec_tlu_pipelining_disable, + input [3:0] io_lsu_trigger_match_m, + input io_lsu_pmu_misaligned_m, + input io_dec_tlu_debug_stall, + input io_dec_tlu_flush_leak_one_r, + input io_dec_debug_fence_d, + input io_dec_i0_icaf_d, + input io_dec_i0_icaf_second_d, + input [1:0] io_dec_i0_icaf_type_d, + input io_dec_i0_dbecc_d, + input io_dec_i0_brp_valid, + input [11:0] io_dec_i0_brp_bits_toffset, + input [1:0] io_dec_i0_brp_bits_hist, + input io_dec_i0_brp_bits_br_error, + input io_dec_i0_brp_bits_br_start_error, + input io_dec_i0_brp_bits_bank, + input [30:0] io_dec_i0_brp_bits_prett, + input io_dec_i0_brp_bits_way, + input io_dec_i0_brp_bits_ret, + input [7:0] io_dec_i0_bp_index, + input [7:0] io_dec_i0_bp_fghr, + input [4:0] io_dec_i0_bp_btag, + input [8:0] io_dec_i0_bp_fa_index, + input io_lsu_idle_any, + input io_lsu_load_stall_any, + input io_lsu_store_stall_any, + input io_exu_div_wren, + input io_dec_tlu_i0_kill_writeb_wb, + input io_dec_tlu_flush_lower_wb, + input io_dec_tlu_i0_kill_writeb_r, + input io_dec_tlu_flush_lower_r, + input io_dec_tlu_flush_pause_r, + input io_dec_tlu_presync_d, + input io_dec_tlu_postsync_d, + input io_dec_i0_pc4_d, + input [31:0] io_dec_csr_rddata_d, + input io_dec_csr_legal_d, + input [31:0] io_lsu_result_m, + input [31:0] io_lsu_result_corr_r, + input io_exu_flush_final, + input [31:0] io_dec_i0_instr_d, + input io_dec_ib0_valid_d, + input io_active_clk, + input io_free_l2clk, + input io_clk_override, + output [4:0] io_dec_i0_rs1_d, + output [4:0] io_dec_i0_rs2_d, + output [4:0] io_dec_i0_waddr_r, + output io_dec_i0_wen_r, + output [31:0] io_dec_i0_wdata_r, + output io_dec_qual_lsu_d, + output io_lsu_p_valid, + output io_lsu_p_bits_fast_int, + output io_lsu_p_bits_stack, + output io_lsu_p_bits_by, + output io_lsu_p_bits_half, + output io_lsu_p_bits_word, + output io_lsu_p_bits_dword, + output io_lsu_p_bits_load, + output io_lsu_p_bits_store, + output io_lsu_p_bits_unsign, + output io_lsu_p_bits_dma, + output io_lsu_p_bits_store_data_bypass_d, + output io_lsu_p_bits_load_ldst_bypass_d, + output io_lsu_p_bits_store_data_bypass_m, + output [4:0] io_div_waddr_wb, + output io_dec_lsu_valid_raw_d, + output [11:0] io_dec_lsu_offset_d, + output io_dec_csr_wen_unq_d, + output io_dec_csr_any_unq_d, + output [11:0] io_dec_csr_rdaddr_d, + output io_dec_csr_wen_r, + output [11:0] io_dec_csr_wraddr_r, + output [31:0] io_dec_csr_wrdata_r, + output io_dec_csr_stall_int_ff, + output io_dec_tlu_i0_valid_r, + output io_dec_tlu_packet_r_legal, + output io_dec_tlu_packet_r_icaf, + output io_dec_tlu_packet_r_icaf_second, + output [1:0] io_dec_tlu_packet_r_icaf_type, + output io_dec_tlu_packet_r_fence_i, + output [3:0] io_dec_tlu_packet_r_i0trigger, + output [3:0] io_dec_tlu_packet_r_pmu_i0_itype, + output io_dec_tlu_packet_r_pmu_i0_br_unpred, + output io_dec_tlu_packet_r_pmu_divide, + output io_dec_tlu_packet_r_pmu_lsu_misaligned, + output [30:0] io_dec_tlu_i0_pc_r, + output [31:0] io_dec_illegal_inst, + output [8:0] io_dec_fa_error_index, + output io_dec_pmu_instr_decoded, + output io_dec_pmu_decode_stall, + output io_dec_pmu_presync_stall, + output io_dec_pmu_postsync_stall, + output io_dec_nonblock_load_wen, + output [4:0] io_dec_nonblock_load_waddr, + output io_dec_pause_state, + output io_dec_pause_state_cg, + output io_dec_div_active, + input io_scan_mode +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [31:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; + reg [31:0] _RAND_75; + reg [31:0] _RAND_76; + reg [31:0] _RAND_77; + reg [31:0] _RAND_78; + reg [31:0] _RAND_79; + reg [31:0] _RAND_80; + reg [31:0] _RAND_81; + reg [31:0] _RAND_82; + reg [31:0] _RAND_83; + reg [31:0] _RAND_84; + reg [31:0] _RAND_85; + reg [31:0] _RAND_86; + reg [31:0] _RAND_87; + reg [31:0] _RAND_88; + reg [31:0] _RAND_89; +`endif // RANDOMIZE_REG_INIT + wire [31:0] i0_dec_io_ins; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_clz; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_ctz; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_pcnt; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sext_b; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sext_h; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_slo; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sro; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_min; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_max; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_pack; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_packu; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_packh; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_rol; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_ror; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_grev; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_gorc; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_zbb; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sbset; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sbclr; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sbinv; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sbext; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_zbs; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_bext; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_bdep; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_zbe; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_clmul; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_clmulh; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_clmulr; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_zbc; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_shfl; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_unshfl; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_zbp; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_crc32_b; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_crc32_h; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_crc32_w; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_crc32c_b; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_crc32c_h; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_crc32c_w; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_zbr; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_bfp; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_zbf; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sh1add; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sh2add; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sh3add; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_zba; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_alu; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_rd; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_pc; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_load; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_store; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_add; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sub; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_land; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_lor; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sll; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_sra; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_srl; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_slt; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_beq; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_bne; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_bge; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_blt; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_jal; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_by; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_half; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_word; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_presync; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_mret; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_mul; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_low; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_div; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_rem; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_fence; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 438:22] + wire i0_dec_io_out_legal; // @[dec_decode_ctl.scala 438:22] + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_4_io_en; // @[lib.scala 404:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_5_io_en; // @[lib.scala 404:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_6_io_en; // @[lib.scala 404:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_7_io_en; // @[lib.scala 404:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_8_io_en; // @[lib.scala 404:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_9_io_en; // @[lib.scala 404:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_10_io_en; // @[lib.scala 404:23] + reg leak1_i1_stall; // @[Reg.scala 27:20] + wire _T_367 = ~io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 445:73] + wire _T_368 = leak1_i1_stall & _T_367; // @[dec_decode_ctl.scala 445:71] + wire leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_368; // @[dec_decode_ctl.scala 445:53] + wire _T_2 = leak1_i1_stall_in ^ leak1_i1_stall; // @[lib.scala 448:21] + wire _T_3 = |_T_2; // @[lib.scala 448:29] + wire _T_370 = io_dec_aln_dec_i0_decode_d & leak1_i1_stall; // @[dec_decode_ctl.scala 447:53] + reg leak1_i0_stall; // @[Reg.scala 27:20] + wire _T_372 = leak1_i0_stall & _T_367; // @[dec_decode_ctl.scala 447:89] + wire leak1_i0_stall_in = _T_370 | _T_372; // @[dec_decode_ctl.scala 447:71] + wire _T_6 = leak1_i0_stall_in ^ leak1_i0_stall; // @[lib.scala 448:21] + wire _T_7 = |_T_6; // @[lib.scala 448:29] + reg _T_12; // @[Reg.scala 27:20] + wire _T_10 = io_dec_tlu_flush_extint ^ _T_12; // @[lib.scala 470:21] + wire _T_11 = |_T_10; // @[lib.scala 470:29] + reg pause_stall; // @[Reg.scala 27:20] + wire _T_514 = io_dec_tlu_wr_pause_r | pause_stall; // @[dec_decode_ctl.scala 559:44] + wire _T_507 = ~io_dec_tlu_flush_pause_r; // @[dec_decode_ctl.scala 558:49] + wire _T_508 = io_dec_tlu_flush_lower_r & _T_507; // @[dec_decode_ctl.scala 558:47] + reg [31:0] write_csr_data; // @[Reg.scala 27:20] + wire [31:0] _T_511 = {31'h0,write_csr_data[0]}; // @[Cat.scala 29:58] + wire _T_512 = write_csr_data == _T_511; // @[dec_decode_ctl.scala 558:109] + wire _T_513 = pause_stall & _T_512; // @[dec_decode_ctl.scala 558:91] + wire clear_pause = _T_508 | _T_513; // @[dec_decode_ctl.scala 558:76] + wire _T_515 = ~clear_pause; // @[dec_decode_ctl.scala 559:61] + wire pause_state_in = _T_514 & _T_515; // @[dec_decode_ctl.scala 559:59] + wire _T_14 = pause_state_in ^ pause_stall; // @[lib.scala 470:21] + wire _T_15 = |_T_14; // @[lib.scala 470:29] + reg tlu_wr_pause_r1; // @[Reg.scala 27:20] + wire _T_18 = io_dec_tlu_wr_pause_r ^ tlu_wr_pause_r1; // @[lib.scala 470:21] + wire _T_19 = |_T_18; // @[lib.scala 470:29] + reg tlu_wr_pause_r2; // @[Reg.scala 27:20] + wire _T_22 = tlu_wr_pause_r1 ^ tlu_wr_pause_r2; // @[lib.scala 448:21] + wire _T_23 = |_T_22; // @[lib.scala 448:29] + wire _T_50 = ~leak1_i1_stall; // @[dec_decode_ctl.scala 222:82] + wire _T_51 = io_dec_i0_brp_valid & _T_50; // @[dec_decode_ctl.scala 222:80] + wire i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[dec_decode_ctl.scala 220:43] + wire _T_52 = ~i0_icaf_d; // @[dec_decode_ctl.scala 222:96] + wire i0_brp_valid = _T_51 & _T_52; // @[dec_decode_ctl.scala 222:94] + wire i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_jal = i0_dec_io_out_jal; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire [19:0] i0_pcall_imm = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21]}; // @[Cat.scala 29:58] + wire _T_383 = i0_pcall_imm[19:12] == 8'hff; // @[dec_decode_ctl.scala 452:79] + wire _T_385 = i0_pcall_imm[19:12] == 8'h0; // @[dec_decode_ctl.scala 452:112] + wire i0_pcall_12b_offset = i0_pcall_imm[11] ? _T_383 : _T_385; // @[dec_decode_ctl.scala 452:33] + wire i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire _T_386 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[dec_decode_ctl.scala 453:47] + wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[dec_decode_ctl.scala 678:16] + wire _T_387 = i0r_rd == 5'h1; // @[dec_decode_ctl.scala 453:76] + wire _T_388 = i0r_rd == 5'h5; // @[dec_decode_ctl.scala 453:98] + wire _T_389 = _T_387 | _T_388; // @[dec_decode_ctl.scala 453:89] + wire i0_pcall_case = _T_386 & _T_389; // @[dec_decode_ctl.scala 453:65] + wire i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[dec_decode_ctl.scala 455:38] + wire _T_55 = i0_dp_raw_condbr | i0_pcall_raw; // @[dec_decode_ctl.scala 233:94] + wire _T_394 = ~_T_389; // @[dec_decode_ctl.scala 454:67] + wire i0_pja_case = _T_386 & _T_394; // @[dec_decode_ctl.scala 454:65] + wire i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[dec_decode_ctl.scala 457:38] + wire _T_56 = _T_55 | i0_pja_raw; // @[dec_decode_ctl.scala 233:109] + wire i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire _T_410 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[dec_decode_ctl.scala 461:37] + wire _T_411 = i0r_rd == 5'h0; // @[dec_decode_ctl.scala 461:65] + wire _T_412 = _T_410 & _T_411; // @[dec_decode_ctl.scala 461:55] + wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 676:16] + wire _T_413 = i0r_rs1 == 5'h1; // @[dec_decode_ctl.scala 461:89] + wire _T_414 = i0r_rs1 == 5'h5; // @[dec_decode_ctl.scala 461:111] + wire _T_415 = _T_413 | _T_414; // @[dec_decode_ctl.scala 461:101] + wire i0_pret_case = _T_412 & _T_415; // @[dec_decode_ctl.scala 461:79] + wire i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[dec_decode_ctl.scala 462:32] + wire _T_57 = _T_56 | i0_pret_raw; // @[dec_decode_ctl.scala 233:122] + wire _T_58 = ~_T_57; // @[dec_decode_ctl.scala 233:75] + wire _T_59 = i0_brp_valid & _T_58; // @[dec_decode_ctl.scala 233:73] + wire _T_68 = io_dec_i0_brp_bits_br_error | _T_59; // @[dec_decode_ctl.scala 238:89] + wire _T_61 = i0_brp_valid & io_dec_i0_brp_bits_hist[1]; // @[dec_decode_ctl.scala 236:74] + wire _T_399 = i0_pcall_raw | i0_pja_raw; // @[dec_decode_ctl.scala 459:41] + wire [11:0] _T_408 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[7],io_dec_i0_instr_d[30:25],io_dec_i0_instr_d[11:8]}; // @[Cat.scala 29:58] + wire [11:0] i0_br_offset = _T_399 ? i0_pcall_imm[11:0] : _T_408; // @[dec_decode_ctl.scala 459:26] + wire _T_62 = io_dec_i0_brp_bits_toffset != i0_br_offset; // @[dec_decode_ctl.scala 236:133] + wire _T_63 = _T_61 & _T_62; // @[dec_decode_ctl.scala 236:103] + wire _T_64 = ~i0_pret_raw; // @[dec_decode_ctl.scala 236:153] + wire _T_65 = _T_63 & _T_64; // @[dec_decode_ctl.scala 236:151] + wire _T_69 = _T_68 | _T_65; // @[dec_decode_ctl.scala 238:106] + wire _T_66 = io_dec_i0_brp_bits_ret ^ i0_pret_raw; // @[dec_decode_ctl.scala 237:100] + wire _T_67 = i0_brp_valid & _T_66; // @[dec_decode_ctl.scala 237:74] + wire _T_70 = _T_69 | _T_67; // @[dec_decode_ctl.scala 238:128] + wire _T_77 = _T_70 | io_dec_i0_brp_bits_br_start_error; // @[dec_decode_ctl.scala 243:74] + wire i0_br_error_all = _T_77 & _T_50; // @[dec_decode_ctl.scala 243:111] + wire _T_80 = i0_br_error_all | i0_icaf_d; // @[dec_decode_ctl.scala 280:25] + wire i0_dp_raw_legal = i0_dec_io_out_legal; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_legal = _T_80 | i0_dp_raw_legal; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_csr_read = _T_80 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_csr_write = _T_80 ? 1'h0 : i0_dp_raw_csr_write; // @[dec_decode_ctl.scala 280:50] + wire _T_429 = ~io_dec_debug_fence_d; // @[dec_decode_ctl.scala 519:42] + wire i0_csr_write = i0_dp_csr_write & _T_429; // @[dec_decode_ctl.scala 519:40] + wire any_csr_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 527:34] + wire _T_544 = ~any_csr_d; // @[dec_decode_ctl.scala 590:40] + wire _T_545 = _T_544 | io_dec_csr_legal_d; // @[dec_decode_ctl.scala 590:51] + wire i0_legal = i0_dp_legal & _T_545; // @[dec_decode_ctl.scala 590:37] + wire _T_563 = ~i0_legal; // @[dec_decode_ctl.scala 594:57] + wire shift_illegal = io_dec_aln_dec_i0_decode_d & _T_563; // @[dec_decode_ctl.scala 594:55] + reg illegal_lockout; // @[Reg.scala 27:20] + wire _T_566 = shift_illegal | illegal_lockout; // @[dec_decode_ctl.scala 597:40] + reg flush_final_r; // @[Reg.scala 27:20] + wire _T_567 = ~flush_final_r; // @[dec_decode_ctl.scala 597:61] + wire illegal_lockout_in = _T_566 & _T_567; // @[dec_decode_ctl.scala 597:59] + wire _T_26 = illegal_lockout_in ^ illegal_lockout; // @[lib.scala 448:21] + wire _T_27 = |_T_26; // @[lib.scala 448:29] + wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_postsync = _T_80 | i0_dp_raw_postsync; // @[dec_decode_ctl.scala 280:50] + wire _T_539 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[dec_decode_ctl.scala 586:36] + wire debug_fence_i = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[0]; // @[dec_decode_ctl.scala 578:48] + wire _T_540 = _T_539 | debug_fence_i; // @[dec_decode_ctl.scala 586:60] + wire _T_433 = ~i0_dp_csr_read; // @[dec_decode_ctl.scala 524:41] + wire i0_csr_write_only_d = i0_csr_write & _T_433; // @[dec_decode_ctl.scala 524:39] + wire _T_542 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[dec_decode_ctl.scala 586:112] + wire _T_543 = i0_csr_write_only_d & _T_542; // @[dec_decode_ctl.scala 586:99] + wire i0_postsync = _T_540 | _T_543; // @[dec_decode_ctl.scala 586:76] + wire _T_605 = i0_postsync | _T_563; // @[dec_decode_ctl.scala 628:62] + wire _T_606 = io_dec_aln_dec_i0_decode_d & _T_605; // @[dec_decode_ctl.scala 628:47] + reg postsync_stall; // @[Reg.scala 27:20] + reg x_d_valid; // @[Reg.scala 27:20] + wire _T_607 = postsync_stall & x_d_valid; // @[dec_decode_ctl.scala 628:96] + wire ps_stall_in = _T_606 | _T_607; // @[dec_decode_ctl.scala 628:77] + wire _T_30 = ps_stall_in ^ postsync_stall; // @[lib.scala 448:21] + wire _T_31 = |_T_30; // @[lib.scala 448:29] + reg [3:0] lsu_trigger_match_r; // @[Reg.scala 27:20] + wire [3:0] _T_33 = io_lsu_trigger_match_m ^ lsu_trigger_match_r; // @[lib.scala 448:21] + wire _T_34 = |_T_33; // @[lib.scala 448:29] + reg lsu_pmu_misaligned_r; // @[Reg.scala 27:20] + wire _T_36 = io_lsu_pmu_misaligned_m ^ lsu_pmu_misaligned_r; // @[lib.scala 470:21] + wire _T_37 = |_T_36; // @[lib.scala 470:29] + wire i0_legal_decode_d = io_dec_aln_dec_i0_decode_d & i0_legal; // @[dec_decode_ctl.scala 756:54] + wire i0_dp_raw_div = i0_dec_io_out_div; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_div = _T_80 ? 1'h0 : i0_dp_raw_div; // @[dec_decode_ctl.scala 280:50] + wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 843:55] + wire _T_934 = ~io_exu_div_wren; // @[dec_decode_ctl.scala 845:59] + wire _T_935 = io_dec_div_active & _T_934; // @[dec_decode_ctl.scala 845:57] + reg x_d_bits_i0div; // @[Reg.scala 27:20] + wire _T_918 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 833:48] + reg [4:0] x_d_bits_i0rd; // @[Reg.scala 27:20] + wire _T_919 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 833:77] + wire _T_920 = _T_918 & _T_919; // @[dec_decode_ctl.scala 833:60] + wire _T_922 = _T_918 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 834:33] + wire _T_923 = _T_920 | _T_922; // @[dec_decode_ctl.scala 833:94] + reg r_d_bits_i0div; // @[Reg.scala 27:20] + reg r_d_valid; // @[Reg.scala 27:20] + wire _T_924 = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 835:21] + wire _T_925 = _T_924 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 835:33] + wire _T_926 = _T_925 & io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 835:60] + wire div_flush = _T_923 | _T_926; // @[dec_decode_ctl.scala 834:62] + wire _T_927 = io_dec_div_active & div_flush; // @[dec_decode_ctl.scala 839:51] + wire div_e1_to_r = _T_918 | _T_924; // @[dec_decode_ctl.scala 831:58] + wire _T_928 = ~div_e1_to_r; // @[dec_decode_ctl.scala 840:26] + wire _T_929 = io_dec_div_active & _T_928; // @[dec_decode_ctl.scala 840:24] + reg [4:0] r_d_bits_i0rd; // @[Reg.scala 27:20] + wire _T_930 = r_d_bits_i0rd == io_div_waddr_wb; // @[dec_decode_ctl.scala 840:56] + wire _T_931 = _T_929 & _T_930; // @[dec_decode_ctl.scala 840:39] + reg r_d_bits_i0v; // @[Reg.scala 27:20] + wire _T_857 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 798:51] + wire r_d_in_bits_i0v = r_d_bits_i0v & _T_857; // @[dec_decode_ctl.scala 798:49] + wire _T_868 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 806:47] + wire i0_wen_r = r_d_in_bits_i0v & _T_868; // @[dec_decode_ctl.scala 806:45] + wire _T_932 = _T_931 & i0_wen_r; // @[dec_decode_ctl.scala 840:77] + wire nonblock_div_cancel = _T_927 | _T_932; // @[dec_decode_ctl.scala 839:65] + wire _T_936 = ~nonblock_div_cancel; // @[dec_decode_ctl.scala 845:78] + wire _T_937 = _T_935 & _T_936; // @[dec_decode_ctl.scala 845:76] + wire div_active_in = i0_div_decode_d | _T_937; // @[dec_decode_ctl.scala 845:36] + reg _T_42; // @[Reg.scala 27:20] + wire _T_40 = div_active_in ^ _T_42; // @[lib.scala 470:21] + wire _T_41 = |_T_40; // @[lib.scala 470:29] + wire _T_44 = io_exu_flush_final ^ flush_final_r; // @[lib.scala 470:21] + wire _T_45 = |_T_44; // @[lib.scala 470:29] + reg debug_valid_x; // @[Reg.scala 27:20] + wire _T_47 = io_dec_debug_valid_d ^ debug_valid_x; // @[lib.scala 470:21] + wire _T_48 = |_T_47; // @[lib.scala 470:29] + wire _T_71 = _T_70 & i0_legal_decode_d; // @[dec_decode_ctl.scala 239:74] + wire _T_74 = io_dec_i0_brp_bits_br_start_error & i0_legal_decode_d; // @[dec_decode_ctl.scala 240:96] + wire i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_pm_alu = _T_80 ? 1'h0 : i0_dp_raw_pm_alu; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_fence_i = _T_80 ? 1'h0 : i0_dp_raw_fence_i; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_fence = i0_dec_io_out_fence; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_fence = _T_80 ? 1'h0 : i0_dp_raw_fence; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_rem = i0_dec_io_out_rem; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_low = i0_dec_io_out_low; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_mul = i0_dec_io_out_mul; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_mul = _T_80 ? 1'h0 : i0_dp_raw_mul; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_mret = i0_dec_io_out_mret; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_mret = _T_80 ? 1'h0 : i0_dp_raw_mret; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_ecall = _T_80 ? 1'h0 : i0_dp_raw_ecall; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_ebreak = _T_80 ? 1'h0 : i0_dp_raw_ebreak; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_presync = i0_dec_io_out_presync; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_presync = _T_80 ? 1'h0 : i0_dp_raw_presync; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_csr_imm = _T_80 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_csr_set = _T_80 ? 1'h0 : i0_dp_raw_csr_set; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_csr_clr = _T_80 ? 1'h0 : i0_dp_raw_csr_clr; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_word = i0_dec_io_out_word; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_word = _T_80 ? 1'h0 : i0_dp_raw_word; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_half = i0_dec_io_out_half; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_half = _T_80 ? 1'h0 : i0_dp_raw_half; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_by = i0_dec_io_out_by; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_by = _T_80 ? 1'h0 : i0_dp_raw_by; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_jal = _T_80 ? 1'h0 : i0_dp_raw_jal; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_blt = i0_dec_io_out_blt; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_bge = i0_dec_io_out_bge; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_bne = i0_dec_io_out_bne; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_beq = i0_dec_io_out_beq; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_condbr = _T_80 ? 1'h0 : i0_dp_raw_condbr; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_unsign = _T_80 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_slt = i0_dec_io_out_slt; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_srl = i0_dec_io_out_srl; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sra = i0_dec_io_out_sra; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sll = i0_dec_io_out_sll; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_lor = i0_dec_io_out_lor; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_land = i0_dec_io_out_land; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sub = i0_dec_io_out_sub; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_add = i0_dec_io_out_add; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_lsu = _T_80 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_store = i0_dec_io_out_store; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_store = _T_80 ? 1'h0 : i0_dp_raw_store; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_load = i0_dec_io_out_load; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_load = _T_80 ? 1'h0 : i0_dp_raw_load; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_pc = i0_dec_io_out_pc; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_imm20 = _T_80 ? 1'h0 : i0_dp_raw_imm20; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_shimm5 = _T_80 ? 1'h0 : i0_dp_raw_shimm5; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_rd = i0_dec_io_out_rd; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_rd = _T_80 ? 1'h0 : i0_dp_raw_rd; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_imm12 = _T_80 ? 1'h0 : i0_dp_raw_imm12; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_rs2 = _T_80 | i0_dp_raw_rs2; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_rs1 = _T_80 | i0_dp_raw_rs1; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_alu = i0_dec_io_out_alu; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_alu = _T_80 | i0_dp_raw_alu; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_zba = i0_dec_io_out_zba; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_zba = _T_80 ? 1'h0 : i0_dp_raw_zba; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_sh3add = i0_dec_io_out_sh3add; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sh2add = i0_dec_io_out_sh2add; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sh1add = i0_dec_io_out_sh1add; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_zbf = i0_dec_io_out_zbf; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_zbf = _T_80 ? 1'h0 : i0_dp_raw_zbf; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_bfp = i0_dec_io_out_bfp; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_zbr = i0_dec_io_out_zbr; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_zbr = _T_80 ? 1'h0 : i0_dp_raw_zbr; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_crc32c_w = i0_dec_io_out_crc32c_w; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_crc32c_h = i0_dec_io_out_crc32c_h; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_crc32c_b = i0_dec_io_out_crc32c_b; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_crc32_w = i0_dec_io_out_crc32_w; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_crc32_h = i0_dec_io_out_crc32_h; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_crc32_b = i0_dec_io_out_crc32_b; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_zbp = i0_dec_io_out_zbp; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_zbp = _T_80 ? 1'h0 : i0_dp_raw_zbp; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_unshfl = i0_dec_io_out_unshfl; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_shfl = i0_dec_io_out_shfl; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_zbc = i0_dec_io_out_zbc; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_zbc = _T_80 ? 1'h0 : i0_dp_raw_zbc; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_clmulr = i0_dec_io_out_clmulr; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_clmulh = i0_dec_io_out_clmulh; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_clmul = i0_dec_io_out_clmul; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_zbe = i0_dec_io_out_zbe; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_zbe = _T_80 ? 1'h0 : i0_dp_raw_zbe; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_bdep = i0_dec_io_out_bdep; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_bext = i0_dec_io_out_bext; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_zbs = i0_dec_io_out_zbs; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_zbs = _T_80 ? 1'h0 : i0_dp_raw_zbs; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_sbext = i0_dec_io_out_sbext; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sbinv = i0_dec_io_out_sbinv; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sbclr = i0_dec_io_out_sbclr; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sbset = i0_dec_io_out_sbset; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_zbb = i0_dec_io_out_zbb; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_zbb = _T_80 ? 1'h0 : i0_dp_raw_zbb; // @[dec_decode_ctl.scala 280:50] + wire i0_dp_raw_gorc = i0_dec_io_out_gorc; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_grev = i0_dec_io_out_grev; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_ror = i0_dec_io_out_ror; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_rol = i0_dec_io_out_rol; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_packh = i0_dec_io_out_packh; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_packu = i0_dec_io_out_packu; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_pack = i0_dec_io_out_pack; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_max = i0_dec_io_out_max; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_min = i0_dec_io_out_min; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sro = i0_dec_io_out_sro; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_slo = i0_dec_io_out_slo; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sext_h = i0_dec_io_out_sext_h; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_sext_b = i0_dec_io_out_sext_b; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_pcnt = i0_dec_io_out_pcnt; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_ctz = i0_dec_io_out_ctz; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_dp_raw_clz = i0_dec_io_out_clz; // @[dec_decode_ctl.scala 146:37 dec_decode_ctl.scala 440:12] + wire i0_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 456:38] + wire _T_83 = i0_dp_condbr | i0_pcall; // @[dec_decode_ctl.scala 294:54] + wire i0_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 458:38] + wire _T_84 = _T_83 | i0_pja; // @[dec_decode_ctl.scala 294:65] + wire i0_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 463:32] + wire i0_predict_br = _T_84 | i0_pret; // @[dec_decode_ctl.scala 294:74] + wire _T_86 = io_dec_i0_brp_bits_hist[1] & i0_brp_valid; // @[dec_decode_ctl.scala 295:69] + wire _T_87 = ~_T_86; // @[dec_decode_ctl.scala 295:40] + wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 297:40] + wire cam_data_reset = io_dctl_busbuff_lsu_nonblock_load_data_valid | io_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec_decode_ctl.scala 356:76] + reg [2:0] cam_raw_0_bits_tag; // @[Reg.scala 27:20] + wire [2:0] _GEN_256 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_data_tag}; // @[dec_decode_ctl.scala 367:67] + wire _T_133 = _GEN_256 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 367:67] + wire _T_134 = cam_data_reset & _T_133; // @[dec_decode_ctl.scala 367:45] + reg cam_raw_0_valid; // @[Reg.scala 27:20] + wire cam_data_reset_val_0 = _T_134 & cam_raw_0_valid; // @[dec_decode_ctl.scala 367:88] + wire cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[dec_decode_ctl.scala 371:39] + wire _T_90 = ~cam_0_valid; // @[dec_decode_ctl.scala 348:78] + reg [2:0] cam_raw_1_bits_tag; // @[Reg.scala 27:20] + wire _T_169 = _GEN_256 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 367:67] + wire _T_170 = cam_data_reset & _T_169; // @[dec_decode_ctl.scala 367:45] + reg cam_raw_1_valid; // @[Reg.scala 27:20] + wire cam_data_reset_val_1 = _T_170 & cam_raw_1_valid; // @[dec_decode_ctl.scala 367:88] + wire cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[dec_decode_ctl.scala 371:39] + wire _T_93 = ~cam_1_valid; // @[dec_decode_ctl.scala 348:78] + wire _T_96 = cam_0_valid & _T_93; // @[dec_decode_ctl.scala 348:126] + wire [1:0] _T_98 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 1'h0}; // @[dec_decode_ctl.scala 348:158] + reg [2:0] cam_raw_2_bits_tag; // @[Reg.scala 27:20] + wire _T_205 = _GEN_256 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 367:67] + wire _T_206 = cam_data_reset & _T_205; // @[dec_decode_ctl.scala 367:45] + reg cam_raw_2_valid; // @[Reg.scala 27:20] + wire cam_data_reset_val_2 = _T_206 & cam_raw_2_valid; // @[dec_decode_ctl.scala 367:88] + wire cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[dec_decode_ctl.scala 371:39] + wire _T_99 = ~cam_2_valid; // @[dec_decode_ctl.scala 348:78] + wire _T_102 = cam_0_valid & cam_1_valid; // @[dec_decode_ctl.scala 348:126] + wire _T_105 = _T_102 & _T_99; // @[dec_decode_ctl.scala 348:126] + wire [2:0] _T_107 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 2'h0}; // @[dec_decode_ctl.scala 348:158] + reg [2:0] cam_raw_3_bits_tag; // @[Reg.scala 27:20] + wire _T_241 = _GEN_256 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 367:67] + wire _T_242 = cam_data_reset & _T_241; // @[dec_decode_ctl.scala 367:45] + reg cam_raw_3_valid; // @[Reg.scala 27:20] + wire cam_data_reset_val_3 = _T_242 & cam_raw_3_valid; // @[dec_decode_ctl.scala 367:88] + wire cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[dec_decode_ctl.scala 371:39] + wire _T_108 = ~cam_3_valid; // @[dec_decode_ctl.scala 348:78] + wire _T_114 = _T_102 & cam_2_valid; // @[dec_decode_ctl.scala 348:126] + wire _T_117 = _T_114 & _T_108; // @[dec_decode_ctl.scala 348:126] + wire [3:0] _T_119 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 3'h0}; // @[dec_decode_ctl.scala 348:158] + wire _T_120 = _T_90 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[Mux.scala 27:72] + wire [1:0] _T_121 = _T_96 ? _T_98 : 2'h0; // @[Mux.scala 27:72] + wire [2:0] _T_122 = _T_105 ? _T_107 : 3'h0; // @[Mux.scala 27:72] + wire [3:0] _T_123 = _T_117 ? _T_119 : 4'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_260 = {{1'd0}, _T_120}; // @[Mux.scala 27:72] + wire [1:0] _T_124 = _GEN_260 | _T_121; // @[Mux.scala 27:72] + wire [2:0] _GEN_261 = {{1'd0}, _T_124}; // @[Mux.scala 27:72] + wire [2:0] _T_125 = _GEN_261 | _T_122; // @[Mux.scala 27:72] + wire [3:0] _GEN_262 = {{1'd0}, _T_125}; // @[Mux.scala 27:72] + wire [3:0] cam_wen = _GEN_262 | _T_123; // @[Mux.scala 27:72] + reg x_d_bits_i0load; // @[Reg.scala 27:20] + wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[dec_decode_ctl.scala 359:31] + reg [2:0] _T_815; // @[dec_decode_ctl.scala 764:80] + wire [3:0] i0_pipe_en = {io_dec_aln_dec_i0_decode_d,_T_815}; // @[Cat.scala 29:58] + wire _T_821 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 767:49] + wire i0_r_ctl_en = _T_821 | io_clk_override; // @[dec_decode_ctl.scala 767:53] + reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20] + reg r_d_bits_i0load; // @[Reg.scala 27:20] + wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[dec_decode_ctl.scala 364:56] + wire [2:0] _GEN_263 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_inv_tag_r}; // @[dec_decode_ctl.scala 366:66] + wire _T_130 = _GEN_263 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 366:66] + wire _T_131 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_130; // @[dec_decode_ctl.scala 366:45] + wire cam_inv_reset_val_0 = _T_131 & cam_0_valid; // @[dec_decode_ctl.scala 366:87] + reg [4:0] cam_raw_0_bits_rd; // @[Reg.scala 27:20] + wire _T_142 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 379:85] + wire _T_143 = i0_wen_r & _T_142; // @[dec_decode_ctl.scala 379:64] + reg cam_raw_0_bits_wb; // @[Reg.scala 27:20] + wire _T_145 = _T_143 & cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 379:105] + wire _T_146 = cam_inv_reset_val_0 | _T_145; // @[dec_decode_ctl.scala 379:44] + wire _GEN_110 = _T_146 ? 1'h0 : cam_0_valid; // @[dec_decode_ctl.scala 379:131] + wire [4:0] _GEN_111 = _T_146 ? 5'h0 : cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 379:131] + wire [2:0] _GEN_112 = _T_146 ? 3'h0 : cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 379:131] + wire _GEN_113 = _T_146 ? 1'h0 : cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 379:131] + wire _GEN_114 = cam_wen[0] | _GEN_110; // @[dec_decode_ctl.scala 374:28] + wire _GEN_115 = cam_wen[0] ? 1'h0 : _GEN_113; // @[dec_decode_ctl.scala 374:28] + wire [2:0] cam_in_0_bits_tag = cam_wen[0] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_112; // @[dec_decode_ctl.scala 374:28] + wire [4:0] cam_in_0_bits_rd = cam_wen[0] ? nonblock_load_rd : _GEN_111; // @[dec_decode_ctl.scala 374:28] + wire _T_149 = nonblock_load_valid_m_delay & _T_130; // @[dec_decode_ctl.scala 384:44] + wire _T_151 = _T_149 & cam_0_valid; // @[dec_decode_ctl.scala 384:113] + wire cam_in_0_bits_wb = _T_151 | _GEN_115; // @[dec_decode_ctl.scala 384:135] + wire cam_in_0_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_114; // @[dec_decode_ctl.scala 388:32] + wire [8:0] _T_154 = {cam_in_0_bits_wb,cam_in_0_bits_tag,cam_in_0_bits_rd}; // @[lib.scala 494:61] + wire [8:0] _T_156 = {cam_raw_0_bits_wb,cam_raw_0_bits_tag,cam_raw_0_bits_rd}; // @[lib.scala 494:74] + wire [8:0] _T_157 = _T_154 ^ _T_156; // @[lib.scala 494:68] + wire _T_158 = |_T_157; // @[lib.scala 494:82] + wire _T_159 = cam_in_0_valid ^ cam_raw_0_valid; // @[lib.scala 494:68] + wire _T_160 = |_T_159; // @[lib.scala 494:82] + wire _T_161 = _T_158 | _T_160; // @[lib.scala 494:97] + wire nonblock_load_write_0 = _T_133 & cam_raw_0_valid; // @[dec_decode_ctl.scala 393:71] + wire _T_166 = _GEN_263 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 366:66] + wire _T_167 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_166; // @[dec_decode_ctl.scala 366:45] + wire cam_inv_reset_val_1 = _T_167 & cam_1_valid; // @[dec_decode_ctl.scala 366:87] + reg [4:0] cam_raw_1_bits_rd; // @[Reg.scala 27:20] + wire _T_178 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 379:85] + wire _T_179 = i0_wen_r & _T_178; // @[dec_decode_ctl.scala 379:64] + reg cam_raw_1_bits_wb; // @[Reg.scala 27:20] + wire _T_181 = _T_179 & cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 379:105] + wire _T_182 = cam_inv_reset_val_1 | _T_181; // @[dec_decode_ctl.scala 379:44] + wire _GEN_125 = _T_182 ? 1'h0 : cam_1_valid; // @[dec_decode_ctl.scala 379:131] + wire [4:0] _GEN_126 = _T_182 ? 5'h0 : cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 379:131] + wire [2:0] _GEN_127 = _T_182 ? 3'h0 : cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 379:131] + wire _GEN_128 = _T_182 ? 1'h0 : cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 379:131] + wire _GEN_129 = cam_wen[1] | _GEN_125; // @[dec_decode_ctl.scala 374:28] + wire _GEN_130 = cam_wen[1] ? 1'h0 : _GEN_128; // @[dec_decode_ctl.scala 374:28] + wire [2:0] cam_in_1_bits_tag = cam_wen[1] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_127; // @[dec_decode_ctl.scala 374:28] + wire [4:0] cam_in_1_bits_rd = cam_wen[1] ? nonblock_load_rd : _GEN_126; // @[dec_decode_ctl.scala 374:28] + wire _T_185 = nonblock_load_valid_m_delay & _T_166; // @[dec_decode_ctl.scala 384:44] + wire _T_187 = _T_185 & cam_1_valid; // @[dec_decode_ctl.scala 384:113] + wire cam_in_1_bits_wb = _T_187 | _GEN_130; // @[dec_decode_ctl.scala 384:135] + wire cam_in_1_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_129; // @[dec_decode_ctl.scala 388:32] + wire [8:0] _T_190 = {cam_in_1_bits_wb,cam_in_1_bits_tag,cam_in_1_bits_rd}; // @[lib.scala 494:61] + wire [8:0] _T_192 = {cam_raw_1_bits_wb,cam_raw_1_bits_tag,cam_raw_1_bits_rd}; // @[lib.scala 494:74] + wire [8:0] _T_193 = _T_190 ^ _T_192; // @[lib.scala 494:68] + wire _T_194 = |_T_193; // @[lib.scala 494:82] + wire _T_195 = cam_in_1_valid ^ cam_raw_1_valid; // @[lib.scala 494:68] + wire _T_196 = |_T_195; // @[lib.scala 494:82] + wire _T_197 = _T_194 | _T_196; // @[lib.scala 494:97] + wire nonblock_load_write_1 = _T_169 & cam_raw_1_valid; // @[dec_decode_ctl.scala 393:71] + wire _T_202 = _GEN_263 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 366:66] + wire _T_203 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_202; // @[dec_decode_ctl.scala 366:45] + wire cam_inv_reset_val_2 = _T_203 & cam_2_valid; // @[dec_decode_ctl.scala 366:87] + reg [4:0] cam_raw_2_bits_rd; // @[Reg.scala 27:20] + wire _T_214 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 379:85] + wire _T_215 = i0_wen_r & _T_214; // @[dec_decode_ctl.scala 379:64] + reg cam_raw_2_bits_wb; // @[Reg.scala 27:20] + wire _T_217 = _T_215 & cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 379:105] + wire _T_218 = cam_inv_reset_val_2 | _T_217; // @[dec_decode_ctl.scala 379:44] + wire _GEN_140 = _T_218 ? 1'h0 : cam_2_valid; // @[dec_decode_ctl.scala 379:131] + wire [4:0] _GEN_141 = _T_218 ? 5'h0 : cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 379:131] + wire [2:0] _GEN_142 = _T_218 ? 3'h0 : cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 379:131] + wire _GEN_143 = _T_218 ? 1'h0 : cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 379:131] + wire _GEN_144 = cam_wen[2] | _GEN_140; // @[dec_decode_ctl.scala 374:28] + wire _GEN_145 = cam_wen[2] ? 1'h0 : _GEN_143; // @[dec_decode_ctl.scala 374:28] + wire [2:0] cam_in_2_bits_tag = cam_wen[2] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_142; // @[dec_decode_ctl.scala 374:28] + wire [4:0] cam_in_2_bits_rd = cam_wen[2] ? nonblock_load_rd : _GEN_141; // @[dec_decode_ctl.scala 374:28] + wire _T_221 = nonblock_load_valid_m_delay & _T_202; // @[dec_decode_ctl.scala 384:44] + wire _T_223 = _T_221 & cam_2_valid; // @[dec_decode_ctl.scala 384:113] + wire cam_in_2_bits_wb = _T_223 | _GEN_145; // @[dec_decode_ctl.scala 384:135] + wire cam_in_2_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_144; // @[dec_decode_ctl.scala 388:32] + wire [8:0] _T_226 = {cam_in_2_bits_wb,cam_in_2_bits_tag,cam_in_2_bits_rd}; // @[lib.scala 494:61] + wire [8:0] _T_228 = {cam_raw_2_bits_wb,cam_raw_2_bits_tag,cam_raw_2_bits_rd}; // @[lib.scala 494:74] + wire [8:0] _T_229 = _T_226 ^ _T_228; // @[lib.scala 494:68] + wire _T_230 = |_T_229; // @[lib.scala 494:82] + wire _T_231 = cam_in_2_valid ^ cam_raw_2_valid; // @[lib.scala 494:68] + wire _T_232 = |_T_231; // @[lib.scala 494:82] + wire _T_233 = _T_230 | _T_232; // @[lib.scala 494:97] + wire nonblock_load_write_2 = _T_205 & cam_raw_2_valid; // @[dec_decode_ctl.scala 393:71] + wire _T_238 = _GEN_263 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 366:66] + wire _T_239 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_238; // @[dec_decode_ctl.scala 366:45] + wire cam_inv_reset_val_3 = _T_239 & cam_3_valid; // @[dec_decode_ctl.scala 366:87] + reg [4:0] cam_raw_3_bits_rd; // @[Reg.scala 27:20] + wire _T_250 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 379:85] + wire _T_251 = i0_wen_r & _T_250; // @[dec_decode_ctl.scala 379:64] + reg cam_raw_3_bits_wb; // @[Reg.scala 27:20] + wire _T_253 = _T_251 & cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 379:105] + wire _T_254 = cam_inv_reset_val_3 | _T_253; // @[dec_decode_ctl.scala 379:44] + wire _GEN_155 = _T_254 ? 1'h0 : cam_3_valid; // @[dec_decode_ctl.scala 379:131] + wire [4:0] _GEN_156 = _T_254 ? 5'h0 : cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 379:131] + wire [2:0] _GEN_157 = _T_254 ? 3'h0 : cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 379:131] + wire _GEN_158 = _T_254 ? 1'h0 : cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 379:131] + wire _GEN_159 = cam_wen[3] | _GEN_155; // @[dec_decode_ctl.scala 374:28] + wire _GEN_160 = cam_wen[3] ? 1'h0 : _GEN_158; // @[dec_decode_ctl.scala 374:28] + wire [2:0] cam_in_3_bits_tag = cam_wen[3] ? {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m} : _GEN_157; // @[dec_decode_ctl.scala 374:28] + wire [4:0] cam_in_3_bits_rd = cam_wen[3] ? nonblock_load_rd : _GEN_156; // @[dec_decode_ctl.scala 374:28] + wire _T_257 = nonblock_load_valid_m_delay & _T_238; // @[dec_decode_ctl.scala 384:44] + wire _T_259 = _T_257 & cam_3_valid; // @[dec_decode_ctl.scala 384:113] + wire cam_in_3_bits_wb = _T_259 | _GEN_160; // @[dec_decode_ctl.scala 384:135] + wire cam_in_3_valid = io_dec_tlu_force_halt ? 1'h0 : _GEN_159; // @[dec_decode_ctl.scala 388:32] + wire [8:0] _T_262 = {cam_in_3_bits_wb,cam_in_3_bits_tag,cam_in_3_bits_rd}; // @[lib.scala 494:61] + wire [8:0] _T_264 = {cam_raw_3_bits_wb,cam_raw_3_bits_tag,cam_raw_3_bits_rd}; // @[lib.scala 494:74] + wire [8:0] _T_265 = _T_262 ^ _T_264; // @[lib.scala 494:68] + wire _T_266 = |_T_265; // @[lib.scala 494:82] + wire _T_267 = cam_in_3_valid ^ cam_raw_3_valid; // @[lib.scala 494:68] + wire _T_268 = |_T_267; // @[lib.scala 494:82] + wire _T_269 = _T_266 | _T_268; // @[lib.scala 494:97] + wire nonblock_load_write_3 = _T_241 & cam_raw_3_valid; // @[dec_decode_ctl.scala 393:71] + wire _T_274 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[dec_decode_ctl.scala 398:49] + wire nonblock_load_cancel = _T_274 & i0_wen_r; // @[dec_decode_ctl.scala 398:81] + wire _T_275 = nonblock_load_write_0 | nonblock_load_write_1; // @[dec_decode_ctl.scala 399:108] + wire _T_276 = _T_275 | nonblock_load_write_2; // @[dec_decode_ctl.scala 399:108] + wire _T_277 = _T_276 | nonblock_load_write_3; // @[dec_decode_ctl.scala 399:108] + wire _T_279 = io_dctl_busbuff_lsu_nonblock_load_data_valid & _T_277; // @[dec_decode_ctl.scala 399:77] + wire _T_280 = ~nonblock_load_cancel; // @[dec_decode_ctl.scala 399:122] + wire _T_282 = nonblock_load_rd == i0r_rs1; // @[dec_decode_ctl.scala 400:54] + wire _T_283 = _T_282 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 400:66] + wire _T_284 = _T_283 & io_decode_exu_dec_i0_rs1_en_d; // @[dec_decode_ctl.scala 400:110] + wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 677:16] + wire _T_285 = nonblock_load_rd == i0r_rs2; // @[dec_decode_ctl.scala 400:161] + wire _T_286 = _T_285 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 400:173] + wire _T_287 = _T_286 & io_decode_exu_dec_i0_rs2_en_d; // @[dec_decode_ctl.scala 400:217] + wire i0_nonblock_boundary_stall = _T_284 | _T_287; // @[dec_decode_ctl.scala 400:142] + wire [4:0] _T_289 = nonblock_load_write_0 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_290 = _T_289 & cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 404:88] + wire _T_291 = io_decode_exu_dec_i0_rs1_en_d & cam_0_valid; // @[dec_decode_ctl.scala 404:137] + wire _T_292 = cam_raw_0_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 404:170] + wire _T_293 = _T_291 & _T_292; // @[dec_decode_ctl.scala 404:152] + wire _T_294 = io_decode_exu_dec_i0_rs2_en_d & cam_0_valid; // @[dec_decode_ctl.scala 404:214] + wire _T_295 = cam_raw_0_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 404:247] + wire _T_296 = _T_294 & _T_295; // @[dec_decode_ctl.scala 404:229] + wire [4:0] _T_298 = nonblock_load_write_1 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_299 = _T_298 & cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 404:88] + wire _T_300 = io_decode_exu_dec_i0_rs1_en_d & cam_1_valid; // @[dec_decode_ctl.scala 404:137] + wire _T_301 = cam_raw_1_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 404:170] + wire _T_302 = _T_300 & _T_301; // @[dec_decode_ctl.scala 404:152] + wire _T_303 = io_decode_exu_dec_i0_rs2_en_d & cam_1_valid; // @[dec_decode_ctl.scala 404:214] + wire _T_304 = cam_raw_1_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 404:247] + wire _T_305 = _T_303 & _T_304; // @[dec_decode_ctl.scala 404:229] + wire [4:0] _T_307 = nonblock_load_write_2 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_308 = _T_307 & cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 404:88] + wire _T_309 = io_decode_exu_dec_i0_rs1_en_d & cam_2_valid; // @[dec_decode_ctl.scala 404:137] + wire _T_310 = cam_raw_2_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 404:170] + wire _T_311 = _T_309 & _T_310; // @[dec_decode_ctl.scala 404:152] + wire _T_312 = io_decode_exu_dec_i0_rs2_en_d & cam_2_valid; // @[dec_decode_ctl.scala 404:214] + wire _T_313 = cam_raw_2_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 404:247] + wire _T_314 = _T_312 & _T_313; // @[dec_decode_ctl.scala 404:229] + wire [4:0] _T_316 = nonblock_load_write_3 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_317 = _T_316 & cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 404:88] + wire _T_318 = io_decode_exu_dec_i0_rs1_en_d & cam_3_valid; // @[dec_decode_ctl.scala 404:137] + wire _T_319 = cam_raw_3_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 404:170] + wire _T_320 = _T_318 & _T_319; // @[dec_decode_ctl.scala 404:152] + wire _T_321 = io_decode_exu_dec_i0_rs2_en_d & cam_3_valid; // @[dec_decode_ctl.scala 404:214] + wire _T_322 = cam_raw_3_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 404:247] + wire _T_323 = _T_321 & _T_322; // @[dec_decode_ctl.scala 404:229] + wire [4:0] _T_324 = _T_290 | _T_299; // @[dec_decode_ctl.scala 405:69] + wire [4:0] _T_325 = _T_324 | _T_308; // @[dec_decode_ctl.scala 405:69] + wire _T_326 = _T_293 | _T_302; // @[dec_decode_ctl.scala 405:102] + wire _T_327 = _T_326 | _T_311; // @[dec_decode_ctl.scala 405:102] + wire ld_stall_1 = _T_327 | _T_320; // @[dec_decode_ctl.scala 405:102] + wire _T_328 = _T_296 | _T_305; // @[dec_decode_ctl.scala 405:134] + wire _T_329 = _T_328 | _T_314; // @[dec_decode_ctl.scala 405:134] + wire ld_stall_2 = _T_329 | _T_323; // @[dec_decode_ctl.scala 405:134] + wire _T_330 = ld_stall_1 | ld_stall_2; // @[dec_decode_ctl.scala 407:38] + wire i0_nonblock_load_stall = _T_330 | i0_nonblock_boundary_stall; // @[dec_decode_ctl.scala 407:51] + wire _T_332 = ~i0_predict_br; // @[dec_decode_ctl.scala 416:34] + wire i0_br_unpred = i0_dp_jal & _T_332; // @[dec_decode_ctl.scala 416:32] + wire [3:0] _T_334 = i0_legal_decode_d ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[dec_decode_ctl.scala 517:36] + wire _T_335 = csr_read & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 428:16] + wire _T_337 = ~csr_read; // @[dec_decode_ctl.scala 429:6] + wire _T_338 = _T_337 & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 429:16] + wire _T_340 = ~io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 430:18] + wire _T_341 = csr_read & _T_340; // @[dec_decode_ctl.scala 430:16] + wire _T_343 = i0_dp_zbb | i0_dp_zbs; // @[dec_decode_ctl.scala 431:16] + wire _T_344 = _T_343 | i0_dp_zbe; // @[dec_decode_ctl.scala 431:28] + wire _T_345 = _T_344 | i0_dp_zbc; // @[dec_decode_ctl.scala 431:40] + wire _T_346 = _T_345 | i0_dp_zbp; // @[dec_decode_ctl.scala 431:52] + wire _T_347 = _T_346 | i0_dp_zbr; // @[dec_decode_ctl.scala 431:65] + wire _T_348 = _T_347 | i0_dp_zbf; // @[dec_decode_ctl.scala 431:77] + wire _T_349 = _T_348 | i0_dp_zba; // @[dec_decode_ctl.scala 431:89] + wire [3:0] _T_350 = i0_dp_mul ? 4'h1 : 4'h0; // @[Mux.scala 98:16] + wire [3:0] _T_351 = i0_dp_load ? 4'h2 : _T_350; // @[Mux.scala 98:16] + wire [3:0] _T_352 = i0_dp_store ? 4'h3 : _T_351; // @[Mux.scala 98:16] + wire [3:0] _T_353 = i0_dp_pm_alu ? 4'h4 : _T_352; // @[Mux.scala 98:16] + wire [3:0] _T_354 = _T_349 ? 4'hf : _T_353; // @[Mux.scala 98:16] + wire [3:0] _T_355 = _T_341 ? 4'h5 : _T_354; // @[Mux.scala 98:16] + wire [3:0] _T_356 = _T_338 ? 4'h6 : _T_355; // @[Mux.scala 98:16] + wire [3:0] _T_357 = _T_335 ? 4'h7 : _T_356; // @[Mux.scala 98:16] + wire [3:0] _T_358 = i0_dp_ebreak ? 4'h8 : _T_357; // @[Mux.scala 98:16] + wire [3:0] _T_359 = i0_dp_ecall ? 4'h9 : _T_358; // @[Mux.scala 98:16] + wire [3:0] _T_360 = i0_dp_fence ? 4'ha : _T_359; // @[Mux.scala 98:16] + wire [3:0] _T_361 = i0_dp_fence_i ? 4'hb : _T_360; // @[Mux.scala 98:16] + wire [3:0] _T_362 = i0_dp_mret ? 4'hc : _T_361; // @[Mux.scala 98:16] + wire [3:0] _T_363 = i0_dp_condbr ? 4'hd : _T_362; // @[Mux.scala 98:16] + wire [3:0] _T_364 = i0_dp_jal ? 4'he : _T_363; // @[Mux.scala 98:16] + wire [3:0] d_t_pmu_i0_itype = _T_334 & _T_364; // @[dec_decode_ctl.scala 420:49] + reg lsu_idle; // @[dec_decode_ctl.scala 442:45] + wire _T_418 = ~i0_pcall_case; // @[dec_decode_ctl.scala 464:35] + wire _T_419 = i0_dp_jal & _T_418; // @[dec_decode_ctl.scala 464:32] + wire _T_420 = ~i0_pja_case; // @[dec_decode_ctl.scala 464:52] + wire _T_421 = _T_419 & _T_420; // @[dec_decode_ctl.scala 464:50] + wire _T_422 = ~i0_pret_case; // @[dec_decode_ctl.scala 464:67] + wire _T_425 = i0r_rs1 == 5'h2; // @[dec_decode_ctl.scala 508:41] + wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[dec_decode_ctl.scala 633:40] + wire _T_1018 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 901:43] + reg x_d_bits_i0v; // @[Reg.scala 27:20] + wire _T_992 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 881:59] + wire _T_993 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 881:91] + wire i0_rs1_depend_i0_x = _T_992 & _T_993; // @[dec_decode_ctl.scala 881:74] + wire _T_994 = io_decode_exu_dec_i0_rs1_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 882:59] + wire _T_995 = r_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 882:91] + wire i0_rs1_depend_i0_r = _T_994 & _T_995; // @[dec_decode_ctl.scala 882:74] + wire [1:0] _T_1007 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 888:63] + wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_1007; // @[dec_decode_ctl.scala 888:24] + wire _T_1020 = _T_1018 & i0_rs1_depth_d[0]; // @[dec_decode_ctl.scala 901:58] + reg i0_x_c_load; // @[Reg.scala 27:20] + reg i0_r_c_load; // @[Reg.scala 27:20] + wire _T_1003_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 887:61] + wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_1003_load; // @[dec_decode_ctl.scala 887:24] + wire load_ldst_bypass_d = _T_1020 & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 901:78] + wire _T_996 = io_decode_exu_dec_i0_rs2_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 884:59] + wire _T_997 = x_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 884:91] + wire i0_rs2_depend_i0_x = _T_996 & _T_997; // @[dec_decode_ctl.scala 884:74] + wire _T_998 = io_decode_exu_dec_i0_rs2_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 885:59] + wire _T_999 = r_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 885:91] + wire i0_rs2_depend_i0_r = _T_998 & _T_999; // @[dec_decode_ctl.scala 885:74] + wire [1:0] _T_1016 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 890:63] + wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_1016; // @[dec_decode_ctl.scala 890:24] + wire _T_1023 = i0_dp_store & i0_rs2_depth_d[0]; // @[dec_decode_ctl.scala 902:43] + wire _T_1012_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 889:61] + wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_1012_load; // @[dec_decode_ctl.scala 889:24] + wire store_data_bypass_d = _T_1023 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 902:63] + wire _T_435 = i0_dp_csr_clr | i0_dp_csr_set; // @[dec_decode_ctl.scala 525:42] + wire _T_436 = _T_435 | i0_csr_write; // @[dec_decode_ctl.scala 525:58] + wire [11:0] _T_440 = io_dec_csr_any_unq_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12] + reg r_d_bits_csrwen; // @[Reg.scala 27:20] + wire _T_443 = r_d_bits_csrwen & r_d_valid; // @[dec_decode_ctl.scala 530:53] + wire [11:0] _T_445 = _T_443 ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12] + reg [11:0] r_d_bits_csrwaddr; // @[Reg.scala 27:20] + wire _T_450 = r_d_bits_csrwaddr == 12'h300; // @[dec_decode_ctl.scala 537:50] + wire _T_451 = r_d_bits_csrwaddr == 12'h304; // @[dec_decode_ctl.scala 537:85] + wire _T_452 = _T_450 | _T_451; // @[dec_decode_ctl.scala 537:64] + wire _T_453 = _T_452 & r_d_bits_csrwen; // @[dec_decode_ctl.scala 537:100] + wire _T_454 = _T_453 & r_d_valid; // @[dec_decode_ctl.scala 537:118] + wire _T_455 = ~io_dec_tlu_i0_kill_writeb_wb; // @[dec_decode_ctl.scala 537:132] + reg csr_read_x; // @[dec_decode_ctl.scala 539:52] + reg csr_clr_x; // @[dec_decode_ctl.scala 540:51] + reg csr_set_x; // @[dec_decode_ctl.scala 541:51] + reg csr_write_x; // @[dec_decode_ctl.scala 542:53] + reg csr_imm_x; // @[dec_decode_ctl.scala 543:51] + wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[dec_decode_ctl.scala 769:50] + wire _T_459 = i0_x_data_en & any_csr_d; // @[dec_decode_ctl.scala 546:48] + reg [4:0] csrimm_x; // @[Reg.scala 27:20] + reg [31:0] csr_rddata_x; // @[Reg.scala 27:20] + wire [31:0] _T_493 = {27'h0,csrimm_x}; // @[Cat.scala 29:58] + wire _T_495 = ~csr_imm_x; // @[dec_decode_ctl.scala 551:5] + wire [31:0] _T_496 = csr_imm_x ? _T_493 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_497 = _T_495 ? io_decode_exu_exu_csr_rs1_x : 32'h0; // @[Mux.scala 27:72] + wire [31:0] csr_mask_x = _T_496 | _T_497; // @[Mux.scala 27:72] + wire [31:0] _T_499 = ~csr_mask_x; // @[dec_decode_ctl.scala 554:38] + wire [31:0] _T_500 = csr_rddata_x & _T_499; // @[dec_decode_ctl.scala 554:35] + wire [31:0] _T_501 = csr_rddata_x | csr_mask_x; // @[dec_decode_ctl.scala 555:35] + wire [31:0] _T_502 = csr_clr_x ? _T_500 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_503 = csr_set_x ? _T_501 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_504 = csr_write_x ? csr_mask_x : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_505 = _T_502 | _T_503; // @[Mux.scala 27:72] + wire [31:0] write_csr_data_x = _T_505 | _T_504; // @[Mux.scala 27:72] + wire _T_517 = ~tlu_wr_pause_r1; // @[dec_decode_ctl.scala 562:44] + wire _T_518 = ~tlu_wr_pause_r2; // @[dec_decode_ctl.scala 562:64] + wire _T_519 = _T_517 & _T_518; // @[dec_decode_ctl.scala 562:61] + wire [31:0] _T_522 = write_csr_data - 32'h1; // @[dec_decode_ctl.scala 565:59] + wire _T_524 = csr_clr_x | csr_set_x; // @[dec_decode_ctl.scala 567:34] + wire _T_525 = _T_524 | csr_write_x; // @[dec_decode_ctl.scala 567:46] + wire _T_526 = _T_525 & csr_read_x; // @[dec_decode_ctl.scala 567:61] + wire _T_527 = _T_526 | io_dec_tlu_wr_pause_r; // @[dec_decode_ctl.scala 567:75] + wire csr_data_wen = _T_527 | pause_stall; // @[dec_decode_ctl.scala 567:99] + reg r_d_bits_csrwonly; // @[Reg.scala 27:20] + wire _T_529 = r_d_bits_csrwonly & r_d_valid; // @[dec_decode_ctl.scala 574:50] + wire _T_881 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 822:42] + reg [31:0] i0_result_r_raw; // @[Reg.scala 27:20] + wire [31:0] i0_result_corr_r = _T_881 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 822:27] + reg x_d_bits_csrwonly; // @[Reg.scala 27:20] + wire _T_532 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[dec_decode_ctl.scala 576:43] + reg wbd_bits_csrwonly; // @[Reg.scala 27:20] + wire prior_csr_write = _T_532 | wbd_bits_csrwonly; // @[dec_decode_ctl.scala 576:63] + wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[1]; // @[dec_decode_ctl.scala 579:48] + wire debug_fence = debug_fence_raw | debug_fence_i; // @[dec_decode_ctl.scala 580:40] + wire _T_536 = i0_dp_presync | io_dec_tlu_presync_d; // @[dec_decode_ctl.scala 583:34] + wire _T_537 = _T_536 | debug_fence_i; // @[dec_decode_ctl.scala 583:57] + wire _T_538 = _T_537 | debug_fence_raw; // @[dec_decode_ctl.scala 583:73] + wire i0_presync = _T_538 | io_dec_tlu_pipelining_disable; // @[dec_decode_ctl.scala 583:91] + wire [31:0] _T_562 = {16'h0,io_dec_aln_ifu_i0_cinst}; // @[Cat.scala 29:58] + wire _T_564 = ~illegal_lockout; // @[dec_decode_ctl.scala 595:44] + wire illegal_inst_en = shift_illegal & _T_564; // @[dec_decode_ctl.scala 595:42] + reg [31:0] _T_565; // @[Reg.scala 27:20] + wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[dec_decode_ctl.scala 598:42] + wire _T_569 = i0_dp_csr_read & prior_csr_write; // @[dec_decode_ctl.scala 600:40] + wire _T_570 = _T_569 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 600:59] + wire _T_571 = _T_570 | pause_stall; // @[dec_decode_ctl.scala 600:92] + wire _T_572 = _T_571 | leak1_i0_stall; // @[dec_decode_ctl.scala 600:106] + wire _T_573 = _T_572 | io_dec_tlu_debug_stall; // @[dec_decode_ctl.scala 601:20] + wire _T_574 = _T_573 | postsync_stall; // @[dec_decode_ctl.scala 601:45] + wire prior_inflight = x_d_valid | r_d_valid; // @[dec_decode_ctl.scala 623:41] + wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[dec_decode_ctl.scala 624:31] + wire presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 626:37] + wire _T_575 = _T_574 | presync_stall; // @[dec_decode_ctl.scala 601:62] + wire _T_576 = i0_dp_fence | debug_fence; // @[dec_decode_ctl.scala 602:19] + wire _T_577 = ~lsu_idle; // @[dec_decode_ctl.scala 602:36] + wire _T_578 = _T_576 & _T_577; // @[dec_decode_ctl.scala 602:34] + wire _T_579 = _T_575 | _T_578; // @[dec_decode_ctl.scala 601:79] + wire _T_580 = _T_579 | i0_nonblock_load_stall; // @[dec_decode_ctl.scala 602:47] + wire _T_939 = io_decode_exu_dec_i0_rs1_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 850:60] + wire _T_940 = io_div_waddr_wb == i0r_rs1; // @[dec_decode_ctl.scala 850:99] + wire _T_941 = _T_939 & _T_940; // @[dec_decode_ctl.scala 850:80] + wire _T_942 = io_decode_exu_dec_i0_rs2_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 851:36] + wire _T_943 = io_div_waddr_wb == i0r_rs2; // @[dec_decode_ctl.scala 851:75] + wire _T_944 = _T_942 & _T_943; // @[dec_decode_ctl.scala 851:56] + wire i0_nonblock_div_stall = _T_941 | _T_944; // @[dec_decode_ctl.scala 850:113] + wire _T_582 = _T_580 | i0_nonblock_div_stall; // @[dec_decode_ctl.scala 603:21] + wire i0_block_raw_d = _T_582 | i0_div_prior_div_stall; // @[dec_decode_ctl.scala 603:45] + wire _T_583 = io_lsu_store_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 605:65] + wire i0_store_stall_d = i0_dp_store & _T_583; // @[dec_decode_ctl.scala 605:39] + wire _T_584 = io_lsu_load_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 606:63] + wire i0_load_stall_d = i0_dp_load & _T_584; // @[dec_decode_ctl.scala 606:38] + wire _T_585 = i0_block_raw_d | i0_store_stall_d; // @[dec_decode_ctl.scala 607:38] + wire i0_block_d = _T_585 | i0_load_stall_d; // @[dec_decode_ctl.scala 607:57] + wire _T_586 = ~i0_block_d; // @[dec_decode_ctl.scala 611:54] + wire _T_587 = io_dec_ib0_valid_d & _T_586; // @[dec_decode_ctl.scala 611:52] + wire _T_589 = _T_587 & _T_367; // @[dec_decode_ctl.scala 611:69] + wire _T_592 = ~i0_block_raw_d; // @[dec_decode_ctl.scala 612:46] + wire _T_593 = io_dec_ib0_valid_d & _T_592; // @[dec_decode_ctl.scala 612:44] + wire _T_595 = _T_593 & _T_367; // @[dec_decode_ctl.scala 612:61] + wire i0_exudecode_d = _T_595 & _T_567; // @[dec_decode_ctl.scala 612:89] + wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[dec_decode_ctl.scala 613:46] + wire _T_597 = ~io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 617:51] + wire _T_610 = i0_dp_condbr | i0_dp_jal; // @[dec_decode_ctl.scala 631:53] + wire d_t_icaf = i0_icaf_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 641:40] + wire d_t_icaf_second = io_dec_i0_icaf_second_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 642:58] + wire _T_619 = i0_dp_fence_i | debug_fence_i; // @[dec_decode_ctl.scala 645:44] + wire d_t_fence_i = _T_619 & i0_legal_decode_d; // @[dec_decode_ctl.scala 645:61] + wire [3:0] _T_624 = {io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d}; // @[Cat.scala 29:58] + wire [3:0] d_t_i0trigger = io_dec_i0_trigger_match_d & _T_624; // @[dec_decode_ctl.scala 652:56] + wire _T_818 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 766:49] + wire i0_x_ctl_en = _T_818 | io_clk_override; // @[dec_decode_ctl.scala 766:53] + reg x_t_legal; // @[Reg.scala 27:20] + reg x_t_icaf; // @[Reg.scala 27:20] + reg x_t_icaf_second; // @[Reg.scala 27:20] + reg [1:0] x_t_icaf_type; // @[Reg.scala 27:20] + reg x_t_fence_i; // @[Reg.scala 27:20] + reg [3:0] x_t_i0trigger; // @[Reg.scala 27:20] + reg [3:0] x_t_pmu_i0_itype; // @[Reg.scala 27:20] + reg x_t_pmu_i0_br_unpred; // @[Reg.scala 27:20] + wire [3:0] _T_632 = {io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb}; // @[Cat.scala 29:58] + wire [3:0] _T_633 = ~_T_632; // @[dec_decode_ctl.scala 658:39] + wire [3:0] x_t_in_i0trigger = x_t_i0trigger & _T_633; // @[dec_decode_ctl.scala 658:37] + reg r_t_legal; // @[Reg.scala 27:20] + reg r_t_icaf; // @[Reg.scala 27:20] + reg r_t_icaf_second; // @[Reg.scala 27:20] + reg [1:0] r_t_icaf_type; // @[Reg.scala 27:20] + reg r_t_fence_i; // @[Reg.scala 27:20] + reg [3:0] r_t_i0trigger; // @[Reg.scala 27:20] + reg [3:0] r_t_pmu_i0_itype; // @[Reg.scala 27:20] + reg r_t_pmu_i0_br_unpred; // @[Reg.scala 27:20] + reg r_d_bits_i0store; // @[Reg.scala 27:20] + wire _T_638 = r_d_bits_i0load | r_d_bits_i0store; // @[dec_decode_ctl.scala 664:61] + wire [3:0] _T_642 = {_T_638,_T_638,_T_638,_T_638}; // @[Cat.scala 29:58] + wire [3:0] _T_643 = _T_642 & lsu_trigger_match_r; // @[dec_decode_ctl.scala 664:82] + wire [3:0] _T_644 = _T_643 | r_t_i0trigger; // @[dec_decode_ctl.scala 664:105] + wire _T_657 = i0r_rs1 != 5'h0; // @[dec_decode_ctl.scala 680:60] + wire _T_659 = i0r_rs2 != 5'h0; // @[dec_decode_ctl.scala 681:60] + wire _T_661 = i0r_rd != 5'h0; // @[dec_decode_ctl.scala 682:48] + wire i0_rd_en_d = i0_dp_rd & _T_661; // @[dec_decode_ctl.scala 682:37] + wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[dec_decode_ctl.scala 686:38] + wire _T_662 = ~i0_dp_jal; // @[dec_decode_ctl.scala 687:27] + wire i0_uiimm20 = _T_662 & i0_dp_imm20; // @[dec_decode_ctl.scala 687:38] + wire [9:0] _T_673 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] + wire [18:0] _T_682 = {_T_673,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] + wire [31:0] _T_685 = {_T_682,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31:20]}; // @[Cat.scala 29:58] + wire [31:0] _T_714 = {27'h0,i0r_rs2}; // @[Cat.scala 29:58] + wire [31:0] _T_734 = {_T_673,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21],1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_748 = {io_dec_i0_instr_d[31:12],12'h0}; // @[Cat.scala 29:58] + wire _T_749 = i0_csr_write_only_d & i0_dp_csr_imm; // @[dec_decode_ctl.scala 698:26] + wire [31:0] _T_779 = {27'h0,i0r_rs1}; // @[Cat.scala 29:58] + wire [31:0] _T_780 = i0_dp_imm12 ? _T_685 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_781 = i0_dp_shimm5 ? _T_714 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_782 = i0_jalimm20 ? _T_734 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_783 = i0_uiimm20 ? _T_748 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_784 = _T_749 ? _T_779 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_785 = _T_780 | _T_781; // @[Mux.scala 27:72] + wire [31:0] _T_786 = _T_785 | _T_782; // @[Mux.scala 27:72] + wire [31:0] _T_787 = _T_786 | _T_783; // @[Mux.scala 27:72] + wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[dec_decode_ctl.scala 758:44] + wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[dec_decode_ctl.scala 759:44] + wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[dec_decode_ctl.scala 760:44] + reg i0_x_c_mul; // @[Reg.scala 27:20] + reg i0_x_c_alu; // @[Reg.scala 27:20] + reg i0_r_c_mul; // @[Reg.scala 27:20] + reg i0_r_c_alu; // @[Reg.scala 27:20] + wire _T_824 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 768:49] + wire i0_wb_ctl_en = _T_824 | io_clk_override; // @[dec_decode_ctl.scala 768:53] + wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[dec_decode_ctl.scala 770:50] + wire i0_wb_data_en = i0_pipe_en[1] | io_clk_override; // @[dec_decode_ctl.scala 771:50] + wire d_d_bits_i0v = i0_rd_en_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 777:50] + wire d_d_bits_i0store = i0_dp_store & i0_legal_decode_d; // @[dec_decode_ctl.scala 781:50] + wire d_d_bits_i0div = i0_dp_div & i0_legal_decode_d; // @[dec_decode_ctl.scala 782:50] + wire d_d_bits_csrwen = io_dec_csr_wen_unq_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 784:61] + wire d_d_bits_csrwonly = i0_csr_write_only_d & io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 785:58] + reg x_d_bits_i0store; // @[Reg.scala 27:20] + reg x_d_bits_csrwen; // @[Reg.scala 27:20] + reg [11:0] x_d_bits_csrwaddr; // @[Reg.scala 27:20] + wire _T_847 = x_d_bits_i0v & _T_857; // @[dec_decode_ctl.scala 791:47] + wire x_d_in_bits_i0v = _T_847 & _T_367; // @[dec_decode_ctl.scala 791:76] + wire _T_851 = x_d_valid & _T_857; // @[dec_decode_ctl.scala 792:33] + wire x_d_in_valid = _T_851 & _T_367; // @[dec_decode_ctl.scala 792:62] + wire _T_870 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 807:49] + wire _T_871 = i0_wen_r & _T_870; // @[dec_decode_ctl.scala 807:47] + wire _T_872 = ~i0_load_kill_wen_r; // @[dec_decode_ctl.scala 807:70] + wire _T_874 = x_d_bits_i0v | x_d_bits_csrwen; // @[dec_decode_ctl.scala 811:74] + wire _T_875 = _T_874 | debug_valid_x; // @[dec_decode_ctl.scala 811:92] + wire _T_876 = i0_r_data_en & _T_875; // @[dec_decode_ctl.scala 811:58] + wire _T_878 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 817:47] + wire _T_885 = io_decode_exu_i0_ap_predict_nt & _T_662; // @[dec_decode_ctl.scala 823:71] + wire [11:0] _T_898 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] + reg [11:0] last_br_immed_x; // @[Reg.scala 27:20] + wire trace_enable = ~io_dec_tlu_trace_disable; // @[dec_decode_ctl.scala 858:22] + reg [4:0] _T_947; // @[Reg.scala 27:20] + wire _T_948 = i0_x_data_en & trace_enable; // @[dec_decode_ctl.scala 862:50] + reg [31:0] i0_inst_x; // @[Reg.scala 27:20] + wire _T_950 = i0_r_data_en & trace_enable; // @[dec_decode_ctl.scala 863:50] + reg [31:0] i0_inst_r; // @[Reg.scala 27:20] + wire _T_952 = i0_wb_data_en & trace_enable; // @[dec_decode_ctl.scala 865:51] + reg [31:0] i0_inst_wb; // @[Reg.scala 27:20] + reg [30:0] i0_pc_wb; // @[Reg.scala 27:20] + reg [30:0] dec_i0_pc_r; // @[Reg.scala 27:20] + wire [31:0] _T_958 = {io_dec_alu_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58] + wire [12:0] _T_959 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58] + wire [12:0] _T_962 = _T_958[12:1] + _T_959[12:1]; // @[lib.scala 68:31] + wire [18:0] _T_965 = _T_958[31:13] + 19'h1; // @[lib.scala 69:27] + wire [18:0] _T_968 = _T_958[31:13] - 19'h1; // @[lib.scala 70:27] + wire _T_971 = ~_T_962[12]; // @[lib.scala 72:28] + wire _T_972 = _T_959[12] ^ _T_971; // @[lib.scala 72:26] + wire _T_975 = ~_T_959[12]; // @[lib.scala 73:20] + wire _T_977 = _T_975 & _T_962[12]; // @[lib.scala 73:26] + wire _T_981 = _T_959[12] & _T_971; // @[lib.scala 74:26] + wire [18:0] _T_983 = _T_972 ? _T_958[31:13] : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_984 = _T_977 ? _T_965 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_985 = _T_981 ? _T_968 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_986 = _T_983 | _T_984; // @[Mux.scala 27:72] + wire [18:0] _T_987 = _T_986 | _T_985; // @[Mux.scala 27:72] + wire [31:0] temp_pred_correct_npc_x = {_T_987,_T_962[11:0],1'h0}; // @[Cat.scala 29:58] + wire _T_1003_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 887:61] + wire _T_1003_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 887:61] + wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_1003_mul; // @[dec_decode_ctl.scala 887:24] + wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_1003_alu; // @[dec_decode_ctl.scala 887:24] + wire _T_1012_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 889:61] + wire _T_1012_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 889:61] + wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_1012_mul; // @[dec_decode_ctl.scala 889:24] + wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_1012_alu; // @[dec_decode_ctl.scala 889:24] + wire _T_1025 = io_decode_exu_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 907:73] + wire _T_1026 = io_dec_nonblock_load_waddr == i0r_rs1; // @[dec_decode_ctl.scala 907:130] + wire i0_rs1_nonblock_load_bypass_en_d = _T_1025 & _T_1026; // @[dec_decode_ctl.scala 907:100] + wire _T_1027 = io_decode_exu_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 909:73] + wire _T_1028 = io_dec_nonblock_load_waddr == i0r_rs2; // @[dec_decode_ctl.scala 909:130] + wire i0_rs2_nonblock_load_bypass_en_d = _T_1027 & _T_1028; // @[dec_decode_ctl.scala 909:100] + wire _T_1030 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[dec_decode_ctl.scala 912:66] + wire _T_1031 = i0_rs1_depth_d[0] & _T_1030; // @[dec_decode_ctl.scala 912:45] + wire _T_1033 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 912:108] + wire _T_1036 = _T_1030 | i0_rs1_class_d_load; // @[dec_decode_ctl.scala 912:196] + wire _T_1037 = i0_rs1_depth_d[1] & _T_1036; // @[dec_decode_ctl.scala 912:153] + wire [2:0] i0_rs1bypass = {_T_1031,_T_1033,_T_1037}; // @[Cat.scala 29:58] + wire _T_1041 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[dec_decode_ctl.scala 914:67] + wire _T_1042 = i0_rs2_depth_d[0] & _T_1041; // @[dec_decode_ctl.scala 914:45] + wire _T_1044 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 914:109] + wire _T_1047 = _T_1041 | i0_rs2_class_d_load; // @[dec_decode_ctl.scala 914:196] + wire _T_1048 = i0_rs2_depth_d[1] & _T_1047; // @[dec_decode_ctl.scala 914:153] + wire [2:0] i0_rs2bypass = {_T_1042,_T_1044,_T_1048}; // @[Cat.scala 29:58] + wire _T_1052 = ~i0_rs1bypass[0]; // @[dec_decode_ctl.scala 916:53] + wire _T_1054 = ~i0_rs1bypass[1]; // @[dec_decode_ctl.scala 916:72] + wire _T_1055 = _T_1052 & _T_1054; // @[dec_decode_ctl.scala 916:70] + wire _T_1057 = ~i0_rs1bypass[2]; // @[dec_decode_ctl.scala 916:91] + wire _T_1058 = _T_1055 & _T_1057; // @[dec_decode_ctl.scala 916:89] + wire _T_1059 = _T_1058 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 916:108] + wire [1:0] _T_1063 = {i0_rs1bypass[1],i0_rs1bypass[0]}; // @[Cat.scala 29:58] + wire [1:0] _T_1064 = {_T_1059,i0_rs1bypass[2]}; // @[Cat.scala 29:58] + wire _T_1067 = ~i0_rs2bypass[0]; // @[dec_decode_ctl.scala 917:53] + wire _T_1069 = ~i0_rs2bypass[1]; // @[dec_decode_ctl.scala 917:72] + wire _T_1070 = _T_1067 & _T_1069; // @[dec_decode_ctl.scala 917:70] + wire _T_1072 = ~i0_rs2bypass[2]; // @[dec_decode_ctl.scala 917:91] + wire _T_1073 = _T_1070 & _T_1072; // @[dec_decode_ctl.scala 917:89] + wire _T_1074 = _T_1073 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 917:108] + wire [1:0] _T_1078 = {i0_rs2bypass[1],i0_rs2bypass[0]}; // @[Cat.scala 29:58] + wire [1:0] _T_1079 = {_T_1074,i0_rs2bypass[2]}; // @[Cat.scala 29:58] + wire _T_1081 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 921:68] + wire _T_1082 = io_dec_ib0_valid_d & _T_1081; // @[dec_decode_ctl.scala 921:50] + wire _T_1083 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 921:89] + wire _T_1084 = _T_1082 & _T_1083; // @[dec_decode_ctl.scala 921:87] + wire _T_1086 = _T_1084 & _T_592; // @[dec_decode_ctl.scala 921:121] + wire _T_1088 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 923:6] + wire _T_1089 = _T_1088 & i0_dp_lsu; // @[dec_decode_ctl.scala 923:38] + wire _T_1090 = _T_1089 & i0_dp_load; // @[dec_decode_ctl.scala 923:50] + wire _T_1095 = _T_1089 & i0_dp_store; // @[dec_decode_ctl.scala 924:50] + wire [11:0] _T_1099 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58] + wire [11:0] _T_1100 = _T_1090 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72] + wire [11:0] _T_1101 = _T_1095 ? _T_1099 : 12'h0; // @[Mux.scala 27:72] + dec_dec_ctl i0_dec ( // @[dec_decode_ctl.scala 438:22] + .io_ins(i0_dec_io_ins), + .io_out_clz(i0_dec_io_out_clz), + .io_out_ctz(i0_dec_io_out_ctz), + .io_out_pcnt(i0_dec_io_out_pcnt), + .io_out_sext_b(i0_dec_io_out_sext_b), + .io_out_sext_h(i0_dec_io_out_sext_h), + .io_out_slo(i0_dec_io_out_slo), + .io_out_sro(i0_dec_io_out_sro), + .io_out_min(i0_dec_io_out_min), + .io_out_max(i0_dec_io_out_max), + .io_out_pack(i0_dec_io_out_pack), + .io_out_packu(i0_dec_io_out_packu), + .io_out_packh(i0_dec_io_out_packh), + .io_out_rol(i0_dec_io_out_rol), + .io_out_ror(i0_dec_io_out_ror), + .io_out_grev(i0_dec_io_out_grev), + .io_out_gorc(i0_dec_io_out_gorc), + .io_out_zbb(i0_dec_io_out_zbb), + .io_out_sbset(i0_dec_io_out_sbset), + .io_out_sbclr(i0_dec_io_out_sbclr), + .io_out_sbinv(i0_dec_io_out_sbinv), + .io_out_sbext(i0_dec_io_out_sbext), + .io_out_zbs(i0_dec_io_out_zbs), + .io_out_bext(i0_dec_io_out_bext), + .io_out_bdep(i0_dec_io_out_bdep), + .io_out_zbe(i0_dec_io_out_zbe), + .io_out_clmul(i0_dec_io_out_clmul), + .io_out_clmulh(i0_dec_io_out_clmulh), + .io_out_clmulr(i0_dec_io_out_clmulr), + .io_out_zbc(i0_dec_io_out_zbc), + .io_out_shfl(i0_dec_io_out_shfl), + .io_out_unshfl(i0_dec_io_out_unshfl), + .io_out_zbp(i0_dec_io_out_zbp), + .io_out_crc32_b(i0_dec_io_out_crc32_b), + .io_out_crc32_h(i0_dec_io_out_crc32_h), + .io_out_crc32_w(i0_dec_io_out_crc32_w), + .io_out_crc32c_b(i0_dec_io_out_crc32c_b), + .io_out_crc32c_h(i0_dec_io_out_crc32c_h), + .io_out_crc32c_w(i0_dec_io_out_crc32c_w), + .io_out_zbr(i0_dec_io_out_zbr), + .io_out_bfp(i0_dec_io_out_bfp), + .io_out_zbf(i0_dec_io_out_zbf), + .io_out_sh1add(i0_dec_io_out_sh1add), + .io_out_sh2add(i0_dec_io_out_sh2add), + .io_out_sh3add(i0_dec_io_out_sh3add), + .io_out_zba(i0_dec_io_out_zba), + .io_out_alu(i0_dec_io_out_alu), + .io_out_rs1(i0_dec_io_out_rs1), + .io_out_rs2(i0_dec_io_out_rs2), + .io_out_imm12(i0_dec_io_out_imm12), + .io_out_rd(i0_dec_io_out_rd), + .io_out_shimm5(i0_dec_io_out_shimm5), + .io_out_imm20(i0_dec_io_out_imm20), + .io_out_pc(i0_dec_io_out_pc), + .io_out_load(i0_dec_io_out_load), + .io_out_store(i0_dec_io_out_store), + .io_out_lsu(i0_dec_io_out_lsu), + .io_out_add(i0_dec_io_out_add), + .io_out_sub(i0_dec_io_out_sub), + .io_out_land(i0_dec_io_out_land), + .io_out_lor(i0_dec_io_out_lor), + .io_out_lxor(i0_dec_io_out_lxor), + .io_out_sll(i0_dec_io_out_sll), + .io_out_sra(i0_dec_io_out_sra), + .io_out_srl(i0_dec_io_out_srl), + .io_out_slt(i0_dec_io_out_slt), + .io_out_unsign(i0_dec_io_out_unsign), + .io_out_condbr(i0_dec_io_out_condbr), + .io_out_beq(i0_dec_io_out_beq), + .io_out_bne(i0_dec_io_out_bne), + .io_out_bge(i0_dec_io_out_bge), + .io_out_blt(i0_dec_io_out_blt), + .io_out_jal(i0_dec_io_out_jal), + .io_out_by(i0_dec_io_out_by), + .io_out_half(i0_dec_io_out_half), + .io_out_word(i0_dec_io_out_word), + .io_out_csr_read(i0_dec_io_out_csr_read), + .io_out_csr_clr(i0_dec_io_out_csr_clr), + .io_out_csr_set(i0_dec_io_out_csr_set), + .io_out_csr_write(i0_dec_io_out_csr_write), + .io_out_csr_imm(i0_dec_io_out_csr_imm), + .io_out_presync(i0_dec_io_out_presync), + .io_out_postsync(i0_dec_io_out_postsync), + .io_out_ebreak(i0_dec_io_out_ebreak), + .io_out_ecall(i0_dec_io_out_ecall), + .io_out_mret(i0_dec_io_out_mret), + .io_out_mul(i0_dec_io_out_mul), + .io_out_rs1_sign(i0_dec_io_out_rs1_sign), + .io_out_rs2_sign(i0_dec_io_out_rs2_sign), + .io_out_low(i0_dec_io_out_low), + .io_out_div(i0_dec_io_out_div), + .io_out_rem(i0_dec_io_out_rem), + .io_out_fence(i0_dec_io_out_fence), + .io_out_fence_i(i0_dec_io_out_fence_i), + .io_out_pm_alu(i0_dec_io_out_pm_alu), + .io_out_legal(i0_dec_io_out_legal) + ); + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en) + ); + rvclkhdr rvclkhdr_10 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en) + ); + assign io_decode_exu_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[dec_decode_ctl.scala 773:38] + assign io_decode_exu_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[dec_decode_ctl.scala 774:38] + assign io_decode_exu_i0_ap_clz = _T_80 ? 1'h0 : i0_dp_raw_clz; // @[dec_decode_ctl.scala 317:33] + assign io_decode_exu_i0_ap_ctz = _T_80 ? 1'h0 : i0_dp_raw_ctz; // @[dec_decode_ctl.scala 318:33] + assign io_decode_exu_i0_ap_pcnt = _T_80 ? 1'h0 : i0_dp_raw_pcnt; // @[dec_decode_ctl.scala 319:33] + assign io_decode_exu_i0_ap_sext_b = _T_80 ? 1'h0 : i0_dp_raw_sext_b; // @[dec_decode_ctl.scala 320:33] + assign io_decode_exu_i0_ap_sext_h = _T_80 ? 1'h0 : i0_dp_raw_sext_h; // @[dec_decode_ctl.scala 321:33] + assign io_decode_exu_i0_ap_slo = _T_80 ? 1'h0 : i0_dp_raw_slo; // @[dec_decode_ctl.scala 326:33] + assign io_decode_exu_i0_ap_sro = _T_80 ? 1'h0 : i0_dp_raw_sro; // @[dec_decode_ctl.scala 327:33] + assign io_decode_exu_i0_ap_min = _T_80 ? 1'h0 : i0_dp_raw_min; // @[dec_decode_ctl.scala 328:33] + assign io_decode_exu_i0_ap_max = _T_80 ? 1'h0 : i0_dp_raw_max; // @[dec_decode_ctl.scala 329:33] + assign io_decode_exu_i0_ap_pack = _T_80 ? 1'h0 : i0_dp_raw_pack; // @[dec_decode_ctl.scala 330:33] + assign io_decode_exu_i0_ap_packu = _T_80 ? 1'h0 : i0_dp_raw_packu; // @[dec_decode_ctl.scala 331:33] + assign io_decode_exu_i0_ap_packh = _T_80 ? 1'h0 : i0_dp_raw_packh; // @[dec_decode_ctl.scala 332:33] + assign io_decode_exu_i0_ap_rol = _T_80 ? 1'h0 : i0_dp_raw_rol; // @[dec_decode_ctl.scala 333:33] + assign io_decode_exu_i0_ap_ror = _T_80 ? 1'h0 : i0_dp_raw_ror; // @[dec_decode_ctl.scala 334:33] + assign io_decode_exu_i0_ap_grev = _T_80 ? 1'h0 : i0_dp_raw_grev; // @[dec_decode_ctl.scala 335:33] + assign io_decode_exu_i0_ap_gorc = _T_80 ? 1'h0 : i0_dp_raw_gorc; // @[dec_decode_ctl.scala 336:33] + assign io_decode_exu_i0_ap_zbb = _T_80 ? 1'h0 : i0_dp_raw_zbb; // @[dec_decode_ctl.scala 337:33] + assign io_decode_exu_i0_ap_sbset = _T_80 ? 1'h0 : i0_dp_raw_sbset; // @[dec_decode_ctl.scala 338:33] + assign io_decode_exu_i0_ap_sbclr = _T_80 ? 1'h0 : i0_dp_raw_sbclr; // @[dec_decode_ctl.scala 339:33] + assign io_decode_exu_i0_ap_sbinv = _T_80 ? 1'h0 : i0_dp_raw_sbinv; // @[dec_decode_ctl.scala 340:33] + assign io_decode_exu_i0_ap_sbext = _T_80 ? 1'h0 : i0_dp_raw_sbext; // @[dec_decode_ctl.scala 341:33] + assign io_decode_exu_i0_ap_sh1add = _T_80 ? 1'h0 : i0_dp_raw_sh1add; // @[dec_decode_ctl.scala 322:33] + assign io_decode_exu_i0_ap_sh2add = _T_80 ? 1'h0 : i0_dp_raw_sh2add; // @[dec_decode_ctl.scala 323:33] + assign io_decode_exu_i0_ap_sh3add = _T_80 ? 1'h0 : i0_dp_raw_sh3add; // @[dec_decode_ctl.scala 324:33] + assign io_decode_exu_i0_ap_zba = _T_80 ? 1'h0 : i0_dp_raw_zba; // @[dec_decode_ctl.scala 325:33] + assign io_decode_exu_i0_ap_land = _T_80 ? 1'h0 : i0_dp_raw_land; // @[dec_decode_ctl.scala 305:33] + assign io_decode_exu_i0_ap_lor = _T_80 | i0_dp_raw_lor; // @[dec_decode_ctl.scala 306:33] + assign io_decode_exu_i0_ap_lxor = _T_80 ? 1'h0 : i0_dp_raw_lxor; // @[dec_decode_ctl.scala 307:33] + assign io_decode_exu_i0_ap_sll = _T_80 ? 1'h0 : i0_dp_raw_sll; // @[dec_decode_ctl.scala 308:33] + assign io_decode_exu_i0_ap_srl = _T_80 ? 1'h0 : i0_dp_raw_srl; // @[dec_decode_ctl.scala 309:33] + assign io_decode_exu_i0_ap_sra = _T_80 ? 1'h0 : i0_dp_raw_sra; // @[dec_decode_ctl.scala 310:33] + assign io_decode_exu_i0_ap_beq = _T_80 ? 1'h0 : i0_dp_raw_beq; // @[dec_decode_ctl.scala 313:33] + assign io_decode_exu_i0_ap_bne = _T_80 ? 1'h0 : i0_dp_raw_bne; // @[dec_decode_ctl.scala 314:33] + assign io_decode_exu_i0_ap_blt = _T_80 ? 1'h0 : i0_dp_raw_blt; // @[dec_decode_ctl.scala 315:33] + assign io_decode_exu_i0_ap_bge = _T_80 ? 1'h0 : i0_dp_raw_bge; // @[dec_decode_ctl.scala 316:33] + assign io_decode_exu_i0_ap_add = _T_80 ? 1'h0 : i0_dp_raw_add; // @[dec_decode_ctl.scala 303:33] + assign io_decode_exu_i0_ap_sub = _T_80 ? 1'h0 : i0_dp_raw_sub; // @[dec_decode_ctl.scala 304:33] + assign io_decode_exu_i0_ap_slt = _T_80 ? 1'h0 : i0_dp_raw_slt; // @[dec_decode_ctl.scala 311:33] + assign io_decode_exu_i0_ap_unsign = _T_80 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 312:33] + assign io_decode_exu_i0_ap_jal = _T_421 & _T_422; // @[dec_decode_ctl.scala 344:33] + assign io_decode_exu_i0_ap_predict_t = _T_86 & i0_predict_br; // @[dec_decode_ctl.scala 300:37] + assign io_decode_exu_i0_ap_predict_nt = _T_87 & i0_predict_br; // @[dec_decode_ctl.scala 299:37] + assign io_decode_exu_i0_ap_csr_write = i0_csr_write & _T_433; // @[dec_decode_ctl.scala 342:33] + assign io_decode_exu_i0_ap_csr_imm = _T_80 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 343:33] + assign io_decode_exu_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[dec_decode_ctl.scala 232:57] + assign io_decode_exu_dec_i0_predict_p_d_bits_misp = 1'h0; // @[dec_decode_ctl.scala 223:57] + assign io_decode_exu_dec_i0_predict_p_d_bits_ataken = 1'h0; // @[dec_decode_ctl.scala 224:57] + assign io_decode_exu_dec_i0_predict_p_d_bits_boffset = 1'h0; // @[dec_decode_ctl.scala 225:57] + assign io_decode_exu_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 230:57] + assign io_decode_exu_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_bits_hist; // @[dec_decode_ctl.scala 231:57] + assign io_decode_exu_dec_i0_predict_p_d_bits_toffset = _T_399 ? i0_pcall_imm[11:0] : _T_408; // @[dec_decode_ctl.scala 244:58] + assign io_decode_exu_dec_i0_predict_p_d_bits_br_error = _T_71 & _T_50; // @[dec_decode_ctl.scala 239:58] + assign io_decode_exu_dec_i0_predict_p_d_bits_br_start_error = _T_74 & _T_50; // @[dec_decode_ctl.scala 240:58] + assign io_decode_exu_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 226:57] + assign io_decode_exu_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 227:57] + assign io_decode_exu_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_bits_way; // @[dec_decode_ctl.scala 246:58] + assign io_decode_exu_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 228:57] + assign io_decode_exu_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_bits_prett; // @[dec_decode_ctl.scala 229:57] + assign io_decode_exu_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[dec_decode_ctl.scala 245:58] + assign io_decode_exu_i0_predict_index_d = io_dec_i0_bp_index; // @[dec_decode_ctl.scala 241:58] + assign io_decode_exu_i0_predict_btag_d = io_dec_i0_bp_btag; // @[dec_decode_ctl.scala 242:58] + assign io_decode_exu_dec_i0_rs1_en_d = i0_dp_rs1 & _T_657; // @[dec_decode_ctl.scala 680:35] + assign io_decode_exu_dec_i0_branch_d = _T_610 | i0_br_error_all; // @[dec_decode_ctl.scala 631:37] + assign io_decode_exu_dec_i0_rs2_en_d = i0_dp_rs2 & _T_659; // @[dec_decode_ctl.scala 681:35] + assign io_decode_exu_dec_i0_immed_d = _T_787 | _T_784; // @[dec_decode_ctl.scala 693:32] + assign io_decode_exu_dec_i0_result_r = i0_result_r_raw; // @[dec_decode_ctl.scala 919:41] + assign io_decode_exu_dec_i0_select_pc_d = _T_80 ? 1'h0 : i0_dp_raw_pc; // @[dec_decode_ctl.scala 291:36] + assign io_decode_exu_dec_i0_rs1_bypass_en_d = {_T_1064,_T_1063}; // @[dec_decode_ctl.scala 916:45] + assign io_decode_exu_dec_i0_rs2_bypass_en_d = {_T_1079,_T_1078}; // @[dec_decode_ctl.scala 917:45] + assign io_decode_exu_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 471:32] + assign io_decode_exu_mul_p_bits_rs1_sign = _T_80 ? 1'h0 : i0_dp_raw_rs1_sign; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 472:37] + assign io_decode_exu_mul_p_bits_rs2_sign = _T_80 ? 1'h0 : i0_dp_raw_rs2_sign; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 473:37] + assign io_decode_exu_mul_p_bits_low = _T_80 ? 1'h0 : i0_dp_raw_low; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 474:37] + assign io_decode_exu_mul_p_bits_bext = _T_80 ? 1'h0 : i0_dp_raw_bext; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 475:37] + assign io_decode_exu_mul_p_bits_bdep = _T_80 ? 1'h0 : i0_dp_raw_bdep; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 476:37] + assign io_decode_exu_mul_p_bits_clmul = _T_80 ? 1'h0 : i0_dp_raw_clmul; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 477:37] + assign io_decode_exu_mul_p_bits_clmulh = _T_80 ? 1'h0 : i0_dp_raw_clmulh; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 478:37] + assign io_decode_exu_mul_p_bits_clmulr = _T_80 ? 1'h0 : i0_dp_raw_clmulr; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 479:37] + assign io_decode_exu_mul_p_bits_grev = _T_80 ? 1'h0 : i0_dp_raw_grev; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 480:37] + assign io_decode_exu_mul_p_bits_gorc = _T_80 ? 1'h0 : i0_dp_raw_gorc; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 481:37] + assign io_decode_exu_mul_p_bits_shfl = _T_80 ? 1'h0 : i0_dp_raw_shfl; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 482:37] + assign io_decode_exu_mul_p_bits_unshfl = _T_80 ? 1'h0 : i0_dp_raw_unshfl; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 483:37] + assign io_decode_exu_mul_p_bits_crc32_b = _T_80 ? 1'h0 : i0_dp_raw_crc32_b; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 484:37] + assign io_decode_exu_mul_p_bits_crc32_h = _T_80 ? 1'h0 : i0_dp_raw_crc32_h; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 485:37] + assign io_decode_exu_mul_p_bits_crc32_w = _T_80 ? 1'h0 : i0_dp_raw_crc32_w; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 486:37] + assign io_decode_exu_mul_p_bits_crc32c_b = _T_80 ? 1'h0 : i0_dp_raw_crc32c_b; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 487:37] + assign io_decode_exu_mul_p_bits_crc32c_h = _T_80 ? 1'h0 : i0_dp_raw_crc32c_h; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 488:37] + assign io_decode_exu_mul_p_bits_crc32c_w = _T_80 ? 1'h0 : i0_dp_raw_crc32c_w; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 489:37] + assign io_decode_exu_mul_p_bits_bfp = _T_80 ? 1'h0 : i0_dp_raw_bfp; // @[dec_decode_ctl.scala 117:25 dec_decode_ctl.scala 490:37] + assign io_decode_exu_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[dec_decode_ctl.scala 877:36] + assign io_decode_exu_dec_extint_stall = _T_12; // @[dec_decode_ctl.scala 208:35] + assign io_dec_alu_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[dec_decode_ctl.scala 630:34] + assign io_dec_alu_dec_csr_ren_d = i0_dp_csr_read & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 516:29] + assign io_dec_alu_dec_i0_br_immed_d = _T_885 ? i0_br_offset : _T_898; // @[dec_decode_ctl.scala 823:32] + assign io_dec_div_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 467:29] + assign io_dec_div_div_p_bits_unsign = _T_80 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 468:34] + assign io_dec_div_div_p_bits_rem = _T_80 ? 1'h0 : i0_dp_raw_rem; // @[dec_decode_ctl.scala 469:34] + assign io_dec_div_dec_div_cancel = _T_927 | _T_932; // @[dec_decode_ctl.scala 842:37] + assign io_dec_aln_dec_i0_decode_d = _T_589 & _T_567; // @[dec_decode_ctl.scala 611:30 dec_decode_ctl.scala 674:30] + assign io_dec_i0_inst_wb = i0_inst_wb; // @[dec_decode_ctl.scala 868:21] + assign io_dec_i0_pc_wb = i0_pc_wb; // @[dec_decode_ctl.scala 869:19] + assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 683:19] + assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 684:19] + assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[dec_decode_ctl.scala 805:27] + assign io_dec_i0_wen_r = _T_871 & _T_872; // @[dec_decode_ctl.scala 807:32] + assign io_dec_i0_wdata_r = _T_881 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 808:26] + assign io_dec_qual_lsu_d = _T_80 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 636:21] + assign io_lsu_p_valid = io_decode_exu_dec_extint_stall | lsu_decode_d; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 498:24 dec_decode_ctl.scala 502:35] + assign io_lsu_p_bits_fast_int = io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 497:29] + assign io_lsu_p_bits_stack = io_decode_exu_dec_extint_stall ? 1'h0 : _T_425; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 508:29] + assign io_lsu_p_bits_by = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_by; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 505:40] + assign io_lsu_p_bits_half = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_half; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 506:40] + assign io_lsu_p_bits_word = io_decode_exu_dec_extint_stall | i0_dp_word; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 496:29 dec_decode_ctl.scala 507:40] + assign io_lsu_p_bits_dword = 1'h0; // @[dec_decode_ctl.scala 493:12] + assign io_lsu_p_bits_load = io_decode_exu_dec_extint_stall | i0_dp_load; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 495:29 dec_decode_ctl.scala 503:40] + assign io_lsu_p_bits_store = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_store; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 504:40] + assign io_lsu_p_bits_unsign = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 512:40] + assign io_lsu_p_bits_dma = 1'h0; // @[dec_decode_ctl.scala 493:12] + assign io_lsu_p_bits_store_data_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 510:40] + assign io_lsu_p_bits_load_ldst_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 509:40] + assign io_lsu_p_bits_store_data_bypass_m = 1'h0; // @[dec_decode_ctl.scala 493:12 dec_decode_ctl.scala 511:40] + assign io_div_waddr_wb = _T_947; // @[dec_decode_ctl.scala 860:19] + assign io_dec_lsu_valid_raw_d = _T_1086 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 921:26] + assign io_dec_lsu_offset_d = _T_1100 | _T_1101; // @[dec_decode_ctl.scala 922:23] + assign io_dec_csr_wen_unq_d = _T_436 & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 525:24] + assign io_dec_csr_any_unq_d = any_csr_d & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 528:24] + assign io_dec_csr_rdaddr_d = _T_440 & io_dec_i0_instr_d[31:20]; // @[dec_decode_ctl.scala 529:24] + assign io_dec_csr_wen_r = _T_443 & _T_868; // @[dec_decode_ctl.scala 534:20] + assign io_dec_csr_wraddr_r = _T_445 & r_d_bits_csrwaddr; // @[dec_decode_ctl.scala 530:24] + assign io_dec_csr_wrdata_r = _T_529 ? i0_result_corr_r : write_csr_data; // @[dec_decode_ctl.scala 574:24] + assign io_dec_csr_stall_int_ff = _T_454 & _T_455; // @[dec_decode_ctl.scala 537:27] + assign io_dec_tlu_i0_valid_r = r_d_valid & _T_857; // @[dec_decode_ctl.scala 637:29] + assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_icaf_second = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_second; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_644; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 669:39 dec_decode_ctl.scala 670:39] + assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 669:39] + assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[dec_decode_ctl.scala 872:27] + assign io_dec_illegal_inst = _T_565; // @[dec_decode_ctl.scala 596:23] + assign io_dec_fa_error_index = 9'h0; // @[dec_decode_ctl.scala 255:29] + assign io_dec_pmu_instr_decoded = io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 616:28] + assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_597; // @[dec_decode_ctl.scala 617:27] + assign io_dec_pmu_presync_stall = presync_stall & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 619:29] + assign io_dec_pmu_postsync_stall = postsync_stall & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 618:29] + assign io_dec_nonblock_load_wen = _T_279 & _T_280; // @[dec_decode_ctl.scala 399:28] + assign io_dec_nonblock_load_waddr = _T_325 | _T_317; // @[dec_decode_ctl.scala 396:29 dec_decode_ctl.scala 406:29] + assign io_dec_pause_state = pause_stall; // @[dec_decode_ctl.scala 560:22] + assign io_dec_pause_state_cg = pause_stall & _T_519; // @[dec_decode_ctl.scala 562:25] + assign io_dec_div_active = _T_42; // @[dec_decode_ctl.scala 217:35] + assign i0_dec_io_ins = io_dec_i0_instr_d; // @[dec_decode_ctl.scala 439:16] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = i0_x_data_en & any_csr_d; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = i0_x_data_en & any_csr_d; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = _T_527 | pause_stall; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = shift_illegal & _T_564; // @[lib.scala 407:17] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_4_io_en = i0_r_data_en & _T_875; // @[lib.scala 407:17] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_5_io_en = i0_pipe_en[3] | io_clk_override; // @[lib.scala 407:17] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_6_io_en = i0_legal_decode_d & i0_dp_div; // @[lib.scala 407:17] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_7_io_en = i0_x_data_en & trace_enable; // @[lib.scala 407:17] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_8_io_en = i0_r_data_en & trace_enable; // @[lib.scala 407:17] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_9_io_en = i0_wb_data_en & trace_enable; // @[lib.scala 407:17] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_10_io_en = i0_wb_data_en & trace_enable; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + leak1_i1_stall = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + leak1_i0_stall = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_12 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + pause_stall = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + write_csr_data = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + tlu_wr_pause_r1 = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + tlu_wr_pause_r2 = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + illegal_lockout = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + flush_final_r = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + postsync_stall = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + x_d_valid = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + lsu_trigger_match_r = _RAND_11[3:0]; + _RAND_12 = {1{`RANDOM}}; + lsu_pmu_misaligned_r = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + x_d_bits_i0div = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + x_d_bits_i0rd = _RAND_14[4:0]; + _RAND_15 = {1{`RANDOM}}; + r_d_bits_i0div = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + r_d_valid = _RAND_16[0:0]; + _RAND_17 = {1{`RANDOM}}; + r_d_bits_i0rd = _RAND_17[4:0]; + _RAND_18 = {1{`RANDOM}}; + r_d_bits_i0v = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + _T_42 = _RAND_19[0:0]; + _RAND_20 = {1{`RANDOM}}; + debug_valid_x = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + cam_raw_0_bits_tag = _RAND_21[2:0]; + _RAND_22 = {1{`RANDOM}}; + cam_raw_0_valid = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + cam_raw_1_bits_tag = _RAND_23[2:0]; + _RAND_24 = {1{`RANDOM}}; + cam_raw_1_valid = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + cam_raw_2_bits_tag = _RAND_25[2:0]; + _RAND_26 = {1{`RANDOM}}; + cam_raw_2_valid = _RAND_26[0:0]; + _RAND_27 = {1{`RANDOM}}; + cam_raw_3_bits_tag = _RAND_27[2:0]; + _RAND_28 = {1{`RANDOM}}; + cam_raw_3_valid = _RAND_28[0:0]; + _RAND_29 = {1{`RANDOM}}; + x_d_bits_i0load = _RAND_29[0:0]; + _RAND_30 = {1{`RANDOM}}; + _T_815 = _RAND_30[2:0]; + _RAND_31 = {1{`RANDOM}}; + nonblock_load_valid_m_delay = _RAND_31[0:0]; + _RAND_32 = {1{`RANDOM}}; + r_d_bits_i0load = _RAND_32[0:0]; + _RAND_33 = {1{`RANDOM}}; + cam_raw_0_bits_rd = _RAND_33[4:0]; + _RAND_34 = {1{`RANDOM}}; + cam_raw_0_bits_wb = _RAND_34[0:0]; + _RAND_35 = {1{`RANDOM}}; + cam_raw_1_bits_rd = _RAND_35[4:0]; + _RAND_36 = {1{`RANDOM}}; + cam_raw_1_bits_wb = _RAND_36[0:0]; + _RAND_37 = {1{`RANDOM}}; + cam_raw_2_bits_rd = _RAND_37[4:0]; + _RAND_38 = {1{`RANDOM}}; + cam_raw_2_bits_wb = _RAND_38[0:0]; + _RAND_39 = {1{`RANDOM}}; + cam_raw_3_bits_rd = _RAND_39[4:0]; + _RAND_40 = {1{`RANDOM}}; + cam_raw_3_bits_wb = _RAND_40[0:0]; + _RAND_41 = {1{`RANDOM}}; + lsu_idle = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + x_d_bits_i0v = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + i0_x_c_load = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + i0_r_c_load = _RAND_44[0:0]; + _RAND_45 = {1{`RANDOM}}; + r_d_bits_csrwen = _RAND_45[0:0]; + _RAND_46 = {1{`RANDOM}}; + r_d_bits_csrwaddr = _RAND_46[11:0]; + _RAND_47 = {1{`RANDOM}}; + csr_read_x = _RAND_47[0:0]; + _RAND_48 = {1{`RANDOM}}; + csr_clr_x = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + csr_set_x = _RAND_49[0:0]; + _RAND_50 = {1{`RANDOM}}; + csr_write_x = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + csr_imm_x = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + csrimm_x = _RAND_52[4:0]; + _RAND_53 = {1{`RANDOM}}; + csr_rddata_x = _RAND_53[31:0]; + _RAND_54 = {1{`RANDOM}}; + r_d_bits_csrwonly = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + i0_result_r_raw = _RAND_55[31:0]; + _RAND_56 = {1{`RANDOM}}; + x_d_bits_csrwonly = _RAND_56[0:0]; + _RAND_57 = {1{`RANDOM}}; + wbd_bits_csrwonly = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + _T_565 = _RAND_58[31:0]; + _RAND_59 = {1{`RANDOM}}; + x_t_legal = _RAND_59[0:0]; + _RAND_60 = {1{`RANDOM}}; + x_t_icaf = _RAND_60[0:0]; + _RAND_61 = {1{`RANDOM}}; + x_t_icaf_second = _RAND_61[0:0]; + _RAND_62 = {1{`RANDOM}}; + x_t_icaf_type = _RAND_62[1:0]; + _RAND_63 = {1{`RANDOM}}; + x_t_fence_i = _RAND_63[0:0]; + _RAND_64 = {1{`RANDOM}}; + x_t_i0trigger = _RAND_64[3:0]; + _RAND_65 = {1{`RANDOM}}; + x_t_pmu_i0_itype = _RAND_65[3:0]; + _RAND_66 = {1{`RANDOM}}; + x_t_pmu_i0_br_unpred = _RAND_66[0:0]; + _RAND_67 = {1{`RANDOM}}; + r_t_legal = _RAND_67[0:0]; + _RAND_68 = {1{`RANDOM}}; + r_t_icaf = _RAND_68[0:0]; + _RAND_69 = {1{`RANDOM}}; + r_t_icaf_second = _RAND_69[0:0]; + _RAND_70 = {1{`RANDOM}}; + r_t_icaf_type = _RAND_70[1:0]; + _RAND_71 = {1{`RANDOM}}; + r_t_fence_i = _RAND_71[0:0]; + _RAND_72 = {1{`RANDOM}}; + r_t_i0trigger = _RAND_72[3:0]; + _RAND_73 = {1{`RANDOM}}; + r_t_pmu_i0_itype = _RAND_73[3:0]; + _RAND_74 = {1{`RANDOM}}; + r_t_pmu_i0_br_unpred = _RAND_74[0:0]; + _RAND_75 = {1{`RANDOM}}; + r_d_bits_i0store = _RAND_75[0:0]; + _RAND_76 = {1{`RANDOM}}; + i0_x_c_mul = _RAND_76[0:0]; + _RAND_77 = {1{`RANDOM}}; + i0_x_c_alu = _RAND_77[0:0]; + _RAND_78 = {1{`RANDOM}}; + i0_r_c_mul = _RAND_78[0:0]; + _RAND_79 = {1{`RANDOM}}; + i0_r_c_alu = _RAND_79[0:0]; + _RAND_80 = {1{`RANDOM}}; + x_d_bits_i0store = _RAND_80[0:0]; + _RAND_81 = {1{`RANDOM}}; + x_d_bits_csrwen = _RAND_81[0:0]; + _RAND_82 = {1{`RANDOM}}; + x_d_bits_csrwaddr = _RAND_82[11:0]; + _RAND_83 = {1{`RANDOM}}; + last_br_immed_x = _RAND_83[11:0]; + _RAND_84 = {1{`RANDOM}}; + _T_947 = _RAND_84[4:0]; + _RAND_85 = {1{`RANDOM}}; + i0_inst_x = _RAND_85[31:0]; + _RAND_86 = {1{`RANDOM}}; + i0_inst_r = _RAND_86[31:0]; + _RAND_87 = {1{`RANDOM}}; + i0_inst_wb = _RAND_87[31:0]; + _RAND_88 = {1{`RANDOM}}; + i0_pc_wb = _RAND_88[30:0]; + _RAND_89 = {1{`RANDOM}}; + dec_i0_pc_r = _RAND_89[30:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + leak1_i1_stall = 1'h0; + end + if (reset) begin + leak1_i0_stall = 1'h0; + end + if (reset) begin + _T_12 = 1'h0; + end + if (reset) begin + pause_stall = 1'h0; + end + if (reset) begin + write_csr_data = 32'h0; + end + if (reset) begin + tlu_wr_pause_r1 = 1'h0; + end + if (reset) begin + tlu_wr_pause_r2 = 1'h0; + end + if (reset) begin + illegal_lockout = 1'h0; + end + if (reset) begin + flush_final_r = 1'h0; + end + if (reset) begin + postsync_stall = 1'h0; + end + if (reset) begin + x_d_valid = 1'h0; + end + if (reset) begin + lsu_trigger_match_r = 4'h0; + end + if (reset) begin + lsu_pmu_misaligned_r = 1'h0; + end + if (reset) begin + x_d_bits_i0div = 1'h0; + end + if (reset) begin + x_d_bits_i0rd = 5'h0; + end + if (reset) begin + r_d_bits_i0div = 1'h0; + end + if (reset) begin + r_d_valid = 1'h0; + end + if (reset) begin + r_d_bits_i0rd = 5'h0; + end + if (reset) begin + r_d_bits_i0v = 1'h0; + end + if (reset) begin + _T_42 = 1'h0; + end + if (reset) begin + debug_valid_x = 1'h0; + end + if (reset) begin + cam_raw_0_bits_tag = 3'h0; + end + if (reset) begin + cam_raw_0_valid = 1'h0; + end + if (reset) begin + cam_raw_1_bits_tag = 3'h0; + end + if (reset) begin + cam_raw_1_valid = 1'h0; + end + if (reset) begin + cam_raw_2_bits_tag = 3'h0; + end + if (reset) begin + cam_raw_2_valid = 1'h0; + end + if (reset) begin + cam_raw_3_bits_tag = 3'h0; + end + if (reset) begin + cam_raw_3_valid = 1'h0; + end + if (reset) begin + x_d_bits_i0load = 1'h0; + end + if (reset) begin + _T_815 = 3'h0; + end + if (reset) begin + nonblock_load_valid_m_delay = 1'h0; + end + if (reset) begin + r_d_bits_i0load = 1'h0; + end + if (reset) begin + cam_raw_0_bits_rd = 5'h0; + end + if (reset) begin + cam_raw_0_bits_wb = 1'h0; + end + if (reset) begin + cam_raw_1_bits_rd = 5'h0; + end + if (reset) begin + cam_raw_1_bits_wb = 1'h0; + end + if (reset) begin + cam_raw_2_bits_rd = 5'h0; + end + if (reset) begin + cam_raw_2_bits_wb = 1'h0; + end + if (reset) begin + cam_raw_3_bits_rd = 5'h0; + end + if (reset) begin + cam_raw_3_bits_wb = 1'h0; + end + if (reset) begin + lsu_idle = 1'h0; + end + if (reset) begin + x_d_bits_i0v = 1'h0; + end + if (reset) begin + i0_x_c_load = 1'h0; + end + if (reset) begin + i0_r_c_load = 1'h0; + end + if (reset) begin + r_d_bits_csrwen = 1'h0; + end + if (reset) begin + r_d_bits_csrwaddr = 12'h0; + end + if (reset) begin + csr_read_x = 1'h0; + end + if (reset) begin + csr_clr_x = 1'h0; + end + if (reset) begin + csr_set_x = 1'h0; + end + if (reset) begin + csr_write_x = 1'h0; + end + if (reset) begin + csr_imm_x = 1'h0; + end + if (reset) begin + csrimm_x = 5'h0; + end + if (reset) begin + csr_rddata_x = 32'h0; + end + if (reset) begin + r_d_bits_csrwonly = 1'h0; + end + if (reset) begin + i0_result_r_raw = 32'h0; + end + if (reset) begin + x_d_bits_csrwonly = 1'h0; + end + if (reset) begin + wbd_bits_csrwonly = 1'h0; + end + if (reset) begin + _T_565 = 32'h0; + end + if (reset) begin + x_t_legal = 1'h0; + end + if (reset) begin + x_t_icaf = 1'h0; + end + if (reset) begin + x_t_icaf_second = 1'h0; + end + if (reset) begin + x_t_icaf_type = 2'h0; + end + if (reset) begin + x_t_fence_i = 1'h0; + end + if (reset) begin + x_t_i0trigger = 4'h0; + end + if (reset) begin + x_t_pmu_i0_itype = 4'h0; + end + if (reset) begin + x_t_pmu_i0_br_unpred = 1'h0; + end + if (reset) begin + r_t_legal = 1'h0; + end + if (reset) begin + r_t_icaf = 1'h0; + end + if (reset) begin + r_t_icaf_second = 1'h0; + end + if (reset) begin + r_t_icaf_type = 2'h0; + end + if (reset) begin + r_t_fence_i = 1'h0; + end + if (reset) begin + r_t_i0trigger = 4'h0; + end + if (reset) begin + r_t_pmu_i0_itype = 4'h0; + end + if (reset) begin + r_t_pmu_i0_br_unpred = 1'h0; + end + if (reset) begin + r_d_bits_i0store = 1'h0; + end + if (reset) begin + i0_x_c_mul = 1'h0; + end + if (reset) begin + i0_x_c_alu = 1'h0; + end + if (reset) begin + i0_r_c_mul = 1'h0; + end + if (reset) begin + i0_r_c_alu = 1'h0; + end + if (reset) begin + x_d_bits_i0store = 1'h0; + end + if (reset) begin + x_d_bits_csrwen = 1'h0; + end + if (reset) begin + x_d_bits_csrwaddr = 12'h0; + end + if (reset) begin + last_br_immed_x = 12'h0; + end + if (reset) begin + _T_947 = 5'h0; + end + if (reset) begin + i0_inst_x = 32'h0; + end + if (reset) begin + i0_inst_r = 32'h0; + end + if (reset) begin + i0_inst_wb = 32'h0; + end + if (reset) begin + i0_pc_wb = 31'h0; + end + if (reset) begin + dec_i0_pc_r = 31'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + leak1_i1_stall <= 1'h0; + end else if (_T_3) begin + leak1_i1_stall <= leak1_i1_stall_in; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + leak1_i0_stall <= 1'h0; + end else if (_T_7) begin + leak1_i0_stall <= leak1_i0_stall_in; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_12 <= 1'h0; + end else if (_T_11) begin + _T_12 <= io_dec_tlu_flush_extint; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + pause_stall <= 1'h0; + end else if (_T_15) begin + pause_stall <= pause_state_in; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + write_csr_data <= 32'h0; + end else if (csr_data_wen) begin + if (pause_stall) begin + write_csr_data <= _T_522; + end else if (io_dec_tlu_wr_pause_r) begin + write_csr_data <= io_dec_csr_wrdata_r; + end else begin + write_csr_data <= write_csr_data_x; + end + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + tlu_wr_pause_r1 <= 1'h0; + end else if (_T_19) begin + tlu_wr_pause_r1 <= io_dec_tlu_wr_pause_r; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + tlu_wr_pause_r2 <= 1'h0; + end else if (_T_23) begin + tlu_wr_pause_r2 <= tlu_wr_pause_r1; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + illegal_lockout <= 1'h0; + end else if (_T_27) begin + illegal_lockout <= illegal_lockout_in; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + flush_final_r <= 1'h0; + end else if (_T_45) begin + flush_final_r <= io_exu_flush_final; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + postsync_stall <= 1'h0; + end else if (_T_31) begin + postsync_stall <= ps_stall_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_d_valid <= 1'h0; + end else if (i0_x_ctl_en) begin + x_d_valid <= io_dec_aln_dec_i0_decode_d; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + lsu_trigger_match_r <= 4'h0; + end else if (_T_34) begin + lsu_trigger_match_r <= io_lsu_trigger_match_m; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + lsu_pmu_misaligned_r <= 1'h0; + end else if (_T_37) begin + lsu_pmu_misaligned_r <= io_lsu_pmu_misaligned_m; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_d_bits_i0div <= 1'h0; + end else if (i0_x_ctl_en) begin + x_d_bits_i0div <= d_d_bits_i0div; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_d_bits_i0rd <= 5'h0; + end else if (i0_x_ctl_en) begin + x_d_bits_i0rd <= i0r_rd; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_d_bits_i0div <= 1'h0; + end else if (i0_r_ctl_en) begin + r_d_bits_i0div <= x_d_bits_i0div; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_d_valid <= 1'h0; + end else if (i0_r_ctl_en) begin + r_d_valid <= x_d_in_valid; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_d_bits_i0rd <= 5'h0; + end else if (i0_r_ctl_en) begin + r_d_bits_i0rd <= x_d_bits_i0rd; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_d_bits_i0v <= 1'h0; + end else if (i0_r_ctl_en) begin + r_d_bits_i0v <= x_d_in_bits_i0v; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_42 <= 1'h0; + end else if (_T_41) begin + _T_42 <= div_active_in; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + debug_valid_x <= 1'h0; + end else if (_T_48) begin + debug_valid_x <= io_dec_debug_valid_d; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_0_bits_tag <= 3'h0; + end else if (_T_161) begin + if (cam_wen[0]) begin + cam_raw_0_bits_tag <= {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m}; + end else if (_T_146) begin + cam_raw_0_bits_tag <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_0_valid <= 1'h0; + end else if (_T_161) begin + if (io_dec_tlu_force_halt) begin + cam_raw_0_valid <= 1'h0; + end else begin + cam_raw_0_valid <= _GEN_114; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_1_bits_tag <= 3'h0; + end else if (_T_197) begin + if (cam_wen[1]) begin + cam_raw_1_bits_tag <= {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m}; + end else if (_T_182) begin + cam_raw_1_bits_tag <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_1_valid <= 1'h0; + end else if (_T_197) begin + if (io_dec_tlu_force_halt) begin + cam_raw_1_valid <= 1'h0; + end else begin + cam_raw_1_valid <= _GEN_129; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_2_bits_tag <= 3'h0; + end else if (_T_233) begin + if (cam_wen[2]) begin + cam_raw_2_bits_tag <= {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m}; + end else if (_T_218) begin + cam_raw_2_bits_tag <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_2_valid <= 1'h0; + end else if (_T_233) begin + if (io_dec_tlu_force_halt) begin + cam_raw_2_valid <= 1'h0; + end else begin + cam_raw_2_valid <= _GEN_144; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_3_bits_tag <= 3'h0; + end else if (_T_269) begin + if (cam_wen[3]) begin + cam_raw_3_bits_tag <= {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_tag_m}; + end else if (_T_254) begin + cam_raw_3_bits_tag <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_3_valid <= 1'h0; + end else if (_T_269) begin + if (io_dec_tlu_force_halt) begin + cam_raw_3_valid <= 1'h0; + end else begin + cam_raw_3_valid <= _GEN_159; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_d_bits_i0load <= 1'h0; + end else if (i0_x_ctl_en) begin + x_d_bits_i0load <= i0_d_c_load; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_815 <= 3'h0; + end else begin + _T_815 <= i0_pipe_en[3:1]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + nonblock_load_valid_m_delay <= 1'h0; + end else if (i0_r_ctl_en) begin + nonblock_load_valid_m_delay <= io_dctl_busbuff_lsu_nonblock_load_valid_m; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_d_bits_i0load <= 1'h0; + end else if (i0_r_ctl_en) begin + r_d_bits_i0load <= x_d_bits_i0load; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_0_bits_rd <= 5'h0; + end else if (_T_161) begin + if (cam_wen[0]) begin + if (x_d_bits_i0load) begin + cam_raw_0_bits_rd <= x_d_bits_i0rd; + end else begin + cam_raw_0_bits_rd <= 5'h0; + end + end else if (_T_146) begin + cam_raw_0_bits_rd <= 5'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_0_bits_wb <= 1'h0; + end else if (_T_161) begin + cam_raw_0_bits_wb <= cam_in_0_bits_wb; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_1_bits_rd <= 5'h0; + end else if (_T_197) begin + if (cam_wen[1]) begin + if (x_d_bits_i0load) begin + cam_raw_1_bits_rd <= x_d_bits_i0rd; + end else begin + cam_raw_1_bits_rd <= 5'h0; + end + end else if (_T_182) begin + cam_raw_1_bits_rd <= 5'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_1_bits_wb <= 1'h0; + end else if (_T_197) begin + cam_raw_1_bits_wb <= cam_in_1_bits_wb; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_2_bits_rd <= 5'h0; + end else if (_T_233) begin + if (cam_wen[2]) begin + if (x_d_bits_i0load) begin + cam_raw_2_bits_rd <= x_d_bits_i0rd; + end else begin + cam_raw_2_bits_rd <= 5'h0; + end + end else if (_T_218) begin + cam_raw_2_bits_rd <= 5'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_2_bits_wb <= 1'h0; + end else if (_T_233) begin + cam_raw_2_bits_wb <= cam_in_2_bits_wb; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_3_bits_rd <= 5'h0; + end else if (_T_269) begin + if (cam_wen[3]) begin + if (x_d_bits_i0load) begin + cam_raw_3_bits_rd <= x_d_bits_i0rd; + end else begin + cam_raw_3_bits_rd <= 5'h0; + end + end else if (_T_254) begin + cam_raw_3_bits_rd <= 5'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cam_raw_3_bits_wb <= 1'h0; + end else if (_T_269) begin + cam_raw_3_bits_wb <= cam_in_3_bits_wb; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + lsu_idle <= 1'h0; + end else begin + lsu_idle <= io_lsu_idle_any; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_d_bits_i0v <= 1'h0; + end else if (i0_x_ctl_en) begin + x_d_bits_i0v <= d_d_bits_i0v; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + i0_x_c_load <= 1'h0; + end else if (i0_x_ctl_en) begin + i0_x_c_load <= i0_d_c_load; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + i0_r_c_load <= 1'h0; + end else if (i0_r_ctl_en) begin + i0_r_c_load <= i0_x_c_load; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_d_bits_csrwen <= 1'h0; + end else if (i0_r_ctl_en) begin + r_d_bits_csrwen <= x_d_bits_csrwen; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_d_bits_csrwaddr <= 12'h0; + end else if (i0_r_ctl_en) begin + r_d_bits_csrwaddr <= x_d_bits_csrwaddr; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_read_x <= 1'h0; + end else begin + csr_read_x <= i0_dp_csr_read & i0_legal_decode_d; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_clr_x <= 1'h0; + end else begin + csr_clr_x <= i0_dp_csr_clr & i0_legal_decode_d; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_set_x <= 1'h0; + end else begin + csr_set_x <= i0_dp_csr_set & i0_legal_decode_d; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_write_x <= 1'h0; + end else begin + csr_write_x <= i0_csr_write & i0_legal_decode_d; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_imm_x <= 1'h0; + end else if (_T_80) begin + csr_imm_x <= 1'h0; + end else begin + csr_imm_x <= i0_dp_raw_csr_imm; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + csrimm_x <= 5'h0; + end else if (_T_459) begin + csrimm_x <= i0r_rs1; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + csr_rddata_x <= 32'h0; + end else if (_T_459) begin + csr_rddata_x <= io_dec_csr_rddata_d; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_d_bits_csrwonly <= 1'h0; + end else if (i0_r_ctl_en) begin + r_d_bits_csrwonly <= x_d_bits_csrwonly; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + i0_result_r_raw <= 32'h0; + end else if (_T_876) begin + if (_T_878) begin + i0_result_r_raw <= io_lsu_result_m; + end else begin + i0_result_r_raw <= io_decode_exu_exu_i0_result_x; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_d_bits_csrwonly <= 1'h0; + end else if (i0_x_ctl_en) begin + x_d_bits_csrwonly <= d_d_bits_csrwonly; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + wbd_bits_csrwonly <= 1'h0; + end else if (i0_wb_ctl_en) begin + wbd_bits_csrwonly <= r_d_bits_csrwonly; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_565 <= 32'h0; + end else if (illegal_inst_en) begin + if (io_dec_i0_pc4_d) begin + _T_565 <= io_dec_i0_instr_d; + end else begin + _T_565 <= _T_562; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_t_legal <= 1'h0; + end else if (i0_x_ctl_en) begin + x_t_legal <= i0_legal_decode_d; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_t_icaf <= 1'h0; + end else if (i0_x_ctl_en) begin + x_t_icaf <= d_t_icaf; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_t_icaf_second <= 1'h0; + end else if (i0_x_ctl_en) begin + x_t_icaf_second <= d_t_icaf_second; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_t_icaf_type <= 2'h0; + end else if (i0_x_ctl_en) begin + x_t_icaf_type <= io_dec_i0_icaf_type_d; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_t_fence_i <= 1'h0; + end else if (i0_x_ctl_en) begin + x_t_fence_i <= d_t_fence_i; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_t_i0trigger <= 4'h0; + end else if (i0_x_ctl_en) begin + x_t_i0trigger <= d_t_i0trigger; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_t_pmu_i0_itype <= 4'h0; + end else if (i0_x_ctl_en) begin + x_t_pmu_i0_itype <= d_t_pmu_i0_itype; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_t_pmu_i0_br_unpred <= 1'h0; + end else if (i0_x_ctl_en) begin + x_t_pmu_i0_br_unpred <= i0_br_unpred; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_t_legal <= 1'h0; + end else if (i0_x_ctl_en) begin + r_t_legal <= x_t_legal; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_t_icaf <= 1'h0; + end else if (i0_x_ctl_en) begin + r_t_icaf <= x_t_icaf; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_t_icaf_second <= 1'h0; + end else if (i0_x_ctl_en) begin + r_t_icaf_second <= x_t_icaf_second; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_t_icaf_type <= 2'h0; + end else if (i0_x_ctl_en) begin + r_t_icaf_type <= x_t_icaf_type; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_t_fence_i <= 1'h0; + end else if (i0_x_ctl_en) begin + r_t_fence_i <= x_t_fence_i; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_t_i0trigger <= 4'h0; + end else if (i0_x_ctl_en) begin + r_t_i0trigger <= x_t_in_i0trigger; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_t_pmu_i0_itype <= 4'h0; + end else if (i0_x_ctl_en) begin + r_t_pmu_i0_itype <= x_t_pmu_i0_itype; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_t_pmu_i0_br_unpred <= 1'h0; + end else if (i0_x_ctl_en) begin + r_t_pmu_i0_br_unpred <= x_t_pmu_i0_br_unpred; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + r_d_bits_i0store <= 1'h0; + end else if (i0_r_ctl_en) begin + r_d_bits_i0store <= x_d_bits_i0store; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + i0_x_c_mul <= 1'h0; + end else if (i0_x_ctl_en) begin + i0_x_c_mul <= i0_d_c_mul; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + i0_x_c_alu <= 1'h0; + end else if (i0_x_ctl_en) begin + i0_x_c_alu <= i0_d_c_alu; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + i0_r_c_mul <= 1'h0; + end else if (i0_r_ctl_en) begin + i0_r_c_mul <= i0_x_c_mul; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + i0_r_c_alu <= 1'h0; + end else if (i0_r_ctl_en) begin + i0_r_c_alu <= i0_x_c_alu; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_d_bits_i0store <= 1'h0; + end else if (i0_x_ctl_en) begin + x_d_bits_i0store <= d_d_bits_i0store; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_d_bits_csrwen <= 1'h0; + end else if (i0_x_ctl_en) begin + x_d_bits_csrwen <= d_d_bits_csrwen; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + x_d_bits_csrwaddr <= 12'h0; + end else if (i0_x_ctl_en) begin + if (d_d_bits_csrwen) begin + x_d_bits_csrwaddr <= io_dec_i0_instr_d[31:20]; + end else begin + x_d_bits_csrwaddr <= 12'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + last_br_immed_x <= 12'h0; + end else if (i0_x_data_en) begin + if (io_decode_exu_i0_ap_predict_nt) begin + last_br_immed_x <= _T_898; + end else if (_T_399) begin + last_br_immed_x <= i0_pcall_imm[11:0]; + end else begin + last_br_immed_x <= _T_408; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_947 <= 5'h0; + end else if (i0_div_decode_d) begin + _T_947 <= i0r_rd; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + i0_inst_x <= 32'h0; + end else if (_T_948) begin + if (io_dec_i0_pc4_d) begin + i0_inst_x <= io_dec_i0_instr_d; + end else begin + i0_inst_x <= _T_562; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + i0_inst_r <= 32'h0; + end else if (_T_950) begin + i0_inst_r <= i0_inst_x; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + i0_inst_wb <= 32'h0; + end else if (_T_952) begin + i0_inst_wb <= i0_inst_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + i0_pc_wb <= 31'h0; + end else if (_T_952) begin + i0_pc_wb <= io_dec_tlu_i0_pc_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + dec_i0_pc_r <= 31'h0; + end else if (i0_r_data_en) begin + dec_i0_pc_r <= io_dec_alu_exu_i0_pc_x; + end + end +endmodule diff --git a/dec_gpr_ctl.anno.json b/dec_gpr_ctl.anno.json new file mode 100644 index 00000000..925ff222 --- /dev/null +++ b/dec_gpr_ctl.anno.json @@ -0,0 +1,37 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_gpr_ctl|dec_gpr_ctl>io_gpr_exu_gpr_i0_rs1_d", + "sources":[ + "~dec_gpr_ctl|dec_gpr_ctl>io_raddr0" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_gpr_ctl|dec_gpr_ctl>io_gpr_exu_gpr_i0_rs2_d", + "sources":[ + "~dec_gpr_ctl|dec_gpr_ctl>io_raddr1" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"dec_gpr_ctl.gated_latch", + "resourceId":"/vsrc/gated_latch.sv" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"dec_gpr_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/dec_gpr_ctl.fir b/dec_gpr_ctl.fir new file mode 100644 index 00000000..eb89150f --- /dev/null +++ b/dec_gpr_ctl.fir @@ -0,0 +1,2297 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit dec_gpr_ctl : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_10 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_11 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_12 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_12 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_12 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_13 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_13 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_13 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_14 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_14 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_14 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_15 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_15 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_15 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_16 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_16 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_16 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_17 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_17 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_17 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_18 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_18 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_18 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_19 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_19 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_19 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_20 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_20 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_20 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_21 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_21 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_21 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_22 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_22 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_22 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_23 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_23 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_23 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_24 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_24 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_24 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_25 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_25 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_25 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_26 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_26 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_26 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_27 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_27 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_27 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_28 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_28 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_28 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_29 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_29 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_29 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_30 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_30 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_30 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module dec_gpr_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip raddr0 : UInt<5>, flip raddr1 : UInt<5>, flip wen0 : UInt<1>, flip waddr0 : UInt<5>, flip wd0 : UInt<32>, flip wen1 : UInt<1>, flip waddr1 : UInt<5>, flip wd1 : UInt<32>, flip wen2 : UInt<1>, flip waddr2 : UInt<5>, flip wd2 : UInt<32>, flip scan_mode : UInt<1>, flip gpr_exu : {flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>}} + + wire w0v : UInt<1>[32] @[dec_gpr_ctl.scala 27:30] + w0v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + w0v[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13] + wire w1v : UInt<1>[32] @[dec_gpr_ctl.scala 30:30] + w1v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + w1v[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13] + wire w2v : UInt<1>[32] @[dec_gpr_ctl.scala 33:30] + w2v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + w2v[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13] + wire gpr_in : UInt<32>[32] @[dec_gpr_ctl.scala 36:30] + gpr_in[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + gpr_in[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16] + wire gpr_out : UInt<32>[32] @[dec_gpr_ctl.scala 39:30] + gpr_out[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + gpr_out[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17] + wire gpr_wr_en : UInt<32> + gpr_wr_en <= UInt<1>("h00") + w0v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 43:15] + w1v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 44:15] + w2v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 45:15] + gpr_out[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 46:19] + gpr_in[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 47:18] + io.gpr_exu.gpr_i0_rs1_d <= UInt<1>("h00") @[dec_gpr_ctl.scala 48:32] + io.gpr_exu.gpr_i0_rs2_d <= UInt<1>("h00") @[dec_gpr_ctl.scala 49:32] + node _T = eq(io.waddr0, UInt<1>("h01")) @[dec_gpr_ctl.scala 52:52] + node _T_1 = and(io.wen0, _T) @[dec_gpr_ctl.scala 52:40] + w0v[1] <= _T_1 @[dec_gpr_ctl.scala 52:28] + node _T_2 = eq(io.waddr1, UInt<1>("h01")) @[dec_gpr_ctl.scala 53:52] + node _T_3 = and(io.wen1, _T_2) @[dec_gpr_ctl.scala 53:40] + w1v[1] <= _T_3 @[dec_gpr_ctl.scala 53:28] + node _T_4 = eq(io.waddr2, UInt<1>("h01")) @[dec_gpr_ctl.scala 54:52] + node _T_5 = and(io.wen2, _T_4) @[dec_gpr_ctl.scala 54:40] + w2v[1] <= _T_5 @[dec_gpr_ctl.scala 54:28] + node _T_6 = bits(w0v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_7 = mux(_T_6, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_8 = and(_T_7, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_9 = bits(w1v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_10 = mux(_T_9, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_11 = and(_T_10, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_12 = or(_T_8, _T_11) @[dec_gpr_ctl.scala 55:59] + node _T_13 = bits(w2v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_14 = mux(_T_13, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_15 = and(_T_14, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_16 = or(_T_12, _T_15) @[dec_gpr_ctl.scala 55:88] + gpr_in[1] <= _T_16 @[dec_gpr_ctl.scala 55:28] + node _T_17 = eq(io.waddr0, UInt<2>("h02")) @[dec_gpr_ctl.scala 52:52] + node _T_18 = and(io.wen0, _T_17) @[dec_gpr_ctl.scala 52:40] + w0v[2] <= _T_18 @[dec_gpr_ctl.scala 52:28] + node _T_19 = eq(io.waddr1, UInt<2>("h02")) @[dec_gpr_ctl.scala 53:52] + node _T_20 = and(io.wen1, _T_19) @[dec_gpr_ctl.scala 53:40] + w1v[2] <= _T_20 @[dec_gpr_ctl.scala 53:28] + node _T_21 = eq(io.waddr2, UInt<2>("h02")) @[dec_gpr_ctl.scala 54:52] + node _T_22 = and(io.wen2, _T_21) @[dec_gpr_ctl.scala 54:40] + w2v[2] <= _T_22 @[dec_gpr_ctl.scala 54:28] + node _T_23 = bits(w0v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_24 = mux(_T_23, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_25 = and(_T_24, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_26 = bits(w1v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_27 = mux(_T_26, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_28 = and(_T_27, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_29 = or(_T_25, _T_28) @[dec_gpr_ctl.scala 55:59] + node _T_30 = bits(w2v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_31 = mux(_T_30, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_32 = and(_T_31, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_33 = or(_T_29, _T_32) @[dec_gpr_ctl.scala 55:88] + gpr_in[2] <= _T_33 @[dec_gpr_ctl.scala 55:28] + node _T_34 = eq(io.waddr0, UInt<2>("h03")) @[dec_gpr_ctl.scala 52:52] + node _T_35 = and(io.wen0, _T_34) @[dec_gpr_ctl.scala 52:40] + w0v[3] <= _T_35 @[dec_gpr_ctl.scala 52:28] + node _T_36 = eq(io.waddr1, UInt<2>("h03")) @[dec_gpr_ctl.scala 53:52] + node _T_37 = and(io.wen1, _T_36) @[dec_gpr_ctl.scala 53:40] + w1v[3] <= _T_37 @[dec_gpr_ctl.scala 53:28] + node _T_38 = eq(io.waddr2, UInt<2>("h03")) @[dec_gpr_ctl.scala 54:52] + node _T_39 = and(io.wen2, _T_38) @[dec_gpr_ctl.scala 54:40] + w2v[3] <= _T_39 @[dec_gpr_ctl.scala 54:28] + node _T_40 = bits(w0v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_41 = mux(_T_40, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_42 = and(_T_41, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_43 = bits(w1v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_44 = mux(_T_43, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_45 = and(_T_44, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_46 = or(_T_42, _T_45) @[dec_gpr_ctl.scala 55:59] + node _T_47 = bits(w2v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_48 = mux(_T_47, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_49 = and(_T_48, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_50 = or(_T_46, _T_49) @[dec_gpr_ctl.scala 55:88] + gpr_in[3] <= _T_50 @[dec_gpr_ctl.scala 55:28] + node _T_51 = eq(io.waddr0, UInt<3>("h04")) @[dec_gpr_ctl.scala 52:52] + node _T_52 = and(io.wen0, _T_51) @[dec_gpr_ctl.scala 52:40] + w0v[4] <= _T_52 @[dec_gpr_ctl.scala 52:28] + node _T_53 = eq(io.waddr1, UInt<3>("h04")) @[dec_gpr_ctl.scala 53:52] + node _T_54 = and(io.wen1, _T_53) @[dec_gpr_ctl.scala 53:40] + w1v[4] <= _T_54 @[dec_gpr_ctl.scala 53:28] + node _T_55 = eq(io.waddr2, UInt<3>("h04")) @[dec_gpr_ctl.scala 54:52] + node _T_56 = and(io.wen2, _T_55) @[dec_gpr_ctl.scala 54:40] + w2v[4] <= _T_56 @[dec_gpr_ctl.scala 54:28] + node _T_57 = bits(w0v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_58 = mux(_T_57, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_59 = and(_T_58, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_60 = bits(w1v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_61 = mux(_T_60, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_62 = and(_T_61, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_63 = or(_T_59, _T_62) @[dec_gpr_ctl.scala 55:59] + node _T_64 = bits(w2v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_65 = mux(_T_64, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_66 = and(_T_65, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_67 = or(_T_63, _T_66) @[dec_gpr_ctl.scala 55:88] + gpr_in[4] <= _T_67 @[dec_gpr_ctl.scala 55:28] + node _T_68 = eq(io.waddr0, UInt<3>("h05")) @[dec_gpr_ctl.scala 52:52] + node _T_69 = and(io.wen0, _T_68) @[dec_gpr_ctl.scala 52:40] + w0v[5] <= _T_69 @[dec_gpr_ctl.scala 52:28] + node _T_70 = eq(io.waddr1, UInt<3>("h05")) @[dec_gpr_ctl.scala 53:52] + node _T_71 = and(io.wen1, _T_70) @[dec_gpr_ctl.scala 53:40] + w1v[5] <= _T_71 @[dec_gpr_ctl.scala 53:28] + node _T_72 = eq(io.waddr2, UInt<3>("h05")) @[dec_gpr_ctl.scala 54:52] + node _T_73 = and(io.wen2, _T_72) @[dec_gpr_ctl.scala 54:40] + w2v[5] <= _T_73 @[dec_gpr_ctl.scala 54:28] + node _T_74 = bits(w0v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_75 = mux(_T_74, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_76 = and(_T_75, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_77 = bits(w1v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_78 = mux(_T_77, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_79 = and(_T_78, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_80 = or(_T_76, _T_79) @[dec_gpr_ctl.scala 55:59] + node _T_81 = bits(w2v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_82 = mux(_T_81, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_83 = and(_T_82, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_84 = or(_T_80, _T_83) @[dec_gpr_ctl.scala 55:88] + gpr_in[5] <= _T_84 @[dec_gpr_ctl.scala 55:28] + node _T_85 = eq(io.waddr0, UInt<3>("h06")) @[dec_gpr_ctl.scala 52:52] + node _T_86 = and(io.wen0, _T_85) @[dec_gpr_ctl.scala 52:40] + w0v[6] <= _T_86 @[dec_gpr_ctl.scala 52:28] + node _T_87 = eq(io.waddr1, UInt<3>("h06")) @[dec_gpr_ctl.scala 53:52] + node _T_88 = and(io.wen1, _T_87) @[dec_gpr_ctl.scala 53:40] + w1v[6] <= _T_88 @[dec_gpr_ctl.scala 53:28] + node _T_89 = eq(io.waddr2, UInt<3>("h06")) @[dec_gpr_ctl.scala 54:52] + node _T_90 = and(io.wen2, _T_89) @[dec_gpr_ctl.scala 54:40] + w2v[6] <= _T_90 @[dec_gpr_ctl.scala 54:28] + node _T_91 = bits(w0v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_92 = mux(_T_91, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_93 = and(_T_92, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_94 = bits(w1v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_95 = mux(_T_94, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_96 = and(_T_95, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_97 = or(_T_93, _T_96) @[dec_gpr_ctl.scala 55:59] + node _T_98 = bits(w2v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_99 = mux(_T_98, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_100 = and(_T_99, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_101 = or(_T_97, _T_100) @[dec_gpr_ctl.scala 55:88] + gpr_in[6] <= _T_101 @[dec_gpr_ctl.scala 55:28] + node _T_102 = eq(io.waddr0, UInt<3>("h07")) @[dec_gpr_ctl.scala 52:52] + node _T_103 = and(io.wen0, _T_102) @[dec_gpr_ctl.scala 52:40] + w0v[7] <= _T_103 @[dec_gpr_ctl.scala 52:28] + node _T_104 = eq(io.waddr1, UInt<3>("h07")) @[dec_gpr_ctl.scala 53:52] + node _T_105 = and(io.wen1, _T_104) @[dec_gpr_ctl.scala 53:40] + w1v[7] <= _T_105 @[dec_gpr_ctl.scala 53:28] + node _T_106 = eq(io.waddr2, UInt<3>("h07")) @[dec_gpr_ctl.scala 54:52] + node _T_107 = and(io.wen2, _T_106) @[dec_gpr_ctl.scala 54:40] + w2v[7] <= _T_107 @[dec_gpr_ctl.scala 54:28] + node _T_108 = bits(w0v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_109 = mux(_T_108, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_110 = and(_T_109, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_111 = bits(w1v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_112 = mux(_T_111, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_113 = and(_T_112, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_114 = or(_T_110, _T_113) @[dec_gpr_ctl.scala 55:59] + node _T_115 = bits(w2v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_116 = mux(_T_115, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_117 = and(_T_116, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_118 = or(_T_114, _T_117) @[dec_gpr_ctl.scala 55:88] + gpr_in[7] <= _T_118 @[dec_gpr_ctl.scala 55:28] + node _T_119 = eq(io.waddr0, UInt<4>("h08")) @[dec_gpr_ctl.scala 52:52] + node _T_120 = and(io.wen0, _T_119) @[dec_gpr_ctl.scala 52:40] + w0v[8] <= _T_120 @[dec_gpr_ctl.scala 52:28] + node _T_121 = eq(io.waddr1, UInt<4>("h08")) @[dec_gpr_ctl.scala 53:52] + node _T_122 = and(io.wen1, _T_121) @[dec_gpr_ctl.scala 53:40] + w1v[8] <= _T_122 @[dec_gpr_ctl.scala 53:28] + node _T_123 = eq(io.waddr2, UInt<4>("h08")) @[dec_gpr_ctl.scala 54:52] + node _T_124 = and(io.wen2, _T_123) @[dec_gpr_ctl.scala 54:40] + w2v[8] <= _T_124 @[dec_gpr_ctl.scala 54:28] + node _T_125 = bits(w0v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_126 = mux(_T_125, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_127 = and(_T_126, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_128 = bits(w1v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_129 = mux(_T_128, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_130 = and(_T_129, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_131 = or(_T_127, _T_130) @[dec_gpr_ctl.scala 55:59] + node _T_132 = bits(w2v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_133 = mux(_T_132, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_134 = and(_T_133, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_135 = or(_T_131, _T_134) @[dec_gpr_ctl.scala 55:88] + gpr_in[8] <= _T_135 @[dec_gpr_ctl.scala 55:28] + node _T_136 = eq(io.waddr0, UInt<4>("h09")) @[dec_gpr_ctl.scala 52:52] + node _T_137 = and(io.wen0, _T_136) @[dec_gpr_ctl.scala 52:40] + w0v[9] <= _T_137 @[dec_gpr_ctl.scala 52:28] + node _T_138 = eq(io.waddr1, UInt<4>("h09")) @[dec_gpr_ctl.scala 53:52] + node _T_139 = and(io.wen1, _T_138) @[dec_gpr_ctl.scala 53:40] + w1v[9] <= _T_139 @[dec_gpr_ctl.scala 53:28] + node _T_140 = eq(io.waddr2, UInt<4>("h09")) @[dec_gpr_ctl.scala 54:52] + node _T_141 = and(io.wen2, _T_140) @[dec_gpr_ctl.scala 54:40] + w2v[9] <= _T_141 @[dec_gpr_ctl.scala 54:28] + node _T_142 = bits(w0v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_143 = mux(_T_142, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_144 = and(_T_143, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_145 = bits(w1v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_146 = mux(_T_145, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_147 = and(_T_146, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_148 = or(_T_144, _T_147) @[dec_gpr_ctl.scala 55:59] + node _T_149 = bits(w2v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_150 = mux(_T_149, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_151 = and(_T_150, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_152 = or(_T_148, _T_151) @[dec_gpr_ctl.scala 55:88] + gpr_in[9] <= _T_152 @[dec_gpr_ctl.scala 55:28] + node _T_153 = eq(io.waddr0, UInt<4>("h0a")) @[dec_gpr_ctl.scala 52:52] + node _T_154 = and(io.wen0, _T_153) @[dec_gpr_ctl.scala 52:40] + w0v[10] <= _T_154 @[dec_gpr_ctl.scala 52:28] + node _T_155 = eq(io.waddr1, UInt<4>("h0a")) @[dec_gpr_ctl.scala 53:52] + node _T_156 = and(io.wen1, _T_155) @[dec_gpr_ctl.scala 53:40] + w1v[10] <= _T_156 @[dec_gpr_ctl.scala 53:28] + node _T_157 = eq(io.waddr2, UInt<4>("h0a")) @[dec_gpr_ctl.scala 54:52] + node _T_158 = and(io.wen2, _T_157) @[dec_gpr_ctl.scala 54:40] + w2v[10] <= _T_158 @[dec_gpr_ctl.scala 54:28] + node _T_159 = bits(w0v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_160 = mux(_T_159, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_161 = and(_T_160, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_162 = bits(w1v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_163 = mux(_T_162, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_164 = and(_T_163, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_165 = or(_T_161, _T_164) @[dec_gpr_ctl.scala 55:59] + node _T_166 = bits(w2v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_167 = mux(_T_166, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_168 = and(_T_167, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_169 = or(_T_165, _T_168) @[dec_gpr_ctl.scala 55:88] + gpr_in[10] <= _T_169 @[dec_gpr_ctl.scala 55:28] + node _T_170 = eq(io.waddr0, UInt<4>("h0b")) @[dec_gpr_ctl.scala 52:52] + node _T_171 = and(io.wen0, _T_170) @[dec_gpr_ctl.scala 52:40] + w0v[11] <= _T_171 @[dec_gpr_ctl.scala 52:28] + node _T_172 = eq(io.waddr1, UInt<4>("h0b")) @[dec_gpr_ctl.scala 53:52] + node _T_173 = and(io.wen1, _T_172) @[dec_gpr_ctl.scala 53:40] + w1v[11] <= _T_173 @[dec_gpr_ctl.scala 53:28] + node _T_174 = eq(io.waddr2, UInt<4>("h0b")) @[dec_gpr_ctl.scala 54:52] + node _T_175 = and(io.wen2, _T_174) @[dec_gpr_ctl.scala 54:40] + w2v[11] <= _T_175 @[dec_gpr_ctl.scala 54:28] + node _T_176 = bits(w0v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_177 = mux(_T_176, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_178 = and(_T_177, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_179 = bits(w1v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_180 = mux(_T_179, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_181 = and(_T_180, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_182 = or(_T_178, _T_181) @[dec_gpr_ctl.scala 55:59] + node _T_183 = bits(w2v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_184 = mux(_T_183, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_185 = and(_T_184, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_186 = or(_T_182, _T_185) @[dec_gpr_ctl.scala 55:88] + gpr_in[11] <= _T_186 @[dec_gpr_ctl.scala 55:28] + node _T_187 = eq(io.waddr0, UInt<4>("h0c")) @[dec_gpr_ctl.scala 52:52] + node _T_188 = and(io.wen0, _T_187) @[dec_gpr_ctl.scala 52:40] + w0v[12] <= _T_188 @[dec_gpr_ctl.scala 52:28] + node _T_189 = eq(io.waddr1, UInt<4>("h0c")) @[dec_gpr_ctl.scala 53:52] + node _T_190 = and(io.wen1, _T_189) @[dec_gpr_ctl.scala 53:40] + w1v[12] <= _T_190 @[dec_gpr_ctl.scala 53:28] + node _T_191 = eq(io.waddr2, UInt<4>("h0c")) @[dec_gpr_ctl.scala 54:52] + node _T_192 = and(io.wen2, _T_191) @[dec_gpr_ctl.scala 54:40] + w2v[12] <= _T_192 @[dec_gpr_ctl.scala 54:28] + node _T_193 = bits(w0v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_194 = mux(_T_193, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_195 = and(_T_194, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_196 = bits(w1v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_197 = mux(_T_196, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_198 = and(_T_197, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_199 = or(_T_195, _T_198) @[dec_gpr_ctl.scala 55:59] + node _T_200 = bits(w2v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_201 = mux(_T_200, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_202 = and(_T_201, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_203 = or(_T_199, _T_202) @[dec_gpr_ctl.scala 55:88] + gpr_in[12] <= _T_203 @[dec_gpr_ctl.scala 55:28] + node _T_204 = eq(io.waddr0, UInt<4>("h0d")) @[dec_gpr_ctl.scala 52:52] + node _T_205 = and(io.wen0, _T_204) @[dec_gpr_ctl.scala 52:40] + w0v[13] <= _T_205 @[dec_gpr_ctl.scala 52:28] + node _T_206 = eq(io.waddr1, UInt<4>("h0d")) @[dec_gpr_ctl.scala 53:52] + node _T_207 = and(io.wen1, _T_206) @[dec_gpr_ctl.scala 53:40] + w1v[13] <= _T_207 @[dec_gpr_ctl.scala 53:28] + node _T_208 = eq(io.waddr2, UInt<4>("h0d")) @[dec_gpr_ctl.scala 54:52] + node _T_209 = and(io.wen2, _T_208) @[dec_gpr_ctl.scala 54:40] + w2v[13] <= _T_209 @[dec_gpr_ctl.scala 54:28] + node _T_210 = bits(w0v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_211 = mux(_T_210, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_212 = and(_T_211, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_213 = bits(w1v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_214 = mux(_T_213, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_215 = and(_T_214, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_216 = or(_T_212, _T_215) @[dec_gpr_ctl.scala 55:59] + node _T_217 = bits(w2v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_218 = mux(_T_217, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_219 = and(_T_218, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_220 = or(_T_216, _T_219) @[dec_gpr_ctl.scala 55:88] + gpr_in[13] <= _T_220 @[dec_gpr_ctl.scala 55:28] + node _T_221 = eq(io.waddr0, UInt<4>("h0e")) @[dec_gpr_ctl.scala 52:52] + node _T_222 = and(io.wen0, _T_221) @[dec_gpr_ctl.scala 52:40] + w0v[14] <= _T_222 @[dec_gpr_ctl.scala 52:28] + node _T_223 = eq(io.waddr1, UInt<4>("h0e")) @[dec_gpr_ctl.scala 53:52] + node _T_224 = and(io.wen1, _T_223) @[dec_gpr_ctl.scala 53:40] + w1v[14] <= _T_224 @[dec_gpr_ctl.scala 53:28] + node _T_225 = eq(io.waddr2, UInt<4>("h0e")) @[dec_gpr_ctl.scala 54:52] + node _T_226 = and(io.wen2, _T_225) @[dec_gpr_ctl.scala 54:40] + w2v[14] <= _T_226 @[dec_gpr_ctl.scala 54:28] + node _T_227 = bits(w0v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_228 = mux(_T_227, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_229 = and(_T_228, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_230 = bits(w1v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_231 = mux(_T_230, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_232 = and(_T_231, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_233 = or(_T_229, _T_232) @[dec_gpr_ctl.scala 55:59] + node _T_234 = bits(w2v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_236 = and(_T_235, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_237 = or(_T_233, _T_236) @[dec_gpr_ctl.scala 55:88] + gpr_in[14] <= _T_237 @[dec_gpr_ctl.scala 55:28] + node _T_238 = eq(io.waddr0, UInt<4>("h0f")) @[dec_gpr_ctl.scala 52:52] + node _T_239 = and(io.wen0, _T_238) @[dec_gpr_ctl.scala 52:40] + w0v[15] <= _T_239 @[dec_gpr_ctl.scala 52:28] + node _T_240 = eq(io.waddr1, UInt<4>("h0f")) @[dec_gpr_ctl.scala 53:52] + node _T_241 = and(io.wen1, _T_240) @[dec_gpr_ctl.scala 53:40] + w1v[15] <= _T_241 @[dec_gpr_ctl.scala 53:28] + node _T_242 = eq(io.waddr2, UInt<4>("h0f")) @[dec_gpr_ctl.scala 54:52] + node _T_243 = and(io.wen2, _T_242) @[dec_gpr_ctl.scala 54:40] + w2v[15] <= _T_243 @[dec_gpr_ctl.scala 54:28] + node _T_244 = bits(w0v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_245 = mux(_T_244, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_246 = and(_T_245, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_247 = bits(w1v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_248 = mux(_T_247, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_249 = and(_T_248, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_250 = or(_T_246, _T_249) @[dec_gpr_ctl.scala 55:59] + node _T_251 = bits(w2v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_252 = mux(_T_251, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_253 = and(_T_252, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_254 = or(_T_250, _T_253) @[dec_gpr_ctl.scala 55:88] + gpr_in[15] <= _T_254 @[dec_gpr_ctl.scala 55:28] + node _T_255 = eq(io.waddr0, UInt<5>("h010")) @[dec_gpr_ctl.scala 52:52] + node _T_256 = and(io.wen0, _T_255) @[dec_gpr_ctl.scala 52:40] + w0v[16] <= _T_256 @[dec_gpr_ctl.scala 52:28] + node _T_257 = eq(io.waddr1, UInt<5>("h010")) @[dec_gpr_ctl.scala 53:52] + node _T_258 = and(io.wen1, _T_257) @[dec_gpr_ctl.scala 53:40] + w1v[16] <= _T_258 @[dec_gpr_ctl.scala 53:28] + node _T_259 = eq(io.waddr2, UInt<5>("h010")) @[dec_gpr_ctl.scala 54:52] + node _T_260 = and(io.wen2, _T_259) @[dec_gpr_ctl.scala 54:40] + w2v[16] <= _T_260 @[dec_gpr_ctl.scala 54:28] + node _T_261 = bits(w0v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_262 = mux(_T_261, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_263 = and(_T_262, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_264 = bits(w1v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_265 = mux(_T_264, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_266 = and(_T_265, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_267 = or(_T_263, _T_266) @[dec_gpr_ctl.scala 55:59] + node _T_268 = bits(w2v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_269 = mux(_T_268, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_270 = and(_T_269, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_271 = or(_T_267, _T_270) @[dec_gpr_ctl.scala 55:88] + gpr_in[16] <= _T_271 @[dec_gpr_ctl.scala 55:28] + node _T_272 = eq(io.waddr0, UInt<5>("h011")) @[dec_gpr_ctl.scala 52:52] + node _T_273 = and(io.wen0, _T_272) @[dec_gpr_ctl.scala 52:40] + w0v[17] <= _T_273 @[dec_gpr_ctl.scala 52:28] + node _T_274 = eq(io.waddr1, UInt<5>("h011")) @[dec_gpr_ctl.scala 53:52] + node _T_275 = and(io.wen1, _T_274) @[dec_gpr_ctl.scala 53:40] + w1v[17] <= _T_275 @[dec_gpr_ctl.scala 53:28] + node _T_276 = eq(io.waddr2, UInt<5>("h011")) @[dec_gpr_ctl.scala 54:52] + node _T_277 = and(io.wen2, _T_276) @[dec_gpr_ctl.scala 54:40] + w2v[17] <= _T_277 @[dec_gpr_ctl.scala 54:28] + node _T_278 = bits(w0v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_279 = mux(_T_278, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_280 = and(_T_279, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_281 = bits(w1v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_282 = mux(_T_281, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_283 = and(_T_282, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_284 = or(_T_280, _T_283) @[dec_gpr_ctl.scala 55:59] + node _T_285 = bits(w2v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_286 = mux(_T_285, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_287 = and(_T_286, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_288 = or(_T_284, _T_287) @[dec_gpr_ctl.scala 55:88] + gpr_in[17] <= _T_288 @[dec_gpr_ctl.scala 55:28] + node _T_289 = eq(io.waddr0, UInt<5>("h012")) @[dec_gpr_ctl.scala 52:52] + node _T_290 = and(io.wen0, _T_289) @[dec_gpr_ctl.scala 52:40] + w0v[18] <= _T_290 @[dec_gpr_ctl.scala 52:28] + node _T_291 = eq(io.waddr1, UInt<5>("h012")) @[dec_gpr_ctl.scala 53:52] + node _T_292 = and(io.wen1, _T_291) @[dec_gpr_ctl.scala 53:40] + w1v[18] <= _T_292 @[dec_gpr_ctl.scala 53:28] + node _T_293 = eq(io.waddr2, UInt<5>("h012")) @[dec_gpr_ctl.scala 54:52] + node _T_294 = and(io.wen2, _T_293) @[dec_gpr_ctl.scala 54:40] + w2v[18] <= _T_294 @[dec_gpr_ctl.scala 54:28] + node _T_295 = bits(w0v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_296 = mux(_T_295, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_297 = and(_T_296, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_298 = bits(w1v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_299 = mux(_T_298, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_300 = and(_T_299, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_301 = or(_T_297, _T_300) @[dec_gpr_ctl.scala 55:59] + node _T_302 = bits(w2v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_303 = mux(_T_302, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_304 = and(_T_303, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_305 = or(_T_301, _T_304) @[dec_gpr_ctl.scala 55:88] + gpr_in[18] <= _T_305 @[dec_gpr_ctl.scala 55:28] + node _T_306 = eq(io.waddr0, UInt<5>("h013")) @[dec_gpr_ctl.scala 52:52] + node _T_307 = and(io.wen0, _T_306) @[dec_gpr_ctl.scala 52:40] + w0v[19] <= _T_307 @[dec_gpr_ctl.scala 52:28] + node _T_308 = eq(io.waddr1, UInt<5>("h013")) @[dec_gpr_ctl.scala 53:52] + node _T_309 = and(io.wen1, _T_308) @[dec_gpr_ctl.scala 53:40] + w1v[19] <= _T_309 @[dec_gpr_ctl.scala 53:28] + node _T_310 = eq(io.waddr2, UInt<5>("h013")) @[dec_gpr_ctl.scala 54:52] + node _T_311 = and(io.wen2, _T_310) @[dec_gpr_ctl.scala 54:40] + w2v[19] <= _T_311 @[dec_gpr_ctl.scala 54:28] + node _T_312 = bits(w0v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_313 = mux(_T_312, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_314 = and(_T_313, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_315 = bits(w1v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_316 = mux(_T_315, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_317 = and(_T_316, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_318 = or(_T_314, _T_317) @[dec_gpr_ctl.scala 55:59] + node _T_319 = bits(w2v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_320 = mux(_T_319, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_321 = and(_T_320, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_322 = or(_T_318, _T_321) @[dec_gpr_ctl.scala 55:88] + gpr_in[19] <= _T_322 @[dec_gpr_ctl.scala 55:28] + node _T_323 = eq(io.waddr0, UInt<5>("h014")) @[dec_gpr_ctl.scala 52:52] + node _T_324 = and(io.wen0, _T_323) @[dec_gpr_ctl.scala 52:40] + w0v[20] <= _T_324 @[dec_gpr_ctl.scala 52:28] + node _T_325 = eq(io.waddr1, UInt<5>("h014")) @[dec_gpr_ctl.scala 53:52] + node _T_326 = and(io.wen1, _T_325) @[dec_gpr_ctl.scala 53:40] + w1v[20] <= _T_326 @[dec_gpr_ctl.scala 53:28] + node _T_327 = eq(io.waddr2, UInt<5>("h014")) @[dec_gpr_ctl.scala 54:52] + node _T_328 = and(io.wen2, _T_327) @[dec_gpr_ctl.scala 54:40] + w2v[20] <= _T_328 @[dec_gpr_ctl.scala 54:28] + node _T_329 = bits(w0v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_330 = mux(_T_329, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_331 = and(_T_330, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_332 = bits(w1v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_333 = mux(_T_332, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_334 = and(_T_333, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_335 = or(_T_331, _T_334) @[dec_gpr_ctl.scala 55:59] + node _T_336 = bits(w2v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_337 = mux(_T_336, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_338 = and(_T_337, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_339 = or(_T_335, _T_338) @[dec_gpr_ctl.scala 55:88] + gpr_in[20] <= _T_339 @[dec_gpr_ctl.scala 55:28] + node _T_340 = eq(io.waddr0, UInt<5>("h015")) @[dec_gpr_ctl.scala 52:52] + node _T_341 = and(io.wen0, _T_340) @[dec_gpr_ctl.scala 52:40] + w0v[21] <= _T_341 @[dec_gpr_ctl.scala 52:28] + node _T_342 = eq(io.waddr1, UInt<5>("h015")) @[dec_gpr_ctl.scala 53:52] + node _T_343 = and(io.wen1, _T_342) @[dec_gpr_ctl.scala 53:40] + w1v[21] <= _T_343 @[dec_gpr_ctl.scala 53:28] + node _T_344 = eq(io.waddr2, UInt<5>("h015")) @[dec_gpr_ctl.scala 54:52] + node _T_345 = and(io.wen2, _T_344) @[dec_gpr_ctl.scala 54:40] + w2v[21] <= _T_345 @[dec_gpr_ctl.scala 54:28] + node _T_346 = bits(w0v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_347 = mux(_T_346, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_348 = and(_T_347, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_349 = bits(w1v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_350 = mux(_T_349, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_351 = and(_T_350, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_352 = or(_T_348, _T_351) @[dec_gpr_ctl.scala 55:59] + node _T_353 = bits(w2v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_354 = mux(_T_353, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_355 = and(_T_354, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_356 = or(_T_352, _T_355) @[dec_gpr_ctl.scala 55:88] + gpr_in[21] <= _T_356 @[dec_gpr_ctl.scala 55:28] + node _T_357 = eq(io.waddr0, UInt<5>("h016")) @[dec_gpr_ctl.scala 52:52] + node _T_358 = and(io.wen0, _T_357) @[dec_gpr_ctl.scala 52:40] + w0v[22] <= _T_358 @[dec_gpr_ctl.scala 52:28] + node _T_359 = eq(io.waddr1, UInt<5>("h016")) @[dec_gpr_ctl.scala 53:52] + node _T_360 = and(io.wen1, _T_359) @[dec_gpr_ctl.scala 53:40] + w1v[22] <= _T_360 @[dec_gpr_ctl.scala 53:28] + node _T_361 = eq(io.waddr2, UInt<5>("h016")) @[dec_gpr_ctl.scala 54:52] + node _T_362 = and(io.wen2, _T_361) @[dec_gpr_ctl.scala 54:40] + w2v[22] <= _T_362 @[dec_gpr_ctl.scala 54:28] + node _T_363 = bits(w0v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_364 = mux(_T_363, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_365 = and(_T_364, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_366 = bits(w1v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_367 = mux(_T_366, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_368 = and(_T_367, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_369 = or(_T_365, _T_368) @[dec_gpr_ctl.scala 55:59] + node _T_370 = bits(w2v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_371 = mux(_T_370, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_372 = and(_T_371, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_373 = or(_T_369, _T_372) @[dec_gpr_ctl.scala 55:88] + gpr_in[22] <= _T_373 @[dec_gpr_ctl.scala 55:28] + node _T_374 = eq(io.waddr0, UInt<5>("h017")) @[dec_gpr_ctl.scala 52:52] + node _T_375 = and(io.wen0, _T_374) @[dec_gpr_ctl.scala 52:40] + w0v[23] <= _T_375 @[dec_gpr_ctl.scala 52:28] + node _T_376 = eq(io.waddr1, UInt<5>("h017")) @[dec_gpr_ctl.scala 53:52] + node _T_377 = and(io.wen1, _T_376) @[dec_gpr_ctl.scala 53:40] + w1v[23] <= _T_377 @[dec_gpr_ctl.scala 53:28] + node _T_378 = eq(io.waddr2, UInt<5>("h017")) @[dec_gpr_ctl.scala 54:52] + node _T_379 = and(io.wen2, _T_378) @[dec_gpr_ctl.scala 54:40] + w2v[23] <= _T_379 @[dec_gpr_ctl.scala 54:28] + node _T_380 = bits(w0v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_381 = mux(_T_380, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_382 = and(_T_381, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_383 = bits(w1v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_384 = mux(_T_383, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_385 = and(_T_384, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_386 = or(_T_382, _T_385) @[dec_gpr_ctl.scala 55:59] + node _T_387 = bits(w2v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_388 = mux(_T_387, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_389 = and(_T_388, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_390 = or(_T_386, _T_389) @[dec_gpr_ctl.scala 55:88] + gpr_in[23] <= _T_390 @[dec_gpr_ctl.scala 55:28] + node _T_391 = eq(io.waddr0, UInt<5>("h018")) @[dec_gpr_ctl.scala 52:52] + node _T_392 = and(io.wen0, _T_391) @[dec_gpr_ctl.scala 52:40] + w0v[24] <= _T_392 @[dec_gpr_ctl.scala 52:28] + node _T_393 = eq(io.waddr1, UInt<5>("h018")) @[dec_gpr_ctl.scala 53:52] + node _T_394 = and(io.wen1, _T_393) @[dec_gpr_ctl.scala 53:40] + w1v[24] <= _T_394 @[dec_gpr_ctl.scala 53:28] + node _T_395 = eq(io.waddr2, UInt<5>("h018")) @[dec_gpr_ctl.scala 54:52] + node _T_396 = and(io.wen2, _T_395) @[dec_gpr_ctl.scala 54:40] + w2v[24] <= _T_396 @[dec_gpr_ctl.scala 54:28] + node _T_397 = bits(w0v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_398 = mux(_T_397, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_399 = and(_T_398, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_400 = bits(w1v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_401 = mux(_T_400, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_402 = and(_T_401, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_403 = or(_T_399, _T_402) @[dec_gpr_ctl.scala 55:59] + node _T_404 = bits(w2v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_405 = mux(_T_404, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_406 = and(_T_405, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_407 = or(_T_403, _T_406) @[dec_gpr_ctl.scala 55:88] + gpr_in[24] <= _T_407 @[dec_gpr_ctl.scala 55:28] + node _T_408 = eq(io.waddr0, UInt<5>("h019")) @[dec_gpr_ctl.scala 52:52] + node _T_409 = and(io.wen0, _T_408) @[dec_gpr_ctl.scala 52:40] + w0v[25] <= _T_409 @[dec_gpr_ctl.scala 52:28] + node _T_410 = eq(io.waddr1, UInt<5>("h019")) @[dec_gpr_ctl.scala 53:52] + node _T_411 = and(io.wen1, _T_410) @[dec_gpr_ctl.scala 53:40] + w1v[25] <= _T_411 @[dec_gpr_ctl.scala 53:28] + node _T_412 = eq(io.waddr2, UInt<5>("h019")) @[dec_gpr_ctl.scala 54:52] + node _T_413 = and(io.wen2, _T_412) @[dec_gpr_ctl.scala 54:40] + w2v[25] <= _T_413 @[dec_gpr_ctl.scala 54:28] + node _T_414 = bits(w0v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_415 = mux(_T_414, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_416 = and(_T_415, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_417 = bits(w1v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_418 = mux(_T_417, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_419 = and(_T_418, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_420 = or(_T_416, _T_419) @[dec_gpr_ctl.scala 55:59] + node _T_421 = bits(w2v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_422 = mux(_T_421, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_423 = and(_T_422, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_424 = or(_T_420, _T_423) @[dec_gpr_ctl.scala 55:88] + gpr_in[25] <= _T_424 @[dec_gpr_ctl.scala 55:28] + node _T_425 = eq(io.waddr0, UInt<5>("h01a")) @[dec_gpr_ctl.scala 52:52] + node _T_426 = and(io.wen0, _T_425) @[dec_gpr_ctl.scala 52:40] + w0v[26] <= _T_426 @[dec_gpr_ctl.scala 52:28] + node _T_427 = eq(io.waddr1, UInt<5>("h01a")) @[dec_gpr_ctl.scala 53:52] + node _T_428 = and(io.wen1, _T_427) @[dec_gpr_ctl.scala 53:40] + w1v[26] <= _T_428 @[dec_gpr_ctl.scala 53:28] + node _T_429 = eq(io.waddr2, UInt<5>("h01a")) @[dec_gpr_ctl.scala 54:52] + node _T_430 = and(io.wen2, _T_429) @[dec_gpr_ctl.scala 54:40] + w2v[26] <= _T_430 @[dec_gpr_ctl.scala 54:28] + node _T_431 = bits(w0v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_432 = mux(_T_431, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_433 = and(_T_432, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_434 = bits(w1v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_435 = mux(_T_434, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_436 = and(_T_435, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_437 = or(_T_433, _T_436) @[dec_gpr_ctl.scala 55:59] + node _T_438 = bits(w2v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_439 = mux(_T_438, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_440 = and(_T_439, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_441 = or(_T_437, _T_440) @[dec_gpr_ctl.scala 55:88] + gpr_in[26] <= _T_441 @[dec_gpr_ctl.scala 55:28] + node _T_442 = eq(io.waddr0, UInt<5>("h01b")) @[dec_gpr_ctl.scala 52:52] + node _T_443 = and(io.wen0, _T_442) @[dec_gpr_ctl.scala 52:40] + w0v[27] <= _T_443 @[dec_gpr_ctl.scala 52:28] + node _T_444 = eq(io.waddr1, UInt<5>("h01b")) @[dec_gpr_ctl.scala 53:52] + node _T_445 = and(io.wen1, _T_444) @[dec_gpr_ctl.scala 53:40] + w1v[27] <= _T_445 @[dec_gpr_ctl.scala 53:28] + node _T_446 = eq(io.waddr2, UInt<5>("h01b")) @[dec_gpr_ctl.scala 54:52] + node _T_447 = and(io.wen2, _T_446) @[dec_gpr_ctl.scala 54:40] + w2v[27] <= _T_447 @[dec_gpr_ctl.scala 54:28] + node _T_448 = bits(w0v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_449 = mux(_T_448, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_450 = and(_T_449, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_451 = bits(w1v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_452 = mux(_T_451, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_453 = and(_T_452, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_454 = or(_T_450, _T_453) @[dec_gpr_ctl.scala 55:59] + node _T_455 = bits(w2v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_456 = mux(_T_455, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_457 = and(_T_456, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_458 = or(_T_454, _T_457) @[dec_gpr_ctl.scala 55:88] + gpr_in[27] <= _T_458 @[dec_gpr_ctl.scala 55:28] + node _T_459 = eq(io.waddr0, UInt<5>("h01c")) @[dec_gpr_ctl.scala 52:52] + node _T_460 = and(io.wen0, _T_459) @[dec_gpr_ctl.scala 52:40] + w0v[28] <= _T_460 @[dec_gpr_ctl.scala 52:28] + node _T_461 = eq(io.waddr1, UInt<5>("h01c")) @[dec_gpr_ctl.scala 53:52] + node _T_462 = and(io.wen1, _T_461) @[dec_gpr_ctl.scala 53:40] + w1v[28] <= _T_462 @[dec_gpr_ctl.scala 53:28] + node _T_463 = eq(io.waddr2, UInt<5>("h01c")) @[dec_gpr_ctl.scala 54:52] + node _T_464 = and(io.wen2, _T_463) @[dec_gpr_ctl.scala 54:40] + w2v[28] <= _T_464 @[dec_gpr_ctl.scala 54:28] + node _T_465 = bits(w0v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_466 = mux(_T_465, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_467 = and(_T_466, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_468 = bits(w1v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_469 = mux(_T_468, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_470 = and(_T_469, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_471 = or(_T_467, _T_470) @[dec_gpr_ctl.scala 55:59] + node _T_472 = bits(w2v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_473 = mux(_T_472, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_474 = and(_T_473, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_475 = or(_T_471, _T_474) @[dec_gpr_ctl.scala 55:88] + gpr_in[28] <= _T_475 @[dec_gpr_ctl.scala 55:28] + node _T_476 = eq(io.waddr0, UInt<5>("h01d")) @[dec_gpr_ctl.scala 52:52] + node _T_477 = and(io.wen0, _T_476) @[dec_gpr_ctl.scala 52:40] + w0v[29] <= _T_477 @[dec_gpr_ctl.scala 52:28] + node _T_478 = eq(io.waddr1, UInt<5>("h01d")) @[dec_gpr_ctl.scala 53:52] + node _T_479 = and(io.wen1, _T_478) @[dec_gpr_ctl.scala 53:40] + w1v[29] <= _T_479 @[dec_gpr_ctl.scala 53:28] + node _T_480 = eq(io.waddr2, UInt<5>("h01d")) @[dec_gpr_ctl.scala 54:52] + node _T_481 = and(io.wen2, _T_480) @[dec_gpr_ctl.scala 54:40] + w2v[29] <= _T_481 @[dec_gpr_ctl.scala 54:28] + node _T_482 = bits(w0v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_483 = mux(_T_482, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_484 = and(_T_483, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_485 = bits(w1v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_486 = mux(_T_485, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_487 = and(_T_486, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_488 = or(_T_484, _T_487) @[dec_gpr_ctl.scala 55:59] + node _T_489 = bits(w2v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_490 = mux(_T_489, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_491 = and(_T_490, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_492 = or(_T_488, _T_491) @[dec_gpr_ctl.scala 55:88] + gpr_in[29] <= _T_492 @[dec_gpr_ctl.scala 55:28] + node _T_493 = eq(io.waddr0, UInt<5>("h01e")) @[dec_gpr_ctl.scala 52:52] + node _T_494 = and(io.wen0, _T_493) @[dec_gpr_ctl.scala 52:40] + w0v[30] <= _T_494 @[dec_gpr_ctl.scala 52:28] + node _T_495 = eq(io.waddr1, UInt<5>("h01e")) @[dec_gpr_ctl.scala 53:52] + node _T_496 = and(io.wen1, _T_495) @[dec_gpr_ctl.scala 53:40] + w1v[30] <= _T_496 @[dec_gpr_ctl.scala 53:28] + node _T_497 = eq(io.waddr2, UInt<5>("h01e")) @[dec_gpr_ctl.scala 54:52] + node _T_498 = and(io.wen2, _T_497) @[dec_gpr_ctl.scala 54:40] + w2v[30] <= _T_498 @[dec_gpr_ctl.scala 54:28] + node _T_499 = bits(w0v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_500 = mux(_T_499, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_501 = and(_T_500, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_502 = bits(w1v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_503 = mux(_T_502, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_504 = and(_T_503, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_505 = or(_T_501, _T_504) @[dec_gpr_ctl.scala 55:59] + node _T_506 = bits(w2v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_507 = mux(_T_506, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_508 = and(_T_507, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_509 = or(_T_505, _T_508) @[dec_gpr_ctl.scala 55:88] + gpr_in[30] <= _T_509 @[dec_gpr_ctl.scala 55:28] + node _T_510 = eq(io.waddr0, UInt<5>("h01f")) @[dec_gpr_ctl.scala 52:52] + node _T_511 = and(io.wen0, _T_510) @[dec_gpr_ctl.scala 52:40] + w0v[31] <= _T_511 @[dec_gpr_ctl.scala 52:28] + node _T_512 = eq(io.waddr1, UInt<5>("h01f")) @[dec_gpr_ctl.scala 53:52] + node _T_513 = and(io.wen1, _T_512) @[dec_gpr_ctl.scala 53:40] + w1v[31] <= _T_513 @[dec_gpr_ctl.scala 53:28] + node _T_514 = eq(io.waddr2, UInt<5>("h01f")) @[dec_gpr_ctl.scala 54:52] + node _T_515 = and(io.wen2, _T_514) @[dec_gpr_ctl.scala 54:40] + w2v[31] <= _T_515 @[dec_gpr_ctl.scala 54:28] + node _T_516 = bits(w0v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_517 = mux(_T_516, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_518 = and(_T_517, io.wd0) @[dec_gpr_ctl.scala 55:49] + node _T_519 = bits(w1v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_520 = mux(_T_519, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_521 = and(_T_520, io.wd1) @[dec_gpr_ctl.scala 55:78] + node _T_522 = or(_T_518, _T_521) @[dec_gpr_ctl.scala 55:59] + node _T_523 = bits(w2v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_524 = mux(_T_523, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_525 = and(_T_524, io.wd2) @[dec_gpr_ctl.scala 55:107] + node _T_526 = or(_T_522, _T_525) @[dec_gpr_ctl.scala 55:88] + gpr_in[31] <= _T_526 @[dec_gpr_ctl.scala 55:28] + node _T_527 = cat(w0v[1], w0v[0]) @[Cat.scala 29:58] + node _T_528 = cat(w0v[2], _T_527) @[Cat.scala 29:58] + node _T_529 = cat(w0v[3], _T_528) @[Cat.scala 29:58] + node _T_530 = cat(w0v[4], _T_529) @[Cat.scala 29:58] + node _T_531 = cat(w0v[5], _T_530) @[Cat.scala 29:58] + node _T_532 = cat(w0v[6], _T_531) @[Cat.scala 29:58] + node _T_533 = cat(w0v[7], _T_532) @[Cat.scala 29:58] + node _T_534 = cat(w0v[8], _T_533) @[Cat.scala 29:58] + node _T_535 = cat(w0v[9], _T_534) @[Cat.scala 29:58] + node _T_536 = cat(w0v[10], _T_535) @[Cat.scala 29:58] + node _T_537 = cat(w0v[11], _T_536) @[Cat.scala 29:58] + node _T_538 = cat(w0v[12], _T_537) @[Cat.scala 29:58] + node _T_539 = cat(w0v[13], _T_538) @[Cat.scala 29:58] + node _T_540 = cat(w0v[14], _T_539) @[Cat.scala 29:58] + node _T_541 = cat(w0v[15], _T_540) @[Cat.scala 29:58] + node _T_542 = cat(w0v[16], _T_541) @[Cat.scala 29:58] + node _T_543 = cat(w0v[17], _T_542) @[Cat.scala 29:58] + node _T_544 = cat(w0v[18], _T_543) @[Cat.scala 29:58] + node _T_545 = cat(w0v[19], _T_544) @[Cat.scala 29:58] + node _T_546 = cat(w0v[20], _T_545) @[Cat.scala 29:58] + node _T_547 = cat(w0v[21], _T_546) @[Cat.scala 29:58] + node _T_548 = cat(w0v[22], _T_547) @[Cat.scala 29:58] + node _T_549 = cat(w0v[23], _T_548) @[Cat.scala 29:58] + node _T_550 = cat(w0v[24], _T_549) @[Cat.scala 29:58] + node _T_551 = cat(w0v[25], _T_550) @[Cat.scala 29:58] + node _T_552 = cat(w0v[26], _T_551) @[Cat.scala 29:58] + node _T_553 = cat(w0v[27], _T_552) @[Cat.scala 29:58] + node _T_554 = cat(w0v[28], _T_553) @[Cat.scala 29:58] + node _T_555 = cat(w0v[29], _T_554) @[Cat.scala 29:58] + node _T_556 = cat(w0v[30], _T_555) @[Cat.scala 29:58] + node _T_557 = cat(w0v[31], _T_556) @[Cat.scala 29:58] + node _T_558 = cat(w1v[1], w1v[0]) @[Cat.scala 29:58] + node _T_559 = cat(w1v[2], _T_558) @[Cat.scala 29:58] + node _T_560 = cat(w1v[3], _T_559) @[Cat.scala 29:58] + node _T_561 = cat(w1v[4], _T_560) @[Cat.scala 29:58] + node _T_562 = cat(w1v[5], _T_561) @[Cat.scala 29:58] + node _T_563 = cat(w1v[6], _T_562) @[Cat.scala 29:58] + node _T_564 = cat(w1v[7], _T_563) @[Cat.scala 29:58] + node _T_565 = cat(w1v[8], _T_564) @[Cat.scala 29:58] + node _T_566 = cat(w1v[9], _T_565) @[Cat.scala 29:58] + node _T_567 = cat(w1v[10], _T_566) @[Cat.scala 29:58] + node _T_568 = cat(w1v[11], _T_567) @[Cat.scala 29:58] + node _T_569 = cat(w1v[12], _T_568) @[Cat.scala 29:58] + node _T_570 = cat(w1v[13], _T_569) @[Cat.scala 29:58] + node _T_571 = cat(w1v[14], _T_570) @[Cat.scala 29:58] + node _T_572 = cat(w1v[15], _T_571) @[Cat.scala 29:58] + node _T_573 = cat(w1v[16], _T_572) @[Cat.scala 29:58] + node _T_574 = cat(w1v[17], _T_573) @[Cat.scala 29:58] + node _T_575 = cat(w1v[18], _T_574) @[Cat.scala 29:58] + node _T_576 = cat(w1v[19], _T_575) @[Cat.scala 29:58] + node _T_577 = cat(w1v[20], _T_576) @[Cat.scala 29:58] + node _T_578 = cat(w1v[21], _T_577) @[Cat.scala 29:58] + node _T_579 = cat(w1v[22], _T_578) @[Cat.scala 29:58] + node _T_580 = cat(w1v[23], _T_579) @[Cat.scala 29:58] + node _T_581 = cat(w1v[24], _T_580) @[Cat.scala 29:58] + node _T_582 = cat(w1v[25], _T_581) @[Cat.scala 29:58] + node _T_583 = cat(w1v[26], _T_582) @[Cat.scala 29:58] + node _T_584 = cat(w1v[27], _T_583) @[Cat.scala 29:58] + node _T_585 = cat(w1v[28], _T_584) @[Cat.scala 29:58] + node _T_586 = cat(w1v[29], _T_585) @[Cat.scala 29:58] + node _T_587 = cat(w1v[30], _T_586) @[Cat.scala 29:58] + node _T_588 = cat(w1v[31], _T_587) @[Cat.scala 29:58] + node _T_589 = or(_T_557, _T_588) @[dec_gpr_ctl.scala 57:57] + node _T_590 = cat(w2v[1], w2v[0]) @[Cat.scala 29:58] + node _T_591 = cat(w2v[2], _T_590) @[Cat.scala 29:58] + node _T_592 = cat(w2v[3], _T_591) @[Cat.scala 29:58] + node _T_593 = cat(w2v[4], _T_592) @[Cat.scala 29:58] + node _T_594 = cat(w2v[5], _T_593) @[Cat.scala 29:58] + node _T_595 = cat(w2v[6], _T_594) @[Cat.scala 29:58] + node _T_596 = cat(w2v[7], _T_595) @[Cat.scala 29:58] + node _T_597 = cat(w2v[8], _T_596) @[Cat.scala 29:58] + node _T_598 = cat(w2v[9], _T_597) @[Cat.scala 29:58] + node _T_599 = cat(w2v[10], _T_598) @[Cat.scala 29:58] + node _T_600 = cat(w2v[11], _T_599) @[Cat.scala 29:58] + node _T_601 = cat(w2v[12], _T_600) @[Cat.scala 29:58] + node _T_602 = cat(w2v[13], _T_601) @[Cat.scala 29:58] + node _T_603 = cat(w2v[14], _T_602) @[Cat.scala 29:58] + node _T_604 = cat(w2v[15], _T_603) @[Cat.scala 29:58] + node _T_605 = cat(w2v[16], _T_604) @[Cat.scala 29:58] + node _T_606 = cat(w2v[17], _T_605) @[Cat.scala 29:58] + node _T_607 = cat(w2v[18], _T_606) @[Cat.scala 29:58] + node _T_608 = cat(w2v[19], _T_607) @[Cat.scala 29:58] + node _T_609 = cat(w2v[20], _T_608) @[Cat.scala 29:58] + node _T_610 = cat(w2v[21], _T_609) @[Cat.scala 29:58] + node _T_611 = cat(w2v[22], _T_610) @[Cat.scala 29:58] + node _T_612 = cat(w2v[23], _T_611) @[Cat.scala 29:58] + node _T_613 = cat(w2v[24], _T_612) @[Cat.scala 29:58] + node _T_614 = cat(w2v[25], _T_613) @[Cat.scala 29:58] + node _T_615 = cat(w2v[26], _T_614) @[Cat.scala 29:58] + node _T_616 = cat(w2v[27], _T_615) @[Cat.scala 29:58] + node _T_617 = cat(w2v[28], _T_616) @[Cat.scala 29:58] + node _T_618 = cat(w2v[29], _T_617) @[Cat.scala 29:58] + node _T_619 = cat(w2v[30], _T_618) @[Cat.scala 29:58] + node _T_620 = cat(w2v[31], _T_619) @[Cat.scala 29:58] + node _T_621 = or(_T_589, _T_620) @[dec_gpr_ctl.scala 57:95] + gpr_wr_en <= _T_621 @[dec_gpr_ctl.scala 57:18] + node _T_622 = bits(gpr_wr_en, 1, 1) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr of rvclkhdr @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= _T_622 @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_623 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_622 : @[Reg.scala 28:19] + _T_623 <= gpr_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[1] <= _T_623 @[dec_gpr_ctl.scala 61:27] + node _T_624 = bits(gpr_wr_en, 2, 2) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_624 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_625 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_624 : @[Reg.scala 28:19] + _T_625 <= gpr_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[2] <= _T_625 @[dec_gpr_ctl.scala 61:27] + node _T_626 = bits(gpr_wr_en, 3, 3) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_2.io.en <= _T_626 @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_627 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_626 : @[Reg.scala 28:19] + _T_627 <= gpr_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[3] <= _T_627 @[dec_gpr_ctl.scala 61:27] + node _T_628 = bits(gpr_wr_en, 4, 4) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_3.io.en <= _T_628 @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_629 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_628 : @[Reg.scala 28:19] + _T_629 <= gpr_in[4] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[4] <= _T_629 @[dec_gpr_ctl.scala 61:27] + node _T_630 = bits(gpr_wr_en, 5, 5) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 404:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_4.io.en <= _T_630 @[lib.scala 407:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_631 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_630 : @[Reg.scala 28:19] + _T_631 <= gpr_in[5] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[5] <= _T_631 @[dec_gpr_ctl.scala 61:27] + node _T_632 = bits(gpr_wr_en, 6, 6) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 404:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_5.io.en <= _T_632 @[lib.scala 407:17] + rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_633 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_632 : @[Reg.scala 28:19] + _T_633 <= gpr_in[6] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[6] <= _T_633 @[dec_gpr_ctl.scala 61:27] + node _T_634 = bits(gpr_wr_en, 7, 7) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 404:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_6.io.en <= _T_634 @[lib.scala 407:17] + rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_635 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_634 : @[Reg.scala 28:19] + _T_635 <= gpr_in[7] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[7] <= _T_635 @[dec_gpr_ctl.scala 61:27] + node _T_636 = bits(gpr_wr_en, 8, 8) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 404:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_7.io.en <= _T_636 @[lib.scala 407:17] + rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_637 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_636 : @[Reg.scala 28:19] + _T_637 <= gpr_in[8] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[8] <= _T_637 @[dec_gpr_ctl.scala 61:27] + node _T_638 = bits(gpr_wr_en, 9, 9) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 404:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_8.io.en <= _T_638 @[lib.scala 407:17] + rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_639 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_638 : @[Reg.scala 28:19] + _T_639 <= gpr_in[9] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[9] <= _T_639 @[dec_gpr_ctl.scala 61:27] + node _T_640 = bits(gpr_wr_en, 10, 10) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 404:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_9.io.en <= _T_640 @[lib.scala 407:17] + rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_641 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_640 : @[Reg.scala 28:19] + _T_641 <= gpr_in[10] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[10] <= _T_641 @[dec_gpr_ctl.scala 61:27] + node _T_642 = bits(gpr_wr_en, 11, 11) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 404:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_10.io.en <= _T_642 @[lib.scala 407:17] + rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_643 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_642 : @[Reg.scala 28:19] + _T_643 <= gpr_in[11] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[11] <= _T_643 @[dec_gpr_ctl.scala 61:27] + node _T_644 = bits(gpr_wr_en, 12, 12) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_11 of rvclkhdr_11 @[lib.scala 404:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_11.io.en <= _T_644 @[lib.scala 407:17] + rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_645 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_644 : @[Reg.scala 28:19] + _T_645 <= gpr_in[12] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[12] <= _T_645 @[dec_gpr_ctl.scala 61:27] + node _T_646 = bits(gpr_wr_en, 13, 13) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_12 of rvclkhdr_12 @[lib.scala 404:23] + rvclkhdr_12.clock <= clock + rvclkhdr_12.reset <= reset + rvclkhdr_12.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_12.io.en <= _T_646 @[lib.scala 407:17] + rvclkhdr_12.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_647 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_646 : @[Reg.scala 28:19] + _T_647 <= gpr_in[13] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[13] <= _T_647 @[dec_gpr_ctl.scala 61:27] + node _T_648 = bits(gpr_wr_en, 14, 14) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_13 of rvclkhdr_13 @[lib.scala 404:23] + rvclkhdr_13.clock <= clock + rvclkhdr_13.reset <= reset + rvclkhdr_13.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_13.io.en <= _T_648 @[lib.scala 407:17] + rvclkhdr_13.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_649 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_648 : @[Reg.scala 28:19] + _T_649 <= gpr_in[14] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[14] <= _T_649 @[dec_gpr_ctl.scala 61:27] + node _T_650 = bits(gpr_wr_en, 15, 15) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_14 of rvclkhdr_14 @[lib.scala 404:23] + rvclkhdr_14.clock <= clock + rvclkhdr_14.reset <= reset + rvclkhdr_14.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_14.io.en <= _T_650 @[lib.scala 407:17] + rvclkhdr_14.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_651 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_650 : @[Reg.scala 28:19] + _T_651 <= gpr_in[15] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[15] <= _T_651 @[dec_gpr_ctl.scala 61:27] + node _T_652 = bits(gpr_wr_en, 16, 16) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_15 of rvclkhdr_15 @[lib.scala 404:23] + rvclkhdr_15.clock <= clock + rvclkhdr_15.reset <= reset + rvclkhdr_15.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_15.io.en <= _T_652 @[lib.scala 407:17] + rvclkhdr_15.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_653 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_652 : @[Reg.scala 28:19] + _T_653 <= gpr_in[16] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[16] <= _T_653 @[dec_gpr_ctl.scala 61:27] + node _T_654 = bits(gpr_wr_en, 17, 17) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_16 of rvclkhdr_16 @[lib.scala 404:23] + rvclkhdr_16.clock <= clock + rvclkhdr_16.reset <= reset + rvclkhdr_16.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_16.io.en <= _T_654 @[lib.scala 407:17] + rvclkhdr_16.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_655 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_654 : @[Reg.scala 28:19] + _T_655 <= gpr_in[17] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[17] <= _T_655 @[dec_gpr_ctl.scala 61:27] + node _T_656 = bits(gpr_wr_en, 18, 18) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_17 of rvclkhdr_17 @[lib.scala 404:23] + rvclkhdr_17.clock <= clock + rvclkhdr_17.reset <= reset + rvclkhdr_17.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_17.io.en <= _T_656 @[lib.scala 407:17] + rvclkhdr_17.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_657 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_656 : @[Reg.scala 28:19] + _T_657 <= gpr_in[18] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[18] <= _T_657 @[dec_gpr_ctl.scala 61:27] + node _T_658 = bits(gpr_wr_en, 19, 19) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_18 of rvclkhdr_18 @[lib.scala 404:23] + rvclkhdr_18.clock <= clock + rvclkhdr_18.reset <= reset + rvclkhdr_18.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_18.io.en <= _T_658 @[lib.scala 407:17] + rvclkhdr_18.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_659 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_658 : @[Reg.scala 28:19] + _T_659 <= gpr_in[19] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[19] <= _T_659 @[dec_gpr_ctl.scala 61:27] + node _T_660 = bits(gpr_wr_en, 20, 20) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_19 of rvclkhdr_19 @[lib.scala 404:23] + rvclkhdr_19.clock <= clock + rvclkhdr_19.reset <= reset + rvclkhdr_19.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_19.io.en <= _T_660 @[lib.scala 407:17] + rvclkhdr_19.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_661 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_660 : @[Reg.scala 28:19] + _T_661 <= gpr_in[20] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[20] <= _T_661 @[dec_gpr_ctl.scala 61:27] + node _T_662 = bits(gpr_wr_en, 21, 21) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_20 of rvclkhdr_20 @[lib.scala 404:23] + rvclkhdr_20.clock <= clock + rvclkhdr_20.reset <= reset + rvclkhdr_20.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_20.io.en <= _T_662 @[lib.scala 407:17] + rvclkhdr_20.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_663 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_662 : @[Reg.scala 28:19] + _T_663 <= gpr_in[21] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[21] <= _T_663 @[dec_gpr_ctl.scala 61:27] + node _T_664 = bits(gpr_wr_en, 22, 22) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_21 of rvclkhdr_21 @[lib.scala 404:23] + rvclkhdr_21.clock <= clock + rvclkhdr_21.reset <= reset + rvclkhdr_21.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_21.io.en <= _T_664 @[lib.scala 407:17] + rvclkhdr_21.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_665 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_664 : @[Reg.scala 28:19] + _T_665 <= gpr_in[22] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[22] <= _T_665 @[dec_gpr_ctl.scala 61:27] + node _T_666 = bits(gpr_wr_en, 23, 23) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_22 of rvclkhdr_22 @[lib.scala 404:23] + rvclkhdr_22.clock <= clock + rvclkhdr_22.reset <= reset + rvclkhdr_22.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_22.io.en <= _T_666 @[lib.scala 407:17] + rvclkhdr_22.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_667 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_666 : @[Reg.scala 28:19] + _T_667 <= gpr_in[23] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[23] <= _T_667 @[dec_gpr_ctl.scala 61:27] + node _T_668 = bits(gpr_wr_en, 24, 24) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_23 of rvclkhdr_23 @[lib.scala 404:23] + rvclkhdr_23.clock <= clock + rvclkhdr_23.reset <= reset + rvclkhdr_23.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_23.io.en <= _T_668 @[lib.scala 407:17] + rvclkhdr_23.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_669 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_668 : @[Reg.scala 28:19] + _T_669 <= gpr_in[24] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[24] <= _T_669 @[dec_gpr_ctl.scala 61:27] + node _T_670 = bits(gpr_wr_en, 25, 25) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_24 of rvclkhdr_24 @[lib.scala 404:23] + rvclkhdr_24.clock <= clock + rvclkhdr_24.reset <= reset + rvclkhdr_24.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_24.io.en <= _T_670 @[lib.scala 407:17] + rvclkhdr_24.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_671 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_670 : @[Reg.scala 28:19] + _T_671 <= gpr_in[25] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[25] <= _T_671 @[dec_gpr_ctl.scala 61:27] + node _T_672 = bits(gpr_wr_en, 26, 26) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_25 of rvclkhdr_25 @[lib.scala 404:23] + rvclkhdr_25.clock <= clock + rvclkhdr_25.reset <= reset + rvclkhdr_25.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_25.io.en <= _T_672 @[lib.scala 407:17] + rvclkhdr_25.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_673 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_672 : @[Reg.scala 28:19] + _T_673 <= gpr_in[26] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[26] <= _T_673 @[dec_gpr_ctl.scala 61:27] + node _T_674 = bits(gpr_wr_en, 27, 27) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_26 of rvclkhdr_26 @[lib.scala 404:23] + rvclkhdr_26.clock <= clock + rvclkhdr_26.reset <= reset + rvclkhdr_26.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_26.io.en <= _T_674 @[lib.scala 407:17] + rvclkhdr_26.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_675 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_674 : @[Reg.scala 28:19] + _T_675 <= gpr_in[27] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[27] <= _T_675 @[dec_gpr_ctl.scala 61:27] + node _T_676 = bits(gpr_wr_en, 28, 28) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_27 of rvclkhdr_27 @[lib.scala 404:23] + rvclkhdr_27.clock <= clock + rvclkhdr_27.reset <= reset + rvclkhdr_27.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_27.io.en <= _T_676 @[lib.scala 407:17] + rvclkhdr_27.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_677 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_676 : @[Reg.scala 28:19] + _T_677 <= gpr_in[28] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[28] <= _T_677 @[dec_gpr_ctl.scala 61:27] + node _T_678 = bits(gpr_wr_en, 29, 29) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_28 of rvclkhdr_28 @[lib.scala 404:23] + rvclkhdr_28.clock <= clock + rvclkhdr_28.reset <= reset + rvclkhdr_28.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_28.io.en <= _T_678 @[lib.scala 407:17] + rvclkhdr_28.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_679 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_678 : @[Reg.scala 28:19] + _T_679 <= gpr_in[29] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[29] <= _T_679 @[dec_gpr_ctl.scala 61:27] + node _T_680 = bits(gpr_wr_en, 30, 30) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_29 of rvclkhdr_29 @[lib.scala 404:23] + rvclkhdr_29.clock <= clock + rvclkhdr_29.reset <= reset + rvclkhdr_29.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_29.io.en <= _T_680 @[lib.scala 407:17] + rvclkhdr_29.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_681 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_680 : @[Reg.scala 28:19] + _T_681 <= gpr_in[30] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[30] <= _T_681 @[dec_gpr_ctl.scala 61:27] + node _T_682 = bits(gpr_wr_en, 31, 31) @[dec_gpr_ctl.scala 61:55] + inst rvclkhdr_30 of rvclkhdr_30 @[lib.scala 404:23] + rvclkhdr_30.clock <= clock + rvclkhdr_30.reset <= reset + rvclkhdr_30.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_30.io.en <= _T_682 @[lib.scala 407:17] + rvclkhdr_30.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_683 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_682 : @[Reg.scala 28:19] + _T_683 <= gpr_in[31] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gpr_out[31] <= _T_683 @[dec_gpr_ctl.scala 61:27] + node _T_684 = eq(io.raddr0, UInt<1>("h01")) @[dec_gpr_ctl.scala 64:72] + node _T_685 = bits(_T_684, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_686 = eq(io.raddr0, UInt<2>("h02")) @[dec_gpr_ctl.scala 64:72] + node _T_687 = bits(_T_686, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_688 = eq(io.raddr0, UInt<2>("h03")) @[dec_gpr_ctl.scala 64:72] + node _T_689 = bits(_T_688, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_690 = eq(io.raddr0, UInt<3>("h04")) @[dec_gpr_ctl.scala 64:72] + node _T_691 = bits(_T_690, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_692 = eq(io.raddr0, UInt<3>("h05")) @[dec_gpr_ctl.scala 64:72] + node _T_693 = bits(_T_692, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_694 = eq(io.raddr0, UInt<3>("h06")) @[dec_gpr_ctl.scala 64:72] + node _T_695 = bits(_T_694, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_696 = eq(io.raddr0, UInt<3>("h07")) @[dec_gpr_ctl.scala 64:72] + node _T_697 = bits(_T_696, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_698 = eq(io.raddr0, UInt<4>("h08")) @[dec_gpr_ctl.scala 64:72] + node _T_699 = bits(_T_698, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_700 = eq(io.raddr0, UInt<4>("h09")) @[dec_gpr_ctl.scala 64:72] + node _T_701 = bits(_T_700, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_702 = eq(io.raddr0, UInt<4>("h0a")) @[dec_gpr_ctl.scala 64:72] + node _T_703 = bits(_T_702, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_704 = eq(io.raddr0, UInt<4>("h0b")) @[dec_gpr_ctl.scala 64:72] + node _T_705 = bits(_T_704, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_706 = eq(io.raddr0, UInt<4>("h0c")) @[dec_gpr_ctl.scala 64:72] + node _T_707 = bits(_T_706, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_708 = eq(io.raddr0, UInt<4>("h0d")) @[dec_gpr_ctl.scala 64:72] + node _T_709 = bits(_T_708, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_710 = eq(io.raddr0, UInt<4>("h0e")) @[dec_gpr_ctl.scala 64:72] + node _T_711 = bits(_T_710, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_712 = eq(io.raddr0, UInt<4>("h0f")) @[dec_gpr_ctl.scala 64:72] + node _T_713 = bits(_T_712, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_714 = eq(io.raddr0, UInt<5>("h010")) @[dec_gpr_ctl.scala 64:72] + node _T_715 = bits(_T_714, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_716 = eq(io.raddr0, UInt<5>("h011")) @[dec_gpr_ctl.scala 64:72] + node _T_717 = bits(_T_716, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_718 = eq(io.raddr0, UInt<5>("h012")) @[dec_gpr_ctl.scala 64:72] + node _T_719 = bits(_T_718, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_720 = eq(io.raddr0, UInt<5>("h013")) @[dec_gpr_ctl.scala 64:72] + node _T_721 = bits(_T_720, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_722 = eq(io.raddr0, UInt<5>("h014")) @[dec_gpr_ctl.scala 64:72] + node _T_723 = bits(_T_722, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_724 = eq(io.raddr0, UInt<5>("h015")) @[dec_gpr_ctl.scala 64:72] + node _T_725 = bits(_T_724, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_726 = eq(io.raddr0, UInt<5>("h016")) @[dec_gpr_ctl.scala 64:72] + node _T_727 = bits(_T_726, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_728 = eq(io.raddr0, UInt<5>("h017")) @[dec_gpr_ctl.scala 64:72] + node _T_729 = bits(_T_728, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_730 = eq(io.raddr0, UInt<5>("h018")) @[dec_gpr_ctl.scala 64:72] + node _T_731 = bits(_T_730, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_732 = eq(io.raddr0, UInt<5>("h019")) @[dec_gpr_ctl.scala 64:72] + node _T_733 = bits(_T_732, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_734 = eq(io.raddr0, UInt<5>("h01a")) @[dec_gpr_ctl.scala 64:72] + node _T_735 = bits(_T_734, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_736 = eq(io.raddr0, UInt<5>("h01b")) @[dec_gpr_ctl.scala 64:72] + node _T_737 = bits(_T_736, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_738 = eq(io.raddr0, UInt<5>("h01c")) @[dec_gpr_ctl.scala 64:72] + node _T_739 = bits(_T_738, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_740 = eq(io.raddr0, UInt<5>("h01d")) @[dec_gpr_ctl.scala 64:72] + node _T_741 = bits(_T_740, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_742 = eq(io.raddr0, UInt<5>("h01e")) @[dec_gpr_ctl.scala 64:72] + node _T_743 = bits(_T_742, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_744 = eq(io.raddr0, UInt<5>("h01f")) @[dec_gpr_ctl.scala 64:72] + node _T_745 = bits(_T_744, 0, 0) @[dec_gpr_ctl.scala 64:80] + node _T_746 = mux(_T_685, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_747 = mux(_T_687, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_748 = mux(_T_689, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_749 = mux(_T_691, gpr_out[4], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_750 = mux(_T_693, gpr_out[5], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_751 = mux(_T_695, gpr_out[6], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_752 = mux(_T_697, gpr_out[7], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_753 = mux(_T_699, gpr_out[8], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_754 = mux(_T_701, gpr_out[9], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_755 = mux(_T_703, gpr_out[10], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_756 = mux(_T_705, gpr_out[11], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_757 = mux(_T_707, gpr_out[12], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_758 = mux(_T_709, gpr_out[13], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_759 = mux(_T_711, gpr_out[14], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_760 = mux(_T_713, gpr_out[15], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_761 = mux(_T_715, gpr_out[16], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_762 = mux(_T_717, gpr_out[17], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_763 = mux(_T_719, gpr_out[18], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_764 = mux(_T_721, gpr_out[19], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_765 = mux(_T_723, gpr_out[20], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_766 = mux(_T_725, gpr_out[21], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_767 = mux(_T_727, gpr_out[22], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_768 = mux(_T_729, gpr_out[23], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_769 = mux(_T_731, gpr_out[24], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_770 = mux(_T_733, gpr_out[25], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_771 = mux(_T_735, gpr_out[26], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_772 = mux(_T_737, gpr_out[27], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_773 = mux(_T_739, gpr_out[28], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_774 = mux(_T_741, gpr_out[29], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_775 = mux(_T_743, gpr_out[30], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_776 = mux(_T_745, gpr_out[31], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_777 = or(_T_746, _T_747) @[Mux.scala 27:72] + node _T_778 = or(_T_777, _T_748) @[Mux.scala 27:72] + node _T_779 = or(_T_778, _T_749) @[Mux.scala 27:72] + node _T_780 = or(_T_779, _T_750) @[Mux.scala 27:72] + node _T_781 = or(_T_780, _T_751) @[Mux.scala 27:72] + node _T_782 = or(_T_781, _T_752) @[Mux.scala 27:72] + node _T_783 = or(_T_782, _T_753) @[Mux.scala 27:72] + node _T_784 = or(_T_783, _T_754) @[Mux.scala 27:72] + node _T_785 = or(_T_784, _T_755) @[Mux.scala 27:72] + node _T_786 = or(_T_785, _T_756) @[Mux.scala 27:72] + node _T_787 = or(_T_786, _T_757) @[Mux.scala 27:72] + node _T_788 = or(_T_787, _T_758) @[Mux.scala 27:72] + node _T_789 = or(_T_788, _T_759) @[Mux.scala 27:72] + node _T_790 = or(_T_789, _T_760) @[Mux.scala 27:72] + node _T_791 = or(_T_790, _T_761) @[Mux.scala 27:72] + node _T_792 = or(_T_791, _T_762) @[Mux.scala 27:72] + node _T_793 = or(_T_792, _T_763) @[Mux.scala 27:72] + node _T_794 = or(_T_793, _T_764) @[Mux.scala 27:72] + node _T_795 = or(_T_794, _T_765) @[Mux.scala 27:72] + node _T_796 = or(_T_795, _T_766) @[Mux.scala 27:72] + node _T_797 = or(_T_796, _T_767) @[Mux.scala 27:72] + node _T_798 = or(_T_797, _T_768) @[Mux.scala 27:72] + node _T_799 = or(_T_798, _T_769) @[Mux.scala 27:72] + node _T_800 = or(_T_799, _T_770) @[Mux.scala 27:72] + node _T_801 = or(_T_800, _T_771) @[Mux.scala 27:72] + node _T_802 = or(_T_801, _T_772) @[Mux.scala 27:72] + node _T_803 = or(_T_802, _T_773) @[Mux.scala 27:72] + node _T_804 = or(_T_803, _T_774) @[Mux.scala 27:72] + node _T_805 = or(_T_804, _T_775) @[Mux.scala 27:72] + node _T_806 = or(_T_805, _T_776) @[Mux.scala 27:72] + wire _T_807 : UInt<32> @[Mux.scala 27:72] + _T_807 <= _T_806 @[Mux.scala 27:72] + io.gpr_exu.gpr_i0_rs1_d <= _T_807 @[dec_gpr_ctl.scala 64:32] + node _T_808 = eq(io.raddr1, UInt<1>("h01")) @[dec_gpr_ctl.scala 65:72] + node _T_809 = bits(_T_808, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_810 = eq(io.raddr1, UInt<2>("h02")) @[dec_gpr_ctl.scala 65:72] + node _T_811 = bits(_T_810, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_812 = eq(io.raddr1, UInt<2>("h03")) @[dec_gpr_ctl.scala 65:72] + node _T_813 = bits(_T_812, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_814 = eq(io.raddr1, UInt<3>("h04")) @[dec_gpr_ctl.scala 65:72] + node _T_815 = bits(_T_814, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_816 = eq(io.raddr1, UInt<3>("h05")) @[dec_gpr_ctl.scala 65:72] + node _T_817 = bits(_T_816, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_818 = eq(io.raddr1, UInt<3>("h06")) @[dec_gpr_ctl.scala 65:72] + node _T_819 = bits(_T_818, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_820 = eq(io.raddr1, UInt<3>("h07")) @[dec_gpr_ctl.scala 65:72] + node _T_821 = bits(_T_820, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_822 = eq(io.raddr1, UInt<4>("h08")) @[dec_gpr_ctl.scala 65:72] + node _T_823 = bits(_T_822, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_824 = eq(io.raddr1, UInt<4>("h09")) @[dec_gpr_ctl.scala 65:72] + node _T_825 = bits(_T_824, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_826 = eq(io.raddr1, UInt<4>("h0a")) @[dec_gpr_ctl.scala 65:72] + node _T_827 = bits(_T_826, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_828 = eq(io.raddr1, UInt<4>("h0b")) @[dec_gpr_ctl.scala 65:72] + node _T_829 = bits(_T_828, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_830 = eq(io.raddr1, UInt<4>("h0c")) @[dec_gpr_ctl.scala 65:72] + node _T_831 = bits(_T_830, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_832 = eq(io.raddr1, UInt<4>("h0d")) @[dec_gpr_ctl.scala 65:72] + node _T_833 = bits(_T_832, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_834 = eq(io.raddr1, UInt<4>("h0e")) @[dec_gpr_ctl.scala 65:72] + node _T_835 = bits(_T_834, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_836 = eq(io.raddr1, UInt<4>("h0f")) @[dec_gpr_ctl.scala 65:72] + node _T_837 = bits(_T_836, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_838 = eq(io.raddr1, UInt<5>("h010")) @[dec_gpr_ctl.scala 65:72] + node _T_839 = bits(_T_838, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_840 = eq(io.raddr1, UInt<5>("h011")) @[dec_gpr_ctl.scala 65:72] + node _T_841 = bits(_T_840, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_842 = eq(io.raddr1, UInt<5>("h012")) @[dec_gpr_ctl.scala 65:72] + node _T_843 = bits(_T_842, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_844 = eq(io.raddr1, UInt<5>("h013")) @[dec_gpr_ctl.scala 65:72] + node _T_845 = bits(_T_844, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_846 = eq(io.raddr1, UInt<5>("h014")) @[dec_gpr_ctl.scala 65:72] + node _T_847 = bits(_T_846, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_848 = eq(io.raddr1, UInt<5>("h015")) @[dec_gpr_ctl.scala 65:72] + node _T_849 = bits(_T_848, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_850 = eq(io.raddr1, UInt<5>("h016")) @[dec_gpr_ctl.scala 65:72] + node _T_851 = bits(_T_850, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_852 = eq(io.raddr1, UInt<5>("h017")) @[dec_gpr_ctl.scala 65:72] + node _T_853 = bits(_T_852, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_854 = eq(io.raddr1, UInt<5>("h018")) @[dec_gpr_ctl.scala 65:72] + node _T_855 = bits(_T_854, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_856 = eq(io.raddr1, UInt<5>("h019")) @[dec_gpr_ctl.scala 65:72] + node _T_857 = bits(_T_856, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_858 = eq(io.raddr1, UInt<5>("h01a")) @[dec_gpr_ctl.scala 65:72] + node _T_859 = bits(_T_858, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_860 = eq(io.raddr1, UInt<5>("h01b")) @[dec_gpr_ctl.scala 65:72] + node _T_861 = bits(_T_860, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_862 = eq(io.raddr1, UInt<5>("h01c")) @[dec_gpr_ctl.scala 65:72] + node _T_863 = bits(_T_862, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_864 = eq(io.raddr1, UInt<5>("h01d")) @[dec_gpr_ctl.scala 65:72] + node _T_865 = bits(_T_864, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_866 = eq(io.raddr1, UInt<5>("h01e")) @[dec_gpr_ctl.scala 65:72] + node _T_867 = bits(_T_866, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_868 = eq(io.raddr1, UInt<5>("h01f")) @[dec_gpr_ctl.scala 65:72] + node _T_869 = bits(_T_868, 0, 0) @[dec_gpr_ctl.scala 65:80] + node _T_870 = mux(_T_809, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_871 = mux(_T_811, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_872 = mux(_T_813, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_873 = mux(_T_815, gpr_out[4], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_874 = mux(_T_817, gpr_out[5], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_875 = mux(_T_819, gpr_out[6], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_876 = mux(_T_821, gpr_out[7], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_877 = mux(_T_823, gpr_out[8], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_878 = mux(_T_825, gpr_out[9], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_879 = mux(_T_827, gpr_out[10], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_880 = mux(_T_829, gpr_out[11], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_881 = mux(_T_831, gpr_out[12], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_882 = mux(_T_833, gpr_out[13], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_883 = mux(_T_835, gpr_out[14], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_884 = mux(_T_837, gpr_out[15], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_885 = mux(_T_839, gpr_out[16], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_886 = mux(_T_841, gpr_out[17], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_887 = mux(_T_843, gpr_out[18], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_888 = mux(_T_845, gpr_out[19], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_889 = mux(_T_847, gpr_out[20], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_890 = mux(_T_849, gpr_out[21], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_891 = mux(_T_851, gpr_out[22], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_892 = mux(_T_853, gpr_out[23], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_893 = mux(_T_855, gpr_out[24], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_894 = mux(_T_857, gpr_out[25], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_895 = mux(_T_859, gpr_out[26], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_896 = mux(_T_861, gpr_out[27], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_897 = mux(_T_863, gpr_out[28], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_898 = mux(_T_865, gpr_out[29], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_899 = mux(_T_867, gpr_out[30], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_900 = mux(_T_869, gpr_out[31], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_901 = or(_T_870, _T_871) @[Mux.scala 27:72] + node _T_902 = or(_T_901, _T_872) @[Mux.scala 27:72] + node _T_903 = or(_T_902, _T_873) @[Mux.scala 27:72] + node _T_904 = or(_T_903, _T_874) @[Mux.scala 27:72] + node _T_905 = or(_T_904, _T_875) @[Mux.scala 27:72] + node _T_906 = or(_T_905, _T_876) @[Mux.scala 27:72] + node _T_907 = or(_T_906, _T_877) @[Mux.scala 27:72] + node _T_908 = or(_T_907, _T_878) @[Mux.scala 27:72] + node _T_909 = or(_T_908, _T_879) @[Mux.scala 27:72] + node _T_910 = or(_T_909, _T_880) @[Mux.scala 27:72] + node _T_911 = or(_T_910, _T_881) @[Mux.scala 27:72] + node _T_912 = or(_T_911, _T_882) @[Mux.scala 27:72] + node _T_913 = or(_T_912, _T_883) @[Mux.scala 27:72] + node _T_914 = or(_T_913, _T_884) @[Mux.scala 27:72] + node _T_915 = or(_T_914, _T_885) @[Mux.scala 27:72] + node _T_916 = or(_T_915, _T_886) @[Mux.scala 27:72] + node _T_917 = or(_T_916, _T_887) @[Mux.scala 27:72] + node _T_918 = or(_T_917, _T_888) @[Mux.scala 27:72] + node _T_919 = or(_T_918, _T_889) @[Mux.scala 27:72] + node _T_920 = or(_T_919, _T_890) @[Mux.scala 27:72] + node _T_921 = or(_T_920, _T_891) @[Mux.scala 27:72] + node _T_922 = or(_T_921, _T_892) @[Mux.scala 27:72] + node _T_923 = or(_T_922, _T_893) @[Mux.scala 27:72] + node _T_924 = or(_T_923, _T_894) @[Mux.scala 27:72] + node _T_925 = or(_T_924, _T_895) @[Mux.scala 27:72] + node _T_926 = or(_T_925, _T_896) @[Mux.scala 27:72] + node _T_927 = or(_T_926, _T_897) @[Mux.scala 27:72] + node _T_928 = or(_T_927, _T_898) @[Mux.scala 27:72] + node _T_929 = or(_T_928, _T_899) @[Mux.scala 27:72] + node _T_930 = or(_T_929, _T_900) @[Mux.scala 27:72] + wire _T_931 : UInt<32> @[Mux.scala 27:72] + _T_931 <= _T_930 @[Mux.scala 27:72] + io.gpr_exu.gpr_i0_rs2_d <= _T_931 @[dec_gpr_ctl.scala 65:32] + diff --git a/dec_gpr_ctl.v b/dec_gpr_ctl.v new file mode 100644 index 00000000..bd4215ca --- /dev/null +++ b/dec_gpr_ctl.v @@ -0,0 +1,1395 @@ +module rvclkhdr( + input io_clk, + input io_en +); + wire clkhdr_Q; // @[lib.scala 334:26] + wire clkhdr_CK; // @[lib.scala 334:26] + wire clkhdr_EN; // @[lib.scala 334:26] + wire clkhdr_SE; // @[lib.scala 334:26] + gated_latch clkhdr ( // @[lib.scala 334:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign clkhdr_CK = io_clk; // @[lib.scala 336:18] + assign clkhdr_EN = io_en; // @[lib.scala 337:18] + assign clkhdr_SE = 1'h0; // @[lib.scala 338:18] +endmodule +module dec_gpr_ctl( + input clock, + input reset, + input [4:0] io_raddr0, + input [4:0] io_raddr1, + input io_wen0, + input [4:0] io_waddr0, + input [31:0] io_wd0, + input io_wen1, + input [4:0] io_waddr1, + input [31:0] io_wd1, + input io_wen2, + input [4:0] io_waddr2, + input [31:0] io_wd2, + input io_scan_mode, + output [31:0] io_gpr_exu_gpr_i0_rs1_d, + output [31:0] io_gpr_exu_gpr_i0_rs2_d +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_4_io_en; // @[lib.scala 404:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_5_io_en; // @[lib.scala 404:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_6_io_en; // @[lib.scala 404:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_7_io_en; // @[lib.scala 404:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_8_io_en; // @[lib.scala 404:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_9_io_en; // @[lib.scala 404:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_10_io_en; // @[lib.scala 404:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_11_io_en; // @[lib.scala 404:23] + wire rvclkhdr_12_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_12_io_en; // @[lib.scala 404:23] + wire rvclkhdr_13_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_13_io_en; // @[lib.scala 404:23] + wire rvclkhdr_14_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_14_io_en; // @[lib.scala 404:23] + wire rvclkhdr_15_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_15_io_en; // @[lib.scala 404:23] + wire rvclkhdr_16_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_16_io_en; // @[lib.scala 404:23] + wire rvclkhdr_17_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_17_io_en; // @[lib.scala 404:23] + wire rvclkhdr_18_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_18_io_en; // @[lib.scala 404:23] + wire rvclkhdr_19_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_19_io_en; // @[lib.scala 404:23] + wire rvclkhdr_20_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_20_io_en; // @[lib.scala 404:23] + wire rvclkhdr_21_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_21_io_en; // @[lib.scala 404:23] + wire rvclkhdr_22_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_22_io_en; // @[lib.scala 404:23] + wire rvclkhdr_23_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_23_io_en; // @[lib.scala 404:23] + wire rvclkhdr_24_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_24_io_en; // @[lib.scala 404:23] + wire rvclkhdr_25_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_25_io_en; // @[lib.scala 404:23] + wire rvclkhdr_26_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_26_io_en; // @[lib.scala 404:23] + wire rvclkhdr_27_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_27_io_en; // @[lib.scala 404:23] + wire rvclkhdr_28_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_28_io_en; // @[lib.scala 404:23] + wire rvclkhdr_29_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_29_io_en; // @[lib.scala 404:23] + wire rvclkhdr_30_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_30_io_en; // @[lib.scala 404:23] + wire _T = io_waddr0 == 5'h1; // @[dec_gpr_ctl.scala 52:52] + wire w0v_1 = io_wen0 & _T; // @[dec_gpr_ctl.scala 52:40] + wire _T_2 = io_waddr1 == 5'h1; // @[dec_gpr_ctl.scala 53:52] + wire w1v_1 = io_wen1 & _T_2; // @[dec_gpr_ctl.scala 53:40] + wire _T_4 = io_waddr2 == 5'h1; // @[dec_gpr_ctl.scala 54:52] + wire w2v_1 = io_wen2 & _T_4; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_7 = w0v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_8 = _T_7 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_10 = w1v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_11 = _T_10 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_12 = _T_8 | _T_11; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_14 = w2v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_15 = _T_14 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_1 = _T_12 | _T_15; // @[dec_gpr_ctl.scala 55:88] + wire _T_17 = io_waddr0 == 5'h2; // @[dec_gpr_ctl.scala 52:52] + wire w0v_2 = io_wen0 & _T_17; // @[dec_gpr_ctl.scala 52:40] + wire _T_19 = io_waddr1 == 5'h2; // @[dec_gpr_ctl.scala 53:52] + wire w1v_2 = io_wen1 & _T_19; // @[dec_gpr_ctl.scala 53:40] + wire _T_21 = io_waddr2 == 5'h2; // @[dec_gpr_ctl.scala 54:52] + wire w2v_2 = io_wen2 & _T_21; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_24 = w0v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_25 = _T_24 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_27 = w1v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_28 = _T_27 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_29 = _T_25 | _T_28; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_31 = w2v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_32 = _T_31 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_2 = _T_29 | _T_32; // @[dec_gpr_ctl.scala 55:88] + wire _T_34 = io_waddr0 == 5'h3; // @[dec_gpr_ctl.scala 52:52] + wire w0v_3 = io_wen0 & _T_34; // @[dec_gpr_ctl.scala 52:40] + wire _T_36 = io_waddr1 == 5'h3; // @[dec_gpr_ctl.scala 53:52] + wire w1v_3 = io_wen1 & _T_36; // @[dec_gpr_ctl.scala 53:40] + wire _T_38 = io_waddr2 == 5'h3; // @[dec_gpr_ctl.scala 54:52] + wire w2v_3 = io_wen2 & _T_38; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_41 = w0v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_42 = _T_41 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_44 = w1v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_45 = _T_44 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_46 = _T_42 | _T_45; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_48 = w2v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_49 = _T_48 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_3 = _T_46 | _T_49; // @[dec_gpr_ctl.scala 55:88] + wire _T_51 = io_waddr0 == 5'h4; // @[dec_gpr_ctl.scala 52:52] + wire w0v_4 = io_wen0 & _T_51; // @[dec_gpr_ctl.scala 52:40] + wire _T_53 = io_waddr1 == 5'h4; // @[dec_gpr_ctl.scala 53:52] + wire w1v_4 = io_wen1 & _T_53; // @[dec_gpr_ctl.scala 53:40] + wire _T_55 = io_waddr2 == 5'h4; // @[dec_gpr_ctl.scala 54:52] + wire w2v_4 = io_wen2 & _T_55; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_58 = w0v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_59 = _T_58 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_61 = w1v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_62 = _T_61 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_63 = _T_59 | _T_62; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_65 = w2v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_66 = _T_65 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_4 = _T_63 | _T_66; // @[dec_gpr_ctl.scala 55:88] + wire _T_68 = io_waddr0 == 5'h5; // @[dec_gpr_ctl.scala 52:52] + wire w0v_5 = io_wen0 & _T_68; // @[dec_gpr_ctl.scala 52:40] + wire _T_70 = io_waddr1 == 5'h5; // @[dec_gpr_ctl.scala 53:52] + wire w1v_5 = io_wen1 & _T_70; // @[dec_gpr_ctl.scala 53:40] + wire _T_72 = io_waddr2 == 5'h5; // @[dec_gpr_ctl.scala 54:52] + wire w2v_5 = io_wen2 & _T_72; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_75 = w0v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_76 = _T_75 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_78 = w1v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_79 = _T_78 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_80 = _T_76 | _T_79; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_82 = w2v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_83 = _T_82 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_5 = _T_80 | _T_83; // @[dec_gpr_ctl.scala 55:88] + wire _T_85 = io_waddr0 == 5'h6; // @[dec_gpr_ctl.scala 52:52] + wire w0v_6 = io_wen0 & _T_85; // @[dec_gpr_ctl.scala 52:40] + wire _T_87 = io_waddr1 == 5'h6; // @[dec_gpr_ctl.scala 53:52] + wire w1v_6 = io_wen1 & _T_87; // @[dec_gpr_ctl.scala 53:40] + wire _T_89 = io_waddr2 == 5'h6; // @[dec_gpr_ctl.scala 54:52] + wire w2v_6 = io_wen2 & _T_89; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_92 = w0v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_93 = _T_92 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_95 = w1v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_96 = _T_95 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_97 = _T_93 | _T_96; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_99 = w2v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_100 = _T_99 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_6 = _T_97 | _T_100; // @[dec_gpr_ctl.scala 55:88] + wire _T_102 = io_waddr0 == 5'h7; // @[dec_gpr_ctl.scala 52:52] + wire w0v_7 = io_wen0 & _T_102; // @[dec_gpr_ctl.scala 52:40] + wire _T_104 = io_waddr1 == 5'h7; // @[dec_gpr_ctl.scala 53:52] + wire w1v_7 = io_wen1 & _T_104; // @[dec_gpr_ctl.scala 53:40] + wire _T_106 = io_waddr2 == 5'h7; // @[dec_gpr_ctl.scala 54:52] + wire w2v_7 = io_wen2 & _T_106; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_109 = w0v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_110 = _T_109 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_112 = w1v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_113 = _T_112 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_114 = _T_110 | _T_113; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_116 = w2v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_117 = _T_116 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_7 = _T_114 | _T_117; // @[dec_gpr_ctl.scala 55:88] + wire _T_119 = io_waddr0 == 5'h8; // @[dec_gpr_ctl.scala 52:52] + wire w0v_8 = io_wen0 & _T_119; // @[dec_gpr_ctl.scala 52:40] + wire _T_121 = io_waddr1 == 5'h8; // @[dec_gpr_ctl.scala 53:52] + wire w1v_8 = io_wen1 & _T_121; // @[dec_gpr_ctl.scala 53:40] + wire _T_123 = io_waddr2 == 5'h8; // @[dec_gpr_ctl.scala 54:52] + wire w2v_8 = io_wen2 & _T_123; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_126 = w0v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_127 = _T_126 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_129 = w1v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_130 = _T_129 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_131 = _T_127 | _T_130; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_133 = w2v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_134 = _T_133 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_8 = _T_131 | _T_134; // @[dec_gpr_ctl.scala 55:88] + wire _T_136 = io_waddr0 == 5'h9; // @[dec_gpr_ctl.scala 52:52] + wire w0v_9 = io_wen0 & _T_136; // @[dec_gpr_ctl.scala 52:40] + wire _T_138 = io_waddr1 == 5'h9; // @[dec_gpr_ctl.scala 53:52] + wire w1v_9 = io_wen1 & _T_138; // @[dec_gpr_ctl.scala 53:40] + wire _T_140 = io_waddr2 == 5'h9; // @[dec_gpr_ctl.scala 54:52] + wire w2v_9 = io_wen2 & _T_140; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_143 = w0v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_144 = _T_143 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_146 = w1v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_147 = _T_146 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_148 = _T_144 | _T_147; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_150 = w2v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_151 = _T_150 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_9 = _T_148 | _T_151; // @[dec_gpr_ctl.scala 55:88] + wire _T_153 = io_waddr0 == 5'ha; // @[dec_gpr_ctl.scala 52:52] + wire w0v_10 = io_wen0 & _T_153; // @[dec_gpr_ctl.scala 52:40] + wire _T_155 = io_waddr1 == 5'ha; // @[dec_gpr_ctl.scala 53:52] + wire w1v_10 = io_wen1 & _T_155; // @[dec_gpr_ctl.scala 53:40] + wire _T_157 = io_waddr2 == 5'ha; // @[dec_gpr_ctl.scala 54:52] + wire w2v_10 = io_wen2 & _T_157; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_160 = w0v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_161 = _T_160 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_163 = w1v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_164 = _T_163 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_165 = _T_161 | _T_164; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_167 = w2v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_168 = _T_167 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_10 = _T_165 | _T_168; // @[dec_gpr_ctl.scala 55:88] + wire _T_170 = io_waddr0 == 5'hb; // @[dec_gpr_ctl.scala 52:52] + wire w0v_11 = io_wen0 & _T_170; // @[dec_gpr_ctl.scala 52:40] + wire _T_172 = io_waddr1 == 5'hb; // @[dec_gpr_ctl.scala 53:52] + wire w1v_11 = io_wen1 & _T_172; // @[dec_gpr_ctl.scala 53:40] + wire _T_174 = io_waddr2 == 5'hb; // @[dec_gpr_ctl.scala 54:52] + wire w2v_11 = io_wen2 & _T_174; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_177 = w0v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_178 = _T_177 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_180 = w1v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_181 = _T_180 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_182 = _T_178 | _T_181; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_184 = w2v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_185 = _T_184 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_11 = _T_182 | _T_185; // @[dec_gpr_ctl.scala 55:88] + wire _T_187 = io_waddr0 == 5'hc; // @[dec_gpr_ctl.scala 52:52] + wire w0v_12 = io_wen0 & _T_187; // @[dec_gpr_ctl.scala 52:40] + wire _T_189 = io_waddr1 == 5'hc; // @[dec_gpr_ctl.scala 53:52] + wire w1v_12 = io_wen1 & _T_189; // @[dec_gpr_ctl.scala 53:40] + wire _T_191 = io_waddr2 == 5'hc; // @[dec_gpr_ctl.scala 54:52] + wire w2v_12 = io_wen2 & _T_191; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_194 = w0v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_195 = _T_194 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_197 = w1v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_198 = _T_197 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_199 = _T_195 | _T_198; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_201 = w2v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_202 = _T_201 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_12 = _T_199 | _T_202; // @[dec_gpr_ctl.scala 55:88] + wire _T_204 = io_waddr0 == 5'hd; // @[dec_gpr_ctl.scala 52:52] + wire w0v_13 = io_wen0 & _T_204; // @[dec_gpr_ctl.scala 52:40] + wire _T_206 = io_waddr1 == 5'hd; // @[dec_gpr_ctl.scala 53:52] + wire w1v_13 = io_wen1 & _T_206; // @[dec_gpr_ctl.scala 53:40] + wire _T_208 = io_waddr2 == 5'hd; // @[dec_gpr_ctl.scala 54:52] + wire w2v_13 = io_wen2 & _T_208; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_211 = w0v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_212 = _T_211 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_214 = w1v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_215 = _T_214 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_216 = _T_212 | _T_215; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_218 = w2v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_219 = _T_218 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_13 = _T_216 | _T_219; // @[dec_gpr_ctl.scala 55:88] + wire _T_221 = io_waddr0 == 5'he; // @[dec_gpr_ctl.scala 52:52] + wire w0v_14 = io_wen0 & _T_221; // @[dec_gpr_ctl.scala 52:40] + wire _T_223 = io_waddr1 == 5'he; // @[dec_gpr_ctl.scala 53:52] + wire w1v_14 = io_wen1 & _T_223; // @[dec_gpr_ctl.scala 53:40] + wire _T_225 = io_waddr2 == 5'he; // @[dec_gpr_ctl.scala 54:52] + wire w2v_14 = io_wen2 & _T_225; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_228 = w0v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_229 = _T_228 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_231 = w1v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_232 = _T_231 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_233 = _T_229 | _T_232; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_235 = w2v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_236 = _T_235 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_14 = _T_233 | _T_236; // @[dec_gpr_ctl.scala 55:88] + wire _T_238 = io_waddr0 == 5'hf; // @[dec_gpr_ctl.scala 52:52] + wire w0v_15 = io_wen0 & _T_238; // @[dec_gpr_ctl.scala 52:40] + wire _T_240 = io_waddr1 == 5'hf; // @[dec_gpr_ctl.scala 53:52] + wire w1v_15 = io_wen1 & _T_240; // @[dec_gpr_ctl.scala 53:40] + wire _T_242 = io_waddr2 == 5'hf; // @[dec_gpr_ctl.scala 54:52] + wire w2v_15 = io_wen2 & _T_242; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_245 = w0v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_246 = _T_245 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_248 = w1v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_249 = _T_248 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_250 = _T_246 | _T_249; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_252 = w2v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_253 = _T_252 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_15 = _T_250 | _T_253; // @[dec_gpr_ctl.scala 55:88] + wire _T_255 = io_waddr0 == 5'h10; // @[dec_gpr_ctl.scala 52:52] + wire w0v_16 = io_wen0 & _T_255; // @[dec_gpr_ctl.scala 52:40] + wire _T_257 = io_waddr1 == 5'h10; // @[dec_gpr_ctl.scala 53:52] + wire w1v_16 = io_wen1 & _T_257; // @[dec_gpr_ctl.scala 53:40] + wire _T_259 = io_waddr2 == 5'h10; // @[dec_gpr_ctl.scala 54:52] + wire w2v_16 = io_wen2 & _T_259; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_262 = w0v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_263 = _T_262 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_265 = w1v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_266 = _T_265 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_267 = _T_263 | _T_266; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_269 = w2v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_270 = _T_269 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_16 = _T_267 | _T_270; // @[dec_gpr_ctl.scala 55:88] + wire _T_272 = io_waddr0 == 5'h11; // @[dec_gpr_ctl.scala 52:52] + wire w0v_17 = io_wen0 & _T_272; // @[dec_gpr_ctl.scala 52:40] + wire _T_274 = io_waddr1 == 5'h11; // @[dec_gpr_ctl.scala 53:52] + wire w1v_17 = io_wen1 & _T_274; // @[dec_gpr_ctl.scala 53:40] + wire _T_276 = io_waddr2 == 5'h11; // @[dec_gpr_ctl.scala 54:52] + wire w2v_17 = io_wen2 & _T_276; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_279 = w0v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_280 = _T_279 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_282 = w1v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_283 = _T_282 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_284 = _T_280 | _T_283; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_286 = w2v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_287 = _T_286 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_17 = _T_284 | _T_287; // @[dec_gpr_ctl.scala 55:88] + wire _T_289 = io_waddr0 == 5'h12; // @[dec_gpr_ctl.scala 52:52] + wire w0v_18 = io_wen0 & _T_289; // @[dec_gpr_ctl.scala 52:40] + wire _T_291 = io_waddr1 == 5'h12; // @[dec_gpr_ctl.scala 53:52] + wire w1v_18 = io_wen1 & _T_291; // @[dec_gpr_ctl.scala 53:40] + wire _T_293 = io_waddr2 == 5'h12; // @[dec_gpr_ctl.scala 54:52] + wire w2v_18 = io_wen2 & _T_293; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_296 = w0v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_297 = _T_296 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_299 = w1v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_300 = _T_299 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_301 = _T_297 | _T_300; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_303 = w2v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_304 = _T_303 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_18 = _T_301 | _T_304; // @[dec_gpr_ctl.scala 55:88] + wire _T_306 = io_waddr0 == 5'h13; // @[dec_gpr_ctl.scala 52:52] + wire w0v_19 = io_wen0 & _T_306; // @[dec_gpr_ctl.scala 52:40] + wire _T_308 = io_waddr1 == 5'h13; // @[dec_gpr_ctl.scala 53:52] + wire w1v_19 = io_wen1 & _T_308; // @[dec_gpr_ctl.scala 53:40] + wire _T_310 = io_waddr2 == 5'h13; // @[dec_gpr_ctl.scala 54:52] + wire w2v_19 = io_wen2 & _T_310; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_313 = w0v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_314 = _T_313 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_316 = w1v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_317 = _T_316 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_318 = _T_314 | _T_317; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_320 = w2v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_321 = _T_320 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_19 = _T_318 | _T_321; // @[dec_gpr_ctl.scala 55:88] + wire _T_323 = io_waddr0 == 5'h14; // @[dec_gpr_ctl.scala 52:52] + wire w0v_20 = io_wen0 & _T_323; // @[dec_gpr_ctl.scala 52:40] + wire _T_325 = io_waddr1 == 5'h14; // @[dec_gpr_ctl.scala 53:52] + wire w1v_20 = io_wen1 & _T_325; // @[dec_gpr_ctl.scala 53:40] + wire _T_327 = io_waddr2 == 5'h14; // @[dec_gpr_ctl.scala 54:52] + wire w2v_20 = io_wen2 & _T_327; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_330 = w0v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_331 = _T_330 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_333 = w1v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_334 = _T_333 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_335 = _T_331 | _T_334; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_337 = w2v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_338 = _T_337 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_20 = _T_335 | _T_338; // @[dec_gpr_ctl.scala 55:88] + wire _T_340 = io_waddr0 == 5'h15; // @[dec_gpr_ctl.scala 52:52] + wire w0v_21 = io_wen0 & _T_340; // @[dec_gpr_ctl.scala 52:40] + wire _T_342 = io_waddr1 == 5'h15; // @[dec_gpr_ctl.scala 53:52] + wire w1v_21 = io_wen1 & _T_342; // @[dec_gpr_ctl.scala 53:40] + wire _T_344 = io_waddr2 == 5'h15; // @[dec_gpr_ctl.scala 54:52] + wire w2v_21 = io_wen2 & _T_344; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_347 = w0v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_348 = _T_347 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_350 = w1v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_351 = _T_350 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_352 = _T_348 | _T_351; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_354 = w2v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_355 = _T_354 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_21 = _T_352 | _T_355; // @[dec_gpr_ctl.scala 55:88] + wire _T_357 = io_waddr0 == 5'h16; // @[dec_gpr_ctl.scala 52:52] + wire w0v_22 = io_wen0 & _T_357; // @[dec_gpr_ctl.scala 52:40] + wire _T_359 = io_waddr1 == 5'h16; // @[dec_gpr_ctl.scala 53:52] + wire w1v_22 = io_wen1 & _T_359; // @[dec_gpr_ctl.scala 53:40] + wire _T_361 = io_waddr2 == 5'h16; // @[dec_gpr_ctl.scala 54:52] + wire w2v_22 = io_wen2 & _T_361; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_364 = w0v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_365 = _T_364 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_367 = w1v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_368 = _T_367 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_369 = _T_365 | _T_368; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_371 = w2v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_372 = _T_371 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_22 = _T_369 | _T_372; // @[dec_gpr_ctl.scala 55:88] + wire _T_374 = io_waddr0 == 5'h17; // @[dec_gpr_ctl.scala 52:52] + wire w0v_23 = io_wen0 & _T_374; // @[dec_gpr_ctl.scala 52:40] + wire _T_376 = io_waddr1 == 5'h17; // @[dec_gpr_ctl.scala 53:52] + wire w1v_23 = io_wen1 & _T_376; // @[dec_gpr_ctl.scala 53:40] + wire _T_378 = io_waddr2 == 5'h17; // @[dec_gpr_ctl.scala 54:52] + wire w2v_23 = io_wen2 & _T_378; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_381 = w0v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_382 = _T_381 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_384 = w1v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_385 = _T_384 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_386 = _T_382 | _T_385; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_388 = w2v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_389 = _T_388 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_23 = _T_386 | _T_389; // @[dec_gpr_ctl.scala 55:88] + wire _T_391 = io_waddr0 == 5'h18; // @[dec_gpr_ctl.scala 52:52] + wire w0v_24 = io_wen0 & _T_391; // @[dec_gpr_ctl.scala 52:40] + wire _T_393 = io_waddr1 == 5'h18; // @[dec_gpr_ctl.scala 53:52] + wire w1v_24 = io_wen1 & _T_393; // @[dec_gpr_ctl.scala 53:40] + wire _T_395 = io_waddr2 == 5'h18; // @[dec_gpr_ctl.scala 54:52] + wire w2v_24 = io_wen2 & _T_395; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_398 = w0v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_399 = _T_398 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_401 = w1v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_402 = _T_401 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_403 = _T_399 | _T_402; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_405 = w2v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_406 = _T_405 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_24 = _T_403 | _T_406; // @[dec_gpr_ctl.scala 55:88] + wire _T_408 = io_waddr0 == 5'h19; // @[dec_gpr_ctl.scala 52:52] + wire w0v_25 = io_wen0 & _T_408; // @[dec_gpr_ctl.scala 52:40] + wire _T_410 = io_waddr1 == 5'h19; // @[dec_gpr_ctl.scala 53:52] + wire w1v_25 = io_wen1 & _T_410; // @[dec_gpr_ctl.scala 53:40] + wire _T_412 = io_waddr2 == 5'h19; // @[dec_gpr_ctl.scala 54:52] + wire w2v_25 = io_wen2 & _T_412; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_415 = w0v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_416 = _T_415 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_418 = w1v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_419 = _T_418 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_420 = _T_416 | _T_419; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_422 = w2v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_423 = _T_422 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_25 = _T_420 | _T_423; // @[dec_gpr_ctl.scala 55:88] + wire _T_425 = io_waddr0 == 5'h1a; // @[dec_gpr_ctl.scala 52:52] + wire w0v_26 = io_wen0 & _T_425; // @[dec_gpr_ctl.scala 52:40] + wire _T_427 = io_waddr1 == 5'h1a; // @[dec_gpr_ctl.scala 53:52] + wire w1v_26 = io_wen1 & _T_427; // @[dec_gpr_ctl.scala 53:40] + wire _T_429 = io_waddr2 == 5'h1a; // @[dec_gpr_ctl.scala 54:52] + wire w2v_26 = io_wen2 & _T_429; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_432 = w0v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_433 = _T_432 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_435 = w1v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_436 = _T_435 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_437 = _T_433 | _T_436; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_439 = w2v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_440 = _T_439 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_26 = _T_437 | _T_440; // @[dec_gpr_ctl.scala 55:88] + wire _T_442 = io_waddr0 == 5'h1b; // @[dec_gpr_ctl.scala 52:52] + wire w0v_27 = io_wen0 & _T_442; // @[dec_gpr_ctl.scala 52:40] + wire _T_444 = io_waddr1 == 5'h1b; // @[dec_gpr_ctl.scala 53:52] + wire w1v_27 = io_wen1 & _T_444; // @[dec_gpr_ctl.scala 53:40] + wire _T_446 = io_waddr2 == 5'h1b; // @[dec_gpr_ctl.scala 54:52] + wire w2v_27 = io_wen2 & _T_446; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_449 = w0v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_450 = _T_449 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_452 = w1v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_453 = _T_452 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_454 = _T_450 | _T_453; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_456 = w2v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_457 = _T_456 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_27 = _T_454 | _T_457; // @[dec_gpr_ctl.scala 55:88] + wire _T_459 = io_waddr0 == 5'h1c; // @[dec_gpr_ctl.scala 52:52] + wire w0v_28 = io_wen0 & _T_459; // @[dec_gpr_ctl.scala 52:40] + wire _T_461 = io_waddr1 == 5'h1c; // @[dec_gpr_ctl.scala 53:52] + wire w1v_28 = io_wen1 & _T_461; // @[dec_gpr_ctl.scala 53:40] + wire _T_463 = io_waddr2 == 5'h1c; // @[dec_gpr_ctl.scala 54:52] + wire w2v_28 = io_wen2 & _T_463; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_466 = w0v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_467 = _T_466 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_469 = w1v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_470 = _T_469 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_471 = _T_467 | _T_470; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_473 = w2v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_474 = _T_473 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_28 = _T_471 | _T_474; // @[dec_gpr_ctl.scala 55:88] + wire _T_476 = io_waddr0 == 5'h1d; // @[dec_gpr_ctl.scala 52:52] + wire w0v_29 = io_wen0 & _T_476; // @[dec_gpr_ctl.scala 52:40] + wire _T_478 = io_waddr1 == 5'h1d; // @[dec_gpr_ctl.scala 53:52] + wire w1v_29 = io_wen1 & _T_478; // @[dec_gpr_ctl.scala 53:40] + wire _T_480 = io_waddr2 == 5'h1d; // @[dec_gpr_ctl.scala 54:52] + wire w2v_29 = io_wen2 & _T_480; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_483 = w0v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_484 = _T_483 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_486 = w1v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_487 = _T_486 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_488 = _T_484 | _T_487; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_490 = w2v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_491 = _T_490 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_29 = _T_488 | _T_491; // @[dec_gpr_ctl.scala 55:88] + wire _T_493 = io_waddr0 == 5'h1e; // @[dec_gpr_ctl.scala 52:52] + wire w0v_30 = io_wen0 & _T_493; // @[dec_gpr_ctl.scala 52:40] + wire _T_495 = io_waddr1 == 5'h1e; // @[dec_gpr_ctl.scala 53:52] + wire w1v_30 = io_wen1 & _T_495; // @[dec_gpr_ctl.scala 53:40] + wire _T_497 = io_waddr2 == 5'h1e; // @[dec_gpr_ctl.scala 54:52] + wire w2v_30 = io_wen2 & _T_497; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_500 = w0v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_501 = _T_500 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_503 = w1v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_504 = _T_503 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_505 = _T_501 | _T_504; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_507 = w2v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_508 = _T_507 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_30 = _T_505 | _T_508; // @[dec_gpr_ctl.scala 55:88] + wire _T_510 = io_waddr0 == 5'h1f; // @[dec_gpr_ctl.scala 52:52] + wire w0v_31 = io_wen0 & _T_510; // @[dec_gpr_ctl.scala 52:40] + wire _T_512 = io_waddr1 == 5'h1f; // @[dec_gpr_ctl.scala 53:52] + wire w1v_31 = io_wen1 & _T_512; // @[dec_gpr_ctl.scala 53:40] + wire _T_514 = io_waddr2 == 5'h1f; // @[dec_gpr_ctl.scala 54:52] + wire w2v_31 = io_wen2 & _T_514; // @[dec_gpr_ctl.scala 54:40] + wire [31:0] _T_517 = w0v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_518 = _T_517 & io_wd0; // @[dec_gpr_ctl.scala 55:49] + wire [31:0] _T_520 = w1v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_521 = _T_520 & io_wd1; // @[dec_gpr_ctl.scala 55:78] + wire [31:0] _T_522 = _T_518 | _T_521; // @[dec_gpr_ctl.scala 55:59] + wire [31:0] _T_524 = w2v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_525 = _T_524 & io_wd2; // @[dec_gpr_ctl.scala 55:107] + wire [31:0] gpr_in_31 = _T_522 | _T_525; // @[dec_gpr_ctl.scala 55:88] + wire [9:0] _T_535 = {w0v_9,w0v_8,w0v_7,w0v_6,w0v_5,w0v_4,w0v_3,w0v_2,w0v_1,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_544 = {w0v_18,w0v_17,w0v_16,w0v_15,w0v_14,w0v_13,w0v_12,w0v_11,w0v_10,_T_535}; // @[Cat.scala 29:58] + wire [27:0] _T_553 = {w0v_27,w0v_26,w0v_25,w0v_24,w0v_23,w0v_22,w0v_21,w0v_20,w0v_19,_T_544}; // @[Cat.scala 29:58] + wire [31:0] _T_557 = {w0v_31,w0v_30,w0v_29,w0v_28,_T_553}; // @[Cat.scala 29:58] + wire [9:0] _T_566 = {w1v_9,w1v_8,w1v_7,w1v_6,w1v_5,w1v_4,w1v_3,w1v_2,w1v_1,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_575 = {w1v_18,w1v_17,w1v_16,w1v_15,w1v_14,w1v_13,w1v_12,w1v_11,w1v_10,_T_566}; // @[Cat.scala 29:58] + wire [27:0] _T_584 = {w1v_27,w1v_26,w1v_25,w1v_24,w1v_23,w1v_22,w1v_21,w1v_20,w1v_19,_T_575}; // @[Cat.scala 29:58] + wire [31:0] _T_588 = {w1v_31,w1v_30,w1v_29,w1v_28,_T_584}; // @[Cat.scala 29:58] + wire [31:0] _T_589 = _T_557 | _T_588; // @[dec_gpr_ctl.scala 57:57] + wire [9:0] _T_598 = {w2v_9,w2v_8,w2v_7,w2v_6,w2v_5,w2v_4,w2v_3,w2v_2,w2v_1,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_607 = {w2v_18,w2v_17,w2v_16,w2v_15,w2v_14,w2v_13,w2v_12,w2v_11,w2v_10,_T_598}; // @[Cat.scala 29:58] + wire [27:0] _T_616 = {w2v_27,w2v_26,w2v_25,w2v_24,w2v_23,w2v_22,w2v_21,w2v_20,w2v_19,_T_607}; // @[Cat.scala 29:58] + wire [31:0] _T_620 = {w2v_31,w2v_30,w2v_29,w2v_28,_T_616}; // @[Cat.scala 29:58] + wire [31:0] gpr_wr_en = _T_589 | _T_620; // @[dec_gpr_ctl.scala 57:95] + reg [31:0] gpr_out_1; // @[Reg.scala 27:20] + reg [31:0] gpr_out_2; // @[Reg.scala 27:20] + reg [31:0] gpr_out_3; // @[Reg.scala 27:20] + reg [31:0] gpr_out_4; // @[Reg.scala 27:20] + reg [31:0] gpr_out_5; // @[Reg.scala 27:20] + reg [31:0] gpr_out_6; // @[Reg.scala 27:20] + reg [31:0] gpr_out_7; // @[Reg.scala 27:20] + reg [31:0] gpr_out_8; // @[Reg.scala 27:20] + reg [31:0] gpr_out_9; // @[Reg.scala 27:20] + reg [31:0] gpr_out_10; // @[Reg.scala 27:20] + reg [31:0] gpr_out_11; // @[Reg.scala 27:20] + reg [31:0] gpr_out_12; // @[Reg.scala 27:20] + reg [31:0] gpr_out_13; // @[Reg.scala 27:20] + reg [31:0] gpr_out_14; // @[Reg.scala 27:20] + reg [31:0] gpr_out_15; // @[Reg.scala 27:20] + reg [31:0] gpr_out_16; // @[Reg.scala 27:20] + reg [31:0] gpr_out_17; // @[Reg.scala 27:20] + reg [31:0] gpr_out_18; // @[Reg.scala 27:20] + reg [31:0] gpr_out_19; // @[Reg.scala 27:20] + reg [31:0] gpr_out_20; // @[Reg.scala 27:20] + reg [31:0] gpr_out_21; // @[Reg.scala 27:20] + reg [31:0] gpr_out_22; // @[Reg.scala 27:20] + reg [31:0] gpr_out_23; // @[Reg.scala 27:20] + reg [31:0] gpr_out_24; // @[Reg.scala 27:20] + reg [31:0] gpr_out_25; // @[Reg.scala 27:20] + reg [31:0] gpr_out_26; // @[Reg.scala 27:20] + reg [31:0] gpr_out_27; // @[Reg.scala 27:20] + reg [31:0] gpr_out_28; // @[Reg.scala 27:20] + reg [31:0] gpr_out_29; // @[Reg.scala 27:20] + reg [31:0] gpr_out_30; // @[Reg.scala 27:20] + reg [31:0] gpr_out_31; // @[Reg.scala 27:20] + wire _T_684 = io_raddr0 == 5'h1; // @[dec_gpr_ctl.scala 64:72] + wire _T_686 = io_raddr0 == 5'h2; // @[dec_gpr_ctl.scala 64:72] + wire _T_688 = io_raddr0 == 5'h3; // @[dec_gpr_ctl.scala 64:72] + wire _T_690 = io_raddr0 == 5'h4; // @[dec_gpr_ctl.scala 64:72] + wire _T_692 = io_raddr0 == 5'h5; // @[dec_gpr_ctl.scala 64:72] + wire _T_694 = io_raddr0 == 5'h6; // @[dec_gpr_ctl.scala 64:72] + wire _T_696 = io_raddr0 == 5'h7; // @[dec_gpr_ctl.scala 64:72] + wire _T_698 = io_raddr0 == 5'h8; // @[dec_gpr_ctl.scala 64:72] + wire _T_700 = io_raddr0 == 5'h9; // @[dec_gpr_ctl.scala 64:72] + wire _T_702 = io_raddr0 == 5'ha; // @[dec_gpr_ctl.scala 64:72] + wire _T_704 = io_raddr0 == 5'hb; // @[dec_gpr_ctl.scala 64:72] + wire _T_706 = io_raddr0 == 5'hc; // @[dec_gpr_ctl.scala 64:72] + wire _T_708 = io_raddr0 == 5'hd; // @[dec_gpr_ctl.scala 64:72] + wire _T_710 = io_raddr0 == 5'he; // @[dec_gpr_ctl.scala 64:72] + wire _T_712 = io_raddr0 == 5'hf; // @[dec_gpr_ctl.scala 64:72] + wire _T_714 = io_raddr0 == 5'h10; // @[dec_gpr_ctl.scala 64:72] + wire _T_716 = io_raddr0 == 5'h11; // @[dec_gpr_ctl.scala 64:72] + wire _T_718 = io_raddr0 == 5'h12; // @[dec_gpr_ctl.scala 64:72] + wire _T_720 = io_raddr0 == 5'h13; // @[dec_gpr_ctl.scala 64:72] + wire _T_722 = io_raddr0 == 5'h14; // @[dec_gpr_ctl.scala 64:72] + wire _T_724 = io_raddr0 == 5'h15; // @[dec_gpr_ctl.scala 64:72] + wire _T_726 = io_raddr0 == 5'h16; // @[dec_gpr_ctl.scala 64:72] + wire _T_728 = io_raddr0 == 5'h17; // @[dec_gpr_ctl.scala 64:72] + wire _T_730 = io_raddr0 == 5'h18; // @[dec_gpr_ctl.scala 64:72] + wire _T_732 = io_raddr0 == 5'h19; // @[dec_gpr_ctl.scala 64:72] + wire _T_734 = io_raddr0 == 5'h1a; // @[dec_gpr_ctl.scala 64:72] + wire _T_736 = io_raddr0 == 5'h1b; // @[dec_gpr_ctl.scala 64:72] + wire _T_738 = io_raddr0 == 5'h1c; // @[dec_gpr_ctl.scala 64:72] + wire _T_740 = io_raddr0 == 5'h1d; // @[dec_gpr_ctl.scala 64:72] + wire _T_742 = io_raddr0 == 5'h1e; // @[dec_gpr_ctl.scala 64:72] + wire _T_744 = io_raddr0 == 5'h1f; // @[dec_gpr_ctl.scala 64:72] + wire [31:0] _T_746 = _T_684 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_747 = _T_686 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_748 = _T_688 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_749 = _T_690 ? gpr_out_4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_750 = _T_692 ? gpr_out_5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_751 = _T_694 ? gpr_out_6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_752 = _T_696 ? gpr_out_7 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_753 = _T_698 ? gpr_out_8 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_754 = _T_700 ? gpr_out_9 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_755 = _T_702 ? gpr_out_10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_756 = _T_704 ? gpr_out_11 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_757 = _T_706 ? gpr_out_12 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_758 = _T_708 ? gpr_out_13 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_759 = _T_710 ? gpr_out_14 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_760 = _T_712 ? gpr_out_15 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_761 = _T_714 ? gpr_out_16 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_762 = _T_716 ? gpr_out_17 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_763 = _T_718 ? gpr_out_18 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_764 = _T_720 ? gpr_out_19 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_765 = _T_722 ? gpr_out_20 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_766 = _T_724 ? gpr_out_21 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_767 = _T_726 ? gpr_out_22 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_768 = _T_728 ? gpr_out_23 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_769 = _T_730 ? gpr_out_24 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_770 = _T_732 ? gpr_out_25 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_771 = _T_734 ? gpr_out_26 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_772 = _T_736 ? gpr_out_27 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_773 = _T_738 ? gpr_out_28 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_774 = _T_740 ? gpr_out_29 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_775 = _T_742 ? gpr_out_30 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_776 = _T_744 ? gpr_out_31 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_777 = _T_746 | _T_747; // @[Mux.scala 27:72] + wire [31:0] _T_778 = _T_777 | _T_748; // @[Mux.scala 27:72] + wire [31:0] _T_779 = _T_778 | _T_749; // @[Mux.scala 27:72] + wire [31:0] _T_780 = _T_779 | _T_750; // @[Mux.scala 27:72] + wire [31:0] _T_781 = _T_780 | _T_751; // @[Mux.scala 27:72] + wire [31:0] _T_782 = _T_781 | _T_752; // @[Mux.scala 27:72] + wire [31:0] _T_783 = _T_782 | _T_753; // @[Mux.scala 27:72] + wire [31:0] _T_784 = _T_783 | _T_754; // @[Mux.scala 27:72] + wire [31:0] _T_785 = _T_784 | _T_755; // @[Mux.scala 27:72] + wire [31:0] _T_786 = _T_785 | _T_756; // @[Mux.scala 27:72] + wire [31:0] _T_787 = _T_786 | _T_757; // @[Mux.scala 27:72] + wire [31:0] _T_788 = _T_787 | _T_758; // @[Mux.scala 27:72] + wire [31:0] _T_789 = _T_788 | _T_759; // @[Mux.scala 27:72] + wire [31:0] _T_790 = _T_789 | _T_760; // @[Mux.scala 27:72] + wire [31:0] _T_791 = _T_790 | _T_761; // @[Mux.scala 27:72] + wire [31:0] _T_792 = _T_791 | _T_762; // @[Mux.scala 27:72] + wire [31:0] _T_793 = _T_792 | _T_763; // @[Mux.scala 27:72] + wire [31:0] _T_794 = _T_793 | _T_764; // @[Mux.scala 27:72] + wire [31:0] _T_795 = _T_794 | _T_765; // @[Mux.scala 27:72] + wire [31:0] _T_796 = _T_795 | _T_766; // @[Mux.scala 27:72] + wire [31:0] _T_797 = _T_796 | _T_767; // @[Mux.scala 27:72] + wire [31:0] _T_798 = _T_797 | _T_768; // @[Mux.scala 27:72] + wire [31:0] _T_799 = _T_798 | _T_769; // @[Mux.scala 27:72] + wire [31:0] _T_800 = _T_799 | _T_770; // @[Mux.scala 27:72] + wire [31:0] _T_801 = _T_800 | _T_771; // @[Mux.scala 27:72] + wire [31:0] _T_802 = _T_801 | _T_772; // @[Mux.scala 27:72] + wire [31:0] _T_803 = _T_802 | _T_773; // @[Mux.scala 27:72] + wire [31:0] _T_804 = _T_803 | _T_774; // @[Mux.scala 27:72] + wire [31:0] _T_805 = _T_804 | _T_775; // @[Mux.scala 27:72] + wire _T_808 = io_raddr1 == 5'h1; // @[dec_gpr_ctl.scala 65:72] + wire _T_810 = io_raddr1 == 5'h2; // @[dec_gpr_ctl.scala 65:72] + wire _T_812 = io_raddr1 == 5'h3; // @[dec_gpr_ctl.scala 65:72] + wire _T_814 = io_raddr1 == 5'h4; // @[dec_gpr_ctl.scala 65:72] + wire _T_816 = io_raddr1 == 5'h5; // @[dec_gpr_ctl.scala 65:72] + wire _T_818 = io_raddr1 == 5'h6; // @[dec_gpr_ctl.scala 65:72] + wire _T_820 = io_raddr1 == 5'h7; // @[dec_gpr_ctl.scala 65:72] + wire _T_822 = io_raddr1 == 5'h8; // @[dec_gpr_ctl.scala 65:72] + wire _T_824 = io_raddr1 == 5'h9; // @[dec_gpr_ctl.scala 65:72] + wire _T_826 = io_raddr1 == 5'ha; // @[dec_gpr_ctl.scala 65:72] + wire _T_828 = io_raddr1 == 5'hb; // @[dec_gpr_ctl.scala 65:72] + wire _T_830 = io_raddr1 == 5'hc; // @[dec_gpr_ctl.scala 65:72] + wire _T_832 = io_raddr1 == 5'hd; // @[dec_gpr_ctl.scala 65:72] + wire _T_834 = io_raddr1 == 5'he; // @[dec_gpr_ctl.scala 65:72] + wire _T_836 = io_raddr1 == 5'hf; // @[dec_gpr_ctl.scala 65:72] + wire _T_838 = io_raddr1 == 5'h10; // @[dec_gpr_ctl.scala 65:72] + wire _T_840 = io_raddr1 == 5'h11; // @[dec_gpr_ctl.scala 65:72] + wire _T_842 = io_raddr1 == 5'h12; // @[dec_gpr_ctl.scala 65:72] + wire _T_844 = io_raddr1 == 5'h13; // @[dec_gpr_ctl.scala 65:72] + wire _T_846 = io_raddr1 == 5'h14; // @[dec_gpr_ctl.scala 65:72] + wire _T_848 = io_raddr1 == 5'h15; // @[dec_gpr_ctl.scala 65:72] + wire _T_850 = io_raddr1 == 5'h16; // @[dec_gpr_ctl.scala 65:72] + wire _T_852 = io_raddr1 == 5'h17; // @[dec_gpr_ctl.scala 65:72] + wire _T_854 = io_raddr1 == 5'h18; // @[dec_gpr_ctl.scala 65:72] + wire _T_856 = io_raddr1 == 5'h19; // @[dec_gpr_ctl.scala 65:72] + wire _T_858 = io_raddr1 == 5'h1a; // @[dec_gpr_ctl.scala 65:72] + wire _T_860 = io_raddr1 == 5'h1b; // @[dec_gpr_ctl.scala 65:72] + wire _T_862 = io_raddr1 == 5'h1c; // @[dec_gpr_ctl.scala 65:72] + wire _T_864 = io_raddr1 == 5'h1d; // @[dec_gpr_ctl.scala 65:72] + wire _T_866 = io_raddr1 == 5'h1e; // @[dec_gpr_ctl.scala 65:72] + wire _T_868 = io_raddr1 == 5'h1f; // @[dec_gpr_ctl.scala 65:72] + wire [31:0] _T_870 = _T_808 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_871 = _T_810 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_872 = _T_812 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_873 = _T_814 ? gpr_out_4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_874 = _T_816 ? gpr_out_5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_875 = _T_818 ? gpr_out_6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_876 = _T_820 ? gpr_out_7 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_877 = _T_822 ? gpr_out_8 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_878 = _T_824 ? gpr_out_9 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_879 = _T_826 ? gpr_out_10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_880 = _T_828 ? gpr_out_11 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_881 = _T_830 ? gpr_out_12 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_882 = _T_832 ? gpr_out_13 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_883 = _T_834 ? gpr_out_14 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_884 = _T_836 ? gpr_out_15 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_885 = _T_838 ? gpr_out_16 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_886 = _T_840 ? gpr_out_17 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_887 = _T_842 ? gpr_out_18 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_888 = _T_844 ? gpr_out_19 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_889 = _T_846 ? gpr_out_20 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_890 = _T_848 ? gpr_out_21 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_891 = _T_850 ? gpr_out_22 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_892 = _T_852 ? gpr_out_23 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_893 = _T_854 ? gpr_out_24 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_894 = _T_856 ? gpr_out_25 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_895 = _T_858 ? gpr_out_26 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_896 = _T_860 ? gpr_out_27 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_897 = _T_862 ? gpr_out_28 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_898 = _T_864 ? gpr_out_29 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_899 = _T_866 ? gpr_out_30 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_900 = _T_868 ? gpr_out_31 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_901 = _T_870 | _T_871; // @[Mux.scala 27:72] + wire [31:0] _T_902 = _T_901 | _T_872; // @[Mux.scala 27:72] + wire [31:0] _T_903 = _T_902 | _T_873; // @[Mux.scala 27:72] + wire [31:0] _T_904 = _T_903 | _T_874; // @[Mux.scala 27:72] + wire [31:0] _T_905 = _T_904 | _T_875; // @[Mux.scala 27:72] + wire [31:0] _T_906 = _T_905 | _T_876; // @[Mux.scala 27:72] + wire [31:0] _T_907 = _T_906 | _T_877; // @[Mux.scala 27:72] + wire [31:0] _T_908 = _T_907 | _T_878; // @[Mux.scala 27:72] + wire [31:0] _T_909 = _T_908 | _T_879; // @[Mux.scala 27:72] + wire [31:0] _T_910 = _T_909 | _T_880; // @[Mux.scala 27:72] + wire [31:0] _T_911 = _T_910 | _T_881; // @[Mux.scala 27:72] + wire [31:0] _T_912 = _T_911 | _T_882; // @[Mux.scala 27:72] + wire [31:0] _T_913 = _T_912 | _T_883; // @[Mux.scala 27:72] + wire [31:0] _T_914 = _T_913 | _T_884; // @[Mux.scala 27:72] + wire [31:0] _T_915 = _T_914 | _T_885; // @[Mux.scala 27:72] + wire [31:0] _T_916 = _T_915 | _T_886; // @[Mux.scala 27:72] + wire [31:0] _T_917 = _T_916 | _T_887; // @[Mux.scala 27:72] + wire [31:0] _T_918 = _T_917 | _T_888; // @[Mux.scala 27:72] + wire [31:0] _T_919 = _T_918 | _T_889; // @[Mux.scala 27:72] + wire [31:0] _T_920 = _T_919 | _T_890; // @[Mux.scala 27:72] + wire [31:0] _T_921 = _T_920 | _T_891; // @[Mux.scala 27:72] + wire [31:0] _T_922 = _T_921 | _T_892; // @[Mux.scala 27:72] + wire [31:0] _T_923 = _T_922 | _T_893; // @[Mux.scala 27:72] + wire [31:0] _T_924 = _T_923 | _T_894; // @[Mux.scala 27:72] + wire [31:0] _T_925 = _T_924 | _T_895; // @[Mux.scala 27:72] + wire [31:0] _T_926 = _T_925 | _T_896; // @[Mux.scala 27:72] + wire [31:0] _T_927 = _T_926 | _T_897; // @[Mux.scala 27:72] + wire [31:0] _T_928 = _T_927 | _T_898; // @[Mux.scala 27:72] + wire [31:0] _T_929 = _T_928 | _T_899; // @[Mux.scala 27:72] + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en) + ); + rvclkhdr rvclkhdr_10 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en) + ); + rvclkhdr rvclkhdr_11 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en) + ); + rvclkhdr rvclkhdr_12 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_12_io_clk), + .io_en(rvclkhdr_12_io_en) + ); + rvclkhdr rvclkhdr_13 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_13_io_clk), + .io_en(rvclkhdr_13_io_en) + ); + rvclkhdr rvclkhdr_14 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_14_io_clk), + .io_en(rvclkhdr_14_io_en) + ); + rvclkhdr rvclkhdr_15 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_15_io_clk), + .io_en(rvclkhdr_15_io_en) + ); + rvclkhdr rvclkhdr_16 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_16_io_clk), + .io_en(rvclkhdr_16_io_en) + ); + rvclkhdr rvclkhdr_17 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_17_io_clk), + .io_en(rvclkhdr_17_io_en) + ); + rvclkhdr rvclkhdr_18 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_18_io_clk), + .io_en(rvclkhdr_18_io_en) + ); + rvclkhdr rvclkhdr_19 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_19_io_clk), + .io_en(rvclkhdr_19_io_en) + ); + rvclkhdr rvclkhdr_20 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_20_io_clk), + .io_en(rvclkhdr_20_io_en) + ); + rvclkhdr rvclkhdr_21 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_21_io_clk), + .io_en(rvclkhdr_21_io_en) + ); + rvclkhdr rvclkhdr_22 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_22_io_clk), + .io_en(rvclkhdr_22_io_en) + ); + rvclkhdr rvclkhdr_23 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_23_io_clk), + .io_en(rvclkhdr_23_io_en) + ); + rvclkhdr rvclkhdr_24 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_24_io_clk), + .io_en(rvclkhdr_24_io_en) + ); + rvclkhdr rvclkhdr_25 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_25_io_clk), + .io_en(rvclkhdr_25_io_en) + ); + rvclkhdr rvclkhdr_26 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_26_io_clk), + .io_en(rvclkhdr_26_io_en) + ); + rvclkhdr rvclkhdr_27 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_27_io_clk), + .io_en(rvclkhdr_27_io_en) + ); + rvclkhdr rvclkhdr_28 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_28_io_clk), + .io_en(rvclkhdr_28_io_en) + ); + rvclkhdr rvclkhdr_29 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_29_io_clk), + .io_en(rvclkhdr_29_io_en) + ); + rvclkhdr rvclkhdr_30 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_30_io_clk), + .io_en(rvclkhdr_30_io_en) + ); + assign io_gpr_exu_gpr_i0_rs1_d = _T_805 | _T_776; // @[dec_gpr_ctl.scala 48:32 dec_gpr_ctl.scala 64:32] + assign io_gpr_exu_gpr_i0_rs2_d = _T_929 | _T_900; // @[dec_gpr_ctl.scala 49:32 dec_gpr_ctl.scala 65:32] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = gpr_wr_en[1]; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = gpr_wr_en[2]; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = gpr_wr_en[3]; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = gpr_wr_en[4]; // @[lib.scala 407:17] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_4_io_en = gpr_wr_en[5]; // @[lib.scala 407:17] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_5_io_en = gpr_wr_en[6]; // @[lib.scala 407:17] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_6_io_en = gpr_wr_en[7]; // @[lib.scala 407:17] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_7_io_en = gpr_wr_en[8]; // @[lib.scala 407:17] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_8_io_en = gpr_wr_en[9]; // @[lib.scala 407:17] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_9_io_en = gpr_wr_en[10]; // @[lib.scala 407:17] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_10_io_en = gpr_wr_en[11]; // @[lib.scala 407:17] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_11_io_en = gpr_wr_en[12]; // @[lib.scala 407:17] + assign rvclkhdr_12_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_12_io_en = gpr_wr_en[13]; // @[lib.scala 407:17] + assign rvclkhdr_13_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_13_io_en = gpr_wr_en[14]; // @[lib.scala 407:17] + assign rvclkhdr_14_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_14_io_en = gpr_wr_en[15]; // @[lib.scala 407:17] + assign rvclkhdr_15_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_15_io_en = gpr_wr_en[16]; // @[lib.scala 407:17] + assign rvclkhdr_16_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_16_io_en = gpr_wr_en[17]; // @[lib.scala 407:17] + assign rvclkhdr_17_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_17_io_en = gpr_wr_en[18]; // @[lib.scala 407:17] + assign rvclkhdr_18_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_18_io_en = gpr_wr_en[19]; // @[lib.scala 407:17] + assign rvclkhdr_19_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_19_io_en = gpr_wr_en[20]; // @[lib.scala 407:17] + assign rvclkhdr_20_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_20_io_en = gpr_wr_en[21]; // @[lib.scala 407:17] + assign rvclkhdr_21_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_21_io_en = gpr_wr_en[22]; // @[lib.scala 407:17] + assign rvclkhdr_22_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_22_io_en = gpr_wr_en[23]; // @[lib.scala 407:17] + assign rvclkhdr_23_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_23_io_en = gpr_wr_en[24]; // @[lib.scala 407:17] + assign rvclkhdr_24_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_24_io_en = gpr_wr_en[25]; // @[lib.scala 407:17] + assign rvclkhdr_25_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_25_io_en = gpr_wr_en[26]; // @[lib.scala 407:17] + assign rvclkhdr_26_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_26_io_en = gpr_wr_en[27]; // @[lib.scala 407:17] + assign rvclkhdr_27_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_27_io_en = gpr_wr_en[28]; // @[lib.scala 407:17] + assign rvclkhdr_28_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_28_io_en = gpr_wr_en[29]; // @[lib.scala 407:17] + assign rvclkhdr_29_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_29_io_en = gpr_wr_en[30]; // @[lib.scala 407:17] + assign rvclkhdr_30_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_30_io_en = gpr_wr_en[31]; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + gpr_out_1 = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + gpr_out_2 = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + gpr_out_3 = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + gpr_out_4 = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + gpr_out_5 = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + gpr_out_6 = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + gpr_out_7 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + gpr_out_8 = _RAND_7[31:0]; + _RAND_8 = {1{`RANDOM}}; + gpr_out_9 = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + gpr_out_10 = _RAND_9[31:0]; + _RAND_10 = {1{`RANDOM}}; + gpr_out_11 = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + gpr_out_12 = _RAND_11[31:0]; + _RAND_12 = {1{`RANDOM}}; + gpr_out_13 = _RAND_12[31:0]; + _RAND_13 = {1{`RANDOM}}; + gpr_out_14 = _RAND_13[31:0]; + _RAND_14 = {1{`RANDOM}}; + gpr_out_15 = _RAND_14[31:0]; + _RAND_15 = {1{`RANDOM}}; + gpr_out_16 = _RAND_15[31:0]; + _RAND_16 = {1{`RANDOM}}; + gpr_out_17 = _RAND_16[31:0]; + _RAND_17 = {1{`RANDOM}}; + gpr_out_18 = _RAND_17[31:0]; + _RAND_18 = {1{`RANDOM}}; + gpr_out_19 = _RAND_18[31:0]; + _RAND_19 = {1{`RANDOM}}; + gpr_out_20 = _RAND_19[31:0]; + _RAND_20 = {1{`RANDOM}}; + gpr_out_21 = _RAND_20[31:0]; + _RAND_21 = {1{`RANDOM}}; + gpr_out_22 = _RAND_21[31:0]; + _RAND_22 = {1{`RANDOM}}; + gpr_out_23 = _RAND_22[31:0]; + _RAND_23 = {1{`RANDOM}}; + gpr_out_24 = _RAND_23[31:0]; + _RAND_24 = {1{`RANDOM}}; + gpr_out_25 = _RAND_24[31:0]; + _RAND_25 = {1{`RANDOM}}; + gpr_out_26 = _RAND_25[31:0]; + _RAND_26 = {1{`RANDOM}}; + gpr_out_27 = _RAND_26[31:0]; + _RAND_27 = {1{`RANDOM}}; + gpr_out_28 = _RAND_27[31:0]; + _RAND_28 = {1{`RANDOM}}; + gpr_out_29 = _RAND_28[31:0]; + _RAND_29 = {1{`RANDOM}}; + gpr_out_30 = _RAND_29[31:0]; + _RAND_30 = {1{`RANDOM}}; + gpr_out_31 = _RAND_30[31:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + gpr_out_1 = 32'h0; + end + if (reset) begin + gpr_out_2 = 32'h0; + end + if (reset) begin + gpr_out_3 = 32'h0; + end + if (reset) begin + gpr_out_4 = 32'h0; + end + if (reset) begin + gpr_out_5 = 32'h0; + end + if (reset) begin + gpr_out_6 = 32'h0; + end + if (reset) begin + gpr_out_7 = 32'h0; + end + if (reset) begin + gpr_out_8 = 32'h0; + end + if (reset) begin + gpr_out_9 = 32'h0; + end + if (reset) begin + gpr_out_10 = 32'h0; + end + if (reset) begin + gpr_out_11 = 32'h0; + end + if (reset) begin + gpr_out_12 = 32'h0; + end + if (reset) begin + gpr_out_13 = 32'h0; + end + if (reset) begin + gpr_out_14 = 32'h0; + end + if (reset) begin + gpr_out_15 = 32'h0; + end + if (reset) begin + gpr_out_16 = 32'h0; + end + if (reset) begin + gpr_out_17 = 32'h0; + end + if (reset) begin + gpr_out_18 = 32'h0; + end + if (reset) begin + gpr_out_19 = 32'h0; + end + if (reset) begin + gpr_out_20 = 32'h0; + end + if (reset) begin + gpr_out_21 = 32'h0; + end + if (reset) begin + gpr_out_22 = 32'h0; + end + if (reset) begin + gpr_out_23 = 32'h0; + end + if (reset) begin + gpr_out_24 = 32'h0; + end + if (reset) begin + gpr_out_25 = 32'h0; + end + if (reset) begin + gpr_out_26 = 32'h0; + end + if (reset) begin + gpr_out_27 = 32'h0; + end + if (reset) begin + gpr_out_28 = 32'h0; + end + if (reset) begin + gpr_out_29 = 32'h0; + end + if (reset) begin + gpr_out_30 = 32'h0; + end + if (reset) begin + gpr_out_31 = 32'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_1 <= 32'h0; + end else if (gpr_wr_en[1]) begin + gpr_out_1 <= gpr_in_1; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_2 <= 32'h0; + end else if (gpr_wr_en[2]) begin + gpr_out_2 <= gpr_in_2; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_3 <= 32'h0; + end else if (gpr_wr_en[3]) begin + gpr_out_3 <= gpr_in_3; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_4 <= 32'h0; + end else if (gpr_wr_en[4]) begin + gpr_out_4 <= gpr_in_4; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_5 <= 32'h0; + end else if (gpr_wr_en[5]) begin + gpr_out_5 <= gpr_in_5; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_6 <= 32'h0; + end else if (gpr_wr_en[6]) begin + gpr_out_6 <= gpr_in_6; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_7 <= 32'h0; + end else if (gpr_wr_en[7]) begin + gpr_out_7 <= gpr_in_7; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_8 <= 32'h0; + end else if (gpr_wr_en[8]) begin + gpr_out_8 <= gpr_in_8; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_9 <= 32'h0; + end else if (gpr_wr_en[9]) begin + gpr_out_9 <= gpr_in_9; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_10 <= 32'h0; + end else if (gpr_wr_en[10]) begin + gpr_out_10 <= gpr_in_10; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_11 <= 32'h0; + end else if (gpr_wr_en[11]) begin + gpr_out_11 <= gpr_in_11; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_12 <= 32'h0; + end else if (gpr_wr_en[12]) begin + gpr_out_12 <= gpr_in_12; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_13 <= 32'h0; + end else if (gpr_wr_en[13]) begin + gpr_out_13 <= gpr_in_13; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_14 <= 32'h0; + end else if (gpr_wr_en[14]) begin + gpr_out_14 <= gpr_in_14; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_15 <= 32'h0; + end else if (gpr_wr_en[15]) begin + gpr_out_15 <= gpr_in_15; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_16 <= 32'h0; + end else if (gpr_wr_en[16]) begin + gpr_out_16 <= gpr_in_16; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_17 <= 32'h0; + end else if (gpr_wr_en[17]) begin + gpr_out_17 <= gpr_in_17; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_18 <= 32'h0; + end else if (gpr_wr_en[18]) begin + gpr_out_18 <= gpr_in_18; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_19 <= 32'h0; + end else if (gpr_wr_en[19]) begin + gpr_out_19 <= gpr_in_19; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_20 <= 32'h0; + end else if (gpr_wr_en[20]) begin + gpr_out_20 <= gpr_in_20; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_21 <= 32'h0; + end else if (gpr_wr_en[21]) begin + gpr_out_21 <= gpr_in_21; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_22 <= 32'h0; + end else if (gpr_wr_en[22]) begin + gpr_out_22 <= gpr_in_22; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_23 <= 32'h0; + end else if (gpr_wr_en[23]) begin + gpr_out_23 <= gpr_in_23; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_24 <= 32'h0; + end else if (gpr_wr_en[24]) begin + gpr_out_24 <= gpr_in_24; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_25 <= 32'h0; + end else if (gpr_wr_en[25]) begin + gpr_out_25 <= gpr_in_25; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_26 <= 32'h0; + end else if (gpr_wr_en[26]) begin + gpr_out_26 <= gpr_in_26; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_27 <= 32'h0; + end else if (gpr_wr_en[27]) begin + gpr_out_27 <= gpr_in_27; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_28 <= 32'h0; + end else if (gpr_wr_en[28]) begin + gpr_out_28 <= gpr_in_28; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_29 <= 32'h0; + end else if (gpr_wr_en[29]) begin + gpr_out_29 <= gpr_in_29; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_30 <= 32'h0; + end else if (gpr_wr_en[30]) begin + gpr_out_30 <= gpr_in_30; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gpr_out_31 <= 32'h0; + end else if (gpr_wr_en[31]) begin + gpr_out_31 <= gpr_in_31; + end + end +endmodule diff --git a/dec_ib_ctl.anno.json b/dec_ib_ctl.anno.json new file mode 100644 index 00000000..5873adcd --- /dev/null +++ b/dec_ib_ctl.anno.json @@ -0,0 +1,198 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_debug_valid_d", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_valid", + "~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_type" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_instr_d", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_instr", + "~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_valid", + "~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_type", + "~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_addr", + "~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_bp_btag", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_bp_btag" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_icaf_type_d", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_icaf_type" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_debug_fence_d", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_write", + "~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_type", + "~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_addr", + "~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_bp_fa_index", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_i0_fa_index" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_brp_bits_way", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_i0_brp_bits_way" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_pc4_d", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_pc4" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_icaf_d", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_icaf" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_dbecc_d", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_dbecc" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_ib0_valid_d", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_valid", + "~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_valid", + "~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_type" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_brp_bits_br_error", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_i0_brp_bits_br_error" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_brp_bits_br_start_error", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_i0_brp_bits_br_start_error" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_icaf_second_d", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_icaf_second" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_bp_fghr", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_bp_fghr" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_brp_bits_toffset", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_i0_brp_bits_toffset" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_brp_bits_ret", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_i0_brp_bits_ret" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_brp_bits_bank", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_i0_brp_bits_bank" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_ib_exu_dec_i0_pc_d", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_pc" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_bp_index", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_bp_index" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_ib_exu_dec_debug_wdata_rs1_d", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_write", + "~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_type", + "~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_brp_bits_hist", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_i0_brp_bits_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_brp_valid", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_i0_brp_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_brp_bits_prett", + "sources":[ + "~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_i0_brp_bits_prett" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"dec_ib_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/dec_ib_ctl.fir b/dec_ib_ctl.fir new file mode 100644 index 00000000..0cc29e99 --- /dev/null +++ b/dec_ib_ctl.fir @@ -0,0 +1,73 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit dec_ib_ctl : + module dec_ib_ctl : + input clock : Clock + input reset : UInt<1> + output io : {flip ifu_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_second : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, flip ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dec_debug_valid_d : UInt<1>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, flip ifu_i0_fa_index : UInt<9>, dec_i0_bp_fa_index : UInt<9>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_second_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_fence_d : UInt<1>} + + io.dec_i0_icaf_second_d <= io.ifu_ib.ifu_i0_icaf_second @[dec_ib_ctl.scala 34:35] + io.dec_i0_dbecc_d <= io.ifu_ib.ifu_i0_dbecc @[dec_ib_ctl.scala 35:31] + io.dec_i0_icaf_d <= io.ifu_ib.ifu_i0_icaf @[dec_ib_ctl.scala 36:31] + io.ib_exu.dec_i0_pc_d <= io.ifu_ib.ifu_i0_pc @[dec_ib_ctl.scala 37:31] + io.dec_i0_pc4_d <= io.ifu_ib.ifu_i0_pc4 @[dec_ib_ctl.scala 38:31] + io.dec_i0_icaf_type_d <= io.ifu_ib.ifu_i0_icaf_type @[dec_ib_ctl.scala 39:31] + io.dec_i0_brp.bits.ret <= io.ifu_ib.i0_brp.bits.ret @[dec_ib_ctl.scala 40:31] + io.dec_i0_brp.bits.way <= io.ifu_ib.i0_brp.bits.way @[dec_ib_ctl.scala 40:31] + io.dec_i0_brp.bits.prett <= io.ifu_ib.i0_brp.bits.prett @[dec_ib_ctl.scala 40:31] + io.dec_i0_brp.bits.bank <= io.ifu_ib.i0_brp.bits.bank @[dec_ib_ctl.scala 40:31] + io.dec_i0_brp.bits.br_start_error <= io.ifu_ib.i0_brp.bits.br_start_error @[dec_ib_ctl.scala 40:31] + io.dec_i0_brp.bits.br_error <= io.ifu_ib.i0_brp.bits.br_error @[dec_ib_ctl.scala 40:31] + io.dec_i0_brp.bits.hist <= io.ifu_ib.i0_brp.bits.hist @[dec_ib_ctl.scala 40:31] + io.dec_i0_brp.bits.toffset <= io.ifu_ib.i0_brp.bits.toffset @[dec_ib_ctl.scala 40:31] + io.dec_i0_brp.valid <= io.ifu_ib.i0_brp.valid @[dec_ib_ctl.scala 40:31] + io.dec_i0_bp_index <= io.ifu_ib.ifu_i0_bp_index @[dec_ib_ctl.scala 41:31] + io.dec_i0_bp_fghr <= io.ifu_ib.ifu_i0_bp_fghr @[dec_ib_ctl.scala 42:31] + io.dec_i0_bp_btag <= io.ifu_ib.ifu_i0_bp_btag @[dec_ib_ctl.scala 43:31] + io.dec_i0_bp_fa_index <= io.ifu_i0_fa_index @[dec_ib_ctl.scala 44:25] + node _T = neq(io.dbg_ib.dbg_cmd_type, UInt<2>("h02")) @[dec_ib_ctl.scala 58:74] + node debug_valid = and(io.dbg_ib.dbg_cmd_valid, _T) @[dec_ib_ctl.scala 58:48] + node _T_1 = eq(io.dbg_ib.dbg_cmd_write, UInt<1>("h00")) @[dec_ib_ctl.scala 59:38] + node debug_read = and(debug_valid, _T_1) @[dec_ib_ctl.scala 59:36] + node debug_write = and(debug_valid, io.dbg_ib.dbg_cmd_write) @[dec_ib_ctl.scala 60:36] + io.dec_debug_valid_d <= debug_valid @[dec_ib_ctl.scala 61:24] + node _T_2 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h00")) @[dec_ib_ctl.scala 62:62] + node debug_read_gpr = and(debug_read, _T_2) @[dec_ib_ctl.scala 62:37] + node _T_3 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h00")) @[dec_ib_ctl.scala 63:62] + node debug_write_gpr = and(debug_write, _T_3) @[dec_ib_ctl.scala 63:37] + node _T_4 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h01")) @[dec_ib_ctl.scala 64:62] + node debug_read_csr = and(debug_read, _T_4) @[dec_ib_ctl.scala 64:37] + node _T_5 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h01")) @[dec_ib_ctl.scala 65:62] + node debug_write_csr = and(debug_write, _T_5) @[dec_ib_ctl.scala 65:37] + node dreg = bits(io.dbg_ib.dbg_cmd_addr, 4, 0) @[dec_ib_ctl.scala 67:47] + node dcsr = bits(io.dbg_ib.dbg_cmd_addr, 11, 0) @[dec_ib_ctl.scala 68:47] + node _T_6 = bits(debug_read_gpr, 0, 0) @[dec_ib_ctl.scala 71:20] + node _T_7 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] + node _T_8 = cat(_T_7, dreg) @[Cat.scala 29:58] + node _T_9 = cat(_T_8, UInt<15>("h06033")) @[Cat.scala 29:58] + node _T_10 = bits(debug_write_gpr, 0, 0) @[dec_ib_ctl.scala 72:21] + node _T_11 = cat(UInt<20>("h06"), dreg) @[Cat.scala 29:58] + node _T_12 = cat(_T_11, UInt<7>("h033")) @[Cat.scala 29:58] + node _T_13 = bits(debug_read_csr, 0, 0) @[dec_ib_ctl.scala 73:20] + node _T_14 = cat(dcsr, UInt<20>("h02073")) @[Cat.scala 29:58] + node _T_15 = bits(debug_write_csr, 0, 0) @[dec_ib_ctl.scala 74:21] + node _T_16 = cat(dcsr, UInt<20>("h01073")) @[Cat.scala 29:58] + node _T_17 = mux(_T_6, _T_9, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_18 = mux(_T_10, _T_12, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_19 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_20 = mux(_T_15, _T_16, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72] + node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72] + node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72] + wire ib0_debug_in : UInt<32> @[Mux.scala 27:72] + ib0_debug_in <= _T_23 @[Mux.scala 27:72] + node _T_24 = or(debug_write_gpr, debug_write_csr) @[dec_ib_ctl.scala 78:54] + io.ib_exu.dec_debug_wdata_rs1_d <= _T_24 @[dec_ib_ctl.scala 78:35] + node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[dec_ib_ctl.scala 81:51] + node _T_26 = and(debug_write_csr, _T_25) @[dec_ib_ctl.scala 81:43] + io.dec_debug_fence_d <= _T_26 @[dec_ib_ctl.scala 81:24] + node _T_27 = or(io.ifu_ib.ifu_i0_valid, debug_valid) @[dec_ib_ctl.scala 83:48] + io.dec_ib0_valid_d <= _T_27 @[dec_ib_ctl.scala 83:22] + node _T_28 = bits(debug_valid, 0, 0) @[dec_ib_ctl.scala 84:41] + node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_ib.ifu_i0_instr) @[dec_ib_ctl.scala 84:28] + io.dec_i0_instr_d <= _T_29 @[dec_ib_ctl.scala 84:22] + diff --git a/dec_ib_ctl.v b/dec_ib_ctl.v new file mode 100644 index 00000000..07846546 --- /dev/null +++ b/dec_ib_ctl.v @@ -0,0 +1,103 @@ +module dec_ib_ctl( + input clock, + input reset, + input io_ifu_ib_ifu_i0_icaf, + input [1:0] io_ifu_ib_ifu_i0_icaf_type, + input io_ifu_ib_ifu_i0_icaf_second, + input io_ifu_ib_ifu_i0_dbecc, + input [7:0] io_ifu_ib_ifu_i0_bp_index, + input [7:0] io_ifu_ib_ifu_i0_bp_fghr, + input [4:0] io_ifu_ib_ifu_i0_bp_btag, + input io_ifu_ib_ifu_i0_valid, + input [31:0] io_ifu_ib_ifu_i0_instr, + input [30:0] io_ifu_ib_ifu_i0_pc, + input io_ifu_ib_ifu_i0_pc4, + input io_ifu_ib_i0_brp_valid, + input [11:0] io_ifu_ib_i0_brp_bits_toffset, + input [1:0] io_ifu_ib_i0_brp_bits_hist, + input io_ifu_ib_i0_brp_bits_br_error, + input io_ifu_ib_i0_brp_bits_br_start_error, + input io_ifu_ib_i0_brp_bits_bank, + input [30:0] io_ifu_ib_i0_brp_bits_prett, + input io_ifu_ib_i0_brp_bits_way, + input io_ifu_ib_i0_brp_bits_ret, + output [30:0] io_ib_exu_dec_i0_pc_d, + output io_ib_exu_dec_debug_wdata_rs1_d, + input io_dbg_ib_dbg_cmd_valid, + input io_dbg_ib_dbg_cmd_write, + input [1:0] io_dbg_ib_dbg_cmd_type, + input [31:0] io_dbg_ib_dbg_cmd_addr, + output io_dec_debug_valid_d, + output io_dec_ib0_valid_d, + output [1:0] io_dec_i0_icaf_type_d, + output [31:0] io_dec_i0_instr_d, + output io_dec_i0_pc4_d, + output io_dec_i0_brp_valid, + output [11:0] io_dec_i0_brp_bits_toffset, + output [1:0] io_dec_i0_brp_bits_hist, + output io_dec_i0_brp_bits_br_error, + output io_dec_i0_brp_bits_br_start_error, + output io_dec_i0_brp_bits_bank, + output [30:0] io_dec_i0_brp_bits_prett, + output io_dec_i0_brp_bits_way, + output io_dec_i0_brp_bits_ret, + output [7:0] io_dec_i0_bp_index, + output [7:0] io_dec_i0_bp_fghr, + output [4:0] io_dec_i0_bp_btag, + input [8:0] io_ifu_i0_fa_index, + output [8:0] io_dec_i0_bp_fa_index, + output io_dec_i0_icaf_d, + output io_dec_i0_icaf_second_d, + output io_dec_i0_dbecc_d, + output io_dec_debug_fence_d +); + wire _T = io_dbg_ib_dbg_cmd_type != 2'h2; // @[dec_ib_ctl.scala 58:74] + wire debug_valid = io_dbg_ib_dbg_cmd_valid & _T; // @[dec_ib_ctl.scala 58:48] + wire _T_1 = ~io_dbg_ib_dbg_cmd_write; // @[dec_ib_ctl.scala 59:38] + wire debug_read = debug_valid & _T_1; // @[dec_ib_ctl.scala 59:36] + wire debug_write = debug_valid & io_dbg_ib_dbg_cmd_write; // @[dec_ib_ctl.scala 60:36] + wire _T_2 = io_dbg_ib_dbg_cmd_type == 2'h0; // @[dec_ib_ctl.scala 62:62] + wire debug_read_gpr = debug_read & _T_2; // @[dec_ib_ctl.scala 62:37] + wire debug_write_gpr = debug_write & _T_2; // @[dec_ib_ctl.scala 63:37] + wire _T_4 = io_dbg_ib_dbg_cmd_type == 2'h1; // @[dec_ib_ctl.scala 64:62] + wire debug_read_csr = debug_read & _T_4; // @[dec_ib_ctl.scala 64:37] + wire debug_write_csr = debug_write & _T_4; // @[dec_ib_ctl.scala 65:37] + wire [4:0] dreg = io_dbg_ib_dbg_cmd_addr[4:0]; // @[dec_ib_ctl.scala 67:47] + wire [11:0] dcsr = io_dbg_ib_dbg_cmd_addr[11:0]; // @[dec_ib_ctl.scala 68:47] + wire [31:0] _T_9 = {12'h0,dreg,15'h6033}; // @[Cat.scala 29:58] + wire [31:0] _T_12 = {20'h6,dreg,7'h33}; // @[Cat.scala 29:58] + wire [31:0] _T_14 = {dcsr,20'h2073}; // @[Cat.scala 29:58] + wire [31:0] _T_16 = {dcsr,20'h1073}; // @[Cat.scala 29:58] + wire [31:0] _T_17 = debug_read_gpr ? _T_9 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_18 = debug_write_gpr ? _T_12 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_19 = debug_read_csr ? _T_14 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_20 = debug_write_csr ? _T_16 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72] + wire [31:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72] + wire [31:0] ib0_debug_in = _T_22 | _T_20; // @[Mux.scala 27:72] + wire _T_25 = dcsr == 12'h7c4; // @[dec_ib_ctl.scala 81:51] + assign io_ib_exu_dec_i0_pc_d = io_ifu_ib_ifu_i0_pc; // @[dec_ib_ctl.scala 37:31] + assign io_ib_exu_dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; // @[dec_ib_ctl.scala 78:35] + assign io_dec_debug_valid_d = io_dbg_ib_dbg_cmd_valid & _T; // @[dec_ib_ctl.scala 61:24] + assign io_dec_ib0_valid_d = io_ifu_ib_ifu_i0_valid | debug_valid; // @[dec_ib_ctl.scala 83:22] + assign io_dec_i0_icaf_type_d = io_ifu_ib_ifu_i0_icaf_type; // @[dec_ib_ctl.scala 39:31] + assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_ib_ifu_i0_instr; // @[dec_ib_ctl.scala 84:22] + assign io_dec_i0_pc4_d = io_ifu_ib_ifu_i0_pc4; // @[dec_ib_ctl.scala 38:31] + assign io_dec_i0_brp_valid = io_ifu_ib_i0_brp_valid; // @[dec_ib_ctl.scala 40:31] + assign io_dec_i0_brp_bits_toffset = io_ifu_ib_i0_brp_bits_toffset; // @[dec_ib_ctl.scala 40:31] + assign io_dec_i0_brp_bits_hist = io_ifu_ib_i0_brp_bits_hist; // @[dec_ib_ctl.scala 40:31] + assign io_dec_i0_brp_bits_br_error = io_ifu_ib_i0_brp_bits_br_error; // @[dec_ib_ctl.scala 40:31] + assign io_dec_i0_brp_bits_br_start_error = io_ifu_ib_i0_brp_bits_br_start_error; // @[dec_ib_ctl.scala 40:31] + assign io_dec_i0_brp_bits_bank = io_ifu_ib_i0_brp_bits_bank; // @[dec_ib_ctl.scala 40:31] + assign io_dec_i0_brp_bits_prett = io_ifu_ib_i0_brp_bits_prett; // @[dec_ib_ctl.scala 40:31] + assign io_dec_i0_brp_bits_way = io_ifu_ib_i0_brp_bits_way; // @[dec_ib_ctl.scala 40:31] + assign io_dec_i0_brp_bits_ret = io_ifu_ib_i0_brp_bits_ret; // @[dec_ib_ctl.scala 40:31] + assign io_dec_i0_bp_index = io_ifu_ib_ifu_i0_bp_index; // @[dec_ib_ctl.scala 41:31] + assign io_dec_i0_bp_fghr = io_ifu_ib_ifu_i0_bp_fghr; // @[dec_ib_ctl.scala 42:31] + assign io_dec_i0_bp_btag = io_ifu_ib_ifu_i0_bp_btag; // @[dec_ib_ctl.scala 43:31] + assign io_dec_i0_bp_fa_index = io_ifu_i0_fa_index; // @[dec_ib_ctl.scala 44:25] + assign io_dec_i0_icaf_d = io_ifu_ib_ifu_i0_icaf; // @[dec_ib_ctl.scala 36:31] + assign io_dec_i0_icaf_second_d = io_ifu_ib_ifu_i0_icaf_second; // @[dec_ib_ctl.scala 34:35] + assign io_dec_i0_dbecc_d = io_ifu_ib_ifu_i0_dbecc; // @[dec_ib_ctl.scala 35:31] + assign io_dec_debug_fence_d = debug_write_csr & _T_25; // @[dec_ib_ctl.scala 81:24] +endmodule diff --git a/dec_tlu_ctl.anno.json b/dec_tlu_ctl.anno.json new file mode 100644 index 00000000..94386c42 --- /dev/null +++ b/dec_tlu_ctl.anno.json @@ -0,0 +1,523 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_pause_r", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_hist_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_path_r", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_rst_vec", + "~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_pc_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_nmi_vec", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_addr", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_exc_type", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_npc_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_wr_pause_r", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_rddata_d", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_core_id", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_rdaddr_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_dbg_cmd_done", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_way", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_exu_i0_br_way_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_perfcnt2", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_extint", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_perfcnt1", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_presync_d", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_any_unq_d", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_unq_d", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_rdaddr_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_dec_tlu_i0_commit_cmt", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_leak_one_wb", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_ifc_dec_tlu_flush_noredir_wb", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_lower_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_resume_ack", + "~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_pause_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_perfcnt0", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_postsync_d", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_any_unq_d", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_rdaddr_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_legal_d", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_any_unq_d", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_unq_d", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_rdaddr_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_dbg_cmd_fail", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_dbg_cmd_done", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_dec_tlu_fence_i_wb", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_dec_tlu_flush_err_wb", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_lower_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_core_empty", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req", + "~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_valid", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_valid_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_mp_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_pmu_i0_br_ataken" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_lower_r", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_middle_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_ifc_dec_tlu_flush_noredir_wb", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_pause_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_perfcnt3", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_kill_writeb_r", + "sources":[ + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r", + "~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type", + "~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger", + "~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"dec_tlu_ctl.gated_latch", + "resourceId":"/vsrc/gated_latch.sv" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"dec_tlu_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/dec_tlu_ctl.fir b/dec_tlu_ctl.fir new file mode 100644 index 00000000..9ce0796e --- /dev/null +++ b/dec_tlu_ctl.fir @@ -0,0 +1,9684 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit dec_tlu_ctl : + module int_exc : + input clock : Clock + input reset : AsyncReset + output io : {mhwakeup_ready : UInt<1>, ext_int_ready : UInt<1>, ce_int_ready : UInt<1>, soft_int_ready : UInt<1>, timer_int_ready : UInt<1>, int_timer0_int_hold : UInt<1>, int_timer1_int_hold : UInt<1>, internal_dbg_halt_timers : UInt<1>, take_ext_int_start : UInt<1>, flip ext_int_freeze_d1 : UInt<1>, flip take_ext_int_start_d1 : UInt<1>, flip take_ext_int_start_d2 : UInt<1>, flip take_ext_int_start_d3 : UInt<1>, ext_int_freeze : UInt<1>, take_ext_int : UInt<1>, fast_int_meicpct : UInt<1>, ignore_ext_int_due_to_lsu_stall : UInt<1>, take_ce_int : UInt<1>, take_soft_int : UInt<1>, take_timer_int : UInt<1>, take_int_timer0_int : UInt<1>, take_int_timer1_int : UInt<1>, take_reset : UInt<1>, take_nmi : UInt<1>, synchronous_flush_r : UInt<1>, tlu_flush_lower_r : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, interrupt_valid_r_d1 : UInt<1>, i0_exception_valid_r_d1 : UInt<1>, exc_or_int_valid_r_d1 : UInt<1>, exc_cause_wb : UInt<5>, i0_valid_wb : UInt<1>, trigger_hit_r_d1 : UInt<1>, take_nmi_r_d1 : UInt<1>, pause_expired_wb : UInt<1>, interrupt_valid_r : UInt<1>, exc_cause_r : UInt<5>, i0_exception_valid_r : UInt<1>, tlu_flush_path_r_d1 : UInt<31>, exc_or_int_valid_r : UInt<1>, flip free_l2clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_stall_int_ff : UInt<1>, flip mstatus_mie_ns : UInt<1>, flip mip : UInt<6>, flip mie_ns : UInt<6>, flip mret_r : UInt<1>, flip pmu_fw_tlu_halted_f : UInt<1>, flip int_timer0_int_hold_f : UInt<1>, flip int_timer1_int_hold_f : UInt<1>, flip internal_dbg_halt_mode_f : UInt<1>, flip dcsr_single_step_running : UInt<1>, flip internal_dbg_halt_mode : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip internal_pmu_fw_halt_mode : UInt<1>, flip i_cpu_halt_req_d1 : UInt<1>, flip ebreak_to_debug_mode_r : UInt<1>, flip lsu_fir_error : UInt<2>, flip csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_meicpct : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}, flip dec_csr_any_unq_d : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip reset_delayed : UInt<1>, flip mpc_reset_run_req : UInt<1>, flip nmi_int_detected : UInt<1>, flip dcsr_single_step_running_f : UInt<1>, flip dcsr_single_step_done_f : UInt<1>, flip dcsr : UInt<16>, flip mtvec : UInt<31>, flip tlu_i0_commit_cmt : UInt<1>, flip i0_trigger_hit_r : UInt<1>, flip pause_expired_r : UInt<1>, flip nmi_vec : UInt<31>, flip lsu_i0_rfnpc_r : UInt<1>, flip fence_i_r : UInt<1>, flip iccm_repair_state_rfnpc : UInt<1>, flip i_cpu_run_req_d1 : UInt<1>, flip rfpc_i0_r : UInt<1>, flip lsu_exc_valid_r : UInt<1>, flip trigger_hit_dmode_r : UInt<1>, flip take_halt : UInt<1>, flip rst_vec : UInt<31>, flip lsu_fir_addr : UInt<31>, flip dec_tlu_i0_pc_r : UInt<31>, flip npc_r : UInt<31>, flip mepc : UInt<31>, flip debug_resume_req_f : UInt<1>, flip dpc : UInt<31>, flip npc_r_d1 : UInt<31>, flip tlu_flush_lower_r_d1 : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip ebreak_r : UInt<1>, flip ecall_r : UInt<1>, flip illegal_r : UInt<1>, flip inst_acc_r : UInt<1>, flip lsu_i0_exc_r : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip dec_tlu_wr_pause_r_d1 : UInt<1>} + + node _T = eq(io.lsu_error_pkt_r.bits.exc_type, UInt<1>("h00")) @[dec_tlu_ctl.scala 3017:48] + node lsu_exc_ma_r = and(io.lsu_i0_exc_r, _T) @[dec_tlu_ctl.scala 3017:46] + node lsu_exc_acc_r = and(io.lsu_i0_exc_r, io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 3018:46] + node lsu_exc_st_r = and(io.lsu_i0_exc_r, io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 3019:46] + node _T_1 = or(io.ebreak_r, io.ecall_r) @[dec_tlu_ctl.scala 3031:49] + node _T_2 = or(_T_1, io.illegal_r) @[dec_tlu_ctl.scala 3031:62] + node _T_3 = or(_T_2, io.inst_acc_r) @[dec_tlu_ctl.scala 3031:77] + node _T_4 = not(io.rfpc_i0_r) @[dec_tlu_ctl.scala 3031:96] + node _T_5 = and(_T_3, _T_4) @[dec_tlu_ctl.scala 3031:94] + node _T_6 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 3031:112] + node _T_7 = and(_T_5, _T_6) @[dec_tlu_ctl.scala 3031:110] + io.i0_exception_valid_r <= _T_7 @[dec_tlu_ctl.scala 3031:33] + node _T_8 = bits(io.take_nmi, 0, 0) @[Bitwise.scala 72:15] + node _T_9 = mux(_T_8, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_10 = not(_T_9) @[dec_tlu_ctl.scala 3039:27] + node _T_11 = bits(io.take_ext_int, 0, 0) @[dec_tlu_ctl.scala 3040:35] + node _T_12 = bits(io.take_timer_int, 0, 0) @[dec_tlu_ctl.scala 3041:38] + node _T_13 = bits(io.take_soft_int, 0, 0) @[dec_tlu_ctl.scala 3042:36] + node _T_14 = bits(io.take_int_timer0_int, 0, 0) @[dec_tlu_ctl.scala 3043:43] + node _T_15 = bits(io.take_int_timer1_int, 0, 0) @[dec_tlu_ctl.scala 3044:42] + node _T_16 = bits(io.take_ce_int, 0, 0) @[dec_tlu_ctl.scala 3045:34] + node _T_17 = bits(io.illegal_r, 0, 0) @[dec_tlu_ctl.scala 3046:32] + node _T_18 = bits(io.ecall_r, 0, 0) @[dec_tlu_ctl.scala 3047:30] + node _T_19 = bits(io.inst_acc_r, 0, 0) @[dec_tlu_ctl.scala 3048:34] + node _T_20 = or(io.ebreak_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 3049:31] + node _T_21 = bits(_T_20, 0, 0) @[dec_tlu_ctl.scala 3049:55] + node _T_22 = eq(lsu_exc_st_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 3050:33] + node _T_23 = and(lsu_exc_ma_r, _T_22) @[dec_tlu_ctl.scala 3050:31] + node _T_24 = bits(_T_23, 0, 0) @[dec_tlu_ctl.scala 3050:48] + node _T_25 = eq(lsu_exc_st_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 3051:34] + node _T_26 = and(lsu_exc_acc_r, _T_25) @[dec_tlu_ctl.scala 3051:32] + node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 3051:49] + node _T_28 = and(lsu_exc_ma_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 3052:31] + node _T_29 = bits(_T_28, 0, 0) @[dec_tlu_ctl.scala 3052:48] + node _T_30 = and(lsu_exc_acc_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 3053:32] + node _T_31 = bits(_T_30, 0, 0) @[dec_tlu_ctl.scala 3053:49] + node _T_32 = mux(_T_11, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_33 = mux(_T_12, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_34 = mux(_T_13, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_35 = mux(_T_14, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_36 = mux(_T_15, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_37 = mux(_T_16, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_38 = mux(_T_17, UInt<5>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_39 = mux(_T_18, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_40 = mux(_T_19, UInt<5>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_41 = mux(_T_21, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_42 = mux(_T_24, UInt<5>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_43 = mux(_T_27, UInt<5>("h05"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_44 = mux(_T_29, UInt<5>("h06"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_45 = mux(_T_31, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_46 = or(_T_32, _T_33) @[Mux.scala 27:72] + node _T_47 = or(_T_46, _T_34) @[Mux.scala 27:72] + node _T_48 = or(_T_47, _T_35) @[Mux.scala 27:72] + node _T_49 = or(_T_48, _T_36) @[Mux.scala 27:72] + node _T_50 = or(_T_49, _T_37) @[Mux.scala 27:72] + node _T_51 = or(_T_50, _T_38) @[Mux.scala 27:72] + node _T_52 = or(_T_51, _T_39) @[Mux.scala 27:72] + node _T_53 = or(_T_52, _T_40) @[Mux.scala 27:72] + node _T_54 = or(_T_53, _T_41) @[Mux.scala 27:72] + node _T_55 = or(_T_54, _T_42) @[Mux.scala 27:72] + node _T_56 = or(_T_55, _T_43) @[Mux.scala 27:72] + node _T_57 = or(_T_56, _T_44) @[Mux.scala 27:72] + node _T_58 = or(_T_57, _T_45) @[Mux.scala 27:72] + wire _T_59 : UInt<5> @[Mux.scala 27:72] + _T_59 <= _T_58 @[Mux.scala 27:72] + node _T_60 = and(_T_10, _T_59) @[dec_tlu_ctl.scala 3039:48] + io.exc_cause_r <= _T_60 @[dec_tlu_ctl.scala 3039:24] + node _T_61 = eq(io.dec_csr_stall_int_ff, UInt<1>("h00")) @[dec_tlu_ctl.scala 3064:31] + node _T_62 = and(_T_61, io.mstatus_mie_ns) @[dec_tlu_ctl.scala 3064:56] + node _T_63 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 3064:84] + node _T_64 = and(_T_62, _T_63) @[dec_tlu_ctl.scala 3064:76] + node _T_65 = bits(io.mie_ns, 2, 2) @[dec_tlu_ctl.scala 3064:108] + node _T_66 = and(_T_64, _T_65) @[dec_tlu_ctl.scala 3064:97] + io.mhwakeup_ready <= _T_66 @[dec_tlu_ctl.scala 3064:28] + node _T_67 = eq(io.dec_csr_stall_int_ff, UInt<1>("h00")) @[dec_tlu_ctl.scala 3065:31] + node _T_68 = and(_T_67, io.mstatus_mie_ns) @[dec_tlu_ctl.scala 3065:56] + node _T_69 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 3065:84] + node _T_70 = and(_T_68, _T_69) @[dec_tlu_ctl.scala 3065:76] + node _T_71 = bits(io.mie_ns, 2, 2) @[dec_tlu_ctl.scala 3065:108] + node _T_72 = and(_T_70, _T_71) @[dec_tlu_ctl.scala 3065:97] + node _T_73 = not(io.ignore_ext_int_due_to_lsu_stall) @[dec_tlu_ctl.scala 3065:121] + node _T_74 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 3065:119] + io.ext_int_ready <= _T_74 @[dec_tlu_ctl.scala 3065:28] + node _T_75 = eq(io.dec_csr_stall_int_ff, UInt<1>("h00")) @[dec_tlu_ctl.scala 3066:31] + node _T_76 = and(_T_75, io.mstatus_mie_ns) @[dec_tlu_ctl.scala 3066:56] + node _T_77 = dshr(io.mip, UInt<3>("h05")) @[dec_tlu_ctl.scala 3066:84] + node _T_78 = bits(_T_77, 0, 0) @[dec_tlu_ctl.scala 3066:84] + node _T_79 = and(_T_76, _T_78) @[dec_tlu_ctl.scala 3066:76] + node _T_80 = bits(io.mie_ns, 5, 5) @[dec_tlu_ctl.scala 3066:108] + node _T_81 = and(_T_79, _T_80) @[dec_tlu_ctl.scala 3066:97] + io.ce_int_ready <= _T_81 @[dec_tlu_ctl.scala 3066:28] + node _T_82 = eq(io.dec_csr_stall_int_ff, UInt<1>("h00")) @[dec_tlu_ctl.scala 3067:31] + node _T_83 = and(_T_82, io.mstatus_mie_ns) @[dec_tlu_ctl.scala 3067:56] + node _T_84 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 3067:84] + node _T_85 = and(_T_83, _T_84) @[dec_tlu_ctl.scala 3067:76] + node _T_86 = bits(io.mie_ns, 0, 0) @[dec_tlu_ctl.scala 3067:108] + node _T_87 = and(_T_85, _T_86) @[dec_tlu_ctl.scala 3067:97] + io.soft_int_ready <= _T_87 @[dec_tlu_ctl.scala 3067:28] + node _T_88 = eq(io.dec_csr_stall_int_ff, UInt<1>("h00")) @[dec_tlu_ctl.scala 3068:31] + node _T_89 = and(_T_88, io.mstatus_mie_ns) @[dec_tlu_ctl.scala 3068:56] + node _T_90 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 3068:84] + node _T_91 = and(_T_89, _T_90) @[dec_tlu_ctl.scala 3068:76] + node _T_92 = bits(io.mie_ns, 1, 1) @[dec_tlu_ctl.scala 3068:108] + node _T_93 = and(_T_91, _T_92) @[dec_tlu_ctl.scala 3068:97] + io.timer_int_ready <= _T_93 @[dec_tlu_ctl.scala 3068:28] + node _T_94 = bits(io.mie_ns, 4, 4) @[dec_tlu_ctl.scala 3071:68] + node int_timer0_int_possible = and(io.mstatus_mie_ns, _T_94) @[dec_tlu_ctl.scala 3071:57] + node _T_95 = dshr(io.mip, UInt<3>("h04")) @[dec_tlu_ctl.scala 3072:42] + node _T_96 = bits(_T_95, 0, 0) @[dec_tlu_ctl.scala 3072:42] + node int_timer0_int_ready = and(_T_96, int_timer0_int_possible) @[dec_tlu_ctl.scala 3072:55] + node _T_97 = bits(io.mie_ns, 3, 3) @[dec_tlu_ctl.scala 3073:68] + node int_timer1_int_possible = and(io.mstatus_mie_ns, _T_97) @[dec_tlu_ctl.scala 3073:57] + node _T_98 = dshr(io.mip, UInt<2>("h03")) @[dec_tlu_ctl.scala 3074:42] + node _T_99 = bits(_T_98, 0, 0) @[dec_tlu_ctl.scala 3074:42] + node int_timer1_int_ready = and(_T_99, int_timer1_int_possible) @[dec_tlu_ctl.scala 3074:55] + node _T_100 = or(io.dec_csr_stall_int_ff, io.synchronous_flush_r) @[dec_tlu_ctl.scala 3078:57] + node _T_101 = or(_T_100, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 3078:82] + node int_timer_stalled = or(_T_101, io.mret_r) @[dec_tlu_ctl.scala 3078:109] + node _T_102 = or(io.pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 3080:83] + node _T_103 = and(int_timer0_int_ready, _T_102) @[dec_tlu_ctl.scala 3080:57] + node _T_104 = and(int_timer0_int_possible, io.int_timer0_int_hold_f) @[dec_tlu_ctl.scala 3080:132] + node _T_105 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 3080:161] + node _T_106 = and(_T_104, _T_105) @[dec_tlu_ctl.scala 3080:159] + node _T_107 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 3080:185] + node _T_108 = and(_T_106, _T_107) @[dec_tlu_ctl.scala 3080:183] + node _T_109 = not(io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 3080:210] + node _T_110 = and(_T_108, _T_109) @[dec_tlu_ctl.scala 3080:208] + node _T_111 = or(_T_103, _T_110) @[dec_tlu_ctl.scala 3080:105] + io.int_timer0_int_hold <= _T_111 @[dec_tlu_ctl.scala 3080:32] + node _T_112 = or(io.pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 3081:83] + node _T_113 = and(int_timer1_int_ready, _T_112) @[dec_tlu_ctl.scala 3081:57] + node _T_114 = and(int_timer1_int_possible, io.int_timer1_int_hold_f) @[dec_tlu_ctl.scala 3081:132] + node _T_115 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 3081:161] + node _T_116 = and(_T_114, _T_115) @[dec_tlu_ctl.scala 3081:159] + node _T_117 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 3081:185] + node _T_118 = and(_T_116, _T_117) @[dec_tlu_ctl.scala 3081:183] + node _T_119 = not(io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 3081:210] + node _T_120 = and(_T_118, _T_119) @[dec_tlu_ctl.scala 3081:208] + node _T_121 = or(_T_113, _T_120) @[dec_tlu_ctl.scala 3081:105] + io.int_timer1_int_hold <= _T_121 @[dec_tlu_ctl.scala 3081:32] + node _T_122 = not(io.dcsr_single_step_running) @[dec_tlu_ctl.scala 3083:70] + node _T_123 = and(io.internal_dbg_halt_mode_f, _T_122) @[dec_tlu_ctl.scala 3083:68] + io.internal_dbg_halt_timers <= _T_123 @[dec_tlu_ctl.scala 3083:37] + node _T_124 = not(io.dcsr_single_step_running) @[dec_tlu_ctl.scala 3085:63] + node _T_125 = or(_T_124, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 3085:92] + node _T_126 = and(io.internal_dbg_halt_mode, _T_125) @[dec_tlu_ctl.scala 3085:60] + node _T_127 = or(_T_126, io.internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 3085:118] + node _T_128 = or(_T_127, io.i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 3085:149] + node _T_129 = or(_T_128, io.take_nmi) @[dec_tlu_ctl.scala 3085:172] + node _T_130 = or(_T_129, io.ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 3085:186] + node _T_131 = or(_T_130, io.synchronous_flush_r) @[dec_tlu_ctl.scala 3085:214] + node _T_132 = or(_T_131, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 3085:240] + node _T_133 = or(_T_132, io.mret_r) @[dec_tlu_ctl.scala 3085:267] + node block_interrupts = or(_T_133, io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 3085:279] + node _T_134 = not(block_interrupts) @[dec_tlu_ctl.scala 3093:61] + node _T_135 = and(io.ext_int_ready, _T_134) @[dec_tlu_ctl.scala 3093:59] + io.take_ext_int_start <= _T_135 @[dec_tlu_ctl.scala 3093:39] + node _T_136 = or(io.take_ext_int_start, io.take_ext_int_start_d1) @[dec_tlu_ctl.scala 3094:60] + node _T_137 = or(_T_136, io.take_ext_int_start_d2) @[dec_tlu_ctl.scala 3094:87] + node _T_138 = or(_T_137, io.take_ext_int_start_d3) @[dec_tlu_ctl.scala 3094:114] + io.ext_int_freeze <= _T_138 @[dec_tlu_ctl.scala 3094:35] + node _T_139 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 3095:81] + node _T_140 = not(_T_139) @[dec_tlu_ctl.scala 3095:63] + node _T_141 = and(io.take_ext_int_start_d3, _T_140) @[dec_tlu_ctl.scala 3095:61] + io.take_ext_int <= _T_141 @[dec_tlu_ctl.scala 3095:33] + node _T_142 = and(io.csr_pkt.csr_meicpct, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 3096:63] + io.fast_int_meicpct <= _T_142 @[dec_tlu_ctl.scala 3096:37] + io.ignore_ext_int_due_to_lsu_stall <= io.lsu_fastint_stall_any @[dec_tlu_ctl.scala 3097:52] + node _T_143 = not(io.ext_int_ready) @[dec_tlu_ctl.scala 3110:46] + node _T_144 = and(io.ce_int_ready, _T_143) @[dec_tlu_ctl.scala 3110:44] + node _T_145 = not(block_interrupts) @[dec_tlu_ctl.scala 3110:66] + node _T_146 = and(_T_144, _T_145) @[dec_tlu_ctl.scala 3110:64] + io.take_ce_int <= _T_146 @[dec_tlu_ctl.scala 3110:25] + node _T_147 = not(io.ext_int_ready) @[dec_tlu_ctl.scala 3111:49] + node _T_148 = and(io.soft_int_ready, _T_147) @[dec_tlu_ctl.scala 3111:47] + node _T_149 = not(io.ce_int_ready) @[dec_tlu_ctl.scala 3111:69] + node _T_150 = and(_T_148, _T_149) @[dec_tlu_ctl.scala 3111:67] + node _T_151 = not(block_interrupts) @[dec_tlu_ctl.scala 3111:88] + node _T_152 = and(_T_150, _T_151) @[dec_tlu_ctl.scala 3111:86] + io.take_soft_int <= _T_152 @[dec_tlu_ctl.scala 3111:26] + node _T_153 = not(io.soft_int_ready) @[dec_tlu_ctl.scala 3112:51] + node _T_154 = and(io.timer_int_ready, _T_153) @[dec_tlu_ctl.scala 3112:49] + node _T_155 = not(io.ext_int_ready) @[dec_tlu_ctl.scala 3112:72] + node _T_156 = and(_T_154, _T_155) @[dec_tlu_ctl.scala 3112:70] + node _T_157 = not(io.ce_int_ready) @[dec_tlu_ctl.scala 3112:92] + node _T_158 = and(_T_156, _T_157) @[dec_tlu_ctl.scala 3112:90] + node _T_159 = not(block_interrupts) @[dec_tlu_ctl.scala 3112:111] + node _T_160 = and(_T_158, _T_159) @[dec_tlu_ctl.scala 3112:109] + io.take_timer_int <= _T_160 @[dec_tlu_ctl.scala 3112:27] + node _T_161 = or(int_timer0_int_ready, io.int_timer0_int_hold_f) @[dec_tlu_ctl.scala 3113:57] + node _T_162 = and(_T_161, int_timer0_int_possible) @[dec_tlu_ctl.scala 3113:85] + node _T_163 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 3113:113] + node _T_164 = and(_T_162, _T_163) @[dec_tlu_ctl.scala 3113:111] + node _T_165 = not(io.timer_int_ready) @[dec_tlu_ctl.scala 3113:140] + node _T_166 = and(_T_164, _T_165) @[dec_tlu_ctl.scala 3113:138] + node _T_167 = not(io.soft_int_ready) @[dec_tlu_ctl.scala 3113:162] + node _T_168 = and(_T_166, _T_167) @[dec_tlu_ctl.scala 3113:160] + node _T_169 = not(io.ext_int_ready) @[dec_tlu_ctl.scala 3113:183] + node _T_170 = and(_T_168, _T_169) @[dec_tlu_ctl.scala 3113:181] + node _T_171 = not(io.ce_int_ready) @[dec_tlu_ctl.scala 3113:203] + node _T_172 = and(_T_170, _T_171) @[dec_tlu_ctl.scala 3113:201] + node _T_173 = not(block_interrupts) @[dec_tlu_ctl.scala 3113:222] + node _T_174 = and(_T_172, _T_173) @[dec_tlu_ctl.scala 3113:220] + io.take_int_timer0_int <= _T_174 @[dec_tlu_ctl.scala 3113:32] + node _T_175 = or(int_timer1_int_ready, io.int_timer1_int_hold_f) @[dec_tlu_ctl.scala 3114:57] + node _T_176 = and(_T_175, int_timer1_int_possible) @[dec_tlu_ctl.scala 3114:85] + node _T_177 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 3114:113] + node _T_178 = and(_T_176, _T_177) @[dec_tlu_ctl.scala 3114:111] + node _T_179 = or(int_timer0_int_ready, io.int_timer0_int_hold_f) @[dec_tlu_ctl.scala 3114:163] + node _T_180 = not(_T_179) @[dec_tlu_ctl.scala 3114:140] + node _T_181 = and(_T_178, _T_180) @[dec_tlu_ctl.scala 3114:138] + node _T_182 = not(io.timer_int_ready) @[dec_tlu_ctl.scala 3114:193] + node _T_183 = and(_T_181, _T_182) @[dec_tlu_ctl.scala 3114:191] + node _T_184 = not(io.soft_int_ready) @[dec_tlu_ctl.scala 3114:215] + node _T_185 = and(_T_183, _T_184) @[dec_tlu_ctl.scala 3114:213] + node _T_186 = not(io.ext_int_ready) @[dec_tlu_ctl.scala 3114:236] + node _T_187 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 3114:234] + node _T_188 = not(io.ce_int_ready) @[dec_tlu_ctl.scala 3114:256] + node _T_189 = and(_T_187, _T_188) @[dec_tlu_ctl.scala 3114:254] + node _T_190 = not(block_interrupts) @[dec_tlu_ctl.scala 3114:275] + node _T_191 = and(_T_189, _T_190) @[dec_tlu_ctl.scala 3114:273] + io.take_int_timer1_int <= _T_191 @[dec_tlu_ctl.scala 3114:32] + node _T_192 = and(io.reset_delayed, io.mpc_reset_run_req) @[dec_tlu_ctl.scala 3115:43] + io.take_reset <= _T_192 @[dec_tlu_ctl.scala 3115:23] + node _T_193 = not(io.internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 3116:46] + node _T_194 = and(io.nmi_int_detected, _T_193) @[dec_tlu_ctl.scala 3116:44] + node _T_195 = not(io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 3116:79] + node _T_196 = bits(io.dcsr, 11, 11) @[dec_tlu_ctl.scala 3116:148] + node _T_197 = and(io.dcsr_single_step_running_f, _T_196) @[dec_tlu_ctl.scala 3116:139] + node _T_198 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 3116:164] + node _T_199 = and(_T_197, _T_198) @[dec_tlu_ctl.scala 3116:162] + node _T_200 = not(io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 3116:189] + node _T_201 = and(_T_199, _T_200) @[dec_tlu_ctl.scala 3116:187] + node _T_202 = or(_T_195, _T_201) @[dec_tlu_ctl.scala 3116:106] + node _T_203 = and(_T_194, _T_202) @[dec_tlu_ctl.scala 3116:76] + node _T_204 = not(io.synchronous_flush_r) @[dec_tlu_ctl.scala 3116:220] + node _T_205 = and(_T_203, _T_204) @[dec_tlu_ctl.scala 3116:218] + node _T_206 = not(io.mret_r) @[dec_tlu_ctl.scala 3116:246] + node _T_207 = and(_T_205, _T_206) @[dec_tlu_ctl.scala 3116:244] + node _T_208 = not(io.take_reset) @[dec_tlu_ctl.scala 3116:259] + node _T_209 = and(_T_207, _T_208) @[dec_tlu_ctl.scala 3116:257] + node _T_210 = not(io.ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 3116:276] + node _T_211 = and(_T_209, _T_210) @[dec_tlu_ctl.scala 3116:274] + node _T_212 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 3116:306] + node _T_213 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 3116:375] + node _T_214 = and(io.take_ext_int_start_d3, _T_213) @[dec_tlu_ctl.scala 3116:356] + node _T_215 = or(_T_212, _T_214) @[dec_tlu_ctl.scala 3116:328] + node _T_216 = and(_T_211, _T_215) @[dec_tlu_ctl.scala 3116:303] + io.take_nmi <= _T_216 @[dec_tlu_ctl.scala 3116:21] + node _T_217 = or(io.take_ext_int, io.take_timer_int) @[dec_tlu_ctl.scala 3120:49] + node _T_218 = or(_T_217, io.take_soft_int) @[dec_tlu_ctl.scala 3120:69] + node _T_219 = or(_T_218, io.take_nmi) @[dec_tlu_ctl.scala 3120:88] + node _T_220 = or(_T_219, io.take_ce_int) @[dec_tlu_ctl.scala 3120:102] + node _T_221 = or(_T_220, io.take_int_timer0_int) @[dec_tlu_ctl.scala 3120:119] + node _T_222 = or(_T_221, io.take_int_timer1_int) @[dec_tlu_ctl.scala 3120:144] + io.interrupt_valid_r <= _T_222 @[dec_tlu_ctl.scala 3120:30] + node _T_223 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 3125:42] + node _T_224 = cat(_T_223, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_225 = cat(UInt<25>("h00"), io.exc_cause_r) @[Cat.scala 29:58] + node _T_226 = cat(_T_225, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_227 = add(_T_224, _T_226) @[dec_tlu_ctl.scala 3125:59] + node vectored_path = tail(_T_227, 1) @[dec_tlu_ctl.scala 3125:59] + node _T_228 = bits(io.take_nmi, 0, 0) @[dec_tlu_ctl.scala 3126:46] + node _T_229 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 3126:78] + node _T_230 = eq(_T_229, UInt<1>("h01")) @[dec_tlu_ctl.scala 3126:82] + node _T_231 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 3126:118] + node _T_232 = cat(_T_231, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_233 = mux(_T_230, vectored_path, _T_232) @[dec_tlu_ctl.scala 3126:69] + node interrupt_path = mux(_T_228, io.nmi_vec, _T_233) @[dec_tlu_ctl.scala 3126:33] + node _T_234 = or(io.lsu_i0_rfnpc_r, io.fence_i_r) @[dec_tlu_ctl.scala 3127:44] + node _T_235 = or(_T_234, io.iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 3127:59] + node _T_236 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 3127:113] + node _T_237 = and(io.i_cpu_run_req_d1, _T_236) @[dec_tlu_ctl.scala 3127:111] + node _T_238 = or(_T_235, _T_237) @[dec_tlu_ctl.scala 3127:88] + node _T_239 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 3127:154] + node _T_240 = and(io.rfpc_i0_r, _T_239) @[dec_tlu_ctl.scala 3127:152] + node sel_npc_r = or(_T_238, _T_240) @[dec_tlu_ctl.scala 3127:136] + node _T_241 = and(io.i_cpu_run_req_d1, io.pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 3128:51] + node sel_npc_resume = or(_T_241, io.pause_expired_r) @[dec_tlu_ctl.scala 3128:77] + node _T_242 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 3129:74] + node _T_243 = eq(_T_242, UInt<1>("h00")) @[dec_tlu_ctl.scala 3129:55] + node sel_fir_addr = and(io.take_ext_int_start_d3, _T_243) @[dec_tlu_ctl.scala 3129:53] + node _T_244 = or(io.i0_exception_valid_r, io.rfpc_i0_r) @[dec_tlu_ctl.scala 3130:60] + node _T_245 = or(_T_244, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 3130:75] + node _T_246 = or(_T_245, io.fence_i_r) @[dec_tlu_ctl.scala 3130:96] + node _T_247 = or(_T_246, io.lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 3130:111] + node _T_248 = or(_T_247, io.iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 3130:131] + node _T_249 = or(_T_248, io.debug_resume_req_f) @[dec_tlu_ctl.scala 3130:161] + node _T_250 = or(_T_249, sel_npc_resume) @[dec_tlu_ctl.scala 3130:186] + node _T_251 = or(_T_250, io.dec_tlu_wr_pause_r_d1) @[dec_tlu_ctl.scala 3130:204] + node _T_252 = or(_T_251, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 3130:232] + io.synchronous_flush_r <= _T_252 @[dec_tlu_ctl.scala 3130:33] + node _T_253 = or(io.interrupt_valid_r, io.mret_r) @[dec_tlu_ctl.scala 3131:54] + node _T_254 = or(_T_253, io.synchronous_flush_r) @[dec_tlu_ctl.scala 3131:66] + node _T_255 = or(_T_254, io.take_halt) @[dec_tlu_ctl.scala 3131:91] + node _T_256 = or(_T_255, io.take_reset) @[dec_tlu_ctl.scala 3131:106] + node _T_257 = or(_T_256, io.take_ext_int_start) @[dec_tlu_ctl.scala 3131:122] + io.tlu_flush_lower_r <= _T_257 @[dec_tlu_ctl.scala 3131:30] + node _T_258 = bits(io.take_reset, 0, 0) @[dec_tlu_ctl.scala 3133:50] + node _T_259 = bits(sel_fir_addr, 0, 0) @[dec_tlu_ctl.scala 3134:32] + node _T_260 = eq(io.take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 3135:29] + node _T_261 = eq(sel_npc_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 3135:47] + node _T_262 = and(_T_260, _T_261) @[dec_tlu_ctl.scala 3135:36] + node _T_263 = eq(io.take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 3136:29] + node _T_264 = eq(io.rfpc_i0_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 3136:50] + node _T_265 = and(_T_263, _T_264) @[dec_tlu_ctl.scala 3136:36] + node _T_266 = eq(io.dec_tlu_i0_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 3136:80] + node _T_267 = and(_T_265, _T_266) @[dec_tlu_ctl.scala 3136:57] + node _T_268 = eq(sel_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 3136:98] + node _T_269 = and(_T_267, _T_268) @[dec_tlu_ctl.scala 3136:87] + node _T_270 = eq(io.interrupt_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 3137:38] + node _T_271 = eq(sel_fir_addr, UInt<1>("h00")) @[dec_tlu_ctl.scala 3137:59] + node _T_272 = and(_T_270, _T_271) @[dec_tlu_ctl.scala 3137:45] + node _T_273 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 3138:43] + node _T_274 = not(io.trigger_hit_dmode_r) @[dec_tlu_ctl.scala 3138:89] + node _T_275 = and(io.i0_trigger_hit_r, _T_274) @[dec_tlu_ctl.scala 3138:87] + node _T_276 = or(_T_273, _T_275) @[dec_tlu_ctl.scala 3138:64] + node _T_277 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 3138:117] + node _T_278 = and(_T_276, _T_277) @[dec_tlu_ctl.scala 3138:115] + node _T_279 = not(sel_fir_addr) @[dec_tlu_ctl.scala 3138:141] + node _T_280 = and(_T_278, _T_279) @[dec_tlu_ctl.scala 3138:139] + node _T_281 = bits(_T_280, 0, 0) @[dec_tlu_ctl.scala 3138:156] + node _T_282 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 3138:184] + node _T_283 = cat(_T_282, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_284 = not(io.take_nmi) @[dec_tlu_ctl.scala 3139:18] + node _T_285 = and(_T_284, io.mret_r) @[dec_tlu_ctl.scala 3139:31] + node _T_286 = bits(_T_285, 0, 0) @[dec_tlu_ctl.scala 3139:44] + node _T_287 = not(io.take_nmi) @[dec_tlu_ctl.scala 3140:18] + node _T_288 = and(_T_287, io.debug_resume_req_f) @[dec_tlu_ctl.scala 3140:31] + node _T_289 = bits(_T_288, 0, 0) @[dec_tlu_ctl.scala 3140:56] + node _T_290 = not(io.take_nmi) @[dec_tlu_ctl.scala 3141:18] + node _T_291 = and(_T_290, sel_npc_resume) @[dec_tlu_ctl.scala 3141:31] + node _T_292 = bits(_T_291, 0, 0) @[dec_tlu_ctl.scala 3141:49] + node _T_293 = mux(_T_259, io.lsu_fir_addr, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_294 = mux(_T_262, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_295 = mux(_T_269, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_296 = mux(_T_272, interrupt_path, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_297 = mux(_T_281, _T_283, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_298 = mux(_T_286, io.mepc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_299 = mux(_T_289, io.dpc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_300 = mux(_T_292, io.npc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_301 = or(_T_293, _T_294) @[Mux.scala 27:72] + node _T_302 = or(_T_301, _T_295) @[Mux.scala 27:72] + node _T_303 = or(_T_302, _T_296) @[Mux.scala 27:72] + node _T_304 = or(_T_303, _T_297) @[Mux.scala 27:72] + node _T_305 = or(_T_304, _T_298) @[Mux.scala 27:72] + node _T_306 = or(_T_305, _T_299) @[Mux.scala 27:72] + node _T_307 = or(_T_306, _T_300) @[Mux.scala 27:72] + wire _T_308 : UInt<31> @[Mux.scala 27:72] + _T_308 <= _T_307 @[Mux.scala 27:72] + node tlu_flush_path_r = mux(_T_258, io.rst_vec, _T_308) @[dec_tlu_ctl.scala 3133:35] + node _T_309 = bits(io.tlu_flush_lower_r, 0, 0) @[lib.scala 8:44] + wire _T_310 : UInt<31> @[lib.scala 648:38] + _T_310 <= UInt<1>("h00") @[lib.scala 648:38] + reg _T_311 : UInt, clock with : (reset => (reset, _T_310)) @[Reg.scala 27:20] + when _T_309 : @[Reg.scala 28:19] + _T_311 <= tlu_flush_path_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.tlu_flush_path_r_d1 <= _T_311 @[dec_tlu_ctl.scala 3144:31] + io.dec_tlu_flush_lower_wb <= io.tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 3146:41] + io.dec_tlu_flush_lower_r <= io.tlu_flush_lower_r @[dec_tlu_ctl.scala 3148:41] + io.dec_tlu_flush_path_r <= tlu_flush_path_r @[dec_tlu_ctl.scala 3149:41] + node _T_312 = or(io.lsu_exc_valid_r, io.i0_exception_valid_r) @[dec_tlu_ctl.scala 3152:53] + node _T_313 = or(_T_312, io.interrupt_valid_r) @[dec_tlu_ctl.scala 3152:79] + node _T_314 = not(io.trigger_hit_dmode_r) @[dec_tlu_ctl.scala 3152:127] + node _T_315 = and(io.i0_trigger_hit_r, _T_314) @[dec_tlu_ctl.scala 3152:125] + node _T_316 = or(_T_313, _T_315) @[dec_tlu_ctl.scala 3152:102] + io.exc_or_int_valid_r <= _T_316 @[dec_tlu_ctl.scala 3152:31] + wire _T_317 : UInt + _T_317 <= UInt<1>("h00") + node _T_318 = xor(io.interrupt_valid_r, _T_317) @[lib.scala 448:21] + node _T_319 = orr(_T_318) @[lib.scala 448:29] + reg _T_320 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_319 : @[Reg.scala 28:19] + _T_320 <= io.interrupt_valid_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_317 <= _T_320 @[lib.scala 451:16] + io.interrupt_valid_r_d1 <= _T_317 @[dec_tlu_ctl.scala 3154:59] + wire _T_321 : UInt + _T_321 <= UInt<1>("h00") + node _T_322 = xor(io.i0_exception_valid_r, _T_321) @[lib.scala 448:21] + node _T_323 = orr(_T_322) @[lib.scala 448:29] + reg _T_324 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_323 : @[Reg.scala 28:19] + _T_324 <= io.i0_exception_valid_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_321 <= _T_324 @[lib.scala 451:16] + io.i0_exception_valid_r_d1 <= _T_321 @[dec_tlu_ctl.scala 3155:51] + wire _T_325 : UInt + _T_325 <= UInt<1>("h00") + node _T_326 = xor(io.exc_or_int_valid_r, _T_325) @[lib.scala 448:21] + node _T_327 = orr(_T_326) @[lib.scala 448:29] + reg _T_328 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_327 : @[Reg.scala 28:19] + _T_328 <= io.exc_or_int_valid_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_325 <= _T_328 @[lib.scala 451:16] + io.exc_or_int_valid_r_d1 <= _T_325 @[dec_tlu_ctl.scala 3156:53] + wire _T_329 : UInt + _T_329 <= UInt<1>("h00") + node _T_330 = xor(io.exc_cause_r, _T_329) @[lib.scala 448:21] + node _T_331 = orr(_T_330) @[lib.scala 448:29] + reg _T_332 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_331 : @[Reg.scala 28:19] + _T_332 <= io.exc_cause_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_329 <= _T_332 @[lib.scala 451:16] + io.exc_cause_wb <= _T_329 @[dec_tlu_ctl.scala 3157:65] + node _T_333 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 3158:104] + node _T_334 = and(io.tlu_i0_commit_cmt, _T_333) @[dec_tlu_ctl.scala 3158:102] + wire _T_335 : UInt + _T_335 <= UInt<1>("h00") + node _T_336 = xor(_T_334, _T_335) @[lib.scala 448:21] + node _T_337 = orr(_T_336) @[lib.scala 448:29] + reg _T_338 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_337 : @[Reg.scala 28:19] + _T_338 <= _T_334 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_335 <= _T_338 @[lib.scala 451:16] + io.i0_valid_wb <= _T_335 @[dec_tlu_ctl.scala 3158:71] + wire _T_339 : UInt + _T_339 <= UInt<1>("h00") + node _T_340 = xor(io.i0_trigger_hit_r, _T_339) @[lib.scala 448:21] + node _T_341 = orr(_T_340) @[lib.scala 448:29] + reg _T_342 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_341 : @[Reg.scala 28:19] + _T_342 <= io.i0_trigger_hit_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_339 <= _T_342 @[lib.scala 451:16] + io.trigger_hit_r_d1 <= _T_339 @[dec_tlu_ctl.scala 3159:63] + wire _T_343 : UInt + _T_343 <= UInt<1>("h00") + node _T_344 = xor(io.take_nmi, _T_343) @[lib.scala 448:21] + node _T_345 = orr(_T_344) @[lib.scala 448:29] + reg _T_346 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_345 : @[Reg.scala 28:19] + _T_346 <= io.take_nmi @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_343 <= _T_346 @[lib.scala 451:16] + io.take_nmi_r_d1 <= _T_343 @[dec_tlu_ctl.scala 3160:73] + wire _T_347 : UInt + _T_347 <= UInt<1>("h00") + node _T_348 = xor(io.pause_expired_r, _T_347) @[lib.scala 448:21] + node _T_349 = orr(_T_348) @[lib.scala 448:29] + reg _T_350 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_349 : @[Reg.scala 28:19] + _T_350 <= io.pause_expired_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_347 <= _T_350 @[lib.scala 451:16] + io.pause_expired_wb <= _T_347 @[dec_tlu_ctl.scala 3161:69] + + module perf_mux_and_flops : + input clock : Clock + input reset : AsyncReset + output io : {mhpmc_inc_r : UInt<1>[4], flip mcountinhibit : UInt<7>, flip mhpme_vec : UInt<10>[4], flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip tlu_i0_commit_cmt : UInt<1>, flip illegal_r : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip exu_pmu_i0_br_misp : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip i0_exception_valid_r : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip lsu_pmu_load_external_r : UInt<1>, flip lsu_pmu_store_external_r : UInt<1>, mstatus : UInt<2>, flip mie : UInt<6>, flip ifu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip i0_trigger_hit_r : UInt<1>, flip lsu_exc_valid_r : UInt<1>, flip take_timer_int : UInt<1>, flip take_int_timer0_int : UInt<1>, flip take_int_timer1_int : UInt<1>, flip take_ext_int : UInt<1>, flip tlu_flush_lower_r : UInt<1>, flip dec_tlu_br0_error_r : UInt<1>, flip rfpc_i0_r : UInt<1>, flip dec_tlu_br0_start_error_r : UInt<1>, mcyclel_cout_f : UInt<1>, minstret_enable_f : UInt<1>, minstretl_cout_f : UInt<1>, fw_halted : UInt<1>, meicidpl : UInt<4>, icache_rd_valid_f : UInt<1>, icache_wr_valid_f : UInt<1>, mhpmc_inc_r_d1 : UInt<1>[4], perfcnt_halted_d1 : UInt<1>, mdseac_locked_f : UInt<1>, lsu_single_ecc_error_r_d1 : UInt<1>, lsu_exc_valid_r_d1 : UInt<1>, lsu_i0_exc_r_d1 : UInt<1>, take_ext_int_start_d1 : UInt<1>, take_ext_int_start_d2 : UInt<1>, take_ext_int_start_d3 : UInt<1>, ext_int_freeze_d1 : UInt<1>, mip : UInt<6>, flip mdseac_locked_ns : UInt<1>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_i0_exc_r : UInt<1>, flip take_ext_int_start : UInt<1>, flip ext_int_freeze : UInt<1>, flip mip_ns : UInt<6>, flip mcyclel_cout : UInt<1>, flip wr_mcycleh_r : UInt<1>, flip mcyclel_cout_in : UInt<1>, flip minstret_enable : UInt<1>, flip minstretl_cout_ns : UInt<1>, flip fw_halted_ns : UInt<1>, flip meicidpl_ns : UInt<4>, flip icache_rd_valid : UInt<1>, flip icache_wr_valid : UInt<1>, flip perfcnt_halted : UInt<1>, flip mstatus_ns : UInt<2>, flip scan_mode : UInt<1>, flip free_l2clk : Clock} + + node _T = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] + node _T_1 = mux(_T, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1) @[dec_tlu_ctl.scala 2795:66] + node _T_2 = bits(io.mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2797:57] + node _T_3 = not(_T_2) @[dec_tlu_ctl.scala 2797:40] + node _T_4 = eq(io.mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2798:42] + node _T_5 = bits(_T_4, 0, 0) @[dec_tlu_ctl.scala 2798:70] + node _T_6 = eq(io.mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2799:42] + node _T_7 = bits(_T_6, 0, 0) @[dec_tlu_ctl.scala 2799:70] + node _T_8 = eq(io.mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2800:42] + node _T_9 = bits(_T_8, 0, 0) @[dec_tlu_ctl.scala 2800:70] + node _T_10 = eq(io.mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2801:42] + node _T_11 = bits(_T_10, 0, 0) @[dec_tlu_ctl.scala 2801:70] + node _T_12 = not(io.illegal_r) @[dec_tlu_ctl.scala 2801:104] + node _T_13 = and(io.tlu_i0_commit_cmt, _T_12) @[dec_tlu_ctl.scala 2801:102] + node _T_14 = eq(io.mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2802:42] + node _T_15 = bits(_T_14, 0, 0) @[dec_tlu_ctl.scala 2802:70] + node _T_16 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2802:104] + node _T_17 = and(io.tlu_i0_commit_cmt, _T_16) @[dec_tlu_ctl.scala 2802:102] + node _T_18 = not(io.illegal_r) @[dec_tlu_ctl.scala 2802:125] + node _T_19 = and(_T_17, _T_18) @[dec_tlu_ctl.scala 2802:123] + node _T_20 = eq(io.mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2803:42] + node _T_21 = bits(_T_20, 0, 0) @[dec_tlu_ctl.scala 2803:70] + node _T_22 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2803:102] + node _T_23 = not(io.illegal_r) @[dec_tlu_ctl.scala 2803:125] + node _T_24 = and(_T_22, _T_23) @[dec_tlu_ctl.scala 2803:123] + node _T_25 = eq(io.mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2805:42] + node _T_26 = bits(_T_25, 0, 0) @[dec_tlu_ctl.scala 2805:70] + node _T_27 = eq(io.mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2806:42] + node _T_28 = bits(_T_27, 0, 0) @[dec_tlu_ctl.scala 2806:70] + node _T_29 = eq(io.mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2807:42] + node _T_30 = bits(_T_29, 0, 0) @[dec_tlu_ctl.scala 2807:70] + node _T_31 = eq(io.mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2808:42] + node _T_32 = bits(_T_31, 0, 0) @[dec_tlu_ctl.scala 2808:70] + node _T_33 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2808:99] + node _T_34 = eq(io.mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2809:42] + node _T_35 = bits(_T_34, 0, 0) @[dec_tlu_ctl.scala 2809:70] + node _T_36 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2809:113] + node _T_37 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2809:138] + node _T_38 = and(_T_36, _T_37) @[dec_tlu_ctl.scala 2809:136] + node _T_39 = eq(io.mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2810:42] + node _T_40 = bits(_T_39, 0, 0) @[dec_tlu_ctl.scala 2810:70] + node _T_41 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2810:99] + node _T_42 = eq(io.mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2811:42] + node _T_43 = bits(_T_42, 0, 0) @[dec_tlu_ctl.scala 2811:70] + node _T_44 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2811:99] + node _T_45 = eq(io.mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2812:42] + node _T_46 = bits(_T_45, 0, 0) @[dec_tlu_ctl.scala 2812:70] + node _T_47 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2812:99] + node _T_48 = and(_T_47, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2812:108] + node _T_49 = eq(io.mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2813:42] + node _T_50 = bits(_T_49, 0, 0) @[dec_tlu_ctl.scala 2813:70] + node _T_51 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2813:99] + node _T_52 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2813:150] + node _T_53 = and(_T_51, _T_52) @[dec_tlu_ctl.scala 2813:109] + node _T_54 = eq(io.mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2815:42] + node _T_55 = bits(_T_54, 0, 0) @[dec_tlu_ctl.scala 2815:67] + node _T_56 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2815:97] + node _T_57 = eq(io.mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2816:42] + node _T_58 = bits(_T_57, 0, 0) @[dec_tlu_ctl.scala 2816:67] + node _T_59 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2816:97] + node _T_60 = eq(io.mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2817:42] + node _T_61 = bits(_T_60, 0, 0) @[dec_tlu_ctl.scala 2817:67] + node _T_62 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2817:97] + node _T_63 = eq(io.mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2818:42] + node _T_64 = bits(_T_63, 0, 0) @[dec_tlu_ctl.scala 2818:67] + node _T_65 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2818:97] + node _T_66 = eq(io.mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2819:42] + node _T_67 = bits(_T_66, 0, 0) @[dec_tlu_ctl.scala 2819:67] + node _T_68 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2819:97] + node _T_69 = eq(io.mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2820:42] + node _T_70 = bits(_T_69, 0, 0) @[dec_tlu_ctl.scala 2820:67] + node _T_71 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2820:97] + node _T_72 = eq(io.mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2821:42] + node _T_73 = bits(_T_72, 0, 0) @[dec_tlu_ctl.scala 2821:67] + node _T_74 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2821:97] + node _T_75 = eq(io.mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2822:42] + node _T_76 = bits(_T_75, 0, 0) @[dec_tlu_ctl.scala 2822:67] + node _T_77 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2822:97] + node _T_78 = eq(io.mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2823:42] + node _T_79 = bits(_T_78, 0, 0) @[dec_tlu_ctl.scala 2823:67] + node _T_80 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2823:97] + node _T_81 = eq(io.mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2824:42] + node _T_82 = bits(_T_81, 0, 0) @[dec_tlu_ctl.scala 2824:67] + node _T_83 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2824:97] + node _T_84 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2824:130] + node _T_85 = or(_T_83, _T_84) @[dec_tlu_ctl.scala 2824:109] + node _T_86 = eq(io.mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2826:42] + node _T_87 = bits(_T_86, 0, 0) @[dec_tlu_ctl.scala 2826:70] + node _T_88 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2826:103] + node _T_89 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2826:128] + node _T_90 = and(_T_88, _T_89) @[dec_tlu_ctl.scala 2826:126] + node _T_91 = eq(io.mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2827:42] + node _T_92 = bits(_T_91, 0, 0) @[dec_tlu_ctl.scala 2827:70] + node _T_93 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2827:105] + node _T_94 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2827:130] + node _T_95 = and(_T_93, _T_94) @[dec_tlu_ctl.scala 2827:128] + node _T_96 = eq(io.mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2828:42] + node _T_97 = bits(_T_96, 0, 0) @[dec_tlu_ctl.scala 2828:70] + node _T_98 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2828:118] + node _T_99 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2828:143] + node _T_100 = and(_T_98, _T_99) @[dec_tlu_ctl.scala 2828:141] + node _T_101 = eq(io.mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2829:42] + node _T_102 = bits(_T_101, 0, 0) @[dec_tlu_ctl.scala 2829:70] + node _T_103 = eq(io.mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2830:42] + node _T_104 = bits(_T_103, 0, 0) @[dec_tlu_ctl.scala 2830:70] + node _T_105 = eq(io.mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2831:42] + node _T_106 = bits(_T_105, 0, 0) @[dec_tlu_ctl.scala 2831:70] + node _T_107 = eq(io.mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2832:42] + node _T_108 = bits(_T_107, 0, 0) @[dec_tlu_ctl.scala 2832:70] + node _T_109 = eq(io.mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2833:42] + node _T_110 = bits(_T_109, 0, 0) @[dec_tlu_ctl.scala 2833:70] + node _T_111 = eq(io.mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2834:42] + node _T_112 = bits(_T_111, 0, 0) @[dec_tlu_ctl.scala 2834:70] + node _T_113 = eq(io.mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2835:42] + node _T_114 = bits(_T_113, 0, 0) @[dec_tlu_ctl.scala 2835:70] + node _T_115 = eq(io.mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2836:42] + node _T_116 = bits(_T_115, 0, 0) @[dec_tlu_ctl.scala 2836:70] + node _T_117 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2836:106] + node _T_118 = or(_T_117, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2836:128] + node _T_119 = eq(io.mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2837:42] + node _T_120 = bits(_T_119, 0, 0) @[dec_tlu_ctl.scala 2837:70] + node _T_121 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2837:100] + node _T_122 = or(_T_121, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2837:125] + node _T_123 = eq(io.mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2838:42] + node _T_124 = bits(_T_123, 0, 0) @[dec_tlu_ctl.scala 2838:70] + node _T_125 = eq(io.mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2839:42] + node _T_126 = bits(_T_125, 0, 0) @[dec_tlu_ctl.scala 2839:70] + node _T_127 = eq(io.mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2840:42] + node _T_128 = bits(_T_127, 0, 0) @[dec_tlu_ctl.scala 2840:70] + node _T_129 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2840:105] + node _T_130 = and(_T_129, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2840:137] + node _T_131 = eq(io.mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2842:42] + node _T_132 = bits(_T_131, 0, 0) @[dec_tlu_ctl.scala 2842:70] + node _T_133 = eq(io.mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2843:42] + node _T_134 = bits(_T_133, 0, 0) @[dec_tlu_ctl.scala 2843:70] + node _T_135 = eq(io.mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2844:42] + node _T_136 = bits(_T_135, 0, 0) @[dec_tlu_ctl.scala 2844:70] + node _T_137 = eq(io.mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2845:42] + node _T_138 = bits(_T_137, 0, 0) @[dec_tlu_ctl.scala 2845:70] + node _T_139 = eq(io.mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2846:42] + node _T_140 = bits(_T_139, 0, 0) @[dec_tlu_ctl.scala 2846:70] + node _T_141 = eq(io.mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2847:42] + node _T_142 = bits(_T_141, 0, 0) @[dec_tlu_ctl.scala 2847:70] + node _T_143 = eq(io.mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2848:42] + node _T_144 = bits(_T_143, 0, 0) @[dec_tlu_ctl.scala 2848:70] + node _T_145 = eq(io.mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2849:42] + node _T_146 = bits(_T_145, 0, 0) @[dec_tlu_ctl.scala 2849:70] + node _T_147 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2849:92] + node _T_148 = bits(_T_147, 0, 0) @[dec_tlu_ctl.scala 2849:92] + node _T_149 = not(_T_148) @[dec_tlu_ctl.scala 2849:81] + node _T_150 = eq(io.mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2850:42] + node _T_151 = bits(_T_150, 0, 0) @[dec_tlu_ctl.scala 2850:70] + node _T_152 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2850:92] + node _T_153 = bits(_T_152, 0, 0) @[dec_tlu_ctl.scala 2850:92] + node _T_154 = not(_T_153) @[dec_tlu_ctl.scala 2850:81] + node _T_155 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2850:115] + node _T_156 = bits(io.mie, 5, 0) @[dec_tlu_ctl.scala 2850:129] + node _T_157 = and(_T_155, _T_156) @[dec_tlu_ctl.scala 2850:121] + node _T_158 = orr(_T_157) @[dec_tlu_ctl.scala 2850:136] + node _T_159 = and(_T_154, _T_158) @[dec_tlu_ctl.scala 2850:106] + node _T_160 = eq(io.mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2851:42] + node _T_161 = bits(_T_160, 0, 0) @[dec_tlu_ctl.scala 2851:70] + node _T_162 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2851:99] + node _T_163 = eq(io.mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2852:42] + node _T_164 = bits(_T_163, 0, 0) @[dec_tlu_ctl.scala 2852:70] + node _T_165 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2852:102] + node _T_166 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2852:133] + node _T_167 = and(_T_165, _T_166) @[dec_tlu_ctl.scala 2852:131] + node _T_168 = eq(io.mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2853:42] + node _T_169 = bits(_T_168, 0, 0) @[dec_tlu_ctl.scala 2853:70] + node _T_170 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2853:102] + node _T_171 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2853:134] + node _T_172 = and(_T_170, _T_171) @[dec_tlu_ctl.scala 2853:132] + node _T_173 = eq(io.mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2855:42] + node _T_174 = bits(_T_173, 0, 0) @[dec_tlu_ctl.scala 2855:70] + node _T_175 = eq(io.mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2856:42] + node _T_176 = bits(_T_175, 0, 0) @[dec_tlu_ctl.scala 2856:70] + node _T_177 = eq(io.mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2857:42] + node _T_178 = bits(_T_177, 0, 0) @[dec_tlu_ctl.scala 2857:70] + node _T_179 = eq(io.mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2858:42] + node _T_180 = bits(_T_179, 0, 0) @[dec_tlu_ctl.scala 2858:70] + node _T_181 = eq(io.mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2859:42] + node _T_182 = bits(_T_181, 0, 0) @[dec_tlu_ctl.scala 2859:70] + node _T_183 = mux(_T_5, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_184 = mux(_T_7, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_185 = mux(_T_9, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_186 = mux(_T_11, _T_13, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_187 = mux(_T_15, _T_19, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_188 = mux(_T_21, _T_24, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_189 = mux(_T_26, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_190 = mux(_T_28, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_191 = mux(_T_30, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_192 = mux(_T_32, _T_33, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_193 = mux(_T_35, _T_38, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_194 = mux(_T_40, _T_41, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_195 = mux(_T_43, _T_44, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_196 = mux(_T_46, _T_48, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_197 = mux(_T_50, _T_53, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_198 = mux(_T_55, _T_56, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_199 = mux(_T_58, _T_59, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_200 = mux(_T_61, _T_62, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_201 = mux(_T_64, _T_65, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_202 = mux(_T_67, _T_68, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_203 = mux(_T_70, _T_71, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_204 = mux(_T_73, _T_74, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_205 = mux(_T_76, _T_77, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_206 = mux(_T_79, _T_80, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_207 = mux(_T_82, _T_85, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_208 = mux(_T_87, _T_90, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_209 = mux(_T_92, _T_95, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_210 = mux(_T_97, _T_100, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_211 = mux(_T_102, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_212 = mux(_T_104, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_213 = mux(_T_106, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_214 = mux(_T_108, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_215 = mux(_T_110, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_216 = mux(_T_112, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_217 = mux(_T_114, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_218 = mux(_T_116, _T_118, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_219 = mux(_T_120, _T_122, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_220 = mux(_T_124, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_221 = mux(_T_126, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_222 = mux(_T_128, _T_130, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_223 = mux(_T_132, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_224 = mux(_T_134, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_225 = mux(_T_136, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_226 = mux(_T_138, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_227 = mux(_T_140, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_228 = mux(_T_142, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_229 = mux(_T_144, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_230 = mux(_T_146, _T_149, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_231 = mux(_T_151, _T_159, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_232 = mux(_T_161, _T_162, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_233 = mux(_T_164, _T_167, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_234 = mux(_T_169, _T_172, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_235 = mux(_T_174, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_236 = mux(_T_176, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_237 = mux(_T_178, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_238 = mux(_T_180, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_239 = mux(_T_182, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_240 = or(_T_183, _T_184) @[Mux.scala 27:72] + node _T_241 = or(_T_240, _T_185) @[Mux.scala 27:72] + node _T_242 = or(_T_241, _T_186) @[Mux.scala 27:72] + node _T_243 = or(_T_242, _T_187) @[Mux.scala 27:72] + node _T_244 = or(_T_243, _T_188) @[Mux.scala 27:72] + node _T_245 = or(_T_244, _T_189) @[Mux.scala 27:72] + node _T_246 = or(_T_245, _T_190) @[Mux.scala 27:72] + node _T_247 = or(_T_246, _T_191) @[Mux.scala 27:72] + node _T_248 = or(_T_247, _T_192) @[Mux.scala 27:72] + node _T_249 = or(_T_248, _T_193) @[Mux.scala 27:72] + node _T_250 = or(_T_249, _T_194) @[Mux.scala 27:72] + node _T_251 = or(_T_250, _T_195) @[Mux.scala 27:72] + node _T_252 = or(_T_251, _T_196) @[Mux.scala 27:72] + node _T_253 = or(_T_252, _T_197) @[Mux.scala 27:72] + node _T_254 = or(_T_253, _T_198) @[Mux.scala 27:72] + node _T_255 = or(_T_254, _T_199) @[Mux.scala 27:72] + node _T_256 = or(_T_255, _T_200) @[Mux.scala 27:72] + node _T_257 = or(_T_256, _T_201) @[Mux.scala 27:72] + node _T_258 = or(_T_257, _T_202) @[Mux.scala 27:72] + node _T_259 = or(_T_258, _T_203) @[Mux.scala 27:72] + node _T_260 = or(_T_259, _T_204) @[Mux.scala 27:72] + node _T_261 = or(_T_260, _T_205) @[Mux.scala 27:72] + node _T_262 = or(_T_261, _T_206) @[Mux.scala 27:72] + node _T_263 = or(_T_262, _T_207) @[Mux.scala 27:72] + node _T_264 = or(_T_263, _T_208) @[Mux.scala 27:72] + node _T_265 = or(_T_264, _T_209) @[Mux.scala 27:72] + node _T_266 = or(_T_265, _T_210) @[Mux.scala 27:72] + node _T_267 = or(_T_266, _T_211) @[Mux.scala 27:72] + node _T_268 = or(_T_267, _T_212) @[Mux.scala 27:72] + node _T_269 = or(_T_268, _T_213) @[Mux.scala 27:72] + node _T_270 = or(_T_269, _T_214) @[Mux.scala 27:72] + node _T_271 = or(_T_270, _T_215) @[Mux.scala 27:72] + node _T_272 = or(_T_271, _T_216) @[Mux.scala 27:72] + node _T_273 = or(_T_272, _T_217) @[Mux.scala 27:72] + node _T_274 = or(_T_273, _T_218) @[Mux.scala 27:72] + node _T_275 = or(_T_274, _T_219) @[Mux.scala 27:72] + node _T_276 = or(_T_275, _T_220) @[Mux.scala 27:72] + node _T_277 = or(_T_276, _T_221) @[Mux.scala 27:72] + node _T_278 = or(_T_277, _T_222) @[Mux.scala 27:72] + node _T_279 = or(_T_278, _T_223) @[Mux.scala 27:72] + node _T_280 = or(_T_279, _T_224) @[Mux.scala 27:72] + node _T_281 = or(_T_280, _T_225) @[Mux.scala 27:72] + node _T_282 = or(_T_281, _T_226) @[Mux.scala 27:72] + node _T_283 = or(_T_282, _T_227) @[Mux.scala 27:72] + node _T_284 = or(_T_283, _T_228) @[Mux.scala 27:72] + node _T_285 = or(_T_284, _T_229) @[Mux.scala 27:72] + node _T_286 = or(_T_285, _T_230) @[Mux.scala 27:72] + node _T_287 = or(_T_286, _T_231) @[Mux.scala 27:72] + node _T_288 = or(_T_287, _T_232) @[Mux.scala 27:72] + node _T_289 = or(_T_288, _T_233) @[Mux.scala 27:72] + node _T_290 = or(_T_289, _T_234) @[Mux.scala 27:72] + node _T_291 = or(_T_290, _T_235) @[Mux.scala 27:72] + node _T_292 = or(_T_291, _T_236) @[Mux.scala 27:72] + node _T_293 = or(_T_292, _T_237) @[Mux.scala 27:72] + node _T_294 = or(_T_293, _T_238) @[Mux.scala 27:72] + node _T_295 = or(_T_294, _T_239) @[Mux.scala 27:72] + wire _T_296 : UInt<1> @[Mux.scala 27:72] + _T_296 <= _T_295 @[Mux.scala 27:72] + node _T_297 = and(_T_3, _T_296) @[dec_tlu_ctl.scala 2797:63] + io.mhpmc_inc_r[0] <= _T_297 @[dec_tlu_ctl.scala 2797:35] + node _T_298 = bits(io.mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2797:57] + node _T_299 = not(_T_298) @[dec_tlu_ctl.scala 2797:40] + node _T_300 = eq(io.mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2798:42] + node _T_301 = bits(_T_300, 0, 0) @[dec_tlu_ctl.scala 2798:70] + node _T_302 = eq(io.mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2799:42] + node _T_303 = bits(_T_302, 0, 0) @[dec_tlu_ctl.scala 2799:70] + node _T_304 = eq(io.mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2800:42] + node _T_305 = bits(_T_304, 0, 0) @[dec_tlu_ctl.scala 2800:70] + node _T_306 = eq(io.mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2801:42] + node _T_307 = bits(_T_306, 0, 0) @[dec_tlu_ctl.scala 2801:70] + node _T_308 = not(io.illegal_r) @[dec_tlu_ctl.scala 2801:104] + node _T_309 = and(io.tlu_i0_commit_cmt, _T_308) @[dec_tlu_ctl.scala 2801:102] + node _T_310 = eq(io.mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2802:42] + node _T_311 = bits(_T_310, 0, 0) @[dec_tlu_ctl.scala 2802:70] + node _T_312 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2802:104] + node _T_313 = and(io.tlu_i0_commit_cmt, _T_312) @[dec_tlu_ctl.scala 2802:102] + node _T_314 = not(io.illegal_r) @[dec_tlu_ctl.scala 2802:125] + node _T_315 = and(_T_313, _T_314) @[dec_tlu_ctl.scala 2802:123] + node _T_316 = eq(io.mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2803:42] + node _T_317 = bits(_T_316, 0, 0) @[dec_tlu_ctl.scala 2803:70] + node _T_318 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2803:102] + node _T_319 = not(io.illegal_r) @[dec_tlu_ctl.scala 2803:125] + node _T_320 = and(_T_318, _T_319) @[dec_tlu_ctl.scala 2803:123] + node _T_321 = eq(io.mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2805:42] + node _T_322 = bits(_T_321, 0, 0) @[dec_tlu_ctl.scala 2805:70] + node _T_323 = eq(io.mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2806:42] + node _T_324 = bits(_T_323, 0, 0) @[dec_tlu_ctl.scala 2806:70] + node _T_325 = eq(io.mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2807:42] + node _T_326 = bits(_T_325, 0, 0) @[dec_tlu_ctl.scala 2807:70] + node _T_327 = eq(io.mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2808:42] + node _T_328 = bits(_T_327, 0, 0) @[dec_tlu_ctl.scala 2808:70] + node _T_329 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2808:99] + node _T_330 = eq(io.mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2809:42] + node _T_331 = bits(_T_330, 0, 0) @[dec_tlu_ctl.scala 2809:70] + node _T_332 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2809:113] + node _T_333 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2809:138] + node _T_334 = and(_T_332, _T_333) @[dec_tlu_ctl.scala 2809:136] + node _T_335 = eq(io.mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2810:42] + node _T_336 = bits(_T_335, 0, 0) @[dec_tlu_ctl.scala 2810:70] + node _T_337 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2810:99] + node _T_338 = eq(io.mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2811:42] + node _T_339 = bits(_T_338, 0, 0) @[dec_tlu_ctl.scala 2811:70] + node _T_340 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2811:99] + node _T_341 = eq(io.mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2812:42] + node _T_342 = bits(_T_341, 0, 0) @[dec_tlu_ctl.scala 2812:70] + node _T_343 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2812:99] + node _T_344 = and(_T_343, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2812:108] + node _T_345 = eq(io.mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2813:42] + node _T_346 = bits(_T_345, 0, 0) @[dec_tlu_ctl.scala 2813:70] + node _T_347 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2813:99] + node _T_348 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2813:150] + node _T_349 = and(_T_347, _T_348) @[dec_tlu_ctl.scala 2813:109] + node _T_350 = eq(io.mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2815:42] + node _T_351 = bits(_T_350, 0, 0) @[dec_tlu_ctl.scala 2815:67] + node _T_352 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2815:97] + node _T_353 = eq(io.mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2816:42] + node _T_354 = bits(_T_353, 0, 0) @[dec_tlu_ctl.scala 2816:67] + node _T_355 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2816:97] + node _T_356 = eq(io.mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2817:42] + node _T_357 = bits(_T_356, 0, 0) @[dec_tlu_ctl.scala 2817:67] + node _T_358 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2817:97] + node _T_359 = eq(io.mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2818:42] + node _T_360 = bits(_T_359, 0, 0) @[dec_tlu_ctl.scala 2818:67] + node _T_361 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2818:97] + node _T_362 = eq(io.mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2819:42] + node _T_363 = bits(_T_362, 0, 0) @[dec_tlu_ctl.scala 2819:67] + node _T_364 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2819:97] + node _T_365 = eq(io.mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2820:42] + node _T_366 = bits(_T_365, 0, 0) @[dec_tlu_ctl.scala 2820:67] + node _T_367 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2820:97] + node _T_368 = eq(io.mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2821:42] + node _T_369 = bits(_T_368, 0, 0) @[dec_tlu_ctl.scala 2821:67] + node _T_370 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2821:97] + node _T_371 = eq(io.mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2822:42] + node _T_372 = bits(_T_371, 0, 0) @[dec_tlu_ctl.scala 2822:67] + node _T_373 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2822:97] + node _T_374 = eq(io.mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2823:42] + node _T_375 = bits(_T_374, 0, 0) @[dec_tlu_ctl.scala 2823:67] + node _T_376 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2823:97] + node _T_377 = eq(io.mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2824:42] + node _T_378 = bits(_T_377, 0, 0) @[dec_tlu_ctl.scala 2824:67] + node _T_379 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2824:97] + node _T_380 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2824:130] + node _T_381 = or(_T_379, _T_380) @[dec_tlu_ctl.scala 2824:109] + node _T_382 = eq(io.mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2826:42] + node _T_383 = bits(_T_382, 0, 0) @[dec_tlu_ctl.scala 2826:70] + node _T_384 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2826:103] + node _T_385 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2826:128] + node _T_386 = and(_T_384, _T_385) @[dec_tlu_ctl.scala 2826:126] + node _T_387 = eq(io.mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2827:42] + node _T_388 = bits(_T_387, 0, 0) @[dec_tlu_ctl.scala 2827:70] + node _T_389 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2827:105] + node _T_390 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2827:130] + node _T_391 = and(_T_389, _T_390) @[dec_tlu_ctl.scala 2827:128] + node _T_392 = eq(io.mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2828:42] + node _T_393 = bits(_T_392, 0, 0) @[dec_tlu_ctl.scala 2828:70] + node _T_394 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2828:118] + node _T_395 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2828:143] + node _T_396 = and(_T_394, _T_395) @[dec_tlu_ctl.scala 2828:141] + node _T_397 = eq(io.mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2829:42] + node _T_398 = bits(_T_397, 0, 0) @[dec_tlu_ctl.scala 2829:70] + node _T_399 = eq(io.mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2830:42] + node _T_400 = bits(_T_399, 0, 0) @[dec_tlu_ctl.scala 2830:70] + node _T_401 = eq(io.mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2831:42] + node _T_402 = bits(_T_401, 0, 0) @[dec_tlu_ctl.scala 2831:70] + node _T_403 = eq(io.mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2832:42] + node _T_404 = bits(_T_403, 0, 0) @[dec_tlu_ctl.scala 2832:70] + node _T_405 = eq(io.mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2833:42] + node _T_406 = bits(_T_405, 0, 0) @[dec_tlu_ctl.scala 2833:70] + node _T_407 = eq(io.mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2834:42] + node _T_408 = bits(_T_407, 0, 0) @[dec_tlu_ctl.scala 2834:70] + node _T_409 = eq(io.mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2835:42] + node _T_410 = bits(_T_409, 0, 0) @[dec_tlu_ctl.scala 2835:70] + node _T_411 = eq(io.mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2836:42] + node _T_412 = bits(_T_411, 0, 0) @[dec_tlu_ctl.scala 2836:70] + node _T_413 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2836:106] + node _T_414 = or(_T_413, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2836:128] + node _T_415 = eq(io.mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2837:42] + node _T_416 = bits(_T_415, 0, 0) @[dec_tlu_ctl.scala 2837:70] + node _T_417 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2837:100] + node _T_418 = or(_T_417, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2837:125] + node _T_419 = eq(io.mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2838:42] + node _T_420 = bits(_T_419, 0, 0) @[dec_tlu_ctl.scala 2838:70] + node _T_421 = eq(io.mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2839:42] + node _T_422 = bits(_T_421, 0, 0) @[dec_tlu_ctl.scala 2839:70] + node _T_423 = eq(io.mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2840:42] + node _T_424 = bits(_T_423, 0, 0) @[dec_tlu_ctl.scala 2840:70] + node _T_425 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2840:105] + node _T_426 = and(_T_425, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2840:137] + node _T_427 = eq(io.mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2842:42] + node _T_428 = bits(_T_427, 0, 0) @[dec_tlu_ctl.scala 2842:70] + node _T_429 = eq(io.mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2843:42] + node _T_430 = bits(_T_429, 0, 0) @[dec_tlu_ctl.scala 2843:70] + node _T_431 = eq(io.mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2844:42] + node _T_432 = bits(_T_431, 0, 0) @[dec_tlu_ctl.scala 2844:70] + node _T_433 = eq(io.mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2845:42] + node _T_434 = bits(_T_433, 0, 0) @[dec_tlu_ctl.scala 2845:70] + node _T_435 = eq(io.mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2846:42] + node _T_436 = bits(_T_435, 0, 0) @[dec_tlu_ctl.scala 2846:70] + node _T_437 = eq(io.mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2847:42] + node _T_438 = bits(_T_437, 0, 0) @[dec_tlu_ctl.scala 2847:70] + node _T_439 = eq(io.mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2848:42] + node _T_440 = bits(_T_439, 0, 0) @[dec_tlu_ctl.scala 2848:70] + node _T_441 = eq(io.mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2849:42] + node _T_442 = bits(_T_441, 0, 0) @[dec_tlu_ctl.scala 2849:70] + node _T_443 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2849:92] + node _T_444 = bits(_T_443, 0, 0) @[dec_tlu_ctl.scala 2849:92] + node _T_445 = not(_T_444) @[dec_tlu_ctl.scala 2849:81] + node _T_446 = eq(io.mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2850:42] + node _T_447 = bits(_T_446, 0, 0) @[dec_tlu_ctl.scala 2850:70] + node _T_448 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2850:92] + node _T_449 = bits(_T_448, 0, 0) @[dec_tlu_ctl.scala 2850:92] + node _T_450 = not(_T_449) @[dec_tlu_ctl.scala 2850:81] + node _T_451 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2850:115] + node _T_452 = bits(io.mie, 5, 0) @[dec_tlu_ctl.scala 2850:129] + node _T_453 = and(_T_451, _T_452) @[dec_tlu_ctl.scala 2850:121] + node _T_454 = orr(_T_453) @[dec_tlu_ctl.scala 2850:136] + node _T_455 = and(_T_450, _T_454) @[dec_tlu_ctl.scala 2850:106] + node _T_456 = eq(io.mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2851:42] + node _T_457 = bits(_T_456, 0, 0) @[dec_tlu_ctl.scala 2851:70] + node _T_458 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2851:99] + node _T_459 = eq(io.mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2852:42] + node _T_460 = bits(_T_459, 0, 0) @[dec_tlu_ctl.scala 2852:70] + node _T_461 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2852:102] + node _T_462 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2852:133] + node _T_463 = and(_T_461, _T_462) @[dec_tlu_ctl.scala 2852:131] + node _T_464 = eq(io.mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2853:42] + node _T_465 = bits(_T_464, 0, 0) @[dec_tlu_ctl.scala 2853:70] + node _T_466 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2853:102] + node _T_467 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2853:134] + node _T_468 = and(_T_466, _T_467) @[dec_tlu_ctl.scala 2853:132] + node _T_469 = eq(io.mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2855:42] + node _T_470 = bits(_T_469, 0, 0) @[dec_tlu_ctl.scala 2855:70] + node _T_471 = eq(io.mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2856:42] + node _T_472 = bits(_T_471, 0, 0) @[dec_tlu_ctl.scala 2856:70] + node _T_473 = eq(io.mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2857:42] + node _T_474 = bits(_T_473, 0, 0) @[dec_tlu_ctl.scala 2857:70] + node _T_475 = eq(io.mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2858:42] + node _T_476 = bits(_T_475, 0, 0) @[dec_tlu_ctl.scala 2858:70] + node _T_477 = eq(io.mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2859:42] + node _T_478 = bits(_T_477, 0, 0) @[dec_tlu_ctl.scala 2859:70] + node _T_479 = mux(_T_301, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_480 = mux(_T_303, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_481 = mux(_T_305, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_482 = mux(_T_307, _T_309, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_483 = mux(_T_311, _T_315, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_484 = mux(_T_317, _T_320, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_485 = mux(_T_322, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_486 = mux(_T_324, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_487 = mux(_T_326, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_488 = mux(_T_328, _T_329, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_489 = mux(_T_331, _T_334, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_490 = mux(_T_336, _T_337, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_491 = mux(_T_339, _T_340, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_492 = mux(_T_342, _T_344, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_493 = mux(_T_346, _T_349, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_494 = mux(_T_351, _T_352, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_495 = mux(_T_354, _T_355, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_496 = mux(_T_357, _T_358, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_497 = mux(_T_360, _T_361, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_498 = mux(_T_363, _T_364, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_499 = mux(_T_366, _T_367, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_500 = mux(_T_369, _T_370, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_501 = mux(_T_372, _T_373, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_502 = mux(_T_375, _T_376, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_503 = mux(_T_378, _T_381, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_504 = mux(_T_383, _T_386, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_505 = mux(_T_388, _T_391, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_506 = mux(_T_393, _T_396, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_507 = mux(_T_398, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_508 = mux(_T_400, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_509 = mux(_T_402, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_510 = mux(_T_404, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_511 = mux(_T_406, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_512 = mux(_T_408, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_513 = mux(_T_410, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_514 = mux(_T_412, _T_414, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_515 = mux(_T_416, _T_418, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_516 = mux(_T_420, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_517 = mux(_T_422, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_518 = mux(_T_424, _T_426, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_519 = mux(_T_428, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_520 = mux(_T_430, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_521 = mux(_T_432, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_522 = mux(_T_434, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_523 = mux(_T_436, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_524 = mux(_T_438, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_525 = mux(_T_440, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_526 = mux(_T_442, _T_445, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_527 = mux(_T_447, _T_455, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_528 = mux(_T_457, _T_458, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_529 = mux(_T_460, _T_463, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_530 = mux(_T_465, _T_468, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_531 = mux(_T_470, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_532 = mux(_T_472, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_533 = mux(_T_474, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_534 = mux(_T_476, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_535 = mux(_T_478, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_536 = or(_T_479, _T_480) @[Mux.scala 27:72] + node _T_537 = or(_T_536, _T_481) @[Mux.scala 27:72] + node _T_538 = or(_T_537, _T_482) @[Mux.scala 27:72] + node _T_539 = or(_T_538, _T_483) @[Mux.scala 27:72] + node _T_540 = or(_T_539, _T_484) @[Mux.scala 27:72] + node _T_541 = or(_T_540, _T_485) @[Mux.scala 27:72] + node _T_542 = or(_T_541, _T_486) @[Mux.scala 27:72] + node _T_543 = or(_T_542, _T_487) @[Mux.scala 27:72] + node _T_544 = or(_T_543, _T_488) @[Mux.scala 27:72] + node _T_545 = or(_T_544, _T_489) @[Mux.scala 27:72] + node _T_546 = or(_T_545, _T_490) @[Mux.scala 27:72] + node _T_547 = or(_T_546, _T_491) @[Mux.scala 27:72] + node _T_548 = or(_T_547, _T_492) @[Mux.scala 27:72] + node _T_549 = or(_T_548, _T_493) @[Mux.scala 27:72] + node _T_550 = or(_T_549, _T_494) @[Mux.scala 27:72] + node _T_551 = or(_T_550, _T_495) @[Mux.scala 27:72] + node _T_552 = or(_T_551, _T_496) @[Mux.scala 27:72] + node _T_553 = or(_T_552, _T_497) @[Mux.scala 27:72] + node _T_554 = or(_T_553, _T_498) @[Mux.scala 27:72] + node _T_555 = or(_T_554, _T_499) @[Mux.scala 27:72] + node _T_556 = or(_T_555, _T_500) @[Mux.scala 27:72] + node _T_557 = or(_T_556, _T_501) @[Mux.scala 27:72] + node _T_558 = or(_T_557, _T_502) @[Mux.scala 27:72] + node _T_559 = or(_T_558, _T_503) @[Mux.scala 27:72] + node _T_560 = or(_T_559, _T_504) @[Mux.scala 27:72] + node _T_561 = or(_T_560, _T_505) @[Mux.scala 27:72] + node _T_562 = or(_T_561, _T_506) @[Mux.scala 27:72] + node _T_563 = or(_T_562, _T_507) @[Mux.scala 27:72] + node _T_564 = or(_T_563, _T_508) @[Mux.scala 27:72] + node _T_565 = or(_T_564, _T_509) @[Mux.scala 27:72] + node _T_566 = or(_T_565, _T_510) @[Mux.scala 27:72] + node _T_567 = or(_T_566, _T_511) @[Mux.scala 27:72] + node _T_568 = or(_T_567, _T_512) @[Mux.scala 27:72] + node _T_569 = or(_T_568, _T_513) @[Mux.scala 27:72] + node _T_570 = or(_T_569, _T_514) @[Mux.scala 27:72] + node _T_571 = or(_T_570, _T_515) @[Mux.scala 27:72] + node _T_572 = or(_T_571, _T_516) @[Mux.scala 27:72] + node _T_573 = or(_T_572, _T_517) @[Mux.scala 27:72] + node _T_574 = or(_T_573, _T_518) @[Mux.scala 27:72] + node _T_575 = or(_T_574, _T_519) @[Mux.scala 27:72] + node _T_576 = or(_T_575, _T_520) @[Mux.scala 27:72] + node _T_577 = or(_T_576, _T_521) @[Mux.scala 27:72] + node _T_578 = or(_T_577, _T_522) @[Mux.scala 27:72] + node _T_579 = or(_T_578, _T_523) @[Mux.scala 27:72] + node _T_580 = or(_T_579, _T_524) @[Mux.scala 27:72] + node _T_581 = or(_T_580, _T_525) @[Mux.scala 27:72] + node _T_582 = or(_T_581, _T_526) @[Mux.scala 27:72] + node _T_583 = or(_T_582, _T_527) @[Mux.scala 27:72] + node _T_584 = or(_T_583, _T_528) @[Mux.scala 27:72] + node _T_585 = or(_T_584, _T_529) @[Mux.scala 27:72] + node _T_586 = or(_T_585, _T_530) @[Mux.scala 27:72] + node _T_587 = or(_T_586, _T_531) @[Mux.scala 27:72] + node _T_588 = or(_T_587, _T_532) @[Mux.scala 27:72] + node _T_589 = or(_T_588, _T_533) @[Mux.scala 27:72] + node _T_590 = or(_T_589, _T_534) @[Mux.scala 27:72] + node _T_591 = or(_T_590, _T_535) @[Mux.scala 27:72] + wire _T_592 : UInt<1> @[Mux.scala 27:72] + _T_592 <= _T_591 @[Mux.scala 27:72] + node _T_593 = and(_T_299, _T_592) @[dec_tlu_ctl.scala 2797:63] + io.mhpmc_inc_r[1] <= _T_593 @[dec_tlu_ctl.scala 2797:35] + node _T_594 = bits(io.mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2797:57] + node _T_595 = not(_T_594) @[dec_tlu_ctl.scala 2797:40] + node _T_596 = eq(io.mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2798:42] + node _T_597 = bits(_T_596, 0, 0) @[dec_tlu_ctl.scala 2798:70] + node _T_598 = eq(io.mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2799:42] + node _T_599 = bits(_T_598, 0, 0) @[dec_tlu_ctl.scala 2799:70] + node _T_600 = eq(io.mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2800:42] + node _T_601 = bits(_T_600, 0, 0) @[dec_tlu_ctl.scala 2800:70] + node _T_602 = eq(io.mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2801:42] + node _T_603 = bits(_T_602, 0, 0) @[dec_tlu_ctl.scala 2801:70] + node _T_604 = not(io.illegal_r) @[dec_tlu_ctl.scala 2801:104] + node _T_605 = and(io.tlu_i0_commit_cmt, _T_604) @[dec_tlu_ctl.scala 2801:102] + node _T_606 = eq(io.mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2802:42] + node _T_607 = bits(_T_606, 0, 0) @[dec_tlu_ctl.scala 2802:70] + node _T_608 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2802:104] + node _T_609 = and(io.tlu_i0_commit_cmt, _T_608) @[dec_tlu_ctl.scala 2802:102] + node _T_610 = not(io.illegal_r) @[dec_tlu_ctl.scala 2802:125] + node _T_611 = and(_T_609, _T_610) @[dec_tlu_ctl.scala 2802:123] + node _T_612 = eq(io.mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2803:42] + node _T_613 = bits(_T_612, 0, 0) @[dec_tlu_ctl.scala 2803:70] + node _T_614 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2803:102] + node _T_615 = not(io.illegal_r) @[dec_tlu_ctl.scala 2803:125] + node _T_616 = and(_T_614, _T_615) @[dec_tlu_ctl.scala 2803:123] + node _T_617 = eq(io.mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2805:42] + node _T_618 = bits(_T_617, 0, 0) @[dec_tlu_ctl.scala 2805:70] + node _T_619 = eq(io.mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2806:42] + node _T_620 = bits(_T_619, 0, 0) @[dec_tlu_ctl.scala 2806:70] + node _T_621 = eq(io.mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2807:42] + node _T_622 = bits(_T_621, 0, 0) @[dec_tlu_ctl.scala 2807:70] + node _T_623 = eq(io.mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2808:42] + node _T_624 = bits(_T_623, 0, 0) @[dec_tlu_ctl.scala 2808:70] + node _T_625 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2808:99] + node _T_626 = eq(io.mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2809:42] + node _T_627 = bits(_T_626, 0, 0) @[dec_tlu_ctl.scala 2809:70] + node _T_628 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2809:113] + node _T_629 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2809:138] + node _T_630 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 2809:136] + node _T_631 = eq(io.mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2810:42] + node _T_632 = bits(_T_631, 0, 0) @[dec_tlu_ctl.scala 2810:70] + node _T_633 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2810:99] + node _T_634 = eq(io.mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2811:42] + node _T_635 = bits(_T_634, 0, 0) @[dec_tlu_ctl.scala 2811:70] + node _T_636 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2811:99] + node _T_637 = eq(io.mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2812:42] + node _T_638 = bits(_T_637, 0, 0) @[dec_tlu_ctl.scala 2812:70] + node _T_639 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2812:99] + node _T_640 = and(_T_639, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2812:108] + node _T_641 = eq(io.mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2813:42] + node _T_642 = bits(_T_641, 0, 0) @[dec_tlu_ctl.scala 2813:70] + node _T_643 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2813:99] + node _T_644 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2813:150] + node _T_645 = and(_T_643, _T_644) @[dec_tlu_ctl.scala 2813:109] + node _T_646 = eq(io.mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2815:42] + node _T_647 = bits(_T_646, 0, 0) @[dec_tlu_ctl.scala 2815:67] + node _T_648 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2815:97] + node _T_649 = eq(io.mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2816:42] + node _T_650 = bits(_T_649, 0, 0) @[dec_tlu_ctl.scala 2816:67] + node _T_651 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2816:97] + node _T_652 = eq(io.mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2817:42] + node _T_653 = bits(_T_652, 0, 0) @[dec_tlu_ctl.scala 2817:67] + node _T_654 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2817:97] + node _T_655 = eq(io.mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2818:42] + node _T_656 = bits(_T_655, 0, 0) @[dec_tlu_ctl.scala 2818:67] + node _T_657 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2818:97] + node _T_658 = eq(io.mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2819:42] + node _T_659 = bits(_T_658, 0, 0) @[dec_tlu_ctl.scala 2819:67] + node _T_660 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2819:97] + node _T_661 = eq(io.mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2820:42] + node _T_662 = bits(_T_661, 0, 0) @[dec_tlu_ctl.scala 2820:67] + node _T_663 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2820:97] + node _T_664 = eq(io.mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2821:42] + node _T_665 = bits(_T_664, 0, 0) @[dec_tlu_ctl.scala 2821:67] + node _T_666 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2821:97] + node _T_667 = eq(io.mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2822:42] + node _T_668 = bits(_T_667, 0, 0) @[dec_tlu_ctl.scala 2822:67] + node _T_669 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2822:97] + node _T_670 = eq(io.mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2823:42] + node _T_671 = bits(_T_670, 0, 0) @[dec_tlu_ctl.scala 2823:67] + node _T_672 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2823:97] + node _T_673 = eq(io.mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2824:42] + node _T_674 = bits(_T_673, 0, 0) @[dec_tlu_ctl.scala 2824:67] + node _T_675 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2824:97] + node _T_676 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2824:130] + node _T_677 = or(_T_675, _T_676) @[dec_tlu_ctl.scala 2824:109] + node _T_678 = eq(io.mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2826:42] + node _T_679 = bits(_T_678, 0, 0) @[dec_tlu_ctl.scala 2826:70] + node _T_680 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2826:103] + node _T_681 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2826:128] + node _T_682 = and(_T_680, _T_681) @[dec_tlu_ctl.scala 2826:126] + node _T_683 = eq(io.mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2827:42] + node _T_684 = bits(_T_683, 0, 0) @[dec_tlu_ctl.scala 2827:70] + node _T_685 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2827:105] + node _T_686 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2827:130] + node _T_687 = and(_T_685, _T_686) @[dec_tlu_ctl.scala 2827:128] + node _T_688 = eq(io.mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2828:42] + node _T_689 = bits(_T_688, 0, 0) @[dec_tlu_ctl.scala 2828:70] + node _T_690 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2828:118] + node _T_691 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2828:143] + node _T_692 = and(_T_690, _T_691) @[dec_tlu_ctl.scala 2828:141] + node _T_693 = eq(io.mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2829:42] + node _T_694 = bits(_T_693, 0, 0) @[dec_tlu_ctl.scala 2829:70] + node _T_695 = eq(io.mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2830:42] + node _T_696 = bits(_T_695, 0, 0) @[dec_tlu_ctl.scala 2830:70] + node _T_697 = eq(io.mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2831:42] + node _T_698 = bits(_T_697, 0, 0) @[dec_tlu_ctl.scala 2831:70] + node _T_699 = eq(io.mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2832:42] + node _T_700 = bits(_T_699, 0, 0) @[dec_tlu_ctl.scala 2832:70] + node _T_701 = eq(io.mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2833:42] + node _T_702 = bits(_T_701, 0, 0) @[dec_tlu_ctl.scala 2833:70] + node _T_703 = eq(io.mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2834:42] + node _T_704 = bits(_T_703, 0, 0) @[dec_tlu_ctl.scala 2834:70] + node _T_705 = eq(io.mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2835:42] + node _T_706 = bits(_T_705, 0, 0) @[dec_tlu_ctl.scala 2835:70] + node _T_707 = eq(io.mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2836:42] + node _T_708 = bits(_T_707, 0, 0) @[dec_tlu_ctl.scala 2836:70] + node _T_709 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2836:106] + node _T_710 = or(_T_709, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2836:128] + node _T_711 = eq(io.mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2837:42] + node _T_712 = bits(_T_711, 0, 0) @[dec_tlu_ctl.scala 2837:70] + node _T_713 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2837:100] + node _T_714 = or(_T_713, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2837:125] + node _T_715 = eq(io.mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2838:42] + node _T_716 = bits(_T_715, 0, 0) @[dec_tlu_ctl.scala 2838:70] + node _T_717 = eq(io.mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2839:42] + node _T_718 = bits(_T_717, 0, 0) @[dec_tlu_ctl.scala 2839:70] + node _T_719 = eq(io.mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2840:42] + node _T_720 = bits(_T_719, 0, 0) @[dec_tlu_ctl.scala 2840:70] + node _T_721 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2840:105] + node _T_722 = and(_T_721, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2840:137] + node _T_723 = eq(io.mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2842:42] + node _T_724 = bits(_T_723, 0, 0) @[dec_tlu_ctl.scala 2842:70] + node _T_725 = eq(io.mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2843:42] + node _T_726 = bits(_T_725, 0, 0) @[dec_tlu_ctl.scala 2843:70] + node _T_727 = eq(io.mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2844:42] + node _T_728 = bits(_T_727, 0, 0) @[dec_tlu_ctl.scala 2844:70] + node _T_729 = eq(io.mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2845:42] + node _T_730 = bits(_T_729, 0, 0) @[dec_tlu_ctl.scala 2845:70] + node _T_731 = eq(io.mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2846:42] + node _T_732 = bits(_T_731, 0, 0) @[dec_tlu_ctl.scala 2846:70] + node _T_733 = eq(io.mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2847:42] + node _T_734 = bits(_T_733, 0, 0) @[dec_tlu_ctl.scala 2847:70] + node _T_735 = eq(io.mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2848:42] + node _T_736 = bits(_T_735, 0, 0) @[dec_tlu_ctl.scala 2848:70] + node _T_737 = eq(io.mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2849:42] + node _T_738 = bits(_T_737, 0, 0) @[dec_tlu_ctl.scala 2849:70] + node _T_739 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2849:92] + node _T_740 = bits(_T_739, 0, 0) @[dec_tlu_ctl.scala 2849:92] + node _T_741 = not(_T_740) @[dec_tlu_ctl.scala 2849:81] + node _T_742 = eq(io.mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2850:42] + node _T_743 = bits(_T_742, 0, 0) @[dec_tlu_ctl.scala 2850:70] + node _T_744 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2850:92] + node _T_745 = bits(_T_744, 0, 0) @[dec_tlu_ctl.scala 2850:92] + node _T_746 = not(_T_745) @[dec_tlu_ctl.scala 2850:81] + node _T_747 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2850:115] + node _T_748 = bits(io.mie, 5, 0) @[dec_tlu_ctl.scala 2850:129] + node _T_749 = and(_T_747, _T_748) @[dec_tlu_ctl.scala 2850:121] + node _T_750 = orr(_T_749) @[dec_tlu_ctl.scala 2850:136] + node _T_751 = and(_T_746, _T_750) @[dec_tlu_ctl.scala 2850:106] + node _T_752 = eq(io.mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2851:42] + node _T_753 = bits(_T_752, 0, 0) @[dec_tlu_ctl.scala 2851:70] + node _T_754 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2851:99] + node _T_755 = eq(io.mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2852:42] + node _T_756 = bits(_T_755, 0, 0) @[dec_tlu_ctl.scala 2852:70] + node _T_757 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2852:102] + node _T_758 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2852:133] + node _T_759 = and(_T_757, _T_758) @[dec_tlu_ctl.scala 2852:131] + node _T_760 = eq(io.mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2853:42] + node _T_761 = bits(_T_760, 0, 0) @[dec_tlu_ctl.scala 2853:70] + node _T_762 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2853:102] + node _T_763 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2853:134] + node _T_764 = and(_T_762, _T_763) @[dec_tlu_ctl.scala 2853:132] + node _T_765 = eq(io.mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2855:42] + node _T_766 = bits(_T_765, 0, 0) @[dec_tlu_ctl.scala 2855:70] + node _T_767 = eq(io.mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2856:42] + node _T_768 = bits(_T_767, 0, 0) @[dec_tlu_ctl.scala 2856:70] + node _T_769 = eq(io.mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2857:42] + node _T_770 = bits(_T_769, 0, 0) @[dec_tlu_ctl.scala 2857:70] + node _T_771 = eq(io.mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2858:42] + node _T_772 = bits(_T_771, 0, 0) @[dec_tlu_ctl.scala 2858:70] + node _T_773 = eq(io.mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2859:42] + node _T_774 = bits(_T_773, 0, 0) @[dec_tlu_ctl.scala 2859:70] + node _T_775 = mux(_T_597, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_776 = mux(_T_599, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_777 = mux(_T_601, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_778 = mux(_T_603, _T_605, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_779 = mux(_T_607, _T_611, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_780 = mux(_T_613, _T_616, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_781 = mux(_T_618, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_782 = mux(_T_620, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_783 = mux(_T_622, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_784 = mux(_T_624, _T_625, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_785 = mux(_T_627, _T_630, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_786 = mux(_T_632, _T_633, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_787 = mux(_T_635, _T_636, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_788 = mux(_T_638, _T_640, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_789 = mux(_T_642, _T_645, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_790 = mux(_T_647, _T_648, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_791 = mux(_T_650, _T_651, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_792 = mux(_T_653, _T_654, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_793 = mux(_T_656, _T_657, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_794 = mux(_T_659, _T_660, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_795 = mux(_T_662, _T_663, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_796 = mux(_T_665, _T_666, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_797 = mux(_T_668, _T_669, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_798 = mux(_T_671, _T_672, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_799 = mux(_T_674, _T_677, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_800 = mux(_T_679, _T_682, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_801 = mux(_T_684, _T_687, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_802 = mux(_T_689, _T_692, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_803 = mux(_T_694, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_804 = mux(_T_696, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_805 = mux(_T_698, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_806 = mux(_T_700, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_807 = mux(_T_702, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_808 = mux(_T_704, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_809 = mux(_T_706, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_810 = mux(_T_708, _T_710, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_811 = mux(_T_712, _T_714, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_812 = mux(_T_716, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_813 = mux(_T_718, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_814 = mux(_T_720, _T_722, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_815 = mux(_T_724, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_816 = mux(_T_726, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_817 = mux(_T_728, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_818 = mux(_T_730, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_819 = mux(_T_732, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_820 = mux(_T_734, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_821 = mux(_T_736, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_822 = mux(_T_738, _T_741, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_823 = mux(_T_743, _T_751, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_824 = mux(_T_753, _T_754, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_825 = mux(_T_756, _T_759, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_826 = mux(_T_761, _T_764, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_827 = mux(_T_766, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_828 = mux(_T_768, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_829 = mux(_T_770, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_830 = mux(_T_772, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_831 = mux(_T_774, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_832 = or(_T_775, _T_776) @[Mux.scala 27:72] + node _T_833 = or(_T_832, _T_777) @[Mux.scala 27:72] + node _T_834 = or(_T_833, _T_778) @[Mux.scala 27:72] + node _T_835 = or(_T_834, _T_779) @[Mux.scala 27:72] + node _T_836 = or(_T_835, _T_780) @[Mux.scala 27:72] + node _T_837 = or(_T_836, _T_781) @[Mux.scala 27:72] + node _T_838 = or(_T_837, _T_782) @[Mux.scala 27:72] + node _T_839 = or(_T_838, _T_783) @[Mux.scala 27:72] + node _T_840 = or(_T_839, _T_784) @[Mux.scala 27:72] + node _T_841 = or(_T_840, _T_785) @[Mux.scala 27:72] + node _T_842 = or(_T_841, _T_786) @[Mux.scala 27:72] + node _T_843 = or(_T_842, _T_787) @[Mux.scala 27:72] + node _T_844 = or(_T_843, _T_788) @[Mux.scala 27:72] + node _T_845 = or(_T_844, _T_789) @[Mux.scala 27:72] + node _T_846 = or(_T_845, _T_790) @[Mux.scala 27:72] + node _T_847 = or(_T_846, _T_791) @[Mux.scala 27:72] + node _T_848 = or(_T_847, _T_792) @[Mux.scala 27:72] + node _T_849 = or(_T_848, _T_793) @[Mux.scala 27:72] + node _T_850 = or(_T_849, _T_794) @[Mux.scala 27:72] + node _T_851 = or(_T_850, _T_795) @[Mux.scala 27:72] + node _T_852 = or(_T_851, _T_796) @[Mux.scala 27:72] + node _T_853 = or(_T_852, _T_797) @[Mux.scala 27:72] + node _T_854 = or(_T_853, _T_798) @[Mux.scala 27:72] + node _T_855 = or(_T_854, _T_799) @[Mux.scala 27:72] + node _T_856 = or(_T_855, _T_800) @[Mux.scala 27:72] + node _T_857 = or(_T_856, _T_801) @[Mux.scala 27:72] + node _T_858 = or(_T_857, _T_802) @[Mux.scala 27:72] + node _T_859 = or(_T_858, _T_803) @[Mux.scala 27:72] + node _T_860 = or(_T_859, _T_804) @[Mux.scala 27:72] + node _T_861 = or(_T_860, _T_805) @[Mux.scala 27:72] + node _T_862 = or(_T_861, _T_806) @[Mux.scala 27:72] + node _T_863 = or(_T_862, _T_807) @[Mux.scala 27:72] + node _T_864 = or(_T_863, _T_808) @[Mux.scala 27:72] + node _T_865 = or(_T_864, _T_809) @[Mux.scala 27:72] + node _T_866 = or(_T_865, _T_810) @[Mux.scala 27:72] + node _T_867 = or(_T_866, _T_811) @[Mux.scala 27:72] + node _T_868 = or(_T_867, _T_812) @[Mux.scala 27:72] + node _T_869 = or(_T_868, _T_813) @[Mux.scala 27:72] + node _T_870 = or(_T_869, _T_814) @[Mux.scala 27:72] + node _T_871 = or(_T_870, _T_815) @[Mux.scala 27:72] + node _T_872 = or(_T_871, _T_816) @[Mux.scala 27:72] + node _T_873 = or(_T_872, _T_817) @[Mux.scala 27:72] + node _T_874 = or(_T_873, _T_818) @[Mux.scala 27:72] + node _T_875 = or(_T_874, _T_819) @[Mux.scala 27:72] + node _T_876 = or(_T_875, _T_820) @[Mux.scala 27:72] + node _T_877 = or(_T_876, _T_821) @[Mux.scala 27:72] + node _T_878 = or(_T_877, _T_822) @[Mux.scala 27:72] + node _T_879 = or(_T_878, _T_823) @[Mux.scala 27:72] + node _T_880 = or(_T_879, _T_824) @[Mux.scala 27:72] + node _T_881 = or(_T_880, _T_825) @[Mux.scala 27:72] + node _T_882 = or(_T_881, _T_826) @[Mux.scala 27:72] + node _T_883 = or(_T_882, _T_827) @[Mux.scala 27:72] + node _T_884 = or(_T_883, _T_828) @[Mux.scala 27:72] + node _T_885 = or(_T_884, _T_829) @[Mux.scala 27:72] + node _T_886 = or(_T_885, _T_830) @[Mux.scala 27:72] + node _T_887 = or(_T_886, _T_831) @[Mux.scala 27:72] + wire _T_888 : UInt<1> @[Mux.scala 27:72] + _T_888 <= _T_887 @[Mux.scala 27:72] + node _T_889 = and(_T_595, _T_888) @[dec_tlu_ctl.scala 2797:63] + io.mhpmc_inc_r[2] <= _T_889 @[dec_tlu_ctl.scala 2797:35] + node _T_890 = bits(io.mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2797:57] + node _T_891 = not(_T_890) @[dec_tlu_ctl.scala 2797:40] + node _T_892 = eq(io.mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2798:42] + node _T_893 = bits(_T_892, 0, 0) @[dec_tlu_ctl.scala 2798:70] + node _T_894 = eq(io.mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2799:42] + node _T_895 = bits(_T_894, 0, 0) @[dec_tlu_ctl.scala 2799:70] + node _T_896 = eq(io.mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2800:42] + node _T_897 = bits(_T_896, 0, 0) @[dec_tlu_ctl.scala 2800:70] + node _T_898 = eq(io.mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2801:42] + node _T_899 = bits(_T_898, 0, 0) @[dec_tlu_ctl.scala 2801:70] + node _T_900 = not(io.illegal_r) @[dec_tlu_ctl.scala 2801:104] + node _T_901 = and(io.tlu_i0_commit_cmt, _T_900) @[dec_tlu_ctl.scala 2801:102] + node _T_902 = eq(io.mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2802:42] + node _T_903 = bits(_T_902, 0, 0) @[dec_tlu_ctl.scala 2802:70] + node _T_904 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2802:104] + node _T_905 = and(io.tlu_i0_commit_cmt, _T_904) @[dec_tlu_ctl.scala 2802:102] + node _T_906 = not(io.illegal_r) @[dec_tlu_ctl.scala 2802:125] + node _T_907 = and(_T_905, _T_906) @[dec_tlu_ctl.scala 2802:123] + node _T_908 = eq(io.mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2803:42] + node _T_909 = bits(_T_908, 0, 0) @[dec_tlu_ctl.scala 2803:70] + node _T_910 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2803:102] + node _T_911 = not(io.illegal_r) @[dec_tlu_ctl.scala 2803:125] + node _T_912 = and(_T_910, _T_911) @[dec_tlu_ctl.scala 2803:123] + node _T_913 = eq(io.mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2805:42] + node _T_914 = bits(_T_913, 0, 0) @[dec_tlu_ctl.scala 2805:70] + node _T_915 = eq(io.mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2806:42] + node _T_916 = bits(_T_915, 0, 0) @[dec_tlu_ctl.scala 2806:70] + node _T_917 = eq(io.mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2807:42] + node _T_918 = bits(_T_917, 0, 0) @[dec_tlu_ctl.scala 2807:70] + node _T_919 = eq(io.mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2808:42] + node _T_920 = bits(_T_919, 0, 0) @[dec_tlu_ctl.scala 2808:70] + node _T_921 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2808:99] + node _T_922 = eq(io.mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2809:42] + node _T_923 = bits(_T_922, 0, 0) @[dec_tlu_ctl.scala 2809:70] + node _T_924 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2809:113] + node _T_925 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2809:138] + node _T_926 = and(_T_924, _T_925) @[dec_tlu_ctl.scala 2809:136] + node _T_927 = eq(io.mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2810:42] + node _T_928 = bits(_T_927, 0, 0) @[dec_tlu_ctl.scala 2810:70] + node _T_929 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2810:99] + node _T_930 = eq(io.mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2811:42] + node _T_931 = bits(_T_930, 0, 0) @[dec_tlu_ctl.scala 2811:70] + node _T_932 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2811:99] + node _T_933 = eq(io.mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2812:42] + node _T_934 = bits(_T_933, 0, 0) @[dec_tlu_ctl.scala 2812:70] + node _T_935 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2812:99] + node _T_936 = and(_T_935, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2812:108] + node _T_937 = eq(io.mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2813:42] + node _T_938 = bits(_T_937, 0, 0) @[dec_tlu_ctl.scala 2813:70] + node _T_939 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2813:99] + node _T_940 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2813:150] + node _T_941 = and(_T_939, _T_940) @[dec_tlu_ctl.scala 2813:109] + node _T_942 = eq(io.mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2815:42] + node _T_943 = bits(_T_942, 0, 0) @[dec_tlu_ctl.scala 2815:67] + node _T_944 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2815:97] + node _T_945 = eq(io.mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2816:42] + node _T_946 = bits(_T_945, 0, 0) @[dec_tlu_ctl.scala 2816:67] + node _T_947 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2816:97] + node _T_948 = eq(io.mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2817:42] + node _T_949 = bits(_T_948, 0, 0) @[dec_tlu_ctl.scala 2817:67] + node _T_950 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2817:97] + node _T_951 = eq(io.mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2818:42] + node _T_952 = bits(_T_951, 0, 0) @[dec_tlu_ctl.scala 2818:67] + node _T_953 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2818:97] + node _T_954 = eq(io.mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2819:42] + node _T_955 = bits(_T_954, 0, 0) @[dec_tlu_ctl.scala 2819:67] + node _T_956 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2819:97] + node _T_957 = eq(io.mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2820:42] + node _T_958 = bits(_T_957, 0, 0) @[dec_tlu_ctl.scala 2820:67] + node _T_959 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2820:97] + node _T_960 = eq(io.mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2821:42] + node _T_961 = bits(_T_960, 0, 0) @[dec_tlu_ctl.scala 2821:67] + node _T_962 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2821:97] + node _T_963 = eq(io.mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2822:42] + node _T_964 = bits(_T_963, 0, 0) @[dec_tlu_ctl.scala 2822:67] + node _T_965 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2822:97] + node _T_966 = eq(io.mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2823:42] + node _T_967 = bits(_T_966, 0, 0) @[dec_tlu_ctl.scala 2823:67] + node _T_968 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2823:97] + node _T_969 = eq(io.mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2824:42] + node _T_970 = bits(_T_969, 0, 0) @[dec_tlu_ctl.scala 2824:67] + node _T_971 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2824:97] + node _T_972 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2824:130] + node _T_973 = or(_T_971, _T_972) @[dec_tlu_ctl.scala 2824:109] + node _T_974 = eq(io.mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2826:42] + node _T_975 = bits(_T_974, 0, 0) @[dec_tlu_ctl.scala 2826:70] + node _T_976 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2826:103] + node _T_977 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2826:128] + node _T_978 = and(_T_976, _T_977) @[dec_tlu_ctl.scala 2826:126] + node _T_979 = eq(io.mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2827:42] + node _T_980 = bits(_T_979, 0, 0) @[dec_tlu_ctl.scala 2827:70] + node _T_981 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2827:105] + node _T_982 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2827:130] + node _T_983 = and(_T_981, _T_982) @[dec_tlu_ctl.scala 2827:128] + node _T_984 = eq(io.mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2828:42] + node _T_985 = bits(_T_984, 0, 0) @[dec_tlu_ctl.scala 2828:70] + node _T_986 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2828:118] + node _T_987 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2828:143] + node _T_988 = and(_T_986, _T_987) @[dec_tlu_ctl.scala 2828:141] + node _T_989 = eq(io.mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2829:42] + node _T_990 = bits(_T_989, 0, 0) @[dec_tlu_ctl.scala 2829:70] + node _T_991 = eq(io.mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2830:42] + node _T_992 = bits(_T_991, 0, 0) @[dec_tlu_ctl.scala 2830:70] + node _T_993 = eq(io.mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2831:42] + node _T_994 = bits(_T_993, 0, 0) @[dec_tlu_ctl.scala 2831:70] + node _T_995 = eq(io.mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2832:42] + node _T_996 = bits(_T_995, 0, 0) @[dec_tlu_ctl.scala 2832:70] + node _T_997 = eq(io.mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2833:42] + node _T_998 = bits(_T_997, 0, 0) @[dec_tlu_ctl.scala 2833:70] + node _T_999 = eq(io.mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2834:42] + node _T_1000 = bits(_T_999, 0, 0) @[dec_tlu_ctl.scala 2834:70] + node _T_1001 = eq(io.mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2835:42] + node _T_1002 = bits(_T_1001, 0, 0) @[dec_tlu_ctl.scala 2835:70] + node _T_1003 = eq(io.mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2836:42] + node _T_1004 = bits(_T_1003, 0, 0) @[dec_tlu_ctl.scala 2836:70] + node _T_1005 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2836:106] + node _T_1006 = or(_T_1005, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2836:128] + node _T_1007 = eq(io.mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2837:42] + node _T_1008 = bits(_T_1007, 0, 0) @[dec_tlu_ctl.scala 2837:70] + node _T_1009 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2837:100] + node _T_1010 = or(_T_1009, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2837:125] + node _T_1011 = eq(io.mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2838:42] + node _T_1012 = bits(_T_1011, 0, 0) @[dec_tlu_ctl.scala 2838:70] + node _T_1013 = eq(io.mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2839:42] + node _T_1014 = bits(_T_1013, 0, 0) @[dec_tlu_ctl.scala 2839:70] + node _T_1015 = eq(io.mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2840:42] + node _T_1016 = bits(_T_1015, 0, 0) @[dec_tlu_ctl.scala 2840:70] + node _T_1017 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2840:105] + node _T_1018 = and(_T_1017, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2840:137] + node _T_1019 = eq(io.mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2842:42] + node _T_1020 = bits(_T_1019, 0, 0) @[dec_tlu_ctl.scala 2842:70] + node _T_1021 = eq(io.mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2843:42] + node _T_1022 = bits(_T_1021, 0, 0) @[dec_tlu_ctl.scala 2843:70] + node _T_1023 = eq(io.mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2844:42] + node _T_1024 = bits(_T_1023, 0, 0) @[dec_tlu_ctl.scala 2844:70] + node _T_1025 = eq(io.mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2845:42] + node _T_1026 = bits(_T_1025, 0, 0) @[dec_tlu_ctl.scala 2845:70] + node _T_1027 = eq(io.mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2846:42] + node _T_1028 = bits(_T_1027, 0, 0) @[dec_tlu_ctl.scala 2846:70] + node _T_1029 = eq(io.mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2847:42] + node _T_1030 = bits(_T_1029, 0, 0) @[dec_tlu_ctl.scala 2847:70] + node _T_1031 = eq(io.mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2848:42] + node _T_1032 = bits(_T_1031, 0, 0) @[dec_tlu_ctl.scala 2848:70] + node _T_1033 = eq(io.mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2849:42] + node _T_1034 = bits(_T_1033, 0, 0) @[dec_tlu_ctl.scala 2849:70] + node _T_1035 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2849:92] + node _T_1036 = bits(_T_1035, 0, 0) @[dec_tlu_ctl.scala 2849:92] + node _T_1037 = not(_T_1036) @[dec_tlu_ctl.scala 2849:81] + node _T_1038 = eq(io.mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2850:42] + node _T_1039 = bits(_T_1038, 0, 0) @[dec_tlu_ctl.scala 2850:70] + node _T_1040 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2850:92] + node _T_1041 = bits(_T_1040, 0, 0) @[dec_tlu_ctl.scala 2850:92] + node _T_1042 = not(_T_1041) @[dec_tlu_ctl.scala 2850:81] + node _T_1043 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2850:115] + node _T_1044 = bits(io.mie, 5, 0) @[dec_tlu_ctl.scala 2850:129] + node _T_1045 = and(_T_1043, _T_1044) @[dec_tlu_ctl.scala 2850:121] + node _T_1046 = orr(_T_1045) @[dec_tlu_ctl.scala 2850:136] + node _T_1047 = and(_T_1042, _T_1046) @[dec_tlu_ctl.scala 2850:106] + node _T_1048 = eq(io.mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2851:42] + node _T_1049 = bits(_T_1048, 0, 0) @[dec_tlu_ctl.scala 2851:70] + node _T_1050 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2851:99] + node _T_1051 = eq(io.mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2852:42] + node _T_1052 = bits(_T_1051, 0, 0) @[dec_tlu_ctl.scala 2852:70] + node _T_1053 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2852:102] + node _T_1054 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2852:133] + node _T_1055 = and(_T_1053, _T_1054) @[dec_tlu_ctl.scala 2852:131] + node _T_1056 = eq(io.mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2853:42] + node _T_1057 = bits(_T_1056, 0, 0) @[dec_tlu_ctl.scala 2853:70] + node _T_1058 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2853:102] + node _T_1059 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2853:134] + node _T_1060 = and(_T_1058, _T_1059) @[dec_tlu_ctl.scala 2853:132] + node _T_1061 = eq(io.mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2855:42] + node _T_1062 = bits(_T_1061, 0, 0) @[dec_tlu_ctl.scala 2855:70] + node _T_1063 = eq(io.mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2856:42] + node _T_1064 = bits(_T_1063, 0, 0) @[dec_tlu_ctl.scala 2856:70] + node _T_1065 = eq(io.mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2857:42] + node _T_1066 = bits(_T_1065, 0, 0) @[dec_tlu_ctl.scala 2857:70] + node _T_1067 = eq(io.mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2858:42] + node _T_1068 = bits(_T_1067, 0, 0) @[dec_tlu_ctl.scala 2858:70] + node _T_1069 = eq(io.mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2859:42] + node _T_1070 = bits(_T_1069, 0, 0) @[dec_tlu_ctl.scala 2859:70] + node _T_1071 = mux(_T_893, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1072 = mux(_T_895, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1073 = mux(_T_897, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1074 = mux(_T_899, _T_901, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1075 = mux(_T_903, _T_907, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1076 = mux(_T_909, _T_912, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1077 = mux(_T_914, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1078 = mux(_T_916, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1079 = mux(_T_918, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1080 = mux(_T_920, _T_921, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1081 = mux(_T_923, _T_926, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1082 = mux(_T_928, _T_929, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1083 = mux(_T_931, _T_932, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1084 = mux(_T_934, _T_936, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1085 = mux(_T_938, _T_941, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1086 = mux(_T_943, _T_944, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1087 = mux(_T_946, _T_947, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1088 = mux(_T_949, _T_950, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1089 = mux(_T_952, _T_953, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1090 = mux(_T_955, _T_956, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1091 = mux(_T_958, _T_959, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1092 = mux(_T_961, _T_962, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1093 = mux(_T_964, _T_965, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1094 = mux(_T_967, _T_968, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1095 = mux(_T_970, _T_973, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1096 = mux(_T_975, _T_978, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1097 = mux(_T_980, _T_983, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1098 = mux(_T_985, _T_988, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1099 = mux(_T_990, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1100 = mux(_T_992, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1101 = mux(_T_994, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1102 = mux(_T_996, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1103 = mux(_T_998, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1104 = mux(_T_1000, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1105 = mux(_T_1002, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1106 = mux(_T_1004, _T_1006, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1107 = mux(_T_1008, _T_1010, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1108 = mux(_T_1012, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1109 = mux(_T_1014, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1110 = mux(_T_1016, _T_1018, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1111 = mux(_T_1020, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1112 = mux(_T_1022, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1113 = mux(_T_1024, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1114 = mux(_T_1026, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1115 = mux(_T_1028, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1116 = mux(_T_1030, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1117 = mux(_T_1032, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1118 = mux(_T_1034, _T_1037, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1119 = mux(_T_1039, _T_1047, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1120 = mux(_T_1049, _T_1050, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1121 = mux(_T_1052, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1122 = mux(_T_1057, _T_1060, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1123 = mux(_T_1062, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1124 = mux(_T_1064, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1125 = mux(_T_1066, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1126 = mux(_T_1068, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1127 = mux(_T_1070, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1128 = or(_T_1071, _T_1072) @[Mux.scala 27:72] + node _T_1129 = or(_T_1128, _T_1073) @[Mux.scala 27:72] + node _T_1130 = or(_T_1129, _T_1074) @[Mux.scala 27:72] + node _T_1131 = or(_T_1130, _T_1075) @[Mux.scala 27:72] + node _T_1132 = or(_T_1131, _T_1076) @[Mux.scala 27:72] + node _T_1133 = or(_T_1132, _T_1077) @[Mux.scala 27:72] + node _T_1134 = or(_T_1133, _T_1078) @[Mux.scala 27:72] + node _T_1135 = or(_T_1134, _T_1079) @[Mux.scala 27:72] + node _T_1136 = or(_T_1135, _T_1080) @[Mux.scala 27:72] + node _T_1137 = or(_T_1136, _T_1081) @[Mux.scala 27:72] + node _T_1138 = or(_T_1137, _T_1082) @[Mux.scala 27:72] + node _T_1139 = or(_T_1138, _T_1083) @[Mux.scala 27:72] + node _T_1140 = or(_T_1139, _T_1084) @[Mux.scala 27:72] + node _T_1141 = or(_T_1140, _T_1085) @[Mux.scala 27:72] + node _T_1142 = or(_T_1141, _T_1086) @[Mux.scala 27:72] + node _T_1143 = or(_T_1142, _T_1087) @[Mux.scala 27:72] + node _T_1144 = or(_T_1143, _T_1088) @[Mux.scala 27:72] + node _T_1145 = or(_T_1144, _T_1089) @[Mux.scala 27:72] + node _T_1146 = or(_T_1145, _T_1090) @[Mux.scala 27:72] + node _T_1147 = or(_T_1146, _T_1091) @[Mux.scala 27:72] + node _T_1148 = or(_T_1147, _T_1092) @[Mux.scala 27:72] + node _T_1149 = or(_T_1148, _T_1093) @[Mux.scala 27:72] + node _T_1150 = or(_T_1149, _T_1094) @[Mux.scala 27:72] + node _T_1151 = or(_T_1150, _T_1095) @[Mux.scala 27:72] + node _T_1152 = or(_T_1151, _T_1096) @[Mux.scala 27:72] + node _T_1153 = or(_T_1152, _T_1097) @[Mux.scala 27:72] + node _T_1154 = or(_T_1153, _T_1098) @[Mux.scala 27:72] + node _T_1155 = or(_T_1154, _T_1099) @[Mux.scala 27:72] + node _T_1156 = or(_T_1155, _T_1100) @[Mux.scala 27:72] + node _T_1157 = or(_T_1156, _T_1101) @[Mux.scala 27:72] + node _T_1158 = or(_T_1157, _T_1102) @[Mux.scala 27:72] + node _T_1159 = or(_T_1158, _T_1103) @[Mux.scala 27:72] + node _T_1160 = or(_T_1159, _T_1104) @[Mux.scala 27:72] + node _T_1161 = or(_T_1160, _T_1105) @[Mux.scala 27:72] + node _T_1162 = or(_T_1161, _T_1106) @[Mux.scala 27:72] + node _T_1163 = or(_T_1162, _T_1107) @[Mux.scala 27:72] + node _T_1164 = or(_T_1163, _T_1108) @[Mux.scala 27:72] + node _T_1165 = or(_T_1164, _T_1109) @[Mux.scala 27:72] + node _T_1166 = or(_T_1165, _T_1110) @[Mux.scala 27:72] + node _T_1167 = or(_T_1166, _T_1111) @[Mux.scala 27:72] + node _T_1168 = or(_T_1167, _T_1112) @[Mux.scala 27:72] + node _T_1169 = or(_T_1168, _T_1113) @[Mux.scala 27:72] + node _T_1170 = or(_T_1169, _T_1114) @[Mux.scala 27:72] + node _T_1171 = or(_T_1170, _T_1115) @[Mux.scala 27:72] + node _T_1172 = or(_T_1171, _T_1116) @[Mux.scala 27:72] + node _T_1173 = or(_T_1172, _T_1117) @[Mux.scala 27:72] + node _T_1174 = or(_T_1173, _T_1118) @[Mux.scala 27:72] + node _T_1175 = or(_T_1174, _T_1119) @[Mux.scala 27:72] + node _T_1176 = or(_T_1175, _T_1120) @[Mux.scala 27:72] + node _T_1177 = or(_T_1176, _T_1121) @[Mux.scala 27:72] + node _T_1178 = or(_T_1177, _T_1122) @[Mux.scala 27:72] + node _T_1179 = or(_T_1178, _T_1123) @[Mux.scala 27:72] + node _T_1180 = or(_T_1179, _T_1124) @[Mux.scala 27:72] + node _T_1181 = or(_T_1180, _T_1125) @[Mux.scala 27:72] + node _T_1182 = or(_T_1181, _T_1126) @[Mux.scala 27:72] + node _T_1183 = or(_T_1182, _T_1127) @[Mux.scala 27:72] + wire _T_1184 : UInt<1> @[Mux.scala 27:72] + _T_1184 <= _T_1183 @[Mux.scala 27:72] + node _T_1185 = and(_T_891, _T_1184) @[dec_tlu_ctl.scala 2797:63] + io.mhpmc_inc_r[3] <= _T_1185 @[dec_tlu_ctl.scala 2797:35] + wire _T_1186 : UInt<1> + _T_1186 <= UInt<1>("h00") + node _T_1187 = xor(io.mdseac_locked_ns, _T_1186) @[lib.scala 470:21] + node _T_1188 = orr(_T_1187) @[lib.scala 470:29] + reg _T_1189 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1188 : @[Reg.scala 28:19] + _T_1189 <= io.mdseac_locked_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1186 <= _T_1189 @[lib.scala 473:16] + io.mdseac_locked_f <= _T_1186 @[dec_tlu_ctl.scala 2870:52] + wire _T_1190 : UInt<1> + _T_1190 <= UInt<1>("h00") + node _T_1191 = xor(io.lsu_single_ecc_error_r, _T_1190) @[lib.scala 470:21] + node _T_1192 = orr(_T_1191) @[lib.scala 470:29] + reg _T_1193 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1192 : @[Reg.scala 28:19] + _T_1193 <= io.lsu_single_ecc_error_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1190 <= _T_1193 @[lib.scala 473:16] + io.lsu_single_ecc_error_r_d1 <= _T_1190 @[dec_tlu_ctl.scala 2871:52] + wire _T_1194 : UInt + _T_1194 <= UInt<1>("h00") + node _T_1195 = xor(io.lsu_exc_valid_r, _T_1194) @[lib.scala 448:21] + node _T_1196 = orr(_T_1195) @[lib.scala 448:29] + reg _T_1197 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1196 : @[Reg.scala 28:19] + _T_1197 <= io.lsu_exc_valid_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1194 <= _T_1197 @[lib.scala 451:16] + io.lsu_exc_valid_r_d1 <= _T_1194 @[dec_tlu_ctl.scala 2872:52] + wire _T_1198 : UInt<1> + _T_1198 <= UInt<1>("h00") + node _T_1199 = xor(io.lsu_i0_exc_r, _T_1198) @[lib.scala 470:21] + node _T_1200 = orr(_T_1199) @[lib.scala 470:29] + reg _T_1201 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1200 : @[Reg.scala 28:19] + _T_1201 <= io.lsu_i0_exc_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1198 <= _T_1201 @[lib.scala 473:16] + io.lsu_i0_exc_r_d1 <= _T_1198 @[dec_tlu_ctl.scala 2873:52] + wire _T_1202 : UInt<1> + _T_1202 <= UInt<1>("h00") + node _T_1203 = xor(io.take_ext_int_start, _T_1202) @[lib.scala 470:21] + node _T_1204 = orr(_T_1203) @[lib.scala 470:29] + reg _T_1205 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1204 : @[Reg.scala 28:19] + _T_1205 <= io.take_ext_int_start @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1202 <= _T_1205 @[lib.scala 473:16] + io.take_ext_int_start_d1 <= _T_1202 @[dec_tlu_ctl.scala 2874:52] + wire _T_1206 : UInt<1> + _T_1206 <= UInt<1>("h00") + node _T_1207 = xor(io.take_ext_int_start_d1, _T_1206) @[lib.scala 470:21] + node _T_1208 = orr(_T_1207) @[lib.scala 470:29] + reg _T_1209 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1208 : @[Reg.scala 28:19] + _T_1209 <= io.take_ext_int_start_d1 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1206 <= _T_1209 @[lib.scala 473:16] + io.take_ext_int_start_d2 <= _T_1206 @[dec_tlu_ctl.scala 2875:52] + wire _T_1210 : UInt<1> + _T_1210 <= UInt<1>("h00") + node _T_1211 = xor(io.take_ext_int_start_d2, _T_1210) @[lib.scala 470:21] + node _T_1212 = orr(_T_1211) @[lib.scala 470:29] + reg _T_1213 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1212 : @[Reg.scala 28:19] + _T_1213 <= io.take_ext_int_start_d2 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1210 <= _T_1213 @[lib.scala 473:16] + io.take_ext_int_start_d3 <= _T_1210 @[dec_tlu_ctl.scala 2876:52] + wire _T_1214 : UInt<1> + _T_1214 <= UInt<1>("h00") + node _T_1215 = xor(io.ext_int_freeze, _T_1214) @[lib.scala 470:21] + node _T_1216 = orr(_T_1215) @[lib.scala 470:29] + reg _T_1217 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1216 : @[Reg.scala 28:19] + _T_1217 <= io.ext_int_freeze @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1214 <= _T_1217 @[lib.scala 473:16] + io.ext_int_freeze_d1 <= _T_1214 @[dec_tlu_ctl.scala 2877:52] + wire _T_1218 : UInt + _T_1218 <= UInt<1>("h00") + node _T_1219 = xor(io.mip_ns, _T_1218) @[lib.scala 448:21] + node _T_1220 = orr(_T_1219) @[lib.scala 448:29] + reg _T_1221 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1220 : @[Reg.scala 28:19] + _T_1221 <= io.mip_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1218 <= _T_1221 @[lib.scala 451:16] + io.mip <= _T_1218 @[dec_tlu_ctl.scala 2878:52] + node _T_1222 = not(io.wr_mcycleh_r) @[dec_tlu_ctl.scala 2879:80] + node _T_1223 = and(io.mcyclel_cout, _T_1222) @[dec_tlu_ctl.scala 2879:78] + node _T_1224 = and(_T_1223, io.mcyclel_cout_in) @[dec_tlu_ctl.scala 2879:97] + wire _T_1225 : UInt<1> + _T_1225 <= UInt<1>("h00") + node _T_1226 = xor(_T_1224, _T_1225) @[lib.scala 470:21] + node _T_1227 = orr(_T_1226) @[lib.scala 470:29] + reg _T_1228 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1227 : @[Reg.scala 28:19] + _T_1228 <= _T_1224 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1225 <= _T_1228 @[lib.scala 473:16] + io.mcyclel_cout_f <= _T_1225 @[dec_tlu_ctl.scala 2879:52] + wire _T_1229 : UInt<1> + _T_1229 <= UInt<1>("h00") + node _T_1230 = xor(io.minstret_enable, _T_1229) @[lib.scala 470:21] + node _T_1231 = orr(_T_1230) @[lib.scala 470:29] + reg _T_1232 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1231 : @[Reg.scala 28:19] + _T_1232 <= io.minstret_enable @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1229 <= _T_1232 @[lib.scala 473:16] + io.minstret_enable_f <= _T_1229 @[dec_tlu_ctl.scala 2880:52] + wire _T_1233 : UInt<1> + _T_1233 <= UInt<1>("h00") + node _T_1234 = xor(io.minstretl_cout_ns, _T_1233) @[lib.scala 470:21] + node _T_1235 = orr(_T_1234) @[lib.scala 470:29] + reg _T_1236 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1235 : @[Reg.scala 28:19] + _T_1236 <= io.minstretl_cout_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1233 <= _T_1236 @[lib.scala 473:16] + io.minstretl_cout_f <= _T_1233 @[dec_tlu_ctl.scala 2881:52] + wire _T_1237 : UInt<1> + _T_1237 <= UInt<1>("h00") + node _T_1238 = xor(io.fw_halted_ns, _T_1237) @[lib.scala 470:21] + node _T_1239 = orr(_T_1238) @[lib.scala 470:29] + reg _T_1240 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1239 : @[Reg.scala 28:19] + _T_1240 <= io.fw_halted_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1237 <= _T_1240 @[lib.scala 473:16] + io.fw_halted <= _T_1237 @[dec_tlu_ctl.scala 2882:52] + wire _T_1241 : UInt + _T_1241 <= UInt<1>("h00") + node _T_1242 = xor(io.meicidpl_ns, _T_1241) @[lib.scala 448:21] + node _T_1243 = orr(_T_1242) @[lib.scala 448:29] + reg _T_1244 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1243 : @[Reg.scala 28:19] + _T_1244 <= io.meicidpl_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1241 <= _T_1244 @[lib.scala 451:16] + io.meicidpl <= _T_1241 @[dec_tlu_ctl.scala 2883:52] + wire _T_1245 : UInt<1> + _T_1245 <= UInt<1>("h00") + node _T_1246 = xor(io.icache_rd_valid, _T_1245) @[lib.scala 470:21] + node _T_1247 = orr(_T_1246) @[lib.scala 470:29] + reg _T_1248 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1247 : @[Reg.scala 28:19] + _T_1248 <= io.icache_rd_valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1245 <= _T_1248 @[lib.scala 473:16] + io.icache_rd_valid_f <= _T_1245 @[dec_tlu_ctl.scala 2884:52] + wire _T_1249 : UInt<1> + _T_1249 <= UInt<1>("h00") + node _T_1250 = xor(io.icache_wr_valid, _T_1249) @[lib.scala 470:21] + node _T_1251 = orr(_T_1250) @[lib.scala 470:29] + reg _T_1252 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1251 : @[Reg.scala 28:19] + _T_1252 <= io.icache_wr_valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1249 <= _T_1252 @[lib.scala 473:16] + io.icache_wr_valid_f <= _T_1249 @[dec_tlu_ctl.scala 2885:52] + wire _T_1253 : UInt<1>[4] + _T_1253[0] <= io.mhpmc_inc_r[0] + _T_1253[1] <= io.mhpmc_inc_r[1] + _T_1253[2] <= io.mhpmc_inc_r[2] + _T_1253[3] <= io.mhpmc_inc_r[3] + node _T_1254 = xor(io.mhpmc_inc_r[0], _T_1253[0]) @[lib.scala 518:68] + node _T_1255 = orr(_T_1254) @[lib.scala 518:82] + node _T_1256 = xor(io.mhpmc_inc_r[1], _T_1253[1]) @[lib.scala 518:68] + node _T_1257 = orr(_T_1256) @[lib.scala 518:82] + node _T_1258 = xor(io.mhpmc_inc_r[2], _T_1253[2]) @[lib.scala 518:68] + node _T_1259 = orr(_T_1258) @[lib.scala 518:82] + node _T_1260 = xor(io.mhpmc_inc_r[3], _T_1253[3]) @[lib.scala 518:68] + node _T_1261 = orr(_T_1260) @[lib.scala 518:82] + node _T_1262 = or(_T_1255, _T_1257) @[lib.scala 518:97] + node _T_1263 = or(_T_1262, _T_1259) @[lib.scala 518:97] + node _T_1264 = or(_T_1263, _T_1261) @[lib.scala 518:97] + wire _T_1265 : UInt<1>[4] @[lib.scala 521:46] + _T_1265[0] <= UInt<1>("h00") @[lib.scala 521:46] + _T_1265[1] <= UInt<1>("h00") @[lib.scala 521:46] + _T_1265[2] <= UInt<1>("h00") @[lib.scala 521:46] + _T_1265[3] <= UInt<1>("h00") @[lib.scala 521:46] + reg _T_1266 : UInt<1>[4], io.free_l2clk with : (reset => (reset, _T_1265)) @[Reg.scala 27:20] + when _T_1264 : @[Reg.scala 28:19] + _T_1266[0] <= io.mhpmc_inc_r[0] @[Reg.scala 28:23] + _T_1266[1] <= io.mhpmc_inc_r[1] @[Reg.scala 28:23] + _T_1266[2] <= io.mhpmc_inc_r[2] @[Reg.scala 28:23] + _T_1266[3] <= io.mhpmc_inc_r[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1253[0] <= _T_1266[0] @[lib.scala 521:16] + _T_1253[1] <= _T_1266[1] @[lib.scala 521:16] + _T_1253[2] <= _T_1266[2] @[lib.scala 521:16] + _T_1253[3] <= _T_1266[3] @[lib.scala 521:16] + io.mhpmc_inc_r_d1[0] <= _T_1253[0] @[dec_tlu_ctl.scala 2886:52] + io.mhpmc_inc_r_d1[1] <= _T_1253[1] @[dec_tlu_ctl.scala 2886:52] + io.mhpmc_inc_r_d1[2] <= _T_1253[2] @[dec_tlu_ctl.scala 2886:52] + io.mhpmc_inc_r_d1[3] <= _T_1253[3] @[dec_tlu_ctl.scala 2886:52] + wire _T_1267 : UInt<1> + _T_1267 <= UInt<1>("h00") + node _T_1268 = xor(io.perfcnt_halted, _T_1267) @[lib.scala 470:21] + node _T_1269 = orr(_T_1268) @[lib.scala 470:29] + reg _T_1270 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1269 : @[Reg.scala 28:19] + _T_1270 <= io.perfcnt_halted @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1267 <= _T_1270 @[lib.scala 473:16] + io.perfcnt_halted_d1 <= _T_1267 @[dec_tlu_ctl.scala 2887:52] + wire _T_1271 : UInt + _T_1271 <= UInt<1>("h00") + node _T_1272 = xor(io.mstatus_ns, _T_1271) @[lib.scala 448:21] + node _T_1273 = orr(_T_1272) @[lib.scala 448:29] + reg _T_1274 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1273 : @[Reg.scala 28:19] + _T_1274 <= io.mstatus_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_1271 <= _T_1274 @[lib.scala 451:16] + io.mstatus <= _T_1271 @[dec_tlu_ctl.scala 2888:52] + + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_10 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_11 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module perf_csr : + input clock : Clock + input reset : AsyncReset + output io : {flip free_l2clk : Clock, flip scan_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dcsr : UInt<16>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip mhpme_vec : UInt<10>[4], flip dec_csr_wen_r_mod : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip mhpmc_inc_r : UInt<1>[4], flip mhpmc_inc_r_d1 : UInt<1>[4], flip perfcnt_halted_d1 : UInt<1>, mhpmc3h : UInt<32>, mhpmc3 : UInt<32>, mhpmc4h : UInt<32>, mhpmc4 : UInt<32>, mhpmc5h : UInt<32>, mhpmc5 : UInt<32>, mhpmc6h : UInt<32>, mhpmc6 : UInt<32>, mhpme3 : UInt<10>, mhpme4 : UInt<10>, mhpme5 : UInt<10>, mhpme6 : UInt<10>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>} + + node _T = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2578:63] + node _T_1 = and(io.dec_tlu_dbg_halted, _T) @[dec_tlu_ctl.scala 2578:54] + node perfcnt_halted = or(_T_1, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2578:77] + node _T_2 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2579:77] + node _T_3 = and(io.dec_tlu_dbg_halted, _T_2) @[dec_tlu_ctl.scala 2579:68] + node _T_4 = eq(_T_3, UInt<1>("h00")) @[dec_tlu_ctl.scala 2579:44] + node _T_5 = bits(_T_4, 0, 0) @[Bitwise.scala 72:15] + node _T_6 = mux(_T_5, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_7 = bits(io.mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2579:114] + node _T_8 = bits(io.mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2579:133] + node _T_9 = bits(io.mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2579:152] + node _T_10 = bits(io.mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2579:171] + node _T_11 = cat(_T_9, _T_10) @[Cat.scala 29:58] + node _T_12 = cat(_T_7, _T_8) @[Cat.scala 29:58] + node _T_13 = cat(_T_12, _T_11) @[Cat.scala 29:58] + node perfcnt_during_sleep = and(_T_6, _T_13) @[dec_tlu_ctl.scala 2579:93] + node _T_14 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2582:101] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[dec_tlu_ctl.scala 2582:80] + node _T_16 = and(io.perfcnt_halted_d1, _T_15) @[dec_tlu_ctl.scala 2582:78] + node _T_17 = eq(_T_16, UInt<1>("h00")) @[dec_tlu_ctl.scala 2582:55] + node _T_18 = and(io.mhpmc_inc_r_d1[0], _T_17) @[dec_tlu_ctl.scala 2582:53] + io.dec_tlu_perfcnt0 <= _T_18 @[dec_tlu_ctl.scala 2582:29] + node _T_19 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2583:101] + node _T_20 = eq(_T_19, UInt<1>("h00")) @[dec_tlu_ctl.scala 2583:80] + node _T_21 = and(io.perfcnt_halted_d1, _T_20) @[dec_tlu_ctl.scala 2583:78] + node _T_22 = eq(_T_21, UInt<1>("h00")) @[dec_tlu_ctl.scala 2583:55] + node _T_23 = and(io.mhpmc_inc_r_d1[1], _T_22) @[dec_tlu_ctl.scala 2583:53] + io.dec_tlu_perfcnt1 <= _T_23 @[dec_tlu_ctl.scala 2583:29] + node _T_24 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2584:101] + node _T_25 = eq(_T_24, UInt<1>("h00")) @[dec_tlu_ctl.scala 2584:80] + node _T_26 = and(io.perfcnt_halted_d1, _T_25) @[dec_tlu_ctl.scala 2584:78] + node _T_27 = eq(_T_26, UInt<1>("h00")) @[dec_tlu_ctl.scala 2584:55] + node _T_28 = and(io.mhpmc_inc_r_d1[2], _T_27) @[dec_tlu_ctl.scala 2584:53] + io.dec_tlu_perfcnt2 <= _T_28 @[dec_tlu_ctl.scala 2584:29] + node _T_29 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2585:101] + node _T_30 = eq(_T_29, UInt<1>("h00")) @[dec_tlu_ctl.scala 2585:80] + node _T_31 = and(io.perfcnt_halted_d1, _T_30) @[dec_tlu_ctl.scala 2585:78] + node _T_32 = eq(_T_31, UInt<1>("h00")) @[dec_tlu_ctl.scala 2585:55] + node _T_33 = and(io.mhpmc_inc_r_d1[3], _T_32) @[dec_tlu_ctl.scala 2585:53] + io.dec_tlu_perfcnt3 <= _T_33 @[dec_tlu_ctl.scala 2585:29] + node _T_34 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2591:72] + node _T_35 = eq(_T_34, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2591:79] + node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_35) @[dec_tlu_ctl.scala 2591:50] + node _T_36 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2592:30] + node _T_37 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2592:68] + node _T_38 = or(_T_36, _T_37) @[dec_tlu_ctl.scala 2592:46] + node _T_39 = orr(io.mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2592:96] + node mhpmc3_wr_en1 = and(_T_38, _T_39) @[dec_tlu_ctl.scala 2592:73] + node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2593:43] + node _T_40 = bits(io.mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2596:41] + node _T_41 = bits(io.mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2596:57] + node _T_42 = cat(_T_40, _T_41) @[Cat.scala 29:58] + node _T_43 = cat(UInt<63>("h00"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_44 = add(_T_42, _T_43) @[dec_tlu_ctl.scala 2596:65] + node mhpmc3_incr = tail(_T_44, 1) @[dec_tlu_ctl.scala 2596:65] + node _T_45 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2597:43] + node _T_46 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2597:83] + node mhpmc3_ns = mux(_T_45, io.dec_csr_wrdata_r, _T_46) @[dec_tlu_ctl.scala 2597:28] + node _T_47 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2599:52] + inst rvclkhdr of rvclkhdr @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr.io.en <= _T_47 @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_48 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_47 : @[Reg.scala 28:19] + _T_48 <= mhpmc3_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpmc3 <= _T_48 @[dec_tlu_ctl.scala 2599:19] + node _T_49 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2601:73] + node _T_50 = eq(_T_49, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2601:80] + node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_50) @[dec_tlu_ctl.scala 2601:51] + node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2602:45] + node _T_51 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2603:45] + node _T_52 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2603:85] + node mhpmc3h_ns = mux(_T_51, io.dec_csr_wrdata_r, _T_52) @[dec_tlu_ctl.scala 2603:29] + node _T_53 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2605:56] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_53 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_54 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_53 : @[Reg.scala 28:19] + _T_54 <= mhpmc3h_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpmc3h <= _T_54 @[dec_tlu_ctl.scala 2605:20] + node _T_55 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2612:72] + node _T_56 = eq(_T_55, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2612:79] + node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_56) @[dec_tlu_ctl.scala 2612:50] + node _T_57 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2613:30] + node _T_58 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2613:68] + node _T_59 = or(_T_57, _T_58) @[dec_tlu_ctl.scala 2613:46] + node _T_60 = orr(io.mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2613:96] + node mhpmc4_wr_en1 = and(_T_59, _T_60) @[dec_tlu_ctl.scala 2613:73] + node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2614:43] + node _T_61 = bits(io.mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2618:41] + node _T_62 = bits(io.mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2618:57] + node _T_63 = cat(_T_61, _T_62) @[Cat.scala 29:58] + node _T_64 = cat(UInt<63>("h00"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_65 = add(_T_63, _T_64) @[dec_tlu_ctl.scala 2618:65] + node mhpmc4_incr = tail(_T_65, 1) @[dec_tlu_ctl.scala 2618:65] + node _T_66 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2619:43] + node _T_67 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2619:70] + node _T_68 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2619:89] + node mhpmc4_ns = mux(_T_66, _T_67, _T_68) @[dec_tlu_ctl.scala 2619:28] + node _T_69 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2620:53] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_2.io.en <= _T_69 @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_70 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_69 : @[Reg.scala 28:19] + _T_70 <= mhpmc4_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpmc4 <= _T_70 @[dec_tlu_ctl.scala 2620:19] + node _T_71 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2622:73] + node _T_72 = eq(_T_71, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2622:80] + node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_72) @[dec_tlu_ctl.scala 2622:51] + node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2623:45] + node _T_73 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2624:45] + node _T_74 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2624:85] + node mhpmc4h_ns = mux(_T_73, io.dec_csr_wrdata_r, _T_74) @[dec_tlu_ctl.scala 2624:29] + node _T_75 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2625:56] + inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_3.io.en <= _T_75 @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_76 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_75 : @[Reg.scala 28:19] + _T_76 <= mhpmc4h_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpmc4h <= _T_76 @[dec_tlu_ctl.scala 2625:20] + node _T_77 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2631:72] + node _T_78 = eq(_T_77, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2631:79] + node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_78) @[dec_tlu_ctl.scala 2631:50] + node _T_79 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2632:30] + node _T_80 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2632:68] + node _T_81 = or(_T_79, _T_80) @[dec_tlu_ctl.scala 2632:46] + node _T_82 = orr(io.mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2632:96] + node mhpmc5_wr_en1 = and(_T_81, _T_82) @[dec_tlu_ctl.scala 2632:73] + node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2633:43] + node _T_83 = bits(io.mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2635:41] + node _T_84 = bits(io.mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2635:57] + node _T_85 = cat(_T_83, _T_84) @[Cat.scala 29:58] + node _T_86 = cat(UInt<63>("h00"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_87 = add(_T_85, _T_86) @[dec_tlu_ctl.scala 2635:65] + node mhpmc5_incr = tail(_T_87, 1) @[dec_tlu_ctl.scala 2635:65] + node _T_88 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2636:43] + node _T_89 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2636:83] + node mhpmc5_ns = mux(_T_88, io.dec_csr_wrdata_r, _T_89) @[dec_tlu_ctl.scala 2636:28] + node _T_90 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2638:53] + inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 404:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_4.io.en <= _T_90 @[lib.scala 407:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_91 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_90 : @[Reg.scala 28:19] + _T_91 <= mhpmc5_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpmc5 <= _T_91 @[dec_tlu_ctl.scala 2638:19] + node _T_92 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2640:73] + node _T_93 = eq(_T_92, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2640:80] + node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_93) @[dec_tlu_ctl.scala 2640:51] + node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2641:45] + node _T_94 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2642:45] + node _T_95 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2642:85] + node mhpmc5h_ns = mux(_T_94, io.dec_csr_wrdata_r, _T_95) @[dec_tlu_ctl.scala 2642:29] + node _T_96 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2644:56] + inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 404:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_5.io.en <= _T_96 @[lib.scala 407:17] + rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_97 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_96 : @[Reg.scala 28:19] + _T_97 <= mhpmc5h_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpmc5h <= _T_97 @[dec_tlu_ctl.scala 2644:20] + node _T_98 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2651:72] + node _T_99 = eq(_T_98, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2651:79] + node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_99) @[dec_tlu_ctl.scala 2651:50] + node _T_100 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2652:30] + node _T_101 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2652:68] + node _T_102 = or(_T_100, _T_101) @[dec_tlu_ctl.scala 2652:46] + node _T_103 = orr(io.mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2652:96] + node mhpmc6_wr_en1 = and(_T_102, _T_103) @[dec_tlu_ctl.scala 2652:73] + node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2653:43] + node _T_104 = bits(io.mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2655:41] + node _T_105 = bits(io.mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2655:57] + node _T_106 = cat(_T_104, _T_105) @[Cat.scala 29:58] + node _T_107 = cat(UInt<63>("h00"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_108 = add(_T_106, _T_107) @[dec_tlu_ctl.scala 2655:65] + node mhpmc6_incr = tail(_T_108, 1) @[dec_tlu_ctl.scala 2655:65] + node _T_109 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2656:43] + node _T_110 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2656:83] + node mhpmc6_ns = mux(_T_109, io.dec_csr_wrdata_r, _T_110) @[dec_tlu_ctl.scala 2656:28] + node _T_111 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2659:53] + inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 404:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_6.io.en <= _T_111 @[lib.scala 407:17] + rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_112 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_111 : @[Reg.scala 28:19] + _T_112 <= mhpmc6_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpmc6 <= _T_112 @[dec_tlu_ctl.scala 2659:19] + node _T_113 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2661:73] + node _T_114 = eq(_T_113, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2661:80] + node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_114) @[dec_tlu_ctl.scala 2661:51] + node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2662:45] + node _T_115 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2663:45] + node _T_116 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2663:85] + node mhpmc6h_ns = mux(_T_115, io.dec_csr_wrdata_r, _T_116) @[dec_tlu_ctl.scala 2663:29] + node _T_117 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2665:56] + inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 404:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_7.io.en <= _T_117 @[lib.scala 407:17] + rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_118 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_117 : @[Reg.scala 28:19] + _T_118 <= mhpmc6h_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpmc6h <= _T_118 @[dec_tlu_ctl.scala 2665:20] + node _T_119 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2671:50] + node _T_120 = gt(_T_119, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2671:56] + node _T_121 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2671:94] + node _T_122 = orr(_T_121) @[dec_tlu_ctl.scala 2671:102] + node _T_123 = or(_T_120, _T_122) @[dec_tlu_ctl.scala 2671:72] + node _T_124 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2672:38] + node _T_125 = lt(_T_124, UInt<10>("h0200")) @[dec_tlu_ctl.scala 2672:44] + node _T_126 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2672:82] + node _T_127 = gt(_T_126, UInt<10>("h038")) @[dec_tlu_ctl.scala 2672:88] + node _T_128 = and(_T_125, _T_127) @[dec_tlu_ctl.scala 2672:60] + node _T_129 = or(_T_123, _T_128) @[dec_tlu_ctl.scala 2671:107] + node _T_130 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2673:38] + node _T_131 = lt(_T_130, UInt<10>("h036")) @[dec_tlu_ctl.scala 2673:44] + node _T_132 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2673:82] + node _T_133 = gt(_T_132, UInt<10>("h032")) @[dec_tlu_ctl.scala 2673:88] + node _T_134 = and(_T_131, _T_133) @[dec_tlu_ctl.scala 2673:60] + node _T_135 = or(_T_129, _T_134) @[dec_tlu_ctl.scala 2672:103] + node _T_136 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2674:37] + node _T_137 = eq(_T_136, UInt<10>("h01d")) @[dec_tlu_ctl.scala 2674:43] + node _T_138 = or(_T_135, _T_137) @[dec_tlu_ctl.scala 2673:103] + node _T_139 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2674:81] + node _T_140 = eq(_T_139, UInt<10>("h021")) @[dec_tlu_ctl.scala 2674:87] + node zero_event_r = or(_T_138, _T_140) @[dec_tlu_ctl.scala 2674:59] + node _T_141 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2676:71] + node event_r = mux(zero_event_r, UInt<10>("h00"), _T_141) @[dec_tlu_ctl.scala 2676:26] + node _T_142 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2677:70] + node _T_143 = eq(_T_142, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2677:77] + node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_143) @[dec_tlu_ctl.scala 2677:48] + node _T_144 = bits(wr_mhpme3_r, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 404:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_8.io.en <= _T_144 @[lib.scala 407:17] + rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_145 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_144 : @[Reg.scala 28:19] + _T_145 <= event_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpme3 <= _T_145 @[dec_tlu_ctl.scala 2679:19] + node _T_146 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2684:70] + node _T_147 = eq(_T_146, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2684:77] + node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_147) @[dec_tlu_ctl.scala 2684:48] + node _T_148 = bits(wr_mhpme4_r, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 404:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_9.io.en <= _T_148 @[lib.scala 407:17] + rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_149 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_148 : @[Reg.scala 28:19] + _T_149 <= event_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpme4 <= _T_149 @[dec_tlu_ctl.scala 2685:19] + node _T_150 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2691:70] + node _T_151 = eq(_T_150, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2691:77] + node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_151) @[dec_tlu_ctl.scala 2691:48] + node _T_152 = bits(wr_mhpme5_r, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 404:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_10.io.en <= _T_152 @[lib.scala 407:17] + rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_153 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_152 : @[Reg.scala 28:19] + _T_153 <= event_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpme5 <= _T_153 @[dec_tlu_ctl.scala 2692:19] + node _T_154 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2698:70] + node _T_155 = eq(_T_154, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2698:77] + node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_155) @[dec_tlu_ctl.scala 2698:48] + node _T_156 = bits(wr_mhpme6_r, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_11 of rvclkhdr_11 @[lib.scala 404:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_11.io.en <= _T_156 @[lib.scala 407:17] + rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_157 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_156 : @[Reg.scala 28:19] + _T_157 <= event_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mhpme6 <= _T_157 @[dec_tlu_ctl.scala 2699:19] + + extmodule gated_latch_12 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_12 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_12 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_13 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_13 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_13 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_14 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_14 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_14 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_15 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_15 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_15 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_16 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_16 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_16 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_17 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_17 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_17 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_18 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_18 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_18 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_19 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_19 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_19 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_20 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_20 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_20 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_21 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_21 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_21 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_22 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_22 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_22 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_23 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_23 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_23 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_24 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_24 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_24 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_25 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_25 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_25 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_26 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_26 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_26 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_27 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_27 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_27 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_28 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_28 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_28 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_29 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_29 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_29 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_30 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_30 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_30 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_31 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_31 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_31 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_32 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_32 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_32 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_33 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_33 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_33 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_34 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_34 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_34 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_35 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_35 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_35 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_36 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_36 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_36 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_37 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_37 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_37 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_38 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_38 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_38 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_39 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_39 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_39 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_40 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_40 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_40 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_41 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_41 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_41 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_42 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_42 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_42 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_43 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_43 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_43 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_44 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_44 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_44 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_45 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_45 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_45 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_46 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_46 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_46 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module csr_tlu : + input clock : Clock + input reset : AsyncReset + output io : {flip free_l2clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_i0_decode_d : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip ifu_ic_debug_rd_data_valid : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_pmu_bus_trxn : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, flip dec_csr_wen_r : UInt<1>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_picio_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, dec_tlu_meipt : UInt<4>, flip pic_pl : UInt<4>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meihap : UInt<30>, flip pic_claimid : UInt<8>, flip iccm_dma_sb_error : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_trace_disable : UInt<1>, flip dec_illegal_inst : UInt<32>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip mexintpend : UInt<1>, flip exu_npc_r : UInt<31>, flip mpc_reset_run_req : UInt<1>, flip rst_vec : UInt<31>, flip core_id : UInt<28>, flip dec_timer_rddata_d : UInt<32>, flip dec_timer_read_d : UInt<1>, dec_csr_wen_r_mod : UInt<1>, flip rfpc_i0_r : UInt<1>, flip i0_trigger_hit_r : UInt<1>, fw_halt_req : UInt<1>, mstatus : UInt<2>, flip exc_or_int_valid_r : UInt<1>, flip mret_r : UInt<1>, mstatus_mie_ns : UInt<1>, flip dcsr_single_step_running_f : UInt<1>, dcsr : UInt<16>, mtvec : UInt<31>, mip : UInt<6>, flip dec_timer_t0_pulse : UInt<1>, flip dec_timer_t1_pulse : UInt<1>, flip timer_int_sync : UInt<1>, flip soft_int_sync : UInt<1>, mie_ns : UInt<6>, flip csr_wr_clk : Clock, flip ebreak_to_debug_mode_r : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip lsu_fir_error : UInt<2>, npc_r : UInt<31>, flip tlu_flush_lower_r_d1 : UInt<1>, flip dec_tlu_flush_noredir_r_d1 : UInt<1>, flip tlu_flush_path_r_d1 : UInt<31>, npc_r_d1 : UInt<31>, flip reset_delayed : UInt<1>, mepc : UInt<31>, flip interrupt_valid_r : UInt<1>, flip i0_exception_valid_r : UInt<1>, flip lsu_exc_valid_r : UInt<1>, flip mepc_trigger_hit_sel_pc_r : UInt<1>, flip lsu_single_ecc_error_r : UInt<1>, flip e4e5_int_clk : Clock, flip lsu_i0_exc_r : UInt<1>, flip inst_acc_r : UInt<1>, flip inst_acc_second_r : UInt<1>, flip take_nmi : UInt<1>, flip lsu_error_pkt_addr_r : UInt<32>, flip exc_cause_r : UInt<5>, flip i0_valid_wb : UInt<1>, flip exc_or_int_valid_r_d1 : UInt<1>, flip interrupt_valid_r_d1 : UInt<1>, flip clk_override : UInt<1>, flip i0_exception_valid_r_d1 : UInt<1>, flip exc_cause_wb : UInt<5>, flip nmi_lsu_store_type : UInt<1>, flip nmi_lsu_load_type : UInt<1>, flip tlu_i0_commit_cmt : UInt<1>, flip ebreak_r : UInt<1>, flip ecall_r : UInt<1>, flip illegal_r : UInt<1>, mdseac_locked_ns : UInt<1>, mdseac_locked_f : UInt<1>, flip nmi_int_detected_f : UInt<1>, flip internal_dbg_halt_mode_f2 : UInt<1>, flip ext_int_freeze : UInt<1>, ext_int_freeze_d1 : UInt<1>, take_ext_int_start_d1 : UInt<1>, take_ext_int_start_d2 : UInt<1>, take_ext_int_start_d3 : UInt<1>, flip ic_perr_r : UInt<1>, flip iccm_sbecc_r : UInt<1>, flip ifu_miss_state_idle_f : UInt<1>, flip lsu_idle_any_f : UInt<1>, flip dbg_tlu_halted_f : UInt<1>, flip dbg_tlu_halted : UInt<1>, flip debug_halt_req_f : UInt<1>, force_halt : UInt<1>, flip take_ext_int_start : UInt<1>, flip trigger_hit_dmode_r_d1 : UInt<1>, flip trigger_hit_r_d1 : UInt<1>, flip dcsr_single_step_done_f : UInt<1>, flip ebreak_to_debug_mode_r_d1 : UInt<1>, flip debug_halt_req : UInt<1>, flip allow_dbg_halt_csr_write : UInt<1>, flip internal_dbg_halt_mode_f : UInt<1>, flip enter_debug_halt_req : UInt<1>, flip internal_dbg_halt_mode : UInt<1>, flip request_debug_mode_done : UInt<1>, flip request_debug_mode_r : UInt<1>, dpc : UInt<31>, flip update_hit_bit_r : UInt<4>, flip take_timer_int : UInt<1>, flip take_int_timer0_int : UInt<1>, flip take_int_timer1_int : UInt<1>, flip take_ext_int : UInt<1>, flip tlu_flush_lower_r : UInt<1>, flip dec_tlu_br0_error_r : UInt<1>, flip dec_tlu_br0_start_error_r : UInt<1>, flip lsu_pmu_load_external_r : UInt<1>, flip lsu_pmu_store_external_r : UInt<1>, flip csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_meicpct : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}, mtdata1_t : UInt<10>[4], flip trigger_enabled : UInt<4>, lsu_exc_valid_r_d1 : UInt<1>} + + wire miccme_ce_req : UInt<1> + miccme_ce_req <= UInt<1>("h00") + wire mice_ce_req : UInt<1> + mice_ce_req <= UInt<1>("h00") + wire mdccme_ce_req : UInt<1> + mdccme_ce_req <= UInt<1>("h00") + wire pc_r_d1 : UInt<31> + pc_r_d1 <= UInt<1>("h00") + wire mpmc_b_ns : UInt<1> + mpmc_b_ns <= UInt<1>("h00") + wire mpmc_b : UInt<1> + mpmc_b <= UInt<1>("h00") + wire mcycleh : UInt<32> + mcycleh <= UInt<1>("h00") + wire wr_minstreth_r : UInt<1> + wr_minstreth_r <= UInt<1>("h00") + wire minstretl : UInt<32> + minstretl <= UInt<1>("h00") + wire minstreth : UInt<32> + minstreth <= UInt<1>("h00") + wire mfdc_ns : UInt<16> + mfdc_ns <= UInt<1>("h00") + wire mfdc_int : UInt<16> + mfdc_int <= UInt<1>("h00") + wire mhpme_vec : UInt<10>[4] @[dec_tlu_ctl.scala 1413:47] + wire mtdata2_t : UInt<32>[4] @[dec_tlu_ctl.scala 1414:73] + wire wr_meicpct_r : UInt<1> + wr_meicpct_r <= UInt<1>("h00") + wire force_halt_ctr_f : UInt<32> + force_halt_ctr_f <= UInt<1>("h00") + wire mdccmect_inc : UInt<27> + mdccmect_inc <= UInt<1>("h00") + wire miccmect_inc : UInt<27> + miccmect_inc <= UInt<1>("h00") + wire micect_inc : UInt<27> + micect_inc <= UInt<1>("h00") + wire mdseac_en : UInt<1> + mdseac_en <= UInt<1>("h00") + wire mie : UInt<6> + mie <= UInt<1>("h00") + wire mcyclel : UInt<32> + mcyclel <= UInt<1>("h00") + wire mscratch : UInt<32> + mscratch <= UInt<1>("h00") + wire mcause : UInt<32> + mcause <= UInt<1>("h00") + wire mscause : UInt<4> + mscause <= UInt<1>("h00") + wire mtval : UInt<32> + mtval <= UInt<1>("h00") + wire meicurpl : UInt<4> + meicurpl <= UInt<1>("h00") + wire meipt : UInt<4> + meipt <= UInt<1>("h00") + wire mfdc : UInt<19> + mfdc <= UInt<1>("h00") + wire mtsel : UInt<2> + mtsel <= UInt<1>("h00") + wire micect : UInt<32> + micect <= UInt<1>("h00") + wire miccmect : UInt<32> + miccmect <= UInt<1>("h00") + wire mdccmect : UInt<32> + mdccmect <= UInt<1>("h00") + wire mfdht : UInt<6> + mfdht <= UInt<1>("h00") + wire mfdhs : UInt<2> + mfdhs <= UInt<1>("h00") + wire mcountinhibit : UInt<7> + mcountinhibit <= UInt<1>("h00") + wire mpmc : UInt<1> + mpmc <= UInt<1>("h00") + wire dicad1 : UInt<32> + dicad1 <= UInt<1>("h00") + inst perfmux_flop of perf_mux_and_flops @[dec_tlu_ctl.scala 1455:34] + perfmux_flop.clock <= clock + perfmux_flop.reset <= reset + inst perf_csrs of perf_csr @[dec_tlu_ctl.scala 1456:31] + perf_csrs.clock <= clock + perf_csrs.reset <= reset + node _T = eq(io.i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1472:52] + node _T_1 = and(io.dec_csr_wen_r, _T) @[dec_tlu_ctl.scala 1472:50] + node _T_2 = eq(io.rfpc_i0_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1472:75] + node _T_3 = and(_T_1, _T_2) @[dec_tlu_ctl.scala 1472:73] + io.dec_csr_wen_r_mod <= _T_3 @[dec_tlu_ctl.scala 1472:30] + node _T_4 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1473:71] + node _T_5 = eq(_T_4, UInt<12>("h0300")) @[dec_tlu_ctl.scala 1473:78] + node wr_mstatus_r = and(io.dec_csr_wen_r_mod, _T_5) @[dec_tlu_ctl.scala 1473:49] + node _T_6 = eq(mpmc_b_ns, UInt<1>("h00")) @[dec_tlu_ctl.scala 1476:35] + node set_mie_pmu_fw_halt = and(_T_6, io.fw_halt_req) @[dec_tlu_ctl.scala 1476:46] + node _T_7 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1479:18] + node _T_8 = and(_T_7, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1479:32] + node _T_9 = bits(_T_8, 0, 0) @[dec_tlu_ctl.scala 1479:57] + node _T_10 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1479:81] + node _T_11 = bits(_T_10, 0, 0) @[dec_tlu_ctl.scala 1479:81] + node _T_12 = cat(_T_11, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_13 = and(wr_mstatus_r, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1480:31] + node _T_14 = bits(_T_13, 0, 0) @[dec_tlu_ctl.scala 1480:56] + node _T_15 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1480:89] + node _T_16 = cat(_T_15, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_17 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1481:30] + node _T_18 = and(io.mret_r, _T_17) @[dec_tlu_ctl.scala 1481:28] + node _T_19 = bits(_T_18, 0, 0) @[dec_tlu_ctl.scala 1481:54] + node _T_20 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1481:83] + node _T_21 = cat(UInt<1>("h01"), _T_20) @[Cat.scala 29:58] + node _T_22 = bits(set_mie_pmu_fw_halt, 0, 0) @[dec_tlu_ctl.scala 1482:39] + node _T_23 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1482:63] + node _T_24 = cat(_T_23, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_25 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1483:33] + node _T_26 = and(wr_mstatus_r, _T_25) @[dec_tlu_ctl.scala 1483:31] + node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 1483:57] + node _T_28 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1483:90] + node _T_29 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1483:114] + node _T_30 = cat(_T_28, _T_29) @[Cat.scala 29:58] + node _T_31 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1484:18] + node _T_32 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1484:34] + node _T_33 = and(_T_31, _T_32) @[dec_tlu_ctl.scala 1484:32] + node _T_34 = eq(io.mret_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1484:59] + node _T_35 = and(_T_33, _T_34) @[dec_tlu_ctl.scala 1484:57] + node _T_36 = eq(set_mie_pmu_fw_halt, UInt<1>("h00")) @[dec_tlu_ctl.scala 1484:72] + node _T_37 = and(_T_35, _T_36) @[dec_tlu_ctl.scala 1484:70] + node _T_38 = bits(_T_37, 0, 0) @[dec_tlu_ctl.scala 1484:94] + node _T_39 = mux(_T_9, _T_12, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_40 = mux(_T_14, _T_16, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_41 = mux(_T_19, _T_21, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_42 = mux(_T_22, _T_24, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_43 = mux(_T_27, _T_30, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_44 = mux(_T_38, io.mstatus, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_45 = or(_T_39, _T_40) @[Mux.scala 27:72] + node _T_46 = or(_T_45, _T_41) @[Mux.scala 27:72] + node _T_47 = or(_T_46, _T_42) @[Mux.scala 27:72] + node _T_48 = or(_T_47, _T_43) @[Mux.scala 27:72] + node _T_49 = or(_T_48, _T_44) @[Mux.scala 27:72] + wire mstatus_ns : UInt<2> @[Mux.scala 27:72] + mstatus_ns <= _T_49 @[Mux.scala 27:72] + node _T_50 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1489:40] + node _T_51 = bits(_T_50, 0, 0) @[dec_tlu_ctl.scala 1489:40] + node _T_52 = not(io.dcsr_single_step_running_f) @[dec_tlu_ctl.scala 1489:57] + node _T_53 = bits(io.dcsr, 11, 11) @[dec_tlu_ctl.scala 1489:97] + node _T_54 = or(_T_52, _T_53) @[dec_tlu_ctl.scala 1489:88] + node _T_55 = and(_T_51, _T_54) @[dec_tlu_ctl.scala 1489:54] + io.mstatus_mie_ns <= _T_55 @[dec_tlu_ctl.scala 1489:27] + node _T_56 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1500:69] + node _T_57 = eq(_T_56, UInt<12>("h0305")) @[dec_tlu_ctl.scala 1500:76] + node wr_mtvec_r = and(io.dec_csr_wen_r_mod, _T_57) @[dec_tlu_ctl.scala 1500:47] + node _T_58 = bits(io.dec_csr_wrdata_r, 31, 2) @[dec_tlu_ctl.scala 1501:47] + node _T_59 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1501:75] + node mtvec_ns = cat(_T_58, _T_59) @[Cat.scala 29:58] + node _T_60 = bits(wr_mtvec_r, 0, 0) @[dec_tlu_ctl.scala 1502:49] + inst rvclkhdr of rvclkhdr_12 @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 406:18] + rvclkhdr.io.en <= _T_60 @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_61 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_60 : @[Reg.scala 28:19] + _T_61 <= mtvec_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mtvec <= _T_61 @[dec_tlu_ctl.scala 1502:18] + node _T_62 = or(mdccme_ce_req, miccme_ce_req) @[dec_tlu_ctl.scala 1514:37] + node ce_int = or(_T_62, mice_ce_req) @[dec_tlu_ctl.scala 1514:53] + node _T_63 = cat(io.mexintpend, io.timer_int_sync) @[Cat.scala 29:58] + node _T_64 = cat(_T_63, io.soft_int_sync) @[Cat.scala 29:58] + node _T_65 = cat(ce_int, io.dec_timer_t0_pulse) @[Cat.scala 29:58] + node _T_66 = cat(_T_65, io.dec_timer_t1_pulse) @[Cat.scala 29:58] + node mip_ns = cat(_T_66, _T_64) @[Cat.scala 29:58] + node _T_67 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1530:67] + node _T_68 = eq(_T_67, UInt<12>("h0304")) @[dec_tlu_ctl.scala 1530:74] + node wr_mie_r = and(io.dec_csr_wen_r_mod, _T_68) @[dec_tlu_ctl.scala 1530:45] + node _T_69 = bits(wr_mie_r, 0, 0) @[dec_tlu_ctl.scala 1531:35] + node _T_70 = bits(io.dec_csr_wrdata_r, 30, 28) @[dec_tlu_ctl.scala 1531:66] + node _T_71 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1531:95] + node _T_72 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1531:120] + node _T_73 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1531:144] + node _T_74 = cat(_T_72, _T_73) @[Cat.scala 29:58] + node _T_75 = cat(_T_70, _T_71) @[Cat.scala 29:58] + node _T_76 = cat(_T_75, _T_74) @[Cat.scala 29:58] + node _T_77 = mux(_T_69, _T_76, mie) @[dec_tlu_ctl.scala 1531:25] + io.mie_ns <= _T_77 @[dec_tlu_ctl.scala 1531:19] + reg _T_78 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1533:24] + _T_78 <= io.mie_ns @[dec_tlu_ctl.scala 1533:24] + mie <= _T_78 @[dec_tlu_ctl.scala 1532:13] + node _T_79 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1539:70] + node kill_ebreak_count_r = and(io.ebreak_to_debug_mode_r, _T_79) @[dec_tlu_ctl.scala 1539:61] + node _T_80 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1541:71] + node _T_81 = eq(_T_80, UInt<12>("h0b00")) @[dec_tlu_ctl.scala 1541:78] + node wr_mcyclel_r = and(io.dec_csr_wen_r_mod, _T_81) @[dec_tlu_ctl.scala 1541:49] + node _T_82 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1543:87] + node _T_83 = and(io.dec_tlu_dbg_halted, _T_82) @[dec_tlu_ctl.scala 1543:78] + node _T_84 = or(kill_ebreak_count_r, _T_83) @[dec_tlu_ctl.scala 1543:53] + node _T_85 = or(_T_84, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 1543:101] + node _T_86 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 1543:143] + node _T_87 = or(_T_85, _T_86) @[dec_tlu_ctl.scala 1543:128] + node mcyclel_cout_in = not(_T_87) @[dec_tlu_ctl.scala 1543:31] + wire mcyclel_inc1 : UInt<9> + mcyclel_inc1 <= UInt<1>("h00") + wire mcyclel_inc2 : UInt<25> + mcyclel_inc2 <= UInt<1>("h00") + node _T_88 = bits(mcyclel, 7, 0) @[dec_tlu_ctl.scala 1548:32] + node _T_89 = cat(UInt<7>("h00"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_90 = add(_T_88, _T_89) @[dec_tlu_ctl.scala 1548:38] + mcyclel_inc1 <= _T_90 @[dec_tlu_ctl.scala 1548:22] + node _T_91 = bits(mcyclel, 31, 8) @[dec_tlu_ctl.scala 1549:32] + node _T_92 = bits(mcyclel_inc1, 8, 8) @[dec_tlu_ctl.scala 1549:70] + node _T_93 = cat(UInt<23>("h00"), _T_92) @[Cat.scala 29:58] + node _T_94 = add(_T_91, _T_93) @[dec_tlu_ctl.scala 1549:39] + mcyclel_inc2 <= _T_94 @[dec_tlu_ctl.scala 1549:22] + node _T_95 = bits(mcyclel_inc2, 23, 0) @[dec_tlu_ctl.scala 1550:47] + node _T_96 = bits(mcyclel_inc1, 7, 0) @[dec_tlu_ctl.scala 1550:66] + node mcyclel_inc = cat(_T_95, _T_96) @[Cat.scala 29:58] + node _T_97 = bits(wr_mcyclel_r, 0, 0) @[dec_tlu_ctl.scala 1551:43] + node _T_98 = bits(mcyclel_inc, 31, 0) @[dec_tlu_ctl.scala 1551:83] + node mcyclel_ns = mux(_T_97, io.dec_csr_wrdata_r, _T_98) @[dec_tlu_ctl.scala 1551:29] + node _T_99 = bits(mcyclel_inc2, 24, 24) @[dec_tlu_ctl.scala 1552:40] + node mcyclel_cout = bits(_T_99, 0, 0) @[dec_tlu_ctl.scala 1552:45] + node _T_100 = bits(mcyclel_ns, 31, 8) @[dec_tlu_ctl.scala 1553:41] + node _T_101 = bits(mcyclel_inc1, 8, 8) @[dec_tlu_ctl.scala 1553:78] + node _T_102 = and(_T_101, mcyclel_cout_in) @[dec_tlu_ctl.scala 1553:82] + node _T_103 = bits(_T_102, 0, 0) @[dec_tlu_ctl.scala 1553:108] + node _T_104 = or(wr_mcyclel_r, _T_103) @[dec_tlu_ctl.scala 1553:63] + node _T_105 = bits(_T_104, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_1 of rvclkhdr_13 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_105 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_106 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_105 : @[Reg.scala 28:19] + _T_106 <= _T_100 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_107 = bits(mcyclel_ns, 7, 0) @[dec_tlu_ctl.scala 1553:163] + node _T_108 = or(wr_mcyclel_r, mcyclel_cout_in) @[dec_tlu_ctl.scala 1553:184] + node _T_109 = bits(_T_108, 0, 0) @[dec_tlu_ctl.scala 1553:210] + inst rvclkhdr_2 of rvclkhdr_14 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_2.io.en <= _T_109 @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_110 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_109 : @[Reg.scala 28:19] + _T_110 <= _T_107 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_111 = cat(_T_106, _T_110) @[Cat.scala 29:58] + mcyclel <= _T_111 @[dec_tlu_ctl.scala 1553:17] + node _T_112 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1560:71] + node _T_113 = eq(_T_112, UInt<12>("h0b80")) @[dec_tlu_ctl.scala 1560:78] + node wr_mcycleh_r = and(io.dec_csr_wen_r_mod, _T_113) @[dec_tlu_ctl.scala 1560:49] + node _T_114 = cat(UInt<31>("h00"), perfmux_flop.io.mcyclel_cout_f) @[Cat.scala 29:58] + node _T_115 = add(mcycleh, _T_114) @[dec_tlu_ctl.scala 1562:35] + node mcycleh_inc = tail(_T_115, 1) @[dec_tlu_ctl.scala 1562:35] + node _T_116 = bits(wr_mcycleh_r, 0, 0) @[dec_tlu_ctl.scala 1563:43] + node mcycleh_ns = mux(_T_116, io.dec_csr_wrdata_r, mcycleh_inc) @[dec_tlu_ctl.scala 1563:29] + node _T_117 = or(wr_mcycleh_r, perfmux_flop.io.mcyclel_cout_f) @[dec_tlu_ctl.scala 1565:53] + node _T_118 = bits(_T_117, 0, 0) @[dec_tlu_ctl.scala 1565:87] + inst rvclkhdr_3 of rvclkhdr_15 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_3.io.en <= _T_118 @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_119 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_118 : @[Reg.scala 28:19] + _T_119 <= mcycleh_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mcycleh <= _T_119 @[dec_tlu_ctl.scala 1565:17] + node _T_120 = or(io.ebreak_r, io.ecall_r) @[dec_tlu_ctl.scala 1579:81] + node _T_121 = or(_T_120, io.ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 1579:94] + node _T_122 = or(_T_121, io.illegal_r) @[dec_tlu_ctl.scala 1579:122] + node _T_123 = bits(mcountinhibit, 2, 2) @[dec_tlu_ctl.scala 1579:152] + node _T_124 = or(_T_122, _T_123) @[dec_tlu_ctl.scala 1579:137] + node _T_125 = eq(_T_124, UInt<1>("h00")) @[dec_tlu_ctl.scala 1579:67] + node _T_126 = and(io.dec_tlu_i0_valid_r, _T_125) @[dec_tlu_ctl.scala 1579:65] + node i0_valid_no_ebreak_ecall_r = bits(_T_126, 0, 0) @[dec_tlu_ctl.scala 1579:164] + node _T_127 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1581:73] + node _T_128 = eq(_T_127, UInt<12>("h0b02")) @[dec_tlu_ctl.scala 1581:80] + node wr_minstretl_r = and(io.dec_csr_wen_r_mod, _T_128) @[dec_tlu_ctl.scala 1581:51] + wire minstretl_inc1 : UInt<9> + minstretl_inc1 <= UInt<1>("h00") + wire minstretl_inc2 : UInt<25> + minstretl_inc2 <= UInt<1>("h00") + node _T_129 = bits(minstretl, 7, 0) @[dec_tlu_ctl.scala 1585:36] + node _T_130 = cat(UInt<7>("h00"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_131 = add(_T_129, _T_130) @[dec_tlu_ctl.scala 1585:42] + minstretl_inc1 <= _T_131 @[dec_tlu_ctl.scala 1585:24] + node _T_132 = bits(minstretl, 31, 8) @[dec_tlu_ctl.scala 1586:36] + node _T_133 = bits(minstretl_inc1, 8, 8) @[dec_tlu_ctl.scala 1586:75] + node _T_134 = cat(UInt<23>("h00"), _T_133) @[Cat.scala 29:58] + node _T_135 = add(_T_132, _T_134) @[dec_tlu_ctl.scala 1586:43] + minstretl_inc2 <= _T_135 @[dec_tlu_ctl.scala 1586:24] + node minstretl_cout = bits(minstretl_inc2, 24, 24) @[dec_tlu_ctl.scala 1587:44] + node _T_136 = bits(minstretl_inc2, 23, 0) @[dec_tlu_ctl.scala 1588:47] + node _T_137 = bits(minstretl_inc1, 7, 0) @[dec_tlu_ctl.scala 1588:68] + node minstretl_inc = cat(_T_136, _T_137) @[Cat.scala 29:58] + node _T_138 = and(i0_valid_no_ebreak_ecall_r, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 1589:59] + node minstret_enable = or(_T_138, wr_minstretl_r) @[dec_tlu_ctl.scala 1589:83] + node _T_139 = eq(wr_minstreth_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1590:50] + node _T_140 = and(minstretl_cout, _T_139) @[dec_tlu_ctl.scala 1590:48] + node _T_141 = and(_T_140, i0_valid_no_ebreak_ecall_r) @[dec_tlu_ctl.scala 1590:66] + node _T_142 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1590:97] + node minstretl_cout_ns = and(_T_141, _T_142) @[dec_tlu_ctl.scala 1590:95] + node _T_143 = bits(wr_minstretl_r, 0, 0) @[dec_tlu_ctl.scala 1593:47] + node _T_144 = bits(minstretl_inc, 31, 0) @[dec_tlu_ctl.scala 1593:90] + node minstretl_ns = mux(_T_143, io.dec_csr_wrdata_r, _T_144) @[dec_tlu_ctl.scala 1593:31] + node _T_145 = bits(minstretl_ns, 31, 8) @[dec_tlu_ctl.scala 1595:45] + node _T_146 = bits(minstretl_inc1, 8, 8) @[dec_tlu_ctl.scala 1595:84] + node _T_147 = and(_T_146, minstret_enable) @[dec_tlu_ctl.scala 1595:88] + node _T_148 = or(wr_minstretl_r, _T_147) @[dec_tlu_ctl.scala 1595:67] + node _T_149 = bits(_T_148, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_4 of rvclkhdr_16 @[lib.scala 404:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_4.io.en <= _T_149 @[lib.scala 407:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_150 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_149 : @[Reg.scala 28:19] + _T_150 <= _T_145 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_151 = bits(minstretl_ns, 7, 0) @[dec_tlu_ctl.scala 1595:146] + node _T_152 = bits(minstret_enable, 0, 0) @[dec_tlu_ctl.scala 1595:168] + inst rvclkhdr_5 of rvclkhdr_17 @[lib.scala 404:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_5.io.en <= _T_152 @[lib.scala 407:17] + rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_153 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_152 : @[Reg.scala 28:19] + _T_153 <= _T_151 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_154 = cat(_T_150, _T_153) @[Cat.scala 29:58] + minstretl <= _T_154 @[dec_tlu_ctl.scala 1595:19] + node _T_155 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1605:71] + node _T_156 = eq(_T_155, UInt<12>("h0b82")) @[dec_tlu_ctl.scala 1605:78] + node _T_157 = and(io.dec_csr_wen_r_mod, _T_156) @[dec_tlu_ctl.scala 1605:49] + node _T_158 = bits(_T_157, 0, 0) @[dec_tlu_ctl.scala 1605:94] + wr_minstreth_r <= _T_158 @[dec_tlu_ctl.scala 1605:24] + node _T_159 = cat(UInt<31>("h00"), perfmux_flop.io.minstretl_cout_f) @[Cat.scala 29:58] + node _T_160 = add(minstreth, _T_159) @[dec_tlu_ctl.scala 1609:39] + node minstreth_inc = tail(_T_160, 1) @[dec_tlu_ctl.scala 1609:39] + node _T_161 = bits(wr_minstreth_r, 0, 0) @[dec_tlu_ctl.scala 1610:48] + node minstreth_ns = mux(_T_161, io.dec_csr_wrdata_r, minstreth_inc) @[dec_tlu_ctl.scala 1610:32] + node _T_162 = and(perfmux_flop.io.minstret_enable_f, perfmux_flop.io.minstretl_cout_f) @[dec_tlu_ctl.scala 1612:79] + node _T_163 = or(_T_162, wr_minstreth_r) @[dec_tlu_ctl.scala 1612:116] + node _T_164 = bits(_T_163, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_6 of rvclkhdr_18 @[lib.scala 404:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_6.io.en <= _T_164 @[lib.scala 407:17] + rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_165 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_164 : @[Reg.scala 28:19] + _T_165 <= minstreth_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + minstreth <= _T_165 @[dec_tlu_ctl.scala 1612:19] + node _T_166 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1620:72] + node _T_167 = eq(_T_166, UInt<12>("h0340")) @[dec_tlu_ctl.scala 1620:79] + node wr_mscratch_r = and(io.dec_csr_wen_r_mod, _T_167) @[dec_tlu_ctl.scala 1620:50] + node _T_168 = bits(wr_mscratch_r, 0, 0) @[dec_tlu_ctl.scala 1622:62] + inst rvclkhdr_7 of rvclkhdr_19 @[lib.scala 404:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_7.io.en <= _T_168 @[lib.scala 407:17] + rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_169 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_168 : @[Reg.scala 28:19] + _T_169 <= io.dec_csr_wrdata_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mscratch <= _T_169 @[dec_tlu_ctl.scala 1622:18] + node _T_170 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1631:29] + node _T_171 = eq(io.tlu_flush_lower_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1631:54] + node _T_172 = and(_T_170, _T_171) @[dec_tlu_ctl.scala 1631:52] + node sel_exu_npc_r = and(_T_172, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1631:79] + node _T_173 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1632:31] + node _T_174 = and(_T_173, io.tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 1632:54] + node _T_175 = eq(io.dec_tlu_flush_noredir_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1632:82] + node sel_flush_npc_r = and(_T_174, _T_175) @[dec_tlu_ctl.scala 1632:80] + node _T_176 = eq(sel_exu_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1633:30] + node _T_177 = eq(sel_flush_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1633:47] + node sel_hold_npc_r = and(_T_176, _T_177) @[dec_tlu_ctl.scala 1633:45] + node _T_178 = bits(sel_exu_npc_r, 0, 0) @[dec_tlu_ctl.scala 1636:31] + node _T_179 = eq(io.mpc_reset_run_req, UInt<1>("h00")) @[dec_tlu_ctl.scala 1637:18] + node _T_180 = and(_T_179, io.reset_delayed) @[dec_tlu_ctl.scala 1637:40] + node _T_181 = bits(_T_180, 0, 0) @[dec_tlu_ctl.scala 1637:60] + node _T_182 = bits(sel_flush_npc_r, 0, 0) @[dec_tlu_ctl.scala 1638:33] + node _T_183 = bits(sel_hold_npc_r, 0, 0) @[dec_tlu_ctl.scala 1639:32] + node _T_184 = mux(_T_178, io.exu_npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_185 = mux(_T_181, io.rst_vec, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_186 = mux(_T_182, io.tlu_flush_path_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_187 = mux(_T_183, io.npc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_188 = or(_T_184, _T_185) @[Mux.scala 27:72] + node _T_189 = or(_T_188, _T_186) @[Mux.scala 27:72] + node _T_190 = or(_T_189, _T_187) @[Mux.scala 27:72] + wire _T_191 : UInt<31> @[Mux.scala 27:72] + _T_191 <= _T_190 @[Mux.scala 27:72] + io.npc_r <= _T_191 @[dec_tlu_ctl.scala 1635:18] + node _T_192 = or(sel_exu_npc_r, sel_flush_npc_r) @[dec_tlu_ctl.scala 1641:58] + node _T_193 = or(_T_192, io.reset_delayed) @[dec_tlu_ctl.scala 1641:76] + node _T_194 = bits(_T_193, 0, 0) @[dec_tlu_ctl.scala 1641:96] + wire _T_195 : UInt<31> @[lib.scala 648:38] + _T_195 <= UInt<1>("h00") @[lib.scala 648:38] + reg _T_196 : UInt, clock with : (reset => (reset, _T_195)) @[Reg.scala 27:20] + when _T_194 : @[Reg.scala 28:19] + _T_196 <= io.npc_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.npc_r_d1 <= _T_196 @[dec_tlu_ctl.scala 1641:21] + node _T_197 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1644:28] + node _T_198 = and(_T_197, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1644:51] + node pc0_valid_r = bits(_T_198, 0, 0) @[dec_tlu_ctl.scala 1644:76] + node _T_199 = not(pc0_valid_r) @[dec_tlu_ctl.scala 1648:17] + node _T_200 = mux(pc0_valid_r, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_201 = mux(_T_199, pc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_202 = or(_T_200, _T_201) @[Mux.scala 27:72] + wire pc_r : UInt<31> @[Mux.scala 27:72] + pc_r <= _T_202 @[Mux.scala 27:72] + wire _T_203 : UInt<31> @[lib.scala 648:38] + _T_203 <= UInt<1>("h00") @[lib.scala 648:38] + reg _T_204 : UInt, clock with : (reset => (reset, _T_203)) @[Reg.scala 27:20] + when pc0_valid_r : @[Reg.scala 28:19] + _T_204 <= pc_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + pc_r_d1 <= _T_204 @[dec_tlu_ctl.scala 1650:17] + node _T_205 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1652:68] + node _T_206 = eq(_T_205, UInt<12>("h0341")) @[dec_tlu_ctl.scala 1652:75] + node wr_mepc_r = and(io.dec_csr_wen_r_mod, _T_206) @[dec_tlu_ctl.scala 1652:46] + node _T_207 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1655:42] + node _T_208 = or(_T_207, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1655:63] + node _T_209 = bits(_T_208, 0, 0) @[dec_tlu_ctl.scala 1655:95] + node _T_210 = bits(io.interrupt_valid_r, 0, 0) @[dec_tlu_ctl.scala 1656:40] + node _T_211 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1657:30] + node _T_212 = and(wr_mepc_r, _T_211) @[dec_tlu_ctl.scala 1657:28] + node _T_213 = bits(_T_212, 0, 0) @[dec_tlu_ctl.scala 1657:54] + node _T_214 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 1657:119] + node _T_215 = eq(wr_mepc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1658:18] + node _T_216 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1658:31] + node _T_217 = and(_T_215, _T_216) @[dec_tlu_ctl.scala 1658:29] + node _T_218 = bits(_T_217, 0, 0) @[dec_tlu_ctl.scala 1658:55] + node _T_219 = mux(_T_209, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_220 = mux(_T_210, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_221 = mux(_T_213, _T_214, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_222 = mux(_T_218, io.mepc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_223 = or(_T_219, _T_220) @[Mux.scala 27:72] + node _T_224 = or(_T_223, _T_221) @[Mux.scala 27:72] + node _T_225 = or(_T_224, _T_222) @[Mux.scala 27:72] + wire mepc_ns : UInt<31> @[Mux.scala 27:72] + mepc_ns <= _T_225 @[Mux.scala 27:72] + node _T_226 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1660:59] + node _T_227 = or(_T_226, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1660:80] + node _T_228 = or(_T_227, io.interrupt_valid_r) @[dec_tlu_ctl.scala 1660:111] + node _T_229 = or(_T_228, wr_mepc_r) @[dec_tlu_ctl.scala 1660:134] + node _T_230 = bits(_T_229, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_8 of rvclkhdr_20 @[lib.scala 404:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_8.io.en <= _T_230 @[lib.scala 407:17] + rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_231 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_230 : @[Reg.scala 28:19] + _T_231 <= mepc_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mepc <= _T_231 @[dec_tlu_ctl.scala 1660:17] + node _T_232 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1668:70] + node _T_233 = eq(_T_232, UInt<12>("h0342")) @[dec_tlu_ctl.scala 1668:77] + node wr_mcause_r = and(io.dec_csr_wen_r_mod, _T_233) @[dec_tlu_ctl.scala 1668:48] + node _T_234 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1669:58] + node mcause_sel_nmi_store = and(_T_234, io.nmi_lsu_store_type) @[dec_tlu_ctl.scala 1669:72] + node _T_235 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1670:57] + node mcause_sel_nmi_load = and(_T_235, io.nmi_lsu_load_type) @[dec_tlu_ctl.scala 1670:71] + node _T_236 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1671:55] + node _T_237 = and(_T_236, io.take_ext_int_start_d3) @[dec_tlu_ctl.scala 1671:69] + node _T_238 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1671:115] + node _T_239 = and(_T_237, _T_238) @[dec_tlu_ctl.scala 1671:96] + node _T_240 = eq(io.nmi_int_detected_f, UInt<1>("h00")) @[dec_tlu_ctl.scala 1671:121] + node mcause_sel_nmi_ext = and(_T_239, _T_240) @[dec_tlu_ctl.scala 1671:119] + node _T_241 = andr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1678:58] + node _T_242 = bits(io.lsu_fir_error, 1, 1) @[dec_tlu_ctl.scala 1678:81] + node _T_243 = bits(io.lsu_fir_error, 0, 0) @[dec_tlu_ctl.scala 1678:104] + node _T_244 = not(_T_243) @[dec_tlu_ctl.scala 1678:87] + node _T_245 = and(_T_242, _T_244) @[dec_tlu_ctl.scala 1678:85] + node mcause_fir_error_type = cat(_T_241, _T_245) @[Cat.scala 29:58] + node _T_246 = bits(mcause_sel_nmi_store, 0, 0) @[dec_tlu_ctl.scala 1681:38] + node _T_247 = bits(mcause_sel_nmi_load, 0, 0) @[dec_tlu_ctl.scala 1682:37] + node _T_248 = bits(mcause_sel_nmi_ext, 0, 0) @[dec_tlu_ctl.scala 1683:36] + node _T_249 = cat(UInt<28>("h0f000100"), UInt<2>("h00")) @[Cat.scala 29:58] + node _T_250 = cat(_T_249, mcause_fir_error_type) @[Cat.scala 29:58] + node _T_251 = eq(io.take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 1684:42] + node _T_252 = and(io.exc_or_int_valid_r, _T_251) @[dec_tlu_ctl.scala 1684:40] + node _T_253 = bits(_T_252, 0, 0) @[dec_tlu_ctl.scala 1684:56] + node _T_254 = cat(io.interrupt_valid_r, UInt<26>("h00")) @[Cat.scala 29:58] + node _T_255 = cat(_T_254, io.exc_cause_r) @[Cat.scala 29:58] + node _T_256 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1685:32] + node _T_257 = and(wr_mcause_r, _T_256) @[dec_tlu_ctl.scala 1685:30] + node _T_258 = bits(_T_257, 0, 0) @[dec_tlu_ctl.scala 1685:56] + node _T_259 = eq(wr_mcause_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1686:18] + node _T_260 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1686:33] + node _T_261 = and(_T_259, _T_260) @[dec_tlu_ctl.scala 1686:31] + node _T_262 = bits(_T_261, 0, 0) @[dec_tlu_ctl.scala 1686:57] + node _T_263 = mux(_T_246, UInt<32>("h0f0000000"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_264 = mux(_T_247, UInt<32>("h0f0000001"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_265 = mux(_T_248, _T_250, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_266 = mux(_T_253, _T_255, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_267 = mux(_T_258, io.dec_csr_wrdata_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_268 = mux(_T_262, mcause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_269 = or(_T_263, _T_264) @[Mux.scala 27:72] + node _T_270 = or(_T_269, _T_265) @[Mux.scala 27:72] + node _T_271 = or(_T_270, _T_266) @[Mux.scala 27:72] + node _T_272 = or(_T_271, _T_267) @[Mux.scala 27:72] + node _T_273 = or(_T_272, _T_268) @[Mux.scala 27:72] + wire mcause_ns : UInt<32> @[Mux.scala 27:72] + mcause_ns <= _T_273 @[Mux.scala 27:72] + node _T_274 = or(io.exc_or_int_valid_r, wr_mcause_r) @[dec_tlu_ctl.scala 1688:58] + node _T_275 = bits(_T_274, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_9 of rvclkhdr_21 @[lib.scala 404:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_9.io.en <= _T_275 @[lib.scala 407:17] + rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_276 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_275 : @[Reg.scala 28:19] + _T_276 <= mcause_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mcause <= _T_276 @[dec_tlu_ctl.scala 1688:16] + node _T_277 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1695:71] + node _T_278 = eq(_T_277, UInt<12>("h07ff")) @[dec_tlu_ctl.scala 1695:78] + node wr_mscause_r = and(io.dec_csr_wen_r_mod, _T_278) @[dec_tlu_ctl.scala 1695:49] + node _T_279 = eq(io.dec_tlu_packet_r.icaf_type, UInt<2>("h00")) @[dec_tlu_ctl.scala 1697:63] + node _T_280 = cat(UInt<2>("h00"), io.dec_tlu_packet_r.icaf_type) @[Cat.scala 29:58] + node ifu_mscause = mux(_T_279, UInt<4>("h09"), _T_280) @[dec_tlu_ctl.scala 1697:31] + node _T_281 = bits(io.lsu_i0_exc_r, 0, 0) @[dec_tlu_ctl.scala 1700:33] + node _T_282 = bits(io.i0_trigger_hit_r, 0, 0) @[dec_tlu_ctl.scala 1701:37] + node _T_283 = bits(io.ebreak_r, 0, 0) @[dec_tlu_ctl.scala 1702:29] + node _T_284 = bits(io.inst_acc_r, 0, 0) @[dec_tlu_ctl.scala 1703:31] + node _T_285 = mux(_T_281, io.lsu_error_pkt_r.bits.mscause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_286 = mux(_T_282, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_287 = mux(_T_283, UInt<4>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_288 = mux(_T_284, ifu_mscause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_289 = or(_T_285, _T_286) @[Mux.scala 27:72] + node _T_290 = or(_T_289, _T_287) @[Mux.scala 27:72] + node _T_291 = or(_T_290, _T_288) @[Mux.scala 27:72] + wire mscause_type : UInt<4> @[Mux.scala 27:72] + mscause_type <= _T_291 @[Mux.scala 27:72] + node _T_292 = bits(io.exc_or_int_valid_r, 0, 0) @[dec_tlu_ctl.scala 1707:41] + node _T_293 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1708:33] + node _T_294 = and(wr_mscause_r, _T_293) @[dec_tlu_ctl.scala 1708:31] + node _T_295 = bits(_T_294, 0, 0) @[dec_tlu_ctl.scala 1708:57] + node _T_296 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1708:96] + node _T_297 = eq(wr_mscause_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1709:18] + node _T_298 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1709:34] + node _T_299 = and(_T_297, _T_298) @[dec_tlu_ctl.scala 1709:32] + node _T_300 = bits(_T_299, 0, 0) @[dec_tlu_ctl.scala 1709:58] + node _T_301 = mux(_T_292, mscause_type, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_302 = mux(_T_295, _T_296, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_303 = mux(_T_300, mscause, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_304 = or(_T_301, _T_302) @[Mux.scala 27:72] + node _T_305 = or(_T_304, _T_303) @[Mux.scala 27:72] + wire mscause_ns : UInt<4> @[Mux.scala 27:72] + mscause_ns <= _T_305 @[Mux.scala 27:72] + reg _T_306 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1711:54] + _T_306 <= mscause_ns @[dec_tlu_ctl.scala 1711:54] + mscause <= _T_306 @[dec_tlu_ctl.scala 1711:17] + node _T_307 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1718:69] + node _T_308 = eq(_T_307, UInt<12>("h0343")) @[dec_tlu_ctl.scala 1718:76] + node wr_mtval_r = and(io.dec_csr_wen_r_mod, _T_308) @[dec_tlu_ctl.scala 1718:47] + node _T_309 = not(io.inst_acc_second_r) @[dec_tlu_ctl.scala 1719:90] + node _T_310 = and(io.inst_acc_r, _T_309) @[dec_tlu_ctl.scala 1719:88] + node _T_311 = or(io.ebreak_r, _T_310) @[dec_tlu_ctl.scala 1719:71] + node _T_312 = or(_T_311, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1719:113] + node _T_313 = and(io.exc_or_int_valid_r, _T_312) @[dec_tlu_ctl.scala 1719:56] + node _T_314 = not(io.take_nmi) @[dec_tlu_ctl.scala 1719:147] + node mtval_capture_pc_r = and(_T_313, _T_314) @[dec_tlu_ctl.scala 1719:145] + node _T_315 = and(io.inst_acc_r, io.inst_acc_second_r) @[dec_tlu_ctl.scala 1720:79] + node _T_316 = and(io.exc_or_int_valid_r, _T_315) @[dec_tlu_ctl.scala 1720:62] + node _T_317 = not(io.take_nmi) @[dec_tlu_ctl.scala 1720:105] + node mtval_capture_pc_plus2_r = and(_T_316, _T_317) @[dec_tlu_ctl.scala 1720:103] + node _T_318 = and(io.exc_or_int_valid_r, io.illegal_r) @[dec_tlu_ctl.scala 1721:58] + node _T_319 = not(io.take_nmi) @[dec_tlu_ctl.scala 1721:75] + node mtval_capture_inst_r = and(_T_318, _T_319) @[dec_tlu_ctl.scala 1721:73] + node _T_320 = and(io.exc_or_int_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1722:57] + node _T_321 = not(io.take_nmi) @[dec_tlu_ctl.scala 1722:80] + node mtval_capture_lsu_r = and(_T_320, _T_321) @[dec_tlu_ctl.scala 1722:78] + node _T_322 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1723:53] + node _T_323 = and(io.exc_or_int_valid_r, _T_322) @[dec_tlu_ctl.scala 1723:51] + node _T_324 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1723:75] + node _T_325 = and(_T_323, _T_324) @[dec_tlu_ctl.scala 1723:73] + node _T_326 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1723:99] + node _T_327 = and(_T_325, _T_326) @[dec_tlu_ctl.scala 1723:97] + node _T_328 = not(io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1723:122] + node mtval_clear_r = and(_T_327, _T_328) @[dec_tlu_ctl.scala 1723:120] + node _T_329 = bits(mtval_capture_pc_r, 0, 0) @[dec_tlu_ctl.scala 1727:38] + node _T_330 = cat(pc_r, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_331 = bits(mtval_capture_pc_plus2_r, 0, 0) @[dec_tlu_ctl.scala 1728:44] + node _T_332 = add(pc_r, UInt<31>("h01")) @[dec_tlu_ctl.scala 1728:96] + node _T_333 = tail(_T_332, 1) @[dec_tlu_ctl.scala 1728:96] + node _T_334 = cat(_T_333, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_335 = bits(mtval_capture_inst_r, 0, 0) @[dec_tlu_ctl.scala 1729:40] + node _T_336 = bits(mtval_capture_lsu_r, 0, 0) @[dec_tlu_ctl.scala 1730:39] + node _T_337 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1731:31] + node _T_338 = and(wr_mtval_r, _T_337) @[dec_tlu_ctl.scala 1731:29] + node _T_339 = bits(_T_338, 0, 0) @[dec_tlu_ctl.scala 1731:61] + node _T_340 = not(io.take_nmi) @[dec_tlu_ctl.scala 1732:18] + node _T_341 = not(wr_mtval_r) @[dec_tlu_ctl.scala 1732:33] + node _T_342 = and(_T_340, _T_341) @[dec_tlu_ctl.scala 1732:31] + node _T_343 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1732:47] + node _T_344 = and(_T_342, _T_343) @[dec_tlu_ctl.scala 1732:45] + node _T_345 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1732:69] + node _T_346 = and(_T_344, _T_345) @[dec_tlu_ctl.scala 1732:67] + node _T_347 = not(mtval_clear_r) @[dec_tlu_ctl.scala 1732:93] + node _T_348 = and(_T_346, _T_347) @[dec_tlu_ctl.scala 1732:91] + node _T_349 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1732:110] + node _T_350 = and(_T_348, _T_349) @[dec_tlu_ctl.scala 1732:108] + node _T_351 = bits(_T_350, 0, 0) @[dec_tlu_ctl.scala 1732:132] + node _T_352 = mux(_T_329, _T_330, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_353 = mux(_T_331, _T_334, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_354 = mux(_T_335, io.dec_illegal_inst, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_355 = mux(_T_336, io.lsu_error_pkt_addr_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_356 = mux(_T_339, io.dec_csr_wrdata_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_357 = mux(_T_351, mtval, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_358 = or(_T_352, _T_353) @[Mux.scala 27:72] + node _T_359 = or(_T_358, _T_354) @[Mux.scala 27:72] + node _T_360 = or(_T_359, _T_355) @[Mux.scala 27:72] + node _T_361 = or(_T_360, _T_356) @[Mux.scala 27:72] + node _T_362 = or(_T_361, _T_357) @[Mux.scala 27:72] + wire mtval_ns : UInt<32> @[Mux.scala 27:72] + mtval_ns <= _T_362 @[Mux.scala 27:72] + node _T_363 = or(io.tlu_flush_lower_r, wr_mtval_r) @[dec_tlu_ctl.scala 1734:55] + node _T_364 = bits(_T_363, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_10 of rvclkhdr_22 @[lib.scala 404:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_10.io.en <= _T_364 @[lib.scala 407:17] + rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_365 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_364 : @[Reg.scala 28:19] + _T_365 <= mtval_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mtval <= _T_365 @[dec_tlu_ctl.scala 1734:15] + wire mcgc_int : UInt<10> + mcgc_int <= UInt<1>("h00") + node _T_366 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1752:68] + node _T_367 = eq(_T_366, UInt<12>("h07f8")) @[dec_tlu_ctl.scala 1752:75] + node wr_mcgc_r = and(io.dec_csr_wen_r_mod, _T_367) @[dec_tlu_ctl.scala 1752:46] + node _T_368 = bits(wr_mcgc_r, 0, 0) @[lib.scala 8:44] + node _T_369 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1753:62] + node _T_370 = not(_T_369) @[dec_tlu_ctl.scala 1753:42] + node _T_371 = bits(io.dec_csr_wrdata_r, 8, 0) @[dec_tlu_ctl.scala 1753:86] + node _T_372 = cat(_T_370, _T_371) @[Cat.scala 29:58] + node mcgc_ns = mux(_T_368, _T_372, mcgc_int) @[dec_tlu_ctl.scala 1753:26] + node _T_373 = bits(wr_mcgc_r, 0, 0) @[dec_tlu_ctl.scala 1754:46] + inst rvclkhdr_11 of rvclkhdr_23 @[lib.scala 404:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_11.io.en <= _T_373 @[lib.scala 407:17] + rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_374 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_373 : @[Reg.scala 28:19] + _T_374 <= mcgc_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mcgc_int <= _T_374 @[dec_tlu_ctl.scala 1754:18] + node _T_375 = bits(mcgc_int, 9, 9) @[dec_tlu_ctl.scala 1755:33] + node _T_376 = not(_T_375) @[dec_tlu_ctl.scala 1755:24] + node _T_377 = bits(mcgc_int, 8, 0) @[dec_tlu_ctl.scala 1755:46] + node mcgc = cat(_T_376, _T_377) @[Cat.scala 29:58] + node _T_378 = bits(mcgc, 9, 9) @[dec_tlu_ctl.scala 1756:46] + io.dec_tlu_picio_clk_override <= _T_378 @[dec_tlu_ctl.scala 1756:39] + node _T_379 = bits(mcgc, 8, 8) @[dec_tlu_ctl.scala 1757:45] + io.dec_tlu_misc_clk_override <= _T_379 @[dec_tlu_ctl.scala 1757:38] + node _T_380 = bits(mcgc, 7, 7) @[dec_tlu_ctl.scala 1758:45] + io.dec_tlu_dec_clk_override <= _T_380 @[dec_tlu_ctl.scala 1758:38] + node _T_381 = bits(mcgc, 5, 5) @[dec_tlu_ctl.scala 1759:45] + io.dec_tlu_ifu_clk_override <= _T_381 @[dec_tlu_ctl.scala 1759:38] + node _T_382 = bits(mcgc, 4, 4) @[dec_tlu_ctl.scala 1760:45] + io.dec_tlu_lsu_clk_override <= _T_382 @[dec_tlu_ctl.scala 1760:38] + node _T_383 = bits(mcgc, 3, 3) @[dec_tlu_ctl.scala 1761:45] + io.dec_tlu_bus_clk_override <= _T_383 @[dec_tlu_ctl.scala 1761:38] + node _T_384 = bits(mcgc, 2, 2) @[dec_tlu_ctl.scala 1762:45] + io.dec_tlu_pic_clk_override <= _T_384 @[dec_tlu_ctl.scala 1762:38] + node _T_385 = bits(mcgc, 1, 1) @[dec_tlu_ctl.scala 1763:45] + io.dec_tlu_dccm_clk_override <= _T_385 @[dec_tlu_ctl.scala 1763:38] + node _T_386 = bits(mcgc, 0, 0) @[dec_tlu_ctl.scala 1764:45] + io.dec_tlu_icm_clk_override <= _T_386 @[dec_tlu_ctl.scala 1764:38] + node _T_387 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1785:68] + node _T_388 = eq(_T_387, UInt<12>("h07f9")) @[dec_tlu_ctl.scala 1785:75] + node wr_mfdc_r = and(io.dec_csr_wen_r_mod, _T_388) @[dec_tlu_ctl.scala 1785:46] + node _T_389 = bits(wr_mfdc_r, 0, 0) @[dec_tlu_ctl.scala 1789:46] + inst rvclkhdr_12 of rvclkhdr_24 @[lib.scala 404:23] + rvclkhdr_12.clock <= clock + rvclkhdr_12.reset <= reset + rvclkhdr_12.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_12.io.en <= _T_389 @[lib.scala 407:17] + rvclkhdr_12.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_390 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_389 : @[Reg.scala 28:19] + _T_390 <= mfdc_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mfdc_int <= _T_390 @[dec_tlu_ctl.scala 1789:18] + node _T_391 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1795:52] + node _T_392 = not(_T_391) @[dec_tlu_ctl.scala 1795:32] + node _T_393 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1795:79] + node _T_394 = bits(io.dec_csr_wrdata_r, 11, 7) @[dec_tlu_ctl.scala 1795:103] + node _T_395 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1795:131] + node _T_396 = not(_T_395) @[dec_tlu_ctl.scala 1795:111] + node _T_397 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1795:155] + node _T_398 = cat(_T_396, _T_397) @[Cat.scala 29:58] + node _T_399 = cat(_T_392, _T_393) @[Cat.scala 29:58] + node _T_400 = cat(_T_399, _T_394) @[Cat.scala 29:58] + node _T_401 = cat(_T_400, _T_398) @[Cat.scala 29:58] + mfdc_ns <= _T_401 @[dec_tlu_ctl.scala 1795:25] + node _T_402 = bits(mfdc_int, 15, 13) @[dec_tlu_ctl.scala 1796:41] + node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1796:32] + node _T_404 = bits(mfdc_int, 12, 12) @[dec_tlu_ctl.scala 1796:66] + node _T_405 = bits(mfdc_int, 11, 7) @[dec_tlu_ctl.scala 1796:80] + node _T_406 = bits(mfdc_int, 6, 6) @[dec_tlu_ctl.scala 1796:97] + node _T_407 = not(_T_406) @[dec_tlu_ctl.scala 1796:88] + node _T_408 = bits(mfdc_int, 5, 0) @[dec_tlu_ctl.scala 1796:110] + node _T_409 = cat(_T_405, _T_407) @[Cat.scala 29:58] + node _T_410 = cat(_T_409, _T_408) @[Cat.scala 29:58] + node _T_411 = cat(_T_403, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_412 = cat(_T_411, _T_404) @[Cat.scala 29:58] + node _T_413 = cat(_T_412, _T_410) @[Cat.scala 29:58] + mfdc <= _T_413 @[dec_tlu_ctl.scala 1796:25] + node _T_414 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1806:53] + io.dec_tlu_dma_qos_prty <= _T_414 @[dec_tlu_ctl.scala 1806:46] + node _T_415 = bits(mfdc, 12, 12) @[dec_tlu_ctl.scala 1807:53] + io.dec_tlu_trace_disable <= _T_415 @[dec_tlu_ctl.scala 1807:46] + node _T_416 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1808:53] + io.dec_tlu_external_ldfwd_disable <= _T_416 @[dec_tlu_ctl.scala 1808:46] + node _T_417 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1809:53] + io.dec_tlu_core_ecc_disable <= _T_417 @[dec_tlu_ctl.scala 1809:46] + node _T_418 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1810:53] + io.dec_tlu_sideeffect_posted_disable <= _T_418 @[dec_tlu_ctl.scala 1810:46] + node _T_419 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1811:53] + io.dec_tlu_bpred_disable <= _T_419 @[dec_tlu_ctl.scala 1811:46] + node _T_420 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1812:53] + io.dec_tlu_wb_coalescing_disable <= _T_420 @[dec_tlu_ctl.scala 1812:46] + node _T_421 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1813:53] + io.dec_tlu_pipelining_disable <= _T_421 @[dec_tlu_ctl.scala 1813:46] + node _T_422 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1822:77] + node _T_423 = eq(_T_422, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1822:84] + node _T_424 = and(io.dec_csr_wen_r_mod, _T_423) @[dec_tlu_ctl.scala 1822:55] + node _T_425 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1822:96] + node _T_426 = and(_T_424, _T_425) @[dec_tlu_ctl.scala 1822:94] + node _T_427 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1822:120] + node _T_428 = and(_T_426, _T_427) @[dec_tlu_ctl.scala 1822:118] + io.dec_tlu_wr_pause_r <= _T_428 @[dec_tlu_ctl.scala 1822:31] + node _T_429 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1829:68] + node _T_430 = eq(_T_429, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1829:75] + node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_430) @[dec_tlu_ctl.scala 1829:46] + node _T_431 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1832:46] + node _T_432 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1832:71] + node _T_433 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1832:98] + node _T_434 = not(_T_433) @[dec_tlu_ctl.scala 1832:78] + node _T_435 = and(_T_432, _T_434) @[dec_tlu_ctl.scala 1832:76] + node _T_436 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1833:36] + node _T_437 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1833:61] + node _T_438 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1833:88] + node _T_439 = not(_T_438) @[dec_tlu_ctl.scala 1833:68] + node _T_440 = and(_T_437, _T_439) @[dec_tlu_ctl.scala 1833:66] + node _T_441 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1834:36] + node _T_442 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1834:61] + node _T_443 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1834:88] + node _T_444 = not(_T_443) @[dec_tlu_ctl.scala 1834:68] + node _T_445 = and(_T_442, _T_444) @[dec_tlu_ctl.scala 1834:66] + node _T_446 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1835:36] + node _T_447 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1835:61] + node _T_448 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1835:88] + node _T_449 = not(_T_448) @[dec_tlu_ctl.scala 1835:68] + node _T_450 = and(_T_447, _T_449) @[dec_tlu_ctl.scala 1835:66] + node _T_451 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1836:36] + node _T_452 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1836:61] + node _T_453 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1836:88] + node _T_454 = not(_T_453) @[dec_tlu_ctl.scala 1836:68] + node _T_455 = and(_T_452, _T_454) @[dec_tlu_ctl.scala 1836:66] + node _T_456 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1837:36] + node _T_457 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1837:61] + node _T_458 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1837:88] + node _T_459 = not(_T_458) @[dec_tlu_ctl.scala 1837:68] + node _T_460 = and(_T_457, _T_459) @[dec_tlu_ctl.scala 1837:66] + node _T_461 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1838:36] + node _T_462 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1838:61] + node _T_463 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1838:88] + node _T_464 = not(_T_463) @[dec_tlu_ctl.scala 1838:68] + node _T_465 = and(_T_462, _T_464) @[dec_tlu_ctl.scala 1838:66] + node _T_466 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1839:36] + node _T_467 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1839:61] + node _T_468 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1839:88] + node _T_469 = not(_T_468) @[dec_tlu_ctl.scala 1839:68] + node _T_470 = and(_T_467, _T_469) @[dec_tlu_ctl.scala 1839:66] + node _T_471 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1840:36] + node _T_472 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1840:61] + node _T_473 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1840:88] + node _T_474 = not(_T_473) @[dec_tlu_ctl.scala 1840:68] + node _T_475 = and(_T_472, _T_474) @[dec_tlu_ctl.scala 1840:66] + node _T_476 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1841:36] + node _T_477 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1841:61] + node _T_478 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1841:88] + node _T_479 = not(_T_478) @[dec_tlu_ctl.scala 1841:68] + node _T_480 = and(_T_477, _T_479) @[dec_tlu_ctl.scala 1841:66] + node _T_481 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1842:36] + node _T_482 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1842:61] + node _T_483 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1842:88] + node _T_484 = not(_T_483) @[dec_tlu_ctl.scala 1842:68] + node _T_485 = and(_T_482, _T_484) @[dec_tlu_ctl.scala 1842:66] + node _T_486 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1843:36] + node _T_487 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1843:61] + node _T_488 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1843:88] + node _T_489 = not(_T_488) @[dec_tlu_ctl.scala 1843:68] + node _T_490 = and(_T_487, _T_489) @[dec_tlu_ctl.scala 1843:65] + node _T_491 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1844:36] + node _T_492 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1844:61] + node _T_493 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1844:88] + node _T_494 = not(_T_493) @[dec_tlu_ctl.scala 1844:68] + node _T_495 = and(_T_492, _T_494) @[dec_tlu_ctl.scala 1844:65] + node _T_496 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1845:36] + node _T_497 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1845:61] + node _T_498 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1845:88] + node _T_499 = not(_T_498) @[dec_tlu_ctl.scala 1845:68] + node _T_500 = and(_T_497, _T_499) @[dec_tlu_ctl.scala 1845:65] + node _T_501 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1846:36] + node _T_502 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1846:61] + node _T_503 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1846:88] + node _T_504 = not(_T_503) @[dec_tlu_ctl.scala 1846:68] + node _T_505 = and(_T_502, _T_504) @[dec_tlu_ctl.scala 1846:65] + node _T_506 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1847:36] + node _T_507 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1847:61] + node _T_508 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1847:88] + node _T_509 = not(_T_508) @[dec_tlu_ctl.scala 1847:68] + node _T_510 = and(_T_507, _T_509) @[dec_tlu_ctl.scala 1847:65] + node _T_511 = cat(_T_506, _T_510) @[Cat.scala 29:58] + node _T_512 = cat(_T_501, _T_505) @[Cat.scala 29:58] + node _T_513 = cat(_T_512, _T_511) @[Cat.scala 29:58] + node _T_514 = cat(_T_496, _T_500) @[Cat.scala 29:58] + node _T_515 = cat(_T_491, _T_495) @[Cat.scala 29:58] + node _T_516 = cat(_T_515, _T_514) @[Cat.scala 29:58] + node _T_517 = cat(_T_516, _T_513) @[Cat.scala 29:58] + node _T_518 = cat(_T_486, _T_490) @[Cat.scala 29:58] + node _T_519 = cat(_T_481, _T_485) @[Cat.scala 29:58] + node _T_520 = cat(_T_519, _T_518) @[Cat.scala 29:58] + node _T_521 = cat(_T_476, _T_480) @[Cat.scala 29:58] + node _T_522 = cat(_T_471, _T_475) @[Cat.scala 29:58] + node _T_523 = cat(_T_522, _T_521) @[Cat.scala 29:58] + node _T_524 = cat(_T_523, _T_520) @[Cat.scala 29:58] + node _T_525 = cat(_T_524, _T_517) @[Cat.scala 29:58] + node _T_526 = cat(_T_466, _T_470) @[Cat.scala 29:58] + node _T_527 = cat(_T_461, _T_465) @[Cat.scala 29:58] + node _T_528 = cat(_T_527, _T_526) @[Cat.scala 29:58] + node _T_529 = cat(_T_456, _T_460) @[Cat.scala 29:58] + node _T_530 = cat(_T_451, _T_455) @[Cat.scala 29:58] + node _T_531 = cat(_T_530, _T_529) @[Cat.scala 29:58] + node _T_532 = cat(_T_531, _T_528) @[Cat.scala 29:58] + node _T_533 = cat(_T_446, _T_450) @[Cat.scala 29:58] + node _T_534 = cat(_T_441, _T_445) @[Cat.scala 29:58] + node _T_535 = cat(_T_534, _T_533) @[Cat.scala 29:58] + node _T_536 = cat(_T_436, _T_440) @[Cat.scala 29:58] + node _T_537 = cat(_T_431, _T_435) @[Cat.scala 29:58] + node _T_538 = cat(_T_537, _T_536) @[Cat.scala 29:58] + node _T_539 = cat(_T_538, _T_535) @[Cat.scala 29:58] + node _T_540 = cat(_T_539, _T_532) @[Cat.scala 29:58] + node mrac_in = cat(_T_540, _T_525) @[Cat.scala 29:58] + node _T_541 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1850:45] + inst rvclkhdr_13 of rvclkhdr_25 @[lib.scala 404:23] + rvclkhdr_13.clock <= clock + rvclkhdr_13.reset <= reset + rvclkhdr_13.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_13.io.en <= _T_541 @[lib.scala 407:17] + rvclkhdr_13.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg mrac : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_541 : @[Reg.scala 28:19] + mrac <= mrac_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.dec_tlu_mrac_ff <= mrac @[dec_tlu_ctl.scala 1852:28] + node _T_542 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1860:69] + node _T_543 = eq(_T_542, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1860:76] + node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_543) @[dec_tlu_ctl.scala 1860:47] + node _T_544 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1870:66] + node _T_545 = and(io.mdseac_locked_f, _T_544) @[dec_tlu_ctl.scala 1870:64] + node _T_546 = or(mdseac_en, _T_545) @[dec_tlu_ctl.scala 1870:42] + io.mdseac_locked_ns <= _T_546 @[dec_tlu_ctl.scala 1870:29] + node _T_547 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1872:56] + node _T_548 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1872:93] + node _T_549 = and(_T_547, _T_548) @[dec_tlu_ctl.scala 1872:91] + node _T_550 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1872:118] + node _T_551 = and(_T_549, _T_550) @[dec_tlu_ctl.scala 1872:116] + mdseac_en <= _T_551 @[dec_tlu_ctl.scala 1872:19] + node _T_552 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1874:71] + inst rvclkhdr_14 of rvclkhdr_26 @[lib.scala 404:23] + rvclkhdr_14.clock <= clock + rvclkhdr_14.reset <= reset + rvclkhdr_14.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_14.io.en <= _T_552 @[lib.scala 407:17] + rvclkhdr_14.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg mdseac : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_552 : @[Reg.scala 28:19] + mdseac <= io.lsu_imprecise_error_addr_any @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_553 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1883:69] + node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_553) @[dec_tlu_ctl.scala 1883:46] + node _T_554 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1887:58] + node _T_555 = and(wr_mpmc_r, _T_554) @[dec_tlu_ctl.scala 1887:37] + node _T_556 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1887:64] + node _T_557 = and(_T_555, _T_556) @[dec_tlu_ctl.scala 1887:62] + node _T_558 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1887:96] + node _T_559 = and(_T_557, _T_558) @[dec_tlu_ctl.scala 1887:94] + io.fw_halt_req <= _T_559 @[dec_tlu_ctl.scala 1887:24] + wire fw_halted_ns : UInt<1> + fw_halted_ns <= UInt<1>("h00") + node _T_560 = or(io.fw_halt_req, perfmux_flop.io.fw_halted) @[dec_tlu_ctl.scala 1890:41] + node _T_561 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1890:72] + node _T_562 = and(_T_560, _T_561) @[dec_tlu_ctl.scala 1890:70] + fw_halted_ns <= _T_562 @[dec_tlu_ctl.scala 1890:22] + node _T_563 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1891:36] + node _T_564 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1891:64] + node _T_565 = not(_T_564) @[dec_tlu_ctl.scala 1891:44] + node _T_566 = not(mpmc) @[dec_tlu_ctl.scala 1891:69] + node _T_567 = mux(_T_563, _T_565, _T_566) @[dec_tlu_ctl.scala 1891:25] + mpmc_b_ns <= _T_567 @[dec_tlu_ctl.scala 1891:19] + reg _T_568 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1893:51] + _T_568 <= mpmc_b_ns @[dec_tlu_ctl.scala 1893:51] + mpmc_b <= _T_568 @[dec_tlu_ctl.scala 1893:16] + node _T_569 = not(mpmc_b) @[dec_tlu_ctl.scala 1896:17] + mpmc <= _T_569 @[dec_tlu_ctl.scala 1896:14] + node _T_570 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1905:47] + node _T_571 = gt(_T_570, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1905:55] + node _T_572 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1905:99] + node csr_sat = mux(_T_571, UInt<5>("h01a"), _T_572) @[dec_tlu_ctl.scala 1905:26] + node _T_573 = eq(io.dec_csr_wraddr_r, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1907:71] + node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_573) @[dec_tlu_ctl.scala 1907:48] + node _T_574 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1908:29] + node _T_575 = cat(UInt<26>("h00"), io.ic_perr_r) @[Cat.scala 29:58] + node _T_576 = add(_T_574, _T_575) @[dec_tlu_ctl.scala 1908:36] + node _T_577 = tail(_T_576, 1) @[dec_tlu_ctl.scala 1908:36] + micect_inc <= _T_577 @[dec_tlu_ctl.scala 1908:20] + node _T_578 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1909:42] + node _T_579 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1909:82] + node _T_580 = cat(csr_sat, _T_579) @[Cat.scala 29:58] + node _T_581 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1909:102] + node _T_582 = cat(_T_581, micect_inc) @[Cat.scala 29:58] + node micect_ns = mux(_T_578, _T_580, _T_582) @[dec_tlu_ctl.scala 1909:29] + node _T_583 = or(wr_micect_r, io.ic_perr_r) @[dec_tlu_ctl.scala 1911:49] + node _T_584 = bits(_T_583, 0, 0) @[dec_tlu_ctl.scala 1911:65] + inst rvclkhdr_15 of rvclkhdr_27 @[lib.scala 404:23] + rvclkhdr_15.clock <= clock + rvclkhdr_15.reset <= reset + rvclkhdr_15.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_15.io.en <= _T_584 @[lib.scala 407:17] + rvclkhdr_15.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_585 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_584 : @[Reg.scala 28:19] + _T_585 <= micect_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + micect <= _T_585 @[dec_tlu_ctl.scala 1911:16] + node _T_586 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1913:55] + node _T_587 = dshl(UInt<32>("h0ffffffff"), _T_586) @[dec_tlu_ctl.scala 1913:46] + node _T_588 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1913:86] + node _T_589 = cat(UInt<5>("h00"), _T_588) @[Cat.scala 29:58] + node _T_590 = and(_T_587, _T_589) @[dec_tlu_ctl.scala 1913:64] + node _T_591 = orr(_T_590) @[dec_tlu_ctl.scala 1913:95] + mice_ce_req <= _T_591 @[dec_tlu_ctl.scala 1913:21] + node _T_592 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1922:76] + node _T_593 = eq(_T_592, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1922:83] + node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_593) @[dec_tlu_ctl.scala 1922:54] + node _T_594 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1923:33] + node _T_595 = or(io.iccm_sbecc_r, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1923:74] + node _T_596 = cat(UInt<26>("h00"), _T_595) @[Cat.scala 29:58] + node _T_597 = add(_T_594, _T_596) @[dec_tlu_ctl.scala 1923:40] + node _T_598 = tail(_T_597, 1) @[dec_tlu_ctl.scala 1923:40] + miccmect_inc <= _T_598 @[dec_tlu_ctl.scala 1923:22] + node _T_599 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1924:52] + node _T_600 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1924:92] + node _T_601 = cat(csr_sat, _T_600) @[Cat.scala 29:58] + node _T_602 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1924:114] + node _T_603 = cat(_T_602, miccmect_inc) @[Cat.scala 29:58] + node miccmect_ns = mux(_T_599, _T_601, _T_603) @[dec_tlu_ctl.scala 1924:37] + node _T_604 = or(wr_miccmect_r, io.iccm_sbecc_r) @[dec_tlu_ctl.scala 1926:55] + node _T_605 = or(_T_604, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1926:73] + node _T_606 = bits(_T_605, 0, 0) @[dec_tlu_ctl.scala 1926:97] + inst rvclkhdr_16 of rvclkhdr_28 @[lib.scala 404:23] + rvclkhdr_16.clock <= clock + rvclkhdr_16.reset <= reset + rvclkhdr_16.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_16.io.en <= _T_606 @[lib.scala 407:17] + rvclkhdr_16.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_607 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_606 : @[Reg.scala 28:19] + _T_607 <= miccmect_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + miccmect <= _T_607 @[dec_tlu_ctl.scala 1926:18] + node _T_608 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1928:59] + node _T_609 = dshl(UInt<32>("h0ffffffff"), _T_608) @[dec_tlu_ctl.scala 1928:48] + node _T_610 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1928:92] + node _T_611 = cat(UInt<5>("h00"), _T_610) @[Cat.scala 29:58] + node _T_612 = and(_T_609, _T_611) @[dec_tlu_ctl.scala 1928:68] + node _T_613 = orr(_T_612) @[dec_tlu_ctl.scala 1928:101] + miccme_ce_req <= _T_613 @[dec_tlu_ctl.scala 1928:23] + node _T_614 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1937:76] + node _T_615 = eq(_T_614, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1937:83] + node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_615) @[dec_tlu_ctl.scala 1937:54] + node _T_616 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1938:33] + node _T_617 = cat(UInt<26>("h00"), perfmux_flop.io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] + node _T_618 = add(_T_616, _T_617) @[dec_tlu_ctl.scala 1938:40] + node _T_619 = tail(_T_618, 1) @[dec_tlu_ctl.scala 1938:40] + mdccmect_inc <= _T_619 @[dec_tlu_ctl.scala 1938:22] + node _T_620 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1939:52] + node _T_621 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1939:92] + node _T_622 = cat(csr_sat, _T_621) @[Cat.scala 29:58] + node _T_623 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1939:114] + node _T_624 = cat(_T_623, mdccmect_inc) @[Cat.scala 29:58] + node mdccmect_ns = mux(_T_620, _T_622, _T_624) @[dec_tlu_ctl.scala 1939:37] + node _T_625 = or(wr_mdccmect_r, perfmux_flop.io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1941:56] + node _T_626 = bits(_T_625, 0, 0) @[dec_tlu_ctl.scala 1941:103] + inst rvclkhdr_17 of rvclkhdr_29 @[lib.scala 404:23] + rvclkhdr_17.clock <= clock + rvclkhdr_17.reset <= reset + rvclkhdr_17.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_17.io.en <= _T_626 @[lib.scala 407:17] + rvclkhdr_17.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_627 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_626 : @[Reg.scala 28:19] + _T_627 <= mdccmect_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mdccmect <= _T_627 @[dec_tlu_ctl.scala 1941:18] + node _T_628 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1942:59] + node _T_629 = dshl(UInt<32>("h0ffffffff"), _T_628) @[dec_tlu_ctl.scala 1942:48] + node _T_630 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1942:92] + node _T_631 = cat(UInt<5>("h00"), _T_630) @[Cat.scala 29:58] + node _T_632 = and(_T_629, _T_631) @[dec_tlu_ctl.scala 1942:68] + node _T_633 = orr(_T_632) @[dec_tlu_ctl.scala 1942:101] + mdccme_ce_req <= _T_633 @[dec_tlu_ctl.scala 1942:23] + node _T_634 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1952:69] + node _T_635 = eq(_T_634, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1952:76] + node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_635) @[dec_tlu_ctl.scala 1952:47] + node _T_636 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1954:39] + node _T_637 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1954:66] + node mfdht_ns = mux(_T_636, _T_637, mfdht) @[dec_tlu_ctl.scala 1954:27] + node _T_638 = bits(wr_mfdht_r, 0, 0) @[lib.scala 8:44] + reg _T_639 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_638 : @[Reg.scala 28:19] + _T_639 <= mfdht_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mfdht <= _T_639 @[dec_tlu_ctl.scala 1956:15] + node _T_640 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1965:69] + node _T_641 = eq(_T_640, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1965:76] + node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_641) @[dec_tlu_ctl.scala 1965:47] + node _T_642 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1967:39] + node _T_643 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1967:67] + node _T_644 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1968:42] + node _T_645 = and(io.dbg_tlu_halted, _T_644) @[dec_tlu_ctl.scala 1968:40] + node _T_646 = bits(_T_645, 0, 0) @[dec_tlu_ctl.scala 1968:64] + node _T_647 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1968:77] + node _T_648 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1968:97] + node _T_649 = cat(_T_647, _T_648) @[Cat.scala 29:58] + node _T_650 = mux(_T_646, _T_649, mfdhs) @[dec_tlu_ctl.scala 1968:20] + node mfdhs_ns = mux(_T_642, _T_643, _T_650) @[dec_tlu_ctl.scala 1967:27] + node _T_651 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1970:76] + node _T_652 = bits(_T_651, 0, 0) @[dec_tlu_ctl.scala 1970:97] + reg _T_653 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_652 : @[Reg.scala 28:19] + _T_653 <= mfdhs_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mfdhs <= _T_653 @[dec_tlu_ctl.scala 1970:15] + node _T_654 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1972:54] + node _T_655 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1972:81] + node _T_656 = tail(_T_655, 1) @[dec_tlu_ctl.scala 1972:81] + node _T_657 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1973:41] + node _T_658 = mux(_T_657, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1973:20] + node force_halt_ctr = mux(_T_654, _T_656, _T_658) @[dec_tlu_ctl.scala 1972:33] + node _T_659 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1975:56] + inst rvclkhdr_18 of rvclkhdr_30 @[lib.scala 404:23] + rvclkhdr_18.clock <= clock + rvclkhdr_18.reset <= reset + rvclkhdr_18.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_18.io.en <= _T_659 @[lib.scala 407:17] + rvclkhdr_18.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_660 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_659 : @[Reg.scala 28:19] + _T_660 <= force_halt_ctr @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + force_halt_ctr_f <= _T_660 @[dec_tlu_ctl.scala 1975:26] + node _T_661 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1977:31] + node _T_662 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1977:86] + node _T_663 = dshl(UInt<32>("h0ffffffff"), _T_662) @[dec_tlu_ctl.scala 1977:78] + node _T_664 = and(force_halt_ctr_f, _T_663) @[dec_tlu_ctl.scala 1977:55] + node _T_665 = orr(_T_664) @[dec_tlu_ctl.scala 1977:94] + node _T_666 = and(_T_661, _T_665) @[dec_tlu_ctl.scala 1977:35] + io.force_halt <= _T_666 @[dec_tlu_ctl.scala 1977:23] + node _T_667 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1985:69] + node _T_668 = eq(_T_667, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1985:76] + node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_668) @[dec_tlu_ctl.scala 1985:47] + node _T_669 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1987:47] + node _T_670 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1987:66] + inst rvclkhdr_19 of rvclkhdr_31 @[lib.scala 404:23] + rvclkhdr_19.clock <= clock + rvclkhdr_19.reset <= reset + rvclkhdr_19.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_19.io.en <= _T_670 @[lib.scala 407:17] + rvclkhdr_19.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg meivt : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_670 : @[Reg.scala 28:19] + meivt <= _T_669 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_671 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1999:56] + inst rvclkhdr_20 of rvclkhdr_32 @[lib.scala 404:23] + rvclkhdr_20.clock <= clock + rvclkhdr_20.reset <= reset + rvclkhdr_20.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_20.io.en <= _T_671 @[lib.scala 407:17] + rvclkhdr_20.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg meihap : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_671 : @[Reg.scala 28:19] + meihap <= io.pic_claimid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_672 = cat(meivt, meihap) @[Cat.scala 29:58] + io.dec_tlu_meihap <= _T_672 @[dec_tlu_ctl.scala 2000:27] + node _T_673 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2009:72] + node _T_674 = eq(_T_673, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 2009:79] + node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_674) @[dec_tlu_ctl.scala 2009:50] + node _T_675 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 2010:45] + node _T_676 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2010:72] + node meicurpl_ns = mux(_T_675, _T_676, meicurpl) @[dec_tlu_ctl.scala 2010:30] + reg _T_677 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2012:53] + _T_677 <= meicurpl_ns @[dec_tlu_ctl.scala 2012:53] + meicurpl <= _T_677 @[dec_tlu_ctl.scala 2012:18] + io.dec_tlu_meicurpl <= meicurpl @[dec_tlu_ctl.scala 2014:29] + node _T_678 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2024:73] + node _T_679 = eq(_T_678, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 2024:80] + node _T_680 = and(io.dec_csr_wen_r_mod, _T_679) @[dec_tlu_ctl.scala 2024:51] + node wr_meicidpl_r = or(_T_680, io.take_ext_int_start) @[dec_tlu_ctl.scala 2024:95] + node _T_681 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 2026:44] + node _T_682 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 2027:35] + node _T_683 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2027:62] + node _T_684 = mux(_T_682, _T_683, perfmux_flop.io.meicidpl) @[dec_tlu_ctl.scala 2027:20] + node meicidpl_ns = mux(_T_681, io.pic_pl, _T_684) @[dec_tlu_ctl.scala 2026:30] + node _T_685 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2036:69] + node _T_686 = eq(_T_685, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 2036:76] + node _T_687 = and(io.dec_csr_wen_r_mod, _T_686) @[dec_tlu_ctl.scala 2036:47] + node _T_688 = or(_T_687, io.take_ext_int_start) @[dec_tlu_ctl.scala 2036:90] + wr_meicpct_r <= _T_688 @[dec_tlu_ctl.scala 2036:22] + node _T_689 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2045:69] + node _T_690 = eq(_T_689, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 2045:76] + node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_690) @[dec_tlu_ctl.scala 2045:47] + node _T_691 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 2046:39] + node _T_692 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2046:66] + node meipt_ns = mux(_T_691, _T_692, meipt) @[dec_tlu_ctl.scala 2046:27] + reg _T_693 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2048:50] + _T_693 <= meipt_ns @[dec_tlu_ctl.scala 2048:50] + meipt <= _T_693 @[dec_tlu_ctl.scala 2048:15] + io.dec_tlu_meipt <= meipt @[dec_tlu_ctl.scala 2050:26] + node _T_694 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2076:96] + node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_694) @[dec_tlu_ctl.scala 2076:73] + node _T_695 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2079:47] + node _T_696 = and(io.dcsr_single_step_done_f, _T_695) @[dec_tlu_ctl.scala 2079:45] + node _T_697 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2079:79] + node _T_698 = and(_T_696, _T_697) @[dec_tlu_ctl.scala 2079:77] + node _T_699 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2079:114] + node _T_700 = and(_T_698, _T_699) @[dec_tlu_ctl.scala 2079:112] + node _T_701 = bits(_T_700, 0, 0) @[dec_tlu_ctl.scala 2079:134] + node _T_702 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2080:38] + node _T_703 = and(io.debug_halt_req, _T_702) @[dec_tlu_ctl.scala 2080:36] + node _T_704 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2080:70] + node _T_705 = and(_T_703, _T_704) @[dec_tlu_ctl.scala 2080:68] + node _T_706 = bits(_T_705, 0, 0) @[dec_tlu_ctl.scala 2080:104] + node _T_707 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2081:49] + node _T_708 = and(io.ebreak_to_debug_mode_r_d1, _T_707) @[dec_tlu_ctl.scala 2081:47] + node _T_709 = bits(_T_708, 0, 0) @[dec_tlu_ctl.scala 2081:83] + node _T_710 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2082:51] + node _T_711 = mux(_T_701, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_712 = mux(_T_706, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_713 = mux(_T_709, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_714 = mux(_T_710, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_715 = or(_T_711, _T_712) @[Mux.scala 27:72] + node _T_716 = or(_T_715, _T_713) @[Mux.scala 27:72] + node _T_717 = or(_T_716, _T_714) @[Mux.scala 27:72] + wire dcsr_cause : UInt<3> @[Mux.scala 27:72] + dcsr_cause <= _T_717 @[Mux.scala 27:72] + node _T_718 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2084:53] + node _T_719 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2084:98] + node _T_720 = eq(_T_719, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2084:105] + node wr_dcsr_r = and(_T_718, _T_720) @[dec_tlu_ctl.scala 2084:76] + node _T_721 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2090:76] + node _T_722 = eq(_T_721, UInt<3>("h03")) @[dec_tlu_ctl.scala 2090:82] + node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_722) @[dec_tlu_ctl.scala 2090:66] + node _T_723 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2091:66] + node _T_724 = or(_T_723, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2091:85] + node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_724) @[dec_tlu_ctl.scala 2091:63] + node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 2093:55] + node _T_725 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2094:51] + node _T_726 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2094:71] + node _T_727 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2094:98] + node _T_728 = cat(_T_727, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_729 = cat(_T_726, dcsr_cause) @[Cat.scala 29:58] + node _T_730 = cat(_T_729, _T_728) @[Cat.scala 29:58] + node _T_731 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2095:31] + node _T_732 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2095:62] + node _T_733 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2095:97] + node _T_734 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2095:123] + node _T_735 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2095:167] + node _T_736 = or(nmi_in_debug_mode, _T_735) @[dec_tlu_ctl.scala 2095:158] + node _T_737 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2095:191] + node _T_738 = cat(_T_737, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_739 = cat(UInt<2>("h00"), _T_736) @[Cat.scala 29:58] + node _T_740 = cat(_T_739, _T_738) @[Cat.scala 29:58] + node _T_741 = cat(UInt<1>("h00"), _T_734) @[Cat.scala 29:58] + node _T_742 = cat(_T_732, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_743 = cat(_T_742, _T_733) @[Cat.scala 29:58] + node _T_744 = cat(_T_743, _T_741) @[Cat.scala 29:58] + node _T_745 = cat(_T_744, _T_740) @[Cat.scala 29:58] + node _T_746 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2095:224] + node _T_747 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2095:258] + node _T_748 = cat(_T_747, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_749 = cat(_T_746, nmi_in_debug_mode) @[Cat.scala 29:58] + node _T_750 = cat(_T_749, _T_748) @[Cat.scala 29:58] + node _T_751 = mux(_T_731, _T_745, _T_750) @[dec_tlu_ctl.scala 2095:20] + node dcsr_ns = mux(_T_725, _T_730, _T_751) @[dec_tlu_ctl.scala 2094:26] + node _T_752 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2098:61] + node _T_753 = or(_T_752, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2098:73] + node _T_754 = or(_T_753, io.take_nmi) @[dec_tlu_ctl.scala 2098:101] + node _T_755 = bits(_T_754, 0, 0) @[dec_tlu_ctl.scala 2098:116] + inst rvclkhdr_21 of rvclkhdr_33 @[lib.scala 404:23] + rvclkhdr_21.clock <= clock + rvclkhdr_21.reset <= reset + rvclkhdr_21.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_21.io.en <= _T_755 @[lib.scala 407:17] + rvclkhdr_21.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_756 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_755 : @[Reg.scala 28:19] + _T_756 <= dcsr_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.dcsr <= _T_756 @[dec_tlu_ctl.scala 2098:17] + node _T_757 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2106:52] + node _T_758 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2106:97] + node _T_759 = eq(_T_758, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2106:104] + node wr_dpc_r = and(_T_757, _T_759) @[dec_tlu_ctl.scala 2106:75] + node _T_760 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2107:51] + node _T_761 = and(io.dbg_tlu_halted, _T_760) @[dec_tlu_ctl.scala 2107:49] + node _T_762 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2107:74] + node dpc_capture_npc = and(_T_761, _T_762) @[dec_tlu_ctl.scala 2107:72] + node _T_763 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2111:18] + node _T_764 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2111:36] + node _T_765 = and(_T_763, _T_764) @[dec_tlu_ctl.scala 2111:34] + node _T_766 = and(_T_765, wr_dpc_r) @[dec_tlu_ctl.scala 2111:53] + node _T_767 = bits(_T_766, 0, 0) @[dec_tlu_ctl.scala 2111:65] + node _T_768 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2111:94] + node _T_769 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2112:34] + node _T_770 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2113:18] + node _T_771 = and(_T_770, dpc_capture_npc) @[dec_tlu_ctl.scala 2113:34] + node _T_772 = bits(_T_771, 0, 0) @[dec_tlu_ctl.scala 2113:53] + node _T_773 = mux(_T_767, _T_768, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_774 = mux(_T_769, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_775 = mux(_T_772, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_776 = or(_T_773, _T_774) @[Mux.scala 27:72] + node _T_777 = or(_T_776, _T_775) @[Mux.scala 27:72] + wire dpc_ns : UInt<31> @[Mux.scala 27:72] + dpc_ns <= _T_777 @[Mux.scala 27:72] + node _T_778 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2115:43] + node _T_779 = or(_T_778, dpc_capture_npc) @[dec_tlu_ctl.scala 2115:60] + node _T_780 = bits(_T_779, 0, 0) @[dec_tlu_ctl.scala 2115:79] + inst rvclkhdr_22 of rvclkhdr_34 @[lib.scala 404:23] + rvclkhdr_22.clock <= clock + rvclkhdr_22.reset <= reset + rvclkhdr_22.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_22.io.en <= _T_780 @[lib.scala 407:17] + rvclkhdr_22.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_781 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_780 : @[Reg.scala 28:19] + _T_781 <= dpc_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.dpc <= _T_781 @[dec_tlu_ctl.scala 2115:16] + node _T_782 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2129:50] + node _T_783 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2129:75] + node _T_784 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2129:103] + node _T_785 = cat(_T_782, _T_783) @[Cat.scala 29:58] + node dicawics_ns = cat(_T_785, _T_784) @[Cat.scala 29:58] + node _T_786 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2130:57] + node _T_787 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2130:102] + node _T_788 = eq(_T_787, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2130:109] + node wr_dicawics_r = and(_T_786, _T_788) @[dec_tlu_ctl.scala 2130:80] + node _T_789 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2132:57] + inst rvclkhdr_23 of rvclkhdr_35 @[lib.scala 404:23] + rvclkhdr_23.clock <= clock + rvclkhdr_23.reset <= reset + rvclkhdr_23.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_23.io.en <= _T_789 @[lib.scala 407:17] + rvclkhdr_23.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg dicawics : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_789 : @[Reg.scala 28:19] + dicawics <= dicawics_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_790 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2148:55] + node _T_791 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2148:100] + node _T_792 = eq(_T_791, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2148:107] + node wr_dicad0_r = and(_T_790, _T_792) @[dec_tlu_ctl.scala 2148:78] + node _T_793 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2149:41] + node _T_794 = bits(io.ifu_ic_debug_rd_data, 31, 0) @[dec_tlu_ctl.scala 2149:93] + node dicad0_ns = mux(_T_793, io.dec_csr_wrdata_r, _T_794) @[dec_tlu_ctl.scala 2149:28] + node _T_795 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2151:53] + node _T_796 = bits(_T_795, 0, 0) @[dec_tlu_ctl.scala 2151:86] + inst rvclkhdr_24 of rvclkhdr_36 @[lib.scala 404:23] + rvclkhdr_24.clock <= clock + rvclkhdr_24.reset <= reset + rvclkhdr_24.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_24.io.en <= _T_796 @[lib.scala 407:17] + rvclkhdr_24.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg dicad0 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_796 : @[Reg.scala 28:19] + dicad0 <= dicad0_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_797 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2161:56] + node _T_798 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2161:101] + node _T_799 = eq(_T_798, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2161:108] + node wr_dicad0h_r = and(_T_797, _T_799) @[dec_tlu_ctl.scala 2161:79] + node _T_800 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2163:43] + node _T_801 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2163:95] + node dicad0h_ns = mux(_T_800, io.dec_csr_wrdata_r, _T_801) @[dec_tlu_ctl.scala 2163:29] + node _T_802 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2165:55] + node _T_803 = bits(_T_802, 0, 0) @[dec_tlu_ctl.scala 2165:88] + inst rvclkhdr_25 of rvclkhdr_37 @[lib.scala 404:23] + rvclkhdr_25.clock <= clock + rvclkhdr_25.reset <= reset + rvclkhdr_25.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_25.io.en <= _T_803 @[lib.scala 407:17] + rvclkhdr_25.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg dicad0h : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_803 : @[Reg.scala 28:19] + dicad0h <= dicad0h_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wire _T_804 : UInt<7> + _T_804 <= UInt<1>("h00") + node _T_805 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2173:63] + node _T_806 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2173:108] + node _T_807 = eq(_T_806, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2173:115] + node _T_808 = and(_T_805, _T_807) @[dec_tlu_ctl.scala 2173:86] + node _T_809 = bits(_T_808, 0, 0) @[dec_tlu_ctl.scala 2175:49] + node _T_810 = bits(io.dec_csr_wrdata_r, 6, 0) @[dec_tlu_ctl.scala 2175:76] + node _T_811 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2175:106] + node _T_812 = mux(_T_809, _T_810, _T_811) @[dec_tlu_ctl.scala 2175:36] + node _T_813 = or(_T_808, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2177:61] + node _T_814 = bits(_T_813, 0, 0) @[dec_tlu_ctl.scala 2177:94] + inst rvclkhdr_26 of rvclkhdr_38 @[lib.scala 404:23] + rvclkhdr_26.clock <= clock + rvclkhdr_26.reset <= reset + rvclkhdr_26.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_26.io.en <= _T_814 @[lib.scala 407:17] + rvclkhdr_26.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_815 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_814 : @[Reg.scala 28:19] + _T_815 <= _T_812 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_804 <= _T_815 @[dec_tlu_ctl.scala 2177:28] + node _T_816 = cat(UInt<25>("h00"), _T_804) @[Cat.scala 29:58] + dicad1 <= _T_816 @[dec_tlu_ctl.scala 2178:24] + node _T_817 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2200:76] + node _T_818 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2200:90] + node _T_819 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2200:104] + node _T_820 = cat(_T_817, _T_818) @[Cat.scala 29:58] + node _T_821 = cat(_T_820, _T_819) @[Cat.scala 29:58] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_821 @[dec_tlu_ctl.scala 2200:63] + io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2203:48] + node _T_822 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2205:59] + node _T_823 = and(_T_822, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2205:82] + node _T_824 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2205:105] + node _T_825 = and(_T_823, _T_824) @[dec_tlu_ctl.scala 2205:103] + node _T_826 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2205:149] + node _T_827 = eq(_T_826, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2205:156] + node icache_rd_valid = and(_T_825, _T_827) @[dec_tlu_ctl.scala 2205:127] + node _T_828 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2206:59] + node _T_829 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2206:104] + node _T_830 = eq(_T_829, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2206:111] + node icache_wr_valid = and(_T_828, _T_830) @[dec_tlu_ctl.scala 2206:82] + io.dec_tlu_ic_diag_pkt.icache_rd_valid <= perfmux_flop.io.icache_rd_valid_f @[dec_tlu_ctl.scala 2211:48] + io.dec_tlu_ic_diag_pkt.icache_wr_valid <= perfmux_flop.io.icache_wr_valid_f @[dec_tlu_ctl.scala 2212:48] + node _T_831 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2220:69] + node _T_832 = eq(_T_831, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2220:76] + node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_832) @[dec_tlu_ctl.scala 2220:47] + node _T_833 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2221:39] + node _T_834 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2221:66] + node mtsel_ns = mux(_T_833, _T_834, mtsel) @[dec_tlu_ctl.scala 2221:27] + reg _T_835 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2223:50] + _T_835 <= mtsel_ns @[dec_tlu_ctl.scala 2223:50] + mtsel <= _T_835 @[dec_tlu_ctl.scala 2223:15] + node _T_836 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2258:45] + node _T_837 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2258:71] + node _T_838 = not(_T_837) @[dec_tlu_ctl.scala 2258:51] + node tdata_load = and(_T_836, _T_838) @[dec_tlu_ctl.scala 2258:49] + node _T_839 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2260:47] + node _T_840 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2260:73] + node _T_841 = not(_T_840) @[dec_tlu_ctl.scala 2260:53] + node tdata_opcode = and(_T_839, _T_841) @[dec_tlu_ctl.scala 2260:51] + node _T_842 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2262:48] + node _T_843 = and(_T_842, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2262:53] + node _T_844 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2262:97] + node tdata_action = and(_T_843, _T_844) @[dec_tlu_ctl.scala 2262:76] + node _T_845 = bits(mtsel, 0, 0) @[dec_tlu_ctl.scala 2265:36] + node _T_846 = bits(mtsel, 1, 1) @[dec_tlu_ctl.scala 2266:26] + node _T_847 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2266:51] + node _T_848 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2266:75] + node _T_849 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2266:113] + node _T_850 = not(_T_849) @[dec_tlu_ctl.scala 2266:93] + node _T_851 = and(_T_848, _T_850) @[dec_tlu_ctl.scala 2266:91] + node _T_852 = not(_T_851) @[dec_tlu_ctl.scala 2266:58] + node _T_853 = and(_T_847, _T_852) @[dec_tlu_ctl.scala 2266:56] + node _T_854 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2267:44] + node _T_855 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2267:68] + node _T_856 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2267:106] + node _T_857 = not(_T_856) @[dec_tlu_ctl.scala 2267:86] + node _T_858 = and(_T_855, _T_857) @[dec_tlu_ctl.scala 2267:84] + node _T_859 = not(_T_858) @[dec_tlu_ctl.scala 2267:51] + node _T_860 = and(_T_854, _T_859) @[dec_tlu_ctl.scala 2267:49] + node _T_861 = mux(_T_846, _T_853, _T_860) @[dec_tlu_ctl.scala 2266:20] + node tdata_chain = mux(_T_845, UInt<1>("h00"), _T_861) @[dec_tlu_ctl.scala 2265:30] + node _T_862 = bits(mtsel, 1, 1) @[dec_tlu_ctl.scala 2270:41] + node _T_863 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2270:65] + node _T_864 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2270:89] + node _T_865 = not(_T_864) @[dec_tlu_ctl.scala 2270:73] + node _T_866 = bits(io.mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 2270:122] + node _T_867 = and(_T_865, _T_866) @[dec_tlu_ctl.scala 2270:105] + node _T_868 = and(_T_863, _T_867) @[dec_tlu_ctl.scala 2270:70] + node _T_869 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2271:36] + node _T_870 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2271:60] + node _T_871 = not(_T_870) @[dec_tlu_ctl.scala 2271:44] + node _T_872 = bits(io.mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 2271:93] + node _T_873 = and(_T_871, _T_872) @[dec_tlu_ctl.scala 2271:76] + node _T_874 = and(_T_869, _T_873) @[dec_tlu_ctl.scala 2271:41] + node tdata_kill_write = mux(_T_862, _T_868, _T_874) @[dec_tlu_ctl.scala 2270:35] + node _T_875 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2273:54] + node _T_876 = and(_T_875, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2273:59] + node _T_877 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2273:101] + node _T_878 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2273:157] + node _T_879 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2273:197] + node _T_880 = cat(_T_879, tdata_load) @[Cat.scala 29:58] + node _T_881 = cat(_T_878, tdata_opcode) @[Cat.scala 29:58] + node _T_882 = cat(_T_881, _T_880) @[Cat.scala 29:58] + node _T_883 = cat(tdata_action, tdata_chain) @[Cat.scala 29:58] + node _T_884 = cat(_T_876, _T_877) @[Cat.scala 29:58] + node _T_885 = cat(_T_884, _T_883) @[Cat.scala 29:58] + node tdata_wrdata_r = cat(_T_885, _T_882) @[Cat.scala 29:58] + node _T_886 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2276:120] + node _T_887 = eq(_T_886, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2276:127] + node _T_888 = and(io.dec_csr_wen_r_mod, _T_887) @[dec_tlu_ctl.scala 2276:98] + node _T_889 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2276:149] + node _T_890 = and(_T_888, _T_889) @[dec_tlu_ctl.scala 2276:140] + node _T_891 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2276:182] + node _T_892 = eq(_T_891, UInt<1>("h00")) @[dec_tlu_ctl.scala 2276:166] + node _T_893 = or(_T_892, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2276:198] + node _T_894 = and(_T_890, _T_893) @[dec_tlu_ctl.scala 2276:163] + node _T_895 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2276:269] + node _T_896 = eq(_T_895, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2276:276] + node _T_897 = and(io.dec_csr_wen_r_mod, _T_896) @[dec_tlu_ctl.scala 2276:247] + node _T_898 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2276:298] + node _T_899 = and(_T_897, _T_898) @[dec_tlu_ctl.scala 2276:289] + node _T_900 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2276:331] + node _T_901 = eq(_T_900, UInt<1>("h00")) @[dec_tlu_ctl.scala 2276:315] + node _T_902 = or(_T_901, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2276:347] + node _T_903 = and(_T_899, _T_902) @[dec_tlu_ctl.scala 2276:312] + node _T_904 = eq(tdata_kill_write, UInt<1>("h00")) @[dec_tlu_ctl.scala 2276:373] + node _T_905 = and(_T_903, _T_904) @[dec_tlu_ctl.scala 2276:371] + node _T_906 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2276:120] + node _T_907 = eq(_T_906, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2276:127] + node _T_908 = and(io.dec_csr_wen_r_mod, _T_907) @[dec_tlu_ctl.scala 2276:98] + node _T_909 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:149] + node _T_910 = and(_T_908, _T_909) @[dec_tlu_ctl.scala 2276:140] + node _T_911 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2276:182] + node _T_912 = eq(_T_911, UInt<1>("h00")) @[dec_tlu_ctl.scala 2276:166] + node _T_913 = or(_T_912, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2276:198] + node _T_914 = and(_T_910, _T_913) @[dec_tlu_ctl.scala 2276:163] + node _T_915 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2276:269] + node _T_916 = eq(_T_915, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2276:276] + node _T_917 = and(io.dec_csr_wen_r_mod, _T_916) @[dec_tlu_ctl.scala 2276:247] + node _T_918 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:298] + node _T_919 = and(_T_917, _T_918) @[dec_tlu_ctl.scala 2276:289] + node _T_920 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2276:331] + node _T_921 = eq(_T_920, UInt<1>("h00")) @[dec_tlu_ctl.scala 2276:315] + node _T_922 = or(_T_921, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2276:347] + node _T_923 = and(_T_919, _T_922) @[dec_tlu_ctl.scala 2276:312] + node _T_924 = eq(tdata_kill_write, UInt<1>("h00")) @[dec_tlu_ctl.scala 2276:373] + node _T_925 = and(_T_923, _T_924) @[dec_tlu_ctl.scala 2276:371] + wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2276:49] + wr_mtdata1_t_r[0] <= _T_894 @[dec_tlu_ctl.scala 2276:49] + wr_mtdata1_t_r[1] <= _T_905 @[dec_tlu_ctl.scala 2276:49] + wr_mtdata1_t_r[2] <= _T_914 @[dec_tlu_ctl.scala 2276:49] + wr_mtdata1_t_r[3] <= _T_925 @[dec_tlu_ctl.scala 2276:49] + node _T_926 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2278:77] + node _T_927 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2278:120] + node _T_928 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2278:144] + node _T_929 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2278:165] + node _T_930 = or(_T_928, _T_929) @[dec_tlu_ctl.scala 2278:148] + node _T_931 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2278:185] + node _T_932 = cat(_T_927, _T_930) @[Cat.scala 29:58] + node _T_933 = cat(_T_932, _T_931) @[Cat.scala 29:58] + node _T_934 = mux(_T_926, tdata_wrdata_r, _T_933) @[dec_tlu_ctl.scala 2278:58] + node _T_935 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2278:77] + node _T_936 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2278:120] + node _T_937 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2278:144] + node _T_938 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2278:165] + node _T_939 = or(_T_937, _T_938) @[dec_tlu_ctl.scala 2278:148] + node _T_940 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2278:185] + node _T_941 = cat(_T_936, _T_939) @[Cat.scala 29:58] + node _T_942 = cat(_T_941, _T_940) @[Cat.scala 29:58] + node _T_943 = mux(_T_935, tdata_wrdata_r, _T_942) @[dec_tlu_ctl.scala 2278:58] + node _T_944 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2278:77] + node _T_945 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2278:120] + node _T_946 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2278:144] + node _T_947 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2278:165] + node _T_948 = or(_T_946, _T_947) @[dec_tlu_ctl.scala 2278:148] + node _T_949 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2278:185] + node _T_950 = cat(_T_945, _T_948) @[Cat.scala 29:58] + node _T_951 = cat(_T_950, _T_949) @[Cat.scala 29:58] + node _T_952 = mux(_T_944, tdata_wrdata_r, _T_951) @[dec_tlu_ctl.scala 2278:58] + node _T_953 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2278:77] + node _T_954 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2278:120] + node _T_955 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2278:144] + node _T_956 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2278:165] + node _T_957 = or(_T_955, _T_956) @[dec_tlu_ctl.scala 2278:148] + node _T_958 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2278:185] + node _T_959 = cat(_T_954, _T_957) @[Cat.scala 29:58] + node _T_960 = cat(_T_959, _T_958) @[Cat.scala 29:58] + node _T_961 = mux(_T_953, tdata_wrdata_r, _T_960) @[dec_tlu_ctl.scala 2278:58] + wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2278:49] + mtdata1_t_ns[0] <= _T_934 @[dec_tlu_ctl.scala 2278:49] + mtdata1_t_ns[1] <= _T_943 @[dec_tlu_ctl.scala 2278:49] + mtdata1_t_ns[2] <= _T_952 @[dec_tlu_ctl.scala 2278:49] + mtdata1_t_ns[3] <= _T_961 @[dec_tlu_ctl.scala 2278:49] + node _T_962 = bits(io.trigger_enabled, 0, 0) @[dec_tlu_ctl.scala 2282:91] + node _T_963 = or(_T_962, wr_mtdata1_t_r[0]) @[dec_tlu_ctl.scala 2282:95] + node _T_964 = bits(_T_963, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_27 of rvclkhdr_39 @[lib.scala 404:23] + rvclkhdr_27.clock <= clock + rvclkhdr_27.reset <= reset + rvclkhdr_27.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_27.io.en <= _T_964 @[lib.scala 407:17] + rvclkhdr_27.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_965 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_964 : @[Reg.scala 28:19] + _T_965 <= mtdata1_t_ns[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mtdata1_t[0] <= _T_965 @[dec_tlu_ctl.scala 2282:47] + node _T_966 = bits(io.trigger_enabled, 1, 1) @[dec_tlu_ctl.scala 2282:91] + node _T_967 = or(_T_966, wr_mtdata1_t_r[1]) @[dec_tlu_ctl.scala 2282:95] + node _T_968 = bits(_T_967, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_28 of rvclkhdr_40 @[lib.scala 404:23] + rvclkhdr_28.clock <= clock + rvclkhdr_28.reset <= reset + rvclkhdr_28.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_28.io.en <= _T_968 @[lib.scala 407:17] + rvclkhdr_28.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_969 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_968 : @[Reg.scala 28:19] + _T_969 <= mtdata1_t_ns[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mtdata1_t[1] <= _T_969 @[dec_tlu_ctl.scala 2282:47] + node _T_970 = bits(io.trigger_enabled, 2, 2) @[dec_tlu_ctl.scala 2282:91] + node _T_971 = or(_T_970, wr_mtdata1_t_r[2]) @[dec_tlu_ctl.scala 2282:95] + node _T_972 = bits(_T_971, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_29 of rvclkhdr_41 @[lib.scala 404:23] + rvclkhdr_29.clock <= clock + rvclkhdr_29.reset <= reset + rvclkhdr_29.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_29.io.en <= _T_972 @[lib.scala 407:17] + rvclkhdr_29.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_973 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_972 : @[Reg.scala 28:19] + _T_973 <= mtdata1_t_ns[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mtdata1_t[2] <= _T_973 @[dec_tlu_ctl.scala 2282:47] + node _T_974 = bits(io.trigger_enabled, 3, 3) @[dec_tlu_ctl.scala 2282:91] + node _T_975 = or(_T_974, wr_mtdata1_t_r[3]) @[dec_tlu_ctl.scala 2282:95] + node _T_976 = bits(_T_975, 0, 0) @[lib.scala 8:44] + inst rvclkhdr_30 of rvclkhdr_42 @[lib.scala 404:23] + rvclkhdr_30.clock <= clock + rvclkhdr_30.reset <= reset + rvclkhdr_30.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_30.io.en <= _T_976 @[lib.scala 407:17] + rvclkhdr_30.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_977 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_976 : @[Reg.scala 28:19] + _T_977 <= mtdata1_t_ns[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.mtdata1_t[3] <= _T_977 @[dec_tlu_ctl.scala 2282:47] + node _T_978 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2285:66] + node _T_979 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2285:112] + node _T_980 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2285:150] + node _T_981 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2285:182] + node _T_982 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2285:214] + node _T_983 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2285:246] + node _T_984 = cat(UInt<3>("h00"), _T_983) @[Cat.scala 29:58] + node _T_985 = cat(_T_981, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_986 = cat(_T_985, _T_982) @[Cat.scala 29:58] + node _T_987 = cat(_T_986, _T_984) @[Cat.scala 29:58] + node _T_988 = cat(_T_980, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_989 = cat(UInt<4>("h02"), _T_979) @[Cat.scala 29:58] + node _T_990 = cat(_T_989, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_991 = cat(_T_990, _T_988) @[Cat.scala 29:58] + node _T_992 = cat(_T_991, _T_987) @[Cat.scala 29:58] + node _T_993 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2285:66] + node _T_994 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2285:112] + node _T_995 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2285:150] + node _T_996 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2285:182] + node _T_997 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2285:214] + node _T_998 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2285:246] + node _T_999 = cat(UInt<3>("h00"), _T_998) @[Cat.scala 29:58] + node _T_1000 = cat(_T_996, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1001 = cat(_T_1000, _T_997) @[Cat.scala 29:58] + node _T_1002 = cat(_T_1001, _T_999) @[Cat.scala 29:58] + node _T_1003 = cat(_T_995, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_1004 = cat(UInt<4>("h02"), _T_994) @[Cat.scala 29:58] + node _T_1005 = cat(_T_1004, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_1006 = cat(_T_1005, _T_1003) @[Cat.scala 29:58] + node _T_1007 = cat(_T_1006, _T_1002) @[Cat.scala 29:58] + node _T_1008 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2285:66] + node _T_1009 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2285:112] + node _T_1010 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2285:150] + node _T_1011 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2285:182] + node _T_1012 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2285:214] + node _T_1013 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2285:246] + node _T_1014 = cat(UInt<3>("h00"), _T_1013) @[Cat.scala 29:58] + node _T_1015 = cat(_T_1011, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1016 = cat(_T_1015, _T_1012) @[Cat.scala 29:58] + node _T_1017 = cat(_T_1016, _T_1014) @[Cat.scala 29:58] + node _T_1018 = cat(_T_1010, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_1019 = cat(UInt<4>("h02"), _T_1009) @[Cat.scala 29:58] + node _T_1020 = cat(_T_1019, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_1021 = cat(_T_1020, _T_1018) @[Cat.scala 29:58] + node _T_1022 = cat(_T_1021, _T_1017) @[Cat.scala 29:58] + node _T_1023 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2285:66] + node _T_1024 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2285:112] + node _T_1025 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2285:150] + node _T_1026 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2285:182] + node _T_1027 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2285:214] + node _T_1028 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2285:246] + node _T_1029 = cat(UInt<3>("h00"), _T_1028) @[Cat.scala 29:58] + node _T_1030 = cat(_T_1026, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1031 = cat(_T_1030, _T_1027) @[Cat.scala 29:58] + node _T_1032 = cat(_T_1031, _T_1029) @[Cat.scala 29:58] + node _T_1033 = cat(_T_1025, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_1034 = cat(UInt<4>("h02"), _T_1024) @[Cat.scala 29:58] + node _T_1035 = cat(_T_1034, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_1036 = cat(_T_1035, _T_1033) @[Cat.scala 29:58] + node _T_1037 = cat(_T_1036, _T_1032) @[Cat.scala 29:58] + node _T_1038 = mux(_T_978, _T_992, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1039 = mux(_T_993, _T_1007, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1040 = mux(_T_1008, _T_1022, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1041 = mux(_T_1023, _T_1037, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1042 = or(_T_1038, _T_1039) @[Mux.scala 27:72] + node _T_1043 = or(_T_1042, _T_1040) @[Mux.scala 27:72] + node _T_1044 = or(_T_1043, _T_1041) @[Mux.scala 27:72] + wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72] + mtdata1_tsel_out <= _T_1044 @[Mux.scala 27:72] + node _T_1045 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2287:66] + io.trigger_pkt_any[0].select <= _T_1045 @[dec_tlu_ctl.scala 2287:48] + node _T_1046 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2288:69] + io.trigger_pkt_any[0].match_pkt <= _T_1046 @[dec_tlu_ctl.scala 2288:51] + node _T_1047 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2289:66] + io.trigger_pkt_any[0].store <= _T_1047 @[dec_tlu_ctl.scala 2289:48] + node _T_1048 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2290:66] + io.trigger_pkt_any[0].load <= _T_1048 @[dec_tlu_ctl.scala 2290:48] + node _T_1049 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2291:66] + io.trigger_pkt_any[0].execute <= _T_1049 @[dec_tlu_ctl.scala 2291:48] + node _T_1050 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2292:66] + io.trigger_pkt_any[0].m <= _T_1050 @[dec_tlu_ctl.scala 2292:48] + node _T_1051 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2287:66] + io.trigger_pkt_any[1].select <= _T_1051 @[dec_tlu_ctl.scala 2287:48] + node _T_1052 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2288:69] + io.trigger_pkt_any[1].match_pkt <= _T_1052 @[dec_tlu_ctl.scala 2288:51] + node _T_1053 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2289:66] + io.trigger_pkt_any[1].store <= _T_1053 @[dec_tlu_ctl.scala 2289:48] + node _T_1054 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2290:66] + io.trigger_pkt_any[1].load <= _T_1054 @[dec_tlu_ctl.scala 2290:48] + node _T_1055 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2291:66] + io.trigger_pkt_any[1].execute <= _T_1055 @[dec_tlu_ctl.scala 2291:48] + node _T_1056 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2292:66] + io.trigger_pkt_any[1].m <= _T_1056 @[dec_tlu_ctl.scala 2292:48] + node _T_1057 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2287:66] + io.trigger_pkt_any[2].select <= _T_1057 @[dec_tlu_ctl.scala 2287:48] + node _T_1058 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2288:69] + io.trigger_pkt_any[2].match_pkt <= _T_1058 @[dec_tlu_ctl.scala 2288:51] + node _T_1059 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2289:66] + io.trigger_pkt_any[2].store <= _T_1059 @[dec_tlu_ctl.scala 2289:48] + node _T_1060 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2290:66] + io.trigger_pkt_any[2].load <= _T_1060 @[dec_tlu_ctl.scala 2290:48] + node _T_1061 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2291:66] + io.trigger_pkt_any[2].execute <= _T_1061 @[dec_tlu_ctl.scala 2291:48] + node _T_1062 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2292:66] + io.trigger_pkt_any[2].m <= _T_1062 @[dec_tlu_ctl.scala 2292:48] + node _T_1063 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2287:66] + io.trigger_pkt_any[3].select <= _T_1063 @[dec_tlu_ctl.scala 2287:48] + node _T_1064 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2288:69] + io.trigger_pkt_any[3].match_pkt <= _T_1064 @[dec_tlu_ctl.scala 2288:51] + node _T_1065 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2289:66] + io.trigger_pkt_any[3].store <= _T_1065 @[dec_tlu_ctl.scala 2289:48] + node _T_1066 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2290:66] + io.trigger_pkt_any[3].load <= _T_1066 @[dec_tlu_ctl.scala 2290:48] + node _T_1067 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2291:66] + io.trigger_pkt_any[3].execute <= _T_1067 @[dec_tlu_ctl.scala 2291:48] + node _T_1068 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2292:66] + io.trigger_pkt_any[3].m <= _T_1068 @[dec_tlu_ctl.scala 2292:48] + node _T_1069 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2299:98] + node _T_1070 = eq(_T_1069, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2299:105] + node _T_1071 = and(io.dec_csr_wen_r_mod, _T_1070) @[dec_tlu_ctl.scala 2299:76] + node _T_1072 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2299:127] + node _T_1073 = and(_T_1071, _T_1072) @[dec_tlu_ctl.scala 2299:118] + node _T_1074 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2299:160] + node _T_1075 = not(_T_1074) @[dec_tlu_ctl.scala 2299:144] + node _T_1076 = or(_T_1075, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2299:176] + node _T_1077 = and(_T_1073, _T_1076) @[dec_tlu_ctl.scala 2299:141] + node _T_1078 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2299:98] + node _T_1079 = eq(_T_1078, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2299:105] + node _T_1080 = and(io.dec_csr_wen_r_mod, _T_1079) @[dec_tlu_ctl.scala 2299:76] + node _T_1081 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2299:127] + node _T_1082 = and(_T_1080, _T_1081) @[dec_tlu_ctl.scala 2299:118] + node _T_1083 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2299:160] + node _T_1084 = not(_T_1083) @[dec_tlu_ctl.scala 2299:144] + node _T_1085 = or(_T_1084, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2299:176] + node _T_1086 = and(_T_1082, _T_1085) @[dec_tlu_ctl.scala 2299:141] + node _T_1087 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2299:98] + node _T_1088 = eq(_T_1087, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2299:105] + node _T_1089 = and(io.dec_csr_wen_r_mod, _T_1088) @[dec_tlu_ctl.scala 2299:76] + node _T_1090 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2299:127] + node _T_1091 = and(_T_1089, _T_1090) @[dec_tlu_ctl.scala 2299:118] + node _T_1092 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2299:160] + node _T_1093 = not(_T_1092) @[dec_tlu_ctl.scala 2299:144] + node _T_1094 = or(_T_1093, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2299:176] + node _T_1095 = and(_T_1091, _T_1094) @[dec_tlu_ctl.scala 2299:141] + node _T_1096 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2299:98] + node _T_1097 = eq(_T_1096, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2299:105] + node _T_1098 = and(io.dec_csr_wen_r_mod, _T_1097) @[dec_tlu_ctl.scala 2299:76] + node _T_1099 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2299:127] + node _T_1100 = and(_T_1098, _T_1099) @[dec_tlu_ctl.scala 2299:118] + node _T_1101 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2299:160] + node _T_1102 = not(_T_1101) @[dec_tlu_ctl.scala 2299:144] + node _T_1103 = or(_T_1102, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2299:176] + node _T_1104 = and(_T_1100, _T_1103) @[dec_tlu_ctl.scala 2299:141] + wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2299:49] + wr_mtdata2_t_r[0] <= _T_1077 @[dec_tlu_ctl.scala 2299:49] + wr_mtdata2_t_r[1] <= _T_1086 @[dec_tlu_ctl.scala 2299:49] + wr_mtdata2_t_r[2] <= _T_1095 @[dec_tlu_ctl.scala 2299:49] + wr_mtdata2_t_r[3] <= _T_1104 @[dec_tlu_ctl.scala 2299:49] + node _T_1105 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2300:92] + inst rvclkhdr_31 of rvclkhdr_43 @[lib.scala 404:23] + rvclkhdr_31.clock <= clock + rvclkhdr_31.reset <= reset + rvclkhdr_31.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_31.io.en <= _T_1105 @[lib.scala 407:17] + rvclkhdr_31.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1106 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1105 : @[Reg.scala 28:19] + _T_1106 <= io.dec_csr_wrdata_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mtdata2_t[0] <= _T_1106 @[dec_tlu_ctl.scala 2300:44] + node _T_1107 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2300:92] + inst rvclkhdr_32 of rvclkhdr_44 @[lib.scala 404:23] + rvclkhdr_32.clock <= clock + rvclkhdr_32.reset <= reset + rvclkhdr_32.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_32.io.en <= _T_1107 @[lib.scala 407:17] + rvclkhdr_32.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1108 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1107 : @[Reg.scala 28:19] + _T_1108 <= io.dec_csr_wrdata_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mtdata2_t[1] <= _T_1108 @[dec_tlu_ctl.scala 2300:44] + node _T_1109 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2300:92] + inst rvclkhdr_33 of rvclkhdr_45 @[lib.scala 404:23] + rvclkhdr_33.clock <= clock + rvclkhdr_33.reset <= reset + rvclkhdr_33.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_33.io.en <= _T_1109 @[lib.scala 407:17] + rvclkhdr_33.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1110 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1109 : @[Reg.scala 28:19] + _T_1110 <= io.dec_csr_wrdata_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mtdata2_t[2] <= _T_1110 @[dec_tlu_ctl.scala 2300:44] + node _T_1111 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2300:92] + inst rvclkhdr_34 of rvclkhdr_46 @[lib.scala 404:23] + rvclkhdr_34.clock <= clock + rvclkhdr_34.reset <= reset + rvclkhdr_34.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_34.io.en <= _T_1111 @[lib.scala 407:17] + rvclkhdr_34.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_1112 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1111 : @[Reg.scala 28:19] + _T_1112 <= io.dec_csr_wrdata_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mtdata2_t[3] <= _T_1112 @[dec_tlu_ctl.scala 2300:44] + node _T_1113 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2304:65] + node _T_1114 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2304:65] + node _T_1115 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2304:65] + node _T_1116 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2304:65] + node _T_1117 = mux(_T_1113, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1118 = mux(_T_1114, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1119 = mux(_T_1115, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1120 = mux(_T_1116, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1121 = or(_T_1117, _T_1118) @[Mux.scala 27:72] + node _T_1122 = or(_T_1121, _T_1119) @[Mux.scala 27:72] + node _T_1123 = or(_T_1122, _T_1120) @[Mux.scala 27:72] + wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72] + mtdata2_tsel_out <= _T_1123 @[Mux.scala 27:72] + io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2305:59] + io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2305:59] + io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2305:59] + io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[dec_tlu_ctl.scala 2305:59] + mhpme_vec[0] <= perf_csrs.io.mhpme3 @[dec_tlu_ctl.scala 2313:22] + mhpme_vec[1] <= perf_csrs.io.mhpme4 @[dec_tlu_ctl.scala 2314:22] + mhpme_vec[2] <= perf_csrs.io.mhpme5 @[dec_tlu_ctl.scala 2315:22] + mhpme_vec[3] <= perf_csrs.io.mhpme6 @[dec_tlu_ctl.scala 2316:22] + perfmux_flop.io.mcountinhibit <= mcountinhibit @[dec_tlu_ctl.scala 2321:57] + perfmux_flop.io.mhpme_vec[0] <= mhpme_vec[0] @[dec_tlu_ctl.scala 2322:57] + perfmux_flop.io.mhpme_vec[1] <= mhpme_vec[1] @[dec_tlu_ctl.scala 2322:57] + perfmux_flop.io.mhpme_vec[2] <= mhpme_vec[2] @[dec_tlu_ctl.scala 2322:57] + perfmux_flop.io.mhpme_vec[3] <= mhpme_vec[3] @[dec_tlu_ctl.scala 2322:57] + perfmux_flop.io.ifu_pmu_ic_hit <= io.ifu_pmu_ic_hit @[dec_tlu_ctl.scala 2323:57] + perfmux_flop.io.ifu_pmu_ic_miss <= io.ifu_pmu_ic_miss @[dec_tlu_ctl.scala 2324:57] + perfmux_flop.io.tlu_i0_commit_cmt <= io.tlu_i0_commit_cmt @[dec_tlu_ctl.scala 2325:57] + perfmux_flop.io.illegal_r <= io.illegal_r @[dec_tlu_ctl.scala 2326:57] + perfmux_flop.io.exu_pmu_i0_pc4 <= io.exu_pmu_i0_pc4 @[dec_tlu_ctl.scala 2327:57] + perfmux_flop.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[dec_tlu_ctl.scala 2328:57] + perfmux_flop.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[dec_tlu_ctl.scala 2329:57] + perfmux_flop.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.dec_tlu_packet_r.icaf_second <= io.dec_tlu_packet_r.icaf_second @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[dec_tlu_ctl.scala 2330:57] + perfmux_flop.io.exu_pmu_i0_br_misp <= io.exu_pmu_i0_br_misp @[dec_tlu_ctl.scala 2331:57] + perfmux_flop.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[dec_tlu_ctl.scala 2332:57] + perfmux_flop.io.exu_pmu_i0_br_ataken <= io.exu_pmu_i0_br_ataken @[dec_tlu_ctl.scala 2333:57] + perfmux_flop.io.ifu_pmu_fetch_stall <= io.ifu_pmu_fetch_stall @[dec_tlu_ctl.scala 2334:57] + perfmux_flop.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[dec_tlu_ctl.scala 2335:57] + perfmux_flop.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[dec_tlu_ctl.scala 2336:57] + perfmux_flop.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec_tlu_ctl.scala 2337:57] + perfmux_flop.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[dec_tlu_ctl.scala 2338:57] + perfmux_flop.io.dma_iccm_stall_any <= io.dma_iccm_stall_any @[dec_tlu_ctl.scala 2339:57] + perfmux_flop.io.i0_exception_valid_r <= io.i0_exception_valid_r @[dec_tlu_ctl.scala 2340:57] + perfmux_flop.io.dec_tlu_pmu_fw_halted <= io.dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 2341:57] + perfmux_flop.io.dma_pmu_any_read <= io.dma_pmu_any_read @[dec_tlu_ctl.scala 2342:57] + perfmux_flop.io.dma_pmu_any_write <= io.dma_pmu_any_write @[dec_tlu_ctl.scala 2343:57] + perfmux_flop.io.dma_pmu_dccm_read <= io.dma_pmu_dccm_read @[dec_tlu_ctl.scala 2344:57] + perfmux_flop.io.dma_pmu_dccm_write <= io.dma_pmu_dccm_write @[dec_tlu_ctl.scala 2345:57] + perfmux_flop.io.lsu_pmu_load_external_r <= io.lsu_pmu_load_external_r @[dec_tlu_ctl.scala 2346:57] + perfmux_flop.io.lsu_pmu_store_external_r <= io.lsu_pmu_store_external_r @[dec_tlu_ctl.scala 2347:57] + io.mstatus <= perfmux_flop.io.mstatus @[dec_tlu_ctl.scala 2348:26] + io.mip <= perfmux_flop.io.mip @[dec_tlu_ctl.scala 2349:18] + perfmux_flop.io.mie <= mie @[dec_tlu_ctl.scala 2350:57] + perfmux_flop.io.ifu_pmu_bus_trxn <= io.ifu_pmu_bus_trxn @[dec_tlu_ctl.scala 2351:57] + perfmux_flop.io.lsu_pmu_bus_trxn <= io.lsu_pmu_bus_trxn @[dec_tlu_ctl.scala 2352:57] + perfmux_flop.io.lsu_pmu_bus_misaligned <= io.lsu_pmu_bus_misaligned @[dec_tlu_ctl.scala 2353:57] + perfmux_flop.io.ifu_pmu_bus_error <= io.ifu_pmu_bus_error @[dec_tlu_ctl.scala 2354:57] + perfmux_flop.io.lsu_pmu_bus_error <= io.lsu_pmu_bus_error @[dec_tlu_ctl.scala 2355:57] + perfmux_flop.io.ifu_pmu_bus_busy <= io.ifu_pmu_bus_busy @[dec_tlu_ctl.scala 2356:57] + perfmux_flop.io.lsu_pmu_bus_busy <= io.lsu_pmu_bus_busy @[dec_tlu_ctl.scala 2357:57] + perfmux_flop.io.i0_trigger_hit_r <= io.i0_trigger_hit_r @[dec_tlu_ctl.scala 2358:57] + perfmux_flop.io.lsu_exc_valid_r <= io.lsu_exc_valid_r @[dec_tlu_ctl.scala 2359:57] + perfmux_flop.io.take_timer_int <= io.take_timer_int @[dec_tlu_ctl.scala 2360:57] + perfmux_flop.io.take_int_timer0_int <= io.take_int_timer0_int @[dec_tlu_ctl.scala 2361:57] + perfmux_flop.io.take_int_timer1_int <= io.take_int_timer1_int @[dec_tlu_ctl.scala 2362:57] + perfmux_flop.io.take_ext_int <= io.take_ext_int @[dec_tlu_ctl.scala 2363:57] + perfmux_flop.io.tlu_flush_lower_r <= io.tlu_flush_lower_r @[dec_tlu_ctl.scala 2364:57] + perfmux_flop.io.dec_tlu_br0_error_r <= io.dec_tlu_br0_error_r @[dec_tlu_ctl.scala 2365:57] + perfmux_flop.io.rfpc_i0_r <= io.rfpc_i0_r @[dec_tlu_ctl.scala 2366:57] + perfmux_flop.io.dec_tlu_br0_start_error_r <= io.dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 2367:57] + io.mdseac_locked_f <= perfmux_flop.io.mdseac_locked_f @[dec_tlu_ctl.scala 2378:42] + io.lsu_exc_valid_r_d1 <= perfmux_flop.io.lsu_exc_valid_r_d1 @[dec_tlu_ctl.scala 2380:42] + io.take_ext_int_start_d1 <= perfmux_flop.io.take_ext_int_start_d1 @[dec_tlu_ctl.scala 2382:42] + io.take_ext_int_start_d2 <= perfmux_flop.io.take_ext_int_start_d2 @[dec_tlu_ctl.scala 2383:42] + io.take_ext_int_start_d3 <= perfmux_flop.io.take_ext_int_start_d3 @[dec_tlu_ctl.scala 2384:42] + io.ext_int_freeze_d1 <= perfmux_flop.io.ext_int_freeze_d1 @[dec_tlu_ctl.scala 2385:42] + perfmux_flop.io.mdseac_locked_ns <= io.mdseac_locked_ns @[dec_tlu_ctl.scala 2389:55] + perfmux_flop.io.lsu_single_ecc_error_r <= io.lsu_single_ecc_error_r @[dec_tlu_ctl.scala 2390:55] + perfmux_flop.io.lsu_i0_exc_r <= io.lsu_i0_exc_r @[dec_tlu_ctl.scala 2391:55] + perfmux_flop.io.take_ext_int_start <= io.take_ext_int_start @[dec_tlu_ctl.scala 2392:55] + perfmux_flop.io.ext_int_freeze <= io.ext_int_freeze @[dec_tlu_ctl.scala 2393:55] + perfmux_flop.io.mip_ns <= mip_ns @[dec_tlu_ctl.scala 2394:55] + perfmux_flop.io.mcyclel_cout <= mcyclel_cout @[dec_tlu_ctl.scala 2395:55] + perfmux_flop.io.wr_mcycleh_r <= wr_mcycleh_r @[dec_tlu_ctl.scala 2396:55] + perfmux_flop.io.mcyclel_cout_in <= mcyclel_cout_in @[dec_tlu_ctl.scala 2397:55] + perfmux_flop.io.minstret_enable <= minstret_enable @[dec_tlu_ctl.scala 2398:55] + perfmux_flop.io.minstretl_cout_ns <= minstretl_cout_ns @[dec_tlu_ctl.scala 2399:55] + perfmux_flop.io.fw_halted_ns <= fw_halted_ns @[dec_tlu_ctl.scala 2400:55] + perfmux_flop.io.meicidpl_ns <= meicidpl_ns @[dec_tlu_ctl.scala 2401:55] + perfmux_flop.io.icache_rd_valid <= icache_rd_valid @[dec_tlu_ctl.scala 2402:55] + perfmux_flop.io.icache_wr_valid <= icache_wr_valid @[dec_tlu_ctl.scala 2403:55] + node _T_1124 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2404:91] + node _T_1125 = and(io.dec_tlu_dbg_halted, _T_1124) @[dec_tlu_ctl.scala 2404:82] + node _T_1126 = or(_T_1125, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2404:105] + perfmux_flop.io.perfcnt_halted <= _T_1126 @[dec_tlu_ctl.scala 2404:55] + perfmux_flop.io.mstatus_ns <= mstatus_ns @[dec_tlu_ctl.scala 2405:55] + perfmux_flop.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 2406:55] + perfmux_flop.io.free_l2clk <= io.free_l2clk @[dec_tlu_ctl.scala 2407:56] + perf_csrs.io.free_l2clk <= io.free_l2clk @[dec_tlu_ctl.scala 2411:50] + perf_csrs.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 2412:50] + perf_csrs.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[dec_tlu_ctl.scala 2413:50] + perf_csrs.io.dcsr <= io.dcsr @[dec_tlu_ctl.scala 2414:50] + perf_csrs.io.dec_tlu_pmu_fw_halted <= io.dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 2415:50] + perf_csrs.io.mhpme_vec[0] <= mhpme_vec[0] @[dec_tlu_ctl.scala 2416:50] + perf_csrs.io.mhpme_vec[1] <= mhpme_vec[1] @[dec_tlu_ctl.scala 2416:50] + perf_csrs.io.mhpme_vec[2] <= mhpme_vec[2] @[dec_tlu_ctl.scala 2416:50] + perf_csrs.io.mhpme_vec[3] <= mhpme_vec[3] @[dec_tlu_ctl.scala 2416:50] + perf_csrs.io.dec_csr_wen_r_mod <= io.dec_csr_wen_r_mod @[dec_tlu_ctl.scala 2417:50] + perf_csrs.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 2418:50] + perf_csrs.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 2419:50] + perf_csrs.io.mhpmc_inc_r[0] <= perfmux_flop.io.mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2420:50] + perf_csrs.io.mhpmc_inc_r[1] <= perfmux_flop.io.mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2420:50] + perf_csrs.io.mhpmc_inc_r[2] <= perfmux_flop.io.mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2420:50] + perf_csrs.io.mhpmc_inc_r[3] <= perfmux_flop.io.mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2420:50] + perf_csrs.io.mhpmc_inc_r_d1[0] <= perfmux_flop.io.mhpmc_inc_r_d1[0] @[dec_tlu_ctl.scala 2421:50] + perf_csrs.io.mhpmc_inc_r_d1[1] <= perfmux_flop.io.mhpmc_inc_r_d1[1] @[dec_tlu_ctl.scala 2421:50] + perf_csrs.io.mhpmc_inc_r_d1[2] <= perfmux_flop.io.mhpmc_inc_r_d1[2] @[dec_tlu_ctl.scala 2421:50] + perf_csrs.io.mhpmc_inc_r_d1[3] <= perfmux_flop.io.mhpmc_inc_r_d1[3] @[dec_tlu_ctl.scala 2421:50] + perf_csrs.io.perfcnt_halted_d1 <= perfmux_flop.io.perfcnt_halted_d1 @[dec_tlu_ctl.scala 2422:50] + io.dec_tlu_perfcnt0 <= perf_csrs.io.dec_tlu_perfcnt0 @[dec_tlu_ctl.scala 2436:29] + io.dec_tlu_perfcnt1 <= perf_csrs.io.dec_tlu_perfcnt1 @[dec_tlu_ctl.scala 2437:29] + io.dec_tlu_perfcnt2 <= perf_csrs.io.dec_tlu_perfcnt2 @[dec_tlu_ctl.scala 2438:29] + io.dec_tlu_perfcnt3 <= perf_csrs.io.dec_tlu_perfcnt3 @[dec_tlu_ctl.scala 2439:29] + node _T_1127 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2455:77] + node _T_1128 = eq(_T_1127, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2455:84] + node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_1128) @[dec_tlu_ctl.scala 2455:55] + node _T_1129 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2457:61] + wire temp_ncount0 : UInt<1> + temp_ncount0 <= _T_1129 + node _T_1130 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2458:61] + wire temp_ncount1 : UInt<1> + temp_ncount1 <= _T_1130 + node _T_1131 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2459:62] + wire temp_ncount6_2 : UInt<5> + temp_ncount6_2 <= _T_1131 + node _T_1132 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2460:81] + node _T_1133 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2460:110] + reg _T_1134 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1133 : @[Reg.scala 28:19] + _T_1134 <= _T_1132 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + temp_ncount6_2 <= _T_1134 @[dec_tlu_ctl.scala 2460:24] + node _T_1135 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2462:79] + node _T_1136 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2462:106] + reg _T_1137 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1136 : @[Reg.scala 28:19] + _T_1137 <= _T_1135 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + temp_ncount0 <= _T_1137 @[dec_tlu_ctl.scala 2462:22] + node _T_1138 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_1139 = cat(_T_1138, temp_ncount0) @[Cat.scala 29:58] + mcountinhibit <= _T_1139 @[dec_tlu_ctl.scala 2463:23] + node _T_1140 = eq(io.dec_tlu_trace_disable, UInt<1>("h00")) @[dec_tlu_ctl.scala 2468:42] + node _T_1141 = and(_T_1140, io.i0_valid_wb) @[dec_tlu_ctl.scala 2468:68] + io.dec_tlu_i0_valid_wb1 <= _T_1141 @[dec_tlu_ctl.scala 2468:39] + node _T_1142 = eq(io.dec_tlu_trace_disable, UInt<1>("h00")) @[dec_tlu_ctl.scala 2469:42] + node _T_1143 = or(io.i0_exception_valid_r_d1, perfmux_flop.io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2469:98] + node _T_1144 = eq(io.trigger_hit_dmode_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 2469:158] + node _T_1145 = and(io.trigger_hit_r_d1, _T_1144) @[dec_tlu_ctl.scala 2469:156] + node _T_1146 = or(_T_1143, _T_1145) @[dec_tlu_ctl.scala 2469:133] + node _T_1147 = and(_T_1142, _T_1146) @[dec_tlu_ctl.scala 2469:68] + io.dec_tlu_i0_exc_valid_wb1 <= _T_1147 @[dec_tlu_ctl.scala 2469:39] + node _T_1148 = eq(io.dec_tlu_trace_disable, UInt<1>("h00")) @[dec_tlu_ctl.scala 2470:49] + node _T_1149 = bits(_T_1148, 0, 0) @[Bitwise.scala 72:15] + node _T_1150 = mux(_T_1149, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node dec_tlu_exc_cause_wb1_raw = and(_T_1150, io.exc_cause_wb) @[dec_tlu_ctl.scala 2470:77] + node _T_1151 = eq(io.dec_tlu_trace_disable, UInt<1>("h00")) @[dec_tlu_ctl.scala 2471:42] + node dec_tlu_int_valid_wb1_raw = and(_T_1151, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2471:68] + wire dec_tlu_exc_cause_wb2 : UInt + dec_tlu_exc_cause_wb2 <= UInt<1>("h00") + node _T_1152 = xor(dec_tlu_exc_cause_wb1_raw, dec_tlu_exc_cause_wb2) @[lib.scala 448:21] + node _T_1153 = orr(_T_1152) @[lib.scala 448:29] + reg _T_1154 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1153 : @[Reg.scala 28:19] + _T_1154 <= dec_tlu_exc_cause_wb1_raw @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dec_tlu_exc_cause_wb2 <= _T_1154 @[lib.scala 451:16] + wire dec_tlu_int_valid_wb2 : UInt<1> + dec_tlu_int_valid_wb2 <= UInt<1>("h00") + node _T_1155 = xor(dec_tlu_int_valid_wb1_raw, dec_tlu_int_valid_wb2) @[lib.scala 470:21] + node _T_1156 = orr(_T_1155) @[lib.scala 470:29] + reg _T_1157 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1156 : @[Reg.scala 28:19] + _T_1157 <= dec_tlu_int_valid_wb1_raw @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dec_tlu_int_valid_wb2 <= _T_1157 @[lib.scala 473:16] + node _T_1158 = mux(dec_tlu_int_valid_wb2, dec_tlu_exc_cause_wb2, dec_tlu_exc_cause_wb1_raw) @[dec_tlu_ctl.scala 2477:40] + io.dec_tlu_exc_cause_wb1 <= _T_1158 @[dec_tlu_ctl.scala 2477:34] + io.dec_tlu_int_valid_wb1 <= dec_tlu_int_valid_wb2 @[dec_tlu_ctl.scala 2478:34] + io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2479:31] + node _T_1159 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2486:37] + node _T_1160 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2487:42] + node _T_1161 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2488:40] + node _T_1162 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2489:39] + node _T_1163 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2490:40] + node _T_1164 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1165 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2491:40] + node _T_1166 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2491:103] + node _T_1167 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2491:128] + node _T_1168 = cat(UInt<3>("h00"), _T_1167) @[Cat.scala 29:58] + node _T_1169 = cat(_T_1168, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1170 = cat(UInt<3>("h00"), _T_1166) @[Cat.scala 29:58] + node _T_1171 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] + node _T_1172 = cat(_T_1171, _T_1170) @[Cat.scala 29:58] + node _T_1173 = cat(_T_1172, _T_1169) @[Cat.scala 29:58] + node _T_1174 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2492:38] + node _T_1175 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2492:70] + node _T_1176 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2492:96] + node _T_1177 = cat(_T_1175, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_1178 = cat(_T_1177, _T_1176) @[Cat.scala 29:58] + node _T_1179 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2493:36] + node _T_1180 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2493:78] + node _T_1181 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2493:102] + node _T_1182 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2493:123] + node _T_1183 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2493:144] + node _T_1184 = cat(_T_1183, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1185 = cat(_T_1182, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1186 = cat(_T_1185, _T_1184) @[Cat.scala 29:58] + node _T_1187 = cat(_T_1181, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1188 = cat(UInt<1>("h00"), _T_1180) @[Cat.scala 29:58] + node _T_1189 = cat(_T_1188, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_1190 = cat(_T_1189, _T_1187) @[Cat.scala 29:58] + node _T_1191 = cat(_T_1190, _T_1186) @[Cat.scala 29:58] + node _T_1192 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2494:36] + node _T_1193 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2494:75] + node _T_1194 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2494:96] + node _T_1195 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2494:114] + node _T_1196 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2494:132] + node _T_1197 = cat(_T_1196, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1198 = cat(_T_1195, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1199 = cat(_T_1198, _T_1197) @[Cat.scala 29:58] + node _T_1200 = cat(_T_1194, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1201 = cat(UInt<1>("h00"), _T_1193) @[Cat.scala 29:58] + node _T_1202 = cat(_T_1201, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_1203 = cat(_T_1202, _T_1200) @[Cat.scala 29:58] + node _T_1204 = cat(_T_1203, _T_1199) @[Cat.scala 29:58] + node _T_1205 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2495:40] + node _T_1206 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2495:65] + node _T_1207 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2496:40] + node _T_1208 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2496:69] + node _T_1209 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2497:42] + node _T_1210 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2497:72] + node _T_1211 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2498:42] + node _T_1212 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2498:72] + node _T_1213 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2499:41] + node _T_1214 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2499:66] + node _T_1215 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2500:37] + node _T_1216 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_1217 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2501:39] + node _T_1218 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2501:64] + node _T_1219 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2502:40] + node _T_1220 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2502:80] + node _T_1221 = cat(UInt<28>("h00"), _T_1220) @[Cat.scala 29:58] + node _T_1222 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2503:38] + node _T_1223 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2503:63] + node _T_1224 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2504:37] + node _T_1225 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2504:62] + node _T_1226 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2505:39] + node _T_1227 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2505:64] + node _T_1228 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2506:38] + node _T_1229 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] + node _T_1230 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2507:39] + node _T_1231 = cat(meivt, meihap) @[Cat.scala 29:58] + node _T_1232 = cat(_T_1231, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_1233 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2508:41] + node _T_1234 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2508:81] + node _T_1235 = cat(UInt<28>("h00"), _T_1234) @[Cat.scala 29:58] + node _T_1236 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2509:41] + node _T_1237 = bits(perfmux_flop.io.meicidpl, 3, 0) @[dec_tlu_ctl.scala 2509:97] + node _T_1238 = cat(UInt<28>("h00"), _T_1237) @[Cat.scala 29:58] + node _T_1239 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2510:38] + node _T_1240 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2510:78] + node _T_1241 = cat(UInt<28>("h00"), _T_1240) @[Cat.scala 29:58] + node _T_1242 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2511:37] + node _T_1243 = bits(mcgc, 9, 0) @[dec_tlu_ctl.scala 2511:77] + node _T_1244 = cat(UInt<22>("h00"), _T_1243) @[Cat.scala 29:58] + node _T_1245 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2512:37] + node _T_1246 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2512:77] + node _T_1247 = cat(UInt<13>("h00"), _T_1246) @[Cat.scala 29:58] + node _T_1248 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2513:37] + node _T_1249 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2513:85] + node _T_1250 = cat(UInt<16>("h04000"), _T_1249) @[Cat.scala 29:58] + node _T_1251 = cat(_T_1250, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_1252 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2514:36] + node _T_1253 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_1254 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2515:39] + node _T_1255 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2515:64] + node _T_1256 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2516:40] + node _T_1257 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2516:65] + node _T_1258 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2517:39] + node _T_1259 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2517:64] + node _T_1260 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2518:41] + node _T_1261 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2518:80] + node _T_1262 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2518:104] + node _T_1263 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2518:131] + node _T_1264 = cat(UInt<3>("h00"), _T_1263) @[Cat.scala 29:58] + node _T_1265 = cat(_T_1264, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_1266 = cat(UInt<2>("h00"), _T_1262) @[Cat.scala 29:58] + node _T_1267 = cat(UInt<7>("h00"), _T_1261) @[Cat.scala 29:58] + node _T_1268 = cat(_T_1267, _T_1266) @[Cat.scala 29:58] + node _T_1269 = cat(_T_1268, _T_1265) @[Cat.scala 29:58] + node _T_1270 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2519:38] + node _T_1271 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2519:78] + node _T_1272 = cat(UInt<30>("h00"), _T_1271) @[Cat.scala 29:58] + node _T_1273 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2520:40] + node _T_1274 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2520:74] + node _T_1275 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2521:40] + node _T_1276 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2521:74] + node _T_1277 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2522:39] + node _T_1278 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2522:64] + node _T_1279 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2523:41] + node _T_1280 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2523:66] + node _T_1281 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2524:41] + node _T_1282 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2524:66] + node _T_1283 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2525:39] + node _T_1284 = bits(perf_csrs.io.mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2525:77] + node _T_1285 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2526:39] + node _T_1286 = bits(perf_csrs.io.mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2526:77] + node _T_1287 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2527:39] + node _T_1288 = bits(perf_csrs.io.mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2527:77] + node _T_1289 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2528:39] + node _T_1290 = bits(perf_csrs.io.mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2528:77] + node _T_1291 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2529:40] + node _T_1292 = bits(perf_csrs.io.mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2529:78] + node _T_1293 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2530:40] + node _T_1294 = bits(perf_csrs.io.mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2530:78] + node _T_1295 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2531:40] + node _T_1296 = bits(perf_csrs.io.mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2531:78] + node _T_1297 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2532:40] + node _T_1298 = bits(perf_csrs.io.mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2532:78] + node _T_1299 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2533:38] + node _T_1300 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2533:78] + node _T_1301 = cat(UInt<26>("h00"), _T_1300) @[Cat.scala 29:58] + node _T_1302 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2534:38] + node _T_1303 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2534:78] + node _T_1304 = cat(UInt<30>("h00"), _T_1303) @[Cat.scala 29:58] + node _T_1305 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2535:39] + node _T_1306 = bits(perf_csrs.io.mhpme3, 9, 0) @[dec_tlu_ctl.scala 2535:92] + node _T_1307 = cat(UInt<22>("h00"), _T_1306) @[Cat.scala 29:58] + node _T_1308 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2536:39] + node _T_1309 = bits(perf_csrs.io.mhpme4, 9, 0) @[dec_tlu_ctl.scala 2536:92] + node _T_1310 = cat(UInt<22>("h00"), _T_1309) @[Cat.scala 29:58] + node _T_1311 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2537:39] + node _T_1312 = bits(perf_csrs.io.mhpme5, 9, 0) @[dec_tlu_ctl.scala 2537:91] + node _T_1313 = cat(UInt<22>("h00"), _T_1312) @[Cat.scala 29:58] + node _T_1314 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2538:39] + node _T_1315 = bits(perf_csrs.io.mhpme6, 9, 0) @[dec_tlu_ctl.scala 2538:91] + node _T_1316 = cat(UInt<22>("h00"), _T_1315) @[Cat.scala 29:58] + node _T_1317 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2539:46] + node _T_1318 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2539:86] + node _T_1319 = cat(UInt<25>("h00"), _T_1318) @[Cat.scala 29:58] + node _T_1320 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2540:37] + node _T_1321 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] + node _T_1322 = cat(_T_1321, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_1323 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2541:37] + node _T_1324 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2541:76] + node _T_1325 = mux(_T_1159, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1326 = mux(_T_1160, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1327 = mux(_T_1161, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1328 = mux(_T_1162, UInt<32>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1329 = mux(_T_1163, _T_1164, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1330 = mux(_T_1165, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1331 = mux(_T_1174, _T_1178, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1332 = mux(_T_1179, _T_1191, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1333 = mux(_T_1192, _T_1204, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1334 = mux(_T_1205, _T_1206, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1335 = mux(_T_1207, _T_1208, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1336 = mux(_T_1209, _T_1210, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1337 = mux(_T_1211, _T_1212, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1338 = mux(_T_1213, _T_1214, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1339 = mux(_T_1215, _T_1216, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1340 = mux(_T_1217, _T_1218, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1341 = mux(_T_1219, _T_1221, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1342 = mux(_T_1222, _T_1223, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1343 = mux(_T_1224, _T_1225, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1344 = mux(_T_1226, _T_1227, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1345 = mux(_T_1228, _T_1229, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1346 = mux(_T_1230, _T_1232, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1347 = mux(_T_1233, _T_1235, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1348 = mux(_T_1236, _T_1238, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1349 = mux(_T_1239, _T_1241, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1350 = mux(_T_1242, _T_1244, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1351 = mux(_T_1245, _T_1247, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1352 = mux(_T_1248, _T_1251, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1353 = mux(_T_1252, _T_1253, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1354 = mux(_T_1254, _T_1255, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1355 = mux(_T_1256, _T_1257, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1356 = mux(_T_1258, _T_1259, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1357 = mux(_T_1260, _T_1269, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1358 = mux(_T_1270, _T_1272, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1359 = mux(_T_1273, _T_1274, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1360 = mux(_T_1275, _T_1276, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1361 = mux(_T_1277, _T_1278, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1362 = mux(_T_1279, _T_1280, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1363 = mux(_T_1281, _T_1282, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1364 = mux(_T_1283, _T_1284, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1365 = mux(_T_1285, _T_1286, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1366 = mux(_T_1287, _T_1288, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1367 = mux(_T_1289, _T_1290, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1368 = mux(_T_1291, _T_1292, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1369 = mux(_T_1293, _T_1294, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1370 = mux(_T_1295, _T_1296, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1371 = mux(_T_1297, _T_1298, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1372 = mux(_T_1299, _T_1301, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1373 = mux(_T_1302, _T_1304, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1374 = mux(_T_1305, _T_1307, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1375 = mux(_T_1308, _T_1310, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1376 = mux(_T_1311, _T_1313, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1377 = mux(_T_1314, _T_1316, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1378 = mux(_T_1317, _T_1319, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1379 = mux(_T_1320, _T_1322, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1380 = mux(_T_1323, _T_1324, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1381 = or(_T_1325, _T_1326) @[Mux.scala 27:72] + node _T_1382 = or(_T_1381, _T_1327) @[Mux.scala 27:72] + node _T_1383 = or(_T_1382, _T_1328) @[Mux.scala 27:72] + node _T_1384 = or(_T_1383, _T_1329) @[Mux.scala 27:72] + node _T_1385 = or(_T_1384, _T_1330) @[Mux.scala 27:72] + node _T_1386 = or(_T_1385, _T_1331) @[Mux.scala 27:72] + node _T_1387 = or(_T_1386, _T_1332) @[Mux.scala 27:72] + node _T_1388 = or(_T_1387, _T_1333) @[Mux.scala 27:72] + node _T_1389 = or(_T_1388, _T_1334) @[Mux.scala 27:72] + node _T_1390 = or(_T_1389, _T_1335) @[Mux.scala 27:72] + node _T_1391 = or(_T_1390, _T_1336) @[Mux.scala 27:72] + node _T_1392 = or(_T_1391, _T_1337) @[Mux.scala 27:72] + node _T_1393 = or(_T_1392, _T_1338) @[Mux.scala 27:72] + node _T_1394 = or(_T_1393, _T_1339) @[Mux.scala 27:72] + node _T_1395 = or(_T_1394, _T_1340) @[Mux.scala 27:72] + node _T_1396 = or(_T_1395, _T_1341) @[Mux.scala 27:72] + node _T_1397 = or(_T_1396, _T_1342) @[Mux.scala 27:72] + node _T_1398 = or(_T_1397, _T_1343) @[Mux.scala 27:72] + node _T_1399 = or(_T_1398, _T_1344) @[Mux.scala 27:72] + node _T_1400 = or(_T_1399, _T_1345) @[Mux.scala 27:72] + node _T_1401 = or(_T_1400, _T_1346) @[Mux.scala 27:72] + node _T_1402 = or(_T_1401, _T_1347) @[Mux.scala 27:72] + node _T_1403 = or(_T_1402, _T_1348) @[Mux.scala 27:72] + node _T_1404 = or(_T_1403, _T_1349) @[Mux.scala 27:72] + node _T_1405 = or(_T_1404, _T_1350) @[Mux.scala 27:72] + node _T_1406 = or(_T_1405, _T_1351) @[Mux.scala 27:72] + node _T_1407 = or(_T_1406, _T_1352) @[Mux.scala 27:72] + node _T_1408 = or(_T_1407, _T_1353) @[Mux.scala 27:72] + node _T_1409 = or(_T_1408, _T_1354) @[Mux.scala 27:72] + node _T_1410 = or(_T_1409, _T_1355) @[Mux.scala 27:72] + node _T_1411 = or(_T_1410, _T_1356) @[Mux.scala 27:72] + node _T_1412 = or(_T_1411, _T_1357) @[Mux.scala 27:72] + node _T_1413 = or(_T_1412, _T_1358) @[Mux.scala 27:72] + node _T_1414 = or(_T_1413, _T_1359) @[Mux.scala 27:72] + node _T_1415 = or(_T_1414, _T_1360) @[Mux.scala 27:72] + node _T_1416 = or(_T_1415, _T_1361) @[Mux.scala 27:72] + node _T_1417 = or(_T_1416, _T_1362) @[Mux.scala 27:72] + node _T_1418 = or(_T_1417, _T_1363) @[Mux.scala 27:72] + node _T_1419 = or(_T_1418, _T_1364) @[Mux.scala 27:72] + node _T_1420 = or(_T_1419, _T_1365) @[Mux.scala 27:72] + node _T_1421 = or(_T_1420, _T_1366) @[Mux.scala 27:72] + node _T_1422 = or(_T_1421, _T_1367) @[Mux.scala 27:72] + node _T_1423 = or(_T_1422, _T_1368) @[Mux.scala 27:72] + node _T_1424 = or(_T_1423, _T_1369) @[Mux.scala 27:72] + node _T_1425 = or(_T_1424, _T_1370) @[Mux.scala 27:72] + node _T_1426 = or(_T_1425, _T_1371) @[Mux.scala 27:72] + node _T_1427 = or(_T_1426, _T_1372) @[Mux.scala 27:72] + node _T_1428 = or(_T_1427, _T_1373) @[Mux.scala 27:72] + node _T_1429 = or(_T_1428, _T_1374) @[Mux.scala 27:72] + node _T_1430 = or(_T_1429, _T_1375) @[Mux.scala 27:72] + node _T_1431 = or(_T_1430, _T_1376) @[Mux.scala 27:72] + node _T_1432 = or(_T_1431, _T_1377) @[Mux.scala 27:72] + node _T_1433 = or(_T_1432, _T_1378) @[Mux.scala 27:72] + node _T_1434 = or(_T_1433, _T_1379) @[Mux.scala 27:72] + node _T_1435 = or(_T_1434, _T_1380) @[Mux.scala 27:72] + wire _T_1436 : UInt @[Mux.scala 27:72] + _T_1436 <= _T_1435 @[Mux.scala 27:72] + io.dec_csr_rddata_d <= _T_1436 @[dec_tlu_ctl.scala 2485:28] + + extmodule gated_latch_47 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_47 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_47 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_48 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_48 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_48 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_49 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_49 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_49 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_50 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_50 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_50 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_51 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_51 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_51 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_52 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_52 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_52 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module dec_timer_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip free_l2clk : Clock, flip csr_wr_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wen_r_mod : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip csr_mitctl0 : UInt<1>, flip csr_mitctl1 : UInt<1>, flip csr_mitb0 : UInt<1>, flip csr_mitb1 : UInt<1>, flip csr_mitcnt0 : UInt<1>, flip csr_mitcnt1 : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip internal_dbg_halt_timers : UInt<1>, dec_timer_rddata_d : UInt<32>, dec_timer_read_d : UInt<1>, dec_timer_t0_pulse : UInt<1>, dec_timer_t1_pulse : UInt<1>} + + wire mitctl1 : UInt<4> + mitctl1 <= UInt<1>("h00") + wire mitctl0 : UInt<3> + mitctl0 <= UInt<1>("h00") + wire mitb1 : UInt<32> + mitb1 <= UInt<1>("h00") + wire mitb0 : UInt<32> + mitb0 <= UInt<1>("h00") + wire mitcnt1 : UInt<32> + mitcnt1 <= UInt<1>("h00") + wire mitcnt0 : UInt<32> + mitcnt0 <= UInt<1>("h00") + node mit0_match_ns = geq(mitcnt0, mitb0) @[dec_tlu_ctl.scala 3277:36] + node mit1_match_ns = geq(mitcnt1, mitb1) @[dec_tlu_ctl.scala 3278:36] + io.dec_timer_t0_pulse <= mit0_match_ns @[dec_tlu_ctl.scala 3280:31] + io.dec_timer_t1_pulse <= mit1_match_ns @[dec_tlu_ctl.scala 3281:31] + node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[dec_tlu_ctl.scala 3288:72] + node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[dec_tlu_ctl.scala 3288:49] + node _T_1 = bits(mitctl0, 0, 0) @[dec_tlu_ctl.scala 3290:37] + node _T_2 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 3290:56] + node _T_3 = bits(mitctl0, 2, 2) @[dec_tlu_ctl.scala 3290:85] + node _T_4 = or(_T_2, _T_3) @[dec_tlu_ctl.scala 3290:76] + node _T_5 = and(_T_1, _T_4) @[dec_tlu_ctl.scala 3290:53] + node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 3290:112] + node _T_7 = bits(mitctl0, 1, 1) @[dec_tlu_ctl.scala 3290:147] + node _T_8 = or(_T_6, _T_7) @[dec_tlu_ctl.scala 3290:138] + node _T_9 = and(_T_5, _T_8) @[dec_tlu_ctl.scala 3290:109] + node _T_10 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 3290:173] + node mitcnt0_inc_ok = and(_T_9, _T_10) @[dec_tlu_ctl.scala 3290:171] + wire mitcnt0_inc1 : UInt<9> + mitcnt0_inc1 <= UInt<1>("h00") + wire mitcnt0_inc2 : UInt<24> + mitcnt0_inc2 <= UInt<1>("h00") + node _T_11 = bits(mitcnt0, 7, 0) @[dec_tlu_ctl.scala 3293:32] + node _T_12 = cat(UInt<7>("h00"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_13 = add(_T_11, _T_12) @[dec_tlu_ctl.scala 3293:38] + node _T_14 = tail(_T_13, 1) @[dec_tlu_ctl.scala 3293:38] + mitcnt0_inc1 <= _T_14 @[dec_tlu_ctl.scala 3293:22] + node mitcnt0_inc_cout = bits(mitcnt0_inc1, 8, 8) @[dec_tlu_ctl.scala 3294:44] + node _T_15 = bits(mitcnt0, 31, 8) @[dec_tlu_ctl.scala 3295:32] + node _T_16 = cat(UInt<23>("h00"), mitcnt0_inc_cout) @[Cat.scala 29:58] + node _T_17 = add(_T_15, _T_16) @[dec_tlu_ctl.scala 3295:39] + node _T_18 = tail(_T_17, 1) @[dec_tlu_ctl.scala 3295:39] + mitcnt0_inc2 <= _T_18 @[dec_tlu_ctl.scala 3295:22] + node _T_19 = bits(mitcnt0_inc1, 7, 0) @[dec_tlu_ctl.scala 3296:56] + node mitcnt0_inc = cat(mitcnt0_inc2, _T_19) @[Cat.scala 29:58] + node _T_20 = bits(wr_mitcnt0_r, 0, 0) @[lib.scala 8:44] + node _T_21 = bits(mit0_match_ns, 0, 0) @[lib.scala 8:44] + node _T_22 = mux(_T_21, UInt<1>("h00"), mitcnt0_inc) @[dec_tlu_ctl.scala 3298:69] + node mitcnt0_ns = mux(_T_20, io.dec_csr_wrdata_r, _T_22) @[dec_tlu_ctl.scala 3298:30] + node _T_23 = bits(mitcnt0_ns, 31, 8) @[dec_tlu_ctl.scala 3301:48] + node _T_24 = and(mitcnt0_inc_ok, mitcnt0_inc_cout) @[dec_tlu_ctl.scala 3301:87] + node _T_25 = or(wr_mitcnt0_r, _T_24) @[dec_tlu_ctl.scala 3301:69] + node _T_26 = or(_T_25, mit0_match_ns) @[dec_tlu_ctl.scala 3301:107] + node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 3301:124] + inst rvclkhdr of rvclkhdr_47 @[lib.scala 404:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr.io.en <= _T_27 @[lib.scala 407:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_28 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_27 : @[Reg.scala 28:19] + _T_28 <= _T_23 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_29 = bits(mitcnt0_ns, 7, 0) @[dec_tlu_ctl.scala 3302:34] + node _T_30 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[dec_tlu_ctl.scala 3302:54] + node _T_31 = or(_T_30, mit0_match_ns) @[dec_tlu_ctl.scala 3302:71] + node _T_32 = bits(_T_31, 0, 0) @[dec_tlu_ctl.scala 3302:88] + inst rvclkhdr_1 of rvclkhdr_48 @[lib.scala 404:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_1.io.en <= _T_32 @[lib.scala 407:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_33 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_32 : @[Reg.scala 28:19] + _T_33 <= _T_29 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_34 = cat(_T_28, _T_33) @[Cat.scala 29:58] + mitcnt0 <= _T_34 @[dec_tlu_ctl.scala 3301:25] + node _T_35 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[dec_tlu_ctl.scala 3309:72] + node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_35) @[dec_tlu_ctl.scala 3309:49] + node _T_36 = bits(mitctl1, 0, 0) @[dec_tlu_ctl.scala 3311:37] + node _T_37 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 3311:56] + node _T_38 = bits(mitctl1, 2, 2) @[dec_tlu_ctl.scala 3311:85] + node _T_39 = or(_T_37, _T_38) @[dec_tlu_ctl.scala 3311:76] + node _T_40 = and(_T_36, _T_39) @[dec_tlu_ctl.scala 3311:53] + node _T_41 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 3311:112] + node _T_42 = bits(mitctl1, 1, 1) @[dec_tlu_ctl.scala 3311:147] + node _T_43 = or(_T_41, _T_42) @[dec_tlu_ctl.scala 3311:138] + node _T_44 = and(_T_40, _T_43) @[dec_tlu_ctl.scala 3311:109] + node _T_45 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 3311:173] + node _T_46 = and(_T_44, _T_45) @[dec_tlu_ctl.scala 3311:171] + node _T_47 = bits(mitctl1, 3, 3) @[dec_tlu_ctl.scala 3311:213] + node _T_48 = not(_T_47) @[dec_tlu_ctl.scala 3311:205] + node _T_49 = or(_T_48, mit0_match_ns) @[dec_tlu_ctl.scala 3311:217] + node mitcnt1_inc_ok = and(_T_46, _T_49) @[dec_tlu_ctl.scala 3311:202] + wire mitcnt1_inc1 : UInt<9> + mitcnt1_inc1 <= UInt<1>("h00") + wire mitcnt1_inc2 : UInt<24> + mitcnt1_inc2 <= UInt<1>("h00") + node _T_50 = bits(mitcnt1, 7, 0) @[dec_tlu_ctl.scala 3316:32] + node _T_51 = cat(UInt<7>("h00"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_52 = add(_T_50, _T_51) @[dec_tlu_ctl.scala 3316:38] + node _T_53 = tail(_T_52, 1) @[dec_tlu_ctl.scala 3316:38] + mitcnt1_inc1 <= _T_53 @[dec_tlu_ctl.scala 3316:22] + node mitcnt1_inc_cout = bits(mitcnt1_inc1, 8, 8) @[dec_tlu_ctl.scala 3317:44] + node _T_54 = bits(mitcnt1, 31, 8) @[dec_tlu_ctl.scala 3318:32] + node _T_55 = cat(UInt<23>("h00"), mitcnt1_inc_cout) @[Cat.scala 29:58] + node _T_56 = add(_T_54, _T_55) @[dec_tlu_ctl.scala 3318:39] + node _T_57 = tail(_T_56, 1) @[dec_tlu_ctl.scala 3318:39] + mitcnt1_inc2 <= _T_57 @[dec_tlu_ctl.scala 3318:22] + node _T_58 = bits(mitcnt1_inc1, 7, 0) @[dec_tlu_ctl.scala 3319:56] + node mitcnt1_inc = cat(mitcnt1_inc2, _T_58) @[Cat.scala 29:58] + node _T_59 = bits(wr_mitcnt1_r, 0, 0) @[dec_tlu_ctl.scala 3321:43] + node _T_60 = bits(mit1_match_ns, 0, 0) @[dec_tlu_ctl.scala 3321:90] + node _T_61 = mux(_T_60, UInt<1>("h00"), mitcnt1_inc) @[dec_tlu_ctl.scala 3321:75] + node mitcnt1_ns = mux(_T_59, io.dec_csr_wrdata_r, _T_61) @[dec_tlu_ctl.scala 3321:29] + node _T_62 = bits(mitcnt1_ns, 31, 8) @[dec_tlu_ctl.scala 3323:48] + node _T_63 = and(mitcnt1_inc_ok, mitcnt1_inc_cout) @[dec_tlu_ctl.scala 3323:87] + node _T_64 = or(wr_mitcnt1_r, _T_63) @[dec_tlu_ctl.scala 3323:69] + node _T_65 = or(_T_64, mit1_match_ns) @[dec_tlu_ctl.scala 3323:107] + node _T_66 = bits(_T_65, 0, 0) @[dec_tlu_ctl.scala 3323:124] + inst rvclkhdr_2 of rvclkhdr_49 @[lib.scala 404:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_2.io.en <= _T_66 @[lib.scala 407:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_67 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_66 : @[Reg.scala 28:19] + _T_67 <= _T_62 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_68 = bits(mitcnt1_ns, 7, 0) @[dec_tlu_ctl.scala 3324:34] + node _T_69 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[dec_tlu_ctl.scala 3324:54] + node _T_70 = or(_T_69, mit1_match_ns) @[dec_tlu_ctl.scala 3324:71] + node _T_71 = bits(_T_70, 0, 0) @[dec_tlu_ctl.scala 3324:88] + inst rvclkhdr_3 of rvclkhdr_50 @[lib.scala 404:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= io.free_l2clk @[lib.scala 406:18] + rvclkhdr_3.io.en <= _T_71 @[lib.scala 407:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg _T_72 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_71 : @[Reg.scala 28:19] + _T_72 <= _T_68 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_73 = cat(_T_67, _T_72) @[Cat.scala 29:58] + mitcnt1 <= _T_73 @[dec_tlu_ctl.scala 3323:25] + node _T_74 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[dec_tlu_ctl.scala 3333:70] + node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_74) @[dec_tlu_ctl.scala 3333:47] + node _T_75 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 3334:38] + node _T_76 = bits(wr_mitb0_r, 0, 0) @[dec_tlu_ctl.scala 3334:71] + inst rvclkhdr_4 of rvclkhdr_51 @[lib.scala 404:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_4.io.en <= _T_76 @[lib.scala 407:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg mitb0_b : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_76 : @[Reg.scala 28:19] + mitb0_b <= _T_75 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_77 = not(mitb0_b) @[dec_tlu_ctl.scala 3335:22] + mitb0 <= _T_77 @[dec_tlu_ctl.scala 3335:19] + node _T_78 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[dec_tlu_ctl.scala 3342:69] + node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_78) @[dec_tlu_ctl.scala 3342:47] + node _T_79 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 3343:29] + node _T_80 = bits(wr_mitb1_r, 0, 0) @[dec_tlu_ctl.scala 3343:62] + inst rvclkhdr_5 of rvclkhdr_52 @[lib.scala 404:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 406:18] + rvclkhdr_5.io.en <= _T_80 @[lib.scala 407:17] + rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24] + reg mitb1_b : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_80 : @[Reg.scala 28:19] + mitb1_b <= _T_79 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_81 = not(mitb1_b) @[dec_tlu_ctl.scala 3344:18] + mitb1 <= _T_81 @[dec_tlu_ctl.scala 3344:15] + node _T_82 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[dec_tlu_ctl.scala 3355:72] + node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_82) @[dec_tlu_ctl.scala 3355:49] + node _T_83 = bits(wr_mitctl0_r, 0, 0) @[dec_tlu_ctl.scala 3356:45] + node _T_84 = bits(io.dec_csr_wrdata_r, 2, 0) @[dec_tlu_ctl.scala 3356:72] + node _T_85 = bits(mitctl0, 2, 0) @[dec_tlu_ctl.scala 3356:86] + node mitctl0_ns = mux(_T_83, _T_84, _T_85) @[dec_tlu_ctl.scala 3356:31] + node _T_86 = bits(mitctl0_ns, 0, 0) @[dec_tlu_ctl.scala 3358:41] + node mitctl0_0_b_ns = not(_T_86) @[dec_tlu_ctl.scala 3358:30] + node _T_87 = bits(wr_mitctl0_r, 0, 0) @[lib.scala 8:44] + reg mitctl0_0_b : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_87 : @[Reg.scala 28:19] + mitctl0_0_b <= mitctl0_0_b_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_88 = bits(mitctl0_ns, 2, 1) @[dec_tlu_ctl.scala 3360:82] + node _T_89 = bits(wr_mitctl0_r, 0, 0) @[lib.scala 8:44] + reg _T_90 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_89 : @[Reg.scala 28:19] + _T_90 <= _T_88 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_91 = not(mitctl0_0_b) @[dec_tlu_ctl.scala 3360:107] + node _T_92 = cat(_T_90, _T_91) @[Cat.scala 29:58] + mitctl0 <= _T_92 @[dec_tlu_ctl.scala 3360:31] + node _T_93 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[dec_tlu_ctl.scala 3370:71] + node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_93) @[dec_tlu_ctl.scala 3370:49] + node _T_94 = bits(wr_mitctl1_r, 0, 0) @[dec_tlu_ctl.scala 3371:45] + node _T_95 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 3371:71] + node _T_96 = bits(mitctl1, 3, 0) @[dec_tlu_ctl.scala 3371:85] + node mitctl1_ns = mux(_T_94, _T_95, _T_96) @[dec_tlu_ctl.scala 3371:31] + node _T_97 = bits(mitctl1_ns, 0, 0) @[dec_tlu_ctl.scala 3372:40] + node mitctl1_0_b_ns = not(_T_97) @[dec_tlu_ctl.scala 3372:29] + node _T_98 = bits(wr_mitctl1_r, 0, 0) @[lib.scala 8:44] + reg mitctl1_0_b : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_98 : @[Reg.scala 28:19] + mitctl1_0_b <= mitctl1_0_b_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_99 = bits(mitctl1_ns, 3, 1) @[dec_tlu_ctl.scala 3374:67] + node _T_100 = bits(wr_mitctl1_r, 0, 0) @[lib.scala 8:44] + reg _T_101 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_100 : @[Reg.scala 28:19] + _T_101 <= _T_99 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_102 = not(mitctl1_0_b) @[dec_tlu_ctl.scala 3374:92] + node _T_103 = cat(_T_101, _T_102) @[Cat.scala 29:58] + mitctl1 <= _T_103 @[dec_tlu_ctl.scala 3374:16] + node _T_104 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[dec_tlu_ctl.scala 3376:51] + node _T_105 = or(_T_104, io.csr_mitb1) @[dec_tlu_ctl.scala 3376:68] + node _T_106 = or(_T_105, io.csr_mitb0) @[dec_tlu_ctl.scala 3376:83] + node _T_107 = or(_T_106, io.csr_mitctl0) @[dec_tlu_ctl.scala 3376:98] + node _T_108 = or(_T_107, io.csr_mitctl1) @[dec_tlu_ctl.scala 3376:115] + io.dec_timer_read_d <= _T_108 @[dec_tlu_ctl.scala 3376:33] + node _T_109 = bits(io.csr_mitcnt0, 0, 0) @[dec_tlu_ctl.scala 3378:32] + node _T_110 = bits(mitcnt0, 31, 0) @[dec_tlu_ctl.scala 3378:51] + node _T_111 = bits(io.csr_mitcnt1, 0, 0) @[dec_tlu_ctl.scala 3379:32] + node _T_112 = bits(io.csr_mitb0, 0, 0) @[dec_tlu_ctl.scala 3380:30] + node _T_113 = bits(io.csr_mitb1, 0, 0) @[dec_tlu_ctl.scala 3381:30] + node _T_114 = bits(io.csr_mitctl0, 0, 0) @[dec_tlu_ctl.scala 3382:32] + node _T_115 = mux(UInt<1>("h00"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12] + node _T_116 = cat(_T_115, mitctl0) @[Cat.scala 29:58] + node _T_117 = bits(io.csr_mitctl1, 0, 0) @[dec_tlu_ctl.scala 3383:32] + node _T_118 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] + node _T_119 = cat(_T_118, mitctl1) @[Cat.scala 29:58] + node _T_120 = mux(_T_109, _T_110, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_121 = mux(_T_111, mitcnt1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_122 = mux(_T_112, mitb0, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_123 = mux(_T_113, mitb1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_124 = mux(_T_114, _T_116, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_125 = mux(_T_117, _T_119, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_126 = or(_T_120, _T_121) @[Mux.scala 27:72] + node _T_127 = or(_T_126, _T_122) @[Mux.scala 27:72] + node _T_128 = or(_T_127, _T_123) @[Mux.scala 27:72] + node _T_129 = or(_T_128, _T_124) @[Mux.scala 27:72] + node _T_130 = or(_T_129, _T_125) @[Mux.scala 27:72] + wire _T_131 : UInt<32> @[Mux.scala 27:72] + _T_131 <= _T_130 @[Mux.scala 27:72] + io.dec_timer_rddata_d <= _T_131 @[dec_tlu_ctl.scala 3377:33] + + module dec_decode_csr_read : + input clock : Clock + input reset : AsyncReset + output io : {flip dec_csr_rdaddr_d : UInt<12>, csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_meicpct : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}} + + node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1 = eq(_T, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_3 = eq(_T_2, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_5 = eq(_T_4, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_7 = eq(_T_6, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_9 = and(_T_1, _T_3) @[dec_tlu_ctl.scala 3173:198] + node _T_10 = and(_T_9, _T_5) @[dec_tlu_ctl.scala 3173:198] + node _T_11 = and(_T_10, _T_7) @[dec_tlu_ctl.scala 3173:198] + node _T_12 = and(_T_11, _T_8) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_misa <= _T_12 @[dec_tlu_ctl.scala 3175:57] + node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_17 = eq(_T_16, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_19 = and(_T_13, _T_15) @[dec_tlu_ctl.scala 3173:198] + node _T_20 = and(_T_19, _T_17) @[dec_tlu_ctl.scala 3173:198] + node _T_21 = and(_T_20, _T_18) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mvendorid <= _T_21 @[dec_tlu_ctl.scala 3176:57] + node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_27 = eq(_T_26, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_28 = and(_T_22, _T_24) @[dec_tlu_ctl.scala 3173:198] + node _T_29 = and(_T_28, _T_25) @[dec_tlu_ctl.scala 3173:198] + node _T_30 = and(_T_29, _T_27) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_marchid <= _T_30 @[dec_tlu_ctl.scala 3177:57] + node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_36 = and(_T_31, _T_33) @[dec_tlu_ctl.scala 3173:198] + node _T_37 = and(_T_36, _T_34) @[dec_tlu_ctl.scala 3173:198] + node _T_38 = and(_T_37, _T_35) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mimpid <= _T_38 @[dec_tlu_ctl.scala 3178:57] + node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_41 = eq(_T_40, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_43 = and(_T_39, _T_41) @[dec_tlu_ctl.scala 3173:198] + node _T_44 = and(_T_43, _T_42) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhartid <= _T_44 @[dec_tlu_ctl.scala 3179:57] + node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_46 = eq(_T_45, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_50 = eq(_T_49, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_52 = eq(_T_51, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_54 = eq(_T_53, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_55 = and(_T_46, _T_48) @[dec_tlu_ctl.scala 3173:198] + node _T_56 = and(_T_55, _T_50) @[dec_tlu_ctl.scala 3173:198] + node _T_57 = and(_T_56, _T_52) @[dec_tlu_ctl.scala 3173:198] + node _T_58 = and(_T_57, _T_54) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mstatus <= _T_58 @[dec_tlu_ctl.scala 3180:57] + node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_60 = eq(_T_59, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_62 = eq(_T_61, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_64 = eq(_T_63, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_67 = and(_T_60, _T_62) @[dec_tlu_ctl.scala 3173:198] + node _T_68 = and(_T_67, _T_64) @[dec_tlu_ctl.scala 3173:198] + node _T_69 = and(_T_68, _T_65) @[dec_tlu_ctl.scala 3173:198] + node _T_70 = and(_T_69, _T_66) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mtvec <= _T_70 @[dec_tlu_ctl.scala 3181:57] + node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_72 = eq(_T_71, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_75 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 3173:198] + node _T_76 = and(_T_75, _T_74) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mip <= _T_76 @[dec_tlu_ctl.scala 3182:65] + node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_78 = eq(_T_77, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_80 = eq(_T_79, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_85 = eq(_T_84, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_86 = and(_T_78, _T_80) @[dec_tlu_ctl.scala 3173:198] + node _T_87 = and(_T_86, _T_82) @[dec_tlu_ctl.scala 3173:198] + node _T_88 = and(_T_87, _T_83) @[dec_tlu_ctl.scala 3173:198] + node _T_89 = and(_T_88, _T_85) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mie <= _T_89 @[dec_tlu_ctl.scala 3183:65] + node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_94 = eq(_T_93, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_96 = eq(_T_95, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_100 = eq(_T_99, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_101 = and(_T_90, _T_92) @[dec_tlu_ctl.scala 3173:198] + node _T_102 = and(_T_101, _T_94) @[dec_tlu_ctl.scala 3173:198] + node _T_103 = and(_T_102, _T_96) @[dec_tlu_ctl.scala 3173:198] + node _T_104 = and(_T_103, _T_98) @[dec_tlu_ctl.scala 3173:198] + node _T_105 = and(_T_104, _T_100) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mcyclel <= _T_105 @[dec_tlu_ctl.scala 3184:57] + node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_108 = eq(_T_107, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_110 = eq(_T_109, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_112 = eq(_T_111, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_114 = eq(_T_113, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_116 = eq(_T_115, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_119 = and(_T_106, _T_108) @[dec_tlu_ctl.scala 3173:198] + node _T_120 = and(_T_119, _T_110) @[dec_tlu_ctl.scala 3173:198] + node _T_121 = and(_T_120, _T_112) @[dec_tlu_ctl.scala 3173:198] + node _T_122 = and(_T_121, _T_114) @[dec_tlu_ctl.scala 3173:198] + node _T_123 = and(_T_122, _T_116) @[dec_tlu_ctl.scala 3173:198] + node _T_124 = and(_T_123, _T_118) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mcycleh <= _T_124 @[dec_tlu_ctl.scala 3185:57] + node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_126 = eq(_T_125, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_128 = eq(_T_127, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_130 = eq(_T_129, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_134 = eq(_T_133, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_137 = eq(_T_136, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_138 = and(_T_126, _T_128) @[dec_tlu_ctl.scala 3173:198] + node _T_139 = and(_T_138, _T_130) @[dec_tlu_ctl.scala 3173:198] + node _T_140 = and(_T_139, _T_132) @[dec_tlu_ctl.scala 3173:198] + node _T_141 = and(_T_140, _T_134) @[dec_tlu_ctl.scala 3173:198] + node _T_142 = and(_T_141, _T_135) @[dec_tlu_ctl.scala 3173:198] + node _T_143 = and(_T_142, _T_137) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_minstretl <= _T_143 @[dec_tlu_ctl.scala 3186:57] + node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_145 = eq(_T_144, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_148 = eq(_T_147, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_152 = eq(_T_151, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_155 = eq(_T_154, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_156 = and(_T_145, _T_146) @[dec_tlu_ctl.scala 3173:198] + node _T_157 = and(_T_156, _T_148) @[dec_tlu_ctl.scala 3173:198] + node _T_158 = and(_T_157, _T_150) @[dec_tlu_ctl.scala 3173:198] + node _T_159 = and(_T_158, _T_152) @[dec_tlu_ctl.scala 3173:198] + node _T_160 = and(_T_159, _T_153) @[dec_tlu_ctl.scala 3173:198] + node _T_161 = and(_T_160, _T_155) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_minstreth <= _T_161 @[dec_tlu_ctl.scala 3187:57] + node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_163 = eq(_T_162, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_166 = eq(_T_165, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_170 = eq(_T_169, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_171 = and(_T_163, _T_164) @[dec_tlu_ctl.scala 3173:198] + node _T_172 = and(_T_171, _T_166) @[dec_tlu_ctl.scala 3173:198] + node _T_173 = and(_T_172, _T_168) @[dec_tlu_ctl.scala 3173:198] + node _T_174 = and(_T_173, _T_170) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mscratch <= _T_174 @[dec_tlu_ctl.scala 3188:57] + node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_181 = and(_T_176, _T_177) @[dec_tlu_ctl.scala 3173:198] + node _T_182 = and(_T_181, _T_179) @[dec_tlu_ctl.scala 3173:198] + node _T_183 = and(_T_182, _T_180) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mepc <= _T_183 @[dec_tlu_ctl.scala 3189:57] + node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_185 = eq(_T_184, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_189 = eq(_T_188, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_190 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 3173:198] + node _T_191 = and(_T_190, _T_187) @[dec_tlu_ctl.scala 3173:198] + node _T_192 = and(_T_191, _T_189) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mcause <= _T_192 @[dec_tlu_ctl.scala 3190:57] + node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_196 = and(_T_193, _T_194) @[dec_tlu_ctl.scala 3173:198] + node _T_197 = and(_T_196, _T_195) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mscause <= _T_197 @[dec_tlu_ctl.scala 3191:57] + node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_199 = eq(_T_198, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_203 = and(_T_199, _T_200) @[dec_tlu_ctl.scala 3173:198] + node _T_204 = and(_T_203, _T_201) @[dec_tlu_ctl.scala 3173:198] + node _T_205 = and(_T_204, _T_202) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mtval <= _T_205 @[dec_tlu_ctl.scala 3192:57] + node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_207 = eq(_T_206, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_210 = eq(_T_209, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_212 = eq(_T_211, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_214 = eq(_T_213, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_217 = and(_T_207, _T_208) @[dec_tlu_ctl.scala 3173:198] + node _T_218 = and(_T_217, _T_210) @[dec_tlu_ctl.scala 3173:198] + node _T_219 = and(_T_218, _T_212) @[dec_tlu_ctl.scala 3173:198] + node _T_220 = and(_T_219, _T_214) @[dec_tlu_ctl.scala 3173:198] + node _T_221 = and(_T_220, _T_216) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mrac <= _T_221 @[dec_tlu_ctl.scala 3193:57] + node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_224 = eq(_T_223, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_226 = eq(_T_225, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_229 = eq(_T_228, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_230 = and(_T_222, _T_224) @[dec_tlu_ctl.scala 3173:198] + node _T_231 = and(_T_230, _T_226) @[dec_tlu_ctl.scala 3173:198] + node _T_232 = and(_T_231, _T_227) @[dec_tlu_ctl.scala 3173:198] + node _T_233 = and(_T_232, _T_229) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_dmst <= _T_233 @[dec_tlu_ctl.scala 3194:57] + node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_237 = eq(_T_236, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_240 = and(_T_234, _T_235) @[dec_tlu_ctl.scala 3173:198] + node _T_241 = and(_T_240, _T_237) @[dec_tlu_ctl.scala 3173:198] + node _T_242 = and(_T_241, _T_239) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mdseac <= _T_242 @[dec_tlu_ctl.scala 3195:57] + node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_246 = and(_T_243, _T_244) @[dec_tlu_ctl.scala 3173:198] + node _T_247 = and(_T_246, _T_245) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_meihap <= _T_247 @[dec_tlu_ctl.scala 3196:57] + node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_255 = eq(_T_254, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_258 = and(_T_249, _T_250) @[dec_tlu_ctl.scala 3173:198] + node _T_259 = and(_T_258, _T_251) @[dec_tlu_ctl.scala 3173:198] + node _T_260 = and(_T_259, _T_253) @[dec_tlu_ctl.scala 3173:198] + node _T_261 = and(_T_260, _T_255) @[dec_tlu_ctl.scala 3173:198] + node _T_262 = and(_T_261, _T_257) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_meivt <= _T_262 @[dec_tlu_ctl.scala 3197:57] + node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_266 = eq(_T_265, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_268 = and(_T_263, _T_264) @[dec_tlu_ctl.scala 3173:198] + node _T_269 = and(_T_268, _T_266) @[dec_tlu_ctl.scala 3173:198] + node _T_270 = and(_T_269, _T_267) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_meipt <= _T_270 @[dec_tlu_ctl.scala 3198:57] + node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_274 = and(_T_271, _T_272) @[dec_tlu_ctl.scala 3173:198] + node _T_275 = and(_T_274, _T_273) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_meicurpl <= _T_275 @[dec_tlu_ctl.scala 3199:57] + node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_280 = and(_T_276, _T_277) @[dec_tlu_ctl.scala 3173:198] + node _T_281 = and(_T_280, _T_278) @[dec_tlu_ctl.scala 3173:198] + node _T_282 = and(_T_281, _T_279) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_meicidpl <= _T_282 @[dec_tlu_ctl.scala 3200:57] + node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_285 = eq(_T_284, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_289 = eq(_T_288, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_290 = and(_T_283, _T_285) @[dec_tlu_ctl.scala 3173:198] + node _T_291 = and(_T_290, _T_286) @[dec_tlu_ctl.scala 3173:198] + node _T_292 = and(_T_291, _T_287) @[dec_tlu_ctl.scala 3173:198] + node _T_293 = and(_T_292, _T_289) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_dcsr <= _T_293 @[dec_tlu_ctl.scala 3201:57] + node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_298 = eq(_T_297, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_299 = and(_T_294, _T_295) @[dec_tlu_ctl.scala 3173:198] + node _T_300 = and(_T_299, _T_296) @[dec_tlu_ctl.scala 3173:198] + node _T_301 = and(_T_300, _T_298) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mcgc <= _T_301 @[dec_tlu_ctl.scala 3202:57] + node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_308 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 3173:198] + node _T_309 = and(_T_308, _T_304) @[dec_tlu_ctl.scala 3173:198] + node _T_310 = and(_T_309, _T_306) @[dec_tlu_ctl.scala 3173:198] + node _T_311 = and(_T_310, _T_307) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mfdc <= _T_311 @[dec_tlu_ctl.scala 3203:57] + node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_318 = and(_T_312, _T_314) @[dec_tlu_ctl.scala 3173:198] + node _T_319 = and(_T_318, _T_315) @[dec_tlu_ctl.scala 3173:198] + node _T_320 = and(_T_319, _T_316) @[dec_tlu_ctl.scala 3173:198] + node _T_321 = and(_T_320, _T_317) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_dpc <= _T_321 @[dec_tlu_ctl.scala 3204:65] + node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_325 = eq(_T_324, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_330 = and(_T_322, _T_323) @[dec_tlu_ctl.scala 3173:198] + node _T_331 = and(_T_330, _T_325) @[dec_tlu_ctl.scala 3173:198] + node _T_332 = and(_T_331, _T_327) @[dec_tlu_ctl.scala 3173:198] + node _T_333 = and(_T_332, _T_329) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mtsel <= _T_333 @[dec_tlu_ctl.scala 3205:57] + node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_336 = eq(_T_335, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_340 = and(_T_334, _T_336) @[dec_tlu_ctl.scala 3173:198] + node _T_341 = and(_T_340, _T_338) @[dec_tlu_ctl.scala 3173:198] + node _T_342 = and(_T_341, _T_339) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mtdata1 <= _T_342 @[dec_tlu_ctl.scala 3206:57] + node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_348 = and(_T_343, _T_344) @[dec_tlu_ctl.scala 3173:198] + node _T_349 = and(_T_348, _T_346) @[dec_tlu_ctl.scala 3173:198] + node _T_350 = and(_T_349, _T_347) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mtdata2 <= _T_350 @[dec_tlu_ctl.scala 3207:57] + node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_355 = eq(_T_354, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_359 = eq(_T_358, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_361 = and(_T_351, _T_353) @[dec_tlu_ctl.scala 3173:198] + node _T_362 = and(_T_361, _T_355) @[dec_tlu_ctl.scala 3173:198] + node _T_363 = and(_T_362, _T_357) @[dec_tlu_ctl.scala 3173:198] + node _T_364 = and(_T_363, _T_359) @[dec_tlu_ctl.scala 3173:198] + node _T_365 = and(_T_364, _T_360) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpmc3 <= _T_365 @[dec_tlu_ctl.scala 3208:57] + node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_370 = eq(_T_369, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_372 = eq(_T_371, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_375 = eq(_T_374, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_377 = eq(_T_376, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_378 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 3173:198] + node _T_379 = and(_T_378, _T_370) @[dec_tlu_ctl.scala 3173:198] + node _T_380 = and(_T_379, _T_372) @[dec_tlu_ctl.scala 3173:198] + node _T_381 = and(_T_380, _T_373) @[dec_tlu_ctl.scala 3173:198] + node _T_382 = and(_T_381, _T_375) @[dec_tlu_ctl.scala 3173:198] + node _T_383 = and(_T_382, _T_377) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpmc4 <= _T_383 @[dec_tlu_ctl.scala 3209:57] + node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_388 = eq(_T_387, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_390 = eq(_T_389, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_394 = and(_T_384, _T_386) @[dec_tlu_ctl.scala 3173:198] + node _T_395 = and(_T_394, _T_388) @[dec_tlu_ctl.scala 3173:198] + node _T_396 = and(_T_395, _T_390) @[dec_tlu_ctl.scala 3173:198] + node _T_397 = and(_T_396, _T_392) @[dec_tlu_ctl.scala 3173:198] + node _T_398 = and(_T_397, _T_393) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpmc5 <= _T_398 @[dec_tlu_ctl.scala 3210:57] + node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_402 = eq(_T_401, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_404 = eq(_T_403, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_406 = eq(_T_405, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_410 = eq(_T_409, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_411 = and(_T_400, _T_402) @[dec_tlu_ctl.scala 3173:198] + node _T_412 = and(_T_411, _T_404) @[dec_tlu_ctl.scala 3173:198] + node _T_413 = and(_T_412, _T_406) @[dec_tlu_ctl.scala 3173:198] + node _T_414 = and(_T_413, _T_407) @[dec_tlu_ctl.scala 3173:198] + node _T_415 = and(_T_414, _T_408) @[dec_tlu_ctl.scala 3173:198] + node _T_416 = and(_T_415, _T_410) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpmc6 <= _T_416 @[dec_tlu_ctl.scala 3211:57] + node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_421 = eq(_T_420, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_426 = and(_T_417, _T_419) @[dec_tlu_ctl.scala 3173:198] + node _T_427 = and(_T_426, _T_421) @[dec_tlu_ctl.scala 3173:198] + node _T_428 = and(_T_427, _T_423) @[dec_tlu_ctl.scala 3173:198] + node _T_429 = and(_T_428, _T_424) @[dec_tlu_ctl.scala 3173:198] + node _T_430 = and(_T_429, _T_425) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpmc3h <= _T_430 @[dec_tlu_ctl.scala 3212:57] + node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_433 = eq(_T_432, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_440 = eq(_T_439, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_442 = eq(_T_441, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_443 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 3173:198] + node _T_444 = and(_T_443, _T_435) @[dec_tlu_ctl.scala 3173:198] + node _T_445 = and(_T_444, _T_437) @[dec_tlu_ctl.scala 3173:198] + node _T_446 = and(_T_445, _T_438) @[dec_tlu_ctl.scala 3173:198] + node _T_447 = and(_T_446, _T_440) @[dec_tlu_ctl.scala 3173:198] + node _T_448 = and(_T_447, _T_442) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpmc4h <= _T_448 @[dec_tlu_ctl.scala 3213:57] + node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_453 = eq(_T_452, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_458 = and(_T_449, _T_451) @[dec_tlu_ctl.scala 3173:198] + node _T_459 = and(_T_458, _T_453) @[dec_tlu_ctl.scala 3173:198] + node _T_460 = and(_T_459, _T_454) @[dec_tlu_ctl.scala 3173:198] + node _T_461 = and(_T_460, _T_456) @[dec_tlu_ctl.scala 3173:198] + node _T_462 = and(_T_461, _T_457) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpmc5h <= _T_462 @[dec_tlu_ctl.scala 3214:57] + node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_465 = eq(_T_464, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_473 = eq(_T_472, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_474 = and(_T_463, _T_465) @[dec_tlu_ctl.scala 3173:198] + node _T_475 = and(_T_474, _T_467) @[dec_tlu_ctl.scala 3173:198] + node _T_476 = and(_T_475, _T_469) @[dec_tlu_ctl.scala 3173:198] + node _T_477 = and(_T_476, _T_470) @[dec_tlu_ctl.scala 3173:198] + node _T_478 = and(_T_477, _T_471) @[dec_tlu_ctl.scala 3173:198] + node _T_479 = and(_T_478, _T_473) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpmc6h <= _T_479 @[dec_tlu_ctl.scala 3215:57] + node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_490 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 3173:198] + node _T_491 = and(_T_490, _T_484) @[dec_tlu_ctl.scala 3173:198] + node _T_492 = and(_T_491, _T_486) @[dec_tlu_ctl.scala 3173:198] + node _T_493 = and(_T_492, _T_488) @[dec_tlu_ctl.scala 3173:198] + node _T_494 = and(_T_493, _T_489) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpme3 <= _T_494 @[dec_tlu_ctl.scala 3216:57] + node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_499 = eq(_T_498, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_504 = eq(_T_503, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_505 = and(_T_495, _T_497) @[dec_tlu_ctl.scala 3173:198] + node _T_506 = and(_T_505, _T_499) @[dec_tlu_ctl.scala 3173:198] + node _T_507 = and(_T_506, _T_500) @[dec_tlu_ctl.scala 3173:198] + node _T_508 = and(_T_507, _T_502) @[dec_tlu_ctl.scala 3173:198] + node _T_509 = and(_T_508, _T_504) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpme4 <= _T_509 @[dec_tlu_ctl.scala 3217:57] + node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_512 = eq(_T_511, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_514 = eq(_T_513, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_517 = eq(_T_516, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_519 = and(_T_510, _T_512) @[dec_tlu_ctl.scala 3173:198] + node _T_520 = and(_T_519, _T_514) @[dec_tlu_ctl.scala 3173:198] + node _T_521 = and(_T_520, _T_515) @[dec_tlu_ctl.scala 3173:198] + node _T_522 = and(_T_521, _T_517) @[dec_tlu_ctl.scala 3173:198] + node _T_523 = and(_T_522, _T_518) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpme5 <= _T_523 @[dec_tlu_ctl.scala 3218:57] + node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_526 = eq(_T_525, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_528 = eq(_T_527, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_533 = and(_T_524, _T_526) @[dec_tlu_ctl.scala 3173:198] + node _T_534 = and(_T_533, _T_528) @[dec_tlu_ctl.scala 3173:198] + node _T_535 = and(_T_534, _T_529) @[dec_tlu_ctl.scala 3173:198] + node _T_536 = and(_T_535, _T_530) @[dec_tlu_ctl.scala 3173:198] + node _T_537 = and(_T_536, _T_532) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mhpme6 <= _T_537 @[dec_tlu_ctl.scala 3219:57] + node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_539 = eq(_T_538, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_542 = eq(_T_541, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_544 = eq(_T_543, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_546 = eq(_T_545, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_548 = eq(_T_547, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_549 = and(_T_539, _T_540) @[dec_tlu_ctl.scala 3173:198] + node _T_550 = and(_T_549, _T_542) @[dec_tlu_ctl.scala 3173:198] + node _T_551 = and(_T_550, _T_544) @[dec_tlu_ctl.scala 3173:198] + node _T_552 = and(_T_551, _T_546) @[dec_tlu_ctl.scala 3173:198] + node _T_553 = and(_T_552, _T_548) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mcountinhibit <= _T_553 @[dec_tlu_ctl.scala 3220:49] + node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_556 = eq(_T_555, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_561 = eq(_T_560, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_562 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 3173:198] + node _T_563 = and(_T_562, _T_557) @[dec_tlu_ctl.scala 3173:198] + node _T_564 = and(_T_563, _T_559) @[dec_tlu_ctl.scala 3173:198] + node _T_565 = and(_T_564, _T_561) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mitctl0 <= _T_565 @[dec_tlu_ctl.scala 3221:57] + node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_568 = eq(_T_567, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_572 = and(_T_566, _T_568) @[dec_tlu_ctl.scala 3173:198] + node _T_573 = and(_T_572, _T_569) @[dec_tlu_ctl.scala 3173:198] + node _T_574 = and(_T_573, _T_570) @[dec_tlu_ctl.scala 3173:198] + node _T_575 = and(_T_574, _T_571) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mitctl1 <= _T_575 @[dec_tlu_ctl.scala 3222:57] + node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_578 = eq(_T_577, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_581 = eq(_T_580, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_583 = and(_T_576, _T_578) @[dec_tlu_ctl.scala 3173:198] + node _T_584 = and(_T_583, _T_579) @[dec_tlu_ctl.scala 3173:198] + node _T_585 = and(_T_584, _T_581) @[dec_tlu_ctl.scala 3173:198] + node _T_586 = and(_T_585, _T_582) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mitb0 <= _T_586 @[dec_tlu_ctl.scala 3223:57] + node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_592 = eq(_T_591, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_593 = and(_T_587, _T_588) @[dec_tlu_ctl.scala 3173:198] + node _T_594 = and(_T_593, _T_589) @[dec_tlu_ctl.scala 3173:198] + node _T_595 = and(_T_594, _T_590) @[dec_tlu_ctl.scala 3173:198] + node _T_596 = and(_T_595, _T_592) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mitb1 <= _T_596 @[dec_tlu_ctl.scala 3224:57] + node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_599 = eq(_T_598, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_602 = eq(_T_601, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_605 = and(_T_597, _T_599) @[dec_tlu_ctl.scala 3173:198] + node _T_606 = and(_T_605, _T_600) @[dec_tlu_ctl.scala 3173:198] + node _T_607 = and(_T_606, _T_602) @[dec_tlu_ctl.scala 3173:198] + node _T_608 = and(_T_607, _T_604) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mitcnt0 <= _T_608 @[dec_tlu_ctl.scala 3225:57] + node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_612 = eq(_T_611, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_614 = and(_T_609, _T_610) @[dec_tlu_ctl.scala 3173:198] + node _T_615 = and(_T_614, _T_612) @[dec_tlu_ctl.scala 3173:198] + node _T_616 = and(_T_615, _T_613) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mitcnt1 <= _T_616 @[dec_tlu_ctl.scala 3226:57] + node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_619 = eq(_T_618, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_621 = eq(_T_620, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_624 = and(_T_617, _T_619) @[dec_tlu_ctl.scala 3173:198] + node _T_625 = and(_T_624, _T_621) @[dec_tlu_ctl.scala 3173:198] + node _T_626 = and(_T_625, _T_622) @[dec_tlu_ctl.scala 3173:198] + node _T_627 = and(_T_626, _T_623) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mpmc <= _T_627 @[dec_tlu_ctl.scala 3227:57] + node _T_628 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_630 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_631 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_632 = eq(_T_631, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_633 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 3173:198] + node _T_634 = and(_T_633, _T_630) @[dec_tlu_ctl.scala 3173:198] + node _T_635 = and(_T_634, _T_632) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_meicpct <= _T_635 @[dec_tlu_ctl.scala 3229:57] + node _T_636 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_637 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_638 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_639 = eq(_T_638, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_640 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_641 = eq(_T_640, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_642 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_643 = eq(_T_642, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_644 = and(_T_636, _T_637) @[dec_tlu_ctl.scala 3173:198] + node _T_645 = and(_T_644, _T_639) @[dec_tlu_ctl.scala 3173:198] + node _T_646 = and(_T_645, _T_641) @[dec_tlu_ctl.scala 3173:198] + node _T_647 = and(_T_646, _T_643) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_micect <= _T_647 @[dec_tlu_ctl.scala 3231:57] + node _T_648 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_649 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_650 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_651 = eq(_T_650, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_652 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_653 = and(_T_648, _T_649) @[dec_tlu_ctl.scala 3173:198] + node _T_654 = and(_T_653, _T_651) @[dec_tlu_ctl.scala 3173:198] + node _T_655 = and(_T_654, _T_652) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_miccmect <= _T_655 @[dec_tlu_ctl.scala 3232:57] + node _T_656 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_657 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_658 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_659 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_660 = eq(_T_659, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_661 = and(_T_656, _T_657) @[dec_tlu_ctl.scala 3173:198] + node _T_662 = and(_T_661, _T_658) @[dec_tlu_ctl.scala 3173:198] + node _T_663 = and(_T_662, _T_660) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mdccmect <= _T_663 @[dec_tlu_ctl.scala 3233:57] + node _T_664 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_665 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_666 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_667 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_668 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_669 = eq(_T_668, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_670 = and(_T_664, _T_665) @[dec_tlu_ctl.scala 3173:198] + node _T_671 = and(_T_670, _T_666) @[dec_tlu_ctl.scala 3173:198] + node _T_672 = and(_T_671, _T_667) @[dec_tlu_ctl.scala 3173:198] + node _T_673 = and(_T_672, _T_669) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mfdht <= _T_673 @[dec_tlu_ctl.scala 3234:57] + node _T_674 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_675 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_676 = eq(_T_675, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_677 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_678 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_679 = and(_T_674, _T_676) @[dec_tlu_ctl.scala 3173:198] + node _T_680 = and(_T_679, _T_677) @[dec_tlu_ctl.scala 3173:198] + node _T_681 = and(_T_680, _T_678) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_mfdhs <= _T_681 @[dec_tlu_ctl.scala 3235:57] + node _T_682 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_683 = eq(_T_682, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_684 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_685 = eq(_T_684, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_686 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_687 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_688 = eq(_T_687, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_689 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_690 = eq(_T_689, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_692 = eq(_T_691, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_693 = and(_T_683, _T_685) @[dec_tlu_ctl.scala 3173:198] + node _T_694 = and(_T_693, _T_686) @[dec_tlu_ctl.scala 3173:198] + node _T_695 = and(_T_694, _T_688) @[dec_tlu_ctl.scala 3173:198] + node _T_696 = and(_T_695, _T_690) @[dec_tlu_ctl.scala 3173:198] + node _T_697 = and(_T_696, _T_692) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_dicawics <= _T_697 @[dec_tlu_ctl.scala 3236:57] + node _T_698 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_699 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_701 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_702 = eq(_T_701, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_703 = and(_T_698, _T_699) @[dec_tlu_ctl.scala 3173:198] + node _T_704 = and(_T_703, _T_700) @[dec_tlu_ctl.scala 3173:198] + node _T_705 = and(_T_704, _T_702) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_dicad0h <= _T_705 @[dec_tlu_ctl.scala 3237:57] + node _T_706 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_707 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_708 = eq(_T_707, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_710 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_711 = eq(_T_710, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_712 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_713 = and(_T_706, _T_708) @[dec_tlu_ctl.scala 3173:198] + node _T_714 = and(_T_713, _T_709) @[dec_tlu_ctl.scala 3173:198] + node _T_715 = and(_T_714, _T_711) @[dec_tlu_ctl.scala 3173:198] + node _T_716 = and(_T_715, _T_712) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_dicad0 <= _T_716 @[dec_tlu_ctl.scala 3238:57] + node _T_717 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_718 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_719 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_720 = eq(_T_719, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_721 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_722 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_723 = eq(_T_722, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_724 = and(_T_717, _T_718) @[dec_tlu_ctl.scala 3173:198] + node _T_725 = and(_T_724, _T_720) @[dec_tlu_ctl.scala 3173:198] + node _T_726 = and(_T_725, _T_721) @[dec_tlu_ctl.scala 3173:198] + node _T_727 = and(_T_726, _T_723) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_dicad1 <= _T_727 @[dec_tlu_ctl.scala 3239:57] + node _T_728 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_729 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_730 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_731 = eq(_T_730, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_732 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_733 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_734 = and(_T_728, _T_729) @[dec_tlu_ctl.scala 3173:198] + node _T_735 = and(_T_734, _T_731) @[dec_tlu_ctl.scala 3173:198] + node _T_736 = and(_T_735, _T_732) @[dec_tlu_ctl.scala 3173:198] + node _T_737 = and(_T_736, _T_733) @[dec_tlu_ctl.scala 3173:198] + io.csr_pkt.csr_dicago <= _T_737 @[dec_tlu_ctl.scala 3240:57] + node _T_738 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_739 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_740 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_741 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_742 = eq(_T_741, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_743 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_744 = and(_T_738, _T_739) @[dec_tlu_ctl.scala 3173:198] + node _T_745 = and(_T_744, _T_740) @[dec_tlu_ctl.scala 3173:198] + node _T_746 = and(_T_745, _T_742) @[dec_tlu_ctl.scala 3173:198] + node _T_747 = and(_T_746, _T_743) @[dec_tlu_ctl.scala 3173:198] + node _T_748 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_749 = eq(_T_748, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_750 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_751 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_752 = eq(_T_751, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_753 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_754 = eq(_T_753, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_755 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_756 = eq(_T_755, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_757 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_758 = eq(_T_757, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_759 = and(_T_749, _T_750) @[dec_tlu_ctl.scala 3173:198] + node _T_760 = and(_T_759, _T_752) @[dec_tlu_ctl.scala 3173:198] + node _T_761 = and(_T_760, _T_754) @[dec_tlu_ctl.scala 3173:198] + node _T_762 = and(_T_761, _T_756) @[dec_tlu_ctl.scala 3173:198] + node _T_763 = and(_T_762, _T_758) @[dec_tlu_ctl.scala 3173:198] + node _T_764 = or(_T_747, _T_763) @[dec_tlu_ctl.scala 3241:81] + node _T_765 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_766 = eq(_T_765, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_767 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_768 = eq(_T_767, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_769 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_770 = eq(_T_769, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_771 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_773 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_774 = eq(_T_773, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_775 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_776 = and(_T_766, _T_768) @[dec_tlu_ctl.scala 3173:198] + node _T_777 = and(_T_776, _T_770) @[dec_tlu_ctl.scala 3173:198] + node _T_778 = and(_T_777, _T_772) @[dec_tlu_ctl.scala 3173:198] + node _T_779 = and(_T_778, _T_774) @[dec_tlu_ctl.scala 3173:198] + node _T_780 = and(_T_779, _T_775) @[dec_tlu_ctl.scala 3173:198] + node _T_781 = or(_T_764, _T_780) @[dec_tlu_ctl.scala 3241:121] + node _T_782 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_783 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_784 = eq(_T_783, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_785 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_786 = eq(_T_785, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_787 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_788 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_789 = eq(_T_788, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_790 = and(_T_782, _T_784) @[dec_tlu_ctl.scala 3173:198] + node _T_791 = and(_T_790, _T_786) @[dec_tlu_ctl.scala 3173:198] + node _T_792 = and(_T_791, _T_787) @[dec_tlu_ctl.scala 3173:198] + node _T_793 = and(_T_792, _T_789) @[dec_tlu_ctl.scala 3173:198] + node _T_794 = or(_T_781, _T_793) @[dec_tlu_ctl.scala 3241:155] + node _T_795 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_796 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_797 = eq(_T_796, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_798 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_799 = eq(_T_798, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_800 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_801 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_802 = eq(_T_801, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_803 = and(_T_795, _T_797) @[dec_tlu_ctl.scala 3173:198] + node _T_804 = and(_T_803, _T_799) @[dec_tlu_ctl.scala 3173:198] + node _T_805 = and(_T_804, _T_800) @[dec_tlu_ctl.scala 3173:198] + node _T_806 = and(_T_805, _T_802) @[dec_tlu_ctl.scala 3173:198] + node _T_807 = or(_T_794, _T_806) @[dec_tlu_ctl.scala 3242:49] + node _T_808 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_809 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_810 = eq(_T_809, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_811 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_813 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_814 = eq(_T_813, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_815 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_816 = eq(_T_815, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_817 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_818 = and(_T_808, _T_810) @[dec_tlu_ctl.scala 3173:198] + node _T_819 = and(_T_818, _T_812) @[dec_tlu_ctl.scala 3173:198] + node _T_820 = and(_T_819, _T_814) @[dec_tlu_ctl.scala 3173:198] + node _T_821 = and(_T_820, _T_816) @[dec_tlu_ctl.scala 3173:198] + node _T_822 = and(_T_821, _T_817) @[dec_tlu_ctl.scala 3173:198] + node _T_823 = or(_T_807, _T_822) @[dec_tlu_ctl.scala 3242:89] + io.csr_pkt.presync <= _T_823 @[dec_tlu_ctl.scala 3241:34] + node _T_824 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_825 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_826 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_827 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_828 = eq(_T_827, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_829 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_830 = and(_T_824, _T_825) @[dec_tlu_ctl.scala 3173:198] + node _T_831 = and(_T_830, _T_826) @[dec_tlu_ctl.scala 3173:198] + node _T_832 = and(_T_831, _T_828) @[dec_tlu_ctl.scala 3173:198] + node _T_833 = and(_T_832, _T_829) @[dec_tlu_ctl.scala 3173:198] + node _T_834 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_835 = eq(_T_834, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_836 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_837 = eq(_T_836, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_838 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_840 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_841 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_842 = and(_T_835, _T_837) @[dec_tlu_ctl.scala 3173:198] + node _T_843 = and(_T_842, _T_839) @[dec_tlu_ctl.scala 3173:198] + node _T_844 = and(_T_843, _T_840) @[dec_tlu_ctl.scala 3173:198] + node _T_845 = and(_T_844, _T_841) @[dec_tlu_ctl.scala 3173:198] + node _T_846 = or(_T_833, _T_845) @[dec_tlu_ctl.scala 3243:81] + node _T_847 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_848 = eq(_T_847, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_849 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_851 = eq(_T_850, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_853 = and(_T_848, _T_849) @[dec_tlu_ctl.scala 3173:198] + node _T_854 = and(_T_853, _T_851) @[dec_tlu_ctl.scala 3173:198] + node _T_855 = and(_T_854, _T_852) @[dec_tlu_ctl.scala 3173:198] + node _T_856 = or(_T_846, _T_855) @[dec_tlu_ctl.scala 3243:121] + node _T_857 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_858 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_859 = eq(_T_858, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_860 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_861 = eq(_T_860, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_862 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_863 = and(_T_857, _T_859) @[dec_tlu_ctl.scala 3173:198] + node _T_864 = and(_T_863, _T_861) @[dec_tlu_ctl.scala 3173:198] + node _T_865 = and(_T_864, _T_862) @[dec_tlu_ctl.scala 3173:198] + node _T_866 = or(_T_856, _T_865) @[dec_tlu_ctl.scala 3243:162] + node _T_867 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_868 = eq(_T_867, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_869 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_870 = eq(_T_869, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_871 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_872 = eq(_T_871, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_873 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_874 = eq(_T_873, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_875 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_876 = eq(_T_875, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_877 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_878 = eq(_T_877, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_879 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_880 = eq(_T_879, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_881 = and(_T_868, _T_870) @[dec_tlu_ctl.scala 3173:198] + node _T_882 = and(_T_881, _T_872) @[dec_tlu_ctl.scala 3173:198] + node _T_883 = and(_T_882, _T_874) @[dec_tlu_ctl.scala 3173:198] + node _T_884 = and(_T_883, _T_876) @[dec_tlu_ctl.scala 3173:198] + node _T_885 = and(_T_884, _T_878) @[dec_tlu_ctl.scala 3173:198] + node _T_886 = and(_T_885, _T_880) @[dec_tlu_ctl.scala 3173:198] + node _T_887 = or(_T_866, _T_886) @[dec_tlu_ctl.scala 3244:57] + node _T_888 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_889 = eq(_T_888, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_890 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_891 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_892 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_893 = eq(_T_892, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_894 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_896 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_897 = eq(_T_896, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_898 = and(_T_889, _T_890) @[dec_tlu_ctl.scala 3173:198] + node _T_899 = and(_T_898, _T_891) @[dec_tlu_ctl.scala 3173:198] + node _T_900 = and(_T_899, _T_893) @[dec_tlu_ctl.scala 3173:198] + node _T_901 = and(_T_900, _T_895) @[dec_tlu_ctl.scala 3173:198] + node _T_902 = and(_T_901, _T_897) @[dec_tlu_ctl.scala 3173:198] + node _T_903 = or(_T_887, _T_902) @[dec_tlu_ctl.scala 3244:97] + node _T_904 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_905 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_906 = eq(_T_905, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_907 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_908 = eq(_T_907, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_909 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_910 = eq(_T_909, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_911 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_912 = and(_T_904, _T_906) @[dec_tlu_ctl.scala 3173:198] + node _T_913 = and(_T_912, _T_908) @[dec_tlu_ctl.scala 3173:198] + node _T_914 = and(_T_913, _T_910) @[dec_tlu_ctl.scala 3173:198] + node _T_915 = and(_T_914, _T_911) @[dec_tlu_ctl.scala 3173:198] + node _T_916 = or(_T_903, _T_915) @[dec_tlu_ctl.scala 3244:130] + io.csr_pkt.postsync <= _T_916 @[dec_tlu_ctl.scala 3243:30] + node _T_917 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_918 = eq(_T_917, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_919 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_920 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_921 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_922 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_923 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_924 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_925 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_926 = eq(_T_925, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_927 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_928 = eq(_T_927, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_929 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_930 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_931 = eq(_T_930, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_932 = and(_T_918, _T_919) @[dec_tlu_ctl.scala 3173:198] + node _T_933 = and(_T_932, _T_920) @[dec_tlu_ctl.scala 3173:198] + node _T_934 = and(_T_933, _T_921) @[dec_tlu_ctl.scala 3173:198] + node _T_935 = and(_T_934, _T_922) @[dec_tlu_ctl.scala 3173:198] + node _T_936 = and(_T_935, _T_923) @[dec_tlu_ctl.scala 3173:198] + node _T_937 = and(_T_936, _T_924) @[dec_tlu_ctl.scala 3173:198] + node _T_938 = and(_T_937, _T_926) @[dec_tlu_ctl.scala 3173:198] + node _T_939 = and(_T_938, _T_928) @[dec_tlu_ctl.scala 3173:198] + node _T_940 = and(_T_939, _T_929) @[dec_tlu_ctl.scala 3173:198] + node _T_941 = and(_T_940, _T_931) @[dec_tlu_ctl.scala 3173:198] + node _T_942 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_943 = eq(_T_942, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_944 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_945 = eq(_T_944, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_946 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_947 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_948 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_950 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_951 = eq(_T_950, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_952 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_953 = eq(_T_952, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_954 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_955 = eq(_T_954, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_956 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_957 = eq(_T_956, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_958 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_959 = eq(_T_958, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_960 = and(_T_943, _T_945) @[dec_tlu_ctl.scala 3173:198] + node _T_961 = and(_T_960, _T_946) @[dec_tlu_ctl.scala 3173:198] + node _T_962 = and(_T_961, _T_947) @[dec_tlu_ctl.scala 3173:198] + node _T_963 = and(_T_962, _T_949) @[dec_tlu_ctl.scala 3173:198] + node _T_964 = and(_T_963, _T_951) @[dec_tlu_ctl.scala 3173:198] + node _T_965 = and(_T_964, _T_953) @[dec_tlu_ctl.scala 3173:198] + node _T_966 = and(_T_965, _T_955) @[dec_tlu_ctl.scala 3173:198] + node _T_967 = and(_T_966, _T_957) @[dec_tlu_ctl.scala 3173:198] + node _T_968 = and(_T_967, _T_959) @[dec_tlu_ctl.scala 3173:198] + node _T_969 = or(_T_941, _T_968) @[dec_tlu_ctl.scala 3246:81] + node _T_970 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_971 = eq(_T_970, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_972 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_973 = eq(_T_972, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_974 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_975 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_976 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_977 = eq(_T_976, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_978 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_979 = eq(_T_978, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_980 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_983 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_984 = eq(_T_983, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_985 = and(_T_971, _T_973) @[dec_tlu_ctl.scala 3173:198] + node _T_986 = and(_T_985, _T_974) @[dec_tlu_ctl.scala 3173:198] + node _T_987 = and(_T_986, _T_975) @[dec_tlu_ctl.scala 3173:198] + node _T_988 = and(_T_987, _T_977) @[dec_tlu_ctl.scala 3173:198] + node _T_989 = and(_T_988, _T_979) @[dec_tlu_ctl.scala 3173:198] + node _T_990 = and(_T_989, _T_980) @[dec_tlu_ctl.scala 3173:198] + node _T_991 = and(_T_990, _T_982) @[dec_tlu_ctl.scala 3173:198] + node _T_992 = and(_T_991, _T_984) @[dec_tlu_ctl.scala 3173:198] + node _T_993 = or(_T_969, _T_992) @[dec_tlu_ctl.scala 3246:129] + node _T_994 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_995 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_996 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_997 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_998 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_999 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1000 = eq(_T_999, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1001 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1003 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_1004 = eq(_T_1003, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1005 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_1006 = eq(_T_1005, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1007 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_1008 = eq(_T_1007, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_1009 = and(_T_994, _T_995) @[dec_tlu_ctl.scala 3173:198] + node _T_1010 = and(_T_1009, _T_996) @[dec_tlu_ctl.scala 3173:198] + node _T_1011 = and(_T_1010, _T_997) @[dec_tlu_ctl.scala 3173:198] + node _T_1012 = and(_T_1011, _T_998) @[dec_tlu_ctl.scala 3173:198] + node _T_1013 = and(_T_1012, _T_1000) @[dec_tlu_ctl.scala 3173:198] + node _T_1014 = and(_T_1013, _T_1002) @[dec_tlu_ctl.scala 3173:198] + node _T_1015 = and(_T_1014, _T_1004) @[dec_tlu_ctl.scala 3173:198] + node _T_1016 = and(_T_1015, _T_1006) @[dec_tlu_ctl.scala 3173:198] + node _T_1017 = and(_T_1016, _T_1008) @[dec_tlu_ctl.scala 3173:198] + node _T_1018 = or(_T_993, _T_1017) @[dec_tlu_ctl.scala 3247:73] + node _T_1019 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1020 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1021 = eq(_T_1020, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1022 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1023 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1024 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1026 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1028 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_1030 = and(_T_1019, _T_1021) @[dec_tlu_ctl.scala 3173:198] + node _T_1031 = and(_T_1030, _T_1022) @[dec_tlu_ctl.scala 3173:198] + node _T_1032 = and(_T_1031, _T_1023) @[dec_tlu_ctl.scala 3173:198] + node _T_1033 = and(_T_1032, _T_1025) @[dec_tlu_ctl.scala 3173:198] + node _T_1034 = and(_T_1033, _T_1027) @[dec_tlu_ctl.scala 3173:198] + node _T_1035 = and(_T_1034, _T_1029) @[dec_tlu_ctl.scala 3173:198] + node _T_1036 = or(_T_1018, _T_1035) @[dec_tlu_ctl.scala 3247:121] + node _T_1037 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1038 = eq(_T_1037, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1039 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_1040 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1041 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1042 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1043 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_1044 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_1045 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_1046 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_1047 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_1048 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_1049 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_1050 = and(_T_1038, _T_1039) @[dec_tlu_ctl.scala 3173:198] + node _T_1051 = and(_T_1050, _T_1040) @[dec_tlu_ctl.scala 3173:198] + node _T_1052 = and(_T_1051, _T_1041) @[dec_tlu_ctl.scala 3173:198] + node _T_1053 = and(_T_1052, _T_1042) @[dec_tlu_ctl.scala 3173:198] + node _T_1054 = and(_T_1053, _T_1043) @[dec_tlu_ctl.scala 3173:198] + node _T_1055 = and(_T_1054, _T_1044) @[dec_tlu_ctl.scala 3173:198] + node _T_1056 = and(_T_1055, _T_1045) @[dec_tlu_ctl.scala 3173:198] + node _T_1057 = and(_T_1056, _T_1046) @[dec_tlu_ctl.scala 3173:198] + node _T_1058 = and(_T_1057, _T_1047) @[dec_tlu_ctl.scala 3173:198] + node _T_1059 = and(_T_1058, _T_1048) @[dec_tlu_ctl.scala 3173:198] + node _T_1060 = and(_T_1059, _T_1049) @[dec_tlu_ctl.scala 3173:198] + node _T_1061 = or(_T_1036, _T_1060) @[dec_tlu_ctl.scala 3248:73] + node _T_1062 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1063 = eq(_T_1062, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1064 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_1065 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1066 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1067 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1068 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_1069 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_1070 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_1071 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_1072 = eq(_T_1071, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1073 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_1074 = eq(_T_1073, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1075 = and(_T_1063, _T_1064) @[dec_tlu_ctl.scala 3173:198] + node _T_1076 = and(_T_1075, _T_1065) @[dec_tlu_ctl.scala 3173:198] + node _T_1077 = and(_T_1076, _T_1066) @[dec_tlu_ctl.scala 3173:198] + node _T_1078 = and(_T_1077, _T_1067) @[dec_tlu_ctl.scala 3173:198] + node _T_1079 = and(_T_1078, _T_1068) @[dec_tlu_ctl.scala 3173:198] + node _T_1080 = and(_T_1079, _T_1069) @[dec_tlu_ctl.scala 3173:198] + node _T_1081 = and(_T_1080, _T_1070) @[dec_tlu_ctl.scala 3173:198] + node _T_1082 = and(_T_1081, _T_1072) @[dec_tlu_ctl.scala 3173:198] + node _T_1083 = and(_T_1082, _T_1074) @[dec_tlu_ctl.scala 3173:198] + node _T_1084 = or(_T_1061, _T_1083) @[dec_tlu_ctl.scala 3248:121] + node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1086 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1087 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1088 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_1089 = eq(_T_1088, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1090 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1091 = eq(_T_1090, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1094 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_1095 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_1096 = eq(_T_1095, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1097 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_1098 = eq(_T_1097, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1099 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_1100 = and(_T_1085, _T_1086) @[dec_tlu_ctl.scala 3173:198] + node _T_1101 = and(_T_1100, _T_1087) @[dec_tlu_ctl.scala 3173:198] + node _T_1102 = and(_T_1101, _T_1089) @[dec_tlu_ctl.scala 3173:198] + node _T_1103 = and(_T_1102, _T_1091) @[dec_tlu_ctl.scala 3173:198] + node _T_1104 = and(_T_1103, _T_1093) @[dec_tlu_ctl.scala 3173:198] + node _T_1105 = and(_T_1104, _T_1094) @[dec_tlu_ctl.scala 3173:198] + node _T_1106 = and(_T_1105, _T_1096) @[dec_tlu_ctl.scala 3173:198] + node _T_1107 = and(_T_1106, _T_1098) @[dec_tlu_ctl.scala 3173:198] + node _T_1108 = and(_T_1107, _T_1099) @[dec_tlu_ctl.scala 3173:198] + node _T_1109 = or(_T_1084, _T_1108) @[dec_tlu_ctl.scala 3249:73] + node _T_1110 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1111 = eq(_T_1110, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1112 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_1113 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1114 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1115 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1116 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1117 = eq(_T_1116, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1118 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_1119 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_1120 = eq(_T_1119, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1121 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_1122 = eq(_T_1121, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1123 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_1124 = eq(_T_1123, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1125 = and(_T_1111, _T_1112) @[dec_tlu_ctl.scala 3173:198] + node _T_1126 = and(_T_1125, _T_1113) @[dec_tlu_ctl.scala 3173:198] + node _T_1127 = and(_T_1126, _T_1114) @[dec_tlu_ctl.scala 3173:198] + node _T_1128 = and(_T_1127, _T_1115) @[dec_tlu_ctl.scala 3173:198] + node _T_1129 = and(_T_1128, _T_1117) @[dec_tlu_ctl.scala 3173:198] + node _T_1130 = and(_T_1129, _T_1118) @[dec_tlu_ctl.scala 3173:198] + node _T_1131 = and(_T_1130, _T_1120) @[dec_tlu_ctl.scala 3173:198] + node _T_1132 = and(_T_1131, _T_1122) @[dec_tlu_ctl.scala 3173:198] + node _T_1133 = and(_T_1132, _T_1124) @[dec_tlu_ctl.scala 3173:198] + node _T_1134 = or(_T_1109, _T_1133) @[dec_tlu_ctl.scala 3249:129] + node _T_1135 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1136 = eq(_T_1135, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1137 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1138 = eq(_T_1137, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1139 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1140 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1141 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_1142 = eq(_T_1141, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1143 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1144 = eq(_T_1143, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1145 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_1146 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_1147 = and(_T_1136, _T_1138) @[dec_tlu_ctl.scala 3173:198] + node _T_1148 = and(_T_1147, _T_1139) @[dec_tlu_ctl.scala 3173:198] + node _T_1149 = and(_T_1148, _T_1140) @[dec_tlu_ctl.scala 3173:198] + node _T_1150 = and(_T_1149, _T_1142) @[dec_tlu_ctl.scala 3173:198] + node _T_1151 = and(_T_1150, _T_1144) @[dec_tlu_ctl.scala 3173:198] + node _T_1152 = and(_T_1151, _T_1145) @[dec_tlu_ctl.scala 3173:198] + node _T_1153 = and(_T_1152, _T_1146) @[dec_tlu_ctl.scala 3173:198] + node _T_1154 = or(_T_1134, _T_1153) @[dec_tlu_ctl.scala 3250:73] + node _T_1155 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1156 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1157 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1158 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1160 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1162 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1163 = eq(_T_1162, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1164 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_1165 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_1166 = eq(_T_1165, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1167 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_1168 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_1169 = eq(_T_1168, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1170 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_1171 = eq(_T_1170, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_1172 = and(_T_1155, _T_1156) @[dec_tlu_ctl.scala 3173:198] + node _T_1173 = and(_T_1172, _T_1157) @[dec_tlu_ctl.scala 3173:198] + node _T_1174 = and(_T_1173, _T_1159) @[dec_tlu_ctl.scala 3173:198] + node _T_1175 = and(_T_1174, _T_1161) @[dec_tlu_ctl.scala 3173:198] + node _T_1176 = and(_T_1175, _T_1163) @[dec_tlu_ctl.scala 3173:198] + node _T_1177 = and(_T_1176, _T_1164) @[dec_tlu_ctl.scala 3173:198] + node _T_1178 = and(_T_1177, _T_1166) @[dec_tlu_ctl.scala 3173:198] + node _T_1179 = and(_T_1178, _T_1167) @[dec_tlu_ctl.scala 3173:198] + node _T_1180 = and(_T_1179, _T_1169) @[dec_tlu_ctl.scala 3173:198] + node _T_1181 = and(_T_1180, _T_1171) @[dec_tlu_ctl.scala 3173:198] + node _T_1182 = or(_T_1154, _T_1181) @[dec_tlu_ctl.scala 3250:129] + node _T_1183 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1185 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_1186 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1187 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1188 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1189 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_1190 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1191 = eq(_T_1190, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1192 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_1193 = eq(_T_1192, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1194 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_1195 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_1196 = and(_T_1184, _T_1185) @[dec_tlu_ctl.scala 3173:198] + node _T_1197 = and(_T_1196, _T_1186) @[dec_tlu_ctl.scala 3173:198] + node _T_1198 = and(_T_1197, _T_1187) @[dec_tlu_ctl.scala 3173:198] + node _T_1199 = and(_T_1198, _T_1188) @[dec_tlu_ctl.scala 3173:198] + node _T_1200 = and(_T_1199, _T_1189) @[dec_tlu_ctl.scala 3173:198] + node _T_1201 = and(_T_1200, _T_1191) @[dec_tlu_ctl.scala 3173:198] + node _T_1202 = and(_T_1201, _T_1193) @[dec_tlu_ctl.scala 3173:198] + node _T_1203 = and(_T_1202, _T_1194) @[dec_tlu_ctl.scala 3173:198] + node _T_1204 = and(_T_1203, _T_1195) @[dec_tlu_ctl.scala 3173:198] + node _T_1205 = or(_T_1182, _T_1204) @[dec_tlu_ctl.scala 3251:65] + node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_1216 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_1217 = eq(_T_1216, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1218 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_1219 = and(_T_1207, _T_1208) @[dec_tlu_ctl.scala 3173:198] + node _T_1220 = and(_T_1219, _T_1209) @[dec_tlu_ctl.scala 3173:198] + node _T_1221 = and(_T_1220, _T_1210) @[dec_tlu_ctl.scala 3173:198] + node _T_1222 = and(_T_1221, _T_1211) @[dec_tlu_ctl.scala 3173:198] + node _T_1223 = and(_T_1222, _T_1212) @[dec_tlu_ctl.scala 3173:198] + node _T_1224 = and(_T_1223, _T_1214) @[dec_tlu_ctl.scala 3173:198] + node _T_1225 = and(_T_1224, _T_1215) @[dec_tlu_ctl.scala 3173:198] + node _T_1226 = and(_T_1225, _T_1217) @[dec_tlu_ctl.scala 3173:198] + node _T_1227 = and(_T_1226, _T_1218) @[dec_tlu_ctl.scala 3173:198] + node _T_1228 = or(_T_1205, _T_1227) @[dec_tlu_ctl.scala 3251:121] + node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1230 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1231 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1232 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_1233 = eq(_T_1232, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1234 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1235 = eq(_T_1234, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_1242 = eq(_T_1241, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1243 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_1244 = and(_T_1229, _T_1230) @[dec_tlu_ctl.scala 3173:198] + node _T_1245 = and(_T_1244, _T_1231) @[dec_tlu_ctl.scala 3173:198] + node _T_1246 = and(_T_1245, _T_1233) @[dec_tlu_ctl.scala 3173:198] + node _T_1247 = and(_T_1246, _T_1235) @[dec_tlu_ctl.scala 3173:198] + node _T_1248 = and(_T_1247, _T_1237) @[dec_tlu_ctl.scala 3173:198] + node _T_1249 = and(_T_1248, _T_1238) @[dec_tlu_ctl.scala 3173:198] + node _T_1250 = and(_T_1249, _T_1240) @[dec_tlu_ctl.scala 3173:198] + node _T_1251 = and(_T_1250, _T_1242) @[dec_tlu_ctl.scala 3173:198] + node _T_1252 = and(_T_1251, _T_1243) @[dec_tlu_ctl.scala 3173:198] + node _T_1253 = or(_T_1228, _T_1252) @[dec_tlu_ctl.scala 3252:73] + node _T_1254 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1255 = eq(_T_1254, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1256 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1257 = eq(_T_1256, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1258 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1259 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1260 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_1261 = eq(_T_1260, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1262 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1264 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_1265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_1266 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106] + node _T_1267 = and(_T_1255, _T_1257) @[dec_tlu_ctl.scala 3173:198] + node _T_1268 = and(_T_1267, _T_1258) @[dec_tlu_ctl.scala 3173:198] + node _T_1269 = and(_T_1268, _T_1259) @[dec_tlu_ctl.scala 3173:198] + node _T_1270 = and(_T_1269, _T_1261) @[dec_tlu_ctl.scala 3173:198] + node _T_1271 = and(_T_1270, _T_1263) @[dec_tlu_ctl.scala 3173:198] + node _T_1272 = and(_T_1271, _T_1264) @[dec_tlu_ctl.scala 3173:198] + node _T_1273 = and(_T_1272, _T_1265) @[dec_tlu_ctl.scala 3173:198] + node _T_1274 = and(_T_1273, _T_1266) @[dec_tlu_ctl.scala 3173:198] + node _T_1275 = or(_T_1253, _T_1274) @[dec_tlu_ctl.scala 3252:129] + node _T_1276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1277 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1279 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1280 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1281 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1282 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1283 = eq(_T_1282, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1284 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_1285 = eq(_T_1284, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1286 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_1287 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_1288 = eq(_T_1287, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1289 = and(_T_1276, _T_1278) @[dec_tlu_ctl.scala 3173:198] + node _T_1290 = and(_T_1289, _T_1279) @[dec_tlu_ctl.scala 3173:198] + node _T_1291 = and(_T_1290, _T_1280) @[dec_tlu_ctl.scala 3173:198] + node _T_1292 = and(_T_1291, _T_1281) @[dec_tlu_ctl.scala 3173:198] + node _T_1293 = and(_T_1292, _T_1283) @[dec_tlu_ctl.scala 3173:198] + node _T_1294 = and(_T_1293, _T_1285) @[dec_tlu_ctl.scala 3173:198] + node _T_1295 = and(_T_1294, _T_1286) @[dec_tlu_ctl.scala 3173:198] + node _T_1296 = and(_T_1295, _T_1288) @[dec_tlu_ctl.scala 3173:198] + node _T_1297 = or(_T_1275, _T_1296) @[dec_tlu_ctl.scala 3253:73] + node _T_1298 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1299 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1300 = eq(_T_1299, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1301 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1302 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1303 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1304 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1305 = eq(_T_1304, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1306 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_1307 = eq(_T_1306, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1308 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_1309 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_1310 = eq(_T_1309, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1311 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_1313 = and(_T_1298, _T_1300) @[dec_tlu_ctl.scala 3173:198] + node _T_1314 = and(_T_1313, _T_1301) @[dec_tlu_ctl.scala 3173:198] + node _T_1315 = and(_T_1314, _T_1302) @[dec_tlu_ctl.scala 3173:198] + node _T_1316 = and(_T_1315, _T_1303) @[dec_tlu_ctl.scala 3173:198] + node _T_1317 = and(_T_1316, _T_1305) @[dec_tlu_ctl.scala 3173:198] + node _T_1318 = and(_T_1317, _T_1307) @[dec_tlu_ctl.scala 3173:198] + node _T_1319 = and(_T_1318, _T_1308) @[dec_tlu_ctl.scala 3173:198] + node _T_1320 = and(_T_1319, _T_1310) @[dec_tlu_ctl.scala 3173:198] + node _T_1321 = and(_T_1320, _T_1312) @[dec_tlu_ctl.scala 3173:198] + node _T_1322 = or(_T_1297, _T_1321) @[dec_tlu_ctl.scala 3253:129] + node _T_1323 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1324 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1326 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1327 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1328 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1329 = eq(_T_1328, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1330 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1331 = eq(_T_1330, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1332 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106] + node _T_1333 = and(_T_1323, _T_1325) @[dec_tlu_ctl.scala 3173:198] + node _T_1334 = and(_T_1333, _T_1326) @[dec_tlu_ctl.scala 3173:198] + node _T_1335 = and(_T_1334, _T_1327) @[dec_tlu_ctl.scala 3173:198] + node _T_1336 = and(_T_1335, _T_1329) @[dec_tlu_ctl.scala 3173:198] + node _T_1337 = and(_T_1336, _T_1331) @[dec_tlu_ctl.scala 3173:198] + node _T_1338 = and(_T_1337, _T_1332) @[dec_tlu_ctl.scala 3173:198] + node _T_1339 = or(_T_1322, _T_1338) @[dec_tlu_ctl.scala 3254:73] + node _T_1340 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1341 = eq(_T_1340, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1342 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_1343 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1344 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1345 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1346 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_1347 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1349 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_1350 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_1351 = eq(_T_1350, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1352 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_1353 = and(_T_1341, _T_1342) @[dec_tlu_ctl.scala 3173:198] + node _T_1354 = and(_T_1353, _T_1343) @[dec_tlu_ctl.scala 3173:198] + node _T_1355 = and(_T_1354, _T_1344) @[dec_tlu_ctl.scala 3173:198] + node _T_1356 = and(_T_1355, _T_1345) @[dec_tlu_ctl.scala 3173:198] + node _T_1357 = and(_T_1356, _T_1346) @[dec_tlu_ctl.scala 3173:198] + node _T_1358 = and(_T_1357, _T_1348) @[dec_tlu_ctl.scala 3173:198] + node _T_1359 = and(_T_1358, _T_1349) @[dec_tlu_ctl.scala 3173:198] + node _T_1360 = and(_T_1359, _T_1351) @[dec_tlu_ctl.scala 3173:198] + node _T_1361 = and(_T_1360, _T_1352) @[dec_tlu_ctl.scala 3173:198] + node _T_1362 = or(_T_1339, _T_1361) @[dec_tlu_ctl.scala 3254:129] + node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_1373 = eq(_T_1372, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1374 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_1375 = eq(_T_1374, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_1376 = and(_T_1364, _T_1365) @[dec_tlu_ctl.scala 3173:198] + node _T_1377 = and(_T_1376, _T_1366) @[dec_tlu_ctl.scala 3173:198] + node _T_1378 = and(_T_1377, _T_1367) @[dec_tlu_ctl.scala 3173:198] + node _T_1379 = and(_T_1378, _T_1368) @[dec_tlu_ctl.scala 3173:198] + node _T_1380 = and(_T_1379, _T_1369) @[dec_tlu_ctl.scala 3173:198] + node _T_1381 = and(_T_1380, _T_1371) @[dec_tlu_ctl.scala 3173:198] + node _T_1382 = and(_T_1381, _T_1373) @[dec_tlu_ctl.scala 3173:198] + node _T_1383 = and(_T_1382, _T_1375) @[dec_tlu_ctl.scala 3173:198] + node _T_1384 = or(_T_1362, _T_1383) @[dec_tlu_ctl.scala 3255:73] + node _T_1385 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1386 = eq(_T_1385, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1387 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_1388 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1389 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1390 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1391 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_1392 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1393 = eq(_T_1392, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1394 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_1395 = eq(_T_1394, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1396 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_1397 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1399 = and(_T_1386, _T_1387) @[dec_tlu_ctl.scala 3173:198] + node _T_1400 = and(_T_1399, _T_1388) @[dec_tlu_ctl.scala 3173:198] + node _T_1401 = and(_T_1400, _T_1389) @[dec_tlu_ctl.scala 3173:198] + node _T_1402 = and(_T_1401, _T_1390) @[dec_tlu_ctl.scala 3173:198] + node _T_1403 = and(_T_1402, _T_1391) @[dec_tlu_ctl.scala 3173:198] + node _T_1404 = and(_T_1403, _T_1393) @[dec_tlu_ctl.scala 3173:198] + node _T_1405 = and(_T_1404, _T_1395) @[dec_tlu_ctl.scala 3173:198] + node _T_1406 = and(_T_1405, _T_1396) @[dec_tlu_ctl.scala 3173:198] + node _T_1407 = and(_T_1406, _T_1398) @[dec_tlu_ctl.scala 3173:198] + node _T_1408 = or(_T_1384, _T_1407) @[dec_tlu_ctl.scala 3255:129] + node _T_1409 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1410 = eq(_T_1409, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1411 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106] + node _T_1412 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1413 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1414 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106] + node _T_1415 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1417 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_1418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_1419 = eq(_T_1418, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_1423 = eq(_T_1422, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1424 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_1425 = eq(_T_1424, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_1426 = and(_T_1410, _T_1411) @[dec_tlu_ctl.scala 3173:198] + node _T_1427 = and(_T_1426, _T_1412) @[dec_tlu_ctl.scala 3173:198] + node _T_1428 = and(_T_1427, _T_1413) @[dec_tlu_ctl.scala 3173:198] + node _T_1429 = and(_T_1428, _T_1414) @[dec_tlu_ctl.scala 3173:198] + node _T_1430 = and(_T_1429, _T_1416) @[dec_tlu_ctl.scala 3173:198] + node _T_1431 = and(_T_1430, _T_1417) @[dec_tlu_ctl.scala 3173:198] + node _T_1432 = and(_T_1431, _T_1419) @[dec_tlu_ctl.scala 3173:198] + node _T_1433 = and(_T_1432, _T_1421) @[dec_tlu_ctl.scala 3173:198] + node _T_1434 = and(_T_1433, _T_1423) @[dec_tlu_ctl.scala 3173:198] + node _T_1435 = and(_T_1434, _T_1425) @[dec_tlu_ctl.scala 3173:198] + node _T_1436 = or(_T_1408, _T_1435) @[dec_tlu_ctl.scala 3256:73] + node _T_1437 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1438 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1440 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1441 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1442 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1443 = eq(_T_1442, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1444 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1445 = eq(_T_1444, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1446 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106] + node _T_1447 = and(_T_1437, _T_1439) @[dec_tlu_ctl.scala 3173:198] + node _T_1448 = and(_T_1447, _T_1440) @[dec_tlu_ctl.scala 3173:198] + node _T_1449 = and(_T_1448, _T_1441) @[dec_tlu_ctl.scala 3173:198] + node _T_1450 = and(_T_1449, _T_1443) @[dec_tlu_ctl.scala 3173:198] + node _T_1451 = and(_T_1450, _T_1445) @[dec_tlu_ctl.scala 3173:198] + node _T_1452 = and(_T_1451, _T_1446) @[dec_tlu_ctl.scala 3173:198] + node _T_1453 = or(_T_1436, _T_1452) @[dec_tlu_ctl.scala 3256:121] + node _T_1454 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1455 = eq(_T_1454, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1456 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1457 = eq(_T_1456, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1458 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1459 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1460 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_1461 = eq(_T_1460, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1462 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106] + node _T_1463 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1464 = eq(_T_1463, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1465 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1467 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1469 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149] + node _T_1470 = eq(_T_1469, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1471 = and(_T_1455, _T_1457) @[dec_tlu_ctl.scala 3173:198] + node _T_1472 = and(_T_1471, _T_1458) @[dec_tlu_ctl.scala 3173:198] + node _T_1473 = and(_T_1472, _T_1459) @[dec_tlu_ctl.scala 3173:198] + node _T_1474 = and(_T_1473, _T_1461) @[dec_tlu_ctl.scala 3173:198] + node _T_1475 = and(_T_1474, _T_1462) @[dec_tlu_ctl.scala 3173:198] + node _T_1476 = and(_T_1475, _T_1464) @[dec_tlu_ctl.scala 3173:198] + node _T_1477 = and(_T_1476, _T_1466) @[dec_tlu_ctl.scala 3173:198] + node _T_1478 = and(_T_1477, _T_1468) @[dec_tlu_ctl.scala 3173:198] + node _T_1479 = and(_T_1478, _T_1470) @[dec_tlu_ctl.scala 3173:198] + node _T_1480 = or(_T_1453, _T_1479) @[dec_tlu_ctl.scala 3257:81] + node _T_1481 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1482 = eq(_T_1481, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1483 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1485 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1486 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1487 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_1488 = eq(_T_1487, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1489 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1490 = eq(_T_1489, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1491 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149] + node _T_1492 = eq(_T_1491, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1493 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149] + node _T_1494 = eq(_T_1493, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1495 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149] + node _T_1496 = eq(_T_1495, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1497 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185] + node _T_1498 = eq(_T_1497, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165] + node _T_1499 = and(_T_1482, _T_1484) @[dec_tlu_ctl.scala 3173:198] + node _T_1500 = and(_T_1499, _T_1485) @[dec_tlu_ctl.scala 3173:198] + node _T_1501 = and(_T_1500, _T_1486) @[dec_tlu_ctl.scala 3173:198] + node _T_1502 = and(_T_1501, _T_1488) @[dec_tlu_ctl.scala 3173:198] + node _T_1503 = and(_T_1502, _T_1490) @[dec_tlu_ctl.scala 3173:198] + node _T_1504 = and(_T_1503, _T_1492) @[dec_tlu_ctl.scala 3173:198] + node _T_1505 = and(_T_1504, _T_1494) @[dec_tlu_ctl.scala 3173:198] + node _T_1506 = and(_T_1505, _T_1496) @[dec_tlu_ctl.scala 3173:198] + node _T_1507 = and(_T_1506, _T_1498) @[dec_tlu_ctl.scala 3173:198] + node _T_1508 = or(_T_1480, _T_1507) @[dec_tlu_ctl.scala 3257:129] + node _T_1509 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1510 = eq(_T_1509, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1511 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1513 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1514 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1515 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_1516 = eq(_T_1515, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1517 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1518 = eq(_T_1517, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1519 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_1520 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_1521 = and(_T_1510, _T_1512) @[dec_tlu_ctl.scala 3173:198] + node _T_1522 = and(_T_1521, _T_1513) @[dec_tlu_ctl.scala 3173:198] + node _T_1523 = and(_T_1522, _T_1514) @[dec_tlu_ctl.scala 3173:198] + node _T_1524 = and(_T_1523, _T_1516) @[dec_tlu_ctl.scala 3173:198] + node _T_1525 = and(_T_1524, _T_1518) @[dec_tlu_ctl.scala 3173:198] + node _T_1526 = and(_T_1525, _T_1519) @[dec_tlu_ctl.scala 3173:198] + node _T_1527 = and(_T_1526, _T_1520) @[dec_tlu_ctl.scala 3173:198] + node _T_1528 = or(_T_1508, _T_1527) @[dec_tlu_ctl.scala 3258:65] + node _T_1529 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1530 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1531 = eq(_T_1530, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1532 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1533 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1534 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1536 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1537 = eq(_T_1536, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1538 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106] + node _T_1539 = and(_T_1529, _T_1531) @[dec_tlu_ctl.scala 3173:198] + node _T_1540 = and(_T_1539, _T_1532) @[dec_tlu_ctl.scala 3173:198] + node _T_1541 = and(_T_1540, _T_1533) @[dec_tlu_ctl.scala 3173:198] + node _T_1542 = and(_T_1541, _T_1535) @[dec_tlu_ctl.scala 3173:198] + node _T_1543 = and(_T_1542, _T_1537) @[dec_tlu_ctl.scala 3173:198] + node _T_1544 = and(_T_1543, _T_1538) @[dec_tlu_ctl.scala 3173:198] + node _T_1545 = or(_T_1528, _T_1544) @[dec_tlu_ctl.scala 3258:121] + node _T_1546 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149] + node _T_1547 = eq(_T_1546, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1548 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1549 = eq(_T_1548, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1550 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1551 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1552 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149] + node _T_1553 = eq(_T_1552, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1555 = eq(_T_1554, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1556 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106] + node _T_1557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_1558 = and(_T_1547, _T_1549) @[dec_tlu_ctl.scala 3173:198] + node _T_1559 = and(_T_1558, _T_1550) @[dec_tlu_ctl.scala 3173:198] + node _T_1560 = and(_T_1559, _T_1551) @[dec_tlu_ctl.scala 3173:198] + node _T_1561 = and(_T_1560, _T_1553) @[dec_tlu_ctl.scala 3173:198] + node _T_1562 = and(_T_1561, _T_1555) @[dec_tlu_ctl.scala 3173:198] + node _T_1563 = and(_T_1562, _T_1556) @[dec_tlu_ctl.scala 3173:198] + node _T_1564 = and(_T_1563, _T_1557) @[dec_tlu_ctl.scala 3173:198] + node _T_1565 = or(_T_1545, _T_1564) @[dec_tlu_ctl.scala 3259:81] + node _T_1566 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106] + node _T_1567 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149] + node _T_1568 = eq(_T_1567, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1569 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106] + node _T_1570 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106] + node _T_1571 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149] + node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1573 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149] + node _T_1574 = eq(_T_1573, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129] + node _T_1575 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106] + node _T_1576 = and(_T_1566, _T_1568) @[dec_tlu_ctl.scala 3173:198] + node _T_1577 = and(_T_1576, _T_1569) @[dec_tlu_ctl.scala 3173:198] + node _T_1578 = and(_T_1577, _T_1570) @[dec_tlu_ctl.scala 3173:198] + node _T_1579 = and(_T_1578, _T_1572) @[dec_tlu_ctl.scala 3173:198] + node _T_1580 = and(_T_1579, _T_1574) @[dec_tlu_ctl.scala 3173:198] + node _T_1581 = and(_T_1580, _T_1575) @[dec_tlu_ctl.scala 3173:198] + node _T_1582 = or(_T_1565, _T_1581) @[dec_tlu_ctl.scala 3259:137] + io.csr_pkt.legal <= _T_1582 @[dec_tlu_ctl.scala 3246:26] + + module dec_tlu_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}, flip free_clk : Clock, flip free_l2clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_tlu_core_empty : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_extint : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_trace_disable : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_picio_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip tlu_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}, flip tlu_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, flip tlu_mem : {flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, flip tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, flip lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, dec_pic : {flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip mexintpend : UInt<1>}} + + wire mtdata1_t : UInt<10>[4] @[dec_tlu_ctl.scala 162:67] + wire pause_expired_wb : UInt<1> + pause_expired_wb <= UInt<1>("h00") + wire take_nmi_r_d1 : UInt<1> + take_nmi_r_d1 <= UInt<1>("h00") + wire exc_or_int_valid_r_d1 : UInt<1> + exc_or_int_valid_r_d1 <= UInt<1>("h00") + wire interrupt_valid_r_d1 : UInt<1> + interrupt_valid_r_d1 <= UInt<1>("h00") + wire tlu_flush_lower_r : UInt<1> + tlu_flush_lower_r <= UInt<1>("h00") + wire synchronous_flush_r : UInt<1> + synchronous_flush_r <= UInt<1>("h00") + wire interrupt_valid_r : UInt<1> + interrupt_valid_r <= UInt<1>("h00") + wire take_nmi : UInt<1> + take_nmi <= UInt<1>("h00") + wire take_reset : UInt<1> + take_reset <= UInt<1>("h00") + wire take_int_timer1_int : UInt<1> + take_int_timer1_int <= UInt<1>("h00") + wire take_int_timer0_int : UInt<1> + take_int_timer0_int <= UInt<1>("h00") + wire take_timer_int : UInt<1> + take_timer_int <= UInt<1>("h00") + wire take_soft_int : UInt<1> + take_soft_int <= UInt<1>("h00") + wire take_ce_int : UInt<1> + take_ce_int <= UInt<1>("h00") + wire take_ext_int_start : UInt<1> + take_ext_int_start <= UInt<1>("h00") + wire ext_int_freeze : UInt<1> + ext_int_freeze <= UInt<1>("h00") + wire take_ext_int_start_d2 : UInt<1> + take_ext_int_start_d2 <= UInt<1>("h00") + wire take_ext_int_start_d3 : UInt<1> + take_ext_int_start_d3 <= UInt<1>("h00") + wire fast_int_meicpct : UInt<1> + fast_int_meicpct <= UInt<1>("h00") + wire ignore_ext_int_due_to_lsu_stall : UInt<1> + ignore_ext_int_due_to_lsu_stall <= UInt<1>("h00") + wire take_ext_int : UInt<1> + take_ext_int <= UInt<1>("h00") + wire internal_dbg_halt_timers : UInt<1> + internal_dbg_halt_timers <= UInt<1>("h00") + wire int_timer1_int_hold : UInt<1> + int_timer1_int_hold <= UInt<1>("h00") + wire int_timer0_int_hold : UInt<1> + int_timer0_int_hold <= UInt<1>("h00") + wire mhwakeup_ready : UInt<1> + mhwakeup_ready <= UInt<1>("h00") + wire ext_int_ready : UInt<1> + ext_int_ready <= UInt<1>("h00") + wire ce_int_ready : UInt<1> + ce_int_ready <= UInt<1>("h00") + wire soft_int_ready : UInt<1> + soft_int_ready <= UInt<1>("h00") + wire timer_int_ready : UInt<1> + timer_int_ready <= UInt<1>("h00") + wire ebreak_to_debug_mode_r_d1 : UInt<1> + ebreak_to_debug_mode_r_d1 <= UInt<1>("h00") + wire ebreak_to_debug_mode_r : UInt<1> + ebreak_to_debug_mode_r <= UInt<1>("h00") + wire inst_acc_r : UInt<1> + inst_acc_r <= UInt<1>("h00") + wire inst_acc_r_raw : UInt<1> + inst_acc_r_raw <= UInt<1>("h00") + wire iccm_sbecc_r : UInt<1> + iccm_sbecc_r <= UInt<1>("h00") + wire ic_perr_r : UInt<1> + ic_perr_r <= UInt<1>("h00") + wire fence_i_r : UInt<1> + fence_i_r <= UInt<1>("h00") + wire ebreak_r : UInt<1> + ebreak_r <= UInt<1>("h00") + wire ecall_r : UInt<1> + ecall_r <= UInt<1>("h00") + wire illegal_r : UInt<1> + illegal_r <= UInt<1>("h00") + wire mret_r : UInt<1> + mret_r <= UInt<1>("h00") + wire iccm_repair_state_ns : UInt<1> + iccm_repair_state_ns <= UInt<1>("h00") + wire rfpc_i0_r : UInt<1> + rfpc_i0_r <= UInt<1>("h00") + wire tlu_i0_kill_writeb_r : UInt<1> + tlu_i0_kill_writeb_r <= UInt<1>("h00") + wire lsu_exc_valid_r_d1 : UInt<1> + lsu_exc_valid_r_d1 <= UInt<1>("h00") + wire lsu_i0_exc_r_raw : UInt<1> + lsu_i0_exc_r_raw <= UInt<1>("h00") + wire mdseac_locked_f : UInt<1> + mdseac_locked_f <= UInt<1>("h00") + wire i_cpu_run_req_d1 : UInt<1> + i_cpu_run_req_d1 <= UInt<1>("h00") + wire cpu_run_ack : UInt<1> + cpu_run_ack <= UInt<1>("h00") + wire cpu_halt_status : UInt<1> + cpu_halt_status <= UInt<1>("h00") + wire cpu_halt_ack : UInt<1> + cpu_halt_ack <= UInt<1>("h00") + wire pmu_fw_tlu_halted : UInt<1> + pmu_fw_tlu_halted <= UInt<1>("h00") + wire internal_pmu_fw_halt_mode : UInt<1> + internal_pmu_fw_halt_mode <= UInt<1>("h00") + wire pmu_fw_halt_req_ns : UInt<1> + pmu_fw_halt_req_ns <= UInt<1>("h00") + wire pmu_fw_halt_req_f : UInt<1> + pmu_fw_halt_req_f <= UInt<1>("h00") + wire pmu_fw_tlu_halted_f : UInt<1> + pmu_fw_tlu_halted_f <= UInt<1>("h00") + wire int_timer0_int_hold_f : UInt<1> + int_timer0_int_hold_f <= UInt<1>("h00") + wire int_timer1_int_hold_f : UInt<1> + int_timer1_int_hold_f <= UInt<1>("h00") + wire trigger_hit_dmode_r : UInt<1> + trigger_hit_dmode_r <= UInt<1>("h00") + wire i0_trigger_hit_r : UInt<1> + i0_trigger_hit_r <= UInt<1>("h00") + wire pause_expired_r : UInt<1> + pause_expired_r <= UInt<1>("h00") + wire dec_tlu_pmu_fw_halted : UInt<1> + dec_tlu_pmu_fw_halted <= UInt<1>("h00") + wire dec_tlu_flush_noredir_r_d1 : UInt<1> + dec_tlu_flush_noredir_r_d1 <= UInt<1>("h00") + wire halt_taken_f : UInt<1> + halt_taken_f <= UInt<1>("h00") + wire lsu_idle_any_f : UInt<1> + lsu_idle_any_f <= UInt<1>("h00") + wire ifu_miss_state_idle_f : UInt<1> + ifu_miss_state_idle_f <= UInt<1>("h00") + wire dbg_tlu_halted_f : UInt<1> + dbg_tlu_halted_f <= UInt<1>("h00") + wire debug_halt_req_f : UInt<1> + debug_halt_req_f <= UInt<1>("h00") + wire debug_resume_req_f_raw : UInt<1> + debug_resume_req_f_raw <= UInt<1>("h00") + wire debug_resume_req_f : UInt<1> + debug_resume_req_f <= UInt<1>("h00") + wire trigger_hit_dmode_r_d1 : UInt<1> + trigger_hit_dmode_r_d1 <= UInt<1>("h00") + wire dcsr_single_step_done_f : UInt<1> + dcsr_single_step_done_f <= UInt<1>("h00") + wire debug_halt_req_d1 : UInt<1> + debug_halt_req_d1 <= UInt<1>("h00") + wire request_debug_mode_r_d1 : UInt<1> + request_debug_mode_r_d1 <= UInt<1>("h00") + wire request_debug_mode_done_f : UInt<1> + request_debug_mode_done_f <= UInt<1>("h00") + wire dcsr_single_step_running_f : UInt<1> + dcsr_single_step_running_f <= UInt<1>("h00") + wire dec_tlu_flush_pause_r_d1 : UInt<1> + dec_tlu_flush_pause_r_d1 <= UInt<1>("h00") + wire dbg_halt_req_held : UInt<1> + dbg_halt_req_held <= UInt<1>("h00") + wire debug_halt_req_ns : UInt<1> + debug_halt_req_ns <= UInt<1>("h00") + wire internal_dbg_halt_mode : UInt<1> + internal_dbg_halt_mode <= UInt<1>("h00") + wire core_empty : UInt<1> + core_empty <= UInt<1>("h00") + wire dbg_halt_req_final : UInt<1> + dbg_halt_req_final <= UInt<1>("h00") + wire debug_brkpt_status_ns : UInt<1> + debug_brkpt_status_ns <= UInt<1>("h00") + wire mpc_debug_halt_ack_ns : UInt<1> + mpc_debug_halt_ack_ns <= UInt<1>("h00") + wire mpc_debug_run_ack_ns : UInt<1> + mpc_debug_run_ack_ns <= UInt<1>("h00") + wire mpc_halt_state_ns : UInt<1> + mpc_halt_state_ns <= UInt<1>("h00") + wire mpc_run_state_ns : UInt<1> + mpc_run_state_ns <= UInt<1>("h00") + wire dbg_halt_state_ns : UInt<1> + dbg_halt_state_ns <= UInt<1>("h00") + wire dbg_run_state_ns : UInt<1> + dbg_run_state_ns <= UInt<1>("h00") + wire dbg_halt_state_f : UInt<1> + dbg_halt_state_f <= UInt<1>("h00") + wire mpc_halt_state_f : UInt<1> + mpc_halt_state_f <= UInt<1>("h00") + wire nmi_int_detected : UInt<1> + nmi_int_detected <= UInt<1>("h00") + wire nmi_lsu_load_type : UInt<1> + nmi_lsu_load_type <= UInt<1>("h00") + wire nmi_lsu_store_type : UInt<1> + nmi_lsu_store_type <= UInt<1>("h00") + wire reset_delayed : UInt<1> + reset_delayed <= UInt<1>("h00") + wire debug_mode_status : UInt<1> + debug_mode_status <= UInt<1>("h00") + wire e5_valid : UInt<1> + e5_valid <= UInt<1>("h00") + wire ic_perr_r_d1 : UInt<1> + ic_perr_r_d1 <= UInt<1>("h00") + wire iccm_sbecc_r_d1 : UInt<1> + iccm_sbecc_r_d1 <= UInt<1>("h00") + wire npc_r : UInt<31> + npc_r <= UInt<1>("h00") + wire npc_r_d1 : UInt<31> + npc_r_d1 <= UInt<1>("h00") + wire mie_ns : UInt<6> + mie_ns <= UInt<1>("h00") + wire mepc : UInt<31> + mepc <= UInt<1>("h00") + wire mdseac_locked_ns : UInt<1> + mdseac_locked_ns <= UInt<1>("h00") + wire force_halt : UInt<1> + force_halt <= UInt<1>("h00") + wire dpc : UInt<31> + dpc <= UInt<1>("h00") + wire mstatus_mie_ns : UInt<1> + mstatus_mie_ns <= UInt<1>("h00") + wire dec_csr_wen_r_mod : UInt<1> + dec_csr_wen_r_mod <= UInt<1>("h00") + wire fw_halt_req : UInt<1> + fw_halt_req <= UInt<1>("h00") + wire mstatus : UInt<2> + mstatus <= UInt<1>("h00") + wire dcsr : UInt<16> + dcsr <= UInt<1>("h00") + wire mtvec : UInt<31> + mtvec <= UInt<1>("h00") + wire mip : UInt<6> + mip <= UInt<1>("h00") + wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_meicpct : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[dec_tlu_ctl.scala 278:47] + wire dec_tlu_mpc_halted_only_ns : UInt<1> + dec_tlu_mpc_halted_only_ns <= UInt<1>("h00") + node _T = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 281:39] + node _T_1 = and(_T, mpc_halt_state_f) @[dec_tlu_ctl.scala 281:57] + dec_tlu_mpc_halted_only_ns <= _T_1 @[dec_tlu_ctl.scala 281:36] + inst int_exc of int_exc @[dec_tlu_ctl.scala 282:29] + int_exc.clock <= clock + int_exc.reset <= reset + inst csr of csr_tlu @[dec_tlu_ctl.scala 283:23] + csr.clock <= clock + csr.reset <= reset + inst int_timers of dec_timer_ctl @[dec_tlu_ctl.scala 284:30] + int_timers.clock <= clock + int_timers.reset <= reset + int_timers.io.free_l2clk <= io.free_l2clk @[dec_tlu_ctl.scala 285:65] + int_timers.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 286:57] + int_timers.io.dec_csr_wen_r_mod <= dec_csr_wen_r_mod @[dec_tlu_ctl.scala 287:49] + int_timers.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 289:49] + int_timers.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 290:49] + int_timers.io.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 291:57] + int_timers.io.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 292:57] + int_timers.io.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 293:57] + int_timers.io.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 294:57] + int_timers.io.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 295:57] + int_timers.io.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 296:57] + int_timers.io.dec_pause_state <= io.dec_pause_state @[dec_tlu_ctl.scala 297:49] + int_timers.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 298:49] + int_timers.io.internal_dbg_halt_timers <= internal_dbg_halt_timers @[dec_tlu_ctl.scala 299:47] + node _T_2 = cat(io.i_cpu_run_req, io.mpc_debug_halt_req) @[Cat.scala 29:58] + node _T_3 = cat(_T_2, io.mpc_debug_run_req) @[Cat.scala 29:58] + node _T_4 = cat(io.soft_int, io.i_cpu_halt_req) @[Cat.scala 29:58] + node _T_5 = cat(io.nmi_int, io.timer_int) @[Cat.scala 29:58] + node _T_6 = cat(_T_5, _T_4) @[Cat.scala 29:58] + node _T_7 = cat(_T_6, _T_3) @[Cat.scala 29:58] + reg _T_8 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 37:81] + _T_8 <= _T_7 @[lib.scala 37:81] + reg syncro_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 37:58] + syncro_ff <= _T_8 @[lib.scala 37:58] + node nmi_int_sync = bits(syncro_ff, 6, 6) @[dec_tlu_ctl.scala 311:75] + node timer_int_sync = bits(syncro_ff, 5, 5) @[dec_tlu_ctl.scala 312:67] + node soft_int_sync = bits(syncro_ff, 4, 4) @[dec_tlu_ctl.scala 313:67] + node i_cpu_halt_req_sync = bits(syncro_ff, 3, 3) @[dec_tlu_ctl.scala 314:59] + node i_cpu_run_req_sync = bits(syncro_ff, 2, 2) @[dec_tlu_ctl.scala 315:59] + node mpc_debug_halt_req_sync_raw = bits(syncro_ff, 1, 1) @[dec_tlu_ctl.scala 316:51] + node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[dec_tlu_ctl.scala 317:59] + node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 320:59] + node _T_10 = bits(_T_9, 0, 0) @[dec_tlu_ctl.scala 320:75] + int_timers.io.csr_wr_clk <= clock @[dec_tlu_ctl.scala 321:52] + node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[dec_tlu_ctl.scala 325:35] + node _T_11 = or(debug_mode_status, i_cpu_run_req_d1) @[dec_tlu_ctl.scala 326:55] + node _T_12 = or(_T_11, interrupt_valid_r) @[dec_tlu_ctl.scala 326:74] + node _T_13 = or(_T_12, interrupt_valid_r_d1) @[dec_tlu_ctl.scala 326:94] + node _T_14 = or(_T_13, reset_delayed) @[dec_tlu_ctl.scala 326:117] + node _T_15 = or(_T_14, pause_expired_r) @[dec_tlu_ctl.scala 326:133] + node _T_16 = or(_T_15, pause_expired_wb) @[dec_tlu_ctl.scala 326:151] + node _T_17 = or(_T_16, ic_perr_r) @[dec_tlu_ctl.scala 326:170] + node _T_18 = or(_T_17, iccm_sbecc_r) @[dec_tlu_ctl.scala 326:183] + node flush_clkvalid = or(_T_18, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 326:199] + node _T_19 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 329:50] + node _T_20 = bits(_T_19, 0, 0) @[dec_tlu_ctl.scala 329:66] + node _T_21 = or(e4e5_valid, flush_clkvalid) @[dec_tlu_ctl.scala 330:54] + node _T_22 = bits(_T_21, 0, 0) @[dec_tlu_ctl.scala 330:72] + wire ifu_ic_error_start_f : UInt<1> + ifu_ic_error_start_f <= UInt<1>("h00") + node _T_23 = xor(io.tlu_mem.ifu_ic_error_start, ifu_ic_error_start_f) @[lib.scala 470:21] + node _T_24 = orr(_T_23) @[lib.scala 470:29] + reg _T_25 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_24 : @[Reg.scala 28:19] + _T_25 <= io.tlu_mem.ifu_ic_error_start @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ifu_ic_error_start_f <= _T_25 @[lib.scala 473:16] + wire ifu_iccm_rd_ecc_single_err_f : UInt<1> + ifu_iccm_rd_ecc_single_err_f <= UInt<1>("h00") + node _T_26 = xor(io.tlu_mem.ifu_iccm_rd_ecc_single_err, ifu_iccm_rd_ecc_single_err_f) @[lib.scala 470:21] + node _T_27 = orr(_T_26) @[lib.scala 470:29] + reg _T_28 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_27 : @[Reg.scala 28:19] + _T_28 <= io.tlu_mem.ifu_iccm_rd_ecc_single_err @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ifu_iccm_rd_ecc_single_err_f <= _T_28 @[lib.scala 473:16] + wire iccm_repair_state_d1 : UInt + iccm_repair_state_d1 <= UInt<1>("h00") + node _T_29 = xor(iccm_repair_state_ns, iccm_repair_state_d1) @[lib.scala 448:21] + node _T_30 = orr(_T_29) @[lib.scala 448:29] + reg _T_31 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_30 : @[Reg.scala 28:19] + _T_31 <= iccm_repair_state_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + iccm_repair_state_d1 <= _T_31 @[lib.scala 451:16] + wire _T_32 : UInt + _T_32 <= UInt<1>("h00") + node _T_33 = xor(io.dec_tlu_i0_valid_r, _T_32) @[lib.scala 448:21] + node _T_34 = orr(_T_33) @[lib.scala 448:29] + reg _T_35 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_34 : @[Reg.scala 28:19] + _T_35 <= io.dec_tlu_i0_valid_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_32 <= _T_35 @[lib.scala 451:16] + e5_valid <= _T_32 @[dec_tlu_ctl.scala 338:75] + wire _T_36 : UInt + _T_36 <= UInt<1>("h00") + node _T_37 = xor(internal_dbg_halt_mode, _T_36) @[lib.scala 448:21] + node _T_38 = orr(_T_37) @[lib.scala 448:29] + reg _T_39 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_38 : @[Reg.scala 28:19] + _T_39 <= internal_dbg_halt_mode @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_36 <= _T_39 @[lib.scala 451:16] + debug_mode_status <= _T_36 @[dec_tlu_ctl.scala 339:51] + wire lsu_pmu_load_external_r : UInt<1> + lsu_pmu_load_external_r <= UInt<1>("h00") + node _T_40 = xor(io.lsu_tlu.lsu_pmu_load_external_m, lsu_pmu_load_external_r) @[lib.scala 470:21] + node _T_41 = orr(_T_40) @[lib.scala 470:29] + reg _T_42 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_41 : @[Reg.scala 28:19] + _T_42 <= io.lsu_tlu.lsu_pmu_load_external_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + lsu_pmu_load_external_r <= _T_42 @[lib.scala 473:16] + wire lsu_pmu_store_external_r : UInt<1> + lsu_pmu_store_external_r <= UInt<1>("h00") + node _T_43 = xor(io.lsu_tlu.lsu_pmu_store_external_m, lsu_pmu_store_external_r) @[lib.scala 470:21] + node _T_44 = orr(_T_43) @[lib.scala 470:29] + reg _T_45 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_44 : @[Reg.scala 28:19] + _T_45 <= io.lsu_tlu.lsu_pmu_store_external_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + lsu_pmu_store_external_r <= _T_45 @[lib.scala 473:16] + wire tlu_flush_lower_r_d1 : UInt + tlu_flush_lower_r_d1 <= UInt<1>("h00") + node _T_46 = xor(tlu_flush_lower_r, tlu_flush_lower_r_d1) @[lib.scala 448:21] + node _T_47 = orr(_T_46) @[lib.scala 448:29] + reg _T_48 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_47 : @[Reg.scala 28:19] + _T_48 <= tlu_flush_lower_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + tlu_flush_lower_r_d1 <= _T_48 @[lib.scala 451:16] + wire _T_49 : UInt + _T_49 <= UInt<1>("h00") + node _T_50 = xor(tlu_i0_kill_writeb_r, _T_49) @[lib.scala 448:21] + node _T_51 = orr(_T_50) @[lib.scala 448:29] + reg _T_52 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_51 : @[Reg.scala 28:19] + _T_52 <= tlu_i0_kill_writeb_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_49 <= _T_52 @[lib.scala 451:16] + io.dec_tlu_i0_kill_writeb_wb <= _T_49 @[dec_tlu_ctl.scala 343:41] + wire internal_dbg_halt_mode_f2 : UInt + internal_dbg_halt_mode_f2 <= UInt<1>("h00") + node _T_53 = xor(debug_mode_status, internal_dbg_halt_mode_f2) @[lib.scala 448:21] + node _T_54 = orr(_T_53) @[lib.scala 448:29] + reg _T_55 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_54 : @[Reg.scala 28:19] + _T_55 <= debug_mode_status @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + internal_dbg_halt_mode_f2 <= _T_55 @[lib.scala 451:16] + wire _T_56 : UInt + _T_56 <= UInt<1>("h00") + node _T_57 = xor(force_halt, _T_56) @[lib.scala 448:21] + node _T_58 = orr(_T_57) @[lib.scala 448:29] + reg _T_59 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_58 : @[Reg.scala 28:19] + _T_59 <= force_halt @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_56 <= _T_59 @[lib.scala 451:16] + io.tlu_mem.dec_tlu_force_halt <= _T_56 @[dec_tlu_ctl.scala 345:41] + io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 349:41] + wire nmi_int_delayed : UInt<1> + nmi_int_delayed <= UInt<1>("h00") + node _T_60 = xor(nmi_int_sync, nmi_int_delayed) @[lib.scala 470:21] + node _T_61 = orr(_T_60) @[lib.scala 470:29] + reg _T_62 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_61 : @[Reg.scala 28:19] + _T_62 <= nmi_int_sync @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + nmi_int_delayed <= _T_62 @[lib.scala 473:16] + wire nmi_int_detected_f : UInt + nmi_int_detected_f <= UInt<1>("h00") + node _T_63 = xor(nmi_int_detected, nmi_int_detected_f) @[lib.scala 448:21] + node _T_64 = orr(_T_63) @[lib.scala 448:29] + reg _T_65 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_64 : @[Reg.scala 28:19] + _T_65 <= nmi_int_detected @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + nmi_int_detected_f <= _T_65 @[lib.scala 451:16] + wire nmi_lsu_load_type_f : UInt + nmi_lsu_load_type_f <= UInt<1>("h00") + node _T_66 = xor(nmi_lsu_load_type, nmi_lsu_load_type_f) @[lib.scala 448:21] + node _T_67 = orr(_T_66) @[lib.scala 448:29] + reg _T_68 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_67 : @[Reg.scala 28:19] + _T_68 <= nmi_lsu_load_type @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + nmi_lsu_load_type_f <= _T_68 @[lib.scala 451:16] + wire nmi_lsu_store_type_f : UInt + nmi_lsu_store_type_f <= UInt<1>("h00") + node _T_69 = xor(nmi_lsu_store_type, nmi_lsu_store_type_f) @[lib.scala 448:21] + node _T_70 = orr(_T_69) @[lib.scala 448:29] + reg _T_71 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_70 : @[Reg.scala 28:19] + _T_71 <= nmi_lsu_store_type @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + nmi_lsu_store_type_f <= _T_71 @[lib.scala 451:16] + wire nmi_fir_type : UInt<1> + nmi_fir_type <= UInt<1>("h00") + node _T_72 = not(mdseac_locked_f) @[dec_tlu_ctl.scala 357:32] + node _T_73 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 357:96] + node _T_74 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 357:49] + node _T_75 = not(nmi_fir_type) @[dec_tlu_ctl.scala 357:146] + node nmi_lsu_detected = and(_T_74, _T_75) @[dec_tlu_ctl.scala 357:144] + node _T_76 = not(nmi_int_delayed) @[dec_tlu_ctl.scala 360:45] + node _T_77 = and(nmi_int_sync, _T_76) @[dec_tlu_ctl.scala 360:43] + node _T_78 = or(_T_77, nmi_lsu_detected) @[dec_tlu_ctl.scala 360:63] + node _T_79 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 360:106] + node _T_80 = and(nmi_int_detected_f, _T_79) @[dec_tlu_ctl.scala 360:104] + node _T_81 = or(_T_78, _T_80) @[dec_tlu_ctl.scala 360:82] + node _T_82 = or(_T_81, nmi_fir_type) @[dec_tlu_ctl.scala 360:122] + nmi_int_detected <= _T_82 @[dec_tlu_ctl.scala 360:26] + node _T_83 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 362:49] + node _T_84 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 362:121] + node _T_85 = and(nmi_int_detected_f, _T_84) @[dec_tlu_ctl.scala 362:119] + node _T_86 = not(_T_85) @[dec_tlu_ctl.scala 362:98] + node _T_87 = and(_T_83, _T_86) @[dec_tlu_ctl.scala 362:95] + node _T_88 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 362:164] + node _T_89 = and(nmi_lsu_load_type_f, _T_88) @[dec_tlu_ctl.scala 362:162] + node _T_90 = or(_T_87, _T_89) @[dec_tlu_ctl.scala 362:138] + nmi_lsu_load_type <= _T_90 @[dec_tlu_ctl.scala 362:28] + node _T_91 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 363:49] + node _T_92 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 363:121] + node _T_93 = and(nmi_int_detected_f, _T_92) @[dec_tlu_ctl.scala 363:119] + node _T_94 = not(_T_93) @[dec_tlu_ctl.scala 363:98] + node _T_95 = and(_T_91, _T_94) @[dec_tlu_ctl.scala 363:96] + node _T_96 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 363:164] + node _T_97 = and(nmi_lsu_store_type_f, _T_96) @[dec_tlu_ctl.scala 363:162] + node _T_98 = or(_T_95, _T_97) @[dec_tlu_ctl.scala 363:138] + nmi_lsu_store_type <= _T_98 @[dec_tlu_ctl.scala 363:28] + node _T_99 = not(nmi_int_detected_f) @[dec_tlu_ctl.scala 365:25] + node _T_100 = and(_T_99, csr.io.take_ext_int_start_d3) @[dec_tlu_ctl.scala 365:45] + node _T_101 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 365:95] + node _T_102 = and(_T_100, _T_101) @[dec_tlu_ctl.scala 365:76] + nmi_fir_type <= _T_102 @[dec_tlu_ctl.scala 365:22] + wire reset_detect : UInt + reset_detect <= UInt<1>("h00") + node _T_103 = xor(UInt<1>("h01"), reset_detect) @[lib.scala 448:21] + node _T_104 = orr(_T_103) @[lib.scala 448:29] + reg _T_105 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_104 : @[Reg.scala 28:19] + _T_105 <= UInt<1>("h01") @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reset_detect <= _T_105 @[lib.scala 451:16] + wire reset_detected : UInt + reset_detected <= UInt<1>("h00") + node _T_106 = xor(reset_detect, reset_detected) @[lib.scala 448:21] + node _T_107 = orr(_T_106) @[lib.scala 448:29] + reg _T_108 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_107 : @[Reg.scala 28:19] + _T_108 <= reset_detect @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reset_detected <= _T_108 @[lib.scala 451:16] + node _T_109 = xor(reset_detect, reset_detected) @[dec_tlu_ctl.scala 369:64] + reset_delayed <= _T_109 @[dec_tlu_ctl.scala 369:49] + node _T_110 = eq(csr.io.ext_int_freeze_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 376:69] + node mpc_debug_halt_req_sync = and(mpc_debug_halt_req_sync_raw, _T_110) @[dec_tlu_ctl.scala 376:67] + wire mpc_debug_halt_req_sync_f : UInt<1> + mpc_debug_halt_req_sync_f <= UInt<1>("h00") + node _T_111 = xor(mpc_debug_halt_req_sync, mpc_debug_halt_req_sync_f) @[lib.scala 470:21] + node _T_112 = orr(_T_111) @[lib.scala 470:29] + reg _T_113 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_112 : @[Reg.scala 28:19] + _T_113 <= mpc_debug_halt_req_sync @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mpc_debug_halt_req_sync_f <= _T_113 @[lib.scala 473:16] + wire mpc_debug_run_req_sync_f : UInt<1> + mpc_debug_run_req_sync_f <= UInt<1>("h00") + node _T_114 = xor(mpc_debug_run_req_sync, mpc_debug_run_req_sync_f) @[lib.scala 470:21] + node _T_115 = orr(_T_114) @[lib.scala 470:29] + reg _T_116 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_115 : @[Reg.scala 28:19] + _T_116 <= mpc_debug_run_req_sync @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mpc_debug_run_req_sync_f <= _T_116 @[lib.scala 473:16] + wire _T_117 : UInt + _T_117 <= UInt<1>("h00") + node _T_118 = xor(mpc_halt_state_ns, _T_117) @[lib.scala 448:21] + node _T_119 = orr(_T_118) @[lib.scala 448:29] + reg _T_120 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_119 : @[Reg.scala 28:19] + _T_120 <= mpc_halt_state_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_117 <= _T_120 @[lib.scala 451:16] + mpc_halt_state_f <= _T_117 @[dec_tlu_ctl.scala 379:62] + wire mpc_run_state_f : UInt + mpc_run_state_f <= UInt<1>("h00") + node _T_121 = xor(mpc_run_state_ns, mpc_run_state_f) @[lib.scala 448:21] + node _T_122 = orr(_T_121) @[lib.scala 448:29] + reg _T_123 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_122 : @[Reg.scala 28:19] + _T_123 <= mpc_run_state_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mpc_run_state_f <= _T_123 @[lib.scala 451:16] + wire debug_brkpt_status_f : UInt + debug_brkpt_status_f <= UInt<1>("h00") + node _T_124 = xor(debug_brkpt_status_ns, debug_brkpt_status_f) @[lib.scala 448:21] + node _T_125 = orr(_T_124) @[lib.scala 448:29] + reg _T_126 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_125 : @[Reg.scala 28:19] + _T_126 <= debug_brkpt_status_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + debug_brkpt_status_f <= _T_126 @[lib.scala 451:16] + wire mpc_debug_halt_ack_f : UInt + mpc_debug_halt_ack_f <= UInt<1>("h00") + node _T_127 = xor(mpc_debug_halt_ack_ns, mpc_debug_halt_ack_f) @[lib.scala 448:21] + node _T_128 = orr(_T_127) @[lib.scala 448:29] + reg _T_129 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_128 : @[Reg.scala 28:19] + _T_129 <= mpc_debug_halt_ack_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mpc_debug_halt_ack_f <= _T_129 @[lib.scala 451:16] + wire mpc_debug_run_ack_f : UInt + mpc_debug_run_ack_f <= UInt<1>("h00") + node _T_130 = xor(mpc_debug_run_ack_ns, mpc_debug_run_ack_f) @[lib.scala 448:21] + node _T_131 = orr(_T_130) @[lib.scala 448:29] + reg _T_132 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_131 : @[Reg.scala 28:19] + _T_132 <= mpc_debug_run_ack_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mpc_debug_run_ack_f <= _T_132 @[lib.scala 451:16] + wire _T_133 : UInt + _T_133 <= UInt<1>("h00") + node _T_134 = xor(dbg_halt_state_ns, _T_133) @[lib.scala 448:21] + node _T_135 = orr(_T_134) @[lib.scala 448:29] + reg _T_136 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_135 : @[Reg.scala 28:19] + _T_136 <= dbg_halt_state_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_133 <= _T_136 @[lib.scala 451:16] + dbg_halt_state_f <= _T_133 @[dec_tlu_ctl.scala 384:62] + wire dbg_run_state_f : UInt + dbg_run_state_f <= UInt<1>("h00") + node _T_137 = xor(dbg_run_state_ns, dbg_run_state_f) @[lib.scala 448:21] + node _T_138 = orr(_T_137) @[lib.scala 448:29] + reg _T_139 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_138 : @[Reg.scala 28:19] + _T_139 <= dbg_run_state_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dbg_run_state_f <= _T_139 @[lib.scala 451:16] + wire _T_140 : UInt + _T_140 <= UInt<1>("h00") + node _T_141 = xor(dec_tlu_mpc_halted_only_ns, _T_140) @[lib.scala 448:21] + node _T_142 = orr(_T_141) @[lib.scala 448:29] + reg _T_143 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_142 : @[Reg.scala 28:19] + _T_143 <= dec_tlu_mpc_halted_only_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_140 <= _T_143 @[lib.scala 451:16] + io.dec_tlu_mpc_halted_only <= _T_140 @[dec_tlu_ctl.scala 386:42] + node _T_144 = not(mpc_debug_halt_req_sync_f) @[dec_tlu_ctl.scala 390:71] + node mpc_debug_halt_req_sync_pulse = and(mpc_debug_halt_req_sync, _T_144) @[dec_tlu_ctl.scala 390:69] + node _T_145 = not(mpc_debug_run_req_sync_f) @[dec_tlu_ctl.scala 391:70] + node mpc_debug_run_req_sync_pulse = and(mpc_debug_run_req_sync, _T_145) @[dec_tlu_ctl.scala 391:68] + node _T_146 = or(mpc_halt_state_f, mpc_debug_halt_req_sync_pulse) @[dec_tlu_ctl.scala 393:48] + node _T_147 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 393:99] + node _T_148 = and(reset_delayed, _T_147) @[dec_tlu_ctl.scala 393:97] + node _T_149 = or(_T_146, _T_148) @[dec_tlu_ctl.scala 393:80] + node _T_150 = not(mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 393:125] + node _T_151 = and(_T_149, _T_150) @[dec_tlu_ctl.scala 393:123] + mpc_halt_state_ns <= _T_151 @[dec_tlu_ctl.scala 393:27] + node _T_152 = not(mpc_debug_run_ack_f) @[dec_tlu_ctl.scala 394:80] + node _T_153 = and(mpc_debug_run_req_sync_pulse, _T_152) @[dec_tlu_ctl.scala 394:78] + node _T_154 = or(mpc_run_state_f, _T_153) @[dec_tlu_ctl.scala 394:46] + node _T_155 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 394:133] + node _T_156 = and(debug_mode_status, _T_155) @[dec_tlu_ctl.scala 394:131] + node _T_157 = and(_T_154, _T_156) @[dec_tlu_ctl.scala 394:103] + mpc_run_state_ns <= _T_157 @[dec_tlu_ctl.scala 394:26] + node _T_158 = or(dbg_halt_req_final, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 397:70] + node _T_159 = or(_T_158, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 397:96] + node _T_160 = or(_T_159, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 397:121] + node _T_161 = or(dbg_halt_state_f, _T_160) @[dec_tlu_ctl.scala 397:48] + node _T_162 = not(io.dbg_resume_req) @[dec_tlu_ctl.scala 397:153] + node _T_163 = and(_T_161, _T_162) @[dec_tlu_ctl.scala 397:151] + dbg_halt_state_ns <= _T_163 @[dec_tlu_ctl.scala 397:27] + node _T_164 = or(dbg_run_state_f, io.dbg_resume_req) @[dec_tlu_ctl.scala 398:46] + node _T_165 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 398:97] + node _T_166 = and(debug_mode_status, _T_165) @[dec_tlu_ctl.scala 398:95] + node _T_167 = and(_T_164, _T_166) @[dec_tlu_ctl.scala 398:67] + dbg_run_state_ns <= _T_167 @[dec_tlu_ctl.scala 398:26] + node _T_168 = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 401:39] + node _T_169 = and(_T_168, mpc_halt_state_f) @[dec_tlu_ctl.scala 401:57] + dec_tlu_mpc_halted_only_ns <= _T_169 @[dec_tlu_ctl.scala 401:36] + node debug_brkpt_valid = or(ebreak_to_debug_mode_r_d1, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 404:59] + node _T_170 = or(debug_brkpt_valid, debug_brkpt_status_f) @[dec_tlu_ctl.scala 405:53] + node _T_171 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 405:105] + node _T_172 = and(internal_dbg_halt_mode, _T_171) @[dec_tlu_ctl.scala 405:103] + node _T_173 = and(_T_170, _T_172) @[dec_tlu_ctl.scala 405:77] + debug_brkpt_status_ns <= _T_173 @[dec_tlu_ctl.scala 405:31] + node _T_174 = and(mpc_halt_state_f, debug_mode_status) @[dec_tlu_ctl.scala 408:51] + node _T_175 = and(_T_174, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 408:78] + node _T_176 = and(_T_175, core_empty) @[dec_tlu_ctl.scala 408:104] + mpc_debug_halt_ack_ns <= _T_176 @[dec_tlu_ctl.scala 408:31] + node _T_177 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 409:59] + node _T_178 = and(mpc_debug_run_req_sync, _T_177) @[dec_tlu_ctl.scala 409:57] + node _T_179 = not(mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 409:80] + node _T_180 = and(_T_178, _T_179) @[dec_tlu_ctl.scala 409:78] + node _T_181 = and(mpc_debug_run_ack_f, mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 409:129] + node _T_182 = or(_T_180, _T_181) @[dec_tlu_ctl.scala 409:106] + mpc_debug_run_ack_ns <= _T_182 @[dec_tlu_ctl.scala 409:30] + io.mpc_debug_halt_ack <= mpc_debug_halt_ack_f @[dec_tlu_ctl.scala 412:31] + io.mpc_debug_run_ack <= mpc_debug_run_ack_f @[dec_tlu_ctl.scala 413:31] + io.debug_brkpt_status <= debug_brkpt_status_f @[dec_tlu_ctl.scala 414:31] + node _T_183 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 417:53] + node dbg_halt_req_held_ns = and(_T_183, csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 417:74] + node _T_184 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 418:48] + node _T_185 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 418:71] + node _T_186 = and(_T_184, _T_185) @[dec_tlu_ctl.scala 418:69] + dbg_halt_req_final <= _T_186 @[dec_tlu_ctl.scala 418:28] + node _T_187 = or(dbg_halt_req_final, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 421:50] + node _T_188 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 421:95] + node _T_189 = and(reset_delayed, _T_188) @[dec_tlu_ctl.scala 421:93] + node _T_190 = or(_T_187, _T_189) @[dec_tlu_ctl.scala 421:76] + node _T_191 = not(debug_mode_status) @[dec_tlu_ctl.scala 421:121] + node _T_192 = and(_T_190, _T_191) @[dec_tlu_ctl.scala 421:119] + node _T_193 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 421:149] + node debug_halt_req = and(_T_192, _T_193) @[dec_tlu_ctl.scala 421:147] + node _T_194 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 423:32] + node _T_195 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 423:75] + node _T_196 = and(mpc_run_state_ns, _T_195) @[dec_tlu_ctl.scala 423:73] + node _T_197 = not(mpc_halt_state_ns) @[dec_tlu_ctl.scala 423:117] + node _T_198 = and(dbg_run_state_ns, _T_197) @[dec_tlu_ctl.scala 423:115] + node _T_199 = or(_T_196, _T_198) @[dec_tlu_ctl.scala 423:95] + node debug_resume_req = and(_T_194, _T_199) @[dec_tlu_ctl.scala 423:52] + node _T_200 = or(debug_halt_req_f, pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 428:43] + node _T_201 = not(synchronous_flush_r) @[dec_tlu_ctl.scala 428:66] + node _T_202 = and(_T_200, _T_201) @[dec_tlu_ctl.scala 428:64] + node _T_203 = not(mret_r) @[dec_tlu_ctl.scala 428:89] + node _T_204 = and(_T_202, _T_203) @[dec_tlu_ctl.scala 428:87] + node _T_205 = not(halt_taken_f) @[dec_tlu_ctl.scala 428:99] + node _T_206 = and(_T_204, _T_205) @[dec_tlu_ctl.scala 428:97] + node _T_207 = not(dec_tlu_flush_noredir_r_d1) @[dec_tlu_ctl.scala 428:115] + node _T_208 = and(_T_206, _T_207) @[dec_tlu_ctl.scala 428:113] + node _T_209 = not(take_reset) @[dec_tlu_ctl.scala 428:145] + node take_halt = and(_T_208, _T_209) @[dec_tlu_ctl.scala 428:143] + node _T_210 = eq(dec_tlu_flush_pause_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 431:56] + node _T_211 = and(dec_tlu_flush_noredir_r_d1, _T_210) @[dec_tlu_ctl.scala 431:54] + node _T_212 = eq(csr.io.take_ext_int_start_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 431:84] + node _T_213 = and(_T_211, _T_212) @[dec_tlu_ctl.scala 431:82] + node _T_214 = eq(dbg_tlu_halted_f, UInt<1>("h00")) @[dec_tlu_ctl.scala 431:133] + node _T_215 = and(halt_taken_f, _T_214) @[dec_tlu_ctl.scala 431:131] + node _T_216 = eq(pmu_fw_tlu_halted_f, UInt<1>("h00")) @[dec_tlu_ctl.scala 431:153] + node _T_217 = and(_T_215, _T_216) @[dec_tlu_ctl.scala 431:151] + node _T_218 = eq(interrupt_valid_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 431:176] + node _T_219 = and(_T_217, _T_218) @[dec_tlu_ctl.scala 431:174] + node halt_taken = or(_T_213, _T_219) @[dec_tlu_ctl.scala 431:115] + node _T_220 = and(io.lsu_idle_any, lsu_idle_any_f) @[dec_tlu_ctl.scala 435:53] + node _T_221 = and(_T_220, io.tlu_mem.ifu_miss_state_idle) @[dec_tlu_ctl.scala 435:70] + node _T_222 = and(_T_221, ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 435:103] + node _T_223 = not(debug_halt_req) @[dec_tlu_ctl.scala 435:129] + node _T_224 = and(_T_222, _T_223) @[dec_tlu_ctl.scala 435:127] + node _T_225 = not(debug_halt_req_d1) @[dec_tlu_ctl.scala 435:147] + node _T_226 = and(_T_224, _T_225) @[dec_tlu_ctl.scala 435:145] + node _T_227 = not(io.dec_div_active) @[dec_tlu_ctl.scala 435:168] + node _T_228 = and(_T_226, _T_227) @[dec_tlu_ctl.scala 435:166] + node _T_229 = or(force_halt, _T_228) @[dec_tlu_ctl.scala 435:34] + core_empty <= _T_229 @[dec_tlu_ctl.scala 435:20] + io.dec_tlu_core_empty <= core_empty @[dec_tlu_ctl.scala 436:31] + node _T_230 = not(debug_mode_status) @[dec_tlu_ctl.scala 441:37] + node _T_231 = and(_T_230, debug_halt_req) @[dec_tlu_ctl.scala 441:63] + node _T_232 = or(_T_231, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 441:81] + node _T_233 = or(_T_232, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 441:107] + node enter_debug_halt_req = or(_T_233, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 441:132] + node _T_234 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 444:111] + node _T_235 = not(_T_234) @[dec_tlu_ctl.scala 444:106] + node _T_236 = and(debug_resume_req_f, _T_235) @[dec_tlu_ctl.scala 444:104] + node _T_237 = not(_T_236) @[dec_tlu_ctl.scala 444:83] + node _T_238 = and(debug_mode_status, _T_237) @[dec_tlu_ctl.scala 444:81] + node _T_239 = or(debug_halt_req_ns, _T_238) @[dec_tlu_ctl.scala 444:53] + internal_dbg_halt_mode <= _T_239 @[dec_tlu_ctl.scala 444:32] + node _T_240 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 447:67] + node allow_dbg_halt_csr_write = and(debug_mode_status, _T_240) @[dec_tlu_ctl.scala 447:65] + node _T_241 = and(debug_halt_req_f, core_empty) @[dec_tlu_ctl.scala 452:48] + node _T_242 = and(_T_241, halt_taken) @[dec_tlu_ctl.scala 452:61] + node _T_243 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 452:97] + node _T_244 = and(dbg_tlu_halted_f, _T_243) @[dec_tlu_ctl.scala 452:95] + node dbg_tlu_halted = or(_T_242, _T_244) @[dec_tlu_ctl.scala 452:75] + node _T_245 = not(dbg_tlu_halted) @[dec_tlu_ctl.scala 454:73] + node _T_246 = and(debug_halt_req_f, _T_245) @[dec_tlu_ctl.scala 454:71] + node _T_247 = or(enter_debug_halt_req, _T_246) @[dec_tlu_ctl.scala 454:51] + debug_halt_req_ns <= _T_247 @[dec_tlu_ctl.scala 454:27] + node _T_248 = and(debug_resume_req_f, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 455:49] + node resume_ack_ns = and(_T_248, dbg_run_state_ns) @[dec_tlu_ctl.scala 455:68] + node _T_249 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 457:61] + node _T_250 = and(io.dec_tlu_i0_valid_r, _T_249) @[dec_tlu_ctl.scala 457:59] + node _T_251 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 457:90] + node _T_252 = and(_T_250, _T_251) @[dec_tlu_ctl.scala 457:84] + node _T_253 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 457:104] + node dcsr_single_step_done = and(_T_252, _T_253) @[dec_tlu_ctl.scala 457:102] + node _T_254 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 459:66] + node _T_255 = and(debug_resume_req_f, _T_254) @[dec_tlu_ctl.scala 459:60] + node _T_256 = not(dcsr_single_step_done_f) @[dec_tlu_ctl.scala 459:111] + node _T_257 = and(dcsr_single_step_running_f, _T_256) @[dec_tlu_ctl.scala 459:109] + node dcsr_single_step_running = or(_T_255, _T_257) @[dec_tlu_ctl.scala 459:79] + node dbg_cmd_done_ns = and(io.dec_tlu_i0_valid_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 461:53] + node _T_258 = or(trigger_hit_dmode_r, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 464:57] + node _T_259 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 464:112] + node _T_260 = and(request_debug_mode_r_d1, _T_259) @[dec_tlu_ctl.scala 464:110] + node request_debug_mode_r = or(_T_258, _T_260) @[dec_tlu_ctl.scala 464:83] + node _T_261 = or(request_debug_mode_r_d1, request_debug_mode_done_f) @[dec_tlu_ctl.scala 466:64] + node _T_262 = not(dbg_tlu_halted_f) @[dec_tlu_ctl.scala 466:95] + node request_debug_mode_done = and(_T_261, _T_262) @[dec_tlu_ctl.scala 466:93] + wire _T_263 : UInt<1> + _T_263 <= UInt<1>("h00") + node _T_264 = xor(io.tlu_ifc.dec_tlu_flush_noredir_wb, _T_263) @[lib.scala 470:21] + node _T_265 = orr(_T_264) @[lib.scala 470:29] + reg _T_266 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_265 : @[Reg.scala 28:19] + _T_266 <= io.tlu_ifc.dec_tlu_flush_noredir_wb @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_263 <= _T_266 @[lib.scala 473:16] + dec_tlu_flush_noredir_r_d1 <= _T_263 @[dec_tlu_ctl.scala 468:51] + wire _T_267 : UInt + _T_267 <= UInt<1>("h00") + node _T_268 = xor(halt_taken, _T_267) @[lib.scala 448:21] + node _T_269 = orr(_T_268) @[lib.scala 448:29] + reg _T_270 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_269 : @[Reg.scala 28:19] + _T_270 <= halt_taken @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_267 <= _T_270 @[lib.scala 451:16] + halt_taken_f <= _T_267 @[dec_tlu_ctl.scala 469:65] + wire _T_271 : UInt + _T_271 <= UInt<1>("h00") + node _T_272 = xor(io.lsu_idle_any, _T_271) @[lib.scala 448:21] + node _T_273 = orr(_T_272) @[lib.scala 448:29] + reg _T_274 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_273 : @[Reg.scala 28:19] + _T_274 <= io.lsu_idle_any @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_271 <= _T_274 @[lib.scala 451:16] + lsu_idle_any_f <= _T_271 @[dec_tlu_ctl.scala 470:63] + wire _T_275 : UInt<1> + _T_275 <= UInt<1>("h00") + node _T_276 = xor(io.tlu_mem.ifu_miss_state_idle, _T_275) @[lib.scala 470:21] + node _T_277 = orr(_T_276) @[lib.scala 470:29] + reg _T_278 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_277 : @[Reg.scala 28:19] + _T_278 <= io.tlu_mem.ifu_miss_state_idle @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_275 <= _T_278 @[lib.scala 473:16] + ifu_miss_state_idle_f <= _T_275 @[dec_tlu_ctl.scala 471:53] + wire _T_279 : UInt + _T_279 <= UInt<1>("h00") + node _T_280 = xor(dbg_tlu_halted, _T_279) @[lib.scala 448:21] + node _T_281 = orr(_T_280) @[lib.scala 448:29] + reg _T_282 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_281 : @[Reg.scala 28:19] + _T_282 <= dbg_tlu_halted @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_279 <= _T_282 @[lib.scala 451:16] + dbg_tlu_halted_f <= _T_279 @[dec_tlu_ctl.scala 472:63] + wire _T_283 : UInt + _T_283 <= UInt<1>("h00") + node _T_284 = xor(resume_ack_ns, _T_283) @[lib.scala 448:21] + node _T_285 = orr(_T_284) @[lib.scala 448:29] + reg _T_286 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_285 : @[Reg.scala 28:19] + _T_286 <= resume_ack_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_283 <= _T_286 @[lib.scala 451:16] + io.dec_tlu_resume_ack <= _T_283 @[dec_tlu_ctl.scala 473:53] + wire _T_287 : UInt + _T_287 <= UInt<1>("h00") + node _T_288 = xor(debug_halt_req_ns, _T_287) @[lib.scala 448:21] + node _T_289 = orr(_T_288) @[lib.scala 448:29] + reg _T_290 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_289 : @[Reg.scala 28:19] + _T_290 <= debug_halt_req_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_287 <= _T_290 @[lib.scala 451:16] + debug_halt_req_f <= _T_287 @[dec_tlu_ctl.scala 474:63] + wire _T_291 : UInt + _T_291 <= UInt<1>("h00") + node _T_292 = xor(debug_resume_req, _T_291) @[lib.scala 448:21] + node _T_293 = orr(_T_292) @[lib.scala 448:29] + reg _T_294 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_293 : @[Reg.scala 28:19] + _T_294 <= debug_resume_req @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_291 <= _T_294 @[lib.scala 451:16] + debug_resume_req_f_raw <= _T_291 @[dec_tlu_ctl.scala 475:57] + wire _T_295 : UInt + _T_295 <= UInt<1>("h00") + node _T_296 = xor(trigger_hit_dmode_r, _T_295) @[lib.scala 448:21] + node _T_297 = orr(_T_296) @[lib.scala 448:29] + reg _T_298 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_297 : @[Reg.scala 28:19] + _T_298 <= trigger_hit_dmode_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_295 <= _T_298 @[lib.scala 451:16] + trigger_hit_dmode_r_d1 <= _T_295 @[dec_tlu_ctl.scala 476:51] + wire _T_299 : UInt + _T_299 <= UInt<1>("h00") + node _T_300 = xor(dcsr_single_step_done, _T_299) @[lib.scala 448:21] + node _T_301 = orr(_T_300) @[lib.scala 448:29] + reg _T_302 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_301 : @[Reg.scala 28:19] + _T_302 <= dcsr_single_step_done @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_299 <= _T_302 @[lib.scala 451:16] + dcsr_single_step_done_f <= _T_299 @[dec_tlu_ctl.scala 477:51] + wire _T_303 : UInt + _T_303 <= UInt<1>("h00") + node _T_304 = xor(debug_halt_req, _T_303) @[lib.scala 448:21] + node _T_305 = orr(_T_304) @[lib.scala 448:29] + reg _T_306 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_305 : @[Reg.scala 28:19] + _T_306 <= debug_halt_req @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_303 <= _T_306 @[lib.scala 451:16] + debug_halt_req_d1 <= _T_303 @[dec_tlu_ctl.scala 478:63] + wire dec_tlu_wr_pause_r_d1 : UInt + dec_tlu_wr_pause_r_d1 <= UInt<1>("h00") + node _T_307 = xor(io.dec_tlu_wr_pause_r, dec_tlu_wr_pause_r_d1) @[lib.scala 448:21] + node _T_308 = orr(_T_307) @[lib.scala 448:29] + reg _T_309 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_308 : @[Reg.scala 28:19] + _T_309 <= io.dec_tlu_wr_pause_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dec_tlu_wr_pause_r_d1 <= _T_309 @[lib.scala 451:16] + wire dec_pause_state_f : UInt + dec_pause_state_f <= UInt<1>("h00") + node _T_310 = xor(io.dec_pause_state, dec_pause_state_f) @[lib.scala 448:21] + node _T_311 = orr(_T_310) @[lib.scala 448:29] + reg _T_312 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_311 : @[Reg.scala 28:19] + _T_312 <= io.dec_pause_state @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dec_pause_state_f <= _T_312 @[lib.scala 451:16] + wire _T_313 : UInt + _T_313 <= UInt<1>("h00") + node _T_314 = xor(request_debug_mode_r, _T_313) @[lib.scala 448:21] + node _T_315 = orr(_T_314) @[lib.scala 448:29] + reg _T_316 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_315 : @[Reg.scala 28:19] + _T_316 <= request_debug_mode_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_313 <= _T_316 @[lib.scala 451:16] + request_debug_mode_r_d1 <= _T_313 @[dec_tlu_ctl.scala 481:49] + wire _T_317 : UInt + _T_317 <= UInt<1>("h00") + node _T_318 = xor(request_debug_mode_done, _T_317) @[lib.scala 448:21] + node _T_319 = orr(_T_318) @[lib.scala 448:29] + reg _T_320 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_319 : @[Reg.scala 28:19] + _T_320 <= request_debug_mode_done @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_317 <= _T_320 @[lib.scala 451:16] + request_debug_mode_done_f <= _T_317 @[dec_tlu_ctl.scala 482:49] + wire _T_321 : UInt + _T_321 <= UInt<1>("h00") + node _T_322 = xor(dcsr_single_step_running, _T_321) @[lib.scala 448:21] + node _T_323 = orr(_T_322) @[lib.scala 448:29] + reg _T_324 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_323 : @[Reg.scala 28:19] + _T_324 <= dcsr_single_step_running @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_321 <= _T_324 @[lib.scala 451:16] + dcsr_single_step_running_f <= _T_321 @[dec_tlu_ctl.scala 483:49] + wire _T_325 : UInt + _T_325 <= UInt<1>("h00") + node _T_326 = xor(io.dec_tlu_flush_pause_r, _T_325) @[lib.scala 448:21] + node _T_327 = orr(_T_326) @[lib.scala 448:29] + reg _T_328 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_327 : @[Reg.scala 28:19] + _T_328 <= io.dec_tlu_flush_pause_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_325 <= _T_328 @[lib.scala 451:16] + dec_tlu_flush_pause_r_d1 <= _T_325 @[dec_tlu_ctl.scala 484:49] + wire _T_329 : UInt + _T_329 <= UInt<1>("h00") + node _T_330 = xor(dbg_halt_req_held_ns, _T_329) @[lib.scala 448:21] + node _T_331 = orr(_T_330) @[lib.scala 448:29] + reg _T_332 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_331 : @[Reg.scala 28:19] + _T_332 <= dbg_halt_req_held_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_329 <= _T_332 @[lib.scala 451:16] + dbg_halt_req_held <= _T_329 @[dec_tlu_ctl.scala 485:57] + node _T_333 = not(io.dbg_halt_req) @[dec_tlu_ctl.scala 489:56] + node _T_334 = and(debug_resume_req_f_raw, _T_333) @[dec_tlu_ctl.scala 489:54] + debug_resume_req_f <= _T_334 @[dec_tlu_ctl.scala 489:28] + io.dec_tlu_debug_stall <= debug_halt_req_f @[dec_tlu_ctl.scala 491:41] + io.dec_tlu_dbg_halted <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 492:41] + io.dec_tlu_debug_mode <= debug_mode_status @[dec_tlu_ctl.scala 493:41] + dec_tlu_pmu_fw_halted <= pmu_fw_tlu_halted_f @[dec_tlu_ctl.scala 494:41] + node _T_335 = and(fence_i_r, internal_dbg_halt_mode) @[dec_tlu_ctl.scala 497:71] + node _T_336 = or(take_halt, _T_335) @[dec_tlu_ctl.scala 497:58] + node _T_337 = or(_T_336, io.dec_tlu_flush_pause_r) @[dec_tlu_ctl.scala 497:97] + node _T_338 = and(i0_trigger_hit_r, trigger_hit_dmode_r) @[dec_tlu_ctl.scala 497:144] + node _T_339 = or(_T_337, _T_338) @[dec_tlu_ctl.scala 497:124] + node _T_340 = or(_T_339, take_ext_int_start) @[dec_tlu_ctl.scala 497:167] + io.tlu_ifc.dec_tlu_flush_noredir_wb <= _T_340 @[dec_tlu_ctl.scala 497:45] + io.dec_tlu_flush_extint <= take_ext_int_start @[dec_tlu_ctl.scala 499:33] + node _T_341 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 502:61] + node _T_342 = and(dec_tlu_wr_pause_r_d1, _T_341) @[dec_tlu_ctl.scala 502:59] + node _T_343 = not(take_ext_int_start) @[dec_tlu_ctl.scala 502:82] + node _T_344 = and(_T_342, _T_343) @[dec_tlu_ctl.scala 502:80] + io.dec_tlu_flush_pause_r <= _T_344 @[dec_tlu_ctl.scala 502:34] + node _T_345 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 504:28] + node _T_346 = and(_T_345, dec_pause_state_f) @[dec_tlu_ctl.scala 504:48] + node _T_347 = or(ext_int_ready, ce_int_ready) @[dec_tlu_ctl.scala 504:86] + node _T_348 = or(_T_347, timer_int_ready) @[dec_tlu_ctl.scala 504:101] + node _T_349 = or(_T_348, soft_int_ready) @[dec_tlu_ctl.scala 504:119] + node _T_350 = or(_T_349, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 504:136] + node _T_351 = or(_T_350, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 504:160] + node _T_352 = or(_T_351, nmi_int_detected) @[dec_tlu_ctl.scala 504:184] + node _T_353 = or(_T_352, csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 504:203] + node _T_354 = not(_T_353) @[dec_tlu_ctl.scala 504:70] + node _T_355 = and(_T_346, _T_354) @[dec_tlu_ctl.scala 504:68] + node _T_356 = not(interrupt_valid_r_d1) @[dec_tlu_ctl.scala 504:233] + node _T_357 = and(_T_355, _T_356) @[dec_tlu_ctl.scala 504:231] + node _T_358 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 504:257] + node _T_359 = and(_T_357, _T_358) @[dec_tlu_ctl.scala 504:255] + node _T_360 = not(pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 504:277] + node _T_361 = and(_T_359, _T_360) @[dec_tlu_ctl.scala 504:275] + node _T_362 = not(halt_taken_f) @[dec_tlu_ctl.scala 504:298] + node _T_363 = and(_T_361, _T_362) @[dec_tlu_ctl.scala 504:296] + pause_expired_r <= _T_363 @[dec_tlu_ctl.scala 504:25] + node _T_364 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 506:88] + node _T_365 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_364) @[dec_tlu_ctl.scala 506:82] + node _T_366 = or(io.dec_tlu_resume_ack, dcsr_single_step_running) @[dec_tlu_ctl.scala 506:125] + node _T_367 = and(_T_365, _T_366) @[dec_tlu_ctl.scala 506:100] + node _T_368 = not(io.tlu_ifc.dec_tlu_flush_noredir_wb) @[dec_tlu_ctl.scala 506:155] + node _T_369 = and(_T_367, _T_368) @[dec_tlu_ctl.scala 506:153] + io.tlu_bp.dec_tlu_flush_leak_one_wb <= _T_369 @[dec_tlu_ctl.scala 506:45] + node _T_370 = or(ic_perr_r, iccm_sbecc_r) @[dec_tlu_ctl.scala 507:90] + node _T_371 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_370) @[dec_tlu_ctl.scala 507:77] + io.tlu_mem.dec_tlu_flush_err_wb <= _T_371 @[dec_tlu_ctl.scala 507:41] + io.dec_dbg_cmd_done <= dbg_cmd_done_ns @[dec_tlu_ctl.scala 510:29] + node _T_372 = and(illegal_r, io.dec_dbg_cmd_done) @[dec_tlu_ctl.scala 511:42] + io.dec_dbg_cmd_fail <= _T_372 @[dec_tlu_ctl.scala 511:29] + node _T_373 = bits(mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 524:48] + node _T_374 = bits(mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 524:75] + node _T_375 = bits(mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 524:102] + node _T_376 = bits(mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 524:129] + node _T_377 = cat(_T_375, _T_376) @[Cat.scala 29:58] + node _T_378 = cat(_T_373, _T_374) @[Cat.scala 29:58] + node trigger_execute = cat(_T_378, _T_377) @[Cat.scala 29:58] + node _T_379 = bits(mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 525:52] + node _T_380 = bits(mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 525:79] + node _T_381 = bits(mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 525:106] + node _T_382 = bits(mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 525:133] + node _T_383 = cat(_T_381, _T_382) @[Cat.scala 29:58] + node _T_384 = cat(_T_379, _T_380) @[Cat.scala 29:58] + node trigger_data = cat(_T_384, _T_383) @[Cat.scala 29:58] + node _T_385 = bits(mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 526:52] + node _T_386 = bits(mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 526:79] + node _T_387 = bits(mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 526:106] + node _T_388 = bits(mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 526:133] + node _T_389 = cat(_T_387, _T_388) @[Cat.scala 29:58] + node _T_390 = cat(_T_385, _T_386) @[Cat.scala 29:58] + node trigger_store = cat(_T_390, _T_389) @[Cat.scala 29:58] + node _T_391 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 529:53] + node _T_392 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 529:79] + node _T_393 = or(_T_391, _T_392) @[dec_tlu_ctl.scala 529:70] + node _T_394 = bits(mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 529:108] + node _T_395 = and(_T_393, _T_394) @[dec_tlu_ctl.scala 529:94] + node _T_396 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 530:30] + node _T_397 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 530:56] + node _T_398 = or(_T_396, _T_397) @[dec_tlu_ctl.scala 530:47] + node _T_399 = bits(mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 530:85] + node _T_400 = and(_T_398, _T_399) @[dec_tlu_ctl.scala 530:71] + node _T_401 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 531:30] + node _T_402 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 531:56] + node _T_403 = or(_T_401, _T_402) @[dec_tlu_ctl.scala 531:47] + node _T_404 = bits(mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 531:85] + node _T_405 = and(_T_403, _T_404) @[dec_tlu_ctl.scala 531:71] + node _T_406 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 532:30] + node _T_407 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 532:56] + node _T_408 = or(_T_406, _T_407) @[dec_tlu_ctl.scala 532:47] + node _T_409 = bits(mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 532:85] + node _T_410 = and(_T_408, _T_409) @[dec_tlu_ctl.scala 532:71] + node _T_411 = cat(_T_405, _T_410) @[Cat.scala 29:58] + node _T_412 = cat(_T_395, _T_400) @[Cat.scala 29:58] + node trigger_enabled = cat(_T_412, _T_411) @[Cat.scala 29:58] + node _T_413 = and(trigger_execute, trigger_data) @[dec_tlu_ctl.scala 535:62] + node _T_414 = bits(inst_acc_r_raw, 0, 0) @[Bitwise.scala 72:15] + node _T_415 = mux(_T_414, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_416 = and(_T_413, _T_415) @[dec_tlu_ctl.scala 535:77] + node _T_417 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 535:142] + node _T_418 = bits(_T_417, 0, 0) @[Bitwise.scala 72:15] + node _T_419 = mux(_T_418, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_420 = or(_T_416, _T_419) @[dec_tlu_ctl.scala 535:103] + node i0_iside_trigger_has_pri_r = not(_T_420) @[dec_tlu_ctl.scala 535:43] + node _T_421 = and(trigger_store, trigger_data) @[dec_tlu_ctl.scala 538:56] + node _T_422 = bits(lsu_i0_exc_r_raw, 0, 0) @[Bitwise.scala 72:15] + node _T_423 = mux(_T_422, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 538:71] + node i0_lsu_trigger_has_pri_r = not(_T_424) @[dec_tlu_ctl.scala 538:40] + node _T_425 = bits(io.dec_tlu_i0_valid_r, 0, 0) @[Bitwise.scala 72:15] + node _T_426 = mux(_T_425, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_427 = bits(io.dec_tlu_packet_r.i0trigger, 3, 0) @[dec_tlu_ctl.scala 543:89] + node _T_428 = and(_T_426, _T_427) @[dec_tlu_ctl.scala 543:58] + node _T_429 = and(_T_428, i0_iside_trigger_has_pri_r) @[dec_tlu_ctl.scala 543:95] + node _T_430 = and(_T_429, i0_lsu_trigger_has_pri_r) @[dec_tlu_ctl.scala 543:124] + node i0trigger_qual_r = and(_T_430, trigger_enabled) @[dec_tlu_ctl.scala 543:151] + node _T_431 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 545:64] + node _T_432 = bits(_T_431, 0, 0) @[Bitwise.scala 72:15] + node _T_433 = mux(_T_432, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_434 = not(_T_433) @[dec_tlu_ctl.scala 545:29] + node i0_trigger_r = and(_T_434, i0trigger_qual_r) @[dec_tlu_ctl.scala 545:90] + node _T_435 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 548:58] + node _T_436 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 548:78] + node _T_437 = not(_T_436) @[dec_tlu_ctl.scala 548:65] + node _T_438 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 548:108] + node _T_439 = or(_T_437, _T_438) @[dec_tlu_ctl.scala 548:94] + node _T_440 = and(_T_435, _T_439) @[dec_tlu_ctl.scala 548:62] + node _T_441 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 549:29] + node _T_442 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 549:49] + node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 549:36] + node _T_444 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 549:79] + node _T_445 = or(_T_443, _T_444) @[dec_tlu_ctl.scala 549:65] + node _T_446 = and(_T_441, _T_445) @[dec_tlu_ctl.scala 549:33] + node _T_447 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 550:29] + node _T_448 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 550:49] + node _T_449 = not(_T_448) @[dec_tlu_ctl.scala 550:36] + node _T_450 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 550:79] + node _T_451 = or(_T_449, _T_450) @[dec_tlu_ctl.scala 550:65] + node _T_452 = and(_T_447, _T_451) @[dec_tlu_ctl.scala 550:33] + node _T_453 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 551:29] + node _T_454 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 551:49] + node _T_455 = not(_T_454) @[dec_tlu_ctl.scala 551:36] + node _T_456 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 551:79] + node _T_457 = or(_T_455, _T_456) @[dec_tlu_ctl.scala 551:65] + node _T_458 = and(_T_453, _T_457) @[dec_tlu_ctl.scala 551:33] + node _T_459 = cat(_T_452, _T_458) @[Cat.scala 29:58] + node _T_460 = cat(_T_440, _T_446) @[Cat.scala 29:58] + node i0_trigger_chain_masked_r = cat(_T_460, _T_459) @[Cat.scala 29:58] + node i0_trigger_hit_raw_r = orr(i0_trigger_chain_masked_r) @[dec_tlu_ctl.scala 555:62] + i0_trigger_hit_r <= i0_trigger_hit_raw_r @[dec_tlu_ctl.scala 557:33] + node _T_461 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 561:52] + node _T_462 = bits(mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 561:83] + node _T_463 = and(_T_461, _T_462) @[dec_tlu_ctl.scala 561:69] + node _T_464 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 562:29] + node _T_465 = bits(mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 562:60] + node _T_466 = and(_T_464, _T_465) @[dec_tlu_ctl.scala 562:46] + node _T_467 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 562:91] + node _T_468 = not(_T_467) @[dec_tlu_ctl.scala 562:78] + node _T_469 = and(_T_466, _T_468) @[dec_tlu_ctl.scala 562:76] + node _T_470 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 563:29] + node _T_471 = bits(mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 563:60] + node _T_472 = and(_T_470, _T_471) @[dec_tlu_ctl.scala 563:46] + node _T_473 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 564:29] + node _T_474 = bits(mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 564:60] + node _T_475 = and(_T_473, _T_474) @[dec_tlu_ctl.scala 564:46] + node _T_476 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 564:91] + node _T_477 = not(_T_476) @[dec_tlu_ctl.scala 564:78] + node _T_478 = and(_T_475, _T_477) @[dec_tlu_ctl.scala 564:76] + node _T_479 = cat(_T_472, _T_478) @[Cat.scala 29:58] + node _T_480 = cat(_T_463, _T_469) @[Cat.scala 29:58] + node trigger_action = cat(_T_480, _T_479) @[Cat.scala 29:58] + node _T_481 = orr(i0_trigger_r) @[dec_tlu_ctl.scala 567:59] + node _T_482 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 567:65] + node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 567:63] + node _T_484 = bits(_T_483, 0, 0) @[Bitwise.scala 72:15] + node _T_485 = mux(_T_484, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_486 = bits(i0_trigger_chain_masked_r, 3, 3) @[dec_tlu_ctl.scala 567:108] + node _T_487 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 567:125] + node _T_488 = bits(i0_trigger_chain_masked_r, 1, 1) @[dec_tlu_ctl.scala 567:155] + node _T_489 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 567:172] + node _T_490 = cat(_T_488, _T_489) @[Cat.scala 29:58] + node _T_491 = cat(_T_486, _T_487) @[Cat.scala 29:58] + node _T_492 = cat(_T_491, _T_490) @[Cat.scala 29:58] + node update_hit_bit_r = and(_T_485, _T_492) @[dec_tlu_ctl.scala 567:77] + node _T_493 = and(i0_trigger_chain_masked_r, trigger_action) @[dec_tlu_ctl.scala 570:62] + node i0_trigger_action_r = orr(_T_493) @[dec_tlu_ctl.scala 570:80] + node _T_494 = and(i0_trigger_hit_r, i0_trigger_action_r) @[dec_tlu_ctl.scala 572:50] + trigger_hit_dmode_r <= _T_494 @[dec_tlu_ctl.scala 572:29] + node _T_495 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 574:60] + node mepc_trigger_hit_sel_pc_r = and(i0_trigger_hit_r, _T_495) @[dec_tlu_ctl.scala 574:58] + node _T_496 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 601:62] + node _T_497 = and(i_cpu_halt_req_sync, _T_496) @[dec_tlu_ctl.scala 601:60] + node _T_498 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 601:87] + node i_cpu_halt_req_sync_qual = and(_T_497, _T_498) @[dec_tlu_ctl.scala 601:85] + node _T_499 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 602:60] + node _T_500 = and(i_cpu_run_req_sync, _T_499) @[dec_tlu_ctl.scala 602:58] + node _T_501 = and(_T_500, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 602:83] + node _T_502 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 602:107] + node i_cpu_run_req_sync_qual = and(_T_501, _T_502) @[dec_tlu_ctl.scala 602:105] + wire i_cpu_halt_req_d1 : UInt + i_cpu_halt_req_d1 <= UInt<1>("h00") + node _T_503 = xor(i_cpu_halt_req_sync_qual, i_cpu_halt_req_d1) @[lib.scala 448:21] + node _T_504 = orr(_T_503) @[lib.scala 448:29] + reg _T_505 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_504 : @[Reg.scala 28:19] + _T_505 <= i_cpu_halt_req_sync_qual @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + i_cpu_halt_req_d1 <= _T_505 @[lib.scala 451:16] + wire i_cpu_run_req_d1_raw : UInt + i_cpu_run_req_d1_raw <= UInt<1>("h00") + node _T_506 = xor(i_cpu_run_req_sync_qual, i_cpu_run_req_d1_raw) @[lib.scala 448:21] + node _T_507 = orr(_T_506) @[lib.scala 448:29] + reg _T_508 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_507 : @[Reg.scala 28:19] + _T_508 <= i_cpu_run_req_sync_qual @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + i_cpu_run_req_d1_raw <= _T_508 @[lib.scala 451:16] + wire _T_509 : UInt + _T_509 <= UInt<1>("h00") + node _T_510 = xor(cpu_halt_status, _T_509) @[lib.scala 448:21] + node _T_511 = orr(_T_510) @[lib.scala 448:29] + reg _T_512 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_511 : @[Reg.scala 28:19] + _T_512 <= cpu_halt_status @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_509 <= _T_512 @[lib.scala 451:16] + io.o_cpu_halt_status <= _T_509 @[dec_tlu_ctl.scala 606:60] + wire _T_513 : UInt + _T_513 <= UInt<1>("h00") + node _T_514 = xor(cpu_halt_ack, _T_513) @[lib.scala 448:21] + node _T_515 = orr(_T_514) @[lib.scala 448:29] + reg _T_516 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_515 : @[Reg.scala 28:19] + _T_516 <= cpu_halt_ack @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_513 <= _T_516 @[lib.scala 451:16] + io.o_cpu_halt_ack <= _T_513 @[dec_tlu_ctl.scala 607:68] + wire _T_517 : UInt + _T_517 <= UInt<1>("h00") + node _T_518 = xor(cpu_run_ack, _T_517) @[lib.scala 448:21] + node _T_519 = orr(_T_518) @[lib.scala 448:29] + reg _T_520 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_519 : @[Reg.scala 28:19] + _T_520 <= cpu_run_ack @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_517 <= _T_520 @[lib.scala 451:16] + io.o_cpu_run_ack <= _T_517 @[dec_tlu_ctl.scala 608:68] + wire internal_pmu_fw_halt_mode_f : UInt + internal_pmu_fw_halt_mode_f <= UInt<1>("h00") + node _T_521 = xor(internal_pmu_fw_halt_mode, internal_pmu_fw_halt_mode_f) @[lib.scala 448:21] + node _T_522 = orr(_T_521) @[lib.scala 448:29] + reg _T_523 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_522 : @[Reg.scala 28:19] + _T_523 <= internal_pmu_fw_halt_mode @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + internal_pmu_fw_halt_mode_f <= _T_523 @[lib.scala 451:16] + wire _T_524 : UInt + _T_524 <= UInt<1>("h00") + node _T_525 = xor(pmu_fw_halt_req_ns, _T_524) @[lib.scala 448:21] + node _T_526 = orr(_T_525) @[lib.scala 448:29] + reg _T_527 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_526 : @[Reg.scala 28:19] + _T_527 <= pmu_fw_halt_req_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_524 <= _T_527 @[lib.scala 451:16] + pmu_fw_halt_req_f <= _T_524 @[dec_tlu_ctl.scala 610:62] + wire _T_528 : UInt + _T_528 <= UInt<1>("h00") + node _T_529 = xor(pmu_fw_tlu_halted, _T_528) @[lib.scala 448:21] + node _T_530 = orr(_T_529) @[lib.scala 448:29] + reg _T_531 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_530 : @[Reg.scala 28:19] + _T_531 <= pmu_fw_tlu_halted @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_528 <= _T_531 @[lib.scala 451:16] + pmu_fw_tlu_halted_f <= _T_528 @[dec_tlu_ctl.scala 611:60] + wire _T_532 : UInt + _T_532 <= UInt<1>("h00") + node _T_533 = xor(int_timer0_int_hold, _T_532) @[lib.scala 448:21] + node _T_534 = orr(_T_533) @[lib.scala 448:29] + reg _T_535 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_534 : @[Reg.scala 28:19] + _T_535 <= int_timer0_int_hold @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_532 <= _T_535 @[lib.scala 451:16] + int_timer0_int_hold_f <= _T_532 @[dec_tlu_ctl.scala 612:52] + wire _T_536 : UInt + _T_536 <= UInt<1>("h00") + node _T_537 = xor(int_timer1_int_hold, _T_536) @[lib.scala 448:21] + node _T_538 = orr(_T_537) @[lib.scala 448:29] + reg _T_539 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_538 : @[Reg.scala 28:19] + _T_539 <= int_timer1_int_hold @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_536 <= _T_539 @[lib.scala 451:16] + int_timer1_int_hold_f <= _T_536 @[dec_tlu_ctl.scala 613:52] + node _T_540 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 617:57] + node ext_halt_pulse = and(i_cpu_halt_req_sync_qual, _T_540) @[dec_tlu_ctl.scala 617:55] + node enter_pmu_fw_halt_req = or(ext_halt_pulse, fw_halt_req) @[dec_tlu_ctl.scala 618:53] + node _T_541 = not(pmu_fw_tlu_halted) @[dec_tlu_ctl.scala 619:77] + node _T_542 = and(pmu_fw_halt_req_f, _T_541) @[dec_tlu_ctl.scala 619:75] + node _T_543 = or(enter_pmu_fw_halt_req, _T_542) @[dec_tlu_ctl.scala 619:54] + node _T_544 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 619:100] + node _T_545 = and(_T_543, _T_544) @[dec_tlu_ctl.scala 619:98] + pmu_fw_halt_req_ns <= _T_545 @[dec_tlu_ctl.scala 619:28] + node _T_546 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 620:90] + node _T_547 = and(internal_pmu_fw_halt_mode_f, _T_546) @[dec_tlu_ctl.scala 620:88] + node _T_548 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 620:110] + node _T_549 = and(_T_547, _T_548) @[dec_tlu_ctl.scala 620:108] + node _T_550 = or(pmu_fw_halt_req_ns, _T_549) @[dec_tlu_ctl.scala 620:57] + internal_pmu_fw_halt_mode <= _T_550 @[dec_tlu_ctl.scala 620:35] + node _T_551 = and(pmu_fw_halt_req_f, core_empty) @[dec_tlu_ctl.scala 623:50] + node _T_552 = and(_T_551, halt_taken) @[dec_tlu_ctl.scala 623:63] + node _T_553 = not(enter_debug_halt_req) @[dec_tlu_ctl.scala 623:78] + node _T_554 = and(_T_552, _T_553) @[dec_tlu_ctl.scala 623:76] + node _T_555 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 623:126] + node _T_556 = and(pmu_fw_tlu_halted_f, _T_555) @[dec_tlu_ctl.scala 623:124] + node _T_557 = or(_T_554, _T_556) @[dec_tlu_ctl.scala 623:101] + node _T_558 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 623:148] + node _T_559 = and(_T_557, _T_558) @[dec_tlu_ctl.scala 623:146] + pmu_fw_tlu_halted <= _T_559 @[dec_tlu_ctl.scala 623:27] + node _T_560 = and(i_cpu_halt_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 625:44] + node _T_561 = and(io.o_cpu_halt_ack, i_cpu_halt_req_sync) @[dec_tlu_ctl.scala 625:88] + node _T_562 = or(_T_560, _T_561) @[dec_tlu_ctl.scala 625:67] + cpu_halt_ack <= _T_562 @[dec_tlu_ctl.scala 625:22] + node _T_563 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 626:51] + node _T_564 = and(pmu_fw_tlu_halted_f, _T_563) @[dec_tlu_ctl.scala 626:49] + node _T_565 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 626:96] + node _T_566 = and(io.o_cpu_halt_status, _T_565) @[dec_tlu_ctl.scala 626:94] + node _T_567 = not(debug_mode_status) @[dec_tlu_ctl.scala 626:116] + node _T_568 = and(_T_566, _T_567) @[dec_tlu_ctl.scala 626:114] + node _T_569 = or(_T_564, _T_568) @[dec_tlu_ctl.scala 626:70] + cpu_halt_status <= _T_569 @[dec_tlu_ctl.scala 626:25] + node _T_570 = not(pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 627:25] + node _T_571 = and(_T_570, i_cpu_run_req_sync) @[dec_tlu_ctl.scala 627:46] + node _T_572 = and(io.o_cpu_halt_status, i_cpu_run_req_d1_raw) @[dec_tlu_ctl.scala 627:92] + node _T_573 = or(_T_571, _T_572) @[dec_tlu_ctl.scala 627:68] + node _T_574 = and(io.o_cpu_run_ack, i_cpu_run_req_sync) @[dec_tlu_ctl.scala 627:136] + node _T_575 = or(_T_573, _T_574) @[dec_tlu_ctl.scala 627:116] + cpu_run_ack <= _T_575 @[dec_tlu_ctl.scala 627:21] + io.o_debug_mode_status <= debug_mode_status @[dec_tlu_ctl.scala 630:32] + node _T_576 = or(nmi_int_detected, timer_int_ready) @[dec_tlu_ctl.scala 633:71] + node _T_577 = or(_T_576, soft_int_ready) @[dec_tlu_ctl.scala 633:89] + node _T_578 = or(_T_577, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 633:106] + node _T_579 = or(_T_578, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 633:130] + node _T_580 = and(io.dec_pic.mhwakeup, mhwakeup_ready) @[dec_tlu_ctl.scala 633:177] + node _T_581 = or(_T_579, _T_580) @[dec_tlu_ctl.scala 633:154] + node _T_582 = and(_T_581, io.o_cpu_halt_status) @[dec_tlu_ctl.scala 633:196] + node _T_583 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 633:221] + node _T_584 = and(_T_582, _T_583) @[dec_tlu_ctl.scala 633:219] + node _T_585 = or(i_cpu_run_req_d1_raw, _T_584) @[dec_tlu_ctl.scala 633:50] + i_cpu_run_req_d1 <= _T_585 @[dec_tlu_ctl.scala 633:26] + node _T_586 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 642:62] + node lsu_exc_valid_r_raw = and(io.lsu_error_pkt_r.valid, _T_586) @[dec_tlu_ctl.scala 642:60] + lsu_i0_exc_r_raw <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 643:26] + node _T_587 = and(lsu_i0_exc_r_raw, lsu_exc_valid_r_raw) @[dec_tlu_ctl.scala 644:45] + node _T_588 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 644:69] + node _T_589 = and(_T_587, _T_588) @[dec_tlu_ctl.scala 644:67] + node _T_590 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 644:89] + node lsu_exc_valid_r = and(_T_589, _T_590) @[dec_tlu_ctl.scala 644:87] + node _T_591 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 651:54] + node _T_592 = and(io.dec_tlu_i0_valid_r, _T_591) @[dec_tlu_ctl.scala 651:52] + node _T_593 = not(io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 651:75] + node _T_594 = and(_T_593, io.lsu_error_pkt_r.bits.single_ecc_error) @[dec_tlu_ctl.scala 651:110] + node lsu_i0_rfnpc_r = and(_T_592, _T_594) @[dec_tlu_ctl.scala 651:72] + node _T_595 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 654:57] + node _T_596 = and(io.dec_tlu_i0_valid_r, _T_595) @[dec_tlu_ctl.scala 654:55] + node _T_597 = not(lsu_exc_valid_r) @[dec_tlu_ctl.scala 654:70] + node _T_598 = and(_T_596, _T_597) @[dec_tlu_ctl.scala 654:68] + node _T_599 = not(inst_acc_r) @[dec_tlu_ctl.scala 654:87] + node _T_600 = and(_T_598, _T_599) @[dec_tlu_ctl.scala 654:84] + node _T_601 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 654:101] + node _T_602 = and(_T_600, _T_601) @[dec_tlu_ctl.scala 654:99] + node _T_603 = not(request_debug_mode_r_d1) @[dec_tlu_ctl.scala 654:126] + node _T_604 = and(_T_602, _T_603) @[dec_tlu_ctl.scala 654:124] + node _T_605 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 654:153] + node tlu_i0_commit_cmt = and(_T_604, _T_605) @[dec_tlu_ctl.scala 654:151] + node _T_606 = or(rfpc_i0_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 657:43] + node _T_607 = or(_T_606, inst_acc_r) @[dec_tlu_ctl.scala 657:58] + node _T_608 = and(illegal_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 657:84] + node _T_609 = or(_T_607, _T_608) @[dec_tlu_ctl.scala 657:71] + node _T_610 = or(_T_609, i0_trigger_hit_r) @[dec_tlu_ctl.scala 657:109] + tlu_i0_kill_writeb_r <= _T_610 @[dec_tlu_ctl.scala 657:30] + io.tlu_mem.dec_tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 658:42] + node _T_611 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 663:49] + node _T_612 = and(io.dec_tlu_i0_valid_r, _T_611) @[dec_tlu_ctl.scala 663:47] + node _T_613 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 663:103] + node _T_614 = and(_T_612, _T_613) @[dec_tlu_ctl.scala 663:71] + node _T_615 = or(ic_perr_r, iccm_sbecc_r) @[dec_tlu_ctl.scala 663:156] + node _T_616 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 663:174] + node _T_617 = and(_T_615, _T_616) @[dec_tlu_ctl.scala 663:172] + node _T_618 = or(_T_614, _T_617) @[dec_tlu_ctl.scala 663:142] + node _T_619 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 663:205] + node _T_620 = and(_T_618, _T_619) @[dec_tlu_ctl.scala 663:202] + node _T_621 = not(lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 663:226] + node _T_622 = and(_T_620, _T_621) @[dec_tlu_ctl.scala 663:223] + rfpc_i0_r <= _T_622 @[dec_tlu_ctl.scala 663:19] + node _T_623 = not(io.tlu_exu.dec_tlu_flush_lower_r) @[dec_tlu_ctl.scala 666:72] + node _T_624 = and(iccm_repair_state_d1, _T_623) @[dec_tlu_ctl.scala 666:70] + node _T_625 = or(iccm_sbecc_r, _T_624) @[dec_tlu_ctl.scala 666:46] + iccm_repair_state_ns <= _T_625 @[dec_tlu_ctl.scala 666:30] + node _T_626 = and(tlu_i0_commit_cmt, iccm_repair_state_d1) @[dec_tlu_ctl.scala 672:57] + node _T_627 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 672:93] + node _T_628 = or(_T_627, mret_r) @[dec_tlu_ctl.scala 672:103] + node _T_629 = or(_T_628, take_reset) @[dec_tlu_ctl.scala 672:112] + node _T_630 = or(_T_629, illegal_r) @[dec_tlu_ctl.scala 672:125] + node _T_631 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 672:181] + node _T_632 = and(dec_csr_wen_r_mod, _T_631) @[dec_tlu_ctl.scala 672:158] + node _T_633 = or(_T_630, _T_632) @[dec_tlu_ctl.scala 672:137] + node _T_634 = not(_T_633) @[dec_tlu_ctl.scala 672:82] + node iccm_repair_state_rfnpc = and(_T_626, _T_634) @[dec_tlu_ctl.scala 672:80] + wire dec_tlu_br0_error_r : UInt<1> + dec_tlu_br0_error_r <= UInt<1>("h00") + wire dec_tlu_br0_start_error_r : UInt<1> + dec_tlu_br0_start_error_r <= UInt<1>("h00") + wire dec_tlu_br0_v_r : UInt<1> + dec_tlu_br0_v_r <= UInt<1>("h00") + node _T_635 = and(io.tlu_exu.exu_i0_br_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 679:69] + node _T_636 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 679:95] + node _T_637 = and(_T_635, _T_636) @[dec_tlu_ctl.scala 679:93] + dec_tlu_br0_error_r <= _T_637 @[dec_tlu_ctl.scala 679:37] + node _T_638 = and(io.tlu_exu.exu_i0_br_start_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 680:81] + node _T_639 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 680:107] + node _T_640 = and(_T_638, _T_639) @[dec_tlu_ctl.scala 680:105] + dec_tlu_br0_start_error_r <= _T_640 @[dec_tlu_ctl.scala 680:43] + node _T_641 = and(io.tlu_exu.exu_i0_br_valid_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 681:65] + node _T_642 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 681:91] + node _T_643 = and(_T_641, _T_642) @[dec_tlu_ctl.scala 681:89] + node _T_644 = not(io.tlu_exu.exu_i0_br_mp_r) @[dec_tlu_ctl.scala 681:116] + node _T_645 = not(io.tlu_exu.exu_pmu_i0_br_ataken) @[dec_tlu_ctl.scala 681:145] + node _T_646 = or(_T_644, _T_645) @[dec_tlu_ctl.scala 681:143] + node _T_647 = and(_T_643, _T_646) @[dec_tlu_ctl.scala 681:113] + dec_tlu_br0_v_r <= _T_647 @[dec_tlu_ctl.scala 681:33] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist <= io.tlu_exu.exu_i0_br_hist_r @[dec_tlu_ctl.scala 684:73] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 685:73] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 686:73] + io.tlu_bp.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[dec_tlu_ctl.scala 687:73] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[dec_tlu_ctl.scala 688:73] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle <= io.tlu_exu.exu_i0_br_middle_r @[dec_tlu_ctl.scala 689:81] + node _T_648 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 703:57] + node _T_649 = and(_T_648, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 703:70] + node _T_650 = eq(i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 703:96] + node _T_651 = and(_T_649, _T_650) @[dec_tlu_ctl.scala 703:94] + node _T_652 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 703:121] + node _T_653 = not(_T_652) @[dec_tlu_ctl.scala 703:116] + node _T_654 = and(_T_651, _T_653) @[dec_tlu_ctl.scala 703:114] + node _T_655 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 703:138] + node _T_656 = and(_T_654, _T_655) @[dec_tlu_ctl.scala 703:136] + ebreak_r <= _T_656 @[dec_tlu_ctl.scala 703:19] + node _T_657 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h09")) @[dec_tlu_ctl.scala 704:57] + node _T_658 = and(_T_657, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 704:70] + node _T_659 = eq(i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 704:96] + node _T_660 = and(_T_658, _T_659) @[dec_tlu_ctl.scala 704:94] + node _T_661 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 704:116] + node _T_662 = and(_T_660, _T_661) @[dec_tlu_ctl.scala 704:114] + ecall_r <= _T_662 @[dec_tlu_ctl.scala 704:19] + node _T_663 = not(io.dec_tlu_packet_r.legal) @[dec_tlu_ctl.scala 705:23] + node _T_664 = and(_T_663, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 705:52] + node _T_665 = eq(i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 705:78] + node _T_666 = and(_T_664, _T_665) @[dec_tlu_ctl.scala 705:76] + node _T_667 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 705:98] + node _T_668 = and(_T_666, _T_667) @[dec_tlu_ctl.scala 705:96] + illegal_r <= _T_668 @[dec_tlu_ctl.scala 705:19] + node _T_669 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h0c")) @[dec_tlu_ctl.scala 706:57] + node _T_670 = and(_T_669, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 706:70] + node _T_671 = eq(i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 706:96] + node _T_672 = and(_T_670, _T_671) @[dec_tlu_ctl.scala 706:94] + node _T_673 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 706:116] + node _T_674 = and(_T_672, _T_673) @[dec_tlu_ctl.scala 706:114] + mret_r <= _T_674 @[dec_tlu_ctl.scala 706:19] + node _T_675 = and(io.dec_tlu_packet_r.fence_i, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 708:55] + node _T_676 = eq(i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 708:81] + node _T_677 = and(_T_675, _T_676) @[dec_tlu_ctl.scala 708:79] + node _T_678 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 708:102] + node _T_679 = and(_T_677, _T_678) @[dec_tlu_ctl.scala 708:100] + fence_i_r <= _T_679 @[dec_tlu_ctl.scala 708:22] + node _T_680 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 709:49] + node _T_681 = and(ifu_ic_error_start_f, _T_680) @[dec_tlu_ctl.scala 709:47] + node _T_682 = eq(debug_mode_status, UInt<1>("h00")) @[dec_tlu_ctl.scala 709:78] + node _T_683 = or(_T_682, dcsr_single_step_running) @[dec_tlu_ctl.scala 709:104] + node _T_684 = and(_T_681, _T_683) @[dec_tlu_ctl.scala 709:75] + node _T_685 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 709:134] + node _T_686 = and(_T_684, _T_685) @[dec_tlu_ctl.scala 709:132] + ic_perr_r <= _T_686 @[dec_tlu_ctl.scala 709:22] + node _T_687 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 710:57] + node _T_688 = and(ifu_iccm_rd_ecc_single_err_f, _T_687) @[dec_tlu_ctl.scala 710:55] + node _T_689 = eq(debug_mode_status, UInt<1>("h00")) @[dec_tlu_ctl.scala 710:86] + node _T_690 = or(_T_689, dcsr_single_step_running) @[dec_tlu_ctl.scala 710:112] + node _T_691 = and(_T_688, _T_690) @[dec_tlu_ctl.scala 710:83] + node _T_692 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 710:142] + node _T_693 = and(_T_691, _T_692) @[dec_tlu_ctl.scala 710:140] + iccm_sbecc_r <= _T_693 @[dec_tlu_ctl.scala 710:22] + node _T_694 = and(io.dec_tlu_packet_r.icaf, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 712:54] + inst_acc_r_raw <= _T_694 @[dec_tlu_ctl.scala 712:25] + node _T_695 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 713:40] + node _T_696 = and(inst_acc_r_raw, _T_695) @[dec_tlu_ctl.scala 713:38] + node _T_697 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 713:53] + node _T_698 = and(_T_696, _T_697) @[dec_tlu_ctl.scala 713:51] + inst_acc_r <= _T_698 @[dec_tlu_ctl.scala 713:20] + node _T_699 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 716:69] + node _T_700 = and(_T_699, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 716:82] + node _T_701 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 716:108] + node _T_702 = and(_T_700, _T_701) @[dec_tlu_ctl.scala 716:106] + node _T_703 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 716:132] + node _T_704 = and(_T_702, _T_703) @[dec_tlu_ctl.scala 716:126] + node _T_705 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 716:149] + node _T_706 = and(_T_704, _T_705) @[dec_tlu_ctl.scala 716:147] + ebreak_to_debug_mode_r <= _T_706 @[dec_tlu_ctl.scala 716:32] + reg _T_707 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 718:64] + _T_707 <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 718:64] + ebreak_to_debug_mode_r_d1 <= _T_707 @[dec_tlu_ctl.scala 718:34] + io.tlu_mem.dec_tlu_fence_i_wb <= fence_i_r @[dec_tlu_ctl.scala 719:39] + int_exc.io.free_l2clk <= io.free_l2clk @[dec_tlu_ctl.scala 722:49] + int_exc.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 723:49] + int_exc.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[dec_tlu_ctl.scala 724:49] + int_exc.io.mstatus_mie_ns <= mstatus_mie_ns @[dec_tlu_ctl.scala 725:49] + int_exc.io.mip <= mip @[dec_tlu_ctl.scala 726:49] + int_exc.io.mie_ns <= mie_ns @[dec_tlu_ctl.scala 727:49] + int_exc.io.mret_r <= mret_r @[dec_tlu_ctl.scala 728:49] + int_exc.io.pmu_fw_tlu_halted_f <= pmu_fw_tlu_halted_f @[dec_tlu_ctl.scala 729:49] + int_exc.io.int_timer0_int_hold_f <= int_timer0_int_hold_f @[dec_tlu_ctl.scala 730:49] + int_exc.io.int_timer1_int_hold_f <= int_timer1_int_hold_f @[dec_tlu_ctl.scala 731:49] + int_exc.io.internal_dbg_halt_mode_f <= debug_mode_status @[dec_tlu_ctl.scala 732:49] + int_exc.io.dcsr_single_step_running <= dcsr_single_step_running @[dec_tlu_ctl.scala 733:49] + int_exc.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 734:49] + int_exc.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 735:49] + int_exc.io.internal_pmu_fw_halt_mode <= internal_pmu_fw_halt_mode @[dec_tlu_ctl.scala 736:49] + int_exc.io.i_cpu_halt_req_d1 <= i_cpu_halt_req_d1 @[dec_tlu_ctl.scala 737:49] + int_exc.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 738:49] + int_exc.io.lsu_fir_error <= io.lsu_fir_error @[dec_tlu_ctl.scala 739:49] + int_exc.io.csr_pkt.legal <= csr_pkt.legal @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.postsync <= csr_pkt.postsync @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.presync <= csr_pkt.presync @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 740:49] + int_exc.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[dec_tlu_ctl.scala 740:49] + int_exc.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[dec_tlu_ctl.scala 741:49] + int_exc.io.lsu_fastint_stall_any <= io.lsu_fastint_stall_any @[dec_tlu_ctl.scala 742:49] + int_exc.io.reset_delayed <= reset_delayed @[dec_tlu_ctl.scala 743:49] + int_exc.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 744:49] + int_exc.io.nmi_int_detected <= nmi_int_detected @[dec_tlu_ctl.scala 745:49] + int_exc.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[dec_tlu_ctl.scala 746:49] + int_exc.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[dec_tlu_ctl.scala 747:49] + int_exc.io.dcsr <= dcsr @[dec_tlu_ctl.scala 748:49] + int_exc.io.mtvec <= mtvec @[dec_tlu_ctl.scala 749:49] + int_exc.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 750:49] + int_exc.io.i0_trigger_hit_r <= i0_trigger_hit_r @[dec_tlu_ctl.scala 751:49] + int_exc.io.pause_expired_r <= pause_expired_r @[dec_tlu_ctl.scala 752:49] + int_exc.io.nmi_vec <= io.nmi_vec @[dec_tlu_ctl.scala 753:49] + int_exc.io.lsu_i0_rfnpc_r <= lsu_i0_rfnpc_r @[dec_tlu_ctl.scala 754:49] + int_exc.io.fence_i_r <= fence_i_r @[dec_tlu_ctl.scala 755:49] + int_exc.io.iccm_repair_state_rfnpc <= iccm_repair_state_rfnpc @[dec_tlu_ctl.scala 756:49] + int_exc.io.i_cpu_run_req_d1 <= i_cpu_run_req_d1 @[dec_tlu_ctl.scala 757:49] + int_exc.io.rfpc_i0_r <= rfpc_i0_r @[dec_tlu_ctl.scala 758:49] + int_exc.io.lsu_exc_valid_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 759:49] + int_exc.io.trigger_hit_dmode_r <= trigger_hit_dmode_r @[dec_tlu_ctl.scala 760:49] + int_exc.io.take_halt <= take_halt @[dec_tlu_ctl.scala 761:49] + int_exc.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 762:49] + int_exc.io.lsu_fir_addr <= io.lsu_fir_addr @[dec_tlu_ctl.scala 763:49] + int_exc.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[dec_tlu_ctl.scala 764:49] + int_exc.io.npc_r <= npc_r @[dec_tlu_ctl.scala 765:49] + int_exc.io.mepc <= mepc @[dec_tlu_ctl.scala 766:49] + int_exc.io.debug_resume_req_f <= debug_resume_req_f @[dec_tlu_ctl.scala 767:49] + int_exc.io.dpc <= dpc @[dec_tlu_ctl.scala 768:49] + int_exc.io.npc_r_d1 <= npc_r_d1 @[dec_tlu_ctl.scala 769:49] + int_exc.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 770:49] + int_exc.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[dec_tlu_ctl.scala 771:49] + int_exc.io.ebreak_r <= ebreak_r @[dec_tlu_ctl.scala 772:49] + int_exc.io.ecall_r <= ecall_r @[dec_tlu_ctl.scala 773:49] + int_exc.io.illegal_r <= illegal_r @[dec_tlu_ctl.scala 774:49] + int_exc.io.inst_acc_r <= inst_acc_r @[dec_tlu_ctl.scala 775:49] + int_exc.io.lsu_i0_exc_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 776:49] + int_exc.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 777:49] + int_exc.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 777:49] + int_exc.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 777:49] + int_exc.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 777:49] + int_exc.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 777:49] + int_exc.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 777:49] + int_exc.io.dec_tlu_wr_pause_r_d1 <= dec_tlu_wr_pause_r_d1 @[dec_tlu_ctl.scala 778:42] + mhwakeup_ready <= int_exc.io.mhwakeup_ready @[dec_tlu_ctl.scala 780:43] + ext_int_ready <= int_exc.io.ext_int_ready @[dec_tlu_ctl.scala 781:43] + ce_int_ready <= int_exc.io.ce_int_ready @[dec_tlu_ctl.scala 782:43] + soft_int_ready <= int_exc.io.soft_int_ready @[dec_tlu_ctl.scala 783:43] + timer_int_ready <= int_exc.io.timer_int_ready @[dec_tlu_ctl.scala 784:43] + int_timer0_int_hold <= int_exc.io.int_timer0_int_hold @[dec_tlu_ctl.scala 785:43] + int_timer1_int_hold <= int_exc.io.int_timer1_int_hold @[dec_tlu_ctl.scala 786:43] + internal_dbg_halt_timers <= int_exc.io.internal_dbg_halt_timers @[dec_tlu_ctl.scala 787:43] + take_ext_int_start <= int_exc.io.take_ext_int_start @[dec_tlu_ctl.scala 788:43] + int_exc.io.ext_int_freeze_d1 <= csr.io.ext_int_freeze_d1 @[dec_tlu_ctl.scala 789:42] + int_exc.io.take_ext_int_start_d1 <= csr.io.take_ext_int_start_d1 @[dec_tlu_ctl.scala 790:44] + int_exc.io.take_ext_int_start_d2 <= csr.io.take_ext_int_start_d2 @[dec_tlu_ctl.scala 791:44] + int_exc.io.take_ext_int_start_d3 <= csr.io.take_ext_int_start_d3 @[dec_tlu_ctl.scala 792:44] + ext_int_freeze <= int_exc.io.ext_int_freeze @[dec_tlu_ctl.scala 796:43] + take_ext_int <= int_exc.io.take_ext_int @[dec_tlu_ctl.scala 797:43] + fast_int_meicpct <= int_exc.io.fast_int_meicpct @[dec_tlu_ctl.scala 798:43] + ignore_ext_int_due_to_lsu_stall <= int_exc.io.ignore_ext_int_due_to_lsu_stall @[dec_tlu_ctl.scala 799:43] + take_ce_int <= int_exc.io.take_ce_int @[dec_tlu_ctl.scala 800:43] + take_soft_int <= int_exc.io.take_soft_int @[dec_tlu_ctl.scala 801:43] + take_timer_int <= int_exc.io.take_timer_int @[dec_tlu_ctl.scala 802:43] + take_int_timer0_int <= int_exc.io.take_int_timer0_int @[dec_tlu_ctl.scala 803:43] + take_int_timer1_int <= int_exc.io.take_int_timer1_int @[dec_tlu_ctl.scala 804:43] + take_reset <= int_exc.io.take_reset @[dec_tlu_ctl.scala 805:43] + take_nmi <= int_exc.io.take_nmi @[dec_tlu_ctl.scala 806:43] + synchronous_flush_r <= int_exc.io.synchronous_flush_r @[dec_tlu_ctl.scala 807:43] + tlu_flush_lower_r <= int_exc.io.tlu_flush_lower_r @[dec_tlu_ctl.scala 808:43] + io.dec_tlu_flush_lower_wb <= int_exc.io.dec_tlu_flush_lower_wb @[dec_tlu_ctl.scala 809:46] + io.tlu_exu.dec_tlu_flush_lower_r <= int_exc.io.dec_tlu_flush_lower_r @[dec_tlu_ctl.scala 810:54] + io.tlu_exu.dec_tlu_flush_path_r <= int_exc.io.dec_tlu_flush_path_r @[dec_tlu_ctl.scala 811:54] + interrupt_valid_r_d1 <= int_exc.io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 812:43] + exc_or_int_valid_r_d1 <= int_exc.io.exc_or_int_valid_r_d1 @[dec_tlu_ctl.scala 813:43] + take_nmi_r_d1 <= int_exc.io.take_nmi_r_d1 @[dec_tlu_ctl.scala 814:43] + pause_expired_wb <= int_exc.io.pause_expired_wb @[dec_tlu_ctl.scala 815:43] + interrupt_valid_r <= int_exc.io.interrupt_valid_r @[dec_tlu_ctl.scala 816:43] + csr.io.ext_int_freeze <= int_exc.io.ext_int_freeze @[dec_tlu_ctl.scala 820:32] + csr.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 821:50] + csr.io.free_l2clk <= io.free_l2clk @[dec_tlu_ctl.scala 822:50] + csr.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 823:50] + csr.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 824:50] + csr.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 825:50] + csr.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 826:50] + csr.io.dec_csr_wen_unq_d <= io.dec_csr_wen_unq_d @[dec_tlu_ctl.scala 827:50] + csr.io.dec_i0_decode_d <= io.dec_i0_decode_d @[dec_tlu_ctl.scala 828:50] + csr.io.ifu_ic_debug_rd_data_valid <= io.tlu_mem.ifu_ic_debug_rd_data_valid @[dec_tlu_ctl.scala 829:50] + csr.io.ifu_pmu_bus_trxn <= io.tlu_mem.ifu_pmu_bus_trxn @[dec_tlu_ctl.scala 830:50] + csr.io.dma_iccm_stall_any <= io.tlu_dma.dma_iccm_stall_any @[dec_tlu_ctl.scala 831:50] + csr.io.dma_dccm_stall_any <= io.tlu_dma.dma_dccm_stall_any @[dec_tlu_ctl.scala 832:50] + csr.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec_tlu_ctl.scala 833:50] + csr.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[dec_tlu_ctl.scala 834:50] + csr.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[dec_tlu_ctl.scala 835:50] + csr.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[dec_tlu_ctl.scala 836:50] + csr.io.ifu_pmu_fetch_stall <= io.tlu_ifc.ifu_pmu_fetch_stall @[dec_tlu_ctl.scala 837:50] + csr.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec_tlu_ctl.scala 838:50] + csr.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[dec_tlu_ctl.scala 838:50] + csr.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec_tlu_ctl.scala 838:50] + csr.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[dec_tlu_ctl.scala 838:50] + csr.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[dec_tlu_ctl.scala 838:50] + csr.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[dec_tlu_ctl.scala 838:50] + csr.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[dec_tlu_ctl.scala 838:50] + csr.io.dec_tlu_packet_r.icaf_second <= io.dec_tlu_packet_r.icaf_second @[dec_tlu_ctl.scala 838:50] + csr.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[dec_tlu_ctl.scala 838:50] + csr.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[dec_tlu_ctl.scala 838:50] + csr.io.exu_pmu_i0_br_ataken <= io.tlu_exu.exu_pmu_i0_br_ataken @[dec_tlu_ctl.scala 839:50] + csr.io.exu_pmu_i0_br_misp <= io.tlu_exu.exu_pmu_i0_br_misp @[dec_tlu_ctl.scala 840:50] + csr.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[dec_tlu_ctl.scala 841:50] + csr.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[dec_tlu_ctl.scala 842:50] + csr.io.exu_pmu_i0_pc4 <= io.tlu_exu.exu_pmu_i0_pc4 @[dec_tlu_ctl.scala 843:50] + csr.io.ifu_pmu_ic_miss <= io.tlu_mem.ifu_pmu_ic_miss @[dec_tlu_ctl.scala 844:50] + csr.io.ifu_pmu_ic_hit <= io.tlu_mem.ifu_pmu_ic_hit @[dec_tlu_ctl.scala 845:50] + csr.io.dec_csr_wen_r <= io.dec_csr_wen_r @[dec_tlu_ctl.scala 846:50] + csr.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[dec_tlu_ctl.scala 847:50] + csr.io.dma_pmu_dccm_write <= io.tlu_dma.dma_pmu_dccm_write @[dec_tlu_ctl.scala 848:50] + csr.io.dma_pmu_dccm_read <= io.tlu_dma.dma_pmu_dccm_read @[dec_tlu_ctl.scala 849:50] + csr.io.dma_pmu_any_write <= io.tlu_dma.dma_pmu_any_write @[dec_tlu_ctl.scala 850:50] + csr.io.dma_pmu_any_read <= io.tlu_dma.dma_pmu_any_read @[dec_tlu_ctl.scala 851:50] + csr.io.lsu_pmu_bus_busy <= io.tlu_busbuff.lsu_pmu_bus_busy @[dec_tlu_ctl.scala 852:50] + csr.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[dec_tlu_ctl.scala 853:50] + csr.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 854:50] + csr.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[dec_tlu_ctl.scala 855:50] + csr.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[dec_tlu_ctl.scala 856:50] + csr.io.ifu_pmu_bus_busy <= io.tlu_mem.ifu_pmu_bus_busy @[dec_tlu_ctl.scala 857:50] + csr.io.lsu_pmu_bus_error <= io.tlu_busbuff.lsu_pmu_bus_error @[dec_tlu_ctl.scala 858:50] + csr.io.ifu_pmu_bus_error <= io.tlu_mem.ifu_pmu_bus_error @[dec_tlu_ctl.scala 859:50] + csr.io.lsu_pmu_bus_misaligned <= io.tlu_busbuff.lsu_pmu_bus_misaligned @[dec_tlu_ctl.scala 860:50] + csr.io.lsu_pmu_bus_trxn <= io.tlu_busbuff.lsu_pmu_bus_trxn @[dec_tlu_ctl.scala 861:50] + csr.io.ifu_ic_debug_rd_data <= io.tlu_mem.ifu_ic_debug_rd_data @[dec_tlu_ctl.scala 862:50] + csr.io.pic_pl <= io.dec_pic.pic_pl @[dec_tlu_ctl.scala 863:50] + csr.io.pic_claimid <= io.dec_pic.pic_claimid @[dec_tlu_ctl.scala 864:50] + csr.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[dec_tlu_ctl.scala 865:50] + csr.io.lsu_imprecise_error_addr_any <= io.tlu_busbuff.lsu_imprecise_error_addr_any @[dec_tlu_ctl.scala 866:50] + csr.io.lsu_imprecise_error_load_any <= io.tlu_busbuff.lsu_imprecise_error_load_any @[dec_tlu_ctl.scala 867:50] + csr.io.lsu_imprecise_error_store_any <= io.tlu_busbuff.lsu_imprecise_error_store_any @[dec_tlu_ctl.scala 868:50] + csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 869:50] + csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 870:50] + csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 870:50] + csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 870:50] + csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 870:50] + csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 870:50] + csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 870:50] + csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 871:50] + csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 872:50] + csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 873:50] + csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 874:50] + csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 875:50] + csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 876:50] + csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 877:50] + io.dec_pic.dec_tlu_meicurpl <= csr.io.dec_tlu_meicurpl @[dec_tlu_ctl.scala 878:58] + io.tlu_exu.dec_tlu_meihap <= csr.io.dec_tlu_meihap @[dec_tlu_ctl.scala 879:58] + io.dec_pic.dec_tlu_meipt <= csr.io.dec_tlu_meipt @[dec_tlu_ctl.scala 880:58] + io.dec_tlu_int_valid_wb1 <= csr.io.dec_tlu_int_valid_wb1 @[dec_tlu_ctl.scala 881:50] + io.dec_tlu_i0_exc_valid_wb1 <= csr.io.dec_tlu_i0_exc_valid_wb1 @[dec_tlu_ctl.scala 882:50] + io.dec_tlu_i0_valid_wb1 <= csr.io.dec_tlu_i0_valid_wb1 @[dec_tlu_ctl.scala 883:50] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[dec_tlu_ctl.scala 884:58] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[dec_tlu_ctl.scala 884:58] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics <= csr.io.dec_tlu_ic_diag_pkt.icache_dicawics @[dec_tlu_ctl.scala 884:58] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata <= csr.io.dec_tlu_ic_diag_pkt.icache_wrdata @[dec_tlu_ctl.scala 884:58] + io.trigger_pkt_any[0].tdata2 <= csr.io.trigger_pkt_any[0].tdata2 @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[0].m <= csr.io.trigger_pkt_any[0].m @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[0].match_pkt <= csr.io.trigger_pkt_any[0].match_pkt @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[1].match_pkt <= csr.io.trigger_pkt_any[1].match_pkt @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[2].match_pkt <= csr.io.trigger_pkt_any[2].match_pkt @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[3].match_pkt <= csr.io.trigger_pkt_any[3].match_pkt @[dec_tlu_ctl.scala 885:46] + io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[dec_tlu_ctl.scala 885:46] + io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[dec_tlu_ctl.scala 886:46] + io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[dec_tlu_ctl.scala 887:46] + io.dec_tlu_perfcnt0 <= csr.io.dec_tlu_perfcnt0 @[dec_tlu_ctl.scala 888:46] + io.dec_tlu_perfcnt1 <= csr.io.dec_tlu_perfcnt1 @[dec_tlu_ctl.scala 889:46] + io.dec_tlu_perfcnt2 <= csr.io.dec_tlu_perfcnt2 @[dec_tlu_ctl.scala 890:46] + io.dec_tlu_perfcnt3 <= csr.io.dec_tlu_perfcnt3 @[dec_tlu_ctl.scala 891:46] + io.dec_tlu_misc_clk_override <= csr.io.dec_tlu_misc_clk_override @[dec_tlu_ctl.scala 892:46] + io.dec_tlu_picio_clk_override <= csr.io.dec_tlu_picio_clk_override @[dec_tlu_ctl.scala 893:46] + io.dec_tlu_dec_clk_override <= csr.io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 894:46] + io.dec_tlu_ifu_clk_override <= csr.io.dec_tlu_ifu_clk_override @[dec_tlu_ctl.scala 895:46] + io.dec_tlu_lsu_clk_override <= csr.io.dec_tlu_lsu_clk_override @[dec_tlu_ctl.scala 896:46] + io.dec_tlu_bus_clk_override <= csr.io.dec_tlu_bus_clk_override @[dec_tlu_ctl.scala 897:46] + io.dec_tlu_pic_clk_override <= csr.io.dec_tlu_pic_clk_override @[dec_tlu_ctl.scala 898:46] + io.dec_tlu_dccm_clk_override <= csr.io.dec_tlu_dccm_clk_override @[dec_tlu_ctl.scala 899:46] + io.dec_tlu_icm_clk_override <= csr.io.dec_tlu_icm_clk_override @[dec_tlu_ctl.scala 900:46] + io.dec_csr_rddata_d <= csr.io.dec_csr_rddata_d @[dec_tlu_ctl.scala 901:46] + io.dec_tlu_pipelining_disable <= csr.io.dec_tlu_pipelining_disable @[dec_tlu_ctl.scala 902:46] + io.dec_tlu_wr_pause_r <= csr.io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 903:46] + io.tlu_ifc.dec_tlu_mrac_ff <= csr.io.dec_tlu_mrac_ff @[dec_tlu_ctl.scala 904:54] + io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= csr.io.dec_tlu_wb_coalescing_disable @[dec_tlu_ctl.scala 905:58] + io.tlu_bp.dec_tlu_bpred_disable <= csr.io.dec_tlu_bpred_disable @[dec_tlu_ctl.scala 906:53] + io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= csr.io.dec_tlu_sideeffect_posted_disable @[dec_tlu_ctl.scala 907:58] + io.tlu_mem.dec_tlu_core_ecc_disable <= csr.io.dec_tlu_core_ecc_disable @[dec_tlu_ctl.scala 908:54] + io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= csr.io.dec_tlu_external_ldfwd_disable @[dec_tlu_ctl.scala 909:58] + io.tlu_dma.dec_tlu_dma_qos_prty <= csr.io.dec_tlu_dma_qos_prty @[dec_tlu_ctl.scala 910:54] + io.dec_tlu_trace_disable <= csr.io.dec_tlu_trace_disable @[dec_tlu_ctl.scala 911:49] + csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 912:50] + csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 913:50] + csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 913:50] + csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 913:50] + csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 913:50] + csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 913:50] + csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 913:50] + csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 914:50] + csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 915:50] + csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 916:50] + csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 917:50] + csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 918:50] + csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 919:50] + csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 920:50] + csr.io.rfpc_i0_r <= rfpc_i0_r @[dec_tlu_ctl.scala 923:45] + csr.io.i0_trigger_hit_r <= i0_trigger_hit_r @[dec_tlu_ctl.scala 924:45] + csr.io.exc_or_int_valid_r <= int_exc.io.exc_or_int_valid_r @[dec_tlu_ctl.scala 925:45] + csr.io.mret_r <= mret_r @[dec_tlu_ctl.scala 926:45] + csr.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[dec_tlu_ctl.scala 927:45] + csr.io.dec_timer_t0_pulse <= int_timers.io.dec_timer_t0_pulse @[dec_tlu_ctl.scala 928:45] + csr.io.dec_timer_t1_pulse <= int_timers.io.dec_timer_t1_pulse @[dec_tlu_ctl.scala 929:45] + csr.io.timer_int_sync <= timer_int_sync @[dec_tlu_ctl.scala 930:45] + csr.io.soft_int_sync <= soft_int_sync @[dec_tlu_ctl.scala 931:45] + csr.io.csr_wr_clk <= clock @[dec_tlu_ctl.scala 932:45] + csr.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 933:45] + csr.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 934:45] + csr.io.lsu_fir_error <= io.lsu_fir_error @[dec_tlu_ctl.scala 935:45] + csr.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 936:45] + csr.io.dec_tlu_flush_noredir_r_d1 <= dec_tlu_flush_noredir_r_d1 @[dec_tlu_ctl.scala 937:45] + csr.io.tlu_flush_path_r_d1 <= int_exc.io.tlu_flush_path_r_d1 @[dec_tlu_ctl.scala 938:45] + csr.io.reset_delayed <= reset_delayed @[dec_tlu_ctl.scala 939:45] + csr.io.interrupt_valid_r <= interrupt_valid_r @[dec_tlu_ctl.scala 940:45] + csr.io.i0_exception_valid_r <= int_exc.io.i0_exception_valid_r @[dec_tlu_ctl.scala 941:45] + csr.io.lsu_exc_valid_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 942:45] + csr.io.mepc_trigger_hit_sel_pc_r <= mepc_trigger_hit_sel_pc_r @[dec_tlu_ctl.scala 943:45] + csr.io.lsu_single_ecc_error_r <= io.lsu_single_ecc_error_incr @[dec_tlu_ctl.scala 944:45] + csr.io.e4e5_int_clk <= clock @[dec_tlu_ctl.scala 945:45] + csr.io.lsu_i0_exc_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 946:45] + csr.io.inst_acc_r <= inst_acc_r @[dec_tlu_ctl.scala 947:45] + csr.io.inst_acc_second_r <= io.dec_tlu_packet_r.icaf_second @[dec_tlu_ctl.scala 948:45] + csr.io.take_nmi <= take_nmi @[dec_tlu_ctl.scala 949:45] + csr.io.lsu_error_pkt_addr_r <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 950:45] + csr.io.exc_cause_r <= int_exc.io.exc_cause_r @[dec_tlu_ctl.scala 951:45] + csr.io.i0_valid_wb <= int_exc.io.i0_valid_wb @[dec_tlu_ctl.scala 952:45] + csr.io.exc_or_int_valid_r_d1 <= exc_or_int_valid_r_d1 @[dec_tlu_ctl.scala 953:45] + csr.io.interrupt_valid_r_d1 <= interrupt_valid_r_d1 @[dec_tlu_ctl.scala 954:45] + csr.io.clk_override <= io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 955:45] + csr.io.i0_exception_valid_r_d1 <= int_exc.io.i0_exception_valid_r_d1 @[dec_tlu_ctl.scala 956:45] + csr.io.exc_cause_wb <= int_exc.io.exc_cause_wb @[dec_tlu_ctl.scala 958:45] + csr.io.nmi_lsu_store_type <= nmi_lsu_store_type @[dec_tlu_ctl.scala 959:45] + csr.io.nmi_lsu_load_type <= nmi_lsu_load_type @[dec_tlu_ctl.scala 960:45] + csr.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 961:45] + csr.io.ebreak_r <= ebreak_r @[dec_tlu_ctl.scala 962:45] + csr.io.ecall_r <= ecall_r @[dec_tlu_ctl.scala 963:45] + csr.io.illegal_r <= illegal_r @[dec_tlu_ctl.scala 964:45] + mdseac_locked_f <= csr.io.mdseac_locked_f @[dec_tlu_ctl.scala 965:27] + csr.io.nmi_int_detected_f <= nmi_int_detected_f @[dec_tlu_ctl.scala 966:45] + csr.io.internal_dbg_halt_mode_f2 <= internal_dbg_halt_mode_f2 @[dec_tlu_ctl.scala 967:45] + csr.io.ic_perr_r <= ic_perr_r @[dec_tlu_ctl.scala 969:45] + csr.io.iccm_sbecc_r <= iccm_sbecc_r @[dec_tlu_ctl.scala 970:45] + csr.io.ifu_miss_state_idle_f <= ifu_miss_state_idle_f @[dec_tlu_ctl.scala 972:45] + csr.io.lsu_idle_any_f <= lsu_idle_any_f @[dec_tlu_ctl.scala 973:45] + csr.io.dbg_tlu_halted_f <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 974:45] + csr.io.dbg_tlu_halted <= dbg_tlu_halted @[dec_tlu_ctl.scala 975:45] + csr.io.debug_halt_req_f <= debug_halt_req_f @[dec_tlu_ctl.scala 976:59] + csr.io.take_ext_int_start <= take_ext_int_start @[dec_tlu_ctl.scala 977:55] + csr.io.trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r_d1 @[dec_tlu_ctl.scala 978:43] + csr.io.trigger_hit_r_d1 <= int_exc.io.trigger_hit_r_d1 @[dec_tlu_ctl.scala 979:43] + csr.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[dec_tlu_ctl.scala 980:43] + csr.io.ebreak_to_debug_mode_r_d1 <= ebreak_to_debug_mode_r_d1 @[dec_tlu_ctl.scala 981:45] + csr.io.debug_halt_req <= debug_halt_req @[dec_tlu_ctl.scala 982:51] + csr.io.allow_dbg_halt_csr_write <= allow_dbg_halt_csr_write @[dec_tlu_ctl.scala 983:45] + csr.io.internal_dbg_halt_mode_f <= debug_mode_status @[dec_tlu_ctl.scala 984:45] + csr.io.enter_debug_halt_req <= enter_debug_halt_req @[dec_tlu_ctl.scala 985:45] + csr.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 986:45] + csr.io.request_debug_mode_done <= request_debug_mode_done @[dec_tlu_ctl.scala 987:45] + csr.io.request_debug_mode_r <= request_debug_mode_r @[dec_tlu_ctl.scala 988:45] + csr.io.update_hit_bit_r <= update_hit_bit_r @[dec_tlu_ctl.scala 989:45] + csr.io.take_timer_int <= take_timer_int @[dec_tlu_ctl.scala 990:45] + csr.io.take_int_timer0_int <= take_int_timer0_int @[dec_tlu_ctl.scala 991:45] + csr.io.take_int_timer1_int <= take_int_timer1_int @[dec_tlu_ctl.scala 992:45] + csr.io.take_ext_int <= take_ext_int @[dec_tlu_ctl.scala 993:45] + csr.io.tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 994:45] + csr.io.dec_tlu_br0_error_r <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 995:45] + csr.io.dec_tlu_br0_start_error_r <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 996:45] + csr.io.lsu_pmu_load_external_r <= lsu_pmu_load_external_r @[dec_tlu_ctl.scala 997:45] + csr.io.lsu_pmu_store_external_r <= lsu_pmu_store_external_r @[dec_tlu_ctl.scala 998:45] + csr.io.trigger_enabled <= trigger_enabled @[dec_tlu_ctl.scala 999:45] + csr.io.csr_pkt.legal <= csr_pkt.legal @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.postsync <= csr_pkt.postsync @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.presync <= csr_pkt.presync @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 1000:45] + csr.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[dec_tlu_ctl.scala 1000:45] + npc_r <= csr.io.npc_r @[dec_tlu_ctl.scala 1002:37] + npc_r_d1 <= csr.io.npc_r_d1 @[dec_tlu_ctl.scala 1003:37] + mie_ns <= csr.io.mie_ns @[dec_tlu_ctl.scala 1004:37] + mepc <= csr.io.mepc @[dec_tlu_ctl.scala 1005:37] + mdseac_locked_ns <= csr.io.mdseac_locked_ns @[dec_tlu_ctl.scala 1006:37] + force_halt <= csr.io.force_halt @[dec_tlu_ctl.scala 1007:37] + dpc <= csr.io.dpc @[dec_tlu_ctl.scala 1008:37] + mstatus_mie_ns <= csr.io.mstatus_mie_ns @[dec_tlu_ctl.scala 1009:37] + dec_csr_wen_r_mod <= csr.io.dec_csr_wen_r_mod @[dec_tlu_ctl.scala 1010:37] + fw_halt_req <= csr.io.fw_halt_req @[dec_tlu_ctl.scala 1011:37] + mstatus <= csr.io.mstatus @[dec_tlu_ctl.scala 1012:37] + dcsr <= csr.io.dcsr @[dec_tlu_ctl.scala 1013:37] + mtvec <= csr.io.mtvec @[dec_tlu_ctl.scala 1014:37] + mip <= csr.io.mip @[dec_tlu_ctl.scala 1015:37] + mtdata1_t[0] <= csr.io.mtdata1_t[0] @[dec_tlu_ctl.scala 1016:39] + mtdata1_t[1] <= csr.io.mtdata1_t[1] @[dec_tlu_ctl.scala 1016:39] + mtdata1_t[2] <= csr.io.mtdata1_t[2] @[dec_tlu_ctl.scala 1016:39] + mtdata1_t[3] <= csr.io.mtdata1_t[3] @[dec_tlu_ctl.scala 1016:39] + inst csr_read of dec_decode_csr_read @[dec_tlu_ctl.scala 1017:28] + csr_read.clock <= clock + csr_read.reset <= reset + csr_read.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 1018:37] + csr_pkt.legal <= csr_read.io.csr_pkt.legal @[dec_tlu_ctl.scala 1019:16] + csr_pkt.postsync <= csr_read.io.csr_pkt.postsync @[dec_tlu_ctl.scala 1019:16] + csr_pkt.presync <= csr_read.io.csr_pkt.presync @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_dicago <= csr_read.io.csr_pkt.csr_dicago @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_dicad1 <= csr_read.io.csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_dicad0 <= csr_read.io.csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_dicad0h <= csr_read.io.csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_dicawics <= csr_read.io.csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mfdhs <= csr_read.io.csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mfdht <= csr_read.io.csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mdccmect <= csr_read.io.csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_miccmect <= csr_read.io.csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_micect <= csr_read.io.csr_pkt.csr_micect @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_meicpct <= csr_read.io.csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mpmc <= csr_read.io.csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mitcnt1 <= csr_read.io.csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mitcnt0 <= csr_read.io.csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mitb1 <= csr_read.io.csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mitb0 <= csr_read.io.csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mitctl1 <= csr_read.io.csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mitctl0 <= csr_read.io.csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mcountinhibit <= csr_read.io.csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpme6 <= csr_read.io.csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpme5 <= csr_read.io.csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpme4 <= csr_read.io.csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpme3 <= csr_read.io.csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpmc6h <= csr_read.io.csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpmc5h <= csr_read.io.csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpmc4h <= csr_read.io.csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpmc3h <= csr_read.io.csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpmc6 <= csr_read.io.csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpmc5 <= csr_read.io.csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpmc4 <= csr_read.io.csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhpmc3 <= csr_read.io.csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mtdata2 <= csr_read.io.csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mtdata1 <= csr_read.io.csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mtsel <= csr_read.io.csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_dpc <= csr_read.io.csr_pkt.csr_dpc @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mfdc <= csr_read.io.csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mcgc <= csr_read.io.csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_dcsr <= csr_read.io.csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_meicidpl <= csr_read.io.csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_meicurpl <= csr_read.io.csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_meipt <= csr_read.io.csr_pkt.csr_meipt @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_meivt <= csr_read.io.csr_pkt.csr_meivt @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_meihap <= csr_read.io.csr_pkt.csr_meihap @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mdseac <= csr_read.io.csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_dmst <= csr_read.io.csr_pkt.csr_dmst @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mrac <= csr_read.io.csr_pkt.csr_mrac @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mtval <= csr_read.io.csr_pkt.csr_mtval @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mscause <= csr_read.io.csr_pkt.csr_mscause @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mcause <= csr_read.io.csr_pkt.csr_mcause @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mepc <= csr_read.io.csr_pkt.csr_mepc @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mscratch <= csr_read.io.csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_minstreth <= csr_read.io.csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_minstretl <= csr_read.io.csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mcycleh <= csr_read.io.csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mcyclel <= csr_read.io.csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mie <= csr_read.io.csr_pkt.csr_mie @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mip <= csr_read.io.csr_pkt.csr_mip @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mtvec <= csr_read.io.csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mstatus <= csr_read.io.csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mhartid <= csr_read.io.csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mimpid <= csr_read.io.csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_marchid <= csr_read.io.csr_pkt.csr_marchid @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_mvendorid <= csr_read.io.csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 1019:16] + csr_pkt.csr_misa <= csr_read.io.csr_pkt.csr_misa @[dec_tlu_ctl.scala 1019:16] + node _T_708 = and(csr_pkt.presync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1021:50] + node _T_709 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 1021:75] + node _T_710 = and(_T_708, _T_709) @[dec_tlu_ctl.scala 1021:73] + io.dec_tlu_presync_d <= _T_710 @[dec_tlu_ctl.scala 1021:31] + node _T_711 = and(csr_pkt.postsync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1022:51] + io.dec_tlu_postsync_d <= _T_711 @[dec_tlu_ctl.scala 1022:31] + node _T_712 = or(csr_pkt.csr_mitcnt0, csr_pkt.csr_mitcnt1) @[dec_tlu_ctl.scala 1025:58] + node _T_713 = or(_T_712, csr_pkt.csr_mitb0) @[dec_tlu_ctl.scala 1025:80] + node _T_714 = or(_T_713, csr_pkt.csr_mitb1) @[dec_tlu_ctl.scala 1025:100] + node _T_715 = or(_T_714, csr_pkt.csr_mitctl0) @[dec_tlu_ctl.scala 1025:120] + node _T_716 = or(_T_715, csr_pkt.csr_mitctl1) @[dec_tlu_ctl.scala 1025:142] + node _T_717 = not(UInt<1>("h01")) @[dec_tlu_ctl.scala 1025:167] + node conditionally_illegal = and(_T_716, _T_717) @[dec_tlu_ctl.scala 1025:165] + node _T_718 = or(csr_pkt.csr_dcsr, csr_pkt.csr_dpc) @[dec_tlu_ctl.scala 1026:63] + node _T_719 = or(_T_718, csr_pkt.csr_dmst) @[dec_tlu_ctl.scala 1026:81] + node _T_720 = or(_T_719, csr_pkt.csr_dicawics) @[dec_tlu_ctl.scala 1026:100] + node _T_721 = or(_T_720, csr_pkt.csr_dicad0) @[dec_tlu_ctl.scala 1026:123] + node _T_722 = or(_T_721, csr_pkt.csr_dicad0h) @[dec_tlu_ctl.scala 1026:144] + node _T_723 = or(_T_722, csr_pkt.csr_dicad1) @[dec_tlu_ctl.scala 1026:166] + node _T_724 = or(_T_723, csr_pkt.csr_dicago) @[dec_tlu_ctl.scala 1026:187] + node _T_725 = not(_T_724) @[dec_tlu_ctl.scala 1026:44] + node _T_726 = or(_T_725, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1026:209] + node _T_727 = and(csr_pkt.legal, _T_726) @[dec_tlu_ctl.scala 1026:41] + node _T_728 = not(fast_int_meicpct) @[dec_tlu_ctl.scala 1026:231] + node _T_729 = and(_T_727, _T_728) @[dec_tlu_ctl.scala 1026:229] + node _T_730 = not(conditionally_illegal) @[dec_tlu_ctl.scala 1026:251] + node valid_csr = and(_T_729, _T_730) @[dec_tlu_ctl.scala 1026:249] + node _T_731 = and(io.dec_csr_any_unq_d, valid_csr) @[dec_tlu_ctl.scala 1028:54] + node _T_732 = or(csr_pkt.csr_mvendorid, csr_pkt.csr_marchid) @[dec_tlu_ctl.scala 1028:115] + node _T_733 = or(_T_732, csr_pkt.csr_mimpid) @[dec_tlu_ctl.scala 1028:137] + node _T_734 = or(_T_733, csr_pkt.csr_mhartid) @[dec_tlu_ctl.scala 1028:158] + node _T_735 = or(_T_734, csr_pkt.csr_mdseac) @[dec_tlu_ctl.scala 1028:180] + node _T_736 = or(_T_735, csr_pkt.csr_meihap) @[dec_tlu_ctl.scala 1028:201] + node _T_737 = and(io.dec_csr_wen_unq_d, _T_736) @[dec_tlu_ctl.scala 1028:90] + node _T_738 = not(_T_737) @[dec_tlu_ctl.scala 1028:67] + node _T_739 = and(_T_731, _T_738) @[dec_tlu_ctl.scala 1028:65] + io.dec_csr_legal_d <= _T_739 @[dec_tlu_ctl.scala 1028:28] + diff --git a/dec_tlu_ctl.v b/dec_tlu_ctl.v new file mode 100644 index 00000000..d5534d2a --- /dev/null +++ b/dec_tlu_ctl.v @@ -0,0 +1,8413 @@ +module int_exc( + input clock, + input reset, + output io_mhwakeup_ready, + output io_ext_int_ready, + output io_ce_int_ready, + output io_soft_int_ready, + output io_timer_int_ready, + output io_int_timer0_int_hold, + output io_int_timer1_int_hold, + output io_internal_dbg_halt_timers, + output io_take_ext_int_start, + input io_ext_int_freeze_d1, + input io_take_ext_int_start_d1, + input io_take_ext_int_start_d2, + input io_take_ext_int_start_d3, + output io_ext_int_freeze, + output io_take_ext_int, + output io_fast_int_meicpct, + output io_ignore_ext_int_due_to_lsu_stall, + output io_take_ce_int, + output io_take_soft_int, + output io_take_timer_int, + output io_take_int_timer0_int, + output io_take_int_timer1_int, + output io_take_reset, + output io_take_nmi, + output io_synchronous_flush_r, + output io_tlu_flush_lower_r, + output io_dec_tlu_flush_lower_wb, + output io_dec_tlu_flush_lower_r, + output [30:0] io_dec_tlu_flush_path_r, + output io_interrupt_valid_r_d1, + output io_i0_exception_valid_r_d1, + output io_exc_or_int_valid_r_d1, + output [4:0] io_exc_cause_wb, + output io_i0_valid_wb, + output io_trigger_hit_r_d1, + output io_take_nmi_r_d1, + output io_interrupt_valid_r, + output [4:0] io_exc_cause_r, + output io_i0_exception_valid_r, + output [30:0] io_tlu_flush_path_r_d1, + output io_exc_or_int_valid_r, + input io_dec_csr_stall_int_ff, + input io_mstatus_mie_ns, + input [5:0] io_mip, + input [5:0] io_mie_ns, + input io_mret_r, + input io_pmu_fw_tlu_halted_f, + input io_int_timer0_int_hold_f, + input io_int_timer1_int_hold_f, + input io_internal_dbg_halt_mode_f, + input io_dcsr_single_step_running, + input io_internal_dbg_halt_mode, + input io_dec_tlu_i0_valid_r, + input io_internal_pmu_fw_halt_mode, + input io_i_cpu_halt_req_d1, + input io_ebreak_to_debug_mode_r, + input [1:0] io_lsu_fir_error, + input io_csr_pkt_csr_meicpct, + input io_dec_csr_any_unq_d, + input io_lsu_fastint_stall_any, + input io_reset_delayed, + input io_mpc_reset_run_req, + input io_nmi_int_detected, + input io_dcsr_single_step_running_f, + input io_dcsr_single_step_done_f, + input [15:0] io_dcsr, + input [30:0] io_mtvec, + input io_tlu_i0_commit_cmt, + input io_i0_trigger_hit_r, + input io_pause_expired_r, + input [30:0] io_nmi_vec, + input io_lsu_i0_rfnpc_r, + input io_fence_i_r, + input io_iccm_repair_state_rfnpc, + input io_i_cpu_run_req_d1, + input io_rfpc_i0_r, + input io_lsu_exc_valid_r, + input io_trigger_hit_dmode_r, + input io_take_halt, + input [30:0] io_rst_vec, + input [30:0] io_lsu_fir_addr, + input [30:0] io_dec_tlu_i0_pc_r, + input [30:0] io_npc_r, + input [30:0] io_mepc, + input io_debug_resume_req_f, + input [30:0] io_dpc, + input [30:0] io_npc_r_d1, + input io_tlu_flush_lower_r_d1, + input io_dec_tlu_dbg_halted, + input io_ebreak_r, + input io_ecall_r, + input io_illegal_r, + input io_inst_acc_r, + input io_lsu_i0_exc_r, + input io_lsu_error_pkt_r_bits_inst_type, + input io_lsu_error_pkt_r_bits_exc_type, + input io_dec_tlu_wr_pause_r_d1 +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; +`endif // RANDOMIZE_REG_INIT + wire _T = ~io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 3017:48] + wire lsu_exc_ma_r = io_lsu_i0_exc_r & _T; // @[dec_tlu_ctl.scala 3017:46] + wire lsu_exc_acc_r = io_lsu_i0_exc_r & io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 3018:46] + wire lsu_exc_st_r = io_lsu_i0_exc_r & io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 3019:46] + wire _T_1 = io_ebreak_r | io_ecall_r; // @[dec_tlu_ctl.scala 3031:49] + wire _T_2 = _T_1 | io_illegal_r; // @[dec_tlu_ctl.scala 3031:62] + wire _T_3 = _T_2 | io_inst_acc_r; // @[dec_tlu_ctl.scala 3031:77] + wire _T_4 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 3031:96] + wire _T_5 = _T_3 & _T_4; // @[dec_tlu_ctl.scala 3031:94] + wire _T_6 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 3031:112] + wire [4:0] _T_9 = io_take_nmi ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_10 = ~_T_9; // @[dec_tlu_ctl.scala 3039:27] + wire _T_20 = io_ebreak_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 3049:31] + wire _T_22 = ~lsu_exc_st_r; // @[dec_tlu_ctl.scala 3050:33] + wire _T_23 = lsu_exc_ma_r & _T_22; // @[dec_tlu_ctl.scala 3050:31] + wire _T_26 = lsu_exc_acc_r & _T_22; // @[dec_tlu_ctl.scala 3051:32] + wire _T_28 = lsu_exc_ma_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 3052:31] + wire _T_30 = lsu_exc_acc_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 3053:32] + wire [4:0] _T_32 = io_take_ext_int ? 5'hb : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_33 = io_take_timer_int ? 5'h7 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_34 = io_take_soft_int ? 5'h3 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_35 = io_take_int_timer0_int ? 5'h1d : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_36 = io_take_int_timer1_int ? 5'h1c : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_37 = io_take_ce_int ? 5'h1e : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_38 = io_illegal_r ? 5'h2 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_39 = io_ecall_r ? 5'hb : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_40 = io_inst_acc_r ? 5'h1 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_41 = _T_20 ? 5'h3 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_42 = _T_23 ? 5'h4 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_43 = _T_26 ? 5'h5 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_44 = _T_28 ? 5'h6 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_45 = _T_30 ? 5'h7 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_46 = _T_32 | _T_33; // @[Mux.scala 27:72] + wire [4:0] _T_47 = _T_46 | _T_34; // @[Mux.scala 27:72] + wire [4:0] _T_48 = _T_47 | _T_35; // @[Mux.scala 27:72] + wire [4:0] _T_49 = _T_48 | _T_36; // @[Mux.scala 27:72] + wire [4:0] _T_50 = _T_49 | _T_37; // @[Mux.scala 27:72] + wire [4:0] _T_51 = _T_50 | _T_38; // @[Mux.scala 27:72] + wire [4:0] _T_52 = _T_51 | _T_39; // @[Mux.scala 27:72] + wire [4:0] _T_53 = _T_52 | _T_40; // @[Mux.scala 27:72] + wire [4:0] _T_54 = _T_53 | _T_41; // @[Mux.scala 27:72] + wire [4:0] _T_55 = _T_54 | _T_42; // @[Mux.scala 27:72] + wire [4:0] _T_56 = _T_55 | _T_43; // @[Mux.scala 27:72] + wire [4:0] _T_57 = _T_56 | _T_44; // @[Mux.scala 27:72] + wire [4:0] _T_58 = _T_57 | _T_45; // @[Mux.scala 27:72] + wire _T_61 = ~io_dec_csr_stall_int_ff; // @[dec_tlu_ctl.scala 3064:31] + wire _T_62 = _T_61 & io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 3064:56] + wire _T_64 = _T_62 & io_mip[2]; // @[dec_tlu_ctl.scala 3064:76] + wire _T_66 = _T_64 & io_mie_ns[2]; // @[dec_tlu_ctl.scala 3064:97] + wire _T_73 = ~io_ignore_ext_int_due_to_lsu_stall; // @[dec_tlu_ctl.scala 3065:121] + wire [5:0] _T_77 = {{5'd0}, io_mip[5]}; // @[dec_tlu_ctl.scala 3066:84] + wire _T_79 = _T_62 & _T_77[0]; // @[dec_tlu_ctl.scala 3066:76] + wire _T_85 = _T_62 & io_mip[0]; // @[dec_tlu_ctl.scala 3067:76] + wire _T_91 = _T_62 & io_mip[1]; // @[dec_tlu_ctl.scala 3068:76] + wire int_timer0_int_possible = io_mstatus_mie_ns & io_mie_ns[4]; // @[dec_tlu_ctl.scala 3071:57] + wire [5:0] _T_95 = {{4'd0}, io_mip[5:4]}; // @[dec_tlu_ctl.scala 3072:42] + wire int_timer0_int_ready = _T_95[0] & int_timer0_int_possible; // @[dec_tlu_ctl.scala 3072:55] + wire int_timer1_int_possible = io_mstatus_mie_ns & io_mie_ns[3]; // @[dec_tlu_ctl.scala 3073:57] + wire [5:0] _T_98 = {{3'd0}, io_mip[5:3]}; // @[dec_tlu_ctl.scala 3074:42] + wire int_timer1_int_ready = _T_98[0] & int_timer1_int_possible; // @[dec_tlu_ctl.scala 3074:55] + wire _T_100 = io_dec_csr_stall_int_ff | io_synchronous_flush_r; // @[dec_tlu_ctl.scala 3078:57] + wire _T_101 = _T_100 | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 3078:82] + wire int_timer_stalled = _T_101 | io_mret_r; // @[dec_tlu_ctl.scala 3078:109] + wire _T_102 = io_pmu_fw_tlu_halted_f | int_timer_stalled; // @[dec_tlu_ctl.scala 3080:83] + wire _T_103 = int_timer0_int_ready & _T_102; // @[dec_tlu_ctl.scala 3080:57] + wire _T_104 = int_timer0_int_possible & io_int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 3080:132] + wire _T_105 = ~io_interrupt_valid_r; // @[dec_tlu_ctl.scala 3080:161] + wire _T_106 = _T_104 & _T_105; // @[dec_tlu_ctl.scala 3080:159] + wire _T_107 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 3080:185] + wire _T_108 = _T_106 & _T_107; // @[dec_tlu_ctl.scala 3080:183] + wire _T_109 = ~io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 3080:210] + wire _T_110 = _T_108 & _T_109; // @[dec_tlu_ctl.scala 3080:208] + wire _T_113 = int_timer1_int_ready & _T_102; // @[dec_tlu_ctl.scala 3081:57] + wire _T_114 = int_timer1_int_possible & io_int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 3081:132] + wire _T_116 = _T_114 & _T_105; // @[dec_tlu_ctl.scala 3081:159] + wire _T_118 = _T_116 & _T_107; // @[dec_tlu_ctl.scala 3081:183] + wire _T_120 = _T_118 & _T_109; // @[dec_tlu_ctl.scala 3081:208] + wire _T_122 = ~io_dcsr_single_step_running; // @[dec_tlu_ctl.scala 3083:70] + wire _T_125 = _T_122 | io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 3085:92] + wire _T_126 = io_internal_dbg_halt_mode & _T_125; // @[dec_tlu_ctl.scala 3085:60] + wire _T_127 = _T_126 | io_internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 3085:118] + wire _T_128 = _T_127 | io_i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 3085:149] + wire _T_129 = _T_128 | io_take_nmi; // @[dec_tlu_ctl.scala 3085:172] + wire _T_130 = _T_129 | io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 3085:186] + wire _T_131 = _T_130 | io_synchronous_flush_r; // @[dec_tlu_ctl.scala 3085:214] + wire _T_132 = _T_131 | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 3085:240] + wire _T_133 = _T_132 | io_mret_r; // @[dec_tlu_ctl.scala 3085:267] + wire block_interrupts = _T_133 | io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 3085:279] + wire _T_134 = ~block_interrupts; // @[dec_tlu_ctl.scala 3093:61] + wire _T_136 = io_take_ext_int_start | io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 3094:60] + wire _T_137 = _T_136 | io_take_ext_int_start_d2; // @[dec_tlu_ctl.scala 3094:87] + wire _T_139 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 3095:81] + wire _T_140 = ~_T_139; // @[dec_tlu_ctl.scala 3095:63] + wire _T_141 = io_take_ext_int_start_d3 & _T_140; // @[dec_tlu_ctl.scala 3095:61] + wire _T_143 = ~io_ext_int_ready; // @[dec_tlu_ctl.scala 3110:46] + wire _T_144 = io_ce_int_ready & _T_143; // @[dec_tlu_ctl.scala 3110:44] + wire _T_148 = io_soft_int_ready & _T_143; // @[dec_tlu_ctl.scala 3111:47] + wire _T_149 = ~io_ce_int_ready; // @[dec_tlu_ctl.scala 3111:69] + wire _T_150 = _T_148 & _T_149; // @[dec_tlu_ctl.scala 3111:67] + wire _T_153 = ~io_soft_int_ready; // @[dec_tlu_ctl.scala 3112:51] + wire _T_154 = io_timer_int_ready & _T_153; // @[dec_tlu_ctl.scala 3112:49] + wire _T_156 = _T_154 & _T_143; // @[dec_tlu_ctl.scala 3112:70] + wire _T_158 = _T_156 & _T_149; // @[dec_tlu_ctl.scala 3112:90] + wire _T_161 = int_timer0_int_ready | io_int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 3113:57] + wire _T_162 = _T_161 & int_timer0_int_possible; // @[dec_tlu_ctl.scala 3113:85] + wire _T_164 = _T_162 & _T_61; // @[dec_tlu_ctl.scala 3113:111] + wire _T_165 = ~io_timer_int_ready; // @[dec_tlu_ctl.scala 3113:140] + wire _T_166 = _T_164 & _T_165; // @[dec_tlu_ctl.scala 3113:138] + wire _T_168 = _T_166 & _T_153; // @[dec_tlu_ctl.scala 3113:160] + wire _T_170 = _T_168 & _T_143; // @[dec_tlu_ctl.scala 3113:181] + wire _T_172 = _T_170 & _T_149; // @[dec_tlu_ctl.scala 3113:201] + wire _T_175 = int_timer1_int_ready | io_int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 3114:57] + wire _T_176 = _T_175 & int_timer1_int_possible; // @[dec_tlu_ctl.scala 3114:85] + wire _T_178 = _T_176 & _T_61; // @[dec_tlu_ctl.scala 3114:111] + wire _T_180 = ~_T_161; // @[dec_tlu_ctl.scala 3114:140] + wire _T_181 = _T_178 & _T_180; // @[dec_tlu_ctl.scala 3114:138] + wire _T_183 = _T_181 & _T_165; // @[dec_tlu_ctl.scala 3114:191] + wire _T_185 = _T_183 & _T_153; // @[dec_tlu_ctl.scala 3114:213] + wire _T_187 = _T_185 & _T_143; // @[dec_tlu_ctl.scala 3114:234] + wire _T_189 = _T_187 & _T_149; // @[dec_tlu_ctl.scala 3114:254] + wire _T_193 = ~io_internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 3116:46] + wire _T_194 = io_nmi_int_detected & _T_193; // @[dec_tlu_ctl.scala 3116:44] + wire _T_195 = ~io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 3116:79] + wire _T_197 = io_dcsr_single_step_running_f & io_dcsr[11]; // @[dec_tlu_ctl.scala 3116:139] + wire _T_198 = ~io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 3116:164] + wire _T_199 = _T_197 & _T_198; // @[dec_tlu_ctl.scala 3116:162] + wire _T_200 = ~io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 3116:189] + wire _T_201 = _T_199 & _T_200; // @[dec_tlu_ctl.scala 3116:187] + wire _T_202 = _T_195 | _T_201; // @[dec_tlu_ctl.scala 3116:106] + wire _T_203 = _T_194 & _T_202; // @[dec_tlu_ctl.scala 3116:76] + wire _T_204 = ~io_synchronous_flush_r; // @[dec_tlu_ctl.scala 3116:220] + wire _T_205 = _T_203 & _T_204; // @[dec_tlu_ctl.scala 3116:218] + wire _T_206 = ~io_mret_r; // @[dec_tlu_ctl.scala 3116:246] + wire _T_207 = _T_205 & _T_206; // @[dec_tlu_ctl.scala 3116:244] + wire _T_208 = ~io_take_reset; // @[dec_tlu_ctl.scala 3116:259] + wire _T_209 = _T_207 & _T_208; // @[dec_tlu_ctl.scala 3116:257] + wire _T_210 = ~io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 3116:276] + wire _T_211 = _T_209 & _T_210; // @[dec_tlu_ctl.scala 3116:274] + wire _T_212 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 3116:306] + wire _T_214 = io_take_ext_int_start_d3 & _T_139; // @[dec_tlu_ctl.scala 3116:356] + wire _T_215 = _T_212 | _T_214; // @[dec_tlu_ctl.scala 3116:328] + wire _T_217 = io_take_ext_int | io_take_timer_int; // @[dec_tlu_ctl.scala 3120:49] + wire _T_218 = _T_217 | io_take_soft_int; // @[dec_tlu_ctl.scala 3120:69] + wire _T_219 = _T_218 | io_take_nmi; // @[dec_tlu_ctl.scala 3120:88] + wire _T_220 = _T_219 | io_take_ce_int; // @[dec_tlu_ctl.scala 3120:102] + wire _T_221 = _T_220 | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 3120:119] + wire [30:0] _T_224 = {io_mtvec[30:1],1'h0}; // @[Cat.scala 29:58] + wire [30:0] _T_226 = {25'h0,io_exc_cause_r,1'h0}; // @[Cat.scala 29:58] + wire [30:0] vectored_path = _T_224 + _T_226; // @[dec_tlu_ctl.scala 3125:59] + wire [30:0] _T_233 = io_mtvec[0] ? vectored_path : _T_224; // @[dec_tlu_ctl.scala 3126:69] + wire [30:0] interrupt_path = io_take_nmi ? io_nmi_vec : _T_233; // @[dec_tlu_ctl.scala 3126:33] + wire _T_234 = io_lsu_i0_rfnpc_r | io_fence_i_r; // @[dec_tlu_ctl.scala 3127:44] + wire _T_235 = _T_234 | io_iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 3127:59] + wire _T_237 = io_i_cpu_run_req_d1 & _T_105; // @[dec_tlu_ctl.scala 3127:111] + wire _T_238 = _T_235 | _T_237; // @[dec_tlu_ctl.scala 3127:88] + wire _T_240 = io_rfpc_i0_r & _T_198; // @[dec_tlu_ctl.scala 3127:152] + wire sel_npc_r = _T_238 | _T_240; // @[dec_tlu_ctl.scala 3127:136] + wire _T_241 = io_i_cpu_run_req_d1 & io_pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 3128:51] + wire sel_npc_resume = _T_241 | io_pause_expired_r; // @[dec_tlu_ctl.scala 3128:77] + wire _T_244 = io_i0_exception_valid_r | io_rfpc_i0_r; // @[dec_tlu_ctl.scala 3130:60] + wire _T_245 = _T_244 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 3130:75] + wire _T_246 = _T_245 | io_fence_i_r; // @[dec_tlu_ctl.scala 3130:96] + wire _T_247 = _T_246 | io_lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 3130:111] + wire _T_248 = _T_247 | io_iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 3130:131] + wire _T_249 = _T_248 | io_debug_resume_req_f; // @[dec_tlu_ctl.scala 3130:161] + wire _T_250 = _T_249 | sel_npc_resume; // @[dec_tlu_ctl.scala 3130:186] + wire _T_251 = _T_250 | io_dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 3130:204] + wire _T_253 = io_interrupt_valid_r | io_mret_r; // @[dec_tlu_ctl.scala 3131:54] + wire _T_254 = _T_253 | io_synchronous_flush_r; // @[dec_tlu_ctl.scala 3131:66] + wire _T_255 = _T_254 | io_take_halt; // @[dec_tlu_ctl.scala 3131:91] + wire _T_256 = _T_255 | io_take_reset; // @[dec_tlu_ctl.scala 3131:106] + wire _T_260 = ~io_take_nmi; // @[dec_tlu_ctl.scala 3135:29] + wire _T_262 = _T_260 & sel_npc_r; // @[dec_tlu_ctl.scala 3135:36] + wire _T_265 = _T_260 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 3136:36] + wire _T_267 = _T_265 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 3136:57] + wire _T_268 = ~sel_npc_r; // @[dec_tlu_ctl.scala 3136:98] + wire _T_269 = _T_267 & _T_268; // @[dec_tlu_ctl.scala 3136:87] + wire _T_271 = ~_T_141; // @[dec_tlu_ctl.scala 3137:59] + wire _T_272 = io_interrupt_valid_r & _T_271; // @[dec_tlu_ctl.scala 3137:45] + wire _T_273 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 3138:43] + wire _T_274 = ~io_trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 3138:89] + wire _T_275 = io_i0_trigger_hit_r & _T_274; // @[dec_tlu_ctl.scala 3138:87] + wire _T_276 = _T_273 | _T_275; // @[dec_tlu_ctl.scala 3138:64] + wire _T_278 = _T_276 & _T_105; // @[dec_tlu_ctl.scala 3138:115] + wire _T_280 = _T_278 & _T_271; // @[dec_tlu_ctl.scala 3138:139] + wire _T_285 = _T_260 & io_mret_r; // @[dec_tlu_ctl.scala 3139:31] + wire _T_288 = _T_260 & io_debug_resume_req_f; // @[dec_tlu_ctl.scala 3140:31] + wire _T_291 = _T_260 & sel_npc_resume; // @[dec_tlu_ctl.scala 3141:31] + wire [30:0] _T_293 = _T_141 ? io_lsu_fir_addr : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_294 = _T_262 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_295 = _T_269 ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_296 = _T_272 ? interrupt_path : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_297 = _T_280 ? _T_224 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_298 = _T_285 ? io_mepc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_299 = _T_288 ? io_dpc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_300 = _T_291 ? io_npc_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_301 = _T_293 | _T_294; // @[Mux.scala 27:72] + wire [30:0] _T_302 = _T_301 | _T_295; // @[Mux.scala 27:72] + wire [30:0] _T_303 = _T_302 | _T_296; // @[Mux.scala 27:72] + wire [30:0] _T_304 = _T_303 | _T_297; // @[Mux.scala 27:72] + wire [30:0] _T_305 = _T_304 | _T_298; // @[Mux.scala 27:72] + wire [30:0] _T_306 = _T_305 | _T_299; // @[Mux.scala 27:72] + wire [30:0] _T_307 = _T_306 | _T_300; // @[Mux.scala 27:72] + reg [30:0] _T_311; // @[Reg.scala 27:20] + wire _T_312 = io_lsu_exc_valid_r | io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 3152:53] + wire _T_313 = _T_312 | io_interrupt_valid_r; // @[dec_tlu_ctl.scala 3152:79] + reg _T_320; // @[Reg.scala 27:20] + wire _T_318 = io_interrupt_valid_r ^ _T_320; // @[lib.scala 448:21] + wire _T_319 = |_T_318; // @[lib.scala 448:29] + reg _T_324; // @[Reg.scala 27:20] + wire _T_322 = io_i0_exception_valid_r ^ _T_324; // @[lib.scala 448:21] + wire _T_323 = |_T_322; // @[lib.scala 448:29] + reg _T_328; // @[Reg.scala 27:20] + wire _T_326 = io_exc_or_int_valid_r ^ _T_328; // @[lib.scala 448:21] + wire _T_327 = |_T_326; // @[lib.scala 448:29] + reg [4:0] _T_332; // @[Reg.scala 27:20] + wire [4:0] _T_330 = io_exc_cause_r ^ _T_332; // @[lib.scala 448:21] + wire _T_331 = |_T_330; // @[lib.scala 448:29] + wire _T_333 = ~io_illegal_r; // @[dec_tlu_ctl.scala 3158:104] + wire _T_334 = io_tlu_i0_commit_cmt & _T_333; // @[dec_tlu_ctl.scala 3158:102] + reg _T_338; // @[Reg.scala 27:20] + wire _T_336 = _T_334 ^ _T_338; // @[lib.scala 448:21] + wire _T_337 = |_T_336; // @[lib.scala 448:29] + reg _T_342; // @[Reg.scala 27:20] + wire _T_340 = io_i0_trigger_hit_r ^ _T_342; // @[lib.scala 448:21] + wire _T_341 = |_T_340; // @[lib.scala 448:29] + reg _T_346; // @[Reg.scala 27:20] + wire _T_344 = io_take_nmi ^ _T_346; // @[lib.scala 448:21] + wire _T_345 = |_T_344; // @[lib.scala 448:29] + assign io_mhwakeup_ready = _T_64 & io_mie_ns[2]; // @[dec_tlu_ctl.scala 3064:28] + assign io_ext_int_ready = _T_66 & _T_73; // @[dec_tlu_ctl.scala 3065:28] + assign io_ce_int_ready = _T_79 & io_mie_ns[5]; // @[dec_tlu_ctl.scala 3066:28] + assign io_soft_int_ready = _T_85 & io_mie_ns[0]; // @[dec_tlu_ctl.scala 3067:28] + assign io_timer_int_ready = _T_91 & io_mie_ns[1]; // @[dec_tlu_ctl.scala 3068:28] + assign io_int_timer0_int_hold = _T_103 | _T_110; // @[dec_tlu_ctl.scala 3080:32] + assign io_int_timer1_int_hold = _T_113 | _T_120; // @[dec_tlu_ctl.scala 3081:32] + assign io_internal_dbg_halt_timers = io_internal_dbg_halt_mode_f & _T_122; // @[dec_tlu_ctl.scala 3083:37] + assign io_take_ext_int_start = io_ext_int_ready & _T_134; // @[dec_tlu_ctl.scala 3093:39] + assign io_ext_int_freeze = _T_137 | io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 3094:35] + assign io_take_ext_int = io_take_ext_int_start_d3 & _T_140; // @[dec_tlu_ctl.scala 3095:33] + assign io_fast_int_meicpct = io_csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 3096:37] + assign io_ignore_ext_int_due_to_lsu_stall = io_lsu_fastint_stall_any; // @[dec_tlu_ctl.scala 3097:52] + assign io_take_ce_int = _T_144 & _T_134; // @[dec_tlu_ctl.scala 3110:25] + assign io_take_soft_int = _T_150 & _T_134; // @[dec_tlu_ctl.scala 3111:26] + assign io_take_timer_int = _T_158 & _T_134; // @[dec_tlu_ctl.scala 3112:27] + assign io_take_int_timer0_int = _T_172 & _T_134; // @[dec_tlu_ctl.scala 3113:32] + assign io_take_int_timer1_int = _T_189 & _T_134; // @[dec_tlu_ctl.scala 3114:32] + assign io_take_reset = io_reset_delayed & io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 3115:23] + assign io_take_nmi = _T_211 & _T_215; // @[dec_tlu_ctl.scala 3116:21] + assign io_synchronous_flush_r = _T_251 | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 3130:33] + assign io_tlu_flush_lower_r = _T_256 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 3131:30] + assign io_dec_tlu_flush_lower_wb = io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 3146:41] + assign io_dec_tlu_flush_lower_r = io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 3148:41] + assign io_dec_tlu_flush_path_r = io_take_reset ? io_rst_vec : _T_307; // @[dec_tlu_ctl.scala 3149:41] + assign io_interrupt_valid_r_d1 = _T_320; // @[dec_tlu_ctl.scala 3154:59] + assign io_i0_exception_valid_r_d1 = _T_324; // @[dec_tlu_ctl.scala 3155:51] + assign io_exc_or_int_valid_r_d1 = _T_328; // @[dec_tlu_ctl.scala 3156:53] + assign io_exc_cause_wb = _T_332; // @[dec_tlu_ctl.scala 3157:65] + assign io_i0_valid_wb = _T_338; // @[dec_tlu_ctl.scala 3158:71] + assign io_trigger_hit_r_d1 = _T_342; // @[dec_tlu_ctl.scala 3159:63] + assign io_take_nmi_r_d1 = _T_346; // @[dec_tlu_ctl.scala 3160:73] + assign io_interrupt_valid_r = _T_221 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 3120:30] + assign io_exc_cause_r = _T_10 & _T_58; // @[dec_tlu_ctl.scala 3039:24] + assign io_i0_exception_valid_r = _T_5 & _T_6; // @[dec_tlu_ctl.scala 3031:33] + assign io_tlu_flush_path_r_d1 = _T_311; // @[dec_tlu_ctl.scala 3144:31] + assign io_exc_or_int_valid_r = _T_313 | _T_275; // @[dec_tlu_ctl.scala 3152:31] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T_311 = _RAND_0[30:0]; + _RAND_1 = {1{`RANDOM}}; + _T_320 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_324 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + _T_328 = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + _T_332 = _RAND_4[4:0]; + _RAND_5 = {1{`RANDOM}}; + _T_338 = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + _T_342 = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + _T_346 = _RAND_7[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_311 = 31'h0; + end + if (reset) begin + _T_320 = 1'h0; + end + if (reset) begin + _T_324 = 1'h0; + end + if (reset) begin + _T_328 = 1'h0; + end + if (reset) begin + _T_332 = 5'h0; + end + if (reset) begin + _T_338 = 1'h0; + end + if (reset) begin + _T_342 = 1'h0; + end + if (reset) begin + _T_346 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_311 <= 31'h0; + end else if (io_tlu_flush_lower_r) begin + if (io_take_reset) begin + _T_311 <= io_rst_vec; + end else begin + _T_311 <= _T_307; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_320 <= 1'h0; + end else if (_T_319) begin + _T_320 <= io_interrupt_valid_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_324 <= 1'h0; + end else if (_T_323) begin + _T_324 <= io_i0_exception_valid_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_328 <= 1'h0; + end else if (_T_327) begin + _T_328 <= io_exc_or_int_valid_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_332 <= 5'h0; + end else if (_T_331) begin + _T_332 <= io_exc_cause_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_338 <= 1'h0; + end else if (_T_337) begin + _T_338 <= _T_334; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_342 <= 1'h0; + end else if (_T_341) begin + _T_342 <= io_i0_trigger_hit_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_346 <= 1'h0; + end else if (_T_345) begin + _T_346 <= io_take_nmi; + end + end +endmodule +module perf_mux_and_flops( + input reset, + output io_mhpmc_inc_r_0, + output io_mhpmc_inc_r_1, + output io_mhpmc_inc_r_2, + output io_mhpmc_inc_r_3, + input [6:0] io_mcountinhibit, + input [9:0] io_mhpme_vec_0, + input [9:0] io_mhpme_vec_1, + input [9:0] io_mhpme_vec_2, + input [9:0] io_mhpme_vec_3, + input io_ifu_pmu_ic_hit, + input io_ifu_pmu_ic_miss, + input io_tlu_i0_commit_cmt, + input io_illegal_r, + input io_exu_pmu_i0_pc4, + input io_ifu_pmu_instr_aligned, + input io_dec_pmu_instr_decoded, + input [3:0] io_dec_tlu_packet_r_pmu_i0_itype, + input io_dec_tlu_packet_r_pmu_i0_br_unpred, + input io_dec_tlu_packet_r_pmu_divide, + input io_dec_tlu_packet_r_pmu_lsu_misaligned, + input io_exu_pmu_i0_br_misp, + input io_dec_pmu_decode_stall, + input io_exu_pmu_i0_br_ataken, + input io_ifu_pmu_fetch_stall, + input io_dec_pmu_postsync_stall, + input io_dec_pmu_presync_stall, + input io_lsu_store_stall_any, + input io_dma_dccm_stall_any, + input io_dma_iccm_stall_any, + input io_i0_exception_valid_r, + input io_dec_tlu_pmu_fw_halted, + input io_dma_pmu_any_read, + input io_dma_pmu_any_write, + input io_dma_pmu_dccm_read, + input io_dma_pmu_dccm_write, + input io_lsu_pmu_load_external_r, + input io_lsu_pmu_store_external_r, + output [1:0] io_mstatus, + input [5:0] io_mie, + input io_ifu_pmu_bus_trxn, + input io_lsu_pmu_bus_trxn, + input io_lsu_pmu_bus_misaligned, + input io_ifu_pmu_bus_error, + input io_lsu_pmu_bus_error, + input io_ifu_pmu_bus_busy, + input io_lsu_pmu_bus_busy, + input io_i0_trigger_hit_r, + input io_lsu_exc_valid_r, + input io_take_timer_int, + input io_take_int_timer0_int, + input io_take_int_timer1_int, + input io_take_ext_int, + input io_tlu_flush_lower_r, + input io_dec_tlu_br0_error_r, + input io_rfpc_i0_r, + input io_dec_tlu_br0_start_error_r, + output io_mcyclel_cout_f, + output io_minstret_enable_f, + output io_minstretl_cout_f, + output [3:0] io_meicidpl, + output io_icache_rd_valid_f, + output io_icache_wr_valid_f, + output io_mhpmc_inc_r_d1_0, + output io_mhpmc_inc_r_d1_1, + output io_mhpmc_inc_r_d1_2, + output io_mhpmc_inc_r_d1_3, + output io_perfcnt_halted_d1, + output io_mdseac_locked_f, + output io_lsu_single_ecc_error_r_d1, + output io_lsu_i0_exc_r_d1, + output io_take_ext_int_start_d1, + output io_take_ext_int_start_d2, + output io_take_ext_int_start_d3, + output io_ext_int_freeze_d1, + output [5:0] io_mip, + input io_mdseac_locked_ns, + input io_lsu_single_ecc_error_r, + input io_lsu_i0_exc_r, + input io_take_ext_int_start, + input io_ext_int_freeze, + input [5:0] io_mip_ns, + input io_mcyclel_cout, + input io_wr_mcycleh_r, + input io_mcyclel_cout_in, + input io_minstret_enable, + input io_minstretl_cout_ns, + input [3:0] io_meicidpl_ns, + input io_icache_rd_valid, + input io_icache_wr_valid, + input io_perfcnt_halted, + input [1:0] io_mstatus_ns, + input io_free_l2clk +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; +`endif // RANDOMIZE_REG_INIT + wire [3:0] _T_1 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1; // @[dec_tlu_ctl.scala 2795:66] + wire _T_3 = ~io_mcountinhibit[3]; // @[dec_tlu_ctl.scala 2797:40] + wire _T_4 = io_mhpme_vec_0 == 10'h1; // @[dec_tlu_ctl.scala 2798:42] + wire _T_6 = io_mhpme_vec_0 == 10'h2; // @[dec_tlu_ctl.scala 2799:42] + wire _T_8 = io_mhpme_vec_0 == 10'h3; // @[dec_tlu_ctl.scala 2800:42] + wire _T_10 = io_mhpme_vec_0 == 10'h4; // @[dec_tlu_ctl.scala 2801:42] + wire _T_12 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2801:104] + wire _T_13 = io_tlu_i0_commit_cmt & _T_12; // @[dec_tlu_ctl.scala 2801:102] + wire _T_14 = io_mhpme_vec_0 == 10'h5; // @[dec_tlu_ctl.scala 2802:42] + wire _T_16 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2802:104] + wire _T_17 = io_tlu_i0_commit_cmt & _T_16; // @[dec_tlu_ctl.scala 2802:102] + wire _T_19 = _T_17 & _T_12; // @[dec_tlu_ctl.scala 2802:123] + wire _T_20 = io_mhpme_vec_0 == 10'h6; // @[dec_tlu_ctl.scala 2803:42] + wire _T_22 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2803:102] + wire _T_24 = _T_22 & _T_12; // @[dec_tlu_ctl.scala 2803:123] + wire _T_25 = io_mhpme_vec_0 == 10'h7; // @[dec_tlu_ctl.scala 2805:42] + wire _T_27 = io_mhpme_vec_0 == 10'h8; // @[dec_tlu_ctl.scala 2806:42] + wire _T_29 = io_mhpme_vec_0 == 10'h1e; // @[dec_tlu_ctl.scala 2807:42] + wire _T_31 = io_mhpme_vec_0 == 10'h9; // @[dec_tlu_ctl.scala 2808:42] + wire _T_33 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2808:99] + wire _T_34 = io_mhpme_vec_0 == 10'ha; // @[dec_tlu_ctl.scala 2809:42] + wire _T_36 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2809:113] + wire _T_38 = _T_36 & _T_12; // @[dec_tlu_ctl.scala 2809:136] + wire _T_39 = io_mhpme_vec_0 == 10'hb; // @[dec_tlu_ctl.scala 2810:42] + wire _T_41 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2810:99] + wire _T_42 = io_mhpme_vec_0 == 10'hc; // @[dec_tlu_ctl.scala 2811:42] + wire _T_44 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2811:99] + wire _T_45 = io_mhpme_vec_0 == 10'hd; // @[dec_tlu_ctl.scala 2812:42] + wire _T_48 = _T_41 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2812:108] + wire _T_49 = io_mhpme_vec_0 == 10'he; // @[dec_tlu_ctl.scala 2813:42] + wire _T_53 = _T_44 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2813:109] + wire _T_54 = io_mhpme_vec_0 == 10'hf; // @[dec_tlu_ctl.scala 2815:42] + wire _T_56 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2815:97] + wire _T_57 = io_mhpme_vec_0 == 10'h10; // @[dec_tlu_ctl.scala 2816:42] + wire _T_59 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2816:97] + wire _T_60 = io_mhpme_vec_0 == 10'h12; // @[dec_tlu_ctl.scala 2817:42] + wire _T_62 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2817:97] + wire _T_63 = io_mhpme_vec_0 == 10'h11; // @[dec_tlu_ctl.scala 2818:42] + wire _T_65 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2818:97] + wire _T_66 = io_mhpme_vec_0 == 10'h13; // @[dec_tlu_ctl.scala 2819:42] + wire _T_68 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2819:97] + wire _T_69 = io_mhpme_vec_0 == 10'h14; // @[dec_tlu_ctl.scala 2820:42] + wire _T_71 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2820:97] + wire _T_72 = io_mhpme_vec_0 == 10'h15; // @[dec_tlu_ctl.scala 2821:42] + wire _T_74 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2821:97] + wire _T_75 = io_mhpme_vec_0 == 10'h16; // @[dec_tlu_ctl.scala 2822:42] + wire _T_77 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2822:97] + wire _T_78 = io_mhpme_vec_0 == 10'h17; // @[dec_tlu_ctl.scala 2823:42] + wire _T_80 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2823:97] + wire _T_81 = io_mhpme_vec_0 == 10'h18; // @[dec_tlu_ctl.scala 2824:42] + wire _T_83 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2824:97] + wire _T_84 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2824:130] + wire _T_85 = _T_83 | _T_84; // @[dec_tlu_ctl.scala 2824:109] + wire _T_86 = io_mhpme_vec_0 == 10'h19; // @[dec_tlu_ctl.scala 2826:42] + wire _T_88 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2826:103] + wire _T_90 = _T_88 & _T_12; // @[dec_tlu_ctl.scala 2826:126] + wire _T_91 = io_mhpme_vec_0 == 10'h1a; // @[dec_tlu_ctl.scala 2827:42] + wire _T_93 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2827:105] + wire _T_95 = _T_93 & _T_12; // @[dec_tlu_ctl.scala 2827:128] + wire _T_96 = io_mhpme_vec_0 == 10'h1b; // @[dec_tlu_ctl.scala 2828:42] + wire _T_98 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2828:118] + wire _T_100 = _T_98 & _T_12; // @[dec_tlu_ctl.scala 2828:141] + wire _T_101 = io_mhpme_vec_0 == 10'h1c; // @[dec_tlu_ctl.scala 2829:42] + wire _T_105 = io_mhpme_vec_0 == 10'h1f; // @[dec_tlu_ctl.scala 2831:42] + wire _T_107 = io_mhpme_vec_0 == 10'h20; // @[dec_tlu_ctl.scala 2832:42] + wire _T_109 = io_mhpme_vec_0 == 10'h22; // @[dec_tlu_ctl.scala 2833:42] + wire _T_111 = io_mhpme_vec_0 == 10'h23; // @[dec_tlu_ctl.scala 2834:42] + wire _T_113 = io_mhpme_vec_0 == 10'h24; // @[dec_tlu_ctl.scala 2835:42] + wire _T_115 = io_mhpme_vec_0 == 10'h25; // @[dec_tlu_ctl.scala 2836:42] + wire _T_117 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2836:106] + wire _T_118 = _T_117 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2836:128] + wire _T_119 = io_mhpme_vec_0 == 10'h26; // @[dec_tlu_ctl.scala 2837:42] + wire _T_121 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2837:100] + wire _T_122 = _T_121 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2837:125] + wire _T_123 = io_mhpme_vec_0 == 10'h27; // @[dec_tlu_ctl.scala 2838:42] + wire _T_125 = io_mhpme_vec_0 == 10'h28; // @[dec_tlu_ctl.scala 2839:42] + wire _T_127 = io_mhpme_vec_0 == 10'h29; // @[dec_tlu_ctl.scala 2840:42] + wire _T_129 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2840:105] + wire _T_130 = _T_129 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2840:137] + wire _T_131 = io_mhpme_vec_0 == 10'h2a; // @[dec_tlu_ctl.scala 2842:42] + wire _T_133 = io_mhpme_vec_0 == 10'h2b; // @[dec_tlu_ctl.scala 2843:42] + wire _T_135 = io_mhpme_vec_0 == 10'h2c; // @[dec_tlu_ctl.scala 2844:42] + wire _T_137 = io_mhpme_vec_0 == 10'h2d; // @[dec_tlu_ctl.scala 2845:42] + wire _T_139 = io_mhpme_vec_0 == 10'h2e; // @[dec_tlu_ctl.scala 2846:42] + wire _T_141 = io_mhpme_vec_0 == 10'h2f; // @[dec_tlu_ctl.scala 2847:42] + wire _T_143 = io_mhpme_vec_0 == 10'h30; // @[dec_tlu_ctl.scala 2848:42] + wire _T_145 = io_mhpme_vec_0 == 10'h31; // @[dec_tlu_ctl.scala 2849:42] + wire _T_149 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2849:81] + wire _T_150 = io_mhpme_vec_0 == 10'h32; // @[dec_tlu_ctl.scala 2850:42] + wire [5:0] _T_157 = io_mip & io_mie; // @[dec_tlu_ctl.scala 2850:121] + wire _T_158 = |_T_157; // @[dec_tlu_ctl.scala 2850:136] + wire _T_159 = _T_149 & _T_158; // @[dec_tlu_ctl.scala 2850:106] + wire _T_160 = io_mhpme_vec_0 == 10'h36; // @[dec_tlu_ctl.scala 2851:42] + wire _T_162 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2851:99] + wire _T_163 = io_mhpme_vec_0 == 10'h37; // @[dec_tlu_ctl.scala 2852:42] + wire _T_165 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2852:102] + wire _T_167 = _T_165 & _T_12; // @[dec_tlu_ctl.scala 2852:131] + wire _T_168 = io_mhpme_vec_0 == 10'h38; // @[dec_tlu_ctl.scala 2853:42] + wire _T_170 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2853:102] + wire _T_172 = _T_170 & _T_12; // @[dec_tlu_ctl.scala 2853:132] + wire _T_173 = io_mhpme_vec_0 == 10'h200; // @[dec_tlu_ctl.scala 2855:42] + wire _T_175 = io_mhpme_vec_0 == 10'h201; // @[dec_tlu_ctl.scala 2856:42] + wire _T_177 = io_mhpme_vec_0 == 10'h202; // @[dec_tlu_ctl.scala 2857:42] + wire _T_179 = io_mhpme_vec_0 == 10'h203; // @[dec_tlu_ctl.scala 2858:42] + wire _T_181 = io_mhpme_vec_0 == 10'h204; // @[dec_tlu_ctl.scala 2859:42] + wire _T_184 = _T_6 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_185 = _T_8 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_186 = _T_10 & _T_13; // @[Mux.scala 27:72] + wire _T_187 = _T_14 & _T_19; // @[Mux.scala 27:72] + wire _T_188 = _T_20 & _T_24; // @[Mux.scala 27:72] + wire _T_189 = _T_25 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_190 = _T_27 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_191 = _T_29 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_192 = _T_31 & _T_33; // @[Mux.scala 27:72] + wire _T_193 = _T_34 & _T_38; // @[Mux.scala 27:72] + wire _T_194 = _T_39 & _T_41; // @[Mux.scala 27:72] + wire _T_195 = _T_42 & _T_44; // @[Mux.scala 27:72] + wire _T_196 = _T_45 & _T_48; // @[Mux.scala 27:72] + wire _T_197 = _T_49 & _T_53; // @[Mux.scala 27:72] + wire _T_198 = _T_54 & _T_56; // @[Mux.scala 27:72] + wire _T_199 = _T_57 & _T_59; // @[Mux.scala 27:72] + wire _T_200 = _T_60 & _T_62; // @[Mux.scala 27:72] + wire _T_201 = _T_63 & _T_65; // @[Mux.scala 27:72] + wire _T_202 = _T_66 & _T_68; // @[Mux.scala 27:72] + wire _T_203 = _T_69 & _T_71; // @[Mux.scala 27:72] + wire _T_204 = _T_72 & _T_74; // @[Mux.scala 27:72] + wire _T_205 = _T_75 & _T_77; // @[Mux.scala 27:72] + wire _T_206 = _T_78 & _T_80; // @[Mux.scala 27:72] + wire _T_207 = _T_81 & _T_85; // @[Mux.scala 27:72] + wire _T_208 = _T_86 & _T_90; // @[Mux.scala 27:72] + wire _T_209 = _T_91 & _T_95; // @[Mux.scala 27:72] + wire _T_210 = _T_96 & _T_100; // @[Mux.scala 27:72] + wire _T_211 = _T_101 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_213 = _T_105 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_214 = _T_107 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_215 = _T_109 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_216 = _T_111 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_217 = _T_113 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_218 = _T_115 & _T_118; // @[Mux.scala 27:72] + wire _T_219 = _T_119 & _T_122; // @[Mux.scala 27:72] + wire _T_220 = _T_123 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_221 = _T_125 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_222 = _T_127 & _T_130; // @[Mux.scala 27:72] + wire _T_223 = _T_131 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_224 = _T_133 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_225 = _T_135 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_226 = _T_137 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_227 = _T_139 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_228 = _T_141 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_229 = _T_143 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_230 = _T_145 & _T_149; // @[Mux.scala 27:72] + wire _T_231 = _T_150 & _T_159; // @[Mux.scala 27:72] + wire _T_232 = _T_160 & _T_162; // @[Mux.scala 27:72] + wire _T_233 = _T_163 & _T_167; // @[Mux.scala 27:72] + wire _T_234 = _T_168 & _T_172; // @[Mux.scala 27:72] + wire _T_235 = _T_173 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_236 = _T_175 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_237 = _T_177 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_238 = _T_179 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_239 = _T_181 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_240 = _T_4 | _T_184; // @[Mux.scala 27:72] + wire _T_241 = _T_240 | _T_185; // @[Mux.scala 27:72] + wire _T_242 = _T_241 | _T_186; // @[Mux.scala 27:72] + wire _T_243 = _T_242 | _T_187; // @[Mux.scala 27:72] + wire _T_244 = _T_243 | _T_188; // @[Mux.scala 27:72] + wire _T_245 = _T_244 | _T_189; // @[Mux.scala 27:72] + wire _T_246 = _T_245 | _T_190; // @[Mux.scala 27:72] + wire _T_247 = _T_246 | _T_191; // @[Mux.scala 27:72] + wire _T_248 = _T_247 | _T_192; // @[Mux.scala 27:72] + wire _T_249 = _T_248 | _T_193; // @[Mux.scala 27:72] + wire _T_250 = _T_249 | _T_194; // @[Mux.scala 27:72] + wire _T_251 = _T_250 | _T_195; // @[Mux.scala 27:72] + wire _T_252 = _T_251 | _T_196; // @[Mux.scala 27:72] + wire _T_253 = _T_252 | _T_197; // @[Mux.scala 27:72] + wire _T_254 = _T_253 | _T_198; // @[Mux.scala 27:72] + wire _T_255 = _T_254 | _T_199; // @[Mux.scala 27:72] + wire _T_256 = _T_255 | _T_200; // @[Mux.scala 27:72] + wire _T_257 = _T_256 | _T_201; // @[Mux.scala 27:72] + wire _T_258 = _T_257 | _T_202; // @[Mux.scala 27:72] + wire _T_259 = _T_258 | _T_203; // @[Mux.scala 27:72] + wire _T_260 = _T_259 | _T_204; // @[Mux.scala 27:72] + wire _T_261 = _T_260 | _T_205; // @[Mux.scala 27:72] + wire _T_262 = _T_261 | _T_206; // @[Mux.scala 27:72] + wire _T_263 = _T_262 | _T_207; // @[Mux.scala 27:72] + wire _T_264 = _T_263 | _T_208; // @[Mux.scala 27:72] + wire _T_265 = _T_264 | _T_209; // @[Mux.scala 27:72] + wire _T_266 = _T_265 | _T_210; // @[Mux.scala 27:72] + wire _T_267 = _T_266 | _T_211; // @[Mux.scala 27:72] + wire _T_268 = _T_267 | _T_191; // @[Mux.scala 27:72] + wire _T_269 = _T_268 | _T_213; // @[Mux.scala 27:72] + wire _T_270 = _T_269 | _T_214; // @[Mux.scala 27:72] + wire _T_271 = _T_270 | _T_215; // @[Mux.scala 27:72] + wire _T_272 = _T_271 | _T_216; // @[Mux.scala 27:72] + wire _T_273 = _T_272 | _T_217; // @[Mux.scala 27:72] + wire _T_274 = _T_273 | _T_218; // @[Mux.scala 27:72] + wire _T_275 = _T_274 | _T_219; // @[Mux.scala 27:72] + wire _T_276 = _T_275 | _T_220; // @[Mux.scala 27:72] + wire _T_277 = _T_276 | _T_221; // @[Mux.scala 27:72] + wire _T_278 = _T_277 | _T_222; // @[Mux.scala 27:72] + wire _T_279 = _T_278 | _T_223; // @[Mux.scala 27:72] + wire _T_280 = _T_279 | _T_224; // @[Mux.scala 27:72] + wire _T_281 = _T_280 | _T_225; // @[Mux.scala 27:72] + wire _T_282 = _T_281 | _T_226; // @[Mux.scala 27:72] + wire _T_283 = _T_282 | _T_227; // @[Mux.scala 27:72] + wire _T_284 = _T_283 | _T_228; // @[Mux.scala 27:72] + wire _T_285 = _T_284 | _T_229; // @[Mux.scala 27:72] + wire _T_286 = _T_285 | _T_230; // @[Mux.scala 27:72] + wire _T_287 = _T_286 | _T_231; // @[Mux.scala 27:72] + wire _T_288 = _T_287 | _T_232; // @[Mux.scala 27:72] + wire _T_289 = _T_288 | _T_233; // @[Mux.scala 27:72] + wire _T_290 = _T_289 | _T_234; // @[Mux.scala 27:72] + wire _T_291 = _T_290 | _T_235; // @[Mux.scala 27:72] + wire _T_292 = _T_291 | _T_236; // @[Mux.scala 27:72] + wire _T_293 = _T_292 | _T_237; // @[Mux.scala 27:72] + wire _T_294 = _T_293 | _T_238; // @[Mux.scala 27:72] + wire _T_295 = _T_294 | _T_239; // @[Mux.scala 27:72] + wire _T_299 = ~io_mcountinhibit[4]; // @[dec_tlu_ctl.scala 2797:40] + wire _T_300 = io_mhpme_vec_1 == 10'h1; // @[dec_tlu_ctl.scala 2798:42] + wire _T_302 = io_mhpme_vec_1 == 10'h2; // @[dec_tlu_ctl.scala 2799:42] + wire _T_304 = io_mhpme_vec_1 == 10'h3; // @[dec_tlu_ctl.scala 2800:42] + wire _T_306 = io_mhpme_vec_1 == 10'h4; // @[dec_tlu_ctl.scala 2801:42] + wire _T_310 = io_mhpme_vec_1 == 10'h5; // @[dec_tlu_ctl.scala 2802:42] + wire _T_316 = io_mhpme_vec_1 == 10'h6; // @[dec_tlu_ctl.scala 2803:42] + wire _T_321 = io_mhpme_vec_1 == 10'h7; // @[dec_tlu_ctl.scala 2805:42] + wire _T_323 = io_mhpme_vec_1 == 10'h8; // @[dec_tlu_ctl.scala 2806:42] + wire _T_325 = io_mhpme_vec_1 == 10'h1e; // @[dec_tlu_ctl.scala 2807:42] + wire _T_327 = io_mhpme_vec_1 == 10'h9; // @[dec_tlu_ctl.scala 2808:42] + wire _T_330 = io_mhpme_vec_1 == 10'ha; // @[dec_tlu_ctl.scala 2809:42] + wire _T_335 = io_mhpme_vec_1 == 10'hb; // @[dec_tlu_ctl.scala 2810:42] + wire _T_338 = io_mhpme_vec_1 == 10'hc; // @[dec_tlu_ctl.scala 2811:42] + wire _T_341 = io_mhpme_vec_1 == 10'hd; // @[dec_tlu_ctl.scala 2812:42] + wire _T_345 = io_mhpme_vec_1 == 10'he; // @[dec_tlu_ctl.scala 2813:42] + wire _T_350 = io_mhpme_vec_1 == 10'hf; // @[dec_tlu_ctl.scala 2815:42] + wire _T_353 = io_mhpme_vec_1 == 10'h10; // @[dec_tlu_ctl.scala 2816:42] + wire _T_356 = io_mhpme_vec_1 == 10'h12; // @[dec_tlu_ctl.scala 2817:42] + wire _T_359 = io_mhpme_vec_1 == 10'h11; // @[dec_tlu_ctl.scala 2818:42] + wire _T_362 = io_mhpme_vec_1 == 10'h13; // @[dec_tlu_ctl.scala 2819:42] + wire _T_365 = io_mhpme_vec_1 == 10'h14; // @[dec_tlu_ctl.scala 2820:42] + wire _T_368 = io_mhpme_vec_1 == 10'h15; // @[dec_tlu_ctl.scala 2821:42] + wire _T_371 = io_mhpme_vec_1 == 10'h16; // @[dec_tlu_ctl.scala 2822:42] + wire _T_374 = io_mhpme_vec_1 == 10'h17; // @[dec_tlu_ctl.scala 2823:42] + wire _T_377 = io_mhpme_vec_1 == 10'h18; // @[dec_tlu_ctl.scala 2824:42] + wire _T_382 = io_mhpme_vec_1 == 10'h19; // @[dec_tlu_ctl.scala 2826:42] + wire _T_387 = io_mhpme_vec_1 == 10'h1a; // @[dec_tlu_ctl.scala 2827:42] + wire _T_392 = io_mhpme_vec_1 == 10'h1b; // @[dec_tlu_ctl.scala 2828:42] + wire _T_397 = io_mhpme_vec_1 == 10'h1c; // @[dec_tlu_ctl.scala 2829:42] + wire _T_401 = io_mhpme_vec_1 == 10'h1f; // @[dec_tlu_ctl.scala 2831:42] + wire _T_403 = io_mhpme_vec_1 == 10'h20; // @[dec_tlu_ctl.scala 2832:42] + wire _T_405 = io_mhpme_vec_1 == 10'h22; // @[dec_tlu_ctl.scala 2833:42] + wire _T_407 = io_mhpme_vec_1 == 10'h23; // @[dec_tlu_ctl.scala 2834:42] + wire _T_409 = io_mhpme_vec_1 == 10'h24; // @[dec_tlu_ctl.scala 2835:42] + wire _T_411 = io_mhpme_vec_1 == 10'h25; // @[dec_tlu_ctl.scala 2836:42] + wire _T_415 = io_mhpme_vec_1 == 10'h26; // @[dec_tlu_ctl.scala 2837:42] + wire _T_419 = io_mhpme_vec_1 == 10'h27; // @[dec_tlu_ctl.scala 2838:42] + wire _T_421 = io_mhpme_vec_1 == 10'h28; // @[dec_tlu_ctl.scala 2839:42] + wire _T_423 = io_mhpme_vec_1 == 10'h29; // @[dec_tlu_ctl.scala 2840:42] + wire _T_427 = io_mhpme_vec_1 == 10'h2a; // @[dec_tlu_ctl.scala 2842:42] + wire _T_429 = io_mhpme_vec_1 == 10'h2b; // @[dec_tlu_ctl.scala 2843:42] + wire _T_431 = io_mhpme_vec_1 == 10'h2c; // @[dec_tlu_ctl.scala 2844:42] + wire _T_433 = io_mhpme_vec_1 == 10'h2d; // @[dec_tlu_ctl.scala 2845:42] + wire _T_435 = io_mhpme_vec_1 == 10'h2e; // @[dec_tlu_ctl.scala 2846:42] + wire _T_437 = io_mhpme_vec_1 == 10'h2f; // @[dec_tlu_ctl.scala 2847:42] + wire _T_439 = io_mhpme_vec_1 == 10'h30; // @[dec_tlu_ctl.scala 2848:42] + wire _T_441 = io_mhpme_vec_1 == 10'h31; // @[dec_tlu_ctl.scala 2849:42] + wire _T_446 = io_mhpme_vec_1 == 10'h32; // @[dec_tlu_ctl.scala 2850:42] + wire _T_456 = io_mhpme_vec_1 == 10'h36; // @[dec_tlu_ctl.scala 2851:42] + wire _T_459 = io_mhpme_vec_1 == 10'h37; // @[dec_tlu_ctl.scala 2852:42] + wire _T_464 = io_mhpme_vec_1 == 10'h38; // @[dec_tlu_ctl.scala 2853:42] + wire _T_469 = io_mhpme_vec_1 == 10'h200; // @[dec_tlu_ctl.scala 2855:42] + wire _T_471 = io_mhpme_vec_1 == 10'h201; // @[dec_tlu_ctl.scala 2856:42] + wire _T_473 = io_mhpme_vec_1 == 10'h202; // @[dec_tlu_ctl.scala 2857:42] + wire _T_475 = io_mhpme_vec_1 == 10'h203; // @[dec_tlu_ctl.scala 2858:42] + wire _T_477 = io_mhpme_vec_1 == 10'h204; // @[dec_tlu_ctl.scala 2859:42] + wire _T_480 = _T_302 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_481 = _T_304 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_482 = _T_306 & _T_13; // @[Mux.scala 27:72] + wire _T_483 = _T_310 & _T_19; // @[Mux.scala 27:72] + wire _T_484 = _T_316 & _T_24; // @[Mux.scala 27:72] + wire _T_485 = _T_321 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_486 = _T_323 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_487 = _T_325 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_488 = _T_327 & _T_33; // @[Mux.scala 27:72] + wire _T_489 = _T_330 & _T_38; // @[Mux.scala 27:72] + wire _T_490 = _T_335 & _T_41; // @[Mux.scala 27:72] + wire _T_491 = _T_338 & _T_44; // @[Mux.scala 27:72] + wire _T_492 = _T_341 & _T_48; // @[Mux.scala 27:72] + wire _T_493 = _T_345 & _T_53; // @[Mux.scala 27:72] + wire _T_494 = _T_350 & _T_56; // @[Mux.scala 27:72] + wire _T_495 = _T_353 & _T_59; // @[Mux.scala 27:72] + wire _T_496 = _T_356 & _T_62; // @[Mux.scala 27:72] + wire _T_497 = _T_359 & _T_65; // @[Mux.scala 27:72] + wire _T_498 = _T_362 & _T_68; // @[Mux.scala 27:72] + wire _T_499 = _T_365 & _T_71; // @[Mux.scala 27:72] + wire _T_500 = _T_368 & _T_74; // @[Mux.scala 27:72] + wire _T_501 = _T_371 & _T_77; // @[Mux.scala 27:72] + wire _T_502 = _T_374 & _T_80; // @[Mux.scala 27:72] + wire _T_503 = _T_377 & _T_85; // @[Mux.scala 27:72] + wire _T_504 = _T_382 & _T_90; // @[Mux.scala 27:72] + wire _T_505 = _T_387 & _T_95; // @[Mux.scala 27:72] + wire _T_506 = _T_392 & _T_100; // @[Mux.scala 27:72] + wire _T_507 = _T_397 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_509 = _T_401 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_510 = _T_403 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_511 = _T_405 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_512 = _T_407 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_513 = _T_409 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_514 = _T_411 & _T_118; // @[Mux.scala 27:72] + wire _T_515 = _T_415 & _T_122; // @[Mux.scala 27:72] + wire _T_516 = _T_419 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_517 = _T_421 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_518 = _T_423 & _T_130; // @[Mux.scala 27:72] + wire _T_519 = _T_427 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_520 = _T_429 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_521 = _T_431 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_522 = _T_433 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_523 = _T_435 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_524 = _T_437 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_525 = _T_439 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_526 = _T_441 & _T_149; // @[Mux.scala 27:72] + wire _T_527 = _T_446 & _T_159; // @[Mux.scala 27:72] + wire _T_528 = _T_456 & _T_162; // @[Mux.scala 27:72] + wire _T_529 = _T_459 & _T_167; // @[Mux.scala 27:72] + wire _T_530 = _T_464 & _T_172; // @[Mux.scala 27:72] + wire _T_531 = _T_469 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_532 = _T_471 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_533 = _T_473 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_534 = _T_475 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_535 = _T_477 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_536 = _T_300 | _T_480; // @[Mux.scala 27:72] + wire _T_537 = _T_536 | _T_481; // @[Mux.scala 27:72] + wire _T_538 = _T_537 | _T_482; // @[Mux.scala 27:72] + wire _T_539 = _T_538 | _T_483; // @[Mux.scala 27:72] + wire _T_540 = _T_539 | _T_484; // @[Mux.scala 27:72] + wire _T_541 = _T_540 | _T_485; // @[Mux.scala 27:72] + wire _T_542 = _T_541 | _T_486; // @[Mux.scala 27:72] + wire _T_543 = _T_542 | _T_487; // @[Mux.scala 27:72] + wire _T_544 = _T_543 | _T_488; // @[Mux.scala 27:72] + wire _T_545 = _T_544 | _T_489; // @[Mux.scala 27:72] + wire _T_546 = _T_545 | _T_490; // @[Mux.scala 27:72] + wire _T_547 = _T_546 | _T_491; // @[Mux.scala 27:72] + wire _T_548 = _T_547 | _T_492; // @[Mux.scala 27:72] + wire _T_549 = _T_548 | _T_493; // @[Mux.scala 27:72] + wire _T_550 = _T_549 | _T_494; // @[Mux.scala 27:72] + wire _T_551 = _T_550 | _T_495; // @[Mux.scala 27:72] + wire _T_552 = _T_551 | _T_496; // @[Mux.scala 27:72] + wire _T_553 = _T_552 | _T_497; // @[Mux.scala 27:72] + wire _T_554 = _T_553 | _T_498; // @[Mux.scala 27:72] + wire _T_555 = _T_554 | _T_499; // @[Mux.scala 27:72] + wire _T_556 = _T_555 | _T_500; // @[Mux.scala 27:72] + wire _T_557 = _T_556 | _T_501; // @[Mux.scala 27:72] + wire _T_558 = _T_557 | _T_502; // @[Mux.scala 27:72] + wire _T_559 = _T_558 | _T_503; // @[Mux.scala 27:72] + wire _T_560 = _T_559 | _T_504; // @[Mux.scala 27:72] + wire _T_561 = _T_560 | _T_505; // @[Mux.scala 27:72] + wire _T_562 = _T_561 | _T_506; // @[Mux.scala 27:72] + wire _T_563 = _T_562 | _T_507; // @[Mux.scala 27:72] + wire _T_564 = _T_563 | _T_487; // @[Mux.scala 27:72] + wire _T_565 = _T_564 | _T_509; // @[Mux.scala 27:72] + wire _T_566 = _T_565 | _T_510; // @[Mux.scala 27:72] + wire _T_567 = _T_566 | _T_511; // @[Mux.scala 27:72] + wire _T_568 = _T_567 | _T_512; // @[Mux.scala 27:72] + wire _T_569 = _T_568 | _T_513; // @[Mux.scala 27:72] + wire _T_570 = _T_569 | _T_514; // @[Mux.scala 27:72] + wire _T_571 = _T_570 | _T_515; // @[Mux.scala 27:72] + wire _T_572 = _T_571 | _T_516; // @[Mux.scala 27:72] + wire _T_573 = _T_572 | _T_517; // @[Mux.scala 27:72] + wire _T_574 = _T_573 | _T_518; // @[Mux.scala 27:72] + wire _T_575 = _T_574 | _T_519; // @[Mux.scala 27:72] + wire _T_576 = _T_575 | _T_520; // @[Mux.scala 27:72] + wire _T_577 = _T_576 | _T_521; // @[Mux.scala 27:72] + wire _T_578 = _T_577 | _T_522; // @[Mux.scala 27:72] + wire _T_579 = _T_578 | _T_523; // @[Mux.scala 27:72] + wire _T_580 = _T_579 | _T_524; // @[Mux.scala 27:72] + wire _T_581 = _T_580 | _T_525; // @[Mux.scala 27:72] + wire _T_582 = _T_581 | _T_526; // @[Mux.scala 27:72] + wire _T_583 = _T_582 | _T_527; // @[Mux.scala 27:72] + wire _T_584 = _T_583 | _T_528; // @[Mux.scala 27:72] + wire _T_585 = _T_584 | _T_529; // @[Mux.scala 27:72] + wire _T_586 = _T_585 | _T_530; // @[Mux.scala 27:72] + wire _T_587 = _T_586 | _T_531; // @[Mux.scala 27:72] + wire _T_588 = _T_587 | _T_532; // @[Mux.scala 27:72] + wire _T_589 = _T_588 | _T_533; // @[Mux.scala 27:72] + wire _T_590 = _T_589 | _T_534; // @[Mux.scala 27:72] + wire _T_591 = _T_590 | _T_535; // @[Mux.scala 27:72] + wire _T_595 = ~io_mcountinhibit[5]; // @[dec_tlu_ctl.scala 2797:40] + wire _T_596 = io_mhpme_vec_2 == 10'h1; // @[dec_tlu_ctl.scala 2798:42] + wire _T_598 = io_mhpme_vec_2 == 10'h2; // @[dec_tlu_ctl.scala 2799:42] + wire _T_600 = io_mhpme_vec_2 == 10'h3; // @[dec_tlu_ctl.scala 2800:42] + wire _T_602 = io_mhpme_vec_2 == 10'h4; // @[dec_tlu_ctl.scala 2801:42] + wire _T_606 = io_mhpme_vec_2 == 10'h5; // @[dec_tlu_ctl.scala 2802:42] + wire _T_612 = io_mhpme_vec_2 == 10'h6; // @[dec_tlu_ctl.scala 2803:42] + wire _T_617 = io_mhpme_vec_2 == 10'h7; // @[dec_tlu_ctl.scala 2805:42] + wire _T_619 = io_mhpme_vec_2 == 10'h8; // @[dec_tlu_ctl.scala 2806:42] + wire _T_621 = io_mhpme_vec_2 == 10'h1e; // @[dec_tlu_ctl.scala 2807:42] + wire _T_623 = io_mhpme_vec_2 == 10'h9; // @[dec_tlu_ctl.scala 2808:42] + wire _T_626 = io_mhpme_vec_2 == 10'ha; // @[dec_tlu_ctl.scala 2809:42] + wire _T_631 = io_mhpme_vec_2 == 10'hb; // @[dec_tlu_ctl.scala 2810:42] + wire _T_634 = io_mhpme_vec_2 == 10'hc; // @[dec_tlu_ctl.scala 2811:42] + wire _T_637 = io_mhpme_vec_2 == 10'hd; // @[dec_tlu_ctl.scala 2812:42] + wire _T_641 = io_mhpme_vec_2 == 10'he; // @[dec_tlu_ctl.scala 2813:42] + wire _T_646 = io_mhpme_vec_2 == 10'hf; // @[dec_tlu_ctl.scala 2815:42] + wire _T_649 = io_mhpme_vec_2 == 10'h10; // @[dec_tlu_ctl.scala 2816:42] + wire _T_652 = io_mhpme_vec_2 == 10'h12; // @[dec_tlu_ctl.scala 2817:42] + wire _T_655 = io_mhpme_vec_2 == 10'h11; // @[dec_tlu_ctl.scala 2818:42] + wire _T_658 = io_mhpme_vec_2 == 10'h13; // @[dec_tlu_ctl.scala 2819:42] + wire _T_661 = io_mhpme_vec_2 == 10'h14; // @[dec_tlu_ctl.scala 2820:42] + wire _T_664 = io_mhpme_vec_2 == 10'h15; // @[dec_tlu_ctl.scala 2821:42] + wire _T_667 = io_mhpme_vec_2 == 10'h16; // @[dec_tlu_ctl.scala 2822:42] + wire _T_670 = io_mhpme_vec_2 == 10'h17; // @[dec_tlu_ctl.scala 2823:42] + wire _T_673 = io_mhpme_vec_2 == 10'h18; // @[dec_tlu_ctl.scala 2824:42] + wire _T_678 = io_mhpme_vec_2 == 10'h19; // @[dec_tlu_ctl.scala 2826:42] + wire _T_683 = io_mhpme_vec_2 == 10'h1a; // @[dec_tlu_ctl.scala 2827:42] + wire _T_688 = io_mhpme_vec_2 == 10'h1b; // @[dec_tlu_ctl.scala 2828:42] + wire _T_693 = io_mhpme_vec_2 == 10'h1c; // @[dec_tlu_ctl.scala 2829:42] + wire _T_697 = io_mhpme_vec_2 == 10'h1f; // @[dec_tlu_ctl.scala 2831:42] + wire _T_699 = io_mhpme_vec_2 == 10'h20; // @[dec_tlu_ctl.scala 2832:42] + wire _T_701 = io_mhpme_vec_2 == 10'h22; // @[dec_tlu_ctl.scala 2833:42] + wire _T_703 = io_mhpme_vec_2 == 10'h23; // @[dec_tlu_ctl.scala 2834:42] + wire _T_705 = io_mhpme_vec_2 == 10'h24; // @[dec_tlu_ctl.scala 2835:42] + wire _T_707 = io_mhpme_vec_2 == 10'h25; // @[dec_tlu_ctl.scala 2836:42] + wire _T_711 = io_mhpme_vec_2 == 10'h26; // @[dec_tlu_ctl.scala 2837:42] + wire _T_715 = io_mhpme_vec_2 == 10'h27; // @[dec_tlu_ctl.scala 2838:42] + wire _T_717 = io_mhpme_vec_2 == 10'h28; // @[dec_tlu_ctl.scala 2839:42] + wire _T_719 = io_mhpme_vec_2 == 10'h29; // @[dec_tlu_ctl.scala 2840:42] + wire _T_723 = io_mhpme_vec_2 == 10'h2a; // @[dec_tlu_ctl.scala 2842:42] + wire _T_725 = io_mhpme_vec_2 == 10'h2b; // @[dec_tlu_ctl.scala 2843:42] + wire _T_727 = io_mhpme_vec_2 == 10'h2c; // @[dec_tlu_ctl.scala 2844:42] + wire _T_729 = io_mhpme_vec_2 == 10'h2d; // @[dec_tlu_ctl.scala 2845:42] + wire _T_731 = io_mhpme_vec_2 == 10'h2e; // @[dec_tlu_ctl.scala 2846:42] + wire _T_733 = io_mhpme_vec_2 == 10'h2f; // @[dec_tlu_ctl.scala 2847:42] + wire _T_735 = io_mhpme_vec_2 == 10'h30; // @[dec_tlu_ctl.scala 2848:42] + wire _T_737 = io_mhpme_vec_2 == 10'h31; // @[dec_tlu_ctl.scala 2849:42] + wire _T_742 = io_mhpme_vec_2 == 10'h32; // @[dec_tlu_ctl.scala 2850:42] + wire _T_752 = io_mhpme_vec_2 == 10'h36; // @[dec_tlu_ctl.scala 2851:42] + wire _T_755 = io_mhpme_vec_2 == 10'h37; // @[dec_tlu_ctl.scala 2852:42] + wire _T_760 = io_mhpme_vec_2 == 10'h38; // @[dec_tlu_ctl.scala 2853:42] + wire _T_765 = io_mhpme_vec_2 == 10'h200; // @[dec_tlu_ctl.scala 2855:42] + wire _T_767 = io_mhpme_vec_2 == 10'h201; // @[dec_tlu_ctl.scala 2856:42] + wire _T_769 = io_mhpme_vec_2 == 10'h202; // @[dec_tlu_ctl.scala 2857:42] + wire _T_771 = io_mhpme_vec_2 == 10'h203; // @[dec_tlu_ctl.scala 2858:42] + wire _T_773 = io_mhpme_vec_2 == 10'h204; // @[dec_tlu_ctl.scala 2859:42] + wire _T_776 = _T_598 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_777 = _T_600 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_778 = _T_602 & _T_13; // @[Mux.scala 27:72] + wire _T_779 = _T_606 & _T_19; // @[Mux.scala 27:72] + wire _T_780 = _T_612 & _T_24; // @[Mux.scala 27:72] + wire _T_781 = _T_617 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_782 = _T_619 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_783 = _T_621 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_784 = _T_623 & _T_33; // @[Mux.scala 27:72] + wire _T_785 = _T_626 & _T_38; // @[Mux.scala 27:72] + wire _T_786 = _T_631 & _T_41; // @[Mux.scala 27:72] + wire _T_787 = _T_634 & _T_44; // @[Mux.scala 27:72] + wire _T_788 = _T_637 & _T_48; // @[Mux.scala 27:72] + wire _T_789 = _T_641 & _T_53; // @[Mux.scala 27:72] + wire _T_790 = _T_646 & _T_56; // @[Mux.scala 27:72] + wire _T_791 = _T_649 & _T_59; // @[Mux.scala 27:72] + wire _T_792 = _T_652 & _T_62; // @[Mux.scala 27:72] + wire _T_793 = _T_655 & _T_65; // @[Mux.scala 27:72] + wire _T_794 = _T_658 & _T_68; // @[Mux.scala 27:72] + wire _T_795 = _T_661 & _T_71; // @[Mux.scala 27:72] + wire _T_796 = _T_664 & _T_74; // @[Mux.scala 27:72] + wire _T_797 = _T_667 & _T_77; // @[Mux.scala 27:72] + wire _T_798 = _T_670 & _T_80; // @[Mux.scala 27:72] + wire _T_799 = _T_673 & _T_85; // @[Mux.scala 27:72] + wire _T_800 = _T_678 & _T_90; // @[Mux.scala 27:72] + wire _T_801 = _T_683 & _T_95; // @[Mux.scala 27:72] + wire _T_802 = _T_688 & _T_100; // @[Mux.scala 27:72] + wire _T_803 = _T_693 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_805 = _T_697 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_806 = _T_699 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_807 = _T_701 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_808 = _T_703 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_809 = _T_705 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_810 = _T_707 & _T_118; // @[Mux.scala 27:72] + wire _T_811 = _T_711 & _T_122; // @[Mux.scala 27:72] + wire _T_812 = _T_715 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_813 = _T_717 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_814 = _T_719 & _T_130; // @[Mux.scala 27:72] + wire _T_815 = _T_723 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_816 = _T_725 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_817 = _T_727 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_818 = _T_729 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_819 = _T_731 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_820 = _T_733 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_821 = _T_735 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_822 = _T_737 & _T_149; // @[Mux.scala 27:72] + wire _T_823 = _T_742 & _T_159; // @[Mux.scala 27:72] + wire _T_824 = _T_752 & _T_162; // @[Mux.scala 27:72] + wire _T_825 = _T_755 & _T_167; // @[Mux.scala 27:72] + wire _T_826 = _T_760 & _T_172; // @[Mux.scala 27:72] + wire _T_827 = _T_765 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_828 = _T_767 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_829 = _T_769 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_830 = _T_771 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_831 = _T_773 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_832 = _T_596 | _T_776; // @[Mux.scala 27:72] + wire _T_833 = _T_832 | _T_777; // @[Mux.scala 27:72] + wire _T_834 = _T_833 | _T_778; // @[Mux.scala 27:72] + wire _T_835 = _T_834 | _T_779; // @[Mux.scala 27:72] + wire _T_836 = _T_835 | _T_780; // @[Mux.scala 27:72] + wire _T_837 = _T_836 | _T_781; // @[Mux.scala 27:72] + wire _T_838 = _T_837 | _T_782; // @[Mux.scala 27:72] + wire _T_839 = _T_838 | _T_783; // @[Mux.scala 27:72] + wire _T_840 = _T_839 | _T_784; // @[Mux.scala 27:72] + wire _T_841 = _T_840 | _T_785; // @[Mux.scala 27:72] + wire _T_842 = _T_841 | _T_786; // @[Mux.scala 27:72] + wire _T_843 = _T_842 | _T_787; // @[Mux.scala 27:72] + wire _T_844 = _T_843 | _T_788; // @[Mux.scala 27:72] + wire _T_845 = _T_844 | _T_789; // @[Mux.scala 27:72] + wire _T_846 = _T_845 | _T_790; // @[Mux.scala 27:72] + wire _T_847 = _T_846 | _T_791; // @[Mux.scala 27:72] + wire _T_848 = _T_847 | _T_792; // @[Mux.scala 27:72] + wire _T_849 = _T_848 | _T_793; // @[Mux.scala 27:72] + wire _T_850 = _T_849 | _T_794; // @[Mux.scala 27:72] + wire _T_851 = _T_850 | _T_795; // @[Mux.scala 27:72] + wire _T_852 = _T_851 | _T_796; // @[Mux.scala 27:72] + wire _T_853 = _T_852 | _T_797; // @[Mux.scala 27:72] + wire _T_854 = _T_853 | _T_798; // @[Mux.scala 27:72] + wire _T_855 = _T_854 | _T_799; // @[Mux.scala 27:72] + wire _T_856 = _T_855 | _T_800; // @[Mux.scala 27:72] + wire _T_857 = _T_856 | _T_801; // @[Mux.scala 27:72] + wire _T_858 = _T_857 | _T_802; // @[Mux.scala 27:72] + wire _T_859 = _T_858 | _T_803; // @[Mux.scala 27:72] + wire _T_860 = _T_859 | _T_783; // @[Mux.scala 27:72] + wire _T_861 = _T_860 | _T_805; // @[Mux.scala 27:72] + wire _T_862 = _T_861 | _T_806; // @[Mux.scala 27:72] + wire _T_863 = _T_862 | _T_807; // @[Mux.scala 27:72] + wire _T_864 = _T_863 | _T_808; // @[Mux.scala 27:72] + wire _T_865 = _T_864 | _T_809; // @[Mux.scala 27:72] + wire _T_866 = _T_865 | _T_810; // @[Mux.scala 27:72] + wire _T_867 = _T_866 | _T_811; // @[Mux.scala 27:72] + wire _T_868 = _T_867 | _T_812; // @[Mux.scala 27:72] + wire _T_869 = _T_868 | _T_813; // @[Mux.scala 27:72] + wire _T_870 = _T_869 | _T_814; // @[Mux.scala 27:72] + wire _T_871 = _T_870 | _T_815; // @[Mux.scala 27:72] + wire _T_872 = _T_871 | _T_816; // @[Mux.scala 27:72] + wire _T_873 = _T_872 | _T_817; // @[Mux.scala 27:72] + wire _T_874 = _T_873 | _T_818; // @[Mux.scala 27:72] + wire _T_875 = _T_874 | _T_819; // @[Mux.scala 27:72] + wire _T_876 = _T_875 | _T_820; // @[Mux.scala 27:72] + wire _T_877 = _T_876 | _T_821; // @[Mux.scala 27:72] + wire _T_878 = _T_877 | _T_822; // @[Mux.scala 27:72] + wire _T_879 = _T_878 | _T_823; // @[Mux.scala 27:72] + wire _T_880 = _T_879 | _T_824; // @[Mux.scala 27:72] + wire _T_881 = _T_880 | _T_825; // @[Mux.scala 27:72] + wire _T_882 = _T_881 | _T_826; // @[Mux.scala 27:72] + wire _T_883 = _T_882 | _T_827; // @[Mux.scala 27:72] + wire _T_884 = _T_883 | _T_828; // @[Mux.scala 27:72] + wire _T_885 = _T_884 | _T_829; // @[Mux.scala 27:72] + wire _T_886 = _T_885 | _T_830; // @[Mux.scala 27:72] + wire _T_887 = _T_886 | _T_831; // @[Mux.scala 27:72] + wire _T_891 = ~io_mcountinhibit[6]; // @[dec_tlu_ctl.scala 2797:40] + wire _T_892 = io_mhpme_vec_3 == 10'h1; // @[dec_tlu_ctl.scala 2798:42] + wire _T_894 = io_mhpme_vec_3 == 10'h2; // @[dec_tlu_ctl.scala 2799:42] + wire _T_896 = io_mhpme_vec_3 == 10'h3; // @[dec_tlu_ctl.scala 2800:42] + wire _T_898 = io_mhpme_vec_3 == 10'h4; // @[dec_tlu_ctl.scala 2801:42] + wire _T_902 = io_mhpme_vec_3 == 10'h5; // @[dec_tlu_ctl.scala 2802:42] + wire _T_908 = io_mhpme_vec_3 == 10'h6; // @[dec_tlu_ctl.scala 2803:42] + wire _T_913 = io_mhpme_vec_3 == 10'h7; // @[dec_tlu_ctl.scala 2805:42] + wire _T_915 = io_mhpme_vec_3 == 10'h8; // @[dec_tlu_ctl.scala 2806:42] + wire _T_917 = io_mhpme_vec_3 == 10'h1e; // @[dec_tlu_ctl.scala 2807:42] + wire _T_919 = io_mhpme_vec_3 == 10'h9; // @[dec_tlu_ctl.scala 2808:42] + wire _T_922 = io_mhpme_vec_3 == 10'ha; // @[dec_tlu_ctl.scala 2809:42] + wire _T_927 = io_mhpme_vec_3 == 10'hb; // @[dec_tlu_ctl.scala 2810:42] + wire _T_930 = io_mhpme_vec_3 == 10'hc; // @[dec_tlu_ctl.scala 2811:42] + wire _T_933 = io_mhpme_vec_3 == 10'hd; // @[dec_tlu_ctl.scala 2812:42] + wire _T_937 = io_mhpme_vec_3 == 10'he; // @[dec_tlu_ctl.scala 2813:42] + wire _T_942 = io_mhpme_vec_3 == 10'hf; // @[dec_tlu_ctl.scala 2815:42] + wire _T_945 = io_mhpme_vec_3 == 10'h10; // @[dec_tlu_ctl.scala 2816:42] + wire _T_948 = io_mhpme_vec_3 == 10'h12; // @[dec_tlu_ctl.scala 2817:42] + wire _T_951 = io_mhpme_vec_3 == 10'h11; // @[dec_tlu_ctl.scala 2818:42] + wire _T_954 = io_mhpme_vec_3 == 10'h13; // @[dec_tlu_ctl.scala 2819:42] + wire _T_957 = io_mhpme_vec_3 == 10'h14; // @[dec_tlu_ctl.scala 2820:42] + wire _T_960 = io_mhpme_vec_3 == 10'h15; // @[dec_tlu_ctl.scala 2821:42] + wire _T_963 = io_mhpme_vec_3 == 10'h16; // @[dec_tlu_ctl.scala 2822:42] + wire _T_966 = io_mhpme_vec_3 == 10'h17; // @[dec_tlu_ctl.scala 2823:42] + wire _T_969 = io_mhpme_vec_3 == 10'h18; // @[dec_tlu_ctl.scala 2824:42] + wire _T_974 = io_mhpme_vec_3 == 10'h19; // @[dec_tlu_ctl.scala 2826:42] + wire _T_979 = io_mhpme_vec_3 == 10'h1a; // @[dec_tlu_ctl.scala 2827:42] + wire _T_984 = io_mhpme_vec_3 == 10'h1b; // @[dec_tlu_ctl.scala 2828:42] + wire _T_989 = io_mhpme_vec_3 == 10'h1c; // @[dec_tlu_ctl.scala 2829:42] + wire _T_993 = io_mhpme_vec_3 == 10'h1f; // @[dec_tlu_ctl.scala 2831:42] + wire _T_995 = io_mhpme_vec_3 == 10'h20; // @[dec_tlu_ctl.scala 2832:42] + wire _T_997 = io_mhpme_vec_3 == 10'h22; // @[dec_tlu_ctl.scala 2833:42] + wire _T_999 = io_mhpme_vec_3 == 10'h23; // @[dec_tlu_ctl.scala 2834:42] + wire _T_1001 = io_mhpme_vec_3 == 10'h24; // @[dec_tlu_ctl.scala 2835:42] + wire _T_1003 = io_mhpme_vec_3 == 10'h25; // @[dec_tlu_ctl.scala 2836:42] + wire _T_1007 = io_mhpme_vec_3 == 10'h26; // @[dec_tlu_ctl.scala 2837:42] + wire _T_1011 = io_mhpme_vec_3 == 10'h27; // @[dec_tlu_ctl.scala 2838:42] + wire _T_1013 = io_mhpme_vec_3 == 10'h28; // @[dec_tlu_ctl.scala 2839:42] + wire _T_1015 = io_mhpme_vec_3 == 10'h29; // @[dec_tlu_ctl.scala 2840:42] + wire _T_1019 = io_mhpme_vec_3 == 10'h2a; // @[dec_tlu_ctl.scala 2842:42] + wire _T_1021 = io_mhpme_vec_3 == 10'h2b; // @[dec_tlu_ctl.scala 2843:42] + wire _T_1023 = io_mhpme_vec_3 == 10'h2c; // @[dec_tlu_ctl.scala 2844:42] + wire _T_1025 = io_mhpme_vec_3 == 10'h2d; // @[dec_tlu_ctl.scala 2845:42] + wire _T_1027 = io_mhpme_vec_3 == 10'h2e; // @[dec_tlu_ctl.scala 2846:42] + wire _T_1029 = io_mhpme_vec_3 == 10'h2f; // @[dec_tlu_ctl.scala 2847:42] + wire _T_1031 = io_mhpme_vec_3 == 10'h30; // @[dec_tlu_ctl.scala 2848:42] + wire _T_1033 = io_mhpme_vec_3 == 10'h31; // @[dec_tlu_ctl.scala 2849:42] + wire _T_1038 = io_mhpme_vec_3 == 10'h32; // @[dec_tlu_ctl.scala 2850:42] + wire _T_1048 = io_mhpme_vec_3 == 10'h36; // @[dec_tlu_ctl.scala 2851:42] + wire _T_1051 = io_mhpme_vec_3 == 10'h37; // @[dec_tlu_ctl.scala 2852:42] + wire _T_1056 = io_mhpme_vec_3 == 10'h38; // @[dec_tlu_ctl.scala 2853:42] + wire _T_1061 = io_mhpme_vec_3 == 10'h200; // @[dec_tlu_ctl.scala 2855:42] + wire _T_1063 = io_mhpme_vec_3 == 10'h201; // @[dec_tlu_ctl.scala 2856:42] + wire _T_1065 = io_mhpme_vec_3 == 10'h202; // @[dec_tlu_ctl.scala 2857:42] + wire _T_1067 = io_mhpme_vec_3 == 10'h203; // @[dec_tlu_ctl.scala 2858:42] + wire _T_1069 = io_mhpme_vec_3 == 10'h204; // @[dec_tlu_ctl.scala 2859:42] + wire _T_1072 = _T_894 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1073 = _T_896 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1074 = _T_898 & _T_13; // @[Mux.scala 27:72] + wire _T_1075 = _T_902 & _T_19; // @[Mux.scala 27:72] + wire _T_1076 = _T_908 & _T_24; // @[Mux.scala 27:72] + wire _T_1077 = _T_913 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1078 = _T_915 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1079 = _T_917 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1080 = _T_919 & _T_33; // @[Mux.scala 27:72] + wire _T_1081 = _T_922 & _T_38; // @[Mux.scala 27:72] + wire _T_1082 = _T_927 & _T_41; // @[Mux.scala 27:72] + wire _T_1083 = _T_930 & _T_44; // @[Mux.scala 27:72] + wire _T_1084 = _T_933 & _T_48; // @[Mux.scala 27:72] + wire _T_1085 = _T_937 & _T_53; // @[Mux.scala 27:72] + wire _T_1086 = _T_942 & _T_56; // @[Mux.scala 27:72] + wire _T_1087 = _T_945 & _T_59; // @[Mux.scala 27:72] + wire _T_1088 = _T_948 & _T_62; // @[Mux.scala 27:72] + wire _T_1089 = _T_951 & _T_65; // @[Mux.scala 27:72] + wire _T_1090 = _T_954 & _T_68; // @[Mux.scala 27:72] + wire _T_1091 = _T_957 & _T_71; // @[Mux.scala 27:72] + wire _T_1092 = _T_960 & _T_74; // @[Mux.scala 27:72] + wire _T_1093 = _T_963 & _T_77; // @[Mux.scala 27:72] + wire _T_1094 = _T_966 & _T_80; // @[Mux.scala 27:72] + wire _T_1095 = _T_969 & _T_85; // @[Mux.scala 27:72] + wire _T_1096 = _T_974 & _T_90; // @[Mux.scala 27:72] + wire _T_1097 = _T_979 & _T_95; // @[Mux.scala 27:72] + wire _T_1098 = _T_984 & _T_100; // @[Mux.scala 27:72] + wire _T_1099 = _T_989 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1101 = _T_993 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1102 = _T_995 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1103 = _T_997 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1104 = _T_999 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1105 = _T_1001 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1106 = _T_1003 & _T_118; // @[Mux.scala 27:72] + wire _T_1107 = _T_1007 & _T_122; // @[Mux.scala 27:72] + wire _T_1108 = _T_1011 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1109 = _T_1013 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1110 = _T_1015 & _T_130; // @[Mux.scala 27:72] + wire _T_1111 = _T_1019 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1112 = _T_1021 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1113 = _T_1023 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1114 = _T_1025 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1115 = _T_1027 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1116 = _T_1029 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1117 = _T_1031 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1118 = _T_1033 & _T_149; // @[Mux.scala 27:72] + wire _T_1119 = _T_1038 & _T_159; // @[Mux.scala 27:72] + wire _T_1120 = _T_1048 & _T_162; // @[Mux.scala 27:72] + wire _T_1121 = _T_1051 & _T_167; // @[Mux.scala 27:72] + wire _T_1122 = _T_1056 & _T_172; // @[Mux.scala 27:72] + wire _T_1123 = _T_1061 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1124 = _T_1063 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1125 = _T_1065 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1126 = _T_1067 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1127 = _T_1069 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1128 = _T_892 | _T_1072; // @[Mux.scala 27:72] + wire _T_1129 = _T_1128 | _T_1073; // @[Mux.scala 27:72] + wire _T_1130 = _T_1129 | _T_1074; // @[Mux.scala 27:72] + wire _T_1131 = _T_1130 | _T_1075; // @[Mux.scala 27:72] + wire _T_1132 = _T_1131 | _T_1076; // @[Mux.scala 27:72] + wire _T_1133 = _T_1132 | _T_1077; // @[Mux.scala 27:72] + wire _T_1134 = _T_1133 | _T_1078; // @[Mux.scala 27:72] + wire _T_1135 = _T_1134 | _T_1079; // @[Mux.scala 27:72] + wire _T_1136 = _T_1135 | _T_1080; // @[Mux.scala 27:72] + wire _T_1137 = _T_1136 | _T_1081; // @[Mux.scala 27:72] + wire _T_1138 = _T_1137 | _T_1082; // @[Mux.scala 27:72] + wire _T_1139 = _T_1138 | _T_1083; // @[Mux.scala 27:72] + wire _T_1140 = _T_1139 | _T_1084; // @[Mux.scala 27:72] + wire _T_1141 = _T_1140 | _T_1085; // @[Mux.scala 27:72] + wire _T_1142 = _T_1141 | _T_1086; // @[Mux.scala 27:72] + wire _T_1143 = _T_1142 | _T_1087; // @[Mux.scala 27:72] + wire _T_1144 = _T_1143 | _T_1088; // @[Mux.scala 27:72] + wire _T_1145 = _T_1144 | _T_1089; // @[Mux.scala 27:72] + wire _T_1146 = _T_1145 | _T_1090; // @[Mux.scala 27:72] + wire _T_1147 = _T_1146 | _T_1091; // @[Mux.scala 27:72] + wire _T_1148 = _T_1147 | _T_1092; // @[Mux.scala 27:72] + wire _T_1149 = _T_1148 | _T_1093; // @[Mux.scala 27:72] + wire _T_1150 = _T_1149 | _T_1094; // @[Mux.scala 27:72] + wire _T_1151 = _T_1150 | _T_1095; // @[Mux.scala 27:72] + wire _T_1152 = _T_1151 | _T_1096; // @[Mux.scala 27:72] + wire _T_1153 = _T_1152 | _T_1097; // @[Mux.scala 27:72] + wire _T_1154 = _T_1153 | _T_1098; // @[Mux.scala 27:72] + wire _T_1155 = _T_1154 | _T_1099; // @[Mux.scala 27:72] + wire _T_1156 = _T_1155 | _T_1079; // @[Mux.scala 27:72] + wire _T_1157 = _T_1156 | _T_1101; // @[Mux.scala 27:72] + wire _T_1158 = _T_1157 | _T_1102; // @[Mux.scala 27:72] + wire _T_1159 = _T_1158 | _T_1103; // @[Mux.scala 27:72] + wire _T_1160 = _T_1159 | _T_1104; // @[Mux.scala 27:72] + wire _T_1161 = _T_1160 | _T_1105; // @[Mux.scala 27:72] + wire _T_1162 = _T_1161 | _T_1106; // @[Mux.scala 27:72] + wire _T_1163 = _T_1162 | _T_1107; // @[Mux.scala 27:72] + wire _T_1164 = _T_1163 | _T_1108; // @[Mux.scala 27:72] + wire _T_1165 = _T_1164 | _T_1109; // @[Mux.scala 27:72] + wire _T_1166 = _T_1165 | _T_1110; // @[Mux.scala 27:72] + wire _T_1167 = _T_1166 | _T_1111; // @[Mux.scala 27:72] + wire _T_1168 = _T_1167 | _T_1112; // @[Mux.scala 27:72] + wire _T_1169 = _T_1168 | _T_1113; // @[Mux.scala 27:72] + wire _T_1170 = _T_1169 | _T_1114; // @[Mux.scala 27:72] + wire _T_1171 = _T_1170 | _T_1115; // @[Mux.scala 27:72] + wire _T_1172 = _T_1171 | _T_1116; // @[Mux.scala 27:72] + wire _T_1173 = _T_1172 | _T_1117; // @[Mux.scala 27:72] + wire _T_1174 = _T_1173 | _T_1118; // @[Mux.scala 27:72] + wire _T_1175 = _T_1174 | _T_1119; // @[Mux.scala 27:72] + wire _T_1176 = _T_1175 | _T_1120; // @[Mux.scala 27:72] + wire _T_1177 = _T_1176 | _T_1121; // @[Mux.scala 27:72] + wire _T_1178 = _T_1177 | _T_1122; // @[Mux.scala 27:72] + wire _T_1179 = _T_1178 | _T_1123; // @[Mux.scala 27:72] + wire _T_1180 = _T_1179 | _T_1124; // @[Mux.scala 27:72] + wire _T_1181 = _T_1180 | _T_1125; // @[Mux.scala 27:72] + wire _T_1182 = _T_1181 | _T_1126; // @[Mux.scala 27:72] + wire _T_1183 = _T_1182 | _T_1127; // @[Mux.scala 27:72] + reg _T_1189; // @[Reg.scala 27:20] + wire _T_1187 = io_mdseac_locked_ns ^ _T_1189; // @[lib.scala 470:21] + wire _T_1188 = |_T_1187; // @[lib.scala 470:29] + reg _T_1193; // @[Reg.scala 27:20] + wire _T_1191 = io_lsu_single_ecc_error_r ^ _T_1193; // @[lib.scala 470:21] + wire _T_1192 = |_T_1191; // @[lib.scala 470:29] + reg _T_1201; // @[Reg.scala 27:20] + wire _T_1199 = io_lsu_i0_exc_r ^ _T_1201; // @[lib.scala 470:21] + wire _T_1200 = |_T_1199; // @[lib.scala 470:29] + reg _T_1205; // @[Reg.scala 27:20] + wire _T_1203 = io_take_ext_int_start ^ _T_1205; // @[lib.scala 470:21] + wire _T_1204 = |_T_1203; // @[lib.scala 470:29] + reg _T_1209; // @[Reg.scala 27:20] + wire _T_1207 = io_take_ext_int_start_d1 ^ _T_1209; // @[lib.scala 470:21] + wire _T_1208 = |_T_1207; // @[lib.scala 470:29] + reg _T_1213; // @[Reg.scala 27:20] + wire _T_1211 = io_take_ext_int_start_d2 ^ _T_1213; // @[lib.scala 470:21] + wire _T_1212 = |_T_1211; // @[lib.scala 470:29] + reg _T_1217; // @[Reg.scala 27:20] + wire _T_1215 = io_ext_int_freeze ^ _T_1217; // @[lib.scala 470:21] + wire _T_1216 = |_T_1215; // @[lib.scala 470:29] + reg [5:0] _T_1221; // @[Reg.scala 27:20] + wire [5:0] _T_1219 = io_mip_ns ^ _T_1221; // @[lib.scala 448:21] + wire _T_1220 = |_T_1219; // @[lib.scala 448:29] + wire _T_1222 = ~io_wr_mcycleh_r; // @[dec_tlu_ctl.scala 2879:80] + wire _T_1223 = io_mcyclel_cout & _T_1222; // @[dec_tlu_ctl.scala 2879:78] + wire _T_1224 = _T_1223 & io_mcyclel_cout_in; // @[dec_tlu_ctl.scala 2879:97] + reg _T_1228; // @[Reg.scala 27:20] + wire _T_1226 = _T_1224 ^ _T_1228; // @[lib.scala 470:21] + wire _T_1227 = |_T_1226; // @[lib.scala 470:29] + reg _T_1232; // @[Reg.scala 27:20] + wire _T_1230 = io_minstret_enable ^ _T_1232; // @[lib.scala 470:21] + wire _T_1231 = |_T_1230; // @[lib.scala 470:29] + reg _T_1236; // @[Reg.scala 27:20] + wire _T_1234 = io_minstretl_cout_ns ^ _T_1236; // @[lib.scala 470:21] + wire _T_1235 = |_T_1234; // @[lib.scala 470:29] + reg [3:0] _T_1244; // @[Reg.scala 27:20] + wire [3:0] _T_1242 = io_meicidpl_ns ^ _T_1244; // @[lib.scala 448:21] + wire _T_1243 = |_T_1242; // @[lib.scala 448:29] + reg _T_1248; // @[Reg.scala 27:20] + wire _T_1246 = io_icache_rd_valid ^ _T_1248; // @[lib.scala 470:21] + wire _T_1247 = |_T_1246; // @[lib.scala 470:29] + reg _T_1252; // @[Reg.scala 27:20] + wire _T_1250 = io_icache_wr_valid ^ _T_1252; // @[lib.scala 470:21] + wire _T_1251 = |_T_1250; // @[lib.scala 470:29] + reg _T_1266_0; // @[Reg.scala 27:20] + wire _T_1254 = io_mhpmc_inc_r_0 ^ _T_1266_0; // @[lib.scala 518:68] + wire _T_1255 = |_T_1254; // @[lib.scala 518:82] + reg _T_1266_1; // @[Reg.scala 27:20] + wire _T_1256 = io_mhpmc_inc_r_1 ^ _T_1266_1; // @[lib.scala 518:68] + wire _T_1257 = |_T_1256; // @[lib.scala 518:82] + reg _T_1266_2; // @[Reg.scala 27:20] + wire _T_1258 = io_mhpmc_inc_r_2 ^ _T_1266_2; // @[lib.scala 518:68] + wire _T_1259 = |_T_1258; // @[lib.scala 518:82] + reg _T_1266_3; // @[Reg.scala 27:20] + wire _T_1260 = io_mhpmc_inc_r_3 ^ _T_1266_3; // @[lib.scala 518:68] + wire _T_1261 = |_T_1260; // @[lib.scala 518:82] + wire _T_1262 = _T_1255 | _T_1257; // @[lib.scala 518:97] + wire _T_1263 = _T_1262 | _T_1259; // @[lib.scala 518:97] + wire _T_1264 = _T_1263 | _T_1261; // @[lib.scala 518:97] + reg _T_1270; // @[Reg.scala 27:20] + wire _T_1268 = io_perfcnt_halted ^ _T_1270; // @[lib.scala 470:21] + wire _T_1269 = |_T_1268; // @[lib.scala 470:29] + reg [1:0] _T_1274; // @[Reg.scala 27:20] + wire [1:0] _T_1272 = io_mstatus_ns ^ _T_1274; // @[lib.scala 448:21] + wire _T_1273 = |_T_1272; // @[lib.scala 448:29] + assign io_mhpmc_inc_r_0 = _T_3 & _T_295; // @[dec_tlu_ctl.scala 2797:35] + assign io_mhpmc_inc_r_1 = _T_299 & _T_591; // @[dec_tlu_ctl.scala 2797:35] + assign io_mhpmc_inc_r_2 = _T_595 & _T_887; // @[dec_tlu_ctl.scala 2797:35] + assign io_mhpmc_inc_r_3 = _T_891 & _T_1183; // @[dec_tlu_ctl.scala 2797:35] + assign io_mstatus = _T_1274; // @[dec_tlu_ctl.scala 2888:52] + assign io_mcyclel_cout_f = _T_1228; // @[dec_tlu_ctl.scala 2879:52] + assign io_minstret_enable_f = _T_1232; // @[dec_tlu_ctl.scala 2880:52] + assign io_minstretl_cout_f = _T_1236; // @[dec_tlu_ctl.scala 2881:52] + assign io_meicidpl = _T_1244; // @[dec_tlu_ctl.scala 2883:52] + assign io_icache_rd_valid_f = _T_1248; // @[dec_tlu_ctl.scala 2884:52] + assign io_icache_wr_valid_f = _T_1252; // @[dec_tlu_ctl.scala 2885:52] + assign io_mhpmc_inc_r_d1_0 = _T_1266_0; // @[dec_tlu_ctl.scala 2886:52] + assign io_mhpmc_inc_r_d1_1 = _T_1266_1; // @[dec_tlu_ctl.scala 2886:52] + assign io_mhpmc_inc_r_d1_2 = _T_1266_2; // @[dec_tlu_ctl.scala 2886:52] + assign io_mhpmc_inc_r_d1_3 = _T_1266_3; // @[dec_tlu_ctl.scala 2886:52] + assign io_perfcnt_halted_d1 = _T_1270; // @[dec_tlu_ctl.scala 2887:52] + assign io_mdseac_locked_f = _T_1189; // @[dec_tlu_ctl.scala 2870:52] + assign io_lsu_single_ecc_error_r_d1 = _T_1193; // @[dec_tlu_ctl.scala 2871:52] + assign io_lsu_i0_exc_r_d1 = _T_1201; // @[dec_tlu_ctl.scala 2873:52] + assign io_take_ext_int_start_d1 = _T_1205; // @[dec_tlu_ctl.scala 2874:52] + assign io_take_ext_int_start_d2 = _T_1209; // @[dec_tlu_ctl.scala 2875:52] + assign io_take_ext_int_start_d3 = _T_1213; // @[dec_tlu_ctl.scala 2876:52] + assign io_ext_int_freeze_d1 = _T_1217; // @[dec_tlu_ctl.scala 2877:52] + assign io_mip = _T_1221; // @[dec_tlu_ctl.scala 2878:52] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T_1189 = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + _T_1193 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_1201 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + _T_1205 = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + _T_1209 = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + _T_1213 = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + _T_1217 = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + _T_1221 = _RAND_7[5:0]; + _RAND_8 = {1{`RANDOM}}; + _T_1228 = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + _T_1232 = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + _T_1236 = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + _T_1244 = _RAND_11[3:0]; + _RAND_12 = {1{`RANDOM}}; + _T_1248 = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + _T_1252 = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + _T_1266_0 = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + _T_1266_1 = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + _T_1266_2 = _RAND_16[0:0]; + _RAND_17 = {1{`RANDOM}}; + _T_1266_3 = _RAND_17[0:0]; + _RAND_18 = {1{`RANDOM}}; + _T_1270 = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + _T_1274 = _RAND_19[1:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_1189 = 1'h0; + end + if (reset) begin + _T_1193 = 1'h0; + end + if (reset) begin + _T_1201 = 1'h0; + end + if (reset) begin + _T_1205 = 1'h0; + end + if (reset) begin + _T_1209 = 1'h0; + end + if (reset) begin + _T_1213 = 1'h0; + end + if (reset) begin + _T_1217 = 1'h0; + end + if (reset) begin + _T_1221 = 6'h0; + end + if (reset) begin + _T_1228 = 1'h0; + end + if (reset) begin + _T_1232 = 1'h0; + end + if (reset) begin + _T_1236 = 1'h0; + end + if (reset) begin + _T_1244 = 4'h0; + end + if (reset) begin + _T_1248 = 1'h0; + end + if (reset) begin + _T_1252 = 1'h0; + end + if (reset) begin + _T_1266_0 = 1'h0; + end + if (reset) begin + _T_1266_1 = 1'h0; + end + if (reset) begin + _T_1266_2 = 1'h0; + end + if (reset) begin + _T_1266_3 = 1'h0; + end + if (reset) begin + _T_1270 = 1'h0; + end + if (reset) begin + _T_1274 = 2'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1189 <= 1'h0; + end else if (_T_1188) begin + _T_1189 <= io_mdseac_locked_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1193 <= 1'h0; + end else if (_T_1192) begin + _T_1193 <= io_lsu_single_ecc_error_r; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1201 <= 1'h0; + end else if (_T_1200) begin + _T_1201 <= io_lsu_i0_exc_r; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1205 <= 1'h0; + end else if (_T_1204) begin + _T_1205 <= io_take_ext_int_start; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1209 <= 1'h0; + end else if (_T_1208) begin + _T_1209 <= io_take_ext_int_start_d1; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1213 <= 1'h0; + end else if (_T_1212) begin + _T_1213 <= io_take_ext_int_start_d2; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1217 <= 1'h0; + end else if (_T_1216) begin + _T_1217 <= io_ext_int_freeze; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1221 <= 6'h0; + end else if (_T_1220) begin + _T_1221 <= io_mip_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1228 <= 1'h0; + end else if (_T_1227) begin + _T_1228 <= _T_1224; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1232 <= 1'h0; + end else if (_T_1231) begin + _T_1232 <= io_minstret_enable; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1236 <= 1'h0; + end else if (_T_1235) begin + _T_1236 <= io_minstretl_cout_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1244 <= 4'h0; + end else if (_T_1243) begin + _T_1244 <= io_meicidpl_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1248 <= 1'h0; + end else if (_T_1247) begin + _T_1248 <= io_icache_rd_valid; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1252 <= 1'h0; + end else if (_T_1251) begin + _T_1252 <= io_icache_wr_valid; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1266_0 <= 1'h0; + end else if (_T_1264) begin + _T_1266_0 <= io_mhpmc_inc_r_0; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1266_1 <= 1'h0; + end else if (_T_1264) begin + _T_1266_1 <= io_mhpmc_inc_r_1; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1266_2 <= 1'h0; + end else if (_T_1264) begin + _T_1266_2 <= io_mhpmc_inc_r_2; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1266_3 <= 1'h0; + end else if (_T_1264) begin + _T_1266_3 <= io_mhpmc_inc_r_3; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1270 <= 1'h0; + end else if (_T_1269) begin + _T_1270 <= io_perfcnt_halted; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_1274 <= 2'h0; + end else if (_T_1273) begin + _T_1274 <= io_mstatus_ns; + end + end +endmodule +module rvclkhdr( + input io_clk, + input io_en +); + wire clkhdr_Q; // @[lib.scala 334:26] + wire clkhdr_CK; // @[lib.scala 334:26] + wire clkhdr_EN; // @[lib.scala 334:26] + wire clkhdr_SE; // @[lib.scala 334:26] + gated_latch clkhdr ( // @[lib.scala 334:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign clkhdr_CK = io_clk; // @[lib.scala 336:18] + assign clkhdr_EN = io_en; // @[lib.scala 337:18] + assign clkhdr_SE = 1'h0; // @[lib.scala 338:18] +endmodule +module perf_csr( + input clock, + input reset, + input io_free_l2clk, + input io_dec_tlu_dbg_halted, + input [15:0] io_dcsr, + input io_dec_tlu_pmu_fw_halted, + input [9:0] io_mhpme_vec_0, + input [9:0] io_mhpme_vec_1, + input [9:0] io_mhpme_vec_2, + input [9:0] io_mhpme_vec_3, + input io_dec_csr_wen_r_mod, + input [11:0] io_dec_csr_wraddr_r, + input [31:0] io_dec_csr_wrdata_r, + input io_mhpmc_inc_r_0, + input io_mhpmc_inc_r_1, + input io_mhpmc_inc_r_2, + input io_mhpmc_inc_r_3, + input io_mhpmc_inc_r_d1_0, + input io_mhpmc_inc_r_d1_1, + input io_mhpmc_inc_r_d1_2, + input io_mhpmc_inc_r_d1_3, + input io_perfcnt_halted_d1, + output [31:0] io_mhpmc3h, + output [31:0] io_mhpmc3, + output [31:0] io_mhpmc4h, + output [31:0] io_mhpmc4, + output [31:0] io_mhpmc5h, + output [31:0] io_mhpmc5, + output [31:0] io_mhpmc6h, + output [31:0] io_mhpmc6, + output [9:0] io_mhpme3, + output [9:0] io_mhpme4, + output [9:0] io_mhpme5, + output [9:0] io_mhpme6, + output io_dec_tlu_perfcnt0, + output io_dec_tlu_perfcnt1, + output io_dec_tlu_perfcnt2, + output io_dec_tlu_perfcnt3 +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_4_io_en; // @[lib.scala 404:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_5_io_en; // @[lib.scala 404:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_6_io_en; // @[lib.scala 404:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_7_io_en; // @[lib.scala 404:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_8_io_en; // @[lib.scala 404:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_9_io_en; // @[lib.scala 404:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_10_io_en; // @[lib.scala 404:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_11_io_en; // @[lib.scala 404:23] + wire _T_1 = io_dec_tlu_dbg_halted & io_dcsr[10]; // @[dec_tlu_ctl.scala 2578:54] + wire perfcnt_halted = _T_1 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2578:77] + wire _T_4 = ~_T_1; // @[dec_tlu_ctl.scala 2579:44] + wire [3:0] _T_6 = _T_4 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_13 = {io_mhpme_vec_3[9],io_mhpme_vec_2[9],io_mhpme_vec_1[9],io_mhpme_vec_0[9]}; // @[Cat.scala 29:58] + wire [3:0] perfcnt_during_sleep = _T_6 & _T_13; // @[dec_tlu_ctl.scala 2579:93] + wire _T_15 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2582:80] + wire _T_16 = io_perfcnt_halted_d1 & _T_15; // @[dec_tlu_ctl.scala 2582:78] + wire _T_17 = ~_T_16; // @[dec_tlu_ctl.scala 2582:55] + wire _T_20 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2583:80] + wire _T_21 = io_perfcnt_halted_d1 & _T_20; // @[dec_tlu_ctl.scala 2583:78] + wire _T_22 = ~_T_21; // @[dec_tlu_ctl.scala 2583:55] + wire _T_25 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2584:80] + wire _T_26 = io_perfcnt_halted_d1 & _T_25; // @[dec_tlu_ctl.scala 2584:78] + wire _T_27 = ~_T_26; // @[dec_tlu_ctl.scala 2584:55] + wire _T_30 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2585:80] + wire _T_31 = io_perfcnt_halted_d1 & _T_30; // @[dec_tlu_ctl.scala 2585:78] + wire _T_32 = ~_T_31; // @[dec_tlu_ctl.scala 2585:55] + wire _T_35 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2591:79] + wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_35; // @[dec_tlu_ctl.scala 2591:50] + wire _T_36 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2592:30] + wire _T_38 = _T_36 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2592:46] + wire _T_39 = |io_mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2592:96] + wire mhpmc3_wr_en1 = _T_38 & _T_39; // @[dec_tlu_ctl.scala 2592:73] + wire mhpmc3_wr_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[dec_tlu_ctl.scala 2593:43] + wire [63:0] _T_42 = {io_mhpmc3h,io_mhpmc3}; // @[Cat.scala 29:58] + wire [63:0] mhpmc3_incr = _T_42 + 64'h1; // @[dec_tlu_ctl.scala 2596:65] + reg [31:0] _T_48; // @[Reg.scala 27:20] + wire _T_50 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2601:80] + wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_50; // @[dec_tlu_ctl.scala 2601:51] + wire mhpmc3h_wr_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1; // @[dec_tlu_ctl.scala 2602:45] + reg [31:0] _T_54; // @[Reg.scala 27:20] + wire _T_56 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2612:79] + wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_56; // @[dec_tlu_ctl.scala 2612:50] + wire _T_59 = _T_36 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2613:46] + wire _T_60 = |io_mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2613:96] + wire mhpmc4_wr_en1 = _T_59 & _T_60; // @[dec_tlu_ctl.scala 2613:73] + wire mhpmc4_wr_en = mhpmc4_wr_en0 | mhpmc4_wr_en1; // @[dec_tlu_ctl.scala 2614:43] + wire [63:0] _T_63 = {io_mhpmc4h,io_mhpmc4}; // @[Cat.scala 29:58] + wire [63:0] mhpmc4_incr = _T_63 + 64'h1; // @[dec_tlu_ctl.scala 2618:65] + reg [31:0] _T_70; // @[Reg.scala 27:20] + wire _T_72 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2622:80] + wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_72; // @[dec_tlu_ctl.scala 2622:51] + wire mhpmc4h_wr_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1; // @[dec_tlu_ctl.scala 2623:45] + reg [31:0] _T_76; // @[Reg.scala 27:20] + wire _T_78 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2631:79] + wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_78; // @[dec_tlu_ctl.scala 2631:50] + wire _T_81 = _T_36 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2632:46] + wire _T_82 = |io_mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2632:96] + wire mhpmc5_wr_en1 = _T_81 & _T_82; // @[dec_tlu_ctl.scala 2632:73] + wire mhpmc5_wr_en = mhpmc5_wr_en0 | mhpmc5_wr_en1; // @[dec_tlu_ctl.scala 2633:43] + wire [63:0] _T_85 = {io_mhpmc5h,io_mhpmc5}; // @[Cat.scala 29:58] + wire [63:0] mhpmc5_incr = _T_85 + 64'h1; // @[dec_tlu_ctl.scala 2635:65] + reg [31:0] _T_91; // @[Reg.scala 27:20] + wire _T_93 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2640:80] + wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_93; // @[dec_tlu_ctl.scala 2640:51] + wire mhpmc5h_wr_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1; // @[dec_tlu_ctl.scala 2641:45] + reg [31:0] _T_97; // @[Reg.scala 27:20] + wire _T_99 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2651:79] + wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_99; // @[dec_tlu_ctl.scala 2651:50] + wire _T_102 = _T_36 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2652:46] + wire _T_103 = |io_mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2652:96] + wire mhpmc6_wr_en1 = _T_102 & _T_103; // @[dec_tlu_ctl.scala 2652:73] + wire mhpmc6_wr_en = mhpmc6_wr_en0 | mhpmc6_wr_en1; // @[dec_tlu_ctl.scala 2653:43] + wire [63:0] _T_106 = {io_mhpmc6h,io_mhpmc6}; // @[Cat.scala 29:58] + wire [63:0] mhpmc6_incr = _T_106 + 64'h1; // @[dec_tlu_ctl.scala 2655:65] + reg [31:0] _T_112; // @[Reg.scala 27:20] + wire _T_114 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2661:80] + wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_114; // @[dec_tlu_ctl.scala 2661:51] + wire mhpmc6h_wr_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[dec_tlu_ctl.scala 2662:45] + reg [31:0] _T_118; // @[Reg.scala 27:20] + wire _T_120 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2671:56] + wire _T_122 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2671:102] + wire _T_123 = _T_120 | _T_122; // @[dec_tlu_ctl.scala 2671:72] + wire _T_125 = io_dec_csr_wrdata_r[9:0] < 10'h200; // @[dec_tlu_ctl.scala 2672:44] + wire _T_127 = io_dec_csr_wrdata_r[9:0] > 10'h38; // @[dec_tlu_ctl.scala 2672:88] + wire _T_128 = _T_125 & _T_127; // @[dec_tlu_ctl.scala 2672:60] + wire _T_129 = _T_123 | _T_128; // @[dec_tlu_ctl.scala 2671:107] + wire _T_131 = io_dec_csr_wrdata_r[9:0] < 10'h36; // @[dec_tlu_ctl.scala 2673:44] + wire _T_133 = io_dec_csr_wrdata_r[9:0] > 10'h32; // @[dec_tlu_ctl.scala 2673:88] + wire _T_134 = _T_131 & _T_133; // @[dec_tlu_ctl.scala 2673:60] + wire _T_135 = _T_129 | _T_134; // @[dec_tlu_ctl.scala 2672:103] + wire _T_137 = io_dec_csr_wrdata_r[9:0] == 10'h1d; // @[dec_tlu_ctl.scala 2674:43] + wire _T_138 = _T_135 | _T_137; // @[dec_tlu_ctl.scala 2673:103] + wire _T_140 = io_dec_csr_wrdata_r[9:0] == 10'h21; // @[dec_tlu_ctl.scala 2674:87] + wire zero_event_r = _T_138 | _T_140; // @[dec_tlu_ctl.scala 2674:59] + wire _T_143 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2677:77] + wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_143; // @[dec_tlu_ctl.scala 2677:48] + reg [9:0] _T_145; // @[Reg.scala 27:20] + wire _T_147 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2684:77] + wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_147; // @[dec_tlu_ctl.scala 2684:48] + reg [9:0] _T_149; // @[Reg.scala 27:20] + wire _T_151 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2691:77] + wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_151; // @[dec_tlu_ctl.scala 2691:48] + reg [9:0] _T_153; // @[Reg.scala 27:20] + wire _T_155 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2698:77] + wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_155; // @[dec_tlu_ctl.scala 2698:48] + reg [9:0] _T_157; // @[Reg.scala 27:20] + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en) + ); + rvclkhdr rvclkhdr_10 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en) + ); + rvclkhdr rvclkhdr_11 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en) + ); + assign io_mhpmc3h = _T_54; // @[dec_tlu_ctl.scala 2605:20] + assign io_mhpmc3 = _T_48; // @[dec_tlu_ctl.scala 2599:19] + assign io_mhpmc4h = _T_76; // @[dec_tlu_ctl.scala 2625:20] + assign io_mhpmc4 = _T_70; // @[dec_tlu_ctl.scala 2620:19] + assign io_mhpmc5h = _T_97; // @[dec_tlu_ctl.scala 2644:20] + assign io_mhpmc5 = _T_91; // @[dec_tlu_ctl.scala 2638:19] + assign io_mhpmc6h = _T_118; // @[dec_tlu_ctl.scala 2665:20] + assign io_mhpmc6 = _T_112; // @[dec_tlu_ctl.scala 2659:19] + assign io_mhpme3 = _T_145; // @[dec_tlu_ctl.scala 2679:19] + assign io_mhpme4 = _T_149; // @[dec_tlu_ctl.scala 2685:19] + assign io_mhpme5 = _T_153; // @[dec_tlu_ctl.scala 2692:19] + assign io_mhpme6 = _T_157; // @[dec_tlu_ctl.scala 2699:19] + assign io_dec_tlu_perfcnt0 = io_mhpmc_inc_r_d1_0 & _T_17; // @[dec_tlu_ctl.scala 2582:29] + assign io_dec_tlu_perfcnt1 = io_mhpmc_inc_r_d1_1 & _T_22; // @[dec_tlu_ctl.scala 2583:29] + assign io_dec_tlu_perfcnt2 = io_mhpmc_inc_r_d1_2 & _T_27; // @[dec_tlu_ctl.scala 2584:29] + assign io_dec_tlu_perfcnt3 = io_mhpmc_inc_r_d1_3 & _T_32; // @[dec_tlu_ctl.scala 2585:29] + assign rvclkhdr_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = mhpmc4_wr_en0 | mhpmc4_wr_en1; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1; // @[lib.scala 407:17] + assign rvclkhdr_4_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_4_io_en = mhpmc5_wr_en0 | mhpmc5_wr_en1; // @[lib.scala 407:17] + assign rvclkhdr_5_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_5_io_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1; // @[lib.scala 407:17] + assign rvclkhdr_6_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_6_io_en = mhpmc6_wr_en0 | mhpmc6_wr_en1; // @[lib.scala 407:17] + assign rvclkhdr_7_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_7_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[lib.scala 407:17] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_8_io_en = io_dec_csr_wen_r_mod & _T_143; // @[lib.scala 407:17] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_9_io_en = io_dec_csr_wen_r_mod & _T_147; // @[lib.scala 407:17] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_151; // @[lib.scala 407:17] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_11_io_en = io_dec_csr_wen_r_mod & _T_155; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T_48 = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + _T_54 = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + _T_70 = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + _T_76 = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + _T_91 = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + _T_97 = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + _T_112 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + _T_118 = _RAND_7[31:0]; + _RAND_8 = {1{`RANDOM}}; + _T_145 = _RAND_8[9:0]; + _RAND_9 = {1{`RANDOM}}; + _T_149 = _RAND_9[9:0]; + _RAND_10 = {1{`RANDOM}}; + _T_153 = _RAND_10[9:0]; + _RAND_11 = {1{`RANDOM}}; + _T_157 = _RAND_11[9:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_48 = 32'h0; + end + if (reset) begin + _T_54 = 32'h0; + end + if (reset) begin + _T_70 = 32'h0; + end + if (reset) begin + _T_76 = 32'h0; + end + if (reset) begin + _T_91 = 32'h0; + end + if (reset) begin + _T_97 = 32'h0; + end + if (reset) begin + _T_112 = 32'h0; + end + if (reset) begin + _T_118 = 32'h0; + end + if (reset) begin + _T_145 = 10'h0; + end + if (reset) begin + _T_149 = 10'h0; + end + if (reset) begin + _T_153 = 10'h0; + end + if (reset) begin + _T_157 = 10'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_48 <= 32'h0; + end else if (mhpmc3_wr_en) begin + if (mhpmc3_wr_en0) begin + _T_48 <= io_dec_csr_wrdata_r; + end else begin + _T_48 <= mhpmc3_incr[31:0]; + end + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_54 <= 32'h0; + end else if (mhpmc3h_wr_en) begin + if (mhpmc3h_wr_en0) begin + _T_54 <= io_dec_csr_wrdata_r; + end else begin + _T_54 <= mhpmc3_incr[63:32]; + end + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_70 <= 32'h0; + end else if (mhpmc4_wr_en) begin + if (mhpmc4_wr_en0) begin + _T_70 <= io_dec_csr_wrdata_r; + end else begin + _T_70 <= mhpmc4_incr[31:0]; + end + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_76 <= 32'h0; + end else if (mhpmc4h_wr_en) begin + if (mhpmc4h_wr_en0) begin + _T_76 <= io_dec_csr_wrdata_r; + end else begin + _T_76 <= mhpmc4_incr[63:32]; + end + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_91 <= 32'h0; + end else if (mhpmc5_wr_en) begin + if (mhpmc5_wr_en0) begin + _T_91 <= io_dec_csr_wrdata_r; + end else begin + _T_91 <= mhpmc5_incr[31:0]; + end + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_97 <= 32'h0; + end else if (mhpmc5h_wr_en) begin + if (mhpmc5h_wr_en0) begin + _T_97 <= io_dec_csr_wrdata_r; + end else begin + _T_97 <= mhpmc5_incr[63:32]; + end + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_112 <= 32'h0; + end else if (mhpmc6_wr_en) begin + if (mhpmc6_wr_en0) begin + _T_112 <= io_dec_csr_wrdata_r; + end else begin + _T_112 <= mhpmc6_incr[31:0]; + end + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_118 <= 32'h0; + end else if (mhpmc6h_wr_en) begin + if (mhpmc6h_wr_en0) begin + _T_118 <= io_dec_csr_wrdata_r; + end else begin + _T_118 <= mhpmc6_incr[63:32]; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_145 <= 10'h0; + end else if (wr_mhpme3_r) begin + if (zero_event_r) begin + _T_145 <= 10'h0; + end else begin + _T_145 <= io_dec_csr_wrdata_r[9:0]; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_149 <= 10'h0; + end else if (wr_mhpme4_r) begin + if (zero_event_r) begin + _T_149 <= 10'h0; + end else begin + _T_149 <= io_dec_csr_wrdata_r[9:0]; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_153 <= 10'h0; + end else if (wr_mhpme5_r) begin + if (zero_event_r) begin + _T_153 <= 10'h0; + end else begin + _T_153 <= io_dec_csr_wrdata_r[9:0]; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_157 <= 10'h0; + end else if (wr_mhpme6_r) begin + if (zero_event_r) begin + _T_157 <= 10'h0; + end else begin + _T_157 <= io_dec_csr_wrdata_r[9:0]; + end + end + end +endmodule +module csr_tlu( + input clock, + input reset, + input io_free_l2clk, + input io_free_clk, + input [31:0] io_dec_csr_wrdata_r, + input [11:0] io_dec_csr_wraddr_r, + input [11:0] io_dec_csr_rdaddr_d, + input io_dec_csr_wen_unq_d, + input io_dec_i0_decode_d, + output [70:0] io_dec_tlu_ic_diag_pkt_icache_wrdata, + output [16:0] io_dec_tlu_ic_diag_pkt_icache_dicawics, + output io_dec_tlu_ic_diag_pkt_icache_rd_valid, + output io_dec_tlu_ic_diag_pkt_icache_wr_valid, + input io_ifu_ic_debug_rd_data_valid, + output io_trigger_pkt_any_0_select, + output io_trigger_pkt_any_0_match_pkt, + output io_trigger_pkt_any_0_store, + output io_trigger_pkt_any_0_load, + output io_trigger_pkt_any_0_execute, + output io_trigger_pkt_any_0_m, + output [31:0] io_trigger_pkt_any_0_tdata2, + output io_trigger_pkt_any_1_select, + output io_trigger_pkt_any_1_match_pkt, + output io_trigger_pkt_any_1_store, + output io_trigger_pkt_any_1_load, + output io_trigger_pkt_any_1_execute, + output io_trigger_pkt_any_1_m, + output [31:0] io_trigger_pkt_any_1_tdata2, + output io_trigger_pkt_any_2_select, + output io_trigger_pkt_any_2_match_pkt, + output io_trigger_pkt_any_2_store, + output io_trigger_pkt_any_2_load, + output io_trigger_pkt_any_2_execute, + output io_trigger_pkt_any_2_m, + output [31:0] io_trigger_pkt_any_2_tdata2, + output io_trigger_pkt_any_3_select, + output io_trigger_pkt_any_3_match_pkt, + output io_trigger_pkt_any_3_store, + output io_trigger_pkt_any_3_load, + output io_trigger_pkt_any_3_execute, + output io_trigger_pkt_any_3_m, + output [31:0] io_trigger_pkt_any_3_tdata2, + input io_ifu_pmu_bus_trxn, + input io_dma_iccm_stall_any, + input io_dma_dccm_stall_any, + input io_lsu_store_stall_any, + input io_dec_pmu_presync_stall, + input io_dec_pmu_postsync_stall, + input io_dec_pmu_decode_stall, + input io_ifu_pmu_fetch_stall, + input [1:0] io_dec_tlu_packet_r_icaf_type, + input [3:0] io_dec_tlu_packet_r_pmu_i0_itype, + input io_dec_tlu_packet_r_pmu_i0_br_unpred, + input io_dec_tlu_packet_r_pmu_divide, + input io_dec_tlu_packet_r_pmu_lsu_misaligned, + input io_exu_pmu_i0_br_ataken, + input io_exu_pmu_i0_br_misp, + input io_dec_pmu_instr_decoded, + input io_ifu_pmu_instr_aligned, + input io_exu_pmu_i0_pc4, + input io_ifu_pmu_ic_miss, + input io_ifu_pmu_ic_hit, + output io_dec_tlu_int_valid_wb1, + output io_dec_tlu_i0_exc_valid_wb1, + output io_dec_tlu_i0_valid_wb1, + input io_dec_csr_wen_r, + output [31:0] io_dec_tlu_mtval_wb1, + output [4:0] io_dec_tlu_exc_cause_wb1, + output io_dec_tlu_perfcnt0, + output io_dec_tlu_perfcnt1, + output io_dec_tlu_perfcnt2, + output io_dec_tlu_perfcnt3, + input io_dec_tlu_dbg_halted, + input io_dma_pmu_dccm_write, + input io_dma_pmu_dccm_read, + input io_dma_pmu_any_write, + input io_dma_pmu_any_read, + input io_lsu_pmu_bus_busy, + input [30:0] io_dec_tlu_i0_pc_r, + input io_dec_tlu_i0_valid_r, + input io_dec_csr_any_unq_d, + output io_dec_tlu_misc_clk_override, + output io_dec_tlu_picio_clk_override, + output io_dec_tlu_dec_clk_override, + output io_dec_tlu_ifu_clk_override, + output io_dec_tlu_lsu_clk_override, + output io_dec_tlu_bus_clk_override, + output io_dec_tlu_pic_clk_override, + output io_dec_tlu_dccm_clk_override, + output io_dec_tlu_icm_clk_override, + output [31:0] io_dec_csr_rddata_d, + output io_dec_tlu_pipelining_disable, + output io_dec_tlu_wr_pause_r, + input io_ifu_pmu_bus_busy, + input io_lsu_pmu_bus_error, + input io_ifu_pmu_bus_error, + input io_lsu_pmu_bus_misaligned, + input io_lsu_pmu_bus_trxn, + input [70:0] io_ifu_ic_debug_rd_data, + output [3:0] io_dec_tlu_meipt, + input [3:0] io_pic_pl, + output [3:0] io_dec_tlu_meicurpl, + output [29:0] io_dec_tlu_meihap, + input [7:0] io_pic_claimid, + input io_iccm_dma_sb_error, + input [31:0] io_lsu_imprecise_error_addr_any, + input io_lsu_imprecise_error_load_any, + input io_lsu_imprecise_error_store_any, + output [31:0] io_dec_tlu_mrac_ff, + output io_dec_tlu_wb_coalescing_disable, + output io_dec_tlu_bpred_disable, + output io_dec_tlu_sideeffect_posted_disable, + output io_dec_tlu_core_ecc_disable, + output io_dec_tlu_external_ldfwd_disable, + output [2:0] io_dec_tlu_dma_qos_prty, + output io_dec_tlu_trace_disable, + input [31:0] io_dec_illegal_inst, + input [3:0] io_lsu_error_pkt_r_bits_mscause, + input io_mexintpend, + input [30:0] io_exu_npc_r, + input io_mpc_reset_run_req, + input [30:0] io_rst_vec, + input [27:0] io_core_id, + input [31:0] io_dec_timer_rddata_d, + input io_dec_timer_read_d, + output io_dec_csr_wen_r_mod, + input io_rfpc_i0_r, + input io_i0_trigger_hit_r, + output io_fw_halt_req, + output [1:0] io_mstatus, + input io_exc_or_int_valid_r, + input io_mret_r, + output io_mstatus_mie_ns, + input io_dcsr_single_step_running_f, + output [15:0] io_dcsr, + output [30:0] io_mtvec, + output [5:0] io_mip, + input io_dec_timer_t0_pulse, + input io_dec_timer_t1_pulse, + input io_timer_int_sync, + input io_soft_int_sync, + output [5:0] io_mie_ns, + input io_csr_wr_clk, + input io_ebreak_to_debug_mode_r, + input io_dec_tlu_pmu_fw_halted, + input [1:0] io_lsu_fir_error, + output [30:0] io_npc_r, + input io_tlu_flush_lower_r_d1, + input io_dec_tlu_flush_noredir_r_d1, + input [30:0] io_tlu_flush_path_r_d1, + output [30:0] io_npc_r_d1, + input io_reset_delayed, + output [30:0] io_mepc, + input io_interrupt_valid_r, + input io_i0_exception_valid_r, + input io_lsu_exc_valid_r, + input io_mepc_trigger_hit_sel_pc_r, + input io_lsu_single_ecc_error_r, + input io_e4e5_int_clk, + input io_lsu_i0_exc_r, + input io_inst_acc_r, + input io_inst_acc_second_r, + input io_take_nmi, + input [31:0] io_lsu_error_pkt_addr_r, + input [4:0] io_exc_cause_r, + input io_i0_valid_wb, + input io_interrupt_valid_r_d1, + input io_i0_exception_valid_r_d1, + input [4:0] io_exc_cause_wb, + input io_nmi_lsu_store_type, + input io_nmi_lsu_load_type, + input io_tlu_i0_commit_cmt, + input io_ebreak_r, + input io_ecall_r, + input io_illegal_r, + output io_mdseac_locked_ns, + output io_mdseac_locked_f, + input io_nmi_int_detected_f, + input io_internal_dbg_halt_mode_f2, + input io_ext_int_freeze, + output io_ext_int_freeze_d1, + output io_take_ext_int_start_d1, + output io_take_ext_int_start_d2, + output io_take_ext_int_start_d3, + input io_ic_perr_r, + input io_iccm_sbecc_r, + input io_ifu_miss_state_idle_f, + input io_lsu_idle_any_f, + input io_dbg_tlu_halted_f, + input io_dbg_tlu_halted, + input io_debug_halt_req_f, + output io_force_halt, + input io_take_ext_int_start, + input io_trigger_hit_dmode_r_d1, + input io_trigger_hit_r_d1, + input io_dcsr_single_step_done_f, + input io_ebreak_to_debug_mode_r_d1, + input io_debug_halt_req, + input io_allow_dbg_halt_csr_write, + input io_internal_dbg_halt_mode_f, + input io_enter_debug_halt_req, + input io_internal_dbg_halt_mode, + input io_request_debug_mode_done, + input io_request_debug_mode_r, + output [30:0] io_dpc, + input [3:0] io_update_hit_bit_r, + input io_take_timer_int, + input io_take_int_timer0_int, + input io_take_int_timer1_int, + input io_take_ext_int, + input io_tlu_flush_lower_r, + input io_dec_tlu_br0_error_r, + input io_dec_tlu_br0_start_error_r, + input io_lsu_pmu_load_external_r, + input io_lsu_pmu_store_external_r, + input io_csr_pkt_csr_misa, + input io_csr_pkt_csr_mvendorid, + input io_csr_pkt_csr_marchid, + input io_csr_pkt_csr_mimpid, + input io_csr_pkt_csr_mhartid, + input io_csr_pkt_csr_mstatus, + input io_csr_pkt_csr_mtvec, + input io_csr_pkt_csr_mip, + input io_csr_pkt_csr_mie, + input io_csr_pkt_csr_mcyclel, + input io_csr_pkt_csr_mcycleh, + input io_csr_pkt_csr_minstretl, + input io_csr_pkt_csr_minstreth, + input io_csr_pkt_csr_mscratch, + input io_csr_pkt_csr_mepc, + input io_csr_pkt_csr_mcause, + input io_csr_pkt_csr_mscause, + input io_csr_pkt_csr_mtval, + input io_csr_pkt_csr_mrac, + input io_csr_pkt_csr_mdseac, + input io_csr_pkt_csr_meihap, + input io_csr_pkt_csr_meivt, + input io_csr_pkt_csr_meipt, + input io_csr_pkt_csr_meicurpl, + input io_csr_pkt_csr_meicidpl, + input io_csr_pkt_csr_dcsr, + input io_csr_pkt_csr_mcgc, + input io_csr_pkt_csr_mfdc, + input io_csr_pkt_csr_dpc, + input io_csr_pkt_csr_mtsel, + input io_csr_pkt_csr_mtdata1, + input io_csr_pkt_csr_mtdata2, + input io_csr_pkt_csr_mhpmc3, + input io_csr_pkt_csr_mhpmc4, + input io_csr_pkt_csr_mhpmc5, + input io_csr_pkt_csr_mhpmc6, + input io_csr_pkt_csr_mhpmc3h, + input io_csr_pkt_csr_mhpmc4h, + input io_csr_pkt_csr_mhpmc5h, + input io_csr_pkt_csr_mhpmc6h, + input io_csr_pkt_csr_mhpme3, + input io_csr_pkt_csr_mhpme4, + input io_csr_pkt_csr_mhpme5, + input io_csr_pkt_csr_mhpme6, + input io_csr_pkt_csr_mcountinhibit, + input io_csr_pkt_csr_mpmc, + input io_csr_pkt_csr_micect, + input io_csr_pkt_csr_miccmect, + input io_csr_pkt_csr_mdccmect, + input io_csr_pkt_csr_mfdht, + input io_csr_pkt_csr_mfdhs, + input io_csr_pkt_csr_dicawics, + input io_csr_pkt_csr_dicad0h, + input io_csr_pkt_csr_dicad0, + input io_csr_pkt_csr_dicad1, + output [9:0] io_mtdata1_t_0, + output [9:0] io_mtdata1_t_1, + output [9:0] io_mtdata1_t_2, + output [9:0] io_mtdata1_t_3, + input [3:0] io_trigger_enabled +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; +`endif // RANDOMIZE_REG_INIT + wire perfmux_flop_reset; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 1455:34] + wire [6:0] perfmux_flop_io_mcountinhibit; // @[dec_tlu_ctl.scala 1455:34] + wire [9:0] perfmux_flop_io_mhpme_vec_0; // @[dec_tlu_ctl.scala 1455:34] + wire [9:0] perfmux_flop_io_mhpme_vec_1; // @[dec_tlu_ctl.scala 1455:34] + wire [9:0] perfmux_flop_io_mhpme_vec_2; // @[dec_tlu_ctl.scala 1455:34] + wire [9:0] perfmux_flop_io_mhpme_vec_3; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_illegal_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 1455:34] + wire [3:0] perfmux_flop_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dma_pmu_any_read; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dma_pmu_any_write; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 1455:34] + wire [1:0] perfmux_flop_io_mstatus; // @[dec_tlu_ctl.scala 1455:34] + wire [5:0] perfmux_flop_io_mie; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_take_timer_int; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_take_ext_int; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_tlu_br0_error_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mcyclel_cout_f; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_minstret_enable_f; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_minstretl_cout_f; // @[dec_tlu_ctl.scala 1455:34] + wire [3:0] perfmux_flop_io_meicidpl; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_icache_rd_valid_f; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_icache_wr_valid_f; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_perfcnt_halted_d1; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_take_ext_int_start_d2; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1455:34] + wire [5:0] perfmux_flop_io_mip; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mdseac_locked_ns; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_single_ecc_error_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_take_ext_int_start; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_ext_int_freeze; // @[dec_tlu_ctl.scala 1455:34] + wire [5:0] perfmux_flop_io_mip_ns; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mcyclel_cout; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_wr_mcycleh_r; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_mcyclel_cout_in; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_minstret_enable; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_minstretl_cout_ns; // @[dec_tlu_ctl.scala 1455:34] + wire [3:0] perfmux_flop_io_meicidpl_ns; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_icache_rd_valid; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_icache_wr_valid; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_perfcnt_halted; // @[dec_tlu_ctl.scala 1455:34] + wire [1:0] perfmux_flop_io_mstatus_ns; // @[dec_tlu_ctl.scala 1455:34] + wire perfmux_flop_io_free_l2clk; // @[dec_tlu_ctl.scala 1455:34] + wire perf_csrs_clock; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_reset; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_free_l2clk; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 1456:31] + wire [15:0] perf_csrs_io_dcsr; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 1456:31] + wire [9:0] perf_csrs_io_mhpme_vec_0; // @[dec_tlu_ctl.scala 1456:31] + wire [9:0] perf_csrs_io_mhpme_vec_1; // @[dec_tlu_ctl.scala 1456:31] + wire [9:0] perf_csrs_io_mhpme_vec_2; // @[dec_tlu_ctl.scala 1456:31] + wire [9:0] perf_csrs_io_mhpme_vec_3; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 1456:31] + wire [11:0] perf_csrs_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 1456:31] + wire [31:0] perf_csrs_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_perfcnt_halted_d1; // @[dec_tlu_ctl.scala 1456:31] + wire [31:0] perf_csrs_io_mhpmc3h; // @[dec_tlu_ctl.scala 1456:31] + wire [31:0] perf_csrs_io_mhpmc3; // @[dec_tlu_ctl.scala 1456:31] + wire [31:0] perf_csrs_io_mhpmc4h; // @[dec_tlu_ctl.scala 1456:31] + wire [31:0] perf_csrs_io_mhpmc4; // @[dec_tlu_ctl.scala 1456:31] + wire [31:0] perf_csrs_io_mhpmc5h; // @[dec_tlu_ctl.scala 1456:31] + wire [31:0] perf_csrs_io_mhpmc5; // @[dec_tlu_ctl.scala 1456:31] + wire [31:0] perf_csrs_io_mhpmc6h; // @[dec_tlu_ctl.scala 1456:31] + wire [31:0] perf_csrs_io_mhpmc6; // @[dec_tlu_ctl.scala 1456:31] + wire [9:0] perf_csrs_io_mhpme3; // @[dec_tlu_ctl.scala 1456:31] + wire [9:0] perf_csrs_io_mhpme4; // @[dec_tlu_ctl.scala 1456:31] + wire [9:0] perf_csrs_io_mhpme5; // @[dec_tlu_ctl.scala 1456:31] + wire [9:0] perf_csrs_io_mhpme6; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 1456:31] + wire perf_csrs_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 1456:31] + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_4_io_en; // @[lib.scala 404:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_5_io_en; // @[lib.scala 404:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_6_io_en; // @[lib.scala 404:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_7_io_en; // @[lib.scala 404:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_8_io_en; // @[lib.scala 404:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_9_io_en; // @[lib.scala 404:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_10_io_en; // @[lib.scala 404:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_11_io_en; // @[lib.scala 404:23] + wire rvclkhdr_12_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_12_io_en; // @[lib.scala 404:23] + wire rvclkhdr_13_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_13_io_en; // @[lib.scala 404:23] + wire rvclkhdr_14_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_14_io_en; // @[lib.scala 404:23] + wire rvclkhdr_15_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_15_io_en; // @[lib.scala 404:23] + wire rvclkhdr_16_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_16_io_en; // @[lib.scala 404:23] + wire rvclkhdr_17_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_17_io_en; // @[lib.scala 404:23] + wire rvclkhdr_18_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_18_io_en; // @[lib.scala 404:23] + wire rvclkhdr_19_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_19_io_en; // @[lib.scala 404:23] + wire rvclkhdr_20_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_20_io_en; // @[lib.scala 404:23] + wire rvclkhdr_21_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_21_io_en; // @[lib.scala 404:23] + wire rvclkhdr_22_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_22_io_en; // @[lib.scala 404:23] + wire rvclkhdr_23_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_23_io_en; // @[lib.scala 404:23] + wire rvclkhdr_24_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_24_io_en; // @[lib.scala 404:23] + wire rvclkhdr_25_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_25_io_en; // @[lib.scala 404:23] + wire rvclkhdr_26_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_26_io_en; // @[lib.scala 404:23] + wire rvclkhdr_27_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_27_io_en; // @[lib.scala 404:23] + wire rvclkhdr_28_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_28_io_en; // @[lib.scala 404:23] + wire rvclkhdr_29_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_29_io_en; // @[lib.scala 404:23] + wire rvclkhdr_30_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_30_io_en; // @[lib.scala 404:23] + wire rvclkhdr_31_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_31_io_en; // @[lib.scala 404:23] + wire rvclkhdr_32_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_32_io_en; // @[lib.scala 404:23] + wire rvclkhdr_33_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_33_io_en; // @[lib.scala 404:23] + wire rvclkhdr_34_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_34_io_en; // @[lib.scala 404:23] + wire _T = ~io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 1472:52] + wire _T_1 = io_dec_csr_wen_r & _T; // @[dec_tlu_ctl.scala 1472:50] + wire _T_2 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1472:75] + wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[dec_tlu_ctl.scala 1473:78] + wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[dec_tlu_ctl.scala 1473:49] + wire _T_553 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1883:69] + wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_553; // @[dec_tlu_ctl.scala 1883:46] + wire _T_565 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1891:44] + reg mpmc_b; // @[dec_tlu_ctl.scala 1893:51] + wire mpmc = ~mpmc_b; // @[dec_tlu_ctl.scala 1896:17] + wire _T_566 = ~mpmc; // @[dec_tlu_ctl.scala 1891:69] + wire mpmc_b_ns = wr_mpmc_r ? _T_565 : _T_566; // @[dec_tlu_ctl.scala 1891:25] + wire _T_6 = ~mpmc_b_ns; // @[dec_tlu_ctl.scala 1476:35] + wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[dec_tlu_ctl.scala 1476:46] + wire _T_7 = ~wr_mstatus_r; // @[dec_tlu_ctl.scala 1479:18] + wire _T_8 = _T_7 & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1479:32] + wire [1:0] _T_12 = {io_mstatus[0],1'h0}; // @[Cat.scala 29:58] + wire _T_13 = wr_mstatus_r & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1480:31] + wire [1:0] _T_16 = {io_dec_csr_wrdata_r[3],1'h0}; // @[Cat.scala 29:58] + wire _T_17 = ~io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1481:30] + wire _T_18 = io_mret_r & _T_17; // @[dec_tlu_ctl.scala 1481:28] + wire [1:0] _T_21 = {1'h1,io_mstatus[1]}; // @[Cat.scala 29:58] + wire [1:0] _T_24 = {io_mstatus[1],1'h1}; // @[Cat.scala 29:58] + wire _T_26 = wr_mstatus_r & _T_17; // @[dec_tlu_ctl.scala 1483:31] + wire [1:0] _T_30 = {io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58] + wire _T_33 = _T_7 & _T_17; // @[dec_tlu_ctl.scala 1484:32] + wire _T_34 = ~io_mret_r; // @[dec_tlu_ctl.scala 1484:59] + wire _T_35 = _T_33 & _T_34; // @[dec_tlu_ctl.scala 1484:57] + wire _T_36 = ~set_mie_pmu_fw_halt; // @[dec_tlu_ctl.scala 1484:72] + wire _T_37 = _T_35 & _T_36; // @[dec_tlu_ctl.scala 1484:70] + wire [1:0] _T_39 = _T_8 ? _T_12 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_40 = _T_13 ? _T_16 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_41 = _T_18 ? _T_21 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_42 = set_mie_pmu_fw_halt ? _T_24 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_43 = _T_26 ? _T_30 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_44 = _T_37 ? io_mstatus : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_45 = _T_39 | _T_40; // @[Mux.scala 27:72] + wire [1:0] _T_46 = _T_45 | _T_41; // @[Mux.scala 27:72] + wire [1:0] _T_47 = _T_46 | _T_42; // @[Mux.scala 27:72] + wire [1:0] _T_48 = _T_47 | _T_43; // @[Mux.scala 27:72] + wire _T_52 = ~io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 1489:57] + wire _T_54 = _T_52 | io_dcsr[11]; // @[dec_tlu_ctl.scala 1489:88] + wire _T_57 = io_dec_csr_wraddr_r == 12'h305; // @[dec_tlu_ctl.scala 1500:76] + wire wr_mtvec_r = io_dec_csr_wen_r_mod & _T_57; // @[dec_tlu_ctl.scala 1500:47] + wire [30:0] mtvec_ns = {io_dec_csr_wrdata_r[31:2],io_dec_csr_wrdata_r[0]}; // @[Cat.scala 29:58] + reg [30:0] _T_61; // @[Reg.scala 27:20] + reg [31:0] mdccmect; // @[Reg.scala 27:20] + wire [62:0] _T_629 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1942:48] + wire [31:0] _T_631 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_43 = {{31'd0}, _T_631}; // @[dec_tlu_ctl.scala 1942:68] + wire [62:0] _T_632 = _T_629 & _GEN_43; // @[dec_tlu_ctl.scala 1942:68] + wire mdccme_ce_req = |_T_632; // @[dec_tlu_ctl.scala 1942:101] + reg [31:0] miccmect; // @[Reg.scala 27:20] + wire [62:0] _T_609 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1928:48] + wire [31:0] _T_611 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_44 = {{31'd0}, _T_611}; // @[dec_tlu_ctl.scala 1928:68] + wire [62:0] _T_612 = _T_609 & _GEN_44; // @[dec_tlu_ctl.scala 1928:68] + wire miccme_ce_req = |_T_612; // @[dec_tlu_ctl.scala 1928:101] + wire _T_62 = mdccme_ce_req | miccme_ce_req; // @[dec_tlu_ctl.scala 1514:37] + reg [31:0] micect; // @[Reg.scala 27:20] + wire [62:0] _T_587 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1913:46] + wire [31:0] _T_589 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_45 = {{31'd0}, _T_589}; // @[dec_tlu_ctl.scala 1913:64] + wire [62:0] _T_590 = _T_587 & _GEN_45; // @[dec_tlu_ctl.scala 1913:64] + wire mice_ce_req = |_T_590; // @[dec_tlu_ctl.scala 1913:95] + wire ce_int = _T_62 | mice_ce_req; // @[dec_tlu_ctl.scala 1514:53] + wire [2:0] _T_64 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58] + wire [2:0] _T_66 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58] + wire _T_68 = io_dec_csr_wraddr_r == 12'h304; // @[dec_tlu_ctl.scala 1530:74] + wire wr_mie_r = io_dec_csr_wen_r_mod & _T_68; // @[dec_tlu_ctl.scala 1530:45] + wire [5:0] _T_76 = {io_dec_csr_wrdata_r[30:28],io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58] + reg [5:0] mie; // @[dec_tlu_ctl.scala 1533:24] + wire kill_ebreak_count_r = io_ebreak_to_debug_mode_r & io_dcsr[10]; // @[dec_tlu_ctl.scala 1539:61] + wire _T_81 = io_dec_csr_wraddr_r == 12'hb00; // @[dec_tlu_ctl.scala 1541:78] + wire wr_mcyclel_r = io_dec_csr_wen_r_mod & _T_81; // @[dec_tlu_ctl.scala 1541:49] + wire _T_83 = io_dec_tlu_dbg_halted & io_dcsr[10]; // @[dec_tlu_ctl.scala 1543:78] + wire _T_84 = kill_ebreak_count_r | _T_83; // @[dec_tlu_ctl.scala 1543:53] + wire _T_85 = _T_84 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 1543:101] + reg [4:0] temp_ncount6_2; // @[Reg.scala 27:20] + wire [5:0] _T_1138 = {temp_ncount6_2,1'h0}; // @[Cat.scala 29:58] + reg temp_ncount0; // @[Reg.scala 27:20] + wire [6:0] mcountinhibit = {temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire _T_87 = _T_85 | mcountinhibit[0]; // @[dec_tlu_ctl.scala 1543:128] + wire mcyclel_cout_in = ~_T_87; // @[dec_tlu_ctl.scala 1543:31] + reg [23:0] _T_106; // @[Reg.scala 27:20] + reg [7:0] _T_110; // @[Reg.scala 27:20] + wire [31:0] mcyclel = {_T_106,_T_110}; // @[Cat.scala 29:58] + wire [8:0] mcyclel_inc1 = mcyclel[7:0] + 8'h1; // @[dec_tlu_ctl.scala 1548:38] + wire [23:0] _T_93 = {23'h0,mcyclel_inc1[8]}; // @[Cat.scala 29:58] + wire [24:0] mcyclel_inc2 = mcyclel[31:8] + _T_93; // @[dec_tlu_ctl.scala 1549:39] + wire [31:0] mcyclel_inc = {mcyclel_inc2[23:0],mcyclel_inc1[7:0]}; // @[Cat.scala 29:58] + wire [31:0] mcyclel_ns = wr_mcyclel_r ? io_dec_csr_wrdata_r : mcyclel_inc; // @[dec_tlu_ctl.scala 1551:29] + wire _T_102 = mcyclel_inc1[8] & mcyclel_cout_in; // @[dec_tlu_ctl.scala 1553:82] + wire _T_104 = wr_mcyclel_r | _T_102; // @[dec_tlu_ctl.scala 1553:63] + wire _T_108 = wr_mcyclel_r | mcyclel_cout_in; // @[dec_tlu_ctl.scala 1553:184] + wire _T_113 = io_dec_csr_wraddr_r == 12'hb80; // @[dec_tlu_ctl.scala 1560:78] + wire wr_mcycleh_r = io_dec_csr_wen_r_mod & _T_113; // @[dec_tlu_ctl.scala 1560:49] + wire [31:0] _T_114 = {31'h0,perfmux_flop_io_mcyclel_cout_f}; // @[Cat.scala 29:58] + reg [31:0] mcycleh; // @[Reg.scala 27:20] + wire [31:0] mcycleh_inc = mcycleh + _T_114; // @[dec_tlu_ctl.scala 1562:35] + wire _T_117 = wr_mcycleh_r | perfmux_flop_io_mcyclel_cout_f; // @[dec_tlu_ctl.scala 1565:53] + wire _T_120 = io_ebreak_r | io_ecall_r; // @[dec_tlu_ctl.scala 1579:81] + wire _T_121 = _T_120 | io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 1579:94] + wire _T_122 = _T_121 | io_illegal_r; // @[dec_tlu_ctl.scala 1579:122] + wire _T_124 = _T_122 | mcountinhibit[2]; // @[dec_tlu_ctl.scala 1579:137] + wire _T_125 = ~_T_124; // @[dec_tlu_ctl.scala 1579:67] + wire i0_valid_no_ebreak_ecall_r = io_dec_tlu_i0_valid_r & _T_125; // @[dec_tlu_ctl.scala 1579:65] + wire _T_128 = io_dec_csr_wraddr_r == 12'hb02; // @[dec_tlu_ctl.scala 1581:80] + wire wr_minstretl_r = io_dec_csr_wen_r_mod & _T_128; // @[dec_tlu_ctl.scala 1581:51] + reg [23:0] _T_150; // @[Reg.scala 27:20] + reg [7:0] _T_153; // @[Reg.scala 27:20] + wire [31:0] minstretl = {_T_150,_T_153}; // @[Cat.scala 29:58] + wire [8:0] minstretl_inc1 = minstretl[7:0] + 8'h1; // @[dec_tlu_ctl.scala 1585:42] + wire [23:0] _T_134 = {23'h0,minstretl_inc1[8]}; // @[Cat.scala 29:58] + wire [24:0] minstretl_inc2 = minstretl[31:8] + _T_134; // @[dec_tlu_ctl.scala 1586:43] + wire minstretl_cout = minstretl_inc2[24]; // @[dec_tlu_ctl.scala 1587:44] + wire [31:0] minstretl_inc = {minstretl_inc2[23:0],minstretl_inc1[7:0]}; // @[Cat.scala 29:58] + wire _T_138 = i0_valid_no_ebreak_ecall_r & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 1589:59] + wire minstret_enable = _T_138 | wr_minstretl_r; // @[dec_tlu_ctl.scala 1589:83] + wire _T_156 = io_dec_csr_wraddr_r == 12'hb82; // @[dec_tlu_ctl.scala 1605:78] + wire wr_minstreth_r = io_dec_csr_wen_r_mod & _T_156; // @[dec_tlu_ctl.scala 1605:49] + wire _T_139 = ~wr_minstreth_r; // @[dec_tlu_ctl.scala 1590:50] + wire _T_140 = minstretl_cout & _T_139; // @[dec_tlu_ctl.scala 1590:48] + wire _T_141 = _T_140 & i0_valid_no_ebreak_ecall_r; // @[dec_tlu_ctl.scala 1590:66] + wire _T_142 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 1590:97] + wire [31:0] minstretl_ns = wr_minstretl_r ? io_dec_csr_wrdata_r : minstretl_inc; // @[dec_tlu_ctl.scala 1593:31] + wire _T_147 = minstretl_inc1[8] & minstret_enable; // @[dec_tlu_ctl.scala 1595:88] + wire _T_148 = wr_minstretl_r | _T_147; // @[dec_tlu_ctl.scala 1595:67] + wire [31:0] _T_159 = {31'h0,perfmux_flop_io_minstretl_cout_f}; // @[Cat.scala 29:58] + reg [31:0] minstreth; // @[Reg.scala 27:20] + wire [31:0] minstreth_inc = minstreth + _T_159; // @[dec_tlu_ctl.scala 1609:39] + wire _T_162 = perfmux_flop_io_minstret_enable_f & perfmux_flop_io_minstretl_cout_f; // @[dec_tlu_ctl.scala 1612:79] + wire _T_163 = _T_162 | wr_minstreth_r; // @[dec_tlu_ctl.scala 1612:116] + wire _T_167 = io_dec_csr_wraddr_r == 12'h340; // @[dec_tlu_ctl.scala 1620:79] + wire wr_mscratch_r = io_dec_csr_wen_r_mod & _T_167; // @[dec_tlu_ctl.scala 1620:50] + reg [31:0] mscratch; // @[Reg.scala 27:20] + wire _T_171 = ~io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1631:54] + wire _T_172 = _T_142 & _T_171; // @[dec_tlu_ctl.scala 1631:52] + wire sel_exu_npc_r = _T_172 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1631:79] + wire _T_174 = _T_142 & io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1632:54] + wire _T_175 = ~io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 1632:82] + wire sel_flush_npc_r = _T_174 & _T_175; // @[dec_tlu_ctl.scala 1632:80] + wire _T_176 = ~sel_exu_npc_r; // @[dec_tlu_ctl.scala 1633:30] + wire _T_177 = ~sel_flush_npc_r; // @[dec_tlu_ctl.scala 1633:47] + wire sel_hold_npc_r = _T_176 & _T_177; // @[dec_tlu_ctl.scala 1633:45] + wire _T_179 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 1637:18] + wire _T_180 = _T_179 & io_reset_delayed; // @[dec_tlu_ctl.scala 1637:40] + wire [30:0] _T_184 = sel_exu_npc_r ? io_exu_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_185 = _T_180 ? io_rst_vec : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_186 = sel_flush_npc_r ? io_tlu_flush_path_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_187 = sel_hold_npc_r ? io_npc_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_188 = _T_184 | _T_185; // @[Mux.scala 27:72] + wire [30:0] _T_189 = _T_188 | _T_186; // @[Mux.scala 27:72] + wire _T_192 = sel_exu_npc_r | sel_flush_npc_r; // @[dec_tlu_ctl.scala 1641:58] + wire _T_193 = _T_192 | io_reset_delayed; // @[dec_tlu_ctl.scala 1641:76] + reg [30:0] _T_196; // @[Reg.scala 27:20] + wire pc0_valid_r = _T_142 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1644:51] + wire _T_199 = ~pc0_valid_r; // @[dec_tlu_ctl.scala 1648:17] + wire [30:0] _T_200 = pc0_valid_r ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] + reg [30:0] pc_r_d1; // @[Reg.scala 27:20] + wire [30:0] _T_201 = _T_199 ? pc_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] pc_r = _T_200 | _T_201; // @[Mux.scala 27:72] + wire _T_206 = io_dec_csr_wraddr_r == 12'h341; // @[dec_tlu_ctl.scala 1652:75] + wire wr_mepc_r = io_dec_csr_wen_r_mod & _T_206; // @[dec_tlu_ctl.scala 1652:46] + wire _T_207 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1655:42] + wire _T_208 = _T_207 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1655:63] + wire _T_212 = wr_mepc_r & _T_17; // @[dec_tlu_ctl.scala 1657:28] + wire _T_215 = ~wr_mepc_r; // @[dec_tlu_ctl.scala 1658:18] + wire _T_217 = _T_215 & _T_17; // @[dec_tlu_ctl.scala 1658:29] + wire [30:0] _T_219 = _T_208 ? pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_220 = io_interrupt_valid_r ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_221 = _T_212 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_222 = _T_217 ? io_mepc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_223 = _T_219 | _T_220; // @[Mux.scala 27:72] + wire [30:0] _T_224 = _T_223 | _T_221; // @[Mux.scala 27:72] + wire [30:0] mepc_ns = _T_224 | _T_222; // @[Mux.scala 27:72] + wire _T_228 = _T_208 | io_interrupt_valid_r; // @[dec_tlu_ctl.scala 1660:111] + wire _T_229 = _T_228 | wr_mepc_r; // @[dec_tlu_ctl.scala 1660:134] + reg [30:0] _T_231; // @[Reg.scala 27:20] + wire _T_233 = io_dec_csr_wraddr_r == 12'h342; // @[dec_tlu_ctl.scala 1668:77] + wire wr_mcause_r = io_dec_csr_wen_r_mod & _T_233; // @[dec_tlu_ctl.scala 1668:48] + wire _T_234 = io_exc_or_int_valid_r & io_take_nmi; // @[dec_tlu_ctl.scala 1669:58] + wire mcause_sel_nmi_store = _T_234 & io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 1669:72] + wire mcause_sel_nmi_load = _T_234 & io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 1670:71] + wire _T_237 = _T_234 & io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 1671:69] + wire _T_238 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 1671:115] + wire _T_239 = _T_237 & _T_238; // @[dec_tlu_ctl.scala 1671:96] + wire _T_240 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1671:121] + wire mcause_sel_nmi_ext = _T_239 & _T_240; // @[dec_tlu_ctl.scala 1671:119] + wire _T_241 = &io_lsu_fir_error; // @[dec_tlu_ctl.scala 1678:58] + wire _T_244 = ~io_lsu_fir_error[0]; // @[dec_tlu_ctl.scala 1678:87] + wire _T_245 = io_lsu_fir_error[1] & _T_244; // @[dec_tlu_ctl.scala 1678:85] + wire [31:0] _T_250 = {30'h3c000400,_T_241,_T_245}; // @[Cat.scala 29:58] + wire _T_251 = ~io_take_nmi; // @[dec_tlu_ctl.scala 1684:42] + wire _T_252 = io_exc_or_int_valid_r & _T_251; // @[dec_tlu_ctl.scala 1684:40] + wire [31:0] _T_255 = {io_interrupt_valid_r,26'h0,io_exc_cause_r}; // @[Cat.scala 29:58] + wire _T_257 = wr_mcause_r & _T_17; // @[dec_tlu_ctl.scala 1685:30] + wire _T_259 = ~wr_mcause_r; // @[dec_tlu_ctl.scala 1686:18] + wire _T_261 = _T_259 & _T_17; // @[dec_tlu_ctl.scala 1686:31] + wire [31:0] _T_263 = mcause_sel_nmi_store ? 32'hf0000000 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_264 = mcause_sel_nmi_load ? 32'hf0000001 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_265 = mcause_sel_nmi_ext ? _T_250 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_266 = _T_252 ? _T_255 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_267 = _T_257 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] + reg [31:0] mcause; // @[Reg.scala 27:20] + wire [31:0] _T_268 = _T_261 ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_269 = _T_263 | _T_264; // @[Mux.scala 27:72] + wire [31:0] _T_270 = _T_269 | _T_265; // @[Mux.scala 27:72] + wire [31:0] _T_271 = _T_270 | _T_266; // @[Mux.scala 27:72] + wire [31:0] _T_272 = _T_271 | _T_267; // @[Mux.scala 27:72] + wire [31:0] mcause_ns = _T_272 | _T_268; // @[Mux.scala 27:72] + wire _T_274 = io_exc_or_int_valid_r | wr_mcause_r; // @[dec_tlu_ctl.scala 1688:58] + wire _T_278 = io_dec_csr_wraddr_r == 12'h7ff; // @[dec_tlu_ctl.scala 1695:78] + wire wr_mscause_r = io_dec_csr_wen_r_mod & _T_278; // @[dec_tlu_ctl.scala 1695:49] + wire _T_279 = io_dec_tlu_packet_r_icaf_type == 2'h0; // @[dec_tlu_ctl.scala 1697:63] + wire [3:0] _T_280 = {2'h0,io_dec_tlu_packet_r_icaf_type}; // @[Cat.scala 29:58] + wire [3:0] ifu_mscause = _T_279 ? 4'h9 : _T_280; // @[dec_tlu_ctl.scala 1697:31] + wire [3:0] _T_285 = io_lsu_i0_exc_r ? io_lsu_error_pkt_r_bits_mscause : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_286 = io_i0_trigger_hit_r ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_287 = io_ebreak_r ? 4'h2 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_288 = io_inst_acc_r ? ifu_mscause : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_289 = _T_285 | _T_286; // @[Mux.scala 27:72] + wire [3:0] _T_290 = _T_289 | _T_287; // @[Mux.scala 27:72] + wire [3:0] mscause_type = _T_290 | _T_288; // @[Mux.scala 27:72] + wire _T_294 = wr_mscause_r & _T_17; // @[dec_tlu_ctl.scala 1708:31] + wire _T_297 = ~wr_mscause_r; // @[dec_tlu_ctl.scala 1709:18] + wire _T_299 = _T_297 & _T_17; // @[dec_tlu_ctl.scala 1709:32] + wire [3:0] _T_301 = io_exc_or_int_valid_r ? mscause_type : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_302 = _T_294 ? io_dec_csr_wrdata_r[3:0] : 4'h0; // @[Mux.scala 27:72] + reg [3:0] mscause; // @[dec_tlu_ctl.scala 1711:54] + wire [3:0] _T_303 = _T_299 ? mscause : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_304 = _T_301 | _T_302; // @[Mux.scala 27:72] + wire _T_308 = io_dec_csr_wraddr_r == 12'h343; // @[dec_tlu_ctl.scala 1718:76] + wire wr_mtval_r = io_dec_csr_wen_r_mod & _T_308; // @[dec_tlu_ctl.scala 1718:47] + wire _T_309 = ~io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1719:90] + wire _T_310 = io_inst_acc_r & _T_309; // @[dec_tlu_ctl.scala 1719:88] + wire _T_311 = io_ebreak_r | _T_310; // @[dec_tlu_ctl.scala 1719:71] + wire _T_312 = _T_311 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1719:113] + wire _T_313 = io_exc_or_int_valid_r & _T_312; // @[dec_tlu_ctl.scala 1719:56] + wire mtval_capture_pc_r = _T_313 & _T_251; // @[dec_tlu_ctl.scala 1719:145] + wire _T_315 = io_inst_acc_r & io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1720:79] + wire _T_316 = io_exc_or_int_valid_r & _T_315; // @[dec_tlu_ctl.scala 1720:62] + wire mtval_capture_pc_plus2_r = _T_316 & _T_251; // @[dec_tlu_ctl.scala 1720:103] + wire _T_318 = io_exc_or_int_valid_r & io_illegal_r; // @[dec_tlu_ctl.scala 1721:58] + wire mtval_capture_inst_r = _T_318 & _T_251; // @[dec_tlu_ctl.scala 1721:73] + wire _T_320 = io_exc_or_int_valid_r & io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1722:57] + wire mtval_capture_lsu_r = _T_320 & _T_251; // @[dec_tlu_ctl.scala 1722:78] + wire _T_322 = ~mtval_capture_pc_r; // @[dec_tlu_ctl.scala 1723:53] + wire _T_323 = io_exc_or_int_valid_r & _T_322; // @[dec_tlu_ctl.scala 1723:51] + wire _T_324 = ~mtval_capture_inst_r; // @[dec_tlu_ctl.scala 1723:75] + wire _T_325 = _T_323 & _T_324; // @[dec_tlu_ctl.scala 1723:73] + wire _T_326 = ~mtval_capture_lsu_r; // @[dec_tlu_ctl.scala 1723:99] + wire _T_327 = _T_325 & _T_326; // @[dec_tlu_ctl.scala 1723:97] + wire _T_328 = ~io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1723:122] + wire mtval_clear_r = _T_327 & _T_328; // @[dec_tlu_ctl.scala 1723:120] + wire [31:0] _T_330 = {pc_r,1'h0}; // @[Cat.scala 29:58] + wire [30:0] _T_333 = pc_r + 31'h1; // @[dec_tlu_ctl.scala 1728:96] + wire [31:0] _T_334 = {_T_333,1'h0}; // @[Cat.scala 29:58] + wire _T_337 = ~io_interrupt_valid_r; // @[dec_tlu_ctl.scala 1731:31] + wire _T_338 = wr_mtval_r & _T_337; // @[dec_tlu_ctl.scala 1731:29] + wire _T_341 = ~wr_mtval_r; // @[dec_tlu_ctl.scala 1732:33] + wire _T_342 = _T_251 & _T_341; // @[dec_tlu_ctl.scala 1732:31] + wire _T_344 = _T_342 & _T_322; // @[dec_tlu_ctl.scala 1732:45] + wire _T_346 = _T_344 & _T_324; // @[dec_tlu_ctl.scala 1732:67] + wire _T_347 = ~mtval_clear_r; // @[dec_tlu_ctl.scala 1732:93] + wire _T_348 = _T_346 & _T_347; // @[dec_tlu_ctl.scala 1732:91] + wire _T_350 = _T_348 & _T_326; // @[dec_tlu_ctl.scala 1732:108] + wire [31:0] _T_352 = mtval_capture_pc_r ? _T_330 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_353 = mtval_capture_pc_plus2_r ? _T_334 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_354 = mtval_capture_inst_r ? io_dec_illegal_inst : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_355 = mtval_capture_lsu_r ? io_lsu_error_pkt_addr_r : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_356 = _T_338 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] + reg [31:0] mtval; // @[Reg.scala 27:20] + wire [31:0] _T_357 = _T_350 ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_358 = _T_352 | _T_353; // @[Mux.scala 27:72] + wire [31:0] _T_359 = _T_358 | _T_354; // @[Mux.scala 27:72] + wire [31:0] _T_360 = _T_359 | _T_355; // @[Mux.scala 27:72] + wire [31:0] _T_361 = _T_360 | _T_356; // @[Mux.scala 27:72] + wire [31:0] mtval_ns = _T_361 | _T_357; // @[Mux.scala 27:72] + wire _T_363 = io_tlu_flush_lower_r | wr_mtval_r; // @[dec_tlu_ctl.scala 1734:55] + wire _T_367 = io_dec_csr_wraddr_r == 12'h7f8; // @[dec_tlu_ctl.scala 1752:75] + wire wr_mcgc_r = io_dec_csr_wen_r_mod & _T_367; // @[dec_tlu_ctl.scala 1752:46] + wire _T_370 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1753:42] + wire [9:0] _T_372 = {_T_370,io_dec_csr_wrdata_r[8:0]}; // @[Cat.scala 29:58] + reg [9:0] mcgc_int; // @[Reg.scala 27:20] + wire _T_376 = ~mcgc_int[9]; // @[dec_tlu_ctl.scala 1755:24] + wire [9:0] mcgc = {_T_376,mcgc_int[8:0]}; // @[Cat.scala 29:58] + wire _T_388 = io_dec_csr_wraddr_r == 12'h7f9; // @[dec_tlu_ctl.scala 1785:75] + wire wr_mfdc_r = io_dec_csr_wen_r_mod & _T_388; // @[dec_tlu_ctl.scala 1785:46] + reg [15:0] mfdc_int; // @[Reg.scala 27:20] + wire [2:0] _T_392 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1795:32] + wire _T_396 = ~io_dec_csr_wrdata_r[6]; // @[dec_tlu_ctl.scala 1795:111] + wire [15:0] mfdc_ns = {_T_392,io_dec_csr_wrdata_r[12],io_dec_csr_wrdata_r[11:7],_T_396,io_dec_csr_wrdata_r[5:0]}; // @[Cat.scala 29:58] + wire [2:0] _T_403 = ~mfdc_int[15:13]; // @[dec_tlu_ctl.scala 1796:32] + wire _T_407 = ~mfdc_int[6]; // @[dec_tlu_ctl.scala 1796:88] + wire [18:0] mfdc = {_T_403,3'h0,mfdc_int[12],mfdc_int[11:7],_T_407,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire _T_423 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1822:84] + wire _T_424 = io_dec_csr_wen_r_mod & _T_423; // @[dec_tlu_ctl.scala 1822:55] + wire _T_426 = _T_424 & _T_337; // @[dec_tlu_ctl.scala 1822:94] + wire _T_427 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1822:120] + wire _T_430 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1829:75] + wire wr_mrac_r = io_dec_csr_wen_r_mod & _T_430; // @[dec_tlu_ctl.scala 1829:46] + wire _T_434 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1832:78] + wire _T_435 = io_dec_csr_wrdata_r[30] & _T_434; // @[dec_tlu_ctl.scala 1832:76] + wire _T_439 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1833:68] + wire _T_440 = io_dec_csr_wrdata_r[28] & _T_439; // @[dec_tlu_ctl.scala 1833:66] + wire _T_444 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1834:68] + wire _T_445 = io_dec_csr_wrdata_r[26] & _T_444; // @[dec_tlu_ctl.scala 1834:66] + wire _T_449 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1835:68] + wire _T_450 = io_dec_csr_wrdata_r[24] & _T_449; // @[dec_tlu_ctl.scala 1835:66] + wire _T_454 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1836:68] + wire _T_455 = io_dec_csr_wrdata_r[22] & _T_454; // @[dec_tlu_ctl.scala 1836:66] + wire _T_459 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1837:68] + wire _T_460 = io_dec_csr_wrdata_r[20] & _T_459; // @[dec_tlu_ctl.scala 1837:66] + wire _T_464 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1838:68] + wire _T_465 = io_dec_csr_wrdata_r[18] & _T_464; // @[dec_tlu_ctl.scala 1838:66] + wire _T_469 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1839:68] + wire _T_470 = io_dec_csr_wrdata_r[16] & _T_469; // @[dec_tlu_ctl.scala 1839:66] + wire _T_474 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1840:68] + wire _T_475 = io_dec_csr_wrdata_r[14] & _T_474; // @[dec_tlu_ctl.scala 1840:66] + wire _T_479 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1841:68] + wire _T_480 = io_dec_csr_wrdata_r[12] & _T_479; // @[dec_tlu_ctl.scala 1841:66] + wire _T_484 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1842:68] + wire _T_485 = io_dec_csr_wrdata_r[10] & _T_484; // @[dec_tlu_ctl.scala 1842:66] + wire _T_490 = io_dec_csr_wrdata_r[8] & _T_370; // @[dec_tlu_ctl.scala 1843:65] + wire _T_494 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1844:68] + wire _T_495 = io_dec_csr_wrdata_r[6] & _T_494; // @[dec_tlu_ctl.scala 1844:65] + wire _T_499 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1845:68] + wire _T_500 = io_dec_csr_wrdata_r[4] & _T_499; // @[dec_tlu_ctl.scala 1845:65] + wire _T_504 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1846:68] + wire _T_505 = io_dec_csr_wrdata_r[2] & _T_504; // @[dec_tlu_ctl.scala 1846:65] + wire _T_510 = io_dec_csr_wrdata_r[0] & _T_565; // @[dec_tlu_ctl.scala 1847:65] + wire [7:0] _T_517 = {io_dec_csr_wrdata_r[7],_T_495,io_dec_csr_wrdata_r[5],_T_500,io_dec_csr_wrdata_r[3],_T_505,io_dec_csr_wrdata_r[1],_T_510}; // @[Cat.scala 29:58] + wire [15:0] _T_525 = {io_dec_csr_wrdata_r[15],_T_475,io_dec_csr_wrdata_r[13],_T_480,io_dec_csr_wrdata_r[11],_T_485,io_dec_csr_wrdata_r[9],_T_490,_T_517}; // @[Cat.scala 29:58] + wire [7:0] _T_532 = {io_dec_csr_wrdata_r[23],_T_455,io_dec_csr_wrdata_r[21],_T_460,io_dec_csr_wrdata_r[19],_T_465,io_dec_csr_wrdata_r[17],_T_470}; // @[Cat.scala 29:58] + wire [31:0] mrac_in = {io_dec_csr_wrdata_r[31],_T_435,io_dec_csr_wrdata_r[29],_T_440,io_dec_csr_wrdata_r[27],_T_445,io_dec_csr_wrdata_r[25],_T_450,_T_532,_T_525}; // @[Cat.scala 29:58] + reg [31:0] mrac; // @[Reg.scala 27:20] + wire _T_543 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1860:76] + wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_543; // @[dec_tlu_ctl.scala 1860:47] + wire _T_544 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1870:66] + wire _T_545 = io_mdseac_locked_f & _T_544; // @[dec_tlu_ctl.scala 1870:64] + wire _T_547 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1872:56] + wire _T_549 = _T_547 & _T_240; // @[dec_tlu_ctl.scala 1872:91] + wire _T_550 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1872:118] + wire mdseac_en = _T_549 & _T_550; // @[dec_tlu_ctl.scala 1872:116] + reg [31:0] mdseac; // @[Reg.scala 27:20] + wire _T_555 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1887:37] + wire _T_556 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1887:64] + wire _T_557 = _T_555 & _T_556; // @[dec_tlu_ctl.scala 1887:62] + wire _T_558 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1887:96] + wire _T_571 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1905:55] + wire [4:0] csr_sat = _T_571 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1905:26] + wire _T_573 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1907:71] + wire wr_micect_r = io_dec_csr_wen_r_mod & _T_573; // @[dec_tlu_ctl.scala 1907:48] + wire [26:0] _T_575 = {26'h0,io_ic_perr_r}; // @[Cat.scala 29:58] + wire [26:0] micect_inc = micect[26:0] + _T_575; // @[dec_tlu_ctl.scala 1908:36] + wire [31:0] _T_580 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_582 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] + wire _T_583 = wr_micect_r | io_ic_perr_r; // @[dec_tlu_ctl.scala 1911:49] + wire _T_593 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1922:83] + wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_593; // @[dec_tlu_ctl.scala 1922:54] + wire _T_595 = io_iccm_sbecc_r | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1923:74] + wire [26:0] _T_596 = {26'h0,_T_595}; // @[Cat.scala 29:58] + wire [26:0] miccmect_inc = miccmect[26:0] + _T_596; // @[dec_tlu_ctl.scala 1923:40] + wire [31:0] _T_603 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] + wire _T_604 = wr_miccmect_r | io_iccm_sbecc_r; // @[dec_tlu_ctl.scala 1926:55] + wire _T_605 = _T_604 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1926:73] + wire _T_615 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1937:83] + wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_615; // @[dec_tlu_ctl.scala 1937:54] + wire [26:0] _T_617 = {26'h0,perfmux_flop_io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] + wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_617; // @[dec_tlu_ctl.scala 1938:40] + wire [31:0] _T_624 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] + wire _T_625 = wr_mdccmect_r | perfmux_flop_io_lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 1941:56] + wire _T_635 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1952:76] + wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_635; // @[dec_tlu_ctl.scala 1952:47] + reg [5:0] mfdht; // @[Reg.scala 27:20] + wire _T_641 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1965:76] + wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_641; // @[dec_tlu_ctl.scala 1965:47] + wire _T_644 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1968:42] + wire _T_645 = io_dbg_tlu_halted & _T_644; // @[dec_tlu_ctl.scala 1968:40] + wire _T_647 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1968:77] + wire _T_648 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1968:97] + wire [1:0] _T_649 = {_T_647,_T_648}; // @[Cat.scala 29:58] + reg [1:0] mfdhs; // @[Reg.scala 27:20] + wire _T_651 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1970:76] + reg [31:0] force_halt_ctr_f; // @[Reg.scala 27:20] + wire [31:0] _T_656 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1972:81] + wire [62:0] _T_663 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1977:78] + wire [62:0] _GEN_46 = {{31'd0}, force_halt_ctr_f}; // @[dec_tlu_ctl.scala 1977:55] + wire [62:0] _T_664 = _GEN_46 & _T_663; // @[dec_tlu_ctl.scala 1977:55] + wire _T_665 = |_T_664; // @[dec_tlu_ctl.scala 1977:94] + wire _T_668 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1985:76] + wire wr_meivt_r = io_dec_csr_wen_r_mod & _T_668; // @[dec_tlu_ctl.scala 1985:47] + reg [21:0] meivt; // @[Reg.scala 27:20] + wire _T_686 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 2036:76] + wire _T_687 = io_dec_csr_wen_r_mod & _T_686; // @[dec_tlu_ctl.scala 2036:47] + wire wr_meicpct_r = _T_687 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 2036:90] + reg [7:0] meihap; // @[Reg.scala 27:20] + wire _T_674 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 2009:79] + wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_674; // @[dec_tlu_ctl.scala 2009:50] + reg [3:0] meicurpl; // @[dec_tlu_ctl.scala 2012:53] + wire _T_679 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 2024:80] + wire _T_680 = io_dec_csr_wen_r_mod & _T_679; // @[dec_tlu_ctl.scala 2024:51] + wire wr_meicidpl_r = _T_680 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 2024:95] + wire [3:0] _T_684 = wr_meicidpl_r ? io_dec_csr_wrdata_r[3:0] : perfmux_flop_io_meicidpl; // @[dec_tlu_ctl.scala 2027:20] + wire _T_690 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 2045:76] + wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_690; // @[dec_tlu_ctl.scala 2045:47] + reg [3:0] meipt; // @[dec_tlu_ctl.scala 2048:50] + wire _T_694 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2076:96] + wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_694; // @[dec_tlu_ctl.scala 2076:73] + wire _T_695 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2079:47] + wire _T_696 = io_dcsr_single_step_done_f & _T_695; // @[dec_tlu_ctl.scala 2079:45] + wire _T_697 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2079:79] + wire _T_698 = _T_696 & _T_697; // @[dec_tlu_ctl.scala 2079:77] + wire _T_699 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2079:114] + wire _T_700 = _T_698 & _T_699; // @[dec_tlu_ctl.scala 2079:112] + wire _T_703 = io_debug_halt_req & _T_695; // @[dec_tlu_ctl.scala 2080:36] + wire _T_705 = _T_703 & _T_697; // @[dec_tlu_ctl.scala 2080:68] + wire _T_708 = io_ebreak_to_debug_mode_r_d1 & _T_697; // @[dec_tlu_ctl.scala 2081:47] + wire [2:0] _T_711 = _T_700 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_712 = _T_705 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_713 = _T_708 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_714 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_715 = _T_711 | _T_712; // @[Mux.scala 27:72] + wire [2:0] _T_716 = _T_715 | _T_713; // @[Mux.scala 27:72] + wire [2:0] dcsr_cause = _T_716 | _T_714; // @[Mux.scala 27:72] + wire _T_718 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2084:53] + wire _T_720 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2084:105] + wire wr_dcsr_r = _T_718 & _T_720; // @[dec_tlu_ctl.scala 2084:76] + wire _T_722 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2090:82] + wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_722; // @[dec_tlu_ctl.scala 2090:66] + wire _T_723 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2091:66] + wire _T_724 = _T_723 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2091:85] + wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_724; // @[dec_tlu_ctl.scala 2091:63] + wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 2093:55] + wire [15:0] _T_730 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] + wire _T_736 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2095:158] + wire [15:0] _T_745 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_736,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] + wire [15:0] _T_750 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] + wire _T_752 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2098:61] + wire _T_753 = _T_752 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2098:73] + wire _T_754 = _T_753 | io_take_nmi; // @[dec_tlu_ctl.scala 2098:101] + reg [15:0] _T_756; // @[Reg.scala 27:20] + wire _T_759 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2106:104] + wire wr_dpc_r = _T_718 & _T_759; // @[dec_tlu_ctl.scala 2106:75] + wire _T_762 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2107:74] + wire dpc_capture_npc = _T_645 & _T_762; // @[dec_tlu_ctl.scala 2107:72] + wire _T_763 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2111:18] + wire _T_764 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2111:36] + wire _T_765 = _T_763 & _T_764; // @[dec_tlu_ctl.scala 2111:34] + wire _T_766 = _T_765 & wr_dpc_r; // @[dec_tlu_ctl.scala 2111:53] + wire _T_771 = _T_763 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2113:34] + wire [30:0] _T_773 = _T_766 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_774 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_775 = _T_771 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_776 = _T_773 | _T_774; // @[Mux.scala 27:72] + wire [30:0] dpc_ns = _T_776 | _T_775; // @[Mux.scala 27:72] + wire _T_778 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2115:43] + wire _T_779 = _T_778 | dpc_capture_npc; // @[dec_tlu_ctl.scala 2115:60] + reg [30:0] _T_781; // @[Reg.scala 27:20] + wire [16:0] dicawics_ns = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20],io_dec_csr_wrdata_r[16:3]}; // @[Cat.scala 29:58] + wire _T_788 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2130:109] + wire wr_dicawics_r = _T_718 & _T_788; // @[dec_tlu_ctl.scala 2130:80] + reg [16:0] dicawics; // @[Reg.scala 27:20] + wire _T_792 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2148:107] + wire wr_dicad0_r = _T_718 & _T_792; // @[dec_tlu_ctl.scala 2148:78] + wire _T_795 = wr_dicad0_r | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2151:53] + reg [31:0] dicad0; // @[Reg.scala 27:20] + wire _T_799 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2161:108] + wire wr_dicad0h_r = _T_718 & _T_799; // @[dec_tlu_ctl.scala 2161:79] + wire _T_802 = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2165:55] + reg [31:0] dicad0h; // @[Reg.scala 27:20] + wire _T_807 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2173:115] + wire _T_808 = _T_718 & _T_807; // @[dec_tlu_ctl.scala 2173:86] + wire _T_813 = _T_808 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2177:61] + reg [6:0] _T_815; // @[Reg.scala 27:20] + wire [31:0] dicad1 = {25'h0,_T_815}; // @[Cat.scala 29:58] + wire [38:0] _T_820 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] + wire _T_822 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2205:59] + wire _T_823 = _T_822 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2205:82] + wire _T_824 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2205:105] + wire _T_825 = _T_823 & _T_824; // @[dec_tlu_ctl.scala 2205:103] + wire _T_827 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2205:156] + wire _T_830 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2206:111] + wire _T_832 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2220:76] + wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_832; // @[dec_tlu_ctl.scala 2220:47] + reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2223:50] + wire tdata_load = io_dec_csr_wrdata_r[0] & _T_464; // @[dec_tlu_ctl.scala 2258:49] + wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_464; // @[dec_tlu_ctl.scala 2260:51] + wire _T_843 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2262:53] + wire tdata_action = _T_843 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2262:76] + wire _T_851 = io_mtdata1_t_3[9] & _T_444; // @[dec_tlu_ctl.scala 2266:91] + wire _T_852 = ~_T_851; // @[dec_tlu_ctl.scala 2266:58] + wire _T_853 = io_dec_csr_wrdata_r[11] & _T_852; // @[dec_tlu_ctl.scala 2266:56] + wire _T_858 = io_mtdata1_t_1[9] & _T_444; // @[dec_tlu_ctl.scala 2267:84] + wire _T_859 = ~_T_858; // @[dec_tlu_ctl.scala 2267:51] + wire _T_860 = io_dec_csr_wrdata_r[11] & _T_859; // @[dec_tlu_ctl.scala 2267:49] + wire _T_861 = mtsel[1] ? _T_853 : _T_860; // @[dec_tlu_ctl.scala 2266:20] + wire tdata_chain = mtsel[0] ? 1'h0 : _T_861; // @[dec_tlu_ctl.scala 2265:30] + wire _T_865 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2270:73] + wire _T_867 = _T_865 & io_mtdata1_t_2[5]; // @[dec_tlu_ctl.scala 2270:105] + wire _T_868 = io_dec_csr_wrdata_r[27] & _T_867; // @[dec_tlu_ctl.scala 2270:70] + wire _T_871 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2271:44] + wire _T_873 = _T_871 & io_mtdata1_t_0[5]; // @[dec_tlu_ctl.scala 2271:76] + wire _T_874 = io_dec_csr_wrdata_r[27] & _T_873; // @[dec_tlu_ctl.scala 2271:41] + wire tdata_kill_write = mtsel[1] ? _T_868 : _T_874; // @[dec_tlu_ctl.scala 2270:35] + wire [9:0] tdata_wrdata_r = {_T_843,io_dec_csr_wrdata_r[20:19],tdata_action,tdata_chain,io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] + wire _T_887 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2276:127] + wire _T_888 = io_dec_csr_wen_r_mod & _T_887; // @[dec_tlu_ctl.scala 2276:98] + wire _T_889 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2276:149] + wire _T_890 = _T_888 & _T_889; // @[dec_tlu_ctl.scala 2276:140] + wire _T_893 = _T_871 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2276:198] + wire wr_mtdata1_t_r_0 = _T_890 & _T_893; // @[dec_tlu_ctl.scala 2276:163] + wire _T_898 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2276:298] + wire _T_899 = _T_888 & _T_898; // @[dec_tlu_ctl.scala 2276:289] + wire _T_901 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2276:315] + wire _T_902 = _T_901 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2276:347] + wire _T_903 = _T_899 & _T_902; // @[dec_tlu_ctl.scala 2276:312] + wire _T_904 = ~tdata_kill_write; // @[dec_tlu_ctl.scala 2276:373] + wire wr_mtdata1_t_r_1 = _T_903 & _T_904; // @[dec_tlu_ctl.scala 2276:371] + wire _T_909 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2276:149] + wire _T_910 = _T_888 & _T_909; // @[dec_tlu_ctl.scala 2276:140] + wire _T_913 = _T_865 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2276:198] + wire wr_mtdata1_t_r_2 = _T_910 & _T_913; // @[dec_tlu_ctl.scala 2276:163] + wire _T_918 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2276:298] + wire _T_919 = _T_888 & _T_918; // @[dec_tlu_ctl.scala 2276:289] + wire _T_921 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2276:315] + wire _T_922 = _T_921 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2276:347] + wire _T_923 = _T_919 & _T_922; // @[dec_tlu_ctl.scala 2276:312] + wire wr_mtdata1_t_r_3 = _T_923 & _T_904; // @[dec_tlu_ctl.scala 2276:371] + wire _T_930 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2278:148] + wire [9:0] _T_933 = {io_mtdata1_t_0[9],_T_930,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] + wire _T_939 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2278:148] + wire [9:0] _T_942 = {io_mtdata1_t_1[9],_T_939,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] + wire _T_948 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2278:148] + wire [9:0] _T_951 = {io_mtdata1_t_2[9],_T_948,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] + wire _T_957 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2278:148] + wire [9:0] _T_960 = {io_mtdata1_t_3[9],_T_957,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] + wire _T_963 = io_trigger_enabled[0] | wr_mtdata1_t_r_0; // @[dec_tlu_ctl.scala 2282:95] + reg [9:0] _T_965; // @[Reg.scala 27:20] + wire _T_967 = io_trigger_enabled[1] | wr_mtdata1_t_r_1; // @[dec_tlu_ctl.scala 2282:95] + reg [9:0] _T_969; // @[Reg.scala 27:20] + wire _T_971 = io_trigger_enabled[2] | wr_mtdata1_t_r_2; // @[dec_tlu_ctl.scala 2282:95] + reg [9:0] _T_973; // @[Reg.scala 27:20] + wire _T_975 = io_trigger_enabled[3] | wr_mtdata1_t_r_3; // @[dec_tlu_ctl.scala 2282:95] + reg [9:0] _T_977; // @[Reg.scala 27:20] + wire [31:0] _T_992 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_1007 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_1022 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_1037 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_1038 = _T_889 ? _T_992 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1039 = _T_898 ? _T_1007 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1040 = _T_909 ? _T_1022 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1041 = _T_918 ? _T_1037 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1042 = _T_1038 | _T_1039; // @[Mux.scala 27:72] + wire [31:0] _T_1043 = _T_1042 | _T_1040; // @[Mux.scala 27:72] + wire [31:0] mtdata1_tsel_out = _T_1043 | _T_1041; // @[Mux.scala 27:72] + wire _T_1070 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2299:105] + wire _T_1071 = io_dec_csr_wen_r_mod & _T_1070; // @[dec_tlu_ctl.scala 2299:76] + wire _T_1073 = _T_1071 & _T_889; // @[dec_tlu_ctl.scala 2299:118] + wire wr_mtdata2_t_r_0 = _T_1073 & _T_893; // @[dec_tlu_ctl.scala 2299:141] + wire _T_1082 = _T_1071 & _T_898; // @[dec_tlu_ctl.scala 2299:118] + wire wr_mtdata2_t_r_1 = _T_1082 & _T_902; // @[dec_tlu_ctl.scala 2299:141] + wire _T_1091 = _T_1071 & _T_909; // @[dec_tlu_ctl.scala 2299:118] + wire wr_mtdata2_t_r_2 = _T_1091 & _T_913; // @[dec_tlu_ctl.scala 2299:141] + wire _T_1100 = _T_1071 & _T_918; // @[dec_tlu_ctl.scala 2299:118] + wire wr_mtdata2_t_r_3 = _T_1100 & _T_922; // @[dec_tlu_ctl.scala 2299:141] + reg [31:0] mtdata2_t_0; // @[Reg.scala 27:20] + reg [31:0] mtdata2_t_1; // @[Reg.scala 27:20] + reg [31:0] mtdata2_t_2; // @[Reg.scala 27:20] + reg [31:0] mtdata2_t_3; // @[Reg.scala 27:20] + wire [31:0] _T_1117 = _T_889 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1118 = _T_898 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1119 = _T_909 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1120 = _T_918 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1121 = _T_1117 | _T_1118; // @[Mux.scala 27:72] + wire [31:0] _T_1122 = _T_1121 | _T_1119; // @[Mux.scala 27:72] + wire [31:0] mtdata2_tsel_out = _T_1122 | _T_1120; // @[Mux.scala 27:72] + wire _T_1128 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2455:84] + wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_1128; // @[dec_tlu_ctl.scala 2455:55] + wire _T_1140 = ~io_dec_tlu_trace_disable; // @[dec_tlu_ctl.scala 2468:42] + wire _T_1143 = io_i0_exception_valid_r_d1 | perfmux_flop_io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2469:98] + wire _T_1144 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2469:158] + wire _T_1145 = io_trigger_hit_r_d1 & _T_1144; // @[dec_tlu_ctl.scala 2469:156] + wire _T_1146 = _T_1143 | _T_1145; // @[dec_tlu_ctl.scala 2469:133] + wire [4:0] _T_1150 = _T_1140 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] dec_tlu_exc_cause_wb1_raw = _T_1150 & io_exc_cause_wb; // @[dec_tlu_ctl.scala 2470:77] + wire dec_tlu_int_valid_wb1_raw = _T_1140 & io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2471:68] + reg [4:0] dec_tlu_exc_cause_wb2; // @[Reg.scala 27:20] + wire [4:0] _T_1152 = dec_tlu_exc_cause_wb1_raw ^ dec_tlu_exc_cause_wb2; // @[lib.scala 448:21] + wire _T_1153 = |_T_1152; // @[lib.scala 448:29] + reg dec_tlu_int_valid_wb2; // @[Reg.scala 27:20] + wire _T_1155 = dec_tlu_int_valid_wb1_raw ^ dec_tlu_int_valid_wb2; // @[lib.scala 470:21] + wire _T_1156 = |_T_1155; // @[lib.scala 470:29] + wire [31:0] _T_1164 = {io_core_id,4'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1173 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1178 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] + wire [31:0] _T_1191 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1204 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1216 = {io_mepc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1221 = {28'h0,mscause}; // @[Cat.scala 29:58] + wire [31:0] _T_1229 = {meivt,10'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1232 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1235 = {28'h0,meicurpl}; // @[Cat.scala 29:58] + wire [3:0] _T_1237 = perfmux_flop_io_meicidpl; // @[dec_tlu_ctl.scala 2509:97] + wire [31:0] _T_1238 = {28'h0,_T_1237}; // @[Cat.scala 29:58] + wire [31:0] _T_1241 = {28'h0,meipt}; // @[Cat.scala 29:58] + wire [31:0] _T_1244 = {22'h0,_T_376,mcgc_int[8:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_1247 = {13'h0,_T_403,3'h0,mfdc_int[12],mfdc_int[11:7],_T_407,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_1251 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] + wire [31:0] _T_1253 = {io_dpc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1269 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1272 = {30'h0,mtsel}; // @[Cat.scala 29:58] + wire [31:0] _T_1284 = perf_csrs_io_mhpmc3; // @[dec_tlu_ctl.scala 2525:77] + wire [31:0] _T_1286 = perf_csrs_io_mhpmc4; // @[dec_tlu_ctl.scala 2526:77] + wire [31:0] _T_1288 = perf_csrs_io_mhpmc5; // @[dec_tlu_ctl.scala 2527:77] + wire [31:0] _T_1290 = perf_csrs_io_mhpmc6; // @[dec_tlu_ctl.scala 2528:77] + wire [31:0] _T_1292 = perf_csrs_io_mhpmc3h; // @[dec_tlu_ctl.scala 2529:78] + wire [31:0] _T_1294 = perf_csrs_io_mhpmc4h; // @[dec_tlu_ctl.scala 2530:78] + wire [31:0] _T_1296 = perf_csrs_io_mhpmc5h; // @[dec_tlu_ctl.scala 2531:78] + wire [31:0] _T_1298 = perf_csrs_io_mhpmc6h; // @[dec_tlu_ctl.scala 2532:78] + wire [31:0] _T_1301 = {26'h0,mfdht}; // @[Cat.scala 29:58] + wire [31:0] _T_1304 = {30'h0,mfdhs}; // @[Cat.scala 29:58] + wire [9:0] _T_1306 = perf_csrs_io_mhpme3; // @[dec_tlu_ctl.scala 2535:92] + wire [31:0] _T_1307 = {22'h0,_T_1306}; // @[Cat.scala 29:58] + wire [9:0] _T_1309 = perf_csrs_io_mhpme4; // @[dec_tlu_ctl.scala 2536:92] + wire [31:0] _T_1310 = {22'h0,_T_1309}; // @[Cat.scala 29:58] + wire [9:0] _T_1312 = perf_csrs_io_mhpme5; // @[dec_tlu_ctl.scala 2537:91] + wire [31:0] _T_1313 = {22'h0,_T_1312}; // @[Cat.scala 29:58] + wire [9:0] _T_1315 = perf_csrs_io_mhpme6; // @[dec_tlu_ctl.scala 2538:91] + wire [31:0] _T_1316 = {22'h0,_T_1315}; // @[Cat.scala 29:58] + wire [31:0] _T_1319 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire [31:0] _T_1322 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_1325 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1326 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1327 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1328 = io_csr_pkt_csr_mimpid ? 32'h3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1329 = io_csr_pkt_csr_mhartid ? _T_1164 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1330 = io_csr_pkt_csr_mstatus ? _T_1173 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1331 = io_csr_pkt_csr_mtvec ? _T_1178 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1332 = io_csr_pkt_csr_mip ? _T_1191 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1333 = io_csr_pkt_csr_mie ? _T_1204 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1334 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1335 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1336 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1337 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1338 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1339 = io_csr_pkt_csr_mepc ? _T_1216 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1340 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1341 = io_csr_pkt_csr_mscause ? _T_1221 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1342 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1343 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1344 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1345 = io_csr_pkt_csr_meivt ? _T_1229 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1346 = io_csr_pkt_csr_meihap ? _T_1232 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1347 = io_csr_pkt_csr_meicurpl ? _T_1235 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1348 = io_csr_pkt_csr_meicidpl ? _T_1238 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1349 = io_csr_pkt_csr_meipt ? _T_1241 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1350 = io_csr_pkt_csr_mcgc ? _T_1244 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1351 = io_csr_pkt_csr_mfdc ? _T_1247 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1352 = io_csr_pkt_csr_dcsr ? _T_1251 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1353 = io_csr_pkt_csr_dpc ? _T_1253 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1354 = io_csr_pkt_csr_dicad0 ? dicad0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1355 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1356 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1357 = io_csr_pkt_csr_dicawics ? _T_1269 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1358 = io_csr_pkt_csr_mtsel ? _T_1272 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1359 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1360 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1361 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1362 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1363 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1364 = io_csr_pkt_csr_mhpmc3 ? _T_1284 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1365 = io_csr_pkt_csr_mhpmc4 ? _T_1286 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1366 = io_csr_pkt_csr_mhpmc5 ? _T_1288 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1367 = io_csr_pkt_csr_mhpmc6 ? _T_1290 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1368 = io_csr_pkt_csr_mhpmc3h ? _T_1292 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1369 = io_csr_pkt_csr_mhpmc4h ? _T_1294 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1370 = io_csr_pkt_csr_mhpmc5h ? _T_1296 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1371 = io_csr_pkt_csr_mhpmc6h ? _T_1298 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1372 = io_csr_pkt_csr_mfdht ? _T_1301 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1373 = io_csr_pkt_csr_mfdhs ? _T_1304 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1374 = io_csr_pkt_csr_mhpme3 ? _T_1307 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1375 = io_csr_pkt_csr_mhpme4 ? _T_1310 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1376 = io_csr_pkt_csr_mhpme5 ? _T_1313 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1377 = io_csr_pkt_csr_mhpme6 ? _T_1316 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1378 = io_csr_pkt_csr_mcountinhibit ? _T_1319 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1379 = io_csr_pkt_csr_mpmc ? _T_1322 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1380 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1381 = _T_1325 | _T_1326; // @[Mux.scala 27:72] + wire [31:0] _T_1382 = _T_1381 | _T_1327; // @[Mux.scala 27:72] + wire [31:0] _T_1383 = _T_1382 | _T_1328; // @[Mux.scala 27:72] + wire [31:0] _T_1384 = _T_1383 | _T_1329; // @[Mux.scala 27:72] + wire [31:0] _T_1385 = _T_1384 | _T_1330; // @[Mux.scala 27:72] + wire [31:0] _T_1386 = _T_1385 | _T_1331; // @[Mux.scala 27:72] + wire [31:0] _T_1387 = _T_1386 | _T_1332; // @[Mux.scala 27:72] + wire [31:0] _T_1388 = _T_1387 | _T_1333; // @[Mux.scala 27:72] + wire [31:0] _T_1389 = _T_1388 | _T_1334; // @[Mux.scala 27:72] + wire [31:0] _T_1390 = _T_1389 | _T_1335; // @[Mux.scala 27:72] + wire [31:0] _T_1391 = _T_1390 | _T_1336; // @[Mux.scala 27:72] + wire [31:0] _T_1392 = _T_1391 | _T_1337; // @[Mux.scala 27:72] + wire [31:0] _T_1393 = _T_1392 | _T_1338; // @[Mux.scala 27:72] + wire [31:0] _T_1394 = _T_1393 | _T_1339; // @[Mux.scala 27:72] + wire [31:0] _T_1395 = _T_1394 | _T_1340; // @[Mux.scala 27:72] + wire [31:0] _T_1396 = _T_1395 | _T_1341; // @[Mux.scala 27:72] + wire [31:0] _T_1397 = _T_1396 | _T_1342; // @[Mux.scala 27:72] + wire [31:0] _T_1398 = _T_1397 | _T_1343; // @[Mux.scala 27:72] + wire [31:0] _T_1399 = _T_1398 | _T_1344; // @[Mux.scala 27:72] + wire [31:0] _T_1400 = _T_1399 | _T_1345; // @[Mux.scala 27:72] + wire [31:0] _T_1401 = _T_1400 | _T_1346; // @[Mux.scala 27:72] + wire [31:0] _T_1402 = _T_1401 | _T_1347; // @[Mux.scala 27:72] + wire [31:0] _T_1403 = _T_1402 | _T_1348; // @[Mux.scala 27:72] + wire [31:0] _T_1404 = _T_1403 | _T_1349; // @[Mux.scala 27:72] + wire [31:0] _T_1405 = _T_1404 | _T_1350; // @[Mux.scala 27:72] + wire [31:0] _T_1406 = _T_1405 | _T_1351; // @[Mux.scala 27:72] + wire [31:0] _T_1407 = _T_1406 | _T_1352; // @[Mux.scala 27:72] + wire [31:0] _T_1408 = _T_1407 | _T_1353; // @[Mux.scala 27:72] + wire [31:0] _T_1409 = _T_1408 | _T_1354; // @[Mux.scala 27:72] + wire [31:0] _T_1410 = _T_1409 | _T_1355; // @[Mux.scala 27:72] + wire [31:0] _T_1411 = _T_1410 | _T_1356; // @[Mux.scala 27:72] + wire [31:0] _T_1412 = _T_1411 | _T_1357; // @[Mux.scala 27:72] + wire [31:0] _T_1413 = _T_1412 | _T_1358; // @[Mux.scala 27:72] + wire [31:0] _T_1414 = _T_1413 | _T_1359; // @[Mux.scala 27:72] + wire [31:0] _T_1415 = _T_1414 | _T_1360; // @[Mux.scala 27:72] + wire [31:0] _T_1416 = _T_1415 | _T_1361; // @[Mux.scala 27:72] + wire [31:0] _T_1417 = _T_1416 | _T_1362; // @[Mux.scala 27:72] + wire [31:0] _T_1418 = _T_1417 | _T_1363; // @[Mux.scala 27:72] + wire [31:0] _T_1419 = _T_1418 | _T_1364; // @[Mux.scala 27:72] + wire [31:0] _T_1420 = _T_1419 | _T_1365; // @[Mux.scala 27:72] + wire [31:0] _T_1421 = _T_1420 | _T_1366; // @[Mux.scala 27:72] + wire [31:0] _T_1422 = _T_1421 | _T_1367; // @[Mux.scala 27:72] + wire [31:0] _T_1423 = _T_1422 | _T_1368; // @[Mux.scala 27:72] + wire [31:0] _T_1424 = _T_1423 | _T_1369; // @[Mux.scala 27:72] + wire [31:0] _T_1425 = _T_1424 | _T_1370; // @[Mux.scala 27:72] + wire [31:0] _T_1426 = _T_1425 | _T_1371; // @[Mux.scala 27:72] + wire [31:0] _T_1427 = _T_1426 | _T_1372; // @[Mux.scala 27:72] + wire [31:0] _T_1428 = _T_1427 | _T_1373; // @[Mux.scala 27:72] + wire [31:0] _T_1429 = _T_1428 | _T_1374; // @[Mux.scala 27:72] + wire [31:0] _T_1430 = _T_1429 | _T_1375; // @[Mux.scala 27:72] + wire [31:0] _T_1431 = _T_1430 | _T_1376; // @[Mux.scala 27:72] + wire [31:0] _T_1432 = _T_1431 | _T_1377; // @[Mux.scala 27:72] + wire [31:0] _T_1433 = _T_1432 | _T_1378; // @[Mux.scala 27:72] + wire [31:0] _T_1434 = _T_1433 | _T_1379; // @[Mux.scala 27:72] + perf_mux_and_flops perfmux_flop ( // @[dec_tlu_ctl.scala 1455:34] + .reset(perfmux_flop_reset), + .io_mhpmc_inc_r_0(perfmux_flop_io_mhpmc_inc_r_0), + .io_mhpmc_inc_r_1(perfmux_flop_io_mhpmc_inc_r_1), + .io_mhpmc_inc_r_2(perfmux_flop_io_mhpmc_inc_r_2), + .io_mhpmc_inc_r_3(perfmux_flop_io_mhpmc_inc_r_3), + .io_mcountinhibit(perfmux_flop_io_mcountinhibit), + .io_mhpme_vec_0(perfmux_flop_io_mhpme_vec_0), + .io_mhpme_vec_1(perfmux_flop_io_mhpme_vec_1), + .io_mhpme_vec_2(perfmux_flop_io_mhpme_vec_2), + .io_mhpme_vec_3(perfmux_flop_io_mhpme_vec_3), + .io_ifu_pmu_ic_hit(perfmux_flop_io_ifu_pmu_ic_hit), + .io_ifu_pmu_ic_miss(perfmux_flop_io_ifu_pmu_ic_miss), + .io_tlu_i0_commit_cmt(perfmux_flop_io_tlu_i0_commit_cmt), + .io_illegal_r(perfmux_flop_io_illegal_r), + .io_exu_pmu_i0_pc4(perfmux_flop_io_exu_pmu_i0_pc4), + .io_ifu_pmu_instr_aligned(perfmux_flop_io_ifu_pmu_instr_aligned), + .io_dec_pmu_instr_decoded(perfmux_flop_io_dec_pmu_instr_decoded), + .io_dec_tlu_packet_r_pmu_i0_itype(perfmux_flop_io_dec_tlu_packet_r_pmu_i0_itype), + .io_dec_tlu_packet_r_pmu_i0_br_unpred(perfmux_flop_io_dec_tlu_packet_r_pmu_i0_br_unpred), + .io_dec_tlu_packet_r_pmu_divide(perfmux_flop_io_dec_tlu_packet_r_pmu_divide), + .io_dec_tlu_packet_r_pmu_lsu_misaligned(perfmux_flop_io_dec_tlu_packet_r_pmu_lsu_misaligned), + .io_exu_pmu_i0_br_misp(perfmux_flop_io_exu_pmu_i0_br_misp), + .io_dec_pmu_decode_stall(perfmux_flop_io_dec_pmu_decode_stall), + .io_exu_pmu_i0_br_ataken(perfmux_flop_io_exu_pmu_i0_br_ataken), + .io_ifu_pmu_fetch_stall(perfmux_flop_io_ifu_pmu_fetch_stall), + .io_dec_pmu_postsync_stall(perfmux_flop_io_dec_pmu_postsync_stall), + .io_dec_pmu_presync_stall(perfmux_flop_io_dec_pmu_presync_stall), + .io_lsu_store_stall_any(perfmux_flop_io_lsu_store_stall_any), + .io_dma_dccm_stall_any(perfmux_flop_io_dma_dccm_stall_any), + .io_dma_iccm_stall_any(perfmux_flop_io_dma_iccm_stall_any), + .io_i0_exception_valid_r(perfmux_flop_io_i0_exception_valid_r), + .io_dec_tlu_pmu_fw_halted(perfmux_flop_io_dec_tlu_pmu_fw_halted), + .io_dma_pmu_any_read(perfmux_flop_io_dma_pmu_any_read), + .io_dma_pmu_any_write(perfmux_flop_io_dma_pmu_any_write), + .io_dma_pmu_dccm_read(perfmux_flop_io_dma_pmu_dccm_read), + .io_dma_pmu_dccm_write(perfmux_flop_io_dma_pmu_dccm_write), + .io_lsu_pmu_load_external_r(perfmux_flop_io_lsu_pmu_load_external_r), + .io_lsu_pmu_store_external_r(perfmux_flop_io_lsu_pmu_store_external_r), + .io_mstatus(perfmux_flop_io_mstatus), + .io_mie(perfmux_flop_io_mie), + .io_ifu_pmu_bus_trxn(perfmux_flop_io_ifu_pmu_bus_trxn), + .io_lsu_pmu_bus_trxn(perfmux_flop_io_lsu_pmu_bus_trxn), + .io_lsu_pmu_bus_misaligned(perfmux_flop_io_lsu_pmu_bus_misaligned), + .io_ifu_pmu_bus_error(perfmux_flop_io_ifu_pmu_bus_error), + .io_lsu_pmu_bus_error(perfmux_flop_io_lsu_pmu_bus_error), + .io_ifu_pmu_bus_busy(perfmux_flop_io_ifu_pmu_bus_busy), + .io_lsu_pmu_bus_busy(perfmux_flop_io_lsu_pmu_bus_busy), + .io_i0_trigger_hit_r(perfmux_flop_io_i0_trigger_hit_r), + .io_lsu_exc_valid_r(perfmux_flop_io_lsu_exc_valid_r), + .io_take_timer_int(perfmux_flop_io_take_timer_int), + .io_take_int_timer0_int(perfmux_flop_io_take_int_timer0_int), + .io_take_int_timer1_int(perfmux_flop_io_take_int_timer1_int), + .io_take_ext_int(perfmux_flop_io_take_ext_int), + .io_tlu_flush_lower_r(perfmux_flop_io_tlu_flush_lower_r), + .io_dec_tlu_br0_error_r(perfmux_flop_io_dec_tlu_br0_error_r), + .io_rfpc_i0_r(perfmux_flop_io_rfpc_i0_r), + .io_dec_tlu_br0_start_error_r(perfmux_flop_io_dec_tlu_br0_start_error_r), + .io_mcyclel_cout_f(perfmux_flop_io_mcyclel_cout_f), + .io_minstret_enable_f(perfmux_flop_io_minstret_enable_f), + .io_minstretl_cout_f(perfmux_flop_io_minstretl_cout_f), + .io_meicidpl(perfmux_flop_io_meicidpl), + .io_icache_rd_valid_f(perfmux_flop_io_icache_rd_valid_f), + .io_icache_wr_valid_f(perfmux_flop_io_icache_wr_valid_f), + .io_mhpmc_inc_r_d1_0(perfmux_flop_io_mhpmc_inc_r_d1_0), + .io_mhpmc_inc_r_d1_1(perfmux_flop_io_mhpmc_inc_r_d1_1), + .io_mhpmc_inc_r_d1_2(perfmux_flop_io_mhpmc_inc_r_d1_2), + .io_mhpmc_inc_r_d1_3(perfmux_flop_io_mhpmc_inc_r_d1_3), + .io_perfcnt_halted_d1(perfmux_flop_io_perfcnt_halted_d1), + .io_mdseac_locked_f(perfmux_flop_io_mdseac_locked_f), + .io_lsu_single_ecc_error_r_d1(perfmux_flop_io_lsu_single_ecc_error_r_d1), + .io_lsu_i0_exc_r_d1(perfmux_flop_io_lsu_i0_exc_r_d1), + .io_take_ext_int_start_d1(perfmux_flop_io_take_ext_int_start_d1), + .io_take_ext_int_start_d2(perfmux_flop_io_take_ext_int_start_d2), + .io_take_ext_int_start_d3(perfmux_flop_io_take_ext_int_start_d3), + .io_ext_int_freeze_d1(perfmux_flop_io_ext_int_freeze_d1), + .io_mip(perfmux_flop_io_mip), + .io_mdseac_locked_ns(perfmux_flop_io_mdseac_locked_ns), + .io_lsu_single_ecc_error_r(perfmux_flop_io_lsu_single_ecc_error_r), + .io_lsu_i0_exc_r(perfmux_flop_io_lsu_i0_exc_r), + .io_take_ext_int_start(perfmux_flop_io_take_ext_int_start), + .io_ext_int_freeze(perfmux_flop_io_ext_int_freeze), + .io_mip_ns(perfmux_flop_io_mip_ns), + .io_mcyclel_cout(perfmux_flop_io_mcyclel_cout), + .io_wr_mcycleh_r(perfmux_flop_io_wr_mcycleh_r), + .io_mcyclel_cout_in(perfmux_flop_io_mcyclel_cout_in), + .io_minstret_enable(perfmux_flop_io_minstret_enable), + .io_minstretl_cout_ns(perfmux_flop_io_minstretl_cout_ns), + .io_meicidpl_ns(perfmux_flop_io_meicidpl_ns), + .io_icache_rd_valid(perfmux_flop_io_icache_rd_valid), + .io_icache_wr_valid(perfmux_flop_io_icache_wr_valid), + .io_perfcnt_halted(perfmux_flop_io_perfcnt_halted), + .io_mstatus_ns(perfmux_flop_io_mstatus_ns), + .io_free_l2clk(perfmux_flop_io_free_l2clk) + ); + perf_csr perf_csrs ( // @[dec_tlu_ctl.scala 1456:31] + .clock(perf_csrs_clock), + .reset(perf_csrs_reset), + .io_free_l2clk(perf_csrs_io_free_l2clk), + .io_dec_tlu_dbg_halted(perf_csrs_io_dec_tlu_dbg_halted), + .io_dcsr(perf_csrs_io_dcsr), + .io_dec_tlu_pmu_fw_halted(perf_csrs_io_dec_tlu_pmu_fw_halted), + .io_mhpme_vec_0(perf_csrs_io_mhpme_vec_0), + .io_mhpme_vec_1(perf_csrs_io_mhpme_vec_1), + .io_mhpme_vec_2(perf_csrs_io_mhpme_vec_2), + .io_mhpme_vec_3(perf_csrs_io_mhpme_vec_3), + .io_dec_csr_wen_r_mod(perf_csrs_io_dec_csr_wen_r_mod), + .io_dec_csr_wraddr_r(perf_csrs_io_dec_csr_wraddr_r), + .io_dec_csr_wrdata_r(perf_csrs_io_dec_csr_wrdata_r), + .io_mhpmc_inc_r_0(perf_csrs_io_mhpmc_inc_r_0), + .io_mhpmc_inc_r_1(perf_csrs_io_mhpmc_inc_r_1), + .io_mhpmc_inc_r_2(perf_csrs_io_mhpmc_inc_r_2), + .io_mhpmc_inc_r_3(perf_csrs_io_mhpmc_inc_r_3), + .io_mhpmc_inc_r_d1_0(perf_csrs_io_mhpmc_inc_r_d1_0), + .io_mhpmc_inc_r_d1_1(perf_csrs_io_mhpmc_inc_r_d1_1), + .io_mhpmc_inc_r_d1_2(perf_csrs_io_mhpmc_inc_r_d1_2), + .io_mhpmc_inc_r_d1_3(perf_csrs_io_mhpmc_inc_r_d1_3), + .io_perfcnt_halted_d1(perf_csrs_io_perfcnt_halted_d1), + .io_mhpmc3h(perf_csrs_io_mhpmc3h), + .io_mhpmc3(perf_csrs_io_mhpmc3), + .io_mhpmc4h(perf_csrs_io_mhpmc4h), + .io_mhpmc4(perf_csrs_io_mhpmc4), + .io_mhpmc5h(perf_csrs_io_mhpmc5h), + .io_mhpmc5(perf_csrs_io_mhpmc5), + .io_mhpmc6h(perf_csrs_io_mhpmc6h), + .io_mhpmc6(perf_csrs_io_mhpmc6), + .io_mhpme3(perf_csrs_io_mhpme3), + .io_mhpme4(perf_csrs_io_mhpme4), + .io_mhpme5(perf_csrs_io_mhpme5), + .io_mhpme6(perf_csrs_io_mhpme6), + .io_dec_tlu_perfcnt0(perf_csrs_io_dec_tlu_perfcnt0), + .io_dec_tlu_perfcnt1(perf_csrs_io_dec_tlu_perfcnt1), + .io_dec_tlu_perfcnt2(perf_csrs_io_dec_tlu_perfcnt2), + .io_dec_tlu_perfcnt3(perf_csrs_io_dec_tlu_perfcnt3) + ); + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en) + ); + rvclkhdr rvclkhdr_10 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en) + ); + rvclkhdr rvclkhdr_11 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en) + ); + rvclkhdr rvclkhdr_12 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_12_io_clk), + .io_en(rvclkhdr_12_io_en) + ); + rvclkhdr rvclkhdr_13 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_13_io_clk), + .io_en(rvclkhdr_13_io_en) + ); + rvclkhdr rvclkhdr_14 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_14_io_clk), + .io_en(rvclkhdr_14_io_en) + ); + rvclkhdr rvclkhdr_15 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_15_io_clk), + .io_en(rvclkhdr_15_io_en) + ); + rvclkhdr rvclkhdr_16 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_16_io_clk), + .io_en(rvclkhdr_16_io_en) + ); + rvclkhdr rvclkhdr_17 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_17_io_clk), + .io_en(rvclkhdr_17_io_en) + ); + rvclkhdr rvclkhdr_18 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_18_io_clk), + .io_en(rvclkhdr_18_io_en) + ); + rvclkhdr rvclkhdr_19 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_19_io_clk), + .io_en(rvclkhdr_19_io_en) + ); + rvclkhdr rvclkhdr_20 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_20_io_clk), + .io_en(rvclkhdr_20_io_en) + ); + rvclkhdr rvclkhdr_21 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_21_io_clk), + .io_en(rvclkhdr_21_io_en) + ); + rvclkhdr rvclkhdr_22 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_22_io_clk), + .io_en(rvclkhdr_22_io_en) + ); + rvclkhdr rvclkhdr_23 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_23_io_clk), + .io_en(rvclkhdr_23_io_en) + ); + rvclkhdr rvclkhdr_24 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_24_io_clk), + .io_en(rvclkhdr_24_io_en) + ); + rvclkhdr rvclkhdr_25 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_25_io_clk), + .io_en(rvclkhdr_25_io_en) + ); + rvclkhdr rvclkhdr_26 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_26_io_clk), + .io_en(rvclkhdr_26_io_en) + ); + rvclkhdr rvclkhdr_27 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_27_io_clk), + .io_en(rvclkhdr_27_io_en) + ); + rvclkhdr rvclkhdr_28 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_28_io_clk), + .io_en(rvclkhdr_28_io_en) + ); + rvclkhdr rvclkhdr_29 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_29_io_clk), + .io_en(rvclkhdr_29_io_en) + ); + rvclkhdr rvclkhdr_30 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_30_io_clk), + .io_en(rvclkhdr_30_io_en) + ); + rvclkhdr rvclkhdr_31 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_31_io_clk), + .io_en(rvclkhdr_31_io_en) + ); + rvclkhdr rvclkhdr_32 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_32_io_clk), + .io_en(rvclkhdr_32_io_en) + ); + rvclkhdr rvclkhdr_33 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_33_io_clk), + .io_en(rvclkhdr_33_io_en) + ); + rvclkhdr rvclkhdr_34 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_34_io_clk), + .io_en(rvclkhdr_34_io_en) + ); + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_820,dicad0}; // @[dec_tlu_ctl.scala 2200:63] + assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2203:48] + assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = perfmux_flop_io_icache_rd_valid_f; // @[dec_tlu_ctl.scala 2211:48] + assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = perfmux_flop_io_icache_wr_valid_f; // @[dec_tlu_ctl.scala 2212:48] + assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[dec_tlu_ctl.scala 2287:48] + assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[dec_tlu_ctl.scala 2288:51] + assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[dec_tlu_ctl.scala 2289:48] + assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[dec_tlu_ctl.scala 2290:48] + assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[dec_tlu_ctl.scala 2291:48] + assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 2292:48] + assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[dec_tlu_ctl.scala 2305:59] + assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[dec_tlu_ctl.scala 2287:48] + assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[dec_tlu_ctl.scala 2288:51] + assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[dec_tlu_ctl.scala 2289:48] + assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[dec_tlu_ctl.scala 2290:48] + assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[dec_tlu_ctl.scala 2291:48] + assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 2292:48] + assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[dec_tlu_ctl.scala 2305:59] + assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[dec_tlu_ctl.scala 2287:48] + assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[dec_tlu_ctl.scala 2288:51] + assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[dec_tlu_ctl.scala 2289:48] + assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[dec_tlu_ctl.scala 2290:48] + assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[dec_tlu_ctl.scala 2291:48] + assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 2292:48] + assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[dec_tlu_ctl.scala 2305:59] + assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[dec_tlu_ctl.scala 2287:48] + assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[dec_tlu_ctl.scala 2288:51] + assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[dec_tlu_ctl.scala 2289:48] + assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[dec_tlu_ctl.scala 2290:48] + assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2291:48] + assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2292:48] + assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2305:59] + assign io_dec_tlu_int_valid_wb1 = dec_tlu_int_valid_wb2; // @[dec_tlu_ctl.scala 2478:34] + assign io_dec_tlu_i0_exc_valid_wb1 = _T_1140 & _T_1146; // @[dec_tlu_ctl.scala 2469:39] + assign io_dec_tlu_i0_valid_wb1 = _T_1140 & io_i0_valid_wb; // @[dec_tlu_ctl.scala 2468:39] + assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2479:31] + assign io_dec_tlu_exc_cause_wb1 = dec_tlu_int_valid_wb2 ? dec_tlu_exc_cause_wb2 : dec_tlu_exc_cause_wb1_raw; // @[dec_tlu_ctl.scala 2477:34] + assign io_dec_tlu_perfcnt0 = perf_csrs_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 2436:29] + assign io_dec_tlu_perfcnt1 = perf_csrs_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 2437:29] + assign io_dec_tlu_perfcnt2 = perf_csrs_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 2438:29] + assign io_dec_tlu_perfcnt3 = perf_csrs_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 2439:29] + assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1757:38] + assign io_dec_tlu_picio_clk_override = mcgc[9]; // @[dec_tlu_ctl.scala 1756:39] + assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1758:38] + assign io_dec_tlu_ifu_clk_override = mcgc[5]; // @[dec_tlu_ctl.scala 1759:38] + assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1760:38] + assign io_dec_tlu_bus_clk_override = mcgc[3]; // @[dec_tlu_ctl.scala 1761:38] + assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1762:38] + assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1763:38] + assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1764:38] + assign io_dec_csr_rddata_d = _T_1434 | _T_1380; // @[dec_tlu_ctl.scala 2485:28] + assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1813:46] + assign io_dec_tlu_wr_pause_r = _T_426 & _T_427; // @[dec_tlu_ctl.scala 1822:31] + assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 2050:26] + assign io_dec_tlu_meicurpl = meicurpl; // @[dec_tlu_ctl.scala 2014:29] + assign io_dec_tlu_meihap = {meivt,meihap}; // @[dec_tlu_ctl.scala 2000:27] + assign io_dec_tlu_mrac_ff = mrac; // @[dec_tlu_ctl.scala 1852:28] + assign io_dec_tlu_wb_coalescing_disable = mfdc[2]; // @[dec_tlu_ctl.scala 1812:46] + assign io_dec_tlu_bpred_disable = mfdc[3]; // @[dec_tlu_ctl.scala 1811:46] + assign io_dec_tlu_sideeffect_posted_disable = mfdc[6]; // @[dec_tlu_ctl.scala 1810:46] + assign io_dec_tlu_core_ecc_disable = mfdc[8]; // @[dec_tlu_ctl.scala 1809:46] + assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[dec_tlu_ctl.scala 1808:46] + assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[dec_tlu_ctl.scala 1806:46] + assign io_dec_tlu_trace_disable = mfdc[12]; // @[dec_tlu_ctl.scala 1807:46] + assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[dec_tlu_ctl.scala 1472:30] + assign io_fw_halt_req = _T_557 & _T_558; // @[dec_tlu_ctl.scala 1887:24] + assign io_mstatus = perfmux_flop_io_mstatus; // @[dec_tlu_ctl.scala 2348:26] + assign io_mstatus_mie_ns = io_mstatus[0] & _T_54; // @[dec_tlu_ctl.scala 1489:27] + assign io_dcsr = _T_756; // @[dec_tlu_ctl.scala 2098:17] + assign io_mtvec = _T_61; // @[dec_tlu_ctl.scala 1502:18] + assign io_mip = perfmux_flop_io_mip; // @[dec_tlu_ctl.scala 2349:18] + assign io_mie_ns = wr_mie_r ? _T_76 : mie; // @[dec_tlu_ctl.scala 1531:19] + assign io_npc_r = _T_189 | _T_187; // @[dec_tlu_ctl.scala 1635:18] + assign io_npc_r_d1 = _T_196; // @[dec_tlu_ctl.scala 1641:21] + assign io_mepc = _T_231; // @[dec_tlu_ctl.scala 1660:17] + assign io_mdseac_locked_ns = mdseac_en | _T_545; // @[dec_tlu_ctl.scala 1870:29] + assign io_mdseac_locked_f = perfmux_flop_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 2378:42] + assign io_ext_int_freeze_d1 = perfmux_flop_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 2385:42] + assign io_take_ext_int_start_d1 = perfmux_flop_io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 2382:42] + assign io_take_ext_int_start_d2 = perfmux_flop_io_take_ext_int_start_d2; // @[dec_tlu_ctl.scala 2383:42] + assign io_take_ext_int_start_d3 = perfmux_flop_io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 2384:42] + assign io_force_halt = mfdht[0] & _T_665; // @[dec_tlu_ctl.scala 1977:23] + assign io_dpc = _T_781; // @[dec_tlu_ctl.scala 2115:16] + assign io_mtdata1_t_0 = _T_965; // @[dec_tlu_ctl.scala 2282:47] + assign io_mtdata1_t_1 = _T_969; // @[dec_tlu_ctl.scala 2282:47] + assign io_mtdata1_t_2 = _T_973; // @[dec_tlu_ctl.scala 2282:47] + assign io_mtdata1_t_3 = _T_977; // @[dec_tlu_ctl.scala 2282:47] + assign perfmux_flop_reset = reset; + assign perfmux_flop_io_mcountinhibit = {_T_1138,temp_ncount0}; // @[dec_tlu_ctl.scala 2321:57] + assign perfmux_flop_io_mhpme_vec_0 = perf_csrs_io_mhpme3; // @[dec_tlu_ctl.scala 2322:57] + assign perfmux_flop_io_mhpme_vec_1 = perf_csrs_io_mhpme4; // @[dec_tlu_ctl.scala 2322:57] + assign perfmux_flop_io_mhpme_vec_2 = perf_csrs_io_mhpme5; // @[dec_tlu_ctl.scala 2322:57] + assign perfmux_flop_io_mhpme_vec_3 = perf_csrs_io_mhpme6; // @[dec_tlu_ctl.scala 2322:57] + assign perfmux_flop_io_ifu_pmu_ic_hit = io_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 2323:57] + assign perfmux_flop_io_ifu_pmu_ic_miss = io_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 2324:57] + assign perfmux_flop_io_tlu_i0_commit_cmt = io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2325:57] + assign perfmux_flop_io_illegal_r = io_illegal_r; // @[dec_tlu_ctl.scala 2326:57] + assign perfmux_flop_io_exu_pmu_i0_pc4 = io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2327:57] + assign perfmux_flop_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 2328:57] + assign perfmux_flop_io_dec_pmu_instr_decoded = io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 2329:57] + assign perfmux_flop_io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 2330:57] + assign perfmux_flop_io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 2330:57] + assign perfmux_flop_io_dec_tlu_packet_r_pmu_divide = io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 2330:57] + assign perfmux_flop_io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2330:57] + assign perfmux_flop_io_exu_pmu_i0_br_misp = io_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 2331:57] + assign perfmux_flop_io_dec_pmu_decode_stall = io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 2332:57] + assign perfmux_flop_io_exu_pmu_i0_br_ataken = io_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 2333:57] + assign perfmux_flop_io_ifu_pmu_fetch_stall = io_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 2334:57] + assign perfmux_flop_io_dec_pmu_postsync_stall = io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 2335:57] + assign perfmux_flop_io_dec_pmu_presync_stall = io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 2336:57] + assign perfmux_flop_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 2337:57] + assign perfmux_flop_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 2338:57] + assign perfmux_flop_io_dma_iccm_stall_any = io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 2339:57] + assign perfmux_flop_io_i0_exception_valid_r = io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 2340:57] + assign perfmux_flop_io_dec_tlu_pmu_fw_halted = io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2341:57] + assign perfmux_flop_io_dma_pmu_any_read = io_dma_pmu_any_read; // @[dec_tlu_ctl.scala 2342:57] + assign perfmux_flop_io_dma_pmu_any_write = io_dma_pmu_any_write; // @[dec_tlu_ctl.scala 2343:57] + assign perfmux_flop_io_dma_pmu_dccm_read = io_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 2344:57] + assign perfmux_flop_io_dma_pmu_dccm_write = io_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 2345:57] + assign perfmux_flop_io_lsu_pmu_load_external_r = io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2346:57] + assign perfmux_flop_io_lsu_pmu_store_external_r = io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2347:57] + assign perfmux_flop_io_mie = mie; // @[dec_tlu_ctl.scala 2350:57] + assign perfmux_flop_io_ifu_pmu_bus_trxn = io_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 2351:57] + assign perfmux_flop_io_lsu_pmu_bus_trxn = io_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 2352:57] + assign perfmux_flop_io_lsu_pmu_bus_misaligned = io_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 2353:57] + assign perfmux_flop_io_ifu_pmu_bus_error = io_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 2354:57] + assign perfmux_flop_io_lsu_pmu_bus_error = io_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 2355:57] + assign perfmux_flop_io_ifu_pmu_bus_busy = io_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 2356:57] + assign perfmux_flop_io_lsu_pmu_bus_busy = io_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 2357:57] + assign perfmux_flop_io_i0_trigger_hit_r = io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2358:57] + assign perfmux_flop_io_lsu_exc_valid_r = io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2359:57] + assign perfmux_flop_io_take_timer_int = io_take_timer_int; // @[dec_tlu_ctl.scala 2360:57] + assign perfmux_flop_io_take_int_timer0_int = io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2361:57] + assign perfmux_flop_io_take_int_timer1_int = io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2362:57] + assign perfmux_flop_io_take_ext_int = io_take_ext_int; // @[dec_tlu_ctl.scala 2363:57] + assign perfmux_flop_io_tlu_flush_lower_r = io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 2364:57] + assign perfmux_flop_io_dec_tlu_br0_error_r = io_dec_tlu_br0_error_r; // @[dec_tlu_ctl.scala 2365:57] + assign perfmux_flop_io_rfpc_i0_r = io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2366:57] + assign perfmux_flop_io_dec_tlu_br0_start_error_r = io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2367:57] + assign perfmux_flop_io_mdseac_locked_ns = io_mdseac_locked_ns; // @[dec_tlu_ctl.scala 2389:55] + assign perfmux_flop_io_lsu_single_ecc_error_r = io_lsu_single_ecc_error_r; // @[dec_tlu_ctl.scala 2390:55] + assign perfmux_flop_io_lsu_i0_exc_r = io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 2391:55] + assign perfmux_flop_io_take_ext_int_start = io_take_ext_int_start; // @[dec_tlu_ctl.scala 2392:55] + assign perfmux_flop_io_ext_int_freeze = io_ext_int_freeze; // @[dec_tlu_ctl.scala 2393:55] + assign perfmux_flop_io_mip_ns = {_T_66,_T_64}; // @[dec_tlu_ctl.scala 2394:55] + assign perfmux_flop_io_mcyclel_cout = mcyclel_inc2[24]; // @[dec_tlu_ctl.scala 2395:55] + assign perfmux_flop_io_wr_mcycleh_r = io_dec_csr_wen_r_mod & _T_113; // @[dec_tlu_ctl.scala 2396:55] + assign perfmux_flop_io_mcyclel_cout_in = ~_T_87; // @[dec_tlu_ctl.scala 2397:55] + assign perfmux_flop_io_minstret_enable = _T_138 | wr_minstretl_r; // @[dec_tlu_ctl.scala 2398:55] + assign perfmux_flop_io_minstretl_cout_ns = _T_141 & _T_142; // @[dec_tlu_ctl.scala 2399:55] + assign perfmux_flop_io_meicidpl_ns = wr_meicpct_r ? io_pic_pl : _T_684; // @[dec_tlu_ctl.scala 2401:55] + assign perfmux_flop_io_icache_rd_valid = _T_825 & _T_827; // @[dec_tlu_ctl.scala 2402:55] + assign perfmux_flop_io_icache_wr_valid = _T_718 & _T_830; // @[dec_tlu_ctl.scala 2403:55] + assign perfmux_flop_io_perfcnt_halted = _T_83 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2404:55] + assign perfmux_flop_io_mstatus_ns = _T_48 | _T_44; // @[dec_tlu_ctl.scala 2405:55] + assign perfmux_flop_io_free_l2clk = io_free_l2clk; // @[dec_tlu_ctl.scala 2407:56] + assign perf_csrs_clock = clock; + assign perf_csrs_reset = reset; + assign perf_csrs_io_free_l2clk = io_free_l2clk; // @[dec_tlu_ctl.scala 2411:50] + assign perf_csrs_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 2413:50] + assign perf_csrs_io_dcsr = io_dcsr; // @[dec_tlu_ctl.scala 2414:50] + assign perf_csrs_io_dec_tlu_pmu_fw_halted = io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2415:50] + assign perf_csrs_io_mhpme_vec_0 = perf_csrs_io_mhpme3; // @[dec_tlu_ctl.scala 2416:50] + assign perf_csrs_io_mhpme_vec_1 = perf_csrs_io_mhpme4; // @[dec_tlu_ctl.scala 2416:50] + assign perf_csrs_io_mhpme_vec_2 = perf_csrs_io_mhpme5; // @[dec_tlu_ctl.scala 2416:50] + assign perf_csrs_io_mhpme_vec_3 = perf_csrs_io_mhpme6; // @[dec_tlu_ctl.scala 2416:50] + assign perf_csrs_io_dec_csr_wen_r_mod = io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2417:50] + assign perf_csrs_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 2418:50] + assign perf_csrs_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 2419:50] + assign perf_csrs_io_mhpmc_inc_r_0 = perfmux_flop_io_mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2420:50] + assign perf_csrs_io_mhpmc_inc_r_1 = perfmux_flop_io_mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2420:50] + assign perf_csrs_io_mhpmc_inc_r_2 = perfmux_flop_io_mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2420:50] + assign perf_csrs_io_mhpmc_inc_r_3 = perfmux_flop_io_mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2420:50] + assign perf_csrs_io_mhpmc_inc_r_d1_0 = perfmux_flop_io_mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2421:50] + assign perf_csrs_io_mhpmc_inc_r_d1_1 = perfmux_flop_io_mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2421:50] + assign perf_csrs_io_mhpmc_inc_r_d1_2 = perfmux_flop_io_mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2421:50] + assign perf_csrs_io_mhpmc_inc_r_d1_3 = perfmux_flop_io_mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2421:50] + assign perf_csrs_io_perfcnt_halted_d1 = perfmux_flop_io_perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2422:50] + assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_57; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = wr_mcyclel_r | _T_102; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = wr_mcyclel_r | mcyclel_cout_in; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = wr_mcycleh_r | perfmux_flop_io_mcyclel_cout_f; // @[lib.scala 407:17] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_4_io_en = wr_minstretl_r | _T_147; // @[lib.scala 407:17] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_5_io_en = _T_138 | wr_minstretl_r; // @[lib.scala 407:17] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_6_io_en = _T_162 | wr_minstreth_r; // @[lib.scala 407:17] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_7_io_en = io_dec_csr_wen_r_mod & _T_167; // @[lib.scala 407:17] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_8_io_en = _T_228 | wr_mepc_r; // @[lib.scala 407:17] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_9_io_en = io_exc_or_int_valid_r | wr_mcause_r; // @[lib.scala 407:17] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_10_io_en = io_tlu_flush_lower_r | wr_mtval_r; // @[lib.scala 407:17] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_11_io_en = io_dec_csr_wen_r_mod & _T_367; // @[lib.scala 407:17] + assign rvclkhdr_12_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_12_io_en = io_dec_csr_wen_r_mod & _T_388; // @[lib.scala 407:17] + assign rvclkhdr_13_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_13_io_en = io_dec_csr_wen_r_mod & _T_430; // @[lib.scala 407:17] + assign rvclkhdr_14_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_14_io_en = _T_549 & _T_550; // @[lib.scala 407:17] + assign rvclkhdr_15_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_15_io_en = wr_micect_r | io_ic_perr_r; // @[lib.scala 407:17] + assign rvclkhdr_16_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_16_io_en = _T_604 | io_iccm_dma_sb_error; // @[lib.scala 407:17] + assign rvclkhdr_17_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_17_io_en = wr_mdccmect_r | perfmux_flop_io_lsu_single_ecc_error_r_d1; // @[lib.scala 407:17] + assign rvclkhdr_18_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_18_io_en = mfdht[0]; // @[lib.scala 407:17] + assign rvclkhdr_19_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_19_io_en = io_dec_csr_wen_r_mod & _T_668; // @[lib.scala 407:17] + assign rvclkhdr_20_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_20_io_en = _T_687 | io_take_ext_int_start; // @[lib.scala 407:17] + assign rvclkhdr_21_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_21_io_en = _T_753 | io_take_nmi; // @[lib.scala 407:17] + assign rvclkhdr_22_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_22_io_en = _T_778 | dpc_capture_npc; // @[lib.scala 407:17] + assign rvclkhdr_23_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_23_io_en = _T_718 & _T_788; // @[lib.scala 407:17] + assign rvclkhdr_24_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_24_io_en = wr_dicad0_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 407:17] + assign rvclkhdr_25_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_25_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 407:17] + assign rvclkhdr_26_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_26_io_en = _T_808 | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 407:17] + assign rvclkhdr_27_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_27_io_en = io_trigger_enabled[0] | wr_mtdata1_t_r_0; // @[lib.scala 407:17] + assign rvclkhdr_28_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_28_io_en = io_trigger_enabled[1] | wr_mtdata1_t_r_1; // @[lib.scala 407:17] + assign rvclkhdr_29_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_29_io_en = io_trigger_enabled[2] | wr_mtdata1_t_r_2; // @[lib.scala 407:17] + assign rvclkhdr_30_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_30_io_en = io_trigger_enabled[3] | wr_mtdata1_t_r_3; // @[lib.scala 407:17] + assign rvclkhdr_31_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_31_io_en = _T_1073 & _T_893; // @[lib.scala 407:17] + assign rvclkhdr_32_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_32_io_en = _T_1082 & _T_902; // @[lib.scala 407:17] + assign rvclkhdr_33_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_33_io_en = _T_1091 & _T_913; // @[lib.scala 407:17] + assign rvclkhdr_34_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_34_io_en = _T_1100 & _T_922; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + mpmc_b = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + _T_61 = _RAND_1[30:0]; + _RAND_2 = {1{`RANDOM}}; + mdccmect = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + miccmect = _RAND_3[31:0]; + _RAND_4 = {1{`RANDOM}}; + micect = _RAND_4[31:0]; + _RAND_5 = {1{`RANDOM}}; + mie = _RAND_5[5:0]; + _RAND_6 = {1{`RANDOM}}; + temp_ncount6_2 = _RAND_6[4:0]; + _RAND_7 = {1{`RANDOM}}; + temp_ncount0 = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + _T_106 = _RAND_8[23:0]; + _RAND_9 = {1{`RANDOM}}; + _T_110 = _RAND_9[7:0]; + _RAND_10 = {1{`RANDOM}}; + mcycleh = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + _T_150 = _RAND_11[23:0]; + _RAND_12 = {1{`RANDOM}}; + _T_153 = _RAND_12[7:0]; + _RAND_13 = {1{`RANDOM}}; + minstreth = _RAND_13[31:0]; + _RAND_14 = {1{`RANDOM}}; + mscratch = _RAND_14[31:0]; + _RAND_15 = {1{`RANDOM}}; + _T_196 = _RAND_15[30:0]; + _RAND_16 = {1{`RANDOM}}; + pc_r_d1 = _RAND_16[30:0]; + _RAND_17 = {1{`RANDOM}}; + _T_231 = _RAND_17[30:0]; + _RAND_18 = {1{`RANDOM}}; + mcause = _RAND_18[31:0]; + _RAND_19 = {1{`RANDOM}}; + mscause = _RAND_19[3:0]; + _RAND_20 = {1{`RANDOM}}; + mtval = _RAND_20[31:0]; + _RAND_21 = {1{`RANDOM}}; + mcgc_int = _RAND_21[9:0]; + _RAND_22 = {1{`RANDOM}}; + mfdc_int = _RAND_22[15:0]; + _RAND_23 = {1{`RANDOM}}; + mrac = _RAND_23[31:0]; + _RAND_24 = {1{`RANDOM}}; + mdseac = _RAND_24[31:0]; + _RAND_25 = {1{`RANDOM}}; + mfdht = _RAND_25[5:0]; + _RAND_26 = {1{`RANDOM}}; + mfdhs = _RAND_26[1:0]; + _RAND_27 = {1{`RANDOM}}; + force_halt_ctr_f = _RAND_27[31:0]; + _RAND_28 = {1{`RANDOM}}; + meivt = _RAND_28[21:0]; + _RAND_29 = {1{`RANDOM}}; + meihap = _RAND_29[7:0]; + _RAND_30 = {1{`RANDOM}}; + meicurpl = _RAND_30[3:0]; + _RAND_31 = {1{`RANDOM}}; + meipt = _RAND_31[3:0]; + _RAND_32 = {1{`RANDOM}}; + _T_756 = _RAND_32[15:0]; + _RAND_33 = {1{`RANDOM}}; + _T_781 = _RAND_33[30:0]; + _RAND_34 = {1{`RANDOM}}; + dicawics = _RAND_34[16:0]; + _RAND_35 = {1{`RANDOM}}; + dicad0 = _RAND_35[31:0]; + _RAND_36 = {1{`RANDOM}}; + dicad0h = _RAND_36[31:0]; + _RAND_37 = {1{`RANDOM}}; + _T_815 = _RAND_37[6:0]; + _RAND_38 = {1{`RANDOM}}; + mtsel = _RAND_38[1:0]; + _RAND_39 = {1{`RANDOM}}; + _T_965 = _RAND_39[9:0]; + _RAND_40 = {1{`RANDOM}}; + _T_969 = _RAND_40[9:0]; + _RAND_41 = {1{`RANDOM}}; + _T_973 = _RAND_41[9:0]; + _RAND_42 = {1{`RANDOM}}; + _T_977 = _RAND_42[9:0]; + _RAND_43 = {1{`RANDOM}}; + mtdata2_t_0 = _RAND_43[31:0]; + _RAND_44 = {1{`RANDOM}}; + mtdata2_t_1 = _RAND_44[31:0]; + _RAND_45 = {1{`RANDOM}}; + mtdata2_t_2 = _RAND_45[31:0]; + _RAND_46 = {1{`RANDOM}}; + mtdata2_t_3 = _RAND_46[31:0]; + _RAND_47 = {1{`RANDOM}}; + dec_tlu_exc_cause_wb2 = _RAND_47[4:0]; + _RAND_48 = {1{`RANDOM}}; + dec_tlu_int_valid_wb2 = _RAND_48[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + mpmc_b = 1'h0; + end + if (reset) begin + _T_61 = 31'h0; + end + if (reset) begin + mdccmect = 32'h0; + end + if (reset) begin + miccmect = 32'h0; + end + if (reset) begin + micect = 32'h0; + end + if (reset) begin + mie = 6'h0; + end + if (reset) begin + temp_ncount6_2 = 5'h0; + end + if (reset) begin + temp_ncount0 = 1'h0; + end + if (reset) begin + _T_106 = 24'h0; + end + if (reset) begin + _T_110 = 8'h0; + end + if (reset) begin + mcycleh = 32'h0; + end + if (reset) begin + _T_150 = 24'h0; + end + if (reset) begin + _T_153 = 8'h0; + end + if (reset) begin + minstreth = 32'h0; + end + if (reset) begin + mscratch = 32'h0; + end + if (reset) begin + _T_196 = 31'h0; + end + if (reset) begin + pc_r_d1 = 31'h0; + end + if (reset) begin + _T_231 = 31'h0; + end + if (reset) begin + mcause = 32'h0; + end + if (reset) begin + mscause = 4'h0; + end + if (reset) begin + mtval = 32'h0; + end + if (reset) begin + mcgc_int = 10'h0; + end + if (reset) begin + mfdc_int = 16'h0; + end + if (reset) begin + mrac = 32'h0; + end + if (reset) begin + mdseac = 32'h0; + end + if (reset) begin + mfdht = 6'h0; + end + if (reset) begin + mfdhs = 2'h0; + end + if (reset) begin + force_halt_ctr_f = 32'h0; + end + if (reset) begin + meivt = 22'h0; + end + if (reset) begin + meihap = 8'h0; + end + if (reset) begin + meicurpl = 4'h0; + end + if (reset) begin + meipt = 4'h0; + end + if (reset) begin + _T_756 = 16'h0; + end + if (reset) begin + _T_781 = 31'h0; + end + if (reset) begin + dicawics = 17'h0; + end + if (reset) begin + dicad0 = 32'h0; + end + if (reset) begin + dicad0h = 32'h0; + end + if (reset) begin + _T_815 = 7'h0; + end + if (reset) begin + mtsel = 2'h0; + end + if (reset) begin + _T_965 = 10'h0; + end + if (reset) begin + _T_969 = 10'h0; + end + if (reset) begin + _T_973 = 10'h0; + end + if (reset) begin + _T_977 = 10'h0; + end + if (reset) begin + mtdata2_t_0 = 32'h0; + end + if (reset) begin + mtdata2_t_1 = 32'h0; + end + if (reset) begin + mtdata2_t_2 = 32'h0; + end + if (reset) begin + mtdata2_t_3 = 32'h0; + end + if (reset) begin + dec_tlu_exc_cause_wb2 = 5'h0; + end + if (reset) begin + dec_tlu_int_valid_wb2 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mpmc_b <= 1'h0; + end else if (wr_mpmc_r) begin + mpmc_b <= _T_565; + end else begin + mpmc_b <= _T_566; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_61 <= 31'h0; + end else if (wr_mtvec_r) begin + _T_61 <= mtvec_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + mdccmect <= 32'h0; + end else if (_T_625) begin + if (wr_mdccmect_r) begin + mdccmect <= _T_580; + end else begin + mdccmect <= _T_624; + end + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + miccmect <= 32'h0; + end else if (_T_605) begin + if (wr_miccmect_r) begin + miccmect <= _T_580; + end else begin + miccmect <= _T_603; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + micect <= 32'h0; + end else if (_T_583) begin + if (wr_micect_r) begin + micect <= _T_580; + end else begin + micect <= _T_582; + end + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mie <= 6'h0; + end else begin + mie <= io_mie_ns; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + temp_ncount6_2 <= 5'h0; + end else if (wr_mcountinhibit_r) begin + temp_ncount6_2 <= io_dec_csr_wrdata_r[6:2]; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + temp_ncount0 <= 1'h0; + end else if (wr_mcountinhibit_r) begin + temp_ncount0 <= io_dec_csr_wrdata_r[0]; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_106 <= 24'h0; + end else if (_T_104) begin + _T_106 <= mcyclel_ns[31:8]; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_110 <= 8'h0; + end else if (_T_108) begin + _T_110 <= mcyclel_ns[7:0]; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + mcycleh <= 32'h0; + end else if (_T_117) begin + if (wr_mcycleh_r) begin + mcycleh <= io_dec_csr_wrdata_r; + end else begin + mcycleh <= mcycleh_inc; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_150 <= 24'h0; + end else if (_T_148) begin + _T_150 <= minstretl_ns[31:8]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_153 <= 8'h0; + end else if (minstret_enable) begin + _T_153 <= minstretl_ns[7:0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + minstreth <= 32'h0; + end else if (_T_163) begin + if (wr_minstreth_r) begin + minstreth <= io_dec_csr_wrdata_r; + end else begin + minstreth <= minstreth_inc; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mscratch <= 32'h0; + end else if (wr_mscratch_r) begin + mscratch <= io_dec_csr_wrdata_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_196 <= 31'h0; + end else if (_T_193) begin + _T_196 <= io_npc_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + pc_r_d1 <= 31'h0; + end else if (pc0_valid_r) begin + pc_r_d1 <= pc_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_231 <= 31'h0; + end else if (_T_229) begin + _T_231 <= mepc_ns; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mcause <= 32'h0; + end else if (_T_274) begin + mcause <= mcause_ns; + end + end + always @(posedge io_e4e5_int_clk or posedge reset) begin + if (reset) begin + mscause <= 4'h0; + end else begin + mscause <= _T_304 | _T_303; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mtval <= 32'h0; + end else if (_T_363) begin + mtval <= mtval_ns; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mcgc_int <= 10'h0; + end else if (wr_mcgc_r) begin + if (wr_mcgc_r) begin + mcgc_int <= _T_372; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mfdc_int <= 16'h0; + end else if (wr_mfdc_r) begin + mfdc_int <= mfdc_ns; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mrac <= 32'h0; + end else if (wr_mrac_r) begin + mrac <= mrac_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mdseac <= 32'h0; + end else if (mdseac_en) begin + mdseac <= io_lsu_imprecise_error_addr_any; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mfdht <= 6'h0; + end else if (wr_mfdht_r) begin + if (wr_mfdht_r) begin + mfdht <= io_dec_csr_wrdata_r[5:0]; + end + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + mfdhs <= 2'h0; + end else if (_T_651) begin + if (wr_mfdhs_r) begin + mfdhs <= io_dec_csr_wrdata_r[1:0]; + end else if (_T_645) begin + mfdhs <= _T_649; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + force_halt_ctr_f <= 32'h0; + end else if (mfdht[0]) begin + if (io_debug_halt_req_f) begin + force_halt_ctr_f <= _T_656; + end else if (io_dbg_tlu_halted_f) begin + force_halt_ctr_f <= 32'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + meivt <= 22'h0; + end else if (wr_meivt_r) begin + meivt <= io_dec_csr_wrdata_r[31:10]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + meihap <= 8'h0; + end else if (wr_meicpct_r) begin + meihap <= io_pic_claimid; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + meicurpl <= 4'h0; + end else if (wr_meicurpl_r) begin + meicurpl <= io_dec_csr_wrdata_r[3:0]; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + meipt <= 4'h0; + end else if (wr_meipt_r) begin + meipt <= io_dec_csr_wrdata_r[3:0]; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_756 <= 16'h0; + end else if (_T_754) begin + if (enter_debug_halt_req_le) begin + _T_756 <= _T_730; + end else if (wr_dcsr_r) begin + _T_756 <= _T_745; + end else begin + _T_756 <= _T_750; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_781 <= 31'h0; + end else if (_T_779) begin + _T_781 <= dpc_ns; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + dicawics <= 17'h0; + end else if (wr_dicawics_r) begin + dicawics <= dicawics_ns; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + dicad0 <= 32'h0; + end else if (_T_795) begin + if (wr_dicad0_r) begin + dicad0 <= io_dec_csr_wrdata_r; + end else begin + dicad0 <= io_ifu_ic_debug_rd_data[31:0]; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + dicad0h <= 32'h0; + end else if (_T_802) begin + if (wr_dicad0h_r) begin + dicad0h <= io_dec_csr_wrdata_r; + end else begin + dicad0h <= io_ifu_ic_debug_rd_data[63:32]; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_815 <= 7'h0; + end else if (_T_813) begin + if (_T_808) begin + _T_815 <= io_dec_csr_wrdata_r[6:0]; + end else begin + _T_815 <= io_ifu_ic_debug_rd_data[70:64]; + end + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mtsel <= 2'h0; + end else if (wr_mtsel_r) begin + mtsel <= io_dec_csr_wrdata_r[1:0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_965 <= 10'h0; + end else if (_T_963) begin + if (wr_mtdata1_t_r_0) begin + _T_965 <= tdata_wrdata_r; + end else begin + _T_965 <= _T_933; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_969 <= 10'h0; + end else if (_T_967) begin + if (wr_mtdata1_t_r_1) begin + _T_969 <= tdata_wrdata_r; + end else begin + _T_969 <= _T_942; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_973 <= 10'h0; + end else if (_T_971) begin + if (wr_mtdata1_t_r_2) begin + _T_973 <= tdata_wrdata_r; + end else begin + _T_973 <= _T_951; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_977 <= 10'h0; + end else if (_T_975) begin + if (wr_mtdata1_t_r_3) begin + _T_977 <= tdata_wrdata_r; + end else begin + _T_977 <= _T_960; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mtdata2_t_0 <= 32'h0; + end else if (wr_mtdata2_t_r_0) begin + mtdata2_t_0 <= io_dec_csr_wrdata_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mtdata2_t_1 <= 32'h0; + end else if (wr_mtdata2_t_r_1) begin + mtdata2_t_1 <= io_dec_csr_wrdata_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mtdata2_t_2 <= 32'h0; + end else if (wr_mtdata2_t_r_2) begin + mtdata2_t_2 <= io_dec_csr_wrdata_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mtdata2_t_3 <= 32'h0; + end else if (wr_mtdata2_t_r_3) begin + mtdata2_t_3 <= io_dec_csr_wrdata_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + dec_tlu_exc_cause_wb2 <= 5'h0; + end else if (_T_1153) begin + dec_tlu_exc_cause_wb2 <= dec_tlu_exc_cause_wb1_raw; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + dec_tlu_int_valid_wb2 <= 1'h0; + end else if (_T_1156) begin + dec_tlu_int_valid_wb2 <= dec_tlu_int_valid_wb1_raw; + end + end +endmodule +module dec_timer_ctl( + input clock, + input reset, + input io_free_l2clk, + input io_csr_wr_clk, + input io_dec_csr_wen_r_mod, + input [11:0] io_dec_csr_wraddr_r, + input [31:0] io_dec_csr_wrdata_r, + input io_csr_mitctl0, + input io_csr_mitctl1, + input io_csr_mitb0, + input io_csr_mitb1, + input io_csr_mitcnt0, + input io_csr_mitcnt1, + input io_dec_pause_state, + input io_dec_tlu_pmu_fw_halted, + input io_internal_dbg_halt_timers, + output [31:0] io_dec_timer_rddata_d, + output io_dec_timer_read_d, + output io_dec_timer_t0_pulse, + output io_dec_timer_t1_pulse +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_io_en; // @[lib.scala 404:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_1_io_en; // @[lib.scala 404:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_2_io_en; // @[lib.scala 404:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_3_io_en; // @[lib.scala 404:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_4_io_en; // @[lib.scala 404:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 404:23] + wire rvclkhdr_5_io_en; // @[lib.scala 404:23] + reg [23:0] _T_28; // @[Reg.scala 27:20] + reg [7:0] _T_33; // @[Reg.scala 27:20] + wire [31:0] mitcnt0 = {_T_28,_T_33}; // @[Cat.scala 29:58] + reg [31:0] mitb0_b; // @[Reg.scala 27:20] + wire [31:0] mitb0 = ~mitb0_b; // @[dec_tlu_ctl.scala 3335:22] + wire mit0_match_ns = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 3277:36] + reg [23:0] _T_67; // @[Reg.scala 27:20] + reg [7:0] _T_72; // @[Reg.scala 27:20] + wire [31:0] mitcnt1 = {_T_67,_T_72}; // @[Cat.scala 29:58] + reg [31:0] mitb1_b; // @[Reg.scala 27:20] + wire [31:0] mitb1 = ~mitb1_b; // @[dec_tlu_ctl.scala 3344:18] + wire mit1_match_ns = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 3278:36] + wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[dec_tlu_ctl.scala 3288:72] + wire wr_mitcnt0_r = io_dec_csr_wen_r_mod & _T; // @[dec_tlu_ctl.scala 3288:49] + reg [1:0] _T_90; // @[Reg.scala 27:20] + reg mitctl0_0_b; // @[Reg.scala 27:20] + wire _T_91 = ~mitctl0_0_b; // @[dec_tlu_ctl.scala 3360:107] + wire [2:0] mitctl0 = {_T_90,_T_91}; // @[Cat.scala 29:58] + wire _T_2 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 3290:56] + wire _T_4 = _T_2 | mitctl0[2]; // @[dec_tlu_ctl.scala 3290:76] + wire _T_5 = mitctl0[0] & _T_4; // @[dec_tlu_ctl.scala 3290:53] + wire _T_6 = ~io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 3290:112] + wire _T_8 = _T_6 | mitctl0[1]; // @[dec_tlu_ctl.scala 3290:138] + wire _T_9 = _T_5 & _T_8; // @[dec_tlu_ctl.scala 3290:109] + wire _T_10 = ~io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 3290:173] + wire mitcnt0_inc_ok = _T_9 & _T_10; // @[dec_tlu_ctl.scala 3290:171] + wire [7:0] _T_14 = mitcnt0[7:0] + 8'h1; // @[dec_tlu_ctl.scala 3293:38] + wire [8:0] mitcnt0_inc1 = {{1'd0}, _T_14}; // @[dec_tlu_ctl.scala 3293:22] + wire mitcnt0_inc_cout = mitcnt0_inc1[8]; // @[dec_tlu_ctl.scala 3294:44] + wire [23:0] _T_16 = {23'h0,mitcnt0_inc_cout}; // @[Cat.scala 29:58] + wire [23:0] mitcnt0_inc2 = mitcnt0[31:8] + _T_16; // @[dec_tlu_ctl.scala 3295:39] + wire [31:0] mitcnt0_inc = {mitcnt0_inc2,mitcnt0_inc1[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_22 = mit0_match_ns ? 32'h0 : mitcnt0_inc; // @[dec_tlu_ctl.scala 3298:69] + wire [31:0] mitcnt0_ns = wr_mitcnt0_r ? io_dec_csr_wrdata_r : _T_22; // @[dec_tlu_ctl.scala 3298:30] + wire _T_24 = mitcnt0_inc_ok & mitcnt0_inc_cout; // @[dec_tlu_ctl.scala 3301:87] + wire _T_25 = wr_mitcnt0_r | _T_24; // @[dec_tlu_ctl.scala 3301:69] + wire _T_26 = _T_25 | mit0_match_ns; // @[dec_tlu_ctl.scala 3301:107] + wire _T_30 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[dec_tlu_ctl.scala 3302:54] + wire _T_31 = _T_30 | mit0_match_ns; // @[dec_tlu_ctl.scala 3302:71] + wire _T_35 = io_dec_csr_wraddr_r == 12'h7d5; // @[dec_tlu_ctl.scala 3309:72] + wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_35; // @[dec_tlu_ctl.scala 3309:49] + reg [2:0] _T_101; // @[Reg.scala 27:20] + reg mitctl1_0_b; // @[Reg.scala 27:20] + wire _T_102 = ~mitctl1_0_b; // @[dec_tlu_ctl.scala 3374:92] + wire [3:0] mitctl1 = {_T_101,_T_102}; // @[Cat.scala 29:58] + wire _T_39 = _T_2 | mitctl1[2]; // @[dec_tlu_ctl.scala 3311:76] + wire _T_40 = mitctl1[0] & _T_39; // @[dec_tlu_ctl.scala 3311:53] + wire _T_43 = _T_6 | mitctl1[1]; // @[dec_tlu_ctl.scala 3311:138] + wire _T_44 = _T_40 & _T_43; // @[dec_tlu_ctl.scala 3311:109] + wire _T_46 = _T_44 & _T_10; // @[dec_tlu_ctl.scala 3311:171] + wire _T_48 = ~mitctl1[3]; // @[dec_tlu_ctl.scala 3311:205] + wire _T_49 = _T_48 | mit0_match_ns; // @[dec_tlu_ctl.scala 3311:217] + wire mitcnt1_inc_ok = _T_46 & _T_49; // @[dec_tlu_ctl.scala 3311:202] + wire [7:0] _T_53 = mitcnt1[7:0] + 8'h1; // @[dec_tlu_ctl.scala 3316:38] + wire [8:0] mitcnt1_inc1 = {{1'd0}, _T_53}; // @[dec_tlu_ctl.scala 3316:22] + wire mitcnt1_inc_cout = mitcnt1_inc1[8]; // @[dec_tlu_ctl.scala 3317:44] + wire [23:0] _T_55 = {23'h0,mitcnt1_inc_cout}; // @[Cat.scala 29:58] + wire [23:0] mitcnt1_inc2 = mitcnt1[31:8] + _T_55; // @[dec_tlu_ctl.scala 3318:39] + wire [31:0] mitcnt1_inc = {mitcnt1_inc2,mitcnt1_inc1[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_61 = mit1_match_ns ? 32'h0 : mitcnt1_inc; // @[dec_tlu_ctl.scala 3321:75] + wire [31:0] mitcnt1_ns = wr_mitcnt1_r ? io_dec_csr_wrdata_r : _T_61; // @[dec_tlu_ctl.scala 3321:29] + wire _T_63 = mitcnt1_inc_ok & mitcnt1_inc_cout; // @[dec_tlu_ctl.scala 3323:87] + wire _T_64 = wr_mitcnt1_r | _T_63; // @[dec_tlu_ctl.scala 3323:69] + wire _T_65 = _T_64 | mit1_match_ns; // @[dec_tlu_ctl.scala 3323:107] + wire _T_69 = wr_mitcnt1_r | mitcnt1_inc_ok; // @[dec_tlu_ctl.scala 3324:54] + wire _T_70 = _T_69 | mit1_match_ns; // @[dec_tlu_ctl.scala 3324:71] + wire _T_74 = io_dec_csr_wraddr_r == 12'h7d3; // @[dec_tlu_ctl.scala 3333:70] + wire wr_mitb0_r = io_dec_csr_wen_r_mod & _T_74; // @[dec_tlu_ctl.scala 3333:47] + wire [31:0] _T_75 = ~io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 3334:38] + wire _T_78 = io_dec_csr_wraddr_r == 12'h7d6; // @[dec_tlu_ctl.scala 3342:69] + wire wr_mitb1_r = io_dec_csr_wen_r_mod & _T_78; // @[dec_tlu_ctl.scala 3342:47] + wire _T_82 = io_dec_csr_wraddr_r == 12'h7d4; // @[dec_tlu_ctl.scala 3355:72] + wire wr_mitctl0_r = io_dec_csr_wen_r_mod & _T_82; // @[dec_tlu_ctl.scala 3355:49] + wire [2:0] mitctl0_ns = wr_mitctl0_r ? io_dec_csr_wrdata_r[2:0] : mitctl0; // @[dec_tlu_ctl.scala 3356:31] + wire mitctl0_0_b_ns = ~mitctl0_ns[0]; // @[dec_tlu_ctl.scala 3358:30] + wire _T_93 = io_dec_csr_wraddr_r == 12'h7d7; // @[dec_tlu_ctl.scala 3370:71] + wire wr_mitctl1_r = io_dec_csr_wen_r_mod & _T_93; // @[dec_tlu_ctl.scala 3370:49] + wire [3:0] mitctl1_ns = wr_mitctl1_r ? io_dec_csr_wrdata_r[3:0] : mitctl1; // @[dec_tlu_ctl.scala 3371:31] + wire mitctl1_0_b_ns = ~mitctl1_ns[0]; // @[dec_tlu_ctl.scala 3372:29] + wire _T_104 = io_csr_mitcnt1 | io_csr_mitcnt0; // @[dec_tlu_ctl.scala 3376:51] + wire _T_105 = _T_104 | io_csr_mitb1; // @[dec_tlu_ctl.scala 3376:68] + wire _T_106 = _T_105 | io_csr_mitb0; // @[dec_tlu_ctl.scala 3376:83] + wire _T_107 = _T_106 | io_csr_mitctl0; // @[dec_tlu_ctl.scala 3376:98] + wire [31:0] _T_116 = {29'h0,_T_90,_T_91}; // @[Cat.scala 29:58] + wire [31:0] _T_119 = {28'h0,_T_101,_T_102}; // @[Cat.scala 29:58] + wire [31:0] _T_120 = io_csr_mitcnt0 ? mitcnt0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_121 = io_csr_mitcnt1 ? mitcnt1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_122 = io_csr_mitb0 ? mitb0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_123 = io_csr_mitb1 ? mitb1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_124 = io_csr_mitctl0 ? _T_116 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_125 = io_csr_mitctl1 ? _T_119 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_126 = _T_120 | _T_121; // @[Mux.scala 27:72] + wire [31:0] _T_127 = _T_126 | _T_122; // @[Mux.scala 27:72] + wire [31:0] _T_128 = _T_127 | _T_123; // @[Mux.scala 27:72] + wire [31:0] _T_129 = _T_128 | _T_124; // @[Mux.scala 27:72] + rvclkhdr rvclkhdr ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 404:23] + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en) + ); + assign io_dec_timer_rddata_d = _T_129 | _T_125; // @[dec_tlu_ctl.scala 3377:33] + assign io_dec_timer_read_d = _T_107 | io_csr_mitctl1; // @[dec_tlu_ctl.scala 3376:33] + assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 3280:31] + assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 3281:31] + assign rvclkhdr_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_io_en = _T_25 | mit0_match_ns; // @[lib.scala 407:17] + assign rvclkhdr_1_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_1_io_en = _T_30 | mit0_match_ns; // @[lib.scala 407:17] + assign rvclkhdr_2_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_2_io_en = _T_64 | mit1_match_ns; // @[lib.scala 407:17] + assign rvclkhdr_3_io_clk = io_free_l2clk; // @[lib.scala 406:18] + assign rvclkhdr_3_io_en = _T_69 | mit1_match_ns; // @[lib.scala 407:17] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_4_io_en = io_dec_csr_wen_r_mod & _T_74; // @[lib.scala 407:17] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18] + assign rvclkhdr_5_io_en = io_dec_csr_wen_r_mod & _T_78; // @[lib.scala 407:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T_28 = _RAND_0[23:0]; + _RAND_1 = {1{`RANDOM}}; + _T_33 = _RAND_1[7:0]; + _RAND_2 = {1{`RANDOM}}; + mitb0_b = _RAND_2[31:0]; + _RAND_3 = {1{`RANDOM}}; + _T_67 = _RAND_3[23:0]; + _RAND_4 = {1{`RANDOM}}; + _T_72 = _RAND_4[7:0]; + _RAND_5 = {1{`RANDOM}}; + mitb1_b = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + _T_90 = _RAND_6[1:0]; + _RAND_7 = {1{`RANDOM}}; + mitctl0_0_b = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + _T_101 = _RAND_8[2:0]; + _RAND_9 = {1{`RANDOM}}; + mitctl1_0_b = _RAND_9[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_28 = 24'h0; + end + if (reset) begin + _T_33 = 8'h0; + end + if (reset) begin + mitb0_b = 32'h0; + end + if (reset) begin + _T_67 = 24'h0; + end + if (reset) begin + _T_72 = 8'h0; + end + if (reset) begin + mitb1_b = 32'h0; + end + if (reset) begin + _T_90 = 2'h0; + end + if (reset) begin + mitctl0_0_b = 1'h0; + end + if (reset) begin + _T_101 = 3'h0; + end + if (reset) begin + mitctl1_0_b = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_28 <= 24'h0; + end else if (_T_26) begin + _T_28 <= mitcnt0_ns[31:8]; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_33 <= 8'h0; + end else if (_T_31) begin + _T_33 <= mitcnt0_ns[7:0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mitb0_b <= 32'h0; + end else if (wr_mitb0_r) begin + mitb0_b <= _T_75; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_67 <= 24'h0; + end else if (_T_65) begin + _T_67 <= mitcnt1_ns[31:8]; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_72 <= 8'h0; + end else if (_T_70) begin + _T_72 <= mitcnt1_ns[7:0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + mitb1_b <= 32'h0; + end else if (wr_mitb1_r) begin + mitb1_b <= _T_75; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + _T_90 <= 2'h0; + end else if (wr_mitctl0_r) begin + _T_90 <= mitctl0_ns[2:1]; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mitctl0_0_b <= 1'h0; + end else if (wr_mitctl0_r) begin + mitctl0_0_b <= mitctl0_0_b_ns; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + _T_101 <= 3'h0; + end else if (wr_mitctl1_r) begin + _T_101 <= mitctl1_ns[3:1]; + end + end + always @(posedge io_csr_wr_clk or posedge reset) begin + if (reset) begin + mitctl1_0_b <= 1'h0; + end else if (wr_mitctl1_r) begin + mitctl1_0_b <= mitctl1_0_b_ns; + end + end +endmodule +module dec_decode_csr_read( + input [11:0] io_dec_csr_rdaddr_d, + output io_csr_pkt_csr_misa, + output io_csr_pkt_csr_mvendorid, + output io_csr_pkt_csr_marchid, + output io_csr_pkt_csr_mimpid, + output io_csr_pkt_csr_mhartid, + output io_csr_pkt_csr_mstatus, + output io_csr_pkt_csr_mtvec, + output io_csr_pkt_csr_mip, + output io_csr_pkt_csr_mie, + output io_csr_pkt_csr_mcyclel, + output io_csr_pkt_csr_mcycleh, + output io_csr_pkt_csr_minstretl, + output io_csr_pkt_csr_minstreth, + output io_csr_pkt_csr_mscratch, + output io_csr_pkt_csr_mepc, + output io_csr_pkt_csr_mcause, + output io_csr_pkt_csr_mscause, + output io_csr_pkt_csr_mtval, + output io_csr_pkt_csr_mrac, + output io_csr_pkt_csr_dmst, + output io_csr_pkt_csr_mdseac, + output io_csr_pkt_csr_meihap, + output io_csr_pkt_csr_meivt, + output io_csr_pkt_csr_meipt, + output io_csr_pkt_csr_meicurpl, + output io_csr_pkt_csr_meicidpl, + output io_csr_pkt_csr_dcsr, + output io_csr_pkt_csr_mcgc, + output io_csr_pkt_csr_mfdc, + output io_csr_pkt_csr_dpc, + output io_csr_pkt_csr_mtsel, + output io_csr_pkt_csr_mtdata1, + output io_csr_pkt_csr_mtdata2, + output io_csr_pkt_csr_mhpmc3, + output io_csr_pkt_csr_mhpmc4, + output io_csr_pkt_csr_mhpmc5, + output io_csr_pkt_csr_mhpmc6, + output io_csr_pkt_csr_mhpmc3h, + output io_csr_pkt_csr_mhpmc4h, + output io_csr_pkt_csr_mhpmc5h, + output io_csr_pkt_csr_mhpmc6h, + output io_csr_pkt_csr_mhpme3, + output io_csr_pkt_csr_mhpme4, + output io_csr_pkt_csr_mhpme5, + output io_csr_pkt_csr_mhpme6, + output io_csr_pkt_csr_mcountinhibit, + output io_csr_pkt_csr_mitctl0, + output io_csr_pkt_csr_mitctl1, + output io_csr_pkt_csr_mitb0, + output io_csr_pkt_csr_mitb1, + output io_csr_pkt_csr_mitcnt0, + output io_csr_pkt_csr_mitcnt1, + output io_csr_pkt_csr_mpmc, + output io_csr_pkt_csr_meicpct, + output io_csr_pkt_csr_micect, + output io_csr_pkt_csr_miccmect, + output io_csr_pkt_csr_mdccmect, + output io_csr_pkt_csr_mfdht, + output io_csr_pkt_csr_mfdhs, + output io_csr_pkt_csr_dicawics, + output io_csr_pkt_csr_dicad0h, + output io_csr_pkt_csr_dicad0, + output io_csr_pkt_csr_dicad1, + output io_csr_pkt_csr_dicago, + output io_csr_pkt_presync, + output io_csr_pkt_postsync, + output io_csr_pkt_legal +); + wire _T_1 = ~io_dec_csr_rdaddr_d[11]; // @[dec_tlu_ctl.scala 3173:129] + wire _T_3 = ~io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:129] + wire _T_5 = ~io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:129] + wire _T_7 = ~io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:129] + wire _T_9 = _T_1 & _T_3; // @[dec_tlu_ctl.scala 3173:198] + wire _T_10 = _T_9 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_11 = _T_10 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_15 = ~io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 3173:129] + wire _T_17 = ~io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:129] + wire _T_19 = io_dec_csr_rdaddr_d[10] & _T_15; // @[dec_tlu_ctl.scala 3173:198] + wire _T_20 = _T_19 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_27 = ~io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:165] + wire _T_29 = _T_19 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_36 = io_dec_csr_rdaddr_d[10] & _T_3; // @[dec_tlu_ctl.scala 3173:198] + wire _T_37 = _T_36 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_69 = _T_10 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_70 = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_75 = _T_15 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_94 = ~io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:129] + wire _T_96 = ~io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:129] + wire _T_101 = io_dec_csr_rdaddr_d[11] & _T_15; // @[dec_tlu_ctl.scala 3173:198] + wire _T_102 = _T_101 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_103 = _T_102 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_104 = _T_103 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_119 = io_dec_csr_rdaddr_d[7] & _T_3; // @[dec_tlu_ctl.scala 3173:198] + wire _T_120 = _T_119 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_121 = _T_120 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_122 = _T_121 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_123 = _T_122 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_138 = _T_15 & _T_3; // @[dec_tlu_ctl.scala 3173:198] + wire _T_139 = _T_138 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_140 = _T_139 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_141 = _T_140 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_142 = _T_141 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_145 = ~io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 3173:129] + wire _T_156 = _T_145 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_157 = _T_156 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_158 = _T_157 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_159 = _T_158 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_160 = _T_159 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_172 = _T_75 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_173 = _T_172 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_182 = _T_75 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_183 = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_191 = _T_75 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_196 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_217 = _T_1 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_218 = _T_217 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_219 = _T_218 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_220 = _T_219 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_230 = io_dec_csr_rdaddr_d[10] & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_231 = _T_230 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_232 = _T_231 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_240 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_241 = _T_240 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_258 = _T_145 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_259 = _T_258 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_260 = _T_259 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_261 = _T_260 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_268 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_269 = _T_268 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_281 = _T_268 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_291 = _T_36 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_292 = _T_291 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_299 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_300 = _T_299 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_310 = _T_300 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_311 = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_330 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_331 = _T_330 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_332 = _T_331 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_342 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_381 = _T_103 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_382 = _T_381 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_397 = _T_103 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_411 = _T_15 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_412 = _T_411 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_413 = _T_412 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_414 = _T_413 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_415 = _T_414 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_426 = io_dec_csr_rdaddr_d[7] & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_427 = _T_426 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_428 = _T_427 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_429 = _T_428 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_444 = _T_119 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_445 = _T_444 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_446 = _T_445 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_447 = _T_446 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_460 = _T_427 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_461 = _T_460 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_478 = _T_446 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_490 = _T_15 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_491 = _T_490 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_492 = _T_491 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_493 = _T_492 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_505 = io_dec_csr_rdaddr_d[5] & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_506 = _T_505 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_507 = _T_506 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_508 = _T_507 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_536 = _T_507 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_553 = _T_493 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_562 = io_dec_csr_rdaddr_d[6] & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_563 = _T_562 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_564 = _T_563 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_572 = io_dec_csr_rdaddr_d[6] & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_573 = _T_572 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_574 = _T_573 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_585 = _T_563 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_593 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_594 = _T_593 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_595 = _T_594 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_614 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_615 = _T_614 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_624 = io_dec_csr_rdaddr_d[6] & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_625 = _T_624 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_626 = _T_625 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_645 = _T_196 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_646 = _T_645 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_662 = _T_196 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_670 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_671 = _T_670 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_672 = _T_671 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_680 = _T_624 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_693 = _T_1 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_694 = _T_693 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_695 = _T_694 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_696 = _T_695 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_703 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_704 = _T_703 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_714 = _T_230 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_715 = _T_714 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_725 = _T_703 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_726 = _T_725 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_764 = _T_311 | _T_553; // @[dec_tlu_ctl.scala 3241:81] + wire _T_776 = _T_3 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_777 = _T_776 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_778 = _T_777 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_779 = _T_778 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_780 = _T_779 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_781 = _T_764 | _T_780; // @[dec_tlu_ctl.scala 3241:121] + wire _T_790 = io_dec_csr_rdaddr_d[11] & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_791 = _T_790 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_792 = _T_791 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_793 = _T_792 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_794 = _T_781 | _T_793; // @[dec_tlu_ctl.scala 3241:155] + wire _T_805 = _T_791 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_806 = _T_805 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_807 = _T_794 | _T_806; // @[dec_tlu_ctl.scala 3242:49] + wire _T_818 = io_dec_csr_rdaddr_d[7] & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_819 = _T_818 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_820 = _T_819 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_821 = _T_820 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_822 = _T_821 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_846 = _T_311 | _T_70; // @[dec_tlu_ctl.scala 3243:81] + wire _T_856 = _T_846 | _T_183; // @[dec_tlu_ctl.scala 3243:121] + wire _T_866 = _T_856 | _T_342; // @[dec_tlu_ctl.scala 3243:162] + wire _T_881 = _T_1 & _T_15; // @[dec_tlu_ctl.scala 3173:198] + wire _T_882 = _T_881 & _T_3; // @[dec_tlu_ctl.scala 3173:198] + wire _T_883 = _T_882 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_884 = _T_883 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_885 = _T_884 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_886 = _T_885 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_887 = _T_866 | _T_886; // @[dec_tlu_ctl.scala 3244:57] + wire _T_899 = _T_217 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_900 = _T_899 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_901 = _T_900 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_902 = _T_901 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_903 = _T_887 | _T_902; // @[dec_tlu_ctl.scala 3244:97] + wire _T_914 = _T_231 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_915 = _T_914 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_932 = _T_1 & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_933 = _T_932 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_934 = _T_933 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_935 = _T_934 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_936 = _T_935 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_937 = _T_936 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_938 = _T_937 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_939 = _T_938 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_940 = _T_939 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_941 = _T_940 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_960 = _T_1 & _T_145; // @[dec_tlu_ctl.scala 3173:198] + wire _T_961 = _T_960 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_962 = _T_961 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_963 = _T_962 & _T_15; // @[dec_tlu_ctl.scala 3173:198] + wire _T_964 = _T_963 & _T_3; // @[dec_tlu_ctl.scala 3173:198] + wire _T_965 = _T_964 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_966 = _T_965 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_967 = _T_966 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_968 = _T_967 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_969 = _T_941 | _T_968; // @[dec_tlu_ctl.scala 3246:81] + wire _T_990 = _T_964 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_991 = _T_990 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_992 = _T_991 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_993 = _T_969 | _T_992; // @[dec_tlu_ctl.scala 3246:129] + wire _T_1009 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1010 = _T_1009 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1011 = _T_1010 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1012 = _T_1011 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1013 = _T_1012 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1014 = _T_1013 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1015 = _T_1014 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1016 = _T_1015 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1017 = _T_1016 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1018 = _T_993 | _T_1017; // @[dec_tlu_ctl.scala 3247:73] + wire _T_1030 = io_dec_csr_rdaddr_d[11] & _T_145; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1031 = _T_1030 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1032 = _T_1031 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1033 = _T_1032 & _T_3; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1034 = _T_1033 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1035 = _T_1034 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1036 = _T_1018 | _T_1035; // @[dec_tlu_ctl.scala 3247:121] + wire _T_1055 = _T_936 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1056 = _T_1055 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1057 = _T_1056 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1058 = _T_1057 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1059 = _T_1058 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1060 = _T_1059 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1061 = _T_1036 | _T_1060; // @[dec_tlu_ctl.scala 3248:73] + wire _T_1082 = _T_1056 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1083 = _T_1082 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1084 = _T_1061 | _T_1083; // @[dec_tlu_ctl.scala 3248:121] + wire _T_1102 = _T_1010 & _T_15; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1103 = _T_1102 & _T_3; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1104 = _T_1103 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1105 = _T_1104 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1106 = _T_1105 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1107 = _T_1106 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1108 = _T_1107 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1109 = _T_1084 | _T_1108; // @[dec_tlu_ctl.scala 3249:73] + wire _T_1129 = _T_935 & _T_3; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1130 = _T_1129 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1131 = _T_1130 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1132 = _T_1131 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1133 = _T_1132 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1134 = _T_1109 | _T_1133; // @[dec_tlu_ctl.scala 3249:129] + wire _T_1153 = _T_990 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1154 = _T_1134 | _T_1153; // @[dec_tlu_ctl.scala 3250:73] + wire _T_1179 = _T_1106 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1180 = _T_1179 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1181 = _T_1180 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1182 = _T_1154 | _T_1181; // @[dec_tlu_ctl.scala 3250:129] + wire _T_1201 = _T_936 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1202 = _T_1201 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1203 = _T_1202 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1204 = _T_1203 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1205 = _T_1182 | _T_1204; // @[dec_tlu_ctl.scala 3251:65] + wire _T_1225 = _T_1201 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1226 = _T_1225 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1227 = _T_1226 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1228 = _T_1205 | _T_1227; // @[dec_tlu_ctl.scala 3251:121] + wire _T_1252 = _T_1107 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1253 = _T_1228 | _T_1252; // @[dec_tlu_ctl.scala 3252:73] + wire _T_1273 = _T_990 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1274 = _T_1273 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1275 = _T_1253 | _T_1274; // @[dec_tlu_ctl.scala 3252:129] + wire _T_1292 = _T_1032 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1293 = _T_1292 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1294 = _T_1293 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1295 = _T_1294 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1296 = _T_1295 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1297 = _T_1275 | _T_1296; // @[dec_tlu_ctl.scala 3253:73] + wire _T_1320 = _T_1295 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1321 = _T_1320 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1322 = _T_1297 | _T_1321; // @[dec_tlu_ctl.scala 3253:129] + wire _T_1338 = _T_1034 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1339 = _T_1322 | _T_1338; // @[dec_tlu_ctl.scala 3254:73] + wire _T_1361 = _T_1226 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1362 = _T_1339 | _T_1361; // @[dec_tlu_ctl.scala 3254:129] + wire _T_1383 = _T_1202 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1384 = _T_1362 | _T_1383; // @[dec_tlu_ctl.scala 3255:73] + wire _T_1407 = _T_1203 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1408 = _T_1384 | _T_1407; // @[dec_tlu_ctl.scala 3255:129] + wire _T_1432 = _T_1130 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1433 = _T_1432 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1434 = _T_1433 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1435 = _T_1434 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1436 = _T_1408 | _T_1435; // @[dec_tlu_ctl.scala 3256:73] + wire _T_1452 = _T_1034 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1453 = _T_1436 | _T_1452; // @[dec_tlu_ctl.scala 3256:121] + wire _T_1475 = _T_963 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1476 = _T_1475 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1477 = _T_1476 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1478 = _T_1477 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1479 = _T_1478 & _T_7; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1480 = _T_1453 | _T_1479; // @[dec_tlu_ctl.scala 3257:81] + wire _T_1503 = _T_963 & _T_5; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1504 = _T_1503 & _T_94; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1505 = _T_1504 & _T_96; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1506 = _T_1505 & _T_17; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1507 = _T_1506 & _T_27; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1508 = _T_1480 | _T_1507; // @[dec_tlu_ctl.scala 3257:129] + wire _T_1527 = _T_990 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1528 = _T_1508 | _T_1527; // @[dec_tlu_ctl.scala 3258:65] + wire _T_1544 = _T_1034 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1545 = _T_1528 | _T_1544; // @[dec_tlu_ctl.scala 3258:121] + wire _T_1564 = _T_990 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + wire _T_1565 = _T_1545 | _T_1564; // @[dec_tlu_ctl.scala 3259:81] + wire _T_1581 = _T_1034 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 3173:198] + assign io_csr_pkt_csr_misa = _T_11 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3175:57] + assign io_csr_pkt_csr_mvendorid = _T_20 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3176:57] + assign io_csr_pkt_csr_marchid = _T_29 & _T_27; // @[dec_tlu_ctl.scala 3177:57] + assign io_csr_pkt_csr_mimpid = _T_37 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3178:57] + assign io_csr_pkt_csr_mhartid = _T_19 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3179:57] + assign io_csr_pkt_csr_mstatus = _T_11 & _T_27; // @[dec_tlu_ctl.scala 3180:57] + assign io_csr_pkt_csr_mtvec = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3181:57] + assign io_csr_pkt_csr_mip = _T_75 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3182:65] + assign io_csr_pkt_csr_mie = _T_69 & _T_27; // @[dec_tlu_ctl.scala 3183:65] + assign io_csr_pkt_csr_mcyclel = _T_104 & _T_17; // @[dec_tlu_ctl.scala 3184:57] + assign io_csr_pkt_csr_mcycleh = _T_123 & _T_17; // @[dec_tlu_ctl.scala 3185:57] + assign io_csr_pkt_csr_minstretl = _T_142 & _T_27; // @[dec_tlu_ctl.scala 3186:57] + assign io_csr_pkt_csr_minstreth = _T_160 & _T_27; // @[dec_tlu_ctl.scala 3187:57] + assign io_csr_pkt_csr_mscratch = _T_173 & _T_27; // @[dec_tlu_ctl.scala 3188:57] + assign io_csr_pkt_csr_mepc = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3189:57] + assign io_csr_pkt_csr_mcause = _T_191 & _T_27; // @[dec_tlu_ctl.scala 3190:57] + assign io_csr_pkt_csr_mscause = _T_196 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3191:57] + assign io_csr_pkt_csr_mtval = _T_191 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3192:57] + assign io_csr_pkt_csr_mrac = _T_220 & _T_17; // @[dec_tlu_ctl.scala 3193:57] + assign io_csr_pkt_csr_dmst = _T_232 & _T_17; // @[dec_tlu_ctl.scala 3194:57] + assign io_csr_pkt_csr_mdseac = _T_241 & _T_96; // @[dec_tlu_ctl.scala 3195:57] + assign io_csr_pkt_csr_meihap = _T_240 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 3196:57] + assign io_csr_pkt_csr_meivt = _T_261 & _T_27; // @[dec_tlu_ctl.scala 3197:57] + assign io_csr_pkt_csr_meipt = _T_269 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3198:57] + assign io_csr_pkt_csr_meicurpl = _T_268 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 3199:57] + assign io_csr_pkt_csr_meicidpl = _T_281 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3200:57] + assign io_csr_pkt_csr_dcsr = _T_292 & _T_27; // @[dec_tlu_ctl.scala 3201:57] + assign io_csr_pkt_csr_mcgc = _T_300 & _T_27; // @[dec_tlu_ctl.scala 3202:57] + assign io_csr_pkt_csr_mfdc = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3203:57] + assign io_csr_pkt_csr_dpc = _T_292 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3204:65] + assign io_csr_pkt_csr_mtsel = _T_332 & _T_27; // @[dec_tlu_ctl.scala 3205:57] + assign io_csr_pkt_csr_mtdata1 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3206:57] + assign io_csr_pkt_csr_mtdata2 = _T_331 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3207:57] + assign io_csr_pkt_csr_mhpmc3 = _T_104 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3208:57] + assign io_csr_pkt_csr_mhpmc4 = _T_382 & _T_27; // @[dec_tlu_ctl.scala 3209:57] + assign io_csr_pkt_csr_mhpmc5 = _T_397 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3210:57] + assign io_csr_pkt_csr_mhpmc6 = _T_415 & _T_27; // @[dec_tlu_ctl.scala 3211:57] + assign io_csr_pkt_csr_mhpmc3h = _T_429 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3212:57] + assign io_csr_pkt_csr_mhpmc4h = _T_447 & _T_27; // @[dec_tlu_ctl.scala 3213:57] + assign io_csr_pkt_csr_mhpmc5h = _T_461 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3214:57] + assign io_csr_pkt_csr_mhpmc6h = _T_478 & _T_27; // @[dec_tlu_ctl.scala 3215:57] + assign io_csr_pkt_csr_mhpme3 = _T_493 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3216:57] + assign io_csr_pkt_csr_mhpme4 = _T_508 & _T_27; // @[dec_tlu_ctl.scala 3217:57] + assign io_csr_pkt_csr_mhpme5 = _T_508 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3218:57] + assign io_csr_pkt_csr_mhpme6 = _T_536 & _T_27; // @[dec_tlu_ctl.scala 3219:57] + assign io_csr_pkt_csr_mcountinhibit = _T_493 & _T_27; // @[dec_tlu_ctl.scala 3220:49] + assign io_csr_pkt_csr_mitctl0 = _T_564 & _T_27; // @[dec_tlu_ctl.scala 3221:57] + assign io_csr_pkt_csr_mitctl1 = _T_574 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3222:57] + assign io_csr_pkt_csr_mitb0 = _T_585 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3223:57] + assign io_csr_pkt_csr_mitb1 = _T_595 & _T_27; // @[dec_tlu_ctl.scala 3224:57] + assign io_csr_pkt_csr_mitcnt0 = _T_585 & _T_27; // @[dec_tlu_ctl.scala 3225:57] + assign io_csr_pkt_csr_mitcnt1 = _T_615 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3226:57] + assign io_csr_pkt_csr_mpmc = _T_626 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 3227:57] + assign io_csr_pkt_csr_meicpct = _T_281 & _T_27; // @[dec_tlu_ctl.scala 3229:57] + assign io_csr_pkt_csr_micect = _T_646 & _T_27; // @[dec_tlu_ctl.scala 3231:57] + assign io_csr_pkt_csr_miccmect = _T_645 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3232:57] + assign io_csr_pkt_csr_mdccmect = _T_662 & _T_27; // @[dec_tlu_ctl.scala 3233:57] + assign io_csr_pkt_csr_mfdht = _T_672 & _T_27; // @[dec_tlu_ctl.scala 3234:57] + assign io_csr_pkt_csr_mfdhs = _T_680 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3235:57] + assign io_csr_pkt_csr_dicawics = _T_696 & _T_27; // @[dec_tlu_ctl.scala 3236:57] + assign io_csr_pkt_csr_dicad0h = _T_704 & _T_17; // @[dec_tlu_ctl.scala 3237:57] + assign io_csr_pkt_csr_dicad0 = _T_715 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3238:57] + assign io_csr_pkt_csr_dicad1 = _T_726 & _T_27; // @[dec_tlu_ctl.scala 3239:57] + assign io_csr_pkt_csr_dicago = _T_726 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 3240:57] + assign io_csr_pkt_presync = _T_807 | _T_822; // @[dec_tlu_ctl.scala 3241:34] + assign io_csr_pkt_postsync = _T_903 | _T_915; // @[dec_tlu_ctl.scala 3243:30] + assign io_csr_pkt_legal = _T_1565 | _T_1581; // @[dec_tlu_ctl.scala 3246:26] +endmodule +module dec_tlu_ctl( + input clock, + input reset, + output [29:0] io_tlu_exu_dec_tlu_meihap, + output io_tlu_exu_dec_tlu_flush_lower_r, + output [30:0] io_tlu_exu_dec_tlu_flush_path_r, + input [1:0] io_tlu_exu_exu_i0_br_hist_r, + input io_tlu_exu_exu_i0_br_error_r, + input io_tlu_exu_exu_i0_br_start_error_r, + input [7:0] io_tlu_exu_exu_i0_br_index_r, + input io_tlu_exu_exu_i0_br_valid_r, + input io_tlu_exu_exu_i0_br_mp_r, + input io_tlu_exu_exu_i0_br_middle_r, + input io_tlu_exu_exu_pmu_i0_br_misp, + input io_tlu_exu_exu_pmu_i0_br_ataken, + input io_tlu_exu_exu_pmu_i0_pc4, + input [30:0] io_tlu_exu_exu_npc_r, + input io_tlu_dma_dma_pmu_dccm_read, + input io_tlu_dma_dma_pmu_dccm_write, + input io_tlu_dma_dma_pmu_any_read, + input io_tlu_dma_dma_pmu_any_write, + output [2:0] io_tlu_dma_dec_tlu_dma_qos_prty, + input io_tlu_dma_dma_dccm_stall_any, + input io_tlu_dma_dma_iccm_stall_any, + input io_free_clk, + input io_free_l2clk, + input io_scan_mode, + input [30:0] io_rst_vec, + input io_nmi_int, + input [30:0] io_nmi_vec, + input io_i_cpu_halt_req, + input io_i_cpu_run_req, + input io_lsu_fastint_stall_any, + input io_lsu_idle_any, + input io_dec_pmu_instr_decoded, + input io_dec_pmu_decode_stall, + input io_dec_pmu_presync_stall, + input io_dec_pmu_postsync_stall, + input io_lsu_store_stall_any, + input [30:0] io_lsu_fir_addr, + input [1:0] io_lsu_fir_error, + input io_iccm_dma_sb_error, + input io_lsu_error_pkt_r_valid, + input io_lsu_error_pkt_r_bits_single_ecc_error, + input io_lsu_error_pkt_r_bits_inst_type, + input io_lsu_error_pkt_r_bits_exc_type, + input [3:0] io_lsu_error_pkt_r_bits_mscause, + input [31:0] io_lsu_error_pkt_r_bits_addr, + input io_lsu_single_ecc_error_incr, + input io_dec_pause_state, + input io_dec_csr_wen_unq_d, + input io_dec_csr_any_unq_d, + input [11:0] io_dec_csr_rdaddr_d, + input io_dec_csr_wen_r, + input [11:0] io_dec_csr_wraddr_r, + input [31:0] io_dec_csr_wrdata_r, + input io_dec_csr_stall_int_ff, + input io_dec_tlu_i0_valid_r, + input [30:0] io_dec_tlu_i0_pc_r, + input io_dec_tlu_packet_r_legal, + input io_dec_tlu_packet_r_icaf, + input io_dec_tlu_packet_r_icaf_second, + input [1:0] io_dec_tlu_packet_r_icaf_type, + input io_dec_tlu_packet_r_fence_i, + input [3:0] io_dec_tlu_packet_r_i0trigger, + input [3:0] io_dec_tlu_packet_r_pmu_i0_itype, + input io_dec_tlu_packet_r_pmu_i0_br_unpred, + input io_dec_tlu_packet_r_pmu_divide, + input io_dec_tlu_packet_r_pmu_lsu_misaligned, + input [31:0] io_dec_illegal_inst, + input io_dec_i0_decode_d, + input io_exu_i0_br_way_r, + output io_dec_tlu_core_empty, + output io_dec_dbg_cmd_done, + output io_dec_dbg_cmd_fail, + output io_dec_tlu_dbg_halted, + output io_dec_tlu_debug_mode, + output io_dec_tlu_resume_ack, + output io_dec_tlu_debug_stall, + output io_dec_tlu_mpc_halted_only, + output io_dec_tlu_flush_extint, + input io_dbg_halt_req, + input io_dbg_resume_req, + input io_dec_div_active, + output io_trigger_pkt_any_0_select, + output io_trigger_pkt_any_0_match_pkt, + output io_trigger_pkt_any_0_store, + output io_trigger_pkt_any_0_load, + output io_trigger_pkt_any_0_execute, + output io_trigger_pkt_any_0_m, + output [31:0] io_trigger_pkt_any_0_tdata2, + output io_trigger_pkt_any_1_select, + output io_trigger_pkt_any_1_match_pkt, + output io_trigger_pkt_any_1_store, + output io_trigger_pkt_any_1_load, + output io_trigger_pkt_any_1_execute, + output io_trigger_pkt_any_1_m, + output [31:0] io_trigger_pkt_any_1_tdata2, + output io_trigger_pkt_any_2_select, + output io_trigger_pkt_any_2_match_pkt, + output io_trigger_pkt_any_2_store, + output io_trigger_pkt_any_2_load, + output io_trigger_pkt_any_2_execute, + output io_trigger_pkt_any_2_m, + output [31:0] io_trigger_pkt_any_2_tdata2, + output io_trigger_pkt_any_3_select, + output io_trigger_pkt_any_3_match_pkt, + output io_trigger_pkt_any_3_store, + output io_trigger_pkt_any_3_load, + output io_trigger_pkt_any_3_execute, + output io_trigger_pkt_any_3_m, + output [31:0] io_trigger_pkt_any_3_tdata2, + input io_timer_int, + input io_soft_int, + output io_o_cpu_halt_status, + output io_o_cpu_halt_ack, + output io_o_cpu_run_ack, + output io_o_debug_mode_status, + input [27:0] io_core_id, + input io_mpc_debug_halt_req, + input io_mpc_debug_run_req, + input io_mpc_reset_run_req, + output io_mpc_debug_halt_ack, + output io_mpc_debug_run_ack, + output io_debug_brkpt_status, + output [31:0] io_dec_csr_rddata_d, + output io_dec_csr_legal_d, + output io_dec_tlu_i0_kill_writeb_wb, + output io_dec_tlu_i0_kill_writeb_r, + output io_dec_tlu_wr_pause_r, + output io_dec_tlu_flush_pause_r, + output io_dec_tlu_presync_d, + output io_dec_tlu_postsync_d, + output io_dec_tlu_perfcnt0, + output io_dec_tlu_perfcnt1, + output io_dec_tlu_perfcnt2, + output io_dec_tlu_perfcnt3, + output io_dec_tlu_i0_exc_valid_wb1, + output io_dec_tlu_i0_valid_wb1, + output io_dec_tlu_int_valid_wb1, + output [4:0] io_dec_tlu_exc_cause_wb1, + output [31:0] io_dec_tlu_mtval_wb1, + output io_dec_tlu_pipelining_disable, + output io_dec_tlu_trace_disable, + output io_dec_tlu_misc_clk_override, + output io_dec_tlu_dec_clk_override, + output io_dec_tlu_ifu_clk_override, + output io_dec_tlu_lsu_clk_override, + output io_dec_tlu_bus_clk_override, + output io_dec_tlu_pic_clk_override, + output io_dec_tlu_picio_clk_override, + output io_dec_tlu_dccm_clk_override, + output io_dec_tlu_icm_clk_override, + output io_dec_tlu_flush_lower_wb, + input io_ifu_pmu_instr_aligned, + output io_tlu_bp_dec_tlu_br0_r_pkt_valid, + output [1:0] io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist, + output io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error, + output io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error, + output io_tlu_bp_dec_tlu_br0_r_pkt_bits_way, + output io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle, + output io_tlu_bp_dec_tlu_flush_leak_one_wb, + output io_tlu_bp_dec_tlu_bpred_disable, + output io_tlu_ifc_dec_tlu_flush_noredir_wb, + output [31:0] io_tlu_ifc_dec_tlu_mrac_ff, + input io_tlu_ifc_ifu_pmu_fetch_stall, + output io_tlu_mem_dec_tlu_flush_err_wb, + output io_tlu_mem_dec_tlu_i0_commit_cmt, + output io_tlu_mem_dec_tlu_force_halt, + output io_tlu_mem_dec_tlu_fence_i_wb, + output [70:0] io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata, + output [16:0] io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics, + output io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid, + output io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid, + output io_tlu_mem_dec_tlu_core_ecc_disable, + input io_tlu_mem_ifu_pmu_ic_miss, + input io_tlu_mem_ifu_pmu_ic_hit, + input io_tlu_mem_ifu_pmu_bus_error, + input io_tlu_mem_ifu_pmu_bus_busy, + input io_tlu_mem_ifu_pmu_bus_trxn, + input io_tlu_mem_ifu_ic_error_start, + input io_tlu_mem_ifu_iccm_rd_ecc_single_err, + input [70:0] io_tlu_mem_ifu_ic_debug_rd_data, + input io_tlu_mem_ifu_ic_debug_rd_data_valid, + input io_tlu_mem_ifu_miss_state_idle, + input io_tlu_busbuff_lsu_pmu_bus_trxn, + input io_tlu_busbuff_lsu_pmu_bus_misaligned, + input io_tlu_busbuff_lsu_pmu_bus_error, + input io_tlu_busbuff_lsu_pmu_bus_busy, + output io_tlu_busbuff_dec_tlu_external_ldfwd_disable, + output io_tlu_busbuff_dec_tlu_wb_coalescing_disable, + output io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, + input io_tlu_busbuff_lsu_imprecise_error_load_any, + input io_tlu_busbuff_lsu_imprecise_error_store_any, + input [31:0] io_tlu_busbuff_lsu_imprecise_error_addr_any, + input io_lsu_tlu_lsu_pmu_load_external_m, + input io_lsu_tlu_lsu_pmu_store_external_m, + input [7:0] io_dec_pic_pic_claimid, + input [3:0] io_dec_pic_pic_pl, + input io_dec_pic_mhwakeup, + output [3:0] io_dec_pic_dec_tlu_meicurpl, + output [3:0] io_dec_pic_dec_tlu_meipt, + input io_dec_pic_mexintpend +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; +`endif // RANDOMIZE_REG_INIT + wire int_exc_clock; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_reset; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_mhwakeup_ready; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_ext_int_ready; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_ce_int_ready; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_soft_int_ready; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_timer_int_ready; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_int_timer0_int_hold; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_int_timer1_int_hold; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_ext_int_start; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_ext_int_start_d2; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_ext_int_freeze; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_ext_int; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_fast_int_meicpct; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_ignore_ext_int_due_to_lsu_stall; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_ce_int; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_soft_int; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_timer_int; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_reset; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_nmi; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_synchronous_flush_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dec_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_dec_tlu_flush_path_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 282:29] + wire [4:0] int_exc_io_exc_cause_wb; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_i0_valid_wb; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_trigger_hit_r_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_nmi_r_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 282:29] + wire [4:0] int_exc_io_exc_cause_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dec_csr_stall_int_ff; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 282:29] + wire [5:0] int_exc_io_mip; // @[dec_tlu_ctl.scala 282:29] + wire [5:0] int_exc_io_mie_ns; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_mret_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dcsr_single_step_running; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 282:29] + wire [1:0] int_exc_io_lsu_fir_error; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_lsu_fastint_stall_any; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_reset_delayed; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_nmi_int_detected; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 282:29] + wire [15:0] int_exc_io_dcsr; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_mtvec; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_pause_expired_r; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_nmi_vec; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_fence_i_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_rfpc_i0_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_take_halt; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_rst_vec; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_lsu_fir_addr; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_npc_r; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_mepc; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_debug_resume_req_f; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_dpc; // @[dec_tlu_ctl.scala 282:29] + wire [30:0] int_exc_io_npc_r_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_ebreak_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_ecall_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_illegal_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_inst_acc_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 282:29] + wire int_exc_io_dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 282:29] + wire csr_clock; // @[dec_tlu_ctl.scala 283:23] + wire csr_reset; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_free_l2clk; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_free_clk; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 283:23] + wire [11:0] csr_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 283:23] + wire [11:0] csr_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 283:23] + wire [70:0] csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 283:23] + wire [16:0] csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 283:23] + wire [1:0] csr_io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 283:23] + wire [3:0] csr_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 283:23] + wire [4:0] csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dma_pmu_any_write; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dma_pmu_any_read; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 283:23] + wire [30:0] csr_io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_picio_clk_override; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_ifu_clk_override; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 283:23] + wire [70:0] csr_io_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 283:23] + wire [3:0] csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 283:23] + wire [3:0] csr_io_pic_pl; // @[dec_tlu_ctl.scala 283:23] + wire [3:0] csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 283:23] + wire [29:0] csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 283:23] + wire [7:0] csr_io_pic_claimid; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 283:23] + wire [2:0] csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_trace_disable; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_dec_illegal_inst; // @[dec_tlu_ctl.scala 283:23] + wire [3:0] csr_io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_mexintpend; // @[dec_tlu_ctl.scala 283:23] + wire [30:0] csr_io_exu_npc_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 283:23] + wire [30:0] csr_io_rst_vec; // @[dec_tlu_ctl.scala 283:23] + wire [27:0] csr_io_core_id; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_rfpc_i0_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 283:23] + wire [1:0] csr_io_mstatus; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_mret_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 283:23] + wire [15:0] csr_io_dcsr; // @[dec_tlu_ctl.scala 283:23] + wire [30:0] csr_io_mtvec; // @[dec_tlu_ctl.scala 283:23] + wire [5:0] csr_io_mip; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_timer_int_sync; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_soft_int_sync; // @[dec_tlu_ctl.scala 283:23] + wire [5:0] csr_io_mie_ns; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_wr_clk; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 283:23] + wire [1:0] csr_io_lsu_fir_error; // @[dec_tlu_ctl.scala 283:23] + wire [30:0] csr_io_npc_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 283:23] + wire [30:0] csr_io_tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 283:23] + wire [30:0] csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_reset_delayed; // @[dec_tlu_ctl.scala 283:23] + wire [30:0] csr_io_mepc; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_single_ecc_error_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_e4e5_int_clk; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_inst_acc_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_inst_acc_second_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_take_nmi; // @[dec_tlu_ctl.scala 283:23] + wire [31:0] csr_io_lsu_error_pkt_addr_r; // @[dec_tlu_ctl.scala 283:23] + wire [4:0] csr_io_exc_cause_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_i0_valid_wb; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 283:23] + wire [4:0] csr_io_exc_cause_wb; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ebreak_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ecall_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_illegal_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_mdseac_locked_ns; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ext_int_freeze; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_take_ext_int_start_d2; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ic_perr_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_iccm_sbecc_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_debug_halt_req_f; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_force_halt; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_take_ext_int_start; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_trigger_hit_r_d1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_debug_halt_req; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_allow_dbg_halt_csr_write; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_enter_debug_halt_req; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_request_debug_mode_done; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_request_debug_mode_r; // @[dec_tlu_ctl.scala 283:23] + wire [30:0] csr_io_dpc; // @[dec_tlu_ctl.scala 283:23] + wire [3:0] csr_io_update_hit_bit_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_take_timer_int; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_take_ext_int; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_br0_error_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 283:23] + wire csr_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 283:23] + wire [9:0] csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 283:23] + wire [9:0] csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 283:23] + wire [9:0] csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 283:23] + wire [9:0] csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 283:23] + wire [3:0] csr_io_trigger_enabled; // @[dec_tlu_ctl.scala 283:23] + wire int_timers_clock; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_reset; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_free_l2clk; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_csr_wr_clk; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 284:30] + wire [11:0] int_timers_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 284:30] + wire [31:0] int_timers_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_csr_mitctl0; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_csr_mitctl1; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_csr_mitb0; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_csr_mitb1; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_csr_mitcnt0; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_csr_mitcnt1; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_dec_pause_state; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 284:30] + wire [31:0] int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 284:30] + wire int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 284:30] + wire [11:0] csr_read_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 1017:28] + wire csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 1017:28] + reg dbg_halt_state_f; // @[Reg.scala 27:20] + wire _T = ~dbg_halt_state_f; // @[dec_tlu_ctl.scala 281:39] + reg mpc_halt_state_f; // @[Reg.scala 27:20] + wire _T_1 = _T & mpc_halt_state_f; // @[dec_tlu_ctl.scala 281:57] + wire [2:0] _T_3 = {io_i_cpu_run_req,io_mpc_debug_halt_req,io_mpc_debug_run_req}; // @[Cat.scala 29:58] + wire [3:0] _T_6 = {io_nmi_int,io_timer_int,io_soft_int,io_i_cpu_halt_req}; // @[Cat.scala 29:58] + reg [6:0] _T_8; // @[lib.scala 37:81] + reg [6:0] syncro_ff; // @[lib.scala 37:58] + wire nmi_int_sync = syncro_ff[6]; // @[dec_tlu_ctl.scala 311:75] + wire i_cpu_halt_req_sync = syncro_ff[3]; // @[dec_tlu_ctl.scala 314:59] + wire i_cpu_run_req_sync = syncro_ff[2]; // @[dec_tlu_ctl.scala 315:59] + wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[dec_tlu_ctl.scala 316:51] + wire mpc_debug_run_req_sync = syncro_ff[0]; // @[dec_tlu_ctl.scala 317:59] + wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 1010:37] + reg debug_mode_status; // @[Reg.scala 27:20] + reg i_cpu_run_req_d1_raw; // @[Reg.scala 27:20] + reg nmi_int_delayed; // @[Reg.scala 27:20] + wire _T_76 = ~nmi_int_delayed; // @[dec_tlu_ctl.scala 360:45] + wire _T_77 = nmi_int_sync & _T_76; // @[dec_tlu_ctl.scala 360:43] + wire mdseac_locked_f = csr_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 965:27] + wire _T_72 = ~mdseac_locked_f; // @[dec_tlu_ctl.scala 357:32] + wire _T_73 = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 357:96] + wire _T_74 = _T_72 & _T_73; // @[dec_tlu_ctl.scala 357:49] + reg nmi_int_detected_f; // @[Reg.scala 27:20] + wire _T_99 = ~nmi_int_detected_f; // @[dec_tlu_ctl.scala 365:25] + wire _T_100 = _T_99 & csr_io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 365:45] + wire _T_101 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 365:95] + wire nmi_fir_type = _T_100 & _T_101; // @[dec_tlu_ctl.scala 365:76] + wire _T_75 = ~nmi_fir_type; // @[dec_tlu_ctl.scala 357:146] + wire nmi_lsu_detected = _T_74 & _T_75; // @[dec_tlu_ctl.scala 357:144] + wire _T_78 = _T_77 | nmi_lsu_detected; // @[dec_tlu_ctl.scala 360:63] + wire take_nmi_r_d1 = int_exc_io_take_nmi_r_d1; // @[dec_tlu_ctl.scala 814:43] + wire _T_79 = ~take_nmi_r_d1; // @[dec_tlu_ctl.scala 360:106] + wire _T_80 = nmi_int_detected_f & _T_79; // @[dec_tlu_ctl.scala 360:104] + wire _T_81 = _T_78 | _T_80; // @[dec_tlu_ctl.scala 360:82] + wire nmi_int_detected = _T_81 | nmi_fir_type; // @[dec_tlu_ctl.scala 360:122] + wire timer_int_ready = int_exc_io_timer_int_ready; // @[dec_tlu_ctl.scala 784:43] + wire _T_576 = nmi_int_detected | timer_int_ready; // @[dec_tlu_ctl.scala 633:71] + wire soft_int_ready = int_exc_io_soft_int_ready; // @[dec_tlu_ctl.scala 783:43] + wire _T_577 = _T_576 | soft_int_ready; // @[dec_tlu_ctl.scala 633:89] + reg int_timer0_int_hold_f; // @[Reg.scala 27:20] + wire _T_578 = _T_577 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 633:106] + reg int_timer1_int_hold_f; // @[Reg.scala 27:20] + wire _T_579 = _T_578 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 633:130] + wire mhwakeup_ready = int_exc_io_mhwakeup_ready; // @[dec_tlu_ctl.scala 780:43] + wire _T_580 = io_dec_pic_mhwakeup & mhwakeup_ready; // @[dec_tlu_ctl.scala 633:177] + wire _T_581 = _T_579 | _T_580; // @[dec_tlu_ctl.scala 633:154] + wire _T_582 = _T_581 & io_o_cpu_halt_status; // @[dec_tlu_ctl.scala 633:196] + reg i_cpu_halt_req_d1; // @[Reg.scala 27:20] + wire _T_583 = ~i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 633:221] + wire _T_584 = _T_582 & _T_583; // @[dec_tlu_ctl.scala 633:219] + wire i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_584; // @[dec_tlu_ctl.scala 633:50] + wire interrupt_valid_r = int_exc_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 816:43] + wire interrupt_valid_r_d1 = int_exc_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 812:43] + reg reset_detect; // @[Reg.scala 27:20] + reg reset_detected; // @[Reg.scala 27:20] + wire reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 369:64] + wire _T_345 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 504:28] + reg dec_pause_state_f; // @[Reg.scala 27:20] + wire _T_346 = _T_345 & dec_pause_state_f; // @[dec_tlu_ctl.scala 504:48] + wire ext_int_ready = int_exc_io_ext_int_ready; // @[dec_tlu_ctl.scala 781:43] + wire ce_int_ready = int_exc_io_ce_int_ready; // @[dec_tlu_ctl.scala 782:43] + wire _T_347 = ext_int_ready | ce_int_ready; // @[dec_tlu_ctl.scala 504:86] + wire _T_348 = _T_347 | timer_int_ready; // @[dec_tlu_ctl.scala 504:101] + wire _T_349 = _T_348 | soft_int_ready; // @[dec_tlu_ctl.scala 504:119] + wire _T_350 = _T_349 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 504:136] + wire _T_351 = _T_350 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 504:160] + wire _T_352 = _T_351 | nmi_int_detected; // @[dec_tlu_ctl.scala 504:184] + wire _T_353 = _T_352 | csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 504:203] + wire _T_354 = ~_T_353; // @[dec_tlu_ctl.scala 504:70] + wire _T_355 = _T_346 & _T_354; // @[dec_tlu_ctl.scala 504:68] + wire _T_356 = ~interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 504:233] + wire _T_357 = _T_355 & _T_356; // @[dec_tlu_ctl.scala 504:231] + reg debug_halt_req_f; // @[Reg.scala 27:20] + wire _T_358 = ~debug_halt_req_f; // @[dec_tlu_ctl.scala 504:257] + wire _T_359 = _T_357 & _T_358; // @[dec_tlu_ctl.scala 504:255] + reg pmu_fw_halt_req_f; // @[Reg.scala 27:20] + wire _T_360 = ~pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 504:277] + wire _T_361 = _T_359 & _T_360; // @[dec_tlu_ctl.scala 504:275] + reg halt_taken_f; // @[Reg.scala 27:20] + wire _T_362 = ~halt_taken_f; // @[dec_tlu_ctl.scala 504:298] + reg ifu_ic_error_start_f; // @[Reg.scala 27:20] + wire _T_680 = ~csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 709:49] + wire _T_681 = ifu_ic_error_start_f & _T_680; // @[dec_tlu_ctl.scala 709:47] + wire _T_682 = ~debug_mode_status; // @[dec_tlu_ctl.scala 709:78] + reg debug_resume_req_f_raw; // @[Reg.scala 27:20] + wire _T_333 = ~io_dbg_halt_req; // @[dec_tlu_ctl.scala 489:56] + wire debug_resume_req_f = debug_resume_req_f_raw & _T_333; // @[dec_tlu_ctl.scala 489:54] + wire [15:0] dcsr = csr_io_dcsr; // @[dec_tlu_ctl.scala 1013:37] + wire _T_255 = debug_resume_req_f & dcsr[2]; // @[dec_tlu_ctl.scala 459:60] + reg dcsr_single_step_running_f; // @[Reg.scala 27:20] + reg dcsr_single_step_done_f; // @[Reg.scala 27:20] + wire _T_256 = ~dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 459:111] + wire _T_257 = dcsr_single_step_running_f & _T_256; // @[dec_tlu_ctl.scala 459:109] + wire dcsr_single_step_running = _T_255 | _T_257; // @[dec_tlu_ctl.scala 459:79] + wire _T_683 = _T_682 | dcsr_single_step_running; // @[dec_tlu_ctl.scala 709:104] + wire _T_684 = _T_681 & _T_683; // @[dec_tlu_ctl.scala 709:75] + reg internal_pmu_fw_halt_mode_f; // @[Reg.scala 27:20] + wire _T_685 = ~internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 709:134] + wire ic_perr_r = _T_684 & _T_685; // @[dec_tlu_ctl.scala 709:132] + reg ifu_iccm_rd_ecc_single_err_f; // @[Reg.scala 27:20] + wire _T_688 = ifu_iccm_rd_ecc_single_err_f & _T_680; // @[dec_tlu_ctl.scala 710:55] + wire _T_691 = _T_688 & _T_683; // @[dec_tlu_ctl.scala 710:83] + wire iccm_sbecc_r = _T_691 & _T_685; // @[dec_tlu_ctl.scala 710:140] + wire _T_23 = io_tlu_mem_ifu_ic_error_start ^ ifu_ic_error_start_f; // @[lib.scala 470:21] + wire _T_24 = |_T_23; // @[lib.scala 470:29] + wire _T_26 = io_tlu_mem_ifu_iccm_rd_ecc_single_err ^ ifu_iccm_rd_ecc_single_err_f; // @[lib.scala 470:21] + wire _T_27 = |_T_26; // @[lib.scala 470:29] + reg iccm_repair_state_d1; // @[Reg.scala 27:20] + wire _T_623 = ~io_tlu_exu_dec_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 666:72] + wire _T_624 = iccm_repair_state_d1 & _T_623; // @[dec_tlu_ctl.scala 666:70] + wire iccm_repair_state_ns = iccm_sbecc_r | _T_624; // @[dec_tlu_ctl.scala 666:46] + wire _T_29 = iccm_repair_state_ns ^ iccm_repair_state_d1; // @[lib.scala 448:21] + wire _T_30 = |_T_29; // @[lib.scala 448:29] + reg dbg_halt_req_held; // @[Reg.scala 27:20] + wire _T_184 = io_dbg_halt_req | dbg_halt_req_held; // @[dec_tlu_ctl.scala 418:48] + wire dbg_halt_req_final = _T_184 & _T_680; // @[dec_tlu_ctl.scala 418:69] + wire mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & _T_680; // @[dec_tlu_ctl.scala 376:67] + wire _T_187 = dbg_halt_req_final | mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 421:50] + wire _T_188 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 421:95] + wire _T_189 = reset_delayed & _T_188; // @[dec_tlu_ctl.scala 421:93] + wire _T_190 = _T_187 | _T_189; // @[dec_tlu_ctl.scala 421:76] + wire _T_192 = _T_190 & _T_682; // @[dec_tlu_ctl.scala 421:119] + wire debug_halt_req = _T_192 & _T_680; // @[dec_tlu_ctl.scala 421:147] + wire _T_231 = _T_682 & debug_halt_req; // @[dec_tlu_ctl.scala 441:63] + wire _T_232 = _T_231 | dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 441:81] + reg trigger_hit_dmode_r_d1; // @[Reg.scala 27:20] + wire _T_233 = _T_232 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 441:107] + reg ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 718:64] + wire enter_debug_halt_req = _T_233 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 441:132] + wire force_halt = csr_io_force_halt; // @[dec_tlu_ctl.scala 1007:37] + reg lsu_idle_any_f; // @[Reg.scala 27:20] + wire _T_220 = io_lsu_idle_any & lsu_idle_any_f; // @[dec_tlu_ctl.scala 435:53] + wire _T_221 = _T_220 & io_tlu_mem_ifu_miss_state_idle; // @[dec_tlu_ctl.scala 435:70] + reg ifu_miss_state_idle_f; // @[Reg.scala 27:20] + wire _T_222 = _T_221 & ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 435:103] + wire _T_223 = ~debug_halt_req; // @[dec_tlu_ctl.scala 435:129] + wire _T_224 = _T_222 & _T_223; // @[dec_tlu_ctl.scala 435:127] + reg debug_halt_req_d1; // @[Reg.scala 27:20] + wire _T_225 = ~debug_halt_req_d1; // @[dec_tlu_ctl.scala 435:147] + wire _T_226 = _T_224 & _T_225; // @[dec_tlu_ctl.scala 435:145] + wire _T_227 = ~io_dec_div_active; // @[dec_tlu_ctl.scala 435:168] + wire _T_228 = _T_226 & _T_227; // @[dec_tlu_ctl.scala 435:166] + wire core_empty = force_halt | _T_228; // @[dec_tlu_ctl.scala 435:34] + wire _T_241 = debug_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 452:48] + reg dec_tlu_flush_noredir_r_d1; // @[Reg.scala 27:20] + reg dec_tlu_flush_pause_r_d1; // @[Reg.scala 27:20] + wire _T_210 = ~dec_tlu_flush_pause_r_d1; // @[dec_tlu_ctl.scala 431:56] + wire _T_211 = dec_tlu_flush_noredir_r_d1 & _T_210; // @[dec_tlu_ctl.scala 431:54] + wire _T_212 = ~csr_io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 431:84] + wire _T_213 = _T_211 & _T_212; // @[dec_tlu_ctl.scala 431:82] + reg dbg_tlu_halted_f; // @[Reg.scala 27:20] + wire _T_214 = ~dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 431:133] + wire _T_215 = halt_taken_f & _T_214; // @[dec_tlu_ctl.scala 431:131] + reg pmu_fw_tlu_halted_f; // @[Reg.scala 27:20] + wire _T_216 = ~pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 431:153] + wire _T_217 = _T_215 & _T_216; // @[dec_tlu_ctl.scala 431:151] + wire _T_219 = _T_217 & _T_356; // @[dec_tlu_ctl.scala 431:174] + wire halt_taken = _T_213 | _T_219; // @[dec_tlu_ctl.scala 431:115] + wire _T_242 = _T_241 & halt_taken; // @[dec_tlu_ctl.scala 452:61] + wire _T_243 = ~debug_resume_req_f; // @[dec_tlu_ctl.scala 452:97] + wire _T_244 = dbg_tlu_halted_f & _T_243; // @[dec_tlu_ctl.scala 452:95] + wire dbg_tlu_halted = _T_242 | _T_244; // @[dec_tlu_ctl.scala 452:75] + wire _T_245 = ~dbg_tlu_halted; // @[dec_tlu_ctl.scala 454:73] + wire _T_246 = debug_halt_req_f & _T_245; // @[dec_tlu_ctl.scala 454:71] + wire debug_halt_req_ns = enter_debug_halt_req | _T_246; // @[dec_tlu_ctl.scala 454:51] + wire _T_235 = ~dcsr[2]; // @[dec_tlu_ctl.scala 444:106] + wire _T_236 = debug_resume_req_f & _T_235; // @[dec_tlu_ctl.scala 444:104] + wire _T_237 = ~_T_236; // @[dec_tlu_ctl.scala 444:83] + wire _T_238 = debug_mode_status & _T_237; // @[dec_tlu_ctl.scala 444:81] + wire internal_dbg_halt_mode = debug_halt_req_ns | _T_238; // @[dec_tlu_ctl.scala 444:53] + wire _T_37 = internal_dbg_halt_mode ^ debug_mode_status; // @[lib.scala 448:21] + wire _T_38 = |_T_37; // @[lib.scala 448:29] + reg lsu_pmu_load_external_r; // @[Reg.scala 27:20] + wire _T_40 = io_lsu_tlu_lsu_pmu_load_external_m ^ lsu_pmu_load_external_r; // @[lib.scala 470:21] + wire _T_41 = |_T_40; // @[lib.scala 470:29] + reg lsu_pmu_store_external_r; // @[Reg.scala 27:20] + wire _T_43 = io_lsu_tlu_lsu_pmu_store_external_m ^ lsu_pmu_store_external_r; // @[lib.scala 470:21] + wire _T_44 = |_T_43; // @[lib.scala 470:29] + wire tlu_flush_lower_r = int_exc_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 808:43] + reg tlu_flush_lower_r_d1; // @[Reg.scala 27:20] + wire _T_46 = tlu_flush_lower_r ^ tlu_flush_lower_r_d1; // @[lib.scala 448:21] + wire _T_47 = |_T_46; // @[lib.scala 448:29] + wire _T_611 = ~tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 663:49] + wire _T_612 = io_dec_tlu_i0_valid_r & _T_611; // @[dec_tlu_ctl.scala 663:47] + wire _T_613 = io_tlu_exu_exu_i0_br_error_r | io_tlu_exu_exu_i0_br_start_error_r; // @[dec_tlu_ctl.scala 663:103] + wire _T_614 = _T_612 & _T_613; // @[dec_tlu_ctl.scala 663:71] + wire _T_615 = ic_perr_r | iccm_sbecc_r; // @[dec_tlu_ctl.scala 663:156] + wire _T_617 = _T_615 & _T_680; // @[dec_tlu_ctl.scala 663:172] + wire _T_618 = _T_614 | _T_617; // @[dec_tlu_ctl.scala 663:142] + wire _T_431 = io_dec_tlu_flush_lower_wb | io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 545:64] + wire [3:0] _T_433 = _T_431 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_434 = ~_T_433; // @[dec_tlu_ctl.scala 545:29] + wire [3:0] _T_426 = io_dec_tlu_i0_valid_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_428 = _T_426 & io_dec_tlu_packet_r_i0trigger; // @[dec_tlu_ctl.scala 543:58] + wire [9:0] mtdata1_t_3 = csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 162:67 dec_tlu_ctl.scala 1016:39] + wire [9:0] mtdata1_t_2 = csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 162:67 dec_tlu_ctl.scala 1016:39] + wire [9:0] mtdata1_t_1 = csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 162:67 dec_tlu_ctl.scala 1016:39] + wire [9:0] mtdata1_t_0 = csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 162:67 dec_tlu_ctl.scala 1016:39] + wire [3:0] trigger_execute = {mtdata1_t_3[2],mtdata1_t_2[2],mtdata1_t_1[2],mtdata1_t_0[2]}; // @[Cat.scala 29:58] + wire [3:0] trigger_data = {mtdata1_t_3[7],mtdata1_t_2[7],mtdata1_t_1[7],mtdata1_t_0[7]}; // @[Cat.scala 29:58] + wire [3:0] _T_413 = trigger_execute & trigger_data; // @[dec_tlu_ctl.scala 535:62] + wire inst_acc_r_raw = io_dec_tlu_packet_r_icaf & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 712:54] + wire [3:0] _T_415 = inst_acc_r_raw ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_416 = _T_413 & _T_415; // @[dec_tlu_ctl.scala 535:77] + wire [3:0] _T_419 = _T_613 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_420 = _T_416 | _T_419; // @[dec_tlu_ctl.scala 535:103] + wire [3:0] i0_iside_trigger_has_pri_r = ~_T_420; // @[dec_tlu_ctl.scala 535:43] + wire [3:0] _T_429 = _T_428 & i0_iside_trigger_has_pri_r; // @[dec_tlu_ctl.scala 543:95] + wire [3:0] trigger_store = {mtdata1_t_3[1],mtdata1_t_2[1],mtdata1_t_1[1],mtdata1_t_0[1]}; // @[Cat.scala 29:58] + wire [3:0] _T_421 = trigger_store & trigger_data; // @[dec_tlu_ctl.scala 538:56] + wire [3:0] _T_423 = io_lsu_error_pkt_r_valid ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_424 = _T_421 & _T_423; // @[dec_tlu_ctl.scala 538:71] + wire [3:0] i0_lsu_trigger_has_pri_r = ~_T_424; // @[dec_tlu_ctl.scala 538:40] + wire [3:0] _T_430 = _T_429 & i0_lsu_trigger_has_pri_r; // @[dec_tlu_ctl.scala 543:124] + wire [1:0] mstatus = csr_io_mstatus; // @[dec_tlu_ctl.scala 1012:37] + wire _T_393 = mtdata1_t_3[6] | mstatus[0]; // @[dec_tlu_ctl.scala 529:70] + wire _T_395 = _T_393 & mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 529:94] + wire _T_398 = mtdata1_t_2[6] | mstatus[0]; // @[dec_tlu_ctl.scala 530:47] + wire _T_400 = _T_398 & mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 530:71] + wire [1:0] _T_412 = {_T_395,_T_400}; // @[Cat.scala 29:58] + wire _T_403 = mtdata1_t_1[6] | mstatus[0]; // @[dec_tlu_ctl.scala 531:47] + wire _T_405 = _T_403 & mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 531:71] + wire _T_408 = mtdata1_t_0[6] | mstatus[0]; // @[dec_tlu_ctl.scala 532:47] + wire _T_410 = _T_408 & mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 532:71] + wire [1:0] _T_411 = {_T_405,_T_410}; // @[Cat.scala 29:58] + wire [3:0] trigger_enabled = {_T_395,_T_400,_T_405,_T_410}; // @[Cat.scala 29:58] + wire [3:0] i0trigger_qual_r = _T_430 & trigger_enabled; // @[dec_tlu_ctl.scala 543:151] + wire [3:0] i0_trigger_r = _T_434 & i0trigger_qual_r; // @[dec_tlu_ctl.scala 545:90] + wire _T_437 = ~mtdata1_t_2[5]; // @[dec_tlu_ctl.scala 548:65] + wire _T_439 = _T_437 | i0_trigger_r[2]; // @[dec_tlu_ctl.scala 548:94] + wire _T_440 = i0_trigger_r[3] & _T_439; // @[dec_tlu_ctl.scala 548:62] + wire _T_445 = _T_437 | i0_trigger_r[3]; // @[dec_tlu_ctl.scala 549:65] + wire _T_446 = i0_trigger_r[2] & _T_445; // @[dec_tlu_ctl.scala 549:33] + wire _T_449 = ~mtdata1_t_0[5]; // @[dec_tlu_ctl.scala 550:36] + wire _T_451 = _T_449 | i0_trigger_r[0]; // @[dec_tlu_ctl.scala 550:65] + wire _T_452 = i0_trigger_r[1] & _T_451; // @[dec_tlu_ctl.scala 550:33] + wire _T_457 = _T_449 | i0_trigger_r[1]; // @[dec_tlu_ctl.scala 551:65] + wire _T_458 = i0_trigger_r[0] & _T_457; // @[dec_tlu_ctl.scala 551:33] + wire [3:0] i0_trigger_chain_masked_r = {_T_440,_T_446,_T_452,_T_458}; // @[Cat.scala 29:58] + wire i0_trigger_hit_raw_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 555:62] + wire _T_619 = ~i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 663:205] + wire _T_620 = _T_618 & _T_619; // @[dec_tlu_ctl.scala 663:202] + wire _T_592 = io_dec_tlu_i0_valid_r & _T_619; // @[dec_tlu_ctl.scala 651:52] + wire _T_593 = ~io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 651:75] + wire _T_594 = _T_593 & io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec_tlu_ctl.scala 651:110] + wire lsu_i0_rfnpc_r = _T_592 & _T_594; // @[dec_tlu_ctl.scala 651:72] + wire _T_621 = ~lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 663:226] + wire rfpc_i0_r = _T_620 & _T_621; // @[dec_tlu_ctl.scala 663:223] + wire _T_586 = ~io_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 642:62] + wire lsu_exc_valid_r_raw = io_lsu_error_pkt_r_valid & _T_586; // @[dec_tlu_ctl.scala 642:60] + wire _T_587 = io_lsu_error_pkt_r_valid & lsu_exc_valid_r_raw; // @[dec_tlu_ctl.scala 644:45] + wire _T_589 = _T_587 & _T_619; // @[dec_tlu_ctl.scala 644:67] + wire _T_590 = ~rfpc_i0_r; // @[dec_tlu_ctl.scala 644:89] + wire lsu_exc_valid_r = _T_589 & _T_590; // @[dec_tlu_ctl.scala 644:87] + wire _T_606 = rfpc_i0_r | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 657:43] + wire _T_696 = inst_acc_r_raw & _T_590; // @[dec_tlu_ctl.scala 713:38] + wire inst_acc_r = _T_696 & _T_619; // @[dec_tlu_ctl.scala 713:51] + wire _T_607 = _T_606 | inst_acc_r; // @[dec_tlu_ctl.scala 657:58] + wire _T_663 = ~io_dec_tlu_packet_r_legal; // @[dec_tlu_ctl.scala 705:23] + wire _T_664 = _T_663 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 705:52] + wire _T_666 = _T_664 & _T_619; // @[dec_tlu_ctl.scala 705:76] + wire illegal_r = _T_666 & _T_590; // @[dec_tlu_ctl.scala 705:96] + wire _T_608 = illegal_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 657:84] + wire _T_609 = _T_607 | _T_608; // @[dec_tlu_ctl.scala 657:71] + wire tlu_i0_kill_writeb_r = _T_609 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 657:109] + reg _T_52; // @[Reg.scala 27:20] + wire _T_50 = tlu_i0_kill_writeb_r ^ _T_52; // @[lib.scala 448:21] + wire _T_51 = |_T_50; // @[lib.scala 448:29] + reg internal_dbg_halt_mode_f2; // @[Reg.scala 27:20] + wire _T_53 = debug_mode_status ^ internal_dbg_halt_mode_f2; // @[lib.scala 448:21] + wire _T_54 = |_T_53; // @[lib.scala 448:29] + reg _T_59; // @[Reg.scala 27:20] + wire _T_57 = force_halt ^ _T_59; // @[lib.scala 448:21] + wire _T_58 = |_T_57; // @[lib.scala 448:29] + wire _T_60 = nmi_int_sync ^ nmi_int_delayed; // @[lib.scala 470:21] + wire _T_61 = |_T_60; // @[lib.scala 470:29] + wire _T_63 = nmi_int_detected ^ nmi_int_detected_f; // @[lib.scala 448:21] + wire _T_64 = |_T_63; // @[lib.scala 448:29] + wire _T_83 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 362:49] + wire _T_86 = ~_T_80; // @[dec_tlu_ctl.scala 362:98] + wire _T_87 = _T_83 & _T_86; // @[dec_tlu_ctl.scala 362:95] + reg nmi_lsu_load_type_f; // @[Reg.scala 27:20] + wire _T_89 = nmi_lsu_load_type_f & _T_79; // @[dec_tlu_ctl.scala 362:162] + wire nmi_lsu_load_type = _T_87 | _T_89; // @[dec_tlu_ctl.scala 362:138] + wire _T_66 = nmi_lsu_load_type ^ nmi_lsu_load_type_f; // @[lib.scala 448:21] + wire _T_67 = |_T_66; // @[lib.scala 448:29] + wire _T_91 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 363:49] + wire _T_95 = _T_91 & _T_86; // @[dec_tlu_ctl.scala 363:96] + reg nmi_lsu_store_type_f; // @[Reg.scala 27:20] + wire _T_97 = nmi_lsu_store_type_f & _T_79; // @[dec_tlu_ctl.scala 363:162] + wire nmi_lsu_store_type = _T_95 | _T_97; // @[dec_tlu_ctl.scala 363:138] + wire _T_69 = nmi_lsu_store_type ^ nmi_lsu_store_type_f; // @[lib.scala 448:21] + wire _T_70 = |_T_69; // @[lib.scala 448:29] + wire _T_103 = 1'h1 ^ reset_detect; // @[lib.scala 448:21] + wire _T_104 = |_T_103; // @[lib.scala 448:29] + wire _T_107 = |reset_delayed; // @[lib.scala 448:29] + reg mpc_debug_halt_req_sync_f; // @[Reg.scala 27:20] + wire _T_111 = mpc_debug_halt_req_sync ^ mpc_debug_halt_req_sync_f; // @[lib.scala 470:21] + wire _T_112 = |_T_111; // @[lib.scala 470:29] + reg mpc_debug_run_req_sync_f; // @[Reg.scala 27:20] + wire _T_114 = mpc_debug_run_req_sync ^ mpc_debug_run_req_sync_f; // @[lib.scala 470:21] + wire _T_115 = |_T_114; // @[lib.scala 470:29] + wire _T_144 = ~mpc_debug_halt_req_sync_f; // @[dec_tlu_ctl.scala 390:71] + wire mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & _T_144; // @[dec_tlu_ctl.scala 390:69] + wire _T_146 = mpc_halt_state_f | mpc_debug_halt_req_sync_pulse; // @[dec_tlu_ctl.scala 393:48] + wire _T_149 = _T_146 | _T_189; // @[dec_tlu_ctl.scala 393:80] + wire _T_150 = ~mpc_debug_run_req_sync; // @[dec_tlu_ctl.scala 393:125] + wire mpc_halt_state_ns = _T_149 & _T_150; // @[dec_tlu_ctl.scala 393:123] + wire _T_118 = mpc_halt_state_ns ^ mpc_halt_state_f; // @[lib.scala 448:21] + wire _T_119 = |_T_118; // @[lib.scala 448:29] + reg mpc_run_state_f; // @[Reg.scala 27:20] + wire _T_145 = ~mpc_debug_run_req_sync_f; // @[dec_tlu_ctl.scala 391:70] + wire mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & _T_145; // @[dec_tlu_ctl.scala 391:68] + reg mpc_debug_run_ack_f; // @[Reg.scala 27:20] + wire _T_152 = ~mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 394:80] + wire _T_153 = mpc_debug_run_req_sync_pulse & _T_152; // @[dec_tlu_ctl.scala 394:78] + wire _T_154 = mpc_run_state_f | _T_153; // @[dec_tlu_ctl.scala 394:46] + wire _T_155 = ~dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 394:133] + wire _T_156 = debug_mode_status & _T_155; // @[dec_tlu_ctl.scala 394:131] + wire mpc_run_state_ns = _T_154 & _T_156; // @[dec_tlu_ctl.scala 394:103] + wire _T_121 = mpc_run_state_ns ^ mpc_run_state_f; // @[lib.scala 448:21] + wire _T_122 = |_T_121; // @[lib.scala 448:29] + wire debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 404:59] + reg debug_brkpt_status_f; // @[Reg.scala 27:20] + wire _T_170 = debug_brkpt_valid | debug_brkpt_status_f; // @[dec_tlu_ctl.scala 405:53] + wire _T_172 = internal_dbg_halt_mode & _T_155; // @[dec_tlu_ctl.scala 405:103] + wire debug_brkpt_status_ns = _T_170 & _T_172; // @[dec_tlu_ctl.scala 405:77] + wire _T_124 = debug_brkpt_status_ns ^ debug_brkpt_status_f; // @[lib.scala 448:21] + wire _T_125 = |_T_124; // @[lib.scala 448:29] + wire _T_174 = mpc_halt_state_f & debug_mode_status; // @[dec_tlu_ctl.scala 408:51] + wire _T_175 = _T_174 & mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 408:78] + wire mpc_debug_halt_ack_ns = _T_175 & core_empty; // @[dec_tlu_ctl.scala 408:104] + reg mpc_debug_halt_ack_f; // @[Reg.scala 27:20] + wire _T_127 = mpc_debug_halt_ack_ns ^ mpc_debug_halt_ack_f; // @[lib.scala 448:21] + wire _T_128 = |_T_127; // @[lib.scala 448:29] + wire _T_158 = dbg_halt_req_final | dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 397:70] + wire _T_159 = _T_158 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 397:96] + wire _T_160 = _T_159 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 397:121] + wire _T_161 = dbg_halt_state_f | _T_160; // @[dec_tlu_ctl.scala 397:48] + wire _T_162 = ~io_dbg_resume_req; // @[dec_tlu_ctl.scala 397:153] + wire dbg_halt_state_ns = _T_161 & _T_162; // @[dec_tlu_ctl.scala 397:151] + wire _T_177 = ~dbg_halt_state_ns; // @[dec_tlu_ctl.scala 409:59] + wire _T_178 = mpc_debug_run_req_sync & _T_177; // @[dec_tlu_ctl.scala 409:57] + wire _T_179 = ~mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 409:80] + wire _T_180 = _T_178 & _T_179; // @[dec_tlu_ctl.scala 409:78] + wire _T_181 = mpc_debug_run_ack_f & mpc_debug_run_req_sync; // @[dec_tlu_ctl.scala 409:129] + wire mpc_debug_run_ack_ns = _T_180 | _T_181; // @[dec_tlu_ctl.scala 409:106] + wire _T_130 = mpc_debug_run_ack_ns ^ mpc_debug_run_ack_f; // @[lib.scala 448:21] + wire _T_131 = |_T_130; // @[lib.scala 448:29] + wire _T_134 = dbg_halt_state_ns ^ dbg_halt_state_f; // @[lib.scala 448:21] + wire _T_135 = |_T_134; // @[lib.scala 448:29] + reg dbg_run_state_f; // @[Reg.scala 27:20] + wire _T_164 = dbg_run_state_f | io_dbg_resume_req; // @[dec_tlu_ctl.scala 398:46] + wire dbg_run_state_ns = _T_164 & _T_156; // @[dec_tlu_ctl.scala 398:67] + wire _T_137 = dbg_run_state_ns ^ dbg_run_state_f; // @[lib.scala 448:21] + wire _T_138 = |_T_137; // @[lib.scala 448:29] + reg _T_143; // @[Reg.scala 27:20] + wire _T_141 = _T_1 ^ _T_143; // @[lib.scala 448:21] + wire _T_142 = |_T_141; // @[lib.scala 448:29] + wire dbg_halt_req_held_ns = _T_184 & csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 417:74] + wire _T_196 = mpc_run_state_ns & _T_177; // @[dec_tlu_ctl.scala 423:73] + wire _T_197 = ~mpc_halt_state_ns; // @[dec_tlu_ctl.scala 423:117] + wire _T_198 = dbg_run_state_ns & _T_197; // @[dec_tlu_ctl.scala 423:115] + wire _T_199 = _T_196 | _T_198; // @[dec_tlu_ctl.scala 423:95] + wire debug_resume_req = _T_243 & _T_199; // @[dec_tlu_ctl.scala 423:52] + wire _T_200 = debug_halt_req_f | pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 428:43] + wire synchronous_flush_r = int_exc_io_synchronous_flush_r; // @[dec_tlu_ctl.scala 807:43] + wire _T_201 = ~synchronous_flush_r; // @[dec_tlu_ctl.scala 428:66] + wire _T_202 = _T_200 & _T_201; // @[dec_tlu_ctl.scala 428:64] + wire _T_669 = io_dec_tlu_packet_r_pmu_i0_itype == 4'hc; // @[dec_tlu_ctl.scala 706:57] + wire _T_670 = _T_669 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 706:70] + wire _T_672 = _T_670 & _T_619; // @[dec_tlu_ctl.scala 706:94] + wire mret_r = _T_672 & _T_590; // @[dec_tlu_ctl.scala 706:114] + wire _T_203 = ~mret_r; // @[dec_tlu_ctl.scala 428:89] + wire _T_204 = _T_202 & _T_203; // @[dec_tlu_ctl.scala 428:87] + wire _T_206 = _T_204 & _T_362; // @[dec_tlu_ctl.scala 428:97] + wire _T_207 = ~dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 428:115] + wire _T_208 = _T_206 & _T_207; // @[dec_tlu_ctl.scala 428:113] + wire take_reset = int_exc_io_take_reset; // @[dec_tlu_ctl.scala 805:43] + wire _T_209 = ~take_reset; // @[dec_tlu_ctl.scala 428:145] + wire take_halt = _T_208 & _T_209; // @[dec_tlu_ctl.scala 428:143] + wire _T_248 = debug_resume_req_f & dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 455:49] + wire resume_ack_ns = _T_248 & dbg_run_state_ns; // @[dec_tlu_ctl.scala 455:68] + wire _T_249 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 457:61] + wire _T_250 = io_dec_tlu_i0_valid_r & _T_249; // @[dec_tlu_ctl.scala 457:59] + wire _T_252 = _T_250 & dcsr[2]; // @[dec_tlu_ctl.scala 457:84] + wire dcsr_single_step_done = _T_252 & _T_590; // @[dec_tlu_ctl.scala 457:102] + wire _T_463 = mtdata1_t_3[6] & mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 561:69] + wire _T_466 = mtdata1_t_2[6] & mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 562:46] + wire _T_469 = _T_466 & _T_437; // @[dec_tlu_ctl.scala 562:76] + wire _T_472 = mtdata1_t_1[6] & mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 563:46] + wire _T_475 = mtdata1_t_0[6] & mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 564:46] + wire _T_478 = _T_475 & _T_449; // @[dec_tlu_ctl.scala 564:76] + wire [3:0] trigger_action = {_T_463,_T_469,_T_472,_T_478}; // @[Cat.scala 29:58] + wire [3:0] _T_493 = i0_trigger_chain_masked_r & trigger_action; // @[dec_tlu_ctl.scala 570:62] + wire i0_trigger_action_r = |_T_493; // @[dec_tlu_ctl.scala 570:80] + wire trigger_hit_dmode_r = i0_trigger_hit_raw_r & i0_trigger_action_r; // @[dec_tlu_ctl.scala 572:50] + wire _T_699 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h8; // @[dec_tlu_ctl.scala 716:69] + wire _T_700 = _T_699 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 716:82] + wire _T_702 = _T_700 & _T_619; // @[dec_tlu_ctl.scala 716:106] + wire _T_704 = _T_702 & dcsr[15]; // @[dec_tlu_ctl.scala 716:126] + wire ebreak_to_debug_mode_r = _T_704 & _T_590; // @[dec_tlu_ctl.scala 716:147] + wire _T_258 = trigger_hit_dmode_r | ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 464:57] + reg request_debug_mode_r_d1; // @[Reg.scala 27:20] + wire _T_260 = request_debug_mode_r_d1 & _T_586; // @[dec_tlu_ctl.scala 464:110] + wire request_debug_mode_r = _T_258 | _T_260; // @[dec_tlu_ctl.scala 464:83] + reg request_debug_mode_done_f; // @[Reg.scala 27:20] + wire _T_261 = request_debug_mode_r_d1 | request_debug_mode_done_f; // @[dec_tlu_ctl.scala 466:64] + wire request_debug_mode_done = _T_261 & _T_214; // @[dec_tlu_ctl.scala 466:93] + wire _T_264 = io_tlu_ifc_dec_tlu_flush_noredir_wb ^ dec_tlu_flush_noredir_r_d1; // @[lib.scala 470:21] + wire _T_265 = |_T_264; // @[lib.scala 470:29] + wire _T_268 = halt_taken ^ halt_taken_f; // @[lib.scala 448:21] + wire _T_269 = |_T_268; // @[lib.scala 448:29] + wire _T_272 = io_lsu_idle_any ^ lsu_idle_any_f; // @[lib.scala 448:21] + wire _T_273 = |_T_272; // @[lib.scala 448:29] + wire _T_276 = io_tlu_mem_ifu_miss_state_idle ^ ifu_miss_state_idle_f; // @[lib.scala 470:21] + wire _T_277 = |_T_276; // @[lib.scala 470:29] + wire _T_280 = dbg_tlu_halted ^ dbg_tlu_halted_f; // @[lib.scala 448:21] + wire _T_281 = |_T_280; // @[lib.scala 448:29] + reg _T_286; // @[Reg.scala 27:20] + wire _T_284 = resume_ack_ns ^ _T_286; // @[lib.scala 448:21] + wire _T_285 = |_T_284; // @[lib.scala 448:29] + wire _T_288 = debug_halt_req_ns ^ debug_halt_req_f; // @[lib.scala 448:21] + wire _T_289 = |_T_288; // @[lib.scala 448:29] + wire _T_292 = debug_resume_req ^ debug_resume_req_f_raw; // @[lib.scala 448:21] + wire _T_293 = |_T_292; // @[lib.scala 448:29] + wire _T_296 = trigger_hit_dmode_r ^ trigger_hit_dmode_r_d1; // @[lib.scala 448:21] + wire _T_297 = |_T_296; // @[lib.scala 448:29] + wire _T_300 = dcsr_single_step_done ^ dcsr_single_step_done_f; // @[lib.scala 448:21] + wire _T_301 = |_T_300; // @[lib.scala 448:29] + wire _T_304 = debug_halt_req ^ debug_halt_req_d1; // @[lib.scala 448:21] + wire _T_305 = |_T_304; // @[lib.scala 448:29] + reg dec_tlu_wr_pause_r_d1; // @[Reg.scala 27:20] + wire _T_307 = io_dec_tlu_wr_pause_r ^ dec_tlu_wr_pause_r_d1; // @[lib.scala 448:21] + wire _T_308 = |_T_307; // @[lib.scala 448:29] + wire _T_310 = io_dec_pause_state ^ dec_pause_state_f; // @[lib.scala 448:21] + wire _T_311 = |_T_310; // @[lib.scala 448:29] + wire _T_314 = request_debug_mode_r ^ request_debug_mode_r_d1; // @[lib.scala 448:21] + wire _T_315 = |_T_314; // @[lib.scala 448:29] + wire _T_318 = request_debug_mode_done ^ request_debug_mode_done_f; // @[lib.scala 448:21] + wire _T_319 = |_T_318; // @[lib.scala 448:29] + wire _T_322 = dcsr_single_step_running ^ dcsr_single_step_running_f; // @[lib.scala 448:21] + wire _T_323 = |_T_322; // @[lib.scala 448:29] + wire _T_326 = io_dec_tlu_flush_pause_r ^ dec_tlu_flush_pause_r_d1; // @[lib.scala 448:21] + wire _T_327 = |_T_326; // @[lib.scala 448:29] + wire _T_330 = dbg_halt_req_held_ns ^ dbg_halt_req_held; // @[lib.scala 448:21] + wire _T_331 = |_T_330; // @[lib.scala 448:29] + wire _T_675 = io_dec_tlu_packet_r_fence_i & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 708:55] + wire _T_677 = _T_675 & _T_619; // @[dec_tlu_ctl.scala 708:79] + wire fence_i_r = _T_677 & _T_590; // @[dec_tlu_ctl.scala 708:100] + wire _T_335 = fence_i_r & internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 497:71] + wire _T_336 = take_halt | _T_335; // @[dec_tlu_ctl.scala 497:58] + wire _T_337 = _T_336 | io_dec_tlu_flush_pause_r; // @[dec_tlu_ctl.scala 497:97] + wire _T_338 = i0_trigger_hit_raw_r & trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 497:144] + wire _T_339 = _T_337 | _T_338; // @[dec_tlu_ctl.scala 497:124] + wire take_ext_int_start = int_exc_io_take_ext_int_start; // @[dec_tlu_ctl.scala 788:43] + wire _T_341 = ~interrupt_valid_r; // @[dec_tlu_ctl.scala 502:61] + wire _T_342 = dec_tlu_wr_pause_r_d1 & _T_341; // @[dec_tlu_ctl.scala 502:59] + wire _T_343 = ~take_ext_int_start; // @[dec_tlu_ctl.scala 502:82] + wire _T_365 = io_tlu_exu_dec_tlu_flush_lower_r & dcsr[2]; // @[dec_tlu_ctl.scala 506:82] + wire _T_366 = io_dec_tlu_resume_ack | dcsr_single_step_running; // @[dec_tlu_ctl.scala 506:125] + wire _T_367 = _T_365 & _T_366; // @[dec_tlu_ctl.scala 506:100] + wire _T_368 = ~io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec_tlu_ctl.scala 506:155] + wire _T_481 = |i0_trigger_r; // @[dec_tlu_ctl.scala 567:59] + wire _T_483 = _T_481 & _T_590; // @[dec_tlu_ctl.scala 567:63] + wire [3:0] _T_485 = _T_483 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_492 = {i0_trigger_chain_masked_r[3],i0_trigger_r[2],i0_trigger_chain_masked_r[1],i0_trigger_r[0]}; // @[Cat.scala 29:58] + wire _T_495 = ~trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 574:60] + wire _T_496 = ~io_dec_tlu_debug_mode; // @[dec_tlu_ctl.scala 601:62] + wire _T_497 = i_cpu_halt_req_sync & _T_496; // @[dec_tlu_ctl.scala 601:60] + wire i_cpu_halt_req_sync_qual = _T_497 & _T_680; // @[dec_tlu_ctl.scala 601:85] + wire _T_500 = i_cpu_run_req_sync & _T_496; // @[dec_tlu_ctl.scala 602:58] + wire _T_501 = _T_500 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 602:83] + wire i_cpu_run_req_sync_qual = _T_501 & _T_680; // @[dec_tlu_ctl.scala 602:105] + wire _T_503 = i_cpu_halt_req_sync_qual ^ i_cpu_halt_req_d1; // @[lib.scala 448:21] + wire _T_504 = |_T_503; // @[lib.scala 448:29] + wire _T_506 = i_cpu_run_req_sync_qual ^ i_cpu_run_req_d1_raw; // @[lib.scala 448:21] + wire _T_507 = |_T_506; // @[lib.scala 448:29] + wire _T_563 = ~i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 626:51] + wire _T_564 = pmu_fw_tlu_halted_f & _T_563; // @[dec_tlu_ctl.scala 626:49] + wire _T_566 = io_o_cpu_halt_status & _T_563; // @[dec_tlu_ctl.scala 626:94] + wire _T_568 = _T_566 & _T_682; // @[dec_tlu_ctl.scala 626:114] + wire cpu_halt_status = _T_564 | _T_568; // @[dec_tlu_ctl.scala 626:70] + reg _T_512; // @[Reg.scala 27:20] + wire _T_510 = cpu_halt_status ^ _T_512; // @[lib.scala 448:21] + wire _T_511 = |_T_510; // @[lib.scala 448:29] + wire _T_560 = i_cpu_halt_req_d1 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 625:44] + wire _T_561 = io_o_cpu_halt_ack & i_cpu_halt_req_sync; // @[dec_tlu_ctl.scala 625:88] + wire cpu_halt_ack = _T_560 | _T_561; // @[dec_tlu_ctl.scala 625:67] + reg _T_516; // @[Reg.scala 27:20] + wire _T_514 = cpu_halt_ack ^ _T_516; // @[lib.scala 448:21] + wire _T_515 = |_T_514; // @[lib.scala 448:29] + wire _T_571 = _T_216 & i_cpu_run_req_sync; // @[dec_tlu_ctl.scala 627:46] + wire _T_572 = io_o_cpu_halt_status & i_cpu_run_req_d1_raw; // @[dec_tlu_ctl.scala 627:92] + wire _T_573 = _T_571 | _T_572; // @[dec_tlu_ctl.scala 627:68] + wire _T_574 = io_o_cpu_run_ack & i_cpu_run_req_sync; // @[dec_tlu_ctl.scala 627:136] + wire cpu_run_ack = _T_573 | _T_574; // @[dec_tlu_ctl.scala 627:116] + reg _T_520; // @[Reg.scala 27:20] + wire _T_518 = cpu_run_ack ^ _T_520; // @[lib.scala 448:21] + wire _T_519 = |_T_518; // @[lib.scala 448:29] + wire ext_halt_pulse = i_cpu_halt_req_sync_qual & _T_583; // @[dec_tlu_ctl.scala 617:55] + wire fw_halt_req = csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 1011:37] + wire enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; // @[dec_tlu_ctl.scala 618:53] + wire _T_551 = pmu_fw_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 623:50] + wire _T_552 = _T_551 & halt_taken; // @[dec_tlu_ctl.scala 623:63] + wire _T_553 = ~enter_debug_halt_req; // @[dec_tlu_ctl.scala 623:78] + wire _T_554 = _T_552 & _T_553; // @[dec_tlu_ctl.scala 623:76] + wire _T_557 = _T_554 | _T_564; // @[dec_tlu_ctl.scala 623:101] + wire pmu_fw_tlu_halted = _T_557 & _T_358; // @[dec_tlu_ctl.scala 623:146] + wire _T_541 = ~pmu_fw_tlu_halted; // @[dec_tlu_ctl.scala 619:77] + wire _T_542 = pmu_fw_halt_req_f & _T_541; // @[dec_tlu_ctl.scala 619:75] + wire _T_543 = enter_pmu_fw_halt_req | _T_542; // @[dec_tlu_ctl.scala 619:54] + wire pmu_fw_halt_req_ns = _T_543 & _T_358; // @[dec_tlu_ctl.scala 619:98] + wire _T_547 = internal_pmu_fw_halt_mode_f & _T_563; // @[dec_tlu_ctl.scala 620:88] + wire _T_549 = _T_547 & _T_358; // @[dec_tlu_ctl.scala 620:108] + wire internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | _T_549; // @[dec_tlu_ctl.scala 620:57] + wire _T_521 = internal_pmu_fw_halt_mode ^ internal_pmu_fw_halt_mode_f; // @[lib.scala 448:21] + wire _T_522 = |_T_521; // @[lib.scala 448:29] + wire _T_525 = pmu_fw_halt_req_ns ^ pmu_fw_halt_req_f; // @[lib.scala 448:21] + wire _T_526 = |_T_525; // @[lib.scala 448:29] + wire _T_529 = pmu_fw_tlu_halted ^ pmu_fw_tlu_halted_f; // @[lib.scala 448:21] + wire _T_530 = |_T_529; // @[lib.scala 448:29] + wire int_timer0_int_hold = int_exc_io_int_timer0_int_hold; // @[dec_tlu_ctl.scala 785:43] + wire _T_533 = int_timer0_int_hold ^ int_timer0_int_hold_f; // @[lib.scala 448:21] + wire _T_534 = |_T_533; // @[lib.scala 448:29] + wire int_timer1_int_hold = int_exc_io_int_timer1_int_hold; // @[dec_tlu_ctl.scala 786:43] + wire _T_537 = int_timer1_int_hold ^ int_timer1_int_hold_f; // @[lib.scala 448:21] + wire _T_538 = |_T_537; // @[lib.scala 448:29] + wire _T_596 = io_dec_tlu_i0_valid_r & _T_590; // @[dec_tlu_ctl.scala 654:55] + wire _T_597 = ~lsu_exc_valid_r; // @[dec_tlu_ctl.scala 654:70] + wire _T_598 = _T_596 & _T_597; // @[dec_tlu_ctl.scala 654:68] + wire _T_599 = ~inst_acc_r; // @[dec_tlu_ctl.scala 654:87] + wire _T_600 = _T_598 & _T_599; // @[dec_tlu_ctl.scala 654:84] + wire _T_602 = _T_600 & _T_249; // @[dec_tlu_ctl.scala 654:99] + wire _T_603 = ~request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 654:126] + wire _T_604 = _T_602 & _T_603; // @[dec_tlu_ctl.scala 654:124] + wire tlu_i0_commit_cmt = _T_604 & _T_619; // @[dec_tlu_ctl.scala 654:151] + wire _T_626 = tlu_i0_commit_cmt & iccm_repair_state_d1; // @[dec_tlu_ctl.scala 672:57] + wire _T_653 = ~dcsr[15]; // @[dec_tlu_ctl.scala 703:116] + wire _T_654 = _T_702 & _T_653; // @[dec_tlu_ctl.scala 703:114] + wire ebreak_r = _T_654 & _T_590; // @[dec_tlu_ctl.scala 703:136] + wire _T_657 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h9; // @[dec_tlu_ctl.scala 704:57] + wire _T_658 = _T_657 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 704:70] + wire _T_660 = _T_658 & _T_619; // @[dec_tlu_ctl.scala 704:94] + wire ecall_r = _T_660 & _T_590; // @[dec_tlu_ctl.scala 704:114] + wire _T_627 = ebreak_r | ecall_r; // @[dec_tlu_ctl.scala 672:93] + wire _T_628 = _T_627 | mret_r; // @[dec_tlu_ctl.scala 672:103] + wire _T_629 = _T_628 | take_reset; // @[dec_tlu_ctl.scala 672:112] + wire _T_630 = _T_629 | illegal_r; // @[dec_tlu_ctl.scala 672:125] + wire _T_631 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 672:181] + wire _T_632 = dec_csr_wen_r_mod & _T_631; // @[dec_tlu_ctl.scala 672:158] + wire _T_633 = _T_630 | _T_632; // @[dec_tlu_ctl.scala 672:137] + wire _T_634 = ~_T_633; // @[dec_tlu_ctl.scala 672:82] + wire _T_635 = io_tlu_exu_exu_i0_br_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 679:69] + wire _T_638 = io_tlu_exu_exu_i0_br_start_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 680:81] + wire _T_641 = io_tlu_exu_exu_i0_br_valid_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 681:65] + wire _T_643 = _T_641 & _T_611; // @[dec_tlu_ctl.scala 681:89] + wire _T_644 = ~io_tlu_exu_exu_i0_br_mp_r; // @[dec_tlu_ctl.scala 681:116] + wire _T_645 = ~io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 681:145] + wire _T_646 = _T_644 | _T_645; // @[dec_tlu_ctl.scala 681:143] + wire csr_pkt_presync = csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_708 = csr_pkt_presync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1021:50] + wire _T_709 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 1021:75] + wire csr_pkt_postsync = csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_718 = csr_pkt_csr_dcsr | csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1026:63] + wire csr_pkt_csr_dmst = csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_719 = _T_718 | csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1026:81] + wire csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_720 = _T_719 | csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1026:100] + wire csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_721 = _T_720 | csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1026:123] + wire csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_722 = _T_721 | csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1026:144] + wire csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_723 = _T_722 | csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1026:166] + wire csr_pkt_csr_dicago = csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_724 = _T_723 | csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1026:187] + wire _T_725 = ~_T_724; // @[dec_tlu_ctl.scala 1026:44] + wire _T_726 = _T_725 | dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1026:209] + wire csr_pkt_legal = csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_727 = csr_pkt_legal & _T_726; // @[dec_tlu_ctl.scala 1026:41] + wire fast_int_meicpct = int_exc_io_fast_int_meicpct; // @[dec_tlu_ctl.scala 798:43] + wire _T_728 = ~fast_int_meicpct; // @[dec_tlu_ctl.scala 1026:231] + wire valid_csr = _T_727 & _T_728; // @[dec_tlu_ctl.scala 1026:229] + wire _T_731 = io_dec_csr_any_unq_d & valid_csr; // @[dec_tlu_ctl.scala 1028:54] + wire csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_732 = csr_pkt_csr_mvendorid | csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1028:115] + wire csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_733 = _T_732 | csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1028:137] + wire csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_734 = _T_733 | csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1028:158] + wire csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_735 = _T_734 | csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1028:180] + wire csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 278:47 dec_tlu_ctl.scala 1019:16] + wire _T_736 = _T_735 | csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1028:201] + wire _T_737 = io_dec_csr_wen_unq_d & _T_736; // @[dec_tlu_ctl.scala 1028:90] + wire _T_738 = ~_T_737; // @[dec_tlu_ctl.scala 1028:67] + int_exc int_exc ( // @[dec_tlu_ctl.scala 282:29] + .clock(int_exc_clock), + .reset(int_exc_reset), + .io_mhwakeup_ready(int_exc_io_mhwakeup_ready), + .io_ext_int_ready(int_exc_io_ext_int_ready), + .io_ce_int_ready(int_exc_io_ce_int_ready), + .io_soft_int_ready(int_exc_io_soft_int_ready), + .io_timer_int_ready(int_exc_io_timer_int_ready), + .io_int_timer0_int_hold(int_exc_io_int_timer0_int_hold), + .io_int_timer1_int_hold(int_exc_io_int_timer1_int_hold), + .io_internal_dbg_halt_timers(int_exc_io_internal_dbg_halt_timers), + .io_take_ext_int_start(int_exc_io_take_ext_int_start), + .io_ext_int_freeze_d1(int_exc_io_ext_int_freeze_d1), + .io_take_ext_int_start_d1(int_exc_io_take_ext_int_start_d1), + .io_take_ext_int_start_d2(int_exc_io_take_ext_int_start_d2), + .io_take_ext_int_start_d3(int_exc_io_take_ext_int_start_d3), + .io_ext_int_freeze(int_exc_io_ext_int_freeze), + .io_take_ext_int(int_exc_io_take_ext_int), + .io_fast_int_meicpct(int_exc_io_fast_int_meicpct), + .io_ignore_ext_int_due_to_lsu_stall(int_exc_io_ignore_ext_int_due_to_lsu_stall), + .io_take_ce_int(int_exc_io_take_ce_int), + .io_take_soft_int(int_exc_io_take_soft_int), + .io_take_timer_int(int_exc_io_take_timer_int), + .io_take_int_timer0_int(int_exc_io_take_int_timer0_int), + .io_take_int_timer1_int(int_exc_io_take_int_timer1_int), + .io_take_reset(int_exc_io_take_reset), + .io_take_nmi(int_exc_io_take_nmi), + .io_synchronous_flush_r(int_exc_io_synchronous_flush_r), + .io_tlu_flush_lower_r(int_exc_io_tlu_flush_lower_r), + .io_dec_tlu_flush_lower_wb(int_exc_io_dec_tlu_flush_lower_wb), + .io_dec_tlu_flush_lower_r(int_exc_io_dec_tlu_flush_lower_r), + .io_dec_tlu_flush_path_r(int_exc_io_dec_tlu_flush_path_r), + .io_interrupt_valid_r_d1(int_exc_io_interrupt_valid_r_d1), + .io_i0_exception_valid_r_d1(int_exc_io_i0_exception_valid_r_d1), + .io_exc_or_int_valid_r_d1(int_exc_io_exc_or_int_valid_r_d1), + .io_exc_cause_wb(int_exc_io_exc_cause_wb), + .io_i0_valid_wb(int_exc_io_i0_valid_wb), + .io_trigger_hit_r_d1(int_exc_io_trigger_hit_r_d1), + .io_take_nmi_r_d1(int_exc_io_take_nmi_r_d1), + .io_interrupt_valid_r(int_exc_io_interrupt_valid_r), + .io_exc_cause_r(int_exc_io_exc_cause_r), + .io_i0_exception_valid_r(int_exc_io_i0_exception_valid_r), + .io_tlu_flush_path_r_d1(int_exc_io_tlu_flush_path_r_d1), + .io_exc_or_int_valid_r(int_exc_io_exc_or_int_valid_r), + .io_dec_csr_stall_int_ff(int_exc_io_dec_csr_stall_int_ff), + .io_mstatus_mie_ns(int_exc_io_mstatus_mie_ns), + .io_mip(int_exc_io_mip), + .io_mie_ns(int_exc_io_mie_ns), + .io_mret_r(int_exc_io_mret_r), + .io_pmu_fw_tlu_halted_f(int_exc_io_pmu_fw_tlu_halted_f), + .io_int_timer0_int_hold_f(int_exc_io_int_timer0_int_hold_f), + .io_int_timer1_int_hold_f(int_exc_io_int_timer1_int_hold_f), + .io_internal_dbg_halt_mode_f(int_exc_io_internal_dbg_halt_mode_f), + .io_dcsr_single_step_running(int_exc_io_dcsr_single_step_running), + .io_internal_dbg_halt_mode(int_exc_io_internal_dbg_halt_mode), + .io_dec_tlu_i0_valid_r(int_exc_io_dec_tlu_i0_valid_r), + .io_internal_pmu_fw_halt_mode(int_exc_io_internal_pmu_fw_halt_mode), + .io_i_cpu_halt_req_d1(int_exc_io_i_cpu_halt_req_d1), + .io_ebreak_to_debug_mode_r(int_exc_io_ebreak_to_debug_mode_r), + .io_lsu_fir_error(int_exc_io_lsu_fir_error), + .io_csr_pkt_csr_meicpct(int_exc_io_csr_pkt_csr_meicpct), + .io_dec_csr_any_unq_d(int_exc_io_dec_csr_any_unq_d), + .io_lsu_fastint_stall_any(int_exc_io_lsu_fastint_stall_any), + .io_reset_delayed(int_exc_io_reset_delayed), + .io_mpc_reset_run_req(int_exc_io_mpc_reset_run_req), + .io_nmi_int_detected(int_exc_io_nmi_int_detected), + .io_dcsr_single_step_running_f(int_exc_io_dcsr_single_step_running_f), + .io_dcsr_single_step_done_f(int_exc_io_dcsr_single_step_done_f), + .io_dcsr(int_exc_io_dcsr), + .io_mtvec(int_exc_io_mtvec), + .io_tlu_i0_commit_cmt(int_exc_io_tlu_i0_commit_cmt), + .io_i0_trigger_hit_r(int_exc_io_i0_trigger_hit_r), + .io_pause_expired_r(int_exc_io_pause_expired_r), + .io_nmi_vec(int_exc_io_nmi_vec), + .io_lsu_i0_rfnpc_r(int_exc_io_lsu_i0_rfnpc_r), + .io_fence_i_r(int_exc_io_fence_i_r), + .io_iccm_repair_state_rfnpc(int_exc_io_iccm_repair_state_rfnpc), + .io_i_cpu_run_req_d1(int_exc_io_i_cpu_run_req_d1), + .io_rfpc_i0_r(int_exc_io_rfpc_i0_r), + .io_lsu_exc_valid_r(int_exc_io_lsu_exc_valid_r), + .io_trigger_hit_dmode_r(int_exc_io_trigger_hit_dmode_r), + .io_take_halt(int_exc_io_take_halt), + .io_rst_vec(int_exc_io_rst_vec), + .io_lsu_fir_addr(int_exc_io_lsu_fir_addr), + .io_dec_tlu_i0_pc_r(int_exc_io_dec_tlu_i0_pc_r), + .io_npc_r(int_exc_io_npc_r), + .io_mepc(int_exc_io_mepc), + .io_debug_resume_req_f(int_exc_io_debug_resume_req_f), + .io_dpc(int_exc_io_dpc), + .io_npc_r_d1(int_exc_io_npc_r_d1), + .io_tlu_flush_lower_r_d1(int_exc_io_tlu_flush_lower_r_d1), + .io_dec_tlu_dbg_halted(int_exc_io_dec_tlu_dbg_halted), + .io_ebreak_r(int_exc_io_ebreak_r), + .io_ecall_r(int_exc_io_ecall_r), + .io_illegal_r(int_exc_io_illegal_r), + .io_inst_acc_r(int_exc_io_inst_acc_r), + .io_lsu_i0_exc_r(int_exc_io_lsu_i0_exc_r), + .io_lsu_error_pkt_r_bits_inst_type(int_exc_io_lsu_error_pkt_r_bits_inst_type), + .io_lsu_error_pkt_r_bits_exc_type(int_exc_io_lsu_error_pkt_r_bits_exc_type), + .io_dec_tlu_wr_pause_r_d1(int_exc_io_dec_tlu_wr_pause_r_d1) + ); + csr_tlu csr ( // @[dec_tlu_ctl.scala 283:23] + .clock(csr_clock), + .reset(csr_reset), + .io_free_l2clk(csr_io_free_l2clk), + .io_free_clk(csr_io_free_clk), + .io_dec_csr_wrdata_r(csr_io_dec_csr_wrdata_r), + .io_dec_csr_wraddr_r(csr_io_dec_csr_wraddr_r), + .io_dec_csr_rdaddr_d(csr_io_dec_csr_rdaddr_d), + .io_dec_csr_wen_unq_d(csr_io_dec_csr_wen_unq_d), + .io_dec_i0_decode_d(csr_io_dec_i0_decode_d), + .io_dec_tlu_ic_diag_pkt_icache_wrdata(csr_io_dec_tlu_ic_diag_pkt_icache_wrdata), + .io_dec_tlu_ic_diag_pkt_icache_dicawics(csr_io_dec_tlu_ic_diag_pkt_icache_dicawics), + .io_dec_tlu_ic_diag_pkt_icache_rd_valid(csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid), + .io_dec_tlu_ic_diag_pkt_icache_wr_valid(csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid), + .io_ifu_ic_debug_rd_data_valid(csr_io_ifu_ic_debug_rd_data_valid), + .io_trigger_pkt_any_0_select(csr_io_trigger_pkt_any_0_select), + .io_trigger_pkt_any_0_match_pkt(csr_io_trigger_pkt_any_0_match_pkt), + .io_trigger_pkt_any_0_store(csr_io_trigger_pkt_any_0_store), + .io_trigger_pkt_any_0_load(csr_io_trigger_pkt_any_0_load), + .io_trigger_pkt_any_0_execute(csr_io_trigger_pkt_any_0_execute), + .io_trigger_pkt_any_0_m(csr_io_trigger_pkt_any_0_m), + .io_trigger_pkt_any_0_tdata2(csr_io_trigger_pkt_any_0_tdata2), + .io_trigger_pkt_any_1_select(csr_io_trigger_pkt_any_1_select), + .io_trigger_pkt_any_1_match_pkt(csr_io_trigger_pkt_any_1_match_pkt), + .io_trigger_pkt_any_1_store(csr_io_trigger_pkt_any_1_store), + .io_trigger_pkt_any_1_load(csr_io_trigger_pkt_any_1_load), + .io_trigger_pkt_any_1_execute(csr_io_trigger_pkt_any_1_execute), + .io_trigger_pkt_any_1_m(csr_io_trigger_pkt_any_1_m), + .io_trigger_pkt_any_1_tdata2(csr_io_trigger_pkt_any_1_tdata2), + .io_trigger_pkt_any_2_select(csr_io_trigger_pkt_any_2_select), + .io_trigger_pkt_any_2_match_pkt(csr_io_trigger_pkt_any_2_match_pkt), + .io_trigger_pkt_any_2_store(csr_io_trigger_pkt_any_2_store), + .io_trigger_pkt_any_2_load(csr_io_trigger_pkt_any_2_load), + .io_trigger_pkt_any_2_execute(csr_io_trigger_pkt_any_2_execute), + .io_trigger_pkt_any_2_m(csr_io_trigger_pkt_any_2_m), + .io_trigger_pkt_any_2_tdata2(csr_io_trigger_pkt_any_2_tdata2), + .io_trigger_pkt_any_3_select(csr_io_trigger_pkt_any_3_select), + .io_trigger_pkt_any_3_match_pkt(csr_io_trigger_pkt_any_3_match_pkt), + .io_trigger_pkt_any_3_store(csr_io_trigger_pkt_any_3_store), + .io_trigger_pkt_any_3_load(csr_io_trigger_pkt_any_3_load), + .io_trigger_pkt_any_3_execute(csr_io_trigger_pkt_any_3_execute), + .io_trigger_pkt_any_3_m(csr_io_trigger_pkt_any_3_m), + .io_trigger_pkt_any_3_tdata2(csr_io_trigger_pkt_any_3_tdata2), + .io_ifu_pmu_bus_trxn(csr_io_ifu_pmu_bus_trxn), + .io_dma_iccm_stall_any(csr_io_dma_iccm_stall_any), + .io_dma_dccm_stall_any(csr_io_dma_dccm_stall_any), + .io_lsu_store_stall_any(csr_io_lsu_store_stall_any), + .io_dec_pmu_presync_stall(csr_io_dec_pmu_presync_stall), + .io_dec_pmu_postsync_stall(csr_io_dec_pmu_postsync_stall), + .io_dec_pmu_decode_stall(csr_io_dec_pmu_decode_stall), + .io_ifu_pmu_fetch_stall(csr_io_ifu_pmu_fetch_stall), + .io_dec_tlu_packet_r_icaf_type(csr_io_dec_tlu_packet_r_icaf_type), + .io_dec_tlu_packet_r_pmu_i0_itype(csr_io_dec_tlu_packet_r_pmu_i0_itype), + .io_dec_tlu_packet_r_pmu_i0_br_unpred(csr_io_dec_tlu_packet_r_pmu_i0_br_unpred), + .io_dec_tlu_packet_r_pmu_divide(csr_io_dec_tlu_packet_r_pmu_divide), + .io_dec_tlu_packet_r_pmu_lsu_misaligned(csr_io_dec_tlu_packet_r_pmu_lsu_misaligned), + .io_exu_pmu_i0_br_ataken(csr_io_exu_pmu_i0_br_ataken), + .io_exu_pmu_i0_br_misp(csr_io_exu_pmu_i0_br_misp), + .io_dec_pmu_instr_decoded(csr_io_dec_pmu_instr_decoded), + .io_ifu_pmu_instr_aligned(csr_io_ifu_pmu_instr_aligned), + .io_exu_pmu_i0_pc4(csr_io_exu_pmu_i0_pc4), + .io_ifu_pmu_ic_miss(csr_io_ifu_pmu_ic_miss), + .io_ifu_pmu_ic_hit(csr_io_ifu_pmu_ic_hit), + .io_dec_tlu_int_valid_wb1(csr_io_dec_tlu_int_valid_wb1), + .io_dec_tlu_i0_exc_valid_wb1(csr_io_dec_tlu_i0_exc_valid_wb1), + .io_dec_tlu_i0_valid_wb1(csr_io_dec_tlu_i0_valid_wb1), + .io_dec_csr_wen_r(csr_io_dec_csr_wen_r), + .io_dec_tlu_mtval_wb1(csr_io_dec_tlu_mtval_wb1), + .io_dec_tlu_exc_cause_wb1(csr_io_dec_tlu_exc_cause_wb1), + .io_dec_tlu_perfcnt0(csr_io_dec_tlu_perfcnt0), + .io_dec_tlu_perfcnt1(csr_io_dec_tlu_perfcnt1), + .io_dec_tlu_perfcnt2(csr_io_dec_tlu_perfcnt2), + .io_dec_tlu_perfcnt3(csr_io_dec_tlu_perfcnt3), + .io_dec_tlu_dbg_halted(csr_io_dec_tlu_dbg_halted), + .io_dma_pmu_dccm_write(csr_io_dma_pmu_dccm_write), + .io_dma_pmu_dccm_read(csr_io_dma_pmu_dccm_read), + .io_dma_pmu_any_write(csr_io_dma_pmu_any_write), + .io_dma_pmu_any_read(csr_io_dma_pmu_any_read), + .io_lsu_pmu_bus_busy(csr_io_lsu_pmu_bus_busy), + .io_dec_tlu_i0_pc_r(csr_io_dec_tlu_i0_pc_r), + .io_dec_tlu_i0_valid_r(csr_io_dec_tlu_i0_valid_r), + .io_dec_csr_any_unq_d(csr_io_dec_csr_any_unq_d), + .io_dec_tlu_misc_clk_override(csr_io_dec_tlu_misc_clk_override), + .io_dec_tlu_picio_clk_override(csr_io_dec_tlu_picio_clk_override), + .io_dec_tlu_dec_clk_override(csr_io_dec_tlu_dec_clk_override), + .io_dec_tlu_ifu_clk_override(csr_io_dec_tlu_ifu_clk_override), + .io_dec_tlu_lsu_clk_override(csr_io_dec_tlu_lsu_clk_override), + .io_dec_tlu_bus_clk_override(csr_io_dec_tlu_bus_clk_override), + .io_dec_tlu_pic_clk_override(csr_io_dec_tlu_pic_clk_override), + .io_dec_tlu_dccm_clk_override(csr_io_dec_tlu_dccm_clk_override), + .io_dec_tlu_icm_clk_override(csr_io_dec_tlu_icm_clk_override), + .io_dec_csr_rddata_d(csr_io_dec_csr_rddata_d), + .io_dec_tlu_pipelining_disable(csr_io_dec_tlu_pipelining_disable), + .io_dec_tlu_wr_pause_r(csr_io_dec_tlu_wr_pause_r), + .io_ifu_pmu_bus_busy(csr_io_ifu_pmu_bus_busy), + .io_lsu_pmu_bus_error(csr_io_lsu_pmu_bus_error), + .io_ifu_pmu_bus_error(csr_io_ifu_pmu_bus_error), + .io_lsu_pmu_bus_misaligned(csr_io_lsu_pmu_bus_misaligned), + .io_lsu_pmu_bus_trxn(csr_io_lsu_pmu_bus_trxn), + .io_ifu_ic_debug_rd_data(csr_io_ifu_ic_debug_rd_data), + .io_dec_tlu_meipt(csr_io_dec_tlu_meipt), + .io_pic_pl(csr_io_pic_pl), + .io_dec_tlu_meicurpl(csr_io_dec_tlu_meicurpl), + .io_dec_tlu_meihap(csr_io_dec_tlu_meihap), + .io_pic_claimid(csr_io_pic_claimid), + .io_iccm_dma_sb_error(csr_io_iccm_dma_sb_error), + .io_lsu_imprecise_error_addr_any(csr_io_lsu_imprecise_error_addr_any), + .io_lsu_imprecise_error_load_any(csr_io_lsu_imprecise_error_load_any), + .io_lsu_imprecise_error_store_any(csr_io_lsu_imprecise_error_store_any), + .io_dec_tlu_mrac_ff(csr_io_dec_tlu_mrac_ff), + .io_dec_tlu_wb_coalescing_disable(csr_io_dec_tlu_wb_coalescing_disable), + .io_dec_tlu_bpred_disable(csr_io_dec_tlu_bpred_disable), + .io_dec_tlu_sideeffect_posted_disable(csr_io_dec_tlu_sideeffect_posted_disable), + .io_dec_tlu_core_ecc_disable(csr_io_dec_tlu_core_ecc_disable), + .io_dec_tlu_external_ldfwd_disable(csr_io_dec_tlu_external_ldfwd_disable), + .io_dec_tlu_dma_qos_prty(csr_io_dec_tlu_dma_qos_prty), + .io_dec_tlu_trace_disable(csr_io_dec_tlu_trace_disable), + .io_dec_illegal_inst(csr_io_dec_illegal_inst), + .io_lsu_error_pkt_r_bits_mscause(csr_io_lsu_error_pkt_r_bits_mscause), + .io_mexintpend(csr_io_mexintpend), + .io_exu_npc_r(csr_io_exu_npc_r), + .io_mpc_reset_run_req(csr_io_mpc_reset_run_req), + .io_rst_vec(csr_io_rst_vec), + .io_core_id(csr_io_core_id), + .io_dec_timer_rddata_d(csr_io_dec_timer_rddata_d), + .io_dec_timer_read_d(csr_io_dec_timer_read_d), + .io_dec_csr_wen_r_mod(csr_io_dec_csr_wen_r_mod), + .io_rfpc_i0_r(csr_io_rfpc_i0_r), + .io_i0_trigger_hit_r(csr_io_i0_trigger_hit_r), + .io_fw_halt_req(csr_io_fw_halt_req), + .io_mstatus(csr_io_mstatus), + .io_exc_or_int_valid_r(csr_io_exc_or_int_valid_r), + .io_mret_r(csr_io_mret_r), + .io_mstatus_mie_ns(csr_io_mstatus_mie_ns), + .io_dcsr_single_step_running_f(csr_io_dcsr_single_step_running_f), + .io_dcsr(csr_io_dcsr), + .io_mtvec(csr_io_mtvec), + .io_mip(csr_io_mip), + .io_dec_timer_t0_pulse(csr_io_dec_timer_t0_pulse), + .io_dec_timer_t1_pulse(csr_io_dec_timer_t1_pulse), + .io_timer_int_sync(csr_io_timer_int_sync), + .io_soft_int_sync(csr_io_soft_int_sync), + .io_mie_ns(csr_io_mie_ns), + .io_csr_wr_clk(csr_io_csr_wr_clk), + .io_ebreak_to_debug_mode_r(csr_io_ebreak_to_debug_mode_r), + .io_dec_tlu_pmu_fw_halted(csr_io_dec_tlu_pmu_fw_halted), + .io_lsu_fir_error(csr_io_lsu_fir_error), + .io_npc_r(csr_io_npc_r), + .io_tlu_flush_lower_r_d1(csr_io_tlu_flush_lower_r_d1), + .io_dec_tlu_flush_noredir_r_d1(csr_io_dec_tlu_flush_noredir_r_d1), + .io_tlu_flush_path_r_d1(csr_io_tlu_flush_path_r_d1), + .io_npc_r_d1(csr_io_npc_r_d1), + .io_reset_delayed(csr_io_reset_delayed), + .io_mepc(csr_io_mepc), + .io_interrupt_valid_r(csr_io_interrupt_valid_r), + .io_i0_exception_valid_r(csr_io_i0_exception_valid_r), + .io_lsu_exc_valid_r(csr_io_lsu_exc_valid_r), + .io_mepc_trigger_hit_sel_pc_r(csr_io_mepc_trigger_hit_sel_pc_r), + .io_lsu_single_ecc_error_r(csr_io_lsu_single_ecc_error_r), + .io_e4e5_int_clk(csr_io_e4e5_int_clk), + .io_lsu_i0_exc_r(csr_io_lsu_i0_exc_r), + .io_inst_acc_r(csr_io_inst_acc_r), + .io_inst_acc_second_r(csr_io_inst_acc_second_r), + .io_take_nmi(csr_io_take_nmi), + .io_lsu_error_pkt_addr_r(csr_io_lsu_error_pkt_addr_r), + .io_exc_cause_r(csr_io_exc_cause_r), + .io_i0_valid_wb(csr_io_i0_valid_wb), + .io_interrupt_valid_r_d1(csr_io_interrupt_valid_r_d1), + .io_i0_exception_valid_r_d1(csr_io_i0_exception_valid_r_d1), + .io_exc_cause_wb(csr_io_exc_cause_wb), + .io_nmi_lsu_store_type(csr_io_nmi_lsu_store_type), + .io_nmi_lsu_load_type(csr_io_nmi_lsu_load_type), + .io_tlu_i0_commit_cmt(csr_io_tlu_i0_commit_cmt), + .io_ebreak_r(csr_io_ebreak_r), + .io_ecall_r(csr_io_ecall_r), + .io_illegal_r(csr_io_illegal_r), + .io_mdseac_locked_ns(csr_io_mdseac_locked_ns), + .io_mdseac_locked_f(csr_io_mdseac_locked_f), + .io_nmi_int_detected_f(csr_io_nmi_int_detected_f), + .io_internal_dbg_halt_mode_f2(csr_io_internal_dbg_halt_mode_f2), + .io_ext_int_freeze(csr_io_ext_int_freeze), + .io_ext_int_freeze_d1(csr_io_ext_int_freeze_d1), + .io_take_ext_int_start_d1(csr_io_take_ext_int_start_d1), + .io_take_ext_int_start_d2(csr_io_take_ext_int_start_d2), + .io_take_ext_int_start_d3(csr_io_take_ext_int_start_d3), + .io_ic_perr_r(csr_io_ic_perr_r), + .io_iccm_sbecc_r(csr_io_iccm_sbecc_r), + .io_ifu_miss_state_idle_f(csr_io_ifu_miss_state_idle_f), + .io_lsu_idle_any_f(csr_io_lsu_idle_any_f), + .io_dbg_tlu_halted_f(csr_io_dbg_tlu_halted_f), + .io_dbg_tlu_halted(csr_io_dbg_tlu_halted), + .io_debug_halt_req_f(csr_io_debug_halt_req_f), + .io_force_halt(csr_io_force_halt), + .io_take_ext_int_start(csr_io_take_ext_int_start), + .io_trigger_hit_dmode_r_d1(csr_io_trigger_hit_dmode_r_d1), + .io_trigger_hit_r_d1(csr_io_trigger_hit_r_d1), + .io_dcsr_single_step_done_f(csr_io_dcsr_single_step_done_f), + .io_ebreak_to_debug_mode_r_d1(csr_io_ebreak_to_debug_mode_r_d1), + .io_debug_halt_req(csr_io_debug_halt_req), + .io_allow_dbg_halt_csr_write(csr_io_allow_dbg_halt_csr_write), + .io_internal_dbg_halt_mode_f(csr_io_internal_dbg_halt_mode_f), + .io_enter_debug_halt_req(csr_io_enter_debug_halt_req), + .io_internal_dbg_halt_mode(csr_io_internal_dbg_halt_mode), + .io_request_debug_mode_done(csr_io_request_debug_mode_done), + .io_request_debug_mode_r(csr_io_request_debug_mode_r), + .io_dpc(csr_io_dpc), + .io_update_hit_bit_r(csr_io_update_hit_bit_r), + .io_take_timer_int(csr_io_take_timer_int), + .io_take_int_timer0_int(csr_io_take_int_timer0_int), + .io_take_int_timer1_int(csr_io_take_int_timer1_int), + .io_take_ext_int(csr_io_take_ext_int), + .io_tlu_flush_lower_r(csr_io_tlu_flush_lower_r), + .io_dec_tlu_br0_error_r(csr_io_dec_tlu_br0_error_r), + .io_dec_tlu_br0_start_error_r(csr_io_dec_tlu_br0_start_error_r), + .io_lsu_pmu_load_external_r(csr_io_lsu_pmu_load_external_r), + .io_lsu_pmu_store_external_r(csr_io_lsu_pmu_store_external_r), + .io_csr_pkt_csr_misa(csr_io_csr_pkt_csr_misa), + .io_csr_pkt_csr_mvendorid(csr_io_csr_pkt_csr_mvendorid), + .io_csr_pkt_csr_marchid(csr_io_csr_pkt_csr_marchid), + .io_csr_pkt_csr_mimpid(csr_io_csr_pkt_csr_mimpid), + .io_csr_pkt_csr_mhartid(csr_io_csr_pkt_csr_mhartid), + .io_csr_pkt_csr_mstatus(csr_io_csr_pkt_csr_mstatus), + .io_csr_pkt_csr_mtvec(csr_io_csr_pkt_csr_mtvec), + .io_csr_pkt_csr_mip(csr_io_csr_pkt_csr_mip), + .io_csr_pkt_csr_mie(csr_io_csr_pkt_csr_mie), + .io_csr_pkt_csr_mcyclel(csr_io_csr_pkt_csr_mcyclel), + .io_csr_pkt_csr_mcycleh(csr_io_csr_pkt_csr_mcycleh), + .io_csr_pkt_csr_minstretl(csr_io_csr_pkt_csr_minstretl), + .io_csr_pkt_csr_minstreth(csr_io_csr_pkt_csr_minstreth), + .io_csr_pkt_csr_mscratch(csr_io_csr_pkt_csr_mscratch), + .io_csr_pkt_csr_mepc(csr_io_csr_pkt_csr_mepc), + .io_csr_pkt_csr_mcause(csr_io_csr_pkt_csr_mcause), + .io_csr_pkt_csr_mscause(csr_io_csr_pkt_csr_mscause), + .io_csr_pkt_csr_mtval(csr_io_csr_pkt_csr_mtval), + .io_csr_pkt_csr_mrac(csr_io_csr_pkt_csr_mrac), + .io_csr_pkt_csr_mdseac(csr_io_csr_pkt_csr_mdseac), + .io_csr_pkt_csr_meihap(csr_io_csr_pkt_csr_meihap), + .io_csr_pkt_csr_meivt(csr_io_csr_pkt_csr_meivt), + .io_csr_pkt_csr_meipt(csr_io_csr_pkt_csr_meipt), + .io_csr_pkt_csr_meicurpl(csr_io_csr_pkt_csr_meicurpl), + .io_csr_pkt_csr_meicidpl(csr_io_csr_pkt_csr_meicidpl), + .io_csr_pkt_csr_dcsr(csr_io_csr_pkt_csr_dcsr), + .io_csr_pkt_csr_mcgc(csr_io_csr_pkt_csr_mcgc), + .io_csr_pkt_csr_mfdc(csr_io_csr_pkt_csr_mfdc), + .io_csr_pkt_csr_dpc(csr_io_csr_pkt_csr_dpc), + .io_csr_pkt_csr_mtsel(csr_io_csr_pkt_csr_mtsel), + .io_csr_pkt_csr_mtdata1(csr_io_csr_pkt_csr_mtdata1), + .io_csr_pkt_csr_mtdata2(csr_io_csr_pkt_csr_mtdata2), + .io_csr_pkt_csr_mhpmc3(csr_io_csr_pkt_csr_mhpmc3), + .io_csr_pkt_csr_mhpmc4(csr_io_csr_pkt_csr_mhpmc4), + .io_csr_pkt_csr_mhpmc5(csr_io_csr_pkt_csr_mhpmc5), + .io_csr_pkt_csr_mhpmc6(csr_io_csr_pkt_csr_mhpmc6), + .io_csr_pkt_csr_mhpmc3h(csr_io_csr_pkt_csr_mhpmc3h), + .io_csr_pkt_csr_mhpmc4h(csr_io_csr_pkt_csr_mhpmc4h), + .io_csr_pkt_csr_mhpmc5h(csr_io_csr_pkt_csr_mhpmc5h), + .io_csr_pkt_csr_mhpmc6h(csr_io_csr_pkt_csr_mhpmc6h), + .io_csr_pkt_csr_mhpme3(csr_io_csr_pkt_csr_mhpme3), + .io_csr_pkt_csr_mhpme4(csr_io_csr_pkt_csr_mhpme4), + .io_csr_pkt_csr_mhpme5(csr_io_csr_pkt_csr_mhpme5), + .io_csr_pkt_csr_mhpme6(csr_io_csr_pkt_csr_mhpme6), + .io_csr_pkt_csr_mcountinhibit(csr_io_csr_pkt_csr_mcountinhibit), + .io_csr_pkt_csr_mpmc(csr_io_csr_pkt_csr_mpmc), + .io_csr_pkt_csr_micect(csr_io_csr_pkt_csr_micect), + .io_csr_pkt_csr_miccmect(csr_io_csr_pkt_csr_miccmect), + .io_csr_pkt_csr_mdccmect(csr_io_csr_pkt_csr_mdccmect), + .io_csr_pkt_csr_mfdht(csr_io_csr_pkt_csr_mfdht), + .io_csr_pkt_csr_mfdhs(csr_io_csr_pkt_csr_mfdhs), + .io_csr_pkt_csr_dicawics(csr_io_csr_pkt_csr_dicawics), + .io_csr_pkt_csr_dicad0h(csr_io_csr_pkt_csr_dicad0h), + .io_csr_pkt_csr_dicad0(csr_io_csr_pkt_csr_dicad0), + .io_csr_pkt_csr_dicad1(csr_io_csr_pkt_csr_dicad1), + .io_mtdata1_t_0(csr_io_mtdata1_t_0), + .io_mtdata1_t_1(csr_io_mtdata1_t_1), + .io_mtdata1_t_2(csr_io_mtdata1_t_2), + .io_mtdata1_t_3(csr_io_mtdata1_t_3), + .io_trigger_enabled(csr_io_trigger_enabled) + ); + dec_timer_ctl int_timers ( // @[dec_tlu_ctl.scala 284:30] + .clock(int_timers_clock), + .reset(int_timers_reset), + .io_free_l2clk(int_timers_io_free_l2clk), + .io_csr_wr_clk(int_timers_io_csr_wr_clk), + .io_dec_csr_wen_r_mod(int_timers_io_dec_csr_wen_r_mod), + .io_dec_csr_wraddr_r(int_timers_io_dec_csr_wraddr_r), + .io_dec_csr_wrdata_r(int_timers_io_dec_csr_wrdata_r), + .io_csr_mitctl0(int_timers_io_csr_mitctl0), + .io_csr_mitctl1(int_timers_io_csr_mitctl1), + .io_csr_mitb0(int_timers_io_csr_mitb0), + .io_csr_mitb1(int_timers_io_csr_mitb1), + .io_csr_mitcnt0(int_timers_io_csr_mitcnt0), + .io_csr_mitcnt1(int_timers_io_csr_mitcnt1), + .io_dec_pause_state(int_timers_io_dec_pause_state), + .io_dec_tlu_pmu_fw_halted(int_timers_io_dec_tlu_pmu_fw_halted), + .io_internal_dbg_halt_timers(int_timers_io_internal_dbg_halt_timers), + .io_dec_timer_rddata_d(int_timers_io_dec_timer_rddata_d), + .io_dec_timer_read_d(int_timers_io_dec_timer_read_d), + .io_dec_timer_t0_pulse(int_timers_io_dec_timer_t0_pulse), + .io_dec_timer_t1_pulse(int_timers_io_dec_timer_t1_pulse) + ); + dec_decode_csr_read csr_read ( // @[dec_tlu_ctl.scala 1017:28] + .io_dec_csr_rdaddr_d(csr_read_io_dec_csr_rdaddr_d), + .io_csr_pkt_csr_misa(csr_read_io_csr_pkt_csr_misa), + .io_csr_pkt_csr_mvendorid(csr_read_io_csr_pkt_csr_mvendorid), + .io_csr_pkt_csr_marchid(csr_read_io_csr_pkt_csr_marchid), + .io_csr_pkt_csr_mimpid(csr_read_io_csr_pkt_csr_mimpid), + .io_csr_pkt_csr_mhartid(csr_read_io_csr_pkt_csr_mhartid), + .io_csr_pkt_csr_mstatus(csr_read_io_csr_pkt_csr_mstatus), + .io_csr_pkt_csr_mtvec(csr_read_io_csr_pkt_csr_mtvec), + .io_csr_pkt_csr_mip(csr_read_io_csr_pkt_csr_mip), + .io_csr_pkt_csr_mie(csr_read_io_csr_pkt_csr_mie), + .io_csr_pkt_csr_mcyclel(csr_read_io_csr_pkt_csr_mcyclel), + .io_csr_pkt_csr_mcycleh(csr_read_io_csr_pkt_csr_mcycleh), + .io_csr_pkt_csr_minstretl(csr_read_io_csr_pkt_csr_minstretl), + .io_csr_pkt_csr_minstreth(csr_read_io_csr_pkt_csr_minstreth), + .io_csr_pkt_csr_mscratch(csr_read_io_csr_pkt_csr_mscratch), + .io_csr_pkt_csr_mepc(csr_read_io_csr_pkt_csr_mepc), + .io_csr_pkt_csr_mcause(csr_read_io_csr_pkt_csr_mcause), + .io_csr_pkt_csr_mscause(csr_read_io_csr_pkt_csr_mscause), + .io_csr_pkt_csr_mtval(csr_read_io_csr_pkt_csr_mtval), + .io_csr_pkt_csr_mrac(csr_read_io_csr_pkt_csr_mrac), + .io_csr_pkt_csr_dmst(csr_read_io_csr_pkt_csr_dmst), + .io_csr_pkt_csr_mdseac(csr_read_io_csr_pkt_csr_mdseac), + .io_csr_pkt_csr_meihap(csr_read_io_csr_pkt_csr_meihap), + .io_csr_pkt_csr_meivt(csr_read_io_csr_pkt_csr_meivt), + .io_csr_pkt_csr_meipt(csr_read_io_csr_pkt_csr_meipt), + .io_csr_pkt_csr_meicurpl(csr_read_io_csr_pkt_csr_meicurpl), + .io_csr_pkt_csr_meicidpl(csr_read_io_csr_pkt_csr_meicidpl), + .io_csr_pkt_csr_dcsr(csr_read_io_csr_pkt_csr_dcsr), + .io_csr_pkt_csr_mcgc(csr_read_io_csr_pkt_csr_mcgc), + .io_csr_pkt_csr_mfdc(csr_read_io_csr_pkt_csr_mfdc), + .io_csr_pkt_csr_dpc(csr_read_io_csr_pkt_csr_dpc), + .io_csr_pkt_csr_mtsel(csr_read_io_csr_pkt_csr_mtsel), + .io_csr_pkt_csr_mtdata1(csr_read_io_csr_pkt_csr_mtdata1), + .io_csr_pkt_csr_mtdata2(csr_read_io_csr_pkt_csr_mtdata2), + .io_csr_pkt_csr_mhpmc3(csr_read_io_csr_pkt_csr_mhpmc3), + .io_csr_pkt_csr_mhpmc4(csr_read_io_csr_pkt_csr_mhpmc4), + .io_csr_pkt_csr_mhpmc5(csr_read_io_csr_pkt_csr_mhpmc5), + .io_csr_pkt_csr_mhpmc6(csr_read_io_csr_pkt_csr_mhpmc6), + .io_csr_pkt_csr_mhpmc3h(csr_read_io_csr_pkt_csr_mhpmc3h), + .io_csr_pkt_csr_mhpmc4h(csr_read_io_csr_pkt_csr_mhpmc4h), + .io_csr_pkt_csr_mhpmc5h(csr_read_io_csr_pkt_csr_mhpmc5h), + .io_csr_pkt_csr_mhpmc6h(csr_read_io_csr_pkt_csr_mhpmc6h), + .io_csr_pkt_csr_mhpme3(csr_read_io_csr_pkt_csr_mhpme3), + .io_csr_pkt_csr_mhpme4(csr_read_io_csr_pkt_csr_mhpme4), + .io_csr_pkt_csr_mhpme5(csr_read_io_csr_pkt_csr_mhpme5), + .io_csr_pkt_csr_mhpme6(csr_read_io_csr_pkt_csr_mhpme6), + .io_csr_pkt_csr_mcountinhibit(csr_read_io_csr_pkt_csr_mcountinhibit), + .io_csr_pkt_csr_mitctl0(csr_read_io_csr_pkt_csr_mitctl0), + .io_csr_pkt_csr_mitctl1(csr_read_io_csr_pkt_csr_mitctl1), + .io_csr_pkt_csr_mitb0(csr_read_io_csr_pkt_csr_mitb0), + .io_csr_pkt_csr_mitb1(csr_read_io_csr_pkt_csr_mitb1), + .io_csr_pkt_csr_mitcnt0(csr_read_io_csr_pkt_csr_mitcnt0), + .io_csr_pkt_csr_mitcnt1(csr_read_io_csr_pkt_csr_mitcnt1), + .io_csr_pkt_csr_mpmc(csr_read_io_csr_pkt_csr_mpmc), + .io_csr_pkt_csr_meicpct(csr_read_io_csr_pkt_csr_meicpct), + .io_csr_pkt_csr_micect(csr_read_io_csr_pkt_csr_micect), + .io_csr_pkt_csr_miccmect(csr_read_io_csr_pkt_csr_miccmect), + .io_csr_pkt_csr_mdccmect(csr_read_io_csr_pkt_csr_mdccmect), + .io_csr_pkt_csr_mfdht(csr_read_io_csr_pkt_csr_mfdht), + .io_csr_pkt_csr_mfdhs(csr_read_io_csr_pkt_csr_mfdhs), + .io_csr_pkt_csr_dicawics(csr_read_io_csr_pkt_csr_dicawics), + .io_csr_pkt_csr_dicad0h(csr_read_io_csr_pkt_csr_dicad0h), + .io_csr_pkt_csr_dicad0(csr_read_io_csr_pkt_csr_dicad0), + .io_csr_pkt_csr_dicad1(csr_read_io_csr_pkt_csr_dicad1), + .io_csr_pkt_csr_dicago(csr_read_io_csr_pkt_csr_dicago), + .io_csr_pkt_presync(csr_read_io_csr_pkt_presync), + .io_csr_pkt_postsync(csr_read_io_csr_pkt_postsync), + .io_csr_pkt_legal(csr_read_io_csr_pkt_legal) + ); + assign io_tlu_exu_dec_tlu_meihap = csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 879:58] + assign io_tlu_exu_dec_tlu_flush_lower_r = int_exc_io_dec_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 810:54] + assign io_tlu_exu_dec_tlu_flush_path_r = int_exc_io_dec_tlu_flush_path_r; // @[dec_tlu_ctl.scala 811:54] + assign io_tlu_dma_dec_tlu_dma_qos_prty = csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 910:54] + assign io_dec_tlu_core_empty = force_halt | _T_228; // @[dec_tlu_ctl.scala 436:31] + assign io_dec_dbg_cmd_done = io_dec_tlu_i0_valid_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 510:29] + assign io_dec_dbg_cmd_fail = illegal_r & io_dec_dbg_cmd_done; // @[dec_tlu_ctl.scala 511:29] + assign io_dec_tlu_dbg_halted = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 492:41] + assign io_dec_tlu_debug_mode = debug_mode_status; // @[dec_tlu_ctl.scala 493:41] + assign io_dec_tlu_resume_ack = _T_286; // @[dec_tlu_ctl.scala 473:53] + assign io_dec_tlu_debug_stall = debug_halt_req_f; // @[dec_tlu_ctl.scala 491:41] + assign io_dec_tlu_mpc_halted_only = _T_143; // @[dec_tlu_ctl.scala 386:42] + assign io_dec_tlu_flush_extint = int_exc_io_take_ext_int_start; // @[dec_tlu_ctl.scala 499:33] + assign io_trigger_pkt_any_0_select = csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_0_match_pkt = csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_0_store = csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_0_load = csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_0_execute = csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_0_m = csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_0_tdata2 = csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_1_select = csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_1_match_pkt = csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_1_store = csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_1_load = csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_1_execute = csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_1_m = csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_1_tdata2 = csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_2_select = csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_2_match_pkt = csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_2_store = csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_2_load = csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_2_execute = csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_2_m = csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_2_tdata2 = csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_3_select = csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_3_match_pkt = csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_3_store = csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_3_load = csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_3_execute = csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_3_m = csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 885:46] + assign io_trigger_pkt_any_3_tdata2 = csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 885:46] + assign io_o_cpu_halt_status = _T_512; // @[dec_tlu_ctl.scala 606:60] + assign io_o_cpu_halt_ack = _T_516; // @[dec_tlu_ctl.scala 607:68] + assign io_o_cpu_run_ack = _T_520; // @[dec_tlu_ctl.scala 608:68] + assign io_o_debug_mode_status = debug_mode_status; // @[dec_tlu_ctl.scala 630:32] + assign io_mpc_debug_halt_ack = mpc_debug_halt_ack_f; // @[dec_tlu_ctl.scala 412:31] + assign io_mpc_debug_run_ack = mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 413:31] + assign io_debug_brkpt_status = debug_brkpt_status_f; // @[dec_tlu_ctl.scala 414:31] + assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 901:46] + assign io_dec_csr_legal_d = _T_731 & _T_738; // @[dec_tlu_ctl.scala 1028:28] + assign io_dec_tlu_i0_kill_writeb_wb = _T_52; // @[dec_tlu_ctl.scala 343:41] + assign io_dec_tlu_i0_kill_writeb_r = _T_609 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 349:41] + assign io_dec_tlu_wr_pause_r = csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 903:46] + assign io_dec_tlu_flush_pause_r = _T_342 & _T_343; // @[dec_tlu_ctl.scala 502:34] + assign io_dec_tlu_presync_d = _T_708 & _T_709; // @[dec_tlu_ctl.scala 1021:31] + assign io_dec_tlu_postsync_d = csr_pkt_postsync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1022:31] + assign io_dec_tlu_perfcnt0 = csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 888:46] + assign io_dec_tlu_perfcnt1 = csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 889:46] + assign io_dec_tlu_perfcnt2 = csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 890:46] + assign io_dec_tlu_perfcnt3 = csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 891:46] + assign io_dec_tlu_i0_exc_valid_wb1 = csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 882:50] + assign io_dec_tlu_i0_valid_wb1 = csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 883:50] + assign io_dec_tlu_int_valid_wb1 = csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 881:50] + assign io_dec_tlu_exc_cause_wb1 = csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 887:46] + assign io_dec_tlu_mtval_wb1 = csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 886:46] + assign io_dec_tlu_pipelining_disable = csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 902:46] + assign io_dec_tlu_trace_disable = csr_io_dec_tlu_trace_disable; // @[dec_tlu_ctl.scala 911:49] + assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 892:46] + assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 894:46] + assign io_dec_tlu_ifu_clk_override = csr_io_dec_tlu_ifu_clk_override; // @[dec_tlu_ctl.scala 895:46] + assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 896:46] + assign io_dec_tlu_bus_clk_override = csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 897:46] + assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 898:46] + assign io_dec_tlu_picio_clk_override = csr_io_dec_tlu_picio_clk_override; // @[dec_tlu_ctl.scala 893:46] + assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 899:46] + assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 900:46] + assign io_dec_tlu_flush_lower_wb = int_exc_io_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 809:46] + assign io_tlu_bp_dec_tlu_br0_r_pkt_valid = _T_643 & _T_646; // @[dec_tlu_ctl.scala 687:73] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist = io_tlu_exu_exu_i0_br_hist_r; // @[dec_tlu_ctl.scala 684:73] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error = _T_635 & _T_611; // @[dec_tlu_ctl.scala 685:73] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error = _T_638 & _T_611; // @[dec_tlu_ctl.scala 686:73] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[dec_tlu_ctl.scala 688:73] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle = io_tlu_exu_exu_i0_br_middle_r; // @[dec_tlu_ctl.scala 689:81] + assign io_tlu_bp_dec_tlu_flush_leak_one_wb = _T_367 & _T_368; // @[dec_tlu_ctl.scala 506:45] + assign io_tlu_bp_dec_tlu_bpred_disable = csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 906:53] + assign io_tlu_ifc_dec_tlu_flush_noredir_wb = _T_339 | take_ext_int_start; // @[dec_tlu_ctl.scala 497:45] + assign io_tlu_ifc_dec_tlu_mrac_ff = csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 904:54] + assign io_tlu_mem_dec_tlu_flush_err_wb = io_tlu_exu_dec_tlu_flush_lower_r & _T_615; // @[dec_tlu_ctl.scala 507:41] + assign io_tlu_mem_dec_tlu_i0_commit_cmt = _T_604 & _T_619; // @[dec_tlu_ctl.scala 658:42] + assign io_tlu_mem_dec_tlu_force_halt = _T_59; // @[dec_tlu_ctl.scala 345:41] + assign io_tlu_mem_dec_tlu_fence_i_wb = _T_677 & _T_590; // @[dec_tlu_ctl.scala 719:39] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata = csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 884:58] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics = csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 884:58] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid = csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 884:58] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid = csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 884:58] + assign io_tlu_mem_dec_tlu_core_ecc_disable = csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 908:54] + assign io_tlu_busbuff_dec_tlu_external_ldfwd_disable = csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 909:58] + assign io_tlu_busbuff_dec_tlu_wb_coalescing_disable = csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 905:58] + assign io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 907:58] + assign io_dec_pic_dec_tlu_meicurpl = csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 878:58] + assign io_dec_pic_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 880:58] + assign int_exc_clock = clock; + assign int_exc_reset = reset; + assign int_exc_io_ext_int_freeze_d1 = csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 789:42] + assign int_exc_io_take_ext_int_start_d1 = csr_io_take_ext_int_start_d1; // @[dec_tlu_ctl.scala 790:44] + assign int_exc_io_take_ext_int_start_d2 = csr_io_take_ext_int_start_d2; // @[dec_tlu_ctl.scala 791:44] + assign int_exc_io_take_ext_int_start_d3 = csr_io_take_ext_int_start_d3; // @[dec_tlu_ctl.scala 792:44] + assign int_exc_io_dec_csr_stall_int_ff = io_dec_csr_stall_int_ff; // @[dec_tlu_ctl.scala 724:49] + assign int_exc_io_mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 725:49] + assign int_exc_io_mip = csr_io_mip; // @[dec_tlu_ctl.scala 726:49] + assign int_exc_io_mie_ns = csr_io_mie_ns; // @[dec_tlu_ctl.scala 727:49] + assign int_exc_io_mret_r = _T_672 & _T_590; // @[dec_tlu_ctl.scala 728:49] + assign int_exc_io_pmu_fw_tlu_halted_f = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 729:49] + assign int_exc_io_int_timer0_int_hold_f = int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 730:49] + assign int_exc_io_int_timer1_int_hold_f = int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 731:49] + assign int_exc_io_internal_dbg_halt_mode_f = debug_mode_status; // @[dec_tlu_ctl.scala 732:49] + assign int_exc_io_dcsr_single_step_running = _T_255 | _T_257; // @[dec_tlu_ctl.scala 733:49] + assign int_exc_io_internal_dbg_halt_mode = debug_halt_req_ns | _T_238; // @[dec_tlu_ctl.scala 734:49] + assign int_exc_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 735:49] + assign int_exc_io_internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | _T_549; // @[dec_tlu_ctl.scala 736:49] + assign int_exc_io_i_cpu_halt_req_d1 = i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 737:49] + assign int_exc_io_ebreak_to_debug_mode_r = _T_704 & _T_590; // @[dec_tlu_ctl.scala 738:49] + assign int_exc_io_lsu_fir_error = io_lsu_fir_error; // @[dec_tlu_ctl.scala 739:49] + assign int_exc_io_csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 740:49] + assign int_exc_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 741:49] + assign int_exc_io_lsu_fastint_stall_any = io_lsu_fastint_stall_any; // @[dec_tlu_ctl.scala 742:49] + assign int_exc_io_reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 743:49] + assign int_exc_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 744:49] + assign int_exc_io_nmi_int_detected = _T_81 | nmi_fir_type; // @[dec_tlu_ctl.scala 745:49] + assign int_exc_io_dcsr_single_step_running_f = dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 746:49] + assign int_exc_io_dcsr_single_step_done_f = dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 747:49] + assign int_exc_io_dcsr = csr_io_dcsr; // @[dec_tlu_ctl.scala 748:49] + assign int_exc_io_mtvec = csr_io_mtvec; // @[dec_tlu_ctl.scala 749:49] + assign int_exc_io_tlu_i0_commit_cmt = _T_604 & _T_619; // @[dec_tlu_ctl.scala 750:49] + assign int_exc_io_i0_trigger_hit_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 751:49] + assign int_exc_io_pause_expired_r = _T_361 & _T_362; // @[dec_tlu_ctl.scala 752:49] + assign int_exc_io_nmi_vec = io_nmi_vec; // @[dec_tlu_ctl.scala 753:49] + assign int_exc_io_lsu_i0_rfnpc_r = _T_592 & _T_594; // @[dec_tlu_ctl.scala 754:49] + assign int_exc_io_fence_i_r = _T_677 & _T_590; // @[dec_tlu_ctl.scala 755:49] + assign int_exc_io_iccm_repair_state_rfnpc = _T_626 & _T_634; // @[dec_tlu_ctl.scala 756:49] + assign int_exc_io_i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_584; // @[dec_tlu_ctl.scala 757:49] + assign int_exc_io_rfpc_i0_r = _T_620 & _T_621; // @[dec_tlu_ctl.scala 758:49] + assign int_exc_io_lsu_exc_valid_r = _T_589 & _T_590; // @[dec_tlu_ctl.scala 759:49] + assign int_exc_io_trigger_hit_dmode_r = i0_trigger_hit_raw_r & i0_trigger_action_r; // @[dec_tlu_ctl.scala 760:49] + assign int_exc_io_take_halt = _T_208 & _T_209; // @[dec_tlu_ctl.scala 761:49] + assign int_exc_io_rst_vec = io_rst_vec; // @[dec_tlu_ctl.scala 762:49] + assign int_exc_io_lsu_fir_addr = io_lsu_fir_addr; // @[dec_tlu_ctl.scala 763:49] + assign int_exc_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 764:49] + assign int_exc_io_npc_r = csr_io_npc_r; // @[dec_tlu_ctl.scala 765:49] + assign int_exc_io_mepc = csr_io_mepc; // @[dec_tlu_ctl.scala 766:49] + assign int_exc_io_debug_resume_req_f = debug_resume_req_f_raw & _T_333; // @[dec_tlu_ctl.scala 767:49] + assign int_exc_io_dpc = csr_io_dpc; // @[dec_tlu_ctl.scala 768:49] + assign int_exc_io_npc_r_d1 = csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 769:49] + assign int_exc_io_tlu_flush_lower_r_d1 = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 770:49] + assign int_exc_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 771:49] + assign int_exc_io_ebreak_r = _T_654 & _T_590; // @[dec_tlu_ctl.scala 772:49] + assign int_exc_io_ecall_r = _T_660 & _T_590; // @[dec_tlu_ctl.scala 773:49] + assign int_exc_io_illegal_r = _T_666 & _T_590; // @[dec_tlu_ctl.scala 774:49] + assign int_exc_io_inst_acc_r = _T_696 & _T_619; // @[dec_tlu_ctl.scala 775:49] + assign int_exc_io_lsu_i0_exc_r = _T_589 & _T_590; // @[dec_tlu_ctl.scala 776:49] + assign int_exc_io_lsu_error_pkt_r_bits_inst_type = io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 777:49] + assign int_exc_io_lsu_error_pkt_r_bits_exc_type = io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 777:49] + assign int_exc_io_dec_tlu_wr_pause_r_d1 = dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 778:42] + assign csr_clock = clock; + assign csr_reset = reset; + assign csr_io_free_l2clk = io_free_l2clk; // @[dec_tlu_ctl.scala 822:50] + assign csr_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 821:50] + assign csr_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 824:50] + assign csr_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 825:50] + assign csr_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 826:50] + assign csr_io_dec_csr_wen_unq_d = io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 827:50] + assign csr_io_dec_i0_decode_d = io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 828:50] + assign csr_io_ifu_ic_debug_rd_data_valid = io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 829:50] + assign csr_io_ifu_pmu_bus_trxn = io_tlu_mem_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 830:50] + assign csr_io_dma_iccm_stall_any = io_tlu_dma_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 831:50] + assign csr_io_dma_dccm_stall_any = io_tlu_dma_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 832:50] + assign csr_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 833:50] + assign csr_io_dec_pmu_presync_stall = io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 834:50] + assign csr_io_dec_pmu_postsync_stall = io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 835:50] + assign csr_io_dec_pmu_decode_stall = io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 836:50] + assign csr_io_ifu_pmu_fetch_stall = io_tlu_ifc_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 837:50] + assign csr_io_dec_tlu_packet_r_icaf_type = io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 838:50] + assign csr_io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 838:50] + assign csr_io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 838:50] + assign csr_io_dec_tlu_packet_r_pmu_divide = io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 838:50] + assign csr_io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 838:50] + assign csr_io_exu_pmu_i0_br_ataken = io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 839:50] + assign csr_io_exu_pmu_i0_br_misp = io_tlu_exu_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 840:50] + assign csr_io_dec_pmu_instr_decoded = io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 841:50] + assign csr_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 842:50] + assign csr_io_exu_pmu_i0_pc4 = io_tlu_exu_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 843:50] + assign csr_io_ifu_pmu_ic_miss = io_tlu_mem_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 844:50] + assign csr_io_ifu_pmu_ic_hit = io_tlu_mem_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 845:50] + assign csr_io_dec_csr_wen_r = io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 846:50] + assign csr_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 847:50] + assign csr_io_dma_pmu_dccm_write = io_tlu_dma_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 848:50] + assign csr_io_dma_pmu_dccm_read = io_tlu_dma_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 849:50] + assign csr_io_dma_pmu_any_write = io_tlu_dma_dma_pmu_any_write; // @[dec_tlu_ctl.scala 850:50] + assign csr_io_dma_pmu_any_read = io_tlu_dma_dma_pmu_any_read; // @[dec_tlu_ctl.scala 851:50] + assign csr_io_lsu_pmu_bus_busy = io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 852:50] + assign csr_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 853:50] + assign csr_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 854:50] + assign csr_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 856:50] + assign csr_io_ifu_pmu_bus_busy = io_tlu_mem_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 857:50] + assign csr_io_lsu_pmu_bus_error = io_tlu_busbuff_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 858:50] + assign csr_io_ifu_pmu_bus_error = io_tlu_mem_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 859:50] + assign csr_io_lsu_pmu_bus_misaligned = io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 860:50] + assign csr_io_lsu_pmu_bus_trxn = io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 861:50] + assign csr_io_ifu_ic_debug_rd_data = io_tlu_mem_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 862:50] + assign csr_io_pic_pl = io_dec_pic_pic_pl; // @[dec_tlu_ctl.scala 863:50] + assign csr_io_pic_claimid = io_dec_pic_pic_claimid; // @[dec_tlu_ctl.scala 864:50] + assign csr_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 865:50] + assign csr_io_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 866:50] + assign csr_io_lsu_imprecise_error_load_any = io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 867:50] + assign csr_io_lsu_imprecise_error_store_any = io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 868:50] + assign csr_io_dec_illegal_inst = io_dec_illegal_inst; // @[dec_tlu_ctl.scala 869:50 dec_tlu_ctl.scala 912:50] + assign csr_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 870:50 dec_tlu_ctl.scala 913:50] + assign csr_io_mexintpend = io_dec_pic_mexintpend; // @[dec_tlu_ctl.scala 871:50 dec_tlu_ctl.scala 914:50] + assign csr_io_exu_npc_r = io_tlu_exu_exu_npc_r; // @[dec_tlu_ctl.scala 872:50 dec_tlu_ctl.scala 915:50] + assign csr_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 873:50 dec_tlu_ctl.scala 916:50] + assign csr_io_rst_vec = io_rst_vec; // @[dec_tlu_ctl.scala 874:50 dec_tlu_ctl.scala 917:50] + assign csr_io_core_id = io_core_id; // @[dec_tlu_ctl.scala 875:50 dec_tlu_ctl.scala 918:50] + assign csr_io_dec_timer_rddata_d = int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 876:50 dec_tlu_ctl.scala 919:50] + assign csr_io_dec_timer_read_d = int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 877:50 dec_tlu_ctl.scala 920:50] + assign csr_io_rfpc_i0_r = _T_620 & _T_621; // @[dec_tlu_ctl.scala 923:45] + assign csr_io_i0_trigger_hit_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 924:45] + assign csr_io_exc_or_int_valid_r = int_exc_io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 925:45] + assign csr_io_mret_r = _T_672 & _T_590; // @[dec_tlu_ctl.scala 926:45] + assign csr_io_dcsr_single_step_running_f = dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 927:45] + assign csr_io_dec_timer_t0_pulse = int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 928:45] + assign csr_io_dec_timer_t1_pulse = int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 929:45] + assign csr_io_timer_int_sync = syncro_ff[5]; // @[dec_tlu_ctl.scala 930:45] + assign csr_io_soft_int_sync = syncro_ff[4]; // @[dec_tlu_ctl.scala 931:45] + assign csr_io_csr_wr_clk = clock; // @[dec_tlu_ctl.scala 932:45] + assign csr_io_ebreak_to_debug_mode_r = _T_704 & _T_590; // @[dec_tlu_ctl.scala 933:45] + assign csr_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 934:45] + assign csr_io_lsu_fir_error = io_lsu_fir_error; // @[dec_tlu_ctl.scala 935:45] + assign csr_io_tlu_flush_lower_r_d1 = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 936:45] + assign csr_io_dec_tlu_flush_noredir_r_d1 = dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 937:45] + assign csr_io_tlu_flush_path_r_d1 = int_exc_io_tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 938:45] + assign csr_io_reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 939:45] + assign csr_io_interrupt_valid_r = int_exc_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 940:45] + assign csr_io_i0_exception_valid_r = int_exc_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 941:45] + assign csr_io_lsu_exc_valid_r = _T_589 & _T_590; // @[dec_tlu_ctl.scala 942:45] + assign csr_io_mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_495; // @[dec_tlu_ctl.scala 943:45] + assign csr_io_lsu_single_ecc_error_r = io_lsu_single_ecc_error_incr; // @[dec_tlu_ctl.scala 944:45] + assign csr_io_e4e5_int_clk = clock; // @[dec_tlu_ctl.scala 945:45] + assign csr_io_lsu_i0_exc_r = _T_589 & _T_590; // @[dec_tlu_ctl.scala 946:45] + assign csr_io_inst_acc_r = _T_696 & _T_619; // @[dec_tlu_ctl.scala 947:45] + assign csr_io_inst_acc_second_r = io_dec_tlu_packet_r_icaf_second; // @[dec_tlu_ctl.scala 948:45] + assign csr_io_take_nmi = int_exc_io_take_nmi; // @[dec_tlu_ctl.scala 949:45] + assign csr_io_lsu_error_pkt_addr_r = io_lsu_error_pkt_r_bits_addr; // @[dec_tlu_ctl.scala 950:45] + assign csr_io_exc_cause_r = int_exc_io_exc_cause_r; // @[dec_tlu_ctl.scala 951:45] + assign csr_io_i0_valid_wb = int_exc_io_i0_valid_wb; // @[dec_tlu_ctl.scala 952:45] + assign csr_io_interrupt_valid_r_d1 = int_exc_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 954:45] + assign csr_io_i0_exception_valid_r_d1 = int_exc_io_i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 956:45] + assign csr_io_exc_cause_wb = int_exc_io_exc_cause_wb; // @[dec_tlu_ctl.scala 958:45] + assign csr_io_nmi_lsu_store_type = _T_95 | _T_97; // @[dec_tlu_ctl.scala 959:45] + assign csr_io_nmi_lsu_load_type = _T_87 | _T_89; // @[dec_tlu_ctl.scala 960:45] + assign csr_io_tlu_i0_commit_cmt = _T_604 & _T_619; // @[dec_tlu_ctl.scala 961:45] + assign csr_io_ebreak_r = _T_654 & _T_590; // @[dec_tlu_ctl.scala 962:45] + assign csr_io_ecall_r = _T_660 & _T_590; // @[dec_tlu_ctl.scala 963:45] + assign csr_io_illegal_r = _T_666 & _T_590; // @[dec_tlu_ctl.scala 964:45] + assign csr_io_nmi_int_detected_f = nmi_int_detected_f; // @[dec_tlu_ctl.scala 966:45] + assign csr_io_internal_dbg_halt_mode_f2 = internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 967:45] + assign csr_io_ext_int_freeze = int_exc_io_ext_int_freeze; // @[dec_tlu_ctl.scala 820:32] + assign csr_io_ic_perr_r = _T_684 & _T_685; // @[dec_tlu_ctl.scala 969:45] + assign csr_io_iccm_sbecc_r = _T_691 & _T_685; // @[dec_tlu_ctl.scala 970:45] + assign csr_io_ifu_miss_state_idle_f = ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 972:45] + assign csr_io_lsu_idle_any_f = lsu_idle_any_f; // @[dec_tlu_ctl.scala 973:45] + assign csr_io_dbg_tlu_halted_f = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 974:45] + assign csr_io_dbg_tlu_halted = _T_242 | _T_244; // @[dec_tlu_ctl.scala 975:45] + assign csr_io_debug_halt_req_f = debug_halt_req_f; // @[dec_tlu_ctl.scala 976:59] + assign csr_io_take_ext_int_start = int_exc_io_take_ext_int_start; // @[dec_tlu_ctl.scala 977:55] + assign csr_io_trigger_hit_dmode_r_d1 = trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 978:43] + assign csr_io_trigger_hit_r_d1 = int_exc_io_trigger_hit_r_d1; // @[dec_tlu_ctl.scala 979:43] + assign csr_io_dcsr_single_step_done_f = dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 980:43] + assign csr_io_ebreak_to_debug_mode_r_d1 = ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 981:45] + assign csr_io_debug_halt_req = _T_192 & _T_680; // @[dec_tlu_ctl.scala 982:51] + assign csr_io_allow_dbg_halt_csr_write = debug_mode_status & _T_155; // @[dec_tlu_ctl.scala 983:45] + assign csr_io_internal_dbg_halt_mode_f = debug_mode_status; // @[dec_tlu_ctl.scala 984:45] + assign csr_io_enter_debug_halt_req = _T_233 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 985:45] + assign csr_io_internal_dbg_halt_mode = debug_halt_req_ns | _T_238; // @[dec_tlu_ctl.scala 986:45] + assign csr_io_request_debug_mode_done = _T_261 & _T_214; // @[dec_tlu_ctl.scala 987:45] + assign csr_io_request_debug_mode_r = _T_258 | _T_260; // @[dec_tlu_ctl.scala 988:45] + assign csr_io_update_hit_bit_r = _T_485 & _T_492; // @[dec_tlu_ctl.scala 989:45] + assign csr_io_take_timer_int = int_exc_io_take_timer_int; // @[dec_tlu_ctl.scala 990:45] + assign csr_io_take_int_timer0_int = int_exc_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 991:45] + assign csr_io_take_int_timer1_int = int_exc_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 992:45] + assign csr_io_take_ext_int = int_exc_io_take_ext_int; // @[dec_tlu_ctl.scala 993:45] + assign csr_io_tlu_flush_lower_r = int_exc_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 994:45] + assign csr_io_dec_tlu_br0_error_r = _T_635 & _T_611; // @[dec_tlu_ctl.scala 995:45] + assign csr_io_dec_tlu_br0_start_error_r = _T_638 & _T_611; // @[dec_tlu_ctl.scala 996:45] + assign csr_io_lsu_pmu_load_external_r = lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 997:45] + assign csr_io_lsu_pmu_store_external_r = lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 998:45] + assign csr_io_csr_pkt_csr_misa = csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mstatus = csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mtvec = csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mip = csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mie = csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mcyclel = csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mcycleh = csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_minstretl = csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_minstreth = csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mscratch = csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mepc = csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mcause = csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mscause = csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mtval = csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mrac = csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_meivt = csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_meipt = csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_meicurpl = csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_meicidpl = csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mcgc = csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mfdc = csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mtsel = csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mtdata1 = csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mtdata2 = csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpmc3 = csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpmc4 = csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpmc5 = csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpmc6 = csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpmc3h = csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpmc4h = csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpmc5h = csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpmc6h = csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpme3 = csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpme4 = csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpme5 = csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mhpme6 = csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mcountinhibit = csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mpmc = csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_micect = csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_miccmect = csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mdccmect = csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mfdht = csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_mfdhs = csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1000:45] + assign csr_io_trigger_enabled = {_T_412,_T_411}; // @[dec_tlu_ctl.scala 999:45] + assign int_timers_clock = clock; + assign int_timers_reset = reset; + assign int_timers_io_free_l2clk = io_free_l2clk; // @[dec_tlu_ctl.scala 285:65] + assign int_timers_io_csr_wr_clk = clock; // @[dec_tlu_ctl.scala 321:52] + assign int_timers_io_dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 287:49] + assign int_timers_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 289:49] + assign int_timers_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 290:49] + assign int_timers_io_csr_mitctl0 = csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 291:57] + assign int_timers_io_csr_mitctl1 = csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 292:57] + assign int_timers_io_csr_mitb0 = csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 293:57] + assign int_timers_io_csr_mitb1 = csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 294:57] + assign int_timers_io_csr_mitcnt0 = csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 295:57] + assign int_timers_io_csr_mitcnt1 = csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 296:57] + assign int_timers_io_dec_pause_state = io_dec_pause_state; // @[dec_tlu_ctl.scala 297:49] + assign int_timers_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 298:49] + assign int_timers_io_internal_dbg_halt_timers = int_exc_io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 299:47] + assign csr_read_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1018:37] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + dbg_halt_state_f = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + mpc_halt_state_f = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_8 = _RAND_2[6:0]; + _RAND_3 = {1{`RANDOM}}; + syncro_ff = _RAND_3[6:0]; + _RAND_4 = {1{`RANDOM}}; + debug_mode_status = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + i_cpu_run_req_d1_raw = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + nmi_int_delayed = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + nmi_int_detected_f = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + int_timer0_int_hold_f = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + int_timer1_int_hold_f = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + i_cpu_halt_req_d1 = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + reset_detect = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + reset_detected = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + dec_pause_state_f = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + debug_halt_req_f = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + pmu_fw_halt_req_f = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + halt_taken_f = _RAND_16[0:0]; + _RAND_17 = {1{`RANDOM}}; + ifu_ic_error_start_f = _RAND_17[0:0]; + _RAND_18 = {1{`RANDOM}}; + debug_resume_req_f_raw = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + dcsr_single_step_running_f = _RAND_19[0:0]; + _RAND_20 = {1{`RANDOM}}; + dcsr_single_step_done_f = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + internal_pmu_fw_halt_mode_f = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + ifu_iccm_rd_ecc_single_err_f = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + iccm_repair_state_d1 = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + dbg_halt_req_held = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + trigger_hit_dmode_r_d1 = _RAND_25[0:0]; + _RAND_26 = {1{`RANDOM}}; + ebreak_to_debug_mode_r_d1 = _RAND_26[0:0]; + _RAND_27 = {1{`RANDOM}}; + lsu_idle_any_f = _RAND_27[0:0]; + _RAND_28 = {1{`RANDOM}}; + ifu_miss_state_idle_f = _RAND_28[0:0]; + _RAND_29 = {1{`RANDOM}}; + debug_halt_req_d1 = _RAND_29[0:0]; + _RAND_30 = {1{`RANDOM}}; + dec_tlu_flush_noredir_r_d1 = _RAND_30[0:0]; + _RAND_31 = {1{`RANDOM}}; + dec_tlu_flush_pause_r_d1 = _RAND_31[0:0]; + _RAND_32 = {1{`RANDOM}}; + dbg_tlu_halted_f = _RAND_32[0:0]; + _RAND_33 = {1{`RANDOM}}; + pmu_fw_tlu_halted_f = _RAND_33[0:0]; + _RAND_34 = {1{`RANDOM}}; + lsu_pmu_load_external_r = _RAND_34[0:0]; + _RAND_35 = {1{`RANDOM}}; + lsu_pmu_store_external_r = _RAND_35[0:0]; + _RAND_36 = {1{`RANDOM}}; + tlu_flush_lower_r_d1 = _RAND_36[0:0]; + _RAND_37 = {1{`RANDOM}}; + _T_52 = _RAND_37[0:0]; + _RAND_38 = {1{`RANDOM}}; + internal_dbg_halt_mode_f2 = _RAND_38[0:0]; + _RAND_39 = {1{`RANDOM}}; + _T_59 = _RAND_39[0:0]; + _RAND_40 = {1{`RANDOM}}; + nmi_lsu_load_type_f = _RAND_40[0:0]; + _RAND_41 = {1{`RANDOM}}; + nmi_lsu_store_type_f = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + mpc_debug_halt_req_sync_f = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + mpc_debug_run_req_sync_f = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + mpc_run_state_f = _RAND_44[0:0]; + _RAND_45 = {1{`RANDOM}}; + mpc_debug_run_ack_f = _RAND_45[0:0]; + _RAND_46 = {1{`RANDOM}}; + debug_brkpt_status_f = _RAND_46[0:0]; + _RAND_47 = {1{`RANDOM}}; + mpc_debug_halt_ack_f = _RAND_47[0:0]; + _RAND_48 = {1{`RANDOM}}; + dbg_run_state_f = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + _T_143 = _RAND_49[0:0]; + _RAND_50 = {1{`RANDOM}}; + request_debug_mode_r_d1 = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + request_debug_mode_done_f = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + _T_286 = _RAND_52[0:0]; + _RAND_53 = {1{`RANDOM}}; + dec_tlu_wr_pause_r_d1 = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + _T_512 = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + _T_516 = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + _T_520 = _RAND_56[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + dbg_halt_state_f = 1'h0; + end + if (reset) begin + mpc_halt_state_f = 1'h0; + end + if (reset) begin + _T_8 = 7'h0; + end + if (reset) begin + syncro_ff = 7'h0; + end + if (reset) begin + debug_mode_status = 1'h0; + end + if (reset) begin + i_cpu_run_req_d1_raw = 1'h0; + end + if (reset) begin + nmi_int_delayed = 1'h0; + end + if (reset) begin + nmi_int_detected_f = 1'h0; + end + if (reset) begin + int_timer0_int_hold_f = 1'h0; + end + if (reset) begin + int_timer1_int_hold_f = 1'h0; + end + if (reset) begin + i_cpu_halt_req_d1 = 1'h0; + end + if (reset) begin + reset_detect = 1'h0; + end + if (reset) begin + reset_detected = 1'h0; + end + if (reset) begin + dec_pause_state_f = 1'h0; + end + if (reset) begin + debug_halt_req_f = 1'h0; + end + if (reset) begin + pmu_fw_halt_req_f = 1'h0; + end + if (reset) begin + halt_taken_f = 1'h0; + end + if (reset) begin + ifu_ic_error_start_f = 1'h0; + end + if (reset) begin + debug_resume_req_f_raw = 1'h0; + end + if (reset) begin + dcsr_single_step_running_f = 1'h0; + end + if (reset) begin + dcsr_single_step_done_f = 1'h0; + end + if (reset) begin + internal_pmu_fw_halt_mode_f = 1'h0; + end + if (reset) begin + ifu_iccm_rd_ecc_single_err_f = 1'h0; + end + if (reset) begin + iccm_repair_state_d1 = 1'h0; + end + if (reset) begin + dbg_halt_req_held = 1'h0; + end + if (reset) begin + trigger_hit_dmode_r_d1 = 1'h0; + end + if (reset) begin + ebreak_to_debug_mode_r_d1 = 1'h0; + end + if (reset) begin + lsu_idle_any_f = 1'h0; + end + if (reset) begin + ifu_miss_state_idle_f = 1'h0; + end + if (reset) begin + debug_halt_req_d1 = 1'h0; + end + if (reset) begin + dec_tlu_flush_noredir_r_d1 = 1'h0; + end + if (reset) begin + dec_tlu_flush_pause_r_d1 = 1'h0; + end + if (reset) begin + dbg_tlu_halted_f = 1'h0; + end + if (reset) begin + pmu_fw_tlu_halted_f = 1'h0; + end + if (reset) begin + lsu_pmu_load_external_r = 1'h0; + end + if (reset) begin + lsu_pmu_store_external_r = 1'h0; + end + if (reset) begin + tlu_flush_lower_r_d1 = 1'h0; + end + if (reset) begin + _T_52 = 1'h0; + end + if (reset) begin + internal_dbg_halt_mode_f2 = 1'h0; + end + if (reset) begin + _T_59 = 1'h0; + end + if (reset) begin + nmi_lsu_load_type_f = 1'h0; + end + if (reset) begin + nmi_lsu_store_type_f = 1'h0; + end + if (reset) begin + mpc_debug_halt_req_sync_f = 1'h0; + end + if (reset) begin + mpc_debug_run_req_sync_f = 1'h0; + end + if (reset) begin + mpc_run_state_f = 1'h0; + end + if (reset) begin + mpc_debug_run_ack_f = 1'h0; + end + if (reset) begin + debug_brkpt_status_f = 1'h0; + end + if (reset) begin + mpc_debug_halt_ack_f = 1'h0; + end + if (reset) begin + dbg_run_state_f = 1'h0; + end + if (reset) begin + _T_143 = 1'h0; + end + if (reset) begin + request_debug_mode_r_d1 = 1'h0; + end + if (reset) begin + request_debug_mode_done_f = 1'h0; + end + if (reset) begin + _T_286 = 1'h0; + end + if (reset) begin + dec_tlu_wr_pause_r_d1 = 1'h0; + end + if (reset) begin + _T_512 = 1'h0; + end + if (reset) begin + _T_516 = 1'h0; + end + if (reset) begin + _T_520 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dbg_halt_state_f <= 1'h0; + end else if (_T_135) begin + dbg_halt_state_f <= dbg_halt_state_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + mpc_halt_state_f <= 1'h0; + end else if (_T_119) begin + mpc_halt_state_f <= mpc_halt_state_ns; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_8 <= 7'h0; + end else begin + _T_8 <= {_T_6,_T_3}; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + syncro_ff <= 7'h0; + end else begin + syncro_ff <= _T_8; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + debug_mode_status <= 1'h0; + end else if (_T_38) begin + debug_mode_status <= internal_dbg_halt_mode; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + i_cpu_run_req_d1_raw <= 1'h0; + end else if (_T_507) begin + i_cpu_run_req_d1_raw <= i_cpu_run_req_sync_qual; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + nmi_int_delayed <= 1'h0; + end else if (_T_61) begin + nmi_int_delayed <= nmi_int_sync; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + nmi_int_detected_f <= 1'h0; + end else if (_T_64) begin + nmi_int_detected_f <= nmi_int_detected; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + int_timer0_int_hold_f <= 1'h0; + end else if (_T_534) begin + int_timer0_int_hold_f <= int_timer0_int_hold; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + int_timer1_int_hold_f <= 1'h0; + end else if (_T_538) begin + int_timer1_int_hold_f <= int_timer1_int_hold; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + i_cpu_halt_req_d1 <= 1'h0; + end else if (_T_504) begin + i_cpu_halt_req_d1 <= i_cpu_halt_req_sync_qual; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + reset_detect <= 1'h0; + end else begin + reset_detect <= _T_104 | reset_detect; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + reset_detected <= 1'h0; + end else if (_T_107) begin + reset_detected <= reset_detect; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dec_pause_state_f <= 1'h0; + end else if (_T_311) begin + dec_pause_state_f <= io_dec_pause_state; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + debug_halt_req_f <= 1'h0; + end else if (_T_289) begin + debug_halt_req_f <= debug_halt_req_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + pmu_fw_halt_req_f <= 1'h0; + end else if (_T_526) begin + pmu_fw_halt_req_f <= pmu_fw_halt_req_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + halt_taken_f <= 1'h0; + end else if (_T_269) begin + halt_taken_f <= halt_taken; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + ifu_ic_error_start_f <= 1'h0; + end else if (_T_24) begin + ifu_ic_error_start_f <= io_tlu_mem_ifu_ic_error_start; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + debug_resume_req_f_raw <= 1'h0; + end else if (_T_293) begin + debug_resume_req_f_raw <= debug_resume_req; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dcsr_single_step_running_f <= 1'h0; + end else if (_T_323) begin + dcsr_single_step_running_f <= dcsr_single_step_running; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dcsr_single_step_done_f <= 1'h0; + end else if (_T_301) begin + dcsr_single_step_done_f <= dcsr_single_step_done; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + internal_pmu_fw_halt_mode_f <= 1'h0; + end else if (_T_522) begin + internal_pmu_fw_halt_mode_f <= internal_pmu_fw_halt_mode; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + ifu_iccm_rd_ecc_single_err_f <= 1'h0; + end else if (_T_27) begin + ifu_iccm_rd_ecc_single_err_f <= io_tlu_mem_ifu_iccm_rd_ecc_single_err; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + iccm_repair_state_d1 <= 1'h0; + end else if (_T_30) begin + iccm_repair_state_d1 <= iccm_repair_state_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dbg_halt_req_held <= 1'h0; + end else if (_T_331) begin + dbg_halt_req_held <= dbg_halt_req_held_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + trigger_hit_dmode_r_d1 <= 1'h0; + end else if (_T_297) begin + trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ebreak_to_debug_mode_r_d1 <= 1'h0; + end else begin + ebreak_to_debug_mode_r_d1 <= _T_704 & _T_590; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + lsu_idle_any_f <= 1'h0; + end else if (_T_273) begin + lsu_idle_any_f <= io_lsu_idle_any; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + ifu_miss_state_idle_f <= 1'h0; + end else if (_T_277) begin + ifu_miss_state_idle_f <= io_tlu_mem_ifu_miss_state_idle; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + debug_halt_req_d1 <= 1'h0; + end else if (_T_305) begin + debug_halt_req_d1 <= debug_halt_req; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dec_tlu_flush_noredir_r_d1 <= 1'h0; + end else if (_T_265) begin + dec_tlu_flush_noredir_r_d1 <= io_tlu_ifc_dec_tlu_flush_noredir_wb; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dec_tlu_flush_pause_r_d1 <= 1'h0; + end else if (_T_327) begin + dec_tlu_flush_pause_r_d1 <= io_dec_tlu_flush_pause_r; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dbg_tlu_halted_f <= 1'h0; + end else if (_T_281) begin + dbg_tlu_halted_f <= dbg_tlu_halted; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + pmu_fw_tlu_halted_f <= 1'h0; + end else if (_T_530) begin + pmu_fw_tlu_halted_f <= pmu_fw_tlu_halted; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + lsu_pmu_load_external_r <= 1'h0; + end else if (_T_41) begin + lsu_pmu_load_external_r <= io_lsu_tlu_lsu_pmu_load_external_m; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + lsu_pmu_store_external_r <= 1'h0; + end else if (_T_44) begin + lsu_pmu_store_external_r <= io_lsu_tlu_lsu_pmu_store_external_m; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + tlu_flush_lower_r_d1 <= 1'h0; + end else if (_T_47) begin + tlu_flush_lower_r_d1 <= tlu_flush_lower_r; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_52 <= 1'h0; + end else if (_T_51) begin + _T_52 <= tlu_i0_kill_writeb_r; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + internal_dbg_halt_mode_f2 <= 1'h0; + end else if (_T_54) begin + internal_dbg_halt_mode_f2 <= debug_mode_status; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_59 <= 1'h0; + end else if (_T_58) begin + _T_59 <= force_halt; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + nmi_lsu_load_type_f <= 1'h0; + end else if (_T_67) begin + nmi_lsu_load_type_f <= nmi_lsu_load_type; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + nmi_lsu_store_type_f <= 1'h0; + end else if (_T_70) begin + nmi_lsu_store_type_f <= nmi_lsu_store_type; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + mpc_debug_halt_req_sync_f <= 1'h0; + end else if (_T_112) begin + mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + mpc_debug_run_req_sync_f <= 1'h0; + end else if (_T_115) begin + mpc_debug_run_req_sync_f <= mpc_debug_run_req_sync; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + mpc_run_state_f <= 1'h0; + end else if (_T_122) begin + mpc_run_state_f <= mpc_run_state_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + mpc_debug_run_ack_f <= 1'h0; + end else if (_T_131) begin + mpc_debug_run_ack_f <= mpc_debug_run_ack_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + debug_brkpt_status_f <= 1'h0; + end else if (_T_125) begin + debug_brkpt_status_f <= debug_brkpt_status_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + mpc_debug_halt_ack_f <= 1'h0; + end else if (_T_128) begin + mpc_debug_halt_ack_f <= mpc_debug_halt_ack_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dbg_run_state_f <= 1'h0; + end else if (_T_138) begin + dbg_run_state_f <= dbg_run_state_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_143 <= 1'h0; + end else if (_T_142) begin + _T_143 <= _T_1; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + request_debug_mode_r_d1 <= 1'h0; + end else if (_T_315) begin + request_debug_mode_r_d1 <= request_debug_mode_r; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + request_debug_mode_done_f <= 1'h0; + end else if (_T_319) begin + request_debug_mode_done_f <= request_debug_mode_done; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_286 <= 1'h0; + end else if (_T_285) begin + _T_286 <= resume_ack_ns; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + dec_tlu_wr_pause_r_d1 <= 1'h0; + end else if (_T_308) begin + dec_tlu_wr_pause_r_d1 <= io_dec_tlu_wr_pause_r; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_512 <= 1'h0; + end else if (_T_511) begin + _T_512 <= cpu_halt_status; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_516 <= 1'h0; + end else if (_T_515) begin + _T_516 <= cpu_halt_ack; + end + end + always @(posedge io_free_l2clk or posedge reset) begin + if (reset) begin + _T_520 <= 1'h0; + end else if (_T_519) begin + _T_520 <= cpu_run_ack; + end + end +endmodule diff --git a/src/main/scala/dec/dec.scala b/src/main/scala/dec/dec.scala index b3803cd8..09bcef20 100644 --- a/src/main/scala/dec/dec.scala +++ b/src/main/scala/dec/dec.scala @@ -1,301 +1,325 @@ -//package dec -//import chisel3._ -//import chisel3.util._ -//import include._ -//import lib._ -//import lsu._ -// -//class dec_IO extends Bundle with lib { -// val free_clk = Input(Clock()) -// val active_clk = Input(Clock()) -// val lsu_fastint_stall_any = Input(Bool()) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle -// val dec_pause_state_cg = Output(Bool()) // to top for active state clock gating -// val rst_vec = Input(UInt(31.W)) // [31:1] reset vector, from core pins -// -// val nmi_int = Input(Bool()) // NMI pin -// val nmi_vec = Input(UInt(31.W)) // [31:1] NMI vector, from pins -// -// val i_cpu_halt_req = Input(Bool()) // Asynchronous Halt request to CPU -// val i_cpu_run_req = Input(Bool()) // Asynchronous Restart request to CPU -// -// val o_cpu_halt_status = Output(Bool()) // Halt status of core (pmu/fw) -// val o_cpu_halt_ack = Output(Bool()) // Halt request ack -// val o_cpu_run_ack = Output(Bool()) // Run request ack -// val o_debug_mode_status = Output(Bool()) // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request -// -// val core_id = Input(UInt(28.W)) // [31:4] CORE ID -// -// val mpc_debug_halt_req = Input(Bool()) // Async halt request -// val mpc_debug_run_req = Input(Bool()) // Async run request -// val mpc_reset_run_req = Input(Bool()) // Run/halt after reset -// val mpc_debug_halt_ack = Output(Bool()) // Halt ack -// val mpc_debug_run_ack = Output(Bool()) // Run ack -// val debug_brkpt_status = Output(Bool()) // debug breakpoint -// val lsu_pmu_misaligned_m = Input(Bool()) // D side load or store misaligned -// -// -// val lsu_fir_addr = Input(UInt(31.W)) //[31:1] Fast int address -// val lsu_fir_error = Input(UInt(2.W)) //[1:0] Fast int lookup error -// -// val lsu_trigger_match_m = Input(UInt(4.W)) -// val lsu_idle_any = Input(Bool()) // lsu idle for halting -// val lsu_error_pkt_r = Flipped(Valid(new lsu_error_pkt_t)) // LSU exception/error packet -// val lsu_single_ecc_error_incr = Input(Bool())// LSU inc SB error counter -// val exu_div_result = Input(UInt(32.W)) // final div result -// val exu_div_wren = Input(UInt(1.W)) // Divide write enable to GPR -// val lsu_result_m = Input(UInt(32.W)) // load result -// val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected load data -// -// val lsu_load_stall_any = Input(Bool()) // This is for blocking loads -// val lsu_store_stall_any = Input(Bool()) // This is for blocking stores -// -// -// val iccm_dma_sb_error = Input(Bool()) // ICCM DMA single bit error -// -// val exu_flush_final = Input(Bool()) // slot0 flush -// val timer_int = Input(Bool()) // Timer interrupt pending (from pin) -// val soft_int = Input(Bool()) // Software interrupt pending (from pin) -// -// -// -// // Debug start -// val dbg_halt_req = Input(Bool()) // DM requests a halt -// val dbg_resume_req = Input(Bool()) // DM requests a resume -// val dec_tlu_dbg_halted = Output(Bool()) // Core is halted and ready for debug command -// val dec_tlu_debug_mode = Output(Bool()) // Core is in debug mode -// val dec_tlu_resume_ack = Output(Bool()) // Resume acknowledge -// val dec_tlu_mpc_halted_only = Output(Bool()) // Core is halted only due to MPC -// val dec_dbg_rddata = Output(UInt(32.W)) // debug command read data -// -// val dec_dbg_cmd_done = Output(Bool()) // abstract command is done -// val dec_dbg_cmd_fail = Output(Bool()) // abstract command failed (illegal reg address) -// -// val trigger_pkt_any = Output(Vec(4,new trigger_pkt_t)) // info needed by debug trigger blocks -// val exu_i0_br_way_r = Input(Bool()) // way hit or repl -// val lsu_p = Valid(new lsu_pkt_t) // lsu packet -// val dec_lsu_offset_d = Output(UInt(12.W)) // 12b offset for load/store addresses -// val dec_tlu_i0_kill_writeb_r = Output(Bool()) // I0 is flushed, don't writeback any results to arch state -// val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc -// val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc -// val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc -// val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc -// val dec_lsu_valid_raw_d = Output(Bool()) -// val rv_trace_pkt = (new trace_pkt_t) // trace packet -// -// // clock gating overrides from mcgc -// val dec_tlu_misc_clk_override = Output(Bool()) // override misc clock domain gating -// val dec_tlu_ifu_clk_override = Output(Bool()) // override fetch clock domain gating -// val dec_tlu_lsu_clk_override = Output(Bool()) // override load/store clock domain gating -// val dec_tlu_bus_clk_override = Output(Bool()) // override bus clock domain gating -// val dec_tlu_pic_clk_override = Output(Bool()) // override PIC clock domain gating -// val dec_tlu_dccm_clk_override = Output(Bool()) // override DCCM clock domain gating -// val dec_tlu_icm_clk_override = Output(Bool()) // override ICCM clock domain gating -// -// val scan_mode = Input(Bool()) -// val ifu_dec = Flipped(new ifu_dec) -// val dec_exu = Flipped(new dec_exu) -// val lsu_dec = Flipped (new lsu_dec) -// val lsu_tlu = Flipped (new lsu_tlu) -// val dec_dbg = new dec_dbg -// val dec_dma = new dec_dma -// val dec_pic = new dec_pic -//} -//class dec extends Module with param with RequireAsyncReset{ -// val io = IO(new dec_IO) -// -// val dec_i0_inst_wb1 = WireInit(UInt(32.W),0.U) -// val dec_i0_pc_wb1 = WireInit(UInt(32.W),0.U) -// val dec_tlu_i0_valid_wb1 = WireInit(UInt(1.W),0.U) -// val dec_tlu_int_valid_wb1 = WireInit(UInt(1.W),0.U) -// -// val dec_tlu_exc_cause_wb1 = WireInit(UInt(5.W),0.U) -// val dec_tlu_mtval_wb1 = WireInit(UInt(32.W),0.U) -// val dec_tlu_i0_exc_valid_wb1 = WireInit(Bool(),0.B) -// -// -// //--------------------------------------------------------------------------// -// val instbuff = Module(new dec_ib_ctl) -// val decode = Module(new dec_decode_ctl) -// val gpr = Module(new dec_gpr_ctl) -// val tlu = Module(new dec_tlu_ctl) -// val dec_trigger = Module(new dec_trigger) -// -// //connections for dec_Ib -// //inputs -// instbuff.io.ifu_ib <> io.ifu_dec.dec_aln.aln_ib -// instbuff.io.ib_exu <> io.dec_exu.ib_exu -// instbuff.io.dbg_ib <> io.dec_dbg.dbg_ib -// dec_trigger.io.dec_i0_pc_d := instbuff.io.ib_exu.dec_i0_pc_d -// dec_trigger.io.trigger_pkt_any := tlu.io.trigger_pkt_any -// -// val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d -// dontTouch(dec_i0_trigger_match_d) -// decode.io.dec_aln <> io.ifu_dec.dec_aln.aln_dec -// -// decode.io.decode_exu<> io.dec_exu.decode_exu -// decode.io.dec_alu<> io.dec_exu.dec_alu -// decode.io.dec_div<> io.dec_exu.dec_div -// decode.io.dctl_dma <> io.dec_dma.dctl_dma -// decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint -// decode.io.dec_tlu_force_halt := tlu.io.tlu_mem.dec_tlu_force_halt -// decode.io.dctl_busbuff <> io.lsu_dec.dctl_busbuff -// decode.io.dec_i0_trigger_match_d := dec_i0_trigger_match_d -// decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r -// decode.io.dec_tlu_pipelining_disable := tlu.io.dec_tlu_pipelining_disable -// decode.io.lsu_trigger_match_m := io.lsu_trigger_match_m -// decode.io.lsu_pmu_misaligned_m := io.lsu_pmu_misaligned_m -// decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall -// decode.io.dec_tlu_flush_leak_one_r := tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb -// decode.io.dec_debug_fence_d := instbuff.io.dec_debug_fence_d -// decode.io.dbg_dctl <> io.dec_dbg.dbg_dctl -// decode.io.dec_i0_icaf_d := instbuff.io.dec_i0_icaf_d -// decode.io.dec_i0_icaf_f1_d := instbuff.io.dec_i0_icaf_f1_d -// decode.io.dec_i0_icaf_type_d := instbuff.io.dec_i0_icaf_type_d -// decode.io.dec_i0_dbecc_d := instbuff.io.dec_i0_dbecc_d -// decode.io.dec_i0_brp := instbuff.io.dec_i0_brp -// decode.io.dec_i0_bp_index := instbuff.io.dec_i0_bp_index -// decode.io.dec_i0_bp_fghr := instbuff.io.dec_i0_bp_fghr -// decode.io.dec_i0_bp_btag := instbuff.io.dec_i0_bp_btag -// decode.io.dec_i0_pc_d := instbuff.io.ib_exu.dec_i0_pc_d -// decode.io.lsu_idle_any := io.lsu_idle_any -// decode.io.lsu_load_stall_any := io.lsu_load_stall_any -// decode.io.lsu_store_stall_any := io.lsu_store_stall_any -// decode.io.exu_div_wren := io.exu_div_wren -// decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb -// decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb -// decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r -// decode.io.dec_tlu_flush_lower_r := tlu.io.tlu_exu.dec_tlu_flush_lower_r -// decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r -// decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d -// decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d -// decode.io.dec_i0_pc4_d := instbuff.io.dec_i0_pc4_d -// decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d -// decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d -// decode.io.lsu_result_m := io.lsu_result_m -// decode.io.lsu_result_corr_r := io.lsu_result_corr_r -// decode.io.exu_flush_final := io.exu_flush_final -// decode.io.dec_i0_instr_d := instbuff.io.dec_i0_instr_d -// decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d -// decode.io.free_clk := io.free_clk -// decode.io.active_clk := io.active_clk -// decode.io.clk_override := tlu.io.dec_tlu_dec_clk_override -// decode.io.scan_mode := io.scan_mode -// dec_i0_inst_wb1 := decode.io.dec_i0_inst_wb1 //for tracer -// dec_i0_pc_wb1 := decode.io.dec_i0_pc_wb1 //for tracer -// io.lsu_p := decode.io.lsu_p -// io.dec_lsu_valid_raw_d := decode.io.dec_lsu_valid_raw_d -// io.dec_lsu_offset_d := decode.io.dec_lsu_offset_d -// io.dec_pause_state_cg := decode.io.dec_pause_state_cg -// gpr.io.raddr0 := decode.io.dec_i0_rs1_d -// gpr.io.raddr1 := decode.io.dec_i0_rs2_d -// gpr.io.wen0 := decode.io.dec_i0_wen_r -// gpr.io.waddr0 := decode.io.dec_i0_waddr_r -// gpr.io.wd0 := decode.io.dec_i0_wdata_r -// gpr.io.wen1 := decode.io.dec_nonblock_load_wen -// gpr.io.waddr1 := decode.io.dec_nonblock_load_waddr -// gpr.io.wd1 := io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data -// gpr.io.wen2 := io.exu_div_wren -// gpr.io.waddr2 := decode.io.div_waddr_wb -// gpr.io.wd2 := io.exu_div_result -// gpr.io.scan_mode := io.scan_mode -// io.dec_exu.gpr_exu <> gpr.io.gpr_exu -// tlu.io.tlu_mem <> io.ifu_dec.dec_mem_ctrl -// tlu.io.tlu_ifc <> io.ifu_dec.dec_ifc -// tlu.io.tlu_bp <> io.ifu_dec.dec_bp -// tlu.io.tlu_exu <> io.dec_exu.tlu_exu -// tlu.io.tlu_dma <> io.dec_dma.tlu_dma -// tlu.io.active_clk := io.active_clk -// tlu.io.free_clk := io.free_clk -// tlu.io.scan_mode := io.scan_mode -// tlu.io.rst_vec := io.rst_vec -// tlu.io.nmi_int := io.nmi_int -// tlu.io.nmi_vec := io.nmi_vec -// tlu.io.i_cpu_halt_req := io.i_cpu_halt_req -// tlu.io.i_cpu_run_req := io.i_cpu_run_req -// tlu.io.lsu_fastint_stall_any := io.lsu_fastint_stall_any -// tlu.io.ifu_pmu_instr_aligned := io.ifu_dec.dec_aln.ifu_pmu_instr_aligned -// tlu.io.dec_pmu_instr_decoded := decode.io.dec_pmu_instr_decoded -// tlu.io.dec_pmu_decode_stall := decode.io.dec_pmu_decode_stall -// tlu.io.dec_pmu_presync_stall := decode.io.dec_pmu_presync_stall -// tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall -// tlu.io.lsu_store_stall_any := io.lsu_store_stall_any -// io.lsu_dec.tlu_busbuff <> tlu.io.tlu_busbuff -// io.lsu_tlu <> tlu.io.lsu_tlu -// io.dec_pic <> tlu.io.dec_pic -// tlu.io.lsu_fir_addr := io.lsu_fir_addr -// tlu.io.lsu_fir_error := io.lsu_fir_error -// tlu.io.iccm_dma_sb_error := io.iccm_dma_sb_error -// tlu.io.lsu_error_pkt_r := io.lsu_error_pkt_r -// tlu.io.lsu_single_ecc_error_incr := io.lsu_single_ecc_error_incr -// tlu.io.dec_pause_state := decode.io.dec_pause_state -// tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d -// tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d -// tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d -// tlu.io.dec_csr_wen_r := decode.io.dec_csr_wen_r -// tlu.io.dec_csr_wraddr_r := decode.io.dec_csr_wraddr_r -// tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r -// tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff -// tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r -// tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r -// tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r -// tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst -// tlu.io.dec_i0_decode_d := decode.io.dec_aln.dec_i0_decode_d -// tlu.io.exu_i0_br_way_r := io.exu_i0_br_way_r -// tlu.io.dbg_halt_req := io.dbg_halt_req -// tlu.io.dbg_resume_req := io.dbg_resume_req -// tlu.io.lsu_idle_any := io.lsu_idle_any -// tlu.io.dec_div_active := decode.io.dec_div_active -// tlu.io.timer_int := io.timer_int -// tlu.io.soft_int := io.soft_int -// tlu.io.core_id := io.core_id -// tlu.io.mpc_debug_halt_req := io.mpc_debug_halt_req -// tlu.io.mpc_debug_run_req := io.mpc_debug_run_req -// tlu.io.mpc_reset_run_req := io.mpc_reset_run_req -// io.dec_dbg_cmd_done := tlu.io.dec_dbg_cmd_done -// io.dec_dbg_cmd_fail := tlu.io.dec_dbg_cmd_fail -// io.dec_tlu_dbg_halted := tlu.io.dec_tlu_dbg_halted -// io.dec_tlu_debug_mode := tlu.io.dec_tlu_debug_mode -// io.dec_tlu_resume_ack := tlu.io.dec_tlu_resume_ack -// io.dec_tlu_mpc_halted_only := tlu.io.dec_tlu_mpc_halted_only -// io.trigger_pkt_any := tlu.io.trigger_pkt_any -// io.o_cpu_halt_status := tlu.io.o_cpu_halt_status -// io.o_cpu_halt_ack := tlu.io.o_cpu_halt_ack -// io.o_cpu_run_ack := tlu.io.o_cpu_run_ack -// io.o_debug_mode_status := tlu.io.o_debug_mode_status -// io.mpc_debug_halt_ack := tlu.io.mpc_debug_halt_ack -// io.mpc_debug_run_ack := tlu.io.mpc_debug_run_ack -// io.debug_brkpt_status := tlu.io.debug_brkpt_status -// io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r -// io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0 -// io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1 -// io.dec_tlu_perfcnt2 := tlu.io.dec_tlu_perfcnt2 -// io.dec_tlu_perfcnt3 := tlu.io.dec_tlu_perfcnt3 -// dec_tlu_i0_exc_valid_wb1 := tlu.io.dec_tlu_i0_exc_valid_wb1 -// dec_tlu_i0_valid_wb1 := tlu.io.dec_tlu_i0_valid_wb1 -// dec_tlu_int_valid_wb1 := tlu.io.dec_tlu_int_valid_wb1 -// dec_tlu_exc_cause_wb1 := tlu.io.dec_tlu_exc_cause_wb1 -// dec_tlu_mtval_wb1 := tlu.io.dec_tlu_mtval_wb1 -// io.dec_tlu_misc_clk_override := tlu.io.dec_tlu_misc_clk_override -// io.dec_tlu_ifu_clk_override := tlu.io.dec_tlu_ifu_clk_override -// io.dec_tlu_lsu_clk_override := tlu.io.dec_tlu_lsu_clk_override -// io.dec_tlu_bus_clk_override := tlu.io.dec_tlu_bus_clk_override -// io.dec_tlu_pic_clk_override := tlu.io.dec_tlu_pic_clk_override -// io.dec_tlu_dccm_clk_override := tlu.io.dec_tlu_dccm_clk_override -// io.dec_tlu_icm_clk_override := tlu.io.dec_tlu_icm_clk_override -// -// //--------------------------------------------------------------------------// -// -// io.rv_trace_pkt.rv_i_insn_ip := decode.io.dec_i0_inst_wb1 -// io.rv_trace_pkt.rv_i_address_ip := Cat(decode.io.dec_i0_pc_wb1, 0.U) -// io.rv_trace_pkt.rv_i_valid_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_valid_wb1 | tlu.io.dec_tlu_i0_exc_valid_wb1) -// io.rv_trace_pkt.rv_i_exception_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) -// io.rv_trace_pkt.rv_i_ecause_ip := tlu.io.dec_tlu_exc_cause_wb1(4,0) -// io.rv_trace_pkt.rv_i_interrupt_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, 0.U) -// io.rv_trace_pkt.rv_i_tval_ip := tlu.io.dec_tlu_mtval_wb1 -// -// -// // debug command read data -// io.dec_dbg_rddata := decode.io.dec_i0_wdata_r -//} -// -// +package dec +import chisel3._ +import chisel3.util._ +import include._ +import lib._ +import lsu._ + +class dec_IO extends Bundle with lib { + val free_clk = Input(Clock()) + val active_clk = Input(Clock()) + val free_l2clk = Input(Clock()) + val lsu_fastint_stall_any = Input(Bool()) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle + val dec_pause_state_cg = Output(Bool()) // to top for active state clock gating + val dec_tlu_core_empty = Output(Bool()) + val rst_vec = Input(UInt(31.W)) // [31:1] reset vector, from core pins + val ifu_i0_fa_index = Input(UInt(log2Ceil(BTB_SIZE).W)) + val dec_fa_error_index = Output(UInt(log2Ceil(BTB_SIZE).W)) + val nmi_int = Input(Bool()) // NMI pin + val nmi_vec = Input(UInt(31.W)) // [31:1] NMI vector, from pins + val lsu_nonblock_load_data = Input(UInt(32.W)) + + val i_cpu_halt_req = Input(Bool()) // Asynchronous Halt request to CPU + val i_cpu_run_req = Input(Bool()) // Asynchronous Restart request to CPU + + val o_cpu_halt_status = Output(Bool()) // Halt status of core (pmu/fw) + val o_cpu_halt_ack = Output(Bool()) // Halt request ack + val o_cpu_run_ack = Output(Bool()) // Run request ack + val o_debug_mode_status = Output(Bool()) // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request + + val core_id = Input(UInt(28.W)) // [31:4] CORE ID + + val mpc_debug_halt_req = Input(Bool()) // Async halt request + val mpc_debug_run_req = Input(Bool()) // Async run request + val mpc_reset_run_req = Input(Bool()) // Run/halt after reset + val mpc_debug_halt_ack = Output(Bool()) // Halt ack + val mpc_debug_run_ack = Output(Bool()) // Run ack + val debug_brkpt_status = Output(Bool()) // debug breakpoint + val lsu_pmu_misaligned_m = Input(Bool()) // D side load or store misaligned + + + val lsu_fir_addr = Input(UInt(31.W)) //[31:1] Fast int address + val lsu_fir_error = Input(UInt(2.W)) //[1:0] Fast int lookup error + + val lsu_trigger_match_m = Input(UInt(4.W)) + val lsu_idle_any = Input(Bool()) // lsu idle for halting + val lsu_error_pkt_r = Flipped(Valid(new lsu_error_pkt_t)) // LSU exception/error packet + val lsu_single_ecc_error_incr = Input(Bool())// LSU inc SB error counter + val exu_div_result = Input(UInt(32.W)) // final div result + val exu_div_wren = Input(UInt(1.W)) // Divide write enable to GPR + val lsu_result_m = Input(UInt(32.W)) // load result + val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected load data + + val lsu_load_stall_any = Input(Bool()) // This is for blocking loads + val lsu_store_stall_any = Input(Bool()) // This is for blocking stores + + + val iccm_dma_sb_error = Input(Bool()) // ICCM DMA single bit error + + val exu_flush_final = Input(Bool()) // slot0 flush + val timer_int = Input(Bool()) // Timer interrupt pending (from pin) + val soft_int = Input(Bool()) // Software interrupt pending (from pin) + + + + // Debug start + val dbg_halt_req = Input(Bool()) // DM requests a halt + val dbg_resume_req = Input(Bool()) // DM requests a resume + val dec_tlu_dbg_halted = Output(Bool()) // Core is halted and ready for debug command + val dec_tlu_debug_mode = Output(Bool()) // Core is in debug mode + val dec_tlu_resume_ack = Output(Bool()) // Resume acknowledge + val dec_tlu_mpc_halted_only = Output(Bool()) // Core is halted only due to MPC + val dec_dbg_rddata = Output(UInt(32.W)) // debug command read data + val dec_csr_rddata_d = Output(UInt(32.W)) + + val dec_dbg_cmd_done = Output(Bool()) // abstract command is done + val dec_dbg_cmd_fail = Output(Bool()) // abstract command failed (illegal reg address) + + val trigger_pkt_any = Output(Vec(4,new trigger_pkt_t)) // info needed by debug trigger blocks + val exu_i0_br_way_r = Input(Bool()) // way hit or repl + val lsu_p = Valid(new lsu_pkt_t) // lsu packet + val dec_lsu_offset_d = Output(UInt(12.W)) // 12b offset for load/store addresses + val dec_tlu_i0_kill_writeb_r = Output(Bool()) // I0 is flushed, don't writeback any results to arch state + val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc + val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc + val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc + val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc + val dec_tlu_flush_lower_wb = Output(Bool()) + val dec_lsu_valid_raw_d = Output(Bool()) + val trace_rv_trace_pkt = (new trace_pkt_t) // trace packet + + // clock gating overrides from mcgc + val dec_tlu_misc_clk_override = Output(Bool()) // override misc clock domain gating + val dec_tlu_ifu_clk_override = Output(Bool()) // override fetch clock domain gating + val dec_tlu_lsu_clk_override = Output(Bool()) // override load/store clock domain gating + val dec_tlu_bus_clk_override = Output(Bool()) // override bus clock domain gating + val dec_tlu_pic_clk_override = Output(Bool()) // override PIC clock domain gating + val dec_tlu_picio_clk_override = Output(Bool()) + val dec_tlu_dccm_clk_override = Output(Bool()) // override DCCM clock domain gating + val dec_tlu_icm_clk_override = Output(Bool()) // override ICCM clock domain gating + + val scan_mode = Input(Bool()) + val ifu_dec = Flipped(new ifu_dec) + val dec_exu = Flipped(new dec_exu) + val lsu_dec = Flipped (new lsu_dec) + val lsu_tlu = Flipped (new lsu_tlu) + val dec_dbg = new dec_dbg + val dec_dma = new dec_dma + val dec_pic = new dec_pic +} +class dec extends Module with param with RequireAsyncReset{ + val io = IO(new dec_IO) + + val dec_i0_inst_wb1 = WireInit(UInt(32.W),0.U) + val dec_i0_pc_wb1 = WireInit(UInt(32.W),0.U) + val dec_tlu_i0_valid_wb1 = WireInit(UInt(1.W),0.U) + val dec_tlu_int_valid_wb1 = WireInit(UInt(1.W),0.U) + + val dec_tlu_exc_cause_wb1 = WireInit(UInt(5.W),0.U) + val dec_tlu_mtval_wb1 = WireInit(UInt(32.W),0.U) + val dec_tlu_i0_exc_valid_wb1 = WireInit(Bool(),0.B) + val dec_tlu_trace_disable = WireInit(Bool(),0.B) + // val dec_i0_bp_fa_index = WireInit(UInt(log2Ceil(BTB_SIZE).W),0.U) + //val dec_debug_valid_d = WireInit(Bool(),0.B) + + + + //--------------------------------------------------------------------------// + val instbuff = Module(new dec_ib_ctl) + val decode = Module(new dec_decode_ctl) + val gpr = Module(new dec_gpr_ctl) + val tlu = Module(new dec_tlu_ctl) + val dec_trigger = Module(new dec_trigger) + + //connections for dec_Ib + //inputs + instbuff.io.ifu_ib <> io.ifu_dec.dec_aln.aln_ib + instbuff.io.ib_exu <> io.dec_exu.ib_exu + instbuff.io.dbg_ib <> io.dec_dbg.dbg_ib + instbuff.io.ifu_i0_fa_index := io.ifu_i0_fa_index + dec_trigger.io.dec_i0_pc_d := instbuff.io.ib_exu.dec_i0_pc_d + dec_trigger.io.trigger_pkt_any := tlu.io.trigger_pkt_any + + val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d + dontTouch(dec_i0_trigger_match_d) + decode.io.dec_aln <> io.ifu_dec.dec_aln.aln_dec + + decode.io.decode_exu<> io.dec_exu.decode_exu + decode.io.dec_alu<> io.dec_exu.dec_alu + decode.io.dec_div<> io.dec_exu.dec_div + decode.io.dctl_dma <> io.dec_dma.dctl_dma + decode.io.dec_tlu_trace_disable := tlu.io.dec_tlu_trace_disable + decode.io.dec_debug_valid_d := instbuff.io.dec_debug_fence_d + decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint + decode.io.dec_tlu_force_halt := tlu.io.tlu_mem.dec_tlu_force_halt + decode.io.dctl_busbuff <> io.lsu_dec.dctl_busbuff + decode.io.dec_i0_trigger_match_d := dec_i0_trigger_match_d + decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r + decode.io.dec_tlu_pipelining_disable := tlu.io.dec_tlu_pipelining_disable + decode.io.lsu_trigger_match_m := io.lsu_trigger_match_m + decode.io.lsu_pmu_misaligned_m := io.lsu_pmu_misaligned_m + decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall + decode.io.dec_i0_bp_fa_index := instbuff.io.dec_i0_bp_fa_index + decode.io.dec_tlu_flush_leak_one_r := tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb + decode.io.dec_debug_fence_d := instbuff.io.dec_debug_fence_d + decode.io.dbg_dctl <> io.dec_dbg.dbg_dctl + decode.io.dec_i0_icaf_d := instbuff.io.dec_i0_icaf_d + decode.io.dec_i0_icaf_second_d := instbuff.io.dec_i0_icaf_second_d + decode.io.dec_i0_icaf_type_d := instbuff.io.dec_i0_icaf_type_d + decode.io.dec_i0_dbecc_d := instbuff.io.dec_i0_dbecc_d + decode.io.dec_i0_brp := instbuff.io.dec_i0_brp + decode.io.dec_i0_bp_index := instbuff.io.dec_i0_bp_index + decode.io.dec_i0_bp_fghr := instbuff.io.dec_i0_bp_fghr + decode.io.dec_i0_bp_btag := instbuff.io.dec_i0_bp_btag + decode.io.lsu_idle_any := io.lsu_idle_any + decode.io.lsu_load_stall_any := io.lsu_load_stall_any + decode.io.lsu_store_stall_any := io.lsu_store_stall_any + decode.io.exu_div_wren := io.exu_div_wren + decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb + decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb + decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r + decode.io.dec_tlu_flush_lower_r := tlu.io.tlu_exu.dec_tlu_flush_lower_r + decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r + decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d + decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d + decode.io.dec_i0_pc4_d := instbuff.io.dec_i0_pc4_d + decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d + decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d + decode.io.lsu_result_m := io.lsu_result_m + decode.io.lsu_result_corr_r := io.lsu_result_corr_r + decode.io.exu_flush_final := io.exu_flush_final + decode.io.dec_i0_instr_d := instbuff.io.dec_i0_instr_d + decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d + decode.io.free_l2clk := io.free_l2clk + decode.io.active_clk := io.active_clk + decode.io.clk_override := tlu.io.dec_tlu_dec_clk_override + decode.io.scan_mode := io.scan_mode + dec_i0_inst_wb1 := decode.io.dec_i0_inst_wb //for tracer + dec_i0_pc_wb1 := decode.io.dec_i0_pc_wb //for tracer + io.lsu_p := decode.io.lsu_p + io.dec_lsu_valid_raw_d := decode.io.dec_lsu_valid_raw_d + io.dec_lsu_offset_d := decode.io.dec_lsu_offset_d + io.dec_pause_state_cg := decode.io.dec_pause_state_cg + io.dec_exu.decode_exu.dec_qual_lsu_d := decode.io.decode_exu.dec_qual_lsu_d + io.dec_fa_error_index :=decode.io.dec_fa_error_index + + gpr.io.raddr0 := decode.io.dec_i0_rs1_d + gpr.io.raddr1 := decode.io.dec_i0_rs2_d + gpr.io.wen0 := decode.io.dec_i0_wen_r + gpr.io.waddr0 := decode.io.dec_i0_waddr_r + gpr.io.wd0 := decode.io.dec_i0_wdata_r + gpr.io.wen1 := decode.io.dec_nonblock_load_wen + gpr.io.waddr1 := decode.io.dec_nonblock_load_waddr + gpr.io.wd1 := io.lsu_nonblock_load_data + gpr.io.wen2 := io.exu_div_wren + gpr.io.waddr2 := decode.io.div_waddr_wb + gpr.io.wd2 := io.exu_div_result + gpr.io.scan_mode := io.scan_mode + io.dec_exu.gpr_exu <> gpr.io.gpr_exu + + tlu.io.tlu_mem <> io.ifu_dec.dec_mem_ctrl + tlu.io.tlu_ifc <> io.ifu_dec.dec_ifc + tlu.io.tlu_bp <> io.ifu_dec.dec_bp + tlu.io.tlu_exu <> io.dec_exu.tlu_exu + tlu.io.tlu_dma <> io.dec_dma.tlu_dma + tlu.io.free_l2clk := io.free_l2clk + tlu.io.free_clk := io.free_clk + tlu.io.scan_mode := io.scan_mode + tlu.io.rst_vec := io.rst_vec + tlu.io.nmi_int := io.nmi_int + tlu.io.nmi_vec := io.nmi_vec + tlu.io.i_cpu_halt_req := io.i_cpu_halt_req + tlu.io.i_cpu_run_req := io.i_cpu_run_req + tlu.io.lsu_fastint_stall_any := io.lsu_fastint_stall_any + tlu.io.ifu_pmu_instr_aligned := io.ifu_dec.dec_aln.ifu_pmu_instr_aligned + tlu.io.dec_pmu_instr_decoded := decode.io.dec_pmu_instr_decoded + tlu.io.dec_pmu_decode_stall := decode.io.dec_pmu_decode_stall + tlu.io.dec_pmu_presync_stall := decode.io.dec_pmu_presync_stall + tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall + tlu.io.lsu_store_stall_any := io.lsu_store_stall_any + io.lsu_dec.tlu_busbuff <> tlu.io.tlu_busbuff + io.lsu_tlu <> tlu.io.lsu_tlu + io.dec_pic <> tlu.io.dec_pic + tlu.io.lsu_fir_addr := io.lsu_fir_addr + tlu.io.lsu_fir_error := io.lsu_fir_error + tlu.io.iccm_dma_sb_error := io.iccm_dma_sb_error + tlu.io.lsu_error_pkt_r := io.lsu_error_pkt_r + tlu.io.lsu_single_ecc_error_incr := io.lsu_single_ecc_error_incr + tlu.io.dec_pause_state := decode.io.dec_pause_state + tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d + tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d + tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d + tlu.io.dec_csr_wen_r := decode.io.dec_csr_wen_r + tlu.io.dec_csr_wraddr_r := decode.io.dec_csr_wraddr_r + tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r + tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff + tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r + tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r + tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r + tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst + tlu.io.dec_i0_decode_d := decode.io.dec_aln.dec_i0_decode_d + tlu.io.exu_i0_br_way_r := io.exu_i0_br_way_r + tlu.io.dbg_halt_req := io.dbg_halt_req + tlu.io.dbg_resume_req := io.dbg_resume_req + tlu.io.lsu_idle_any := io.lsu_idle_any + tlu.io.dec_div_active := decode.io.dec_div_active + tlu.io.timer_int := io.timer_int + tlu.io.soft_int := io.soft_int + tlu.io.core_id := io.core_id + tlu.io.mpc_debug_halt_req := io.mpc_debug_halt_req + tlu.io.mpc_debug_run_req := io.mpc_debug_run_req + tlu.io.mpc_reset_run_req := io.mpc_reset_run_req + io.dec_dbg_cmd_done := tlu.io.dec_dbg_cmd_done + io.dec_dbg_cmd_fail := tlu.io.dec_dbg_cmd_fail + io.dec_tlu_dbg_halted := tlu.io.dec_tlu_dbg_halted + io.dec_tlu_debug_mode := tlu.io.dec_tlu_debug_mode + io.dec_tlu_resume_ack := tlu.io.dec_tlu_resume_ack + io.dec_tlu_mpc_halted_only := tlu.io.dec_tlu_mpc_halted_only + io.trigger_pkt_any := tlu.io.trigger_pkt_any + io.o_cpu_halt_status := tlu.io.o_cpu_halt_status + io.o_cpu_halt_ack := tlu.io.o_cpu_halt_ack + io.o_cpu_run_ack := tlu.io.o_cpu_run_ack + io.o_debug_mode_status := tlu.io.o_debug_mode_status + io.mpc_debug_halt_ack := tlu.io.mpc_debug_halt_ack + io.mpc_debug_run_ack := tlu.io.mpc_debug_run_ack + io.debug_brkpt_status := tlu.io.debug_brkpt_status + io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r + io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0 + io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1 + io.dec_tlu_perfcnt2 := tlu.io.dec_tlu_perfcnt2 + io.dec_tlu_perfcnt3 := tlu.io.dec_tlu_perfcnt3 + dec_tlu_i0_exc_valid_wb1 := tlu.io.dec_tlu_i0_exc_valid_wb1 + dec_tlu_i0_valid_wb1 := tlu.io.dec_tlu_i0_valid_wb1 + dec_tlu_int_valid_wb1 := tlu.io.dec_tlu_int_valid_wb1 + dec_tlu_exc_cause_wb1 := tlu.io.dec_tlu_exc_cause_wb1 + dec_tlu_mtval_wb1 := tlu.io.dec_tlu_mtval_wb1 + io.dec_tlu_misc_clk_override := tlu.io.dec_tlu_misc_clk_override + io.dec_tlu_ifu_clk_override := tlu.io.dec_tlu_ifu_clk_override + io.dec_tlu_lsu_clk_override := tlu.io.dec_tlu_lsu_clk_override + io.dec_tlu_bus_clk_override := tlu.io.dec_tlu_bus_clk_override + io.dec_tlu_pic_clk_override := tlu.io.dec_tlu_pic_clk_override + io.dec_tlu_dccm_clk_override := tlu.io.dec_tlu_dccm_clk_override + io.dec_tlu_icm_clk_override := tlu.io.dec_tlu_icm_clk_override + io.dec_tlu_picio_clk_override := tlu.io.dec_tlu_icm_clk_override + io.dec_tlu_core_empty := tlu.io.dec_tlu_core_empty + io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d + io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb + + //--------------------------------------------------------------------------// + + io.trace_rv_trace_pkt.rv_i_insn_ip := decode.io.dec_i0_inst_wb + io.trace_rv_trace_pkt.rv_i_address_ip := Cat(decode.io.dec_i0_pc_wb, 0.U) + io.trace_rv_trace_pkt.rv_i_valid_ip := tlu.io.dec_tlu_int_valid_wb1 | tlu.io.dec_tlu_i0_valid_wb1 | tlu.io.dec_tlu_i0_exc_valid_wb1 + io.trace_rv_trace_pkt.rv_i_exception_ip := tlu.io.dec_tlu_int_valid_wb1 | tlu.io.dec_tlu_i0_exc_valid_wb1 + io.trace_rv_trace_pkt.rv_i_ecause_ip := tlu.io.dec_tlu_exc_cause_wb1(4,0) + io.trace_rv_trace_pkt.rv_i_interrupt_ip := tlu.io.dec_tlu_int_valid_wb1 + io.trace_rv_trace_pkt.rv_i_tval_ip := tlu.io.dec_tlu_mtval_wb1 + + + // debug command read data + io.dec_dbg_rddata := decode.io.dec_i0_wdata_r +} +object dec_main extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new dec())) +} + diff --git a/src/main/scala/dec/dec_dec_ctl.scala b/src/main/scala/dec/dec_dec_ctl.scala index 9c66f0f7..592946c3 100644 --- a/src/main/scala/dec/dec_dec_ctl.scala +++ b/src/main/scala/dec/dec_dec_ctl.scala @@ -17,105 +17,254 @@ class dec_dec_ctl extends Module with lib{ pat.reduce(_&_) } - io.out.alu := io.ins(2) | io.ins(6) | (!io.ins(25)&io.ins(4)) | (!io.ins(5)&io.ins(4)) - io.out.rs1 := pattern(List(-14,-13,-2)) | pattern(List(-13,11,-2)) | - pattern(List(19,13,-2)) | pattern(List(-13,10,-2)) | - pattern(List(18,13,-2)) | pattern(List(-13,9,-2)) | - pattern(List(17,13,-2)) | pattern(List(-13,8,-2)) | - pattern(List(16,13,-2)) | pattern(List(-13,7,-2)) | - pattern(List(15,13,-2)) |pattern(List(-4,-3)) | pattern(List(-6,-2)) + io.out.alu := pattern(List(30,24,23,-22,-21,-20,14,-5,4)) | pattern(List(29,-27,-24,4)) | + pattern(List(-25,-13,-12,4)) | pattern(List(-30,-25,13,12)) | pattern(List(27,25,14,4)) | + pattern(List(29,27,-14,4)) | pattern(List(29,-14,5,4)) | pattern(List(-27,-25,14,4)) | + pattern(List(30,-29,-13,4)) | pattern(List(-30,-27,-25,4)) | pattern(List(13,-5,4)) | + pattern(List(-12,-5,4)) | pattern(List(2)) | pattern(List(6)) | pattern(List(30,24,23,22,21,20,-5,4)) | + pattern(List(-30,29,-24,-23,22,21,20,-5,4)) | pattern(List(-30,24,-23,-22,-21,-20,-5,4)) + + io.out.rs1 := pattern(List(-14,-13,-2)) | pattern(List(-13,11,-2)) | pattern(List(19,13,-2)) | + pattern(List(-13,10,-2)) | pattern(List(18,13,-2)) | pattern(List(-13,9,-2)) | pattern(List(17,13,-2)) | + pattern(List(-13,8,-2)) | pattern(List(16,13,-2)) | pattern(List(-13,7,-2)) | + pattern(List(15,13,-2)) | pattern(List(-4,-3)) | pattern(List(-6,-2)) + io.out.rs2 := pattern(List(5,-4,-2)) | pattern(List(-6,5,-2)) - io.out.imm12 := pattern(List(-4,-3,2)) | pattern(List(13,-5,4,-2)) | - pattern(List(-13,-12,6,4)) | pattern(List(-12,-5,4,-2)) - io.out.rd := (!io.ins(5) & !io.ins(2)) | (io.ins(5) & io.ins(2)) | io.ins(4) - io.out.shimm5 := pattern(List(-13,12,-5,4,-2)) - io.out.imm20 := (io.ins(5)&io.ins(3)) | (io.ins(4)&io.ins(2)) - io.out.pc := (!io.ins(5) & !io.ins(3) & io.ins(2)) | (io.ins(5) & io.ins(3)) + + io.out.imm12 := pattern(List(-4,-3,2)) | pattern(List(13,-5,4,-2)) | pattern(List(-13,-12,6,4)) | pattern(List(-12,-5,4,-2)) + + io.out.rd := pattern(List(-5,-2)) | pattern(List(5,2)) | pattern(List(4)) + + io.out.shimm5 := pattern(List(27,-13,12,-5,4,-2)) | pattern(List(-30,-13,12,-5,4,-2)) | pattern(List(14,-13,12,-5,4,-2)) + + io.out.imm20 := pattern(List(5,3)) | pattern(List(4,2)) + + io.out.pc := pattern(List(-5,-3,2)) | pattern(List(5,3)) + io.out.load := pattern(List(-5,-4,-2)) + io.out.store := pattern(List(-6,5,-4)) + io.out.lsu := pattern(List(-6,-4,-2)) - io.out.add := pattern(List(-14,-13,-12,-5,4)) | pattern(List(-5,-3,2)) | - pattern(List(-30,-25,-14,-13,-12,-6,4,-2)) - io.out.sub := pattern(List(30,-12,-6,5,4,-2)) | pattern(List(-25,-14,13,-6,4,-2)) | - pattern(List(-14,13,-5,4,-2)) | pattern(List(6,-4,-2)) - io.out.land := pattern(List(14,13,12,-5,-2)) | pattern(List(-25,14,13,12,-6,-2)) - io.out.lor := pattern(List(-6,3)) | pattern(List(-25,14,13,-12,-6,-2)) | - pattern(List(5,4,2)) | pattern(List(-13,-12,6,4)) | - pattern(List(14,13,-12,-5,-2)) - io.out.lxor := pattern(List(-25,14,-13,-12,4,-2)) | pattern(List(14,-13,-12,-5,4,-2)) - io.out.sll := pattern(List(-25,-14,-13,12,-6,4,-2)) - io.out.sra := pattern(List(30,-13,12,-6,4,-2)) - io.out.srl := pattern(List(-30,-25,14,-13,12,-6,4,-2)) - io.out.slt := pattern(List(-25,-14,13,-6,4,-2)) | pattern(List(-14,13,-5,4,-2)) - io.out.unsign := pattern(List(-14,13,12,-5,-2)) | pattern(List(13,6,-4,-2)) | - pattern(List(14,-5,-4)) | pattern(List(-25,-14,13,12,-6,-2)) | - pattern(List(25,14,12,-6,5,-2)) + + io.out.add := pattern(List(-14,-13,-12,-5,4)) | pattern(List(-5,-3,2)) | pattern(List(-30,-25,-14,-13,-12,-6,4,-2)) + + io.out.sub := pattern(List(30,-14,-12,-6,5,4,-2)) | pattern(List(-29,-25,-14,13,-6,4,-2)) | + pattern(List(27,25,14,-6,5,-2)) | pattern(List(-14,13,-5,4,-2)) | pattern(List(6,-4,-2)) + + io.out.land := pattern(List(-27,-25,14,13,12,-6,-2)) | pattern(List(14,13,12,-5,-2)) + + io.out.lor := pattern(List(-6,3)) | pattern(List(-29,-27,-25,14,13,-12,-6,-2)) | pattern(List(5,4,2)) | + pattern(List(-13,-12,6,4)) | pattern(List(14,13,-12,-5,-2)) + + io.out.lxor := pattern(List(-29,-27,-25,14,-13,-12,4,-2)) | pattern(List(14,-13,-12,-5,4,-2)) + + io.out.sll := pattern(List(-29,-27,-25,-14,-13,12,-6,4,-2)) + + io.out.sra := pattern(List(30,-29,-27,-13,12,-6,4,-2)) + + io.out.srl := pattern(List(-30,-29,-27,-25,14,-13,12,-6,4,-2)) + + io.out.slt := pattern(List(-29,-25,-14,13,-6,4,-2)) | pattern(List(-14,13,-5,4,-2)) + + io.out.unsign := pattern(List(-27,25,14,12,-6,5,-2)) | pattern(List(-14,13,12,-5,-2)) | + pattern(List(13,6,-4,-2)) | pattern(List(14,-5,-4)) | pattern(List(-25,-14,13,12,-6,-2)) | + pattern(List(27,25,14,13,-6,5,-2)) + io.out.condbr := pattern(List(6,-4,-2)) + io.out.beq := pattern(List(-14,-12,6,-4,-2)) + io.out.bne := pattern(List(-14,12,6,-4,-2)) + io.out.bge := pattern(List(14,12,5,-4,-2)) + io.out.blt := pattern(List(14,-12,5,-4,-2)) + io.out.jal := pattern(List(6,2)) + io.out.by := pattern(List(-13,-12,-6,-4,-2)) + io.out.half := pattern(List(12,-6,-4,-2)) + io.out.word := pattern(List(13,-6,-4)) - io.out.csr_read := pattern(List(13,6,4)) | pattern(List(7,6,4)) | - pattern(List(8,6,4)) | pattern(List(9,6,4)) | pattern(List(10,6,4)) | - pattern(List(11,6,4)) + + io.out.csr_read := pattern(List(13,6,4)) | pattern(List(7,6,4)) | pattern(List(8,6,4)) | + pattern(List(9,6,4)) | pattern(List(10,6,4)) | pattern(List(11,6,4)) + io.out.csr_clr := pattern(List(15,13,12,6,4)) | pattern(List(16,13,12,6,4)) | - pattern(List(17,13,12,6,4)) | pattern(List(18,13,12,6,4)) | - pattern(List(19,13,12,6,4)) + pattern(List(17,13,12,6,4)) | pattern(List(18,13,12,6,4)) | pattern(List(19,13,12,6,4)) + + io.out.csr_set := pattern(List(15,-12,6,4)) | pattern(List(16,-12,6,4)) | pattern(List(17,-12,6,4)) | + pattern(List(18,-12,6,4)) | pattern(List(19,-12,6,4)) + io.out.csr_write := pattern(List(-13,12,6,4)) - io.out.csr_imm := pattern(List(14,-13,6,4)) | pattern(List(15,14,6,4)) | - pattern(List(16,14,6,4)) | pattern(List(17,14,6,4)) | - pattern(List(18,14,6,4)) | pattern(List(19,14,6,4)) - io.out.csr_set := pattern(List(15,-12,6,4)) | pattern(List(16,-12,6,4)) | - pattern(List(17,-12,6,4)) | pattern(List(18,-12,6,4)) | - pattern(List(19,-12,6,4)) - io.out.ebreak := pattern(List(-22,20,-13,-12,6,4)) - io.out.ecall := pattern(List(-21,-20,-13,-12,6,4)) - io.out.mret := pattern(List(29,-13,-12,6,4)) - io.out.mul := pattern(List(25,-14,-6,5,4,-2)) - io.out.rs1_sign := pattern(List(25,-14,13,-12,-6,5,4,-2)) | - pattern(List(25,-14,-13,12,-6,4,-2)) - io.out.rs2_sign := pattern(List(25,-14,-13,12,-6,4,-2)) - io.out.low := pattern(List(25,-14,-13,-12,5,4,-2)) - io.out.div := pattern(List(25,14,-6,5,-2)) - io.out.rem := pattern(List(25,14,13,-6,5,-2)) - io.out.fence := pattern(List(-5,3)) - io.out.fence_i := pattern(List(12,-5,3)) - io.out.pm_alu := pattern(List(28,22,-13,-12,4)) | pattern(List(4,2)) | - pattern(List(-25,-6,4)) | pattern(List(-5,4)) - io.out.presync := pattern(List(-5,3)) | pattern(List(-13,7,6,4)) | - pattern(List(-13,8,6,4)) | pattern(List(-13,9,6,4)) | - pattern(List(-13,10,6,4)) | pattern(List(-13,11,6,4)) | - pattern(List(15,13,6,4)) | pattern(List(16,13,6,4)) | - pattern(List(17,13,6,4)) | pattern(List(18,13,6,4)) | - pattern(List(19,13,6,4)) - io.out.postsync := pattern(List(12,-5,3)) | pattern(List(-22,-13,-12,6,4)) | - pattern(List(-13,7,6,4)) | pattern(List(-13,8,6,4)) | - pattern(List(-13,9,6,4)) | pattern(List(-13,10,6,4)) | - pattern(List(-13,11,6,4)) | pattern(List(15,13,6,4)) | - pattern(List(16,13,6,4)) | pattern(List(17,13,6,4)) | + + io.out.csr_imm := pattern(List(14,-13,6,4)) | pattern(List(15,14,6,4)) | pattern(List(16,14,6,4)) | + pattern(List(17,14,6,4)) | pattern(List(18,14,6,4)) | pattern(List(19,14,6,4)) + + io.out.presync := pattern(List(-5,3)) | pattern(List(-13,7,6,4)) | pattern(List(-13,8,6,4)) | + pattern(List(-13,9,6,4)) | pattern(List(-13,10,6,4)) | pattern(List(-13,11,6,4)) | + pattern(List(15,13,6,4)) | pattern(List(16,13,6,4)) | pattern(List(17,13,6,4)) | pattern(List(18,13,6,4)) | pattern(List(19,13,6,4)) - io.out.legal := pattern(List(-31,-30,29,28,-27,-26,-25,-24,-23,-22,21,-20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)) | - pattern(List(-31,-30,-29,28,-27,-26,-25,-24,-23,22,-21,20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)) | + + io.out.postsync := pattern(List(12,-5,3)) | pattern(List(-22,-13,-12,6,4)) | + pattern(List(-13,7,6,4)) | pattern(List(-13,8,6,4)) | pattern(List(-13,9,6,4)) | pattern(List(-13,10,6,4)) | + pattern(List(-13,11,6,4)) | pattern(List(15,13,6,4)) | pattern(List(16,13,6,4)) | pattern(List(17,13,6,4)) | + pattern(List(18,13,6,4)) | pattern(List(19,13,6,4)) + + io.out.ebreak := pattern(List(-22,20,-13,-12,6,4)) + + io.out.ecall := pattern(List(-21,-20,-13,-12,6,4)) + + io.out.mret := pattern(List(29,-13,-12,6,4)) + + io.out.mul := pattern(List(-30,27,24,20,14,-13,12,-5,4,-2)) | pattern(List(29,27,-24,23,14,-13,12,-5,4,-2)) | + pattern(List(29,27,-24,-20,14,-13,12,-5,4,-2)) | pattern(List(27,-25,13,-12,-6,5,4,-2)) | + pattern(List(30,27,13,-6,5,4,-2)) | pattern(List(29,27,22,-20,14,-13,12,-5,4,-2)) | + pattern(List(29,27,-21,20,14,-13,12,-5,4,-2)) | pattern(List(29,27,-22,21,14,-13,12,-5,4,-2)) | + pattern(List(30,29,27,-23,14,-13,12,-5,4,-2)) | pattern(List(-30,27,23,14,-13,12,-5,4,-2)) | + pattern(List(-30,-29,27,-25,-13,12,-6,4,-2)) | pattern(List(25,-14,-6,5,4,-2)) | + pattern(List(30,-27,24,-14,-13,12,-5,4,-2)) | pattern(List(29,27,14,-6,5,-2)) + + io.out.rs1_sign := pattern(List(-27,25,-14,13,-12,-6,5,4,-2)) | pattern(List(-27,25,-14,-13,12,-6,4,-2)) + + io.out.rs2_sign := pattern(List(-27,25,-14,-13,12,-6,4,-2)) + + io.out.low := pattern(List(25,-14,-13,-12,5,4,-2)) + + io.out.div := pattern(List(-27,25,14,-6,5,-2)) + + io.out.rem := pattern(List(-27,25,14,13,-6,5,-2)) + + io.out.fence := pattern(List(-5,3)) + + io.out.fence_i := pattern(List(12,-5,3)) + + io.out.clz := pattern(List(30,-27,-24,-22,-21,-20,-14,-13,12,-5,4,-2)) + + io.out.ctz := pattern(List(30,-27,-24,-22,20,-14,-13,12,-5,4,-2)) + + io.out.pcnt := pattern(List(30,-27,-24,21,-14,-13,12,-5,4,-2)) + + io.out.sext_b := pattern(List(30,-27,22,-20,-14,-13,12,-5,4,-2)) + + io.out.sext_h := pattern(List(30,-27,22,20,-14,-13,12,-5,4,-2)) + + io.out.slo := pattern(List(-30,29,-27,-14,-13,12,-6,4,-2)) + + io.out.sro := pattern(List(-30,29,-27,14,-13,12,-6,4,-2)) + + io.out.min := pattern(List(27,25,14,-12,-6,5,-2)) + + io.out.max := pattern(List(27,25,14,12,-6,5,-2)) + + io.out.pack := pattern(List(-30,27,-25,-13,-12,5,4,-2)) + + io.out.packu := pattern(List(30,27,-13,-12,5,4,-2)) + + io.out.packh := pattern(List(-30,27,-25,13,12,-6,5,-2)) + + io.out.rol := pattern(List(30,-27,-14,12,-6,5,4,-2)) + + io.out.ror := pattern(List(30,29,-27,14,-13,12,-6,4,-2)) + + io.out.zbb := pattern(List(30,-27,-24,-14,-13,12,-5,4,-2)) | pattern(List(-30,27,14,13,12,-6,5,-2)) | + pattern(List(30,29,-27,14,-13,12,-5,4,-2)) | pattern(List(27,-13,-12,5,4,-2)) | + pattern(List(30,14,-13,-12,-6,5,-2)) | pattern(List(30,-27,13,-6,5,4,-2)) | + pattern(List(30,29,-27,-6,5,4,-2)) | pattern(List(30,29,24,23,22,21,20,14,-13,12,-5,4,-2)) | + pattern(List(-30,29,27,-24,-23,22,21,20,14,-13,12,-5,4,-2)) | + pattern(List(-30,27,24,-23,-22,-21,-20,14,-13,12,-5,4,-2)) | + pattern(List(30,29,24,23,-22,-21,-20,14,-13,12,-5,4,-2)) | pattern(List(27,25,14,-6,5,-2)) + + io.out.sbset := pattern(List(-30,29,27,-14,-13,12,-6,4,-2)) + + io.out.sbclr := pattern(List(30,-29,-14,-13,12,-6,4,-2)) + + io.out.sbinv := pattern(List(30,29,27,-14,-13,12,-6,4,-2)) + + io.out.sbext := pattern(List(30,-29,27,14,-13,12,-6,4,-2)) + + io.out.zbs := pattern(List(29,27,-14,-13,12,-6,4,-2)) | pattern(List(30,-29,27,-13,12,-6,4,-2)) + + io.out.bext := pattern(List(-30,27,-25,13,-12,-6,5,4,-2)) + + io.out.bdep := pattern(List(30,27,13,-12,-6,5,4,-2)) + + io.out.zbe := pattern(List(27,-25,13,-12,-6,5,4,-2)) + + io.out.clmul := pattern(List(27,25,-14,-13,-6,5,4,-2)) + + io.out.clmulh := pattern(List(27,-14,13,12,-6,5,-2)) + + io.out.clmulr := pattern(List(27,-14,-12,-6,5,4,-2)) + + io.out.zbc := pattern(List(27,25,-14,-6,5,4,-2)) + + io.out.grev := pattern(List(30,29,27,14,-13,12,-6,4,-2)) + + io.out.gorc := pattern(List(-30,29,27,14,-13,12,-6,4,-2)) + + io.out.shfl := pattern(List(-30,-29,27,-25,-14,-13,12,-6,4,-2)) + + io.out.unshfl := pattern(List(-30,-29,27,-25,14,-13,12,-6,4,-2)) + + io.out.zbp := pattern(List(-30,29,-27,-13,12,-5,4,-2)) | pattern(List(-30,-29,27,-13,12,-5,4,-2)) | + pattern(List(30,-27,13,-6,5,4,-2)) | pattern(List(27,-25,-13,-12,5,4,-2)) | + pattern(List(30,14,-13,-12,5,4,-2)) | pattern(List(29,-27,12,-6,5,4,-2)) | + pattern(List(-30,-29,27,-25,12,-6,5,4,-2)) | pattern(List(29,14,-13,12,-6,4,-2)) + + io.out.crc32_b := pattern(List(30,-27,24,-23,-21,-20,-14,-13,12,-5,4,-2)) + + io.out.crc32_h := pattern(List(30,-27,24,-23,20,-14,-13,12,-5,4,-2)) + + io.out.crc32_w := pattern(List(30,-27,24,-23,21,-14,-13,12,-5,4,-2)) + + io.out.crc32c_b := pattern(List(30,-27,23,-21,-20,-14,-13,12,-5 ,4,-2)) + + io.out.crc32c_h := pattern(List(30,-27,23,20,-14,-13,12,-5,4,-2)) + + io.out.crc32c_w := pattern(List(30,-27,23,21,-14,-13,12,-5,4,-2)) + + io.out.zbr := pattern(List(30,-27,24,-14,-13,12,-5,4,-2)) + + io.out.bfp := pattern(List(30,27,13,12,-6,5,-2)) + + io.out.zbf := pattern(List(30,27,13,12,-6,5,-2)) + + io.out.sh1add := pattern(List(29,-14,-12,-6,5,4,-2)) + + io.out.sh2add := pattern(List(29,14,-13,-12,5,4,-2)) + + io.out.sh3add := pattern(List(29,14,13,-6,5,-2)) + + io.out.zba := pattern(List(29,-12,-6,5,4,-2)) + + io.out.pm_alu := pattern(List(28,22,-13,-12,4)) | pattern(List(-30,-29,-27,-25,-6,4)) | + pattern(List(-29,-27,-25,-13,12,-6,4)) | pattern(List(-29,-27,-25,-14,-6,4)) | + pattern(List(13,-5,4)) | pattern(List(4,2)) | pattern(List(-12,-5,4)) + + + io.out.legal := pattern(List(-31,-30,-29,28,-27,-26,-25,-24,-23,22,-21,20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)) | + pattern(List(-31,-30,29,28,-27,-26,-25,-24,-23,-22,21,-20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)) | pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,5,4,-3,-2,1,0)) | - pattern(List(-31,-30,-29,-28,-27,-26,-25,-6,4,-3,1,0)) | - pattern(List(-31,-29,-28,-27,-26,-25,-14,-13,-12,-6,-3,-2,1,0)) | - pattern(List(-31,-29,-28,-27,-26,-25,14,-13,12,-6,4,-3,1,0)) | - pattern(List(-31,-30,-29,-28,-27,-26,-6,5,4,-3,1,0)) | - pattern(List(-14,-13,-12,6,5,-4,-3,1,0)) | - pattern(List(14,6,5,-4,-3,-2,1,0)) | - pattern(List(-12,-6,-5,4,-3,1,0)) | - pattern(List(-14,-13,5,-4,-3,-2,1,0)) | - pattern(List(12,6,5,4,-3,-2,1,0)) | + pattern(List(-31,29,-28,-26,-25,24,-22,-20,-6,-5,4,-3,1,0)) | pattern(List(-31,29,-28,-26,-25,24,-22,-21,-6,-5,4,-3,1,0)) | + pattern(List(-31,29,-28,-26,-25,-23,-22,-20,-6,-5,4,-3,1,0)) | pattern(List(-31,29,-28,-26,-25,-24,-23,-21,-6,-5,4,-3,1,0)) | + pattern(List(-31,-30,-29,-28,-26,25,13,-6,4,-3,1,0)) | pattern(List(-31,-30,-28,-26,-25,-24,-6,-5,4,-3,1,0)) | + pattern(List(-31,-30,-28,-27,-26,-25,14,-12,-6,4,-3,1,0)) | pattern(List(-31,-30,-28,-27,-26,-25,13,-12,-6,4,-3,1,0)) | + pattern(List(-31,-29,-28,-27,-26,-25,-13,-12,-6,4,-3,1,0)) | pattern(List(-31,-28,-27,-26,-25,14,-6,-5,4,-3,1,0)) | + pattern(List(-31,-30,-29,-28,-26,-13,12,5,4,-3,-2,1,0)) | pattern(List(-31,-30,-29,-28,-26,14,-6,5,4,-3,1,0)) | + pattern(List(-31,30,-28,27,-26,-25,-13,12,-6,4,-3,1,0)) | pattern(List(-31,29,-28,27,-26,-25 ,-6,-5,4,-3,1,0)) | + pattern(List(-31,-30,-28,-27,-26,-25,-6,-5,4,-3,1,0)) | pattern(List(-31,-30,-29,-28,-27,-26,-6,5,4,-3,1,0)) | + pattern(List(-14,-13,-12,6,5,-4,-3,1,0)) | pattern(List(-31,-29,-28,-26,-25,14,-6,5,4,-3,1,0)) | + pattern(List(-31,29,-28,-26,-25,-13,12,5,4,-3,-2,1,0)) | pattern(List(14,6,5,-4,-3,-2,1,0)) | + pattern(List(-14,-13,5,-4,-3,-2,1,0)) | pattern(List(-12,-6,-5,4,-3,1,0)) | pattern(List(-13,12,6,5,-3,-2,1,0)) | pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-20,-19,-18,-17,-16,-15,-14,-13,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)) | pattern(List(-31,-30,-29,-28,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)) | - pattern(List(13,6,5,4,-3,-2,1,0)) | - pattern(List(-13,-6,-5,-4,-3,-2,1,0)) | - pattern(List(6,5,-4,3,2,1,0)) | - pattern(List(13,-6,-5,4,-3,1,0)) | - pattern(List(-14,-12,-6,-4,-3,-2,1,0)) | - pattern(List(-6,4,-3,2,1,0)) + pattern(List(13,6,5,4,-3,-2,1,0)) | pattern(List(6,5,-4,3,2,1,0)) | pattern(List(-14,-12,-6,-4,-3,-2,1,0)) | + pattern(List(-13,-6,-5,-4,-3,-2,1,0)) | pattern(List(13,-6,-5,4,-3,1,0)) | pattern(List(-6,4,-3,2,1,0)) + +} +object dec_dec extends App { + (new chisel3.stage.ChiselStage).emitVerilog(new dec_dec_ctl()) } diff --git a/src/main/scala/dec/dec_decode_ctl.scala b/src/main/scala/dec/dec_decode_ctl.scala index 7ef4e7e5..aeaf2437 100644 --- a/src/main/scala/dec/dec_decode_ctl.scala +++ b/src/main/scala/dec/dec_decode_ctl.scala @@ -1,785 +1,925 @@ -//package dec -//import chisel3._ -// -//import scala.collection._ -//import chisel3.util._ -//import include._ -//import lib._ -//import exu._ -//import lsu._ -// -//class dec_decode_ctl extends Module with lib with RequireAsyncReset{ -// val io = IO(new Bundle{ -// val decode_exu = Flipped(new decode_exu) //connection with exu top -// val dec_alu = Flipped(new dec_alu) //connection with alu -// val dec_div = Flipped(new dec_div) //connection with divider -// val dctl_busbuff = Flipped(new dctl_busbuff()) //connection with bus buffer -// val dctl_dma = new dctl_dma //connection with dma -// val dec_aln = Flipped(new aln_dec) //connection with aligner -// val dbg_dctl = new dbg_dctl() //connection with dbg -// val dec_tlu_flush_extint = Input(Bool()) -// val dec_tlu_force_halt = Input(Bool()) // invalidate nonblock load cam on a force halt event -// val dec_i0_inst_wb1 = Output(UInt(32.W)) // 32b instruction at wb+1 for trace encoder -// val dec_i0_pc_wb1 = Output(UInt(31.W)) // 31b pc at wb+1 for trace encoder -// val dec_i0_trigger_match_d = Input(UInt(4.W)) // i0 decode trigger matches -// val dec_tlu_wr_pause_r = Input(Bool()) // pause instruction at r -// val dec_tlu_pipelining_disable = Input(Bool()) // pipeline disable - presync, i0 decode only -// val lsu_trigger_match_m = Input(UInt(4.W)) // lsu trigger matches -// val lsu_pmu_misaligned_m = Input(Bool()) // perf mon: load/store misalign -// val dec_tlu_debug_stall = Input(Bool()) // debug stall decode -// val dec_tlu_flush_leak_one_r = Input(Bool()) // leak1 instruction -// val dec_debug_fence_d = Input(Bool()) // debug fence instruction -// val dec_i0_icaf_d = Input(Bool()) // icache access fault -// val dec_i0_icaf_f1_d = Input(Bool()) // i0 instruction access fault at decode for f1 fetch group -// val dec_i0_icaf_type_d = Input(UInt(2.W)) // i0 instruction access fault type -// val dec_i0_dbecc_d = Input(Bool()) // icache/iccm double-bit error -// val dec_i0_brp = Flipped(Valid(new br_pkt_t)) // branch packet -// val dec_i0_bp_index = Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index -// val dec_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR -// val dec_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag -// val dec_i0_pc_d = Input(UInt(31.W)) // pc -// val lsu_idle_any = Input(Bool()) // lsu idle: if fence instr & !!!!!!!!!!!!!!!!!!!!!!!!!lsu_idle then stall decode -// val lsu_load_stall_any = Input(Bool()) // stall any load at decode -// val lsu_store_stall_any = Input(Bool()) // stall any store at decode6 -// val exu_div_wren = Input(Bool()) // nonblocking divide write enable to GPR. -// val dec_tlu_i0_kill_writeb_wb = Input(Bool()) // I0 is flushed, don't writeback any results to arch state -// val dec_tlu_flush_lower_wb = Input(Bool()) // trap lower flush -// val dec_tlu_i0_kill_writeb_r = Input(Bool()) // I0 is flushed, don't writeback any results to arch state -// val dec_tlu_flush_lower_r = Input(Bool()) // trap lower flush -// val dec_tlu_flush_pause_r = Input(Bool()) // don't clear pause state on initial lower flush -// val dec_tlu_presync_d = Input(Bool()) // CSR read needs to be presync'd -// val dec_tlu_postsync_d = Input(Bool()) // CSR ops that need to be postsync'd -// val dec_i0_pc4_d = Input(Bool()) // inst is 4B inst else 2B -// val dec_csr_rddata_d = Input(UInt(32.W)) // csr read data at wb -// val dec_csr_legal_d = Input(Bool()) // csr indicates legal operation -// val lsu_result_m = Input(UInt(32.W)) // load result -// val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected data for writing gpr's, not for bypassing -// val exu_flush_final = Input(Bool()) // lower flush or i0 flush at X or D -// val dec_i0_instr_d = Input(UInt(32.W)) // inst at decode -// val dec_ib0_valid_d = Input(Bool()) // inst valid at decode -// val free_clk = Input(Clock()) -// val active_clk = Input(Clock()) // clk except for halt / pause -// val clk_override = Input(Bool()) // test stuff -// val dec_i0_rs1_d = Output(UInt(5.W)) // rs1 logical source -// val dec_i0_rs2_d = Output(UInt(5.W)) -// val dec_i0_waddr_r = Output(UInt(5.W)) // i0 logical source to write to gpr's -// val dec_i0_wen_r = Output(Bool()) // i0 write enable -// val dec_i0_wdata_r = Output(UInt(32.W)) // i0 write data -// val lsu_p = Valid(new lsu_pkt_t) // load/store packet -// val div_waddr_wb = Output(UInt(5.W)) // DIV write address to GPR -// val dec_lsu_valid_raw_d = Output(Bool()) -// val dec_lsu_offset_d = Output(UInt(12.W)) -// val dec_csr_wen_unq_d = Output(Bool()) // valid csr with write - for csr legal -// val dec_csr_any_unq_d = Output(Bool()) // valid csr - for csr legal -// val dec_csr_rdaddr_d = Output(UInt(12.W)) // read address for csr -// val dec_csr_wen_r = Output(Bool()) // csr write enable at r -// val dec_csr_wraddr_r = Output(UInt(12.W)) // write address for csr -// val dec_csr_wrdata_r = Output(UInt(32.W)) // csr write data at r -// val dec_csr_stall_int_ff = Output(Bool()) // csr is mie/mstatus -// val dec_tlu_i0_valid_r = Output(Bool()) // i0 valid inst at c -// val dec_tlu_packet_r = Output(new trap_pkt_t) // trap packet -// val dec_tlu_i0_pc_r = Output(UInt(31.W)) // i0 trap pc -// val dec_illegal_inst = Output(UInt(32.W)) // illegal inst -// val dec_pmu_instr_decoded = Output(Bool()) // number of instructions decode this cycle encoded -// val dec_pmu_decode_stall = Output(Bool()) // decode is stalled -// val dec_pmu_presync_stall = Output(Bool()) // decode has presync stall -// val dec_pmu_postsync_stall = Output(Bool()) // decode has postsync stall -// val dec_nonblock_load_wen = Output(Bool()) // write enable for nonblock load -// val dec_nonblock_load_waddr = Output(UInt(5.W)) // logical write addr for nonblock load -// val dec_pause_state = Output(Bool()) // core in pause state -// val dec_pause_state_cg = Output(Bool()) // pause state for clock-gating -// val dec_div_active = Output(Bool()) // non-block divide is active -// val scan_mode = Input(Bool()) -//}) -// //packets zero initialization -// io.decode_exu.mul_p := 0.U.asTypeOf(io.decode_exu.mul_p) -// // Vals defined -// val leak1_i1_stall_in = WireInit(UInt(1.W), 0.U) -// val leak1_i0_stall_in = WireInit(UInt(1.W), 0.U) -// val i0r = Wire(new reg_pkt_t) -// val d_t = Wire(new trap_pkt_t) -// val x_t = Wire(new trap_pkt_t) -// val x_t_in = Wire(new trap_pkt_t) -// val r_t = Wire(new trap_pkt_t) -// val r_t_in = Wire(new trap_pkt_t) -// val d_d = Wire(Valid(new dest_pkt_t)) -// val x_d = Wire(Valid(new dest_pkt_t)) -// val r_d = Wire(Valid(new dest_pkt_t)) -// val r_d_in = Wire(Valid(new dest_pkt_t)) -// val wbd = Wire(Valid(new dest_pkt_t)) -// val i0_d_c = Wire(new class_pkt_t) -// val i0_rs1_class_d = Wire(new class_pkt_t) -// val i0_rs2_class_d = Wire(new class_pkt_t) -// val i0_rs1_depth_d = WireInit(UInt(2.W),0.U) -// val i0_rs2_depth_d = WireInit(UInt(2.W),0.U) -// val cam_wen = WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U) -// val cam = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t))) -// val cam_write = WireInit(UInt(1.W), 0.U) -// val cam_inv_reset_val = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) -// val cam_data_reset_val = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) -// val nonblock_load_write = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) -// val cam_raw = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t))) -// val cam_in = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t))) -// val i0_dp = Wire(new dec_pkt_t) -// val i0_dp_raw = Wire(new dec_pkt_t) -// val i0_rs1bypass = WireInit(UInt(3.W), 0.U) -// val i0_rs2bypass = WireInit(UInt(3.W), 0.U) -// val illegal_lockout = WireInit(UInt(1.W), 0.U) -// val postsync_stall = WireInit(UInt(1.W), 0.U) -// val ps_stall_in = WireInit(UInt(1.W), 0.U) -// val i0_pipe_en = WireInit(UInt(4.W), 0.U) -// val i0_load_block_d = WireInit(UInt(1.W), 0.U) -// val load_ldst_bypass_d = WireInit(UInt(1.W), 0.U) -// val store_data_bypass_d = WireInit(UInt(1.W), 0.U) -// val store_data_bypass_m = WireInit(UInt(1.W), 0.U) -// val tlu_wr_pause_r1 = WireInit(UInt(1.W), 0.U) -// val tlu_wr_pause_r2 = WireInit(UInt(1.W), 0.U) -// val leak1_i1_stall = WireInit(UInt(1.W), 0.U) -// val leak1_i0_stall = WireInit(UInt(1.W), 0.U) -// val pause_state = WireInit(Bool(), 0.B) -// val flush_final_r = WireInit(UInt(1.W), 0.U) -// val illegal_lockout_in = WireInit(UInt(1.W), 0.U) -// val lsu_idle = WireInit(Bool(), 0.B) -// val pause_state_in = WireInit(Bool(), 0.B) -// val leak1_mode = WireInit(UInt(1.W), 0.U) -// val i0_pcall = WireInit(UInt(1.W), 0.U) -// val i0_pja = WireInit(UInt(1.W), 0.U) -// val i0_pret = WireInit(UInt(1.W), 0.U) -// val i0_legal_decode_d = WireInit(UInt(1.W), 0.U) -// val i0_pcall_raw = WireInit(UInt(1.W), 0.U) -// val i0_pja_raw = WireInit(UInt(1.W), 0.U) -// val i0_pret_raw = WireInit(UInt(1.W), 0.U) -// val i0_br_offset = WireInit(UInt(12.W), 0.U) -// val i0_csr_write_only_d = WireInit(UInt(1.W), 0.U) -// val i0_jal = WireInit(UInt(1.W), 0.U) -// val i0_wen_r = WireInit(UInt(1.W), 0.U) -// val i0_x_ctl_en = WireInit(UInt(1.W), 0.U) -// val i0_r_ctl_en = WireInit(UInt(1.W), 0.U) -// val i0_wb_ctl_en = WireInit(UInt(1.W), 0.U) -// val i0_x_data_en = WireInit(UInt(1.W), 0.U) -// val i0_r_data_en = WireInit(UInt(1.W), 0.U) -// val i0_wb_data_en = WireInit(UInt(1.W), 0.U) -// val i0_wb1_data_en = WireInit(UInt(1.W), 0.U) -// val i0_nonblock_load_stall = WireInit(UInt(1.W), 0.U) -// val csr_ren_qual_d = WireInit(Bool(), 0.B) -// val lsu_decode_d = WireInit(UInt(1.W), 0.U) -// val mul_decode_d = WireInit(UInt(1.W), 0.U) -// val div_decode_d = WireInit(UInt(1.W), 0.U) -// val write_csr_data = WireInit(UInt(32.W),0.U) -// val i0_result_corr_r = WireInit(UInt(32.W),0.U) -// val presync_stall = WireInit(UInt(1.W), 0.U) -// val i0_nonblock_div_stall = WireInit(UInt(1.W), 0.U) -// val debug_fence = WireInit(Bool(), 0.B) -// val i0_immed_d = WireInit(UInt(32.W), 0.U) -// val i0_result_x = WireInit(UInt(32.W), 0.U) -// val i0_result_r = WireInit(UInt(32.W), 0.U) -// ////////////////////////////////////////////////////////////////////// -// // Start - Data gating {{ -// val data_gate_en = (io.dec_tlu_wr_pause_r ^ tlu_wr_pause_r1 ) | // replaces free_clk -// (tlu_wr_pause_r1 ^ tlu_wr_pause_r2 ) | // replaces free_clk -// (io.dec_tlu_flush_extint ^ io.decode_exu.dec_extint_stall) | -// (leak1_i1_stall_in ^ leak1_i1_stall ) | // replaces free_clk -// (leak1_i0_stall_in ^ leak1_i0_stall ) | // replaces free_clk -// (pause_state_in ^ pause_state ) | // replaces free_clk -// (ps_stall_in ^ postsync_stall ) | // replaces free_clk -// (io.exu_flush_final ^ flush_final_r ) | // replaces free_clk -// (illegal_lockout_in ^ illegal_lockout ) // replaces active_clk -// -// -// val data_gate_clk = rvclkhdr(clock,data_gate_en.asBool(),io.scan_mode) -// // End - Data gating -// -// val i0_brp_valid = io.dec_i0_brp.valid & !leak1_mode -// io.decode_exu.dec_i0_predict_p_d.bits.misp := 0.U -// io.decode_exu.dec_i0_predict_p_d.bits.ataken := 0.U -// io.decode_exu.dec_i0_predict_p_d.bits.boffset := 0.U -// io.decode_exu.dec_i0_predict_p_d.bits.pcall := i0_pcall // don't mark as pcall if branch error -// io.decode_exu.dec_i0_predict_p_d.bits.pja := i0_pja -// io.decode_exu.dec_i0_predict_p_d.bits.pret := i0_pret -// io.decode_exu.dec_i0_predict_p_d.bits.prett := io.dec_i0_brp.bits.prett -// io.decode_exu.dec_i0_predict_p_d.bits.pc4 := io.dec_i0_pc4_d -// io.decode_exu.dec_i0_predict_p_d.bits.hist := io.dec_i0_brp.bits.hist -// io.decode_exu.dec_i0_predict_p_d.valid := i0_brp_valid & i0_legal_decode_d -// val i0_notbr_error = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw) -// -// // no toffset error for a pret -// val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.bits.hist(1) & (io.dec_i0_brp.bits.toffset =/= i0_br_offset) & !i0_pret_raw -// val i0_ret_error = i0_brp_valid & io.dec_i0_brp.bits.ret & !i0_pret_raw; -// val i0_br_error = io.dec_i0_brp.bits.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error -// io.decode_exu.dec_i0_predict_p_d.bits.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode -// io.decode_exu.dec_i0_predict_p_d.bits.br_start_error := io.dec_i0_brp.bits.br_start_error & i0_legal_decode_d & !leak1_mode -// io.decode_exu.i0_predict_index_d := io.dec_i0_bp_index -// io.decode_exu.i0_predict_btag_d := io.dec_i0_bp_btag -// val i0_br_error_all = (i0_br_error | io.dec_i0_brp.bits.br_start_error) & !leak1_mode -// io.decode_exu.dec_i0_predict_p_d.bits.toffset := i0_br_offset -// io.decode_exu.i0_predict_fghr_d := io.dec_i0_bp_fghr -// io.decode_exu.dec_i0_predict_p_d.bits.way := io.dec_i0_brp.bits.way -// // end -// -// // on br error turn anything into a nop -// // on i0 instruction fetch access fault turn anything into a nop -// // nop => alu rs1 imm12 rd lor -// val i0_icaf_d = io.dec_i0_icaf_d | io.dec_i0_dbecc_d -// val i0_instr_error = i0_icaf_d; -// i0_dp := i0_dp_raw -// when((i0_br_error_all | i0_instr_error).asBool){ -// i0_dp := 0.U.asTypeOf(i0_dp) -// i0_dp.alu := 1.B -// i0_dp.rs1 := 1.B -// i0_dp.rs2 := 1.B -// i0_dp.lor := 1.B -// i0_dp.legal := 1.B -// i0_dp.postsync := 1.B -// } -// -// val i0 = io.dec_i0_instr_d -// io.decode_exu.dec_i0_select_pc_d := i0_dp.pc -// -// // branches that can be predicted -// val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret; -// val i0_predict_nt = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br -// val i0_predict_t = (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br -// val i0_ap_pc2 = !io.dec_i0_pc4_d -// val i0_ap_pc4 = io.dec_i0_pc4_d -// io.decode_exu.i0_ap.predict_nt := i0_predict_nt -// io.decode_exu.i0_ap.predict_t := i0_predict_t -// -// io.decode_exu.i0_ap.add := i0_dp.add -// io.decode_exu.i0_ap.sub := i0_dp.sub -// io.decode_exu.i0_ap.land := i0_dp.land -// io.decode_exu.i0_ap.lor := i0_dp.lor -// io.decode_exu.i0_ap.lxor := i0_dp.lxor -// io.decode_exu.i0_ap.sll := i0_dp.sll -// io.decode_exu.i0_ap.srl := i0_dp.srl -// io.decode_exu.i0_ap.sra := i0_dp.sra -// io.decode_exu.i0_ap.slt := i0_dp.slt -// io.decode_exu.i0_ap.unsign := i0_dp.unsign -// io.decode_exu.i0_ap.beq := i0_dp.beq -// io.decode_exu.i0_ap.bne := i0_dp.bne -// io.decode_exu.i0_ap.blt := i0_dp.blt -// io.decode_exu.i0_ap.bge := i0_dp.bge -// io.decode_exu.i0_ap.csr_write := i0_csr_write_only_d -// io.decode_exu.i0_ap.csr_imm := i0_dp.csr_imm -// io.decode_exu.i0_ap.jal := i0_jal -// -// // non block load cam logic -// // val found=Wire(UInt(1.W)) -// cam_wen := Mux1H((0 until LSU_NUM_NBLOAD).map(i=>(0 to i).map(j=> if(i==j) !cam(j).valid else cam(j).valid).reduce(_.asBool&_.asBool).asBool -> (cam_write << i))) -// -// cam_write := io.dctl_busbuff.lsu_nonblock_load_valid_m -// val cam_write_tag = io.dctl_busbuff.lsu_nonblock_load_tag_m(LSU_NUM_NBLOAD_WIDTH-1,0) -// -// val cam_inv_reset = io.dctl_busbuff.lsu_nonblock_load_inv_r -// val cam_inv_reset_tag = io.dctl_busbuff.lsu_nonblock_load_inv_tag_r -// -// val cam_data_reset = io.dctl_busbuff.lsu_nonblock_load_data_valid | io.dctl_busbuff.lsu_nonblock_load_data_error -// val cam_data_reset_tag = io.dctl_busbuff.lsu_nonblock_load_data_tag -// -// val nonblock_load_rd = Mux(x_d.bits.i0load.asBool, x_d.bits.i0rd, 0.U(5.W)) // rd data -// val load_data_tag = io.dctl_busbuff.lsu_nonblock_load_data_tag -// // case of multiple loads to same dest ie. x1 ... you have to invalidate the older one -// // don't writeback a nonblock load -// val nonblock_load_valid_m_delay=withClock(io.active_clk){RegEnable(io.dctl_busbuff.lsu_nonblock_load_valid_m,0.U, i0_r_ctl_en.asBool)} -// val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.bits.i0load -// for(i <- 0 until LSU_NUM_NBLOAD){ -// cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).bits.tag) & cam(i).valid -// cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).bits.tag) & cam_raw(i).valid -// cam_in(i):=0.U.asTypeOf(cam(0)) -// cam(i):=cam_raw(i) -// -// when(cam_data_reset_val(i).asBool){ -// cam(i).valid := 0.U(1.W) -// } -// when(cam_wen(i).asBool){ -// cam_in(i).valid := 1.U(1.W) -// cam_in(i).bits.wb := 0.U(1.W) -// cam_in(i).bits.tag := cam_write_tag -// cam_in(i).bits.rd := nonblock_load_rd -// }.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.bits.i0rd === cam(i).bits.rd) && cam(i).bits.wb.asBool)){ -// cam_in(i).valid := 0.U -// }.otherwise{ -// cam_in(i) := cam(i) -// } -// when(nonblock_load_valid_m_delay===1.U && (io.dctl_busbuff.lsu_nonblock_load_inv_tag_r === cam(i).bits.tag) && cam(i).valid===1.U){ -// cam_in(i).bits.wb := 1.U -// } -// // force debug halt forces cam valids to 0; highest priority -// when(io.dec_tlu_force_halt){ -// cam_in(i).valid := 0.U -// } -// -// cam_raw(i):=withClock(io.free_clk){RegNext(cam_in(i),0.U.asTypeOf(cam(0)))} -// nonblock_load_write(i) := (load_data_tag === cam_raw(i).bits.tag) & cam_raw(i).valid -// } -// -// io.dec_nonblock_load_waddr:=0.U(5.W) -// // cancel if any younger inst (including another nonblock) committing this cycle -// val nonblock_load_cancel = ((r_d_in.bits.i0rd === io.dec_nonblock_load_waddr) & i0_wen_r) -// io.dec_nonblock_load_wen := (io.dctl_busbuff.lsu_nonblock_load_data_valid && nonblock_load_write.reduce(_|_).asBool && !nonblock_load_cancel) -// val i0_nonblock_boundary_stall = ((nonblock_load_rd===i0r.rs1) & io.dctl_busbuff.lsu_nonblock_load_valid_m & io.decode_exu.dec_i0_rs1_en_d)|((nonblock_load_rd===i0r.rs2) & io.dctl_busbuff.lsu_nonblock_load_valid_m & io.decode_exu.dec_i0_rs2_en_d) -// -// i0_nonblock_load_stall := i0_nonblock_boundary_stall -// -// val cal_temp= for(i <-0 until LSU_NUM_NBLOAD) yield ((Fill(5,nonblock_load_write(i)) & cam(i).bits.rd), io.decode_exu.dec_i0_rs1_en_d & cam(i).valid & (cam(i).bits.rd === i0r.rs1), io.decode_exu.dec_i0_rs2_en_d & cam(i).valid & (cam(i).bits.rd === i0r.rs2)) -// val (waddr, ld_stall_1, ld_stall_2) = (cal_temp.map(_._1).reduce(_|_) , cal_temp.map(_._2).reduce(_|_), cal_temp.map(_._3).reduce(_|_) ) -// io.dec_nonblock_load_waddr:=waddr -// i0_nonblock_load_stall:=ld_stall_1 | ld_stall_2 | i0_nonblock_boundary_stall -// //i0_nonblock_load_stall:=ld_stall_2 -// -// // end non block load cam logic -// -// // pmu start -// -// val csr_read = csr_ren_qual_d -// val csr_write = io.dec_csr_wen_unq_d -// val i0_br_unpred = i0_dp.jal & !i0_predict_br -// -// // the classes must be mutually exclusive with one another -// import inst_pkt_t._ -// d_t.pmu_i0_itype :=Fill(4,i0_legal_decode_d) & MuxCase(NULL ,Array( -// i0_dp.jal -> JAL, -// i0_dp.condbr -> CONDBR, -// i0_dp.mret -> MRET, -// i0_dp.fence_i -> FENCEI, -// i0_dp.fence -> FENCE, -// i0_dp.ecall -> ECALL, -// i0_dp.ebreak -> EBREAK, -// ( csr_read & csr_write).asBool -> CSRRW, -// (!csr_read & csr_write).asBool -> CSRWRITE, -// ( csr_read & !csr_write).asBool -> CSRREAD, -// i0_dp.pm_alu -> ALU, -// i0_dp.store -> STORE, -// i0_dp.load -> LOAD, -// i0_dp.mul -> MUL)) -// // end pmu -// -// val i0_dec =Module(new dec_dec_ctl) -// i0_dec.io.ins:= i0 -// i0_dp_raw:=i0_dec.io.out -// -// lsu_idle:=withClock(io.active_clk){RegNext(io.lsu_idle_any,0.U)} -// -// // can't make this clock active_clock -// leak1_i1_stall_in := (io.dec_tlu_flush_leak_one_r | (leak1_i1_stall & !io.dec_tlu_flush_lower_r)) -// leak1_i1_stall := withClock(data_gate_clk){RegNext(leak1_i1_stall_in,0.U)} -// leak1_mode := leak1_i1_stall -// leak1_i0_stall_in := ((io.dec_aln.dec_i0_decode_d & leak1_i1_stall) | (leak1_i0_stall & !io.dec_tlu_flush_lower_r)) -// leak1_i0_stall := withClock(data_gate_clk){RegNext(leak1_i0_stall_in,0.U)} -// -// // 12b jal's can be predicted - these are calls -// -// val i0_pcall_imm = Cat(i0(31),i0(19,12),i0(20),i0(30,21)) -// val i0_pcall_12b_offset = Mux(i0_pcall_imm(11).asBool, i0_pcall_imm(19,12) === 0xff.U , i0_pcall_imm(19,12) === 0.U(8.W)) -// val i0_pcall_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & (i0r.rd === 1.U(5.W) | i0r.rd === 5.U(5.W)) -// val i0_pja_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & !(i0r.rd === 1.U(5.W) | i0r.rd === 5.U(5.W)) -// i0_pcall_raw := i0_dp_raw.jal & i0_pcall_case // this includes ja -// i0_pcall := i0_dp.jal & i0_pcall_case -// i0_pja_raw := i0_dp_raw.jal & i0_pja_case -// i0_pja := i0_dp.jal & i0_pja_case -// i0_br_offset := Mux((i0_pcall_raw | i0_pja_raw).asBool, i0_pcall_imm(11,0) , Cat(i0(31),i0(7),i0(30,25),i0(11,8))) -// // jalr with rd==0, rs1==1 or rs1==5 is a ret -// val i0_pret_case = (i0_dp_raw.jal & i0_dp_raw.imm12 & (i0r.rd === 0.U(5.W)) & (i0r.rs1===1.U(5.W) | i0r.rs1 === 5.U(5.W))) -// i0_pret_raw := i0_dp_raw.jal & i0_pret_case -// i0_pret := i0_dp.jal & i0_pret_case -// i0_jal := i0_dp.jal & !i0_pcall_case & !i0_pja_case & !i0_pret_case -// /////////////////////////////////////////////////////////////////////////////////////////////////////////// -// -// io.dec_div.div_p.valid := div_decode_d -// io.dec_div.div_p.bits.unsign := i0_dp.unsign -// io.dec_div.div_p.bits.rem := i0_dp.rem -// -// io.decode_exu.mul_p.valid := mul_decode_d -// io.decode_exu.mul_p.bits.rs1_sign := i0_dp.rs1_sign -// io.decode_exu.mul_p.bits.rs2_sign := i0_dp.rs2_sign -// io.decode_exu.mul_p.bits.low := i0_dp.low -// -// io.decode_exu.dec_extint_stall := withClock(data_gate_clk){RegNext(io.dec_tlu_flush_extint,0.U)} -// -// io.lsu_p := 0.U.asTypeOf(io.lsu_p) -// when (io.decode_exu.dec_extint_stall){ -// io.lsu_p.bits.load := 1.U(1.W) -// io.lsu_p.bits.word := 1.U(1.W) -// io.lsu_p.bits.fast_int := 1.U(1.W) -// io.lsu_p.valid := 1.U(1.W) -// }.otherwise { -// io.lsu_p.valid := lsu_decode_d -// io.lsu_p.bits.load := i0_dp.load -// io.lsu_p.bits.store := i0_dp.store -// io.lsu_p.bits.by := i0_dp.by -// io.lsu_p.bits.half := i0_dp.half -// io.lsu_p.bits.word := i0_dp.word -// io.lsu_p.bits.load_ldst_bypass_d := load_ldst_bypass_d -// io.lsu_p.bits.store_data_bypass_d := store_data_bypass_d -// io.lsu_p.bits.store_data_bypass_m := store_data_bypass_m -// io.lsu_p.bits.unsign := i0_dp.unsign -// } -// -// ////////////////////////////////////// -// io.dec_alu.dec_csr_ren_d := i0_dp.csr_read //H: assigning csr read enable signal decoded from decode_ctl going as input to EXU -// csr_ren_qual_d := i0_dp.csr_read & i0_legal_decode_d.asBool //csr_ren_qual_d assigned as csr_read above -// -// val i0_csr_write = i0_dp.csr_write & !io.dec_debug_fence_d -// val csr_clr_d = i0_dp.csr_clr & i0_legal_decode_d.asBool -// val csr_set_d = i0_dp.csr_set & i0_legal_decode_d.asBool -// val csr_write_d = i0_csr_write & i0_legal_decode_d.asBool -// -// i0_csr_write_only_d := i0_csr_write & !i0_dp.csr_read -// io.dec_csr_wen_unq_d := (i0_dp.csr_clr | i0_dp.csr_set | i0_csr_write) // for csr legal, can't write read-only csr -// //dec_csr_wen_unq_d assigned as csr_write above -// -// io.dec_csr_rdaddr_d := i0(31,20) -// io.dec_csr_wraddr_r := r_d.bits.csrwaddr //r_d is a dest_pkt -// -// // make sure csr doesn't write same cycle as dec_tlu_flush_lower_wb -// // also use valid so it's flushable -// io.dec_csr_wen_r := r_d.bits.csrwen & r_d.valid & !io.dec_tlu_i0_kill_writeb_r; -// -// // If we are writing MIE or MSTATUS, hold off the external interrupt for a cycle on the write. -// io.dec_csr_stall_int_ff := ((r_d.bits.csrwaddr === "h300".U) | (r_d.bits.csrwaddr === "h304".U)) & r_d.bits.csrwen & r_d.valid & !io.dec_tlu_i0_kill_writeb_wb; -// -// val csr_read_x = withClock(io.active_clk){RegNext(csr_ren_qual_d,init=0.B)} -// val csr_clr_x = withClock(io.active_clk){RegNext(csr_clr_d, init=0.B)} -// val csr_set_x = withClock(io.active_clk){RegNext(csr_set_d, init=0.B)} -// val csr_write_x = withClock(io.active_clk){RegNext(csr_write_d, init=0.B)} -// val csr_imm_x = withClock(io.active_clk){RegNext(i0_dp.csr_imm, init=0.U)} -// -// // perform the update operation if any -// val csrimm_x = rvdffe(i0(19,15),i0_x_data_en.asBool,clock,io.scan_mode) -// val csr_rddata_x = rvdffe(io.dec_csr_rddata_d,i0_x_data_en.asBool,clock,io.scan_mode) -// -// val csr_mask_x = Mux1H(Seq( -// csr_imm_x.asBool -> Cat(repl(27,0.U),csrimm_x(4,0)), -// !csr_imm_x.asBool -> io.decode_exu.exu_csr_rs1_x)) -// -// val write_csr_data_x = Mux1H(Seq( -// csr_clr_x -> (csr_rddata_x & (~csr_mask_x).asUInt), -// csr_set_x -> (csr_rddata_x | csr_mask_x), -// csr_write_x -> ( csr_mask_x))) -// // pause instruction -// val clear_pause = (io.dec_tlu_flush_lower_r & !io.dec_tlu_flush_pause_r) | (pause_state & (write_csr_data === Cat(Fill(31,0.U),write_csr_data(0)))) // if 0 or 1 then exit pause state - 1 cycle pause -// pause_state_in := (io.dec_tlu_wr_pause_r | pause_state) & !clear_pause -// pause_state := withClock(data_gate_clk){RegNext(pause_state_in, 0.U)} -// io.dec_pause_state := pause_state -// tlu_wr_pause_r1 := withClock(data_gate_clk){RegNext(io.dec_tlu_wr_pause_r, 0.U)} -// tlu_wr_pause_r2 := withClock(data_gate_clk){RegNext(tlu_wr_pause_r1, 0.U)} -// //pause for clock gating -// io.dec_pause_state_cg := (pause_state & (!tlu_wr_pause_r1 && !tlu_wr_pause_r2)) -// // end pause -// -// val write_csr_data_in = Mux(pause_state,(write_csr_data - 1.U(32.W)), -// Mux(io.dec_tlu_wr_pause_r,io.dec_csr_wrdata_r,write_csr_data_x)) -// val csr_data_wen = ((csr_clr_x | csr_set_x | csr_write_x) & csr_read_x) | io.dec_tlu_wr_pause_r | pause_state -// write_csr_data := rvdffe(write_csr_data_in,csr_data_wen,clock,io.scan_mode) -// -// // will hold until write-back at which time the CSR will be updated while GPR is possibly written with prior CSR -// val pause_stall = pause_state -// -// // for csr write only data is produced by the alu -// io.dec_csr_wrdata_r := Mux(r_d.bits.csrwonly.asBool,i0_result_corr_r,write_csr_data) -// -// val prior_csr_write = x_d.bits.csrwonly | r_d.bits.csrwonly | wbd.bits.csrwonly; -// -// val debug_fence_i = io.dec_debug_fence_d & io.dbg_dctl.dbg_cmd_wrdata(0) -// val debug_fence_raw = io.dec_debug_fence_d & io.dbg_dctl.dbg_cmd_wrdata(1) -// debug_fence := debug_fence_raw | debug_fence_i -// -// // some CSR reads need to be presync'd -// val i0_presync = i0_dp.presync | io.dec_tlu_presync_d | debug_fence_i | debug_fence_raw | io.dec_tlu_pipelining_disable // both fence's presync -// -// // some CSR writes need to be postsync'd -// val i0_postsync = i0_dp.postsync | io.dec_tlu_postsync_d | debug_fence_i | (i0_csr_write_only_d & (i0(31,20) === "h7c2".U)) -// -// val any_csr_d = i0_dp.csr_read | i0_csr_write -// io.dec_csr_any_unq_d := any_csr_d -// val i0_legal = i0_dp.legal & (!any_csr_d | io.dec_csr_legal_d) -// val i0_inst_d = Mux(io.dec_i0_pc4_d,i0,Cat(repl(16,0.U), io.dec_aln.ifu_i0_cinst)) -// // illegal inst handling -// -// val shift_illegal = io.dec_aln.dec_i0_decode_d & !i0_legal//lm: valid but not legal -// val illegal_inst_en = shift_illegal & !illegal_lockout -// io.dec_illegal_inst := rvdffe(i0_inst_d,illegal_inst_en,clock,io.scan_mode) -// illegal_lockout_in := (shift_illegal | illegal_lockout) & !flush_final_r -// illegal_lockout := withClock(data_gate_clk){RegNext(illegal_lockout_in, 0.U)} -// val i0_div_prior_div_stall = i0_dp.div & io.dec_div_active -// //stalls signals -// val i0_block_raw_d = (i0_dp.csr_read & prior_csr_write) | io.decode_exu.dec_extint_stall | pause_stall | -// leak1_i0_stall | io.dec_tlu_debug_stall | postsync_stall | presync_stall | -// ((i0_dp.fence | debug_fence) & !lsu_idle) | i0_nonblock_load_stall | -// i0_load_block_d | i0_nonblock_div_stall | i0_div_prior_div_stall -// -// val i0_store_stall_d = i0_dp.store & (io.lsu_store_stall_any | io.dctl_dma.dma_dccm_stall_any) -// val i0_load_stall_d = i0_dp.load & (io.lsu_load_stall_any | io.dctl_dma.dma_dccm_stall_any) -// val i0_block_d = i0_block_raw_d | i0_store_stall_d | i0_load_stall_d -// val i0_exublock_d = i0_block_raw_d -// -// //decode valid -// io.dec_aln.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r -// val i0_exudecode_d = io.dec_ib0_valid_d & !i0_exublock_d & !io.dec_tlu_flush_lower_r & !flush_final_r -// val i0_exulegal_decode_d = i0_exudecode_d & i0_legal -// -// // performance monitor signals -// io.dec_pmu_instr_decoded := io.dec_aln.dec_i0_decode_d -// io.dec_pmu_decode_stall := io.dec_ib0_valid_d & !io.dec_aln.dec_i0_decode_d -// io.dec_pmu_postsync_stall := postsync_stall.asBool -// io.dec_pmu_presync_stall := presync_stall.asBool -// -// val prior_inflight_x = x_d.valid -// val prior_inflight_wb = r_d.valid -// val prior_inflight = prior_inflight_x | prior_inflight_wb -// val prior_inflight_eff = Mux(i0_dp.div,prior_inflight_x,prior_inflight) -// -// presync_stall := (i0_presync & prior_inflight_eff) -// postsync_stall := withClock(data_gate_clk){RegNext(ps_stall_in, 0.U)} -// // illegals will postsync -// ps_stall_in := (io.dec_aln.dec_i0_decode_d & (i0_postsync | !i0_legal) ) | ( postsync_stall & prior_inflight_x) -// -// io.dec_alu.dec_i0_alu_decode_d := i0_exulegal_decode_d & i0_dp.alu -// -// lsu_decode_d := i0_legal_decode_d & i0_dp.lsu -// mul_decode_d := i0_exulegal_decode_d & i0_dp.mul -// div_decode_d := i0_exulegal_decode_d & i0_dp.div -// -// io.dec_tlu_i0_valid_r := r_d.valid & !io.dec_tlu_flush_lower_wb -// -// //traps for TLU (tlu stuff) -// d_t.legal := i0_legal_decode_d -// d_t.icaf := i0_icaf_d & i0_legal_decode_d // dbecc is icaf exception -// d_t.icaf_f1 := io.dec_i0_icaf_f1_d & i0_legal_decode_d // this includes icaf and dbecc -// d_t.icaf_type := io.dec_i0_icaf_type_d -// -// d_t.fence_i := (i0_dp.fence_i | debug_fence_i) & i0_legal_decode_d -// -// // put pmu info into the trap packet -// d_t.pmu_i0_br_unpred := i0_br_unpred -// d_t.pmu_divide := 0.U(1.W) -// d_t.pmu_lsu_misaligned := 0.U(1.W) -// -// d_t.i0trigger := io.dec_i0_trigger_match_d & repl(4,io.dec_aln.dec_i0_decode_d) -// -// -// x_t := rvdffe(d_t,i0_x_ctl_en.asBool,clock,io.scan_mode) -// -// x_t_in := x_t -// x_t_in.i0trigger := x_t.i0trigger & ~(repl(4,io.dec_tlu_flush_lower_wb)) -// -// r_t := rvdffe(x_t_in,i0_x_ctl_en.asBool,clock,io.scan_mode) -// val lsu_trigger_match_r = RegNext(io.lsu_trigger_match_m, 0.U) -// val lsu_pmu_misaligned_r = RegNext(io.lsu_pmu_misaligned_m, 0.U) -// -// r_t_in := r_t -// -// r_t_in.i0trigger := (repl(4,(r_d.bits.i0load | r_d.bits.i0store)) & lsu_trigger_match_r) | r_t.i0trigger -// r_t_in.pmu_lsu_misaligned := lsu_pmu_misaligned_r // only valid if a load/store is valid in DC3 stage -// -// when (io.dec_tlu_flush_lower_wb.asBool) {r_t_in := 0.U.asTypeOf(r_t_in) } -// -// io.dec_tlu_packet_r := r_t_in -// io.dec_tlu_packet_r.pmu_divide := r_d.bits.i0div & r_d.valid -// // end tlu stuff -// -// flush_final_r := withClock(data_gate_clk){RegNext(io.exu_flush_final, 0.U)} -// -// io.dec_aln.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r -// -// i0r.rs1 := i0(19,15) //H: assigning reg packets the instructions bits -// i0r.rs2 := i0(24,20) -// i0r.rd := i0(11,7) -// -// io.decode_exu.dec_i0_rs1_en_d := i0_dp.rs1 & (i0r.rs1 =/= 0.U(5.W)) // if rs1_en=0 then read will be all 0's -// io.decode_exu.dec_i0_rs2_en_d := i0_dp.rs2 & (i0r.rs2 =/= 0.U(5.W)) -// val i0_rd_en_d = i0_dp.rd & (i0r.rd =/= 0.U(5.W)) -// io.dec_i0_rs1_d := i0r.rs1//H:assiging packets to output signals leading to gprfile -// io.dec_i0_rs2_d := i0r.rs2 -// -// val i0_jalimm20 = i0_dp.jal & i0_dp.imm20 // H:jal (used at line 915) -// val i0_uiimm20 = !i0_dp.jal & i0_dp.imm20 -// -// io.decode_exu.dec_i0_immed_d := Mux1H(Seq( -// i0_dp.csr_read -> io.dec_csr_rddata_d, -// !i0_dp.csr_read -> i0_immed_d)) -// -// i0_immed_d := Mux1H(Seq( -// i0_dp.imm12 -> Cat(repl(20,i0(31)),i0(31,20)), // jalr -// i0_dp.shimm5 -> Cat(repl(27,0.U),i0(24,20)), -// i0_jalimm20 -> Cat(repl(12,i0(31)),i0(19,12),i0(20),i0(30,21),0.U), -// i0_uiimm20 -> Cat(i0(31,12),repl(12,0.U)), -// (i0_csr_write_only_d & i0_dp.csr_imm).asBool -> Cat(repl(27,0.U),i0(19,15)))) // for csr's that only write -// -// i0_legal_decode_d := io.dec_aln.dec_i0_decode_d & i0_legal -// -// i0_d_c.mul := i0_dp.mul & i0_legal_decode_d -// i0_d_c.load := i0_dp.load & i0_legal_decode_d -// i0_d_c.alu := i0_dp.alu & i0_legal_decode_d -// -// val i0_x_c = withClock(io.active_clk){RegEnable(i0_d_c,0.U.asTypeOf(i0_d_c), i0_x_ctl_en.asBool)} -// val i0_r_c = withClock(io.active_clk){RegEnable(i0_x_c,0.U.asTypeOf(i0_x_c), i0_r_ctl_en.asBool)} -// i0_pipe_en := Cat(io.dec_aln.dec_i0_decode_d,withClock(io.active_clk){RegNext(i0_pipe_en(3,1), init=0.U)}) -// -// i0_x_ctl_en := (i0_pipe_en(3,2).orR | io.clk_override) -// i0_r_ctl_en := (i0_pipe_en(2,1).orR | io.clk_override) -// i0_wb_ctl_en := (i0_pipe_en(1,0).orR | io.clk_override) -// i0_x_data_en := ( i0_pipe_en(3) | io.clk_override) -// i0_r_data_en := ( i0_pipe_en(2) | io.clk_override) -// i0_wb_data_en := ( i0_pipe_en(1) | io.clk_override) -// i0_wb1_data_en := ( i0_pipe_en(0) | io.clk_override) -// -// io.decode_exu.dec_data_en := Cat(i0_x_data_en, i0_r_data_en) -// io.decode_exu.dec_ctl_en := Cat(i0_x_ctl_en, i0_r_ctl_en) -// -// d_d.bits.i0rd := i0r.rd -// d_d.bits.i0v := i0_rd_en_d & i0_legal_decode_d -// d_d.valid := io.dec_aln.dec_i0_decode_d // has flush_final_r -// -// d_d.bits.i0load := i0_dp.load & i0_legal_decode_d -// d_d.bits.i0store := i0_dp.store & i0_legal_decode_d -// d_d.bits.i0div := i0_dp.div & i0_legal_decode_d -// -// d_d.bits.csrwen := io.dec_csr_wen_unq_d & i0_legal_decode_d -// d_d.bits.csrwonly := i0_csr_write_only_d & io.dec_aln.dec_i0_decode_d -// d_d.bits.csrwaddr := i0(31,20) -// -// x_d := rvdffe(d_d, i0_x_ctl_en.asBool,clock,io.scan_mode) -// val x_d_in = Wire(Valid(new dest_pkt_t)) -// x_d_in := x_d -// x_d_in.bits.i0v := x_d.bits.i0v & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r -// x_d_in.valid := x_d.valid & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r -// -// r_d := rvdffe(x_d_in,i0_r_ctl_en.asBool,clock,io.scan_mode) -// r_d_in := r_d -// r_d_in.bits.i0rd := r_d.bits.i0rd -// -// r_d_in.bits.i0v := (r_d.bits.i0v & !io.dec_tlu_flush_lower_wb) -// r_d_in.valid := (r_d.valid & !io.dec_tlu_flush_lower_wb) -// r_d_in.bits.i0load := r_d.bits.i0load & !io.dec_tlu_flush_lower_wb -// r_d_in.bits.i0store := r_d.bits.i0store & !io.dec_tlu_flush_lower_wb -// -// wbd := rvdffe(r_d_in,i0_wb_ctl_en.asBool,clock,io.scan_mode) -// -// io.dec_i0_waddr_r := r_d_in.bits.i0rd -// i0_wen_r := r_d_in.bits.i0v & !io.dec_tlu_i0_kill_writeb_r -// io.dec_i0_wen_r := i0_wen_r & !r_d_in.bits.i0div & !i0_load_kill_wen_r // don't write a nonblock load 1st time down the pipe -// io.dec_i0_wdata_r := i0_result_corr_r -// -// val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode) -// if ( LOAD_TO_USE_PLUS1) { -// i0_result_x := io.decode_exu.exu_i0_result_x -// i0_result_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_m, i0_result_r_raw) -// } -// else { -// i0_result_x := Mux((x_d.bits.i0v & x_d.bits.i0load).asBool,io.lsu_result_m,io.decode_exu.exu_i0_result_x) -// i0_result_r := i0_result_r_raw -// } -// -// // correct lsu load data - don't use for bypass, do pass down the pipe -// i0_result_corr_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_corr_r,i0_result_r_raw) -// io.dec_alu.dec_i0_br_immed_d := Mux((io.decode_exu.i0_ap.predict_nt & !i0_dp.jal).asBool,i0_br_offset,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2)) -// val last_br_immed_d = WireInit(UInt(12.W),0.U) -// last_br_immed_d := Mux((io.decode_exu.i0_ap.predict_nt).asBool,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2),i0_br_offset) -// val last_br_immed_x = WireInit(UInt(12.W),0.U) -// last_br_immed_x := rvdffe(last_br_immed_d,i0_x_data_en.asBool,clock,io.scan_mode) -// -// // divide stuff -// -// val div_e1_to_r = (x_d.bits.i0div & x_d.valid) | (r_d.bits.i0div & r_d.valid) -// -// val div_flush = (x_d.bits.i0div & x_d.valid & (x_d.bits.i0rd === 0.U(5.W))) | -// (x_d.bits.i0div & x_d.valid & io.dec_tlu_flush_lower_r ) | -// (r_d.bits.i0div & r_d.valid & io.dec_tlu_flush_lower_r & io.dec_tlu_i0_kill_writeb_r) -// -// // cancel if any younger inst committing this cycle to same dest as nonblock divide -// -// val nonblock_div_cancel = (io.dec_div_active & div_flush) | -// (io.dec_div_active & !div_e1_to_r & (r_d.bits.i0rd === io.div_waddr_wb) & i0_wen_r) -// -// io.dec_div.dec_div_cancel := nonblock_div_cancel.asBool -// val i0_div_decode_d = i0_legal_decode_d & i0_dp.div -// -// val div_active_in = i0_div_decode_d | (io.dec_div_active & !io.exu_div_wren & !nonblock_div_cancel) -// -// io.dec_div_active := withClock(io.free_clk){RegNext(div_active_in, 0.U)} -// -// // nonblocking div scheme -// i0_nonblock_div_stall := (io.decode_exu.dec_i0_rs1_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs1)) | -// (io.decode_exu.dec_i0_rs2_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs2)) -// -// io.div_waddr_wb := RegEnable(i0r.rd,0.U,i0_div_decode_d.asBool) -// ///div end -// -// //for tracing instruction -// val i0_wb_en = i0_wb_data_en -// val i0_wb1_en = i0_wb1_data_en -// -// val div_inst = rvdffe(i0_inst_d(24,7),i0_div_decode_d.asBool,clock,io.scan_mode) -// val i0_inst_x = rvdffe(i0_inst_d,i0_x_data_en.asBool,clock,io.scan_mode) -// val i0_inst_r = rvdffe(i0_inst_x,i0_r_data_en.asBool,clock,io.scan_mode) -// val i0_inst_wb_in = i0_inst_r -// val i0_inst_wb = rvdffe(i0_inst_wb_in,i0_wb_en.asBool,clock,io.scan_mode) -// io.dec_i0_inst_wb1 := rvdffe(i0_inst_wb,i0_wb1_en.asBool,clock,io.scan_mode) -// val i0_pc_wb = rvdffe(io.dec_tlu_i0_pc_r,i0_wb_en.asBool,clock,io.scan_mode) -// -// io.dec_i0_pc_wb1 := rvdffe(i0_pc_wb,i0_wb1_en.asBool,clock,io.scan_mode) -// val dec_i0_pc_r = rvdffe(io.dec_alu.exu_i0_pc_x,i0_r_data_en.asBool,clock,io.scan_mode) -// -// io.dec_tlu_i0_pc_r := dec_i0_pc_r -// -// //end tracing -// -// val temp_pred_correct_npc_x = rvbradder(Cat(io.dec_alu.exu_i0_pc_x,0.U),Cat(last_br_immed_x,0.U)) -// io.decode_exu.pred_correct_npc_x := temp_pred_correct_npc_x(31,1) -// -// // scheduling logic for primary alu's -// -// val i0_rs1_depend_i0_x = io.decode_exu.dec_i0_rs1_en_d & x_d.bits.i0v & (x_d.bits.i0rd === i0r.rs1) -// val i0_rs1_depend_i0_r = io.decode_exu.dec_i0_rs1_en_d & r_d.bits.i0v & (r_d.bits.i0rd === i0r.rs1) -// -// val i0_rs2_depend_i0_x = io.decode_exu.dec_i0_rs2_en_d & x_d.bits.i0v & (x_d.bits.i0rd === i0r.rs2) -// val i0_rs2_depend_i0_r = io.decode_exu.dec_i0_rs2_en_d & r_d.bits.i0v & (r_d.bits.i0rd === i0r.rs2) -// // order the producers as follows: , i0_x, i0_r, i0_wb -// i0_rs1_class_d := Mux(i0_rs1_depend_i0_x.asBool,i0_x_c,Mux(i0_rs1_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs1_class_d))) -// i0_rs1_depth_d := Mux(i0_rs1_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs1_depend_i0_r.asBool, 2.U(2.W), 0.U)) -// i0_rs2_class_d := Mux(i0_rs2_depend_i0_x.asBool,i0_x_c,Mux(i0_rs2_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs2_class_d))) -// i0_rs2_depth_d := Mux(i0_rs2_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs2_depend_i0_r.asBool, 2.U(2.W), 0.U)) -// -// // stores will bypass load data in the lsu pipe -// if (LOAD_TO_USE_PLUS1) { -// i0_load_block_d := (i0_rs1_class_d.load & i0_rs1_depth_d) | (i0_rs2_class_d.load & i0_rs2_depth_d(0) & !i0_dp.store) -// load_ldst_bypass_d := (i0_dp.load | i0_dp.store) & i0_rs1_depth_d(1) & i0_rs1_class_d.load -// store_data_bypass_d := i0_dp.store & (i0_rs2_depth_d(1) & i0_rs2_class_d.load) -// store_data_bypass_m := i0_dp.store & (i0_rs2_depth_d(0) & i0_rs2_class_d.load) -// } -// else { -// i0_load_block_d := 0.B -// load_ldst_bypass_d := (i0_dp.load | i0_dp.store) & i0_rs1_depth_d(0) & i0_rs1_class_d.load -// store_data_bypass_d := i0_dp.store & i0_rs2_depth_d(0) & i0_rs2_class_d.load -// store_data_bypass_m := 0.B -// } -// // add nonblock load rs1/rs2 bypass cases -// -// val i0_rs1_nonblock_load_bypass_en_d = io.decode_exu.dec_i0_rs1_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs1) -// -// val i0_rs2_nonblock_load_bypass_en_d = io.decode_exu.dec_i0_rs2_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs2) -// -// // bit 2 is priority match, bit 0 lowest priority , i0_x, i0_r -// i0_rs1bypass := Cat((i0_rs1_depth_d(0) &(i0_rs1_class_d.alu | i0_rs1_class_d.mul)),(i0_rs1_depth_d(0) & (i0_rs1_class_d.load)), (i0_rs1_depth_d(1) & (i0_rs1_class_d.alu | i0_rs1_class_d.mul | i0_rs1_class_d.load))) -// -// i0_rs2bypass := Cat((i0_rs2_depth_d(0) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul)),(i0_rs2_depth_d(0) & (i0_rs2_class_d.load)),(i0_rs2_depth_d(1) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul | i0_rs2_class_d.load))) -// -// io.decode_exu.dec_i0_rs1_bypass_en_d := Cat(i0_rs1bypass(2),(i0_rs1bypass(1) | i0_rs1bypass(0) | (!i0_rs1bypass(2) & i0_rs1_nonblock_load_bypass_en_d))) -// io.decode_exu.dec_i0_rs2_bypass_en_d := Cat(i0_rs2bypass(2),(i0_rs2bypass(1) | i0_rs2bypass(0) | (!i0_rs2bypass(2) & i0_rs2_nonblock_load_bypass_en_d))) -// -// -// io.decode_exu.dec_i0_rs1_bypass_data_d := Mux1H(Seq( -// i0_rs1bypass(1).asBool -> io.lsu_result_m, -// i0_rs1bypass(0).asBool -> i0_result_r, -// (!i0_rs1bypass(1) & !i0_rs1bypass(0) & i0_rs1_nonblock_load_bypass_en_d).asBool -> io.dctl_busbuff.lsu_nonblock_load_data, -// )) -// io.decode_exu.dec_i0_rs2_bypass_data_d := Mux1H(Seq( -// i0_rs2bypass(1).asBool -> io.lsu_result_m, -// i0_rs2bypass(0).asBool -> i0_result_r, -// (!i0_rs2bypass(1) & !i0_rs2bypass(0) & i0_rs2_nonblock_load_bypass_en_d).asBool -> io.dctl_busbuff.lsu_nonblock_load_data, -// )) -// io.dec_lsu_valid_raw_d := ((io.dec_ib0_valid_d & (i0_dp_raw.load | i0_dp_raw.store) & !io.dctl_dma.dma_dccm_stall_any & !i0_block_raw_d) | io.decode_exu.dec_extint_stall) -// io.dec_lsu_offset_d := Mux1H(Seq( -// (!io.decode_exu.dec_extint_stall & i0_dp.lsu & i0_dp.load).asBool -> i0(31,20), -// (!io.decode_exu.dec_extint_stall & i0_dp.lsu & i0_dp.store).asBool -> Cat(i0(31,25),i0(11,7)))) -//} \ No newline at end of file +package dec +import chisel3._ + +import scala.collection._ +import chisel3.util._ +import include._ +import lib._ +import exu._ +import lsu._ + +class dec_decode_ctl extends Module with lib with RequireAsyncReset{ + val io = IO(new Bundle{ + val decode_exu = Flipped(new decode_exu) //connection with exu top + val dec_alu = Flipped(new dec_alu) //connection with alu + val dec_div = Flipped(new dec_div) //connection with divider + val dctl_busbuff = Flipped(new dctl_busbuff()) //connection with bus buffer + val dctl_dma = new dctl_dma //connection with dma + val dec_aln = Flipped(new aln_dec) //connection with aligner + val dbg_dctl = new dbg_dctl() //connection with dbg + + val dec_tlu_trace_disable = Input(Bool()) + val dec_debug_valid_d = Input(Bool()) + + + val dec_tlu_flush_extint = Input(Bool()) + val dec_tlu_force_halt = Input(Bool()) // invalidate nonblock load cam on a force halt event + + val dec_i0_inst_wb = Output(UInt(32.W)) // 32b instruction at wb+1 for trace encoder + val dec_i0_pc_wb = Output(UInt(31.W)) // 31b pc at wb+1 for trace encoder + + val dec_i0_trigger_match_d = Input(UInt(4.W)) // i0 decode trigger matches + val dec_tlu_wr_pause_r = Input(Bool()) // pause instruction at r + val dec_tlu_pipelining_disable = Input(Bool()) // pipeline disable - presync, i0 decode only + val lsu_trigger_match_m = Input(UInt(4.W)) // lsu trigger matches + val lsu_pmu_misaligned_m = Input(Bool()) // perf mon: load/store misalign + val dec_tlu_debug_stall = Input(Bool()) // debug stall decode + val dec_tlu_flush_leak_one_r = Input(Bool()) // leak1 instruction + val dec_debug_fence_d = Input(Bool()) // debug fence instruction + val dec_i0_icaf_d = Input(Bool()) // icache access fault + + val dec_i0_icaf_second_d = Input(Bool()) // i0 instruction access fault at decode for f1 fetch group + + val dec_i0_icaf_type_d = Input(UInt(2.W)) // i0 instruction access fault type + val dec_i0_dbecc_d = Input(Bool()) // icache/iccm double-bit error + val dec_i0_brp = Flipped(Valid(new br_pkt_t)) // branch packet + val dec_i0_bp_index = Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index + val dec_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR + val dec_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag + + val dec_i0_bp_fa_index = Input(UInt(log2Ceil(BTB_SIZE).W)) // Fully associt btb index + + // val dec_i0_pc_d = Input(UInt(31.W)) // pc + val lsu_idle_any = Input(Bool()) // lsu idle: if fence instr & !!!!!!!!!!!!!!!!!!!!!!!!!lsu_idle then stall decode + val lsu_load_stall_any = Input(Bool()) // stall any load at decode + val lsu_store_stall_any = Input(Bool()) // stall any store at decode6 + val exu_div_wren = Input(Bool()) // nonblocking divide write enable to GPR. + val dec_tlu_i0_kill_writeb_wb = Input(Bool()) // I0 is flushed, don't writeback any results to arch state + val dec_tlu_flush_lower_wb = Input(Bool()) // trap lower flush + val dec_tlu_i0_kill_writeb_r = Input(Bool()) // I0 is flushed, don't writeback any results to arch state + val dec_tlu_flush_lower_r = Input(Bool()) // trap lower flush + val dec_tlu_flush_pause_r = Input(Bool()) // don't clear pause state on initial lower flush + val dec_tlu_presync_d = Input(Bool()) // CSR read needs to be presync'd + val dec_tlu_postsync_d = Input(Bool()) // CSR ops that need to be postsync'd + val dec_i0_pc4_d = Input(Bool()) // inst is 4B inst else 2B + val dec_csr_rddata_d = Input(UInt(32.W)) // csr read data at wb + val dec_csr_legal_d = Input(Bool()) // csr indicates legal operation + val lsu_result_m = Input(UInt(32.W)) // load result + val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected data for writing gpr's, not for bypassing + val exu_flush_final = Input(Bool()) // lower flush or i0 flush at X or D + val dec_i0_instr_d = Input(UInt(32.W)) // inst at decode + val dec_ib0_valid_d = Input(Bool()) // inst valid at decode + + val active_clk = Input(Clock()) // Clock only while core active. Through two clock headers. For flops without second clock header built in. + val free_l2clk = Input(Clock()) // Clock always. Through one clock header. For flops with second header built in. + val clk_override = Input(Bool()) // Override non-functional clock gating + + val dec_i0_rs1_d = Output(UInt(5.W)) // rs1 logical source + val dec_i0_rs2_d = Output(UInt(5.W)) + val dec_i0_waddr_r = Output(UInt(5.W)) // i0 logical source to write to gpr's + val dec_i0_wen_r = Output(Bool()) // i0 write enable + val dec_i0_wdata_r = Output(UInt(32.W)) // i0 write data + + // val dec_i0_branch_d = Output(Bool()) // Branch in D-stage + // val dec_i0_result_r = Output(UInt(32.W)) // Result R-stage + // val dec_qual_lsu_d = Output(Bool())// LSU instruction at D. Use to quiet LSU operands + + val lsu_p = Valid(new lsu_pkt_t) // load/store packet + val div_waddr_wb = Output(UInt(5.W)) // DIV write address to GPR + val dec_lsu_valid_raw_d = Output(Bool()) + val dec_lsu_offset_d = Output(UInt(12.W)) + val dec_csr_wen_unq_d = Output(Bool()) // valid csr with write - for csr legal + val dec_csr_any_unq_d = Output(Bool()) // valid csr - for csr legal + val dec_csr_rdaddr_d = Output(UInt(12.W)) // read address for csr + val dec_csr_wen_r = Output(Bool()) // csr write enable at r + val dec_csr_wraddr_r = Output(UInt(12.W)) // write address for csr + val dec_csr_wrdata_r = Output(UInt(32.W)) // csr write data at r + val dec_csr_stall_int_ff = Output(Bool()) // csr is mie/mstatus + val dec_tlu_i0_valid_r = Output(Bool()) // i0 valid inst at c + val dec_tlu_packet_r = Output(new trap_pkt_t) // trap packet + val dec_tlu_i0_pc_r = Output(UInt(31.W)) // i0 trap pc + val dec_illegal_inst = Output(UInt(32.W)) // illegal inst + + val dec_fa_error_index = Output(UInt(log2Ceil(BTB_SIZE).W)) // Fully associt btb error index + + val dec_pmu_instr_decoded = Output(Bool()) // number of instructions decode this cycle encoded + val dec_pmu_decode_stall = Output(Bool()) // decode is stalled + val dec_pmu_presync_stall = Output(Bool()) // decode has presync stall + val dec_pmu_postsync_stall = Output(Bool()) // decode has postsync stall + val dec_nonblock_load_wen = Output(Bool()) // write enable for nonblock load + val dec_nonblock_load_waddr = Output(UInt(5.W)) // logical write addr for nonblock load + val dec_pause_state = Output(Bool()) // core in pause state + val dec_pause_state_cg = Output(Bool()) // pause state for clock-gating + val dec_div_active = Output(Bool()) // non-block divide is active + val scan_mode = Input(Bool()) + }) + //packets zero initialization + io.decode_exu.mul_p := 0.U.asTypeOf(io.decode_exu.mul_p) + // Vals defined + val leak1_i1_stall_in = WireInit(UInt(1.W), 0.U) + val leak1_i0_stall_in = WireInit(UInt(1.W), 0.U) + val i0r = Wire(new reg_pkt_t) + val d_t = Wire(new trap_pkt_t) + val x_t = Wire(new trap_pkt_t) + val x_t_in = Wire(new trap_pkt_t) + val r_t = Wire(new trap_pkt_t) + val r_t_in = Wire(new trap_pkt_t) + val d_d = Wire(Valid(new dest_pkt_t)) + val x_d = Wire(Valid(new dest_pkt_t)) + val r_d = Wire(Valid(new dest_pkt_t)) + val r_d_in = Wire(Valid(new dest_pkt_t)) + val wbd = Wire(Valid(new dest_pkt_t)) + val i0_d_c = Wire(new class_pkt_t) + val i0_rs1_class_d = Wire(new class_pkt_t) + val i0_rs2_class_d = Wire(new class_pkt_t) + val i0_rs1_depth_d = WireInit(UInt(2.W),0.U) + val i0_rs2_depth_d = WireInit(UInt(2.W),0.U) + val cam_wen = WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U) + val cam = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t))) + val cam_write = WireInit(UInt(1.W), 0.U) + val cam_inv_reset_val = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) + val cam_data_reset_val = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) + val nonblock_load_write = Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) + val cam_raw = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t))) + val cam_in = Wire(Vec(LSU_NUM_NBLOAD,Valid(new load_cam_pkt_t))) + val i0_dp = Wire(new dec_pkt_t) + val i0_dp_raw = Wire(new dec_pkt_t) + val i0_rs1bypass = WireInit(UInt(3.W), 0.U) + val i0_rs2bypass = WireInit(UInt(3.W), 0.U) + val illegal_lockout = WireInit(UInt(1.W), 0.U) + val postsync_stall = WireInit(UInt(1.W), 0.U) + val ps_stall_in = WireInit(UInt(1.W), 0.U) + val i0_pipe_en = WireInit(UInt(4.W), 0.U) + val i0_load_block_d = WireInit(UInt(1.W), 0.U) + val load_ldst_bypass_d = WireInit(UInt(1.W), 0.U) + val store_data_bypass_d = WireInit(UInt(1.W), 0.U) + val store_data_bypass_m = WireInit(UInt(1.W), 0.U) + val tlu_wr_pause_r1 = WireInit(UInt(1.W), 0.U) + val tlu_wr_pause_r2 = WireInit(UInt(1.W), 0.U) + val leak1_i1_stall = WireInit(UInt(1.W), 0.U) + val leak1_i0_stall = WireInit(UInt(1.W), 0.U) + val pause_state = WireInit(Bool(), 0.B) + val flush_final_r = WireInit(UInt(1.W), 0.U) + val illegal_lockout_in = WireInit(UInt(1.W), 0.U) + val lsu_idle = WireInit(Bool(), 0.B) + val pause_state_in = WireInit(Bool(), 0.B) + val leak1_mode = WireInit(UInt(1.W), 0.U) + val i0_pcall = WireInit(UInt(1.W), 0.U) + val i0_pja = WireInit(UInt(1.W), 0.U) + val i0_pret = WireInit(UInt(1.W), 0.U) + val i0_legal_decode_d = WireInit(UInt(1.W), 0.U) + val i0_pcall_raw = WireInit(UInt(1.W), 0.U) + val i0_pja_raw = WireInit(UInt(1.W), 0.U) + val i0_pret_raw = WireInit(UInt(1.W), 0.U) + val i0_br_offset = WireInit(UInt(12.W), 0.U) + val i0_csr_write_only_d = WireInit(UInt(1.W), 0.U) + val i0_jal = WireInit(UInt(1.W), 0.U) + val i0_wen_r = WireInit(UInt(1.W), 0.U) + val i0_x_ctl_en = WireInit(UInt(1.W), 0.U) + val i0_r_ctl_en = WireInit(UInt(1.W), 0.U) + val i0_wb_ctl_en = WireInit(UInt(1.W), 0.U) + val i0_x_data_en = WireInit(UInt(1.W), 0.U) + val i0_r_data_en = WireInit(UInt(1.W), 0.U) + val i0_wb_data_en = WireInit(UInt(1.W), 0.U) + val i0_wb1_data_en = WireInit(UInt(1.W), 0.U) + val i0_nonblock_load_stall = WireInit(UInt(1.W), 0.U) + val csr_ren_qual_d = WireInit(Bool(), 0.B) + val lsu_decode_d = WireInit(UInt(1.W), 0.U) + val mul_decode_d = WireInit(UInt(1.W), 0.U) + val div_decode_d = WireInit(UInt(1.W), 0.U) + val write_csr_data = WireInit(UInt(32.W),0.U) + val i0_result_corr_r = WireInit(UInt(32.W),0.U) + val presync_stall = WireInit(UInt(1.W), 0.U) + val i0_nonblock_div_stall = WireInit(UInt(1.W), 0.U) + val debug_fence = WireInit(Bool(), 0.B) + val i0_immed_d = WireInit(UInt(32.W), 0.U) + val i0_result_x = WireInit(UInt(32.W), 0.U) + val i0_result_r = WireInit(UInt(32.W), 0.U) + val i0_br_error_all = WireInit(Bool(),0.B) + val i0_brp_valid = WireInit(Bool(),0.B) + val btb_error_found_f = WireInit(Bool(),0.B) + val fa_error_index_ns = WireInit(Bool(),0.B) + val btb_error_found = WireInit(Bool(),0.B) + val div_active_in = WireInit(Bool(),0.B) + ////////////////////////////////////////////////////////////////////// + + leak1_i1_stall := rvdffie(leak1_i1_stall_in, io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + leak1_i0_stall := rvdffie(leak1_i0_stall_in, io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + io.decode_exu.dec_extint_stall := rvdffie(io.dec_tlu_flush_extint, io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + pause_state := rvdffie(pause_state_in, io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + tlu_wr_pause_r1 := rvdffie(io.dec_tlu_wr_pause_r, io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + tlu_wr_pause_r2 := rvdffie(tlu_wr_pause_r1, io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + illegal_lockout := rvdffie(illegal_lockout_in, io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + postsync_stall := rvdffie(ps_stall_in, io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + + val lsu_trigger_match_r = rvdffie(io.lsu_trigger_match_m, io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + val lsu_pmu_misaligned_r = rvdffie(io.lsu_pmu_misaligned_m, io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + io.dec_div_active := rvdffie(div_active_in, io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + flush_final_r := rvdffie(io.exu_flush_final, io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + val debug_valid_x = rvdffie(io.dec_debug_valid_d, io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + val i0_icaf_d = io.dec_i0_icaf_d | io.dec_i0_dbecc_d + if(BTB_ENABLE){ + i0_brp_valid := io.dec_i0_brp.valid & !leak1_mode & !i0_icaf_d + io.decode_exu.dec_i0_predict_p_d.bits.misp := 0.U + io.decode_exu.dec_i0_predict_p_d.bits.ataken := 0.U + io.decode_exu.dec_i0_predict_p_d.bits.boffset := 0.U + io.decode_exu.dec_i0_predict_p_d.bits.pcall := i0_pcall // don't mark as pcall if branch error + io.decode_exu.dec_i0_predict_p_d.bits.pja := i0_pja + io.decode_exu.dec_i0_predict_p_d.bits.pret := i0_pret + io.decode_exu.dec_i0_predict_p_d.bits.prett := io.dec_i0_brp.bits.prett + io.decode_exu.dec_i0_predict_p_d.bits.pc4 := io.dec_i0_pc4_d + io.decode_exu.dec_i0_predict_p_d.bits.hist := io.dec_i0_brp.bits.hist + io.decode_exu.dec_i0_predict_p_d.valid := i0_brp_valid & i0_legal_decode_d + val i0_notbr_error = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw) + + // no toffset error for a pret + val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.bits.hist(1) & (io.dec_i0_brp.bits.toffset =/= i0_br_offset) & !i0_pret_raw + val i0_ret_error = i0_brp_valid & (io.dec_i0_brp.bits.ret ^ i0_pret_raw) + val i0_br_error = io.dec_i0_brp.bits.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error + io.decode_exu.dec_i0_predict_p_d.bits.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode + io.decode_exu.dec_i0_predict_p_d.bits.br_start_error := io.dec_i0_brp.bits.br_start_error & i0_legal_decode_d & !leak1_mode + io.decode_exu.i0_predict_index_d := io.dec_i0_bp_index + io.decode_exu.i0_predict_btag_d := io.dec_i0_bp_btag + i0_br_error_all := (i0_br_error | io.dec_i0_brp.bits.br_start_error) & !leak1_mode + io.decode_exu.dec_i0_predict_p_d.bits.toffset := i0_br_offset + io.decode_exu.i0_predict_fghr_d := io.dec_i0_bp_fghr + io.decode_exu.dec_i0_predict_p_d.bits.way := io.dec_i0_brp.bits.way + if(BTB_FULLYA){ + + io.dec_fa_error_index := withClock(io.active_clk){RegNext(fa_error_index_ns,0.U)} + val btb_error_found_f = withClock(io.active_clk){RegNext(btb_error_found,0.B)} + btb_error_found := (i0_br_error_all | btb_error_found_f) & ~io.dec_tlu_flush_lower_r + fa_error_index_ns := Mux(i0_br_error_all & ~btb_error_found_f, io.dec_i0_bp_fa_index , io.dec_fa_error_index) + + }else{ + io.dec_fa_error_index := 0.U + } + + }else{ + io.decode_exu.dec_i0_predict_p_d := 0.U + io.decode_exu.dec_i0_predict_p_d.bits.pcall := i0_pcall // don't mark as pcall if branch error + io.decode_exu.dec_i0_predict_p_d.bits.pja := i0_pja + io.decode_exu.dec_i0_predict_p_d.bits.pret := i0_pret + io.decode_exu.dec_i0_predict_p_d.bits.pc4 := io.dec_i0_pc4_d + + i0_br_error_all := 0.U + io.decode_exu.i0_predict_index_d := 0.U + io.decode_exu.i0_predict_btag_d := 0.U + io.decode_exu.i0_predict_fghr_d := 0.U + i0_brp_valid := 0.U + } + + // end + + // on br error turn anything into a nop + // on i0 instruction fetch access fault turn anything into a nop + // nop => alu rs1 imm12 rd lor + + val i0_instr_error = i0_icaf_d + i0_dp := i0_dp_raw + when((i0_br_error_all | i0_instr_error).asBool){ + i0_dp := 0.U.asTypeOf(i0_dp) + i0_dp.alu := 1.B + i0_dp.rs1 := 1.B + i0_dp.rs2 := 1.B + i0_dp.lor := 1.B + i0_dp.legal := 1.B + i0_dp.postsync := 1.B + } + + val i0 = io.dec_i0_instr_d + io.decode_exu.dec_i0_select_pc_d := i0_dp.pc + + // branches that can be predicted + val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret + val i0_predict_nt = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br + val i0_predict_t = (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br + val i0_ap_pc2 = !io.dec_i0_pc4_d + val i0_ap_pc4 = io.dec_i0_pc4_d + io.decode_exu.i0_ap.predict_nt := i0_predict_nt + io.decode_exu.i0_ap.predict_t := i0_predict_t + + + io.decode_exu.i0_ap.add := i0_dp.add + io.decode_exu.i0_ap.sub := i0_dp.sub + io.decode_exu.i0_ap.land := i0_dp.land + io.decode_exu.i0_ap.lor := i0_dp.lor + io.decode_exu.i0_ap.lxor := i0_dp.lxor + io.decode_exu.i0_ap.sll := i0_dp.sll + io.decode_exu.i0_ap.srl := i0_dp.srl + io.decode_exu.i0_ap.sra := i0_dp.sra + io.decode_exu.i0_ap.slt := i0_dp.slt + io.decode_exu.i0_ap.unsign := i0_dp.unsign + io.decode_exu.i0_ap.beq := i0_dp.beq + io.decode_exu.i0_ap.bne := i0_dp.bne + io.decode_exu.i0_ap.blt := i0_dp.blt + io.decode_exu.i0_ap.bge := i0_dp.bge + io.decode_exu.i0_ap.clz := i0_dp.clz + io.decode_exu.i0_ap.ctz := i0_dp.ctz + io.decode_exu.i0_ap.pcnt := i0_dp.pcnt + io.decode_exu.i0_ap.sext_b := i0_dp.sext_b + io.decode_exu.i0_ap.sext_h := i0_dp.sext_h + io.decode_exu.i0_ap.sh1add := i0_dp.sh1add + io.decode_exu.i0_ap.sh2add := i0_dp.sh2add + io.decode_exu.i0_ap.sh3add := i0_dp.sh3add + io.decode_exu.i0_ap.zba := i0_dp.zba + io.decode_exu.i0_ap.slo := i0_dp.slo + io.decode_exu.i0_ap.sro := i0_dp.sro + io.decode_exu.i0_ap.min := i0_dp.min + io.decode_exu.i0_ap.max := i0_dp.max + io.decode_exu.i0_ap.pack := i0_dp.pack + io.decode_exu.i0_ap.packu := i0_dp.packu + io.decode_exu.i0_ap.packh := i0_dp.packh + io.decode_exu.i0_ap.rol := i0_dp.rol + io.decode_exu.i0_ap.ror := i0_dp.ror + io.decode_exu.i0_ap.grev := i0_dp.grev + io.decode_exu.i0_ap.gorc := i0_dp.gorc + io.decode_exu.i0_ap.zbb := i0_dp.zbb + io.decode_exu.i0_ap.sbset := i0_dp.sbset + io.decode_exu.i0_ap.sbclr := i0_dp.sbclr + io.decode_exu.i0_ap.sbinv := i0_dp.sbinv + io.decode_exu.i0_ap.sbext := i0_dp.sbext + io.decode_exu.i0_ap.csr_write := i0_csr_write_only_d + io.decode_exu.i0_ap.csr_imm := i0_dp.csr_imm + io.decode_exu.i0_ap.jal := i0_jal + + // non block load cam logic + // val found=Wire(UInt(1.W)) + cam_wen := Mux1H((0 until LSU_NUM_NBLOAD).map(i=>(0 to i).map(j=> if(i==j) !cam(j).valid else cam(j).valid).reduce(_.asBool&_.asBool).asBool -> (cam_write << i))) + + cam_write := io.dctl_busbuff.lsu_nonblock_load_valid_m + val cam_write_tag = io.dctl_busbuff.lsu_nonblock_load_tag_m(LSU_NUM_NBLOAD_WIDTH-1,0) + + val cam_inv_reset = io.dctl_busbuff.lsu_nonblock_load_inv_r + val cam_inv_reset_tag = io.dctl_busbuff.lsu_nonblock_load_inv_tag_r + + val cam_data_reset = io.dctl_busbuff.lsu_nonblock_load_data_valid | io.dctl_busbuff.lsu_nonblock_load_data_error + val cam_data_reset_tag = io.dctl_busbuff.lsu_nonblock_load_data_tag + + val nonblock_load_rd = Mux(x_d.bits.i0load.asBool, x_d.bits.i0rd, 0.U(5.W)) // rd data + val load_data_tag = io.dctl_busbuff.lsu_nonblock_load_data_tag + // case of multiple loads to same dest ie. x1 ... you have to invalidate the older one + // don't writeback a nonblock load + val nonblock_load_valid_m_delay=withClock(io.active_clk){RegEnable(io.dctl_busbuff.lsu_nonblock_load_valid_m,0.U, i0_r_ctl_en.asBool)} + val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.bits.i0load + for(i <- 0 until LSU_NUM_NBLOAD){ + cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).bits.tag) & cam(i).valid + cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).bits.tag) & cam_raw(i).valid + cam_in(i):=0.U.asTypeOf(cam(0)) + cam(i):=cam_raw(i) + + when(cam_data_reset_val(i).asBool){ + cam(i).valid := 0.U(1.W) + } + when(cam_wen(i).asBool){ + cam_in(i).valid := 1.U(1.W) + cam_in(i).bits.wb := 0.U(1.W) + cam_in(i).bits.tag := cam_write_tag + cam_in(i).bits.rd := nonblock_load_rd + }.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.bits.i0rd === cam(i).bits.rd) && cam(i).bits.wb.asBool)){ + cam_in(i).valid := 0.U + }.otherwise{ + cam_in(i) := cam(i) + } + when(nonblock_load_valid_m_delay===1.U && (io.dctl_busbuff.lsu_nonblock_load_inv_tag_r === cam(i).bits.tag) && cam(i).valid===1.U){ + cam_in(i).bits.wb := 1.U + } + // force debug halt forces cam valids to 0 highest priority + when(io.dec_tlu_force_halt){ + cam_in(i).valid := 0.U + } + + cam_raw(i):=rvdffie(cam_in(i),clock,reset.asAsyncReset(),io.scan_mode) + nonblock_load_write(i) := (load_data_tag === cam_raw(i).bits.tag) & cam_raw(i).valid + } + + io.dec_nonblock_load_waddr:=0.U(5.W) + // cancel if any younger inst (including another nonblock) committing this cycle + val nonblock_load_cancel = ((r_d_in.bits.i0rd === io.dec_nonblock_load_waddr) & i0_wen_r) + io.dec_nonblock_load_wen := (io.dctl_busbuff.lsu_nonblock_load_data_valid && nonblock_load_write.reduce(_|_).asBool && !nonblock_load_cancel) + val i0_nonblock_boundary_stall = ((nonblock_load_rd===i0r.rs1) & io.dctl_busbuff.lsu_nonblock_load_valid_m & io.decode_exu.dec_i0_rs1_en_d)|((nonblock_load_rd===i0r.rs2) & io.dctl_busbuff.lsu_nonblock_load_valid_m & io.decode_exu.dec_i0_rs2_en_d) + + i0_nonblock_load_stall := i0_nonblock_boundary_stall + + val cal_temp= for(i <-0 until LSU_NUM_NBLOAD) yield ((Fill(5,nonblock_load_write(i)) & cam(i).bits.rd), io.decode_exu.dec_i0_rs1_en_d & cam(i).valid & (cam(i).bits.rd === i0r.rs1), io.decode_exu.dec_i0_rs2_en_d & cam(i).valid & (cam(i).bits.rd === i0r.rs2)) + val (waddr, ld_stall_1, ld_stall_2) = (cal_temp.map(_._1).reduce(_|_) , cal_temp.map(_._2).reduce(_|_), cal_temp.map(_._3).reduce(_|_) ) + io.dec_nonblock_load_waddr:=waddr + i0_nonblock_load_stall:=ld_stall_1 | ld_stall_2 | i0_nonblock_boundary_stall + //i0_nonblock_load_stall:=ld_stall_2 + + // end non block load cam logic + + // pmu start + + val csr_read = csr_ren_qual_d + val csr_write = io.dec_csr_wen_unq_d + val i0_br_unpred = i0_dp.jal & !i0_predict_br + + // the classes must be mutually exclusive with one another + import inst_pkt_t._ + d_t.pmu_i0_itype :=Fill(4,i0_legal_decode_d) & MuxCase(NULL ,Array( + i0_dp.jal -> JAL, + i0_dp.condbr -> CONDBR, + i0_dp.mret -> MRET, + i0_dp.fence_i -> FENCEI, + i0_dp.fence -> FENCE, + i0_dp.ecall -> ECALL, + i0_dp.ebreak -> EBREAK, + ( csr_read & csr_write).asBool -> CSRRW, + (!csr_read & csr_write).asBool -> CSRWRITE, + ( csr_read & !csr_write).asBool -> CSRREAD, + (i0_dp.zbb | i0_dp.zbs | i0_dp.zbe | i0_dp.zbc | i0_dp.zbp | i0_dp.zbr | i0_dp.zbf | i0_dp.zba) -> BITMANIPU, + i0_dp.pm_alu -> ALU, + i0_dp.store -> STORE, + i0_dp.load -> LOAD, + i0_dp.mul -> MUL)) + // end pmu + + val i0_dec =Module(new dec_dec_ctl) + i0_dec.io.ins:= i0 + i0_dp_raw:=i0_dec.io.out + + lsu_idle:=withClock(io.active_clk){RegNext(io.lsu_idle_any,0.U)} + + // can't make this clock active_clock + leak1_i1_stall_in := (io.dec_tlu_flush_leak_one_r | (leak1_i1_stall & !io.dec_tlu_flush_lower_r)) + leak1_mode := leak1_i1_stall + leak1_i0_stall_in := ((io.dec_aln.dec_i0_decode_d & leak1_i1_stall) | (leak1_i0_stall & !io.dec_tlu_flush_lower_r)) + + // 12b jal's can be predicted - these are calls + + val i0_pcall_imm = Cat(i0(31),i0(19,12),i0(20),i0(30,21)) + val i0_pcall_12b_offset = Mux(i0_pcall_imm(11).asBool, i0_pcall_imm(19,12) === 0xff.U , i0_pcall_imm(19,12) === 0.U(8.W)) + val i0_pcall_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & (i0r.rd === 1.U(5.W) | i0r.rd === 5.U(5.W)) + val i0_pja_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & !(i0r.rd === 1.U(5.W) | i0r.rd === 5.U(5.W)) + i0_pcall_raw := i0_dp_raw.jal & i0_pcall_case // this includes ja + i0_pcall := i0_dp.jal & i0_pcall_case + i0_pja_raw := i0_dp_raw.jal & i0_pja_case + i0_pja := i0_dp.jal & i0_pja_case + i0_br_offset := Mux((i0_pcall_raw | i0_pja_raw).asBool, i0_pcall_imm(11,0) , Cat(i0(31),i0(7),i0(30,25),i0(11,8))) + // jalr with rd==0, rs1==1 or rs1==5 is a ret + val i0_pret_case = (i0_dp_raw.jal & i0_dp_raw.imm12 & (i0r.rd === 0.U(5.W)) & (i0r.rs1===1.U(5.W) | i0r.rs1 === 5.U(5.W))) + i0_pret_raw := i0_dp_raw.jal & i0_pret_case + i0_pret := i0_dp.jal & i0_pret_case + i0_jal := i0_dp.jal & !i0_pcall_case & !i0_pja_case & !i0_pret_case + /////////////////////////////////////////////////////////////////////////////////////////////////////////// + + io.dec_div.div_p.valid := div_decode_d + io.dec_div.div_p.bits.unsign := i0_dp.unsign + io.dec_div.div_p.bits.rem := i0_dp.rem + + io.decode_exu.mul_p.valid := mul_decode_d + io.decode_exu.mul_p.bits.rs1_sign := i0_dp.rs1_sign + io.decode_exu.mul_p.bits.rs2_sign := i0_dp.rs2_sign + io.decode_exu.mul_p.bits.low := i0_dp.low + io.decode_exu.mul_p.bits.bext := i0_dp.bext + io.decode_exu.mul_p.bits.bdep := i0_dp.bdep + io.decode_exu.mul_p.bits.clmul := i0_dp.clmul + io.decode_exu.mul_p.bits.clmulh := i0_dp.clmulh + io.decode_exu.mul_p.bits.clmulr := i0_dp.clmulr + io.decode_exu.mul_p.bits.grev := i0_dp.grev + io.decode_exu.mul_p.bits.gorc := i0_dp.gorc + io.decode_exu.mul_p.bits.shfl := i0_dp.shfl + io.decode_exu.mul_p.bits.unshfl := i0_dp.unshfl + io.decode_exu.mul_p.bits.crc32_b := i0_dp.crc32_b + io.decode_exu.mul_p.bits.crc32_h := i0_dp.crc32_h + io.decode_exu.mul_p.bits.crc32_w := i0_dp.crc32_w + io.decode_exu.mul_p.bits.crc32c_b := i0_dp.crc32c_b + io.decode_exu.mul_p.bits.crc32c_h := i0_dp.crc32c_h + io.decode_exu.mul_p.bits.crc32c_w := i0_dp.crc32c_w + io.decode_exu.mul_p.bits.bfp := i0_dp.bfp + + + io.lsu_p := 0.U.asTypeOf(io.lsu_p) + when (io.decode_exu.dec_extint_stall){ + io.lsu_p.bits.load := 1.U(1.W) + io.lsu_p.bits.word := 1.U(1.W) + io.lsu_p.bits.fast_int := 1.U(1.W) + io.lsu_p.valid := 1.U(1.W) + + + }.otherwise { + io.lsu_p.valid := lsu_decode_d + io.lsu_p.bits.load := i0_dp.load + io.lsu_p.bits.store := i0_dp.store + io.lsu_p.bits.by := i0_dp.by + io.lsu_p.bits.half := i0_dp.half + io.lsu_p.bits.word := i0_dp.word + io.lsu_p.bits.stack := (i0r.rs1 === 2.U(5.W)) // stack reference + io.lsu_p.bits.load_ldst_bypass_d := load_ldst_bypass_d + io.lsu_p.bits.store_data_bypass_d := store_data_bypass_d + io.lsu_p.bits.store_data_bypass_m := store_data_bypass_m + io.lsu_p.bits.unsign := i0_dp.unsign + } + + ////////////////////////////////////// + io.dec_alu.dec_csr_ren_d := i0_dp.csr_read & io.dec_ib0_valid_d//H: ing csr read enable signal decoded from decode_ctl going as input to EXU + csr_ren_qual_d := i0_dp.csr_read & i0_legal_decode_d.asBool //csr_ren_qual_d ed as csr_read above + + val i0_csr_write = i0_dp.csr_write & !io.dec_debug_fence_d + val csr_clr_d = i0_dp.csr_clr & i0_legal_decode_d.asBool + val csr_set_d = i0_dp.csr_set & i0_legal_decode_d.asBool + val csr_write_d = i0_csr_write & i0_legal_decode_d.asBool + + i0_csr_write_only_d := i0_csr_write & !i0_dp.csr_read + io.dec_csr_wen_unq_d := (i0_dp.csr_clr | i0_dp.csr_set | i0_csr_write) & io.dec_ib0_valid_d // for csr legal, can't write read-only csr + //dec_csr_wen_unq_d ed as csr_write above + val any_csr_d = i0_dp.csr_read | i0_csr_write + io.dec_csr_any_unq_d := any_csr_d & io.dec_ib0_valid_d + io.dec_csr_rdaddr_d := Fill(12,io.dec_csr_any_unq_d) & i0(31,20) + io.dec_csr_wraddr_r := Fill(12,(r_d.bits.csrwen & r_d.valid)) & r_d.bits.csrwaddr //r_d is a dest_pkt + + // make sure csr doesn't write same cycle as dec_tlu_flush_lower_wb + // also use valid so it's flushable + io.dec_csr_wen_r := r_d.bits.csrwen & r_d.valid & !io.dec_tlu_i0_kill_writeb_r + + // If we are writing MIE or MSTATUS, hold off the external interrupt for a cycle on the write. + io.dec_csr_stall_int_ff := ((r_d.bits.csrwaddr === "h300".U) | (r_d.bits.csrwaddr === "h304".U)) & r_d.bits.csrwen & r_d.valid & !io.dec_tlu_i0_kill_writeb_wb + + val csr_read_x = withClock(io.active_clk){RegNext(csr_ren_qual_d,init=0.B)} + val csr_clr_x = withClock(io.active_clk){RegNext(csr_clr_d, init=0.B)} + val csr_set_x = withClock(io.active_clk){RegNext(csr_set_d, init=0.B)} + val csr_write_x = withClock(io.active_clk){RegNext(csr_write_d, init=0.B)} + val csr_imm_x = withClock(io.active_clk){RegNext(i0_dp.csr_imm, init=0.U)} + + // perform the update operation if any + val csrimm_x = rvdffe(i0(19,15),i0_x_data_en & any_csr_d.asBool,clock,io.scan_mode) + val csr_rddata_x = rvdffe(io.dec_csr_rddata_d,i0_x_data_en & any_csr_d.asBool,clock,io.scan_mode) + + val csr_mask_x = Mux1H(Seq( + csr_imm_x.asBool -> Cat(repl(27,0.U),csrimm_x(4,0)), + !csr_imm_x.asBool -> io.decode_exu.exu_csr_rs1_x)) + + val write_csr_data_x = Mux1H(Seq( + csr_clr_x -> (csr_rddata_x & (~csr_mask_x).asUInt), + csr_set_x -> (csr_rddata_x | csr_mask_x), + csr_write_x -> ( csr_mask_x))) + // pause instruction + val clear_pause = (io.dec_tlu_flush_lower_r & !io.dec_tlu_flush_pause_r) | (pause_state & (write_csr_data === Cat(Fill(31,0.U),write_csr_data(0)))) // if 0 or 1 then exit pause state - 1 cycle pause + pause_state_in := (io.dec_tlu_wr_pause_r | pause_state) & !clear_pause + io.dec_pause_state := pause_state + //pause for clock gating + io.dec_pause_state_cg := (pause_state & (!tlu_wr_pause_r1 && !tlu_wr_pause_r2)) + // end pause + + val write_csr_data_in = Mux(pause_state,(write_csr_data - 1.U(32.W)), + Mux(io.dec_tlu_wr_pause_r,io.dec_csr_wrdata_r,write_csr_data_x)) + val csr_data_wen = ((csr_clr_x | csr_set_x | csr_write_x) & csr_read_x) | io.dec_tlu_wr_pause_r | pause_state + write_csr_data := rvdffe(write_csr_data_in,csr_data_wen,io.free_l2clk,io.scan_mode) + + // will hold until write-back at which time the CSR will be updated while GPR is possibly written with prior CSR + val pause_stall = pause_state + + // for csr write only data is produced by the alu + io.dec_csr_wrdata_r := Mux((r_d.bits.csrwonly & r_d.valid).asBool,i0_result_corr_r,write_csr_data) + + val prior_csr_write = x_d.bits.csrwonly | r_d.bits.csrwonly | wbd.bits.csrwonly + + val debug_fence_i = io.dec_debug_fence_d & io.dbg_dctl.dbg_cmd_wrdata(0) + val debug_fence_raw = io.dec_debug_fence_d & io.dbg_dctl.dbg_cmd_wrdata(1) + debug_fence := debug_fence_raw | debug_fence_i + + // some CSR reads need to be presync'd + val i0_presync = i0_dp.presync | io.dec_tlu_presync_d | debug_fence_i | debug_fence_raw | io.dec_tlu_pipelining_disable // both fence's presync + + // some CSR writes need to be postsync'd + val i0_postsync = i0_dp.postsync | io.dec_tlu_postsync_d | debug_fence_i | (i0_csr_write_only_d & (i0(31,20) === "h7c2".U)) + + + + val i0_legal = i0_dp.legal & (!any_csr_d | io.dec_csr_legal_d) + val i0_inst_d = Mux(io.dec_i0_pc4_d,i0,Cat(repl(16,0.U), io.dec_aln.ifu_i0_cinst)) + // illegal inst handling + + val shift_illegal = io.dec_aln.dec_i0_decode_d & !i0_legal//lm: valid but not legal + val illegal_inst_en = shift_illegal & !illegal_lockout + io.dec_illegal_inst := rvdffe(i0_inst_d,illegal_inst_en,clock,io.scan_mode) + illegal_lockout_in := (shift_illegal | illegal_lockout) & !flush_final_r + val i0_div_prior_div_stall = i0_dp.div & io.dec_div_active + //stalls signals + val i0_block_raw_d = (i0_dp.csr_read & prior_csr_write) | io.decode_exu.dec_extint_stall | pause_stall | + leak1_i0_stall | io.dec_tlu_debug_stall | postsync_stall | presync_stall | + ((i0_dp.fence | debug_fence) & !lsu_idle) | i0_nonblock_load_stall | + i0_load_block_d | i0_nonblock_div_stall | i0_div_prior_div_stall + + val i0_store_stall_d = i0_dp.store & (io.lsu_store_stall_any | io.dctl_dma.dma_dccm_stall_any) + val i0_load_stall_d = i0_dp.load & (io.lsu_load_stall_any | io.dctl_dma.dma_dccm_stall_any) + val i0_block_d = i0_block_raw_d | i0_store_stall_d | i0_load_stall_d + val i0_exublock_d = i0_block_raw_d + + //decode valid + io.dec_aln.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r + val i0_exudecode_d = io.dec_ib0_valid_d & !i0_exublock_d & !io.dec_tlu_flush_lower_r & !flush_final_r + val i0_exulegal_decode_d = i0_exudecode_d & i0_legal + + // performance monitor signals + io.dec_pmu_instr_decoded := io.dec_aln.dec_i0_decode_d + io.dec_pmu_decode_stall := io.dec_ib0_valid_d & !io.dec_aln.dec_i0_decode_d + io.dec_pmu_postsync_stall := postsync_stall.asBool & io.dec_ib0_valid_d + io.dec_pmu_presync_stall := presync_stall.asBool & io.dec_ib0_valid_d + + val prior_inflight_x = x_d.valid + val prior_inflight_wb = r_d.valid + val prior_inflight = prior_inflight_x | prior_inflight_wb + val prior_inflight_eff = Mux(i0_dp.div,prior_inflight_x,prior_inflight) + + presync_stall := (i0_presync & prior_inflight_eff) + // illegals will postsync + ps_stall_in := (io.dec_aln.dec_i0_decode_d & (i0_postsync | !i0_legal) ) | ( postsync_stall & prior_inflight_x) + + io.dec_alu.dec_i0_alu_decode_d := i0_exulegal_decode_d & i0_dp.alu + io.decode_exu.dec_i0_branch_d := i0_dp.condbr | i0_dp.jal | i0_br_error_all + + lsu_decode_d := i0_legal_decode_d & i0_dp.lsu + mul_decode_d := i0_exulegal_decode_d & i0_dp.mul + div_decode_d := i0_exulegal_decode_d & i0_dp.div + io.decode_exu.dec_qual_lsu_d := i0_dp.lsu + io.dec_tlu_i0_valid_r := r_d.valid & !io.dec_tlu_flush_lower_wb + + //traps for TLU (tlu stuff) + d_t.legal := i0_legal_decode_d + d_t.icaf := i0_icaf_d & i0_legal_decode_d // dbecc is icaf exception + d_t.icaf_second := io.dec_i0_icaf_second_d & i0_legal_decode_d // this includes icaf and dbecc + d_t.icaf_type := io.dec_i0_icaf_type_d + + d_t.fence_i := (i0_dp.fence_i | debug_fence_i) & i0_legal_decode_d + + // put pmu info into the trap packet + d_t.pmu_i0_br_unpred := i0_br_unpred + d_t.pmu_divide := 0.U(1.W) + d_t.pmu_lsu_misaligned := 0.U(1.W) + + d_t.i0trigger := io.dec_i0_trigger_match_d & repl(4,io.dec_aln.dec_i0_decode_d) + + + x_t := rvdfflie(d_t,clock,reset.asAsyncReset,i0_x_ctl_en.asBool,io.scan_mode, elements = 3) + + x_t_in := x_t + x_t_in.i0trigger := x_t.i0trigger & ~(repl(4,io.dec_tlu_flush_lower_wb)) + + r_t := rvdfflie(x_t_in,clock,reset.asAsyncReset,i0_x_ctl_en.asBool,io.scan_mode, elements = 3) + + r_t_in := r_t + + r_t_in.i0trigger := (repl(4,(r_d.bits.i0load | r_d.bits.i0store)) & lsu_trigger_match_r) | r_t.i0trigger + r_t_in.pmu_lsu_misaligned := lsu_pmu_misaligned_r // only valid if a load/store is valid in DC3 stage + + when (io.dec_tlu_flush_lower_wb.asBool) {r_t_in := 0.U.asTypeOf(r_t_in) } + + io.dec_tlu_packet_r := r_t_in + io.dec_tlu_packet_r.pmu_divide := r_d.bits.i0div & r_d.valid + // end tlu stuff + + + io.dec_aln.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r + + i0r.rs1 := i0(19,15) //H: ing reg packets the instructions bits + i0r.rs2 := i0(24,20) + i0r.rd := i0(11,7) + + io.decode_exu.dec_i0_rs1_en_d := i0_dp.rs1 & (i0r.rs1 =/= 0.U(5.W)) // if rs1_en=0 then read will be all 0's + io.decode_exu.dec_i0_rs2_en_d := i0_dp.rs2 & (i0r.rs2 =/= 0.U(5.W)) + val i0_rd_en_d = i0_dp.rd & (i0r.rd =/= 0.U(5.W)) + io.dec_i0_rs1_d := i0r.rs1//H:assiging packets to output signals leading to gprfile + io.dec_i0_rs2_d := i0r.rs2 + + val i0_jalimm20 = i0_dp.jal & i0_dp.imm20 // H:jal (used at line 915) + val i0_uiimm20 = !i0_dp.jal & i0_dp.imm20 + + // io.decode_exu.dec_i0_immed_d := Mux1H(Seq( + // i0_dp.csr_read -> io.dec_csr_rddata_d, + // !i0_dp.csr_read -> i0_immed_d)) + + io.decode_exu.dec_i0_immed_d := Mux1H(Seq( + i0_dp.imm12 -> Cat(repl(20,i0(31)),i0(31,20)), // jalr + i0_dp.shimm5 -> Cat(repl(27,0.U),i0(24,20)), + i0_jalimm20 -> Cat(repl(12,i0(31)),i0(19,12),i0(20),i0(30,21),0.U), + i0_uiimm20 -> Cat(i0(31,12),repl(12,0.U)), + (i0_csr_write_only_d & i0_dp.csr_imm).asBool -> Cat(repl(27,0.U),i0(19,15)))) // for csr's that only write + + val bitmanip_zbb_legal = WireInit(Bool(),0.B) + val bitmanip_zbs_legal = WireInit(Bool(),0.B) + val bitmanip_zbe_legal = WireInit(Bool(),0.B) + val bitmanip_zbc_legal = WireInit(Bool(),0.B) + val bitmanip_zbp_legal = WireInit(Bool(),0.B) + val bitmanip_zbr_legal = WireInit(Bool(),0.B) + val bitmanip_zbf_legal = WireInit(Bool(),0.B) + val bitmanip_zba_legal = WireInit(Bool(),0.B) + val bitmanip_zbb_zbp_legal = WireInit(Bool(),0.B) + val bitmanip_legal = WireInit(Bool(),0.B) + if (BITMANIP_ZBB == 1) + bitmanip_zbb_legal := 1.B + else + bitmanip_zbb_legal := !(i0_dp.zbb & !i0_dp.zbp) + + if (BITMANIP_ZBS == 1) + bitmanip_zbs_legal := 1.B + else + bitmanip_zbs_legal := !i0_dp.zbs + + if (BITMANIP_ZBE == 1) + bitmanip_zbe_legal := 1.B + else + bitmanip_zbe_legal := !i0_dp.zbe + + if (BITMANIP_ZBC == 1) + bitmanip_zbc_legal := 1.B + else + bitmanip_zbc_legal := !i0_dp.zbc + + if (BITMANIP_ZBP == 1) + bitmanip_zbp_legal := 1.B + else + bitmanip_zbp_legal := !(i0_dp.zbp & !i0_dp.zbb) + + if (BITMANIP_ZBR == 1) + bitmanip_zbr_legal := 1.B + else + bitmanip_zbr_legal := !i0_dp.zbr + + if (BITMANIP_ZBF == 1) + bitmanip_zbf_legal := 1.B + else + bitmanip_zbf_legal := !i0_dp.zbf + + if (BITMANIP_ZBA == 1) + bitmanip_zba_legal := 1.B + else + bitmanip_zba_legal := !i0_dp.zba + + if ( (BITMANIP_ZBB == 1) | (BITMANIP_ZBP == 1) ) + bitmanip_zbb_zbp_legal := 1.B + else + bitmanip_zbb_zbp_legal := !(i0_dp.zbb & i0_dp.zbp) + + bitmanip_legal := bitmanip_zbb_legal & bitmanip_zbs_legal & bitmanip_zbe_legal & bitmanip_zbc_legal & bitmanip_zbp_legal & bitmanip_zbr_legal & bitmanip_zbf_legal & bitmanip_zba_legal & bitmanip_zbb_zbp_legal + i0_legal_decode_d := io.dec_aln.dec_i0_decode_d & i0_legal + + i0_d_c.mul := i0_dp.mul & i0_legal_decode_d + i0_d_c.load := i0_dp.load & i0_legal_decode_d + i0_d_c.alu := i0_dp.alu & i0_legal_decode_d + + val i0_x_c = withClock(io.active_clk){RegEnable(i0_d_c,0.U.asTypeOf(i0_d_c), i0_x_ctl_en.asBool)} + val i0_r_c = withClock(io.active_clk){RegEnable(i0_x_c,0.U.asTypeOf(i0_x_c), i0_r_ctl_en.asBool)} + i0_pipe_en := Cat(io.dec_aln.dec_i0_decode_d,withClock(io.active_clk){RegNext(i0_pipe_en(3,1), init=0.U)}) + + i0_x_ctl_en := (i0_pipe_en(3,2).orR | io.clk_override) + i0_r_ctl_en := (i0_pipe_en(2,1).orR | io.clk_override) + i0_wb_ctl_en := (i0_pipe_en(1,0).orR | io.clk_override) + i0_x_data_en := ( i0_pipe_en(3) | io.clk_override) + i0_r_data_en := ( i0_pipe_en(2) | io.clk_override) + i0_wb_data_en := ( i0_pipe_en(1) | io.clk_override) + + io.decode_exu.dec_data_en := Cat(i0_x_data_en, i0_r_data_en) + io.decode_exu.dec_ctl_en := Cat(i0_x_ctl_en, i0_r_ctl_en) + + d_d.bits.i0rd := i0r.rd + d_d.bits.i0v := i0_rd_en_d & i0_legal_decode_d + d_d.valid := io.dec_aln.dec_i0_decode_d // has flush_final_r + + d_d.bits.i0load := i0_dp.load & i0_legal_decode_d + d_d.bits.i0store := i0_dp.store & i0_legal_decode_d + d_d.bits.i0div := i0_dp.div & i0_legal_decode_d + + d_d.bits.csrwen := io.dec_csr_wen_unq_d & i0_legal_decode_d + d_d.bits.csrwonly := i0_csr_write_only_d & io.dec_aln.dec_i0_decode_d + d_d.bits.csrwaddr := Mux(d_d.bits.csrwen, i0(31,20), 0.U) + + x_d := rvdfflie(d_d,clock,reset.asAsyncReset(), i0_x_ctl_en.asBool,io.scan_mode,elements = 4) + val x_d_in = Wire(Valid(new dest_pkt_t)) + x_d_in := x_d + x_d_in.bits.i0v := x_d.bits.i0v & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r + x_d_in.valid := x_d.valid & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r + + r_d := rvdfflie(x_d_in,clock,reset.asAsyncReset(),i0_r_ctl_en.asBool,io.scan_mode, elements = 4) + r_d_in := r_d + r_d_in.bits.i0rd := r_d.bits.i0rd + + r_d_in.bits.i0v := (r_d.bits.i0v & !io.dec_tlu_flush_lower_wb) + r_d_in.valid := (r_d.valid & !io.dec_tlu_flush_lower_wb) + r_d_in.bits.i0load := r_d.bits.i0load & !io.dec_tlu_flush_lower_wb + r_d_in.bits.i0store := r_d.bits.i0store & !io.dec_tlu_flush_lower_wb + + wbd := rvdfflie(r_d_in,clock,reset.asAsyncReset(),i0_wb_ctl_en.asBool,io.scan_mode, elements = 4) + + io.dec_i0_waddr_r := r_d_in.bits.i0rd + i0_wen_r := r_d_in.bits.i0v & !io.dec_tlu_i0_kill_writeb_r + io.dec_i0_wen_r := i0_wen_r & !r_d_in.bits.i0div & !i0_load_kill_wen_r // don't write a nonblock load 1st time down the pipe + io.dec_i0_wdata_r := i0_result_corr_r + + + val i0_result_r_raw = rvdffe(i0_result_x,(i0_r_data_en & (x_d.bits.i0v | x_d.bits.csrwen | debug_valid_x)) === 1.B,clock,io.scan_mode) + if ( LOAD_TO_USE_PLUS1) { + i0_result_x := io.decode_exu.exu_i0_result_x + i0_result_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_m, i0_result_r_raw) + } + else { + i0_result_x := Mux((x_d.bits.i0v & x_d.bits.i0load).asBool,io.lsu_result_m,io.decode_exu.exu_i0_result_x) + i0_result_r := i0_result_r_raw + } + + // correct lsu load data - don't use for bypass, do pass down the pipe + i0_result_corr_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_corr_r,i0_result_r_raw) + io.dec_alu.dec_i0_br_immed_d := Mux((io.decode_exu.i0_ap.predict_nt & !i0_dp.jal).asBool,i0_br_offset,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2)) + val last_br_immed_d = WireInit(UInt(12.W),0.U) + last_br_immed_d := Mux((io.decode_exu.i0_ap.predict_nt).asBool,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2),i0_br_offset) + val last_br_immed_x = WireInit(UInt(12.W),0.U) + last_br_immed_x := rvdffe(last_br_immed_d,i0_x_data_en.asBool,clock,io.scan_mode) + + // divide stuff + + val div_e1_to_r = (x_d.bits.i0div & x_d.valid) | (r_d.bits.i0div & r_d.valid) + + val div_flush = (x_d.bits.i0div & x_d.valid & (x_d.bits.i0rd === 0.U(5.W))) | + (x_d.bits.i0div & x_d.valid & io.dec_tlu_flush_lower_r ) | + (r_d.bits.i0div & r_d.valid & io.dec_tlu_flush_lower_r & io.dec_tlu_i0_kill_writeb_r) + + // cancel if any younger inst committing this cycle to same dest as nonblock divide + + val nonblock_div_cancel = (io.dec_div_active & div_flush) | + (io.dec_div_active & !div_e1_to_r & (r_d.bits.i0rd === io.div_waddr_wb) & i0_wen_r) + + io.dec_div.dec_div_cancel := nonblock_div_cancel.asBool + val i0_div_decode_d = i0_legal_decode_d & i0_dp.div + + div_active_in := i0_div_decode_d | (io.dec_div_active & !io.exu_div_wren & !nonblock_div_cancel) + + // io.dec_div_active := withClock(io.free_l2clk){RegNext(div_active_in, 0.U)} + + // nonblocking div scheme + i0_nonblock_div_stall := (io.decode_exu.dec_i0_rs1_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs1)) | + (io.decode_exu.dec_i0_rs2_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs2)) + + + ///div end + + //for tracing instruction + val i0_wb_en = i0_wb_data_en + val trace_enable = ~io.dec_tlu_trace_disable + + io.div_waddr_wb := rvdffe(i0r.rd,i0_div_decode_d.asBool(),clock,io.scan_mode) + + val i0_inst_x = rvdffe(i0_inst_d,(i0_x_data_en & trace_enable),clock,io.scan_mode) + val i0_inst_r = rvdffe(i0_inst_x,(i0_r_data_en & trace_enable),clock,io.scan_mode) + val i0_inst_wb_in = i0_inst_r + val i0_inst_wb = rvdffe(i0_inst_wb_in,(i0_wb_en & trace_enable),clock,io.scan_mode) + val i0_pc_wb = rvdffe(io.dec_tlu_i0_pc_r,(i0_wb_en & trace_enable),clock,io.scan_mode) + + io.dec_i0_inst_wb := i0_inst_wb + io.dec_i0_pc_wb := i0_pc_wb + val dec_i0_pc_r = rvdffpcie(io.dec_alu.exu_i0_pc_x,i0_r_data_en.asBool,reset.asAsyncReset(),clock,io.scan_mode) + + io.dec_tlu_i0_pc_r := dec_i0_pc_r + + //end tracing + + val temp_pred_correct_npc_x = rvbradder(Cat(io.dec_alu.exu_i0_pc_x,0.U),Cat(last_br_immed_x,0.U)) + io.decode_exu.pred_correct_npc_x := temp_pred_correct_npc_x(31,1) + + // scheduling logic for primary alu's + + val i0_rs1_depend_i0_x = io.decode_exu.dec_i0_rs1_en_d & x_d.bits.i0v & (x_d.bits.i0rd === i0r.rs1) + val i0_rs1_depend_i0_r = io.decode_exu.dec_i0_rs1_en_d & r_d.bits.i0v & (r_d.bits.i0rd === i0r.rs1) + + val i0_rs2_depend_i0_x = io.decode_exu.dec_i0_rs2_en_d & x_d.bits.i0v & (x_d.bits.i0rd === i0r.rs2) + val i0_rs2_depend_i0_r = io.decode_exu.dec_i0_rs2_en_d & r_d.bits.i0v & (r_d.bits.i0rd === i0r.rs2) + // order the producers as follows: , i0_x, i0_r, i0_wb + i0_rs1_class_d := Mux(i0_rs1_depend_i0_x.asBool,i0_x_c,Mux(i0_rs1_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs1_class_d))) + i0_rs1_depth_d := Mux(i0_rs1_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs1_depend_i0_r.asBool, 2.U(2.W), 0.U)) + i0_rs2_class_d := Mux(i0_rs2_depend_i0_x.asBool,i0_x_c,Mux(i0_rs2_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs2_class_d))) + i0_rs2_depth_d := Mux(i0_rs2_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs2_depend_i0_r.asBool, 2.U(2.W), 0.U)) + + // stores will bypass load data in the lsu pipe + if (LOAD_TO_USE_PLUS1) { + i0_load_block_d := (i0_rs1_class_d.load & i0_rs1_depth_d) | (i0_rs2_class_d.load & i0_rs2_depth_d(0) & !i0_dp.store) + load_ldst_bypass_d := (i0_dp.load | i0_dp.store) & i0_rs1_depth_d(1) & i0_rs1_class_d.load + store_data_bypass_d := i0_dp.store & (i0_rs2_depth_d(1) & i0_rs2_class_d.load) + store_data_bypass_m := i0_dp.store & (i0_rs2_depth_d(0) & i0_rs2_class_d.load) + } + else { + i0_load_block_d := 0.B + load_ldst_bypass_d := (i0_dp.load | i0_dp.store) & i0_rs1_depth_d(0) & i0_rs1_class_d.load + store_data_bypass_d := i0_dp.store & i0_rs2_depth_d(0) & i0_rs2_class_d.load + store_data_bypass_m := 0.B + } + // add nonblock load rs1/rs2 bypass cases + + val i0_rs1_nonblock_load_bypass_en_d = io.decode_exu.dec_i0_rs1_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs1) + + val i0_rs2_nonblock_load_bypass_en_d = io.decode_exu.dec_i0_rs2_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs2) + + // bit 2 is priority match, bit 0 lowest priority , i0_x, i0_r + i0_rs1bypass := Cat((i0_rs1_depth_d(0) &(i0_rs1_class_d.alu | i0_rs1_class_d.mul)),(i0_rs1_depth_d(0) & (i0_rs1_class_d.load)), (i0_rs1_depth_d(1) & (i0_rs1_class_d.alu | i0_rs1_class_d.mul | i0_rs1_class_d.load))) + + i0_rs2bypass := Cat((i0_rs2_depth_d(0) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul)),(i0_rs2_depth_d(0) & (i0_rs2_class_d.load)),(i0_rs2_depth_d(1) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul | i0_rs2_class_d.load))) + + io.decode_exu.dec_i0_rs1_bypass_en_d := Cat(!i0_rs1bypass(0) & !i0_rs1bypass(1) & !i0_rs1bypass(2) & i0_rs1_nonblock_load_bypass_en_d,i0_rs1bypass(2),i0_rs1bypass(1),i0_rs1bypass(0) ) + io.decode_exu.dec_i0_rs2_bypass_en_d := Cat(!i0_rs2bypass(0) & !i0_rs2bypass(1) & !i0_rs2bypass(2) & i0_rs2_nonblock_load_bypass_en_d,i0_rs2bypass(2),i0_rs2bypass(1),i0_rs2bypass(0) ) + + io.decode_exu.dec_i0_result_r := i0_result_r + + io.dec_lsu_valid_raw_d := ((io.dec_ib0_valid_d & (i0_dp_raw.load | i0_dp_raw.store) & !io.dctl_dma.dma_dccm_stall_any & !i0_block_raw_d) | io.decode_exu.dec_extint_stall) + io.dec_lsu_offset_d := Mux1H(Seq( + (!io.decode_exu.dec_extint_stall & i0_dp.lsu & i0_dp.load).asBool -> i0(31,20), + (!io.decode_exu.dec_extint_stall & i0_dp.lsu & i0_dp.store).asBool -> Cat(i0(31,25),i0(11,7)))) +} diff --git a/src/main/scala/dec/dec_gpr_ctl.scala b/src/main/scala/dec/dec_gpr_ctl.scala index 3302dca6..14afa169 100644 --- a/src/main/scala/dec/dec_gpr_ctl.scala +++ b/src/main/scala/dec/dec_gpr_ctl.scala @@ -47,20 +47,20 @@ class dec_gpr_ctl extends Module with lib with RequireAsyncReset{ gpr_in(0):=0.U io.gpr_exu.gpr_i0_rs1_d:=0.U io.gpr_exu.gpr_i0_rs2_d:=0.U - // GPR Write logic - for (j <-1 until 32){ - w0v(j) := io.wen0 & (io.waddr0===j.asUInt) - w1v(j) := io.wen1 & (io.waddr1===j.asUInt) - w2v(j) := io.wen2 & (io.waddr2===j.asUInt) - gpr_in(j) := (Fill(32,w0v(j)) & io.wd0) | (Fill(32,w1v(j)) & io.wd1) | (Fill(32,w2v(j)) & io.wd2) - } + // GPR Write logic + for (j <-1 until 32){ + w0v(j) := io.wen0 & (io.waddr0===j.asUInt) + w1v(j) := io.wen1 & (io.waddr1===j.asUInt) + w2v(j) := io.wen2 & (io.waddr2===j.asUInt) + gpr_in(j) := (Fill(32,w0v(j)) & io.wd0) | (Fill(32,w1v(j)) & io.wd1) | (Fill(32,w2v(j)) & io.wd2) + } gpr_wr_en:= (w0v.reverse).reduceRight(Cat(_,_)) | (w1v.reverse).reduceRight(Cat(_,_)) | (w2v.reverse).reduceRight(Cat(_,_)) // GPR Write Enables for power savings - for (j <-1 until 32){ - gpr_out(j):=rvdffe(gpr_in(j),gpr_wr_en(j),clock,io.scan_mode) - } - // GPR Read logic + for (j <-1 until 32){ + gpr_out(j):=rvdffe(gpr_in(j),gpr_wr_en(j),clock,io.scan_mode) + } + // GPR Read logic io.gpr_exu.gpr_i0_rs1_d:=Mux1H((1 until 32).map(i => (io.raddr0===i.U).asBool -> gpr_out(i))) io.gpr_exu.gpr_i0_rs2_d:=Mux1H((1 until 32).map(i => (io.raddr1===i.U).asBool -> gpr_out(i))) } diff --git a/src/main/scala/dec/dec_ib_ctl.scala b/src/main/scala/dec/dec_ib_ctl.scala index 0b993f52..4536e001 100644 --- a/src/main/scala/dec/dec_ib_ctl.scala +++ b/src/main/scala/dec/dec_ib_ctl.scala @@ -10,6 +10,8 @@ class dec_ib_ctl_IO extends Bundle with param{ val ifu_ib = Flipped(new aln_ib) val ib_exu = Flipped(new ib_exu) val dbg_ib = new dbg_ib + val dec_debug_valid_d =Output(UInt(1.W)) + val dec_ib0_valid_d =Output(UInt(1.W)) // ib0 valid val dec_i0_icaf_type_d =Output(UInt(2.W)) // i0 instruction access fault type val dec_i0_instr_d =Output(UInt(32.W)) // i0 inst at decode @@ -18,15 +20,18 @@ class dec_ib_ctl_IO extends Bundle with param{ val dec_i0_bp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index val dec_i0_bp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // BP FGHR val dec_i0_bp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // BP tag + val ifu_i0_fa_index =Input(UInt(log2Ceil(BTB_SIZE).W)) + val dec_i0_bp_fa_index =Output(UInt(log2Ceil(BTB_SIZE).W)) + val dec_i0_icaf_d =Output(UInt(1.W)) // i0 instruction access fault at decode - val dec_i0_icaf_f1_d =Output(UInt(1.W)) // i0 instruction access fault at decode for f1 fetch group + val dec_i0_icaf_second_d =Output(UInt(1.W)) // i0 instruction access fault at decode for f1 fetch group val dec_i0_dbecc_d =Output(UInt(1.W)) // i0 double-bit error at decode val dec_debug_fence_d =Output(UInt(1.W)) // debug fence inst } class dec_ib_ctl extends Module with param{ val io=IO(new dec_ib_ctl_IO) - io.dec_i0_icaf_f1_d :=io.ifu_ib.ifu_i0_icaf_f1 + io.dec_i0_icaf_second_d :=io.ifu_ib.ifu_i0_icaf_second io.dec_i0_dbecc_d :=io.ifu_ib.ifu_i0_dbecc io.dec_i0_icaf_d :=io.ifu_ib.ifu_i0_icaf io.ib_exu.dec_i0_pc_d :=io.ifu_ib.ifu_i0_pc @@ -36,6 +41,7 @@ class dec_ib_ctl extends Module with param{ io.dec_i0_bp_index :=io.ifu_ib.ifu_i0_bp_index io.dec_i0_bp_fghr :=io.ifu_ib.ifu_i0_bp_fghr io.dec_i0_bp_btag :=io.ifu_ib.ifu_i0_bp_btag + io.dec_i0_bp_fa_index := io.ifu_i0_fa_index // GPR accesses // put reg to read on rs1 @@ -52,7 +58,7 @@ class dec_ib_ctl extends Module with param{ val debug_valid =io.dbg_ib.dbg_cmd_valid & (io.dbg_ib.dbg_cmd_type =/= 2.U) val debug_read =debug_valid & !io.dbg_ib.dbg_cmd_write val debug_write =debug_valid & io.dbg_ib.dbg_cmd_write - + io.dec_debug_valid_d := debug_valid val debug_read_gpr = debug_read & (io.dbg_ib.dbg_cmd_type===0.U) val debug_write_gpr = debug_write & (io.dbg_ib.dbg_cmd_type===0.U) val debug_read_csr = debug_read & (io.dbg_ib.dbg_cmd_type===1.U) @@ -62,11 +68,11 @@ class dec_ib_ctl extends Module with param{ val dcsr = io.dbg_ib.dbg_cmd_addr(11,0) val ib0_debug_in =Mux1H(Seq( - debug_read_gpr.asBool -> Cat(Fill(12,0.U(1.W)),dreg,"b110000000110011".U), - debug_write_gpr.asBool -> Cat("b00000000000000000110".U(20.W),dreg,"b0110011".U(7.W)), - debug_read_csr.asBool -> Cat(dcsr,"b00000010000001110011".U(20.W)), - debug_write_csr.asBool -> Cat(dcsr,"b00000001000001110011".U(20.W)) - )) + debug_read_gpr.asBool -> Cat(Fill(12,0.U(1.W)),dreg,"b110000000110011".U), + debug_write_gpr.asBool -> Cat("b00000000000000000110".U(20.W),dreg,"b0110011".U(7.W)), + debug_read_csr.asBool -> Cat(dcsr,"b00000010000001110011".U(20.W)), + debug_write_csr.asBool -> Cat(dcsr,"b00000001000001110011".U(20.W)) + )) // machine is in halted state, pipe empty, write will always happen next cycle io.ib_exu.dec_debug_wdata_rs1_d := debug_write_gpr | debug_write_csr @@ -77,5 +83,4 @@ class dec_ib_ctl extends Module with param{ io.dec_ib0_valid_d := io.ifu_ib.ifu_i0_valid | debug_valid io.dec_i0_instr_d := Mux(debug_valid.asBool,ib0_debug_in,io.ifu_ib.ifu_i0_instr) - } diff --git a/src/main/scala/dec/dec_tlu_ctl.scala b/src/main/scala/dec/dec_tlu_ctl.scala index 445472f6..6b141736 100644 --- a/src/main/scala/dec/dec_tlu_ctl.scala +++ b/src/main/scala/dec/dec_tlu_ctl.scala @@ -28,8 +28,8 @@ trait CSR_VAL { val DCSR_STEPIE =11 val DCSR_STOPC =10 val DCSR_STEP =2 - - val MTDATA1_DMODE =9 + + val MTDATA1_DMODE =9 val MTDATA1_SEL =7 val MTDATA1_ACTION =6 val MTDATA1_CHAIN =5 @@ -45,21 +45,22 @@ trait CSR_VAL { class dec_tlu_ctl_IO extends Bundle with lib { val tlu_exu = Flipped(new tlu_exu) val tlu_dma = new tlu_dma - val active_clk = Input(Clock()) + // val active_clk = Input(Clock()) val free_clk = Input(Clock()) + val free_l2clk = Input(Clock()) val scan_mode = Input(Bool()) - val rst_vec = Input(UInt(31.W)) // reset vector, from core pins - val nmi_int = Input(UInt(1.W)) // nmi pin - val nmi_vec = Input(UInt(31.W)) // nmi vector - val i_cpu_halt_req = Input(UInt(1.W)) // Asynchronous Halt request to CPU - val i_cpu_run_req = Input(UInt(1.W)) // Asynchronous Restart request to CPU + val rst_vec = Input(UInt(31.W)) // reset vector, from core pins + val nmi_int = Input(UInt(1.W)) // nmi pin + val nmi_vec = Input(UInt(31.W)) // nmi vector + val i_cpu_halt_req = Input(UInt(1.W)) // Asynchronous Halt request to CPU + val i_cpu_run_req = Input(UInt(1.W)) // Asynchronous Restart request to CPU val lsu_fastint_stall_any = Input(UInt(1.W)) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle - val lsu_idle_any = Input(UInt(1.W)) // lsu is idle + val lsu_idle_any = Input(UInt(1.W)) // lsu is idle // perf counter inputs - val dec_pmu_instr_decoded = Input(UInt(1.W))// decoded instructions - val dec_pmu_decode_stall = Input(UInt(1.W))// decode stall - val dec_pmu_presync_stall = Input(UInt(1.W))// decode stall due to presync'd inst - val dec_pmu_postsync_stall = Input(UInt(1.W))// decode stall due to postsync'd inst + val dec_pmu_instr_decoded = Input(UInt(1.W))// decoded instructions + val dec_pmu_decode_stall = Input(UInt(1.W))// decode stall + val dec_pmu_presync_stall = Input(UInt(1.W))// decode stall due to presync'd inst + val dec_pmu_postsync_stall = Input(UInt(1.W))// decode stall due to postsync'd inst val lsu_store_stall_any = Input(UInt(1.W))// SB or WB is full, stall decode val lsu_fir_addr = Input(UInt(31.W)) // Fast int address val lsu_fir_error = Input(UInt(2.W)) // Fast int lookup error @@ -81,6 +82,7 @@ class dec_tlu_ctl_IO extends Bundle with lib { val dec_i0_decode_d = Input(UInt(1.W)) // decode valid, used for clean icache diagnostics val exu_i0_br_way_r = Input(UInt(1.W))// way hit or repl + val dec_tlu_core_empty = Output(UInt(1.W)) // abstract command done // Debug start val dec_dbg_cmd_done = Output(UInt(1.W)) // abstract command done val dec_dbg_cmd_fail = Output(UInt(1.W)) // abstract command failed @@ -94,10 +96,10 @@ class dec_tlu_ctl_IO extends Bundle with lib { val dbg_resume_req = Input(UInt(1.W)) // DM requests a resume val dec_div_active = Input(UInt(1.W)) // oop div is active val trigger_pkt_any = Output(Vec(4,new trigger_pkt_t))// trigger info for trigger blocks -// val pic_claimid = Input(UInt(8.W)) // pic claimid for csr -// val pic_pl = Input(UInt(4.W)) // pic priv level for csr -// val mhwakeup = Input(UInt(1.W)) // high priority external int, wakeup if halted -// val mexintpend= Input(UInt(1.W)) // external interrupt pending + // val pic_claimid = Input(UInt(8.W)) // pic claimid for csr + // val pic_pl = Input(UInt(4.W)) // pic priv level for csr + // val mhwakeup = Input(UInt(1.W)) // high priority external int, wakeup if halted + // val mexintpend= Input(UInt(1.W)) // external interrupt pending val timer_int= Input(UInt(1.W)) // timer interrupt pending val soft_int= Input(UInt(1.W)) // software interrupt pending val o_cpu_halt_status = Output(UInt(1.W)) // PMU interface, halted @@ -112,8 +114,8 @@ class dec_tlu_ctl_IO extends Bundle with lib { val mpc_debug_halt_ack = Output(UInt(1.W)) // Halt ack val mpc_debug_run_ack = Output(UInt(1.W)) // Run ack val debug_brkpt_status = Output(UInt(1.W)) // debug breakpoint -// val dec_tlu_meicurpl = Output(UInt(4.W)) // to PIC -// val dec_tlu_meipt = Output(UInt(4.W)) // to PIC + // val dec_tlu_meicurpl = Output(UInt(4.W)) // to PIC + // val dec_tlu_meipt = Output(UInt(4.W)) // to PIC val dec_csr_rddata_d = Output(UInt(32.W)) // csr read data at wb val dec_csr_legal_d = Output(UInt(1.W)) // csr indicates legal operation val dec_tlu_i0_kill_writeb_wb = Output(UInt(1.W)) // I0 is flushed, don't writeback any results to arch state @@ -132,6 +134,8 @@ class dec_tlu_ctl_IO extends Bundle with lib { val dec_tlu_exc_cause_wb1 = Output(UInt(5.W)) // exception or int cause val dec_tlu_mtval_wb1 = Output(UInt(32.W)) // MTVAL value val dec_tlu_pipelining_disable = Output(UInt(1.W)) // disable pipelining + + val dec_tlu_trace_disable = Output(Bool()) // disable pipelining // clock gating overrides from mcgc val dec_tlu_misc_clk_override = Output(UInt(1.W)) // override misc clock domain gating val dec_tlu_dec_clk_override = Output(UInt(1.W)) // override decode clock domain gating @@ -139,6 +143,8 @@ class dec_tlu_ctl_IO extends Bundle with lib { val dec_tlu_lsu_clk_override = Output(UInt(1.W)) // override load/store clock domain gating val dec_tlu_bus_clk_override = Output(UInt(1.W)) // override bus clock domain gating val dec_tlu_pic_clk_override = Output(UInt(1.W)) // override PIC clock domain gating + + val dec_tlu_picio_clk_override = Output(UInt(1.W)) // override PIC clock domain gating val dec_tlu_dccm_clk_override = Output(UInt(1.W)) // override DCCM clock domain gating val dec_tlu_icm_clk_override = Output(UInt(1.W)) // override ICCM clock domain gating val dec_tlu_flush_lower_wb = Output(Bool()) @@ -151,284 +157,300 @@ class dec_tlu_ctl_IO extends Bundle with lib { val dec_pic = new dec_pic } class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ - val io = IO(new dec_tlu_ctl_IO) + val io = IO(new dec_tlu_ctl_IO) val mtdata1_t = Wire(Vec(4,UInt(10.W))) - val pause_expired_wb = WireInit(UInt(1.W), 0.U) - val take_nmi_r_d1 = WireInit(UInt(1.W),0.U) - val exc_or_int_valid_r_d1 = WireInit(UInt(1.W),0.U) - val interrupt_valid_r_d1 = WireInit(UInt(1.W),0.U) - val tlu_flush_lower_r = WireInit(UInt(1.W),0.U) - val synchronous_flush_r = WireInit(UInt(1.W),0.U) - val interrupt_valid_r = WireInit(UInt(1.W),0.U) - val take_nmi = WireInit(UInt(1.W),0.U) - val take_reset = WireInit(UInt(1.W),0.U) - val take_int_timer1_int = WireInit(UInt(1.W),0.U) - val take_int_timer0_int = WireInit(UInt(1.W),0.U) - val take_timer_int = WireInit(UInt(1.W),0.U) - val take_soft_int = WireInit(UInt(1.W),0.U) - val take_ce_int = WireInit(UInt(1.W),0.U) - val take_ext_int_start = WireInit(UInt(1.W),0.U) - val ext_int_freeze = WireInit(UInt(1.W),0.U) - val ext_int_freeze_d1 = WireInit(UInt(1.W),0.U) - val take_ext_int_start_d1 = WireInit(UInt(1.W),0.U) - val take_ext_int_start_d2 = WireInit(UInt(1.W),0.U) - val take_ext_int_start_d3 = WireInit(UInt(1.W),0.U) - val fast_int_meicpct = WireInit(UInt(1.W),0.U) - val ignore_ext_int_due_to_lsu_stall = WireInit(UInt(1.W),0.U) - val take_ext_int = WireInit(UInt(1.W),0.U) - val internal_dbg_halt_timers = WireInit(UInt(1.W),0.U) - val int_timer1_int_hold = WireInit(UInt(1.W),0.U) - val int_timer0_int_hold = WireInit(UInt(1.W),0.U) - val mhwakeup_ready = WireInit(UInt(1.W),0.U) - val ext_int_ready = WireInit(UInt(1.W),0.U) - val ce_int_ready = WireInit(UInt(1.W),0.U) - val soft_int_ready = WireInit(UInt(1.W),0.U) - val timer_int_ready = WireInit(UInt(1.W),0.U) - val ebreak_to_debug_mode_r_d1 = WireInit(UInt(1.W),0.U) - val ebreak_to_debug_mode_r = WireInit(UInt(1.W),0.U) - val inst_acc_r = WireInit(UInt(1.W),0.U) - val inst_acc_r_raw = WireInit(UInt(1.W),0.U) - val iccm_sbecc_r = WireInit(UInt(1.W),0.U) - val ic_perr_r = WireInit(UInt(1.W),0.U) - val fence_i_r = WireInit(UInt(1.W),0.U) - val ebreak_r = WireInit(UInt(1.W),0.U) - val ecall_r = WireInit(UInt(1.W),0.U) - val illegal_r = WireInit(UInt(1.W),0.U) - val mret_r = WireInit(UInt(1.W),0.U) - val iccm_repair_state_ns = WireInit(UInt(1.W),0.U) - val rfpc_i0_r = WireInit(UInt(1.W),0.U) - val tlu_i0_kill_writeb_r = WireInit(UInt(1.W),0.U) - val lsu_exc_valid_r_d1 = WireInit(UInt(1.W),0.U) - val lsu_i0_exc_r_raw = WireInit(UInt(1.W),0.U) - val mdseac_locked_f = WireInit(UInt(1.W),0.U) - val i_cpu_run_req_d1 = WireInit(UInt(1.W),0.U) - val cpu_run_ack = WireInit(UInt(1.W),0.U) - val cpu_halt_status = WireInit(UInt(1.W),0.U) - val cpu_halt_ack = WireInit(UInt(1.W),0.U) - val pmu_fw_tlu_halted = WireInit(UInt(1.W),0.U) - val internal_pmu_fw_halt_mode = WireInit(UInt(1.W),0.U) - val pmu_fw_halt_req_ns = WireInit(UInt(1.W),0.U) - val pmu_fw_halt_req_f = WireInit(UInt(1.W),0.U) - val pmu_fw_tlu_halted_f = WireInit(UInt(1.W),0.U) - val int_timer0_int_hold_f = WireInit(UInt(1.W),0.U) - val int_timer1_int_hold_f = WireInit(UInt(1.W),0.U) - val trigger_hit_dmode_r = WireInit(UInt(1.W),0.U) - val i0_trigger_hit_r = WireInit(UInt(1.W),0.U) - val pause_expired_r = WireInit(UInt(1.W),0.U) - val dec_tlu_pmu_fw_halted = WireInit(UInt(1.W),0.U) - val dec_tlu_flush_noredir_r_d1= WireInit(UInt(1.W),0.U) - val halt_taken_f = WireInit(UInt(1.W),0.U) - val lsu_idle_any_f = WireInit(UInt(1.W),0.U) - val ifu_miss_state_idle_f = WireInit(UInt(1.W),0.U) - val dbg_tlu_halted_f = WireInit(UInt(1.W),0.U) - val debug_halt_req_f = WireInit(UInt(1.W),0.U) - val debug_resume_req_f = WireInit(UInt(1.W),0.U) - val trigger_hit_dmode_r_d1 = WireInit(UInt(1.W),0.U) - val dcsr_single_step_done_f = WireInit(UInt(1.W),0.U) - val debug_halt_req_d1 = WireInit(UInt(1.W),0.U) - val request_debug_mode_r_d1 = WireInit(UInt(1.W),0.U) - val request_debug_mode_done_f = WireInit(UInt(1.W),0.U) - val dcsr_single_step_running_f = WireInit(UInt(1.W),0.U) - val dec_tlu_flush_pause_r_d1 = WireInit(UInt(1.W),0.U) - val dbg_halt_req_held = WireInit(UInt(1.W),0.U) - val debug_halt_req_ns = WireInit(UInt(1.W),0.U) - val internal_dbg_halt_mode = WireInit(UInt(1.W),0.U) - val core_empty = WireInit(UInt(1.W),0.U) - val dbg_halt_req_final = WireInit(UInt(1.W),0.U) - val debug_brkpt_status_ns = WireInit(UInt(1.W),0.U) - val mpc_debug_halt_ack_ns = WireInit(UInt(1.W),0.U) - val mpc_debug_run_ack_ns = WireInit(UInt(1.W),0.U) - val mpc_halt_state_ns = WireInit(UInt(1.W),0.U) - val mpc_run_state_ns = WireInit(UInt(1.W),0.U) - val dbg_halt_state_ns = WireInit(UInt(1.W),0.U) - val dbg_run_state_ns = WireInit(UInt(1.W),0.U) - val dbg_halt_state_f = WireInit(UInt(1.W),0.U) - val mpc_halt_state_f = WireInit(UInt(1.W),0.U) - val nmi_int_detected = WireInit(UInt(1.W),0.U) - val nmi_lsu_load_type = WireInit(UInt(1.W),0.U) - val nmi_lsu_store_type = WireInit(UInt(1.W),0.U) - val reset_delayed = WireInit(UInt(1.W),0.U) - val internal_dbg_halt_mode_f = WireInit(UInt(1.W),0.U) - val e5_valid = WireInit(UInt(1.W),0.U) - val ic_perr_r_d1 = WireInit(UInt(1.W),0.U) - val iccm_sbecc_r_d1 = WireInit(UInt(1.W),0.U) + val pause_expired_wb =WireInit(UInt(1.W), 0.U) + val take_nmi_r_d1 =WireInit(UInt(1.W),0.U) + val exc_or_int_valid_r_d1 =WireInit(UInt(1.W),0.U) + val interrupt_valid_r_d1 =WireInit(Bool(),0.B) + val tlu_flush_lower_r =WireInit(UInt(1.W),0.U) + val synchronous_flush_r =WireInit(UInt(1.W),0.U) + val interrupt_valid_r =WireInit(UInt(1.W),0.U) + val take_nmi =WireInit(UInt(1.W),0.U) + val take_reset =WireInit(UInt(1.W),0.U) + val take_int_timer1_int =WireInit(UInt(1.W),0.U) + val take_int_timer0_int =WireInit(UInt(1.W),0.U) + val take_timer_int =WireInit(UInt(1.W),0.U) + val take_soft_int =WireInit(UInt(1.W),0.U) + val take_ce_int =WireInit(UInt(1.W),0.U) + val take_ext_int_start =WireInit(UInt(1.W),0.U) + val ext_int_freeze =WireInit(UInt(1.W),0.U) + // val ext_int_freeze_d1 =WireInit(UInt(1.W),0.U) + // val take_ext_int_start_d1 =WireInit(UInt(1.W),0.U) + val take_ext_int_start_d2 =WireInit(UInt(1.W),0.U) + val take_ext_int_start_d3 =WireInit(UInt(1.W),0.U) + val fast_int_meicpct =WireInit(UInt(1.W),0.U) + val ignore_ext_int_due_to_lsu_stall =WireInit(UInt(1.W),0.U) + val take_ext_int =WireInit(UInt(1.W),0.U) + val internal_dbg_halt_timers =WireInit(UInt(1.W),0.U) + val int_timer1_int_hold =WireInit(UInt(1.W),0.U) + val int_timer0_int_hold =WireInit(UInt(1.W),0.U) + val mhwakeup_ready =WireInit(UInt(1.W),0.U) + val ext_int_ready =WireInit(UInt(1.W),0.U) + val ce_int_ready =WireInit(UInt(1.W),0.U) + val soft_int_ready =WireInit(UInt(1.W),0.U) + val timer_int_ready =WireInit(UInt(1.W),0.U) + val ebreak_to_debug_mode_r_d1 =WireInit(UInt(1.W),0.U) + val ebreak_to_debug_mode_r =WireInit(UInt(1.W),0.U) + val inst_acc_r =WireInit(UInt(1.W),0.U) + val inst_acc_r_raw =WireInit(UInt(1.W),0.U) + val iccm_sbecc_r =WireInit(UInt(1.W),0.U) + val ic_perr_r =WireInit(UInt(1.W),0.U) + val fence_i_r =WireInit(UInt(1.W),0.U) + val ebreak_r =WireInit(UInt(1.W),0.U) + val ecall_r =WireInit(UInt(1.W),0.U) + val illegal_r =WireInit(UInt(1.W),0.U) + val mret_r =WireInit(UInt(1.W),0.U) + val iccm_repair_state_ns =WireInit(UInt(1.W),0.U) + val rfpc_i0_r =WireInit(UInt(1.W),0.U) + val tlu_i0_kill_writeb_r =WireInit(UInt(1.W),0.U) + val lsu_exc_valid_r_d1 =WireInit(UInt(1.W),0.U) + val lsu_i0_exc_r_raw =WireInit(UInt(1.W),0.U) + val mdseac_locked_f =WireInit(UInt(1.W),0.U) + val i_cpu_run_req_d1 =WireInit(UInt(1.W),0.U) + val cpu_run_ack =WireInit(UInt(1.W),0.U) + val cpu_halt_status =WireInit(UInt(1.W),0.U) + val cpu_halt_ack =WireInit(UInt(1.W),0.U) + val pmu_fw_tlu_halted =WireInit(UInt(1.W),0.U) + val internal_pmu_fw_halt_mode =WireInit(UInt(1.W),0.U) + val pmu_fw_halt_req_ns =WireInit(UInt(1.W),0.U) + val pmu_fw_halt_req_f =WireInit(UInt(1.W),0.U) + val pmu_fw_tlu_halted_f =WireInit(UInt(1.W),0.U) + val int_timer0_int_hold_f =WireInit(UInt(1.W),0.U) + val int_timer1_int_hold_f =WireInit(UInt(1.W),0.U) + val trigger_hit_dmode_r =WireInit(UInt(1.W),0.U) + val i0_trigger_hit_r =WireInit(UInt(1.W),0.U) + val pause_expired_r =WireInit(UInt(1.W),0.U) + val dec_tlu_pmu_fw_halted =WireInit(UInt(1.W),0.U) + val dec_tlu_flush_noredir_r_d1 =WireInit(UInt(1.W),0.U) + val halt_taken_f =WireInit(UInt(1.W),0.U) + val lsu_idle_any_f =WireInit(UInt(1.W),0.U) + val ifu_miss_state_idle_f =WireInit(UInt(1.W),0.U) + val dbg_tlu_halted_f =WireInit(UInt(1.W),0.U) + val debug_halt_req_f =WireInit(UInt(1.W),0.U) + val debug_resume_req_f_raw =WireInit(UInt(1.W),0.U) + val debug_resume_req_f =WireInit(UInt(1.W),0.U) + val trigger_hit_dmode_r_d1 =WireInit(UInt(1.W),0.U) + val dcsr_single_step_done_f =WireInit(UInt(1.W),0.U) + val debug_halt_req_d1 =WireInit(UInt(1.W),0.U) + val request_debug_mode_r_d1 =WireInit(UInt(1.W),0.U) + val request_debug_mode_done_f =WireInit(UInt(1.W),0.U) + val dcsr_single_step_running_f =WireInit(UInt(1.W),0.U) + val dec_tlu_flush_pause_r_d1 =WireInit(UInt(1.W),0.U) + val dbg_halt_req_held =WireInit(UInt(1.W),0.U) + val debug_halt_req_ns =WireInit(UInt(1.W),0.U) + val internal_dbg_halt_mode =WireInit(UInt(1.W),0.U) + val core_empty =WireInit(UInt(1.W),0.U) + val dbg_halt_req_final =WireInit(UInt(1.W),0.U) + val debug_brkpt_status_ns =WireInit(UInt(1.W),0.U) + val mpc_debug_halt_ack_ns =WireInit(UInt(1.W),0.U) + val mpc_debug_run_ack_ns =WireInit(UInt(1.W),0.U) + val mpc_halt_state_ns =WireInit(UInt(1.W),0.U) + val mpc_run_state_ns =WireInit(UInt(1.W),0.U) + val dbg_halt_state_ns =WireInit(UInt(1.W),0.U) + val dbg_run_state_ns =WireInit(UInt(1.W),0.U) + val dbg_halt_state_f =WireInit(UInt(1.W),0.U) + val mpc_halt_state_f =WireInit(UInt(1.W),0.U) + val nmi_int_detected =WireInit(UInt(1.W),0.U) + val nmi_lsu_load_type =WireInit(UInt(1.W),0.U) + val nmi_lsu_store_type =WireInit(UInt(1.W),0.U) + val reset_delayed =WireInit(UInt(1.W),0.U) + val internal_dbg_halt_mode_f =WireInit(UInt(1.W),0.U) + val e5_valid =WireInit(UInt(1.W),0.U) + val ic_perr_r_d1 =WireInit(UInt(1.W),0.U) + val iccm_sbecc_r_d1 =WireInit(UInt(1.W),0.U) - val npc_r = WireInit(UInt(31.W),0.U) - val npc_r_d1 = WireInit(UInt(31.W),0.U) - val mie_ns = WireInit(UInt(6.W),0.U) - val mepc = WireInit(UInt(31.W),0.U) - val mdseac_locked_ns = WireInit(UInt(1.W),0.U) - val force_halt = WireInit(UInt(1.W),0.U) - val dpc = WireInit(UInt(31.W),0.U) - val mstatus_mie_ns = WireInit(UInt(1.W),0.U) - val dec_csr_wen_r_mod = WireInit(UInt(1.W),0.U) - val fw_halt_req = WireInit(UInt(1.W),0.U) - val mstatus = WireInit(UInt(2.W),0.U) - val dcsr = WireInit(UInt(16.W),0.U) - val mtvec = WireInit(UInt(31.W),0.U) - val mip = WireInit(UInt(6.W),0.U) - val csr_pkt = Wire(new dec_tlu_csr_pkt) - val dec_tlu_mpc_halted_only_ns = WireInit(UInt(1.W),0.U) - // tell dbg we are only MPC halted + val npc_r = WireInit(UInt(31.W),0.U) + val npc_r_d1 = WireInit(UInt(31.W),0.U) + val mie_ns = WireInit(UInt(6.W),0.U) + val mepc = WireInit(UInt(31.W),0.U) + val mdseac_locked_ns = WireInit(UInt(1.W),0.U) + val force_halt = WireInit(UInt(1.W),0.U) + val dpc = WireInit(UInt(31.W),0.U) + val mstatus_mie_ns = WireInit(UInt(1.W),0.U) + val dec_csr_wen_r_mod = WireInit(UInt(1.W),0.U) + val fw_halt_req = WireInit(UInt(1.W),0.U) + val mstatus = WireInit(UInt(2.W),0.U) + val dcsr = WireInit(UInt(16.W),0.U) + val mtvec = WireInit(UInt(31.W),0.U) + val mip = WireInit(UInt(6.W),0.U) + val csr_pkt = Wire(new dec_tlu_csr_pkt) + val dec_tlu_mpc_halted_only_ns = WireInit(UInt(1.W),0.U) + // tell dbg we are only MPC halted dec_tlu_mpc_halted_only_ns := ~dbg_halt_state_f & mpc_halt_state_f - val int_timers = Module(new dec_timer_ctl) - int_timers.io.free_clk := io.free_clk - int_timers.io.scan_mode := io.scan_mode - int_timers.io.dec_csr_wen_r_mod := dec_csr_wen_r_mod - int_timers.io.dec_csr_rdaddr_d := io.dec_csr_rdaddr_d - int_timers.io.dec_csr_wraddr_r := io.dec_csr_wraddr_r - int_timers.io.dec_csr_wrdata_r := io.dec_csr_wrdata_r - int_timers.io.csr_mitctl0 := csr_pkt.csr_mitctl0 - int_timers.io.csr_mitctl1 := csr_pkt.csr_mitctl1 - int_timers.io.csr_mitb0 := csr_pkt.csr_mitb0 - int_timers.io.csr_mitb1 := csr_pkt.csr_mitb1 - int_timers.io.csr_mitcnt0 := csr_pkt.csr_mitcnt0 - int_timers.io.csr_mitcnt1 := csr_pkt.csr_mitcnt1 - int_timers.io.dec_pause_state := io.dec_pause_state - int_timers.io.dec_tlu_pmu_fw_halted := dec_tlu_pmu_fw_halted - int_timers.io.internal_dbg_halt_timers := internal_dbg_halt_timers + val int_exc = Module(new int_exc) + val csr=Module(new csr_tlu) + val int_timers=Module(new dec_timer_ctl) + int_timers.io.free_l2clk :=io.free_l2clk + int_timers.io.scan_mode :=io.scan_mode + int_timers.io.dec_csr_wen_r_mod :=dec_csr_wen_r_mod + // int_timers.io.dec_csr_rdaddr_d :=io.dec_csr_rdaddr_d + int_timers.io.dec_csr_wraddr_r :=io.dec_csr_wraddr_r + int_timers.io.dec_csr_wrdata_r :=io.dec_csr_wrdata_r + int_timers.io.csr_mitctl0 :=csr_pkt.csr_mitctl0 + int_timers.io.csr_mitctl1 :=csr_pkt.csr_mitctl1 + int_timers.io.csr_mitb0 :=csr_pkt.csr_mitb0 + int_timers.io.csr_mitb1 :=csr_pkt.csr_mitb1 + int_timers.io.csr_mitcnt0 :=csr_pkt.csr_mitcnt0 + int_timers.io.csr_mitcnt1 :=csr_pkt.csr_mitcnt1 + int_timers.io.dec_pause_state :=io.dec_pause_state + int_timers.io.dec_tlu_pmu_fw_halted :=dec_tlu_pmu_fw_halted + int_timers.io.internal_dbg_halt_timers:=internal_dbg_halt_timers + + val dec_timer_rddata_d =int_timers.io.dec_timer_rddata_d + val dec_timer_read_d =int_timers.io.dec_timer_read_d + val dec_timer_t0_pulse =int_timers.io.dec_timer_t0_pulse + val dec_timer_t1_pulse =int_timers.io.dec_timer_t1_pulse - val dec_timer_rddata_d = int_timers.io.dec_timer_rddata_d - val dec_timer_read_d = int_timers.io.dec_timer_read_d - val dec_timer_t0_pulse = int_timers.io.dec_timer_t0_pulse - val dec_timer_t1_pulse = int_timers.io.dec_timer_t1_pulse - val clk_override = io.dec_tlu_dec_clk_override - // Async inputs to the core have to be sync'd to the core clock. - - val syncro_ff = rvsyncss(Cat(io.nmi_int, io.timer_int, io.soft_int, io.i_cpu_halt_req, io.i_cpu_run_req, io.mpc_debug_halt_req, io.mpc_debug_run_req),io.free_clk) - val nmi_int_sync = syncro_ff(6) - val timer_int_sync = syncro_ff(5) - val soft_int_sync = syncro_ff(4) - val i_cpu_halt_req_sync = syncro_ff(3) - val i_cpu_run_req_sync = syncro_ff(2) - val mpc_debug_halt_req_sync_raw = syncro_ff(1) - val mpc_debug_run_req_sync = syncro_ff(0) - - // for CSRs that have inpipe writes only - val csr_wr_clk = rvclkhdr(clock,(dec_csr_wen_r_mod | clk_override).asBool,io.scan_mode) - val lsu_r_wb_clk = rvclkhdr(clock,(io.lsu_error_pkt_r.valid | lsu_exc_valid_r_d1 | clk_override).asBool,io.scan_mode) + // Async inputs to the core have to be sync'd to the core clock. - val e4_valid = io.dec_tlu_i0_valid_r - val e4e5_valid = e4_valid | e5_valid - val flush_clkvalid = internal_dbg_halt_mode_f | i_cpu_run_req_d1 | interrupt_valid_r | interrupt_valid_r_d1 | reset_delayed | pause_expired_r | pause_expired_wb | ic_perr_r | ic_perr_r_d1 | iccm_sbecc_r | iccm_sbecc_r_d1 | clk_override - - val e4e5_clk = rvclkhdr(clock,(e4e5_valid | clk_override).asBool,io.scan_mode) - val e4e5_int_clk = rvclkhdr(clock,(e4e5_valid | flush_clkvalid).asBool,io.scan_mode) - - val iccm_repair_state_d1 = withClock(io.free_clk){RegNext(iccm_repair_state_ns,0.U)} - ic_perr_r_d1 := withClock(io.free_clk){RegNext(ic_perr_r,0.U)} - iccm_sbecc_r_d1 := withClock(io.free_clk){RegNext(iccm_sbecc_r,0.U)} - e5_valid := withClock(io.free_clk){RegNext(e4_valid,0.U)} - internal_dbg_halt_mode_f := withClock(io.free_clk){RegNext(internal_dbg_halt_mode,0.U)} - val lsu_pmu_load_external_r = withClock(io.free_clk){RegNext(io.lsu_tlu.lsu_pmu_load_external_m,0.U)} - val lsu_pmu_store_external_r = withClock(io.free_clk){RegNext(io.lsu_tlu.lsu_pmu_store_external_m,0.U)} - val tlu_flush_lower_r_d1 = withClock(io.free_clk){RegNext(tlu_flush_lower_r,0.U)} - io.dec_tlu_i0_kill_writeb_wb := withClock(io.free_clk){RegNext(tlu_i0_kill_writeb_r,0.U)} - val internal_dbg_halt_mode_f2 = withClock(io.free_clk){RegNext(internal_dbg_halt_mode_f,0.U)} - io.tlu_mem.dec_tlu_force_halt := withClock(io.free_clk){RegNext(force_halt,0.U)} + val syncro_ff=rvsyncss(Cat(io.nmi_int, io.timer_int, io.soft_int, io.i_cpu_halt_req, io.i_cpu_run_req, io.mpc_debug_halt_req, io.mpc_debug_run_req),io.free_clk) + val nmi_int_sync =syncro_ff(6) + val timer_int_sync =syncro_ff(5) + val soft_int_sync =syncro_ff(4) + val i_cpu_halt_req_sync =syncro_ff(3) + val i_cpu_run_req_sync =syncro_ff(2) + val mpc_debug_halt_req_sync_raw =syncro_ff(1) + val mpc_debug_run_req_sync =syncro_ff(0) - io.dec_tlu_i0_kill_writeb_r := tlu_i0_kill_writeb_r - val reset_detect = withClock(io.free_clk){RegNext(1.U(1.W),0.U)} - val reset_detected = withClock(io.free_clk){RegNext(reset_detect,0.U)} - reset_delayed := reset_detect ^ reset_detected - - val nmi_int_delayed = withClock(io.free_clk){RegNext(nmi_int_sync,0.U)} - val nmi_int_detected_f = withClock(io.free_clk){RegNext(nmi_int_detected,0.U)} - val nmi_lsu_load_type_f = withClock(io.free_clk){RegNext(nmi_lsu_load_type,0.U)} - val nmi_lsu_store_type_f = withClock(io.free_clk){RegNext(nmi_lsu_store_type,0.U)} + // for CSRs that have inpipe writes only + val csr_wr_clk=rvoclkhdr(clock,(dec_csr_wen_r_mod | clk_override).asBool,io.scan_mode) + int_timers.io.csr_wr_clk := csr_wr_clk + // val lsu_r_wb_clk=rvclkhdr(clock,(io.lsu_error_pkt_r.valid | lsu_exc_valid_r_d1 | clk_override).asBool,io.scan_mode) + + val e4_valid = io.dec_tlu_i0_valid_r + val e4e5_valid = e4_valid | e5_valid + val flush_clkvalid = internal_dbg_halt_mode_f | i_cpu_run_req_d1 | interrupt_valid_r | interrupt_valid_r_d1 | reset_delayed | pause_expired_r | pause_expired_wb | ic_perr_r | iccm_sbecc_r | clk_override + + // dontTouch(flush_clkvalid) + val e4e5_clk=rvoclkhdr(clock,(e4e5_valid | clk_override).asBool,io.scan_mode) + val e4e5_int_clk=rvoclkhdr(clock,(e4e5_valid | flush_clkvalid).asBool,io.scan_mode) + + val ifu_ic_error_start_f =rvdffie(io.tlu_mem.ifu_ic_error_start,io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + val ifu_iccm_rd_ecc_single_err_f =rvdffie(io.tlu_mem.ifu_iccm_rd_ecc_single_err,io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + + val iccm_repair_state_d1 =rvdffie(iccm_repair_state_ns,io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + // ic_perr_r_d1 :=withClock(io.free_clk){RegNext(ic_perr_r,0.U)} + // iccm_sbecc_r_d1 :=withClock(io.free_clk){RegNext(iccm_sbecc_r,0.U)} + e5_valid :=rvdffie(e4_valid,io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + internal_dbg_halt_mode_f :=rvdffie(internal_dbg_halt_mode,io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + val lsu_pmu_load_external_r =rvdffie(io.lsu_tlu.lsu_pmu_load_external_m,io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + val lsu_pmu_store_external_r =rvdffie(io.lsu_tlu.lsu_pmu_store_external_m,io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + val tlu_flush_lower_r_d1 =rvdffie(tlu_flush_lower_r,io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + io.dec_tlu_i0_kill_writeb_wb :=rvdffie(tlu_i0_kill_writeb_r,io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + val internal_dbg_halt_mode_f2 =rvdffie(internal_dbg_halt_mode_f,io.free_l2clk, reset.asAsyncReset(), io.scan_mode) + io.tlu_mem.dec_tlu_force_halt :=rvdffie(force_halt,io.free_l2clk, reset.asAsyncReset(), io.scan_mode) - // Filter subsequent bus errors after the first, until the lock on MDSEAC is cleared - val nmi_lsu_detected = ~mdseac_locked_f & (io.tlu_busbuff.lsu_imprecise_error_load_any | io.tlu_busbuff.lsu_imprecise_error_store_any) - nmi_int_detected := (nmi_int_sync & ~nmi_int_delayed) | nmi_lsu_detected | (nmi_int_detected_f & ~take_nmi_r_d1) |(take_ext_int_start_d3 & io.lsu_fir_error.orR) - // if the first nmi is a lsu type, note it. If there's already an nmi pending, ignore - nmi_lsu_load_type := (nmi_lsu_detected & io.tlu_busbuff.lsu_imprecise_error_load_any & ~(nmi_int_detected_f & ~take_nmi_r_d1)) | (nmi_lsu_load_type_f & ~take_nmi_r_d1) + io.dec_tlu_i0_kill_writeb_r :=tlu_i0_kill_writeb_r + + val nmi_int_delayed =rvdffie(nmi_int_sync, io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + val nmi_int_detected_f =rvdffie(nmi_int_detected, io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + val nmi_lsu_load_type_f =rvdffie(nmi_lsu_load_type, io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + val nmi_lsu_store_type_f =rvdffie(nmi_lsu_store_type, io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + + val nmi_fir_type = WireInit(UInt(1.W),0.U) + val nmi_lsu_detected = ~mdseac_locked_f & (io.tlu_busbuff.lsu_imprecise_error_load_any | io.tlu_busbuff.lsu_imprecise_error_store_any) & ~nmi_fir_type + + // Filter subsequent bus errors after the first, until the lock on MDSEAC is cleared + nmi_int_detected := (nmi_int_sync & ~nmi_int_delayed) | nmi_lsu_detected | (nmi_int_detected_f & ~take_nmi_r_d1) | nmi_fir_type + // if the first nmi is a lsu type, note it. If there's already an nmi pending, ignore. Simultaneous with FIR, drop. + nmi_lsu_load_type := (nmi_lsu_detected & io.tlu_busbuff.lsu_imprecise_error_load_any & ~(nmi_int_detected_f & ~take_nmi_r_d1)) | (nmi_lsu_load_type_f & ~take_nmi_r_d1) nmi_lsu_store_type := (nmi_lsu_detected & io.tlu_busbuff.lsu_imprecise_error_store_any & ~(nmi_int_detected_f & ~take_nmi_r_d1)) | (nmi_lsu_store_type_f & ~take_nmi_r_d1) + nmi_fir_type := ~nmi_int_detected_f & csr.io.take_ext_int_start_d3 & io.lsu_fir_error.orR + + val reset_detect =rvdffie(1.U(1.W), io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + val reset_detected =rvdffie(reset_detect, io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + reset_delayed :=reset_detect ^ reset_detected + + // ---------------------------------------------------------------------- - // MPC halt - // - can interact with debugger halt and v-v - - // fast ints in progress have priority - val mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & ~ext_int_freeze_d1 - val mpc_debug_halt_req_sync_f = withClock(io.free_clk){RegNext(mpc_debug_halt_req_sync,0.U)} - val mpc_debug_run_req_sync_f = withClock(io.free_clk){RegNext(mpc_debug_run_req_sync,0.U)} - mpc_halt_state_f := withClock(io.free_clk){RegNext(mpc_halt_state_ns,0.U)} - val mpc_run_state_f = withClock(io.free_clk){RegNext(mpc_run_state_ns,0.U)} - val debug_brkpt_status_f = withClock(io.free_clk){RegNext(debug_brkpt_status_ns,0.U)} - val mpc_debug_halt_ack_f = withClock(io.free_clk){RegNext(mpc_debug_halt_ack_ns,0.U)} - val mpc_debug_run_ack_f = withClock(io.free_clk){RegNext(mpc_debug_run_ack_ns,0.U)} - dbg_halt_state_f := withClock(io.free_clk){RegNext(dbg_halt_state_ns,0.U)} - val dbg_run_state_f = withClock(io.free_clk){RegNext(dbg_run_state_ns,0.U)} - io.dec_tlu_mpc_halted_only := withClock(io.free_clk){RegNext(dec_tlu_mpc_halted_only_ns,0.U)} + // MPC halt + // - can interact with debugger halt and v-v + // fast ints in progress have priority + val mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & !csr.io.ext_int_freeze_d1 + val mpc_debug_halt_req_sync_f =rvdffie(mpc_debug_halt_req_sync, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(mpc_debug_halt_req_sync,0.U)} + val mpc_debug_run_req_sync_f =rvdffie(mpc_debug_run_req_sync, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(mpc_debug_run_req_sync,0.U)} + mpc_halt_state_f :=rvdffie(mpc_halt_state_ns, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(mpc_halt_state_ns,0.U)} + val mpc_run_state_f =rvdffie(mpc_run_state_ns, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(mpc_run_state_ns,0.U)} + val debug_brkpt_status_f =rvdffie(debug_brkpt_status_ns, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(debug_brkpt_status_ns,0.U)} + val mpc_debug_halt_ack_f =rvdffie(mpc_debug_halt_ack_ns, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(mpc_debug_halt_ack_ns,0.U)} + val mpc_debug_run_ack_f =rvdffie(mpc_debug_run_ack_ns, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(mpc_debug_run_ack_ns,0.U)} + dbg_halt_state_f :=rvdffie(dbg_halt_state_ns, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(dbg_halt_state_ns,0.U)} + val dbg_run_state_f =rvdffie(dbg_run_state_ns, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(dbg_run_state_ns,0.U)} + io.dec_tlu_mpc_halted_only :=rvdffie(dec_tlu_mpc_halted_only_ns, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(dec_tlu_mpc_halted_only_ns,0.U)} - // turn level sensitive requests into pulses + // turn level sensitive requests into pulses val mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & ~mpc_debug_halt_req_sync_f val mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & ~mpc_debug_run_req_sync_f - // states + // states mpc_halt_state_ns := (mpc_halt_state_f | mpc_debug_halt_req_sync_pulse | (reset_delayed & ~io.mpc_reset_run_req)) & ~mpc_debug_run_req_sync mpc_run_state_ns := (mpc_run_state_f | (mpc_debug_run_req_sync_pulse & ~mpc_debug_run_ack_f)) & (internal_dbg_halt_mode_f & ~dcsr_single_step_running_f) - + // note, MPC halt can allow the jtag debugger to just start sending commands. When that happens, set the interal debugger halt state to prevent + // MPC run from starting the core. dbg_halt_state_ns := (dbg_halt_state_f | (dbg_halt_req_final | dcsr_single_step_done_f | trigger_hit_dmode_r_d1 | ebreak_to_debug_mode_r_d1)) & ~io.dbg_resume_req dbg_run_state_ns := (dbg_run_state_f | io.dbg_resume_req) & (internal_dbg_halt_mode_f & ~dcsr_single_step_running_f) - // tell dbg we are only MPC halted + // tell dbg we are only MPC halted dec_tlu_mpc_halted_only_ns := ~dbg_halt_state_f & mpc_halt_state_f - // this asserts from detection of bkpt until after we leave debug mode + // this asserts from detection of bkpt until after we leave debug mode val debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1 debug_brkpt_status_ns := (debug_brkpt_valid | debug_brkpt_status_f) & (internal_dbg_halt_mode & ~dcsr_single_step_running_f) - // acks back to interface + // acks back to interface mpc_debug_halt_ack_ns := mpc_halt_state_f & internal_dbg_halt_mode_f & mpc_debug_halt_req_sync & core_empty mpc_debug_run_ack_ns := (mpc_debug_run_req_sync & ~dbg_halt_state_ns & ~mpc_debug_halt_req_sync) | (mpc_debug_run_ack_f & mpc_debug_run_req_sync) - // Pins + // Pins io.mpc_debug_halt_ack := mpc_debug_halt_ack_f io.mpc_debug_run_ack := mpc_debug_run_ack_f io.debug_brkpt_status := debug_brkpt_status_f - // DBG halt req is a pulse, fast ext int in progress has priority - val dbg_halt_req_held_ns = (io.dbg_halt_req | dbg_halt_req_held) & ext_int_freeze_d1 - dbg_halt_req_final := (io.dbg_halt_req | dbg_halt_req_held) & ~ext_int_freeze_d1 + // DBG halt req is a pulse, fast ext int in progress has priority + val dbg_halt_req_held_ns = (io.dbg_halt_req | dbg_halt_req_held) & csr.io.ext_int_freeze_d1 + dbg_halt_req_final := (io.dbg_halt_req | dbg_halt_req_held) & ~csr.io.ext_int_freeze_d1 - // combine MPC and DBG halt requests - val debug_halt_req = (dbg_halt_req_final | mpc_debug_halt_req_sync | (reset_delayed & ~io.mpc_reset_run_req)) & ~internal_dbg_halt_mode_f & ~ext_int_freeze_d1 + // combine MPC and DBG halt requests + val debug_halt_req = (dbg_halt_req_final | mpc_debug_halt_req_sync | (reset_delayed & ~io.mpc_reset_run_req)) & ~internal_dbg_halt_mode_f & ~csr.io.ext_int_freeze_d1 val debug_resume_req = ~debug_resume_req_f & ((mpc_run_state_ns & ~dbg_halt_state_ns) | (dbg_run_state_ns & ~mpc_halt_state_ns)) - // HALT - // dbg/pmu/fw requests halt, service as soon as lsu is not blocking interrupts + // HALT + // dbg/pmu/fw requests halt, service as soon as lsu is not blocking interrupts val take_halt = (debug_halt_req_f | pmu_fw_halt_req_f) & ~synchronous_flush_r & ~mret_r & ~halt_taken_f & ~dec_tlu_flush_noredir_r_d1 & ~take_reset - // hold after we take a halt, so we don't keep taking halts - val halt_taken = (dec_tlu_flush_noredir_r_d1 & ~dec_tlu_flush_pause_r_d1 & ~take_ext_int_start_d1) | (halt_taken_f & ~dbg_tlu_halted_f & ~pmu_fw_tlu_halted_f & ~interrupt_valid_r_d1) + // hold after we take a halt, so we don't keep taking halts + val halt_taken = (dec_tlu_flush_noredir_r_d1 & !dec_tlu_flush_pause_r_d1 & !csr.io.take_ext_int_start_d1) | (halt_taken_f & !dbg_tlu_halted_f & !pmu_fw_tlu_halted_f & !interrupt_valid_r_d1) - // After doing halt flush (RFNPC) wait until core is idle before asserting a particular halt mode - // It takes a cycle for mb_empty to assert after a fetch, take_halt covers that cycle + // After doing halt flush (RFNPC) wait until core is idle before asserting a particular halt mode + // It takes a cycle for mb_empty to assert after a fetch, take_halt covers that cycle core_empty := force_halt | (io.lsu_idle_any & lsu_idle_any_f & io.tlu_mem.ifu_miss_state_idle & ifu_miss_state_idle_f & ~debug_halt_req & ~debug_halt_req_d1 & ~io.dec_div_active) - -//-------------------------------------------------------------------------------- -// Debug start -// + io.dec_tlu_core_empty := core_empty + //-------------------------------------------------------------------------------- + // Debug start + // val enter_debug_halt_req = (~internal_dbg_halt_mode_f & debug_halt_req) | dcsr_single_step_done_f | trigger_hit_dmode_r_d1 | ebreak_to_debug_mode_r_d1 - // dbg halt state active from request until non-step resume + // dbg halt state active from request until non-step resume internal_dbg_halt_mode := debug_halt_req_ns | (internal_dbg_halt_mode_f & ~(debug_resume_req_f & ~dcsr(DCSR_STEP))) - // dbg halt can access csrs as long as we are not stepping + + // dbg halt can access csrs as long as we are not stepping val allow_dbg_halt_csr_write = internal_dbg_halt_mode_f & ~dcsr_single_step_running_f - // hold debug_halt_req_ns high until we enter debug halt + // hold debug_halt_req_ns high until we enter debug halt val dbg_tlu_halted = (debug_halt_req_f & core_empty & halt_taken) | (dbg_tlu_halted_f & ~debug_resume_req_f) + debug_halt_req_ns := enter_debug_halt_req | (debug_halt_req_f & ~dbg_tlu_halted) val resume_ack_ns = (debug_resume_req_f & dbg_tlu_halted_f & dbg_run_state_ns) @@ -438,2107 +460,2707 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ val dbg_cmd_done_ns = io.dec_tlu_i0_valid_r & io.dec_tlu_dbg_halted - // used to hold off commits after an in-pipe debug mode request (triggers, DCSR) + // used to hold off commits after an in-pipe debug mode request (triggers, DCSR) val request_debug_mode_r = (trigger_hit_dmode_r | ebreak_to_debug_mode_r) | (request_debug_mode_r_d1 & ~io.dec_tlu_flush_lower_wb) val request_debug_mode_done = (request_debug_mode_r_d1 | request_debug_mode_done_f) & ~dbg_tlu_halted_f - - - dec_tlu_flush_noredir_r_d1 := withClock(io.free_clk){RegNext(io.tlu_ifc.dec_tlu_flush_noredir_wb,0.U)} - halt_taken_f := withClock(io.free_clk){RegNext(halt_taken,0.U)} - lsu_idle_any_f := withClock(io.free_clk){RegNext(io.lsu_idle_any,0.U)} - ifu_miss_state_idle_f := withClock(io.free_clk){RegNext(io.tlu_mem.ifu_miss_state_idle,0.U)} - dbg_tlu_halted_f := withClock(io.free_clk){RegNext(dbg_tlu_halted,0.U)} - io.dec_tlu_resume_ack := withClock(io.free_clk){RegNext(resume_ack_ns,0.U)} - debug_halt_req_f := withClock(io.free_clk){RegNext(debug_halt_req_ns,0.U)} - debug_resume_req_f := withClock(io.free_clk){RegNext(debug_resume_req,0.U)} - trigger_hit_dmode_r_d1 := withClock(io.free_clk){RegNext(trigger_hit_dmode_r,0.U)} - dcsr_single_step_done_f := withClock(io.free_clk){RegNext(dcsr_single_step_done,0.U)} - debug_halt_req_d1 := withClock(io.free_clk){RegNext(debug_halt_req,0.U)} - val dec_tlu_wr_pause_r_d1 = withClock(io.free_clk){RegNext(io.dec_tlu_wr_pause_r,0.U)} - val dec_pause_state_f = withClock(io.free_clk){RegNext(io.dec_pause_state,0.U)} - request_debug_mode_r_d1 := withClock(io.free_clk){RegNext(request_debug_mode_r,0.U)} - request_debug_mode_done_f := withClock(io.free_clk){RegNext(request_debug_mode_done,0.U)} - dcsr_single_step_running_f := withClock(io.free_clk){RegNext(dcsr_single_step_running,0.U)} - dec_tlu_flush_pause_r_d1 := withClock(io.free_clk){RegNext(io.dec_tlu_flush_pause_r,0.U)} - dbg_halt_req_held := withClock(io.free_clk){RegNext(dbg_halt_req_held_ns,0.U)} - - + + dec_tlu_flush_noredir_r_d1 :=rvdffie(io.tlu_ifc.dec_tlu_flush_noredir_wb, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(io.tlu_ifc.dec_tlu_flush_noredir_wb,0.U)} + halt_taken_f :=rvdffie(halt_taken, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(halt_taken,0.U)} + lsu_idle_any_f :=rvdffie(io.lsu_idle_any, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(io.lsu_idle_any,0.U)} + ifu_miss_state_idle_f :=rvdffie(io.tlu_mem.ifu_miss_state_idle, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(io.tlu_mem.ifu_miss_state_idle,0.U)} + dbg_tlu_halted_f :=rvdffie(dbg_tlu_halted, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(dbg_tlu_halted,0.U)} + io.dec_tlu_resume_ack :=rvdffie(resume_ack_ns, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(resume_ack_ns,0.U)} + debug_halt_req_f :=rvdffie(debug_halt_req_ns, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(debug_halt_req_ns,0.U)} + debug_resume_req_f_raw :=rvdffie(debug_resume_req, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(debug_resume_req,0.U)} + trigger_hit_dmode_r_d1 :=rvdffie(trigger_hit_dmode_r, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(trigger_hit_dmode_r,0.U)} + dcsr_single_step_done_f :=rvdffie(dcsr_single_step_done, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(dcsr_single_step_done,0.U)} + debug_halt_req_d1 :=rvdffie(debug_halt_req, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(debug_halt_req,0.U)} + val dec_tlu_wr_pause_r_d1 =rvdffie(io.dec_tlu_wr_pause_r, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(io.dec_tlu_wr_pause_r,0.U)} + val dec_pause_state_f =rvdffie(io.dec_pause_state, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(io.dec_pause_state,0.U)} + request_debug_mode_r_d1 :=rvdffie(request_debug_mode_r, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(request_debug_mode_r,0.U)} + request_debug_mode_done_f :=rvdffie(request_debug_mode_done, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(request_debug_mode_done,0.U)} + dcsr_single_step_running_f :=rvdffie(dcsr_single_step_running, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(dcsr_single_step_running,0.U)} + dec_tlu_flush_pause_r_d1 :=rvdffie(io.dec_tlu_flush_pause_r, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(io.dec_tlu_flush_pause_r,0.U)} + dbg_halt_req_held :=rvdffie(dbg_halt_req_held_ns, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(dbg_halt_req_held_ns,0.U)} + + + // MPC run collides with DBG halt, fix it here + debug_resume_req_f := debug_resume_req_f_raw & ~io.dbg_halt_req + io.dec_tlu_debug_stall := debug_halt_req_f io.dec_tlu_dbg_halted := dbg_tlu_halted_f io.dec_tlu_debug_mode := internal_dbg_halt_mode_f dec_tlu_pmu_fw_halted := pmu_fw_tlu_halted_f - // kill fetch redirection on flush if going to halt, or if there's a fence during db-halt + // kill fetch redirection on flush if going to halt, or if there's a fence during db-halt io.tlu_ifc.dec_tlu_flush_noredir_wb := take_halt | (fence_i_r & internal_dbg_halt_mode) | io.dec_tlu_flush_pause_r | (i0_trigger_hit_r & trigger_hit_dmode_r) | take_ext_int_start io.dec_tlu_flush_extint := take_ext_int_start - // 1 cycle after writing the PAUSE counter, flush with noredir to idle F1-D. + // 1 cycle after writing the PAUSE counter, flush with noredir to idle F1-D. io.dec_tlu_flush_pause_r := dec_tlu_wr_pause_r_d1 & ~interrupt_valid_r & ~take_ext_int_start - // detect end of pause counter and rfpc - pause_expired_r := ~io.dec_pause_state & dec_pause_state_f & ~(ext_int_ready | ce_int_ready | timer_int_ready | soft_int_ready | int_timer0_int_hold_f | int_timer1_int_hold_f | nmi_int_detected | ext_int_freeze_d1) & ~interrupt_valid_r_d1 & ~debug_halt_req_f & ~pmu_fw_halt_req_f & ~halt_taken_f + // detect end of pause counter and rfpc + pause_expired_r := ~io.dec_pause_state & dec_pause_state_f & ~(ext_int_ready | ce_int_ready | timer_int_ready | soft_int_ready | int_timer0_int_hold_f | int_timer1_int_hold_f | nmi_int_detected | csr.io.ext_int_freeze_d1) & ~interrupt_valid_r_d1 & ~debug_halt_req_f & ~pmu_fw_halt_req_f & ~halt_taken_f io.tlu_bp.dec_tlu_flush_leak_one_wb := io.tlu_exu.dec_tlu_flush_lower_r & dcsr(DCSR_STEP) & (io.dec_tlu_resume_ack | dcsr_single_step_running) & ~io.tlu_ifc.dec_tlu_flush_noredir_wb - io.tlu_mem.dec_tlu_flush_err_wb := io.tlu_exu.dec_tlu_flush_lower_r & (ic_perr_r_d1 | iccm_sbecc_r_d1) + io.tlu_mem.dec_tlu_flush_err_wb := io.tlu_exu.dec_tlu_flush_lower_r & (ic_perr_r | iccm_sbecc_r) - // If DM attempts to access an illegal CSR, send cmd_fail back + // If DM attempts to access an illegal CSR, send cmd_fail back io.dec_dbg_cmd_done := dbg_cmd_done_ns io.dec_dbg_cmd_fail := illegal_r & io.dec_dbg_cmd_done - //-------------------------------------------------------------------------------- - //-------------------------------------------------------------------------------- - // Triggers - // + //-------------------------------------------------------------------------------- + //-------------------------------------------------------------------------------- + // Triggers + // - // Prioritize trigger hits with other exceptions. - // - // Trigger should have highest priority except: - // - trigger is an execute-data and there is an inst_access exception (lsu triggers won't fire, inst. is nop'd by decode) - // - trigger is a store-data and there is a lsu_acc_exc or lsu_ma_exc. + // Prioritize trigger hits with other exceptions. + // + // Trigger should have highest priority except: + // - trigger is an execute-data and there is an inst_access exception (lsu triggers won't fire, inst. is nop'd by decode) + // - trigger is a store-data and there is a lsu_acc_exc or lsu_ma_exc. val trigger_execute = Cat(mtdata1_t(3)(MTDATA1_EXE), mtdata1_t(2)(MTDATA1_EXE), mtdata1_t(1)(MTDATA1_EXE), mtdata1_t(0)(MTDATA1_EXE)) val trigger_data = Cat(mtdata1_t(3)(MTDATA1_SEL), mtdata1_t(2)(MTDATA1_SEL), mtdata1_t(1)(MTDATA1_SEL), mtdata1_t(0)(MTDATA1_SEL)) val trigger_store = Cat(mtdata1_t(3)(MTDATA1_ST), mtdata1_t(2)(MTDATA1_ST), mtdata1_t(1)(MTDATA1_ST), mtdata1_t(0)(MTDATA1_ST)) - // MSTATUS[MIE] needs to be on to take triggers unless the action is trigger to debug mode. - val trigger_enabled = Cat((mtdata1_t(3)(MTDATA1_ACTION) | mstatus(MSTATUS_MIE)) & mtdata1_t(3)(MTDATA1_M_ENABLED),(mtdata1_t(2)(MTDATA1_ACTION) | mstatus(MSTATUS_MIE)) & mtdata1_t(2)(MTDATA1_M_ENABLED), (mtdata1_t(1)(MTDATA1_ACTION) | mstatus(MSTATUS_MIE)) & mtdata1_t(1)(MTDATA1_M_ENABLED), (mtdata1_t(0)(MTDATA1_ACTION) | mstatus(MSTATUS_MIE)) & mtdata1_t(0)(MTDATA1_M_ENABLED)) + // MSTATUS[MIE] needs to be on to take triggers unless the action is trigger to debug mode. + val trigger_enabled = Cat((mtdata1_t(3)(MTDATA1_ACTION) | mstatus(MSTATUS_MIE)) & mtdata1_t(3)(MTDATA1_M_ENABLED), + (mtdata1_t(2)(MTDATA1_ACTION) | mstatus(MSTATUS_MIE)) & mtdata1_t(2)(MTDATA1_M_ENABLED), + (mtdata1_t(1)(MTDATA1_ACTION) | mstatus(MSTATUS_MIE)) & mtdata1_t(1)(MTDATA1_M_ENABLED), + (mtdata1_t(0)(MTDATA1_ACTION) | mstatus(MSTATUS_MIE)) & mtdata1_t(0)(MTDATA1_M_ENABLED)) - // iside exceptions are always in i0 - val i0_iside_trigger_has_pri_r = ~((trigger_execute & trigger_data & Fill(4,inst_acc_r_raw)) | (Fill(4,io.tlu_exu.exu_i0_br_error_r | io.tlu_exu.exu_i0_br_start_error_r))) + // iside exceptions are always in i0 + val i0_iside_trigger_has_pri_r = ~((trigger_execute & trigger_data & Fill(4,inst_acc_r_raw)) | (Fill(4,io.tlu_exu.exu_i0_br_error_r | io.tlu_exu.exu_i0_br_start_error_r))) - // lsu excs have to line up with their respective triggers since the lsu op can be i0 - val i0_lsu_trigger_has_pri_r = ~(trigger_store & trigger_data & Fill(4,lsu_i0_exc_r_raw)) + // lsu excs have to line up with their respective triggers since the lsu op can be i0 + val i0_lsu_trigger_has_pri_r = ~(trigger_store & trigger_data & Fill(4,lsu_i0_exc_r_raw)) - // trigger hits have to be eval'd to cancel side effect lsu ops even though the pipe is already frozen - val i0_trigger_eval_r = io.dec_tlu_i0_valid_r + // trigger hits have to be eval'd to cancel side effect lsu ops even though the pipe is already frozen + val i0_trigger_eval_r = io.dec_tlu_i0_valid_r - val i0trigger_qual_r = Fill(4,i0_trigger_eval_r) & io.dec_tlu_packet_r.i0trigger(3,0) & i0_iside_trigger_has_pri_r & i0_lsu_trigger_has_pri_r & trigger_enabled - // Qual trigger hits - val i0_trigger_r = ~(Fill(4,io.dec_tlu_flush_lower_wb | io.dec_tlu_dbg_halted)) & i0trigger_qual_r + val i0trigger_qual_r = Fill(4,i0_trigger_eval_r) & io.dec_tlu_packet_r.i0trigger(3,0) & i0_iside_trigger_has_pri_r & i0_lsu_trigger_has_pri_r & trigger_enabled + // Qual trigger hits + val i0_trigger_r = (~(Fill(4,io.dec_tlu_flush_lower_wb | io.dec_tlu_dbg_halted)) & i0trigger_qual_r) - // chaining can mask raw trigger info - val i0_trigger_chain_masked_r = Cat(i0_trigger_r(3) & (~mtdata1_t(2)(MTDATA1_CHAIN) | i0_trigger_r(2)), i0_trigger_r(2) & (~mtdata1_t(2)(MTDATA1_CHAIN) | i0_trigger_r(3)), i0_trigger_r(1) & (~mtdata1_t(0)(MTDATA1_CHAIN) | i0_trigger_r(0)), i0_trigger_r(0) & (~mtdata1_t(0)(MTDATA1_CHAIN) | i0_trigger_r(1))) - - // This is the highest priority by this point. - val i0_trigger_hit_raw_r = i0_trigger_chain_masked_r.orR - - i0_trigger_hit_r := i0_trigger_hit_raw_r - - // Actions include breakpoint, or dmode. Dmode is only possible if the DMODE bit is set. - // Otherwise, take a breakpoint. - val trigger_action = Cat(mtdata1_t(3)(MTDATA1_ACTION) & mtdata1_t(3)(MTDATA1_DMODE), mtdata1_t(2)(MTDATA1_ACTION) & mtdata1_t(2)(MTDATA1_DMODE), mtdata1_t(1)(MTDATA1_ACTION) & mtdata1_t(1)(MTDATA1_DMODE), mtdata1_t(0)(MTDATA1_ACTION) & mtdata1_t(0)(MTDATA1_DMODE)) - - // this is needed to set the HIT bit in the triggers - val update_hit_bit_r = (Fill(4,i0_trigger_hit_r) & i0_trigger_chain_masked_r) - - // action, 1 means dmode. Simultaneous triggers with at least 1 set for dmode force entire action to dmode. - val i0_trigger_action_r = (i0_trigger_chain_masked_r & trigger_action).orR - - trigger_hit_dmode_r := (i0_trigger_hit_r & i0_trigger_action_r) - - val mepc_trigger_hit_sel_pc_r = i0_trigger_hit_r & ~trigger_hit_dmode_r - -// -// Debug end + // chaining can mask raw trigger info + val i0_trigger_chain_masked_r = Cat(i0_trigger_r(3) & (~mtdata1_t(2)(MTDATA1_CHAIN) | i0_trigger_r(2)), + i0_trigger_r(2) & (~mtdata1_t(2)(MTDATA1_CHAIN) | i0_trigger_r(3)), + i0_trigger_r(1) & (~mtdata1_t(0)(MTDATA1_CHAIN) | i0_trigger_r(0)), + i0_trigger_r(0) & (~mtdata1_t(0)(MTDATA1_CHAIN) | i0_trigger_r(1))) - //---------------------------------------------------------------------- - // - // Commit - // - //---------------------------------------------------------------------- + // This is the highest priority by this point. + val i0_trigger_hit_raw_r = i0_trigger_chain_masked_r.orR + + i0_trigger_hit_r := i0_trigger_hit_raw_r + + // Actions include breakpoint, or dmode. Dmode is only possible if the DMODE bit is set. + // Otherwise, take a breakpoint. + val trigger_action = Cat(mtdata1_t(3)(MTDATA1_ACTION) & mtdata1_t(3)(MTDATA1_DMODE), + mtdata1_t(2)(MTDATA1_ACTION) & mtdata1_t(2)(MTDATA1_DMODE) & ~mtdata1_t(2)(MTDATA1_CHAIN), + mtdata1_t(1)(MTDATA1_ACTION) & mtdata1_t(1)(MTDATA1_DMODE), + mtdata1_t(0)(MTDATA1_ACTION) & mtdata1_t(0)(MTDATA1_DMODE) & ~mtdata1_t(0)(MTDATA1_CHAIN)) + + // this is needed to set the HIT bit in the triggers + val update_hit_bit_r = (Fill(4,i0_trigger_r.orR & ~rfpc_i0_r) & Cat(i0_trigger_chain_masked_r(3), i0_trigger_r(2), i0_trigger_chain_masked_r(1), i0_trigger_r(0))) + + // action, 1 means dmode. Simultaneous triggers with at least 1 set for dmode force entire action to dmode. + val i0_trigger_action_r = (i0_trigger_chain_masked_r & trigger_action).orR + + trigger_hit_dmode_r := (i0_trigger_hit_r & i0_trigger_action_r) + + val mepc_trigger_hit_sel_pc_r = i0_trigger_hit_r & ~trigger_hit_dmode_r + + // + // Debug end + + + //---------------------------------------------------------------------- + // + // Commit + // + //---------------------------------------------------------------------- - //-------------------------------------------------------------------------------- - // External halt (not debug halt) - // - Fully interlocked handshake - // i_cpu_halt_req ____|--------------|_______________ - // core_empty ---------------|___________ - // o_cpu_halt_ack _________________|----|__________ - // o_cpu_halt_status _______________|---------------------|_________ - // i_cpu_run_req ______|----------|____ - // o_cpu_run_ack ____________|------|________ - - // debug mode has priority, ignore PMU/FW halt/run while in debug mode - val i_cpu_halt_req_sync_qual = i_cpu_halt_req_sync & ~io.dec_tlu_debug_mode & ~ext_int_freeze_d1 - val i_cpu_run_req_sync_qual = i_cpu_run_req_sync & ~io.dec_tlu_debug_mode & pmu_fw_tlu_halted_f & ~ext_int_freeze_d1 - - val i_cpu_halt_req_d1 = withClock(io.free_clk){RegNext(i_cpu_halt_req_sync_qual,0.U)} - val i_cpu_run_req_d1_raw = withClock(io.free_clk){RegNext(i_cpu_run_req_sync_qual,0.U)} - io.o_cpu_halt_status := withClock(io.free_clk){RegNext(cpu_halt_status,0.U)} - io.o_cpu_halt_ack := withClock(io.free_clk){RegNext(cpu_halt_ack,0.U)} - io.o_cpu_run_ack := withClock(io.free_clk){RegNext(cpu_run_ack,0.U)} - val internal_pmu_fw_halt_mode_f = withClock(io.free_clk){RegNext(internal_pmu_fw_halt_mode,0.U)} - pmu_fw_halt_req_f := withClock(io.free_clk){RegNext(pmu_fw_halt_req_ns,0.U)} - pmu_fw_tlu_halted_f := withClock(io.free_clk){RegNext(pmu_fw_tlu_halted,0.U)} - int_timer0_int_hold_f := withClock(io.free_clk){RegNext(int_timer0_int_hold,0.U)} - int_timer1_int_hold_f := withClock(io.free_clk){RegNext(int_timer1_int_hold,0.U)} - - - // only happens if we aren't in dgb_halt - val ext_halt_pulse = i_cpu_halt_req_sync_qual & ~i_cpu_halt_req_d1 - val enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req - pmu_fw_halt_req_ns := (enter_pmu_fw_halt_req | (pmu_fw_halt_req_f & ~pmu_fw_tlu_halted)) & ~debug_halt_req_f - internal_pmu_fw_halt_mode := pmu_fw_halt_req_ns | (internal_pmu_fw_halt_mode_f & ~i_cpu_run_req_d1 & ~debug_halt_req_f) - - // debug halt has priority - pmu_fw_tlu_halted := ((pmu_fw_halt_req_f & core_empty & halt_taken & ~enter_debug_halt_req) | (pmu_fw_tlu_halted_f & ~i_cpu_run_req_d1)) & ~debug_halt_req_f - - cpu_halt_ack := i_cpu_halt_req_d1 & pmu_fw_tlu_halted_f - cpu_halt_status := (pmu_fw_tlu_halted_f & ~i_cpu_run_req_d1) | (io.o_cpu_halt_status & ~i_cpu_run_req_d1 & ~internal_dbg_halt_mode_f) - cpu_run_ack := (io.o_cpu_halt_status & i_cpu_run_req_sync_qual) | (io.o_cpu_run_ack & i_cpu_run_req_sync_qual) - val debug_mode_status = internal_dbg_halt_mode_f - io.o_debug_mode_status := debug_mode_status - - // high priority interrupts can wakeup from external halt, so can unmasked timer interrupts - i_cpu_run_req_d1 := i_cpu_run_req_d1_raw | ((nmi_int_detected | timer_int_ready | soft_int_ready | int_timer0_int_hold_f | int_timer1_int_hold_f | (io.dec_pic.mhwakeup & mhwakeup_ready)) & io.o_cpu_halt_status & ~i_cpu_halt_req_d1) - - //-------------------------------------------------------------------------------- - //-------------------------------------------------------------------------------- - - val lsu_single_ecc_error_r =io.lsu_single_ecc_error_incr - mdseac_locked_f :=withClock(io.free_clk){RegNext(mdseac_locked_ns,0.U)} - val lsu_single_ecc_error_r_d1 =withClock(io.free_clk){RegNext(lsu_single_ecc_error_r,0.U)} - val lsu_error_pkt_addr_r =io.lsu_error_pkt_r.bits.addr - val lsu_exc_valid_r_raw = io.lsu_error_pkt_r.valid & ~io.dec_tlu_flush_lower_wb - lsu_i0_exc_r_raw := io.lsu_error_pkt_r.valid - val lsu_i0_exc_r = lsu_i0_exc_r_raw & lsu_exc_valid_r_raw & ~i0_trigger_hit_r & ~rfpc_i0_r - val lsu_exc_valid_r = lsu_i0_exc_r - lsu_exc_valid_r_d1 :=withClock(lsu_r_wb_clk){RegNext(lsu_exc_valid_r,0.U)} - val lsu_i0_exc_r_d1 =withClock(lsu_r_wb_clk){RegNext(lsu_i0_exc_r,0.U)} - val lsu_exc_ma_r = lsu_i0_exc_r & ~io.lsu_error_pkt_r.bits.exc_type - val lsu_exc_acc_r = lsu_i0_exc_r & io.lsu_error_pkt_r.bits.exc_type - val lsu_exc_st_r = lsu_i0_exc_r & io.lsu_error_pkt_r.bits.inst_type - - // Single bit ECC errors on loads are RFNPC corrected, with the corrected data written to the GPR. - // LSU turns the load into a store and patches the data in the DCCM - val lsu_i0_rfnpc_r = io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & (~io.lsu_error_pkt_r.bits.inst_type & io.lsu_error_pkt_r.bits.single_ecc_error) - - // Final commit valids - val tlu_i0_commit_cmt = io.dec_tlu_i0_valid_r & ~rfpc_i0_r & ~lsu_i0_exc_r & ~inst_acc_r & ~io.dec_tlu_dbg_halted & ~request_debug_mode_r_d1 & ~i0_trigger_hit_r - - // unified place to manage the killing of arch state writebacks - tlu_i0_kill_writeb_r := rfpc_i0_r | lsu_i0_exc_r | inst_acc_r | (illegal_r & io.dec_tlu_dbg_halted) | i0_trigger_hit_r - io.tlu_mem.dec_tlu_i0_commit_cmt := tlu_i0_commit_cmt + //-------------------------------------------------------------------------------- + // External halt (not debug halt) + // - Fully interlocked handshake + // i_cpu_halt_req ____|--------------|_______________ + // core_empty ---------------|___________ + // o_cpu_halt_ack _________________|----|__________ + // o_cpu_halt_status _______________|---------------------|_________ + // i_cpu_run_req ______|----------|____ + // o_cpu_run_ack ____________|------|________ + // - // refetch PC, microarch flush - // ic errors only in pipe0 - rfpc_i0_r := ((io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (io.tlu_exu.exu_i0_br_error_r | io.tlu_exu.exu_i0_br_start_error_r)) | ((ic_perr_r_d1 | iccm_sbecc_r_d1) & ~ext_int_freeze_d1)) & ~i0_trigger_hit_r & ~lsu_i0_rfnpc_r + // debug mode has priority, ignore PMU/FW halt/run while in debug mode + val i_cpu_halt_req_sync_qual = i_cpu_halt_req_sync & ~io.dec_tlu_debug_mode & ~csr.io.ext_int_freeze_d1 + val i_cpu_run_req_sync_qual = i_cpu_run_req_sync & ~io.dec_tlu_debug_mode & pmu_fw_tlu_halted_f & ~csr.io.ext_int_freeze_d1 - // From the indication of a iccm single bit error until the first commit or flush, maintain a repair state. In the repair state, rfnpc i0 commits. - iccm_repair_state_ns := iccm_sbecc_r_d1 | (iccm_repair_state_d1 & ~io.tlu_exu.dec_tlu_flush_lower_r) + val i_cpu_halt_req_d1 =rvdffie(i_cpu_halt_req_sync_qual, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(i_cpu_halt_req_sync_qual,0.U)} + val i_cpu_run_req_d1_raw =rvdffie(i_cpu_run_req_sync_qual, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(,0.U)} + io.o_cpu_halt_status :=rvdffie(cpu_halt_status, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(cpu_halt_status,0.U)} + io.o_cpu_halt_ack :=rvdffie(cpu_halt_ack, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(cpu_halt_ack,0.U)} + io.o_cpu_run_ack :=rvdffie(cpu_run_ack, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(cpu_run_ack,0.U)} + val internal_pmu_fw_halt_mode_f =rvdffie(internal_pmu_fw_halt_mode, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(internal_pmu_fw_halt_mode,0.U)} + pmu_fw_halt_req_f :=rvdffie(pmu_fw_halt_req_ns, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(pmu_fw_halt_req_ns,0.U)} + pmu_fw_tlu_halted_f :=rvdffie(pmu_fw_tlu_halted, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(pmu_fw_tlu_halted,0.U)} + int_timer0_int_hold_f :=rvdffie(int_timer0_int_hold, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(int_timer0_int_hold,0.U)} + int_timer1_int_hold_f :=rvdffie(int_timer1_int_hold, io.free_l2clk,reset.asAsyncReset(),io.scan_mode)//withClock(io.free_clk){RegNext(int_timer1_int_hold,0.U)} - val MCPC =0x7c2.U(12.W) + // only happens if we aren't in dgb_halt + val ext_halt_pulse = i_cpu_halt_req_sync_qual & ~i_cpu_halt_req_d1 + val enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req + pmu_fw_halt_req_ns := (enter_pmu_fw_halt_req | (pmu_fw_halt_req_f & ~pmu_fw_tlu_halted)) & ~debug_halt_req_f + internal_pmu_fw_halt_mode := pmu_fw_halt_req_ns | (internal_pmu_fw_halt_mode_f & ~i_cpu_run_req_d1 & ~debug_halt_req_f) - // this is a flush of last resort, meaning only assert it if there is no other flush happening. - val iccm_repair_state_rfnpc = tlu_i0_commit_cmt & iccm_repair_state_d1 & ~(ebreak_r | ecall_r | mret_r | take_reset | illegal_r | (dec_csr_wen_r_mod & (io.dec_csr_wraddr_r ===MCPC))) + // debug halt has priority + pmu_fw_tlu_halted := ((pmu_fw_halt_req_f & core_empty & halt_taken & ~enter_debug_halt_req) | (pmu_fw_tlu_halted_f & ~i_cpu_run_req_d1)) & ~debug_halt_req_f - // go ahead and repair the branch error on other flushes, doesn't have to be the rfpc flush - val dec_tlu_br0_error_r = io.tlu_exu.exu_i0_br_error_r & io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 - val dec_tlu_br0_start_error_r = io.tlu_exu.exu_i0_br_start_error_r & io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 - val dec_tlu_br0_v_r = io.tlu_exu.exu_i0_br_valid_r & io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (~io.tlu_exu.exu_i0_br_mp_r | ~io.tlu_exu.exu_pmu_i0_br_ataken) + cpu_halt_ack := (i_cpu_halt_req_d1 & pmu_fw_tlu_halted_f) | (io.o_cpu_halt_ack & i_cpu_halt_req_sync) + cpu_halt_status := (pmu_fw_tlu_halted_f & ~i_cpu_run_req_d1) | (io.o_cpu_halt_status & ~i_cpu_run_req_d1 & ~internal_dbg_halt_mode_f) + cpu_run_ack := (~pmu_fw_tlu_halted_f & i_cpu_run_req_sync) | (io.o_cpu_halt_status & i_cpu_run_req_d1_raw) | (io.o_cpu_run_ack & i_cpu_run_req_sync) + + val debug_mode_status = internal_dbg_halt_mode_f + io.o_debug_mode_status := debug_mode_status + + // high priority interrupts can wakeup from external halt, so can unmasked timer interrupts + i_cpu_run_req_d1 := i_cpu_run_req_d1_raw | ((nmi_int_detected | timer_int_ready | soft_int_ready | int_timer0_int_hold_f | int_timer1_int_hold_f | (io.dec_pic.mhwakeup & mhwakeup_ready)) & io.o_cpu_halt_status & ~i_cpu_halt_req_d1) + + //-------------------------------------------------------------------------------- + //-------------------------------------------------------------------------------- + + val lsu_single_ecc_error_r =io.lsu_single_ecc_error_incr + // mdseac_locked_f :=withClock(io.free_clk){RegNext(mdseac_locked_ns,0.U)} + // val lsu_single_ecc_error_r_d1 =withClock(io.free_clk){RegNext(lsu_single_ecc_error_r,0.U)} + val lsu_error_pkt_addr_r =io.lsu_error_pkt_r.bits.addr + val lsu_exc_valid_r_raw = io.lsu_error_pkt_r.valid & ~io.dec_tlu_flush_lower_wb + lsu_i0_exc_r_raw := io.lsu_error_pkt_r.valid + val lsu_i0_exc_r = lsu_i0_exc_r_raw & lsu_exc_valid_r_raw & ~i0_trigger_hit_r & ~rfpc_i0_r + val lsu_exc_valid_r = lsu_i0_exc_r + // lsu_exc_valid_r_d1 :=withClock(lsu_r_wb_clk){RegNext(lsu_exc_valid_r,0.U)} + // val lsu_i0_exc_r_d1 =withClock(lsu_r_wb_clk){RegNext(lsu_i0_exc_r,0.U)} + + // Single bit ECC errors on loads are RFNPC corrected, with the corrected data written to the GPR. + // LSU turns the load into a store and patches the data in the DCCM + val lsu_i0_rfnpc_r = io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & (~io.lsu_error_pkt_r.bits.inst_type & io.lsu_error_pkt_r.bits.single_ecc_error) + + // Final commit valids + val tlu_i0_commit_cmt = io.dec_tlu_i0_valid_r & ~rfpc_i0_r & ~lsu_i0_exc_r & ~inst_acc_r & ~io.dec_tlu_dbg_halted & ~request_debug_mode_r_d1 & ~i0_trigger_hit_r + + // unified place to manage the killing of arch state writebacks + tlu_i0_kill_writeb_r := rfpc_i0_r | lsu_i0_exc_r | inst_acc_r | (illegal_r & io.dec_tlu_dbg_halted) | i0_trigger_hit_r + io.tlu_mem.dec_tlu_i0_commit_cmt := tlu_i0_commit_cmt - io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist := io.tlu_exu.exu_i0_br_hist_r - io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error := dec_tlu_br0_error_r - io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error := dec_tlu_br0_start_error_r - io.tlu_bp.dec_tlu_br0_r_pkt.valid := dec_tlu_br0_v_r - io.tlu_bp.dec_tlu_br0_r_pkt.bits.way := io.exu_i0_br_way_r - io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle := io.tlu_exu.exu_i0_br_middle_r + // refetch PC, microarch flush + // ic errors only in pipe0 + rfpc_i0_r := ((io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (io.tlu_exu.exu_i0_br_error_r | io.tlu_exu.exu_i0_br_start_error_r)) | ((ic_perr_r | iccm_sbecc_r) & ~csr.io.ext_int_freeze_d1)) & ~i0_trigger_hit_r & ~lsu_i0_rfnpc_r + + // From the indication of a iccm single bit error until the first commit or flush, maintain a repair state. In the repair state, rfnpc i0 commits. + iccm_repair_state_ns := iccm_sbecc_r | (iccm_repair_state_d1 & ~io.tlu_exu.dec_tlu_flush_lower_r) - ebreak_r := (io.dec_tlu_packet_r.pmu_i0_itype === EBREAK) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~dcsr(DCSR_EBREAKM) & ~rfpc_i0_r - ecall_r := (io.dec_tlu_packet_r.pmu_i0_itype === ECALL) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r - illegal_r := ~io.dec_tlu_packet_r.legal & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r - mret_r := (io.dec_tlu_packet_r.pmu_i0_itype === MRET) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r - // fence_i includes debug only fence_i's - fence_i_r := (io.dec_tlu_packet_r.fence_i & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r) & ~rfpc_i0_r - ic_perr_r := io.tlu_mem.ifu_ic_error_start & ~ext_int_freeze_d1 & (~internal_dbg_halt_mode_f | dcsr_single_step_running) & ~internal_pmu_fw_halt_mode_f - iccm_sbecc_r := io.tlu_mem.ifu_iccm_rd_ecc_single_err & ~ext_int_freeze_d1 & (~internal_dbg_halt_mode_f | dcsr_single_step_running) & ~internal_pmu_fw_halt_mode_f - inst_acc_r_raw := io.dec_tlu_packet_r.icaf & io.dec_tlu_i0_valid_r - inst_acc_r := inst_acc_r_raw & ~rfpc_i0_r & ~i0_trigger_hit_r - val inst_acc_second_r = io.dec_tlu_packet_r.icaf_f1 + val MCPC =0x7c2.U(12.W) - ebreak_to_debug_mode_r := (io.dec_tlu_packet_r.pmu_i0_itype === EBREAK) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & dcsr(DCSR_EBREAKM) & ~rfpc_i0_r + // this is a flush of last resort, meaning only assert it if there is no other flush happening. + val iccm_repair_state_rfnpc = tlu_i0_commit_cmt & iccm_repair_state_d1 & ~(ebreak_r | ecall_r | mret_r | take_reset | illegal_r | (dec_csr_wen_r_mod & (io.dec_csr_wraddr_r ===MCPC))) - ebreak_to_debug_mode_r_d1:= withClock(e4e5_clk){RegNext(ebreak_to_debug_mode_r,0.U)} - io.tlu_mem.dec_tlu_fence_i_wb := fence_i_r - - // - // Exceptions - // - // - MEPC <- PC - // - PC <- MTVEC, assert flush_lower - // - MCAUSE <- cause - // - MSCAUSE <- secondary cause - // - MTVAL <- - // - MPIE <- MIE - // - MIE <- 0 - // - val i0_exception_valid_r = (ebreak_r | ecall_r | illegal_r | inst_acc_r) & ~rfpc_i0_r & ~io.dec_tlu_dbg_halted - - // Cause: - // - // 0x2 : illegal - // 0x3 : breakpoint - // 0xb : Environment call M-mode - - val exc_cause_r = Mux1H(Seq( - (take_ext_int & ~take_nmi).asBool -> 0x0b.U(5.W), - (take_timer_int & ~take_nmi).asBool -> 0x07.U(5.W), - (take_soft_int & ~take_nmi).asBool -> 0x03.U(5.W), - (take_int_timer0_int & ~take_nmi).asBool -> 0x1d.U(5.W), - (take_int_timer1_int & ~take_nmi).asBool -> 0x1c.U(5.W), - (take_ce_int & ~take_nmi).asBool -> 0x1e.U(5.W), - (illegal_r & ~take_nmi).asBool -> 0x02.U(5.W), - (ecall_r & ~take_nmi).asBool -> 0x0b.U(5.W), - (inst_acc_r & ~take_nmi).asBool -> 0x01.U(5.W), - ((ebreak_r | i0_trigger_hit_r) & ~take_nmi).asBool -> 0x03.U(5.W), - (lsu_exc_ma_r & ~lsu_exc_st_r & ~take_nmi).asBool -> 0x04.U(5.W), - (lsu_exc_acc_r & ~lsu_exc_st_r & ~take_nmi).asBool -> 0x05.U(5.W), - (lsu_exc_ma_r & lsu_exc_st_r & ~take_nmi).asBool -> 0x06.U(5.W), - (lsu_exc_acc_r & lsu_exc_st_r & ~take_nmi).asBool -> 0x07.U(5.W) - )) - // - // Interrupts - // - // exceptions that are committed have already happened and will cause an int at E4 to wait a cycle - // or more if MSTATUS[MIE] is cleared. - // - // -in priority order, highest to lowest - // -single cycle window where a csr write to MIE/MSTATUS is at E4 when the other conditions for externals are met. - // Hold off externals for a cycle to make sure we are consistent with what was just written - mhwakeup_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MEIP) & mie_ns(MIE_MEIE) - ext_int_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MEIP) & mie_ns(MIE_MEIE) & ~ignore_ext_int_due_to_lsu_stall - ce_int_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MCEIP) & mie_ns(MIE_MCEIE) - soft_int_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MSIP) & mie_ns(MIE_MSIE) - timer_int_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MTIP) & mie_ns(MIE_MTIE) - - // MIP for internal timers pulses for 1 clock, resets the timer counter. Mip won't hold past the various stall conditions. - val int_timer0_int_possible = mstatus_mie_ns & mie_ns(MIE_MITIE0) - val int_timer0_int_ready = mip(MIP_MITIP0) & int_timer0_int_possible - val int_timer1_int_possible = mstatus_mie_ns & mie_ns(MIE_MITIE1) - val int_timer1_int_ready = mip(MIP_MITIP1) & int_timer1_int_possible - - // Internal timers pulse and reset. If core is PMU/FW halted, the pulse will cause an exit from halt, but won't stick around - // Make it sticky, also for 1 cycle stall conditions. - val int_timer_stalled = io.dec_csr_stall_int_ff | synchronous_flush_r | exc_or_int_valid_r_d1 | mret_r - - int_timer0_int_hold := (int_timer0_int_ready & (pmu_fw_tlu_halted_f | int_timer_stalled)) | (int_timer0_int_possible & int_timer0_int_hold_f & ~interrupt_valid_r & ~take_ext_int_start & ~internal_dbg_halt_mode_f) - int_timer1_int_hold := (int_timer1_int_ready & (pmu_fw_tlu_halted_f | int_timer_stalled)) | (int_timer1_int_possible & int_timer1_int_hold_f & ~interrupt_valid_r & ~take_ext_int_start & ~internal_dbg_halt_mode_f) - - internal_dbg_halt_timers := internal_dbg_halt_mode_f & ~dcsr_single_step_running; - - val block_interrupts = ((internal_dbg_halt_mode & (~dcsr_single_step_running | io.dec_tlu_i0_valid_r)) | internal_pmu_fw_halt_mode | i_cpu_halt_req_d1 | take_nmi | ebreak_to_debug_mode_r | synchronous_flush_r | exc_or_int_valid_r_d1 | mret_r | ext_int_freeze_d1) + val dec_tlu_br0_error_r = WireInit(Bool(),0.B) + val dec_tlu_br0_start_error_r = WireInit(Bool(),0.B) + val dec_tlu_br0_v_r = WireInit(Bool(),0.B) + if(BTB_ENABLE){ + // go ahead and repair the branch error on other flushes, doesn't have to be the rfpc flush + dec_tlu_br0_error_r := io.tlu_exu.exu_i0_br_error_r & io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 + dec_tlu_br0_start_error_r := io.tlu_exu.exu_i0_br_start_error_r & io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 + dec_tlu_br0_v_r := io.tlu_exu.exu_i0_br_valid_r & io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (~io.tlu_exu.exu_i0_br_mp_r | ~io.tlu_exu.exu_pmu_i0_br_ataken) - if(FAST_INTERRUPT_REDIRECT) { - take_ext_int_start_d1 := withClock(io.free_clk){RegNext(take_ext_int_start,0.U)} - take_ext_int_start_d2 := withClock(io.free_clk){RegNext(take_ext_int_start_d1,0.U)} - take_ext_int_start_d3 := withClock(io.free_clk){RegNext(take_ext_int_start_d2,0.U)} - ext_int_freeze_d1 := withClock(io.free_clk){RegNext(ext_int_freeze,0.U)} - take_ext_int_start := ext_int_ready & ~block_interrupts; + io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist := io.tlu_exu.exu_i0_br_hist_r + io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error := dec_tlu_br0_error_r + io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error := dec_tlu_br0_start_error_r + io.tlu_bp.dec_tlu_br0_r_pkt.valid := dec_tlu_br0_v_r + io.tlu_bp.dec_tlu_br0_r_pkt.bits.way := io.exu_i0_br_way_r + io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle := io.tlu_exu.exu_i0_br_middle_r - ext_int_freeze := take_ext_int_start | take_ext_int_start_d1 | take_ext_int_start_d2 | take_ext_int_start_d3 - take_ext_int := take_ext_int_start_d3 & ~io.lsu_fir_error.orR - fast_int_meicpct := csr_pkt.csr_meicpct & io.dec_csr_any_unq_d // MEICPCT becomes illegal if fast ints are enabled - ignore_ext_int_due_to_lsu_stall := io.lsu_fastint_stall_any - }else{ - take_ext_int_start := 0.U(1.W) - ext_int_freeze := 0.U(1.W) - ext_int_freeze_d1 := 0.U(1.W) - take_ext_int_start_d1 := 0.U(1.W) - take_ext_int_start_d2 := 0.U(1.W) - take_ext_int_start_d3 := 0.U(1.W) - fast_int_meicpct := 0.U(1.W) - ignore_ext_int_due_to_lsu_stall := 0.U(1.W) - take_ext_int := ext_int_ready & ~block_interrupts + } + // if (pt.BTB_ENABLE==1) + else { + dec_tlu_br0_error_r := 0.U + dec_tlu_br0_start_error_r := 0.U + dec_tlu_br0_v_r := 0.U + io.tlu_bp.dec_tlu_br0_r_pkt := 0.U.asTypeOf(io.tlu_bp.dec_tlu_br0_r_pkt) + // else: !if(pt.BTB_ENABLE==1) } - take_ce_int := ce_int_ready & ~ext_int_ready & ~block_interrupts - take_soft_int := soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts - take_timer_int := timer_int_ready & ~soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts - take_int_timer0_int := (int_timer0_int_ready | int_timer0_int_hold_f) & int_timer0_int_possible & ~io.dec_csr_stall_int_ff & ~timer_int_ready & ~soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts - take_int_timer1_int := (int_timer1_int_ready | int_timer1_int_hold_f) & int_timer1_int_possible & ~io.dec_csr_stall_int_ff & ~(int_timer0_int_ready | int_timer0_int_hold_f) & ~timer_int_ready & ~soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts - take_reset := reset_delayed & io.mpc_reset_run_req - take_nmi := nmi_int_detected & ~internal_pmu_fw_halt_mode & (~internal_dbg_halt_mode | (dcsr_single_step_running_f & dcsr(DCSR_STEPIE) & ~io.dec_tlu_i0_valid_r & ~dcsr_single_step_done_f)) & ~synchronous_flush_r & ~mret_r & ~take_reset & ~ebreak_to_debug_mode_r & (~ext_int_freeze_d1 | (take_ext_int_start_d3 & io.lsu_fir_error.orR)) - - interrupt_valid_r := take_ext_int | take_timer_int | take_soft_int | take_nmi | take_ce_int | take_int_timer0_int | take_int_timer1_int + // only expect these in pipe 0 + ebreak_r := (io.dec_tlu_packet_r.pmu_i0_itype === EBREAK) & io.dec_tlu_i0_valid_r & !i0_trigger_hit_r & ~dcsr(DCSR_EBREAKM) & ~rfpc_i0_r + ecall_r := (io.dec_tlu_packet_r.pmu_i0_itype === ECALL) & io.dec_tlu_i0_valid_r & !i0_trigger_hit_r & ~rfpc_i0_r + illegal_r := ~io.dec_tlu_packet_r.legal & io.dec_tlu_i0_valid_r & !i0_trigger_hit_r & ~rfpc_i0_r + mret_r := (io.dec_tlu_packet_r.pmu_i0_itype === MRET) & io.dec_tlu_i0_valid_r & !i0_trigger_hit_r & ~rfpc_i0_r + // fence_i includes debug only fence_i's + fence_i_r := (io.dec_tlu_packet_r.fence_i & io.dec_tlu_i0_valid_r & !i0_trigger_hit_r) & ~rfpc_i0_r + ic_perr_r := ifu_ic_error_start_f & ~csr.io.ext_int_freeze_d1 & (!internal_dbg_halt_mode_f | dcsr_single_step_running) & ~internal_pmu_fw_halt_mode_f + iccm_sbecc_r := ifu_iccm_rd_ecc_single_err_f & ~csr.io.ext_int_freeze_d1 & (!internal_dbg_halt_mode_f | dcsr_single_step_running) & ~internal_pmu_fw_halt_mode_f + + inst_acc_r_raw := io.dec_tlu_packet_r.icaf & io.dec_tlu_i0_valid_r + inst_acc_r := inst_acc_r_raw & ~rfpc_i0_r & ~i0_trigger_hit_r + val inst_acc_second_r = io.dec_tlu_packet_r.icaf_second + + ebreak_to_debug_mode_r := (io.dec_tlu_packet_r.pmu_i0_itype === EBREAK) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & dcsr(DCSR_EBREAKM) & ~rfpc_i0_r + + ebreak_to_debug_mode_r_d1:= withClock(e4e5_clk){RegNext(ebreak_to_debug_mode_r,0.U)} + io.tlu_mem.dec_tlu_fence_i_wb := fence_i_r - // Compute interrupt path: - // If vectored async is set in mtvec, flush path for interrupts is MTVEC + (4 * CAUSE); - val vectored_path = Cat(mtvec(30,1),0.U(1.W)) + Cat(0.U(25.W),exc_cause_r, 0.U(1.W)) ///After Combining Code revisit this - val interrupt_path = Mux(take_nmi.asBool, io.nmi_vec, Mux(mtvec(0) === 1.U, vectored_path, Cat(mtvec(30,1),0.U(1.W))))///After Combining Code revisit this - val sel_npc_r = lsu_i0_rfnpc_r | fence_i_r | iccm_repair_state_rfnpc | (i_cpu_run_req_d1 & ~interrupt_valid_r) | (rfpc_i0_r & ~io.dec_tlu_i0_valid_r) - val sel_npc_resume = (i_cpu_run_req_d1 & pmu_fw_tlu_halted_f) | pause_expired_r - val sel_fir_addr = take_ext_int_start_d3 & ~io.lsu_fir_error.orR - synchronous_flush_r := i0_exception_valid_r | rfpc_i0_r | lsu_exc_valid_r | fence_i_r | lsu_i0_rfnpc_r | iccm_repair_state_rfnpc | debug_resume_req_f | sel_npc_resume | dec_tlu_wr_pause_r_d1 | i0_trigger_hit_r - tlu_flush_lower_r := interrupt_valid_r | mret_r | synchronous_flush_r | take_halt | take_reset | take_ext_int_start - ///After Combining Code revisit this - val tlu_flush_path_r = Mux(take_reset.asBool, io.rst_vec,Mux1H(Seq( - (sel_fir_addr).asBool -> io.lsu_fir_addr, - (take_nmi===0.U & sel_npc_r===1.U) -> npc_r, - (take_nmi===0.U & rfpc_i0_r===1.U & io.dec_tlu_i0_valid_r===1.U & sel_npc_r===0.U) -> io.dec_tlu_i0_pc_r, - (interrupt_valid_r===1.U & sel_fir_addr===0.U) -> interrupt_path, - ((i0_exception_valid_r | lsu_exc_valid_r | (i0_trigger_hit_r & ~trigger_hit_dmode_r)) & ~interrupt_valid_r & ~sel_fir_addr).asBool -> Cat(mtvec(30,1),0.U(1.W)), - (~take_nmi & mret_r).asBool -> mepc, - (~take_nmi & debug_resume_req_f).asBool -> dpc, - (~take_nmi & sel_npc_resume).asBool -> npc_r_d1 - ))) + int_exc.io.free_l2clk := io.free_l2clk + int_exc.io.scan_mode := io.scan_mode + int_exc.io.dec_csr_stall_int_ff := io.dec_csr_stall_int_ff + int_exc.io.mstatus_mie_ns := mstatus_mie_ns + int_exc.io.mip := mip + int_exc.io.mie_ns := mie_ns + int_exc.io.mret_r := mret_r + int_exc.io.pmu_fw_tlu_halted_f := pmu_fw_tlu_halted_f + int_exc.io.int_timer0_int_hold_f := int_timer0_int_hold_f + int_exc.io.int_timer1_int_hold_f := int_timer1_int_hold_f + int_exc.io.internal_dbg_halt_mode_f := internal_dbg_halt_mode_f + int_exc.io.dcsr_single_step_running := dcsr_single_step_running + int_exc.io.internal_dbg_halt_mode := internal_dbg_halt_mode + int_exc.io.dec_tlu_i0_valid_r := io.dec_tlu_i0_valid_r + int_exc.io.internal_pmu_fw_halt_mode := internal_pmu_fw_halt_mode + int_exc.io.i_cpu_halt_req_d1 := i_cpu_halt_req_d1 + int_exc.io.ebreak_to_debug_mode_r := ebreak_to_debug_mode_r + int_exc.io.lsu_fir_error := io.lsu_fir_error + int_exc.io.csr_pkt := csr_pkt + int_exc.io.dec_csr_any_unq_d := io.dec_csr_any_unq_d + int_exc.io.lsu_fastint_stall_any := io.lsu_fastint_stall_any + int_exc.io.reset_delayed := reset_delayed + int_exc.io.mpc_reset_run_req := io.mpc_reset_run_req + int_exc.io.nmi_int_detected := nmi_int_detected + int_exc.io.dcsr_single_step_running_f := dcsr_single_step_running_f + int_exc.io.dcsr_single_step_done_f := dcsr_single_step_done_f + int_exc.io.dcsr := dcsr + int_exc.io.mtvec := mtvec + int_exc.io.tlu_i0_commit_cmt := tlu_i0_commit_cmt + int_exc.io.i0_trigger_hit_r := i0_trigger_hit_r + int_exc.io.pause_expired_r := pause_expired_r + int_exc.io.nmi_vec := io.nmi_vec + int_exc.io.lsu_i0_rfnpc_r := lsu_i0_rfnpc_r + int_exc.io.fence_i_r := fence_i_r + int_exc.io.iccm_repair_state_rfnpc := iccm_repair_state_rfnpc + int_exc.io.i_cpu_run_req_d1 := i_cpu_run_req_d1 + int_exc.io.rfpc_i0_r := rfpc_i0_r + int_exc.io.lsu_exc_valid_r := lsu_exc_valid_r + int_exc.io.trigger_hit_dmode_r := trigger_hit_dmode_r + int_exc.io.take_halt := take_halt + int_exc.io.rst_vec := io.rst_vec + int_exc.io.lsu_fir_addr := io.lsu_fir_addr + int_exc.io.dec_tlu_i0_pc_r := io.dec_tlu_i0_pc_r + int_exc.io.npc_r := npc_r + int_exc.io.mepc := mepc + int_exc.io.debug_resume_req_f := debug_resume_req_f + int_exc.io.dpc := dpc + int_exc.io.npc_r_d1 := npc_r_d1 + int_exc.io.tlu_flush_lower_r_d1 := tlu_flush_lower_r_d1 + int_exc.io.dec_tlu_dbg_halted := io.dec_tlu_dbg_halted + int_exc.io.ebreak_r := ebreak_r + int_exc.io.ecall_r := ecall_r + int_exc.io.illegal_r := illegal_r + int_exc.io.inst_acc_r := inst_acc_r + int_exc.io.lsu_i0_exc_r := lsu_i0_exc_r + int_exc.io.lsu_error_pkt_r := io.lsu_error_pkt_r + int_exc.io.dec_tlu_wr_pause_r_d1 := dec_tlu_wr_pause_r_d1 + //outputs + mhwakeup_ready := int_exc.io.mhwakeup_ready + ext_int_ready := int_exc.io.ext_int_ready + ce_int_ready := int_exc.io.ce_int_ready + soft_int_ready := int_exc.io.soft_int_ready + timer_int_ready := int_exc.io.timer_int_ready + int_timer0_int_hold := int_exc.io.int_timer0_int_hold + int_timer1_int_hold := int_exc.io.int_timer1_int_hold + internal_dbg_halt_timers := int_exc.io.internal_dbg_halt_timers + take_ext_int_start := int_exc.io.take_ext_int_start + int_exc.io.ext_int_freeze_d1 := csr.io.ext_int_freeze_d1 + int_exc.io.take_ext_int_start_d1 := csr.io.take_ext_int_start_d1 + int_exc.io.take_ext_int_start_d2 := csr.io.take_ext_int_start_d2 + int_exc.io.take_ext_int_start_d3 := csr.io.take_ext_int_start_d3 + // take_ext_int_start_d1 := csr.io.take_ext_int_start_d1 + // take_ext_int_start_d2 := csr.io.take_ext_int_start_d2 + // take_ext_int_start_d3 := csr.io.take_ext_int_start_d3 + ext_int_freeze := int_exc.io.ext_int_freeze + take_ext_int := int_exc.io.take_ext_int + fast_int_meicpct := int_exc.io.fast_int_meicpct + ignore_ext_int_due_to_lsu_stall := int_exc.io.ignore_ext_int_due_to_lsu_stall + take_ce_int := int_exc.io.take_ce_int + take_soft_int := int_exc.io.take_soft_int + take_timer_int := int_exc.io.take_timer_int + take_int_timer0_int := int_exc.io.take_int_timer0_int + take_int_timer1_int := int_exc.io.take_int_timer1_int + take_reset := int_exc.io.take_reset + take_nmi := int_exc.io.take_nmi + synchronous_flush_r := int_exc.io.synchronous_flush_r + tlu_flush_lower_r := int_exc.io.tlu_flush_lower_r + io.dec_tlu_flush_lower_wb := int_exc.io.dec_tlu_flush_lower_wb + io.tlu_exu.dec_tlu_flush_lower_r := int_exc.io.dec_tlu_flush_lower_r + io.tlu_exu.dec_tlu_flush_path_r := int_exc.io.dec_tlu_flush_path_r + interrupt_valid_r_d1 := int_exc.io.interrupt_valid_r_d1 + exc_or_int_valid_r_d1 := int_exc.io.exc_or_int_valid_r_d1 + take_nmi_r_d1 := int_exc.io.take_nmi_r_d1 + pause_expired_wb := int_exc.io.pause_expired_wb + interrupt_valid_r := int_exc.io.interrupt_valid_r - val tlu_flush_path_r_d1=withClock(e4e5_int_clk){RegNext(tlu_flush_path_r,0.U)} ///After Combining Code revisit this + //intrputsd - io.dec_tlu_flush_lower_wb := tlu_flush_lower_r_d1 - io.tlu_exu.dec_tlu_flush_lower_r := tlu_flush_lower_r - io.tlu_exu.dec_tlu_flush_path_r := tlu_flush_path_r ///After Combining Code revisit this - - // this is used to capture mepc, etc. - val exc_or_int_valid_r = lsu_exc_valid_r | i0_exception_valid_r | interrupt_valid_r | (i0_trigger_hit_r & ~trigger_hit_dmode_r) - - interrupt_valid_r_d1 := withClock(e4e5_int_clk){RegNext(interrupt_valid_r,0.U)} - val i0_exception_valid_r_d1 = withClock(e4e5_int_clk){RegNext(i0_exception_valid_r,0.U)} - exc_or_int_valid_r_d1 := withClock(e4e5_int_clk){RegNext(exc_or_int_valid_r,0.U)} - val exc_cause_wb = withClock(e4e5_int_clk){RegNext(exc_cause_r,0.U)} - val i0_valid_wb = withClock(e4e5_int_clk){RegNext((tlu_i0_commit_cmt & ~illegal_r),0.U)} - val trigger_hit_r_d1 = withClock(e4e5_int_clk){RegNext(i0_trigger_hit_r,0.U)} - take_nmi_r_d1 := withClock(e4e5_int_clk){RegNext(take_nmi,0.U)} - pause_expired_wb := withClock(e4e5_int_clk){RegNext(pause_expired_r,0.U)} - -val csr=Module(new csr_tlu) - csr.io.free_clk := io.free_clk - csr.io.active_clk := io.active_clk - csr.io.scan_mode := io.scan_mode - csr.io.dec_csr_wrdata_r := io.dec_csr_wrdata_r - csr.io.dec_csr_wraddr_r := io.dec_csr_wraddr_r - csr.io.dec_csr_rdaddr_d := io.dec_csr_rdaddr_d - csr.io.dec_csr_wen_unq_d := io.dec_csr_wen_unq_d - csr.io.dec_i0_decode_d := io.dec_i0_decode_d - csr.io.ifu_ic_debug_rd_data_valid := io.tlu_mem.ifu_ic_debug_rd_data_valid - csr.io.ifu_pmu_bus_trxn := io.tlu_mem.ifu_pmu_bus_trxn - csr.io.dma_iccm_stall_any := io.tlu_dma.dma_iccm_stall_any - csr.io.dma_dccm_stall_any := io.tlu_dma.dma_dccm_stall_any - csr.io.lsu_store_stall_any := io.lsu_store_stall_any - csr.io.dec_pmu_presync_stall := io.dec_pmu_presync_stall - csr.io.dec_pmu_postsync_stall := io.dec_pmu_postsync_stall - csr.io.dec_pmu_decode_stall := io.dec_pmu_decode_stall - csr.io.ifu_pmu_fetch_stall := io.tlu_ifc.ifu_pmu_fetch_stall - csr.io.dec_tlu_packet_r := io.dec_tlu_packet_r - csr.io.exu_pmu_i0_br_ataken := io.tlu_exu.exu_pmu_i0_br_ataken - csr.io.exu_pmu_i0_br_misp := io.tlu_exu.exu_pmu_i0_br_misp - csr.io.dec_pmu_instr_decoded := io.dec_pmu_instr_decoded - csr.io.ifu_pmu_instr_aligned := io.ifu_pmu_instr_aligned - csr.io.exu_pmu_i0_pc4 := io.tlu_exu.exu_pmu_i0_pc4 - csr.io.ifu_pmu_ic_miss := io.tlu_mem.ifu_pmu_ic_miss - csr.io.ifu_pmu_ic_hit := io.tlu_mem.ifu_pmu_ic_hit - csr.io.dec_csr_wen_r := io.dec_csr_wen_r - csr.io.dec_tlu_dbg_halted := io.dec_tlu_dbg_halted - csr.io.dma_pmu_dccm_write := io.tlu_dma.dma_pmu_dccm_write - csr.io.dma_pmu_dccm_read := io.tlu_dma.dma_pmu_dccm_read - csr.io.dma_pmu_any_write := io.tlu_dma.dma_pmu_any_write - csr.io.dma_pmu_any_read := io.tlu_dma.dma_pmu_any_read - csr.io.lsu_pmu_bus_busy := io.tlu_busbuff.lsu_pmu_bus_busy - csr.io.dec_tlu_i0_pc_r := io.dec_tlu_i0_pc_r - csr.io.dec_tlu_i0_valid_r := io.dec_tlu_i0_valid_r - csr.io.dec_csr_stall_int_ff := io.dec_csr_stall_int_ff - csr.io.dec_csr_any_unq_d := io.dec_csr_any_unq_d - csr.io.ifu_pmu_bus_busy := io.tlu_mem.ifu_pmu_bus_busy - csr.io.lsu_pmu_bus_error := io.tlu_busbuff.lsu_pmu_bus_error - csr.io.ifu_pmu_bus_error := io.tlu_mem.ifu_pmu_bus_error - csr.io.lsu_pmu_bus_misaligned := io.tlu_busbuff.lsu_pmu_bus_misaligned - csr.io.lsu_pmu_bus_trxn := io.tlu_busbuff.lsu_pmu_bus_trxn - csr.io.ifu_ic_debug_rd_data := io.tlu_mem.ifu_ic_debug_rd_data - csr.io.pic_pl := io.dec_pic.pic_pl - csr.io.pic_claimid := io.dec_pic.pic_claimid - csr.io.iccm_dma_sb_error := io.iccm_dma_sb_error - csr.io.lsu_imprecise_error_addr_any := io.tlu_busbuff.lsu_imprecise_error_addr_any - csr.io.lsu_imprecise_error_load_any := io.tlu_busbuff.lsu_imprecise_error_load_any - csr.io.lsu_imprecise_error_store_any := io.tlu_busbuff.lsu_imprecise_error_store_any - csr.io.dec_illegal_inst := io.dec_illegal_inst - csr.io.lsu_error_pkt_r := io.lsu_error_pkt_r - csr.io.mexintpend := io.dec_pic.mexintpend - csr.io.exu_npc_r := io.tlu_exu.exu_npc_r - csr.io.mpc_reset_run_req := io.mpc_reset_run_req - csr.io.rst_vec := io.rst_vec - csr.io.core_id := io.core_id - csr.io.dec_timer_rddata_d := dec_timer_rddata_d - csr.io.dec_timer_read_d := dec_timer_read_d - io.dec_pic.dec_tlu_meicurpl := csr.io.dec_tlu_meicurpl - io.tlu_exu.dec_tlu_meihap := csr.io.dec_tlu_meihap - io.dec_pic.dec_tlu_meipt := csr.io.dec_tlu_meipt - io.dec_tlu_int_valid_wb1 := csr.io.dec_tlu_int_valid_wb1 - io.dec_tlu_i0_exc_valid_wb1 := csr.io.dec_tlu_i0_exc_valid_wb1 - io.dec_tlu_i0_valid_wb1 := csr.io.dec_tlu_i0_valid_wb1 - io.tlu_mem.dec_tlu_ic_diag_pkt := csr.io.dec_tlu_ic_diag_pkt - io.trigger_pkt_any := csr.io.trigger_pkt_any - io.dec_tlu_mtval_wb1 := csr.io.dec_tlu_mtval_wb1 - io.dec_tlu_exc_cause_wb1 := csr.io.dec_tlu_exc_cause_wb1 - io.dec_tlu_perfcnt0 := csr.io.dec_tlu_perfcnt0 - io.dec_tlu_perfcnt1 := csr.io.dec_tlu_perfcnt1 - io.dec_tlu_perfcnt2 := csr.io.dec_tlu_perfcnt2 - io.dec_tlu_perfcnt3 := csr.io.dec_tlu_perfcnt3 - io.dec_tlu_misc_clk_override := csr.io.dec_tlu_misc_clk_override - io.dec_tlu_dec_clk_override := csr.io.dec_tlu_dec_clk_override - io.dec_tlu_ifu_clk_override := csr.io.dec_tlu_ifu_clk_override - io.dec_tlu_lsu_clk_override := csr.io.dec_tlu_lsu_clk_override - io.dec_tlu_bus_clk_override := csr.io.dec_tlu_bus_clk_override - io.dec_tlu_pic_clk_override := csr.io.dec_tlu_pic_clk_override - io.dec_tlu_dccm_clk_override := csr.io.dec_tlu_dccm_clk_override - io.dec_tlu_icm_clk_override := csr.io.dec_tlu_icm_clk_override - io.dec_csr_rddata_d := csr.io.dec_csr_rddata_d - io.dec_tlu_pipelining_disable := csr.io.dec_tlu_pipelining_disable - io.dec_tlu_wr_pause_r := csr.io.dec_tlu_wr_pause_r - io.tlu_ifc.dec_tlu_mrac_ff := csr.io.dec_tlu_mrac_ff - io.tlu_busbuff.dec_tlu_wb_coalescing_disable := csr.io.dec_tlu_wb_coalescing_disable - io.tlu_bp.dec_tlu_bpred_disable := csr.io.dec_tlu_bpred_disable - io.tlu_busbuff.dec_tlu_sideeffect_posted_disable := csr.io.dec_tlu_sideeffect_posted_disable - io.tlu_mem.dec_tlu_core_ecc_disable := csr.io.dec_tlu_core_ecc_disable - io.tlu_busbuff.dec_tlu_external_ldfwd_disable := csr.io.dec_tlu_external_ldfwd_disable - io.tlu_dma.dec_tlu_dma_qos_prty := csr.io.dec_tlu_dma_qos_prty - csr.io.dec_illegal_inst := io.dec_illegal_inst - csr.io.lsu_error_pkt_r := io.lsu_error_pkt_r - csr.io.mexintpend := io.dec_pic.mexintpend - csr.io.exu_npc_r := io.tlu_exu.exu_npc_r - csr.io.mpc_reset_run_req := io.mpc_reset_run_req - csr.io.rst_vec := io.rst_vec - csr.io.core_id := io.core_id - csr.io.dec_timer_rddata_d := dec_timer_rddata_d - csr.io.dec_timer_read_d := dec_timer_read_d + csr.io.ext_int_freeze := int_exc.io.ext_int_freeze + csr.io.free_clk := io.free_clk + csr.io.free_l2clk := io.free_l2clk + csr.io.scan_mode := io.scan_mode + csr.io.dec_csr_wrdata_r := io.dec_csr_wrdata_r + csr.io.dec_csr_wraddr_r := io.dec_csr_wraddr_r + csr.io.dec_csr_rdaddr_d := io.dec_csr_rdaddr_d + csr.io.dec_csr_wen_unq_d := io.dec_csr_wen_unq_d + csr.io.dec_i0_decode_d := io.dec_i0_decode_d + csr.io.ifu_ic_debug_rd_data_valid := io.tlu_mem.ifu_ic_debug_rd_data_valid + csr.io.ifu_pmu_bus_trxn := io.tlu_mem.ifu_pmu_bus_trxn + csr.io.dma_iccm_stall_any :=io.tlu_dma.dma_iccm_stall_any + csr.io.dma_dccm_stall_any :=io.tlu_dma.dma_dccm_stall_any + csr.io.lsu_store_stall_any :=io.lsu_store_stall_any + csr.io.dec_pmu_presync_stall :=io.dec_pmu_presync_stall + csr.io.dec_pmu_postsync_stall :=io.dec_pmu_postsync_stall + csr.io.dec_pmu_decode_stall :=io.dec_pmu_decode_stall + csr.io.ifu_pmu_fetch_stall :=io.tlu_ifc.ifu_pmu_fetch_stall + csr.io.dec_tlu_packet_r :=io.dec_tlu_packet_r + csr.io.exu_pmu_i0_br_ataken :=io.tlu_exu.exu_pmu_i0_br_ataken + csr.io.exu_pmu_i0_br_misp :=io.tlu_exu.exu_pmu_i0_br_misp + csr.io.dec_pmu_instr_decoded :=io.dec_pmu_instr_decoded + csr.io.ifu_pmu_instr_aligned :=io.ifu_pmu_instr_aligned + csr.io.exu_pmu_i0_pc4 :=io.tlu_exu.exu_pmu_i0_pc4 + csr.io.ifu_pmu_ic_miss :=io.tlu_mem.ifu_pmu_ic_miss + csr.io.ifu_pmu_ic_hit :=io.tlu_mem.ifu_pmu_ic_hit + csr.io.dec_csr_wen_r := io.dec_csr_wen_r + csr.io.dec_tlu_dbg_halted := io.dec_tlu_dbg_halted + csr.io.dma_pmu_dccm_write := io.tlu_dma.dma_pmu_dccm_write + csr.io.dma_pmu_dccm_read := io.tlu_dma.dma_pmu_dccm_read + csr.io.dma_pmu_any_write := io.tlu_dma.dma_pmu_any_write + csr.io.dma_pmu_any_read := io.tlu_dma.dma_pmu_any_read + csr.io.lsu_pmu_bus_busy := io.tlu_busbuff.lsu_pmu_bus_busy + csr.io.dec_tlu_i0_pc_r := io.dec_tlu_i0_pc_r + csr.io.dec_tlu_i0_valid_r := io.dec_tlu_i0_valid_r + csr.io.dec_csr_stall_int_ff := io.dec_csr_stall_int_ff + csr.io.dec_csr_any_unq_d := io.dec_csr_any_unq_d + csr.io.ifu_pmu_bus_busy := io.tlu_mem.ifu_pmu_bus_busy + csr.io.lsu_pmu_bus_error := io.tlu_busbuff.lsu_pmu_bus_error + csr.io.ifu_pmu_bus_error := io.tlu_mem.ifu_pmu_bus_error + csr.io.lsu_pmu_bus_misaligned := io.tlu_busbuff.lsu_pmu_bus_misaligned + csr.io.lsu_pmu_bus_trxn := io.tlu_busbuff.lsu_pmu_bus_trxn + csr.io.ifu_ic_debug_rd_data := io.tlu_mem.ifu_ic_debug_rd_data + csr.io.pic_pl := io.dec_pic.pic_pl + csr.io.pic_claimid := io.dec_pic.pic_claimid + csr.io.iccm_dma_sb_error := io.iccm_dma_sb_error + csr.io.lsu_imprecise_error_addr_any := io.tlu_busbuff.lsu_imprecise_error_addr_any + csr.io.lsu_imprecise_error_load_any := io.tlu_busbuff.lsu_imprecise_error_load_any + csr.io.lsu_imprecise_error_store_any := io.tlu_busbuff.lsu_imprecise_error_store_any + csr.io.dec_illegal_inst := io.dec_illegal_inst + csr.io.lsu_error_pkt_r := io.lsu_error_pkt_r + csr.io.mexintpend := io.dec_pic.mexintpend + csr.io.exu_npc_r := io.tlu_exu.exu_npc_r + csr.io.mpc_reset_run_req := io.mpc_reset_run_req + csr.io.rst_vec := io.rst_vec + csr.io.core_id := io.core_id + csr.io.dec_timer_rddata_d := dec_timer_rddata_d + csr.io.dec_timer_read_d := dec_timer_read_d + io.dec_pic.dec_tlu_meicurpl := csr.io.dec_tlu_meicurpl + io.tlu_exu.dec_tlu_meihap := csr.io.dec_tlu_meihap + io.dec_pic.dec_tlu_meipt := csr.io.dec_tlu_meipt + io.dec_tlu_int_valid_wb1 := csr.io.dec_tlu_int_valid_wb1 + io.dec_tlu_i0_exc_valid_wb1 := csr.io.dec_tlu_i0_exc_valid_wb1 + io.dec_tlu_i0_valid_wb1 := csr.io.dec_tlu_i0_valid_wb1 + io.tlu_mem.dec_tlu_ic_diag_pkt := csr.io.dec_tlu_ic_diag_pkt + io.trigger_pkt_any := csr.io.trigger_pkt_any + io.dec_tlu_mtval_wb1 := csr.io.dec_tlu_mtval_wb1 + io.dec_tlu_exc_cause_wb1 := csr.io.dec_tlu_exc_cause_wb1 + io.dec_tlu_perfcnt0 := csr.io.dec_tlu_perfcnt0 + io.dec_tlu_perfcnt1 := csr.io.dec_tlu_perfcnt1 + io.dec_tlu_perfcnt2 := csr.io.dec_tlu_perfcnt2 + io.dec_tlu_perfcnt3 := csr.io.dec_tlu_perfcnt3 + io.dec_tlu_misc_clk_override := csr.io.dec_tlu_misc_clk_override + io.dec_tlu_picio_clk_override := csr.io.dec_tlu_picio_clk_override + io.dec_tlu_dec_clk_override := csr.io.dec_tlu_dec_clk_override + io.dec_tlu_ifu_clk_override := csr.io.dec_tlu_ifu_clk_override + io.dec_tlu_lsu_clk_override := csr.io.dec_tlu_lsu_clk_override + io.dec_tlu_bus_clk_override := csr.io.dec_tlu_bus_clk_override + io.dec_tlu_pic_clk_override := csr.io.dec_tlu_pic_clk_override + io.dec_tlu_dccm_clk_override := csr.io.dec_tlu_dccm_clk_override + io.dec_tlu_icm_clk_override := csr.io.dec_tlu_icm_clk_override + io.dec_csr_rddata_d := csr.io.dec_csr_rddata_d + io.dec_tlu_pipelining_disable := csr.io.dec_tlu_pipelining_disable + io.dec_tlu_wr_pause_r := csr.io.dec_tlu_wr_pause_r + io.tlu_ifc.dec_tlu_mrac_ff := csr.io.dec_tlu_mrac_ff + io.tlu_busbuff.dec_tlu_wb_coalescing_disable := csr.io.dec_tlu_wb_coalescing_disable + io.tlu_bp.dec_tlu_bpred_disable := csr.io.dec_tlu_bpred_disable + io.tlu_busbuff.dec_tlu_sideeffect_posted_disable := csr.io.dec_tlu_sideeffect_posted_disable + io.tlu_mem.dec_tlu_core_ecc_disable := csr.io.dec_tlu_core_ecc_disable + io.tlu_busbuff.dec_tlu_external_ldfwd_disable := csr.io.dec_tlu_external_ldfwd_disable + io.tlu_dma.dec_tlu_dma_qos_prty := csr.io.dec_tlu_dma_qos_prty + io.dec_tlu_trace_disable := csr.io.dec_tlu_trace_disable + csr.io.dec_illegal_inst := io.dec_illegal_inst + csr.io.lsu_error_pkt_r := io.lsu_error_pkt_r + csr.io.mexintpend := io.dec_pic.mexintpend + csr.io.exu_npc_r := io.tlu_exu.exu_npc_r + csr.io.mpc_reset_run_req := io.mpc_reset_run_req + csr.io.rst_vec := io.rst_vec + csr.io.core_id := io.core_id + csr.io.dec_timer_rddata_d := dec_timer_rddata_d + csr.io.dec_timer_read_d := dec_timer_read_d - csr.io.rfpc_i0_r := rfpc_i0_r - csr.io.i0_trigger_hit_r := i0_trigger_hit_r - csr.io.exc_or_int_valid_r := exc_or_int_valid_r - csr.io.mret_r := mret_r - csr.io.dcsr_single_step_running_f := dcsr_single_step_running_f - csr.io.dec_timer_t0_pulse := dec_timer_t0_pulse - csr.io.dec_timer_t1_pulse := dec_timer_t1_pulse - csr.io.timer_int_sync := timer_int_sync - csr.io.soft_int_sync := soft_int_sync - csr.io.csr_wr_clk := csr_wr_clk - csr.io.ebreak_to_debug_mode_r := ebreak_to_debug_mode_r - csr.io.dec_tlu_pmu_fw_halted := dec_tlu_pmu_fw_halted - csr.io.lsu_fir_error := io.lsu_fir_error - csr.io.tlu_flush_lower_r_d1 := tlu_flush_lower_r_d1 - csr.io.dec_tlu_flush_noredir_r_d1 := dec_tlu_flush_noredir_r_d1 - csr.io.tlu_flush_path_r_d1 := tlu_flush_path_r_d1 - csr.io.reset_delayed := reset_delayed - csr.io.interrupt_valid_r := interrupt_valid_r - csr.io.i0_exception_valid_r := i0_exception_valid_r - csr.io.lsu_exc_valid_r := lsu_exc_valid_r - csr.io.mepc_trigger_hit_sel_pc_r := mepc_trigger_hit_sel_pc_r - csr.io.e4e5_int_clk := e4e5_int_clk - csr.io.lsu_i0_exc_r := lsu_i0_exc_r - csr.io.inst_acc_r := inst_acc_r - csr.io.inst_acc_second_r := inst_acc_second_r - csr.io.take_nmi := take_nmi - csr.io.lsu_error_pkt_addr_r := lsu_error_pkt_addr_r - csr.io.exc_cause_r := exc_cause_r - csr.io.i0_valid_wb := i0_valid_wb - csr.io.exc_or_int_valid_r_d1 := exc_or_int_valid_r_d1 - csr.io.interrupt_valid_r_d1 := interrupt_valid_r_d1 - csr.io.clk_override := clk_override - csr.io.i0_exception_valid_r_d1 := i0_exception_valid_r_d1 - csr.io.lsu_i0_exc_r_d1 := lsu_i0_exc_r_d1 - csr.io.exc_cause_wb := exc_cause_wb - csr.io.nmi_lsu_store_type := nmi_lsu_store_type - csr.io.nmi_lsu_load_type := nmi_lsu_load_type - csr.io.tlu_i0_commit_cmt := tlu_i0_commit_cmt - csr.io.ebreak_r := ebreak_r - csr.io.ecall_r := ecall_r - csr.io.illegal_r := illegal_r - csr.io.mdseac_locked_f := mdseac_locked_f - csr.io.nmi_int_detected_f := nmi_int_detected_f - csr.io.internal_dbg_halt_mode_f2 := internal_dbg_halt_mode_f2 - csr.io.ext_int_freeze_d1 := ext_int_freeze_d1 - csr.io.ic_perr_r_d1 := ic_perr_r_d1 - csr.io.iccm_sbecc_r_d1 := iccm_sbecc_r_d1 - csr.io.lsu_single_ecc_error_r_d1 := lsu_single_ecc_error_r_d1 - csr.io.ifu_miss_state_idle_f := ifu_miss_state_idle_f - csr.io.lsu_idle_any_f := lsu_idle_any_f - csr.io.dbg_tlu_halted_f := dbg_tlu_halted_f - csr.io.dbg_tlu_halted := dbg_tlu_halted - csr.io.debug_halt_req_f := debug_halt_req_f - csr.io.take_ext_int_start := take_ext_int_start - csr.io.trigger_hit_dmode_r_d1 := trigger_hit_dmode_r_d1 - csr.io.trigger_hit_r_d1 := trigger_hit_r_d1 - csr.io.dcsr_single_step_done_f := dcsr_single_step_done_f - csr.io.ebreak_to_debug_mode_r_d1 := ebreak_to_debug_mode_r_d1 - csr.io.debug_halt_req := debug_halt_req - csr.io.allow_dbg_halt_csr_write := allow_dbg_halt_csr_write - csr.io.internal_dbg_halt_mode_f := internal_dbg_halt_mode_f - csr.io.enter_debug_halt_req := enter_debug_halt_req - csr.io.internal_dbg_halt_mode := internal_dbg_halt_mode - csr.io.request_debug_mode_done := request_debug_mode_done - csr.io.request_debug_mode_r := request_debug_mode_r - csr.io.update_hit_bit_r := update_hit_bit_r - csr.io.take_timer_int := take_timer_int - csr.io.take_int_timer0_int := take_int_timer0_int - csr.io.take_int_timer1_int := take_int_timer1_int - csr.io.take_ext_int := take_ext_int - csr.io.tlu_flush_lower_r := tlu_flush_lower_r - csr.io.dec_tlu_br0_error_r := dec_tlu_br0_error_r - csr.io.dec_tlu_br0_start_error_r := dec_tlu_br0_start_error_r - csr.io.lsu_pmu_load_external_r := lsu_pmu_load_external_r - csr.io.lsu_pmu_store_external_r := lsu_pmu_store_external_r - csr.io.csr_pkt := csr_pkt + csr.io.rfpc_i0_r := rfpc_i0_r + csr.io.i0_trigger_hit_r := i0_trigger_hit_r + csr.io.exc_or_int_valid_r := int_exc.io.exc_or_int_valid_r + csr.io.mret_r := mret_r + csr.io.dcsr_single_step_running_f := dcsr_single_step_running_f + csr.io.dec_timer_t0_pulse := dec_timer_t0_pulse + csr.io.dec_timer_t1_pulse := dec_timer_t1_pulse + csr.io.timer_int_sync := timer_int_sync + csr.io.soft_int_sync := soft_int_sync + csr.io.csr_wr_clk := csr_wr_clk + csr.io.ebreak_to_debug_mode_r := ebreak_to_debug_mode_r + csr.io.dec_tlu_pmu_fw_halted := dec_tlu_pmu_fw_halted + csr.io.lsu_fir_error := io.lsu_fir_error + csr.io.tlu_flush_lower_r_d1 := tlu_flush_lower_r_d1 + csr.io.dec_tlu_flush_noredir_r_d1 := dec_tlu_flush_noredir_r_d1 + csr.io.tlu_flush_path_r_d1 := int_exc.io.tlu_flush_path_r_d1 + csr.io.reset_delayed := reset_delayed + csr.io.interrupt_valid_r := interrupt_valid_r + csr.io.i0_exception_valid_r := int_exc.io.i0_exception_valid_r + csr.io.lsu_exc_valid_r := lsu_exc_valid_r + csr.io.mepc_trigger_hit_sel_pc_r := mepc_trigger_hit_sel_pc_r + csr.io.lsu_single_ecc_error_r := lsu_single_ecc_error_r + csr.io.e4e5_int_clk := e4e5_int_clk + csr.io.lsu_i0_exc_r := lsu_i0_exc_r + csr.io.inst_acc_r := inst_acc_r + csr.io.inst_acc_second_r := inst_acc_second_r + csr.io.take_nmi := take_nmi + csr.io.lsu_error_pkt_addr_r := lsu_error_pkt_addr_r + csr.io.exc_cause_r := int_exc.io.exc_cause_r + csr.io.i0_valid_wb := int_exc.io.i0_valid_wb + csr.io.exc_or_int_valid_r_d1 := exc_or_int_valid_r_d1 + csr.io.interrupt_valid_r_d1 := interrupt_valid_r_d1 + csr.io.clk_override := clk_override + csr.io.i0_exception_valid_r_d1 := int_exc.io.i0_exception_valid_r_d1 + // lsu_i0_exc_r_d1 := csr.io.lsu_i0_exc_r_d1 + csr.io.exc_cause_wb := int_exc.io.exc_cause_wb + csr.io.nmi_lsu_store_type := nmi_lsu_store_type + csr.io.nmi_lsu_load_type := nmi_lsu_load_type + csr.io.tlu_i0_commit_cmt := tlu_i0_commit_cmt + csr.io.ebreak_r := ebreak_r + csr.io.ecall_r := ecall_r + csr.io.illegal_r := illegal_r + mdseac_locked_f := csr.io.mdseac_locked_f + csr.io.nmi_int_detected_f := nmi_int_detected_f + csr.io.internal_dbg_halt_mode_f2 := internal_dbg_halt_mode_f2 + // ext_int_freeze_d1 := csr.io.ext_int_freeze_d1 + csr.io.ic_perr_r := ic_perr_r + csr.io.iccm_sbecc_r := iccm_sbecc_r + // csr.io.lsu_single_ecc_error_r_d1 := lsu_single_ecc_error_r_d1 + csr.io.ifu_miss_state_idle_f := ifu_miss_state_idle_f + csr.io.lsu_idle_any_f := lsu_idle_any_f + csr.io.dbg_tlu_halted_f := dbg_tlu_halted_f + csr.io.dbg_tlu_halted := dbg_tlu_halted + csr.io.debug_halt_req_f := debug_halt_req_f + csr.io.take_ext_int_start := take_ext_int_start + csr.io.trigger_hit_dmode_r_d1 := trigger_hit_dmode_r_d1 + csr.io.trigger_hit_r_d1 := int_exc.io.trigger_hit_r_d1 + csr.io.dcsr_single_step_done_f := dcsr_single_step_done_f + csr.io.ebreak_to_debug_mode_r_d1 := ebreak_to_debug_mode_r_d1 + csr.io.debug_halt_req := debug_halt_req + csr.io.allow_dbg_halt_csr_write := allow_dbg_halt_csr_write + csr.io.internal_dbg_halt_mode_f := internal_dbg_halt_mode_f + csr.io.enter_debug_halt_req := enter_debug_halt_req + csr.io.internal_dbg_halt_mode := internal_dbg_halt_mode + csr.io.request_debug_mode_done := request_debug_mode_done + csr.io.request_debug_mode_r := request_debug_mode_r + csr.io.update_hit_bit_r := update_hit_bit_r + csr.io.take_timer_int := take_timer_int + csr.io.take_int_timer0_int := take_int_timer0_int + csr.io.take_int_timer1_int := take_int_timer1_int + csr.io.take_ext_int := take_ext_int + csr.io.tlu_flush_lower_r := tlu_flush_lower_r + csr.io.dec_tlu_br0_error_r := dec_tlu_br0_error_r + csr.io.dec_tlu_br0_start_error_r := dec_tlu_br0_start_error_r + csr.io.lsu_pmu_load_external_r := lsu_pmu_load_external_r + csr.io.lsu_pmu_store_external_r := lsu_pmu_store_external_r + csr.io.trigger_enabled := trigger_enabled + csr.io.csr_pkt := csr_pkt - npc_r := csr.io.npc_r - npc_r_d1 := csr.io.npc_r_d1 - mie_ns := csr.io.mie_ns - mepc := csr.io.mepc - mdseac_locked_ns := csr.io.mdseac_locked_ns - force_halt := csr.io.force_halt - dpc := csr.io.dpc - mstatus_mie_ns := csr.io.mstatus_mie_ns - dec_csr_wen_r_mod := csr.io.dec_csr_wen_r_mod - fw_halt_req := csr.io.fw_halt_req - mstatus := csr.io.mstatus - dcsr := csr.io.dcsr - mtvec := csr.io.mtvec - mip := csr.io.mip - mtdata1_t :=csr.io.mtdata1_t - val csr_read=Module(new dec_decode_csr_read) - csr_read.io.dec_csr_rdaddr_d:=io.dec_csr_rdaddr_d + npc_r := csr.io.npc_r + npc_r_d1 := csr.io.npc_r_d1 + mie_ns := csr.io.mie_ns + mepc := csr.io.mepc + mdseac_locked_ns := csr.io.mdseac_locked_ns + force_halt := csr.io.force_halt + dpc := csr.io.dpc + mstatus_mie_ns := csr.io.mstatus_mie_ns + dec_csr_wen_r_mod := csr.io.dec_csr_wen_r_mod + fw_halt_req := csr.io.fw_halt_req + mstatus := csr.io.mstatus + dcsr := csr.io.dcsr + mtvec := csr.io.mtvec + mip := csr.io.mip + mtdata1_t :=csr.io.mtdata1_t + val csr_read=Module(new dec_decode_csr_read) + csr_read.io.dec_csr_rdaddr_d:=io.dec_csr_rdaddr_d csr_pkt:=csr_read.io.csr_pkt -io.dec_tlu_presync_d := csr_pkt.presync & io.dec_csr_any_unq_d & ~io.dec_csr_wen_unq_d -io.dec_tlu_postsync_d := csr_pkt.postsync & io.dec_csr_any_unq_d + io.dec_tlu_presync_d := csr_pkt.presync & io.dec_csr_any_unq_d & ~io.dec_csr_wen_unq_d + io.dec_tlu_postsync_d := csr_pkt.postsync & io.dec_csr_any_unq_d - // allow individual configuration of these features -val conditionally_illegal = (csr_pkt.csr_mitcnt0 | csr_pkt.csr_mitcnt1 | csr_pkt.csr_mitb0 | csr_pkt.csr_mitb1 | csr_pkt.csr_mitctl0 | csr_pkt.csr_mitctl1) & ~TIMER_LEGAL_EN.asUInt -val valid_csr = ( csr_pkt.legal & (~(csr_pkt.csr_dcsr | csr_pkt.csr_dpc | csr_pkt.csr_dmst | csr_pkt.csr_dicawics | csr_pkt.csr_dicad0 | csr_pkt.csr_dicad0h | csr_pkt.csr_dicad1 | csr_pkt.csr_dicago) | dbg_tlu_halted_f) & ~fast_int_meicpct & ~conditionally_illegal) + // allow individual configuration of these features + val conditionally_illegal = (csr_pkt.csr_mitcnt0 | csr_pkt.csr_mitcnt1 | csr_pkt.csr_mitb0 | csr_pkt.csr_mitb1 | csr_pkt.csr_mitctl0 | csr_pkt.csr_mitctl1) & ~TIMER_LEGAL_EN.asUInt + val valid_csr = ( csr_pkt.legal & (~(csr_pkt.csr_dcsr | csr_pkt.csr_dpc | csr_pkt.csr_dmst | csr_pkt.csr_dicawics | csr_pkt.csr_dicad0 | csr_pkt.csr_dicad0h | csr_pkt.csr_dicad1 | csr_pkt.csr_dicago) | dbg_tlu_halted_f) & ~fast_int_meicpct & ~conditionally_illegal) -io.dec_csr_legal_d := ( io.dec_csr_any_unq_d &valid_csr & ~(io.dec_csr_wen_unq_d & (csr_pkt.csr_mvendorid | csr_pkt.csr_marchid | csr_pkt.csr_mimpid | csr_pkt.csr_mhartid | csr_pkt.csr_mdseac | csr_pkt.csr_meihap)) ) + io.dec_csr_legal_d := ( io.dec_csr_any_unq_d &valid_csr & ~(io.dec_csr_wen_unq_d & (csr_pkt.csr_mvendorid | csr_pkt.csr_marchid | csr_pkt.csr_mimpid | csr_pkt.csr_mhartid | csr_pkt.csr_mdseac | csr_pkt.csr_meihap)) ) } trait CSRs{ - val MISA = "h301".U(12.W) - val MVENDORID = "hf11".U(12.W) - val MARCHID = "hf12".U(12.W) - val MIMPID = "hf13".U(12.W) - val MHARTID = "hf14".U(12.W) - val MSTATUS = "h300".U(12.W) - val MTVEC = "h305".U(12.W) - val MIP = "h344".U(12.W) - val MIE = "h304".U(12.W) - val MCYCLEL = "hb00".U(12.W) - val MCYCLEH = "hb80".U(12.W) - val MINSTRETL = "hb02".U(12.W) - val MINSTRETH = "hb82".U(12.W) - val MSCRATCH = "h340".U(12.W) - val MEPC = "h341".U(12.W) - val MCAUSE = "h342".U(12.W) - val MSCAUSE = "h7ff".U(12.W) - val MTVAL = "h343".U(12.W) - val MCGC = "h7f8".U(12.W) - val MFDC = "h7f9".U(12.W) - val MCPC = "h7c2".U(12.W) - val MRAC = "h7c0".U(12.W) - val MDEAU = "hbc0".U(12.W) - val MDSEAC = "hfc0".U(12.W) - val MPMC = "h7c6".U(12.W) - val MICECT = "h7f0".U(12.W) - val MICCMECT = "h7f1".U(12.W) - val MDCCMECT = "h7f2".U(12.W) - val MFDHT = "h7ce".U(12.W) - val MFDHS = "h7cf".U(12.W) - val MEIVT = "hbc8".U(12.W) - val MEIHAP = "hfc8".U(12.W) - val MEICURPL = "hbcc".U(12.W) - val MEICIDPL = "hbcb".U(12.W) - val MEICPCT = "hbca".U(12.W) - val MEIPT = "hbc9".U(12.W) - val DCSR = "h7b0".U(12.W) - val DPC = "h7b1".U(12.W) - val DICAWICS = "h7c8".U(12.W) - val DICAD0 = "h7c9".U(12.W) - val DICAD0H = "h7cc".U(12.W) - val DICAD1 = "h7ca".U(12.W) - val DICAGO = "h7cb".U(12.W) - val MTSEL = "h7a0".U(12.W) - val MTDATA1 = "h7a1".U(12.W) - val MTDATA2 = "h7a2".U(12.W) - val MHPMC3 = "hB03".U(12.W) - val MHPMC3H = "hB83".U(12.W) - val MHPMC4 = "hB04".U(12.W) - val MHPMC4H = "hB84".U(12.W) - val MHPMC5 = "hB05".U(12.W) - val MHPMC5H = "hB85".U(12.W) - val MHPMC6 = "hB06".U(12.W) - val MHPMC6H = "hB86".U(12.W) - val MHPME3 = "h323".U(12.W) - val MHPME4 = "h324".U(12.W) - val MHPME5 = "h325".U(12.W) - val MHPME6 = "h326".U(12.W) - val MCOUNTINHIBIT = "h320".U(12.W) - val MSTATUS_MIE = 0.U - val MIP_MCEIP = 5.U - val MIP_MITIP0 = 4.U - val MIP_MITIP1 = 3.U - val MIP_MEIP = 2 - val MIP_MTIP = 1 - val MIP_MSIP = 0 - val MIE_MCEIE = 5 - val MIE_MITIE0 = 4 - val MIE_MITIE1 = 3 - val MIE_MEIE = 2 - val MIE_MTIE = 1 - val MIE_MSIE = 0 - val DCSR_EBREAKM = 15 - val DCSR_STEPIE = 11 - val DCSR_STOPC = 10 - val DCSR_STEP = 2 - val MTDATA1_DMODE = 9 - val MTDATA1_SEL = 7 - val MTDATA1_ACTION = 6 - val MTDATA1_CHAIN = 5 - val MTDATA1_MATCH = 4 - val MTDATA1_M_ENABLED = 3 - val MTDATA1_EXE = 2 - val MTDATA1_ST = 1 - val MTDATA1_LD = 0 - val MHPME_NOEVENT = 0.U - val MHPME_CLK_ACTIVE = 1.U // OOP - out of pipe - val MHPME_ICACHE_HIT = 2.U // OOP - val MHPME_ICACHE_MISS = 3.U // OOP - val MHPME_INST_COMMIT = 4.U - val MHPME_INST_COMMIT_16B = 5.U - val MHPME_INST_COMMIT_32B = 6.U - val MHPME_INST_ALIGNED = 7.U // OOP - val MHPME_INST_DECODED = 8.U // OOP - val MHPME_INST_MUL = 9.U - val MHPME_INST_DIV = 10.U - val MHPME_INST_LOAD = 11.U - val MHPME_INST_STORE = 12.U - val MHPME_INST_MALOAD = 13.U - val MHPME_INST_MASTORE = 14.U - val MHPME_INST_ALU = 15.U - val MHPME_INST_CSRREAD = 16.U - val MHPME_INST_CSRRW = 17.U - val MHPME_INST_CSRWRITE = 18.U - val MHPME_INST_EBREAK = 19.U - val MHPME_INST_ECALL = 20.U - val MHPME_INST_FENCE = 21.U - val MHPME_INST_FENCEI = 22.U - val MHPME_INST_MRET = 23.U - val MHPME_INST_BRANCH = 24.U - val MHPME_BRANCH_MP = 25.U - val MHPME_BRANCH_TAKEN = 26.U - val MHPME_BRANCH_NOTP = 27.U - val MHPME_FETCH_STALL = 28.U // OOP - val MHPME_ALGNR_STALL = 29.U // OOP - val MHPME_DECODE_STALL = 30.U // OOP - val MHPME_POSTSYNC_STALL = 31.U // OOP - val MHPME_PRESYNC_STALL = 32.U // OOP - val MHPME_LSU_SB_WB_STALL = 34.U // OOP - val MHPME_DMA_DCCM_STALL = 35.U // OOP - val MHPME_DMA_ICCM_STALL = 36.U // OOP - val MHPME_EXC_TAKEN = 37.U - val MHPME_TIMER_INT_TAKEN = 38.U - val MHPME_EXT_INT_TAKEN = 39.U - val MHPME_FLUSH_LOWER = 40.U - val MHPME_BR_ERROR = 41.U - val MHPME_IBUS_TRANS = 42.U // OOP - val MHPME_DBUS_TRANS = 43.U // OOP - val MHPME_DBUS_MA_TRANS = 44.U // OOP - val MHPME_IBUS_ERROR = 45.U // OOP - val MHPME_DBUS_ERROR = 46.U // OOP - val MHPME_IBUS_STALL = 47.U // OOP - val MHPME_DBUS_STALL = 48.U // OOP - val MHPME_INT_DISABLED = 49.U // OOP - val MHPME_INT_STALLED = 50.U // OOP - val MHPME_INST_BITMANIP = 54.U - val MHPME_DBUS_LOAD = 55.U - val MHPME_DBUS_STORE = 56.U - // Counts even during sleep state - val MHPME_SLEEP_CYC = 512.U // OOP - val MHPME_DMA_READ_ALL = 513.U // OOP - val MHPME_DMA_WRITE_ALL = 514.U // OOP - val MHPME_DMA_READ_DCCM = 515.U // OOP - val MHPME_DMA_WRITE_DCCM = 516.U // OOP + val MISA = "h301".U(12.W) + val MVENDORID = "hf11".U(12.W) + val MARCHID = "hf12".U(12.W) + val MIMPID = "hf13".U(12.W) + val MHARTID = "hf14".U(12.W) + val MSTATUS = "h300".U(12.W) + val MTVEC = "h305".U(12.W) + val MIP = "h344".U(12.W) + val MIE = "h304".U(12.W) + val MCYCLEL = "hb00".U(12.W) + val MCYCLEH = "hb80".U(12.W) + val MINSTRETL = "hb02".U(12.W) + val MINSTRETH = "hb82".U(12.W) + val MSCRATCH = "h340".U(12.W) + val MEPC = "h341".U(12.W) + val MCAUSE = "h342".U(12.W) + val MSCAUSE = "h7ff".U(12.W) + val MTVAL = "h343".U(12.W) + val MCGC = "h7f8".U(12.W) + val MFDC = "h7f9".U(12.W) + val MCPC = "h7c2".U(12.W) + val MRAC = "h7c0".U(12.W) + val MDEAU = "hbc0".U(12.W) + val MDSEAC = "hfc0".U(12.W) + val MPMC = "h7c6".U(12.W) + val MICECT = "h7f0".U(12.W) + val MICCMECT = "h7f1".U(12.W) + val MDCCMECT = "h7f2".U(12.W) + val MFDHT = "h7ce".U(12.W) + val MFDHS = "h7cf".U(12.W) + val MEIVT = "hbc8".U(12.W) + val MEIHAP = "hfc8".U(12.W) + val MEICURPL = "hbcc".U(12.W) + val MEICIDPL = "hbcb".U(12.W) + val MEICPCT = "hbca".U(12.W) + val MEIPT = "hbc9".U(12.W) + val DCSR = "h7b0".U(12.W) + val DPC = "h7b1".U(12.W) + val DICAWICS = "h7c8".U(12.W) + val DICAD0 = "h7c9".U(12.W) + val DICAD0H = "h7cc".U(12.W) + val DICAD1 = "h7ca".U(12.W) + val DICAGO = "h7cb".U(12.W) + val MTSEL = "h7a0".U(12.W) + val MTDATA1 = "h7a1".U(12.W) + val MTDATA2 = "h7a2".U(12.W) + val MHPMC3 = "hB03".U(12.W) + val MHPMC3H = "hB83".U(12.W) + val MHPMC4 = "hB04".U(12.W) + val MHPMC4H = "hB84".U(12.W) + val MHPMC5 = "hB05".U(12.W) + val MHPMC5H = "hB85".U(12.W) + val MHPMC6 = "hB06".U(12.W) + val MHPMC6H = "hB86".U(12.W) + val MHPME3 = "h323".U(12.W) + val MHPME4 = "h324".U(12.W) + val MHPME5 = "h325".U(12.W) + val MHPME6 = "h326".U(12.W) + val MCOUNTINHIBIT = "h320".U(12.W) + val MSTATUS_MIE = 0.U + val MIP_MCEIP = 5.U + val MIP_MITIP0 = 4.U + val MIP_MITIP1 = 3.U + val MIP_MEIP = 2 + val MIP_MTIP = 1 + val MIP_MSIP = 0 + val MIE_MCEIE = 5 + val MIE_MITIE0 = 4 + val MIE_MITIE1 = 3 + val MIE_MEIE = 2 + val MIE_MTIE = 1 + val MIE_MSIE = 0 + val DCSR_EBREAKM = 15 + val DCSR_STEPIE = 11 + val DCSR_STOPC = 10 + val DCSR_STEP = 2 + val MTDATA1_DMODE = 9 + val MTDATA1_SEL = 7 + val MTDATA1_ACTION = 6 + val MTDATA1_CHAIN = 5 + val MTDATA1_MATCH = 4 + val MTDATA1_M_ENABLED = 3 + val MTDATA1_EXE = 2 + val MTDATA1_ST = 1 + val MTDATA1_LD = 0 + val MHPME_NOEVENT = 0.U + val MHPME_CLK_ACTIVE = 1.U // OOP - out of pipe + val MHPME_ICACHE_HIT = 2.U // OOP + val MHPME_ICACHE_MISS = 3.U // OOP + val MHPME_INST_COMMIT = 4.U + val MHPME_INST_COMMIT_16B = 5.U + val MHPME_INST_COMMIT_32B = 6.U + val MHPME_INST_ALIGNED = 7.U // OOP + val MHPME_INST_DECODED = 8.U // OOP + val MHPME_INST_MUL = 9.U + val MHPME_INST_DIV = 10.U + val MHPME_INST_LOAD = 11.U + val MHPME_INST_STORE = 12.U + val MHPME_INST_MALOAD = 13.U + val MHPME_INST_MASTORE = 14.U + val MHPME_INST_ALU = 15.U + val MHPME_INST_CSRREAD = 16.U + val MHPME_INST_CSRRW = 17.U + val MHPME_INST_CSRWRITE = 18.U + val MHPME_INST_EBREAK = 19.U + val MHPME_INST_ECALL = 20.U + val MHPME_INST_FENCE = 21.U + val MHPME_INST_FENCEI = 22.U + val MHPME_INST_MRET = 23.U + val MHPME_INST_BRANCH = 24.U + val MHPME_BRANCH_MP = 25.U + val MHPME_BRANCH_TAKEN = 26.U + val MHPME_BRANCH_NOTP = 27.U + val MHPME_FETCH_STALL = 28.U // OOP + // val MHPME_ALGNR_STALL = 29.U // OOP + val MHPME_DECODE_STALL = 30.U // OOP + val MHPME_POSTSYNC_STALL = 31.U // OOP + val MHPME_PRESYNC_STALL = 32.U // OOP + val MHPME_LSU_SB_WB_STALL = 34.U // OOP + val MHPME_DMA_DCCM_STALL = 35.U // OOP + val MHPME_DMA_ICCM_STALL = 36.U // OOP + val MHPME_EXC_TAKEN = 37.U + val MHPME_TIMER_INT_TAKEN = 38.U + val MHPME_EXT_INT_TAKEN = 39.U + val MHPME_FLUSH_LOWER = 40.U + val MHPME_BR_ERROR = 41.U + val MHPME_IBUS_TRANS = 42.U // OOP + val MHPME_DBUS_TRANS = 43.U // OOP + val MHPME_DBUS_MA_TRANS = 44.U // OOP + val MHPME_IBUS_ERROR = 45.U // OOP + val MHPME_DBUS_ERROR = 46.U // OOP + val MHPME_IBUS_STALL = 47.U // OOP + val MHPME_DBUS_STALL = 48.U // OOP + val MHPME_INT_DISABLED = 49.U // OOP + val MHPME_INT_STALLED = 50.U // OOP + val MHPME_INST_BITMANIP = 54.U + val MHPME_DBUS_LOAD = 55.U + val MHPME_DBUS_STORE = 56.U + // Counts even during sleep state + val MHPME_SLEEP_CYC = 512.U // OOP + val MHPME_DMA_READ_ALL = 513.U // OOP + val MHPME_DMA_WRITE_ALL = 514.U // OOP + val MHPME_DMA_READ_DCCM = 515.U // OOP + val MHPME_DMA_WRITE_DCCM = 516.U // OOP + + } class CSR_IO extends Bundle with lib { - val free_clk = Input(Clock()) - val active_clk = Input(Clock()) - val scan_mode = Input(Bool()) - val dec_csr_wrdata_r = Input(UInt(32.W)) - val dec_csr_wraddr_r = Input(UInt(12.W)) - val dec_csr_rdaddr_d = Input(UInt(12.W)) - val dec_csr_wen_unq_d = Input(UInt(1.W)) - val dec_i0_decode_d = Input(UInt(1.W)) - val dec_tlu_ic_diag_pkt = Output(new cache_debug_pkt_t) - val ifu_ic_debug_rd_data_valid = Input(UInt(1.W)) - val trigger_pkt_any = Output(Vec(4, new trigger_pkt_t)) - val ifu_pmu_bus_trxn = Input(UInt(1.W)) - val dma_iccm_stall_any = Input(UInt(1.W)) - val dma_dccm_stall_any = Input(UInt(1.W)) - val lsu_store_stall_any = Input(UInt(1.W)) - val dec_pmu_presync_stall = Input(UInt(1.W)) - val dec_pmu_postsync_stall = Input(UInt(1.W)) - val dec_pmu_decode_stall = Input(UInt(1.W)) - val ifu_pmu_fetch_stall = Input(UInt(1.W)) - val dec_tlu_packet_r = Input(new trap_pkt_t) - val exu_pmu_i0_br_ataken = Input(UInt(1.W)) - val exu_pmu_i0_br_misp = Input(UInt(1.W)) - val dec_pmu_instr_decoded = Input(UInt(1.W)) - val ifu_pmu_instr_aligned = Input(UInt(1.W)) - val exu_pmu_i0_pc4 = Input(UInt(1.W)) - val ifu_pmu_ic_miss = Input(UInt(1.W)) - val ifu_pmu_ic_hit = Input(UInt(1.W)) - val dec_tlu_int_valid_wb1 = Output(UInt(1.W)) - val dec_tlu_i0_exc_valid_wb1 = Output(UInt(1.W)) - val dec_tlu_i0_valid_wb1 = Output(UInt(1.W)) - val dec_csr_wen_r = Input(UInt(1.W)) - val dec_tlu_mtval_wb1 = Output(UInt(32.W)) - val dec_tlu_exc_cause_wb1 = Output(UInt(5.W)) - val dec_tlu_perfcnt0 = Output(UInt(1.W)) - val dec_tlu_perfcnt1 = Output(UInt(1.W)) - val dec_tlu_perfcnt2 = Output(UInt(1.W)) - val dec_tlu_perfcnt3 = Output(UInt(1.W)) - val dec_tlu_dbg_halted = Input(UInt(1.W)) - val dma_pmu_dccm_write = Input(UInt(1.W)) - val dma_pmu_dccm_read = Input(UInt(1.W)) - val dma_pmu_any_write = Input(UInt(1.W)) - val dma_pmu_any_read = Input(UInt(1.W)) - val lsu_pmu_bus_busy = Input(UInt(1.W)) - val dec_tlu_i0_pc_r = Input(UInt(31.W)) - val dec_tlu_i0_valid_r = Input(UInt(1.W)) - val dec_csr_stall_int_ff = Input(UInt(1.W)) - val dec_csr_any_unq_d = Input(UInt(1.W)) - val dec_tlu_misc_clk_override = Output(UInt(1.W)) - val dec_tlu_dec_clk_override = Output(UInt(1.W)) - val dec_tlu_ifu_clk_override = Output(UInt(1.W)) - val dec_tlu_lsu_clk_override = Output(UInt(1.W)) - val dec_tlu_bus_clk_override = Output(UInt(1.W)) - val dec_tlu_pic_clk_override = Output(UInt(1.W)) - val dec_tlu_dccm_clk_override = Output(UInt(1.W)) - val dec_tlu_icm_clk_override = Output(UInt(1.W)) - val dec_csr_rddata_d = Output(UInt(32.W)) - val dec_tlu_pipelining_disable = Output(UInt(1.W)) - val dec_tlu_wr_pause_r = Output(UInt(1.W)) - val ifu_pmu_bus_busy = Input(UInt(1.W)) - val lsu_pmu_bus_error = Input(UInt(1.W)) - val ifu_pmu_bus_error = Input(UInt(1.W)) - val lsu_pmu_bus_misaligned = Input(UInt(1.W)) - val lsu_pmu_bus_trxn = Input(UInt(1.W)) - val ifu_ic_debug_rd_data = Input(UInt(71.W)) - val dec_tlu_meipt = Output(UInt(4.W)) - val pic_pl = Input(UInt(4.W)) - val dec_tlu_meicurpl = Output(UInt(4.W)) - val dec_tlu_meihap = Output(UInt(30.W)) - val pic_claimid = Input(UInt(8.W)) - val iccm_dma_sb_error = Input(UInt(1.W)) - val lsu_imprecise_error_addr_any = Input(UInt(32.W)) - val lsu_imprecise_error_load_any = Input(UInt(1.W)) - val lsu_imprecise_error_store_any = Input(UInt(1.W)) - val dec_tlu_mrac_ff = Output(UInt(32.W)) - val dec_tlu_wb_coalescing_disable = Output(UInt(1.W)) - val dec_tlu_bpred_disable = Output(UInt(1.W)) - val dec_tlu_sideeffect_posted_disable = Output(UInt(1.W)) - val dec_tlu_core_ecc_disable = Output(UInt(1.W)) - val dec_tlu_external_ldfwd_disable = Output(UInt(1.W)) - val dec_tlu_dma_qos_prty = Output(UInt(3.W)) - val dec_illegal_inst = Input(UInt(32.W)) - val lsu_error_pkt_r = Flipped(Valid(new lsu_error_pkt_t))// lsu precise exception/error packet - val mexintpend = Input(UInt(1.W)) - val exu_npc_r = Input(UInt(31.W)) - val mpc_reset_run_req = Input(UInt(1.W)) - val rst_vec = Input(UInt(31.W)) - val core_id = Input(UInt(28.W)) - val dec_timer_rddata_d = Input(UInt(32.W)) - val dec_timer_read_d = Input(UInt(1.W)) - - - ////////////////////////////////////////////////// - val dec_csr_wen_r_mod = Output(UInt(1.W)) - val rfpc_i0_r = Input(UInt(1.W)) - val i0_trigger_hit_r = Input(UInt(1.W)) - val fw_halt_req = Output(UInt(1.W)) - val mstatus = Output(UInt(2.W)) - val exc_or_int_valid_r = Input(UInt(1.W)) // remove this after - val mret_r = Input(UInt(1.W)) - val mstatus_mie_ns = Output(UInt(1.W)) - val dcsr_single_step_running_f = Input(UInt(1.W)) - val dcsr = Output(UInt(16.W)) - val mtvec = Output(UInt(31.W)) - val mip = Output(UInt(6.W)) - val dec_timer_t0_pulse = Input(UInt(1.W)) - val dec_timer_t1_pulse = Input(UInt(1.W)) - val timer_int_sync = Input(UInt(1.W)) - val soft_int_sync = Input(UInt(1.W)) - val mie_ns = Output(UInt(6.W)) - val csr_wr_clk: Clock = Input(Clock()) // remove after - val ebreak_to_debug_mode_r = Input(UInt(1.W)) - val dec_tlu_pmu_fw_halted = Input(UInt(1.W)) - val lsu_fir_error = Input(UInt(2.W)) - val npc_r = Output(UInt(31.W)) - val tlu_flush_lower_r_d1 = Input(UInt(1.W)) - val dec_tlu_flush_noredir_r_d1 = Input(UInt(1.W)) - val tlu_flush_path_r_d1 = Input(UInt(31.W)) - val npc_r_d1 = Output(UInt(31.W)) - val reset_delayed = Input(UInt(1.W)) - val mepc = Output(UInt(31.W)) - val interrupt_valid_r = Input(UInt(1.W)) - val i0_exception_valid_r = Input(UInt(1.W)) //delete after - val lsu_exc_valid_r = Input(UInt(1.W)) - val mepc_trigger_hit_sel_pc_r = Input(UInt(1.W)) //delete after - val e4e5_int_clk = Input(Clock()) //delete after - val lsu_i0_exc_r = Input(UInt(1.W)) - val inst_acc_r = Input(UInt(1.W)) - val inst_acc_second_r = Input(UInt(1.W)) - val take_nmi = Input(UInt(1.W)) - val lsu_error_pkt_addr_r = Input(UInt(32.W)) - val exc_cause_r = Input(UInt(5.W)) - val i0_valid_wb = Input(UInt(1.W)) - val exc_or_int_valid_r_d1 = Input(UInt(1.W)) - val interrupt_valid_r_d1 = Input(UInt(1.W)) - val clk_override = Input(UInt(1.W)) - val i0_exception_valid_r_d1 = Input(UInt(1.W)) - val lsu_i0_exc_r_d1 = Input(UInt(1.W)) - val exc_cause_wb = Input(UInt(5.W)) - val nmi_lsu_store_type = Input(UInt(1.W)) - val nmi_lsu_load_type = Input(UInt(1.W)) - val tlu_i0_commit_cmt = Input(UInt(1.W)) - val ebreak_r = Input(UInt(1.W)) - val ecall_r = Input(UInt(1.W)) - val illegal_r = Input(UInt(1.W)) - val mdseac_locked_ns = Output(UInt(1.W)) - val mdseac_locked_f = Input(UInt(1.W)) - val nmi_int_detected_f = Input(UInt(1.W)) - val internal_dbg_halt_mode_f2 = Input(UInt(1.W)) - val ext_int_freeze_d1 = Input(UInt(1.W)) - val ic_perr_r_d1 = Input(UInt(1.W)) - val iccm_sbecc_r_d1 = Input(UInt(1.W)) - val lsu_single_ecc_error_r_d1 = Input(UInt(1.W)) - val ifu_miss_state_idle_f = Input(UInt(1.W)) - val lsu_idle_any_f = Input(UInt(1.W)) - val dbg_tlu_halted_f = Input(UInt(1.W)) - val dbg_tlu_halted = Input(UInt(1.W)) - val debug_halt_req_f = Input(UInt(1.W)) - val force_halt = Output(UInt(1.W)) - val take_ext_int_start = Input(UInt(1.W)) - val trigger_hit_dmode_r_d1 = Input(UInt(1.W)) - val trigger_hit_r_d1 = Input(UInt(1.W)) - val dcsr_single_step_done_f = Input(UInt(1.W)) - val ebreak_to_debug_mode_r_d1 = Input(UInt(1.W)) - val debug_halt_req = Input(UInt(1.W)) - val allow_dbg_halt_csr_write = Input(UInt(1.W)) - val internal_dbg_halt_mode_f = Input(UInt(1.W)) - val enter_debug_halt_req = Input(UInt(1.W)) - val internal_dbg_halt_mode = Input(UInt(1.W)) - val request_debug_mode_done = Input(UInt(1.W)) - val request_debug_mode_r = Input(UInt(1.W)) - val dpc = Output(UInt(31.W)) - val update_hit_bit_r = Input(UInt(4.W)) - val take_timer_int = Input(UInt(1.W)) - val take_int_timer0_int = Input(UInt(1.W)) - val take_int_timer1_int = Input(UInt(1.W)) - val take_ext_int = Input(UInt(1.W)) - val tlu_flush_lower_r = Input(UInt(1.W)) - val dec_tlu_br0_error_r = Input(UInt(1.W)) - val dec_tlu_br0_start_error_r = Input(UInt(1.W)) - val lsu_pmu_load_external_r = Input(UInt(1.W)) - val lsu_pmu_store_external_r = Input(UInt(1.W)) - val csr_pkt = Input(new dec_tlu_csr_pkt) - val mtdata1_t = Output(Vec(4,UInt(10.W))) + val free_l2clk = Input(Clock()) + val free_clk = Input(Clock()) + // val active_clk = Input(Clock()) + val scan_mode = Input(Bool()) + val dec_csr_wrdata_r = Input(UInt(32.W)) + val dec_csr_wraddr_r = Input(UInt(12.W)) + val dec_csr_rdaddr_d = Input(UInt(12.W)) + val dec_csr_wen_unq_d = Input(UInt(1.W)) + val dec_i0_decode_d = Input(UInt(1.W)) + val dec_tlu_ic_diag_pkt = Output(new cache_debug_pkt_t) + val ifu_ic_debug_rd_data_valid = Input(UInt(1.W)) + val trigger_pkt_any = Output(Vec(4, new trigger_pkt_t)) + val ifu_pmu_bus_trxn = Input(UInt(1.W)) + val dma_iccm_stall_any = Input(UInt(1.W)) + val dma_dccm_stall_any = Input(UInt(1.W)) + val lsu_store_stall_any = Input(UInt(1.W)) + val dec_pmu_presync_stall = Input(UInt(1.W)) + val dec_pmu_postsync_stall = Input(UInt(1.W)) + val dec_pmu_decode_stall = Input(UInt(1.W)) + val ifu_pmu_fetch_stall = Input(UInt(1.W)) + val dec_tlu_packet_r = Input(new trap_pkt_t) + val exu_pmu_i0_br_ataken = Input(UInt(1.W)) + val exu_pmu_i0_br_misp = Input(UInt(1.W)) + val dec_pmu_instr_decoded = Input(UInt(1.W)) + val ifu_pmu_instr_aligned = Input(UInt(1.W)) + val exu_pmu_i0_pc4 = Input(UInt(1.W)) + val ifu_pmu_ic_miss = Input(UInt(1.W)) + val ifu_pmu_ic_hit = Input(UInt(1.W)) + val dec_tlu_int_valid_wb1 = Output(UInt(1.W)) + val dec_tlu_i0_exc_valid_wb1 = Output(UInt(1.W)) + val dec_tlu_i0_valid_wb1 = Output(UInt(1.W)) + val dec_csr_wen_r = Input(UInt(1.W)) + //val dec_tlu_force_halt = Output(UInt(1.W)) + //val dec_tlu_flush_extint = Output(UInt(1.W)) + val dec_tlu_mtval_wb1 = Output(UInt(32.W)) + val dec_tlu_exc_cause_wb1 = Output(UInt(5.W)) + val dec_tlu_perfcnt0 = Output(UInt(1.W)) + val dec_tlu_perfcnt1 = Output(UInt(1.W)) + val dec_tlu_perfcnt2 = Output(UInt(1.W)) + val dec_tlu_perfcnt3 = Output(UInt(1.W)) + val dec_tlu_dbg_halted = Input(UInt(1.W)) + val dma_pmu_dccm_write = Input(UInt(1.W)) + val dma_pmu_dccm_read = Input(UInt(1.W)) + val dma_pmu_any_write = Input(UInt(1.W)) + val dma_pmu_any_read = Input(UInt(1.W)) + val lsu_pmu_bus_busy = Input(UInt(1.W)) + val dec_tlu_i0_pc_r = Input(UInt(31.W)) + val dec_tlu_i0_valid_r = Input(UInt(1.W)) + val dec_csr_stall_int_ff = Input(UInt(1.W)) + val dec_csr_any_unq_d = Input(UInt(1.W)) + val dec_tlu_misc_clk_override = Output(UInt(1.W)) + val dec_tlu_picio_clk_override = Output(UInt(1.W)) + val dec_tlu_dec_clk_override = Output(UInt(1.W)) + val dec_tlu_ifu_clk_override = Output(UInt(1.W)) + val dec_tlu_lsu_clk_override = Output(UInt(1.W)) + val dec_tlu_bus_clk_override = Output(UInt(1.W)) + val dec_tlu_pic_clk_override = Output(UInt(1.W)) + val dec_tlu_dccm_clk_override = Output(UInt(1.W)) + val dec_tlu_icm_clk_override = Output(UInt(1.W)) + //val dec_csr_legal_d = Output(UInt(1.W)) + val dec_csr_rddata_d = Output(UInt(32.W)) + //val dec_tlu_postsync_d = Output(UInt(1.W)) + //val dec_tlu_presync_d = Output(UInt(1.W)) + //val dec_tlu_flush_pause_r = Output(UInt(1.W)) + //val dec_tlu_flush_lower_r = Output(UInt(1.W)) + //val dec_tlu_i0_kill_writeb_r = Output(UInt(1.W)) + //val dec_tlu_flush_lower_wb = Output(UInt(1.W)) + //val dec_tlu_i0_kill_writeb_wb = Output(UInt(1.W)) + // val dec_tlu_flush_leak_one_wb = Output(UInt(1.W)) + //val dec_tlu_debug_stall = Output(UInt(1.W)) + val dec_tlu_pipelining_disable = Output(UInt(1.W)) + val dec_tlu_wr_pause_r = Output(UInt(1.W)) + val ifu_pmu_bus_busy = Input(UInt(1.W)) + val lsu_pmu_bus_error = Input(UInt(1.W)) + val ifu_pmu_bus_error = Input(UInt(1.W)) + val lsu_pmu_bus_misaligned = Input(UInt(1.W)) + val lsu_pmu_bus_trxn = Input(UInt(1.W)) + val ifu_ic_debug_rd_data = Input(UInt(71.W)) + val dec_tlu_meipt = Output(UInt(4.W)) + val pic_pl = Input(UInt(4.W)) + val dec_tlu_meicurpl = Output(UInt(4.W)) + val dec_tlu_meihap = Output(UInt(30.W)) + val pic_claimid = Input(UInt(8.W)) + val iccm_dma_sb_error = Input(UInt(1.W)) + val lsu_imprecise_error_addr_any = Input(UInt(32.W)) + val lsu_imprecise_error_load_any = Input(UInt(1.W)) + val lsu_imprecise_error_store_any = Input(UInt(1.W)) + val dec_tlu_mrac_ff = Output(UInt(32.W)) + val dec_tlu_wb_coalescing_disable = Output(UInt(1.W)) + val dec_tlu_bpred_disable = Output(UInt(1.W)) + val dec_tlu_sideeffect_posted_disable = Output(UInt(1.W)) + val dec_tlu_core_ecc_disable = Output(UInt(1.W)) + val dec_tlu_external_ldfwd_disable = Output(UInt(1.W)) + val dec_tlu_dma_qos_prty = Output(UInt(3.W)) + val dec_tlu_trace_disable = Output(Bool()) + val dec_illegal_inst = Input(UInt(32.W)) + val lsu_error_pkt_r = Flipped(Valid(new lsu_error_pkt_t))// lsu precise exception/error packet + val mexintpend = Input(UInt(1.W)) + val exu_npc_r = Input(UInt(31.W)) + val mpc_reset_run_req = Input(UInt(1.W)) + val rst_vec = Input(UInt(31.W)) + val core_id = Input(UInt(28.W)) + val dec_timer_rddata_d = Input(UInt(32.W)) + val dec_timer_read_d = Input(UInt(1.W)) + + + ////////////////////////////////////////////////// + val dec_csr_wen_r_mod = Output(UInt(1.W)) + val rfpc_i0_r = Input(UInt(1.W)) + val i0_trigger_hit_r = Input(UInt(1.W)) + val fw_halt_req = Output(UInt(1.W)) + val mstatus = Output(UInt(2.W)) + val exc_or_int_valid_r = Input(UInt(1.W)) // remove this after + val mret_r = Input(UInt(1.W)) + val mstatus_mie_ns = Output(UInt(1.W)) + val dcsr_single_step_running_f = Input(UInt(1.W)) + val dcsr = Output(UInt(16.W)) + val mtvec = Output(UInt(31.W)) + val mip = Output(UInt(6.W)) + val dec_timer_t0_pulse = Input(UInt(1.W)) + val dec_timer_t1_pulse = Input(UInt(1.W)) + val timer_int_sync = Input(UInt(1.W)) + val soft_int_sync = Input(UInt(1.W)) + val mie_ns = Output(UInt(6.W)) + val csr_wr_clk: Clock = Input(Clock()) // remove after + val ebreak_to_debug_mode_r = Input(UInt(1.W)) + val dec_tlu_pmu_fw_halted = Input(UInt(1.W)) + val lsu_fir_error = Input(UInt(2.W)) + val npc_r = Output(UInt(31.W)) + val tlu_flush_lower_r_d1 = Input(UInt(1.W)) + val dec_tlu_flush_noredir_r_d1 = Input(UInt(1.W)) + val tlu_flush_path_r_d1 = Input(UInt(31.W)) + val npc_r_d1 = Output(UInt(31.W)) + val reset_delayed = Input(UInt(1.W)) + val mepc = Output(UInt(31.W)) + val interrupt_valid_r = Input(UInt(1.W)) + val i0_exception_valid_r = Input(UInt(1.W)) //delete after + val lsu_exc_valid_r = Input(UInt(1.W)) + val mepc_trigger_hit_sel_pc_r = Input(UInt(1.W)) //delete after + val lsu_single_ecc_error_r = Input(UInt(1.W)) + val e4e5_int_clk = Input(Clock()) //delete after + val lsu_i0_exc_r = Input(UInt(1.W)) + val inst_acc_r = Input(UInt(1.W)) + val inst_acc_second_r = Input(UInt(1.W)) + val take_nmi = Input(UInt(1.W)) + val lsu_error_pkt_addr_r = Input(UInt(32.W)) + val exc_cause_r = Input(UInt(5.W)) + val i0_valid_wb = Input(UInt(1.W)) + val exc_or_int_valid_r_d1 = Input(UInt(1.W)) + val interrupt_valid_r_d1 = Input(Bool()) + val clk_override = Input(UInt(1.W)) + val i0_exception_valid_r_d1 = Input(UInt(1.W)) + + val exc_cause_wb = Input(UInt(5.W)) + val nmi_lsu_store_type = Input(UInt(1.W)) + val nmi_lsu_load_type = Input(UInt(1.W)) + val tlu_i0_commit_cmt = Input(UInt(1.W)) + val ebreak_r = Input(UInt(1.W)) + val ecall_r = Input(UInt(1.W)) + val illegal_r = Input(UInt(1.W)) + val mdseac_locked_ns = Output(UInt(1.W)) + val mdseac_locked_f = Output(UInt(1.W)) + val nmi_int_detected_f = Input(UInt(1.W)) + val internal_dbg_halt_mode_f2 = Input(UInt(1.W)) + val ext_int_freeze = Input(UInt(1.W)) + val ext_int_freeze_d1 = Output(UInt(1.W)) + val take_ext_int_start_d1 = Output(UInt(1.W)) + val take_ext_int_start_d2 = Output(UInt(1.W)) + val take_ext_int_start_d3 = Output(UInt(1.W)) + val ic_perr_r = Input(UInt(1.W)) + val iccm_sbecc_r = Input(UInt(1.W)) + + val ifu_miss_state_idle_f = Input(UInt(1.W)) + val lsu_idle_any_f = Input(UInt(1.W)) + val dbg_tlu_halted_f = Input(UInt(1.W)) + val dbg_tlu_halted = Input(UInt(1.W)) + val debug_halt_req_f = Input(UInt(1.W)) + val force_halt = Output(UInt(1.W)) + val take_ext_int_start = Input(UInt(1.W)) + val trigger_hit_dmode_r_d1 = Input(UInt(1.W)) + val trigger_hit_r_d1 = Input(UInt(1.W)) + val dcsr_single_step_done_f = Input(UInt(1.W)) + val ebreak_to_debug_mode_r_d1 = Input(UInt(1.W)) + val debug_halt_req = Input(UInt(1.W)) + val allow_dbg_halt_csr_write = Input(UInt(1.W)) + val internal_dbg_halt_mode_f = Input(UInt(1.W)) + val enter_debug_halt_req = Input(UInt(1.W)) + val internal_dbg_halt_mode = Input(UInt(1.W)) + val request_debug_mode_done = Input(UInt(1.W)) + val request_debug_mode_r = Input(UInt(1.W)) + val dpc = Output(UInt(31.W)) + val update_hit_bit_r = Input(UInt(4.W)) + val take_timer_int = Input(UInt(1.W)) + val take_int_timer0_int = Input(UInt(1.W)) + val take_int_timer1_int = Input(UInt(1.W)) + val take_ext_int = Input(UInt(1.W)) + val tlu_flush_lower_r = Input(UInt(1.W)) + val dec_tlu_br0_error_r = Input(UInt(1.W)) + val dec_tlu_br0_start_error_r = Input(UInt(1.W)) + val lsu_pmu_load_external_r = Input(UInt(1.W)) + val lsu_pmu_store_external_r = Input(UInt(1.W)) + val csr_pkt = Input(new dec_tlu_csr_pkt) + val mtdata1_t = Output(Vec(4,UInt(10.W))) + val trigger_enabled = Input(UInt(4.W)) + val lsu_exc_valid_r_d1 = Output(UInt(1.W)) } class csr_tlu extends Module with lib with CSRs with RequireAsyncReset { - val io = IO(new CSR_IO) - -////////////////////////////////wires/////////////////////////////// - val miccme_ce_req = WireInit(UInt(1.W),0.U) - val mice_ce_req = WireInit(UInt(1.W),0.U) - val mdccme_ce_req = WireInit(UInt(1.W),0.U) - val pc_r_d1 = WireInit(UInt(31.W),0.U) - val mpmc_b_ns = WireInit(UInt(1.W),0.U) - val mpmc_b = WireInit(UInt(1.W),0.U) -val wr_mcycleh_r = WireInit(UInt(1.W), 0.U) - val mcycleh = WireInit(UInt(32.W),0.U) - val minstretl_inc = WireInit(UInt(33.W),0.U) - val wr_minstreth_r = WireInit(UInt(1.W),0.U) - val minstretl = WireInit(UInt(32.W),0.U) - val minstreth_inc = WireInit(UInt(32.W),0.U) - val minstreth = WireInit(UInt(32.W),0.U) - val mfdc_ns = WireInit(UInt(15.W),0.U) - val mfdc_int = WireInit(UInt(15.W),0.U) - val mhpmc6_incr = WireInit(UInt(64.W),0.U) - val mhpmc5_incr = WireInit(UInt(64.W),0.U) - val mhpmc4_incr = WireInit(UInt(64.W),0.U) - val perfcnt_halted = WireInit(UInt(1.W),0.U) - val mhpmc3_incr = WireInit(UInt(64.W),0.U) - val mhpme_vec = Wire(Vec(4,UInt(10.W))) - val mtdata2_t = Wire(Vec(4,UInt(32.W))) - val wr_meicpct_r = WireInit(UInt(1.W),0.U) - val force_halt_ctr_f = WireInit(UInt(32.W),0.U) - val mdccmect_inc = WireInit(UInt(27.W),0.U) - val miccmect_inc = WireInit(UInt(27.W),0.U) - val micect_inc = WireInit(UInt(27.W),0.U) - val mdseac_en = WireInit(UInt(1.W),0.U) - val mie = WireInit(UInt(6.W),0.U) - val mcyclel = WireInit(UInt(32.W),0.U) - val mscratch = WireInit(UInt(32.W),0.U) - val mcause = WireInit(UInt(32.W),0.U) - val mscause = WireInit(UInt(4.W),0.U) - val mtval = WireInit(UInt(32.W),0.U) - val meicurpl = WireInit(UInt(4.W),0.U) - val meicidpl = WireInit(UInt(4.W),0.U) - val meipt = WireInit(UInt(4.W),0.U) - val mfdc = WireInit(UInt(19.W),0.U) - val mtsel = WireInit(UInt(2.W),0.U) - val micect = WireInit(UInt(32.W),0.U) - val miccmect = WireInit(UInt(32.W),0.U) - val mdccmect = WireInit(UInt(32.W),0.U) - val mhpmc3h = WireInit(UInt(32.W),0.U) - val mhpmc3 = WireInit(UInt(32.W),0.U) - val mhpmc4h = WireInit(UInt(32.W),0.U) - val mhpmc4 = WireInit(UInt(32.W),0.U) - val mhpmc5h = WireInit(UInt(32.W),0.U) - val mhpmc5 = WireInit(UInt(32.W),0.U) - val mhpmc6h = WireInit(UInt(32.W),0.U) - val mhpmc6 = WireInit(UInt(32.W),0.U) - val mhpme3 = WireInit(UInt(10.W),0.U) - val mhpme4 = WireInit(UInt(10.W),0.U) - val mhpme5 = WireInit(UInt(10.W),0.U) - val mhpme6 = WireInit(UInt(10.W),0.U) - val mfdht = WireInit(UInt(6.W),0.U) - val mfdhs = WireInit(UInt(2.W),0.U) - val mcountinhibit = WireInit(UInt(7.W),0.U) - val mpmc = WireInit(UInt(1.W),0.U) - val dicad1 = WireInit(UInt(32.W),0.U) -///////////////////////////////////////////////////////////////////////// - //---------------------------------------------------------------------- - // - // CSRs - // - //---------------------------------------------------------------------- - - // ---------------------------------------------------------------------- - // MSTATUS (RW) - // [12:11] MPP : Prior priv level, always 2'b11, not flopped - // [7] MPIE : Int enable previous [1] - // [3] MIE : Int enable [0] - - //When executing a MRET instruction, supposing MPP holds the value 3, MIE - //is set to MPIE; the privilege mode is changed to 3; MPIE is set to 1; and MPP is set to 3 - - io.dec_csr_wen_r_mod := io.dec_csr_wen_r & !io.i0_trigger_hit_r & !io.rfpc_i0_r - val wr_mstatus_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MSTATUS) - - // set this even if we don't go to fwhalt due to debug halt. We committed the inst, so ... - val set_mie_pmu_fw_halt = !mpmc_b_ns & io.fw_halt_req - - val mstatus_ns = Mux1H(Seq( - (!wr_mstatus_r & io.exc_or_int_valid_r).asBool -> Cat(io.mstatus(MSTATUS_MIE),0.U), - (wr_mstatus_r & io.exc_or_int_valid_r).asBool -> Cat(io.dec_csr_wrdata_r(3),0.U), - (io.mret_r & !io.exc_or_int_valid_r).asBool -> Cat(1.U, io.mstatus(1)), - (set_mie_pmu_fw_halt).asBool -> Cat(io.mstatus(1), 1.U), - (wr_mstatus_r & !io.exc_or_int_valid_r).asBool -> Cat(io.dec_csr_wrdata_r(7), io.dec_csr_wrdata_r(3)), - (!wr_mstatus_r & !io.exc_or_int_valid_r & !io.mret_r & !set_mie_pmu_fw_halt).asBool -> io.mstatus)) - - // gate MIE if we are single stepping and DCSR[STEPIE] is off - io.mstatus_mie_ns := io.mstatus(MSTATUS_MIE) & (~io.dcsr_single_step_running_f | io.dcsr(DCSR_STEPIE)) - io.mstatus := withClock(io.free_clk) { - RegNext(mstatus_ns,0.U) - } - - // ---------------------------------------------------------------------- - // MTVEC (RW) - // [31:2] BASE : Trap vector base address - // [1] - Reserved, not implemented, reads zero - // [0] MODE : 0 = Direct, 1 = Asyncs are vectored to BASE + (4 * CAUSE) - - val wr_mtvec_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTVEC) - val mtvec_ns = Cat(io.dec_csr_wrdata_r(31, 2), io.dec_csr_wrdata_r(0)) - io.mtvec := rvdffe(mtvec_ns, wr_mtvec_r.asBool, clock, io.scan_mode) - - // ---------------------------------------------------------------------- - // MIP (RW) - // - // [30] MCEIP : (RO) M-Mode Correctable Error interrupt pending - // [29] MITIP0 : (RO) M-Mode Internal Timer0 interrupt pending - // [28] MITIP1 : (RO) M-Mode Internal Timer1 interrupt pending - // [11] MEIP : (RO) M-Mode external interrupt pending - // [7] MTIP : (RO) M-Mode timer interrupt pending - // [3] MSIP : (RO) M-Mode software interrupt pending - - val ce_int = (mdccme_ce_req | miccme_ce_req | mice_ce_req) - - val mip_ns = Cat(ce_int, io.dec_timer_t0_pulse, io.dec_timer_t1_pulse, io.mexintpend, io.timer_int_sync, io.soft_int_sync) - io.mip := withClock(io.free_clk) { - RegNext(mip_ns,0.U) - } - - // ---------------------------------------------------------------------- - // MIE (RW) - // [30] MCEIE : (RO) M-Mode Correctable Error interrupt enable - // [29] MITIE0 : (RO) M-Mode Internal Timer0 interrupt enable - // [28] MITIE1 : (RO) M-Mode Internal Timer1 interrupt enable - // [11] MEIE : (RW) M-Mode external interrupt enable - // [7] MTIE : (RW) M-Mode timer interrupt enable - // [3] MSIE : (RW) M-Mode software interrupt enable - - val wr_mie_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MIE) - io.mie_ns := Mux(wr_mie_r.asBool, Cat(io.dec_csr_wrdata_r(30, 28), io.dec_csr_wrdata_r(11), io.dec_csr_wrdata_r(7), io.dec_csr_wrdata_r(3)), mie) - mie := withClock(io.csr_wr_clk) { - RegNext(io.mie_ns,0.U) - } - - // ---------------------------------------------------------------------- - // MCYCLEL (RW) - // [31:0] : Lower Cycle count - - val kill_ebreak_count_r = io.ebreak_to_debug_mode_r & io.dcsr(DCSR_STOPC) - - val wr_mcyclel_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCYCLEL) - - val mcyclel_cout_in = ~(kill_ebreak_count_r | (io.dec_tlu_dbg_halted & io.dcsr(DCSR_STOPC)) | io.dec_tlu_pmu_fw_halted | mcountinhibit(0)) - - - val mcyclel_inc = WireInit(UInt(33.W),0.U) - mcyclel_inc := mcyclel +& Cat(0.U(31.W), mcyclel_cout_in) - val mcyclel_ns = Mux(wr_mcyclel_r.asBool, io.dec_csr_wrdata_r, mcyclel_inc(31,0)) - val mcyclel_cout = mcyclel_inc(32).asBool - mcyclel := rvdffe(mcyclel_ns, (wr_mcyclel_r | mcyclel_cout_in.asUInt).asBool, clock, io.scan_mode) - val mcyclel_cout_f = withClock(io.free_clk) {RegNext((mcyclel_cout & !wr_mcycleh_r),0.U)} - // ---------------------------------------------------------------------- - // MCYCLEH (RW) - // [63:32] : Higher Cycle count - // Chained with mcyclel. Note: mcyclel overflow due to a mcycleh write gets ignored. + val io = IO(new CSR_IO) + + ////////////////////////////////wires/////////////////////////////// + // val lsu_single_ecc_error_r_d1 = WireInit(UInt(1.W),0.U) + // val lsu_i0_exc_r_d1 = WireInit(UInt(1.W),0.U) + val miccme_ce_req = WireInit(UInt(1.W),0.U) + val mice_ce_req = WireInit(UInt(1.W),0.U) + val mdccme_ce_req = WireInit(UInt(1.W),0.U) + val pc_r_d1 = WireInit(UInt(31.W),0.U) + val mpmc_b_ns = WireInit(UInt(1.W),0.U) + val mpmc_b = WireInit(UInt(1.W),0.U) + // val wr_mcycleh_r = WireInit(UInt(1.W), 0.U) + val mcycleh = WireInit(UInt(32.W),0.U) + // val minstretl_inc = WireInit(UInt(33.W),0.U) + val wr_minstreth_r = WireInit(UInt(1.W),0.U) + val minstretl = WireInit(UInt(32.W),0.U) + // val minstreth_inc = WireInit(UInt(32.W),0.U) + val minstreth = WireInit(UInt(32.W),0.U) + val mfdc_ns = WireInit(UInt(16.W),0.U) + val mfdc_int = WireInit(UInt(16.W),0.U) + // val mhpmc6_incr = WireInit(UInt(64.W),0.U) + // val mhpmc5_incr = WireInit(UInt(64.W),0.U) + // val mhpmc4_incr = WireInit(UInt(64.W),0.U) + // val perfcnt_halted = WireInit(UInt(1.W),0.U) + // val mhpmc3_incr = WireInit(UInt(64.W),0.U) + val mhpme_vec = Wire(Vec(4,UInt(10.W))) + val mtdata2_t = Wire(Vec(4,UInt(32.W))) + val wr_meicpct_r = WireInit(UInt(1.W),0.U) + val force_halt_ctr_f = WireInit(UInt(32.W),0.U) + val mdccmect_inc = WireInit(UInt(27.W),0.U) + val miccmect_inc = WireInit(UInt(27.W),0.U) + // val fw_halted = WireInit(UInt(1.W),0.U) + val micect_inc = WireInit(UInt(27.W),0.U) + val mdseac_en = WireInit(UInt(1.W),0.U) + val mie = WireInit(UInt(6.W),0.U) + val mcyclel = WireInit(UInt(32.W),0.U) + val mscratch = WireInit(UInt(32.W),0.U) + val mcause = WireInit(UInt(32.W),0.U) + val mscause = WireInit(UInt(4.W),0.U) + val mtval = WireInit(UInt(32.W),0.U) + val meicurpl = WireInit(UInt(4.W),0.U) + // val meicidpl = WireInit(UInt(4.W),0.U) + val meipt = WireInit(UInt(4.W),0.U) + val mfdc = WireInit(UInt(19.W),0.U) + val mtsel = WireInit(UInt(2.W),0.U) + val micect = WireInit(UInt(32.W),0.U) + val miccmect = WireInit(UInt(32.W),0.U) + val mdccmect = WireInit(UInt(32.W),0.U) + // val mhpmc3h = WireInit(UInt(32.W),0.U) + // val mhpmc3 = WireInit(UInt(32.W),0.U) + // val mhpmc4h = WireInit(UInt(32.W),0.U) + // val mhpmc4 = WireInit(UInt(32.W),0.U) + // val mhpmc5h = WireInit(UInt(32.W),0.U) + // val mhpmc5 = WireInit(UInt(32.W),0.U) + // val mhpmc6h = WireInit(UInt(32.W),0.U) + // val mhpmc6 = WireInit(UInt(32.W),0.U) + // val mhpme3 = WireInit(UInt(10.W),0.U) + // val mhpme4 = WireInit(UInt(10.W),0.U) + // val mhpme5 = WireInit(UInt(10.W),0.U) + // val mhpme6 = WireInit(UInt(10.W),0.U) + val mfdht = WireInit(UInt(6.W),0.U) + val mfdhs = WireInit(UInt(2.W),0.U) + val mcountinhibit = WireInit(UInt(7.W),0.U) + val mpmc = WireInit(UInt(1.W),0.U) + val dicad1 = WireInit(UInt(32.W),0.U) + ///////////////////////////////////////////////////////////////////////// + + val perfmux_flop = Module(new perf_mux_and_flops) + val perf_csrs = Module(new perf_csr) + //---------------------------------------------------------------------- + // + // CSRs + // + //---------------------------------------------------------------------- + + // ---------------------------------------------------------------------- + // MSTATUS (RW) + // [12:11] MPP : Prior priv level, always 2'b11, not flopped + // [7] MPIE : Int enable previous [1] + // [3] MIE : Int enable [0] + + //When executing a MRET instruction, supposing MPP holds the value 3, MIE + //is set to MPIE; the privilege mode is changed to 3; MPIE is set to 1; and MPP is set to 3 + + io.dec_csr_wen_r_mod := io.dec_csr_wen_r & !io.i0_trigger_hit_r & !io.rfpc_i0_r + val wr_mstatus_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MSTATUS) + + // set this even if we don't go to fwhalt due to debug halt. We committed the inst, so ... + val set_mie_pmu_fw_halt = !mpmc_b_ns & io.fw_halt_req + + val mstatus_ns = Mux1H(Seq( + (!wr_mstatus_r & io.exc_or_int_valid_r).asBool -> Cat(io.mstatus(MSTATUS_MIE),0.U), + (wr_mstatus_r & io.exc_or_int_valid_r).asBool -> Cat(io.dec_csr_wrdata_r(3),0.U), + (io.mret_r & !io.exc_or_int_valid_r).asBool -> Cat(1.U, io.mstatus(1)), + (set_mie_pmu_fw_halt).asBool -> Cat(io.mstatus(1), 1.U), + (wr_mstatus_r & !io.exc_or_int_valid_r).asBool -> Cat(io.dec_csr_wrdata_r(7), io.dec_csr_wrdata_r(3)), + (!wr_mstatus_r & !io.exc_or_int_valid_r & !io.mret_r & !set_mie_pmu_fw_halt).asBool -> io.mstatus)) + + + + // gate MIE if we are single stepping and DCSR[STEPIE] is off + io.mstatus_mie_ns := io.mstatus(MSTATUS_MIE) & (~io.dcsr_single_step_running_f | io.dcsr(DCSR_STEPIE)) + // io.mstatus := withClock(io.free_clk) { + // RegNext(mstatus_ns,0.U) + // } + + // ---------------------------------------------------------------------- + // MTVEC (RW) + // [31:2] BASE : Trap vector base address + // [1] - Reserved, not implemented, reads zero + // [0] MODE : 0 = Direct, 1 = Asyncs are vectored to BASE + (4 * CAUSE) + + val wr_mtvec_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTVEC) + val mtvec_ns = Cat(io.dec_csr_wrdata_r(31, 2), io.dec_csr_wrdata_r(0)) + io.mtvec := rvdffe(mtvec_ns, wr_mtvec_r.asBool, clock, io.scan_mode) + + // ---------------------------------------------------------------------- + // MIP (RW) + // + // [30] MCEIP : (RO) M-Mode Correctable Error interrupt pending + // [29] MITIP0 : (RO) M-Mode Internal Timer0 interrupt pending + // [28] MITIP1 : (RO) M-Mode Internal Timer1 interrupt pending + // [11] MEIP : (RO) M-Mode external interrupt pending + // [7] MTIP : (RO) M-Mode timer interrupt pending + // [3] MSIP : (RO) M-Mode software interrupt pending + + val ce_int = (mdccme_ce_req | miccme_ce_req | mice_ce_req) + + val mip_ns = Cat(ce_int, io.dec_timer_t0_pulse, io.dec_timer_t1_pulse, io.mexintpend, io.timer_int_sync, io.soft_int_sync) + // io.mip := withClock(io.free_clk) { + // RegNext(mip_ns,0.U) + // } + + // ---------------------------------------------------------------------- + // MIE (RW) + // [30] MCEIE : (RO) M-Mode Correctable Error interrupt enable + // [29] MITIE0 : (RO) M-Mode Internal Timer0 interrupt enable + // [28] MITIE1 : (RO) M-Mode Internal Timer1 interrupt enable + // [11] MEIE : (RW) M-Mode external interrupt enable + // [7] MTIE : (RW) M-Mode timer interrupt enable + // [3] MSIE : (RW) M-Mode software interrupt enable + + val wr_mie_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MIE) + io.mie_ns := Mux(wr_mie_r.asBool, Cat(io.dec_csr_wrdata_r(30, 28), io.dec_csr_wrdata_r(11), io.dec_csr_wrdata_r(7), io.dec_csr_wrdata_r(3)), mie) + mie := withClock(io.csr_wr_clk) { + RegNext(io.mie_ns,0.U) + } + // ---------------------------------------------------------------------- + // MCYCLEL (RW) + // [31:0] : Lower Cycle count + + val kill_ebreak_count_r = io.ebreak_to_debug_mode_r & io.dcsr(DCSR_STOPC) + + val wr_mcyclel_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCYCLEL) + + val mcyclel_cout_in = ~(kill_ebreak_count_r | (io.dec_tlu_dbg_halted & io.dcsr(DCSR_STOPC)) | io.dec_tlu_pmu_fw_halted | mcountinhibit(0)) + // val mcyclel_cout_f = WireInit(Bool()) + // val mcyclel_inc = WireInit(UInt(32.W),0.U) + val mcyclel_inc1 = WireInit(UInt(9.W),0.U) + val mcyclel_inc2 = WireInit(UInt(25.W),0.U) + mcyclel_inc1 := mcyclel(7,0) +& Cat(0.U(7.W), 1.U(1.W)) + mcyclel_inc2 := mcyclel(31,8) +& Cat(0.U(23.W), mcyclel_inc1(8)) + val mcyclel_inc = Cat(mcyclel_inc2(23,0),mcyclel_inc1(7,0)) + val mcyclel_ns = Mux(wr_mcyclel_r.asBool, io.dec_csr_wrdata_r, mcyclel_inc(31,0)) + val mcyclel_cout = mcyclel_inc2(24).asBool + mcyclel := Cat(rvdffe(mcyclel_ns(31,8), (wr_mcyclel_r | (mcyclel_inc1(8) & mcyclel_cout_in.asUInt).asBool), io.free_l2clk, io.scan_mode),rvdffe(mcyclel_ns(7,0),( wr_mcyclel_r | mcyclel_cout_in.asUInt).asBool, io.free_l2clk, io.scan_mode)) + // val mcyclel_cout_f = withClock(io.free_clk) {RegNext((mcyclel_cout & !wr_mcycleh_r),0.U)} + // ---------------------------------------------------------------------- + // MCYCLEH (RW) + // [63:32] : Higher Cycle count + // Chained with mcyclel. Note: mcyclel overflow due to a mcycleh write gets ignored. + + val wr_mcycleh_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCYCLEH) + + val mcycleh_inc = mcycleh + Cat(0.U(31.W), perfmux_flop.io.mcyclel_cout_f) + val mcycleh_ns = Mux(wr_mcycleh_r.asBool, io.dec_csr_wrdata_r, mcycleh_inc) - wr_mcycleh_r := io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCYCLEH) + mcycleh := rvdffe(mcycleh_ns, (wr_mcycleh_r | perfmux_flop.io.mcyclel_cout_f).asBool, io.free_l2clk, io.scan_mode) - val mcycleh_inc = mcycleh + Cat(0.U(31.W), mcyclel_cout_f) - val mcycleh_ns = Mux(wr_mcycleh_r.asBool, io.dec_csr_wrdata_r, mcycleh_inc) - mcycleh := rvdffe(mcycleh_ns, (wr_mcycleh_r | mcyclel_cout_f).asBool, clock, io.scan_mode) + // ---------------------------------------------------------------------- + // MINSTRETL (RW) + // [31:0] : Lower Instruction retired count + // From the spec "Some CSRs, such as the instructions retired counter, instret, may be modified as side effects + // of instruction execution. In these cases, if a CSR access instruction reads a CSR, it reads the + // value prior to the execution of the instruction. If a CSR access instruction writes a CSR, the + // update occurs after the execution of the instruction. In particular, a value written to instret by + // one instruction will be the value read by the following instruction (i.e., the increment of instret + // caused by the first instruction retiring happens before the write of the new value)." + + + val i0_valid_no_ebreak_ecall_r = (io.dec_tlu_i0_valid_r & !(io.ebreak_r | io.ecall_r | io.ebreak_to_debug_mode_r | io.illegal_r | mcountinhibit(2))).asBool() + + val wr_minstretl_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MINSTRETL) + // val minstretl_inc = WireInit(UInt(32.W)) + val minstretl_inc1 = WireInit(UInt(9.W),0.U) + val minstretl_inc2 = WireInit(UInt(25.W),0.U) + minstretl_inc1 := minstretl(7,0) +& Cat(0.U(7.W), 1.U(1.W)) + minstretl_inc2 := minstretl(31,8) +& Cat(0.U(23.W), minstretl_inc1(8)) + val minstretl_cout = minstretl_inc2(24) + val minstretl_inc = Cat(minstretl_inc2(23,0),minstretl_inc1(7,0)) + val minstret_enable = (i0_valid_no_ebreak_ecall_r & io.tlu_i0_commit_cmt) | wr_minstretl_r + val minstretl_cout_ns = minstretl_cout & !wr_minstreth_r & i0_valid_no_ebreak_ecall_r & !io.dec_tlu_dbg_halted + + + val minstretl_ns = Mux(wr_minstretl_r.asBool, io.dec_csr_wrdata_r , minstretl_inc(31,0)) + + minstretl := Cat(rvdffe(minstretl_ns(31,8),wr_minstretl_r | (minstretl_inc1(8) & minstret_enable),clock,io.scan_mode),rvdffe(minstretl_ns(7,0),minstret_enable.asBool,clock,io.scan_mode)) + // val minstret_enable_f = withClock(io.free_clk){RegNext(minstret_enable,0.U)} + // val minstretl_cout_f = withClock(io.free_clk){RegNext((minstretl_cout & ~wr_minstreth_r),0.U)} + val minstretl_read = minstretl + // ---------------------------------------------------------------------- + // MINSTRETH (RW) + // [63:32] : Higher Instret count + // Chained with minstretl. Note: minstretl overflow due to a minstreth write gets ignored. - // ---------------------------------------------------------------------- - // MINSTRETL (RW) - // [31:0] : Lower Instruction retired count - // From the spec "Some CSRs, such as the instructions retired counter, instret, may be modified as side effects - // of instruction execution. In these cases, if a CSR access instruction reads a CSR, it reads the - // value prior to the execution of the instruction. If a CSR access instruction writes a CSR, the - // update occurs after the execution of the instruction. In particular, a value written to instret by - // one instruction will be the value read by the following instruction (i.e., the increment of instret - // caused by the first instruction retiring happens before the write of the new value)." - - - val i0_valid_no_ebreak_ecall_r = io.tlu_i0_commit_cmt & ~(io.ebreak_r | io.ecall_r | io.ebreak_to_debug_mode_r | io.illegal_r | mcountinhibit(2)).asBool - - val wr_minstretl_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MINSTRETL) - - minstretl_inc := minstretl +& Cat(0.U(31.W),i0_valid_no_ebreak_ecall_r) - val minstretl_cout = minstretl_inc(32) - val minstret_enable = (i0_valid_no_ebreak_ecall_r | wr_minstretl_r).asBool + wr_minstreth_r := (io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MINSTRETH)).asBool - val minstretl_ns = Mux(wr_minstretl_r.asBool, io.dec_csr_wrdata_r , minstretl_inc(31,0)) - minstretl := rvdffe(minstretl_ns,minstret_enable.asBool,clock,io.scan_mode) - val minstret_enable_f = withClock(io.free_clk){RegNext(minstret_enable,0.U)} - val minstretl_cout_f = withClock(io.free_clk){RegNext((minstretl_cout & ~wr_minstreth_r),0.U)} + //val minstret_enable_f = WireInit(Bool()) + // val minstretl_cout_f = WireInit(Bool()) + val minstreth_inc = minstreth + Cat(0.U(31.W), perfmux_flop.io.minstretl_cout_f ) + val minstreth_ns = Mux(wr_minstreth_r.asBool, io.dec_csr_wrdata_r, minstreth_inc) - val minstretl_read = minstretl - // ---------------------------------------------------------------------- - // MINSTRETH (RW) - // [63:32] : Higher Instret count - // Chained with minstretl. Note: minstretl overflow due to a minstreth write gets ignored. + minstreth := rvdffe(minstreth_ns, (perfmux_flop.io.minstret_enable_f & perfmux_flop.io.minstretl_cout_f ) | wr_minstreth_r, clock, io.scan_mode) - wr_minstreth_r := (io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MINSTRETH)).asBool + val minstreth_read = minstreth_inc + // ---------------------------------------------------------------------- + // mscratch (RW) + // [31:0] : Scratch register - minstreth_inc := minstreth + Cat(0.U(31.W), minstretl_cout_f) - val minstreth_ns = Mux(wr_minstreth_r.asBool, io.dec_csr_wrdata_r, minstreth_inc) + val wr_mscratch_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MSCRATCH) - minstreth := rvdffe(minstreth_ns, (minstret_enable_f | wr_minstreth_r).asBool, clock, io.scan_mode) - - val minstreth_read = minstreth_inc + mscratch := rvdffe(io.dec_csr_wrdata_r,wr_mscratch_r.asBool,clock,io.scan_mode) - // ---------------------------------------------------------------------- - // mscratch (RW) - // [31:0] : Scratch register - val wr_mscratch_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MSCRATCH) + // ---------------------------meivt------------------------------------------- + // MEPC (RW) + // [31:1] : Exception PC - mscratch := rvdffe(io.dec_csr_wrdata_r,wr_mscratch_r.asBool,clock,io.scan_mode) + // NPC + val sel_exu_npc_r = !io.dec_tlu_dbg_halted & !io.tlu_flush_lower_r_d1 & io.dec_tlu_i0_valid_r + val sel_flush_npc_r = !io.dec_tlu_dbg_halted & io.tlu_flush_lower_r_d1 & !io.dec_tlu_flush_noredir_r_d1 + val sel_hold_npc_r = !sel_exu_npc_r & !sel_flush_npc_r - // ---------------------------meivt------------------------------------------- - // MEPC (RW) - // [31:1] : Exception PC + io.npc_r := Mux1H(Seq( + sel_exu_npc_r.asBool -> io.exu_npc_r, + (!io.mpc_reset_run_req & io.reset_delayed).asBool -> io.rst_vec, // init to reset vector for mpc halt on reset case + sel_flush_npc_r.asBool -> io.tlu_flush_path_r_d1, + sel_hold_npc_r.asBool -> io.npc_r_d1 )) - // NPC + io.npc_r_d1 := rvdffpcie(io.npc_r,(sel_exu_npc_r | sel_flush_npc_r | io.reset_delayed).asBool,reset.asAsyncReset(),clock,io.scan_mode) + // PC has to be captured for exceptions and interrupts. For MRET, we could execute it and then take an + // interrupt before the next instruction. + val pc0_valid_r = (!io.dec_tlu_dbg_halted & io.dec_tlu_i0_valid_r).asBool - val sel_exu_npc_r = !io.dec_tlu_dbg_halted & !io.tlu_flush_lower_r_d1 & io.dec_tlu_i0_valid_r - val sel_flush_npc_r = !io.dec_tlu_dbg_halted & io.tlu_flush_lower_r_d1 & !io.dec_tlu_flush_noredir_r_d1 - val sel_hold_npc_r = !sel_exu_npc_r & !sel_flush_npc_r + val pc_r = Mux1H( Seq( + pc0_valid_r -> io.dec_tlu_i0_pc_r, + ~pc0_valid_r -> pc_r_d1 )) - io.npc_r := Mux1H(Seq( - sel_exu_npc_r.asBool -> io.exu_npc_r, - (!io.mpc_reset_run_req & io.reset_delayed).asBool -> io.rst_vec, // init to reset vector for mpc halt on reset case - sel_flush_npc_r.asBool -> io.tlu_flush_path_r_d1, - sel_hold_npc_r.asBool -> io.npc_r_d1 )) + pc_r_d1 := rvdffpcie(pc_r, pc0_valid_r,reset.asAsyncReset(), clock, io.scan_mode) - io.npc_r_d1 := rvdffe(io.npc_r,(sel_exu_npc_r | sel_flush_npc_r | io.reset_delayed).asBool,clock,io.scan_mode) - // PC has to be captured for exceptions and interrupts. For MRET, we could execute it and then take an - // interrupt before the next instruction. - val pc0_valid_r = (!io.dec_tlu_dbg_halted & io.dec_tlu_i0_valid_r).asBool + val wr_mepc_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEPC) - val pc_r = Mux1H( Seq( - pc0_valid_r -> io.dec_tlu_i0_pc_r, - ~pc0_valid_r -> pc_r_d1 )) + val mepc_ns = Mux1H( Seq( + (io.i0_exception_valid_r | io.lsu_exc_valid_r | io.mepc_trigger_hit_sel_pc_r).asBool -> pc_r, + (io.interrupt_valid_r).asBool -> io.npc_r, + (wr_mepc_r & !io.exc_or_int_valid_r).asBool -> io.dec_csr_wrdata_r(31,1), + (!wr_mepc_r & !io.exc_or_int_valid_r).asBool -> io.mepc) ) - pc_r_d1 := rvdffe(pc_r, pc0_valid_r, clock, io.scan_mode) + io.mepc := rvdffe(mepc_ns,io.i0_exception_valid_r | io.lsu_exc_valid_r | io.mepc_trigger_hit_sel_pc_r | io.interrupt_valid_r | wr_mepc_r,clock, io.scan_mode)//withClock(io.e4e5_int_clk){RegNext(mepc_ns,0.U)} - val wr_mepc_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEPC) - val mepc_ns = Mux1H( Seq( - (io.i0_exception_valid_r | io.lsu_exc_valid_r | io.mepc_trigger_hit_sel_pc_r).asBool -> pc_r, - (io.interrupt_valid_r).asBool -> io.npc_r, - (wr_mepc_r & !io.exc_or_int_valid_r).asBool -> io.dec_csr_wrdata_r(31,1), - (!wr_mepc_r & !io.exc_or_int_valid_r).asBool -> io.mepc) ) - io.mepc := withClock(io.e4e5_int_clk){RegNext(mepc_ns,0.U)} + // ---------------------------------------------------------------------- + // MCAUSE (RW) + // [31:0] : Exception Cause + val wr_mcause_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCAUSE) + val mcause_sel_nmi_store = io.exc_or_int_valid_r & io.take_nmi & io.nmi_lsu_store_type + val mcause_sel_nmi_load = io.exc_or_int_valid_r & io.take_nmi & io.nmi_lsu_load_type + val mcause_sel_nmi_ext =io.exc_or_int_valid_r & io.take_nmi & io.take_ext_int_start_d3 & io.lsu_fir_error.orR & !io.nmi_int_detected_f + + // FIR value decoder + // 0 –no error + // 1 –uncorrectable ecc => f000_1000 + // 2 –dccm region access error => f000_1001 + // 3 –non dccm region access error => f000_1002 + val mcause_fir_error_type = Cat(io.lsu_fir_error.andR, (io.lsu_fir_error(1) & ~io.lsu_fir_error(0))) + + val mcause_ns = Mux1H(Seq( + mcause_sel_nmi_store.asBool -> "hf000_0000".U(32.W), + mcause_sel_nmi_load.asBool -> "hf000_0001".U(32.W), + mcause_sel_nmi_ext.asBool -> Cat("hf000_100".U(28.W), 0.U(2.W), mcause_fir_error_type), + (io.exc_or_int_valid_r & !io.take_nmi).asBool -> Cat(io.interrupt_valid_r, 0.U(26.W), io.exc_cause_r), + (wr_mcause_r & !io.exc_or_int_valid_r).asBool -> io.dec_csr_wrdata_r, + (!wr_mcause_r & !io.exc_or_int_valid_r).asBool -> mcause) ) + + mcause := rvdffe(mcause_ns,io.exc_or_int_valid_r | wr_mcause_r,clock,io.scan_mode)//withClock(io.e4e5_int_clk){RegNext(mcause_ns,0.U)} + + + // ---------------------------------------------------------------------- + // MSCAUSE (RW) + // [2:0] : Secondary exception Cause + + val wr_mscause_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MSCAUSE) + + val ifu_mscause = Mux((io.dec_tlu_packet_r.icaf_type === 0.U(2.W)), "b1001".U, Cat(0.U(2.W) , io.dec_tlu_packet_r.icaf_type)) + + val mscause_type = Mux1H( Seq( + io.lsu_i0_exc_r.asBool -> io.lsu_error_pkt_r.bits.mscause, + io.i0_trigger_hit_r.asBool -> "b0001".U(4.W), + io.ebreak_r.asBool -> "b0010".U(4.W), + io.inst_acc_r.asBool -> ifu_mscause )) + + + val mscause_ns = Mux1H( Seq( + (io.exc_or_int_valid_r).asBool -> mscause_type, + (wr_mscause_r & !io.exc_or_int_valid_r).asBool -> io.dec_csr_wrdata_r(3,0), + (!wr_mscause_r & !io.exc_or_int_valid_r).asBool -> mscause)) + + mscause := withClock(io.e4e5_int_clk){RegNext(mscause_ns,0.U)} + + // ---------------------------------------------------------------------- + // MTVAL (RW) + // [31:0] : Exception address if relevant + + + val wr_mtval_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTVAL) + val mtval_capture_pc_r = io.exc_or_int_valid_r & (io.ebreak_r | (io.inst_acc_r & ~io.inst_acc_second_r) | io.mepc_trigger_hit_sel_pc_r) & ~io.take_nmi + val mtval_capture_pc_plus2_r = io.exc_or_int_valid_r & (io.inst_acc_r & io.inst_acc_second_r) & ~io.take_nmi + val mtval_capture_inst_r = io.exc_or_int_valid_r & io.illegal_r & ~io.take_nmi + val mtval_capture_lsu_r = io.exc_or_int_valid_r & io.lsu_exc_valid_r & ~io.take_nmi + val mtval_clear_r = io.exc_or_int_valid_r & ~mtval_capture_pc_r & ~mtval_capture_inst_r & ~mtval_capture_lsu_r & ~io.mepc_trigger_hit_sel_pc_r + + + val mtval_ns = Mux1H(Seq( + (mtval_capture_pc_r).asBool -> Cat(pc_r, 0.U(1.W)), + (mtval_capture_pc_plus2_r).asBool -> Cat(pc_r + 1.U(31.W), 0.U(1.W)), + (mtval_capture_inst_r).asBool -> io.dec_illegal_inst, + (mtval_capture_lsu_r).asBool -> io.lsu_error_pkt_addr_r, + (wr_mtval_r & ~io.interrupt_valid_r.asUInt).asBool -> io.dec_csr_wrdata_r, + (~io.take_nmi & ~wr_mtval_r & ~mtval_capture_pc_r & ~mtval_capture_inst_r & ~mtval_clear_r & ~mtval_capture_lsu_r).asBool -> mtval )) + + mtval := rvdffe(mtval_ns,io.tlu_flush_lower_r | wr_mtval_r,clock,io.scan_mode)// withClock(io.e4e5_int_clk){RegNext(mtval_ns,0.U)} + + + // ---------------------------------------------------------------------- + // MCGC (RW) Clock gating control + // [31:10]: Reserved, reads 0x0 + // [9] : picio_clk_override + // [8] : misc_clk_override + // [7] : dec_clk_override + // [6] : Unused + // [5] : ifu_clk_override + // [4] : lsu_clk_override + // [3] : bus_clk_override + // [2] : pic_clk_override + // [1] : dccm_clk_override + // [0] : icm_clk_override + // + val mcgc_int = WireInit(UInt(10.W),0.U) + val wr_mcgc_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCGC) + val mcgc_ns = Mux(wr_mcgc_r, Cat(~io.dec_csr_wrdata_r(9), io.dec_csr_wrdata_r(8,0)), mcgc_int) + mcgc_int := rvdffe(mcgc_ns,wr_mcgc_r.asBool,clock,io.scan_mode) + val mcgc = Cat(~mcgc_int(9), mcgc_int(8,0)) + io.dec_tlu_picio_clk_override := mcgc(9) + io.dec_tlu_misc_clk_override := mcgc(8) + io.dec_tlu_dec_clk_override := mcgc(7) + io.dec_tlu_ifu_clk_override := mcgc(5) + io.dec_tlu_lsu_clk_override := mcgc(4) + io.dec_tlu_bus_clk_override := mcgc(3) + io.dec_tlu_pic_clk_override := mcgc(2) + io.dec_tlu_dccm_clk_override := mcgc(1) + io.dec_tlu_icm_clk_override := mcgc(0) + + // ---------------------------------------------------------------------- + // MFDC (RW) Feature Disable Control + // [31:19] : Reserved, reads 0x0 + // [18:16] : DMA QoS Prty + // [15:13] : Reserved, reads 0x0 + // [12] : Disable trace + // [11] : Disable external load forwarding + // [10] : Disable dual issue + // [9] : Disable pic multiple ints + // [8] : Disable core ecc + // [7] : Disable secondary alu?s + // [6] : Unused, 0x0 + // [5] : Disable non-blocking loads/divides + // [4] : Disable fast divide + // [3] : Disable branch prediction and return stack + // [2] : Disable write buffer coalescing + // [1] : Disable load misses that bypass the write buffer + // [0] : Disable pipelining - Enable single instruction execution + // + val wr_mfdc_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MFDC) - // ---------------------------------------------------------------------- - // MCAUSE (RW) - // [31:0] : Exception Cause - val wr_mcause_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCAUSE) - val mcause_sel_nmi_store = io.exc_or_int_valid_r & io.take_nmi & io.nmi_lsu_store_type - val mcause_sel_nmi_load = io.exc_or_int_valid_r & io.take_nmi & io.nmi_lsu_load_type - val mcause_sel_nmi_ext = io.exc_or_int_valid_r & io.take_nmi & io.lsu_fir_error.orR - // FIR value decoder - // 0 –no error - // 1 –uncorrectable ecc => f000_1000 - // 2 –dccm region access error => f000_1001 - // 3 –non dccm region access error => f000_1002 - val mcause_fir_error_type = Cat(io.lsu_fir_error.andR, (io.lsu_fir_error(1) & ~io.lsu_fir_error(0))) - - val mcause_ns = Mux1H(Seq( - mcause_sel_nmi_store.asBool -> "hf000_0000".U(32.W), - mcause_sel_nmi_load.asBool -> "hf000_0001".U(32.W), - mcause_sel_nmi_ext.asBool -> Cat("hf000_100".U(28.W), 0.U(2.W), mcause_fir_error_type), - (io.exc_or_int_valid_r & ~io.take_nmi).asBool -> Cat(io.interrupt_valid_r, 0.U(26.W), io.exc_cause_r), - (wr_mcause_r & ~io.exc_or_int_valid_r).asBool -> io.dec_csr_wrdata_r, - (~wr_mcause_r & ~io.exc_or_int_valid_r).asBool -> mcause) ) - mcause := withClock(io.e4e5_int_clk){RegNext(mcause_ns,0.U)} - - - // ---------------------------------------------------------------------- - // MSCAUSE (RW) - // [2:0] : Secondary exception Cause - - val wr_mscause_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MSCAUSE) - - val ifu_mscause = Mux((io.dec_tlu_packet_r.icaf_type === 0.U(2.W)), "b1001".U, Cat(0.U(2.W) , io.dec_tlu_packet_r.icaf_type)) - - val mscause_type = Mux1H( Seq( - io.lsu_i0_exc_r.asBool -> io.lsu_error_pkt_r.bits.mscause, - io.i0_trigger_hit_r.asBool -> "b0001".U, - io.ebreak_r.asBool -> "b0010".U, - io.inst_acc_r.asBool -> ifu_mscause )) - - - val mscause_ns = Mux1H( Seq( - (io.exc_or_int_valid_r).asBool -> mscause_type, - (wr_mscause_r & !io.exc_or_int_valid_r).asBool -> io.dec_csr_wrdata_r(3,0), - (!wr_mscause_r & !io.exc_or_int_valid_r).asBool -> mscause)) - - mscause := withClock(io.e4e5_int_clk){RegNext(mscause_ns,0.U)} - - // ---------------------------------------------------------------------- - // MTVAL (RW) - // [31:0] : Exception address if relevant + mfdc_int := rvdffe(mfdc_ns,wr_mfdc_r.asBool,clock,io.scan_mode) + // rvdffe #(15) mfdc_ff (.*, .en(wr_mfdc_r), .din({mfdc_ns[14:0]}), .dout(mfdc_int[14:0])); + + // flip poweron value of bit 6 for AXI build + if(BUILD_AXI4){ + // flip poweron valid of bit 12 + mfdc_ns := Cat(~io.dec_csr_wrdata_r(18,16),io.dec_csr_wrdata_r(12),io.dec_csr_wrdata_r(11,7), ~io.dec_csr_wrdata_r(6), io.dec_csr_wrdata_r(5,0)) + mfdc := Cat(~mfdc_int(15,13),0.U(3.W),mfdc_int(12), mfdc_int(11,7), ~mfdc_int(6), mfdc_int(5,0)) + } + else { + // flip poweron valid of bit 12 + mfdc_ns := Cat(~io.dec_csr_wrdata_r(18,16),io.dec_csr_wrdata_r(12,0)) + mfdc := Cat(~mfdc_int(15,13),0.U(3.W), mfdc_int(12,0)) + } + - val wr_mtval_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTVAL) - val mtval_capture_pc_r = io.exc_or_int_valid_r & (io.ebreak_r | (io.inst_acc_r & ~io.inst_acc_second_r) | io.mepc_trigger_hit_sel_pc_r) & ~io.take_nmi - val mtval_capture_pc_plus2_r = io.exc_or_int_valid_r & (io.inst_acc_r & io.inst_acc_second_r) & ~io.take_nmi - val mtval_capture_inst_r = io.exc_or_int_valid_r & io.illegal_r & ~io.take_nmi - val mtval_capture_lsu_r = io.exc_or_int_valid_r & io.lsu_exc_valid_r & ~io.take_nmi - val mtval_clear_r = io.exc_or_int_valid_r & ~mtval_capture_pc_r & ~mtval_capture_inst_r & ~mtval_capture_lsu_r & ~io.mepc_trigger_hit_sel_pc_r - - - val mtval_ns = Mux1H(Seq( - (mtval_capture_pc_r).asBool -> Cat(pc_r, 0.U(1.W)), - (mtval_capture_pc_plus2_r).asBool -> Cat(pc_r + 1.U(31.W), 0.U(1.W)), - (mtval_capture_inst_r).asBool -> io.dec_illegal_inst, - (mtval_capture_lsu_r).asBool -> io.lsu_error_pkt_addr_r, - (wr_mtval_r & ~io.interrupt_valid_r.asUInt).asBool -> io.dec_csr_wrdata_r, - (~io.take_nmi & ~wr_mtval_r & ~mtval_capture_pc_r & ~mtval_capture_inst_r & ~mtval_clear_r & ~mtval_capture_lsu_r).asBool -> mtval )) - - mtval := withClock(io.e4e5_int_clk){RegNext(mtval_ns,0.U)} - - // ---------------------------------------------------------------------- - // MCGC (RW) Clock gating control - // [31:9] : Reserved, reads 0x0 - // [8] : misc_clk_override - // [7] : dec_clk_override - // [6] : unused - // [5] : ifu_clk_override - // [4] : lsu_clk_override - // [3] : bus_clk_override - // [2] : pic_clk_override - // [1] : dccm_clk_override - // [0] : icm_clk_override - // - val wr_mcgc_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCGC) - - val mcgc = rvdffe(io.dec_csr_wrdata_r(8,0),wr_mcgc_r.asBool,clock,io.scan_mode) - - io.dec_tlu_misc_clk_override := mcgc(8) - io.dec_tlu_dec_clk_override := mcgc(7) - io.dec_tlu_ifu_clk_override := mcgc(5) - io.dec_tlu_lsu_clk_override := mcgc(4) - io.dec_tlu_bus_clk_override := mcgc(3) - io.dec_tlu_pic_clk_override := mcgc(2) - io.dec_tlu_dccm_clk_override := mcgc(1) - io.dec_tlu_icm_clk_override := mcgc(0) - - // ---------------------------------------------------------------------- - // MFDC (RW) Feature Disable Control - // [31:19] : Reserved, reads 0x0 - // [18:16] : DMA QoS Prty - // [15:12] : Reserved, reads 0x0 - // [11] : Disable external load forwarding - // [10] : Disable dual issue - // [9] : Disable pic multiple ints - // [8] : Disable core ecc - // [7] : Unused, 0x0 - // [6] : Disable Sideeffect lsu posting - // [5:4] : Unused, 0x0 - // [3] : Disable branch prediction and return stack - // [2] : Disable write buffer coalescing - // [1] : Unused, 0x0 - // [0] : Disable pipelining - Enable single instruction execution - // - val wr_mfdc_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MFDC) + io.dec_tlu_dma_qos_prty := mfdc(18,16) + io.dec_tlu_trace_disable := mfdc(12) + io.dec_tlu_external_ldfwd_disable := mfdc(11) + io.dec_tlu_core_ecc_disable := mfdc(8) + io.dec_tlu_sideeffect_posted_disable := mfdc(6) + io.dec_tlu_bpred_disable := mfdc(3) + io.dec_tlu_wb_coalescing_disable := mfdc(2) + io.dec_tlu_pipelining_disable := mfdc(0) + // ---------------------------------------------------------------------- + // MCPC (RW) Pause counter + // [31:0] : Reads 0x0, decs in the wb register in decode_ctl - mfdc_int := rvdffe(mfdc_ns,wr_mfdc_r.asBool,clock,io.scan_mode) -// rvdffe #(15) mfdc_ff (.*, .en(wr_mfdc_r), .din({mfdc_ns[14:0]}), .dout(mfdc_int[14:0])); - if(BUILD_AXI4){ - // flip poweron value of bit 6 for AXI build - mfdc_ns := Cat(~io.dec_csr_wrdata_r(18,16),io.dec_csr_wrdata_r(11,7), ~io.dec_csr_wrdata_r(6), io.dec_csr_wrdata_r(5,0)) - mfdc := Cat(~mfdc_int(14,12),0.U(4.W), mfdc_int(11,7), ~mfdc_int(6), mfdc_int(5,0)) - } - else { - mfdc_ns := Cat(~io.dec_csr_wrdata_r(18,16),io.dec_csr_wrdata_r(11,0)) - mfdc := Cat(~mfdc_int(14,12),0.U(4.W), mfdc_int(11,0)) - } + io.dec_tlu_wr_pause_r := io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCPC) & ~io.interrupt_valid_r & ~io.take_ext_int_start - io.dec_tlu_dma_qos_prty := mfdc(18,16) - io.dec_tlu_external_ldfwd_disable := mfdc(11) - io.dec_tlu_core_ecc_disable := mfdc(8) - io.dec_tlu_sideeffect_posted_disable := mfdc(6) - io.dec_tlu_bpred_disable := mfdc(3) - io.dec_tlu_wb_coalescing_disable := mfdc(2) - io.dec_tlu_pipelining_disable := mfdc(0) + // ---------------------------------------------------------------------- + // MRAC (RW) + // [31:0] : Region Access Control Register, 16 regions, {side_effect, cachable} pairs - // ---------------------------------------------------------------------- - // MCPC (RW) Pause counter - // [31:0] : Reads 0x0, decs in the wb register in decode_ctl + val wr_mrac_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MRAC) + // prevent pairs of 0x11, side_effect and cacheable + val mrac_in = Cat(io.dec_csr_wrdata_r(31), io.dec_csr_wrdata_r(30) & ~io.dec_csr_wrdata_r(31), + io.dec_csr_wrdata_r(29), io.dec_csr_wrdata_r(28) & ~io.dec_csr_wrdata_r(29), + io.dec_csr_wrdata_r(27), io.dec_csr_wrdata_r(26) & ~io.dec_csr_wrdata_r(27), + io.dec_csr_wrdata_r(25), io.dec_csr_wrdata_r(24) & ~io.dec_csr_wrdata_r(25), + io.dec_csr_wrdata_r(23), io.dec_csr_wrdata_r(22) & ~io.dec_csr_wrdata_r(23), + io.dec_csr_wrdata_r(21), io.dec_csr_wrdata_r(20) & ~io.dec_csr_wrdata_r(21), + io.dec_csr_wrdata_r(19), io.dec_csr_wrdata_r(18) & ~io.dec_csr_wrdata_r(19), + io.dec_csr_wrdata_r(17), io.dec_csr_wrdata_r(16) & ~io.dec_csr_wrdata_r(17), + io.dec_csr_wrdata_r(15), io.dec_csr_wrdata_r(14) & ~io.dec_csr_wrdata_r(15), + io.dec_csr_wrdata_r(13), io.dec_csr_wrdata_r(12) & ~io.dec_csr_wrdata_r(13), + io.dec_csr_wrdata_r(11), io.dec_csr_wrdata_r(10) & ~io.dec_csr_wrdata_r(11), + io.dec_csr_wrdata_r(9), io.dec_csr_wrdata_r(8) & ~io.dec_csr_wrdata_r(9), + io.dec_csr_wrdata_r(7), io.dec_csr_wrdata_r(6) & ~io.dec_csr_wrdata_r(7), + io.dec_csr_wrdata_r(5), io.dec_csr_wrdata_r(4) & ~io.dec_csr_wrdata_r(5), + io.dec_csr_wrdata_r(3), io.dec_csr_wrdata_r(2) & ~io.dec_csr_wrdata_r(3), + io.dec_csr_wrdata_r(1), io.dec_csr_wrdata_r(0) & ~io.dec_csr_wrdata_r(1)) - io.dec_tlu_wr_pause_r := io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCPC) & ~io.interrupt_valid_r & ~io.take_ext_int_start + val mrac = rvdffe(mrac_in,wr_mrac_r.asBool,clock,io.scan_mode) + // drive to LSU/IFU + io.dec_tlu_mrac_ff := mrac - // ---------------------------------------------------------------------- - // MRAC (RW) - // [31:0] : Region Access Control Register, 16 regions, {side_effect, cachable} pairs + // ---------------------------------------------------------------------- + // MDEAU (WAR0) + // [31:0] : Dbus Error Address Unlock register + // - val wr_mrac_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MRAC) + val wr_mdeau_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MDEAU) - // prevent pairs of 0x11, side_effect and cacheable - val mrac_in = Cat(io.dec_csr_wrdata_r(31), io.dec_csr_wrdata_r(30) & ~io.dec_csr_wrdata_r(31), - io.dec_csr_wrdata_r(29), io.dec_csr_wrdata_r(28) & ~io.dec_csr_wrdata_r(29), - io.dec_csr_wrdata_r(27), io.dec_csr_wrdata_r(26) & ~io.dec_csr_wrdata_r(27), - io.dec_csr_wrdata_r(25), io.dec_csr_wrdata_r(24) & ~io.dec_csr_wrdata_r(25), - io.dec_csr_wrdata_r(23), io.dec_csr_wrdata_r(22) & ~io.dec_csr_wrdata_r(23), - io.dec_csr_wrdata_r(21), io.dec_csr_wrdata_r(20) & ~io.dec_csr_wrdata_r(21), - io.dec_csr_wrdata_r(19), io.dec_csr_wrdata_r(18) & ~io.dec_csr_wrdata_r(19), - io.dec_csr_wrdata_r(17), io.dec_csr_wrdata_r(16) & ~io.dec_csr_wrdata_r(17), - io.dec_csr_wrdata_r(15), io.dec_csr_wrdata_r(14) & ~io.dec_csr_wrdata_r(15), - io.dec_csr_wrdata_r(13), io.dec_csr_wrdata_r(12) & ~io.dec_csr_wrdata_r(13), - io.dec_csr_wrdata_r(11), io.dec_csr_wrdata_r(10) & ~io.dec_csr_wrdata_r(11), - io.dec_csr_wrdata_r(9), io.dec_csr_wrdata_r(8) & ~io.dec_csr_wrdata_r(9), - io.dec_csr_wrdata_r(7), io.dec_csr_wrdata_r(6) & ~io.dec_csr_wrdata_r(7), - io.dec_csr_wrdata_r(5), io.dec_csr_wrdata_r(4) & ~io.dec_csr_wrdata_r(5), - io.dec_csr_wrdata_r(3), io.dec_csr_wrdata_r(2) & ~io.dec_csr_wrdata_r(3), - io.dec_csr_wrdata_r(1), io.dec_csr_wrdata_r(0) & ~io.dec_csr_wrdata_r(1)) + // ---------------------------------------------------------------------- + // MDSEAC (R) + // [31:0] : Dbus Store Error Address Capture register + // - val mrac = rvdffe(mrac_in,wr_mrac_r.asBool,clock,io.scan_mode) - // drive to LSU/IFU - io.dec_tlu_mrac_ff := mrac + // only capture error bus if the MDSEAC reg is not locked + io.mdseac_locked_ns := mdseac_en | (io.mdseac_locked_f & ~wr_mdeau_r) - // ---------------------------------------------------------------------- - // MDEAU (WAR0) - // [31:0] : Dbus Error Address Unlock register - // + mdseac_en := (io.lsu_imprecise_error_store_any | io.lsu_imprecise_error_load_any) & ~io.nmi_int_detected_f & ~io.mdseac_locked_f - val wr_mdeau_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MDEAU) + val mdseac = rvdffe(io.lsu_imprecise_error_addr_any,mdseac_en.asBool,clock,io.scan_mode) + // ---------------------------------------------------------------------- + // MPMC (R0W1) + // [0] : FW halt + // [1] : Set MSTATUS[MIE] on halt - // ---------------------------------------------------------------------- - // MDSEAC (R) - // [31:0] : Dbus Store Error Address Capture register - // - // only capture error bus if the MDSEAC reg is not locked - io.mdseac_locked_ns := mdseac_en | (io.mdseac_locked_f & ~wr_mdeau_r) + val wr_mpmc_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r === MPMC) - mdseac_en := (io.lsu_imprecise_error_store_any | io.lsu_imprecise_error_load_any) & ~io.nmi_int_detected_f & ~io.mdseac_locked_f + // allow the cycle of the dbg halt flush that contains the wr_mpmc_r to + // set the io.mstatus bit potentially, use delayed version of internal dbg halt. + io.fw_halt_req := wr_mpmc_r & io.dec_csr_wrdata_r(0) & ~io.internal_dbg_halt_mode_f2 & ~io.ext_int_freeze_d1 + val fw_halted_ns = WireInit(UInt(1.W),0.U) + // val fw_halted = withClock(io.free_clk){RegNext(fw_halted_ns,0.U)} + fw_halted_ns := (io.fw_halt_req | perfmux_flop.io.fw_halted) & ~set_mie_pmu_fw_halt + mpmc_b_ns := Mux(wr_mpmc_r.asBool, ~io.dec_csr_wrdata_r(1), ~mpmc) - val mdseac = rvdffe(io.lsu_imprecise_error_addr_any,mdseac_en.asBool,clock,io.scan_mode) + mpmc_b := withClock(io.csr_wr_clk){RegNext(mpmc_b_ns,0.U)} - // ---------------------------------------------------------------------- - // MPMC (R0W1) - // [0] : FW halt - // [1] : Set MSTATUS[MIE] on halt + mpmc := ~mpmc_b + // ---------------------------------------------------------------------- + // MICECT (I-Cache error counter/threshold) + // [31:27] : Icache parity error threshold + // [26:0] : Icache parity error count - val wr_mpmc_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MPMC) - // allow the cycle of the dbg halt flush that contains the wr_mpmc_r to - // set the io.mstatus bit potentially, use delayed version of internal dbg halt. - io.fw_halt_req := wr_mpmc_r & io.dec_csr_wrdata_r(0) & ~io.internal_dbg_halt_mode_f2 & ~io.ext_int_freeze_d1 - val fw_halted_ns = WireInit(UInt(1.W),0.U) - val fw_halted = withClock(io.free_clk){RegNext(fw_halted_ns,0.U)} - fw_halted_ns := (io.fw_halt_req | fw_halted) & ~set_mie_pmu_fw_halt - mpmc_b_ns := Mux(wr_mpmc_r.asBool, ~io.dec_csr_wrdata_r(1), ~mpmc) - mpmc_b := withClock(io.csr_wr_clk){RegNext(mpmc_b_ns,0.U)} + val csr_sat = Mux((io.dec_csr_wrdata_r(31,27) > 26.U(5.W)), 26.U(5.W), io.dec_csr_wrdata_r(31,27)) + val wr_micect_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r === MICECT) + micect_inc := micect(26,0) + Cat(0.U(26.W), io.ic_perr_r) + val micect_ns = Mux(wr_micect_r.asBool, Cat(csr_sat, io.dec_csr_wrdata_r(26,0)) , Cat(micect(31,27), micect_inc)) - mpmc := ~mpmc_b + micect := rvdffe(micect_ns,(wr_micect_r | io.ic_perr_r).asBool,clock,io.scan_mode) - // ---------------------------------------------------------------------- - // MICECT (I-Cache error counter/threshold) - // [31:27] : Icache parity error threshold - // [26:0] : Icache parity error count + mice_ce_req := (("hffffffff".U(32.W) << micect(31,27)) & Cat(0.U(5.W), micect(26,0))).orR + // ---------------------------------------------------------------------- + // MICCMECT (ICCM error counter/threshold) + // [31:27] : ICCM parity error threshold + // [26:0] : ICCM parity error count - val csr_sat = Mux((io.dec_csr_wrdata_r(31,27) > 26.U(5.W)), 26.U(5.W), io.dec_csr_wrdata_r(31,27)) - val wr_micect_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MICECT) - micect_inc := micect + Cat(0.U(26.W), io.ic_perr_r_d1) - val micect_ns = Mux(wr_micect_r.asBool, Cat(csr_sat, io.dec_csr_wrdata_r(26,0)) , Cat(micect(31,27), micect_inc)) + val wr_miccmect_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MICCMECT) + miccmect_inc := miccmect(26,0) + Cat(0.U(26.W), (io.iccm_sbecc_r | io.iccm_dma_sb_error)) + val miccmect_ns = Mux(wr_miccmect_r.asBool, Cat(csr_sat, io.dec_csr_wrdata_r(26,0)) , Cat(miccmect(31,27), miccmect_inc)) - micect := rvdffe(micect_ns,(wr_micect_r | io.ic_perr_r_d1).asBool,clock,io.scan_mode) + miccmect := rvdffe(miccmect_ns,(wr_miccmect_r | io.iccm_sbecc_r | io.iccm_dma_sb_error).asBool,io.free_l2clk,io.scan_mode) - mice_ce_req := (("hffffffff".U(32.W) << micect(31,27)) & Cat(0.U(5.W), micect(26,0))).orR + miccme_ce_req := (("hffffffff".U(32.W) << miccmect(31,27)) & Cat(0.U(5.W), miccmect(26,0))).orR + //miccme_ce_req := (Bits("hffffffff".U(32.W)) << miccmect(31,27) & Cat(0.U(5.W), miccmect(26,0))).orR + // ---------------------------------------------------------------------- + // MDCCMECT (DCCM error counter/threshold) + // [31:27] : DCCM parity error threshold + // [26:0] : DCCM parity error count - // ---------------------------------------------------------------------- - // MICCMECT (ICCM error counter/threshold) - // [31:27] : ICCM parity error threshold - // [26:0] : ICCM parity error count + val wr_mdccmect_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MDCCMECT) + mdccmect_inc := mdccmect(26,0) + Cat(0.U(26.W), perfmux_flop.io.lsu_single_ecc_error_r_d1 ) + val mdccmect_ns = Mux(wr_mdccmect_r.asBool, Cat(csr_sat, io.dec_csr_wrdata_r(26,0)) , Cat(mdccmect(31,27), mdccmect_inc)) - val wr_miccmect_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MICCMECT) - miccmect_inc := miccmect(26,0) + Cat(0.U(26.W), (io.iccm_sbecc_r_d1 | io.iccm_dma_sb_error)) - val miccmect_ns = Mux(wr_miccmect_r.asBool, Cat(csr_sat, io.dec_csr_wrdata_r(26,0)) , Cat(miccmect(31,27), miccmect_inc)) + mdccmect := rvdffe(mdccmect_ns, (wr_mdccmect_r | perfmux_flop.io.lsu_single_ecc_error_r_d1 ).asBool, io.free_l2clk, io.scan_mode) + mdccme_ce_req := (("hffffffff".U(32.W) << mdccmect(31,27)) & Cat(0.U(5.W), mdccmect(26,0))).orR - miccmect := rvdffe(miccmect_ns,(wr_miccmect_r | io.iccm_sbecc_r_d1 | io.iccm_dma_sb_error).asBool,clock,io.scan_mode) -miccme_ce_req := (("hffffffff".U(32.W) << miccmect(31,27)) & Cat(0.U(5.W), miccmect(26,0))).orR -//miccme_ce_req := (Bits("hffffffff".U(32.W)) << miccmect(31,27) & Cat(0.U(5.W), miccmect(26,0))).orR - // ---------------------------------------------------------------------- - // MDCCMECT (DCCM error counter/threshold) - // [31:27] : DCCM parity error threshold - // [26:0] : DCCM parity error count + // ---------------------------------------------------------------------- + // MFDHT (Force Debug Halt Threshold) + // [5:1] : Halt timeout threshold (power of 2) + // [0] : Halt timeout enabled - val wr_mdccmect_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MDCCMECT) - mdccmect_inc := mdccmect(26,0) + Cat(0.U(26.W), io.lsu_single_ecc_error_r_d1) - val mdccmect_ns = Mux(wr_mdccmect_r.asBool, Cat(csr_sat, io.dec_csr_wrdata_r(26,0)) , Cat(mdccmect(31,27), mdccmect_inc)) + val wr_mfdht_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MFDHT) - mdccmect := rvdffe(mdccmect_ns, (wr_mdccmect_r | io.lsu_single_ecc_error_r_d1).asBool, clock, io.scan_mode) + val mfdht_ns = Mux(wr_mfdht_r.asBool, io.dec_csr_wrdata_r(5,0) , mfdht) - mdccme_ce_req := (("hffffffff".U(32.W) << mdccmect(31,27)) & Cat(0.U(5.W), mdccmect(26,0))).orR + mfdht := withClock(io.csr_wr_clk){RegEnable(mfdht_ns,0.U,wr_mfdht_r)} + // ---------------------------------------------------------------------- + // MFDHS(RW) + // [1] : LSU operation pending when debug halt threshold reached + // [0] : IFU operation pending when debug halt threshold reached - // ---------------------------------------------------------------------- - // MFDHT (Force Debug Halt Threshold) - // [5:1] : Halt timeout threshold (power of 2) - // [0] : Halt timeout enabled + val wr_mfdhs_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MFDHS) - val wr_mfdht_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MFDHT) + val mfdhs_ns = Mux(wr_mfdhs_r.asBool, io.dec_csr_wrdata_r(1,0) , + Mux((io.dbg_tlu_halted & ~io.dbg_tlu_halted_f).asBool, Cat(~io.lsu_idle_any_f, ~io.ifu_miss_state_idle_f) , mfdhs)) - val mfdht_ns = Mux(wr_mfdht_r.asBool, io.dec_csr_wrdata_r(5,0) , mfdht) + mfdhs := withClock(io.free_clk){RegEnable(mfdhs_ns,0.U,(wr_mfdhs_r | io.dbg_tlu_halted).asBool)} - mfdht := withClock(io.active_clk){RegNext(mfdht_ns,0.U)} + val force_halt_ctr = Mux(io.debug_halt_req_f.asBool, (force_halt_ctr_f + 1.U(32.W)) , + Mux(io.dbg_tlu_halted_f.asBool, 0.U(32.W) , force_halt_ctr_f)) - // ---------------------------------------------------------------------- - // MFDHS(RW) - // [1] : LSU operation pending when debug halt threshold reached - // [0] : IFU operation pending when debug halt threshold reached + force_halt_ctr_f := rvdffe(force_halt_ctr,mfdht(0),clock,io.scan_mode)//withClock(io.active_clk){RegEnable(force_halt_ctr,0.U,mfdht(0))} + io.force_halt := mfdht(0) & (force_halt_ctr_f & ("hffffffff".U(32.W) << mfdht(5,1))).orR - val wr_mfdhs_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MFDHS) + // ---------------------------------------------------------------------- + // MEIVT (External Interrupt Vector Table (R/W)) + // [31:10]: Base address (R/W) + // [9:0] : Reserved, reads 0x0 - val mfdhs_ns = Mux(wr_mfdhs_r.asBool, io.dec_csr_wrdata_r(1,0) , - Mux((io.dbg_tlu_halted & ~io.dbg_tlu_halted_f).asBool, Cat(~io.lsu_idle_any_f, ~io.ifu_miss_state_idle_f) , mfdhs)) + val wr_meivt_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEIVT) - mfdhs := withClock(io.active_clk){RegEnable(mfdhs_ns,0.U,(wr_mfdhs_r | io.dbg_tlu_halted).asBool)} + val meivt = rvdffe(io.dec_csr_wrdata_r(31,10),wr_meivt_r.asBool,clock,io.scan_mode) - val force_halt_ctr = Mux(io.debug_halt_req_f.asBool, (force_halt_ctr_f + 1.U(32.W)) , - Mux(io.dbg_tlu_halted_f.asBool, 0.U(32.W) , force_halt_ctr_f)) + // ---------------------------------------------------------------------- + // MEIHAP (External Interrupt Handler Access Pointer (R)) + // [31:10]: Base address (R/W) + // [9:2] : ClaimID (R) + // [1:0] : Reserved, 0x0 - force_halt_ctr_f := withClock(io.active_clk){RegEnable(force_halt_ctr,0.U,mfdht(0))} - io.force_halt := mfdht(0) & (force_halt_ctr_f & ("hffffffff".U(32.W) << mfdht(5,1))).orR + val wr_meihap_r = wr_meicpct_r - // ---------------------------------------------------------------------- - // MEIVT (External Interrupt Vector Table (R/W)) - // [31:10]: Base address (R/W) - // [9:0] : Reserved, reads 0x0 + val meihap = rvdffe(io.pic_claimid,wr_meihap_r.asBool,clock,io.scan_mode) + io.dec_tlu_meihap := Cat(meivt, meihap) - val wr_meivt_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEIVT) + // ---------------------------------------------------------------------- + // MEICURPL (R/W) + // [31:4] : Reserved (read 0x0) + // [3:0] : CURRPRI - Priority level of current interrupt service routine (R/W) - val meivt = rvdffe(io.dec_csr_wrdata_r(31,10),wr_meivt_r.asBool,clock,io.scan_mode) - // ---------------------------------------------------------------------- - // MEIHAP (External Interrupt Handler Access Pointer (R)) - // [31:10]: Base address (R/W) - // [9:2] : ClaimID (R) - // [1:0] : Reserved, 0x0 - + val wr_meicurpl_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEICURPL) + val meicurpl_ns = Mux(wr_meicurpl_r.asBool, io.dec_csr_wrdata_r(3,0) , meicurpl) - val wr_meihap_r = wr_meicpct_r + meicurpl := withClock(io.csr_wr_clk){RegNext(meicurpl_ns,0.U)} + // PIC needs this reg + io.dec_tlu_meicurpl := meicurpl - val meihap = rvdffe(io.pic_claimid,wr_meihap_r.asBool,clock,io.scan_mode) - io.dec_tlu_meihap := Cat(meivt, meihap) - // ---------------------------------------------------------------------- - // MEICURPL (R/W) - // [31:4] : Reserved (read 0x0) - // [3:0] : CURRPRI - Priority level of current interrupt service routine (R/W) + // ---------------------------------------------------------------------- + // MEICIDPL (R/W) + // [31:4] : Reserved (read 0x0) + // [3:0] : External Interrupt Claim ID's Priority Level Register - val wr_meicurpl_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEICURPL) - val meicurpl_ns = Mux(wr_meicurpl_r.asBool, io.dec_csr_wrdata_r(3,0) , meicurpl) + val wr_meicidpl_r = (io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEICIDPL)) | io.take_ext_int_start - meicurpl := withClock(io.csr_wr_clk){RegNext(meicurpl_ns,0.U)} - // PIC needs this reg - io.dec_tlu_meicurpl := meicurpl + val meicidpl_ns = Mux(wr_meicpct_r.asBool, io.pic_pl, + Mux(wr_meicidpl_r.asBool, io.dec_csr_wrdata_r(3,0) , perfmux_flop.io.meicidpl)) + // meicidpl := withClock(io.free_clk){RegNext(meicidpl_ns,0.U)} - // ---------------------------------------------------------------------- - // MEICIDPL (R/W) - // [31:4] : Reserved (read 0x0) - // [3:0] : External Interrupt Claim ID's Priority Level Register + // ---------------------------------------------------------------------- + // MEICPCT (Capture CLAIMID in MEIHAP and PL in MEICIDPL + // [31:1] : Reserved (read 0x0) + // [0] : Capture (W1, Read 0) + wr_meicpct_r := (io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEICPCT)) | io.take_ext_int_start + // ---------------------------------------------------------------------- + // MEIPT (External Interrupt Priority Threshold) + // [31:4] : Reserved (read 0x0) + // [3:0] : PRITHRESH - val wr_meicidpl_r = (io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEICIDPL)) | io.take_ext_int_start - val meicidpl_ns = Mux(wr_meicpct_r.asBool, io.pic_pl, - Mux(wr_meicidpl_r.asBool, io.dec_csr_wrdata_r(3,0) , meicidpl)) - meicidpl := withClock(io.free_clk){RegNext(meicidpl_ns,0.U)} + val wr_meipt_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEIPT) + val meipt_ns = Mux(wr_meipt_r.asBool, io.dec_csr_wrdata_r(3,0), meipt) - // ---------------------------------------------------------------------- - // MEICPCT (Capture CLAIMID in MEIHAP and PL in MEICIDPL - // [31:1] : Reserved (read 0x0) - // [0] : Capture (W1, Read 0) + meipt := withClock(io.csr_wr_clk){RegNext(meipt_ns,0.U)} + // to PIC + io.dec_tlu_meipt := meipt - wr_meicpct_r := (io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEICPCT)) | io.take_ext_int_start + // ---------------------------------------------------------------------- + // DCSR (R/W) (Only accessible in debug mode) + // [31:28] : xdebugver (hard coded to 0x4) RO + // [27:16] : 0x0, reserved + // [15] : ebreakm + // [14] : 0x0, reserved + // [13] : ebreaks (0x0 for this core) + // [12] : ebreaku (0x0 for this core) + // [11] : stepie + // [10] : stopcount + // [9] : 0x0 //stoptime + // [8:6] : cause (RO) + // [5:4] : 0x0, reserved + // [3] : nmip + // [2] : step + // [1:0] : prv (0x3 for this core) + // - // ---------------------------------------------------------------------- - // MEIPT (External Interrupt Priority Threshold) - // [31:4] : Reserved (read 0x0) - // [3:0] : PRITHRESH + // RV has clarified that 'priority 4' in the spec means top priority. + // 4. single step. 3. Debugger request. 2. Ebreak. 1. Trigger. + // RV debug spec indicates a cause priority change for trigger hits during single step. - val wr_meipt_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEIPT) - val meipt_ns = Mux(wr_meipt_r.asBool, io.dec_csr_wrdata_r(3,0), meipt) + val trigger_hit_for_dscr_cause_r_d1 = io.trigger_hit_dmode_r_d1 | (io.trigger_hit_r_d1 & io.dcsr_single_step_done_f); - meipt := withClock(io.active_clk){RegNext(meipt_ns,0.U)} - // to PIC - io.dec_tlu_meipt := meipt + val dcsr_cause = Mux1H(Seq( + (io.dcsr_single_step_done_f & ~io.ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1 & ~io.debug_halt_req).asBool -> "b100".U(3.W), + (io.debug_halt_req & ~io.ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1).asBool -> "b011".U(3.W), + (io.ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1).asBool -> "b001".U(3.W), + (trigger_hit_for_dscr_cause_r_d1).asBool -> "b010".U(3.W) )) - // ---------------------------------------------------------------------- - // DCSR (R/W) (Only accessible in debug mode) - // [31:28] : xdebugver (hard coded to 0x4) RO - // [27:16] : 0x0, reserved - // [15] : ebreakm - // [14] : 0x0, reserved - // [13] : ebreaks (0x0 for this core) - // [12] : ebreaku (0x0 for this core) - // [11] : stepie - // [10] : stopcount - // [9] : 0x0 //stoptime - // [8:6] : cause (RO) - // [5:4] : 0x0, reserved - // [3] : nmip - // [2] : step - // [1:0] : prv (0x3 for this core) - // + val wr_dcsr_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DCSR) - // RV has clarified that 'priority 4' in the spec means top priority. - // 4. single step. 3. Debugger request. 2. Ebreak. 1. Trigger. - // RV debug spec indicates a cause priority change for trigger hits during single step. + // Multiple halt enter requests can happen before we are halted. + // We have to continue to upgrade based on dcsr_cause priority but we can't downgrade. + val dcsr_cause_upgradeable = io.internal_dbg_halt_mode_f & (io.dcsr(8,6) === "b011".U(3.W)) + val enter_debug_halt_req_le = io.enter_debug_halt_req & (~io.dbg_tlu_halted | dcsr_cause_upgradeable) - val trigger_hit_for_dscr_cause_r_d1 = io.trigger_hit_dmode_r_d1 | (io.trigger_hit_r_d1 & io.dcsr_single_step_done_f); + val nmi_in_debug_mode = io.nmi_int_detected_f & io.internal_dbg_halt_mode_f + val dcsr_ns = Mux(enter_debug_halt_req_le.asBool, Cat(io.dcsr(15,9), dcsr_cause, io.dcsr(5,2),"b11".U(2.W)) ,//prv 0x3 for this core + Mux(wr_dcsr_r.asBool, Cat(io.dec_csr_wrdata_r(15), 0.U(3.W), io.dec_csr_wrdata_r(11,10), 0.U(1.W), io.dcsr(8,6), 0.U(2.W), nmi_in_debug_mode | io.dcsr(3), io.dec_csr_wrdata_r(2), "b11".U(2.W)) , Cat(io.dcsr(15,4), nmi_in_debug_mode, io.dcsr(2),"b11".U(2.W)))) - val dcsr_cause = Mux1H(Seq( -(io.dcsr_single_step_done_f & ~io.ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1 & ~io.debug_halt_req).asBool -> "b100".U(3.W), - (io.debug_halt_req & ~io.ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1).asBool -> "b011".U(3.W), - (io.ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1).asBool -> "b001".U(3.W), - (trigger_hit_for_dscr_cause_r_d1).asBool -> "b010".U(3.W) )) - val wr_dcsr_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DCSR) + io.dcsr := rvdffe(dcsr_ns, (enter_debug_halt_req_le | wr_dcsr_r | io.internal_dbg_halt_mode | io.take_nmi).asBool, io.free_l2clk, io.scan_mode) + // ---------------------------------------------------------------------- + // DPC (R/W) (Only accessible in debug mode) + // [31:0] : Debug PC - // Multiple halt enter requests can happen before we are halted. - // We have to continue to upgrade based on dcsr_cause priority but we can't downgrade. - val dcsr_cause_upgradeable = io.internal_dbg_halt_mode_f & (io.dcsr(8,6) === "b011".U(3.W)) - val enter_debug_halt_req_le = io.enter_debug_halt_req & (~io.dbg_tlu_halted | dcsr_cause_upgradeable) - val nmi_in_debug_mode = io.nmi_int_detected_f & io.internal_dbg_halt_mode_f - val dcsr_ns = Mux(enter_debug_halt_req_le.asBool, Cat(io.dcsr(15,9), dcsr_cause, io.dcsr(5,2),"b11".U(2.W)) ,//prv 0x3 for this core - Mux(wr_dcsr_r.asBool, Cat(io.dec_csr_wrdata_r(15), 0.U(3.W), io.dec_csr_wrdata_r(11,10), 0.U(1.W), io.dcsr(8,6), 0.U(2.W), nmi_in_debug_mode | io.dcsr(3), io.dec_csr_wrdata_r(2), "b11".U(2.W)) , Cat(io.dcsr(15,4), nmi_in_debug_mode, io.dcsr(2),"b11".U(2.W)))) + val wr_dpc_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DPC) + val dpc_capture_npc = io.dbg_tlu_halted & ~io.dbg_tlu_halted_f & ~io.request_debug_mode_done + val dpc_capture_pc = io.request_debug_mode_r - io.dcsr := rvdffe(dcsr_ns, (enter_debug_halt_req_le | wr_dcsr_r | io.internal_dbg_halt_mode | io.take_nmi).asBool, clock, io.scan_mode) + val dpc_ns = Mux1H(Seq( + (~dpc_capture_pc & ~dpc_capture_npc & wr_dpc_r).asBool -> io.dec_csr_wrdata_r(31,1), + (dpc_capture_pc).asBool -> pc_r, + (~dpc_capture_pc & dpc_capture_npc).asBool -> io.npc_r )) - // ---------------------------------------------------------------------- - // DPC (R/W) (Only accessible in debug mode) - // [31:0] : Debug PC + io.dpc := rvdffe(dpc_ns,(wr_dpc_r | dpc_capture_pc | dpc_capture_npc).asBool,clock,io.scan_mode) + // ---------------------------------------------------------------------- + // DICAWICS (R/W) (Only accessible in debug mode) + // [31:25] : Reserved + // [24] : Array select, 0 is data, 1 is tag + // [23:22] : Reserved + // [21:20] : Way select + // [19:17] : Reserved + // [16:3] : Index + // [2:0] : Reserved - val wr_dpc_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DPC) - val dpc_capture_npc = io.dbg_tlu_halted & ~io.dbg_tlu_halted_f & ~io.request_debug_mode_done - val dpc_capture_pc = io.request_debug_mode_r - val dpc_ns = Mux1H(Seq( - (~dpc_capture_pc & ~dpc_capture_npc & wr_dpc_r).asBool -> io.dec_csr_wrdata_r(31,1), - (dpc_capture_pc).asBool -> pc_r, - (~dpc_capture_pc & dpc_capture_npc).asBool -> io.npc_r )) + val dicawics_ns = Cat(io.dec_csr_wrdata_r(24), io.dec_csr_wrdata_r(21,20), io.dec_csr_wrdata_r(16,3)) + val wr_dicawics_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAWICS) - io.dpc := rvdffe(dpc_ns,(wr_dpc_r | dpc_capture_pc | dpc_capture_npc).asBool,clock,io.scan_mode) + val dicawics = rvdffe(dicawics_ns,wr_dicawics_r.asBool,clock,io.scan_mode) - // ---------------------------------------------------------------------- - // DICAWICS (R/W) (Only accessible in debug mode) - // [31:25] : Reserved - // [24] : Array select, 0 is data, 1 is tag - // [23:22] : Reserved - // [21:20] : Way select - // [19:17] : Reserved - // [16:3] : Index - // [2:0] : Reserved + // ---------------------------------------------------------------------- + // DICAD0 (R/W) (Only accessible in debug mode) + // + // If io.dicawics[array] is 0 + // [31:0] : inst data + // + // If io.dicawics[array] is 1 + // [31:16] : Tag + // [15:7] : Reserved + // [6:4] : LRU + // [3:1] : Reserved + // [0] : Valid - - val dicawics_ns = Cat(io.dec_csr_wrdata_r(24), io.dec_csr_wrdata_r(21,20), io.dec_csr_wrdata_r(16,3)) - val wr_dicawics_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAWICS) + val wr_dicad0_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD0) + val dicad0_ns = Mux(wr_dicad0_r.asBool, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data(31,0)) - val dicawics = rvdffe(dicawics_ns,wr_dicawics_r.asBool,clock,io.scan_mode) + val dicad0 = rvdffe(dicad0_ns, (wr_dicad0_r | io.ifu_ic_debug_rd_data_valid).asBool, clock, io.scan_mode) - // ---------------------------------------------------------------------- - // DICAD0 (R/W) (Only accessible in debug mode) - // - // If io.dicawics[array] is 0 - // [31:0] : inst data - // - // If io.dicawics[array] is 1 - // [31:16] : Tag - // [15:7] : Reserved - // [6:4] : LRU - // [3:1] : Reserved - // [0] : Valid + // ---------------------------------------------------------------------- + // DICAD0H (R/W) (Only accessible in debug mode) + // + // If io.dicawics[array] is 0 + // [63:32] : inst data + // - val wr_dicad0_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD0) - val dicad0_ns = Mux(wr_dicad0_r.asBool, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) + val wr_dicad0h_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD0H) - val dicad0 = rvdffe(dicad0_ns, (wr_dicad0_r | io.ifu_ic_debug_rd_data_valid).asBool, clock, io.scan_mode) + val dicad0h_ns = Mux(wr_dicad0h_r.asBool, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data(63,32)) - // ---------------------------------------------------------------------- - // DICAD0H (R/W) (Only accessible in debug mode) - // - // If io.dicawics[array] is 0 - // [63:32] : inst data - // + val dicad0h = rvdffe(dicad0h_ns,(wr_dicad0h_r | io.ifu_ic_debug_rd_data_valid).asBool,clock,io.scan_mode) + if (ICACHE_ECC) { + // ---------------------------------------------------------------------- + // DICAD1 (R/W) (Only accessible in debug mode) + // [6:0] : ECC - val wr_dicad0h_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD0H) + val dicad1_raw = WireInit(UInt(7.W),0.U) + val wr_dicad1_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD1) - val dicad0h_ns = Mux(wr_dicad0h_r.asBool, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data(63,32)) + val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r(6,0), io.ifu_ic_debug_rd_data(70,64)) - val dicad0h = rvdffe(dicad0h_ns,(wr_dicad0h_r | io.ifu_ic_debug_rd_data_valid).asBool,clock,io.scan_mode) + dicad1_raw := rvdffe(dicad1_ns,(wr_dicad1_r | io.ifu_ic_debug_rd_data_valid).asBool,clock,io.scan_mode)//withClock(io.active_clk){RegEnable(dicad1_ns,0.U,(wr_dicad1_r | io.ifu_ic_debug_rd_data_valid).asBool)} + dicad1 := Cat(0.U(25.W), dicad1_raw) - if (ICACHE_ECC) { - // ---------------------------------------------------------------------- - // DICAD1 (R/W) (Only accessible in debug mode) - // [6:0] : ECC + } + else { + // ---------------------------------------------------------------------- + // DICAD1 (R/W) (Only accessible in debug mode) + // [3:0] : Parity - val dicad1_raw = WireInit(UInt(7.W),0.U) - val wr_dicad1_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD1) - val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data(70,64)) - dontTouch(dicad1_ns) + val dicad1_raw = WireInit(UInt(4.W),0.U) + val wr_dicad1_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD1) - dicad1_raw := withClock(io.active_clk){RegEnable(dicad1_ns,0.U,(wr_dicad1_r | io.ifu_ic_debug_rd_data_valid).asBool)} - dicad1 := Cat(0.U(25.W), dicad1_raw) + val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r(3,0), io.ifu_ic_debug_rd_data(67,64)) - } - else { - // ---------------------------------------------------------------------- - // DICAD1 (R/W) (Only accessible in debug mode) - // [3:0] : Parity + dicad1_raw :=withClock(io.free_clk){RegEnable(dicad1_ns,0.U,(wr_dicad1_r | io.ifu_ic_debug_rd_data_valid).asBool)} + dicad1 := Cat(0.U(28.W), dicad1_raw) + } + // ---------------------------------------------------------------------- + // DICAGO (R/W) (Only accessible in debug mode) + // [0] : Go - val dicad1_raw = WireInit(UInt(4.W),0.U) - val wr_dicad1_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD1) + if (ICACHE_ECC) io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(dicad1(6,0), dicad0h(31,0), dicad0(31,0)) + else io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(0.U(3.W),dicad1(3,0), dicad0h(31,0), dicad0(31,0)) - val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r(3,0), io.ifu_ic_debug_rd_data(67,64)) + io.dec_tlu_ic_diag_pkt.icache_dicawics := dicawics - dicad1_raw :=withClock(io.active_clk){RegEnable(dicad1_ns,0.U,(wr_dicad1_r | io.ifu_ic_debug_rd_data_valid).asBool)} - dicad1 := Cat(0.U(28.W), dicad1_raw) - } + val icache_rd_valid = io.allow_dbg_halt_csr_write & io.dec_csr_any_unq_d & io.dec_i0_decode_d & ~io.dec_csr_wen_unq_d & (io.dec_csr_rdaddr_d(11,0) === DICAGO) + val icache_wr_valid = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAGO) - // ---------------------------------------------------------------------- - // DICAGO (R/W) (Only accessible in debug mode) - // [0] : Go + // val icache_rd_valid_f = WireInit(UInt(1.W),0.U) + // val icache_wr_valid_f = WireInit(UInt(1.W),0.U) - if (ICACHE_ECC) io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(dicad1(6,0), dicad0h(31,0), dicad0(31,0)) - else io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(0.U(2.W),dicad1(3,0), dicad0h(31,0), dicad0(31,0)) + io.dec_tlu_ic_diag_pkt.icache_rd_valid := perfmux_flop.io.icache_rd_valid_f + io.dec_tlu_ic_diag_pkt.icache_wr_valid := perfmux_flop.io.icache_wr_valid_f - io.dec_tlu_ic_diag_pkt.icache_dicawics := dicawics + // ---------------------------------------------------------------------- + // MTSEL (R/W) + // [1:0] : Trigger select : 00, 01, 10 are data/address triggers. 11 is inst count - val icache_rd_valid = io.allow_dbg_halt_csr_write & io.dec_csr_any_unq_d & io.dec_i0_decode_d & ~io.dec_csr_wen_unq_d & (io.dec_csr_rdaddr_d(11,0) === DICAGO) - val icache_wr_valid = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAGO) - - val icache_rd_valid_f = withClock(io.active_clk){RegNext(icache_rd_valid,0.U)} - val icache_wr_valid_f = withClock(io.active_clk){RegNext(icache_wr_valid,0.U)} - - io.dec_tlu_ic_diag_pkt.icache_rd_valid := icache_rd_valid_f - io.dec_tlu_ic_diag_pkt.icache_wr_valid := icache_wr_valid_f - - // ---------------------------------------------------------------------- - // MTSEL (R/W) - // [1:0] : Trigger select : 00, 01, 10 are data/address triggers. 11 is inst count + val wr_mtsel_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTSEL) + val mtsel_ns = Mux(wr_mtsel_r.asBool, io.dec_csr_wrdata_r(1,0), mtsel) - val wr_mtsel_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTSEL) - val mtsel_ns = Mux(wr_mtsel_r.asBool, io.dec_csr_wrdata_r(1,0), mtsel) - - mtsel := withClock(io.csr_wr_clk){RegNext(mtsel_ns,0.U)} - // ---------------------------------------------------------------------- - // MTDATA1 (R/W) - // [31:0] : Trigger Data 1 - // for triggers 0, 1, 2 and 3 aka Match Control - // [31:28] : type, hard coded to 0x2 - // [27] : dmode - // [26:21] : hard coded to 0x1f - // [20] : hit - // [19] : select (0 - address, 1 - data) - // [18] : timing, always 'before', reads 0x0 - // [17:12] : action, bits [17:13] not implemented and reads 0x0 - // [11] : chain - // [10:7] : match, bits [10:8] not implemented and reads 0x0 - // [6] : M - // [5:3] : not implemented, reads 0x0 - // [2] : execute - // [1] : store - // [0] : load - // - // decoder ring - // [27] : => 9 - // [20] : => 8 - // [19] : => 7 - // [12] : => 6 - // [11] : => 5 - // [7] : => 4 - // [6] : => 3 - // [2] : => 2 - // [1] : => 1 - // [0] : => 0 - - - - // don't allow setting load-data. - val tdata_load = io.dec_csr_wrdata_r(0) & ~io.dec_csr_wrdata_r(19) - // don't allow setting execute-data. - val tdata_opcode = io.dec_csr_wrdata_r(2) & ~io.dec_csr_wrdata_r(19) - // don't allow clearing DMODE and action=1 - val tdata_action = (io.dec_csr_wrdata_r(27) & io.dbg_tlu_halted_f) & io.dec_csr_wrdata_r(12) - - val tdata_wrdata_r = Cat(io.dec_csr_wrdata_r(27) & io.dbg_tlu_halted_f, io.dec_csr_wrdata_r(20,19), tdata_action, io.dec_csr_wrdata_r(11), - io.dec_csr_wrdata_r(7,6), tdata_opcode, io.dec_csr_wrdata_r(1), tdata_load) - - // If the DMODE bit is set, tdata1 can only be updated in debug_mode - val wr_mtdata1_t_r = VecInit.tabulate(4)(i => io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTDATA1) & (mtsel === i.U(2.W)) & (~io.mtdata1_t(i)(MTDATA1_DMODE) | io.dbg_tlu_halted_f)) - val mtdata1_t_ns = VecInit.tabulate(4)(i => Mux(wr_mtdata1_t_r(i).asBool, tdata_wrdata_r, Cat(io.mtdata1_t(i)(9), io.update_hit_bit_r(i) | io.mtdata1_t(i)(8), io.mtdata1_t(i)(7,0)))) - -for(i <- 0 until 4) { io.mtdata1_t(i) := withClock(io.active_clk){RegNext(mtdata1_t_ns(i),0.U)}} - - -val mtdata1_tsel_out = Mux1H((0 until 4).map(i => (mtsel === i.U(2.W)) -> Cat(2.U(4.W), io.mtdata1_t(i)(9), "b011111".U(6.W), io.mtdata1_t(i)(8,7), 0.U(6.W), io.mtdata1_t(i)(6,5), 0.U(3.W), io.mtdata1_t(i)(4,3), 0.U(3.W), io.mtdata1_t(i)(2,0)))) -for(i <- 0 until 4 ){ - io.trigger_pkt_any(i).select := io.mtdata1_t(i)(MTDATA1_SEL) - io.trigger_pkt_any(i).match_pkt := io.mtdata1_t(i)(MTDATA1_MATCH) - io.trigger_pkt_any(i).store := io.mtdata1_t(i)(MTDATA1_ST) - io.trigger_pkt_any(i).load := io.mtdata1_t(i)(MTDATA1_LD) - io.trigger_pkt_any(i).execute := io.mtdata1_t(i)(MTDATA1_EXE) - io.trigger_pkt_any(i).m := io.mtdata1_t(i)(MTDATA1_M_ENABLED) + mtsel := withClock(io.csr_wr_clk){RegNext(mtsel_ns,0.U)} + // ---------------------------------------------------------------------- + // MTDATA1 (R/W) + // [31:0] : Trigger Data 1 + // for triggers 0, 1, 2 and 3 aka Match Control + // [31:28] : type, hard coded to 0x2 + // [27] : dmode + // [26:21] : hard coded to 0x1f + // [20] : hit + // [19] : select (0 - address, 1 - data) + // [18] : timing, always 'before', reads 0x0 + // [17:12] : action, bits [17:13] not implemented and reads 0x0 + // [11] : chain + // [10:7] : match, bits [10:8] not implemented and reads 0x0 + // [6] : M + // [5:3] : not implemented, reads 0x0 + // [2] : execute + // [1] : store + // [0] : load + // + // decoder ring + // [27] : => 9 + // [20] : => 8 + // [19] : => 7 + // [12] : => 6 + // [11] : => 5 + // [7] : => 4 + // [6] : => 3 + // [2] : => 2 + // [1] : => 1 + // [0] : => 0 + + + + // don't allow setting load-data. + val tdata_load = io.dec_csr_wrdata_r(0) & ~io.dec_csr_wrdata_r(19) + // don't allow setting execute-data. + val tdata_opcode = io.dec_csr_wrdata_r(2) & ~io.dec_csr_wrdata_r(19) + // don't allow clearing DMODE and action=1 + val tdata_action = (io.dec_csr_wrdata_r(27) & io.dbg_tlu_halted_f) & io.dec_csr_wrdata_r(12) + + // Chain bit has conditions: WARL for triggers without chains. Force to zero if dmode is 0 but next trigger dmode is 1. + val tdata_chain = Mux(mtsel(0), 0.U(1.W), // triggers 1 and 3 chain bit is always zero + Mux(mtsel(1), io.dec_csr_wrdata_r(11) & ~(io.mtdata1_t(3)(MTDATA1_DMODE) & ~io.dec_csr_wrdata_r(27)), // trigger 2 + io.dec_csr_wrdata_r(11) & ~(io.mtdata1_t(1)(MTDATA1_DMODE) & ~io.dec_csr_wrdata_r(27)) )) // trigger 0 + + // Kill mtdata1 write if dmode=1 but prior trigger has dmode=0/chain=1. Only applies to T1 and T3 + val tdata_kill_write = Mux(mtsel(1), io.dec_csr_wrdata_r(27) & (~io.mtdata1_t(2)(MTDATA1_DMODE) & io.mtdata1_t(2)(MTDATA1_CHAIN)), // trigger 3 + io.dec_csr_wrdata_r(27) & (~io.mtdata1_t(0)(MTDATA1_DMODE) & io.mtdata1_t(0)(MTDATA1_CHAIN))) // trigger 1 + + val tdata_wrdata_r = Cat(io.dec_csr_wrdata_r(27) & io.dbg_tlu_halted_f, io.dec_csr_wrdata_r(20,19), tdata_action, tdata_chain, io.dec_csr_wrdata_r(7,6), tdata_opcode, io.dec_csr_wrdata_r(1), tdata_load) + + // If the DMODE bit is set, tdata1 can only be updated in debug_mode + val wr_mtdata1_t_r = VecInit.tabulate(4)(i => if(i == 0 || i == 2){io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTDATA1) & (mtsel === i.U(2.W)) & (!io.mtdata1_t(i)(MTDATA1_DMODE) | io.dbg_tlu_halted_f)}else{io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTDATA1) & (mtsel === i.U(2.W)) & (!io.mtdata1_t(i)(MTDATA1_DMODE) | io.dbg_tlu_halted_f) & !tdata_kill_write }) + + val mtdata1_t_ns = VecInit.tabulate(4)(i => Mux(wr_mtdata1_t_r(i).asBool, tdata_wrdata_r, Cat(io.mtdata1_t(i)(9), io.update_hit_bit_r(i) | io.mtdata1_t(i)(8), io.mtdata1_t(i)(7,0)))) + + + + for(i <- 0 until 4) { io.mtdata1_t(i) := rvdffe(mtdata1_t_ns(i),io.trigger_enabled(i) | wr_mtdata1_t_r(i),clock,io.scan_mode)}//withClock(io.active_clk){RegNext(mtdata1_t_ns(i),0.U)}} + + + val mtdata1_tsel_out = Mux1H((0 until 4).map(i => (mtsel === i.U(2.W)) -> Cat(2.U(4.W), io.mtdata1_t(i)(9), "b011111".U(6.W), io.mtdata1_t(i)(8,7), 0.U(6.W), io.mtdata1_t(i)(6,5), 0.U(3.W), io.mtdata1_t(i)(4,3), 0.U(3.W), io.mtdata1_t(i)(2,0)))) + for(i <- 0 until 4 ){ + io.trigger_pkt_any(i).select := io.mtdata1_t(i)(MTDATA1_SEL) + io.trigger_pkt_any(i).match_pkt := io.mtdata1_t(i)(MTDATA1_MATCH) + io.trigger_pkt_any(i).store := io.mtdata1_t(i)(MTDATA1_ST) + io.trigger_pkt_any(i).load := io.mtdata1_t(i)(MTDATA1_LD) + io.trigger_pkt_any(i).execute := io.mtdata1_t(i)(MTDATA1_EXE) + io.trigger_pkt_any(i).m := io.mtdata1_t(i)(MTDATA1_M_ENABLED) + } + + // ---------------------------------------------------------------------- + // MTDATA2 (R/W) + // [31:0] : Trigger Data 2 + // If the DMODE bit is set, tdata2 can only be updated in debug_mode + val wr_mtdata2_t_r = VecInit.tabulate(4)(i => io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTDATA2) & (mtsel === i.U(2.W)) & (~io.mtdata1_t(i)(MTDATA1_DMODE) | io.dbg_tlu_halted_f)) + for(i <- 0 until 4) { mtdata2_t(i) := rvdffe(io.dec_csr_wrdata_r,wr_mtdata2_t_r(i).asBool,clock,io.scan_mode)} + + + + val mtdata2_tsel_out = Mux1H((0 until 4).map(i =>(mtsel === i.U(2.W)) -> mtdata2_t(i))) + for(i <- 0 until 4) {io.trigger_pkt_any(i).tdata2 := mtdata2_t(i)} + + + //---------------------------------------------------------------------- + // Performance Monitor Counters section starts + //---------------------------------------------------------------------- + + // Pack the event selects into a vector for genvar + mhpme_vec(0) := perf_csrs.io.mhpme3 + mhpme_vec(1) := perf_csrs.io.mhpme4 + mhpme_vec(2) := perf_csrs.io.mhpme5 + mhpme_vec(3) := perf_csrs.io.mhpme6 + + // Generate the muxed incs for all counters based on event type + + // val mhpmc_inc_r =perfmux_flop.io.mhpmc_inc_r //mux out + perfmux_flop.io.mcountinhibit := mcountinhibit + perfmux_flop.io.mhpme_vec := mhpme_vec + perfmux_flop.io.ifu_pmu_ic_hit := io.ifu_pmu_ic_hit + perfmux_flop.io.ifu_pmu_ic_miss := io.ifu_pmu_ic_miss + perfmux_flop.io.tlu_i0_commit_cmt := io.tlu_i0_commit_cmt + perfmux_flop.io.illegal_r := io.illegal_r + perfmux_flop.io.exu_pmu_i0_pc4 := io.exu_pmu_i0_pc4 + perfmux_flop.io.ifu_pmu_instr_aligned := io.ifu_pmu_instr_aligned + perfmux_flop.io.dec_pmu_instr_decoded := io.dec_pmu_instr_decoded + perfmux_flop.io.dec_tlu_packet_r := io.dec_tlu_packet_r + perfmux_flop.io.exu_pmu_i0_br_misp := io.exu_pmu_i0_br_misp + perfmux_flop.io.dec_pmu_decode_stall := io.dec_pmu_decode_stall + perfmux_flop.io.exu_pmu_i0_br_ataken := io.exu_pmu_i0_br_ataken + perfmux_flop.io.ifu_pmu_fetch_stall := io.ifu_pmu_fetch_stall + perfmux_flop.io.dec_pmu_postsync_stall := io.dec_pmu_postsync_stall + perfmux_flop.io.dec_pmu_presync_stall := io.dec_pmu_presync_stall + perfmux_flop.io.lsu_store_stall_any := io.lsu_store_stall_any + perfmux_flop.io.dma_dccm_stall_any := io.dma_dccm_stall_any + perfmux_flop.io.dma_iccm_stall_any := io.dma_iccm_stall_any + perfmux_flop.io.i0_exception_valid_r := io.i0_exception_valid_r + perfmux_flop.io.dec_tlu_pmu_fw_halted := io.dec_tlu_pmu_fw_halted + perfmux_flop.io.dma_pmu_any_read := io.dma_pmu_any_read + perfmux_flop.io.dma_pmu_any_write := io.dma_pmu_any_write + perfmux_flop.io.dma_pmu_dccm_read := io.dma_pmu_dccm_read + perfmux_flop.io.dma_pmu_dccm_write := io.dma_pmu_dccm_write + perfmux_flop.io.lsu_pmu_load_external_r := io.lsu_pmu_load_external_r + perfmux_flop.io.lsu_pmu_store_external_r := io.lsu_pmu_store_external_r + io.mstatus := perfmux_flop.io.mstatus + io.mip := perfmux_flop.io.mip + perfmux_flop.io.mie := mie + perfmux_flop.io.ifu_pmu_bus_trxn := io.ifu_pmu_bus_trxn + perfmux_flop.io.lsu_pmu_bus_trxn := io.lsu_pmu_bus_trxn + perfmux_flop.io.lsu_pmu_bus_misaligned := io.lsu_pmu_bus_misaligned + perfmux_flop.io.ifu_pmu_bus_error := io.ifu_pmu_bus_error + perfmux_flop.io.lsu_pmu_bus_error := io.lsu_pmu_bus_error + perfmux_flop.io.ifu_pmu_bus_busy := io.ifu_pmu_bus_busy + perfmux_flop.io.lsu_pmu_bus_busy := io.lsu_pmu_bus_busy + perfmux_flop.io.i0_trigger_hit_r := io.i0_trigger_hit_r + perfmux_flop.io.lsu_exc_valid_r := io.lsu_exc_valid_r + perfmux_flop.io.take_timer_int := io.take_timer_int + perfmux_flop.io.take_int_timer0_int := io.take_int_timer0_int + perfmux_flop.io.take_int_timer1_int := io.take_int_timer1_int + perfmux_flop.io.take_ext_int := io.take_ext_int + perfmux_flop.io.tlu_flush_lower_r := io.tlu_flush_lower_r + perfmux_flop.io.dec_tlu_br0_error_r := io.dec_tlu_br0_error_r + perfmux_flop.io.rfpc_i0_r := io.rfpc_i0_r + perfmux_flop.io.dec_tlu_br0_start_error_r := io.dec_tlu_br0_start_error_r + //flop outputs + // mcyclel_cout_f := perfmux_flop.io.mcyclel_cout_f + // minstret_enable_f := perfmux_flop.io.minstret_enable_f + // minstretl_cout_f := perfmux_flop.io.minstretl_cout_f + // fw_halted := perfmux_flop.io.fw_halted + // meicidpl := perfmux_flop.io.meicidpl + // icache_rd_valid_f := perfmux_flop.io.icache_rd_valid_f + // icache_wr_valid_f := perfmux_flop.io.icache_wr_valid_f + // val mhpmc_inc_r_d1 = perfmux_flop.io.mhpmc_inc_r_d1 + // val perfcnt_halted_d1 = perfmux_flop.io.perfcnt_halted_d1 + io.mdseac_locked_f := perfmux_flop.io.mdseac_locked_f + // lsu_single_ecc_error_r_d1 := perfmux_flop.io.lsu_single_ecc_error_r_d1 + io.lsu_exc_valid_r_d1 := perfmux_flop.io.lsu_exc_valid_r_d1 + // lsu_i0_exc_r_d1 := perfmux_flop.io.lsu_i0_exc_r_d1 + io.take_ext_int_start_d1 := perfmux_flop.io.take_ext_int_start_d1 + io.take_ext_int_start_d2 := perfmux_flop.io.take_ext_int_start_d2 + io.take_ext_int_start_d3 := perfmux_flop.io.take_ext_int_start_d3 + io.ext_int_freeze_d1 := perfmux_flop.io.ext_int_freeze_d1 + + + //flop inputs + perfmux_flop.io.mdseac_locked_ns := io.mdseac_locked_ns + perfmux_flop.io.lsu_single_ecc_error_r := io.lsu_single_ecc_error_r + perfmux_flop.io.lsu_i0_exc_r := io.lsu_i0_exc_r + perfmux_flop.io.take_ext_int_start := io.take_ext_int_start + perfmux_flop.io.ext_int_freeze := io.ext_int_freeze + perfmux_flop.io.mip_ns := mip_ns + perfmux_flop.io.mcyclel_cout := mcyclel_cout + perfmux_flop.io.wr_mcycleh_r := wr_mcycleh_r + perfmux_flop.io.mcyclel_cout_in := mcyclel_cout_in + perfmux_flop.io.minstret_enable := minstret_enable + perfmux_flop.io.minstretl_cout_ns := minstretl_cout_ns + perfmux_flop.io.fw_halted_ns := fw_halted_ns + perfmux_flop.io.meicidpl_ns := meicidpl_ns + perfmux_flop.io.icache_rd_valid := icache_rd_valid + perfmux_flop.io.icache_wr_valid := icache_wr_valid + perfmux_flop.io.perfcnt_halted := ((io.dec_tlu_dbg_halted & io.dcsr(DCSR_STOPC)) | io.dec_tlu_pmu_fw_halted) + perfmux_flop.io.mstatus_ns := mstatus_ns + perfmux_flop.io.scan_mode := io.scan_mode + perfmux_flop.io.free_l2clk := io.free_l2clk + //////////////////////////////////////////////////////////////////////////////////////////////////// + + //Inputs + perf_csrs.io.free_l2clk := io.free_l2clk + perf_csrs.io.scan_mode := io.scan_mode + perf_csrs.io.dec_tlu_dbg_halted := io.dec_tlu_dbg_halted + perf_csrs.io.dcsr := io.dcsr + perf_csrs.io.dec_tlu_pmu_fw_halted := io.dec_tlu_pmu_fw_halted + perf_csrs.io.mhpme_vec := mhpme_vec + perf_csrs.io.dec_csr_wen_r_mod := io.dec_csr_wen_r_mod + perf_csrs.io.dec_csr_wraddr_r := io.dec_csr_wraddr_r + perf_csrs.io.dec_csr_wrdata_r := io.dec_csr_wrdata_r + perf_csrs.io.mhpmc_inc_r := perfmux_flop.io.mhpmc_inc_r + perf_csrs.io.mhpmc_inc_r_d1 := perfmux_flop.io.mhpmc_inc_r_d1 + perf_csrs.io.perfcnt_halted_d1 := perfmux_flop.io.perfcnt_halted_d1 + //Outputs + // mhpmc3h := perf_csrs.io.mhpmc3h + // mhpmc3 := perf_csrs.io.mhpmc3 + // mhpmc4h := perf_csrs.io.mhpmc4h + // mhpmc4 := perf_csrs.io.mhpmc4 + // mhpmc5h := perf_csrs.io.mhpmc5h + // mhpmc5 := perf_csrs.io.mhpmc5 + // mhpmc6h := perf_csrs.io.mhpmc6h + // mhpmc6 := perf_csrs.io.mhpmc6 + // mhpme3 := perf_csrs.io.mhpme3 + // mhpme4 := perf_csrs.io.mhpme4 + // mhpme5 := perf_csrs.io.mhpme5 + // mhpme6 := perf_csrs.io.mhpme6 + io.dec_tlu_perfcnt0 := perf_csrs.io.dec_tlu_perfcnt0 + io.dec_tlu_perfcnt1 := perf_csrs.io.dec_tlu_perfcnt1 + io.dec_tlu_perfcnt2 := perf_csrs.io.dec_tlu_perfcnt2 + io.dec_tlu_perfcnt3 := perf_csrs.io.dec_tlu_perfcnt3 + //---------------------------------------------------------------------- + // Performance Monitor Counters section ends + //---------------------------------------------------------------------- + // ---------------------------------------------------------------------- + + // MCOUNTINHIBIT(RW) + // [31:7] : Reserved, read 0x0 + // [6] : HPM6 disable + // [5] : HPM5 disable + // [4] : HPM4 disable + // [3] : HPM3 disable + // [2] : MINSTRET disable + // [1] : reserved, read 0x0 + // [0] : MCYCLE disable + + val wr_mcountinhibit_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCOUNTINHIBIT) + + val temp_ncount0 = WireInit(UInt(1.W),mcountinhibit(0)) + val temp_ncount1 = WireInit(UInt(1.W),mcountinhibit(1)) + val temp_ncount6_2 = WireInit(UInt(5.W),mcountinhibit(6,2)) + temp_ncount6_2 := withClock(io.csr_wr_clk){RegEnable(io.dec_csr_wrdata_r(6,2),0.U,wr_mcountinhibit_r.asBool)} + + temp_ncount0 := withClock(io.csr_wr_clk){RegEnable(io.dec_csr_wrdata_r(0),0.U,wr_mcountinhibit_r.asBool)} + mcountinhibit := Cat(temp_ncount6_2, 0.U(1.W),temp_ncount0) + //-------------------------------------------------------------------------------- + // trace + //-------------------------------------------------------------------------------- + + io.dec_tlu_i0_valid_wb1 := !io.dec_tlu_trace_disable & io.i0_valid_wb + io.dec_tlu_i0_exc_valid_wb1 := !io.dec_tlu_trace_disable & (io.i0_exception_valid_r_d1 | perfmux_flop.io.lsu_i0_exc_r_d1 | (io.trigger_hit_r_d1 & !io.trigger_hit_dmode_r_d1)) + val dec_tlu_exc_cause_wb1_raw = Fill(5,!io.dec_tlu_trace_disable) & io.exc_cause_wb + val dec_tlu_int_valid_wb1_raw = !io.dec_tlu_trace_disable & io.interrupt_valid_r_d1 + + // skid buffer for ints, reduces trace port count by 1 + val dec_tlu_exc_cause_wb2 = rvdffie(dec_tlu_exc_cause_wb1_raw,clock,reset.asAsyncReset(),io.scan_mode) + val dec_tlu_int_valid_wb2 = rvdffie(dec_tlu_int_valid_wb1_raw,clock,reset.asAsyncReset(),io.scan_mode) + //skid for ints + io.dec_tlu_exc_cause_wb1 := Mux(dec_tlu_int_valid_wb2, dec_tlu_exc_cause_wb2, dec_tlu_exc_cause_wb1_raw) + io.dec_tlu_int_valid_wb1 := dec_tlu_int_valid_wb2 + io.dec_tlu_mtval_wb1 := mtval + + // end trace + //-------------------------------------------------------------------------------- + // CSR read mux + // io.dec_csr_rddata_d:=0.U + io.dec_csr_rddata_d:=Mux1H(Seq( + io.csr_pkt.csr_misa.asBool -> 0x40001104.U(32.W), + io.csr_pkt.csr_mvendorid.asBool -> 0x00000045.U(32.W), + io.csr_pkt.csr_marchid.asBool -> 0x00000010.U(32.W), + io.csr_pkt.csr_mimpid.asBool -> 0x3.U(32.W), + io.csr_pkt.csr_mhartid.asBool -> Cat(io.core_id,0.U(4.W)), + io.csr_pkt.csr_mstatus.asBool -> Cat(0.U(19.W), 3.U(2.W), 0.U(3.W), io.mstatus(1), 0.U(3.W), io.mstatus(0), 0.U(3.W)), + io.csr_pkt.csr_mtvec.asBool -> Cat(io.mtvec(30,1), 0.U(1.W), io.mtvec(0)), + io.csr_pkt.csr_mip.asBool -> Cat(0.U(1.W), io.mip(5,3), 0.U(16.W), io.mip(2), 0.U(3.W), io.mip(1), 0.U(3.W), io.mip(0), 0.U(3.W)), + io.csr_pkt.csr_mie.asBool -> Cat(0.U(1.W), mie(5,3), 0.U(16.W), mie(2), 0.U(3.W), mie(1), 0.U(3.W), mie(0), 0.U(3.W)), + io.csr_pkt.csr_mcyclel.asBool -> mcyclel(31,0), + io.csr_pkt.csr_mcycleh.asBool -> mcycleh_inc(31,0), + io.csr_pkt.csr_minstretl.asBool -> minstretl_read(31,0), + io.csr_pkt.csr_minstreth.asBool -> minstreth_read(31,0), + io.csr_pkt.csr_mscratch.asBool -> mscratch(31,0), + io.csr_pkt.csr_mepc.asBool -> Cat(io.mepc,0.U(1.W)), + io.csr_pkt.csr_mcause.asBool -> mcause(31,0), + io.csr_pkt.csr_mscause.asBool -> Cat(0.U(28.W), mscause(3,0)), + io.csr_pkt.csr_mtval.asBool -> mtval(31,0), + io.csr_pkt.csr_mrac.asBool -> mrac(31,0), + io.csr_pkt.csr_mdseac.asBool -> mdseac(31,0), + io.csr_pkt.csr_meivt.asBool -> Cat(meivt, 0.U(10.W)), + io.csr_pkt.csr_meihap.asBool -> Cat(meivt, meihap, 0.U(2.W)), + io.csr_pkt.csr_meicurpl.asBool -> Cat(0.U(28.W), meicurpl(3,0)), + io.csr_pkt.csr_meicidpl.asBool -> Cat(0.U(28.W), perfmux_flop.io.meicidpl(3,0)), + io.csr_pkt.csr_meipt.asBool -> Cat(0.U(28.W), meipt(3,0)), + io.csr_pkt.csr_mcgc.asBool -> Cat(0.U(22.W), mcgc(9,0)), + io.csr_pkt.csr_mfdc.asBool -> Cat(0.U(13.W), mfdc(18,0)), + io.csr_pkt.csr_dcsr.asBool -> Cat(0x4000.U(16.W), io.dcsr(15,2), 3.U(2.W)), + io.csr_pkt.csr_dpc.asBool -> Cat(io.dpc, 0.U(1.W)), + io.csr_pkt.csr_dicad0.asBool -> dicad0(31,0), + io.csr_pkt.csr_dicad0h.asBool -> dicad0h(31,0), + io.csr_pkt.csr_dicad1.asBool -> dicad1(31,0), + io.csr_pkt.csr_dicawics.asBool -> Cat(0.U(7.W), dicawics(16), 0.U(2.W), dicawics(15,14), 0.U(3.W), dicawics(13,0), 0.U(3.W)), + io.csr_pkt.csr_mtsel.asBool -> Cat(0.U(30.W), mtsel(1,0)), + io.csr_pkt.csr_mtdata1.asBool -> mtdata1_tsel_out(31,0), + io.csr_pkt.csr_mtdata2.asBool -> mtdata2_tsel_out(31,0), + io.csr_pkt.csr_micect.asBool -> micect(31,0), + io.csr_pkt.csr_miccmect.asBool -> miccmect(31,0), + io.csr_pkt.csr_mdccmect.asBool -> mdccmect(31,0), + io.csr_pkt.csr_mhpmc3.asBool -> perf_csrs.io.mhpmc3(31,0), + io.csr_pkt.csr_mhpmc4.asBool -> perf_csrs.io.mhpmc4(31,0), + io.csr_pkt.csr_mhpmc5.asBool -> perf_csrs.io.mhpmc5(31,0), + io.csr_pkt.csr_mhpmc6.asBool -> perf_csrs.io.mhpmc6(31,0), + io.csr_pkt.csr_mhpmc3h.asBool -> perf_csrs.io.mhpmc3h(31,0), + io.csr_pkt.csr_mhpmc4h.asBool -> perf_csrs.io.mhpmc4h(31,0), + io.csr_pkt.csr_mhpmc5h.asBool -> perf_csrs.io.mhpmc5h(31,0), + io.csr_pkt.csr_mhpmc6h.asBool -> perf_csrs.io.mhpmc6h(31,0), + io.csr_pkt.csr_mfdht.asBool -> Cat(0.U(26.W), mfdht(5,0)), + io.csr_pkt.csr_mfdhs.asBool -> Cat(0.U(30.W), mfdhs(1,0)), + io.csr_pkt.csr_mhpme3.asBool -> Cat(0.U(22.W), perf_csrs.io.mhpme3(9,0)), + io.csr_pkt.csr_mhpme4.asBool -> Cat(0.U(22.W), perf_csrs.io.mhpme4(9,0)), + io.csr_pkt.csr_mhpme5.asBool -> Cat(0.U(22.W),perf_csrs.io.mhpme5(9,0)), + io.csr_pkt.csr_mhpme6.asBool -> Cat(0.U(22.W),perf_csrs.io.mhpme6(9,0)), + io.csr_pkt.csr_mcountinhibit.asBool -> Cat(0.U(25.W), mcountinhibit(6,0)), + io.csr_pkt.csr_mpmc.asBool -> Cat(0.U(30.W), mpmc, 0.U(1.W)), + io.dec_timer_read_d.asBool -> io.dec_timer_rddata_d(31,0) + )) } - // ---------------------------------------------------------------------- - // MTDATA2 (R/W) - // [31:0] : Trigger Data 2 - // If the DMODE bit is set, tdata2 can only be updated in debug_mode - val wr_mtdata2_t_r = VecInit.tabulate(4)(i => io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTDATA2) & (mtsel === i.U(2.W)) & (~io.mtdata1_t(i)(MTDATA1_DMODE) | io.dbg_tlu_halted_f)) -for(i <- 0 until 4) { mtdata2_t(i) := rvdffe(io.dec_csr_wrdata_r,wr_mtdata2_t_r(i).asBool,clock,io.scan_mode)} +class perf_csr extends Module with CSRs with lib with RequireAsyncReset{ + val io = IO(new Bundle{ + val free_l2clk = Input(Clock()) + val scan_mode = Input(Bool()) + val dec_tlu_dbg_halted = Input(UInt(1.W)) + val dcsr = Input(UInt(16.W)) + val dec_tlu_pmu_fw_halted = Input(UInt(1.W)) + val mhpme_vec = Input(Vec(4,UInt(10.W))) + val dec_csr_wen_r_mod = Input(UInt(1.W)) + val dec_csr_wraddr_r = Input(UInt(12.W)) + val dec_csr_wrdata_r = Input(UInt(32.W)) + val mhpmc_inc_r = Input(Vec(4,UInt(1.W))) + val mhpmc_inc_r_d1 = Input(Vec(4,UInt(1.W))) + val perfcnt_halted_d1 = Input(Bool()) + + + val mhpmc3h = Output(UInt(32.W)) + val mhpmc3 = Output(UInt(32.W)) + val mhpmc4h = Output(UInt(32.W)) + val mhpmc4 = Output(UInt(32.W)) + val mhpmc5h = Output(UInt(32.W)) + val mhpmc5 = Output(UInt(32.W)) + val mhpmc6h = Output(UInt(32.W)) + val mhpmc6 = Output(UInt(32.W)) + val mhpme3 = Output(UInt(10.W)) + val mhpme4 = Output(UInt(10.W)) + val mhpme5 = Output(UInt(10.W)) + val mhpme6 = Output(UInt(10.W)) + val dec_tlu_perfcnt0 = Output(UInt(1.W)) + val dec_tlu_perfcnt1 = Output(UInt(1.W)) + val dec_tlu_perfcnt2 = Output(UInt(1.W)) + val dec_tlu_perfcnt3 = Output(UInt(1.W)) + }) + val perfcnt_halted = ((io.dec_tlu_dbg_halted & io.dcsr(DCSR_STOPC)) | io.dec_tlu_pmu_fw_halted) + val perfcnt_during_sleep = (Fill(4,!(io.dec_tlu_dbg_halted & io.dcsr(DCSR_STOPC)))) & Cat(io.mhpme_vec(3)(9),io.mhpme_vec(2)(9),io.mhpme_vec(1)(9),io.mhpme_vec(0)(9)) + + + io.dec_tlu_perfcnt0 := io.mhpmc_inc_r_d1(0) & !(io.perfcnt_halted_d1 & !perfcnt_during_sleep(0)) + io.dec_tlu_perfcnt1 := io.mhpmc_inc_r_d1(1) & !(io.perfcnt_halted_d1 & !perfcnt_during_sleep(1)) + io.dec_tlu_perfcnt2 := io.mhpmc_inc_r_d1(2) & !(io.perfcnt_halted_d1 & !perfcnt_during_sleep(2)) + io.dec_tlu_perfcnt3 := io.mhpmc_inc_r_d1(3) & !(io.perfcnt_halted_d1 & !perfcnt_during_sleep(3)) + + // ---------------------------------------------------------------------- + // MHPMC3H(RW), MHPMC3(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 3 + + val mhpmc3_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC3) + val mhpmc3_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep(0)) & ((io.mhpmc_inc_r(0)).orR) + val mhpmc3_wr_en = mhpmc3_wr_en0 | mhpmc3_wr_en1 + + + val mhpmc3_incr = Cat(io.mhpmc3h(31,0),io.mhpmc3(31,0)) + Cat(0.U(63.W),1.U(1.W)) + val mhpmc3_ns = Mux(mhpmc3_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc3_incr(31,0)) + + io.mhpmc3 := rvdffe(mhpmc3_ns,mhpmc3_wr_en.asBool,io.free_l2clk,io.scan_mode) + + val mhpmc3h_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC3H) + val mhpmc3h_wr_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1 + val mhpmc3h_ns = Mux(mhpmc3h_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc3_incr(63,32)) + + io.mhpmc3h := rvdffe(mhpmc3h_ns, mhpmc3h_wr_en.asBool, io.free_l2clk, io.scan_mode) + + + // ---------------------------------------------------------------------- + // MHPMC4H(RW), MHPMC4(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 4 + + val mhpmc4_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC4) + val mhpmc4_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep(1)) & ((io.mhpmc_inc_r(1)).orR) + val mhpmc4_wr_en = mhpmc4_wr_en0 | mhpmc4_wr_en1 -val mtdata2_tsel_out = Mux1H((0 until 4).map(i =>(mtsel === i.U(2.W)) -> mtdata2_t(i))) -for(i <- 0 until 4) {io.trigger_pkt_any(i).tdata2 := mtdata2_t(i)} + val mhpmc4_incr = Cat(io.mhpmc4h(31,0),io.mhpmc4(31,0)) + Cat(0.U(63.W),1.U(1.W)) + val mhpmc4_ns = Mux(mhpmc4_wr_en0.asBool, io.dec_csr_wrdata_r(31,0), mhpmc4_incr(31,0)) + io.mhpmc4 := rvdffe(mhpmc4_ns, mhpmc4_wr_en.asBool, io.free_l2clk, io.scan_mode) + + val mhpmc4h_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC4H) + val mhpmc4h_wr_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1 + val mhpmc4h_ns = Mux(mhpmc4h_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc4_incr(63,32)) + io.mhpmc4h := rvdffe(mhpmc4h_ns, mhpmc4h_wr_en.asBool, io.free_l2clk, io.scan_mode) + + // ---------------------------------------------------------------------- + // MHPMC5H(RW), MHPMC5(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 5 + + val mhpmc5_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC5) + val mhpmc5_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep(2)) & ((io.mhpmc_inc_r(2)).orR) + val mhpmc5_wr_en = mhpmc5_wr_en0 | mhpmc5_wr_en1 + + val mhpmc5_incr = Cat(io.mhpmc5h(31,0),io.mhpmc5(31,0)) + Cat(0.U(63.W),1.U(1.W)) + val mhpmc5_ns = Mux(mhpmc5_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc5_incr(31,0)) + + io.mhpmc5 := rvdffe(mhpmc5_ns, mhpmc5_wr_en.asBool, io.free_l2clk, io.scan_mode) + + val mhpmc5h_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC5H) + val mhpmc5h_wr_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1 + val mhpmc5h_ns = Mux(mhpmc5h_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc5_incr(63,32)) + + io.mhpmc5h := rvdffe(mhpmc5h_ns, mhpmc5h_wr_en.asBool, io.free_l2clk, io.scan_mode) - //---------------------------------------------------------------------- - // Performance Monitor Counters section starts - //---------------------------------------------------------------------- + // ---------------------------------------------------------------------- + // MHPMC6H(RW), MHPMC6(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 6 + + val mhpmc6_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC6) + val mhpmc6_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep(3)) & ((io.mhpmc_inc_r(3)).orR) + val mhpmc6_wr_en = mhpmc6_wr_en0 | mhpmc6_wr_en1 + + val mhpmc6_incr = Cat(io.mhpmc6h(31,0),io.mhpmc6(31,0)) + Cat(0.U(63.W),1.U(1.W)) + val mhpmc6_ns = Mux(mhpmc6_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc6_incr(31,0)) - - // Pack the event selects into a vector for genvar - mhpme_vec(0) := mhpme3 - mhpme_vec(1) := mhpme4 - mhpme_vec(2) := mhpme5 - mhpme_vec(3) := mhpme6 + io.mhpmc6 := rvdffe(mhpmc6_ns, mhpmc6_wr_en.asBool, io.free_l2clk, io.scan_mode) - import inst_pkt_t._ - // only consider committed itypes + val mhpmc6h_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC6H) + val mhpmc6h_wr_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1 + val mhpmc6h_ns = Mux(mhpmc6h_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc6_incr(63,32)) + + io.mhpmc6h := rvdffe(mhpmc6h_ns, mhpmc6h_wr_en.asBool, io.free_l2clk, io.scan_mode) + // ---------------------------------------------------------------------- + // MHPME3(RW) + // [9:0] : Hardware Performance Monitor Event 3 + + // we only have events 0-56 with holes, 512-516, HPME* are WARL so zero otherwise. + val zero_event_r = ((io.dec_csr_wrdata_r(9,0) > 516.U(10.W)) | (io.dec_csr_wrdata_r(31,10).orR) | + ((io.dec_csr_wrdata_r(9,0) < 512.U(10.W)) & (io.dec_csr_wrdata_r(9,0) > 56.U(10.W))) | + ((io.dec_csr_wrdata_r(9,0) < 54.U(10.W)) & (io.dec_csr_wrdata_r(9,0) > 50.U(10.W))) | + (io.dec_csr_wrdata_r(9,0) === 29.U(10.W)) | (io.dec_csr_wrdata_r(9,0) === 33.U(10.W))) + + val event_r = Mux(zero_event_r, 0.U(10.W), io.dec_csr_wrdata_r(9,0)) + val wr_mhpme3_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPME3) + + io.mhpme3 := rvdffe(event_r,wr_mhpme3_r,clock,io.scan_mode)//withClock(io.active_clk){RegEnable(event_r,0.U,wr_mhpme3_r.asBool)} + // ---------------------------------------------------------------------- + // MHPME4(RW) + // [9:0] : Hardware Performance Monitor Event 4 + + val wr_mhpme4_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPME4) + io.mhpme4 := rvdffe(event_r,wr_mhpme4_r,clock,io.scan_mode)//withClock(io.active_clk){RegEnable(event_saturate_r,0.U,wr_mhpme4_r.asBool)} + + // ---------------------------------------------------------------------- + // MHPME5(RW) + // [9:0] : Hardware Performance Monitor Event 5 + + val wr_mhpme5_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPME5) + io.mhpme5 := rvdffe(event_r,wr_mhpme5_r,clock,io.scan_mode)//withClock(io.active_clk){RegEnable(event_saturate_r,0.U,wr_mhpme5_r.asBool)} + + // ---------------------------------------------------------------------- + // MHPME6(RW) + // [9:0] : Hardware Performance Monitor Event 6 + + val wr_mhpme6_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPME6) + io.mhpme6 := rvdffe(event_r,wr_mhpme6_r,clock,io.scan_mode)//withClock(io.active_clk){RegEnable(event_saturate_r,0.U,wr_mhpme6_r.asBool)} +} +class perf_mux_and_flops extends Module with CSRs with lib with RequireAsyncReset{ + val io = IO(new Bundle{ + val mhpmc_inc_r = Output(Vec(4,UInt(1.W))) + val mcountinhibit = Input(UInt(7.W)) + val mhpme_vec =Input(Vec(4,UInt(10.W))) + val ifu_pmu_ic_hit = Input(UInt(1.W)) + val ifu_pmu_ic_miss = Input(UInt(1.W)) + val tlu_i0_commit_cmt = Input(UInt(1.W)) + val illegal_r = Input(UInt(1.W)) + val exu_pmu_i0_pc4 = Input(UInt(1.W)) + val ifu_pmu_instr_aligned = Input(UInt(1.W)) + val dec_pmu_instr_decoded = Input(UInt(1.W)) + val dec_tlu_packet_r = Input(new trap_pkt_t) + val exu_pmu_i0_br_misp = Input(UInt(1.W)) + val dec_pmu_decode_stall = Input(UInt(1.W)) + val exu_pmu_i0_br_ataken = Input(UInt(1.W)) + val ifu_pmu_fetch_stall = Input(UInt(1.W)) + val dec_pmu_postsync_stall = Input(UInt(1.W)) + val dec_pmu_presync_stall = Input(UInt(1.W)) + val lsu_store_stall_any = Input(UInt(1.W)) + val dma_dccm_stall_any = Input(UInt(1.W)) + val dma_iccm_stall_any = Input(UInt(1.W)) + val i0_exception_valid_r = Input(UInt(1.W)) + val dec_tlu_pmu_fw_halted = Input(UInt(1.W)) + val dma_pmu_any_read = Input(UInt(1.W)) + val dma_pmu_any_write = Input(UInt(1.W)) + val dma_pmu_dccm_read = Input(UInt(1.W)) + val dma_pmu_dccm_write = Input(UInt(1.W)) + val lsu_pmu_load_external_r = Input(UInt(1.W)) + val lsu_pmu_store_external_r = Input(UInt(1.W)) + val mstatus = Output(UInt(2.W)) + + val mie = Input(UInt(6.W)) + val ifu_pmu_bus_trxn = Input(UInt(1.W)) + val lsu_pmu_bus_trxn = Input(UInt(1.W)) + val lsu_pmu_bus_misaligned = Input(UInt(1.W)) + val ifu_pmu_bus_error = Input(UInt(1.W)) + val lsu_pmu_bus_error = Input(UInt(1.W)) + val ifu_pmu_bus_busy = Input(UInt(1.W)) + val lsu_pmu_bus_busy = Input(UInt(1.W)) + val i0_trigger_hit_r = Input(UInt(1.W)) + val lsu_exc_valid_r = Input(UInt(1.W)) + val take_timer_int = Input(UInt(1.W)) + val take_int_timer0_int = Input(UInt(1.W)) + val take_int_timer1_int = Input(UInt(1.W)) + val take_ext_int = Input(UInt(1.W)) + val tlu_flush_lower_r = Input(UInt(1.W)) + val dec_tlu_br0_error_r = Input(UInt(1.W)) + val rfpc_i0_r = Input(UInt(1.W)) + val dec_tlu_br0_start_error_r = Input(UInt(1.W)) - val pmu_i0_itype_qual = io.dec_tlu_packet_r.pmu_i0_itype & Fill(4,io.tlu_i0_commit_cmt) - val mhpmc_inc_r = Wire(Vec(4,UInt(1.W))) - val mhpmc_inc_r_d1 = Wire(Vec(4,UInt(1.W))) - - // Generate the muxed incs for all counters based on event type - for(i <- 0 until 4) { - mhpmc_inc_r(i) := (~mcountinhibit(i+3) & (Mux1H(Seq( - (mhpme_vec(i) === MHPME_CLK_ACTIVE ).asBool -> 1.U, - (mhpme_vec(i) === MHPME_ICACHE_HIT ).asBool -> io.ifu_pmu_ic_hit, - (mhpme_vec(i) === MHPME_ICACHE_MISS ).asBool -> io.ifu_pmu_ic_miss, - (mhpme_vec(i) === MHPME_INST_COMMIT ).asBool -> (io.tlu_i0_commit_cmt & ~io.illegal_r), - (mhpme_vec(i) === MHPME_INST_COMMIT_16B ).asBool -> (io.tlu_i0_commit_cmt & ~io.exu_pmu_i0_pc4 & ~io.illegal_r), - (mhpme_vec(i) === MHPME_INST_COMMIT_32B ).asBool -> (io.tlu_i0_commit_cmt & io.exu_pmu_i0_pc4 & ~io.illegal_r), - (mhpme_vec(i) === MHPME_INST_ALIGNED ).asBool -> io.ifu_pmu_instr_aligned, - (mhpme_vec(i) === MHPME_INST_DECODED ).asBool -> io.dec_pmu_instr_decoded, - (mhpme_vec(i) === MHPME_DECODE_STALL ).asBool -> io.dec_pmu_decode_stall, - (mhpme_vec(i) === MHPME_INST_MUL ).asBool -> (pmu_i0_itype_qual === MUL), - (mhpme_vec(i) === MHPME_INST_DIV ).asBool -> (io.dec_tlu_packet_r.pmu_divide & io.tlu_i0_commit_cmt), - (mhpme_vec(i) === MHPME_INST_LOAD ).asBool -> (pmu_i0_itype_qual === LOAD), - (mhpme_vec(i) === MHPME_INST_STORE ).asBool -> (pmu_i0_itype_qual === STORE), - (mhpme_vec(i) === MHPME_INST_MALOAD ).asBool -> (pmu_i0_itype_qual === LOAD & io.dec_tlu_packet_r.pmu_lsu_misaligned), - (mhpme_vec(i) === MHPME_INST_MASTORE ).asBool -> (pmu_i0_itype_qual === STORE & io.dec_tlu_packet_r.pmu_lsu_misaligned.asBool), - (mhpme_vec(i) === MHPME_INST_ALU ).asBool -> (pmu_i0_itype_qual === ALU), - (mhpme_vec(i) === MHPME_INST_CSRREAD ).asBool -> (pmu_i0_itype_qual === CSRREAD), - (mhpme_vec(i) === MHPME_INST_CSRWRITE).asBool -> (pmu_i0_itype_qual === CSRWRITE), - (mhpme_vec(i) === MHPME_INST_CSRRW ).asBool -> (pmu_i0_itype_qual === CSRRW), - (mhpme_vec(i) === MHPME_INST_EBREAK ).asBool -> (pmu_i0_itype_qual === EBREAK), - (mhpme_vec(i) === MHPME_INST_ECALL ).asBool -> (pmu_i0_itype_qual === ECALL), - (mhpme_vec(i) === MHPME_INST_FENCE ).asBool -> (pmu_i0_itype_qual === FENCE), - (mhpme_vec(i) === MHPME_INST_FENCEI ).asBool -> (pmu_i0_itype_qual === FENCEI), - (mhpme_vec(i) === MHPME_INST_MRET ).asBool -> (pmu_i0_itype_qual === MRET), - (mhpme_vec(i) === MHPME_INST_BRANCH ).asBool -> ((pmu_i0_itype_qual === CONDBR) | (pmu_i0_itype_qual === JAL)), - (mhpme_vec(i) === MHPME_BRANCH_MP ).asBool -> (io.exu_pmu_i0_br_misp & io.tlu_i0_commit_cmt), - (mhpme_vec(i) === MHPME_BRANCH_TAKEN ).asBool -> (io.exu_pmu_i0_br_ataken & io.tlu_i0_commit_cmt), - (mhpme_vec(i) === MHPME_BRANCH_NOTP ).asBool -> (io.dec_tlu_packet_r.pmu_i0_br_unpred & io.tlu_i0_commit_cmt), - (mhpme_vec(i) === MHPME_FETCH_STALL ).asBool -> io.ifu_pmu_fetch_stall, - (mhpme_vec(i) === MHPME_DECODE_STALL ).asBool -> io.dec_pmu_decode_stall, - (mhpme_vec(i) === MHPME_POSTSYNC_STALL ).asBool -> io.dec_pmu_postsync_stall, - (mhpme_vec(i) === MHPME_PRESYNC_STALL ).asBool -> io.dec_pmu_presync_stall, - (mhpme_vec(i) === MHPME_LSU_SB_WB_STALL ).asBool -> io.lsu_store_stall_any, - (mhpme_vec(i) === MHPME_DMA_DCCM_STALL ).asBool -> io.dma_dccm_stall_any, - (mhpme_vec(i) === MHPME_DMA_ICCM_STALL ).asBool -> io.dma_iccm_stall_any, - (mhpme_vec(i) === MHPME_EXC_TAKEN ).asBool -> (io.i0_exception_valid_r | io.i0_trigger_hit_r | io.lsu_exc_valid_r), - (mhpme_vec(i) === MHPME_TIMER_INT_TAKEN ).asBool -> (io.take_timer_int | io.take_int_timer0_int | io.take_int_timer1_int), - (mhpme_vec(i) === MHPME_EXT_INT_TAKEN ).asBool -> io.take_ext_int, - (mhpme_vec(i) === MHPME_FLUSH_LOWER ).asBool -> io.tlu_flush_lower_r, - (mhpme_vec(i) === MHPME_BR_ERROR ).asBool -> ((io.dec_tlu_br0_error_r | io.dec_tlu_br0_start_error_r) & io.rfpc_i0_r), - (mhpme_vec(i) === MHPME_IBUS_TRANS ).asBool -> io.ifu_pmu_bus_trxn, - (mhpme_vec(i) === MHPME_DBUS_TRANS ).asBool -> io.lsu_pmu_bus_trxn, - (mhpme_vec(i) === MHPME_DBUS_MA_TRANS ).asBool -> io.lsu_pmu_bus_misaligned, - (mhpme_vec(i) === MHPME_IBUS_ERROR ).asBool -> io.ifu_pmu_bus_error, - (mhpme_vec(i) === MHPME_DBUS_ERROR ).asBool -> io.lsu_pmu_bus_error, - (mhpme_vec(i) === MHPME_IBUS_STALL ).asBool -> io.ifu_pmu_bus_busy, - (mhpme_vec(i) === MHPME_DBUS_STALL ).asBool -> io.lsu_pmu_bus_busy, - (mhpme_vec(i) === MHPME_INT_DISABLED ).asBool -> (~io.mstatus(MSTATUS_MIE)), - (mhpme_vec(i) === MHPME_INT_STALLED ).asBool -> (~io.mstatus(MSTATUS_MIE) & (io.mip(5,0) & mie(5,0)).orR), - (mhpme_vec(i) === MHPME_INST_BITMANIP ).asBool -> (pmu_i0_itype_qual === BITMANIPU), - (mhpme_vec(i) === MHPME_DBUS_LOAD ).asBool -> (io.tlu_i0_commit_cmt & io.lsu_pmu_load_external_r), - (mhpme_vec(i) === MHPME_DBUS_STORE ).asBool -> (io.tlu_i0_commit_cmt & io.lsu_pmu_store_external_r), - // These count even during sleep - (mhpme_vec(i) === MHPME_SLEEP_CYC ).asBool -> io.dec_tlu_pmu_fw_halted, - (mhpme_vec(i) === MHPME_DMA_READ_ALL ).asBool -> io.dma_pmu_any_read, - (mhpme_vec(i) === MHPME_DMA_WRITE_ALL ).asBool -> io.dma_pmu_any_write, - (mhpme_vec(i) === MHPME_DMA_READ_DCCM ).asBool -> io.dma_pmu_dccm_read, - (mhpme_vec(i) === MHPME_DMA_WRITE_DCCM ).asBool -> io.dma_pmu_dccm_write )))) - } - - mhpmc_inc_r_d1(0) := withClock(io.free_clk){RegNext(mhpmc_inc_r(0),0.U)} - mhpmc_inc_r_d1(1) := withClock(io.free_clk){RegNext(mhpmc_inc_r(1),0.U)} - mhpmc_inc_r_d1(2) := withClock(io.free_clk){RegNext(mhpmc_inc_r(2),0.U)} - mhpmc_inc_r_d1(3) := withClock(io.free_clk){RegNext(mhpmc_inc_r(3),0.U)} - val perfcnt_halted_d1 = withClock(io.free_clk){RegNext(perfcnt_halted,0.U)} + val mcyclel_cout_f =Output(Bool()) + val minstret_enable_f =Output(Bool()) + val minstretl_cout_f =Output(Bool()) + val fw_halted =Output(Bool()) + val meicidpl =Output(UInt(4.W)) + val icache_rd_valid_f =Output(Bool()) + val icache_wr_valid_f =Output(Bool()) + val mhpmc_inc_r_d1 =Output(Vec(4,UInt(1.W))) + val perfcnt_halted_d1 =Output(Bool()) + val mdseac_locked_f =Output(Bool()) + val lsu_single_ecc_error_r_d1 =Output(Bool()) + val lsu_exc_valid_r_d1 =Output(Bool()) + val lsu_i0_exc_r_d1 =Output(Bool()) + val take_ext_int_start_d1 =Output(Bool()) + val take_ext_int_start_d2 =Output(Bool()) + val take_ext_int_start_d3 =Output(Bool()) + val ext_int_freeze_d1 =Output(Bool()) + val mip = Output(UInt(6.W)) + val mdseac_locked_ns = Input(Bool()) + val lsu_single_ecc_error_r = Input(Bool()) + val lsu_i0_exc_r = Input(Bool()) + val take_ext_int_start = Input(Bool()) + val ext_int_freeze = Input(Bool()) + val mip_ns = Input(UInt(6.W)) + val mcyclel_cout = Input(Bool()) + val wr_mcycleh_r = Input(Bool()) + val mcyclel_cout_in = Input(Bool()) + val minstret_enable = Input(Bool()) + val minstretl_cout_ns = Input(Bool()) + val fw_halted_ns = Input(Bool()) + val meicidpl_ns = Input(UInt(4.W)) + val icache_rd_valid = Input(Bool()) + val icache_wr_valid = Input(Bool()) + // val mhpmc_inc_r = Input(Bool()) + val perfcnt_halted = Input(Bool()) + val mstatus_ns = Input(UInt(2.W)) + val scan_mode = Input(Bool()) + val free_l2clk = Input(Clock()) - perfcnt_halted := ((io.dec_tlu_dbg_halted & io.dcsr(DCSR_STOPC)) | io.dec_tlu_pmu_fw_halted) - val perfcnt_during_sleep = (Fill(4,~(io.dec_tlu_dbg_halted & io.dcsr(DCSR_STOPC)))) & Cat(mhpme_vec(3)(9),mhpme_vec(2)(9),mhpme_vec(1)(9),mhpme_vec(0)(9)) + }) + import inst_pkt_t._ + val pmu_i0_itype_qual = io.dec_tlu_packet_r.pmu_i0_itype & Fill(4,io.tlu_i0_commit_cmt) + for(i <- 0 until 4) { + io.mhpmc_inc_r(i) := (~io.mcountinhibit(i+3) & (Mux1H(Seq( + (io.mhpme_vec(i) === MHPME_CLK_ACTIVE ).asBool -> 1.U, + (io.mhpme_vec(i) === MHPME_ICACHE_HIT ).asBool -> io.ifu_pmu_ic_hit, + (io.mhpme_vec(i) === MHPME_ICACHE_MISS ).asBool -> io.ifu_pmu_ic_miss, + (io.mhpme_vec(i) === MHPME_INST_COMMIT ).asBool -> (io.tlu_i0_commit_cmt & ~io.illegal_r), + (io.mhpme_vec(i) === MHPME_INST_COMMIT_16B ).asBool -> (io.tlu_i0_commit_cmt & ~io.exu_pmu_i0_pc4 & ~io.illegal_r), + (io.mhpme_vec(i) === MHPME_INST_COMMIT_32B ).asBool -> (io.tlu_i0_commit_cmt & io.exu_pmu_i0_pc4 & ~io.illegal_r), - io.dec_tlu_perfcnt0 := mhpmc_inc_r_d1(0) & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep(0)) - io.dec_tlu_perfcnt1 := mhpmc_inc_r_d1(1) & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep(1)) - io.dec_tlu_perfcnt2 := mhpmc_inc_r_d1(2) & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep(2)) - io.dec_tlu_perfcnt3 := mhpmc_inc_r_d1(3) & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep(3)) + (io.mhpme_vec(i) === MHPME_INST_ALIGNED ).asBool -> io.ifu_pmu_instr_aligned, + (io.mhpme_vec(i) === MHPME_INST_DECODED ).asBool -> io.dec_pmu_instr_decoded, + (io.mhpme_vec(i) === MHPME_DECODE_STALL ).asBool -> io.dec_pmu_decode_stall, + (io.mhpme_vec(i) === MHPME_INST_MUL ).asBool -> (pmu_i0_itype_qual === MUL), + (io.mhpme_vec(i) === MHPME_INST_DIV ).asBool -> (io.dec_tlu_packet_r.pmu_divide & io.tlu_i0_commit_cmt & !io.illegal_r), + (io.mhpme_vec(i) === MHPME_INST_LOAD ).asBool -> (pmu_i0_itype_qual === LOAD), + (io.mhpme_vec(i) === MHPME_INST_STORE ).asBool -> (pmu_i0_itype_qual === STORE), + (io.mhpme_vec(i) === MHPME_INST_MALOAD ).asBool -> (pmu_i0_itype_qual === LOAD & io.dec_tlu_packet_r.pmu_lsu_misaligned), + (io.mhpme_vec(i) === MHPME_INST_MASTORE ).asBool -> (pmu_i0_itype_qual === STORE & io.dec_tlu_packet_r.pmu_lsu_misaligned.asBool), - // ---------------------------------------------------------------------- - // MHPMC3H(RW), MHPMC3(RW) - // [63:32][31:0] : Hardware Performance Monitor Counter 3 + (io.mhpme_vec(i) === MHPME_INST_ALU ).asBool -> (pmu_i0_itype_qual === ALU), + (io.mhpme_vec(i) === MHPME_INST_CSRREAD ).asBool -> (pmu_i0_itype_qual === CSRREAD), + (io.mhpme_vec(i) === MHPME_INST_CSRWRITE).asBool -> (pmu_i0_itype_qual === CSRWRITE), + (io.mhpme_vec(i) === MHPME_INST_CSRRW ).asBool -> (pmu_i0_itype_qual === CSRRW), + (io.mhpme_vec(i) === MHPME_INST_EBREAK ).asBool -> (pmu_i0_itype_qual === EBREAK), + (io.mhpme_vec(i) === MHPME_INST_ECALL ).asBool -> (pmu_i0_itype_qual === ECALL), + (io.mhpme_vec(i) === MHPME_INST_FENCE ).asBool -> (pmu_i0_itype_qual === FENCE), + (io.mhpme_vec(i) === MHPME_INST_FENCEI ).asBool -> (pmu_i0_itype_qual === FENCEI), + (io.mhpme_vec(i) === MHPME_INST_MRET ).asBool -> (pmu_i0_itype_qual === MRET), + (io.mhpme_vec(i) === MHPME_INST_BRANCH ).asBool -> ((pmu_i0_itype_qual === CONDBR) | (pmu_i0_itype_qual === JAL)), - val mhpmc3_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC3) - val mhpmc3_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep(0)) & ((mhpmc_inc_r(0)).orR) - val mhpmc3_wr_en = mhpmc3_wr_en0 | mhpmc3_wr_en1 + (io.mhpme_vec(i) === MHPME_BRANCH_MP ).asBool -> (io.exu_pmu_i0_br_misp & io.tlu_i0_commit_cmt & !io.illegal_r), + (io.mhpme_vec(i) === MHPME_BRANCH_TAKEN ).asBool -> (io.exu_pmu_i0_br_ataken & io.tlu_i0_commit_cmt & !io.illegal_r), + (io.mhpme_vec(i) === MHPME_BRANCH_NOTP ).asBool -> (io.dec_tlu_packet_r.pmu_i0_br_unpred & io.tlu_i0_commit_cmt & !io.illegal_r), + (io.mhpme_vec(i) === MHPME_FETCH_STALL ).asBool -> io.ifu_pmu_fetch_stall, + (io.mhpme_vec(i) === MHPME_DECODE_STALL ).asBool -> io.dec_pmu_decode_stall, + (io.mhpme_vec(i) === MHPME_POSTSYNC_STALL ).asBool -> io.dec_pmu_postsync_stall, + (io.mhpme_vec(i) === MHPME_PRESYNC_STALL ).asBool -> io.dec_pmu_presync_stall, + (io.mhpme_vec(i) === MHPME_LSU_SB_WB_STALL ).asBool -> io.lsu_store_stall_any, + (io.mhpme_vec(i) === MHPME_DMA_DCCM_STALL ).asBool -> io.dma_dccm_stall_any, + (io.mhpme_vec(i) === MHPME_DMA_ICCM_STALL ).asBool -> io.dma_iccm_stall_any, + (io.mhpme_vec(i) === MHPME_EXC_TAKEN ).asBool -> (io.i0_exception_valid_r | io.i0_trigger_hit_r | io.lsu_exc_valid_r), + (io.mhpme_vec(i) === MHPME_TIMER_INT_TAKEN ).asBool -> (io.take_timer_int | io.take_int_timer0_int | io.take_int_timer1_int), + (io.mhpme_vec(i) === MHPME_EXT_INT_TAKEN ).asBool -> io.take_ext_int, + (io.mhpme_vec(i) === MHPME_FLUSH_LOWER ).asBool -> io.tlu_flush_lower_r, + (io.mhpme_vec(i) === MHPME_BR_ERROR ).asBool -> ((io.dec_tlu_br0_error_r | io.dec_tlu_br0_start_error_r) & io.rfpc_i0_r), - - mhpmc3_incr := Cat(mhpmc3h(31,0),mhpmc3(31,0)) + Cat(0.U(63.W),mhpmc_inc_r(0)) - val mhpmc3_ns = Mux(mhpmc3_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc3_incr(31,0)) - - mhpmc3 := rvdffe(mhpmc3_ns,mhpmc3_wr_en.asBool,clock,io.scan_mode) - - val mhpmc3h_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC3H) - val mhpmc3h_wr_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1 - val mhpmc3h_ns = Mux(mhpmc3h_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc3_incr(63,32)) - - mhpmc3h := rvdffe(mhpmc3h_ns, mhpmc3h_wr_en.asBool, clock, io.scan_mode) - // ---------------------------------------------------------------------- - // MHPMC4H(RW), MHPMC4(RW) - // [63:32][31:0] : Hardware Performance Monitor Counter 4 - - val mhpmc4_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC4) - val mhpmc4_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep(1)) & ((mhpmc_inc_r(1)).orR) - val mhpmc4_wr_en = mhpmc4_wr_en0 | mhpmc4_wr_en1 + (io.mhpme_vec(i) === MHPME_IBUS_TRANS ).asBool -> io.ifu_pmu_bus_trxn, + (io.mhpme_vec(i) === MHPME_DBUS_TRANS ).asBool -> io.lsu_pmu_bus_trxn, + (io.mhpme_vec(i) === MHPME_DBUS_MA_TRANS ).asBool -> io.lsu_pmu_bus_misaligned, + (io.mhpme_vec(i) === MHPME_IBUS_ERROR ).asBool -> io.ifu_pmu_bus_error, + (io.mhpme_vec(i) === MHPME_DBUS_ERROR ).asBool -> io.lsu_pmu_bus_error, + (io.mhpme_vec(i) === MHPME_IBUS_STALL ).asBool -> io.ifu_pmu_bus_busy, + (io.mhpme_vec(i) === MHPME_DBUS_STALL ).asBool -> io.lsu_pmu_bus_busy, + (io.mhpme_vec(i) === MHPME_INT_DISABLED ).asBool -> (~io.mstatus(MSTATUS_MIE)), + (io.mhpme_vec(i) === MHPME_INT_STALLED ).asBool -> (~io.mstatus(MSTATUS_MIE) & (io.mip(5,0) & io.mie(5,0)).orR), + (io.mhpme_vec(i) === MHPME_INST_BITMANIP ).asBool -> (pmu_i0_itype_qual === BITMANIPU), + (io.mhpme_vec(i) === MHPME_DBUS_LOAD ).asBool -> (io.tlu_i0_commit_cmt & io.lsu_pmu_load_external_r & !io.illegal_r), + (io.mhpme_vec(i) === MHPME_DBUS_STORE ).asBool -> (io.tlu_i0_commit_cmt & io.lsu_pmu_store_external_r & !io.illegal_r), + // These count even during sleep + (io.mhpme_vec(i) === MHPME_SLEEP_CYC ).asBool -> io.dec_tlu_pmu_fw_halted, + (io.mhpme_vec(i) === MHPME_DMA_READ_ALL ).asBool -> io.dma_pmu_any_read, + (io.mhpme_vec(i) === MHPME_DMA_WRITE_ALL ).asBool -> io.dma_pmu_any_write, + (io.mhpme_vec(i) === MHPME_DMA_READ_DCCM ).asBool -> io.dma_pmu_dccm_read, + (io.mhpme_vec(i) === MHPME_DMA_WRITE_DCCM ).asBool -> io.dma_pmu_dccm_write )))) + } - mhpmc4_incr := Cat(mhpmc4h(31,0),mhpmc4(31,0)) + Cat(0.U(63.W),mhpmc_inc_r(1)) - val mhpmc4_ns = Mux(mhpmc4_wr_en0.asBool, io.dec_csr_wrdata_r(31,0), mhpmc4_incr(31,0)) - mhpmc4 := rvdffe(mhpmc4_ns, mhpmc4_wr_en.asBool, clock, io.scan_mode) - - val mhpmc4h_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC4H) - val mhpmc4h_wr_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1 - val mhpmc4h_ns = Mux(mhpmc4h_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc4_incr(63,32)) - mhpmc4h := rvdffe(mhpmc4h_ns, mhpmc4h_wr_en.asBool, clock, io.scan_mode) - - // ---------------------------------------------------------------------- - // MHPMC5H(RW), MHPMC5(RW) - // [63:32][31:0] : Hardware Performance Monitor Counter 5 - - val mhpmc5_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC5) - val mhpmc5_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep(2)) & ((mhpmc_inc_r(2)).orR) - val mhpmc5_wr_en = mhpmc5_wr_en0 | mhpmc5_wr_en1 - - mhpmc5_incr := Cat(mhpmc5h(31,0),mhpmc5(31,0)) + Cat(0.U(63.W),mhpmc_inc_r(2)) - val mhpmc5_ns = Mux(mhpmc5_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc5_incr(31,0)) - - mhpmc5 := rvdffe(mhpmc5_ns, mhpmc5_wr_en.asBool, clock, io.scan_mode) - - val mhpmc5h_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC5H) - val mhpmc5h_wr_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1 - val mhpmc5h_ns = Mux(mhpmc5h_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc5_incr(63,32)) - - mhpmc5h := rvdffe(mhpmc5h_ns, mhpmc5h_wr_en.asBool, clock, io.scan_mode) - // ---------------------------------------------------------------------- - // MHPMC6H(RW), MHPMC6(RW) - // [63:32][31:0] : Hardware Performance Monitor Counter 6 - - val mhpmc6_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC6) - val mhpmc6_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep(3)) & ((mhpmc_inc_r(3)).orR) - val mhpmc6_wr_en = mhpmc6_wr_en0 | mhpmc6_wr_en1 - - mhpmc6_incr := Cat(mhpmc6h(31,0),mhpmc6(31,0)) + Cat(0.U(63.W),mhpmc_inc_r(3)) - val mhpmc6_ns = Mux(mhpmc6_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc6_incr(31,0)) - - mhpmc6 := rvdffe(mhpmc6_ns, mhpmc6_wr_en.asBool, clock, io.scan_mode) - - val mhpmc6h_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC6H) - val mhpmc6h_wr_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1 - val mhpmc6h_ns = Mux(mhpmc6h_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc6_incr(63,32)) - - mhpmc6h := rvdffe(mhpmc6h_ns, mhpmc6h_wr_en.asBool, clock, io.scan_mode) - - // ---------------------------------------------------------------------- - // MHPME3(RW) - // [9:0] : Hardware Performance Monitor Event 3 - - // we only have events 0-56, 512-516, HPME* are WARL so saturate otherwise - val event_saturate_r = Mux(((io.dec_csr_wrdata_r(9,0) > 516.U(10.W)) | (io.dec_csr_wrdata_r(31,10)).orR), 516.U(10.W), io.dec_csr_wrdata_r(9,0)) - - val wr_mhpme3_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPME3) - - mhpme3 := withClock(io.active_clk){RegEnable(event_saturate_r,0.U,wr_mhpme3_r.asBool)} - // ---------------------------------------------------------------------- - // MHPME4(RW) - // [9:0] : Hardware Performance Monitor Event 4 - - val wr_mhpme4_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPME4) - mhpme4 := withClock(io.active_clk){RegEnable(event_saturate_r,0.U,wr_mhpme4_r.asBool)} - - // ---------------------------------------------------------------------- - // MHPME5(RW) - // [9:0] : Hardware Performance Monitor Event 5 - - val wr_mhpme5_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPME5) - mhpme5 := withClock(io.active_clk){RegEnable(event_saturate_r,0.U,wr_mhpme5_r.asBool)} - - // ---------------------------------------------------------------------- - // MHPME6(RW) - // [9:0] : Hardware Performance Monitor Event 6 - - val wr_mhpme6_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPME6) - mhpme6 := withClock(io.active_clk){RegEnable(event_saturate_r,0.U,wr_mhpme6_r.asBool)} - //---------------------------------------------------------------------- - // Performance Monitor Counters section ends - //---------------------------------------------------------------------- - // ---------------------------------------------------------------------- - - // MCOUNTINHIBIT(RW) - // [31:7] : Reserved, read 0x0 - // [6] : HPM6 disable - // [5] : HPM5 disable - // [4] : HPM4 disable - // [3] : HPM3 disable - // [2] : MINSTRET disable - // [1] : reserved, read 0x0 - // [0] : MCYCLE disable - - val wr_mcountinhibit_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCOUNTINHIBIT) - - val temp_ncount0 = WireInit(UInt(1.W),mcountinhibit(0)) - val temp_ncount1 = WireInit(UInt(1.W),mcountinhibit(1)) - val temp_ncount6_2 = WireInit(UInt(5.W),mcountinhibit(6,2)) - temp_ncount6_2 := withClock(io.active_clk){RegEnable(io.dec_csr_wrdata_r(6,2),0.U,wr_mcountinhibit_r.asBool)} - - temp_ncount0 := withClock(io.active_clk){RegEnable(io.dec_csr_wrdata_r(0),0.U,wr_mcountinhibit_r.asBool)} - mcountinhibit := Cat(temp_ncount6_2, 0.U(1.W),temp_ncount0) - //-------------------------------------------------------------------------------- - // trace - //-------------------------------------------------------------------------------- - - - - val trace_tclk = rvclkhdr(clock, (io.i0_valid_wb | io.exc_or_int_valid_r_d1 | io.interrupt_valid_r_d1 | io.dec_tlu_i0_valid_wb1 | - io.dec_tlu_i0_exc_valid_wb1 | io.dec_tlu_int_valid_wb1 | io.clk_override).asBool, io.scan_mode) - - io.dec_tlu_i0_valid_wb1 := withClock(trace_tclk){RegNext(io.i0_valid_wb,0.U)} - io.dec_tlu_i0_exc_valid_wb1 := withClock(trace_tclk){RegNext((io.i0_exception_valid_r_d1 | io.lsu_i0_exc_r_d1 | (io.trigger_hit_r_d1 & ~io.trigger_hit_dmode_r_d1)),0.U)} - io.dec_tlu_exc_cause_wb1 := withClock(trace_tclk){RegNext(io.exc_cause_wb,0.U)} - io.dec_tlu_int_valid_wb1 := withClock(trace_tclk){RegNext(io.interrupt_valid_r_d1,0.U)} - - io.dec_tlu_mtval_wb1 := mtval - - // end trace - //-------------------------------------------------------------------------------- - // CSR read mux - io.dec_csr_rddata_d:=Mux1H(Seq( - io.csr_pkt.csr_misa.asBool -> 0x40001104.U(32.W), - io.csr_pkt.csr_mvendorid.asBool -> 0x00000045.U(32.W), - io.csr_pkt.csr_marchid.asBool -> 0x00000010.U(32.W), - io.csr_pkt.csr_mimpid.asBool -> 0x2.U(32.W), - io.csr_pkt.csr_mhartid.asBool -> Cat(io.core_id,0.U(4.W)), - io.csr_pkt.csr_mstatus.asBool -> Cat(0.U(19.W), 3.U(2.W), 0.U(3.W), io.mstatus(1), 0.U(3.W), io.mstatus(0), 0.U(3.W)), - io.csr_pkt.csr_mtvec.asBool -> Cat(io.mtvec(30,1), 0.U(1.W), io.mtvec(0)), - io.csr_pkt.csr_mip.asBool -> Cat(0.U(1.W), io.mip(5,3), 0.U(16.W), io.mip(2), 0.U(3.W), io.mip(1), 0.U(3.W), io.mip(0), 0.U(3.W)), - io.csr_pkt.csr_mie.asBool -> Cat(0.U(1.W), mie(5,3), 0.U(16.W), mie(2), 0.U(3.W), mie(1), 0.U(3.W), mie(0), 0.U(3.W)), - io.csr_pkt.csr_mcyclel.asBool -> mcyclel(31,0), - io.csr_pkt.csr_mcycleh.asBool -> mcycleh_inc(31,0), - io.csr_pkt.csr_minstretl.asBool -> minstretl_read(31,0), - io.csr_pkt.csr_minstreth.asBool -> minstreth_read(31,0), - io.csr_pkt.csr_mscratch.asBool -> mscratch(31,0), - io.csr_pkt.csr_mepc.asBool -> Cat(io.mepc,0.U(1.W)), - io.csr_pkt.csr_mcause.asBool -> mcause(31,0), - io.csr_pkt.csr_mscause.asBool -> Cat(0.U(28.W), mscause(3,0)), - io.csr_pkt.csr_mtval.asBool -> mtval(31,0), - io.csr_pkt.csr_mrac.asBool -> mrac(31,0), - io.csr_pkt.csr_mdseac.asBool -> mdseac(31,0), - io.csr_pkt.csr_meivt.asBool -> Cat(meivt, 0.U(10.W)), - io.csr_pkt.csr_meihap.asBool -> Cat(meivt, meihap, 0.U(2.W)), - io.csr_pkt.csr_meicurpl.asBool -> Cat(0.U(28.W), meicurpl(3,0)), - io.csr_pkt.csr_meicidpl.asBool -> Cat(0.U(28.W), meicidpl(3,0)), - io.csr_pkt.csr_meipt.asBool -> Cat(0.U(28.W), meipt(3,0)), - io.csr_pkt.csr_mcgc.asBool -> Cat(0.U(23.W), mcgc(8,0)), - io.csr_pkt.csr_mfdc.asBool -> Cat(0.U(13.W), mfdc(18,0)), - io.csr_pkt.csr_dcsr.asBool -> Cat(0x4000.U(16.W), io.dcsr(15,2), 3.U(2.W)), - io.csr_pkt.csr_dpc.asBool -> Cat(io.dpc, 0.U(1.W)), - io.csr_pkt.csr_dicad0.asBool -> dicad0(31,0), - io.csr_pkt.csr_dicad0h.asBool -> dicad0h(31,0), - io.csr_pkt.csr_dicad1.asBool -> dicad1(31,0), - io.csr_pkt.csr_dicawics.asBool -> Cat(0.U(7.W), dicawics(16), 0.U(2.W), dicawics(15,14), 0.U(3.W), dicawics(13,0), 0.U(3.W)), - io.csr_pkt.csr_mtsel.asBool -> Cat(0.U(30.W), mtsel(1,0)), - io.csr_pkt.csr_mtdata1.asBool -> mtdata1_tsel_out(31,0), - io.csr_pkt.csr_mtdata2.asBool -> mtdata2_tsel_out(31,0), - io.csr_pkt.csr_micect.asBool -> micect(31,0), - io.csr_pkt.csr_miccmect.asBool -> miccmect(31,0), - io.csr_pkt.csr_mdccmect.asBool -> mdccmect(31,0), - io.csr_pkt.csr_mhpmc3.asBool -> mhpmc3(31,0), - io.csr_pkt.csr_mhpmc4.asBool -> mhpmc4(31,0), - io.csr_pkt.csr_mhpmc5.asBool -> mhpmc5(31,0), - io.csr_pkt.csr_mhpmc6.asBool -> mhpmc6(31,0), - io.csr_pkt.csr_mhpmc3h.asBool -> mhpmc3h(31,0), - io.csr_pkt.csr_mhpmc4h.asBool -> mhpmc4h(31,0), - io.csr_pkt.csr_mhpmc5h.asBool -> mhpmc5h(31,0), - io.csr_pkt.csr_mhpmc6h.asBool -> mhpmc6h(31,0), - io.csr_pkt.csr_mfdht.asBool -> Cat(0.U(26.W), mfdht(5,0)), - io.csr_pkt.csr_mfdhs.asBool -> Cat(0.U(30.W), mfdhs(1,0)), - io.csr_pkt.csr_mhpme3.asBool -> Cat(0.U(22.W), mhpme3(9,0)), - io.csr_pkt.csr_mhpme4.asBool -> Cat(0.U(22.W), mhpme4(9,0)), - io.csr_pkt.csr_mhpme5.asBool -> Cat(0.U(22.W),mhpme5(9,0)), - io.csr_pkt.csr_mhpme6.asBool -> Cat(0.U(22.W),mhpme6(9,0)), - io.csr_pkt.csr_mcountinhibit.asBool -> Cat(0.U(25.W), mcountinhibit(6,0)), - io.csr_pkt.csr_mpmc.asBool -> Cat(0.U(30.W), mpmc, 0.U(1.W)), - io.dec_timer_read_d.asBool -> io.dec_timer_rddata_d(31,0) - )) - + + + + if(FAST_INTERRUPT_REDIRECT) { + io.mdseac_locked_f :=rvdffie(io.mdseac_locked_ns,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.lsu_single_ecc_error_r_d1 :=rvdffie(io.lsu_single_ecc_error_r,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.lsu_exc_valid_r_d1 :=rvdffie(io.lsu_exc_valid_r,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.lsu_i0_exc_r_d1 :=rvdffie(io.lsu_i0_exc_r,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.take_ext_int_start_d1 :=rvdffie(io.take_ext_int_start,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.take_ext_int_start_d2 :=rvdffie(io.take_ext_int_start_d1,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.take_ext_int_start_d3 :=rvdffie(io.take_ext_int_start_d2,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.ext_int_freeze_d1 :=rvdffie(io.ext_int_freeze,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.mip :=rvdffie(io.mip_ns,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.mcyclel_cout_f :=rvdffie(io.mcyclel_cout & ~io.wr_mcycleh_r & io.mcyclel_cout_in,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.minstret_enable_f :=rvdffie(io.minstret_enable,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.minstretl_cout_f :=rvdffie(io.minstretl_cout_ns,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.fw_halted :=rvdffie(io.fw_halted_ns,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.meicidpl :=rvdffie(io.meicidpl_ns,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.icache_rd_valid_f :=rvdffie(io.icache_rd_valid,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.icache_wr_valid_f :=rvdffie(io.icache_wr_valid,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.mhpmc_inc_r_d1 :=rvdffie(io.mhpmc_inc_r,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.perfcnt_halted_d1 :=rvdffie(io.perfcnt_halted,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.mstatus :=rvdffie(io.mstatus_ns,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + } + else{ + io.take_ext_int_start_d1 := 0.U + io.take_ext_int_start_d2 :=0.U + io.take_ext_int_start_d3 :=0.U + io.ext_int_freeze_d1 :=0.U + io.mdseac_locked_f :=rvdffie(io.mdseac_locked_ns,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.lsu_single_ecc_error_r_d1 :=rvdffie(io.lsu_single_ecc_error_r,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.lsu_exc_valid_r_d1 :=rvdffie(io.lsu_exc_valid_r,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.lsu_i0_exc_r_d1 :=rvdffie(io.lsu_i0_exc_r,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.mip :=rvdffie(io.mip_ns,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.mcyclel_cout_f :=rvdffie((io.mcyclel_cout & !io.wr_mcycleh_r & io.mcyclel_cout_in),io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.minstret_enable_f :=rvdffie(io.minstret_enable,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.minstretl_cout_f :=rvdffie(io.minstretl_cout_ns,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.fw_halted :=rvdffie(io.fw_halted_ns,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.meicidpl :=rvdffie(io.meicidpl_ns,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.icache_rd_valid_f :=rvdffie(io.icache_rd_valid,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.icache_wr_valid_f :=rvdffie(io.icache_wr_valid,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.mhpmc_inc_r_d1 :=rvdffie(io.mhpmc_inc_r,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.perfcnt_halted_d1 :=rvdffie(io.perfcnt_halted,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + io.mstatus :=rvdffie(io.mstatus_ns,io.free_l2clk,reset.asAsyncReset(),io.scan_mode) + } } +class int_exc extends Module with CSRs with lib with RequireAsyncReset{ + val io = IO(new Bundle{ + val mhwakeup_ready = Output(Bool()) + val ext_int_ready = Output(Bool()) + val ce_int_ready = Output(Bool()) + val soft_int_ready = Output(Bool()) + val timer_int_ready = Output(Bool()) + val int_timer0_int_hold = Output(UInt(1.W)) + val int_timer1_int_hold = Output(UInt(1.W)) + val internal_dbg_halt_timers = Output(UInt(1.W)) + val take_ext_int_start = Output(UInt(1.W)) + val ext_int_freeze_d1 = Input(UInt(1.W)) + val take_ext_int_start_d1 = Input(UInt(1.W)) + val take_ext_int_start_d2 = Input(UInt(1.W)) + val take_ext_int_start_d3 = Input(UInt(1.W)) + val ext_int_freeze = Output(UInt(1.W)) + val take_ext_int = Output(UInt(1.W)) + val fast_int_meicpct = Output(UInt(1.W)) + val ignore_ext_int_due_to_lsu_stall = Output(UInt(1.W)) + val take_ce_int = Output(UInt(1.W)) + val take_soft_int = Output(UInt(1.W)) + val take_timer_int = Output(UInt(1.W)) + val take_int_timer0_int = Output(UInt(1.W)) + val take_int_timer1_int = Output(UInt(1.W)) + val take_reset = Output(UInt(1.W)) + val take_nmi = Output(UInt(1.W)) + val synchronous_flush_r = Output(UInt(1.W)) + val tlu_flush_lower_r = Output(UInt(1.W)) + val dec_tlu_flush_lower_wb = Output(UInt(1.W)) + val dec_tlu_flush_lower_r = Output(UInt(1.W)) + val dec_tlu_flush_path_r = Output(UInt(31.W)) + val interrupt_valid_r_d1 = Output(Bool()) + val i0_exception_valid_r_d1 = Output(UInt(1.W)) + val exc_or_int_valid_r_d1 = Output(UInt(1.W)) + val exc_cause_wb = Output(UInt(5.W)) + val i0_valid_wb = Output(UInt(1.W)) + val trigger_hit_r_d1 = Output(UInt(1.W)) + val take_nmi_r_d1 = Output(UInt(1.W)) + val pause_expired_wb = Output(UInt(1.W)) + val interrupt_valid_r = Output(UInt(1.W)) + val exc_cause_r = Output(UInt(5.W)) + val i0_exception_valid_r = Output(UInt(1.W)) + val tlu_flush_path_r_d1 = Output(UInt(31.W)) + val exc_or_int_valid_r =Output(UInt(1.W)) + + val free_l2clk = Input(Clock()) + val scan_mode = Input(Bool()) + val dec_csr_stall_int_ff = Input(UInt(1.W)) + val mstatus_mie_ns = Input(UInt(1.W)) + val mip = Input(UInt(6.W)) + val mie_ns = Input(UInt(6.W)) + val mret_r = Input(UInt(1.W)) + val pmu_fw_tlu_halted_f = Input(UInt(1.W)) + val int_timer0_int_hold_f = Input(UInt(1.W)) + val int_timer1_int_hold_f = Input(UInt(1.W)) + val internal_dbg_halt_mode_f = Input(UInt(1.W)) + val dcsr_single_step_running = Input(UInt(1.W)) + val internal_dbg_halt_mode = Input(UInt(1.W)) + val dec_tlu_i0_valid_r = Input(UInt(1.W)) + val internal_pmu_fw_halt_mode = Input(UInt(1.W)) + val i_cpu_halt_req_d1 = Input(UInt(1.W)) + val ebreak_to_debug_mode_r = Input(UInt(1.W)) + val lsu_fir_error = Input(UInt(2.W)) + val csr_pkt = Input(new dec_tlu_csr_pkt) + val dec_csr_any_unq_d = Input(UInt(1.W)) + val lsu_fastint_stall_any = Input(UInt(1.W)) + val reset_delayed = Input(UInt(1.W)) + val mpc_reset_run_req = Input(UInt(1.W)) + val nmi_int_detected = Input(UInt(1.W)) + val dcsr_single_step_running_f = Input(UInt(1.W)) + val dcsr_single_step_done_f = Input(UInt(1.W)) + val dcsr = Input(UInt(16.W)) + val mtvec = Input(UInt(31.W)) + + val tlu_i0_commit_cmt = Input(UInt(1.W)) + val i0_trigger_hit_r = Input(UInt(1.W)) + val pause_expired_r = Input(UInt(1.W)) + val nmi_vec = Input(UInt(31.W)) + val lsu_i0_rfnpc_r = Input(UInt(1.W)) + val fence_i_r = Input(UInt(1.W)) + val iccm_repair_state_rfnpc = Input(UInt(1.W)) + val i_cpu_run_req_d1 = Input(UInt(1.W)) + val rfpc_i0_r = Input(UInt(1.W)) + val lsu_exc_valid_r = Input(UInt(1.W)) + val trigger_hit_dmode_r = Input(UInt(1.W)) + val take_halt = Input(UInt(1.W)) + val rst_vec = Input(UInt(31.W)) + val lsu_fir_addr = Input(UInt(31.W)) + val dec_tlu_i0_pc_r = Input(UInt(31.W)) + val npc_r = Input(UInt(31.W)) + val mepc = Input(UInt(31.W)) + val debug_resume_req_f = Input(UInt(1.W)) + val dpc = Input(UInt(31.W)) + val npc_r_d1 = Input(UInt(31.W)) + val tlu_flush_lower_r_d1 = Input(UInt(1.W)) + val dec_tlu_dbg_halted = Input(UInt(1.W)) + val ebreak_r = Input(UInt(1.W)) + val ecall_r = Input(UInt(1.W)) + val illegal_r = Input(UInt(1.W)) + val inst_acc_r = Input(UInt(1.W)) + val lsu_i0_exc_r = Input(UInt(1.W)) + val lsu_error_pkt_r = Flipped(Valid(new lsu_error_pkt_t)) + val dec_tlu_wr_pause_r_d1 = Input(UInt(1.W)) + }) + val lsu_exc_ma_r = io.lsu_i0_exc_r & !io.lsu_error_pkt_r.bits.exc_type + val lsu_exc_acc_r = io.lsu_i0_exc_r & io.lsu_error_pkt_r.bits.exc_type + val lsu_exc_st_r = io.lsu_i0_exc_r & io.lsu_error_pkt_r.bits.inst_type + // + // Exceptions + // + // - MEPC <- PC + // - PC <- MTVEC, assert flush_lower + // - MCAUSE <- cause + // - MSCAUSE <- secondary cause + // - MTVAL <- + // - MPIE <- MIE + // - MIE <- 0 + // + io.i0_exception_valid_r := (io.ebreak_r | io.ecall_r | io.illegal_r | io.inst_acc_r) & ~io.rfpc_i0_r & ~io.dec_tlu_dbg_halted + + // Cause: + // + // 0x2 : illegal + // 0x3 : breakpoint + // 0xb : Environment call M-mode + + io.exc_cause_r := ~Fill(5,io.take_nmi) & Mux1H(Seq( + (io.take_ext_int).asBool -> 0x0b.U(5.W), + (io.take_timer_int ).asBool -> 0x07.U(5.W), + (io.take_soft_int).asBool -> 0x03.U(5.W), + (io.take_int_timer0_int ).asBool -> 0x1d.U(5.W), + (io.take_int_timer1_int).asBool -> 0x1c.U(5.W), + (io.take_ce_int).asBool -> 0x1e.U(5.W), + (io.illegal_r).asBool -> 0x02.U(5.W), + (io.ecall_r).asBool -> 0x0b.U(5.W), + (io.inst_acc_r ).asBool -> 0x01.U(5.W), + ((io.ebreak_r | io.i0_trigger_hit_r)).asBool -> 0x03.U(5.W), + (lsu_exc_ma_r & !lsu_exc_st_r).asBool -> 0x04.U(5.W), + (lsu_exc_acc_r & !lsu_exc_st_r).asBool -> 0x05.U(5.W), + (lsu_exc_ma_r & lsu_exc_st_r ).asBool -> 0x06.U(5.W), + (lsu_exc_acc_r & lsu_exc_st_r ).asBool -> 0x07.U(5.W) + )) + // + // Interrupts + // + // exceptions that are committed have already happened and will cause an int at E4 to wait a cycle + // or more if MSTATUS[MIE] is cleared. + // + // -in priority order, highest to lowest + // -single cycle window where a csr write to MIE/MSTATUS is at E4 when the other conditions for externals are met. + // Hold off externals for a cycle to make sure we are consistent with what was just written + io.mhwakeup_ready := !io.dec_csr_stall_int_ff & io.mstatus_mie_ns & io.mip(MIP_MEIP) & io.mie_ns(MIE_MEIE) + io.ext_int_ready := !io.dec_csr_stall_int_ff & io.mstatus_mie_ns & io.mip(MIP_MEIP) & io.mie_ns(MIE_MEIE) & ~io.ignore_ext_int_due_to_lsu_stall + io.ce_int_ready := !io.dec_csr_stall_int_ff & io.mstatus_mie_ns & io.mip(MIP_MCEIP) & io.mie_ns(MIE_MCEIE) + io.soft_int_ready := !io.dec_csr_stall_int_ff & io.mstatus_mie_ns & io.mip(MIP_MSIP) & io.mie_ns(MIE_MSIE) + io.timer_int_ready := !io.dec_csr_stall_int_ff & io.mstatus_mie_ns & io.mip(MIP_MTIP) & io.mie_ns(MIE_MTIE) + + // MIP for internal timers pulses for 1 clock, resets the timer counter. Mip won't hold past the various stall conditions. + val int_timer0_int_possible = io.mstatus_mie_ns & io.mie_ns(MIE_MITIE0) + val int_timer0_int_ready = io.mip(MIP_MITIP0) & int_timer0_int_possible + val int_timer1_int_possible = io.mstatus_mie_ns & io.mie_ns(MIE_MITIE1) + val int_timer1_int_ready = io.mip(MIP_MITIP1) & int_timer1_int_possible + + // Internal timers pulse and reset. If core is PMU/FW halted, the pulse will cause an exit from halt, but won't stick around + // Make it sticky, also for 1 cycle stall conditions. + val int_timer_stalled = io.dec_csr_stall_int_ff | io.synchronous_flush_r | io.exc_or_int_valid_r_d1 | io.mret_r + + io.int_timer0_int_hold := (int_timer0_int_ready & (io.pmu_fw_tlu_halted_f | int_timer_stalled)) | (int_timer0_int_possible & io.int_timer0_int_hold_f & ~io.interrupt_valid_r & ~io.take_ext_int_start & ~io.internal_dbg_halt_mode_f) + io.int_timer1_int_hold := (int_timer1_int_ready & (io.pmu_fw_tlu_halted_f | int_timer_stalled)) | (int_timer1_int_possible & io.int_timer1_int_hold_f & ~io.interrupt_valid_r & ~io.take_ext_int_start & ~io.internal_dbg_halt_mode_f) + + io.internal_dbg_halt_timers := io.internal_dbg_halt_mode_f & ~io.dcsr_single_step_running + + val block_interrupts = ((io.internal_dbg_halt_mode & (~io.dcsr_single_step_running | io.dec_tlu_i0_valid_r)) | io.internal_pmu_fw_halt_mode | io.i_cpu_halt_req_d1 | io.take_nmi | io.ebreak_to_debug_mode_r | io.synchronous_flush_r | io.exc_or_int_valid_r_d1 | io.mret_r | io.ext_int_freeze_d1) + + + if(FAST_INTERRUPT_REDIRECT) { + // take_ext_int_start_d1:=withClock(io.free_clk){RegNext(take_ext_int_start,0.U)} + // take_ext_int_start_d2:=withClock(io.free_clk){RegNext(take_ext_int_start_d1,0.U)} + // take_ext_int_start_d3:=withClock(io.free_clk){RegNext(take_ext_int_start_d2,0.U)} + // ext_int_freeze_d1 :=withClock(io.free_clk){RegNext(ext_int_freeze,0.U)} + io.take_ext_int_start := io.ext_int_ready & ~block_interrupts; + io.ext_int_freeze := io.take_ext_int_start | io.take_ext_int_start_d1 | io.take_ext_int_start_d2 | io.take_ext_int_start_d3 + io.take_ext_int := io.take_ext_int_start_d3 & ~io.lsu_fir_error.orR + io.fast_int_meicpct := io.csr_pkt.csr_meicpct & io.dec_csr_any_unq_d // MEICPCT becomes illegal if fast ints are enabled + io.ignore_ext_int_due_to_lsu_stall := io.lsu_fastint_stall_any + }else{ + io.take_ext_int_start := 0.U(1.W) + io.ext_int_freeze := 0.U(1.W) + // io.ext_int_freeze_d1 := 0.U(1.W) + // io.take_ext_int_start_d1 := 0.U(1.W) + // io.take_ext_int_start_d2 := 0.U(1.W) + // io.take_ext_int_start_d3 := 0.U(1.W) + io.fast_int_meicpct := 0.U(1.W) + io.ignore_ext_int_due_to_lsu_stall := 0.U(1.W) + io.take_ext_int := io.ext_int_ready & ~block_interrupts + } + + io.take_ce_int := io.ce_int_ready & ~io.ext_int_ready & ~block_interrupts + io.take_soft_int := io.soft_int_ready & ~io.ext_int_ready & ~io.ce_int_ready & ~block_interrupts + io.take_timer_int := io.timer_int_ready & ~io.soft_int_ready & ~io.ext_int_ready & ~io.ce_int_ready & ~block_interrupts + io.take_int_timer0_int := (int_timer0_int_ready | io.int_timer0_int_hold_f) & int_timer0_int_possible & ~io.dec_csr_stall_int_ff & ~io.timer_int_ready & ~io.soft_int_ready & ~io.ext_int_ready & ~io.ce_int_ready & ~block_interrupts + io.take_int_timer1_int := (int_timer1_int_ready | io.int_timer1_int_hold_f) & int_timer1_int_possible & ~io.dec_csr_stall_int_ff & ~(int_timer0_int_ready | io.int_timer0_int_hold_f) & ~io.timer_int_ready & ~io.soft_int_ready & ~io.ext_int_ready & ~io.ce_int_ready & ~block_interrupts + io.take_reset := io.reset_delayed & io.mpc_reset_run_req + io.take_nmi := io.nmi_int_detected & ~io.internal_pmu_fw_halt_mode & (~io.internal_dbg_halt_mode | (io.dcsr_single_step_running_f & io.dcsr(DCSR_STEPIE) & ~io.dec_tlu_i0_valid_r & ~io.dcsr_single_step_done_f))& ~io.synchronous_flush_r & ~io.mret_r & ~io.take_reset & ~io.ebreak_to_debug_mode_r & (~io.ext_int_freeze_d1 | (io.take_ext_int_start_d3 & io.lsu_fir_error.orR)) + + + + io.interrupt_valid_r := io.take_ext_int | io.take_timer_int | io.take_soft_int | io.take_nmi | io.take_ce_int | io.take_int_timer0_int | io.take_int_timer1_int + + + // Compute interrupt path: + // If vectored async is set in mtvec, flush path for interrupts is MTVEC + (4 * CAUSE); + val vectored_path = Cat(io.mtvec(30,1),0.U(1.W)) + Cat(0.U(25.W),io.exc_cause_r, 0.U(1.W)) ///After Combining Code revisit this + val interrupt_path = Mux(io.take_nmi.asBool, io.nmi_vec, Mux(io.mtvec(0) === 1.U, vectored_path, Cat(io.mtvec(30,1),0.U(1.W))))///After Combining Code revisit this + val sel_npc_r = io.lsu_i0_rfnpc_r | io.fence_i_r | io.iccm_repair_state_rfnpc | (io.i_cpu_run_req_d1 & ~io.interrupt_valid_r) | (io.rfpc_i0_r & ~io.dec_tlu_i0_valid_r) + val sel_npc_resume = (io.i_cpu_run_req_d1 & io.pmu_fw_tlu_halted_f) | io.pause_expired_r + val sel_fir_addr = io.take_ext_int_start_d3 & !(io.lsu_fir_error.orR) + io.synchronous_flush_r := io.i0_exception_valid_r | io.rfpc_i0_r | io.lsu_exc_valid_r | io.fence_i_r | io.lsu_i0_rfnpc_r | io.iccm_repair_state_rfnpc | io.debug_resume_req_f | sel_npc_resume | io.dec_tlu_wr_pause_r_d1 | io.i0_trigger_hit_r + io.tlu_flush_lower_r := io.interrupt_valid_r | io.mret_r | io.synchronous_flush_r | io.take_halt | io.take_reset | io.take_ext_int_start + ///After Combining Code revisit this + val tlu_flush_path_r = Mux(io.take_reset.asBool, io.rst_vec,Mux1H(Seq( + (sel_fir_addr).asBool -> io.lsu_fir_addr, + (io.take_nmi===0.U & sel_npc_r===1.U) -> io.npc_r, + (io.take_nmi===0.U & io.rfpc_i0_r===1.U & io.dec_tlu_i0_valid_r===1.U & sel_npc_r===0.U) -> io.dec_tlu_i0_pc_r, + (io.interrupt_valid_r===1.U & sel_fir_addr===0.U) -> interrupt_path, + ((io.i0_exception_valid_r | io.lsu_exc_valid_r | (io.i0_trigger_hit_r & ~io.trigger_hit_dmode_r)) & ~io.interrupt_valid_r & ~sel_fir_addr).asBool -> Cat(io.mtvec(30,1),0.U(1.W)), + (~io.take_nmi & io.mret_r).asBool -> io.mepc, + (~io.take_nmi & io.debug_resume_req_f).asBool -> io.dpc, + (~io.take_nmi & sel_npc_resume).asBool -> io.npc_r_d1 + ))) + + io.tlu_flush_path_r_d1:=rvdffpcie(tlu_flush_path_r,io.tlu_flush_lower_r,reset.asAsyncReset(),clock, io.scan_mode)//withClock(e4e5_int_clk){RegNext(tlu_flush_path_r,0.U)} ///After Combining Code revisit this + + io.dec_tlu_flush_lower_wb := io.tlu_flush_lower_r_d1 + // io.tlu_mem.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb + io.dec_tlu_flush_lower_r := io.tlu_flush_lower_r + io.dec_tlu_flush_path_r := tlu_flush_path_r ///After Combining Code revisit this + + // this is used to capture mepc, etc. + io.exc_or_int_valid_r := io.lsu_exc_valid_r | io.i0_exception_valid_r | io.interrupt_valid_r | (io.i0_trigger_hit_r & ~io.trigger_hit_dmode_r) + + io.interrupt_valid_r_d1 :=rvdffie(io.interrupt_valid_r, clock,reset.asAsyncReset(),io.scan_mode)//withClock(e4e5_int_clk){RegNext(interrupt_valid_r,0.U)} + io.i0_exception_valid_r_d1 :=rvdffie(io.i0_exception_valid_r, clock,reset.asAsyncReset(),io.scan_mode)//withClock(e4e5_int_clk){RegNext(i0_exception_valid_r,0.U)} + io.exc_or_int_valid_r_d1 :=rvdffie(io.exc_or_int_valid_r, clock,reset.asAsyncReset(),io.scan_mode)//withClock(e4e5_int_clk){RegNext(exc_or_int_valid_r,0.U)} + io.exc_cause_wb :=rvdffie(io.exc_cause_r, clock,reset.asAsyncReset(),io.scan_mode)//withClock(e4e5_int_clk){RegNext(exc_cause_r,0.U)} + io.i0_valid_wb :=rvdffie(io.tlu_i0_commit_cmt & !io.illegal_r, clock,reset.asAsyncReset(),io.scan_mode)//withClock(e4e5_int_clk){RegNext((tlu_i0_commit_cmt & ~illegal_r),0.U)} + io.trigger_hit_r_d1 :=rvdffie(io.i0_trigger_hit_r, clock,reset.asAsyncReset(),io.scan_mode)//withClock(e4e5_int_clk){RegNext(i0_trigger_hit_r,0.U)} + io.take_nmi_r_d1 :=rvdffie(io.take_nmi, clock,reset.asAsyncReset(),io.scan_mode)//withClock(e4e5_int_clk){RegNext(take_nmi,0.U)} + io.pause_expired_wb :=rvdffie(io.pause_expired_r, clock,reset.asAsyncReset(),io.scan_mode)//withClock(e4e5_int_clk){RegNext(pause_expired_r,0.U)} + +} class dec_decode_csr_read_IO extends Bundle{ val dec_csr_rdaddr_d=Input(UInt(12.W)) @@ -2549,7 +3171,7 @@ class dec_decode_csr_read extends Module with RequireAsyncReset{ val io=IO(new dec_decode_csr_read_IO) def pattern(y : List[Int]) = (0 until y.size).map(i=> if(y(i)>=0 & y(i)!='z') io.dec_csr_rdaddr_d(y(i)) else if(y(i)<0) !io.dec_csr_rdaddr_d(y(i).abs) else !io.dec_csr_rdaddr_d(0)).reduce(_&_) - // 'z' is used for !io.dec_csr_rdaddr_d(0) + // 'z' is used for !io.dec_csr_rdaddr_d(0) io.csr_pkt.csr_misa :=pattern(List(-11,-6,-5,-2,0)) io.csr_pkt.csr_mvendorid :=pattern(List(10,-7,-1,0)) io.csr_pkt.csr_marchid :=pattern(List(10,-7,1,'z')) @@ -2603,9 +3225,9 @@ class dec_decode_csr_read extends Module with RequireAsyncReset{ io.csr_pkt.csr_mitcnt0 :=pattern(List(6,-5,4,-2,'z')) io.csr_pkt.csr_mitcnt1 :=pattern(List(6,2,-1,0)) io.csr_pkt.csr_mpmc :=pattern(List(6,-4,-3,2,1)) - io.csr_pkt.csr_mcpc :=pattern(List(10,6,-4,-3,-2,1)) + // io.csr_pkt.csr_mcpc :=pattern(List(10,6,-4,-3,-2,1)) io.csr_pkt.csr_meicpct :=pattern(List(11,6,1,'z')) - io.csr_pkt.csr_mdeau :=pattern(List(-10,7,6,-3)) + // io.csr_pkt.csr_mdeau :=pattern(List(-10,7,6,-3)) io.csr_pkt.csr_micect :=pattern(List(6,5,-3,-1,'z')) io.csr_pkt.csr_miccmect :=pattern(List(6,5,-3,0)) io.csr_pkt.csr_mdccmect :=pattern(List(6,5,1,'z')) @@ -2617,25 +3239,25 @@ class dec_decode_csr_read extends Module with RequireAsyncReset{ io.csr_pkt.csr_dicad1 :=pattern(List(10,3,-2,1,'z')) io.csr_pkt.csr_dicago :=pattern(List(10,3,-2,1,0)) io.csr_pkt.presync := pattern(List(10,4,3,-1,0)) | pattern(List(-7,5,-4,-3,-2,'z')) | pattern(List(-6,-5,-4,-3,-2,1)) | - pattern(List(11,-4,-3,2,-1)) | pattern(List(11,-4,-3,1,'z')) | pattern(List(7,-5,-4,-3,-2,1)) + pattern(List(11,-4,-3,2,-1)) | pattern(List(11,-4,-3,1,'z')) | pattern(List(7,-5,-4,-3,-2,1)) io.csr_pkt.postsync := pattern(List(10,4,3,-1,0)) | pattern(List(-11,-6,-5,2,0)) | pattern(List(-7,6,-1,0)) | - pattern(List(10,-4,-3,0)) | pattern(List(-11,-7,-6,-4,-3,-2,'z')) | pattern(List(-11,7,6,-4,-3,-1))| - pattern(List(10,-4,-3,-2,1)) + pattern(List(10,-4,-3,0)) | pattern(List(-11,-7,-6,-4,-3,-2,'z')) | pattern(List(-11,7,6,-4,-3,-1))| + pattern(List(10,-4,-3,-2,1)) io.csr_pkt.legal := pattern(List(-11,10,9,8,7,6,4,-3,-2,1,'z')) | pattern(List(-11,-10,9,8,-7,-6,-5,-4,-3,-1)) | - pattern(List(-11,-10,9,8,-7,-6,5,-1,'z')) | pattern(List(11,9,8,7,6,-5,-4,-2,-1,'z')) | - pattern(List(11,-10,9,8,-6,-5,'z')) | pattern(List(-11,10,9,8,7,6,5,4,3,2,1,0)) | - pattern(List(-11,10,9,8,7,6,5,4,-2,-1)) | pattern(List(11,9,8,-7,-6,-5,4,-3,-2,0)) | - pattern(List(-11,10,9,8,7,-6,5,-3,-2,-1)) | pattern(List(-11,-10,9,8,-7,-6,5,2)) | - pattern(List(11,9,8,-7,-6,-5,4,-3,2,-1,'z')) | pattern(List(-11,10,9,8,7,6,-5,-4,3,1)) | - pattern(List(-11,10,9,8,7,6,-5,4,-3,2)) | pattern(List(11,9,8,-7,-6,-5,4,-3,-2,1)) | - pattern(List(-11,-10,9,8,-7,-6,5,1,0)) | pattern(List(11,-10,9,8,7,-5,-4,3,-2)) | - pattern(List(11,-10,9,8,7,-5,-4,3,-1,'z')) | pattern(List(11,-10,9,8,-6,-5,2)) | - pattern(List(-11,10,9,8,7,6,-5 ,4,-3,1)) | pattern(List(-11,10,9,8,7,6 ,-5,-4,'z')) | - pattern(List(-11,10,9,8,7,6 ,-5,-4,3,-2)) | pattern(List(-11,10,9,8,7,-6,5,-4,-3,-2,'z')) | - pattern(List(11,-10,9,8,-6,-5,1)) | pattern(List(-11,-10,9,8,-7,6,-5,-4,-3,-2)) | - pattern(List(-11,-10,9,8,-7,-5,-4,-3,-1,'z')) | pattern(List(-11,-10,9,8,-7,-6,5,3)) | - pattern(List(11,-10,9,8,-6,-5,3)) | pattern(List(-11,-10,9,8,-7,-6,5,4)) | - pattern(List(11,-10,9,8,-6,-5,4)) + pattern(List(-11,-10,9,8,-7,-6,5,-1,'z')) | pattern(List(11,9,8,7,6,-5,-4,-2,-1,'z')) | + pattern(List(11,-10,9,8,-6,-5,'z')) | pattern(List(-11,10,9,8,7,6,5,4,3,2,1,0)) | + pattern(List(-11,10,9,8,7,6,5,4,-2,-1)) | pattern(List(11,9,8,-7,-6,-5,4,-3,-2,0)) | + pattern(List(-11,10,9,8,7,-6,5,-3,-2,-1)) | pattern(List(-11,-10,9,8,-7,-6,5,2)) | + pattern(List(11,9,8,-7,-6,-5,4,-3,2,-1,'z')) | pattern(List(-11,10,9,8,7,6,-5,-4,3,1)) | + pattern(List(-11,10,9,8,7,6,-5,4,-3,2)) | pattern(List(11,9,8,-7,-6,-5,4,-3,-2,1)) | + pattern(List(-11,-10,9,8,-7,-6,5,1,0)) | pattern(List(11,-10,9,8,7,-5,-4,3,-2)) | + pattern(List(11,-10,9,8,7,-5,-4,3,-1,'z')) | pattern(List(11,-10,9,8,-6,-5,2)) | + pattern(List(-11,10,9,8,7,6,-5 ,4,-3,1)) | pattern(List(-11,10,9,8,7,6 ,-5,-4,'z')) | + pattern(List(-11,10,9,8,7,6 ,-5,-4,3,-2)) | pattern(List(-11,10,9,8,7,-6,5,-4,-3,-2,'z')) | + pattern(List(11,-10,9,8,-6,-5,1)) | pattern(List(-11,-10,9,8,-7,6,-5,-4,-3,-2)) | + pattern(List(-11,-10,9,8,-7,-5,-4,-3,-1,'z')) | pattern(List(-11,-10,9,8,-7,-6,5,3)) | + pattern(List(11,-10,9,8,-6,-5,3)) | pattern(List(-11,-10,9,8,-7,-6,5,4)) | + pattern(List(11,-10,9,8,-6,-5,4)) } @@ -2644,70 +3266,89 @@ class dec_timer_ctl extends Module with lib with RequireAsyncReset{ val MITCTL_ENABLE=0 val MITCTL_ENABLE_HALTED=1 val MITCTL_ENABLE_PAUSED=2 - - val mitctl1=WireInit(UInt(4.W),0.U) - val mitctl0=WireInit(UInt(3.W),0.U) - val mitb1 =WireInit(UInt(32.W),0.U) - val mitb0 =WireInit(UInt(32.W),0.U) - val mitcnt1=WireInit(UInt(32.W),0.U) - val mitcnt0=WireInit(UInt(32.W),0.U) - - val mit0_match_ns=(mitcnt0 >= mitb0).asUInt - val mit1_match_ns=(mitcnt1 >= mitb1).asUInt + + val mitctl1=WireInit(UInt(4.W),0.U) + val mitctl0=WireInit(UInt(3.W),0.U) + val mitb1 =WireInit(UInt(32.W),0.U) + val mitb0 =WireInit(UInt(32.W),0.U) + val mitcnt1=WireInit(UInt(32.W),0.U) + val mitcnt0=WireInit(UInt(32.W),0.U) + + val mit0_match_ns=(mitcnt0 >= mitb0).asUInt + val mit1_match_ns=(mitcnt1 >= mitb1).asUInt io.dec_timer_t0_pulse := mit0_match_ns - io.dec_timer_t1_pulse := mit1_match_ns - // ---------------------------------------------------------------------- - // MITCNT0 (RW) - // [31:0] : Internal Timer Counter 0 + io.dec_timer_t1_pulse := mit1_match_ns + // ---------------------------------------------------------------------- + // MITCNT0 (RW) + // [31:0] : Internal Timer Counter 0 val MITCNT0 =0x7d2.U(12.W) val wr_mitcnt0_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r === MITCNT0) val mitcnt0_inc_ok = mitctl0(MITCTL_ENABLE) & (~io.dec_pause_state | mitctl0(MITCTL_ENABLE_PAUSED)) & (~io.dec_tlu_pmu_fw_halted | mitctl0(MITCTL_ENABLE_HALTED)) & ~io.internal_dbg_halt_timers - val mitcnt0_inc = mitcnt0 + 1.U(32.W) - val mitcnt0_ns =Mux(mit0_match_ns.asBool, 0.U, Mux(wr_mitcnt0_r.asBool, io.dec_csr_wrdata_r, mitcnt0_inc)) - mitcnt0 :=rvdffe(mitcnt0_ns,(wr_mitcnt0_r | mitcnt0_inc_ok | mit0_match_ns).asBool,clock,io.scan_mode) + val mitcnt0_inc1 = WireInit(UInt(9.W),0.U) + val mitcnt0_inc2 = WireInit(UInt(24.W),0.U) + mitcnt0_inc1 := mitcnt0(7,0) + Cat(0.U(7.W), 1.U(1.W)) + val mitcnt0_inc_cout = mitcnt0_inc1(8) + mitcnt0_inc2 := mitcnt0(31,8) + Cat(0.U(23.W), mitcnt0_inc_cout) + val mitcnt0_inc = Cat(mitcnt0_inc2,mitcnt0_inc1(7,0)) - // ---------------------------------------------------------------------- - // MITCNT1 (RW) - // [31:0] : Internal Timer Counter 0 + val mitcnt0_ns = Mux(wr_mitcnt0_r, io.dec_csr_wrdata_r, Mux(mit0_match_ns, 0.U, mitcnt0_inc)) + + + mitcnt0 :=Cat(rvdffe(mitcnt0_ns(31,8),(wr_mitcnt0_r | (mitcnt0_inc_ok & mitcnt0_inc_cout) | mit0_match_ns).asBool,io.free_l2clk,io.scan_mode), + rvdffe(mitcnt0_ns(7,0),(wr_mitcnt0_r | mitcnt0_inc_ok | mit0_match_ns).asBool,io.free_l2clk,io.scan_mode)) + + // ---------------------------------------------------------------------- + // MITCNT1 (RW) + // [31:0] : Internal Timer Counter 0 val MITCNT1=0x7d5.U(12.W) - val wr_mitcnt1_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r === MITCNT1).asUInt + val wr_mitcnt1_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r === MITCNT1).asUInt - val mitcnt1_inc_ok = mitctl1(MITCTL_ENABLE) & (~io.dec_pause_state | mitctl1(MITCTL_ENABLE_PAUSED)) & (~io.dec_tlu_pmu_fw_halted | mitctl1(MITCTL_ENABLE_HALTED)) & ~io.internal_dbg_halt_timers + val mitcnt1_inc_ok = mitctl1(MITCTL_ENABLE) & (~io.dec_pause_state | mitctl1(MITCTL_ENABLE_PAUSED)) & (~io.dec_tlu_pmu_fw_halted | mitctl1(MITCTL_ENABLE_HALTED)) & ~io.internal_dbg_halt_timers & (~mitctl1(3) | mit0_match_ns) - // only inc MITCNT1 if not cascaded with 0, or if 0 overflows - val mitcnt1_inc = mitcnt1 + Cat(Fill(31,0.U(1.W)),(~mitctl1(3) | mit0_match_ns)) - val mitcnt1_ns = Mux(mit1_match_ns.asBool, 0.U, Mux(wr_mitcnt1_r.asBool, io.dec_csr_wrdata_r,mitcnt1_inc)) - mitcnt1 := rvdffe(mitcnt1_ns,(wr_mitcnt1_r | mitcnt1_inc_ok | mit1_match_ns).asBool,clock,io.scan_mode) + // only inc MITCNT1 if not cascaded with 0, or if 0 overflows + val mitcnt1_inc1 = WireInit(UInt(9.W),0.U) + val mitcnt1_inc2 = WireInit(UInt(24.W),0.U) + mitcnt1_inc1 := mitcnt1(7,0) + Cat(0.U(7.W), 1.U(1.W)) + val mitcnt1_inc_cout = mitcnt1_inc1(8) + mitcnt1_inc2 := mitcnt1(31,8) + Cat(0.U(23.W), mitcnt1_inc_cout) + val mitcnt1_inc = Cat(mitcnt1_inc2,mitcnt1_inc1(7,0)) - // ---------------------------------------------------------------------- - // MITB0 (RW) - // [31:0] : Internal Timer Bound 0 + val mitcnt1_ns =Mux(wr_mitcnt1_r.asBool, io.dec_csr_wrdata_r, Mux(mit1_match_ns.asBool, 0.U,mitcnt1_inc)) + + mitcnt1 :=Cat(rvdffe(mitcnt1_ns(31,8),(wr_mitcnt1_r | (mitcnt1_inc_ok & mitcnt1_inc_cout) | mit1_match_ns).asBool,io.free_l2clk,io.scan_mode), + rvdffe(mitcnt1_ns(7,0),(wr_mitcnt1_r | mitcnt1_inc_ok | mit1_match_ns).asBool,io.free_l2clk,io.scan_mode)) + + + + // ---------------------------------------------------------------------- + // MITB0 (RW) + // [31:0] : Internal Timer Bound 0 val MITB0 =0x7d3.U(12.W) val wr_mitb0_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r === MITB0) val mitb0_b = rvdffe((~io.dec_csr_wrdata_r),wr_mitb0_r.asBool,clock,io.scan_mode) mitb0 := ~mitb0_b - // ---------------------------------------------------------------------- - // MITB1 (RW) - // [31:0] : Internal Timer Bound 1 + // ---------------------------------------------------------------------- + // MITB1 (RW) + // [31:0] : Internal Timer Bound 1 - val MITB1 =0x7d6.U(12.W) + val MITB1 =0x7d6.U(12.W) val wr_mitb1_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r=== MITB1) val mitb1_b=rvdffe((~io.dec_csr_wrdata_r),wr_mitb1_r.asBool,clock,io.scan_mode) mitb1 := ~mitb1_b - // ---------------------------------------------------------------------- - // MITCTL0 (RW) Internal Timer Ctl 0 - // [31:3] : Reserved, reads 0x0 - // [2] : Enable while PAUSEd - // [1] : Enable while HALTed - // [0] : Enable (resets to 0x1) + // ---------------------------------------------------------------------- + // MITCTL0 (RW) Internal Timer Ctl 0 + // [31:3] : Reserved, reads 0x0 + // [2] : Enable while PAUSEd + // [1] : Enable while HALTed + // [0] : Enable (resets to 0x1) val MITCTL0 =0x7d4.U(12.W) @@ -2715,40 +3356,41 @@ class dec_timer_ctl extends Module with lib with RequireAsyncReset{ val mitctl0_ns = Mux(wr_mitctl0_r.asBool, io.dec_csr_wrdata_r(2,0), mitctl0(2,0)) val mitctl0_0_b_ns = ~mitctl0_ns(0) - val mitctl0_0_b = withClock(io.free_clk){RegNext(mitctl0_0_b_ns,0.U)} - mitctl0 :=Cat(withClock(io.free_clk){RegNext(mitctl0_ns(2,1),0.U)},~mitctl0_0_b) + val mitctl0_0_b = withClock(io.csr_wr_clk){RegEnable(mitctl0_0_b_ns,0.U,wr_mitctl0_r)} + mitctl0 :=Cat(withClock(io.csr_wr_clk){RegEnable(mitctl0_ns(2,1),0.U,wr_mitctl0_r)},~mitctl0_0_b) - // ---------------------------------------------------------------------- - // MITCTL1 (RW) Internal Timer Ctl 1 - // [31:4] : Reserved, reads 0x0 - // [3] : Cascade - // [2] : Enable while PAUSEd - // [1] : Enable while HALTed - // [0] : Enable (resets to 0x1) + // ---------------------------------------------------------------------- + // MITCTL1 (RW) Internal Timer Ctl 1 + // [31:4] : Reserved, reads 0x0 + // [3] : Cascade + // [2] : Enable while PAUSEd + // [1] : Enable while HALTed + // [0] : Enable (resets to 0x1) val MITCTL1 =0x7d7.U(12.W) val wr_mitctl1_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r=== MITCTL1) - val mitctl1_ns = Mux(wr_mitctl1_r.asBool,io.dec_csr_wrdata_r(3,0), mitctl1(3,0)) + val mitctl1_ns = Mux(wr_mitctl1_r.asBool,io.dec_csr_wrdata_r(3,0), mitctl1(3,0)) val mitctl1_0_b_ns= ~mitctl1_ns(0) - val mitctl1_0_b=withClock(io.free_clk){RegNext(mitctl1_0_b_ns,0.U)} - mitctl1:=Cat(withClock(io.free_clk){RegNext(mitctl1_ns(3,1),0.U)},~mitctl1_0_b) + val mitctl1_0_b=withClock(io.csr_wr_clk){RegEnable(mitctl1_0_b_ns,0.U,wr_mitctl1_r)} + mitctl1:=Cat(withClock(io.csr_wr_clk){RegEnable(mitctl1_ns(3,1),0.U,wr_mitctl1_r)},~mitctl1_0_b) - io.dec_timer_read_d := io.csr_mitcnt1 | io.csr_mitcnt0 | io.csr_mitb1 | io.csr_mitb0 | io.csr_mitctl0 | io.csr_mitctl1 - io.dec_timer_rddata_d :=Mux1H(Seq( - io.csr_mitcnt0.asBool -> mitcnt0(31,0), - io.csr_mitcnt1.asBool -> mitcnt1, - io.csr_mitb0.asBool -> mitb0, - io.csr_mitb1.asBool -> mitb1, - io.csr_mitctl0.asBool -> Cat(Fill(29,0.U(1.W)),mitctl0), - io.csr_mitctl1.asBool -> Cat(Fill(28,0.U(1.W)),mitctl1) - )) + io.dec_timer_read_d := io.csr_mitcnt1 | io.csr_mitcnt0 | io.csr_mitb1 | io.csr_mitb0 | io.csr_mitctl0 | io.csr_mitctl1 + io.dec_timer_rddata_d :=Mux1H(Seq( + io.csr_mitcnt0.asBool -> mitcnt0(31,0), + io.csr_mitcnt1.asBool -> mitcnt1, + io.csr_mitb0.asBool -> mitb0, + io.csr_mitb1.asBool -> mitb1, + io.csr_mitctl0.asBool -> Cat(Fill(29,0.U(1.W)),mitctl0), + io.csr_mitctl1.asBool -> Cat(Fill(28,0.U(1.W)),mitctl1) + )) } class dec_timer_ctl_IO extends Bundle{ - val free_clk =Input(Clock()) - val scan_mode =Input(Bool()) + val free_l2clk =Input(Clock()) + val csr_wr_clk = Input(Clock()) + val scan_mode =Input(Bool()) val dec_csr_wen_r_mod =Input(UInt(1.W)) // csr write enable at wb - val dec_csr_rdaddr_d =Input(UInt(12.W)) // read address for csr + // val dec_csr_rdaddr_d =Input(UInt(12.W)) // read address for csr val dec_csr_wraddr_r =Input(UInt(12.W)) // write address for csr val dec_csr_wrdata_r =Input(UInt(32.W)) // csr write data at wb @@ -2769,3 +3411,6 @@ class dec_timer_ctl_IO extends Bundle{ val dec_timer_t0_pulse =Output(UInt(1.W)) // timer0 int val dec_timer_t1_pulse =Output(UInt(1.W)) // timer1 int } +object tlu extends App { + (new chisel3.stage.ChiselStage).emitVerilog(new dec_tlu_ctl()) +} \ No newline at end of file diff --git a/src/main/scala/exu/exu.scala b/src/main/scala/exu/exu.scala index 5f458ec0..79f3afe7 100644 --- a/src/main/scala/exu/exu.scala +++ b/src/main/scala/exu/exu.scala @@ -21,12 +21,11 @@ class exu extends Module with lib with RequireAsyncReset{ val exu_div_wren = Output(UInt(1.W)) // Divide write enable to GPR //debug val dbg_cmd_wrdata = Input(UInt(32.W)) // Debug data to primary I0 RS1 + val dec_csr_rddata_d = Input(UInt(32.W)) //lsu val lsu_exu = Flipped(new lsu_exu()) //ifu_ifc val exu_flush_path_final = Output(UInt(31.W)) // Target for the oldest flush source - val dec_qual_lsu_d = Input(Bool()) - }) val PREDPIPESIZE = BTB_ADDR_HI - BTB_ADDR_LO + BHT_GHR_SIZE + BTB_BTAG_SIZE +1 @@ -112,14 +111,14 @@ class exu extends Module with lib with RequireAsyncReset{ dontTouch(i0_rs2_d) io.lsu_exu.exu_lsu_rs1_d:=Mux1H(Seq( - (!i0_rs1_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_i0_rs1_en_d & io.dec_qual_lsu_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs1_d, - (i0_rs1_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_qual_lsu_d).asBool -> i0_rs1_bypass_data_d, - (io.dec_exu.decode_exu.dec_extint_stall & io.dec_qual_lsu_d).asBool -> Cat(io.dec_exu.tlu_exu.dec_tlu_meihap,0.U(2.W)) + (!i0_rs1_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_i0_rs1_en_d & io.dec_exu.decode_exu.dec_qual_lsu_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs1_d, + (i0_rs1_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_qual_lsu_d).asBool -> i0_rs1_bypass_data_d, + (io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_qual_lsu_d).asBool -> Cat(io.dec_exu.tlu_exu.dec_tlu_meihap,0.U(2.W)) )) io.lsu_exu.exu_lsu_rs2_d:=Mux1H(Seq( - (!i0_rs2_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_i0_rs2_en_d & io.dec_qual_lsu_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs2_d, - (i0_rs2_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_qual_lsu_d).asBool -> i0_rs2_bypass_data_d + (!i0_rs2_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_i0_rs2_en_d & io.dec_exu.decode_exu.dec_qual_lsu_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs2_d, + (i0_rs2_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_qual_lsu_d).asBool -> i0_rs2_bypass_data_d )) val muldiv_rs1_d=Mux1H(Seq( @@ -129,10 +128,12 @@ class exu extends Module with lib with RequireAsyncReset{ val i_alu=Module(new exu_alu_ctl()) i_alu.io.dec_alu <> io.dec_exu.dec_alu + i_alu.io.scan_mode :=io.scan_mode i_alu.io.enable :=x_data_en i_alu.io.pp_in :=i0_predict_newp_d i_alu.io.flush_upper_x :=i0_flush_upper_x + i_alu.io.csr_rddata_in :=io.dec_csr_rddata_d i_alu.io.dec_tlu_flush_lower_r :=io.dec_exu.tlu_exu.dec_tlu_flush_lower_r i_alu.io.a_in :=i0_rs1_d.asSInt i_alu.io.b_in :=i0_rs2_d diff --git a/src/main/scala/exu/exu_alu_ctl.scala b/src/main/scala/exu/exu_alu_ctl.scala index d27ebf4b..e45ee1d6 100644 --- a/src/main/scala/exu/exu_alu_ctl.scala +++ b/src/main/scala/exu/exu_alu_ctl.scala @@ -9,7 +9,7 @@ class exu_alu_ctl extends Module with lib with RequireAsyncReset{ val io = IO(new Bundle{ val dec_alu = new dec_alu() - //val csr_rddata_in = Input(UInt(32.W)) // CSR data + val csr_rddata_in = Input(UInt(32.W)) // CSR data val dec_i0_pc_d = Input(UInt(31.W)) // for pc=pc+2,4 calculations val scan_mode = Input(UInt(1.W)) // Scan control val flush_upper_x = Input(UInt(1.W)) // Branch flush from previous cycle @@ -156,7 +156,7 @@ class exu_alu_ctl extends Module with lib with RequireAsyncReset{ val lout = Mux1H(Seq( - io.dec_alu.dec_csr_ren_d -> io.dec_alu.dec_csr_rddata_d.asSInt , + io.dec_alu.dec_csr_ren_d -> io.csr_rddata_in.asSInt , (io.i0_ap.land & !ap_zbb).asBool -> (Cat(0.U(1.W),io.a_in).asSInt & io.b_in.asSInt) , (io.i0_ap.lor & !ap_zbb).asBool -> (Cat(0.U(1.W),io.a_in).asSInt | io.b_in.asSInt) , (io.i0_ap.lxor & !ap_zbb).asBool -> (Cat(0.U(1.W),io.a_in).asSInt ^ io.b_in.asSInt) , diff --git a/src/main/scala/ifu/ifu_aln_ctl.scala b/src/main/scala/ifu/ifu_aln_ctl.scala index 3ced6243..5b6040f3 100644 --- a/src/main/scala/ifu/ifu_aln_ctl.scala +++ b/src/main/scala/ifu/ifu_aln_ctl.scala @@ -343,7 +343,7 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset { val icaf_eff = alignicaf(1) | aligndbecc(1) - io.dec_aln.aln_ib.ifu_i0_icaf_f1 := first4B & icaf_eff & alignfromf1 + io.dec_aln.aln_ib.ifu_i0_icaf_second := first4B & icaf_eff & alignfromf1 io.dec_aln.aln_ib.ifu_i0_dbecc := Mux1H(Seq(first4B.asBool->aligndbecc.orR, first2B.asBool->aligndbecc(0))) diff --git a/src/main/scala/include/bundle.scala b/src/main/scala/include/bundle.scala index 76896d8c..91bf90bb 100644 --- a/src/main/scala/include/bundle.scala +++ b/src/main/scala/include/bundle.scala @@ -205,7 +205,6 @@ class dctl_busbuff extends Bundle with lib{ val lsu_nonblock_load_data_valid = Output(Bool()) val lsu_nonblock_load_data_error = Output(Bool()) val lsu_nonblock_load_data_tag = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W)) - val lsu_nonblock_load_data = Output(UInt(32.W)) } class lsu_tlu extends Bundle { val lsu_pmu_load_external_m = Output(Bool()) @@ -247,7 +246,7 @@ class ic_mem extends Bundle with lib { class aln_ib extends Bundle with lib{ val ifu_i0_icaf = Output(Bool()) val ifu_i0_icaf_type = Output(UInt(2.W)) - val ifu_i0_icaf_f1 = Output(Bool()) + val ifu_i0_icaf_second = Output(Bool()) val ifu_i0_dbecc = Output(Bool()) val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W)) @@ -298,12 +297,12 @@ class dma_ifc extends Bundle{ } class trace_pkt_t extends Bundle{ - val rv_i_valid_ip = Output(UInt(2.W) ) + val rv_i_valid_ip = Output(UInt(1.W) ) val rv_i_insn_ip = Output(UInt(32.W) ) val rv_i_address_ip = Output(UInt(32.W) ) - val rv_i_exception_ip = Output(UInt(2.W) ) + val rv_i_exception_ip = Output(UInt(1.W) ) val rv_i_ecause_ip = Output(UInt(5.W) ) - val rv_i_interrupt_ip = Output(UInt(2.W) ) + val rv_i_interrupt_ip = Output(UInt(1.W) ) val rv_i_tval_ip = Output(UInt(32.W) ) } @@ -326,7 +325,7 @@ class dbg_dctl extends Bundle{ class dec_alu extends Bundle { val dec_i0_alu_decode_d = Input(UInt(1.W)) // Valid val dec_csr_ren_d = Input(Bool()) // extra decode - val dec_csr_rddata_d = Input(UInt(32.W)) + // val dec_csr_rddata_d = Input(UInt(32.W)) val dec_i0_br_immed_d = Input(UInt(12.W)) // Branch offset val exu_i0_pc_x = Output(UInt(31.W)) // flopped PC } @@ -372,6 +371,7 @@ class decode_exu extends Bundle with lib{ val dec_i0_rs2_en_d =Input(UInt(1.W)) // Qualify GPR RS2 data val dec_i0_immed_d =Input(UInt(32.W)) // DEC data immediate val dec_i0_result_r =Input(UInt(32.W)) // DEC result in R-stage + val dec_qual_lsu_d = Input(Bool()) val dec_i0_select_pc_d =Input(UInt(1.W)) // PC select to RS1 val dec_i0_rs1_bypass_en_d =Input(UInt(4.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data val dec_i0_rs2_bypass_en_d =Input(UInt(4.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data @@ -469,7 +469,7 @@ class predict_pkt_t extends Bundle { class trap_pkt_t extends Bundle { val legal = UInt(1.W) val icaf = UInt(1.W) - val icaf_f1 = UInt(1.W) + val icaf_second = UInt(1.W) val icaf_type = UInt(2.W) val fence_i = UInt(1.W) val i0trigger = UInt(4.W) @@ -478,7 +478,6 @@ class trap_pkt_t extends Bundle { val pmu_divide = UInt(1.W) val pmu_lsu_misaligned = UInt(1.W) } - class dest_pkt_t extends Bundle { val i0rd = UInt(5.W) val i0load = UInt(1.W) @@ -819,9 +818,9 @@ class dec_tlu_csr_pkt extends Bundle{ val csr_mitcnt0 =UInt(1.W) val csr_mitcnt1 =UInt(1.W) val csr_mpmc =UInt(1.W) - val csr_mcpc =UInt(1.W) + // val csr_mcpc =UInt(1.W) val csr_meicpct =UInt(1.W) - val csr_mdeau =UInt(1.W) + // val csr_mdeau =UInt(1.W) val csr_micect =UInt(1.W) val csr_miccmect =UInt(1.W) val csr_mdccmect =UInt(1.W) diff --git a/src/main/scala/lsu/lsu.scala b/src/main/scala/lsu/lsu.scala index 9cad15db..4963cca9 100644 --- a/src/main/scala/lsu/lsu.scala +++ b/src/main/scala/lsu/lsu.scala @@ -1,358 +1,358 @@ -package lsu - -import lib._ -import chisel3._ -import chisel3.util._ -import include._ -import mem._ - -class lsu extends Module with RequireAsyncReset with param with lib { - val io = IO (new Bundle { - val clk_override = Input(Bool()) - val lsu_dma = new lsu_dma - val lsu_pic = new lsu_pic - val lsu_exu = new lsu_exu - val lsu_dec = new lsu_dec - val dccm = Flipped(new mem_lsu) - val lsu_tlu = new lsu_tlu - val axi = new axi_channels(LSU_BUS_TAG) - - val dec_tlu_flush_lower_r = Input(Bool()) - val dec_tlu_i0_kill_writeb_r = Input(Bool()) - val dec_tlu_force_halt = Input(Bool()) - - val dec_tlu_core_ecc_disable = Input(Bool()) - - val dec_lsu_offset_d = Input(UInt(12.W)) - val lsu_p = Flipped(Valid(new lsu_pkt_t())) - val trigger_pkt_any = Input(Vec(4, new trigger_pkt_t())) - - val dec_lsu_valid_raw_d = Input(Bool()) - val dec_tlu_mrac_ff = Input(UInt(32.W)) - - //Outputs - val lsu_result_m = Output(UInt(32.W)) - val lsu_result_corr_r = Output(UInt(32.W)) - val lsu_load_stall_any = Output(Bool()) - val lsu_store_stall_any = Output(Bool()) - val lsu_fastint_stall_any = Output(Bool()) - val lsu_idle_any = Output(Bool()) - val lsu_active = Output(Bool()) - val lsu_fir_addr = Output(UInt(31.W)) - val lsu_fir_error = Output(UInt(2.W)) - val lsu_single_ecc_error_incr = Output(Bool()) - val lsu_error_pkt_r = Valid(new lsu_error_pkt_t()) - val lsu_pmu_misaligned_m = Output(Bool()) - val lsu_trigger_match_m = Output(UInt(4.W)) - - val lsu_bus_clk_en = Input(Bool()) - - val scan_mode = Input(Bool()) - val active_clk = Input(Clock()) - - }) - val dma_dccm_wdata = WireInit(0.U(64.W)) - val dma_dccm_wdata_lo = WireInit(0.U(32.W)) - val dma_dccm_wdata_hi = WireInit(0.U(32.W)) - val dma_mem_tag_m = WireInit(0.U(3.W)) - val lsu_raw_fwd_lo_r = WireInit(0.U(1.W)) - val lsu_raw_fwd_hi_r = WireInit(0.U(1.W)) - val lsu_busm_clken = WireInit(0.U(1.W)) - val lsu_bus_obuf_c1_clken = WireInit(0.U(1.W)) - val lsu_addr_d = WireInit(0.U(32.W)) - val lsu_addr_m = WireInit(0.U(32.W)) - val lsu_addr_r = WireInit(0.U(32.W)) - val end_addr_d = WireInit(0.U(32.W)) - val end_addr_m = WireInit(0.U(32.W)) - val end_addr_r = WireInit(0.U(32.W)) - val lsu_busreq_r = WireInit(Bool(),false.B) - - val lsu_lsc_ctl = Module(new lsu_lsc_ctl()) - io.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m - io.lsu_result_corr_r := lsu_lsc_ctl.io.lsu_result_corr_r - val dccm_ctl = Module(new lsu_dccm_ctl()) - val stbuf = Module(new lsu_stbuf()) - val ecc = Module(new lsu_ecc()) - val trigger = Module(new lsu_trigger()) - val clkdomain = Module(new lsu_clkdomain()) - val bus_intf = Module(new lsu_bus_intf()) - - val lsu_raw_fwd_lo_m = stbuf.io.stbuf_fwdbyteen_lo_m.orR - val lsu_raw_fwd_hi_m = stbuf.io.stbuf_fwdbyteen_hi_m.orR - - // block stores in decode - for either bus or stbuf reasons - io.lsu_store_stall_any := stbuf.io.lsu_stbuf_full_any | bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff - io.lsu_load_stall_any := bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff - io.lsu_fastint_stall_any := dccm_ctl.io.ld_single_ecc_error_r // Stall the fastint in decode-1 stage - - // Ready to accept dma trxns - // There can't be any inpipe forwarding from non-dma packet to dma packet since they can be flushed so we can't have st in r when dma is in m - val dma_mem_tag_d = io.lsu_dma.dma_mem_tag - val ldst_nodma_mtor = lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) & lsu_lsc_ctl.io.lsu_pkt_m.bits.store - io.lsu_dma.dccm_ready := !(io.dec_lsu_valid_raw_d | ldst_nodma_mtor | dccm_ctl.io.ld_single_ecc_error_r_ff) - val dma_dccm_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_dccm_d & io.lsu_dma.dma_lsc_ctl.dma_mem_sz(1) - val dma_pic_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_pic_d - dma_dccm_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata >> Cat(io.lsu_dma.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores - dma_dccm_wdata_hi := dma_dccm_wdata(63,32) - dma_dccm_wdata_lo := dma_dccm_wdata(31,0) - - val flush_m_up = io.dec_tlu_flush_lower_r - val flush_r = io.dec_tlu_i0_kill_writeb_r - - // lsu halt idle. This is used for entering the halt mode. Also, DMA accesses are allowed during fence. - // Indicates non-idle if there is a instruction valid in d-r or read/write buffers are non-empty since they can come with error - // Store buffer now have only non-dma dccm stores - // stbuf_empty not needed since it has only dccm stores - - io.lsu_idle_any := !((lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma) | (lsu_lsc_ctl.io.lsu_pkt_r.valid & !lsu_lsc_ctl.io.lsu_pkt_r.bits.dma)) & bus_intf.io.lsu_bus_buffer_empty_any - io.lsu_active := (lsu_lsc_ctl.io.lsu_pkt_m.valid | lsu_lsc_ctl.io.lsu_pkt_r.valid | dccm_ctl.io.ld_single_ecc_error_r_ff) | !bus_intf.io.lsu_bus_buffer_empty_any // This includes DMA. Used for gating top clock - // Instantiate the store buffer - val store_stbuf_reqvld_r = lsu_lsc_ctl.io.lsu_pkt_r.valid & lsu_lsc_ctl.io.lsu_pkt_r.bits.store & lsu_lsc_ctl.io.addr_in_dccm_r & !flush_r & (!lsu_lsc_ctl.io.lsu_pkt_r.bits.dma | ((lsu_lsc_ctl.io.lsu_pkt_r.bits.by | lsu_lsc_ctl.io.lsu_pkt_r.bits.half) & !ecc.io.lsu_double_ecc_error_r)) - // Disable Forwarding for now - val lsu_cmpen_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & (lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) - // Bus signals - val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int - // Dual signals - val ldst_dual_d = lsu_addr_d(2) =/= end_addr_d(2) - val ldst_dual_m = lsu_addr_m(2) =/= end_addr_m(2) - val ldst_dual_r = lsu_addr_r(2) =/= end_addr_r(2) - // PMU signals - io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR)) - io.lsu_tlu.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.load & lsu_lsc_ctl.io.addr_external_m - io.lsu_tlu.lsu_pmu_store_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.store & lsu_lsc_ctl.io.addr_external_m - - //LSU_LSC_Control - //Inputs - lsu_lsc_ctl.io.clk_override := io.clk_override - lsu_lsc_ctl.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk - lsu_lsc_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk - lsu_lsc_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk - lsu_lsc_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk - lsu_lsc_ctl.io.lsu_store_c1_m_clk := clkdomain.io.lsu_store_c1_m_clk - lsu_lsc_ctl.io.lsu_ld_data_r := dccm_ctl.io.lsu_ld_data_r - lsu_lsc_ctl.io.lsu_ld_data_corr_r := dccm_ctl.io.lsu_ld_data_corr_r - lsu_lsc_ctl.io.lsu_single_ecc_error_r := ecc.io.lsu_single_ecc_error_r - lsu_lsc_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r - lsu_lsc_ctl.io.lsu_ld_data_m := dccm_ctl.io.lsu_ld_data_m - lsu_lsc_ctl.io.lsu_single_ecc_error_m := ecc.io.lsu_single_ecc_error_m - lsu_lsc_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m - lsu_lsc_ctl.io.flush_m_up := flush_m_up - lsu_lsc_ctl.io.flush_r := flush_r - lsu_lsc_ctl.io.ldst_dual_d := ldst_dual_d - lsu_lsc_ctl.io.ldst_dual_m := ldst_dual_m - lsu_lsc_ctl.io.ldst_dual_r := ldst_dual_r - lsu_lsc_ctl.io.lsu_exu <> io.lsu_exu - lsu_lsc_ctl.io.lsu_p <> io.lsu_p - lsu_lsc_ctl.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d - lsu_lsc_ctl.io.dec_lsu_offset_d := io.dec_lsu_offset_d - lsu_lsc_ctl.io.picm_mask_data_m := dccm_ctl.io.picm_mask_data_m - lsu_lsc_ctl.io.bus_read_data_m := bus_intf.io.bus_read_data_m - lsu_lsc_ctl.io.dma_lsc_ctl <> io.lsu_dma.dma_lsc_ctl - lsu_lsc_ctl.io.dec_tlu_mrac_ff := io.dec_tlu_mrac_ff - lsu_lsc_ctl.io.scan_mode := io.scan_mode - //Outputs - lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d - lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m - lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r - end_addr_d := lsu_lsc_ctl.io.lsu_addr_d - end_addr_m := lsu_lsc_ctl.io.lsu_addr_m - end_addr_r := lsu_lsc_ctl.io.lsu_addr_r - io.lsu_single_ecc_error_incr := lsu_lsc_ctl.io.lsu_single_ecc_error_incr - io.lsu_error_pkt_r <> lsu_lsc_ctl.io.lsu_error_pkt_r - io.lsu_fir_addr <> lsu_lsc_ctl.io.lsu_fir_addr - io.lsu_fir_error <> lsu_lsc_ctl.io.lsu_fir_error - // DCCM Control - //Inputs - dccm_ctl.io.clk_override := io.clk_override - dccm_ctl.io.ldst_dual_m := ldst_dual_m - dccm_ctl.io.ldst_dual_r := ldst_dual_r - dccm_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk - dccm_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk - dccm_ctl.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk - dccm_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk - dccm_ctl.io.lsu_store_c1_r_clk := clkdomain.io.lsu_store_c1_r_clk - dccm_ctl.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d - dccm_ctl.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m - dccm_ctl.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r - dccm_ctl.io.addr_in_dccm_d := lsu_lsc_ctl.io.addr_in_dccm_d - dccm_ctl.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m - dccm_ctl.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r - dccm_ctl.io.addr_in_pic_d := lsu_lsc_ctl.io.addr_in_pic_d - dccm_ctl.io.addr_in_pic_m := lsu_lsc_ctl.io.addr_in_pic_m - dccm_ctl.io.addr_in_pic_r := lsu_lsc_ctl.io.addr_in_pic_r - dccm_ctl.io.lsu_raw_fwd_lo_r := lsu_raw_fwd_lo_r - dccm_ctl.io.lsu_raw_fwd_hi_r := lsu_raw_fwd_hi_r - dccm_ctl.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r - dccm_ctl.io.lsu_addr_d := lsu_addr_d - dccm_ctl.io.lsu_addr_m := lsu_addr_m(DCCM_BITS-1,0) - dccm_ctl.io.lsu_addr_r := lsu_addr_r - dccm_ctl.io.end_addr_d := end_addr_d(DCCM_BITS-1,0) - dccm_ctl.io.end_addr_m := end_addr_m(DCCM_BITS-1,0) - dccm_ctl.io.end_addr_r := end_addr_r(DCCM_BITS-1,0) - dccm_ctl.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any - dccm_ctl.io.stbuf_addr_any := stbuf.io.stbuf_addr_any - dccm_ctl.io.stbuf_data_any := stbuf.io.stbuf_data_any - dccm_ctl.io.stbuf_ecc_any := ecc.io.stbuf_ecc_any - dccm_ctl.io.stbuf_fwddata_hi_m := stbuf.io.stbuf_fwddata_hi_m - dccm_ctl.io.stbuf_fwddata_lo_m := stbuf.io.stbuf_fwddata_lo_m - dccm_ctl.io.stbuf_fwdbyteen_lo_m := stbuf.io.stbuf_fwdbyteen_lo_m - dccm_ctl.io.stbuf_fwdbyteen_hi_m := stbuf.io.stbuf_fwdbyteen_hi_m - dccm_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r - dccm_ctl.io.single_ecc_error_hi_r := ecc.io.single_ecc_error_hi_r - dccm_ctl.io.single_ecc_error_lo_r := ecc.io.single_ecc_error_lo_r - dccm_ctl.io.sec_data_hi_r := ecc.io.sec_data_hi_r - dccm_ctl.io.sec_data_lo_r := ecc.io.sec_data_lo_r - dccm_ctl.io.sec_data_hi_r_ff := ecc.io.sec_data_hi_r_ff - dccm_ctl.io.sec_data_lo_r_ff := ecc.io.sec_data_lo_r_ff - dccm_ctl.io.sec_data_ecc_hi_r_ff := ecc.io.sec_data_ecc_hi_r_ff - dccm_ctl.io.sec_data_ecc_lo_r_ff := ecc.io.sec_data_ecc_lo_r_ff - dccm_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m - dccm_ctl.io.sec_data_hi_m := ecc.io.sec_data_hi_m - dccm_ctl.io.sec_data_lo_m := ecc.io.sec_data_lo_m - dccm_ctl.io.store_data_m := lsu_lsc_ctl.io.store_data_m - dccm_ctl.io.dma_dccm_wen := dma_dccm_wen - dccm_ctl.io.dma_pic_wen := dma_pic_wen - dccm_ctl.io.dma_mem_tag_m := dma_mem_tag_m - dccm_ctl.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo - dccm_ctl.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi - dccm_ctl.io.dma_dccm_wdata_ecc_hi := ecc.io.dma_dccm_wdata_ecc_hi - dccm_ctl.io.dma_dccm_wdata_ecc_lo := ecc.io.dma_dccm_wdata_ecc_lo - dccm_ctl.io.scan_mode := io.scan_mode - //Outputs - io.lsu_dma.dma_dccm_ctl <> dccm_ctl.io.dma_dccm_ctl - io.dccm <> dccm_ctl.io.dccm - io.lsu_pic <> dccm_ctl.io.lsu_pic - //Store Buffer - //Inputs - stbuf.io.ldst_dual_d := ldst_dual_d - stbuf.io.ldst_dual_m := ldst_dual_m - stbuf.io.ldst_dual_r := ldst_dual_r - stbuf.io.lsu_stbuf_c1_clk := clkdomain.io.lsu_stbuf_c1_clk - stbuf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk - stbuf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m - stbuf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r - stbuf.io.store_stbuf_reqvld_r := store_stbuf_reqvld_r - stbuf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r - stbuf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d - stbuf.io.store_data_hi_r := dccm_ctl.io.store_data_hi_r - stbuf.io.store_data_lo_r := dccm_ctl.io.store_data_lo_r - stbuf.io.store_datafn_hi_r := dccm_ctl.io.store_datafn_hi_r - stbuf.io.store_datafn_lo_r := dccm_ctl.io.store_datafn_lo_r - stbuf.io.lsu_stbuf_commit_any := dccm_ctl.io.lsu_stbuf_commit_any - stbuf.io.lsu_addr_d := lsu_addr_d - stbuf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m - stbuf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r - stbuf.io.end_addr_d := end_addr_d - stbuf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m - stbuf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r - stbuf.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m - stbuf.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r - stbuf.io.lsu_cmpen_m := lsu_cmpen_m - stbuf.io.scan_mode := io.scan_mode - - // ECC - //Inputs - ecc.io.clk_override := io.clk_override - ecc.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk - ecc.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m - ecc.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r - ecc.io.stbuf_data_any := stbuf.io.stbuf_data_any - ecc.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable - ecc.io.lsu_dccm_rden_r := dccm_ctl.io.lsu_dccm_rden_r - ecc.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r - ecc.io.lsu_addr_r := lsu_addr_r - ecc.io.end_addr_r := end_addr_r - ecc.io.lsu_addr_m := lsu_addr_m - ecc.io.end_addr_m := end_addr_m - ecc.io.dccm_rdata_hi_r := dccm_ctl.io.dccm_rdata_hi_r - ecc.io.dccm_rdata_lo_r := dccm_ctl.io.dccm_rdata_lo_r - ecc.io.dccm_rdata_hi_m := dccm_ctl.io.dccm_rdata_hi_m - ecc.io.dccm_rdata_lo_m := dccm_ctl.io.dccm_rdata_lo_m - ecc.io.dccm_data_ecc_hi_r := dccm_ctl.io.dccm_data_ecc_hi_r - ecc.io.dccm_data_ecc_lo_r := dccm_ctl.io.dccm_data_ecc_lo_r - ecc.io.dccm_data_ecc_hi_m := dccm_ctl.io.dccm_data_ecc_hi_m - ecc.io.dccm_data_ecc_lo_m := dccm_ctl.io.dccm_data_ecc_lo_m - ecc.io.ld_single_ecc_error_r := dccm_ctl.io.ld_single_ecc_error_r - ecc.io.ld_single_ecc_error_r_ff := dccm_ctl.io.ld_single_ecc_error_r_ff - ecc.io.lsu_dccm_rden_m := dccm_ctl.io.lsu_dccm_rden_m - ecc.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m - ecc.io.dma_dccm_wen := dma_dccm_wen - ecc.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo - ecc.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi - ecc.io.scan_mode := io.scan_mode - - //Trigger - //Inputs - trigger.io.trigger_pkt_any <> io.trigger_pkt_any - trigger.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m - trigger.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m - trigger.io.store_data_m := lsu_lsc_ctl.io.store_data_m - //Outputs - io.lsu_trigger_match_m :=trigger.io.lsu_trigger_match_m - - //Clock Domain - //Inputs - clkdomain.io.active_clk := io.active_clk - clkdomain.io.clk_override := io.clk_override - clkdomain.io.dec_tlu_force_halt := io.dec_tlu_force_halt - clkdomain.io.dma_dccm_req := io.lsu_dma.dma_lsc_ctl.dma_dccm_req - clkdomain.io.ldst_stbuf_reqvld_r := stbuf.io.ldst_stbuf_reqvld_r - clkdomain.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any - clkdomain.io.stbuf_reqvld_flushed_any := stbuf.io.stbuf_reqvld_flushed_any - clkdomain.io.lsu_busreq_r := bus_intf.io.lsu_busreq_r - clkdomain.io.lsu_bus_buffer_pend_any := bus_intf.io.lsu_bus_buffer_pend_any - clkdomain.io.lsu_bus_buffer_empty_any := bus_intf.io.lsu_bus_buffer_empty_any - clkdomain.io.lsu_stbuf_empty_any := stbuf.io.lsu_stbuf_empty_any - clkdomain.io.lsu_bus_clk_en := io.lsu_bus_clk_en - clkdomain.io.lsu_p := io.lsu_p - clkdomain.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d - clkdomain.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m - clkdomain.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r - clkdomain.io.scan_mode := io.scan_mode - - //Bus Interface - //Inputs - bus_intf.io.scan_mode := io.scan_mode - io.lsu_dec.tlu_busbuff <> bus_intf.io.tlu_busbuff - bus_intf.io.clk_override := io.clk_override - bus_intf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk - bus_intf.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk - bus_intf.io.lsu_busm_clken := lsu_busm_clken - bus_intf.io.lsu_bus_obuf_c1_clken := lsu_bus_obuf_c1_clken - bus_intf.io.lsu_bus_ibuf_c1_clk := clkdomain.io.lsu_bus_ibuf_c1_clk - bus_intf.io.lsu_bus_obuf_c1_clk := clkdomain.io.lsu_bus_obuf_c1_clk - bus_intf.io.lsu_bus_buf_c1_clk := clkdomain.io.lsu_bus_buf_c1_clk - bus_intf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk - bus_intf.io.active_clk := io.active_clk - bus_intf.io.lsu_busm_clk := clkdomain.io.lsu_busm_clk - bus_intf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d - bus_intf.io.lsu_busreq_m := lsu_busreq_m - bus_intf.io.ldst_dual_d := ldst_dual_d - bus_intf.io.ldst_dual_m := ldst_dual_m - bus_intf.io.ldst_dual_r := ldst_dual_r - bus_intf.io.lsu_addr_m := lsu_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid) - bus_intf.io.lsu_addr_r := lsu_addr_r & Fill(32,lsu_busreq_r) - bus_intf.io.end_addr_m := end_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid) - bus_intf.io.end_addr_r := end_addr_r & Fill(32,lsu_busreq_r) - bus_intf.io.store_data_r := dccm_ctl.io.store_data_r & Fill(32,lsu_busreq_r) - bus_intf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m - bus_intf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r - bus_intf.io.dec_tlu_force_halt := io.dec_tlu_force_halt - bus_intf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r - bus_intf.io.is_sideeffects_m := lsu_lsc_ctl.io.is_sideeffects_m - bus_intf.io.flush_m_up := flush_m_up - bus_intf.io.flush_r := flush_r - //Outputs - io.lsu_dec.dctl_busbuff <> bus_intf.io.dctl_busbuff - lsu_busreq_r := bus_intf.io.lsu_busreq_r - io.axi <> bus_intf.io.axi - bus_intf.io.lsu_bus_clk_en := io.lsu_bus_clk_en - - withClock(clkdomain.io.lsu_c1_m_clk){dma_mem_tag_m := RegNext(dma_mem_tag_d,0.U)} - withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_hi_r := RegNext(lsu_raw_fwd_hi_m,0.U)} - withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_lo_r := RegNext(lsu_raw_fwd_lo_m,0.U)} - -} -object lsu_main extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new lsu())) -} \ No newline at end of file +//package lsu +// +//import lib._ +//import chisel3._ +//import chisel3.util._ +//import include._ +//import mem._ +// +//class lsu extends Module with RequireAsyncReset with param with lib { +// val io = IO (new Bundle { +// val clk_override = Input(Bool()) +// val lsu_dma = new lsu_dma +// val lsu_pic = new lsu_pic +// val lsu_exu = new lsu_exu +// val lsu_dec = new lsu_dec +// val dccm = Flipped(new mem_lsu) +// val lsu_tlu = new lsu_tlu +// val axi = new axi_channels(LSU_BUS_TAG) +// +// val dec_tlu_flush_lower_r = Input(Bool()) +// val dec_tlu_i0_kill_writeb_r = Input(Bool()) +// val dec_tlu_force_halt = Input(Bool()) +// +// val dec_tlu_core_ecc_disable = Input(Bool()) +// +// val dec_lsu_offset_d = Input(UInt(12.W)) +// val lsu_p = Flipped(Valid(new lsu_pkt_t())) +// val trigger_pkt_any = Input(Vec(4, new trigger_pkt_t())) +// +// val dec_lsu_valid_raw_d = Input(Bool()) +// val dec_tlu_mrac_ff = Input(UInt(32.W)) +// +// //Outputs +// val lsu_result_m = Output(UInt(32.W)) +// val lsu_result_corr_r = Output(UInt(32.W)) +// val lsu_load_stall_any = Output(Bool()) +// val lsu_store_stall_any = Output(Bool()) +// val lsu_fastint_stall_any = Output(Bool()) +// val lsu_idle_any = Output(Bool()) +// val lsu_active = Output(Bool()) +// val lsu_fir_addr = Output(UInt(31.W)) +// val lsu_fir_error = Output(UInt(2.W)) +// val lsu_single_ecc_error_incr = Output(Bool()) +// val lsu_error_pkt_r = Valid(new lsu_error_pkt_t()) +// val lsu_pmu_misaligned_m = Output(Bool()) +// val lsu_trigger_match_m = Output(UInt(4.W)) +// +// val lsu_bus_clk_en = Input(Bool()) +// +// val scan_mode = Input(Bool()) +// val active_clk = Input(Clock()) +// +// }) +// val dma_dccm_wdata = WireInit(0.U(64.W)) +// val dma_dccm_wdata_lo = WireInit(0.U(32.W)) +// val dma_dccm_wdata_hi = WireInit(0.U(32.W)) +// val dma_mem_tag_m = WireInit(0.U(3.W)) +// val lsu_raw_fwd_lo_r = WireInit(0.U(1.W)) +// val lsu_raw_fwd_hi_r = WireInit(0.U(1.W)) +// val lsu_busm_clken = WireInit(0.U(1.W)) +// val lsu_bus_obuf_c1_clken = WireInit(0.U(1.W)) +// val lsu_addr_d = WireInit(0.U(32.W)) +// val lsu_addr_m = WireInit(0.U(32.W)) +// val lsu_addr_r = WireInit(0.U(32.W)) +// val end_addr_d = WireInit(0.U(32.W)) +// val end_addr_m = WireInit(0.U(32.W)) +// val end_addr_r = WireInit(0.U(32.W)) +// val lsu_busreq_r = WireInit(Bool(),false.B) +// +// val lsu_lsc_ctl = Module(new lsu_lsc_ctl()) +// io.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m +// io.lsu_result_corr_r := lsu_lsc_ctl.io.lsu_result_corr_r +// val dccm_ctl = Module(new lsu_dccm_ctl()) +// val stbuf = Module(new lsu_stbuf()) +// val ecc = Module(new lsu_ecc()) +// val trigger = Module(new lsu_trigger()) +// val clkdomain = Module(new lsu_clkdomain()) +// val bus_intf = Module(new lsu_bus_intf()) +// +// val lsu_raw_fwd_lo_m = stbuf.io.stbuf_fwdbyteen_lo_m.orR +// val lsu_raw_fwd_hi_m = stbuf.io.stbuf_fwdbyteen_hi_m.orR +// +// // block stores in decode - for either bus or stbuf reasons +// io.lsu_store_stall_any := stbuf.io.lsu_stbuf_full_any | bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff +// io.lsu_load_stall_any := bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff +// io.lsu_fastint_stall_any := dccm_ctl.io.ld_single_ecc_error_r // Stall the fastint in decode-1 stage +// +// // Ready to accept dma trxns +// // There can't be any inpipe forwarding from non-dma packet to dma packet since they can be flushed so we can't have st in r when dma is in m +// val dma_mem_tag_d = io.lsu_dma.dma_mem_tag +// val ldst_nodma_mtor = lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) & lsu_lsc_ctl.io.lsu_pkt_m.bits.store +// io.lsu_dma.dccm_ready := !(io.dec_lsu_valid_raw_d | ldst_nodma_mtor | dccm_ctl.io.ld_single_ecc_error_r_ff) +// val dma_dccm_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_dccm_d & io.lsu_dma.dma_lsc_ctl.dma_mem_sz(1) +// val dma_pic_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_pic_d +// dma_dccm_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata >> Cat(io.lsu_dma.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores +// dma_dccm_wdata_hi := dma_dccm_wdata(63,32) +// dma_dccm_wdata_lo := dma_dccm_wdata(31,0) +// +// val flush_m_up = io.dec_tlu_flush_lower_r +// val flush_r = io.dec_tlu_i0_kill_writeb_r +// +// // lsu halt idle. This is used for entering the halt mode. Also, DMA accesses are allowed during fence. +// // Indicates non-idle if there is a instruction valid in d-r or read/write buffers are non-empty since they can come with error +// // Store buffer now have only non-dma dccm stores +// // stbuf_empty not needed since it has only dccm stores +// +// io.lsu_idle_any := !((lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma) | (lsu_lsc_ctl.io.lsu_pkt_r.valid & !lsu_lsc_ctl.io.lsu_pkt_r.bits.dma)) & bus_intf.io.lsu_bus_buffer_empty_any +// io.lsu_active := (lsu_lsc_ctl.io.lsu_pkt_m.valid | lsu_lsc_ctl.io.lsu_pkt_r.valid | dccm_ctl.io.ld_single_ecc_error_r_ff) | !bus_intf.io.lsu_bus_buffer_empty_any // This includes DMA. Used for gating top clock +// // Instantiate the store buffer +// val store_stbuf_reqvld_r = lsu_lsc_ctl.io.lsu_pkt_r.valid & lsu_lsc_ctl.io.lsu_pkt_r.bits.store & lsu_lsc_ctl.io.addr_in_dccm_r & !flush_r & (!lsu_lsc_ctl.io.lsu_pkt_r.bits.dma | ((lsu_lsc_ctl.io.lsu_pkt_r.bits.by | lsu_lsc_ctl.io.lsu_pkt_r.bits.half) & !ecc.io.lsu_double_ecc_error_r)) +// // Disable Forwarding for now +// val lsu_cmpen_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & (lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) +// // Bus signals +// val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int +// // Dual signals +// val ldst_dual_d = lsu_addr_d(2) =/= end_addr_d(2) +// val ldst_dual_m = lsu_addr_m(2) =/= end_addr_m(2) +// val ldst_dual_r = lsu_addr_r(2) =/= end_addr_r(2) +// // PMU signals +// io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR)) +// io.lsu_tlu.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.load & lsu_lsc_ctl.io.addr_external_m +// io.lsu_tlu.lsu_pmu_store_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.store & lsu_lsc_ctl.io.addr_external_m +// +// //LSU_LSC_Control +// //Inputs +// lsu_lsc_ctl.io.clk_override := io.clk_override +// lsu_lsc_ctl.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk +// lsu_lsc_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk +// lsu_lsc_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk +// lsu_lsc_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk +// lsu_lsc_ctl.io.lsu_store_c1_m_clk := clkdomain.io.lsu_store_c1_m_clk +// lsu_lsc_ctl.io.lsu_ld_data_r := dccm_ctl.io.lsu_ld_data_r +// lsu_lsc_ctl.io.lsu_ld_data_corr_r := dccm_ctl.io.lsu_ld_data_corr_r +// lsu_lsc_ctl.io.lsu_single_ecc_error_r := ecc.io.lsu_single_ecc_error_r +// lsu_lsc_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r +// lsu_lsc_ctl.io.lsu_ld_data_m := dccm_ctl.io.lsu_ld_data_m +// lsu_lsc_ctl.io.lsu_single_ecc_error_m := ecc.io.lsu_single_ecc_error_m +// lsu_lsc_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m +// lsu_lsc_ctl.io.flush_m_up := flush_m_up +// lsu_lsc_ctl.io.flush_r := flush_r +// lsu_lsc_ctl.io.ldst_dual_d := ldst_dual_d +// lsu_lsc_ctl.io.ldst_dual_m := ldst_dual_m +// lsu_lsc_ctl.io.ldst_dual_r := ldst_dual_r +// lsu_lsc_ctl.io.lsu_exu <> io.lsu_exu +// lsu_lsc_ctl.io.lsu_p <> io.lsu_p +// lsu_lsc_ctl.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d +// lsu_lsc_ctl.io.dec_lsu_offset_d := io.dec_lsu_offset_d +// lsu_lsc_ctl.io.picm_mask_data_m := dccm_ctl.io.picm_mask_data_m +// lsu_lsc_ctl.io.bus_read_data_m := bus_intf.io.bus_read_data_m +// lsu_lsc_ctl.io.dma_lsc_ctl <> io.lsu_dma.dma_lsc_ctl +// lsu_lsc_ctl.io.dec_tlu_mrac_ff := io.dec_tlu_mrac_ff +// lsu_lsc_ctl.io.scan_mode := io.scan_mode +// //Outputs +// lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d +// lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m +// lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r +// end_addr_d := lsu_lsc_ctl.io.lsu_addr_d +// end_addr_m := lsu_lsc_ctl.io.lsu_addr_m +// end_addr_r := lsu_lsc_ctl.io.lsu_addr_r +// io.lsu_single_ecc_error_incr := lsu_lsc_ctl.io.lsu_single_ecc_error_incr +// io.lsu_error_pkt_r <> lsu_lsc_ctl.io.lsu_error_pkt_r +// io.lsu_fir_addr <> lsu_lsc_ctl.io.lsu_fir_addr +// io.lsu_fir_error <> lsu_lsc_ctl.io.lsu_fir_error +// // DCCM Control +// //Inputs +// dccm_ctl.io.clk_override := io.clk_override +// dccm_ctl.io.ldst_dual_m := ldst_dual_m +// dccm_ctl.io.ldst_dual_r := ldst_dual_r +// dccm_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk +// dccm_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk +// dccm_ctl.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk +// dccm_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk +// dccm_ctl.io.lsu_store_c1_r_clk := clkdomain.io.lsu_store_c1_r_clk +// dccm_ctl.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d +// dccm_ctl.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m +// dccm_ctl.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r +// dccm_ctl.io.addr_in_dccm_d := lsu_lsc_ctl.io.addr_in_dccm_d +// dccm_ctl.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m +// dccm_ctl.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r +// dccm_ctl.io.addr_in_pic_d := lsu_lsc_ctl.io.addr_in_pic_d +// dccm_ctl.io.addr_in_pic_m := lsu_lsc_ctl.io.addr_in_pic_m +// dccm_ctl.io.addr_in_pic_r := lsu_lsc_ctl.io.addr_in_pic_r +// dccm_ctl.io.lsu_raw_fwd_lo_r := lsu_raw_fwd_lo_r +// dccm_ctl.io.lsu_raw_fwd_hi_r := lsu_raw_fwd_hi_r +// dccm_ctl.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r +// dccm_ctl.io.lsu_addr_d := lsu_addr_d +// dccm_ctl.io.lsu_addr_m := lsu_addr_m(DCCM_BITS-1,0) +// dccm_ctl.io.lsu_addr_r := lsu_addr_r +// dccm_ctl.io.end_addr_d := end_addr_d(DCCM_BITS-1,0) +// dccm_ctl.io.end_addr_m := end_addr_m(DCCM_BITS-1,0) +// dccm_ctl.io.end_addr_r := end_addr_r(DCCM_BITS-1,0) +// dccm_ctl.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any +// dccm_ctl.io.stbuf_addr_any := stbuf.io.stbuf_addr_any +// dccm_ctl.io.stbuf_data_any := stbuf.io.stbuf_data_any +// dccm_ctl.io.stbuf_ecc_any := ecc.io.stbuf_ecc_any +// dccm_ctl.io.stbuf_fwddata_hi_m := stbuf.io.stbuf_fwddata_hi_m +// dccm_ctl.io.stbuf_fwddata_lo_m := stbuf.io.stbuf_fwddata_lo_m +// dccm_ctl.io.stbuf_fwdbyteen_lo_m := stbuf.io.stbuf_fwdbyteen_lo_m +// dccm_ctl.io.stbuf_fwdbyteen_hi_m := stbuf.io.stbuf_fwdbyteen_hi_m +// dccm_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r +// dccm_ctl.io.single_ecc_error_hi_r := ecc.io.single_ecc_error_hi_r +// dccm_ctl.io.single_ecc_error_lo_r := ecc.io.single_ecc_error_lo_r +// dccm_ctl.io.sec_data_hi_r := ecc.io.sec_data_hi_r +// dccm_ctl.io.sec_data_lo_r := ecc.io.sec_data_lo_r +// dccm_ctl.io.sec_data_hi_r_ff := ecc.io.sec_data_hi_r_ff +// dccm_ctl.io.sec_data_lo_r_ff := ecc.io.sec_data_lo_r_ff +// dccm_ctl.io.sec_data_ecc_hi_r_ff := ecc.io.sec_data_ecc_hi_r_ff +// dccm_ctl.io.sec_data_ecc_lo_r_ff := ecc.io.sec_data_ecc_lo_r_ff +// dccm_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m +// dccm_ctl.io.sec_data_hi_m := ecc.io.sec_data_hi_m +// dccm_ctl.io.sec_data_lo_m := ecc.io.sec_data_lo_m +// dccm_ctl.io.store_data_m := lsu_lsc_ctl.io.store_data_m +// dccm_ctl.io.dma_dccm_wen := dma_dccm_wen +// dccm_ctl.io.dma_pic_wen := dma_pic_wen +// dccm_ctl.io.dma_mem_tag_m := dma_mem_tag_m +// dccm_ctl.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo +// dccm_ctl.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi +// dccm_ctl.io.dma_dccm_wdata_ecc_hi := ecc.io.dma_dccm_wdata_ecc_hi +// dccm_ctl.io.dma_dccm_wdata_ecc_lo := ecc.io.dma_dccm_wdata_ecc_lo +// dccm_ctl.io.scan_mode := io.scan_mode +// //Outputs +// io.lsu_dma.dma_dccm_ctl <> dccm_ctl.io.dma_dccm_ctl +// io.dccm <> dccm_ctl.io.dccm +// io.lsu_pic <> dccm_ctl.io.lsu_pic +// //Store Buffer +// //Inputs +// stbuf.io.ldst_dual_d := ldst_dual_d +// stbuf.io.ldst_dual_m := ldst_dual_m +// stbuf.io.ldst_dual_r := ldst_dual_r +// stbuf.io.lsu_stbuf_c1_clk := clkdomain.io.lsu_stbuf_c1_clk +// stbuf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk +// stbuf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m +// stbuf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r +// stbuf.io.store_stbuf_reqvld_r := store_stbuf_reqvld_r +// stbuf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r +// stbuf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d +// stbuf.io.store_data_hi_r := dccm_ctl.io.store_data_hi_r +// stbuf.io.store_data_lo_r := dccm_ctl.io.store_data_lo_r +// stbuf.io.store_datafn_hi_r := dccm_ctl.io.store_datafn_hi_r +// stbuf.io.store_datafn_lo_r := dccm_ctl.io.store_datafn_lo_r +// stbuf.io.lsu_stbuf_commit_any := dccm_ctl.io.lsu_stbuf_commit_any +// stbuf.io.lsu_addr_d := lsu_addr_d +// stbuf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m +// stbuf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r +// stbuf.io.end_addr_d := end_addr_d +// stbuf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m +// stbuf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r +// stbuf.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m +// stbuf.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r +// stbuf.io.lsu_cmpen_m := lsu_cmpen_m +// stbuf.io.scan_mode := io.scan_mode +// +// // ECC +// //Inputs +// ecc.io.clk_override := io.clk_override +// ecc.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk +// ecc.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m +// ecc.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r +// ecc.io.stbuf_data_any := stbuf.io.stbuf_data_any +// ecc.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable +// ecc.io.lsu_dccm_rden_r := dccm_ctl.io.lsu_dccm_rden_r +// ecc.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r +// ecc.io.lsu_addr_r := lsu_addr_r +// ecc.io.end_addr_r := end_addr_r +// ecc.io.lsu_addr_m := lsu_addr_m +// ecc.io.end_addr_m := end_addr_m +// ecc.io.dccm_rdata_hi_r := dccm_ctl.io.dccm_rdata_hi_r +// ecc.io.dccm_rdata_lo_r := dccm_ctl.io.dccm_rdata_lo_r +// ecc.io.dccm_rdata_hi_m := dccm_ctl.io.dccm_rdata_hi_m +// ecc.io.dccm_rdata_lo_m := dccm_ctl.io.dccm_rdata_lo_m +// ecc.io.dccm_data_ecc_hi_r := dccm_ctl.io.dccm_data_ecc_hi_r +// ecc.io.dccm_data_ecc_lo_r := dccm_ctl.io.dccm_data_ecc_lo_r +// ecc.io.dccm_data_ecc_hi_m := dccm_ctl.io.dccm_data_ecc_hi_m +// ecc.io.dccm_data_ecc_lo_m := dccm_ctl.io.dccm_data_ecc_lo_m +// ecc.io.ld_single_ecc_error_r := dccm_ctl.io.ld_single_ecc_error_r +// ecc.io.ld_single_ecc_error_r_ff := dccm_ctl.io.ld_single_ecc_error_r_ff +// ecc.io.lsu_dccm_rden_m := dccm_ctl.io.lsu_dccm_rden_m +// ecc.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m +// ecc.io.dma_dccm_wen := dma_dccm_wen +// ecc.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo +// ecc.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi +// ecc.io.scan_mode := io.scan_mode +// +// //Trigger +// //Inputs +// trigger.io.trigger_pkt_any <> io.trigger_pkt_any +// trigger.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m +// trigger.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m +// trigger.io.store_data_m := lsu_lsc_ctl.io.store_data_m +// //Outputs +// io.lsu_trigger_match_m :=trigger.io.lsu_trigger_match_m +// +// //Clock Domain +// //Inputs +// clkdomain.io.active_clk := io.active_clk +// clkdomain.io.clk_override := io.clk_override +// clkdomain.io.dec_tlu_force_halt := io.dec_tlu_force_halt +// clkdomain.io.dma_dccm_req := io.lsu_dma.dma_lsc_ctl.dma_dccm_req +// clkdomain.io.ldst_stbuf_reqvld_r := stbuf.io.ldst_stbuf_reqvld_r +// clkdomain.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any +// clkdomain.io.stbuf_reqvld_flushed_any := stbuf.io.stbuf_reqvld_flushed_any +// clkdomain.io.lsu_busreq_r := bus_intf.io.lsu_busreq_r +// clkdomain.io.lsu_bus_buffer_pend_any := bus_intf.io.lsu_bus_buffer_pend_any +// clkdomain.io.lsu_bus_buffer_empty_any := bus_intf.io.lsu_bus_buffer_empty_any +// clkdomain.io.lsu_stbuf_empty_any := stbuf.io.lsu_stbuf_empty_any +// clkdomain.io.lsu_bus_clk_en := io.lsu_bus_clk_en +// clkdomain.io.lsu_p := io.lsu_p +// clkdomain.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d +// clkdomain.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m +// clkdomain.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r +// clkdomain.io.scan_mode := io.scan_mode +// +// //Bus Interface +// //Inputs +// bus_intf.io.scan_mode := io.scan_mode +// io.lsu_dec.tlu_busbuff <> bus_intf.io.tlu_busbuff +// bus_intf.io.clk_override := io.clk_override +// bus_intf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk +// bus_intf.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk +// bus_intf.io.lsu_busm_clken := lsu_busm_clken +// bus_intf.io.lsu_bus_obuf_c1_clken := lsu_bus_obuf_c1_clken +// bus_intf.io.lsu_bus_ibuf_c1_clk := clkdomain.io.lsu_bus_ibuf_c1_clk +// bus_intf.io.lsu_bus_obuf_c1_clk := clkdomain.io.lsu_bus_obuf_c1_clk +// bus_intf.io.lsu_bus_buf_c1_clk := clkdomain.io.lsu_bus_buf_c1_clk +// bus_intf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk +// bus_intf.io.active_clk := io.active_clk +// bus_intf.io.lsu_busm_clk := clkdomain.io.lsu_busm_clk +// bus_intf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d +// bus_intf.io.lsu_busreq_m := lsu_busreq_m +// bus_intf.io.ldst_dual_d := ldst_dual_d +// bus_intf.io.ldst_dual_m := ldst_dual_m +// bus_intf.io.ldst_dual_r := ldst_dual_r +// bus_intf.io.lsu_addr_m := lsu_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid) +// bus_intf.io.lsu_addr_r := lsu_addr_r & Fill(32,lsu_busreq_r) +// bus_intf.io.end_addr_m := end_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid) +// bus_intf.io.end_addr_r := end_addr_r & Fill(32,lsu_busreq_r) +// bus_intf.io.store_data_r := dccm_ctl.io.store_data_r & Fill(32,lsu_busreq_r) +// bus_intf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m +// bus_intf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r +// bus_intf.io.dec_tlu_force_halt := io.dec_tlu_force_halt +// bus_intf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r +// bus_intf.io.is_sideeffects_m := lsu_lsc_ctl.io.is_sideeffects_m +// bus_intf.io.flush_m_up := flush_m_up +// bus_intf.io.flush_r := flush_r +// //Outputs +// io.lsu_dec.dctl_busbuff <> bus_intf.io.dctl_busbuff +// lsu_busreq_r := bus_intf.io.lsu_busreq_r +// io.axi <> bus_intf.io.axi +// bus_intf.io.lsu_bus_clk_en := io.lsu_bus_clk_en +// +// withClock(clkdomain.io.lsu_c1_m_clk){dma_mem_tag_m := RegNext(dma_mem_tag_d,0.U)} +// withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_hi_r := RegNext(lsu_raw_fwd_hi_m,0.U)} +// withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_lo_r := RegNext(lsu_raw_fwd_lo_m,0.U)} +// +//} +//object lsu_main extends App { +// println((new chisel3.stage.ChiselStage).emitVerilog(new lsu())) +//} \ No newline at end of file diff --git a/src/main/scala/lsu/lsu_bus_buffer.scala b/src/main/scala/lsu/lsu_bus_buffer.scala index cad81be0..96d1b244 100644 --- a/src/main/scala/lsu/lsu_bus_buffer.scala +++ b/src/main/scala/lsu/lsu_bus_buffer.scala @@ -1,632 +1,632 @@ -package lsu -import chisel3._ -import chisel3.util._ -import lib._ -import include._ -import chisel3.experimental.{ChiselEnum, chiselName} -import chisel3.util.ImplicitConversions.intToUInt -import ifu._ - -@chiselName -class lsu_bus_buffer extends Module with RequireAsyncReset with lib { - val io = IO(new Bundle { - val clk_override = Input(Bool()) - val scan_mode = Input(Bool()) - val tlu_busbuff = new tlu_busbuff() - val dctl_busbuff = new dctl_busbuff() - val dec_tlu_force_halt = Input(Bool()) - val lsu_bus_obuf_c1_clken = Input(Bool()) - val lsu_busm_clken = Input(Bool()) - val lsu_c2_r_clk = Input(Clock()) - val lsu_bus_ibuf_c1_clk = Input(Clock()) - val lsu_bus_obuf_c1_clk = Input(Clock()) - val lsu_bus_buf_c1_clk = Input(Clock()) - val lsu_free_c2_clk = Input(Clock()) - val lsu_busm_clk = Input(Clock()) - val dec_lsu_valid_raw_d = Input(Bool()) - val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t())) - val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t())) - val lsu_addr_m = Input(UInt(32.W)) - val end_addr_m = Input(UInt(32.W)) - val lsu_addr_r = Input(UInt(32.W)) - val end_addr_r = Input(UInt(32.W)) - val store_data_r = Input(UInt(32.W)) - val no_word_merge_r = Input(Bool()) - val no_dword_merge_r = Input(Bool()) - val lsu_busreq_m = Input(Bool()) - val ld_full_hit_m = Input(Bool()) - val flush_m_up = Input(Bool()) - val flush_r = Input(Bool()) - val lsu_commit_r = Input(Bool()) - val is_sideeffects_r = Input(Bool()) - val ldst_dual_d = Input(Bool()) - val ldst_dual_m = Input(Bool()) - val ldst_dual_r = Input(Bool()) - val ldst_byteen_ext_m = Input(UInt(8.W)) - val lsu_axi = new axi_channels(LSU_BUS_TAG) - val lsu_bus_clk_en = Input(Bool()) - val lsu_bus_clk_en_q = Input(Bool()) - - val lsu_busreq_r = Output(Bool()) - val lsu_bus_buffer_pend_any = Output(Bool()) - val lsu_bus_buffer_full_any = Output(Bool()) - val lsu_bus_buffer_empty_any = Output(Bool()) - // val lsu_bus_idle_any = Output(Bool()) - val ld_byte_hit_buf_lo = Output((UInt(4.W))) - val ld_byte_hit_buf_hi = Output((UInt(4.W))) - val ld_fwddata_buf_lo = Output((UInt(32.W))) - val ld_fwddata_buf_hi = Output((UInt(32.W))) - }) - def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) - def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) - - val DEPTH = LSU_NUM_NBLOAD - val DEPTH_LOG2 = LSU_NUM_NBLOAD_WIDTH - val TIMER = 8 - val TIMER_MAX = TIMER - 1 - val TIMER_LOG2 = if (TIMER < 2) 1 else log2Ceil(TIMER) - - val idle_C :: wait_C :: cmd_C :: resp_C :: done_partial_C :: done_wait_C :: done_C :: Nil = Enum(7) - val buf_addr = Wire(Vec(DEPTH, UInt(32.W))) - val buf_state = Wire(Vec(DEPTH, UInt(3.W))) - val buf_write = WireInit(UInt(DEPTH.W), 0.U) - val CmdPtr0 = WireInit(UInt(DEPTH_LOG2.W), 0.U) - - - val ldst_byteen_hi_m = io.ldst_byteen_ext_m(7, 4) - val ldst_byteen_lo_m = io.ldst_byteen_ext_m(3, 0) - - val ld_addr_hitvec_lo = (0 until DEPTH).map(i => (io.lsu_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m) - val ld_addr_hitvec_hi = (0 until DEPTH).map(i => (io.end_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m) - val ld_byte_hitvecfn_lo = Wire(Vec(4, UInt(DEPTH.W))) - val ld_byte_ibuf_hit_lo = WireInit(UInt(4.W), 0.U) - val ld_byte_hitvecfn_hi = Wire(Vec(4, UInt(DEPTH.W))) - val ld_byte_ibuf_hit_hi = WireInit(UInt(4.W), 0.U) - val buf_byteen = Wire(Vec(DEPTH, UInt(4.W))) - buf_byteen := buf_byteen.map(i=>0.U) - val buf_nxtstate = Wire(Vec(DEPTH, UInt(3.W))) - buf_nxtstate := buf_nxtstate.map(i=>0.U) - val buf_wr_en = Wire(Vec(DEPTH, Bool())) - buf_wr_en := buf_wr_en.map(i=> false.B) - val buf_data_en = Wire(Vec(DEPTH, Bool())) - buf_data_en := buf_data_en.map(i=> false.B) - val buf_state_bus_en = Wire(Vec(DEPTH, Bool())) - buf_state_bus_en := buf_state_bus_en.map(i=> false.B) - val buf_ldfwd_in = Wire(Vec(DEPTH, Bool())) - buf_ldfwd_in := buf_ldfwd_in.map(i=> false.B) - val buf_ldfwd_en = Wire(Vec(DEPTH, Bool())) - buf_ldfwd_en := buf_ldfwd_en.map(i=> io.dec_tlu_force_halt) - val buf_data_in = Wire(Vec(DEPTH, UInt(32.W))) - buf_data_in := buf_data_in.map(i=> 0.U) - val buf_ldfwdtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) - buf_ldfwdtag_in := buf_ldfwdtag_in.map(i=> 0.U) - val buf_error_en = Wire(Vec(DEPTH, Bool())) - buf_error_en := buf_error_en.map(i=> false.B) - val bus_rsp_read_error = WireInit(Bool(), false.B) - val bus_rsp_rdata = WireInit(UInt(64.W), 0.U) - val bus_rsp_write_error = WireInit(Bool(), false.B) - val buf_dualtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) - buf_dualtag := buf_dualtag.map(i=> 0.U) - val buf_ldfwd = WireInit(UInt(DEPTH.W), 0.U) - val buf_resp_state_bus_en = Wire(Vec(DEPTH, Bool())) - buf_resp_state_bus_en := buf_resp_state_bus_en.map(i=> false.B) - val any_done_wait_state = WireInit(Bool(), false.B) - val bus_rsp_write = WireInit(Bool(), false.B) - val bus_rsp_write_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) - val buf_ldfwdtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) - buf_ldfwdtag := buf_ldfwdtag.map(i=> 0.U) - val buf_rst = Wire(Vec(DEPTH, Bool())) - buf_rst := buf_rst.map(i=> false.B) - val ibuf_drainvec_vld = WireInit(UInt(DEPTH.W), 0.U) - val buf_byteen_in = Wire(Vec(DEPTH, UInt(DEPTH.W))) - buf_byteen_in := buf_byteen_in.map(i=> 0.U) - val buf_addr_in = Wire(Vec(DEPTH, UInt(32.W))) - buf_addr_in := buf_addr_in.map(i=> 0.U) - val buf_dual_in = WireInit(UInt(DEPTH.W), 0.U) - val buf_samedw_in = WireInit(UInt(DEPTH.W), 0.U) - val buf_nomerge_in = WireInit(UInt(DEPTH.W), 0.U) - val buf_dualhi_in = WireInit(UInt(DEPTH.W), 0.U) - val buf_dualtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) - buf_dualtag_in := buf_dualtag_in.map(i=> 0.U) - val buf_sideeffect_in = WireInit(UInt(DEPTH.W), 0.U) - val buf_unsign_in = WireInit(UInt(DEPTH.W), 0.U) - val buf_sz_in = Wire(Vec(DEPTH, UInt(2.W))) - buf_sz_in := buf_sz_in.map(i=> 0.U) - val buf_write_in = WireInit(UInt(DEPTH.W), 0.U) - val buf_unsign = WireInit(UInt(DEPTH.W), 0.U) - val buf_error = WireInit(UInt(DEPTH.W), 0.U) - val CmdPtr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U) - - val ibuf_data = WireInit(UInt(32.W), 0.U) - io.ld_byte_hit_buf_lo := (0 until 4).map(i => (ld_byte_hitvecfn_lo(i).orR | ld_byte_ibuf_hit_lo(i)).asUInt).reverse.reduce(Cat(_, _)) - io.ld_byte_hit_buf_hi := (0 until 4).map(i => (ld_byte_hitvecfn_hi(i).orR | ld_byte_ibuf_hit_hi(i)).asUInt).reverse.reduce(Cat(_, _)) - - val ld_byte_hitvec_lo = (0 until 4).map(j => (0 until DEPTH).map(i => (ld_addr_hitvec_lo(i) & buf_byteen(i)(j) & ldst_byteen_lo_m(j)).asUInt).reverse.reduce(Cat(_, _))) - val ld_byte_hitvec_hi = (0 until 4).map(j => (0 until DEPTH).map(i => (ld_addr_hitvec_hi(i) & buf_byteen(i)(j) & ldst_byteen_hi_m(j)).asUInt).reverse.reduce(Cat(_, _))) - - val buf_age_younger = Wire(Vec(DEPTH, UInt(DEPTH.W))) - buf_age_younger := buf_age_younger.map(i=> 0.U) - ld_byte_hitvecfn_lo := (0 until 4).map(j => (0 until DEPTH).map(i => (ld_byte_hitvec_lo(j)(i) & !(ld_byte_hitvec_lo(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_lo(j)).asUInt).reverse.reduce(Cat(_, _))) - ld_byte_hitvecfn_hi := (0 until 4).map(j => (0 until DEPTH).map(i => (ld_byte_hitvec_hi(j)(i) & !(ld_byte_hitvec_hi(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_hi(j)).asUInt).reverse.reduce(Cat(_, _))) - - val ibuf_addr = WireInit(UInt(32.W), 0.U) - val ibuf_write = WireInit(Bool(), false.B) - val ibuf_valid = WireInit(Bool(), false.B) - val ld_addr_ibuf_hit_lo = (io.lsu_addr_m(31, 2) === ibuf_addr(31, 2)) & ibuf_write & ibuf_valid & io.lsu_busreq_m - val ld_addr_ibuf_hit_hi = (io.end_addr_m(31, 2) === ibuf_addr(31, 2)) & ibuf_write & ibuf_valid & io.lsu_busreq_m - - val ibuf_byteen = WireInit(UInt(4.W), 0.U) - - ld_byte_ibuf_hit_lo := Fill(4, ld_addr_ibuf_hit_lo) & ibuf_byteen & ldst_byteen_lo_m - ld_byte_ibuf_hit_hi := Fill(4, ld_addr_ibuf_hit_hi) & ibuf_byteen & ldst_byteen_hi_m - - val buf_data = Wire(Vec(DEPTH, UInt(32.W))) - buf_data := buf_data.map(i=> 0.U) - val fwd_data = WireInit(UInt(32.W), 0.U) - val ld_fwddata_buf_lo_initial = (0 until 4).map(i=>Fill(8, ld_byte_ibuf_hit_lo(i))).reverse.reduce(Cat(_,_)) - val ld_fwddata_buf_hi_initial = (0 until 4).map(i=>Fill(8, ld_byte_ibuf_hit_hi(i))).reverse.reduce(Cat(_,_)) - io.ld_fwddata_buf_lo := Cat((0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(3)(i)) & buf_data(i)(31, 24)).reduce(_ | _), - (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(2)(i)) & buf_data(i)(23, 16)).reduce(_ | _), - (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(1)(i)) & buf_data(i)(15, 8)).reduce(_ | _), - (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(0)(i)) & buf_data(i)(7 , 0)).reduce(_ | _)) | - (ld_fwddata_buf_lo_initial & ibuf_data) - - io.ld_fwddata_buf_hi := Cat((0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(3)(i)) & buf_data(i)(31, 24)).reduce(_ | _), - (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(2)(i)) & buf_data(i)(23, 16)).reduce(_ | _), - (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(1)(i)) & buf_data(i)(15, 8)).reduce(_ | _), - (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(0)(i)) & buf_data(i)(7 , 0)).reduce(_ | _)) | - (ld_fwddata_buf_hi_initial & ibuf_data) - - val bus_coalescing_disable = io.tlu_busbuff.dec_tlu_wb_coalescing_disable | BUILD_AHB_LITE.B - val ldst_byteen_r = Mux1H(Seq(io.lsu_pkt_r.bits.by -> 1.U(4.W), - io.lsu_pkt_r.bits.half -> 3.U(4.W), - io.lsu_pkt_r.bits.word -> 15.U(4.W))) - - val ldst_byteen_hi_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->0.U(4.W), - (io.lsu_addr_r(1,0)===1.U)->Cat(0.U(3.W), ldst_byteen_r(3)), - (io.lsu_addr_r(1,0)===2.U)->Cat(0.U(2.W), ldst_byteen_r(3,2)), - (io.lsu_addr_r(1,0)===3.U)->Cat(0.U(1.W), ldst_byteen_r(3,1)))) - - val ldst_byteen_lo_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->ldst_byteen_r, - (io.lsu_addr_r(1,0)===1.U)->Cat(ldst_byteen_r(2,0), 0.U), - (io.lsu_addr_r(1,0)===2.U)->Cat(ldst_byteen_r(1,0), 0.U(2.W)), - (io.lsu_addr_r(1,0)===3.U)->Cat(ldst_byteen_r(0) , 0.U(3.W)))) - - val store_data_hi_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->0.U(32.W), - (io.lsu_addr_r(1,0)===1.U)->Cat(0.U(24.W) , io.store_data_r(31,24)), - (io.lsu_addr_r(1,0)===2.U)->Cat(0.U(16.W), io.store_data_r(31,16)), - (io.lsu_addr_r(1,0)===3.U)->Cat(0.U(8.W), io.store_data_r(31,8)))) - - val store_data_lo_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->io.store_data_r, - (io.lsu_addr_r(1,0)===1.U)->Cat(io.store_data_r(23,0), 0.U(8.W)), - (io.lsu_addr_r(1,0)===2.U)->Cat(io.store_data_r(15,0), 0.U(16.W)), - (io.lsu_addr_r(1,0)===3.U)->Cat(io.store_data_r(7 ,0) , 0.U(24.W)))) - - - val ldst_samedw_r = io.lsu_addr_r(3) === io.end_addr_r(3) - val is_aligned_r = Mux1H(Seq(io.lsu_pkt_r.bits.word -> (io.lsu_addr_r(1, 0) === 0.U), - io.lsu_pkt_r.bits.half -> !io.lsu_addr_r(0), - io.lsu_pkt_r.bits.by -> 1.U)) - val ibuf_byp = io.lsu_busreq_r & (io.lsu_pkt_r.bits.load | io.no_word_merge_r) & !ibuf_valid - val ibuf_wr_en = io.lsu_busreq_r & io.lsu_commit_r & !ibuf_byp - val ibuf_drain_vld = WireInit(Bool(), false.B) - val ibuf_rst = (ibuf_drain_vld & !ibuf_wr_en) | io.dec_tlu_force_halt - val ibuf_force_drain = io.lsu_busreq_m & !io.lsu_busreq_r & ibuf_valid & (io.lsu_pkt_m.bits.load | (ibuf_addr(31, 2) =/= io.lsu_addr_m(31, 2))) - val ibuf_sideeffect = WireInit(Bool(), false.B) - val ibuf_timer = WireInit(UInt(TIMER_LOG2.W), 0.U) - val ibuf_merge_en = WireInit(Bool(), false.B) - val ibuf_merge_in = WireInit(Bool(), false.B) - ibuf_drain_vld := ibuf_valid & (((ibuf_wr_en | (ibuf_timer === TIMER_MAX.U)) & !(ibuf_merge_en & ibuf_merge_in)) - | ibuf_byp | ibuf_force_drain | ibuf_sideeffect | !ibuf_write | bus_coalescing_disable) - val ibuf_tag = WireInit(UInt(DEPTH_LOG2.W), 0.U) - val WrPtr1_r = WireInit(UInt(DEPTH_LOG2.W), 0.U) - val WrPtr0_r = WireInit(UInt(DEPTH_LOG2.W), 0.U) - - val ibuf_tag_in = Mux(ibuf_merge_en & ibuf_merge_in, ibuf_tag, Mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r)) - val ibuf_dualtag_in = WrPtr0_r - val ibuf_sz_in = Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) - val ibuf_addr_in = Mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) - val ibuf_byteen_in = Mux(ibuf_merge_en & ibuf_merge_in, ibuf_byteen(3, 0) | ldst_byteen_lo_r(3, 0), - Mux(io.ldst_dual_r, ldst_byteen_hi_r(3, 0), ldst_byteen_lo_r(3, 0))) - - - val ibuf_data_in = (0 until 4).map(i => Mux(ibuf_merge_en & ibuf_merge_in, - Mux(ldst_byteen_lo_r(i), store_data_lo_r((8 * i) + 7, 8 * i), ibuf_data((8 * i) + 7, 8 * i)), - Mux(io.ldst_dual_r, store_data_hi_r((8 * i) + 7, 8 * i), store_data_lo_r((8 * i) + 7, 8 * i)))).reverse.reduce(Cat(_, _)) - val ibuf_timer_in = Mux(ibuf_wr_en, 0.U, Mux((ibuf_timer < TIMER_MAX.U).asBool(), ibuf_timer+1.U, ibuf_timer)) - - ibuf_merge_en := io.lsu_busreq_r & io.lsu_commit_r & io.lsu_pkt_r.bits.store & ibuf_valid & ibuf_write & (io.lsu_addr_r(31,2) === ibuf_addr(31,2)) & !io.is_sideeffects_r & !bus_coalescing_disable - ibuf_merge_in := !io.ldst_dual_r - val ibuf_byteen_out = (0 until 4).map(i=>(Mux(ibuf_merge_en & !ibuf_merge_in, ibuf_byteen(i) | ldst_byteen_lo_r(i), ibuf_byteen(i))).asUInt).reverse.reduce(Cat(_,_)) - val ibuf_data_out = (0 until 4).map(i=>Mux(ibuf_merge_en & !ibuf_merge_in, Mux(ldst_byteen_lo_r(i), store_data_lo_r((8*i)+7, 8*i), ibuf_data((8*i)+7, 8*i)), ibuf_data((8*i)+7, 8*i))).reverse.reduce(Cat(_,_)) - - ibuf_valid := withClock(io.lsu_free_c2_clk){RegNext(Mux(ibuf_wr_en, true.B, ibuf_valid) & !ibuf_rst, false.B)} - ibuf_tag := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_tag_in, 0.U, ibuf_wr_en)} - val ibuf_dualtag = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_dualtag_in, 0.U, ibuf_wr_en)} - val ibuf_dual = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.ldst_dual_r, 0.U, ibuf_wr_en)} - val ibuf_samedw = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ldst_samedw_r, 0.U, ibuf_wr_en)} - val ibuf_nomerge = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.no_dword_merge_r, 0.U, ibuf_wr_en)} - ibuf_sideeffect := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.is_sideeffects_r, 0.U, ibuf_wr_en)} - val ibuf_unsign = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.bits.unsign, 0.U, ibuf_wr_en)} - ibuf_write := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.bits.store, 0.U, ibuf_wr_en)} - val ibuf_sz = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_sz_in, 0.U, ibuf_wr_en)} - ibuf_addr := rvdffe(ibuf_addr_in, ibuf_wr_en, clock, io.scan_mode) - ibuf_byteen := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_byteen_in, 0.U, ibuf_wr_en)} - ibuf_data := rvdffe(ibuf_data_in, ibuf_wr_en, clock, io.scan_mode) - ibuf_timer := withClock(io.lsu_free_c2_clk) {RegNext(ibuf_timer_in, 0.U)} - val buf_numvld_wrcmd_any = WireInit(UInt(4.W), 0.U) - val buf_numvld_cmd_any = WireInit(UInt(4.W), 0.U) - val obuf_wr_timer = WireInit(UInt(TIMER_LOG2.W), 0.U) - val buf_nomerge = Wire(Vec(DEPTH, Bool())) - buf_nomerge := buf_nomerge.map(i=> false.B) - - val buf_sideeffect = WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U) - val obuf_force_wr_en = WireInit(Bool(), false.B) - val obuf_wr_en = WireInit(Bool(), false.B) - val obuf_wr_wait = (buf_numvld_wrcmd_any===1.U) & (buf_numvld_cmd_any===1.U) & (obuf_wr_timer =/= TIMER_MAX.U) & - !bus_coalescing_disable & !Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(CmdPtr0===i.U)->buf_nomerge(i))) & - !Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(CmdPtr0===i.U)->buf_sideeffect(i))) & !obuf_force_wr_en - val obuf_wr_timer_in = Mux(obuf_wr_en, 0.U(3.W), Mux(buf_numvld_cmd_any.orR & (obuf_wr_timer(CmdPtr0===i.U)->buf_addr(i)(31,2)))) - val buf_numvld_pend_any = WireInit(UInt(4.W), 0.U) - val ibuf_buf_byp = ibuf_byp & (buf_numvld_pend_any===0.U) & (!io.lsu_pkt_r.bits.store | io.no_dword_merge_r) - val bus_sideeffect_pend = WireInit(Bool(), false.B) - val found_cmdptr0 = WireInit(Bool(), false.B) - val buf_cmd_state_bus_en = Wire(Vec(DEPTH, Bool())) - buf_cmd_state_bus_en := buf_cmd_state_bus_en.map(i=> false.B) - val buf_dual = Wire(Vec(DEPTH, Bool())) - buf_dual := buf_dual.map(i=> false.B) - val buf_samedw = Wire(Vec(DEPTH, Bool())) - buf_samedw := buf_samedw.map(i=> false.B) - val found_cmdptr1 = WireInit(Bool(), false.B) - val bus_cmd_ready = WireInit(Bool(), false.B) - val obuf_valid = WireInit(Bool(), false.B) - val obuf_nosend = WireInit(Bool(), false.B) - // val lsu_bus_cntr_overflow = WireInit(Bool(), false.B) - val bus_addr_match_pending = WireInit(Bool(), false.B) - - obuf_wr_en := ((ibuf_buf_byp & io.lsu_commit_r & !(io.is_sideeffects_r & bus_sideeffect_pend)) | - ((indexing(buf_state, CmdPtr0) === cmd_C) & - found_cmdptr0 & !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !(indexing(buf_sideeffect, CmdPtr0) & bus_sideeffect_pend) & - (!(indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_write, CmdPtr0)) | found_cmdptr1 | indexing(buf_nomerge.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) | - obuf_force_wr_en))) & (bus_cmd_ready | !obuf_valid | obuf_nosend) & !obuf_wr_wait & !bus_addr_match_pending & io.lsu_bus_clk_en - - val bus_cmd_sent = WireInit(Bool(), false.B) - val obuf_rst = ((bus_cmd_sent | (obuf_valid & obuf_nosend)) & !obuf_wr_en & io.lsu_bus_clk_en) | io.dec_tlu_force_halt - val obuf_write_in = Mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, indexing(buf_write, CmdPtr0)) - val obuf_sideeffect_in = Mux(ibuf_buf_byp, io.is_sideeffects_r, indexing(buf_sideeffect, CmdPtr0)) - val obuf_addr_in = Mux(ibuf_buf_byp, io.lsu_addr_r, indexing(buf_addr, CmdPtr0)) - val buf_sz = Wire(Vec(DEPTH, UInt(2.W))) - buf_sz := buf_sz.map(i=> 0.U) - val obuf_sz_in = Mux(ibuf_buf_byp, Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half), indexing(buf_sz, CmdPtr0)) - val obuf_merge_en = WireInit(Bool(), false.B) - val obuf_merge_in = obuf_merge_en - val obuf_tag0_in = Mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) - - val obuf_tag1_in = Mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) - val obuf_cmd_done = WireInit(Bool(), false.B) - val bus_wcmd_sent = WireInit(Bool(), false.B) - val obuf_cmd_done_in = !(obuf_wr_en | obuf_rst) & (obuf_cmd_done | bus_wcmd_sent) - val obuf_data_done = WireInit(Bool(), false.B) - val bus_wdata_sent = WireInit(Bool(), false.B) - val obuf_data_done_in = !(obuf_wr_en | obuf_rst) & (obuf_data_done | bus_wdata_sent) - val obuf_aligned_in = Mux(ibuf_buf_byp, is_aligned_r, obuf_sz_in(1,0)===0.U | (obuf_sz_in(0) & !obuf_addr_in(0)) | (obuf_sz_in(1)&(!obuf_addr_in(1,0).orR))) - - val obuf_nosend_in = WireInit(Bool(), false.B) - val obuf_rdrsp_pend = WireInit(Bool(), false.B) - val bus_rsp_read = WireInit(Bool(), false.B) - val bus_rsp_read_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) - val obuf_rdrsp_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) - val obuf_write = WireInit(Bool(), false.B) - val obuf_rdrsp_pend_in = ((!(obuf_wr_en & !obuf_nosend_in) & obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag))) | (bus_cmd_sent & !obuf_write)) & !io.dec_tlu_force_halt - val obuf_rdrsp_pend_en = io.lsu_bus_clk_en | io.dec_tlu_force_halt - val obuf_tag0 = WireInit(UInt(LSU_BUS_TAG.W), 0.U) - val obuf_rdrsp_tag_in = Mux(bus_cmd_sent & !obuf_write, obuf_tag0, obuf_rdrsp_tag) - val obuf_addr = WireInit(UInt(32.W), 0.U) - val obuf_sideeffect = WireInit(Bool(), false.B) - obuf_nosend_in := (obuf_addr_in(31,3)===obuf_addr(31,3)) & obuf_aligned_in & !obuf_sideeffect & !obuf_write & !obuf_write_in & !io.tlu_busbuff.dec_tlu_external_ldfwd_disable & - ((obuf_valid & !obuf_nosend) | (obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)))) - val obuf_byteen0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(ldst_byteen_lo_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_lo_r)), - Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_byteen, CmdPtr0), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, CmdPtr0)))) - val obuf_byteen1_in = Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(ldst_byteen_hi_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_hi_r)), - Mux(indexing(buf_addr, CmdPtr1)(2).asBool(), Cat(indexing(buf_byteen, CmdPtr1), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, CmdPtr1)))) - - val obuf_data0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_lo_r, 0.U(32.W)), Cat(0.U(32.W), store_data_lo_r)), - Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_data, CmdPtr0), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, CmdPtr0)))) - val obuf_data1_in = Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(store_data_hi_r, 0.U(32.W)), Cat(0.U(32.W), store_data_hi_r)), - Mux(indexing(buf_addr, CmdPtr1)(2).asBool(), Cat(indexing(buf_data, CmdPtr1), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, CmdPtr1)))) - val obuf_byteen_in = (0 until 8).map(i=>(obuf_byteen0_in(i) | (obuf_merge_en & obuf_byteen1_in(i))).asUInt).reverse.reduce(Cat(_,_)) - val obuf_data_in = (0 until 8).map(i=>Mux(obuf_merge_en & obuf_byteen1_in(i), obuf_data1_in((8*i)+7, 8*i), obuf_data0_in((8*i)+7, 8*i))).reverse.reduce(Cat(_,_)) - - val buf_dualhi = Wire(Vec(DEPTH, Bool())) - buf_dualhi := buf_dualhi.map(i=> false.B) - obuf_merge_en := ((CmdPtr0 =/= CmdPtr1) & found_cmdptr0 & found_cmdptr1 & (indexing(buf_state, CmdPtr0) === cmd_C) & (indexing(buf_state, CmdPtr1) === cmd_C) & - !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_sideeffect, CmdPtr0) & - (!indexing(buf_write, CmdPtr0) & indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_dualhi.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0))) | - (ibuf_buf_byp & ldst_samedw_r & io.ldst_dual_r) - val obuf_wr_enQ = rvdff_fpga (obuf_wr_en,io.lsu_busm_clk,io.lsu_busm_clken,clock) - obuf_valid := withClock(io.lsu_free_c2_clk){RegNext(Mux(obuf_wr_en, true.B, obuf_valid) & !obuf_rst, false.B)} - obuf_nosend := withClock(io.lsu_free_c2_clk){RegEnable(obuf_nosend_in, false.B, obuf_wr_en)} - obuf_rdrsp_pend := withClock(io.lsu_free_c2_clk){RegEnable(obuf_rdrsp_pend_in, false.B,obuf_rdrsp_pend_en)} - obuf_cmd_done := rvdff_fpga (obuf_cmd_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) - obuf_data_done := rvdff_fpga (obuf_data_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) - obuf_rdrsp_tag := rvdff_fpga (obuf_rdrsp_tag_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) - - obuf_tag0 := rvdffs_fpga (obuf_tag0_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) - val obuf_tag1 = rvdffs_fpga (obuf_tag1_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) - val obuf_merge = rvdffs_fpga (obuf_merge_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) - obuf_write := rvdffs_fpga (obuf_write_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) - obuf_sideeffect := rvdffs_fpga (obuf_sideeffect_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) - val obuf_sz = rvdffs_fpga (obuf_sz_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) - val obuf_byteen = rvdffs_fpga (obuf_byteen_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) - obuf_addr := rvdffe(obuf_addr_in, obuf_wr_en, clock, io.scan_mode) - val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, clock, io.scan_mode) - obuf_wr_timer := rvdff_fpga (obuf_data_done_in,io.lsu_busm_clk,obuf_wr_en,clock) - val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U) - - - WrPtr0_m := MuxCase(3.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & - !((ibuf_valid & (ibuf_tag===i.U)) | (io.lsu_busreq_r & - ((WrPtr0_r === i.U) | (io.ldst_dual_r & (WrPtr1_r === i.U)))))) -> i.U)) - - - val WrPtr1_m = WireInit(UInt(DEPTH_LOG2.W), 0.U) - WrPtr1_m := MuxCase(3.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) | - (io.lsu_busreq_m & (WrPtr0_m===i.U)) | - (io.lsu_busreq_r & (((WrPtr0_r === i.U)) | - (io.ldst_dual_r & (WrPtr1_r===i.U)))))) -> i.U)) - - val buf_age = Wire(Vec(DEPTH, UInt(DEPTH.W))) - buf_age := buf_age.map(i=> 0.U) - - val CmdPtr0Dec = (0 until DEPTH).map(i=> (!(buf_age(i).orR) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_)) - val CmdPtr1Dec = (0 until DEPTH).map(i=> (!((buf_age(i) & (~CmdPtr0Dec)).orR) & !CmdPtr0Dec(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_)) - val buf_rsp_pickage = Wire(Vec(DEPTH, UInt(DEPTH.W))) - buf_rsp_pickage := buf_rsp_pickage.map(i=> 0.U) - val RspPtrDec = (0 until DEPTH).map(i=> (!(buf_rsp_pickage(i).orR) & (buf_state(i)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_)) - found_cmdptr0 := CmdPtr0Dec.orR - found_cmdptr1 := CmdPtr1Dec.orR - - def Enc8x3(in: UInt) : UInt = Cat(in(4)|in(5)|in(6)|in(7), in(2)|in(3)|in(6)|in(7), in(1)|in(3)|in(5)|in(7)) - - - - val RspPtr = WireInit(UInt(DEPTH_LOG2.W), 0.U) - CmdPtr0 := Enc8x3(Cat(Fill(8-DEPTH, 0.U),CmdPtr0Dec)) - - CmdPtr1 := Enc8x3(Cat(Fill(8-DEPTH, 0.U),CmdPtr1Dec)) - RspPtr := Enc8x3(Cat(Fill(8-DEPTH, 0.U),RspPtrDec)) - val buf_state_en = Wire(Vec(DEPTH, Bool())) - buf_state_en := buf_state_en.map(i=> false.B) - val buf_rspageQ = Wire(Vec(DEPTH, UInt(DEPTH.W))) - buf_rspageQ := buf_rspageQ.map(i=> 0.U) - val buf_rspage_set = Wire(Vec(DEPTH, UInt(DEPTH.W))) - buf_rspage_set := buf_rspage_set.map(i=> 0.U) - val buf_rspage_in = Wire(Vec(DEPTH, UInt(DEPTH.W))) - buf_rspage_in := buf_rspage_in.map(i=> 0.U) - val buf_rspage = Wire(Vec(DEPTH, UInt(DEPTH.W))) - buf_rspage := buf_rspage.map(i=> 0.U) - - val buf_age_in = (0 until DEPTH).map(i=>(0 until DEPTH).map(j=> ((((buf_state(i)===idle_C) & buf_state_en(i)) & - (((buf_state(j)===wait_C) | ((buf_state(j)===cmd_C) & !buf_cmd_state_bus_en(j))) | - (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r === i.U) & (ibuf_tag === j.U)) | - (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r === i.U) & (WrPtr0_r === j.U)))) | buf_age(i)(j)).asUInt).reverse.reduce(Cat(_,_))) - val buf_ageQ = Wire(Vec(DEPTH, UInt(DEPTH.W))) - buf_ageQ := buf_ageQ.map(i=> 0.U) - buf_age := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_ageQ(i)(j) & !((buf_state(j)===cmd_C) & buf_cmd_state_bus_en(j)) & !io.dec_tlu_force_halt ).asUInt).reverse.reduce(Cat(_,_))) - buf_age_younger := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(Mux(i.U===j.U, 0.U, !buf_age(i)(j) & (buf_state(j)=/=idle_C))).asUInt).reverse.reduce(Cat(_,_))) - buf_rsp_pickage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & (buf_state(j)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_))) - - buf_rspage_set := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(((buf_state(i)===idle_C) & buf_state_en(i)) & - (!((buf_state(j)===idle_C) | (buf_state(j)===done_C)) | - (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r===i.U) & (ibuf_tag===j.U)) | - (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r===i.U) & (WrPtr0_r===j.U)))).asUInt).reverse.reduce(Cat(_,_))) - buf_rspage_in := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspage_set(i)(j) | buf_rspage(i)(j)).asUInt).reverse.reduce(Cat(_,_))) - buf_rspage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & !((buf_state(j)===done_C) | (buf_state(j)===idle_C))& !io.dec_tlu_force_halt ).asUInt).reverse.reduce(Cat(_,_))) - ibuf_drainvec_vld := (0 until DEPTH).map(i=>(ibuf_drain_vld & (ibuf_tag === i.U)).asUInt).reverse.reduce(Cat(_,_)) - buf_byteen_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_byteen_out(3,0), - Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), ldst_byteen_hi_r(3,0), ldst_byteen_lo_r(3,0)))) - buf_addr_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_addr, Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), io.end_addr_r, io.lsu_addr_r))) - buf_dual_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_dual, io.ldst_dual_r)).asUInt).reverse.reduce(Cat(_,_)) - buf_samedw_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_samedw, ldst_samedw_r)).asUInt).reverse.reduce(Cat(_,_)) - buf_nomerge_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_nomerge | ibuf_force_drain, io.no_dword_merge_r)).asUInt).reverse.reduce(Cat(_,_)) - buf_dualhi_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_dual ,ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U))).asUInt).reverse.reduce(Cat(_,_)) - buf_dualtag_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_dualtag, Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), WrPtr0_r, WrPtr1_r))) - buf_sideeffect_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_sideeffect, io.is_sideeffects_r)).asUInt).reverse.reduce(Cat(_,_)) - buf_unsign_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_unsign, io.lsu_pkt_r.bits.unsign)).asUInt).reverse.reduce(Cat(_,_)) - buf_sz_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_sz, Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half))) - buf_write_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_write, io.lsu_pkt_r.bits.store)).asUInt).reverse.reduce(Cat(_,_)) - - for(i<- 0 until DEPTH) { - switch(buf_state(i)) { - is(idle_C) { - buf_nxtstate(i) := Mux(io.lsu_bus_clk_en.asBool(), cmd_C, wait_C) - buf_state_en(i) := (io.lsu_busreq_r & io.lsu_commit_r & (((ibuf_byp | io.ldst_dual_r) & !ibuf_merge_en & (i === WrPtr0_r)) | (ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)))) | (ibuf_drain_vld & (i === ibuf_tag)) - buf_wr_en(i) := buf_state_en(i) - buf_data_en(i) := buf_state_en(i) - buf_data_in(i) := Mux((ibuf_drain_vld & (i === ibuf_tag)).asBool(), ibuf_data_out(31, 0), store_data_lo_r(31, 0)) - buf_cmd_state_bus_en(i) := 0.U - buf_rst(i) := io.dec_tlu_force_halt - } - is(wait_C) { - buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, cmd_C) - buf_state_en(i) := io.lsu_bus_clk_en | io.dec_tlu_force_halt - buf_cmd_state_bus_en(i) := 0.U - buf_rst(i) := io.dec_tlu_force_halt - } - is(cmd_C) { - buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((obuf_nosend & bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)), done_wait_C, resp_C)) - buf_cmd_state_bus_en(i) := ((obuf_tag0 === i.asUInt(LSU_BUS_TAG.W)) | (obuf_merge & (obuf_tag1 === i.asUInt(LSU_BUS_TAG.W)))) & obuf_valid & obuf_wr_enQ - buf_state_bus_en(i) := buf_cmd_state_bus_en(i) - buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt - buf_ldfwd_in(i) := true.B - buf_ldfwd_en(i) := buf_state_en(i) & !buf_write(i) & obuf_nosend & !io.dec_tlu_force_halt - buf_ldfwdtag_in(i) := (obuf_rdrsp_tag(LSU_BUS_TAG - 2, 0)).asUInt - buf_data_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read - buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error - buf_data_in(i) := Mux(buf_error_en(i), bus_rsp_rdata(31, 0), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0))) - buf_rst(i) := io.dec_tlu_force_halt - } - is(resp_C) { - buf_nxtstate(i) := Mux((io.dec_tlu_force_halt | (buf_write(i) & !bus_rsp_write_error)).asBool(), idle_C, - Mux((buf_dual(i) & !buf_samedw(i) & !buf_write(i) & (buf_state(buf_dualtag(i)) =/= done_partial_C)), done_partial_C, - Mux((buf_ldfwd(i) | any_done_wait_state | (buf_dual(i) & !buf_samedw(i) & !buf_write(i) & indexing(buf_ldfwd,buf_dualtag(i)) & (buf_state(buf_dualtag(i)) === done_partial_C) & any_done_wait_state)), done_wait_C, done_C))) - buf_resp_state_bus_en(i) := (bus_rsp_write & (bus_rsp_write_tag === (i.asUInt(LSU_BUS_TAG.W)))) | - (bus_rsp_read & ((bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W))) | - (buf_ldfwd(i) & (bus_rsp_read_tag === (buf_ldfwdtag(i)))) | - (buf_dual(i) & buf_dualhi(i) & ~buf_write(i) & buf_samedw(i) & (bus_rsp_read_tag === (buf_dualtag(i)))))) - buf_state_bus_en(i) := buf_resp_state_bus_en(i) - buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt - buf_data_en(i) := buf_state_bus_en(i) & bus_rsp_read & io.lsu_bus_clk_en - buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W)))) | - (bus_rsp_read_error & buf_ldfwd(i) & (bus_rsp_read_tag === buf_ldfwdtag(i))) | - (bus_rsp_write_error & (bus_rsp_write_tag === i.asUInt(LSU_BUS_TAG.W)))) - buf_data_in(i) := Mux((buf_state_en(i) & !buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0)) - buf_cmd_state_bus_en(i) := 0.U - buf_rst(i) := io.dec_tlu_force_halt - } - is(done_partial_C) { // Other part of dual load hasn't returned - buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((buf_ldfwd(i) | buf_ldfwd(buf_dualtag(i)) | any_done_wait_state), done_wait_C, done_C)) - buf_state_bus_en(i) := bus_rsp_read & ((bus_rsp_read_tag === buf_dualtag(i).asUInt()) | - (buf_ldfwd(buf_dualtag(i)) & (bus_rsp_read_tag === buf_ldfwdtag(buf_dualtag(i)).asUInt()))) - buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt - buf_cmd_state_bus_en(i) := 0.U - buf_rst(i) := io.dec_tlu_force_halt - } - is(done_wait_C) { // WAIT state if there are multiple outstanding nb returns - buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, done_C) - buf_state_en(i) := ((RspPtr === i.asUInt(DEPTH_LOG2.W)) | (buf_dual(i) & (buf_dualtag(i) === RspPtr))) | io.dec_tlu_force_halt - buf_cmd_state_bus_en(i) := 0.U - buf_rst(i) := io.dec_tlu_force_halt - } - is(done_C) { - buf_nxtstate(i) := idle_C - buf_rst(i) := true.B - buf_state_en(i) := true.B - buf_ldfwd_in(i) := false.B - buf_ldfwd_en(i) := buf_state_en(i) - buf_cmd_state_bus_en(i) := 0.U - } - } - buf_state(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nxtstate(i), 0.U, buf_state_en(i).asBool())} - buf_ageQ(i) := withClock(io.lsu_bus_buf_c1_clk){RegNext(buf_age_in(i), 0.U)} - buf_rspageQ(i) := withClock(io.lsu_bus_buf_c1_clk){RegNext(buf_rspage_in(i), 0.U)} - buf_dualtag(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dualtag_in(i), 0.U, buf_wr_en(i).asBool())} - buf_dual(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dual_in(i), false.B, buf_wr_en(i).asBool())} - buf_samedw(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_samedw_in(i), false.B, buf_wr_en(i).asBool())} - buf_nomerge(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nomerge_in(i), false.B, buf_wr_en(i).asBool())} - buf_dualhi(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dualhi_in(i), false.B, buf_wr_en(i).asBool())} - } - - buf_ldfwd := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_ldfwd_in(i), false.B, buf_ldfwd_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) - buf_ldfwdtag := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_ldfwdtag_in(i), 0.U, buf_ldfwd_en(i).asBool())}) - buf_sideeffect := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_sideeffect_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) - buf_unsign := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_unsign_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) - buf_write := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_write_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) - buf_sz := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_sz_in(i), 0.U, buf_wr_en(i).asBool())}) - buf_addr := (0 until DEPTH).map(i=>rvdffe(buf_addr_in(i), buf_wr_en(i).asBool(), clock, io.scan_mode)) - buf_byteen := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_byteen_in(i), 0.U, buf_wr_en(i).asBool())}) - buf_data := (0 until DEPTH).map(i=>rvdffe(buf_data_in(i), buf_data_en(i), clock, io.scan_mode)) - buf_error := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegNext(!buf_rst(i) & Mux(buf_error_en(i), true.B, buf_error(i)), false.B)}).asUInt()).reverse.reduce(Cat(_,_)) - val buf_numvld_any = (Mux(io.ldst_dual_m, Cat(io.lsu_busreq_m, 0.U),io.lsu_busreq_m) +& Mux(io.ldst_dual_r, Cat(io.lsu_busreq_r, 0.U),io.lsu_busreq_r) +& ibuf_valid) + buf_state.map(i=>(i=/=idle_C).asUInt).reduce(_+&_) - buf_numvld_wrcmd_any := (0 until DEPTH).map(i=>(buf_write(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _) - buf_numvld_cmd_any := (0 until DEPTH).map(i=>((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _) - buf_numvld_pend_any := (0 until DEPTH).map(i=>((buf_state(i)===wait_C) | ((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i))).asUInt).reverse.reduce(_ +& _) - any_done_wait_state := (0 until DEPTH).map(i=>buf_state(i)===done_wait_C).reverse.reduce(_|_) - io.lsu_bus_buffer_pend_any := buf_numvld_pend_any.orR - io.lsu_bus_buffer_full_any := Mux(io.ldst_dual_d & io.dec_lsu_valid_raw_d, buf_numvld_any>=(DEPTH-1).U, buf_numvld_any===DEPTH.U) - io.lsu_bus_buffer_empty_any := !(buf_state.map(_.orR).reduce(_|_)) & !ibuf_valid & !obuf_valid - - io.dctl_busbuff.lsu_nonblock_load_valid_m := io.lsu_busreq_m & io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.load & !io.flush_m_up & !io.ld_full_hit_m - io.dctl_busbuff.lsu_nonblock_load_tag_m := WrPtr0_m - val lsu_nonblock_load_valid_r = WireInit(Bool(), false.B) - io.dctl_busbuff.lsu_nonblock_load_inv_r := lsu_nonblock_load_valid_r & !io.lsu_commit_r - io.dctl_busbuff.lsu_nonblock_load_inv_tag_r := WrPtr0_r - val lsu_nonblock_load_data_ready = Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (!(buf_write(i))))) - io.dctl_busbuff.lsu_nonblock_load_data_error := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (buf_error(i) & !buf_write(i)))) - io.dctl_busbuff.lsu_nonblock_load_data_tag := Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> i.U)) - val lsu_nonblock_load_data_lo = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> buf_data(i))) - val lsu_nonblock_load_data_hi = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (buf_dual(i) & buf_dualhi(i))) -> buf_data(i))) - val lsu_nonblock_addr_offset = indexing(buf_addr, io.dctl_busbuff.lsu_nonblock_load_data_tag)(1,0) - val lsu_nonblock_sz = indexing(buf_sz, io.dctl_busbuff.lsu_nonblock_load_data_tag) - val lsu_nonblock_unsign = indexing(buf_unsign, io.dctl_busbuff.lsu_nonblock_load_data_tag) - // val lsu_nonblock_dual = indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), io.dctl_busbuff.lsu_nonblock_load_data_tag) - val lsu_nonblock_data_unalgn = Cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) >> (lsu_nonblock_addr_offset * 8.U) - - io.dctl_busbuff.lsu_nonblock_load_data_valid := lsu_nonblock_load_data_ready & !io.dctl_busbuff.lsu_nonblock_load_data_error - io.dctl_busbuff.lsu_nonblock_load_data := Mux1H(Seq((lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(0.U(24.W),lsu_nonblock_data_unalgn(7,0)), - (lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(0.U(16.W),lsu_nonblock_data_unalgn(15,0)), - (!lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(Fill(24,lsu_nonblock_data_unalgn(7)), lsu_nonblock_data_unalgn(7,0)), - (!lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(Fill(16,lsu_nonblock_data_unalgn(15)), lsu_nonblock_data_unalgn(15,0)), - (lsu_nonblock_sz===2.U) -> lsu_nonblock_data_unalgn)) - bus_sideeffect_pend := (0 until DEPTH).map(i=>(buf_state(i)===resp_C) & buf_sideeffect(i) & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable).reduce(_|_) | (obuf_valid & obuf_sideeffect & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) - bus_addr_match_pending := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===resp_C)-> - ( obuf_valid & (obuf_addr(31,3)===buf_addr(i)(31,3)) & !((obuf_tag0===i.U) | (obuf_merge & (obuf_tag1===i.U)))))) - - bus_cmd_ready := Mux(obuf_write, Mux(obuf_cmd_done | obuf_data_done, Mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready), io.lsu_axi.aw.ready & io.lsu_axi.w.ready), io.lsu_axi.ar.ready) - bus_wcmd_sent := io.lsu_axi.aw.valid & io.lsu_axi.aw.ready - bus_wdata_sent := io.lsu_axi.w.valid & io.lsu_axi.w.ready - bus_cmd_sent := ((obuf_cmd_done | bus_wcmd_sent) & (obuf_data_done | bus_wdata_sent)) | (io.lsu_axi.ar.valid & io.lsu_axi.ar.ready) - bus_rsp_read := io.lsu_axi.r.valid & io.lsu_axi.r.ready - bus_rsp_write := io.lsu_axi.b.valid & io.lsu_axi.b.ready - bus_rsp_read_tag := io.lsu_axi.r.bits.id - bus_rsp_write_tag := io.lsu_axi.b.bits.id - bus_rsp_write_error := bus_rsp_write & (io.lsu_axi.b.bits.resp =/= 0.U) - bus_rsp_read_error := bus_rsp_read & (io.lsu_axi.r.bits.resp =/= 0.U) - bus_rsp_rdata := io.lsu_axi.r.bits.data - - // AXI Command signals - io.lsu_axi.aw.valid := obuf_valid & obuf_write & !obuf_cmd_done & !bus_addr_match_pending - io.lsu_axi.aw.bits.id := obuf_tag0 - io.lsu_axi.aw.bits.addr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3), 0.U(3.W))) - io.lsu_axi.aw.bits.size := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W)) - io.lsu_axi.aw.bits.prot := 1.U(3.W) - io.lsu_axi.aw.bits.cache := Mux(obuf_sideeffect, 0.U, 15.U) - io.lsu_axi.aw.bits.region := obuf_addr(31,28) - io.lsu_axi.aw.bits.len := 0.U - io.lsu_axi.aw.bits.burst := 1.U(2.W) - io.lsu_axi.aw.bits.qos := 0.U - io.lsu_axi.aw.bits.lock := 0.U - - io.lsu_axi.w.valid := obuf_valid & obuf_write & !obuf_data_done & !bus_addr_match_pending - io.lsu_axi.w.bits.strb := obuf_byteen & Fill(8, obuf_write) - io.lsu_axi.w.bits.data := obuf_data - io.lsu_axi.w.bits.last := 1.U - - io.lsu_axi.ar.valid := obuf_valid & !obuf_write & !obuf_nosend & !bus_addr_match_pending - io.lsu_axi.ar.bits.id := obuf_tag0 - io.lsu_axi.ar.bits.addr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3),0.U(3.W))) - io.lsu_axi.ar.bits.size := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W)) - io.lsu_axi.ar.bits.prot := 1.U(3.W) - io.lsu_axi.ar.bits.cache := Mux(obuf_sideeffect, 0.U(4.W), 15.U) - io.lsu_axi.ar.bits.region := obuf_addr(31,28) - io.lsu_axi.ar.bits.len := 0.U - io.lsu_axi.ar.bits.burst := 1.U(2.W) - io.lsu_axi.ar.bits.qos := 0.U - io.lsu_axi.ar.bits.lock := 0.U - io.lsu_axi.b.ready := 1.U - io.lsu_axi.r.ready := 1.U - io.tlu_busbuff.lsu_imprecise_error_store_any := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C)->(io.lsu_bus_clk_en_q & buf_error(i) & buf_write(i)))) - val lsu_imprecise_error_store_tag = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & buf_error(i) & buf_write(i))->i.U)) - - io.tlu_busbuff.lsu_imprecise_error_load_any := io.dctl_busbuff.lsu_nonblock_load_data_error & !io.tlu_busbuff.lsu_imprecise_error_store_any - io.tlu_busbuff.lsu_imprecise_error_addr_any := Mux(io.tlu_busbuff.lsu_imprecise_error_store_any, buf_addr(lsu_imprecise_error_store_tag), buf_addr(io.dctl_busbuff.lsu_nonblock_load_data_tag)) - //lsu_bus_cntr_overflow := 0.U - - // io.lsu_bus_idle_any := 1.U - - // PMU signals - io.tlu_busbuff.lsu_pmu_bus_trxn := (io.lsu_axi.aw.valid & io.lsu_axi.aw.ready) | (io.lsu_axi.w.valid & io.lsu_axi.w.ready) | (io.lsu_axi.ar.valid & io.lsu_axi.ar.ready) - io.tlu_busbuff.lsu_pmu_bus_misaligned := io.lsu_busreq_r & io.ldst_dual_r & io.lsu_commit_r - io.tlu_busbuff.lsu_pmu_bus_error := io.tlu_busbuff.lsu_imprecise_error_load_any | io.tlu_busbuff.lsu_imprecise_error_store_any - - io.tlu_busbuff.lsu_pmu_bus_busy := (io.lsu_axi.aw.valid & !io.lsu_axi.aw.ready) | (io.lsu_axi.w.valid & !io.lsu_axi.w.ready) | (io.lsu_axi.ar.valid & !io.lsu_axi.ar.ready) - - WrPtr0_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr0_m, 0.U)} - WrPtr1_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr1_m, 0.U)} - io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)} - lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)} -} -object buffer extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_buffer())) -} +//package lsu +//import chisel3._ +//import chisel3.util._ +//import lib._ +//import include._ +//import chisel3.experimental.{ChiselEnum, chiselName} +//import chisel3.util.ImplicitConversions.intToUInt +//import ifu._ +// +//@chiselName +//class lsu_bus_buffer extends Module with RequireAsyncReset with lib { +// val io = IO(new Bundle { +// val clk_override = Input(Bool()) +// val scan_mode = Input(Bool()) +// val tlu_busbuff = new tlu_busbuff() +// val dctl_busbuff = new dctl_busbuff() +// val dec_tlu_force_halt = Input(Bool()) +// val lsu_bus_obuf_c1_clken = Input(Bool()) +// val lsu_busm_clken = Input(Bool()) +// val lsu_c2_r_clk = Input(Clock()) +// val lsu_bus_ibuf_c1_clk = Input(Clock()) +// val lsu_bus_obuf_c1_clk = Input(Clock()) +// val lsu_bus_buf_c1_clk = Input(Clock()) +// val lsu_free_c2_clk = Input(Clock()) +// val lsu_busm_clk = Input(Clock()) +// val dec_lsu_valid_raw_d = Input(Bool()) +// val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t())) +// val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t())) +// val lsu_addr_m = Input(UInt(32.W)) +// val end_addr_m = Input(UInt(32.W)) +// val lsu_addr_r = Input(UInt(32.W)) +// val end_addr_r = Input(UInt(32.W)) +// val store_data_r = Input(UInt(32.W)) +// val no_word_merge_r = Input(Bool()) +// val no_dword_merge_r = Input(Bool()) +// val lsu_busreq_m = Input(Bool()) +// val ld_full_hit_m = Input(Bool()) +// val flush_m_up = Input(Bool()) +// val flush_r = Input(Bool()) +// val lsu_commit_r = Input(Bool()) +// val is_sideeffects_r = Input(Bool()) +// val ldst_dual_d = Input(Bool()) +// val ldst_dual_m = Input(Bool()) +// val ldst_dual_r = Input(Bool()) +// val ldst_byteen_ext_m = Input(UInt(8.W)) +// val lsu_axi = new axi_channels(LSU_BUS_TAG) +// val lsu_bus_clk_en = Input(Bool()) +// val lsu_bus_clk_en_q = Input(Bool()) +// +// val lsu_busreq_r = Output(Bool()) +// val lsu_bus_buffer_pend_any = Output(Bool()) +// val lsu_bus_buffer_full_any = Output(Bool()) +// val lsu_bus_buffer_empty_any = Output(Bool()) +// // val lsu_bus_idle_any = Output(Bool()) +// val ld_byte_hit_buf_lo = Output((UInt(4.W))) +// val ld_byte_hit_buf_hi = Output((UInt(4.W))) +// val ld_fwddata_buf_lo = Output((UInt(32.W))) +// val ld_fwddata_buf_hi = Output((UInt(32.W))) +// }) +// def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) +// def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) +// +// val DEPTH = LSU_NUM_NBLOAD +// val DEPTH_LOG2 = LSU_NUM_NBLOAD_WIDTH +// val TIMER = 8 +// val TIMER_MAX = TIMER - 1 +// val TIMER_LOG2 = if (TIMER < 2) 1 else log2Ceil(TIMER) +// +// val idle_C :: wait_C :: cmd_C :: resp_C :: done_partial_C :: done_wait_C :: done_C :: Nil = Enum(7) +// val buf_addr = Wire(Vec(DEPTH, UInt(32.W))) +// val buf_state = Wire(Vec(DEPTH, UInt(3.W))) +// val buf_write = WireInit(UInt(DEPTH.W), 0.U) +// val CmdPtr0 = WireInit(UInt(DEPTH_LOG2.W), 0.U) +// +// +// val ldst_byteen_hi_m = io.ldst_byteen_ext_m(7, 4) +// val ldst_byteen_lo_m = io.ldst_byteen_ext_m(3, 0) +// +// val ld_addr_hitvec_lo = (0 until DEPTH).map(i => (io.lsu_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m) +// val ld_addr_hitvec_hi = (0 until DEPTH).map(i => (io.end_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m) +// val ld_byte_hitvecfn_lo = Wire(Vec(4, UInt(DEPTH.W))) +// val ld_byte_ibuf_hit_lo = WireInit(UInt(4.W), 0.U) +// val ld_byte_hitvecfn_hi = Wire(Vec(4, UInt(DEPTH.W))) +// val ld_byte_ibuf_hit_hi = WireInit(UInt(4.W), 0.U) +// val buf_byteen = Wire(Vec(DEPTH, UInt(4.W))) +// buf_byteen := buf_byteen.map(i=>0.U) +// val buf_nxtstate = Wire(Vec(DEPTH, UInt(3.W))) +// buf_nxtstate := buf_nxtstate.map(i=>0.U) +// val buf_wr_en = Wire(Vec(DEPTH, Bool())) +// buf_wr_en := buf_wr_en.map(i=> false.B) +// val buf_data_en = Wire(Vec(DEPTH, Bool())) +// buf_data_en := buf_data_en.map(i=> false.B) +// val buf_state_bus_en = Wire(Vec(DEPTH, Bool())) +// buf_state_bus_en := buf_state_bus_en.map(i=> false.B) +// val buf_ldfwd_in = Wire(Vec(DEPTH, Bool())) +// buf_ldfwd_in := buf_ldfwd_in.map(i=> false.B) +// val buf_ldfwd_en = Wire(Vec(DEPTH, Bool())) +// buf_ldfwd_en := buf_ldfwd_en.map(i=> io.dec_tlu_force_halt) +// val buf_data_in = Wire(Vec(DEPTH, UInt(32.W))) +// buf_data_in := buf_data_in.map(i=> 0.U) +// val buf_ldfwdtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) +// buf_ldfwdtag_in := buf_ldfwdtag_in.map(i=> 0.U) +// val buf_error_en = Wire(Vec(DEPTH, Bool())) +// buf_error_en := buf_error_en.map(i=> false.B) +// val bus_rsp_read_error = WireInit(Bool(), false.B) +// val bus_rsp_rdata = WireInit(UInt(64.W), 0.U) +// val bus_rsp_write_error = WireInit(Bool(), false.B) +// val buf_dualtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) +// buf_dualtag := buf_dualtag.map(i=> 0.U) +// val buf_ldfwd = WireInit(UInt(DEPTH.W), 0.U) +// val buf_resp_state_bus_en = Wire(Vec(DEPTH, Bool())) +// buf_resp_state_bus_en := buf_resp_state_bus_en.map(i=> false.B) +// val any_done_wait_state = WireInit(Bool(), false.B) +// val bus_rsp_write = WireInit(Bool(), false.B) +// val bus_rsp_write_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) +// val buf_ldfwdtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) +// buf_ldfwdtag := buf_ldfwdtag.map(i=> 0.U) +// val buf_rst = Wire(Vec(DEPTH, Bool())) +// buf_rst := buf_rst.map(i=> false.B) +// val ibuf_drainvec_vld = WireInit(UInt(DEPTH.W), 0.U) +// val buf_byteen_in = Wire(Vec(DEPTH, UInt(DEPTH.W))) +// buf_byteen_in := buf_byteen_in.map(i=> 0.U) +// val buf_addr_in = Wire(Vec(DEPTH, UInt(32.W))) +// buf_addr_in := buf_addr_in.map(i=> 0.U) +// val buf_dual_in = WireInit(UInt(DEPTH.W), 0.U) +// val buf_samedw_in = WireInit(UInt(DEPTH.W), 0.U) +// val buf_nomerge_in = WireInit(UInt(DEPTH.W), 0.U) +// val buf_dualhi_in = WireInit(UInt(DEPTH.W), 0.U) +// val buf_dualtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) +// buf_dualtag_in := buf_dualtag_in.map(i=> 0.U) +// val buf_sideeffect_in = WireInit(UInt(DEPTH.W), 0.U) +// val buf_unsign_in = WireInit(UInt(DEPTH.W), 0.U) +// val buf_sz_in = Wire(Vec(DEPTH, UInt(2.W))) +// buf_sz_in := buf_sz_in.map(i=> 0.U) +// val buf_write_in = WireInit(UInt(DEPTH.W), 0.U) +// val buf_unsign = WireInit(UInt(DEPTH.W), 0.U) +// val buf_error = WireInit(UInt(DEPTH.W), 0.U) +// val CmdPtr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U) +// +// val ibuf_data = WireInit(UInt(32.W), 0.U) +// io.ld_byte_hit_buf_lo := (0 until 4).map(i => (ld_byte_hitvecfn_lo(i).orR | ld_byte_ibuf_hit_lo(i)).asUInt).reverse.reduce(Cat(_, _)) +// io.ld_byte_hit_buf_hi := (0 until 4).map(i => (ld_byte_hitvecfn_hi(i).orR | ld_byte_ibuf_hit_hi(i)).asUInt).reverse.reduce(Cat(_, _)) +// +// val ld_byte_hitvec_lo = (0 until 4).map(j => (0 until DEPTH).map(i => (ld_addr_hitvec_lo(i) & buf_byteen(i)(j) & ldst_byteen_lo_m(j)).asUInt).reverse.reduce(Cat(_, _))) +// val ld_byte_hitvec_hi = (0 until 4).map(j => (0 until DEPTH).map(i => (ld_addr_hitvec_hi(i) & buf_byteen(i)(j) & ldst_byteen_hi_m(j)).asUInt).reverse.reduce(Cat(_, _))) +// +// val buf_age_younger = Wire(Vec(DEPTH, UInt(DEPTH.W))) +// buf_age_younger := buf_age_younger.map(i=> 0.U) +// ld_byte_hitvecfn_lo := (0 until 4).map(j => (0 until DEPTH).map(i => (ld_byte_hitvec_lo(j)(i) & !(ld_byte_hitvec_lo(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_lo(j)).asUInt).reverse.reduce(Cat(_, _))) +// ld_byte_hitvecfn_hi := (0 until 4).map(j => (0 until DEPTH).map(i => (ld_byte_hitvec_hi(j)(i) & !(ld_byte_hitvec_hi(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_hi(j)).asUInt).reverse.reduce(Cat(_, _))) +// +// val ibuf_addr = WireInit(UInt(32.W), 0.U) +// val ibuf_write = WireInit(Bool(), false.B) +// val ibuf_valid = WireInit(Bool(), false.B) +// val ld_addr_ibuf_hit_lo = (io.lsu_addr_m(31, 2) === ibuf_addr(31, 2)) & ibuf_write & ibuf_valid & io.lsu_busreq_m +// val ld_addr_ibuf_hit_hi = (io.end_addr_m(31, 2) === ibuf_addr(31, 2)) & ibuf_write & ibuf_valid & io.lsu_busreq_m +// +// val ibuf_byteen = WireInit(UInt(4.W), 0.U) +// +// ld_byte_ibuf_hit_lo := Fill(4, ld_addr_ibuf_hit_lo) & ibuf_byteen & ldst_byteen_lo_m +// ld_byte_ibuf_hit_hi := Fill(4, ld_addr_ibuf_hit_hi) & ibuf_byteen & ldst_byteen_hi_m +// +// val buf_data = Wire(Vec(DEPTH, UInt(32.W))) +// buf_data := buf_data.map(i=> 0.U) +// val fwd_data = WireInit(UInt(32.W), 0.U) +// val ld_fwddata_buf_lo_initial = (0 until 4).map(i=>Fill(8, ld_byte_ibuf_hit_lo(i))).reverse.reduce(Cat(_,_)) +// val ld_fwddata_buf_hi_initial = (0 until 4).map(i=>Fill(8, ld_byte_ibuf_hit_hi(i))).reverse.reduce(Cat(_,_)) +// io.ld_fwddata_buf_lo := Cat((0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(3)(i)) & buf_data(i)(31, 24)).reduce(_ | _), +// (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(2)(i)) & buf_data(i)(23, 16)).reduce(_ | _), +// (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(1)(i)) & buf_data(i)(15, 8)).reduce(_ | _), +// (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(0)(i)) & buf_data(i)(7 , 0)).reduce(_ | _)) | +// (ld_fwddata_buf_lo_initial & ibuf_data) +// +// io.ld_fwddata_buf_hi := Cat((0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(3)(i)) & buf_data(i)(31, 24)).reduce(_ | _), +// (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(2)(i)) & buf_data(i)(23, 16)).reduce(_ | _), +// (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(1)(i)) & buf_data(i)(15, 8)).reduce(_ | _), +// (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(0)(i)) & buf_data(i)(7 , 0)).reduce(_ | _)) | +// (ld_fwddata_buf_hi_initial & ibuf_data) +// +// val bus_coalescing_disable = io.tlu_busbuff.dec_tlu_wb_coalescing_disable | BUILD_AHB_LITE.B +// val ldst_byteen_r = Mux1H(Seq(io.lsu_pkt_r.bits.by -> 1.U(4.W), +// io.lsu_pkt_r.bits.half -> 3.U(4.W), +// io.lsu_pkt_r.bits.word -> 15.U(4.W))) +// +// val ldst_byteen_hi_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->0.U(4.W), +// (io.lsu_addr_r(1,0)===1.U)->Cat(0.U(3.W), ldst_byteen_r(3)), +// (io.lsu_addr_r(1,0)===2.U)->Cat(0.U(2.W), ldst_byteen_r(3,2)), +// (io.lsu_addr_r(1,0)===3.U)->Cat(0.U(1.W), ldst_byteen_r(3,1)))) +// +// val ldst_byteen_lo_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->ldst_byteen_r, +// (io.lsu_addr_r(1,0)===1.U)->Cat(ldst_byteen_r(2,0), 0.U), +// (io.lsu_addr_r(1,0)===2.U)->Cat(ldst_byteen_r(1,0), 0.U(2.W)), +// (io.lsu_addr_r(1,0)===3.U)->Cat(ldst_byteen_r(0) , 0.U(3.W)))) +// +// val store_data_hi_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->0.U(32.W), +// (io.lsu_addr_r(1,0)===1.U)->Cat(0.U(24.W) , io.store_data_r(31,24)), +// (io.lsu_addr_r(1,0)===2.U)->Cat(0.U(16.W), io.store_data_r(31,16)), +// (io.lsu_addr_r(1,0)===3.U)->Cat(0.U(8.W), io.store_data_r(31,8)))) +// +// val store_data_lo_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->io.store_data_r, +// (io.lsu_addr_r(1,0)===1.U)->Cat(io.store_data_r(23,0), 0.U(8.W)), +// (io.lsu_addr_r(1,0)===2.U)->Cat(io.store_data_r(15,0), 0.U(16.W)), +// (io.lsu_addr_r(1,0)===3.U)->Cat(io.store_data_r(7 ,0) , 0.U(24.W)))) +// +// +// val ldst_samedw_r = io.lsu_addr_r(3) === io.end_addr_r(3) +// val is_aligned_r = Mux1H(Seq(io.lsu_pkt_r.bits.word -> (io.lsu_addr_r(1, 0) === 0.U), +// io.lsu_pkt_r.bits.half -> !io.lsu_addr_r(0), +// io.lsu_pkt_r.bits.by -> 1.U)) +// val ibuf_byp = io.lsu_busreq_r & (io.lsu_pkt_r.bits.load | io.no_word_merge_r) & !ibuf_valid +// val ibuf_wr_en = io.lsu_busreq_r & io.lsu_commit_r & !ibuf_byp +// val ibuf_drain_vld = WireInit(Bool(), false.B) +// val ibuf_rst = (ibuf_drain_vld & !ibuf_wr_en) | io.dec_tlu_force_halt +// val ibuf_force_drain = io.lsu_busreq_m & !io.lsu_busreq_r & ibuf_valid & (io.lsu_pkt_m.bits.load | (ibuf_addr(31, 2) =/= io.lsu_addr_m(31, 2))) +// val ibuf_sideeffect = WireInit(Bool(), false.B) +// val ibuf_timer = WireInit(UInt(TIMER_LOG2.W), 0.U) +// val ibuf_merge_en = WireInit(Bool(), false.B) +// val ibuf_merge_in = WireInit(Bool(), false.B) +// ibuf_drain_vld := ibuf_valid & (((ibuf_wr_en | (ibuf_timer === TIMER_MAX.U)) & !(ibuf_merge_en & ibuf_merge_in)) +// | ibuf_byp | ibuf_force_drain | ibuf_sideeffect | !ibuf_write | bus_coalescing_disable) +// val ibuf_tag = WireInit(UInt(DEPTH_LOG2.W), 0.U) +// val WrPtr1_r = WireInit(UInt(DEPTH_LOG2.W), 0.U) +// val WrPtr0_r = WireInit(UInt(DEPTH_LOG2.W), 0.U) +// +// val ibuf_tag_in = Mux(ibuf_merge_en & ibuf_merge_in, ibuf_tag, Mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r)) +// val ibuf_dualtag_in = WrPtr0_r +// val ibuf_sz_in = Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) +// val ibuf_addr_in = Mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) +// val ibuf_byteen_in = Mux(ibuf_merge_en & ibuf_merge_in, ibuf_byteen(3, 0) | ldst_byteen_lo_r(3, 0), +// Mux(io.ldst_dual_r, ldst_byteen_hi_r(3, 0), ldst_byteen_lo_r(3, 0))) +// +// +// val ibuf_data_in = (0 until 4).map(i => Mux(ibuf_merge_en & ibuf_merge_in, +// Mux(ldst_byteen_lo_r(i), store_data_lo_r((8 * i) + 7, 8 * i), ibuf_data((8 * i) + 7, 8 * i)), +// Mux(io.ldst_dual_r, store_data_hi_r((8 * i) + 7, 8 * i), store_data_lo_r((8 * i) + 7, 8 * i)))).reverse.reduce(Cat(_, _)) +// val ibuf_timer_in = Mux(ibuf_wr_en, 0.U, Mux((ibuf_timer < TIMER_MAX.U).asBool(), ibuf_timer+1.U, ibuf_timer)) +// +// ibuf_merge_en := io.lsu_busreq_r & io.lsu_commit_r & io.lsu_pkt_r.bits.store & ibuf_valid & ibuf_write & (io.lsu_addr_r(31,2) === ibuf_addr(31,2)) & !io.is_sideeffects_r & !bus_coalescing_disable +// ibuf_merge_in := !io.ldst_dual_r +// val ibuf_byteen_out = (0 until 4).map(i=>(Mux(ibuf_merge_en & !ibuf_merge_in, ibuf_byteen(i) | ldst_byteen_lo_r(i), ibuf_byteen(i))).asUInt).reverse.reduce(Cat(_,_)) +// val ibuf_data_out = (0 until 4).map(i=>Mux(ibuf_merge_en & !ibuf_merge_in, Mux(ldst_byteen_lo_r(i), store_data_lo_r((8*i)+7, 8*i), ibuf_data((8*i)+7, 8*i)), ibuf_data((8*i)+7, 8*i))).reverse.reduce(Cat(_,_)) +// +// ibuf_valid := withClock(io.lsu_free_c2_clk){RegNext(Mux(ibuf_wr_en, true.B, ibuf_valid) & !ibuf_rst, false.B)} +// ibuf_tag := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_tag_in, 0.U, ibuf_wr_en)} +// val ibuf_dualtag = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_dualtag_in, 0.U, ibuf_wr_en)} +// val ibuf_dual = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.ldst_dual_r, 0.U, ibuf_wr_en)} +// val ibuf_samedw = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ldst_samedw_r, 0.U, ibuf_wr_en)} +// val ibuf_nomerge = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.no_dword_merge_r, 0.U, ibuf_wr_en)} +// ibuf_sideeffect := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.is_sideeffects_r, 0.U, ibuf_wr_en)} +// val ibuf_unsign = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.bits.unsign, 0.U, ibuf_wr_en)} +// ibuf_write := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.bits.store, 0.U, ibuf_wr_en)} +// val ibuf_sz = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_sz_in, 0.U, ibuf_wr_en)} +// ibuf_addr := rvdffe(ibuf_addr_in, ibuf_wr_en, clock, io.scan_mode) +// ibuf_byteen := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_byteen_in, 0.U, ibuf_wr_en)} +// ibuf_data := rvdffe(ibuf_data_in, ibuf_wr_en, clock, io.scan_mode) +// ibuf_timer := withClock(io.lsu_free_c2_clk) {RegNext(ibuf_timer_in, 0.U)} +// val buf_numvld_wrcmd_any = WireInit(UInt(4.W), 0.U) +// val buf_numvld_cmd_any = WireInit(UInt(4.W), 0.U) +// val obuf_wr_timer = WireInit(UInt(TIMER_LOG2.W), 0.U) +// val buf_nomerge = Wire(Vec(DEPTH, Bool())) +// buf_nomerge := buf_nomerge.map(i=> false.B) +// +// val buf_sideeffect = WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U) +// val obuf_force_wr_en = WireInit(Bool(), false.B) +// val obuf_wr_en = WireInit(Bool(), false.B) +// val obuf_wr_wait = (buf_numvld_wrcmd_any===1.U) & (buf_numvld_cmd_any===1.U) & (obuf_wr_timer =/= TIMER_MAX.U) & +// !bus_coalescing_disable & !Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(CmdPtr0===i.U)->buf_nomerge(i))) & +// !Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(CmdPtr0===i.U)->buf_sideeffect(i))) & !obuf_force_wr_en +// val obuf_wr_timer_in = Mux(obuf_wr_en, 0.U(3.W), Mux(buf_numvld_cmd_any.orR & (obuf_wr_timer(CmdPtr0===i.U)->buf_addr(i)(31,2)))) +// val buf_numvld_pend_any = WireInit(UInt(4.W), 0.U) +// val ibuf_buf_byp = ibuf_byp & (buf_numvld_pend_any===0.U) & (!io.lsu_pkt_r.bits.store | io.no_dword_merge_r) +// val bus_sideeffect_pend = WireInit(Bool(), false.B) +// val found_cmdptr0 = WireInit(Bool(), false.B) +// val buf_cmd_state_bus_en = Wire(Vec(DEPTH, Bool())) +// buf_cmd_state_bus_en := buf_cmd_state_bus_en.map(i=> false.B) +// val buf_dual = Wire(Vec(DEPTH, Bool())) +// buf_dual := buf_dual.map(i=> false.B) +// val buf_samedw = Wire(Vec(DEPTH, Bool())) +// buf_samedw := buf_samedw.map(i=> false.B) +// val found_cmdptr1 = WireInit(Bool(), false.B) +// val bus_cmd_ready = WireInit(Bool(), false.B) +// val obuf_valid = WireInit(Bool(), false.B) +// val obuf_nosend = WireInit(Bool(), false.B) +// // val lsu_bus_cntr_overflow = WireInit(Bool(), false.B) +// val bus_addr_match_pending = WireInit(Bool(), false.B) +// +// obuf_wr_en := ((ibuf_buf_byp & io.lsu_commit_r & !(io.is_sideeffects_r & bus_sideeffect_pend)) | +// ((indexing(buf_state, CmdPtr0) === cmd_C) & +// found_cmdptr0 & !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !(indexing(buf_sideeffect, CmdPtr0) & bus_sideeffect_pend) & +// (!(indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_write, CmdPtr0)) | found_cmdptr1 | indexing(buf_nomerge.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) | +// obuf_force_wr_en))) & (bus_cmd_ready | !obuf_valid | obuf_nosend) & !obuf_wr_wait & !bus_addr_match_pending & io.lsu_bus_clk_en +// +// val bus_cmd_sent = WireInit(Bool(), false.B) +// val obuf_rst = ((bus_cmd_sent | (obuf_valid & obuf_nosend)) & !obuf_wr_en & io.lsu_bus_clk_en) | io.dec_tlu_force_halt +// val obuf_write_in = Mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, indexing(buf_write, CmdPtr0)) +// val obuf_sideeffect_in = Mux(ibuf_buf_byp, io.is_sideeffects_r, indexing(buf_sideeffect, CmdPtr0)) +// val obuf_addr_in = Mux(ibuf_buf_byp, io.lsu_addr_r, indexing(buf_addr, CmdPtr0)) +// val buf_sz = Wire(Vec(DEPTH, UInt(2.W))) +// buf_sz := buf_sz.map(i=> 0.U) +// val obuf_sz_in = Mux(ibuf_buf_byp, Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half), indexing(buf_sz, CmdPtr0)) +// val obuf_merge_en = WireInit(Bool(), false.B) +// val obuf_merge_in = obuf_merge_en +// val obuf_tag0_in = Mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) +// +// val obuf_tag1_in = Mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) +// val obuf_cmd_done = WireInit(Bool(), false.B) +// val bus_wcmd_sent = WireInit(Bool(), false.B) +// val obuf_cmd_done_in = !(obuf_wr_en | obuf_rst) & (obuf_cmd_done | bus_wcmd_sent) +// val obuf_data_done = WireInit(Bool(), false.B) +// val bus_wdata_sent = WireInit(Bool(), false.B) +// val obuf_data_done_in = !(obuf_wr_en | obuf_rst) & (obuf_data_done | bus_wdata_sent) +// val obuf_aligned_in = Mux(ibuf_buf_byp, is_aligned_r, obuf_sz_in(1,0)===0.U | (obuf_sz_in(0) & !obuf_addr_in(0)) | (obuf_sz_in(1)&(!obuf_addr_in(1,0).orR))) +// +// val obuf_nosend_in = WireInit(Bool(), false.B) +// val obuf_rdrsp_pend = WireInit(Bool(), false.B) +// val bus_rsp_read = WireInit(Bool(), false.B) +// val bus_rsp_read_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) +// val obuf_rdrsp_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) +// val obuf_write = WireInit(Bool(), false.B) +// val obuf_rdrsp_pend_in = ((!(obuf_wr_en & !obuf_nosend_in) & obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag))) | (bus_cmd_sent & !obuf_write)) & !io.dec_tlu_force_halt +// val obuf_rdrsp_pend_en = io.lsu_bus_clk_en | io.dec_tlu_force_halt +// val obuf_tag0 = WireInit(UInt(LSU_BUS_TAG.W), 0.U) +// val obuf_rdrsp_tag_in = Mux(bus_cmd_sent & !obuf_write, obuf_tag0, obuf_rdrsp_tag) +// val obuf_addr = WireInit(UInt(32.W), 0.U) +// val obuf_sideeffect = WireInit(Bool(), false.B) +// obuf_nosend_in := (obuf_addr_in(31,3)===obuf_addr(31,3)) & obuf_aligned_in & !obuf_sideeffect & !obuf_write & !obuf_write_in & !io.tlu_busbuff.dec_tlu_external_ldfwd_disable & +// ((obuf_valid & !obuf_nosend) | (obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)))) +// val obuf_byteen0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(ldst_byteen_lo_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_lo_r)), +// Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_byteen, CmdPtr0), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, CmdPtr0)))) +// val obuf_byteen1_in = Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(ldst_byteen_hi_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_hi_r)), +// Mux(indexing(buf_addr, CmdPtr1)(2).asBool(), Cat(indexing(buf_byteen, CmdPtr1), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, CmdPtr1)))) +// +// val obuf_data0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_lo_r, 0.U(32.W)), Cat(0.U(32.W), store_data_lo_r)), +// Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_data, CmdPtr0), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, CmdPtr0)))) +// val obuf_data1_in = Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(store_data_hi_r, 0.U(32.W)), Cat(0.U(32.W), store_data_hi_r)), +// Mux(indexing(buf_addr, CmdPtr1)(2).asBool(), Cat(indexing(buf_data, CmdPtr1), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, CmdPtr1)))) +// val obuf_byteen_in = (0 until 8).map(i=>(obuf_byteen0_in(i) | (obuf_merge_en & obuf_byteen1_in(i))).asUInt).reverse.reduce(Cat(_,_)) +// val obuf_data_in = (0 until 8).map(i=>Mux(obuf_merge_en & obuf_byteen1_in(i), obuf_data1_in((8*i)+7, 8*i), obuf_data0_in((8*i)+7, 8*i))).reverse.reduce(Cat(_,_)) +// +// val buf_dualhi = Wire(Vec(DEPTH, Bool())) +// buf_dualhi := buf_dualhi.map(i=> false.B) +// obuf_merge_en := ((CmdPtr0 =/= CmdPtr1) & found_cmdptr0 & found_cmdptr1 & (indexing(buf_state, CmdPtr0) === cmd_C) & (indexing(buf_state, CmdPtr1) === cmd_C) & +// !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_sideeffect, CmdPtr0) & +// (!indexing(buf_write, CmdPtr0) & indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_dualhi.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0))) | +// (ibuf_buf_byp & ldst_samedw_r & io.ldst_dual_r) +// val obuf_wr_enQ = rvdff_fpga (obuf_wr_en,io.lsu_busm_clk,io.lsu_busm_clken,clock) +// obuf_valid := withClock(io.lsu_free_c2_clk){RegNext(Mux(obuf_wr_en, true.B, obuf_valid) & !obuf_rst, false.B)} +// obuf_nosend := withClock(io.lsu_free_c2_clk){RegEnable(obuf_nosend_in, false.B, obuf_wr_en)} +// obuf_rdrsp_pend := withClock(io.lsu_free_c2_clk){RegEnable(obuf_rdrsp_pend_in, false.B,obuf_rdrsp_pend_en)} +// obuf_cmd_done := rvdff_fpga (obuf_cmd_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) +// obuf_data_done := rvdff_fpga (obuf_data_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) +// obuf_rdrsp_tag := rvdff_fpga (obuf_rdrsp_tag_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) +// +// obuf_tag0 := rvdffs_fpga (obuf_tag0_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) +// val obuf_tag1 = rvdffs_fpga (obuf_tag1_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) +// val obuf_merge = rvdffs_fpga (obuf_merge_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) +// obuf_write := rvdffs_fpga (obuf_write_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) +// obuf_sideeffect := rvdffs_fpga (obuf_sideeffect_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) +// val obuf_sz = rvdffs_fpga (obuf_sz_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) +// val obuf_byteen = rvdffs_fpga (obuf_byteen_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) +// obuf_addr := rvdffe(obuf_addr_in, obuf_wr_en, clock, io.scan_mode) +// val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, clock, io.scan_mode) +// obuf_wr_timer := rvdff_fpga (obuf_data_done_in,io.lsu_busm_clk,obuf_wr_en,clock) +// val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U) +// +// +// WrPtr0_m := MuxCase(3.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & +// !((ibuf_valid & (ibuf_tag===i.U)) | (io.lsu_busreq_r & +// ((WrPtr0_r === i.U) | (io.ldst_dual_r & (WrPtr1_r === i.U)))))) -> i.U)) +// +// +// val WrPtr1_m = WireInit(UInt(DEPTH_LOG2.W), 0.U) +// WrPtr1_m := MuxCase(3.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) | +// (io.lsu_busreq_m & (WrPtr0_m===i.U)) | +// (io.lsu_busreq_r & (((WrPtr0_r === i.U)) | +// (io.ldst_dual_r & (WrPtr1_r===i.U)))))) -> i.U)) +// +// val buf_age = Wire(Vec(DEPTH, UInt(DEPTH.W))) +// buf_age := buf_age.map(i=> 0.U) +// +// val CmdPtr0Dec = (0 until DEPTH).map(i=> (!(buf_age(i).orR) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_)) +// val CmdPtr1Dec = (0 until DEPTH).map(i=> (!((buf_age(i) & (~CmdPtr0Dec)).orR) & !CmdPtr0Dec(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_)) +// val buf_rsp_pickage = Wire(Vec(DEPTH, UInt(DEPTH.W))) +// buf_rsp_pickage := buf_rsp_pickage.map(i=> 0.U) +// val RspPtrDec = (0 until DEPTH).map(i=> (!(buf_rsp_pickage(i).orR) & (buf_state(i)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_)) +// found_cmdptr0 := CmdPtr0Dec.orR +// found_cmdptr1 := CmdPtr1Dec.orR +// +// def Enc8x3(in: UInt) : UInt = Cat(in(4)|in(5)|in(6)|in(7), in(2)|in(3)|in(6)|in(7), in(1)|in(3)|in(5)|in(7)) +// +// +// +// val RspPtr = WireInit(UInt(DEPTH_LOG2.W), 0.U) +// CmdPtr0 := Enc8x3(Cat(Fill(8-DEPTH, 0.U),CmdPtr0Dec)) +// +// CmdPtr1 := Enc8x3(Cat(Fill(8-DEPTH, 0.U),CmdPtr1Dec)) +// RspPtr := Enc8x3(Cat(Fill(8-DEPTH, 0.U),RspPtrDec)) +// val buf_state_en = Wire(Vec(DEPTH, Bool())) +// buf_state_en := buf_state_en.map(i=> false.B) +// val buf_rspageQ = Wire(Vec(DEPTH, UInt(DEPTH.W))) +// buf_rspageQ := buf_rspageQ.map(i=> 0.U) +// val buf_rspage_set = Wire(Vec(DEPTH, UInt(DEPTH.W))) +// buf_rspage_set := buf_rspage_set.map(i=> 0.U) +// val buf_rspage_in = Wire(Vec(DEPTH, UInt(DEPTH.W))) +// buf_rspage_in := buf_rspage_in.map(i=> 0.U) +// val buf_rspage = Wire(Vec(DEPTH, UInt(DEPTH.W))) +// buf_rspage := buf_rspage.map(i=> 0.U) +// +// val buf_age_in = (0 until DEPTH).map(i=>(0 until DEPTH).map(j=> ((((buf_state(i)===idle_C) & buf_state_en(i)) & +// (((buf_state(j)===wait_C) | ((buf_state(j)===cmd_C) & !buf_cmd_state_bus_en(j))) | +// (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r === i.U) & (ibuf_tag === j.U)) | +// (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r === i.U) & (WrPtr0_r === j.U)))) | buf_age(i)(j)).asUInt).reverse.reduce(Cat(_,_))) +// val buf_ageQ = Wire(Vec(DEPTH, UInt(DEPTH.W))) +// buf_ageQ := buf_ageQ.map(i=> 0.U) +// buf_age := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_ageQ(i)(j) & !((buf_state(j)===cmd_C) & buf_cmd_state_bus_en(j)) & !io.dec_tlu_force_halt ).asUInt).reverse.reduce(Cat(_,_))) +// buf_age_younger := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(Mux(i.U===j.U, 0.U, !buf_age(i)(j) & (buf_state(j)=/=idle_C))).asUInt).reverse.reduce(Cat(_,_))) +// buf_rsp_pickage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & (buf_state(j)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_))) +// +// buf_rspage_set := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(((buf_state(i)===idle_C) & buf_state_en(i)) & +// (!((buf_state(j)===idle_C) | (buf_state(j)===done_C)) | +// (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r===i.U) & (ibuf_tag===j.U)) | +// (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r===i.U) & (WrPtr0_r===j.U)))).asUInt).reverse.reduce(Cat(_,_))) +// buf_rspage_in := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspage_set(i)(j) | buf_rspage(i)(j)).asUInt).reverse.reduce(Cat(_,_))) +// buf_rspage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & !((buf_state(j)===done_C) | (buf_state(j)===idle_C))& !io.dec_tlu_force_halt ).asUInt).reverse.reduce(Cat(_,_))) +// ibuf_drainvec_vld := (0 until DEPTH).map(i=>(ibuf_drain_vld & (ibuf_tag === i.U)).asUInt).reverse.reduce(Cat(_,_)) +// buf_byteen_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_byteen_out(3,0), +// Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), ldst_byteen_hi_r(3,0), ldst_byteen_lo_r(3,0)))) +// buf_addr_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_addr, Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), io.end_addr_r, io.lsu_addr_r))) +// buf_dual_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_dual, io.ldst_dual_r)).asUInt).reverse.reduce(Cat(_,_)) +// buf_samedw_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_samedw, ldst_samedw_r)).asUInt).reverse.reduce(Cat(_,_)) +// buf_nomerge_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_nomerge | ibuf_force_drain, io.no_dword_merge_r)).asUInt).reverse.reduce(Cat(_,_)) +// buf_dualhi_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_dual ,ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U))).asUInt).reverse.reduce(Cat(_,_)) +// buf_dualtag_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_dualtag, Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), WrPtr0_r, WrPtr1_r))) +// buf_sideeffect_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_sideeffect, io.is_sideeffects_r)).asUInt).reverse.reduce(Cat(_,_)) +// buf_unsign_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_unsign, io.lsu_pkt_r.bits.unsign)).asUInt).reverse.reduce(Cat(_,_)) +// buf_sz_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_sz, Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half))) +// buf_write_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_write, io.lsu_pkt_r.bits.store)).asUInt).reverse.reduce(Cat(_,_)) +// +// for(i<- 0 until DEPTH) { +// switch(buf_state(i)) { +// is(idle_C) { +// buf_nxtstate(i) := Mux(io.lsu_bus_clk_en.asBool(), cmd_C, wait_C) +// buf_state_en(i) := (io.lsu_busreq_r & io.lsu_commit_r & (((ibuf_byp | io.ldst_dual_r) & !ibuf_merge_en & (i === WrPtr0_r)) | (ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)))) | (ibuf_drain_vld & (i === ibuf_tag)) +// buf_wr_en(i) := buf_state_en(i) +// buf_data_en(i) := buf_state_en(i) +// buf_data_in(i) := Mux((ibuf_drain_vld & (i === ibuf_tag)).asBool(), ibuf_data_out(31, 0), store_data_lo_r(31, 0)) +// buf_cmd_state_bus_en(i) := 0.U +// buf_rst(i) := io.dec_tlu_force_halt +// } +// is(wait_C) { +// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, cmd_C) +// buf_state_en(i) := io.lsu_bus_clk_en | io.dec_tlu_force_halt +// buf_cmd_state_bus_en(i) := 0.U +// buf_rst(i) := io.dec_tlu_force_halt +// } +// is(cmd_C) { +// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((obuf_nosend & bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)), done_wait_C, resp_C)) +// buf_cmd_state_bus_en(i) := ((obuf_tag0 === i.asUInt(LSU_BUS_TAG.W)) | (obuf_merge & (obuf_tag1 === i.asUInt(LSU_BUS_TAG.W)))) & obuf_valid & obuf_wr_enQ +// buf_state_bus_en(i) := buf_cmd_state_bus_en(i) +// buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt +// buf_ldfwd_in(i) := true.B +// buf_ldfwd_en(i) := buf_state_en(i) & !buf_write(i) & obuf_nosend & !io.dec_tlu_force_halt +// buf_ldfwdtag_in(i) := (obuf_rdrsp_tag(LSU_BUS_TAG - 2, 0)).asUInt +// buf_data_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read +// buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error +// buf_data_in(i) := Mux(buf_error_en(i), bus_rsp_rdata(31, 0), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0))) +// buf_rst(i) := io.dec_tlu_force_halt +// } +// is(resp_C) { +// buf_nxtstate(i) := Mux((io.dec_tlu_force_halt | (buf_write(i) & !bus_rsp_write_error)).asBool(), idle_C, +// Mux((buf_dual(i) & !buf_samedw(i) & !buf_write(i) & (buf_state(buf_dualtag(i)) =/= done_partial_C)), done_partial_C, +// Mux((buf_ldfwd(i) | any_done_wait_state | (buf_dual(i) & !buf_samedw(i) & !buf_write(i) & indexing(buf_ldfwd,buf_dualtag(i)) & (buf_state(buf_dualtag(i)) === done_partial_C) & any_done_wait_state)), done_wait_C, done_C))) +// buf_resp_state_bus_en(i) := (bus_rsp_write & (bus_rsp_write_tag === (i.asUInt(LSU_BUS_TAG.W)))) | +// (bus_rsp_read & ((bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W))) | +// (buf_ldfwd(i) & (bus_rsp_read_tag === (buf_ldfwdtag(i)))) | +// (buf_dual(i) & buf_dualhi(i) & ~buf_write(i) & buf_samedw(i) & (bus_rsp_read_tag === (buf_dualtag(i)))))) +// buf_state_bus_en(i) := buf_resp_state_bus_en(i) +// buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt +// buf_data_en(i) := buf_state_bus_en(i) & bus_rsp_read & io.lsu_bus_clk_en +// buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W)))) | +// (bus_rsp_read_error & buf_ldfwd(i) & (bus_rsp_read_tag === buf_ldfwdtag(i))) | +// (bus_rsp_write_error & (bus_rsp_write_tag === i.asUInt(LSU_BUS_TAG.W)))) +// buf_data_in(i) := Mux((buf_state_en(i) & !buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0)) +// buf_cmd_state_bus_en(i) := 0.U +// buf_rst(i) := io.dec_tlu_force_halt +// } +// is(done_partial_C) { // Other part of dual load hasn't returned +// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((buf_ldfwd(i) | buf_ldfwd(buf_dualtag(i)) | any_done_wait_state), done_wait_C, done_C)) +// buf_state_bus_en(i) := bus_rsp_read & ((bus_rsp_read_tag === buf_dualtag(i).asUInt()) | +// (buf_ldfwd(buf_dualtag(i)) & (bus_rsp_read_tag === buf_ldfwdtag(buf_dualtag(i)).asUInt()))) +// buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt +// buf_cmd_state_bus_en(i) := 0.U +// buf_rst(i) := io.dec_tlu_force_halt +// } +// is(done_wait_C) { // WAIT state if there are multiple outstanding nb returns +// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, done_C) +// buf_state_en(i) := ((RspPtr === i.asUInt(DEPTH_LOG2.W)) | (buf_dual(i) & (buf_dualtag(i) === RspPtr))) | io.dec_tlu_force_halt +// buf_cmd_state_bus_en(i) := 0.U +// buf_rst(i) := io.dec_tlu_force_halt +// } +// is(done_C) { +// buf_nxtstate(i) := idle_C +// buf_rst(i) := true.B +// buf_state_en(i) := true.B +// buf_ldfwd_in(i) := false.B +// buf_ldfwd_en(i) := buf_state_en(i) +// buf_cmd_state_bus_en(i) := 0.U +// } +// } +// buf_state(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nxtstate(i), 0.U, buf_state_en(i).asBool())} +// buf_ageQ(i) := withClock(io.lsu_bus_buf_c1_clk){RegNext(buf_age_in(i), 0.U)} +// buf_rspageQ(i) := withClock(io.lsu_bus_buf_c1_clk){RegNext(buf_rspage_in(i), 0.U)} +// buf_dualtag(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dualtag_in(i), 0.U, buf_wr_en(i).asBool())} +// buf_dual(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dual_in(i), false.B, buf_wr_en(i).asBool())} +// buf_samedw(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_samedw_in(i), false.B, buf_wr_en(i).asBool())} +// buf_nomerge(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nomerge_in(i), false.B, buf_wr_en(i).asBool())} +// buf_dualhi(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dualhi_in(i), false.B, buf_wr_en(i).asBool())} +// } +// +// buf_ldfwd := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_ldfwd_in(i), false.B, buf_ldfwd_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) +// buf_ldfwdtag := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_ldfwdtag_in(i), 0.U, buf_ldfwd_en(i).asBool())}) +// buf_sideeffect := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_sideeffect_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) +// buf_unsign := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_unsign_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) +// buf_write := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_write_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) +// buf_sz := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_sz_in(i), 0.U, buf_wr_en(i).asBool())}) +// buf_addr := (0 until DEPTH).map(i=>rvdffe(buf_addr_in(i), buf_wr_en(i).asBool(), clock, io.scan_mode)) +// buf_byteen := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_byteen_in(i), 0.U, buf_wr_en(i).asBool())}) +// buf_data := (0 until DEPTH).map(i=>rvdffe(buf_data_in(i), buf_data_en(i), clock, io.scan_mode)) +// buf_error := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegNext(!buf_rst(i) & Mux(buf_error_en(i), true.B, buf_error(i)), false.B)}).asUInt()).reverse.reduce(Cat(_,_)) +// val buf_numvld_any = (Mux(io.ldst_dual_m, Cat(io.lsu_busreq_m, 0.U),io.lsu_busreq_m) +& Mux(io.ldst_dual_r, Cat(io.lsu_busreq_r, 0.U),io.lsu_busreq_r) +& ibuf_valid) + buf_state.map(i=>(i=/=idle_C).asUInt).reduce(_+&_) +// buf_numvld_wrcmd_any := (0 until DEPTH).map(i=>(buf_write(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _) +// buf_numvld_cmd_any := (0 until DEPTH).map(i=>((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _) +// buf_numvld_pend_any := (0 until DEPTH).map(i=>((buf_state(i)===wait_C) | ((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i))).asUInt).reverse.reduce(_ +& _) +// any_done_wait_state := (0 until DEPTH).map(i=>buf_state(i)===done_wait_C).reverse.reduce(_|_) +// io.lsu_bus_buffer_pend_any := buf_numvld_pend_any.orR +// io.lsu_bus_buffer_full_any := Mux(io.ldst_dual_d & io.dec_lsu_valid_raw_d, buf_numvld_any>=(DEPTH-1).U, buf_numvld_any===DEPTH.U) +// io.lsu_bus_buffer_empty_any := !(buf_state.map(_.orR).reduce(_|_)) & !ibuf_valid & !obuf_valid +// +// io.dctl_busbuff.lsu_nonblock_load_valid_m := io.lsu_busreq_m & io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.load & !io.flush_m_up & !io.ld_full_hit_m +// io.dctl_busbuff.lsu_nonblock_load_tag_m := WrPtr0_m +// val lsu_nonblock_load_valid_r = WireInit(Bool(), false.B) +// io.dctl_busbuff.lsu_nonblock_load_inv_r := lsu_nonblock_load_valid_r & !io.lsu_commit_r +// io.dctl_busbuff.lsu_nonblock_load_inv_tag_r := WrPtr0_r +// val lsu_nonblock_load_data_ready = Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (!(buf_write(i))))) +// io.dctl_busbuff.lsu_nonblock_load_data_error := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (buf_error(i) & !buf_write(i)))) +// io.dctl_busbuff.lsu_nonblock_load_data_tag := Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> i.U)) +// val lsu_nonblock_load_data_lo = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> buf_data(i))) +// val lsu_nonblock_load_data_hi = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (buf_dual(i) & buf_dualhi(i))) -> buf_data(i))) +// val lsu_nonblock_addr_offset = indexing(buf_addr, io.dctl_busbuff.lsu_nonblock_load_data_tag)(1,0) +// val lsu_nonblock_sz = indexing(buf_sz, io.dctl_busbuff.lsu_nonblock_load_data_tag) +// val lsu_nonblock_unsign = indexing(buf_unsign, io.dctl_busbuff.lsu_nonblock_load_data_tag) +// // val lsu_nonblock_dual = indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), io.dctl_busbuff.lsu_nonblock_load_data_tag) +// val lsu_nonblock_data_unalgn = Cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) >> (lsu_nonblock_addr_offset * 8.U) +// +// io.dctl_busbuff.lsu_nonblock_load_data_valid := lsu_nonblock_load_data_ready & !io.dctl_busbuff.lsu_nonblock_load_data_error +// io.dctl_busbuff.lsu_nonblock_load_data := Mux1H(Seq((lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(0.U(24.W),lsu_nonblock_data_unalgn(7,0)), +// (lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(0.U(16.W),lsu_nonblock_data_unalgn(15,0)), +// (!lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(Fill(24,lsu_nonblock_data_unalgn(7)), lsu_nonblock_data_unalgn(7,0)), +// (!lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(Fill(16,lsu_nonblock_data_unalgn(15)), lsu_nonblock_data_unalgn(15,0)), +// (lsu_nonblock_sz===2.U) -> lsu_nonblock_data_unalgn)) +// bus_sideeffect_pend := (0 until DEPTH).map(i=>(buf_state(i)===resp_C) & buf_sideeffect(i) & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable).reduce(_|_) | (obuf_valid & obuf_sideeffect & io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) +// bus_addr_match_pending := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===resp_C)-> +// ( obuf_valid & (obuf_addr(31,3)===buf_addr(i)(31,3)) & !((obuf_tag0===i.U) | (obuf_merge & (obuf_tag1===i.U)))))) +// +// bus_cmd_ready := Mux(obuf_write, Mux(obuf_cmd_done | obuf_data_done, Mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready), io.lsu_axi.aw.ready & io.lsu_axi.w.ready), io.lsu_axi.ar.ready) +// bus_wcmd_sent := io.lsu_axi.aw.valid & io.lsu_axi.aw.ready +// bus_wdata_sent := io.lsu_axi.w.valid & io.lsu_axi.w.ready +// bus_cmd_sent := ((obuf_cmd_done | bus_wcmd_sent) & (obuf_data_done | bus_wdata_sent)) | (io.lsu_axi.ar.valid & io.lsu_axi.ar.ready) +// bus_rsp_read := io.lsu_axi.r.valid & io.lsu_axi.r.ready +// bus_rsp_write := io.lsu_axi.b.valid & io.lsu_axi.b.ready +// bus_rsp_read_tag := io.lsu_axi.r.bits.id +// bus_rsp_write_tag := io.lsu_axi.b.bits.id +// bus_rsp_write_error := bus_rsp_write & (io.lsu_axi.b.bits.resp =/= 0.U) +// bus_rsp_read_error := bus_rsp_read & (io.lsu_axi.r.bits.resp =/= 0.U) +// bus_rsp_rdata := io.lsu_axi.r.bits.data +// +// // AXI Command signals +// io.lsu_axi.aw.valid := obuf_valid & obuf_write & !obuf_cmd_done & !bus_addr_match_pending +// io.lsu_axi.aw.bits.id := obuf_tag0 +// io.lsu_axi.aw.bits.addr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3), 0.U(3.W))) +// io.lsu_axi.aw.bits.size := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W)) +// io.lsu_axi.aw.bits.prot := 1.U(3.W) +// io.lsu_axi.aw.bits.cache := Mux(obuf_sideeffect, 0.U, 15.U) +// io.lsu_axi.aw.bits.region := obuf_addr(31,28) +// io.lsu_axi.aw.bits.len := 0.U +// io.lsu_axi.aw.bits.burst := 1.U(2.W) +// io.lsu_axi.aw.bits.qos := 0.U +// io.lsu_axi.aw.bits.lock := 0.U +// +// io.lsu_axi.w.valid := obuf_valid & obuf_write & !obuf_data_done & !bus_addr_match_pending +// io.lsu_axi.w.bits.strb := obuf_byteen & Fill(8, obuf_write) +// io.lsu_axi.w.bits.data := obuf_data +// io.lsu_axi.w.bits.last := 1.U +// +// io.lsu_axi.ar.valid := obuf_valid & !obuf_write & !obuf_nosend & !bus_addr_match_pending +// io.lsu_axi.ar.bits.id := obuf_tag0 +// io.lsu_axi.ar.bits.addr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3),0.U(3.W))) +// io.lsu_axi.ar.bits.size := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W)) +// io.lsu_axi.ar.bits.prot := 1.U(3.W) +// io.lsu_axi.ar.bits.cache := Mux(obuf_sideeffect, 0.U(4.W), 15.U) +// io.lsu_axi.ar.bits.region := obuf_addr(31,28) +// io.lsu_axi.ar.bits.len := 0.U +// io.lsu_axi.ar.bits.burst := 1.U(2.W) +// io.lsu_axi.ar.bits.qos := 0.U +// io.lsu_axi.ar.bits.lock := 0.U +// io.lsu_axi.b.ready := 1.U +// io.lsu_axi.r.ready := 1.U +// io.tlu_busbuff.lsu_imprecise_error_store_any := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C)->(io.lsu_bus_clk_en_q & buf_error(i) & buf_write(i)))) +// val lsu_imprecise_error_store_tag = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & buf_error(i) & buf_write(i))->i.U)) +// +// io.tlu_busbuff.lsu_imprecise_error_load_any := io.dctl_busbuff.lsu_nonblock_load_data_error & !io.tlu_busbuff.lsu_imprecise_error_store_any +// io.tlu_busbuff.lsu_imprecise_error_addr_any := Mux(io.tlu_busbuff.lsu_imprecise_error_store_any, buf_addr(lsu_imprecise_error_store_tag), buf_addr(io.dctl_busbuff.lsu_nonblock_load_data_tag)) +// //lsu_bus_cntr_overflow := 0.U +// +// // io.lsu_bus_idle_any := 1.U +// +// // PMU signals +// io.tlu_busbuff.lsu_pmu_bus_trxn := (io.lsu_axi.aw.valid & io.lsu_axi.aw.ready) | (io.lsu_axi.w.valid & io.lsu_axi.w.ready) | (io.lsu_axi.ar.valid & io.lsu_axi.ar.ready) +// io.tlu_busbuff.lsu_pmu_bus_misaligned := io.lsu_busreq_r & io.ldst_dual_r & io.lsu_commit_r +// io.tlu_busbuff.lsu_pmu_bus_error := io.tlu_busbuff.lsu_imprecise_error_load_any | io.tlu_busbuff.lsu_imprecise_error_store_any +// +// io.tlu_busbuff.lsu_pmu_bus_busy := (io.lsu_axi.aw.valid & !io.lsu_axi.aw.ready) | (io.lsu_axi.w.valid & !io.lsu_axi.w.ready) | (io.lsu_axi.ar.valid & !io.lsu_axi.ar.ready) +// +// WrPtr0_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr0_m, 0.U)} +// WrPtr1_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr1_m, 0.U)} +// io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)} +// lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)} +//} +//object buffer extends App { +// println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_buffer())) +//} diff --git a/src/main/scala/lsu/lsu_bus_intf.scala b/src/main/scala/lsu/lsu_bus_intf.scala index 85492d75..4a246ab5 100644 --- a/src/main/scala/lsu/lsu_bus_intf.scala +++ b/src/main/scala/lsu/lsu_bus_intf.scala @@ -1,205 +1,205 @@ -package lsu -import chisel3._ -import chisel3.util._ -import lib._ -import include._ - -class lsu_bus_intf extends Module with RequireAsyncReset with lib { - val io = IO (new Bundle { - val scan_mode = Input(Bool()) - val clk_override = Input(Bool()) - val tlu_busbuff = new tlu_busbuff() - val lsu_bus_obuf_c1_clken = Input(Bool())// obuf clock enable - val lsu_busm_clken = Input(Bool()) - val lsu_c1_r_clk = Input(Clock()) - val lsu_c2_r_clk = Input(Clock()) - val lsu_bus_ibuf_c1_clk = Input(Clock()) - val lsu_bus_obuf_c1_clk = Input(Clock()) - val lsu_bus_buf_c1_clk = Input(Clock()) - val lsu_free_c2_clk = Input(Clock()) - val active_clk = Input(Clock()) - val lsu_busm_clk = Input(Clock()) - val axi = new axi_channels(LSU_BUS_TAG) - val dec_lsu_valid_raw_d = Input(Bool()) - val lsu_busreq_m = Input(Bool()) - - val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t())) - val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t())) - - val lsu_addr_m = Input(UInt(32.W)) - val lsu_addr_r = Input(UInt(32.W)) - - val end_addr_m = Input(UInt(32.W)) - val end_addr_r = Input(UInt(32.W)) - val ldst_dual_d = Input(Bool()) - val ldst_dual_m = Input(Bool()) - val ldst_dual_r = Input(Bool()) - - val store_data_r = Input(UInt(32.W)) - val dec_tlu_force_halt = Input(Bool()) - - val lsu_commit_r = Input(Bool()) - val is_sideeffects_m = Input(Bool()) - val flush_m_up = Input(Bool()) - val flush_r = Input(Bool()) - - val lsu_busreq_r = Output(Bool()) - val lsu_bus_buffer_pend_any = Output(Bool()) - val lsu_bus_buffer_full_any = Output(Bool()) - val lsu_bus_buffer_empty_any = Output(Bool()) - //val lsu_bus_idle_any = Output(Bool()) - val bus_read_data_m = Output(UInt(32.W)) - - val dctl_busbuff = new dctl_busbuff() - - val lsu_bus_clk_en = Input(Bool()) - }) - - val lsu_bus_clk_en_q = WireInit(Bool(), init = false.B) - val ldst_byteen_m = WireInit(UInt(4.W), init = 0.U) - val ldst_byteen_r = WireInit(UInt(4.W), init = 0.U) - val ldst_byteen_ext_m = WireInit(UInt(8.W), init = 0.U) - val ldst_byteen_ext_r = WireInit(UInt(8.W), init = 0.U) - val ldst_byteen_hi_m = WireInit(UInt(4.W), init = 0.U) - val ldst_byteen_hi_r = WireInit(UInt(4.W), init = 0.U) - val ldst_byteen_lo_m = WireInit(UInt(4.W), init = 0.U) - val ldst_byteen_lo_r = WireInit(UInt(4.W), init = 0.U) - val is_sideeffects_r = WireInit(Bool(), init = false.B) - val store_data_ext_r = WireInit(UInt(64.W), init = 0.U) - val store_data_hi_r = WireInit(UInt(32.W), init = 0.U) - val store_data_lo_r = WireInit(UInt(32.W), init = 0.U) - val addr_match_dw_lo_r_m = WireInit(Bool(), init = false.B) - val addr_match_word_lo_r_m = WireInit(Bool(), init = false.B) - val no_word_merge_r = WireInit(Bool(), init = false.B) - val no_dword_merge_r = WireInit(Bool(), init = false.B) - val ld_addr_rhit_lo_lo = WireInit(Bool(), init = false.B) - val ld_addr_rhit_hi_lo = WireInit(Bool(), init = false.B) - val ld_addr_rhit_lo_hi = WireInit(Bool(), init = false.B) - val ld_addr_rhit_hi_hi = WireInit(Bool(), init = false.B) - val ld_byte_rhit_lo_lo = WireInit(UInt(4.W), init = 0.U) - val ld_byte_rhit_hi_lo = WireInit(UInt(4.W), init = 0.U) - val ld_byte_rhit_lo_hi = WireInit(UInt(4.W), init = 0.U) - val ld_byte_rhit_hi_hi = WireInit(UInt(4.W), init = 0.U) - val ld_byte_hit_lo = WireInit(UInt(4.W), init = 0.U) - val ld_byte_rhit_lo = WireInit(UInt(4.W), init = 0.U) - val ld_byte_hit_hi = WireInit(UInt(4.W), init = 0.U) - val ld_byte_rhit_hi = WireInit(UInt(4.W), init = 0.U) - val ld_fwddata_rpipe_lo = WireInit(UInt(32.W), init = 0.U) - val ld_fwddata_rpipe_hi = WireInit(UInt(32.W), init = 0.U) - val ld_byte_hit_buf_lo = WireInit(UInt(4.W), init = 0.U) - val ld_byte_hit_buf_hi = WireInit(UInt(4.W), init = 0.U) - val ld_fwddata_buf_lo = WireInit(UInt(32.W), init = 0.U) - val ld_fwddata_buf_hi = WireInit(UInt(32.W), init = 0.U) - val ld_fwddata_lo = WireInit(UInt(64.W), init = 0.U) - val ld_fwddata_hi = WireInit(UInt(64.W), init = 0.U) - val ld_fwddata_m = WireInit(UInt(64.W), init = 0.U) - val ld_full_hit_hi_m = WireInit(Bool(), init = true.B) - val ld_full_hit_lo_m = WireInit(Bool(), init = true.B) - val ld_full_hit_m = WireInit(Bool(), init = false.B) - - val bus_buffer = Module(new lsu_bus_buffer) - - bus_buffer.io.scan_mode := io.scan_mode - io.tlu_busbuff <> bus_buffer.io.tlu_busbuff - bus_buffer.io.clk_override := io.clk_override - bus_buffer.io.lsu_bus_obuf_c1_clken := io.lsu_bus_obuf_c1_clken - bus_buffer.io.lsu_busm_clken := io.lsu_busm_clken - bus_buffer.io.dec_tlu_force_halt := io.dec_tlu_force_halt - bus_buffer.io.lsu_c2_r_clk := io.lsu_c2_r_clk - bus_buffer.io.lsu_bus_ibuf_c1_clk := io.lsu_bus_ibuf_c1_clk - bus_buffer.io.lsu_bus_obuf_c1_clk := io.lsu_bus_obuf_c1_clk - bus_buffer.io.lsu_bus_buf_c1_clk := io.lsu_bus_buf_c1_clk - bus_buffer.io.lsu_free_c2_clk := io.lsu_free_c2_clk - bus_buffer.io.lsu_busm_clk := io.lsu_busm_clk - bus_buffer.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d - - // - bus_buffer.io.lsu_pkt_m <> io.lsu_pkt_m - bus_buffer.io.lsu_pkt_r <> io.lsu_pkt_r - // - - bus_buffer.io.lsu_addr_m := io.lsu_addr_m - bus_buffer.io.end_addr_m := io.end_addr_m - bus_buffer.io.lsu_addr_r := io.lsu_addr_r - bus_buffer.io.end_addr_r := io.end_addr_r - bus_buffer.io.store_data_r := io.store_data_r - - bus_buffer.io.lsu_busreq_m := io.lsu_busreq_m - bus_buffer.io.flush_m_up := io.flush_m_up - bus_buffer.io.flush_r := io.flush_r - bus_buffer.io.lsu_commit_r := io.lsu_commit_r - bus_buffer.io.lsu_axi <> io.axi - bus_buffer.io.lsu_bus_clk_en := io.lsu_bus_clk_en - - io.lsu_busreq_r := bus_buffer.io.lsu_busreq_r - io.lsu_bus_buffer_pend_any := bus_buffer.io.lsu_bus_buffer_pend_any - io.lsu_bus_buffer_full_any := bus_buffer.io.lsu_bus_buffer_full_any - io.lsu_bus_buffer_empty_any := bus_buffer.io.lsu_bus_buffer_empty_any - //io.lsu_bus_idle_any := bus_buffer.io.lsu_bus_idle_any - ld_byte_hit_buf_lo := bus_buffer.io.ld_byte_hit_buf_lo - ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi - ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo - ld_fwddata_buf_hi := bus_buffer.io.ld_fwddata_buf_hi - io.dctl_busbuff <> bus_buffer.io.dctl_busbuff - bus_buffer.io.no_word_merge_r := no_word_merge_r - bus_buffer.io.no_dword_merge_r := no_dword_merge_r - bus_buffer.io.is_sideeffects_r := is_sideeffects_r - bus_buffer.io.ldst_dual_d := io.ldst_dual_d - bus_buffer.io.ldst_dual_m := io.ldst_dual_m - bus_buffer.io.ldst_dual_r := io.ldst_dual_r - bus_buffer.io.ldst_byteen_ext_m := ldst_byteen_ext_m - bus_buffer.io.ld_full_hit_m := ld_full_hit_m - bus_buffer.io.lsu_bus_clk_en_q := lsu_bus_clk_en_q - - ldst_byteen_m := Mux1H(Seq(io.lsu_pkt_m.bits.word.asBool -> 15.U(4.W), io.lsu_pkt_m.bits.half.asBool -> 3.U(4.W), io.lsu_pkt_m.bits.by.asBool -> 1.U(4.W))) - addr_match_dw_lo_r_m := (io.lsu_addr_r(31,3) === io.lsu_addr_m(31,3)) - addr_match_word_lo_r_m := addr_match_dw_lo_r_m & !(io.lsu_addr_r(2)^io.lsu_addr_m(2)) - no_word_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_word_lo_r_m) - no_dword_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_dw_lo_r_m) - - ldst_byteen_ext_m := ldst_byteen_m(3,0) << io.lsu_addr_m(1,0) - ldst_byteen_ext_r := ldst_byteen_r(3,0) << io.lsu_addr_r(1,0) - store_data_ext_r := io.store_data_r(31,0) << Cat(io.lsu_addr_r(1,0),0.U(3.W)) - ldst_byteen_hi_m := ldst_byteen_ext_m(7,4) - ldst_byteen_lo_m := ldst_byteen_ext_m(3,0) - ldst_byteen_hi_r := ldst_byteen_ext_r(7,4) - ldst_byteen_lo_r := ldst_byteen_ext_r(3,0) - - store_data_hi_r := store_data_ext_r(63,32) - store_data_lo_r := store_data_ext_r(31,0) - ld_addr_rhit_lo_lo := (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m - ld_addr_rhit_lo_hi := (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m - ld_addr_rhit_hi_lo := (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m - ld_addr_rhit_hi_hi := (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m - - ld_byte_rhit_lo_lo := (0 until 4).map(i =>(ld_addr_rhit_lo_lo & ldst_byteen_lo_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_)) - ld_byte_rhit_lo_hi := (0 until 4).map(i =>(ld_addr_rhit_lo_hi & ldst_byteen_lo_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_)) - ld_byte_rhit_hi_lo := (0 until 4).map(i =>(ld_addr_rhit_hi_lo & ldst_byteen_hi_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_)) - ld_byte_rhit_hi_hi := (0 until 4).map(i =>(ld_addr_rhit_hi_hi & ldst_byteen_hi_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_)) - - ld_byte_hit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) | ld_byte_hit_buf_lo(i)).asUInt).reverse.reduce(Cat(_,_)) - ld_byte_hit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) | ld_byte_hit_buf_hi(i)).asUInt).reverse.reduce(Cat(_,_)) - ld_byte_rhit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) ).asUInt).reverse.reduce(Cat(_,_)) - ld_byte_rhit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) ).asUInt).reverse.reduce(Cat(_,_)) - ld_fwddata_rpipe_lo := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_lo(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_lo(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_)) - ld_fwddata_rpipe_hi := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_hi(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_hi(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_)) - ld_fwddata_lo := (0 until 4).map(i =>(Mux(ld_byte_rhit_lo(i), ld_fwddata_rpipe_lo((8*i)+7,(8*i)), ld_fwddata_buf_lo((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_)) - ld_fwddata_hi := (0 until 4).map(i =>(Mux(ld_byte_rhit_hi(i), ld_fwddata_rpipe_hi((8*i)+7,(8*i)), ld_fwddata_buf_hi((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_)) - ld_full_hit_lo_m := (0 until 4).map(i =>((ld_byte_hit_lo(i) | !ldst_byteen_lo_m(i))).asUInt).reduce(_&_) - ld_full_hit_hi_m := (0 until 4).map(i =>((ld_byte_hit_hi(i) | !ldst_byteen_hi_m(i))).asUInt).reduce(_&_) - ld_full_hit_m := ld_full_hit_lo_m & ld_full_hit_hi_m & io.lsu_busreq_m & io.lsu_pkt_m.bits.load & !io.is_sideeffects_m - ld_fwddata_m := Cat(ld_fwddata_hi(31,0), ld_fwddata_lo(31,0)) >> (8.U*io.lsu_addr_m(1,0)) - io.bus_read_data_m := ld_fwddata_m(31,0) - - withClock(io.active_clk) { - lsu_bus_clk_en_q := RegNext(io.lsu_bus_clk_en, init = 0.U) - } - - withClock(io.lsu_c1_r_clk) { - is_sideeffects_r := RegNext(io.is_sideeffects_m, init = 0.U) - ldst_byteen_r := RegNext(ldst_byteen_m, init = 0.U(4.W)) - } -} -object bus_intf extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_intf())) -} \ No newline at end of file +//package lsu +//import chisel3._ +//import chisel3.util._ +//import lib._ +//import include._ +// +//class lsu_bus_intf extends Module with RequireAsyncReset with lib { +// val io = IO (new Bundle { +// val scan_mode = Input(Bool()) +// val clk_override = Input(Bool()) +// val tlu_busbuff = new tlu_busbuff() +// val lsu_bus_obuf_c1_clken = Input(Bool())// obuf clock enable +// val lsu_busm_clken = Input(Bool()) +// val lsu_c1_r_clk = Input(Clock()) +// val lsu_c2_r_clk = Input(Clock()) +// val lsu_bus_ibuf_c1_clk = Input(Clock()) +// val lsu_bus_obuf_c1_clk = Input(Clock()) +// val lsu_bus_buf_c1_clk = Input(Clock()) +// val lsu_free_c2_clk = Input(Clock()) +// val active_clk = Input(Clock()) +// val lsu_busm_clk = Input(Clock()) +// val axi = new axi_channels(LSU_BUS_TAG) +// val dec_lsu_valid_raw_d = Input(Bool()) +// val lsu_busreq_m = Input(Bool()) +// +// val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t())) +// val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t())) +// +// val lsu_addr_m = Input(UInt(32.W)) +// val lsu_addr_r = Input(UInt(32.W)) +// +// val end_addr_m = Input(UInt(32.W)) +// val end_addr_r = Input(UInt(32.W)) +// val ldst_dual_d = Input(Bool()) +// val ldst_dual_m = Input(Bool()) +// val ldst_dual_r = Input(Bool()) +// +// val store_data_r = Input(UInt(32.W)) +// val dec_tlu_force_halt = Input(Bool()) +// +// val lsu_commit_r = Input(Bool()) +// val is_sideeffects_m = Input(Bool()) +// val flush_m_up = Input(Bool()) +// val flush_r = Input(Bool()) +// +// val lsu_busreq_r = Output(Bool()) +// val lsu_bus_buffer_pend_any = Output(Bool()) +// val lsu_bus_buffer_full_any = Output(Bool()) +// val lsu_bus_buffer_empty_any = Output(Bool()) +// //val lsu_bus_idle_any = Output(Bool()) +// val bus_read_data_m = Output(UInt(32.W)) +// +// val dctl_busbuff = new dctl_busbuff() +// +// val lsu_bus_clk_en = Input(Bool()) +// }) +// +// val lsu_bus_clk_en_q = WireInit(Bool(), init = false.B) +// val ldst_byteen_m = WireInit(UInt(4.W), init = 0.U) +// val ldst_byteen_r = WireInit(UInt(4.W), init = 0.U) +// val ldst_byteen_ext_m = WireInit(UInt(8.W), init = 0.U) +// val ldst_byteen_ext_r = WireInit(UInt(8.W), init = 0.U) +// val ldst_byteen_hi_m = WireInit(UInt(4.W), init = 0.U) +// val ldst_byteen_hi_r = WireInit(UInt(4.W), init = 0.U) +// val ldst_byteen_lo_m = WireInit(UInt(4.W), init = 0.U) +// val ldst_byteen_lo_r = WireInit(UInt(4.W), init = 0.U) +// val is_sideeffects_r = WireInit(Bool(), init = false.B) +// val store_data_ext_r = WireInit(UInt(64.W), init = 0.U) +// val store_data_hi_r = WireInit(UInt(32.W), init = 0.U) +// val store_data_lo_r = WireInit(UInt(32.W), init = 0.U) +// val addr_match_dw_lo_r_m = WireInit(Bool(), init = false.B) +// val addr_match_word_lo_r_m = WireInit(Bool(), init = false.B) +// val no_word_merge_r = WireInit(Bool(), init = false.B) +// val no_dword_merge_r = WireInit(Bool(), init = false.B) +// val ld_addr_rhit_lo_lo = WireInit(Bool(), init = false.B) +// val ld_addr_rhit_hi_lo = WireInit(Bool(), init = false.B) +// val ld_addr_rhit_lo_hi = WireInit(Bool(), init = false.B) +// val ld_addr_rhit_hi_hi = WireInit(Bool(), init = false.B) +// val ld_byte_rhit_lo_lo = WireInit(UInt(4.W), init = 0.U) +// val ld_byte_rhit_hi_lo = WireInit(UInt(4.W), init = 0.U) +// val ld_byte_rhit_lo_hi = WireInit(UInt(4.W), init = 0.U) +// val ld_byte_rhit_hi_hi = WireInit(UInt(4.W), init = 0.U) +// val ld_byte_hit_lo = WireInit(UInt(4.W), init = 0.U) +// val ld_byte_rhit_lo = WireInit(UInt(4.W), init = 0.U) +// val ld_byte_hit_hi = WireInit(UInt(4.W), init = 0.U) +// val ld_byte_rhit_hi = WireInit(UInt(4.W), init = 0.U) +// val ld_fwddata_rpipe_lo = WireInit(UInt(32.W), init = 0.U) +// val ld_fwddata_rpipe_hi = WireInit(UInt(32.W), init = 0.U) +// val ld_byte_hit_buf_lo = WireInit(UInt(4.W), init = 0.U) +// val ld_byte_hit_buf_hi = WireInit(UInt(4.W), init = 0.U) +// val ld_fwddata_buf_lo = WireInit(UInt(32.W), init = 0.U) +// val ld_fwddata_buf_hi = WireInit(UInt(32.W), init = 0.U) +// val ld_fwddata_lo = WireInit(UInt(64.W), init = 0.U) +// val ld_fwddata_hi = WireInit(UInt(64.W), init = 0.U) +// val ld_fwddata_m = WireInit(UInt(64.W), init = 0.U) +// val ld_full_hit_hi_m = WireInit(Bool(), init = true.B) +// val ld_full_hit_lo_m = WireInit(Bool(), init = true.B) +// val ld_full_hit_m = WireInit(Bool(), init = false.B) +// +// val bus_buffer = Module(new lsu_bus_buffer) +// +// bus_buffer.io.scan_mode := io.scan_mode +// io.tlu_busbuff <> bus_buffer.io.tlu_busbuff +// bus_buffer.io.clk_override := io.clk_override +// bus_buffer.io.lsu_bus_obuf_c1_clken := io.lsu_bus_obuf_c1_clken +// bus_buffer.io.lsu_busm_clken := io.lsu_busm_clken +// bus_buffer.io.dec_tlu_force_halt := io.dec_tlu_force_halt +// bus_buffer.io.lsu_c2_r_clk := io.lsu_c2_r_clk +// bus_buffer.io.lsu_bus_ibuf_c1_clk := io.lsu_bus_ibuf_c1_clk +// bus_buffer.io.lsu_bus_obuf_c1_clk := io.lsu_bus_obuf_c1_clk +// bus_buffer.io.lsu_bus_buf_c1_clk := io.lsu_bus_buf_c1_clk +// bus_buffer.io.lsu_free_c2_clk := io.lsu_free_c2_clk +// bus_buffer.io.lsu_busm_clk := io.lsu_busm_clk +// bus_buffer.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d +// +// // +// bus_buffer.io.lsu_pkt_m <> io.lsu_pkt_m +// bus_buffer.io.lsu_pkt_r <> io.lsu_pkt_r +// // +// +// bus_buffer.io.lsu_addr_m := io.lsu_addr_m +// bus_buffer.io.end_addr_m := io.end_addr_m +// bus_buffer.io.lsu_addr_r := io.lsu_addr_r +// bus_buffer.io.end_addr_r := io.end_addr_r +// bus_buffer.io.store_data_r := io.store_data_r +// +// bus_buffer.io.lsu_busreq_m := io.lsu_busreq_m +// bus_buffer.io.flush_m_up := io.flush_m_up +// bus_buffer.io.flush_r := io.flush_r +// bus_buffer.io.lsu_commit_r := io.lsu_commit_r +// bus_buffer.io.lsu_axi <> io.axi +// bus_buffer.io.lsu_bus_clk_en := io.lsu_bus_clk_en +// +// io.lsu_busreq_r := bus_buffer.io.lsu_busreq_r +// io.lsu_bus_buffer_pend_any := bus_buffer.io.lsu_bus_buffer_pend_any +// io.lsu_bus_buffer_full_any := bus_buffer.io.lsu_bus_buffer_full_any +// io.lsu_bus_buffer_empty_any := bus_buffer.io.lsu_bus_buffer_empty_any +// //io.lsu_bus_idle_any := bus_buffer.io.lsu_bus_idle_any +// ld_byte_hit_buf_lo := bus_buffer.io.ld_byte_hit_buf_lo +// ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi +// ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo +// ld_fwddata_buf_hi := bus_buffer.io.ld_fwddata_buf_hi +// io.dctl_busbuff <> bus_buffer.io.dctl_busbuff +// bus_buffer.io.no_word_merge_r := no_word_merge_r +// bus_buffer.io.no_dword_merge_r := no_dword_merge_r +// bus_buffer.io.is_sideeffects_r := is_sideeffects_r +// bus_buffer.io.ldst_dual_d := io.ldst_dual_d +// bus_buffer.io.ldst_dual_m := io.ldst_dual_m +// bus_buffer.io.ldst_dual_r := io.ldst_dual_r +// bus_buffer.io.ldst_byteen_ext_m := ldst_byteen_ext_m +// bus_buffer.io.ld_full_hit_m := ld_full_hit_m +// bus_buffer.io.lsu_bus_clk_en_q := lsu_bus_clk_en_q +// +// ldst_byteen_m := Mux1H(Seq(io.lsu_pkt_m.bits.word.asBool -> 15.U(4.W), io.lsu_pkt_m.bits.half.asBool -> 3.U(4.W), io.lsu_pkt_m.bits.by.asBool -> 1.U(4.W))) +// addr_match_dw_lo_r_m := (io.lsu_addr_r(31,3) === io.lsu_addr_m(31,3)) +// addr_match_word_lo_r_m := addr_match_dw_lo_r_m & !(io.lsu_addr_r(2)^io.lsu_addr_m(2)) +// no_word_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_word_lo_r_m) +// no_dword_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_dw_lo_r_m) +// +// ldst_byteen_ext_m := ldst_byteen_m(3,0) << io.lsu_addr_m(1,0) +// ldst_byteen_ext_r := ldst_byteen_r(3,0) << io.lsu_addr_r(1,0) +// store_data_ext_r := io.store_data_r(31,0) << Cat(io.lsu_addr_r(1,0),0.U(3.W)) +// ldst_byteen_hi_m := ldst_byteen_ext_m(7,4) +// ldst_byteen_lo_m := ldst_byteen_ext_m(3,0) +// ldst_byteen_hi_r := ldst_byteen_ext_r(7,4) +// ldst_byteen_lo_r := ldst_byteen_ext_r(3,0) +// +// store_data_hi_r := store_data_ext_r(63,32) +// store_data_lo_r := store_data_ext_r(31,0) +// ld_addr_rhit_lo_lo := (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m +// ld_addr_rhit_lo_hi := (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m +// ld_addr_rhit_hi_lo := (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m +// ld_addr_rhit_hi_hi := (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m +// +// ld_byte_rhit_lo_lo := (0 until 4).map(i =>(ld_addr_rhit_lo_lo & ldst_byteen_lo_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_)) +// ld_byte_rhit_lo_hi := (0 until 4).map(i =>(ld_addr_rhit_lo_hi & ldst_byteen_lo_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_)) +// ld_byte_rhit_hi_lo := (0 until 4).map(i =>(ld_addr_rhit_hi_lo & ldst_byteen_hi_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_)) +// ld_byte_rhit_hi_hi := (0 until 4).map(i =>(ld_addr_rhit_hi_hi & ldst_byteen_hi_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_)) +// +// ld_byte_hit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) | ld_byte_hit_buf_lo(i)).asUInt).reverse.reduce(Cat(_,_)) +// ld_byte_hit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) | ld_byte_hit_buf_hi(i)).asUInt).reverse.reduce(Cat(_,_)) +// ld_byte_rhit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) ).asUInt).reverse.reduce(Cat(_,_)) +// ld_byte_rhit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) ).asUInt).reverse.reduce(Cat(_,_)) +// ld_fwddata_rpipe_lo := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_lo(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_lo(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_)) +// ld_fwddata_rpipe_hi := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_hi(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_hi(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_)) +// ld_fwddata_lo := (0 until 4).map(i =>(Mux(ld_byte_rhit_lo(i), ld_fwddata_rpipe_lo((8*i)+7,(8*i)), ld_fwddata_buf_lo((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_)) +// ld_fwddata_hi := (0 until 4).map(i =>(Mux(ld_byte_rhit_hi(i), ld_fwddata_rpipe_hi((8*i)+7,(8*i)), ld_fwddata_buf_hi((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_)) +// ld_full_hit_lo_m := (0 until 4).map(i =>((ld_byte_hit_lo(i) | !ldst_byteen_lo_m(i))).asUInt).reduce(_&_) +// ld_full_hit_hi_m := (0 until 4).map(i =>((ld_byte_hit_hi(i) | !ldst_byteen_hi_m(i))).asUInt).reduce(_&_) +// ld_full_hit_m := ld_full_hit_lo_m & ld_full_hit_hi_m & io.lsu_busreq_m & io.lsu_pkt_m.bits.load & !io.is_sideeffects_m +// ld_fwddata_m := Cat(ld_fwddata_hi(31,0), ld_fwddata_lo(31,0)) >> (8.U*io.lsu_addr_m(1,0)) +// io.bus_read_data_m := ld_fwddata_m(31,0) +// +// withClock(io.active_clk) { +// lsu_bus_clk_en_q := RegNext(io.lsu_bus_clk_en, init = 0.U) +// } +// +// withClock(io.lsu_c1_r_clk) { +// is_sideeffects_r := RegNext(io.is_sideeffects_m, init = 0.U) +// ldst_byteen_r := RegNext(ldst_byteen_m, init = 0.U(4.W)) +// } +//} +//object bus_intf extends App { +// println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_intf())) +//} \ No newline at end of file diff --git a/target/scala-2.12/classes/dec/CSR_IO.class b/target/scala-2.12/classes/dec/CSR_IO.class index d1281f45..b8660ee7 100644 Binary files a/target/scala-2.12/classes/dec/CSR_IO.class and b/target/scala-2.12/classes/dec/CSR_IO.class differ diff --git a/target/scala-2.12/classes/dec/CSRs.class b/target/scala-2.12/classes/dec/CSRs.class index 9c9823aa..d45de944 100644 Binary files a/target/scala-2.12/classes/dec/CSRs.class and b/target/scala-2.12/classes/dec/CSRs.class differ diff --git a/target/scala-2.12/classes/dec/csr_tlu.class b/target/scala-2.12/classes/dec/csr_tlu.class index c1388ae0..71129d91 100644 Binary files a/target/scala-2.12/classes/dec/csr_tlu.class and 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