IFC
This commit is contained in:
waleed-lm
parent
a069f8f486
commit
f2b698cb01
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@ -1,4 +1,11 @@
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[
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_sjald",
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"sources":[
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"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
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]
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},
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{
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{
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"class":"firrtl.transforms.CombinationalPath",
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_dout",
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"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_dout",
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File diff suppressed because it is too large
Load Diff
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@ -14,317 +14,318 @@ module el2_ifu_compress_ctl(
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output [4:0] io_ulwimm6d,
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output [4:0] io_ulwimm6d,
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output [5:0] io_simm9d,
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output [5:0] io_simm9d,
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output [7:0] io_uimm9d,
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output [7:0] io_uimm9d,
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output [5:0] io_simm5d
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output [5:0] io_simm5d,
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output [19:0] io_sjald
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);
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);
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wire _T_2 = ~io_din[14]; // @[el2_ifu_compress_ctl.scala 33:83]
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wire _T_2 = ~io_din[14]; // @[el2_ifu_compress_ctl.scala 28:83]
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wire _T_4 = ~io_din[13]; // @[el2_ifu_compress_ctl.scala 33:83]
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wire _T_4 = ~io_din[13]; // @[el2_ifu_compress_ctl.scala 28:83]
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wire _T_7 = ~io_din[6]; // @[el2_ifu_compress_ctl.scala 33:83]
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wire _T_7 = ~io_din[6]; // @[el2_ifu_compress_ctl.scala 28:83]
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wire _T_9 = ~io_din[5]; // @[el2_ifu_compress_ctl.scala 33:83]
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wire _T_9 = ~io_din[5]; // @[el2_ifu_compress_ctl.scala 28:83]
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wire _T_11 = io_din[15] & _T_2; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_11 = io_din[15] & _T_2; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_12 = _T_11 & _T_4; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_12 = _T_11 & _T_4; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_13 = _T_12 & io_din[10]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_13 = _T_12 & io_din[10]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_14 = _T_13 & _T_7; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_14 = _T_13 & _T_7; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_15 = _T_14 & _T_9; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_15 = _T_14 & _T_9; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_16 = _T_15 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_16 = _T_15 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_23 = ~io_din[11]; // @[el2_ifu_compress_ctl.scala 33:83]
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wire _T_23 = ~io_din[11]; // @[el2_ifu_compress_ctl.scala 28:83]
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wire _T_28 = _T_12 & _T_23; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_28 = _T_12 & _T_23; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_29 = _T_28 & io_din[10]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_29 = _T_28 & io_din[10]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_30 = _T_29 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_30 = _T_29 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire out_30 = _T_16 | _T_30; // @[el2_ifu_compress_ctl.scala 36:53]
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wire out_30 = _T_16 | _T_30; // @[el2_ifu_compress_ctl.scala 31:53]
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wire _T_38 = ~io_din[10]; // @[el2_ifu_compress_ctl.scala 33:83]
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wire _T_38 = ~io_din[10]; // @[el2_ifu_compress_ctl.scala 28:83]
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wire _T_40 = ~io_din[9]; // @[el2_ifu_compress_ctl.scala 33:83]
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wire _T_40 = ~io_din[9]; // @[el2_ifu_compress_ctl.scala 28:83]
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wire _T_42 = ~io_din[8]; // @[el2_ifu_compress_ctl.scala 33:83]
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wire _T_42 = ~io_din[8]; // @[el2_ifu_compress_ctl.scala 28:83]
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wire _T_44 = ~io_din[7]; // @[el2_ifu_compress_ctl.scala 33:83]
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wire _T_44 = ~io_din[7]; // @[el2_ifu_compress_ctl.scala 28:83]
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wire _T_50 = ~io_din[4]; // @[el2_ifu_compress_ctl.scala 33:83]
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wire _T_50 = ~io_din[4]; // @[el2_ifu_compress_ctl.scala 28:83]
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wire _T_52 = ~io_din[3]; // @[el2_ifu_compress_ctl.scala 33:83]
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wire _T_52 = ~io_din[3]; // @[el2_ifu_compress_ctl.scala 28:83]
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wire _T_54 = ~io_din[2]; // @[el2_ifu_compress_ctl.scala 33:83]
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wire _T_54 = ~io_din[2]; // @[el2_ifu_compress_ctl.scala 28:83]
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wire _T_56 = _T_2 & io_din[12]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_56 = _T_2 & io_din[12]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_57 = _T_56 & _T_23; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_57 = _T_56 & _T_23; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_58 = _T_57 & _T_38; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_58 = _T_57 & _T_38; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_59 = _T_58 & _T_40; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_59 = _T_58 & _T_40; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_60 = _T_59 & _T_42; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_60 = _T_59 & _T_42; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_61 = _T_60 & _T_44; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_61 = _T_60 & _T_44; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_62 = _T_61 & _T_7; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_62 = _T_61 & _T_7; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_63 = _T_62 & _T_9; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_63 = _T_62 & _T_9; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_64 = _T_63 & _T_50; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_64 = _T_63 & _T_50; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_65 = _T_64 & _T_52; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_65 = _T_64 & _T_52; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_66 = _T_65 & _T_54; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_66 = _T_65 & _T_54; // @[el2_ifu_compress_ctl.scala 28:110]
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wire out_20 = _T_66 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire out_20 = _T_66 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_79 = _T_28 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_79 = _T_28 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_90 = _T_12 & _T_38; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_90 = _T_12 & _T_38; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_91 = _T_90 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_91 = _T_90 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_92 = _T_79 | _T_91; // @[el2_ifu_compress_ctl.scala 38:46]
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wire _T_92 = _T_79 | _T_91; // @[el2_ifu_compress_ctl.scala 33:46]
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wire _T_102 = _T_12 & io_din[6]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_102 = _T_12 & io_din[6]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_103 = _T_102 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_103 = _T_102 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_104 = _T_92 | _T_103; // @[el2_ifu_compress_ctl.scala 38:80]
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wire _T_104 = _T_92 | _T_103; // @[el2_ifu_compress_ctl.scala 33:80]
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wire _T_114 = _T_12 & io_din[5]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_114 = _T_12 & io_din[5]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_115 = _T_114 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_115 = _T_114 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire out_14 = _T_104 | _T_115; // @[el2_ifu_compress_ctl.scala 38:113]
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wire out_14 = _T_104 | _T_115; // @[el2_ifu_compress_ctl.scala 33:113]
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wire _T_128 = _T_12 & io_din[11]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_128 = _T_12 & io_din[11]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_129 = _T_128 & _T_38; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_129 = _T_128 & _T_38; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_130 = _T_129 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_130 = _T_129 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_142 = _T_128 & io_din[6]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_142 = _T_128 & io_din[6]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_143 = _T_142 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_143 = _T_142 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_144 = _T_130 | _T_143; // @[el2_ifu_compress_ctl.scala 40:50]
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wire _T_144 = _T_130 | _T_143; // @[el2_ifu_compress_ctl.scala 35:50]
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wire _T_147 = ~io_din[0]; // @[el2_ifu_compress_ctl.scala 40:101]
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wire _T_147 = ~io_din[0]; // @[el2_ifu_compress_ctl.scala 35:101]
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wire _T_148 = io_din[14] & _T_147; // @[el2_ifu_compress_ctl.scala 40:99]
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wire _T_148 = io_din[14] & _T_147; // @[el2_ifu_compress_ctl.scala 35:99]
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wire out_13 = _T_144 | _T_148; // @[el2_ifu_compress_ctl.scala 40:86]
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wire out_13 = _T_144 | _T_148; // @[el2_ifu_compress_ctl.scala 35:86]
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wire _T_161 = _T_102 & io_din[5]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_161 = _T_102 & io_din[5]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_162 = _T_161 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_162 = _T_161 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_175 = _T_162 | _T_79; // @[el2_ifu_compress_ctl.scala 41:47]
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wire _T_175 = _T_162 | _T_79; // @[el2_ifu_compress_ctl.scala 36:47]
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wire _T_188 = _T_175 | _T_91; // @[el2_ifu_compress_ctl.scala 41:81]
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wire _T_188 = _T_175 | _T_91; // @[el2_ifu_compress_ctl.scala 36:81]
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wire _T_190 = ~io_din[15]; // @[el2_ifu_compress_ctl.scala 33:83]
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wire _T_190 = ~io_din[15]; // @[el2_ifu_compress_ctl.scala 28:83]
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wire _T_194 = _T_190 & _T_2; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_194 = _T_190 & _T_2; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_195 = _T_194 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_195 = _T_194 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_196 = _T_188 | _T_195; // @[el2_ifu_compress_ctl.scala 41:115]
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wire _T_196 = _T_188 | _T_195; // @[el2_ifu_compress_ctl.scala 36:115]
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wire _T_200 = io_din[15] & io_din[14]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_200 = io_din[15] & io_din[14]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_201 = _T_200 & io_din[13]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_201 = _T_200 & io_din[13]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire out_12 = _T_196 | _T_201; // @[el2_ifu_compress_ctl.scala 42:26]
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wire out_12 = _T_196 | _T_201; // @[el2_ifu_compress_ctl.scala 37:26]
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wire _T_217 = _T_11 & _T_7; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_217 = _T_11 & _T_7; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_218 = _T_217 & _T_9; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_218 = _T_217 & _T_9; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_219 = _T_218 & _T_50; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_219 = _T_218 & _T_50; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_220 = _T_219 & _T_52; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_220 = _T_219 & _T_52; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_221 = _T_220 & _T_54; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_221 = _T_220 & _T_54; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_224 = _T_221 & _T_147; // @[el2_ifu_compress_ctl.scala 43:53]
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wire _T_224 = _T_221 & _T_147; // @[el2_ifu_compress_ctl.scala 38:53]
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wire _T_228 = _T_2 & io_din[13]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_228 = _T_2 & io_din[13]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_229 = _T_224 | _T_228; // @[el2_ifu_compress_ctl.scala 43:67]
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wire _T_229 = _T_224 | _T_228; // @[el2_ifu_compress_ctl.scala 38:67]
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wire _T_234 = _T_200 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_234 = _T_200 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire out_6 = _T_229 | _T_234; // @[el2_ifu_compress_ctl.scala 43:88]
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wire out_6 = _T_229 | _T_234; // @[el2_ifu_compress_ctl.scala 38:88]
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wire _T_239 = io_din[15] & _T_147; // @[el2_ifu_compress_ctl.scala 45:24]
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wire _T_239 = io_din[15] & _T_147; // @[el2_ifu_compress_ctl.scala 40:24]
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wire _T_243 = io_din[15] & io_din[11]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_243 = io_din[15] & io_din[11]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_244 = _T_243 & io_din[10]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_244 = _T_243 & io_din[10]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_245 = _T_239 | _T_244; // @[el2_ifu_compress_ctl.scala 45:39]
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wire _T_245 = _T_239 | _T_244; // @[el2_ifu_compress_ctl.scala 40:39]
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wire _T_249 = io_din[13] & _T_42; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_249 = io_din[13] & _T_42; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_250 = _T_245 | _T_249; // @[el2_ifu_compress_ctl.scala 45:63]
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wire _T_250 = _T_245 | _T_249; // @[el2_ifu_compress_ctl.scala 40:63]
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wire _T_253 = io_din[13] & io_din[7]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_253 = io_din[13] & io_din[7]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_254 = _T_250 | _T_253; // @[el2_ifu_compress_ctl.scala 45:83]
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wire _T_254 = _T_250 | _T_253; // @[el2_ifu_compress_ctl.scala 40:83]
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wire _T_257 = io_din[13] & io_din[9]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_257 = io_din[13] & io_din[9]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_258 = _T_254 | _T_257; // @[el2_ifu_compress_ctl.scala 45:102]
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wire _T_258 = _T_254 | _T_257; // @[el2_ifu_compress_ctl.scala 40:102]
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wire _T_261 = io_din[13] & io_din[10]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_261 = io_din[13] & io_din[10]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_262 = _T_258 | _T_261; // @[el2_ifu_compress_ctl.scala 46:22]
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wire _T_262 = _T_258 | _T_261; // @[el2_ifu_compress_ctl.scala 41:22]
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wire _T_265 = io_din[13] & io_din[11]; // @[el2_ifu_compress_ctl.scala 33:110]
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wire _T_265 = io_din[13] & io_din[11]; // @[el2_ifu_compress_ctl.scala 28:110]
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wire _T_266 = _T_262 | _T_265; // @[el2_ifu_compress_ctl.scala 46:42]
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wire _T_266 = _T_262 | _T_265; // @[el2_ifu_compress_ctl.scala 41:42]
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wire _T_271 = _T_266 | _T_228; // @[el2_ifu_compress_ctl.scala 46:62]
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wire _T_271 = _T_266 | _T_228; // @[el2_ifu_compress_ctl.scala 41:62]
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wire out_5 = _T_271 | _T_200; // @[el2_ifu_compress_ctl.scala 46:83]
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wire out_5 = _T_271 | _T_200; // @[el2_ifu_compress_ctl.scala 41:83]
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wire _T_288 = _T_2 & _T_23; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_288 = _T_2 & _T_23; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_289 = _T_288 & _T_38; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_289 = _T_288 & _T_38; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_290 = _T_289 & _T_40; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_290 = _T_289 & _T_40; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_291 = _T_290 & _T_42; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_291 = _T_290 & _T_42; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_292 = _T_291 & _T_44; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_292 = _T_291 & _T_44; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_295 = _T_292 & _T_147; // @[el2_ifu_compress_ctl.scala 49:50]
|
wire _T_295 = _T_292 & _T_147; // @[el2_ifu_compress_ctl.scala 44:50]
|
||||||
wire _T_303 = _T_194 & _T_147; // @[el2_ifu_compress_ctl.scala 49:87]
|
wire _T_303 = _T_194 & _T_147; // @[el2_ifu_compress_ctl.scala 44:87]
|
||||||
wire _T_304 = _T_295 | _T_303; // @[el2_ifu_compress_ctl.scala 49:65]
|
wire _T_304 = _T_295 | _T_303; // @[el2_ifu_compress_ctl.scala 44:65]
|
||||||
wire _T_308 = _T_2 & io_din[6]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_308 = _T_2 & io_din[6]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_311 = _T_308 & _T_147; // @[el2_ifu_compress_ctl.scala 50:23]
|
wire _T_311 = _T_308 & _T_147; // @[el2_ifu_compress_ctl.scala 45:23]
|
||||||
wire _T_312 = _T_304 | _T_311; // @[el2_ifu_compress_ctl.scala 49:102]
|
wire _T_312 = _T_304 | _T_311; // @[el2_ifu_compress_ctl.scala 44:102]
|
||||||
wire _T_317 = _T_190 & io_din[14]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_317 = _T_190 & io_din[14]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_318 = _T_317 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_318 = _T_317 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_319 = _T_312 | _T_318; // @[el2_ifu_compress_ctl.scala 50:38]
|
wire _T_319 = _T_312 | _T_318; // @[el2_ifu_compress_ctl.scala 45:38]
|
||||||
wire _T_323 = _T_2 & io_din[5]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_323 = _T_2 & io_din[5]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_326 = _T_323 & _T_147; // @[el2_ifu_compress_ctl.scala 50:82]
|
wire _T_326 = _T_323 & _T_147; // @[el2_ifu_compress_ctl.scala 45:82]
|
||||||
wire _T_327 = _T_319 | _T_326; // @[el2_ifu_compress_ctl.scala 50:62]
|
wire _T_327 = _T_319 | _T_326; // @[el2_ifu_compress_ctl.scala 45:62]
|
||||||
wire _T_331 = _T_2 & io_din[4]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_331 = _T_2 & io_din[4]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_334 = _T_331 & _T_147; // @[el2_ifu_compress_ctl.scala 51:23]
|
wire _T_334 = _T_331 & _T_147; // @[el2_ifu_compress_ctl.scala 46:23]
|
||||||
wire _T_335 = _T_327 | _T_334; // @[el2_ifu_compress_ctl.scala 50:97]
|
wire _T_335 = _T_327 | _T_334; // @[el2_ifu_compress_ctl.scala 45:97]
|
||||||
wire _T_339 = _T_2 & io_din[3]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_339 = _T_2 & io_din[3]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_342 = _T_339 & _T_147; // @[el2_ifu_compress_ctl.scala 51:58]
|
wire _T_342 = _T_339 & _T_147; // @[el2_ifu_compress_ctl.scala 46:58]
|
||||||
wire _T_343 = _T_335 | _T_342; // @[el2_ifu_compress_ctl.scala 51:38]
|
wire _T_343 = _T_335 | _T_342; // @[el2_ifu_compress_ctl.scala 46:38]
|
||||||
wire _T_347 = _T_2 & io_din[2]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_347 = _T_2 & io_din[2]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_350 = _T_347 & _T_147; // @[el2_ifu_compress_ctl.scala 51:93]
|
wire _T_350 = _T_347 & _T_147; // @[el2_ifu_compress_ctl.scala 46:93]
|
||||||
wire _T_351 = _T_343 | _T_350; // @[el2_ifu_compress_ctl.scala 51:73]
|
wire _T_351 = _T_343 | _T_350; // @[el2_ifu_compress_ctl.scala 46:73]
|
||||||
wire _T_357 = _T_2 & _T_4; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_357 = _T_2 & _T_4; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_358 = _T_357 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_358 = _T_357 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire out_4 = _T_351 | _T_358; // @[el2_ifu_compress_ctl.scala 51:108]
|
wire out_4 = _T_351 | _T_358; // @[el2_ifu_compress_ctl.scala 46:108]
|
||||||
wire _T_380 = _T_56 & io_din[11]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_380 = _T_56 & io_din[11]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_381 = _T_380 & _T_7; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_381 = _T_380 & _T_7; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_382 = _T_381 & _T_9; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_382 = _T_381 & _T_9; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_383 = _T_382 & _T_50; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_383 = _T_382 & _T_50; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_384 = _T_383 & _T_52; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_384 = _T_383 & _T_52; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_385 = _T_384 & _T_54; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_385 = _T_384 & _T_54; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_386 = _T_385 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_386 = _T_385 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_403 = _T_56 & io_din[10]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_403 = _T_56 & io_din[10]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_404 = _T_403 & _T_7; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_404 = _T_403 & _T_7; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_405 = _T_404 & _T_9; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_405 = _T_404 & _T_9; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_406 = _T_405 & _T_50; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_406 = _T_405 & _T_50; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_407 = _T_406 & _T_52; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_407 = _T_406 & _T_52; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_408 = _T_407 & _T_54; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_408 = _T_407 & _T_54; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_409 = _T_408 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_409 = _T_408 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_410 = _T_386 | _T_409; // @[el2_ifu_compress_ctl.scala 58:59]
|
wire _T_410 = _T_386 | _T_409; // @[el2_ifu_compress_ctl.scala 53:59]
|
||||||
wire _T_427 = _T_56 & io_din[9]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_427 = _T_56 & io_din[9]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_428 = _T_427 & _T_7; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_428 = _T_427 & _T_7; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_429 = _T_428 & _T_9; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_429 = _T_428 & _T_9; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_430 = _T_429 & _T_50; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_430 = _T_429 & _T_50; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_431 = _T_430 & _T_52; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_431 = _T_430 & _T_52; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_432 = _T_431 & _T_54; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_432 = _T_431 & _T_54; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_433 = _T_432 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_433 = _T_432 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_434 = _T_410 | _T_433; // @[el2_ifu_compress_ctl.scala 59:59]
|
wire _T_434 = _T_410 | _T_433; // @[el2_ifu_compress_ctl.scala 54:59]
|
||||||
wire _T_451 = _T_56 & io_din[8]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_451 = _T_56 & io_din[8]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_452 = _T_451 & _T_7; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_452 = _T_451 & _T_7; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_453 = _T_452 & _T_9; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_453 = _T_452 & _T_9; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_454 = _T_453 & _T_50; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_454 = _T_453 & _T_50; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_455 = _T_454 & _T_52; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_455 = _T_454 & _T_52; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_456 = _T_455 & _T_54; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_456 = _T_455 & _T_54; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_457 = _T_456 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_457 = _T_456 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_458 = _T_434 | _T_457; // @[el2_ifu_compress_ctl.scala 60:58]
|
wire _T_458 = _T_434 | _T_457; // @[el2_ifu_compress_ctl.scala 55:58]
|
||||||
wire _T_475 = _T_56 & io_din[7]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_475 = _T_56 & io_din[7]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_476 = _T_475 & _T_7; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_476 = _T_475 & _T_7; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_477 = _T_476 & _T_9; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_477 = _T_476 & _T_9; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_478 = _T_477 & _T_50; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_478 = _T_477 & _T_50; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_479 = _T_478 & _T_52; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_479 = _T_478 & _T_52; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_480 = _T_479 & _T_54; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_480 = _T_479 & _T_54; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_481 = _T_480 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_481 = _T_480 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_482 = _T_458 | _T_481; // @[el2_ifu_compress_ctl.scala 61:55]
|
wire _T_482 = _T_458 | _T_481; // @[el2_ifu_compress_ctl.scala 56:55]
|
||||||
wire _T_487 = ~io_din[12]; // @[el2_ifu_compress_ctl.scala 33:83]
|
wire _T_487 = ~io_din[12]; // @[el2_ifu_compress_ctl.scala 28:83]
|
||||||
wire _T_499 = _T_11 & _T_487; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_499 = _T_11 & _T_487; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_500 = _T_499 & _T_7; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_500 = _T_499 & _T_7; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_501 = _T_500 & _T_9; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_501 = _T_500 & _T_9; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_502 = _T_501 & _T_50; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_502 = _T_501 & _T_50; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_503 = _T_502 & _T_52; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_503 = _T_502 & _T_52; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_504 = _T_503 & _T_54; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_504 = _T_503 & _T_54; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_507 = _T_504 & _T_147; // @[el2_ifu_compress_ctl.scala 63:56]
|
wire _T_507 = _T_504 & _T_147; // @[el2_ifu_compress_ctl.scala 58:56]
|
||||||
wire _T_508 = _T_482 | _T_507; // @[el2_ifu_compress_ctl.scala 62:57]
|
wire _T_508 = _T_482 | _T_507; // @[el2_ifu_compress_ctl.scala 57:57]
|
||||||
wire _T_514 = _T_190 & io_din[13]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_514 = _T_190 & io_din[13]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_515 = _T_514 & _T_42; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_515 = _T_514 & _T_42; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_516 = _T_508 | _T_515; // @[el2_ifu_compress_ctl.scala 63:71]
|
wire _T_516 = _T_508 | _T_515; // @[el2_ifu_compress_ctl.scala 58:71]
|
||||||
wire _T_522 = _T_514 & io_din[7]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_522 = _T_514 & io_din[7]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_523 = _T_516 | _T_522; // @[el2_ifu_compress_ctl.scala 64:34]
|
wire _T_523 = _T_516 | _T_522; // @[el2_ifu_compress_ctl.scala 59:34]
|
||||||
wire _T_529 = _T_514 & io_din[9]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_529 = _T_514 & io_din[9]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_530 = _T_523 | _T_529; // @[el2_ifu_compress_ctl.scala 65:33]
|
wire _T_530 = _T_523 | _T_529; // @[el2_ifu_compress_ctl.scala 60:33]
|
||||||
wire _T_536 = _T_514 & io_din[10]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_536 = _T_514 & io_din[10]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_537 = _T_530 | _T_536; // @[el2_ifu_compress_ctl.scala 66:33]
|
wire _T_537 = _T_530 | _T_536; // @[el2_ifu_compress_ctl.scala 61:33]
|
||||||
wire _T_543 = _T_514 & io_din[11]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_543 = _T_514 & io_din[11]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_544 = _T_537 | _T_543; // @[el2_ifu_compress_ctl.scala 67:34]
|
wire _T_544 = _T_537 | _T_543; // @[el2_ifu_compress_ctl.scala 62:34]
|
||||||
wire out_2 = _T_544 | _T_228; // @[el2_ifu_compress_ctl.scala 68:34]
|
wire out_2 = _T_544 | _T_228; // @[el2_ifu_compress_ctl.scala 63:34]
|
||||||
wire [4:0] rs2d = io_din[6:2]; // @[el2_ifu_compress_ctl.scala 77:20]
|
wire [4:0] rs2d = io_din[6:2]; // @[el2_ifu_compress_ctl.scala 72:20]
|
||||||
wire [4:0] rdd = io_din[11:7]; // @[el2_ifu_compress_ctl.scala 78:19]
|
wire [4:0] rdd = io_din[11:7]; // @[el2_ifu_compress_ctl.scala 73:19]
|
||||||
wire [4:0] rdpd = {2'h1,io_din[9:7]}; // @[Cat.scala 29:58]
|
wire [4:0] rdpd = {2'h1,io_din[9:7]}; // @[Cat.scala 29:58]
|
||||||
wire [4:0] rs2pd = {2'h1,io_din[4:2]}; // @[Cat.scala 29:58]
|
wire [4:0] rs2pd = {2'h1,io_din[4:2]}; // @[Cat.scala 29:58]
|
||||||
wire _T_557 = _T_308 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_557 = _T_308 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_564 = _T_317 & io_din[11]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_564 = _T_317 & io_din[11]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_565 = _T_564 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_565 = _T_564 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_566 = _T_557 | _T_565; // @[el2_ifu_compress_ctl.scala 82:33]
|
wire _T_566 = _T_557 | _T_565; // @[el2_ifu_compress_ctl.scala 77:33]
|
||||||
wire _T_572 = _T_323 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_572 = _T_323 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_573 = _T_566 | _T_572; // @[el2_ifu_compress_ctl.scala 82:58]
|
wire _T_573 = _T_566 | _T_572; // @[el2_ifu_compress_ctl.scala 77:58]
|
||||||
wire _T_580 = _T_317 & io_din[10]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_580 = _T_317 & io_din[10]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_581 = _T_580 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_581 = _T_580 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_582 = _T_573 | _T_581; // @[el2_ifu_compress_ctl.scala 82:79]
|
wire _T_582 = _T_573 | _T_581; // @[el2_ifu_compress_ctl.scala 77:79]
|
||||||
wire _T_588 = _T_331 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_588 = _T_331 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_589 = _T_582 | _T_588; // @[el2_ifu_compress_ctl.scala 82:104]
|
wire _T_589 = _T_582 | _T_588; // @[el2_ifu_compress_ctl.scala 77:104]
|
||||||
wire _T_596 = _T_317 & io_din[9]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_596 = _T_317 & io_din[9]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_597 = _T_596 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_597 = _T_596 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_598 = _T_589 | _T_597; // @[el2_ifu_compress_ctl.scala 83:24]
|
wire _T_598 = _T_589 | _T_597; // @[el2_ifu_compress_ctl.scala 78:24]
|
||||||
wire _T_604 = _T_339 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_604 = _T_339 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_605 = _T_598 | _T_604; // @[el2_ifu_compress_ctl.scala 83:48]
|
wire _T_605 = _T_598 | _T_604; // @[el2_ifu_compress_ctl.scala 78:48]
|
||||||
wire _T_613 = _T_317 & _T_42; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_613 = _T_317 & _T_42; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_614 = _T_613 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_614 = _T_613 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_615 = _T_605 | _T_614; // @[el2_ifu_compress_ctl.scala 83:69]
|
wire _T_615 = _T_605 | _T_614; // @[el2_ifu_compress_ctl.scala 78:69]
|
||||||
wire _T_621 = _T_347 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_621 = _T_347 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_622 = _T_615 | _T_621; // @[el2_ifu_compress_ctl.scala 83:94]
|
wire _T_622 = _T_615 | _T_621; // @[el2_ifu_compress_ctl.scala 78:94]
|
||||||
wire _T_629 = _T_317 & io_din[7]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_629 = _T_317 & io_din[7]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_630 = _T_629 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_630 = _T_629 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_631 = _T_622 | _T_630; // @[el2_ifu_compress_ctl.scala 84:22]
|
wire _T_631 = _T_622 | _T_630; // @[el2_ifu_compress_ctl.scala 79:22]
|
||||||
wire _T_635 = _T_190 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_635 = _T_190 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_636 = _T_631 | _T_635; // @[el2_ifu_compress_ctl.scala 84:46]
|
wire _T_636 = _T_631 | _T_635; // @[el2_ifu_compress_ctl.scala 79:46]
|
||||||
wire _T_642 = _T_190 & _T_4; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_642 = _T_190 & _T_4; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_643 = _T_642 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_643 = _T_642 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire rdrd = _T_636 | _T_643; // @[el2_ifu_compress_ctl.scala 84:65]
|
wire rdrd = _T_636 | _T_643; // @[el2_ifu_compress_ctl.scala 79:65]
|
||||||
wire _T_651 = _T_380 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_651 = _T_380 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_659 = _T_403 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_659 = _T_403 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_660 = _T_651 | _T_659; // @[el2_ifu_compress_ctl.scala 86:38]
|
wire _T_660 = _T_651 | _T_659; // @[el2_ifu_compress_ctl.scala 81:38]
|
||||||
wire _T_668 = _T_427 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_668 = _T_427 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_669 = _T_660 | _T_668; // @[el2_ifu_compress_ctl.scala 87:28]
|
wire _T_669 = _T_660 | _T_668; // @[el2_ifu_compress_ctl.scala 82:28]
|
||||||
wire _T_677 = _T_451 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_677 = _T_451 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_678 = _T_669 | _T_677; // @[el2_ifu_compress_ctl.scala 88:27]
|
wire _T_678 = _T_669 | _T_677; // @[el2_ifu_compress_ctl.scala 83:27]
|
||||||
wire _T_686 = _T_475 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_686 = _T_475 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_687 = _T_678 | _T_686; // @[el2_ifu_compress_ctl.scala 89:27]
|
wire _T_687 = _T_678 | _T_686; // @[el2_ifu_compress_ctl.scala 84:27]
|
||||||
wire _T_703 = _T_2 & _T_487; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_703 = _T_2 & _T_487; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_704 = _T_703 & _T_7; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_704 = _T_703 & _T_7; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_705 = _T_704 & _T_9; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_705 = _T_704 & _T_9; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_706 = _T_705 & _T_50; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_706 = _T_705 & _T_50; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_707 = _T_706 & _T_52; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_707 = _T_706 & _T_52; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_708 = _T_707 & _T_54; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_708 = _T_707 & _T_54; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_709 = _T_708 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_709 = _T_708 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_710 = _T_687 | _T_709; // @[el2_ifu_compress_ctl.scala 90:27]
|
wire _T_710 = _T_687 | _T_709; // @[el2_ifu_compress_ctl.scala 85:27]
|
||||||
wire _T_717 = _T_56 & io_din[6]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_717 = _T_56 & io_din[6]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_718 = _T_717 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_718 = _T_717 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_719 = _T_710 | _T_718; // @[el2_ifu_compress_ctl.scala 91:41]
|
wire _T_719 = _T_710 | _T_718; // @[el2_ifu_compress_ctl.scala 86:41]
|
||||||
wire _T_726 = _T_56 & io_din[5]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_726 = _T_56 & io_din[5]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_727 = _T_726 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_727 = _T_726 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_728 = _T_719 | _T_727; // @[el2_ifu_compress_ctl.scala 92:27]
|
wire _T_728 = _T_719 | _T_727; // @[el2_ifu_compress_ctl.scala 87:27]
|
||||||
wire _T_735 = _T_56 & io_din[4]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_735 = _T_56 & io_din[4]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_736 = _T_735 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_736 = _T_735 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_737 = _T_728 | _T_736; // @[el2_ifu_compress_ctl.scala 93:27]
|
wire _T_737 = _T_728 | _T_736; // @[el2_ifu_compress_ctl.scala 88:27]
|
||||||
wire _T_744 = _T_56 & io_din[3]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_744 = _T_56 & io_din[3]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_745 = _T_744 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_745 = _T_744 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_746 = _T_737 | _T_745; // @[el2_ifu_compress_ctl.scala 94:27]
|
wire _T_746 = _T_737 | _T_745; // @[el2_ifu_compress_ctl.scala 89:27]
|
||||||
wire _T_753 = _T_56 & io_din[2]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_753 = _T_56 & io_din[2]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_754 = _T_753 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_754 = _T_753 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_755 = _T_746 | _T_754; // @[el2_ifu_compress_ctl.scala 95:27]
|
wire _T_755 = _T_746 | _T_754; // @[el2_ifu_compress_ctl.scala 90:27]
|
||||||
wire _T_764 = _T_194 & _T_4; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_764 = _T_194 & _T_4; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_765 = _T_764 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_765 = _T_764 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_766 = _T_755 | _T_765; // @[el2_ifu_compress_ctl.scala 96:27]
|
wire _T_766 = _T_755 | _T_765; // @[el2_ifu_compress_ctl.scala 91:27]
|
||||||
wire rdrs1 = _T_766 | _T_195; // @[el2_ifu_compress_ctl.scala 97:30]
|
wire rdrs1 = _T_766 | _T_195; // @[el2_ifu_compress_ctl.scala 92:30]
|
||||||
wire _T_777 = io_din[15] & io_din[6]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_777 = io_din[15] & io_din[6]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_778 = _T_777 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_778 = _T_777 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_782 = io_din[15] & io_din[5]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_782 = io_din[15] & io_din[5]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_783 = _T_782 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_783 = _T_782 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_784 = _T_778 | _T_783; // @[el2_ifu_compress_ctl.scala 100:34]
|
wire _T_784 = _T_778 | _T_783; // @[el2_ifu_compress_ctl.scala 95:34]
|
||||||
wire _T_788 = io_din[15] & io_din[4]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_788 = io_din[15] & io_din[4]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_789 = _T_788 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_789 = _T_788 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_790 = _T_784 | _T_789; // @[el2_ifu_compress_ctl.scala 100:54]
|
wire _T_790 = _T_784 | _T_789; // @[el2_ifu_compress_ctl.scala 95:54]
|
||||||
wire _T_794 = io_din[15] & io_din[3]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_794 = io_din[15] & io_din[3]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_795 = _T_794 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_795 = _T_794 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_796 = _T_790 | _T_795; // @[el2_ifu_compress_ctl.scala 100:74]
|
wire _T_796 = _T_790 | _T_795; // @[el2_ifu_compress_ctl.scala 95:74]
|
||||||
wire _T_800 = io_din[15] & io_din[2]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_800 = io_din[15] & io_din[2]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_801 = _T_800 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_801 = _T_800 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_802 = _T_796 | _T_801; // @[el2_ifu_compress_ctl.scala 100:94]
|
wire _T_802 = _T_796 | _T_801; // @[el2_ifu_compress_ctl.scala 95:94]
|
||||||
wire _T_807 = _T_200 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_807 = _T_200 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire rs2rs2 = _T_802 | _T_807; // @[el2_ifu_compress_ctl.scala 100:114]
|
wire rs2rs2 = _T_802 | _T_807; // @[el2_ifu_compress_ctl.scala 95:114]
|
||||||
wire rdprd = _T_12 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire rdprd = _T_12 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_820 = io_din[15] & _T_4; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_820 = io_din[15] & _T_4; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_821 = _T_820 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_821 = _T_820 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_827 = _T_821 | _T_234; // @[el2_ifu_compress_ctl.scala 104:36]
|
wire _T_827 = _T_821 | _T_234; // @[el2_ifu_compress_ctl.scala 99:36]
|
||||||
wire _T_830 = ~io_din[1]; // @[el2_ifu_compress_ctl.scala 33:83]
|
wire _T_830 = ~io_din[1]; // @[el2_ifu_compress_ctl.scala 28:83]
|
||||||
wire _T_831 = io_din[14] & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_831 = io_din[14] & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_834 = _T_831 & _T_147; // @[el2_ifu_compress_ctl.scala 104:76]
|
wire _T_834 = _T_831 & _T_147; // @[el2_ifu_compress_ctl.scala 99:76]
|
||||||
wire rdprs1 = _T_827 | _T_834; // @[el2_ifu_compress_ctl.scala 104:57]
|
wire rdprs1 = _T_827 | _T_834; // @[el2_ifu_compress_ctl.scala 99:57]
|
||||||
wire _T_846 = _T_128 & io_din[10]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_846 = _T_128 & io_din[10]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_847 = _T_846 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_847 = _T_846 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_851 = io_din[15] & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_851 = io_din[15] & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_854 = _T_851 & _T_147; // @[el2_ifu_compress_ctl.scala 106:66]
|
wire _T_854 = _T_851 & _T_147; // @[el2_ifu_compress_ctl.scala 101:66]
|
||||||
wire rs2prs2 = _T_847 | _T_854; // @[el2_ifu_compress_ctl.scala 106:47]
|
wire rs2prs2 = _T_847 | _T_854; // @[el2_ifu_compress_ctl.scala 101:47]
|
||||||
wire _T_859 = _T_190 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_859 = _T_190 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire rs2prd = _T_859 & _T_147; // @[el2_ifu_compress_ctl.scala 107:33]
|
wire rs2prd = _T_859 & _T_147; // @[el2_ifu_compress_ctl.scala 102:33]
|
||||||
wire _T_866 = _T_2 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_866 = _T_2 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire uimm9_2 = _T_866 & _T_147; // @[el2_ifu_compress_ctl.scala 108:34]
|
wire uimm9_2 = _T_866 & _T_147; // @[el2_ifu_compress_ctl.scala 103:34]
|
||||||
wire _T_875 = _T_317 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_875 = _T_317 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire ulwimm6_2 = _T_875 & _T_147; // @[el2_ifu_compress_ctl.scala 109:39]
|
wire ulwimm6_2 = _T_875 & _T_147; // @[el2_ifu_compress_ctl.scala 104:39]
|
||||||
wire ulwspimm7_2 = _T_317 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire ulwspimm7_2 = _T_317 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_897 = _T_317 & io_din[13]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_897 = _T_317 & io_din[13]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_898 = _T_897 & _T_23; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_898 = _T_897 & _T_23; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_899 = _T_898 & _T_38; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_899 = _T_898 & _T_38; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_900 = _T_899 & _T_40; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_900 = _T_899 & _T_40; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_901 = _T_900 & io_din[8]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_901 = _T_900 & io_din[8]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire rdeq2 = _T_901 & _T_44; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire rdeq2 = _T_901 & _T_44; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1027 = _T_194 & io_din[13]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1027 = _T_194 & io_din[13]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire rdeq1 = _T_482 | _T_1027; // @[el2_ifu_compress_ctl.scala 114:42]
|
wire rdeq1 = _T_482 | _T_1027; // @[el2_ifu_compress_ctl.scala 109:42]
|
||||||
wire _T_1050 = io_din[14] & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1050 = io_din[14] & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1051 = rdeq2 | _T_1050; // @[el2_ifu_compress_ctl.scala 115:53]
|
wire _T_1051 = rdeq2 | _T_1050; // @[el2_ifu_compress_ctl.scala 110:53]
|
||||||
wire rs1eq2 = _T_1051 | uimm9_2; // @[el2_ifu_compress_ctl.scala 115:71]
|
wire rs1eq2 = _T_1051 | uimm9_2; // @[el2_ifu_compress_ctl.scala 110:71]
|
||||||
wire _T_1092 = _T_357 & io_din[11]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1092 = _T_357 & io_din[11]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1093 = _T_1092 & _T_38; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1093 = _T_1092 & _T_38; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1094 = _T_1093 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1094 = _T_1093 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire simm5_0 = _T_1094 | _T_643; // @[el2_ifu_compress_ctl.scala 118:45]
|
wire simm5_0 = _T_1094 | _T_643; // @[el2_ifu_compress_ctl.scala 113:45]
|
||||||
wire _T_1112 = _T_897 & io_din[7]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1112 = _T_897 & io_din[7]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1121 = _T_897 & _T_42; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1121 = _T_897 & _T_42; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1122 = _T_1112 | _T_1121; // @[el2_ifu_compress_ctl.scala 120:44]
|
wire _T_1122 = _T_1112 | _T_1121; // @[el2_ifu_compress_ctl.scala 115:44]
|
||||||
wire _T_1130 = _T_897 & io_din[9]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1130 = _T_897 & io_din[9]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1131 = _T_1122 | _T_1130; // @[el2_ifu_compress_ctl.scala 121:29]
|
wire _T_1131 = _T_1122 | _T_1130; // @[el2_ifu_compress_ctl.scala 116:29]
|
||||||
wire _T_1139 = _T_897 & io_din[10]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1139 = _T_897 & io_din[10]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1140 = _T_1131 | _T_1139; // @[el2_ifu_compress_ctl.scala 122:28]
|
wire _T_1140 = _T_1131 | _T_1139; // @[el2_ifu_compress_ctl.scala 117:28]
|
||||||
wire _T_1148 = _T_897 & io_din[11]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1148 = _T_897 & io_din[11]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire sluimm17_12 = _T_1140 | _T_1148; // @[el2_ifu_compress_ctl.scala 123:29]
|
wire sluimm17_12 = _T_1140 | _T_1148; // @[el2_ifu_compress_ctl.scala 118:29]
|
||||||
wire uimm5_0 = _T_79 | _T_195; // @[el2_ifu_compress_ctl.scala 125:45]
|
wire uimm5_0 = _T_79 | _T_195; // @[el2_ifu_compress_ctl.scala 120:45]
|
||||||
wire [6:0] l1_6 = {out_6,out_5,out_4,_T_228,out_2,1'h1,1'h1}; // @[Cat.scala 29:58]
|
wire [6:0] l1_6 = {out_6,out_5,out_4,_T_228,out_2,1'h1,1'h1}; // @[Cat.scala 29:58]
|
||||||
wire [4:0] _T_1192 = rdrd ? rdd : 5'h0; // @[Mux.scala 27:72]
|
wire [4:0] _T_1192 = rdrd ? rdd : 5'h0; // @[Mux.scala 27:72]
|
||||||
wire [4:0] _T_1193 = rdprd ? rdpd : 5'h0; // @[Mux.scala 27:72]
|
wire [4:0] _T_1193 = rdprd ? rdpd : 5'h0; // @[Mux.scala 27:72]
|
||||||
|
|
@ -344,7 +345,7 @@ module el2_ifu_compress_ctl(
|
||||||
wire [4:0] _T_1222 = rs2rs2 ? rs2d : 5'h0; // @[Mux.scala 27:72]
|
wire [4:0] _T_1222 = rs2rs2 ? rs2d : 5'h0; // @[Mux.scala 27:72]
|
||||||
wire [4:0] _T_1223 = rs2prs2 ? rs2pd : 5'h0; // @[Mux.scala 27:72]
|
wire [4:0] _T_1223 = rs2prs2 ? rs2pd : 5'h0; // @[Mux.scala 27:72]
|
||||||
wire [4:0] _T_1224 = _T_1222 | _T_1223; // @[Mux.scala 27:72]
|
wire [4:0] _T_1224 = _T_1222 | _T_1223; // @[Mux.scala 27:72]
|
||||||
wire [4:0] l1_24 = _T_1219 | _T_1224; // @[el2_ifu_compress_ctl.scala 138:67]
|
wire [4:0] l1_24 = _T_1219 | _T_1224; // @[el2_ifu_compress_ctl.scala 133:67]
|
||||||
wire [14:0] _T_1232 = {out_14,out_13,out_12,l1_11,l1_6}; // @[Cat.scala 29:58]
|
wire [14:0] _T_1232 = {out_14,out_13,out_12,l1_11,l1_6}; // @[Cat.scala 29:58]
|
||||||
wire [16:0] _T_1234 = {1'h0,out_30,2'h0,3'h0,l1_24,l1_19}; // @[Cat.scala 29:58]
|
wire [16:0] _T_1234 = {1'h0,out_30,2'h0,3'h0,l1_24,l1_19}; // @[Cat.scala 29:58]
|
||||||
wire [31:0] l1 = {1'h0,out_30,2'h0,3'h0,l1_24,l1_19,_T_1232}; // @[Cat.scala 29:58]
|
wire [31:0] l1 = {1'h0,out_30,2'h0,3'h0,l1_24,l1_19,_T_1232}; // @[Cat.scala 29:58]
|
||||||
|
|
@ -356,6 +357,7 @@ module el2_ifu_compress_ctl(
|
||||||
wire [5:0] simm9d = {io_din[12],io_din[4:3],io_din[5],io_din[2],io_din[6]}; // @[Cat.scala 29:58]
|
wire [5:0] simm9d = {io_din[12],io_din[4:3],io_din[5],io_din[2],io_din[6]}; // @[Cat.scala 29:58]
|
||||||
wire [3:0] _T_1254 = {io_din[5],io_din[12:10]}; // @[Cat.scala 29:58]
|
wire [3:0] _T_1254 = {io_din[5],io_din[12:10]}; // @[Cat.scala 29:58]
|
||||||
wire [2:0] _T_1258 = {io_din[3:2],io_din[12]}; // @[Cat.scala 29:58]
|
wire [2:0] _T_1258 = {io_din[3:2],io_din[12]}; // @[Cat.scala 29:58]
|
||||||
|
wire [10:0] sjald_1 = {io_din[12],io_din[8],io_din[10:9],io_din[6],io_din[7],io_din[2],io_din[11],io_din[5:4],io_din[3]}; // @[Cat.scala 29:58]
|
||||||
wire [8:0] sjald_12 = io_din[12] ? 9'h1ff : 9'h0; // @[Bitwise.scala 72:12]
|
wire [8:0] sjald_12 = io_din[12] ? 9'h1ff : 9'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [19:0] sjald = {sjald_12,io_din[12],io_din[8],io_din[10:9],io_din[6],io_din[7],io_din[2],io_din[11],io_din[5:4],io_din[3]}; // @[Cat.scala 29:58]
|
wire [19:0] sjald = {sjald_12,io_din[12],io_din[8],io_din[10:9],io_din[6],io_din[7],io_din[2],io_din[11],io_din[5:4],io_din[3]}; // @[Cat.scala 29:58]
|
||||||
wire [14:0] _T_1281 = io_din[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12]
|
wire [14:0] _T_1281 = io_din[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12]
|
||||||
|
|
@ -384,13 +386,13 @@ module el2_ifu_compress_ctl(
|
||||||
wire [11:0] _T_1326 = _T_1325 | _T_1319; // @[Mux.scala 27:72]
|
wire [11:0] _T_1326 = _T_1325 | _T_1319; // @[Mux.scala 27:72]
|
||||||
wire [11:0] _T_1327 = _T_1326 | _T_1320; // @[Mux.scala 27:72]
|
wire [11:0] _T_1327 = _T_1326 | _T_1320; // @[Mux.scala 27:72]
|
||||||
wire [11:0] _T_1328 = _T_1327 | _T_1321; // @[Mux.scala 27:72]
|
wire [11:0] _T_1328 = _T_1327 | _T_1321; // @[Mux.scala 27:72]
|
||||||
wire [11:0] l2_31 = l1[31:20] | _T_1328; // @[el2_ifu_compress_ctl.scala 155:25]
|
wire [11:0] l2_31 = l1[31:20] | _T_1328; // @[el2_ifu_compress_ctl.scala 151:25]
|
||||||
wire [8:0] _T_1335 = _T_228 ? sjald[19:11] : 9'h0; // @[Mux.scala 27:72]
|
wire [8:0] _T_1335 = _T_228 ? sjald[19:11] : 9'h0; // @[Mux.scala 27:72]
|
||||||
wire [7:0] _T_1336 = sluimm17_12 ? sluimmd[7:0] : 8'h0; // @[Mux.scala 27:72]
|
wire [7:0] _T_1336 = sluimm17_12 ? sluimmd[7:0] : 8'h0; // @[Mux.scala 27:72]
|
||||||
wire [8:0] _GEN_0 = {{1'd0}, _T_1336}; // @[Mux.scala 27:72]
|
wire [8:0] _GEN_0 = {{1'd0}, _T_1336}; // @[Mux.scala 27:72]
|
||||||
wire [8:0] _T_1337 = _T_1335 | _GEN_0; // @[Mux.scala 27:72]
|
wire [8:0] _T_1337 = _T_1335 | _GEN_0; // @[Mux.scala 27:72]
|
||||||
wire [8:0] _GEN_1 = {{1'd0}, l1[19:12]}; // @[el2_ifu_compress_ctl.scala 165:25]
|
wire [8:0] _GEN_1 = {{1'd0}, l1[19:12]}; // @[el2_ifu_compress_ctl.scala 161:25]
|
||||||
wire [8:0] l2_19 = _GEN_1 | _T_1337; // @[el2_ifu_compress_ctl.scala 165:25]
|
wire [8:0] l2_19 = _GEN_1 | _T_1337; // @[el2_ifu_compress_ctl.scala 161:25]
|
||||||
wire [32:0] l2 = {l2_31,l2_19,l1[11:0]}; // @[Cat.scala 29:58]
|
wire [32:0] l2 = {l2_31,l2_19,l1[11:0]}; // @[Cat.scala 29:58]
|
||||||
wire [8:0] sbr8d = {io_din[12],io_din[6],io_din[5],io_din[2],io_din[11],io_din[10],io_din[4],io_din[3],1'h0}; // @[Cat.scala 29:58]
|
wire [8:0] sbr8d = {io_din[12],io_din[6],io_din[5],io_din[2],io_din[11],io_din[10],io_din[4],io_din[3],1'h0}; // @[Cat.scala 29:58]
|
||||||
wire [6:0] uswimm6d = {io_din[5],io_din[12:10],io_din[6],2'h0}; // @[Cat.scala 29:58]
|
wire [6:0] uswimm6d = {io_din[5],io_din[12:10],io_din[6],2'h0}; // @[Cat.scala 29:58]
|
||||||
|
|
@ -404,147 +406,148 @@ module el2_ifu_compress_ctl(
|
||||||
wire [6:0] _T_1379 = _T_807 ? _T_1376 : 7'h0; // @[Mux.scala 27:72]
|
wire [6:0] _T_1379 = _T_807 ? _T_1376 : 7'h0; // @[Mux.scala 27:72]
|
||||||
wire [6:0] _T_1380 = _T_1377 | _T_1378; // @[Mux.scala 27:72]
|
wire [6:0] _T_1380 = _T_1377 | _T_1378; // @[Mux.scala 27:72]
|
||||||
wire [6:0] _T_1381 = _T_1380 | _T_1379; // @[Mux.scala 27:72]
|
wire [6:0] _T_1381 = _T_1380 | _T_1379; // @[Mux.scala 27:72]
|
||||||
wire [6:0] l3_31 = l2[31:25] | _T_1381; // @[el2_ifu_compress_ctl.scala 173:25]
|
wire [6:0] l3_31 = l2[31:25] | _T_1381; // @[el2_ifu_compress_ctl.scala 169:25]
|
||||||
wire [12:0] l3_24 = l2[24:12]; // @[el2_ifu_compress_ctl.scala 176:17]
|
wire [12:0] l3_24 = l2[24:12]; // @[el2_ifu_compress_ctl.scala 172:17]
|
||||||
wire [4:0] _T_1387 = {sbr8d[4:1],sbr8d[8]}; // @[Cat.scala 29:58]
|
wire [4:0] _T_1387 = {sbr8d[4:1],sbr8d[8]}; // @[Cat.scala 29:58]
|
||||||
wire [4:0] _T_1392 = _T_234 ? _T_1387 : 5'h0; // @[Mux.scala 27:72]
|
wire [4:0] _T_1392 = _T_234 ? _T_1387 : 5'h0; // @[Mux.scala 27:72]
|
||||||
wire [4:0] _T_1393 = _T_854 ? uswimm6d[4:0] : 5'h0; // @[Mux.scala 27:72]
|
wire [4:0] _T_1393 = _T_854 ? uswimm6d[4:0] : 5'h0; // @[Mux.scala 27:72]
|
||||||
wire [4:0] _T_1394 = _T_807 ? uswspimm7d[4:0] : 5'h0; // @[Mux.scala 27:72]
|
wire [4:0] _T_1394 = _T_807 ? uswspimm7d[4:0] : 5'h0; // @[Mux.scala 27:72]
|
||||||
wire [4:0] _T_1395 = _T_1392 | _T_1393; // @[Mux.scala 27:72]
|
wire [4:0] _T_1395 = _T_1392 | _T_1393; // @[Mux.scala 27:72]
|
||||||
wire [4:0] _T_1396 = _T_1395 | _T_1394; // @[Mux.scala 27:72]
|
wire [4:0] _T_1396 = _T_1395 | _T_1394; // @[Mux.scala 27:72]
|
||||||
wire [4:0] l3_11 = l2[11:7] | _T_1396; // @[el2_ifu_compress_ctl.scala 177:24]
|
wire [4:0] l3_11 = l2[11:7] | _T_1396; // @[el2_ifu_compress_ctl.scala 173:24]
|
||||||
wire [11:0] _T_1399 = {l3_11,l2[6:0]}; // @[Cat.scala 29:58]
|
wire [11:0] _T_1399 = {l3_11,l2[6:0]}; // @[Cat.scala 29:58]
|
||||||
wire [19:0] _T_1400 = {l3_31,l3_24}; // @[Cat.scala 29:58]
|
wire [19:0] _T_1400 = {l3_31,l3_24}; // @[Cat.scala 29:58]
|
||||||
wire [31:0] l3 = {l3_31,l3_24,l3_11,l2[6:0]}; // @[Cat.scala 29:58]
|
wire [31:0] l3 = {l3_31,l3_24,l3_11,l2[6:0]}; // @[Cat.scala 29:58]
|
||||||
wire _T_1407 = _T_4 & _T_487; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1407 = _T_4 & _T_487; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1408 = _T_1407 & io_din[11]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1408 = _T_1407 & io_din[11]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1409 = _T_1408 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1409 = _T_1408 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1412 = _T_1409 & _T_147; // @[el2_ifu_compress_ctl.scala 182:39]
|
wire _T_1412 = _T_1409 & _T_147; // @[el2_ifu_compress_ctl.scala 178:39]
|
||||||
wire _T_1420 = _T_1407 & io_din[6]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1420 = _T_1407 & io_din[6]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1421 = _T_1420 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1421 = _T_1420 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1424 = _T_1421 & _T_147; // @[el2_ifu_compress_ctl.scala 182:79]
|
wire _T_1424 = _T_1421 & _T_147; // @[el2_ifu_compress_ctl.scala 178:79]
|
||||||
wire _T_1425 = _T_1412 | _T_1424; // @[el2_ifu_compress_ctl.scala 182:54]
|
wire _T_1425 = _T_1412 | _T_1424; // @[el2_ifu_compress_ctl.scala 178:54]
|
||||||
wire _T_1434 = _T_642 & io_din[11]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1434 = _T_642 & io_din[11]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1435 = _T_1434 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1435 = _T_1434 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1436 = _T_1425 | _T_1435; // @[el2_ifu_compress_ctl.scala 182:94]
|
wire _T_1436 = _T_1425 | _T_1435; // @[el2_ifu_compress_ctl.scala 178:94]
|
||||||
wire _T_1444 = _T_1407 & io_din[5]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1444 = _T_1407 & io_din[5]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1445 = _T_1444 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1445 = _T_1444 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1448 = _T_1445 & _T_147; // @[el2_ifu_compress_ctl.scala 183:55]
|
wire _T_1448 = _T_1445 & _T_147; // @[el2_ifu_compress_ctl.scala 179:55]
|
||||||
wire _T_1449 = _T_1436 | _T_1448; // @[el2_ifu_compress_ctl.scala 183:30]
|
wire _T_1449 = _T_1436 | _T_1448; // @[el2_ifu_compress_ctl.scala 179:30]
|
||||||
wire _T_1457 = _T_1407 & io_din[10]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1457 = _T_1407 & io_din[10]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1458 = _T_1457 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1458 = _T_1457 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1461 = _T_1458 & _T_147; // @[el2_ifu_compress_ctl.scala 183:96]
|
wire _T_1461 = _T_1458 & _T_147; // @[el2_ifu_compress_ctl.scala 179:96]
|
||||||
wire _T_1462 = _T_1449 | _T_1461; // @[el2_ifu_compress_ctl.scala 183:70]
|
wire _T_1462 = _T_1449 | _T_1461; // @[el2_ifu_compress_ctl.scala 179:70]
|
||||||
wire _T_1471 = _T_642 & io_din[6]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1471 = _T_642 & io_din[6]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1472 = _T_1471 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1472 = _T_1471 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1473 = _T_1462 | _T_1472; // @[el2_ifu_compress_ctl.scala 183:111]
|
wire _T_1473 = _T_1462 | _T_1472; // @[el2_ifu_compress_ctl.scala 179:111]
|
||||||
wire _T_1480 = io_din[15] & _T_487; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1480 = io_din[15] & _T_487; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1481 = _T_1480 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1481 = _T_1480 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1482 = _T_1481 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1482 = _T_1481 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1483 = _T_1473 | _T_1482; // @[el2_ifu_compress_ctl.scala 184:29]
|
wire _T_1483 = _T_1473 | _T_1482; // @[el2_ifu_compress_ctl.scala 180:29]
|
||||||
wire _T_1491 = _T_1407 & io_din[9]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1491 = _T_1407 & io_din[9]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1492 = _T_1491 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1492 = _T_1491 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1495 = _T_1492 & _T_147; // @[el2_ifu_compress_ctl.scala 184:79]
|
wire _T_1495 = _T_1492 & _T_147; // @[el2_ifu_compress_ctl.scala 180:79]
|
||||||
wire _T_1496 = _T_1483 | _T_1495; // @[el2_ifu_compress_ctl.scala 184:54]
|
wire _T_1496 = _T_1483 | _T_1495; // @[el2_ifu_compress_ctl.scala 180:54]
|
||||||
wire _T_1503 = _T_487 & io_din[6]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1503 = _T_487 & io_din[6]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1504 = _T_1503 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1504 = _T_1503 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1505 = _T_1504 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1505 = _T_1504 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1506 = _T_1496 | _T_1505; // @[el2_ifu_compress_ctl.scala 184:94]
|
wire _T_1506 = _T_1496 | _T_1505; // @[el2_ifu_compress_ctl.scala 180:94]
|
||||||
wire _T_1515 = _T_642 & io_din[5]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1515 = _T_642 & io_din[5]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1516 = _T_1515 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1516 = _T_1515 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1517 = _T_1506 | _T_1516; // @[el2_ifu_compress_ctl.scala 184:118]
|
wire _T_1517 = _T_1506 | _T_1516; // @[el2_ifu_compress_ctl.scala 180:118]
|
||||||
wire _T_1525 = _T_1407 & io_din[8]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1525 = _T_1407 & io_din[8]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1526 = _T_1525 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1526 = _T_1525 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1529 = _T_1526 & _T_147; // @[el2_ifu_compress_ctl.scala 185:28]
|
wire _T_1529 = _T_1526 & _T_147; // @[el2_ifu_compress_ctl.scala 181:28]
|
||||||
wire _T_1530 = _T_1517 | _T_1529; // @[el2_ifu_compress_ctl.scala 184:144]
|
wire _T_1530 = _T_1517 | _T_1529; // @[el2_ifu_compress_ctl.scala 180:144]
|
||||||
wire _T_1537 = _T_487 & io_din[5]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1537 = _T_487 & io_din[5]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1538 = _T_1537 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1538 = _T_1537 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1539 = _T_1538 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1539 = _T_1538 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1540 = _T_1530 | _T_1539; // @[el2_ifu_compress_ctl.scala 185:43]
|
wire _T_1540 = _T_1530 | _T_1539; // @[el2_ifu_compress_ctl.scala 181:43]
|
||||||
wire _T_1549 = _T_642 & io_din[10]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1549 = _T_642 & io_din[10]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1550 = _T_1549 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1550 = _T_1549 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1551 = _T_1540 | _T_1550; // @[el2_ifu_compress_ctl.scala 185:67]
|
wire _T_1551 = _T_1540 | _T_1550; // @[el2_ifu_compress_ctl.scala 181:67]
|
||||||
wire _T_1559 = _T_1407 & io_din[7]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1559 = _T_1407 & io_din[7]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1560 = _T_1559 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1560 = _T_1559 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1563 = _T_1560 & _T_147; // @[el2_ifu_compress_ctl.scala 186:28]
|
wire _T_1563 = _T_1560 & _T_147; // @[el2_ifu_compress_ctl.scala 182:28]
|
||||||
wire _T_1564 = _T_1551 | _T_1563; // @[el2_ifu_compress_ctl.scala 185:94]
|
wire _T_1564 = _T_1551 | _T_1563; // @[el2_ifu_compress_ctl.scala 181:94]
|
||||||
wire _T_1572 = io_din[12] & io_din[11]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1572 = io_din[12] & io_din[11]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1573 = _T_1572 & _T_38; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1573 = _T_1572 & _T_38; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1574 = _T_1573 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1574 = _T_1573 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1575 = _T_1574 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1575 = _T_1574 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1576 = _T_1564 | _T_1575; // @[el2_ifu_compress_ctl.scala 186:43]
|
wire _T_1576 = _T_1564 | _T_1575; // @[el2_ifu_compress_ctl.scala 182:43]
|
||||||
wire _T_1585 = _T_642 & io_din[9]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1585 = _T_642 & io_din[9]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1586 = _T_1585 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1586 = _T_1585 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1587 = _T_1576 | _T_1586; // @[el2_ifu_compress_ctl.scala 186:71]
|
wire _T_1587 = _T_1576 | _T_1586; // @[el2_ifu_compress_ctl.scala 182:71]
|
||||||
wire _T_1595 = _T_1407 & io_din[4]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1595 = _T_1407 & io_din[4]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1596 = _T_1595 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1596 = _T_1595 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1599 = _T_1596 & _T_147; // @[el2_ifu_compress_ctl.scala 187:28]
|
wire _T_1599 = _T_1596 & _T_147; // @[el2_ifu_compress_ctl.scala 183:28]
|
||||||
wire _T_1600 = _T_1587 | _T_1599; // @[el2_ifu_compress_ctl.scala 186:97]
|
wire _T_1600 = _T_1587 | _T_1599; // @[el2_ifu_compress_ctl.scala 182:97]
|
||||||
wire _T_1606 = io_din[13] & io_din[12]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1606 = io_din[13] & io_din[12]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1607 = _T_1606 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1607 = _T_1606 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1608 = _T_1607 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1608 = _T_1607 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1609 = _T_1600 | _T_1608; // @[el2_ifu_compress_ctl.scala 187:43]
|
wire _T_1609 = _T_1600 | _T_1608; // @[el2_ifu_compress_ctl.scala 183:43]
|
||||||
wire _T_1618 = _T_642 & io_din[8]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1618 = _T_642 & io_din[8]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1619 = _T_1618 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1619 = _T_1618 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1620 = _T_1609 | _T_1619; // @[el2_ifu_compress_ctl.scala 187:67]
|
wire _T_1620 = _T_1609 | _T_1619; // @[el2_ifu_compress_ctl.scala 183:67]
|
||||||
wire _T_1628 = _T_1407 & io_din[3]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1628 = _T_1407 & io_din[3]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1629 = _T_1628 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1629 = _T_1628 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1632 = _T_1629 & _T_147; // @[el2_ifu_compress_ctl.scala 188:28]
|
wire _T_1632 = _T_1629 & _T_147; // @[el2_ifu_compress_ctl.scala 184:28]
|
||||||
wire _T_1633 = _T_1620 | _T_1632; // @[el2_ifu_compress_ctl.scala 187:93]
|
wire _T_1633 = _T_1620 | _T_1632; // @[el2_ifu_compress_ctl.scala 183:93]
|
||||||
wire _T_1639 = io_din[13] & io_din[4]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1639 = io_din[13] & io_din[4]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1640 = _T_1639 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1640 = _T_1639 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1641 = _T_1640 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1641 = _T_1640 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1642 = _T_1633 | _T_1641; // @[el2_ifu_compress_ctl.scala 188:43]
|
wire _T_1642 = _T_1633 | _T_1641; // @[el2_ifu_compress_ctl.scala 184:43]
|
||||||
wire _T_1650 = _T_1407 & io_din[2]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1650 = _T_1407 & io_din[2]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1651 = _T_1650 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1651 = _T_1650 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1654 = _T_1651 & _T_147; // @[el2_ifu_compress_ctl.scala 188:91]
|
wire _T_1654 = _T_1651 & _T_147; // @[el2_ifu_compress_ctl.scala 184:91]
|
||||||
wire _T_1655 = _T_1642 | _T_1654; // @[el2_ifu_compress_ctl.scala 188:66]
|
wire _T_1655 = _T_1642 | _T_1654; // @[el2_ifu_compress_ctl.scala 184:66]
|
||||||
wire _T_1664 = _T_642 & io_din[7]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1664 = _T_642 & io_din[7]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1665 = _T_1664 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1665 = _T_1664 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1666 = _T_1655 | _T_1665; // @[el2_ifu_compress_ctl.scala 188:106]
|
wire _T_1666 = _T_1655 | _T_1665; // @[el2_ifu_compress_ctl.scala 184:106]
|
||||||
wire _T_1672 = io_din[13] & io_din[3]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1672 = io_din[13] & io_din[3]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1673 = _T_1672 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1673 = _T_1672 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1674 = _T_1673 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1674 = _T_1673 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1675 = _T_1666 | _T_1674; // @[el2_ifu_compress_ctl.scala 189:29]
|
wire _T_1675 = _T_1666 | _T_1674; // @[el2_ifu_compress_ctl.scala 185:29]
|
||||||
wire _T_1681 = io_din[13] & io_din[2]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1681 = io_din[13] & io_din[2]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1682 = _T_1681 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1682 = _T_1681 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1683 = _T_1682 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1683 = _T_1682 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1684 = _T_1675 | _T_1683; // @[el2_ifu_compress_ctl.scala 189:52]
|
wire _T_1684 = _T_1675 | _T_1683; // @[el2_ifu_compress_ctl.scala 185:52]
|
||||||
wire _T_1690 = io_din[14] & _T_4; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1690 = io_din[14] & _T_4; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1691 = _T_1690 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1691 = _T_1690 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1692 = _T_1684 | _T_1691; // @[el2_ifu_compress_ctl.scala 189:75]
|
wire _T_1692 = _T_1684 | _T_1691; // @[el2_ifu_compress_ctl.scala 185:75]
|
||||||
wire _T_1701 = _T_703 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1701 = _T_703 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1702 = _T_1701 & io_din[0]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1702 = _T_1701 & io_din[0]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1703 = _T_1692 | _T_1702; // @[el2_ifu_compress_ctl.scala 189:98]
|
wire _T_1703 = _T_1692 | _T_1702; // @[el2_ifu_compress_ctl.scala 185:98]
|
||||||
wire _T_1710 = _T_820 & io_din[12]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1710 = _T_820 & io_din[12]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1711 = _T_1710 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1711 = _T_1710 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1714 = _T_1711 & _T_147; // @[el2_ifu_compress_ctl.scala 190:54]
|
wire _T_1714 = _T_1711 & _T_147; // @[el2_ifu_compress_ctl.scala 186:54]
|
||||||
wire _T_1715 = _T_1703 | _T_1714; // @[el2_ifu_compress_ctl.scala 190:29]
|
wire _T_1715 = _T_1703 | _T_1714; // @[el2_ifu_compress_ctl.scala 186:29]
|
||||||
wire _T_1724 = _T_642 & _T_487; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1724 = _T_642 & _T_487; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1725 = _T_1724 & io_din[1]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1725 = _T_1724 & io_din[1]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1728 = _T_1725 & _T_147; // @[el2_ifu_compress_ctl.scala 190:96]
|
wire _T_1728 = _T_1725 & _T_147; // @[el2_ifu_compress_ctl.scala 186:96]
|
||||||
wire _T_1729 = _T_1715 | _T_1728; // @[el2_ifu_compress_ctl.scala 190:69]
|
wire _T_1729 = _T_1715 | _T_1728; // @[el2_ifu_compress_ctl.scala 186:69]
|
||||||
wire _T_1738 = _T_642 & io_din[12]; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1738 = _T_642 & io_din[12]; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1739 = _T_1738 & _T_830; // @[el2_ifu_compress_ctl.scala 33:110]
|
wire _T_1739 = _T_1738 & _T_830; // @[el2_ifu_compress_ctl.scala 28:110]
|
||||||
wire _T_1740 = _T_1729 | _T_1739; // @[el2_ifu_compress_ctl.scala 190:111]
|
wire _T_1740 = _T_1729 | _T_1739; // @[el2_ifu_compress_ctl.scala 186:111]
|
||||||
wire _T_1747 = _T_1690 & _T_147; // @[el2_ifu_compress_ctl.scala 191:50]
|
wire _T_1747 = _T_1690 & _T_147; // @[el2_ifu_compress_ctl.scala 187:50]
|
||||||
wire legal = _T_1740 | _T_1747; // @[el2_ifu_compress_ctl.scala 191:30]
|
wire legal = _T_1740 | _T_1747; // @[el2_ifu_compress_ctl.scala 187:30]
|
||||||
wire [31:0] _T_1749 = legal ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
wire [31:0] _T_1749 = legal ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [9:0] _T_1759 = {1'h0,out_30,1'h0,1'h0,1'h0,1'h0,1'h0,1'h0,1'h0,1'h0}; // @[Cat.scala 29:58]
|
wire [9:0] _T_1759 = {1'h0,out_30,1'h0,1'h0,1'h0,1'h0,1'h0,1'h0,1'h0,1'h0}; // @[Cat.scala 29:58]
|
||||||
wire [18:0] _T_1768 = {_T_1759,1'h0,out_20,1'h0,1'h0,1'h0,1'h0,1'h0,out_14,out_13}; // @[Cat.scala 29:58]
|
wire [18:0] _T_1768 = {_T_1759,1'h0,out_20,1'h0,1'h0,1'h0,1'h0,1'h0,out_14,out_13}; // @[Cat.scala 29:58]
|
||||||
wire [27:0] _T_1777 = {_T_1768,out_12,1'h0,1'h0,1'h0,1'h0,1'h0,out_6,out_5,out_4}; // @[Cat.scala 29:58]
|
wire [27:0] _T_1777 = {_T_1768,out_12,1'h0,1'h0,1'h0,1'h0,1'h0,out_6,out_5,out_4}; // @[Cat.scala 29:58]
|
||||||
wire [30:0] _T_1780 = {_T_1777,_T_228,out_2,1'h1}; // @[Cat.scala 29:58]
|
wire [30:0] _T_1780 = {_T_1777,_T_228,out_2,1'h1}; // @[Cat.scala 29:58]
|
||||||
assign io_dout = l3 & _T_1749; // @[el2_ifu_compress_ctl.scala 193:10]
|
assign io_dout = l3 & _T_1749; // @[el2_ifu_compress_ctl.scala 189:10]
|
||||||
assign io_l1 = {_T_1234,_T_1232}; // @[el2_ifu_compress_ctl.scala 194:9]
|
assign io_l1 = {_T_1234,_T_1232}; // @[el2_ifu_compress_ctl.scala 190:9]
|
||||||
assign io_l2 = l2[31:0]; // @[el2_ifu_compress_ctl.scala 195:9]
|
assign io_l2 = l2[31:0]; // @[el2_ifu_compress_ctl.scala 191:9]
|
||||||
assign io_l3 = {_T_1400,_T_1399}; // @[el2_ifu_compress_ctl.scala 196:9]
|
assign io_l3 = {_T_1400,_T_1399}; // @[el2_ifu_compress_ctl.scala 192:9]
|
||||||
assign io_legal = _T_1740 | _T_1747; // @[el2_ifu_compress_ctl.scala 197:12]
|
assign io_legal = _T_1740 | _T_1747; // @[el2_ifu_compress_ctl.scala 193:12]
|
||||||
assign io_o = {_T_1780,1'h1}; // @[el2_ifu_compress_ctl.scala 198:8]
|
assign io_o = {_T_1780,1'h1}; // @[el2_ifu_compress_ctl.scala 194:8]
|
||||||
assign io_sluimmd = {_T_1281,rs2d}; // @[el2_ifu_compress_ctl.scala 154:14]
|
assign io_sluimmd = {_T_1281,rs2d}; // @[el2_ifu_compress_ctl.scala 149:14]
|
||||||
assign io_uimm5d = {io_din[12],rs2d}; // @[el2_ifu_compress_ctl.scala 208:13]
|
assign io_uimm5d = {io_din[12],rs2d}; // @[el2_ifu_compress_ctl.scala 204:13]
|
||||||
assign io_ulwspimm7d = {_T_1258,io_din[6:4]}; // @[el2_ifu_compress_ctl.scala 209:17]
|
assign io_ulwspimm7d = {_T_1258,io_din[6:4]}; // @[el2_ifu_compress_ctl.scala 205:17]
|
||||||
assign io_ulwimm6d = {_T_1254,io_din[6]}; // @[el2_ifu_compress_ctl.scala 210:15]
|
assign io_ulwimm6d = {_T_1254,io_din[6]}; // @[el2_ifu_compress_ctl.scala 206:15]
|
||||||
assign io_simm9d = {_T_1250,_T_1248}; // @[el2_ifu_compress_ctl.scala 211:13]
|
assign io_simm9d = {_T_1250,_T_1248}; // @[el2_ifu_compress_ctl.scala 207:13]
|
||||||
assign io_uimm9d = {_T_1242,_T_1241}; // @[el2_ifu_compress_ctl.scala 212:13]
|
assign io_uimm9d = {_T_1242,_T_1241}; // @[el2_ifu_compress_ctl.scala 208:13]
|
||||||
assign io_simm5d = {io_din[12],rs2d}; // @[el2_ifu_compress_ctl.scala 213:13]
|
assign io_simm5d = {io_din[12],rs2d}; // @[el2_ifu_compress_ctl.scala 209:13]
|
||||||
|
assign io_sjald = {sjald_12,sjald_1}; // @[el2_ifu_compress_ctl.scala 203:12]
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -1,18 +1,40 @@
|
||||||
[
|
[
|
||||||
{
|
{
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_test_out",
|
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
|
||||||
"sources":[
|
"sources":[
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_next_addr_bf",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_btb_addr_bf",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_last_addr_bf",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_next_addr_bf",
|
||||||
|
"sources":[
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_btb_addr_bf",
|
||||||
|
"sources":[
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final"
|
||||||
|
]
|
||||||
|
},
|
||||||
{
|
{
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_pmu_fetch_stall",
|
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_pmu_fetch_stall",
|
||||||
|
|
@ -24,33 +46,6 @@
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_fb_consume1"
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_fb_consume1"
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
|
|
||||||
"sources":[
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
|
||||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_iccm_access_bf",
|
|
||||||
"sources":[
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
{
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_bf",
|
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_bf",
|
||||||
|
|
@ -66,6 +61,15 @@
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f"
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f"
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_last_addr_bf",
|
||||||
|
"sources":[
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f"
|
||||||
|
]
|
||||||
|
},
|
||||||
{
|
{
|
||||||
"class":"firrtl.transforms.CombinationalPath",
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_uncacheable_bf",
|
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_uncacheable_bf",
|
||||||
|
|
@ -73,9 +77,29 @@
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_dec_tlu_mrac_ff",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_dec_tlu_mrac_ff",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_next_addr_bf",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_btb_addr_bf",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_last_addr_bf",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_iccm_access_bf",
|
||||||
|
"sources":[
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_next_addr_bf",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_btb_addr_bf",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
|
||||||
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_sel_last_addr_bf",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
|
||||||
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
|
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
|
||||||
|
|
|
||||||
|
|
@ -3,10 +3,10 @@ circuit el2_ifu_ifc_ctrl :
|
||||||
module el2_ifu_ifc_ctrl :
|
module el2_ifu_ifc_ctrl :
|
||||||
input clock : Clock
|
input clock : Clock
|
||||||
input reset : UInt<1>
|
input reset : UInt<1>
|
||||||
output io : {flip free_clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>, test_out : UInt}
|
output io : {flip free_clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>, sel_last_addr_bf : UInt<1>, sel_btb_addr_bf : UInt<1>, sel_next_addr_bf : UInt<1>}
|
||||||
|
|
||||||
io.ifc_region_acc_fault_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 40:30]
|
io.ifc_region_acc_fault_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 42:30]
|
||||||
io.ifc_dma_access_ok <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 41:24]
|
io.ifc_dma_access_ok <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 43:24]
|
||||||
wire fetch_addr_bf : UInt<32>
|
wire fetch_addr_bf : UInt<32>
|
||||||
fetch_addr_bf <= UInt<1>("h00")
|
fetch_addr_bf <= UInt<1>("h00")
|
||||||
wire fetch_addr_next : UInt<32>
|
wire fetch_addr_next : UInt<32>
|
||||||
|
|
@ -27,12 +27,6 @@ circuit el2_ifu_ifc_ctrl :
|
||||||
wfm <= UInt<1>("h00")
|
wfm <= UInt<1>("h00")
|
||||||
wire idle : UInt<1>
|
wire idle : UInt<1>
|
||||||
idle <= UInt<1>("h00")
|
idle <= UInt<1>("h00")
|
||||||
wire sel_last_addr_bf : UInt<1>
|
|
||||||
sel_last_addr_bf <= UInt<1>("h00")
|
|
||||||
wire sel_btb_addr_bf : UInt<1>
|
|
||||||
sel_btb_addr_bf <= UInt<1>("h00")
|
|
||||||
wire sel_next_addr_bf : UInt<1>
|
|
||||||
sel_next_addr_bf <= UInt<1>("h00")
|
|
||||||
wire miss_f : UInt<1>
|
wire miss_f : UInt<1>
|
||||||
miss_f <= UInt<1>("h00")
|
miss_f <= UInt<1>("h00")
|
||||||
wire miss_a : UInt<1>
|
wire miss_a : UInt<1>
|
||||||
|
|
@ -53,34 +47,34 @@ circuit el2_ifu_ifc_ctrl :
|
||||||
state <= UInt<1>("h00")
|
state <= UInt<1>("h00")
|
||||||
wire dma_iccm_stall_any_f : UInt<1>
|
wire dma_iccm_stall_any_f : UInt<1>
|
||||||
dma_iccm_stall_any_f <= UInt<1>("h00")
|
dma_iccm_stall_any_f <= UInt<1>("h00")
|
||||||
node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctrl.scala 69:36]
|
node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctrl.scala 71:36]
|
||||||
reg _T : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 70:34]
|
reg _T : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 72:34]
|
||||||
_T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctrl.scala 70:34]
|
_T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctrl.scala 72:34]
|
||||||
dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctrl.scala 70:24]
|
dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctrl.scala 72:24]
|
||||||
reg _T_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 72:20]
|
reg _T_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 74:20]
|
||||||
_T_1 <= miss_f @[el2_ifu_ifc_ctrl.scala 72:20]
|
_T_1 <= miss_f @[el2_ifu_ifc_ctrl.scala 74:20]
|
||||||
miss_a <= _T_1 @[el2_ifu_ifc_ctrl.scala 72:10]
|
miss_a <= _T_1 @[el2_ifu_ifc_ctrl.scala 74:10]
|
||||||
node _T_2 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 74:23]
|
node _T_2 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 76:26]
|
||||||
node _T_3 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 74:46]
|
node _T_3 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 76:49]
|
||||||
node _T_4 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 74:68]
|
node _T_4 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 76:71]
|
||||||
node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctrl.scala 74:66]
|
node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctrl.scala 76:69]
|
||||||
node _T_6 = and(_T_2, _T_5) @[el2_ifu_ifc_ctrl.scala 74:43]
|
node _T_6 = and(_T_2, _T_5) @[el2_ifu_ifc_ctrl.scala 76:46]
|
||||||
sel_last_addr_bf <= _T_6 @[el2_ifu_ifc_ctrl.scala 74:20]
|
io.sel_last_addr_bf <= _T_6 @[el2_ifu_ifc_ctrl.scala 76:23]
|
||||||
node _T_7 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 75:23]
|
node _T_7 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 77:26]
|
||||||
node _T_8 = and(_T_7, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 75:43]
|
node _T_8 = and(_T_7, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 77:46]
|
||||||
node _T_9 = and(_T_8, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 75:64]
|
node _T_9 = and(_T_8, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 77:67]
|
||||||
node _T_10 = and(_T_9, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 75:88]
|
node _T_10 = and(_T_9, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 77:91]
|
||||||
sel_btb_addr_bf <= _T_10 @[el2_ifu_ifc_ctrl.scala 75:20]
|
io.sel_btb_addr_bf <= _T_10 @[el2_ifu_ifc_ctrl.scala 77:23]
|
||||||
node _T_11 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 76:23]
|
node _T_11 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 78:26]
|
||||||
node _T_12 = and(_T_11, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 76:43]
|
node _T_12 = and(_T_11, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 78:46]
|
||||||
node _T_13 = not(io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 76:66]
|
node _T_13 = not(io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 78:69]
|
||||||
node _T_14 = and(_T_12, _T_13) @[el2_ifu_ifc_ctrl.scala 76:64]
|
node _T_14 = and(_T_12, _T_13) @[el2_ifu_ifc_ctrl.scala 78:67]
|
||||||
node _T_15 = and(_T_14, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 76:89]
|
node _T_15 = and(_T_14, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 78:92]
|
||||||
sel_next_addr_bf <= _T_15 @[el2_ifu_ifc_ctrl.scala 76:20]
|
io.sel_next_addr_bf <= _T_15 @[el2_ifu_ifc_ctrl.scala 78:23]
|
||||||
node _T_16 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctrl.scala 79:56]
|
node _T_16 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctrl.scala 81:56]
|
||||||
node _T_17 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 80:46]
|
node _T_17 = bits(io.sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 82:49]
|
||||||
node _T_18 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 81:45]
|
node _T_18 = bits(io.sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 83:48]
|
||||||
node _T_19 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 82:46]
|
node _T_19 = bits(io.sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 84:49]
|
||||||
node _T_20 = mux(_T_16, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
|
node _T_20 = mux(_T_16, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
node _T_21 = mux(_T_17, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
node _T_21 = mux(_T_17, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
node _T_22 = mux(_T_18, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
node _T_22 = mux(_T_18, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
|
|
@ -90,17 +84,16 @@ circuit el2_ifu_ifc_ctrl :
|
||||||
node _T_26 = or(_T_25, _T_23) @[Mux.scala 27:72]
|
node _T_26 = or(_T_25, _T_23) @[Mux.scala 27:72]
|
||||||
wire _T_27 : UInt<32> @[Mux.scala 27:72]
|
wire _T_27 : UInt<32> @[Mux.scala 27:72]
|
||||||
_T_27 <= _T_26 @[Mux.scala 27:72]
|
_T_27 <= _T_26 @[Mux.scala 27:72]
|
||||||
io.ifc_fetch_addr_bf <= _T_27 @[el2_ifu_ifc_ctrl.scala 79:24]
|
io.ifc_fetch_addr_bf <= _T_27 @[el2_ifu_ifc_ctrl.scala 81:24]
|
||||||
io.test_out <= io.ifc_fetch_addr_bf @[el2_ifu_ifc_ctrl.scala 84:15]
|
line_wrap <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 88:13]
|
||||||
line_wrap <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 86:13]
|
node _T_28 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctrl.scala 90:46]
|
||||||
node _T_28 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctrl.scala 88:46]
|
node _T_29 = add(_T_28, UInt<1>("h01")) @[el2_ifu_ifc_ctrl.scala 90:52]
|
||||||
node _T_29 = add(_T_28, UInt<1>("h01")) @[el2_ifu_ifc_ctrl.scala 88:52]
|
node _T_30 = tail(_T_29, 1) @[el2_ifu_ifc_ctrl.scala 90:52]
|
||||||
node _T_30 = tail(_T_29, 1) @[el2_ifu_ifc_ctrl.scala 88:52]
|
node _T_31 = bits(line_wrap, 0, 0) @[el2_ifu_ifc_ctrl.scala 91:25]
|
||||||
node _T_31 = bits(line_wrap, 0, 0) @[el2_ifu_ifc_ctrl.scala 89:25]
|
node _T_32 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctrl.scala 91:53]
|
||||||
node _T_32 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctrl.scala 89:53]
|
node _T_33 = mux(_T_31, UInt<1>("h00"), _T_32) @[el2_ifu_ifc_ctrl.scala 91:8]
|
||||||
node _T_33 = mux(_T_31, UInt<1>("h00"), _T_32) @[el2_ifu_ifc_ctrl.scala 89:8]
|
node _T_34 = or(_T_30, _T_33) @[el2_ifu_ifc_ctrl.scala 90:58]
|
||||||
node _T_34 = or(_T_30, _T_33) @[el2_ifu_ifc_ctrl.scala 88:58]
|
fetch_addr_next <= _T_34 @[el2_ifu_ifc_ctrl.scala 90:19]
|
||||||
fetch_addr_next <= _T_34 @[el2_ifu_ifc_ctrl.scala 88:19]
|
|
||||||
node _T_35 = not(idle) @[el2_ifu_ifc_ctrl.scala 93:30]
|
node _T_35 = not(idle) @[el2_ifu_ifc_ctrl.scala 93:30]
|
||||||
io.ifc_fetch_req_bf_raw <= _T_35 @[el2_ifu_ifc_ctrl.scala 93:27]
|
io.ifc_fetch_req_bf_raw <= _T_35 @[el2_ifu_ifc_ctrl.scala 93:27]
|
||||||
node _T_36 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 95:91]
|
node _T_36 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 95:91]
|
||||||
|
|
@ -159,50 +152,50 @@ circuit el2_ifu_ifc_ctrl :
|
||||||
reg _T_81 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 113:19]
|
reg _T_81 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 113:19]
|
||||||
_T_81 <= _T_80 @[el2_ifu_ifc_ctrl.scala 113:19]
|
_T_81 <= _T_80 @[el2_ifu_ifc_ctrl.scala 113:19]
|
||||||
state <= _T_81 @[el2_ifu_ifc_ctrl.scala 113:9]
|
state <= _T_81 @[el2_ifu_ifc_ctrl.scala 113:9]
|
||||||
flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctrl.scala 119:12]
|
flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctrl.scala 118:12]
|
||||||
node _T_82 = not(io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 121:38]
|
node _T_82 = not(io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 120:38]
|
||||||
node _T_83 = and(io.ifu_fb_consume1, _T_82) @[el2_ifu_ifc_ctrl.scala 121:36]
|
node _T_83 = and(io.ifu_fb_consume1, _T_82) @[el2_ifu_ifc_ctrl.scala 120:36]
|
||||||
node _T_84 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 121:61]
|
node _T_84 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 120:61]
|
||||||
node _T_85 = or(_T_84, miss_f) @[el2_ifu_ifc_ctrl.scala 121:81]
|
node _T_85 = or(_T_84, miss_f) @[el2_ifu_ifc_ctrl.scala 120:81]
|
||||||
node _T_86 = and(_T_83, _T_85) @[el2_ifu_ifc_ctrl.scala 121:58]
|
node _T_86 = and(_T_83, _T_85) @[el2_ifu_ifc_ctrl.scala 120:58]
|
||||||
node _T_87 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 122:25]
|
node _T_87 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 121:25]
|
||||||
node _T_88 = or(_T_86, _T_87) @[el2_ifu_ifc_ctrl.scala 121:92]
|
node _T_88 = or(_T_86, _T_87) @[el2_ifu_ifc_ctrl.scala 120:92]
|
||||||
fb_right <= _T_88 @[el2_ifu_ifc_ctrl.scala 121:12]
|
fb_right <= _T_88 @[el2_ifu_ifc_ctrl.scala 120:12]
|
||||||
node _T_89 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 124:39]
|
node _T_89 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 123:39]
|
||||||
node _T_90 = or(_T_89, miss_f) @[el2_ifu_ifc_ctrl.scala 124:59]
|
node _T_90 = or(_T_89, miss_f) @[el2_ifu_ifc_ctrl.scala 123:59]
|
||||||
node _T_91 = and(io.ifu_fb_consume2, _T_90) @[el2_ifu_ifc_ctrl.scala 124:36]
|
node _T_91 = and(io.ifu_fb_consume2, _T_90) @[el2_ifu_ifc_ctrl.scala 123:36]
|
||||||
fb_right2 <= _T_91 @[el2_ifu_ifc_ctrl.scala 124:13]
|
fb_right2 <= _T_91 @[el2_ifu_ifc_ctrl.scala 123:13]
|
||||||
node _T_92 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 125:56]
|
node _T_92 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 124:56]
|
||||||
node _T_93 = not(_T_92) @[el2_ifu_ifc_ctrl.scala 125:35]
|
node _T_93 = not(_T_92) @[el2_ifu_ifc_ctrl.scala 124:35]
|
||||||
node _T_94 = and(io.ifc_fetch_req_f, _T_93) @[el2_ifu_ifc_ctrl.scala 125:33]
|
node _T_94 = and(io.ifc_fetch_req_f, _T_93) @[el2_ifu_ifc_ctrl.scala 124:33]
|
||||||
node _T_95 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 125:80]
|
node _T_95 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 124:80]
|
||||||
node _T_96 = and(_T_94, _T_95) @[el2_ifu_ifc_ctrl.scala 125:78]
|
node _T_96 = and(_T_94, _T_95) @[el2_ifu_ifc_ctrl.scala 124:78]
|
||||||
fb_left <= _T_96 @[el2_ifu_ifc_ctrl.scala 125:11]
|
fb_left <= _T_96 @[el2_ifu_ifc_ctrl.scala 124:11]
|
||||||
node _T_97 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctrl.scala 127:37]
|
node _T_97 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctrl.scala 126:37]
|
||||||
node _T_98 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 128:6]
|
node _T_98 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 127:6]
|
||||||
node _T_99 = and(_T_98, fb_right) @[el2_ifu_ifc_ctrl.scala 128:16]
|
node _T_99 = and(_T_98, fb_right) @[el2_ifu_ifc_ctrl.scala 127:16]
|
||||||
node _T_100 = bits(_T_99, 0, 0) @[el2_ifu_ifc_ctrl.scala 128:28]
|
node _T_100 = bits(_T_99, 0, 0) @[el2_ifu_ifc_ctrl.scala 127:28]
|
||||||
node _T_101 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctrl.scala 128:62]
|
node _T_101 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctrl.scala 127:62]
|
||||||
node _T_102 = cat(UInt<1>("h00"), _T_101) @[Cat.scala 29:58]
|
node _T_102 = cat(UInt<1>("h00"), _T_101) @[Cat.scala 29:58]
|
||||||
node _T_103 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 129:6]
|
node _T_103 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 128:6]
|
||||||
node _T_104 = and(_T_103, fb_right2) @[el2_ifu_ifc_ctrl.scala 129:16]
|
node _T_104 = and(_T_103, fb_right2) @[el2_ifu_ifc_ctrl.scala 128:16]
|
||||||
node _T_105 = bits(_T_104, 0, 0) @[el2_ifu_ifc_ctrl.scala 129:29]
|
node _T_105 = bits(_T_104, 0, 0) @[el2_ifu_ifc_ctrl.scala 128:29]
|
||||||
node _T_106 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctrl.scala 129:63]
|
node _T_106 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctrl.scala 128:63]
|
||||||
node _T_107 = cat(UInt<2>("h00"), _T_106) @[Cat.scala 29:58]
|
node _T_107 = cat(UInt<2>("h00"), _T_106) @[Cat.scala 29:58]
|
||||||
node _T_108 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 130:6]
|
node _T_108 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 129:6]
|
||||||
node _T_109 = and(_T_108, fb_left) @[el2_ifu_ifc_ctrl.scala 130:16]
|
node _T_109 = and(_T_108, fb_left) @[el2_ifu_ifc_ctrl.scala 129:16]
|
||||||
node _T_110 = bits(_T_109, 0, 0) @[el2_ifu_ifc_ctrl.scala 130:27]
|
node _T_110 = bits(_T_109, 0, 0) @[el2_ifu_ifc_ctrl.scala 129:27]
|
||||||
node _T_111 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctrl.scala 130:51]
|
node _T_111 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctrl.scala 129:51]
|
||||||
node _T_112 = cat(_T_111, UInt<1>("h00")) @[Cat.scala 29:58]
|
node _T_112 = cat(_T_111, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||||
node _T_113 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 131:6]
|
node _T_113 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 130:6]
|
||||||
node _T_114 = not(fb_right) @[el2_ifu_ifc_ctrl.scala 131:18]
|
node _T_114 = not(fb_right) @[el2_ifu_ifc_ctrl.scala 130:18]
|
||||||
node _T_115 = and(_T_113, _T_114) @[el2_ifu_ifc_ctrl.scala 131:16]
|
node _T_115 = and(_T_113, _T_114) @[el2_ifu_ifc_ctrl.scala 130:16]
|
||||||
node _T_116 = not(fb_right2) @[el2_ifu_ifc_ctrl.scala 131:30]
|
node _T_116 = not(fb_right2) @[el2_ifu_ifc_ctrl.scala 130:30]
|
||||||
node _T_117 = and(_T_115, _T_116) @[el2_ifu_ifc_ctrl.scala 131:28]
|
node _T_117 = and(_T_115, _T_116) @[el2_ifu_ifc_ctrl.scala 130:28]
|
||||||
node _T_118 = not(fb_left) @[el2_ifu_ifc_ctrl.scala 131:43]
|
node _T_118 = not(fb_left) @[el2_ifu_ifc_ctrl.scala 130:43]
|
||||||
node _T_119 = and(_T_117, _T_118) @[el2_ifu_ifc_ctrl.scala 131:41]
|
node _T_119 = and(_T_117, _T_118) @[el2_ifu_ifc_ctrl.scala 130:41]
|
||||||
node _T_120 = bits(_T_119, 0, 0) @[el2_ifu_ifc_ctrl.scala 131:53]
|
node _T_120 = bits(_T_119, 0, 0) @[el2_ifu_ifc_ctrl.scala 130:53]
|
||||||
node _T_121 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctrl.scala 131:73]
|
node _T_121 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctrl.scala 130:73]
|
||||||
node _T_122 = mux(_T_97, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
node _T_122 = mux(_T_97, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
node _T_123 = mux(_T_100, _T_102, UInt<1>("h00")) @[Mux.scala 27:72]
|
node _T_123 = mux(_T_100, _T_102, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
node _T_124 = mux(_T_105, _T_107, UInt<1>("h00")) @[Mux.scala 27:72]
|
node _T_124 = mux(_T_105, _T_107, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
|
|
@ -214,49 +207,49 @@ circuit el2_ifu_ifc_ctrl :
|
||||||
node _T_130 = or(_T_129, _T_126) @[Mux.scala 27:72]
|
node _T_130 = or(_T_129, _T_126) @[Mux.scala 27:72]
|
||||||
wire _T_131 : UInt<4> @[Mux.scala 27:72]
|
wire _T_131 : UInt<4> @[Mux.scala 27:72]
|
||||||
_T_131 <= _T_130 @[Mux.scala 27:72]
|
_T_131 <= _T_130 @[Mux.scala 27:72]
|
||||||
fb_write_ns <= _T_131 @[el2_ifu_ifc_ctrl.scala 127:15]
|
fb_write_ns <= _T_131 @[el2_ifu_ifc_ctrl.scala 126:15]
|
||||||
node _T_132 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 134:38]
|
node _T_132 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 133:38]
|
||||||
reg _T_133 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 134:26]
|
reg _T_133 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 133:26]
|
||||||
_T_133 <= _T_132 @[el2_ifu_ifc_ctrl.scala 134:26]
|
_T_133 <= _T_132 @[el2_ifu_ifc_ctrl.scala 133:26]
|
||||||
fb_full_f_ns <= _T_133 @[el2_ifu_ifc_ctrl.scala 134:16]
|
fb_full_f_ns <= _T_133 @[el2_ifu_ifc_ctrl.scala 133:16]
|
||||||
node _T_134 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctrl.scala 136:17]
|
node _T_134 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctrl.scala 135:17]
|
||||||
idle <= _T_134 @[el2_ifu_ifc_ctrl.scala 136:8]
|
idle <= _T_134 @[el2_ifu_ifc_ctrl.scala 135:8]
|
||||||
node _T_135 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctrl.scala 137:16]
|
node _T_135 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctrl.scala 136:16]
|
||||||
wfm <= _T_135 @[el2_ifu_ifc_ctrl.scala 137:7]
|
wfm <= _T_135 @[el2_ifu_ifc_ctrl.scala 136:7]
|
||||||
node _T_136 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 139:30]
|
node _T_136 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 138:30]
|
||||||
fb_full_f_ns <= _T_136 @[el2_ifu_ifc_ctrl.scala 139:16]
|
fb_full_f_ns <= _T_136 @[el2_ifu_ifc_ctrl.scala 138:16]
|
||||||
reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 140:26]
|
reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 139:26]
|
||||||
fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctrl.scala 140:26]
|
fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctrl.scala 139:26]
|
||||||
reg _T_137 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 141:24]
|
reg _T_137 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 140:24]
|
||||||
_T_137 <= fb_write_ns @[el2_ifu_ifc_ctrl.scala 141:24]
|
_T_137 <= fb_write_ns @[el2_ifu_ifc_ctrl.scala 140:24]
|
||||||
fb_write_f <= _T_137 @[el2_ifu_ifc_ctrl.scala 141:14]
|
fb_write_f <= _T_137 @[el2_ifu_ifc_ctrl.scala 140:14]
|
||||||
node _T_138 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 144:26]
|
node _T_138 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 143:26]
|
||||||
node _T_139 = or(_T_138, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 144:47]
|
node _T_139 = or(_T_138, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 143:47]
|
||||||
node _T_140 = not(_T_139) @[el2_ifu_ifc_ctrl.scala 144:5]
|
node _T_140 = not(_T_139) @[el2_ifu_ifc_ctrl.scala 143:5]
|
||||||
node _T_141 = and(fb_full_f, _T_140) @[el2_ifu_ifc_ctrl.scala 143:75]
|
node _T_141 = and(fb_full_f, _T_140) @[el2_ifu_ifc_ctrl.scala 142:75]
|
||||||
node _T_142 = or(_T_141, dma_stall) @[el2_ifu_ifc_ctrl.scala 144:70]
|
node _T_142 = or(_T_141, dma_stall) @[el2_ifu_ifc_ctrl.scala 143:70]
|
||||||
node _T_143 = and(io.ifc_fetch_req_bf_raw, _T_142) @[el2_ifu_ifc_ctrl.scala 143:60]
|
node _T_143 = and(io.ifc_fetch_req_bf_raw, _T_142) @[el2_ifu_ifc_ctrl.scala 142:60]
|
||||||
node _T_144 = or(wfm, _T_143) @[el2_ifu_ifc_ctrl.scala 143:33]
|
node _T_144 = or(wfm, _T_143) @[el2_ifu_ifc_ctrl.scala 142:33]
|
||||||
io.ifu_pmu_fetch_stall <= _T_144 @[el2_ifu_ifc_ctrl.scala 143:26]
|
io.ifu_pmu_fetch_stall <= _T_144 @[el2_ifu_ifc_ctrl.scala 142:26]
|
||||||
node _T_145 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
node _T_145 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||||
node _T_146 = bits(_T_145, 31, 28) @[el2_lib.scala 204:25]
|
node _T_146 = bits(_T_145, 31, 28) @[el2_lib.scala 214:25]
|
||||||
node iccm_acc_in_region_bf = eq(_T_146, UInt<4>("h0e")) @[el2_lib.scala 204:47]
|
node iccm_acc_in_region_bf = eq(_T_146, UInt<4>("h0e")) @[el2_lib.scala 214:47]
|
||||||
node _T_147 = bits(_T_145, 31, 16) @[el2_lib.scala 207:14]
|
node _T_147 = bits(_T_145, 31, 16) @[el2_lib.scala 217:14]
|
||||||
node iccm_acc_in_range_bf = eq(_T_147, UInt<16>("h0ee00")) @[el2_lib.scala 207:29]
|
node iccm_acc_in_range_bf = eq(_T_147, UInt<16>("h0ee00")) @[el2_lib.scala 217:29]
|
||||||
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctrl.scala 150:25]
|
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctrl.scala 149:25]
|
||||||
node _T_148 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctrl.scala 151:78]
|
node _T_148 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctrl.scala 150:78]
|
||||||
node _T_149 = cat(_T_148, UInt<1>("h00")) @[Cat.scala 29:58]
|
node _T_149 = cat(_T_148, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||||
node _T_150 = dshr(io.dec_tlu_mrac_ff, _T_149) @[el2_ifu_ifc_ctrl.scala 151:53]
|
node _T_150 = dshr(io.dec_tlu_mrac_ff, _T_149) @[el2_ifu_ifc_ctrl.scala 150:53]
|
||||||
node _T_151 = bits(_T_150, 0, 0) @[el2_ifu_ifc_ctrl.scala 151:53]
|
node _T_151 = bits(_T_150, 0, 0) @[el2_ifu_ifc_ctrl.scala 150:53]
|
||||||
node _T_152 = not(_T_151) @[el2_ifu_ifc_ctrl.scala 151:34]
|
node _T_152 = not(_T_151) @[el2_ifu_ifc_ctrl.scala 150:34]
|
||||||
io.ifc_fetch_uncacheable_bf <= _T_152 @[el2_ifu_ifc_ctrl.scala 151:31]
|
io.ifc_fetch_uncacheable_bf <= _T_152 @[el2_ifu_ifc_ctrl.scala 150:31]
|
||||||
reg _T_153 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 155:32]
|
reg _T_153 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 154:32]
|
||||||
_T_153 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctrl.scala 155:32]
|
_T_153 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctrl.scala 154:32]
|
||||||
io.ifc_fetch_req_f <= _T_153 @[el2_ifu_ifc_ctrl.scala 155:22]
|
io.ifc_fetch_req_f <= _T_153 @[el2_ifu_ifc_ctrl.scala 154:22]
|
||||||
node _T_154 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 158:88]
|
node _T_154 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 157:88]
|
||||||
reg _T_155 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
reg _T_155 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||||
when _T_154 : @[Reg.scala 28:19]
|
when _T_154 : @[Reg.scala 28:19]
|
||||||
_T_155 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
|
_T_155 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
|
||||||
skip @[Reg.scala 28:19]
|
skip @[Reg.scala 28:19]
|
||||||
io.ifc_fetch_addr_f <= _T_155 @[el2_ifu_ifc_ctrl.scala 158:23]
|
io.ifc_fetch_addr_f <= _T_155 @[el2_ifu_ifc_ctrl.scala 157:23]
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -28,7 +28,9 @@ module el2_ifu_ifc_ctrl(
|
||||||
output io_ifc_iccm_access_bf,
|
output io_ifc_iccm_access_bf,
|
||||||
output io_ifc_region_acc_fault_bf,
|
output io_ifc_region_acc_fault_bf,
|
||||||
output io_ifc_dma_access_ok,
|
output io_ifc_dma_access_ok,
|
||||||
output [30:0] io_test_out
|
output io_sel_last_addr_bf,
|
||||||
|
output io_sel_btb_addr_bf,
|
||||||
|
output io_sel_next_addr_bf
|
||||||
);
|
);
|
||||||
`ifdef RANDOMIZE_REG_INIT
|
`ifdef RANDOMIZE_REG_INIT
|
||||||
reg [31:0] _RAND_0;
|
reg [31:0] _RAND_0;
|
||||||
|
|
@ -38,72 +40,69 @@ module el2_ifu_ifc_ctrl(
|
||||||
reg [31:0] _RAND_4;
|
reg [31:0] _RAND_4;
|
||||||
reg [31:0] _RAND_5;
|
reg [31:0] _RAND_5;
|
||||||
`endif // RANDOMIZE_REG_INIT
|
`endif // RANDOMIZE_REG_INIT
|
||||||
reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 70:34]
|
reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 72:34]
|
||||||
wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 69:36]
|
wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 71:36]
|
||||||
wire _T_2 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 74:23]
|
wire _T_2 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 76:26]
|
||||||
wire _T_3 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 74:46]
|
wire _T_3 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 76:49]
|
||||||
wire _T_4 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 74:68]
|
wire _T_4 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 76:71]
|
||||||
wire _T_5 = _T_3 | _T_4; // @[el2_ifu_ifc_ctrl.scala 74:66]
|
wire _T_5 = _T_3 | _T_4; // @[el2_ifu_ifc_ctrl.scala 76:69]
|
||||||
wire sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctrl.scala 74:43]
|
wire _T_8 = _T_2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 77:46]
|
||||||
wire _T_8 = _T_2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 75:43]
|
wire _T_9 = _T_8 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 77:67]
|
||||||
wire _T_9 = _T_8 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 75:64]
|
wire _T_13 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 78:69]
|
||||||
wire sel_btb_addr_bf = _T_9 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 75:88]
|
wire _T_14 = _T_8 & _T_13; // @[el2_ifu_ifc_ctrl.scala 78:67]
|
||||||
wire _T_13 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 76:66]
|
|
||||||
wire _T_14 = _T_8 & _T_13; // @[el2_ifu_ifc_ctrl.scala 76:64]
|
|
||||||
wire sel_next_addr_bf = _T_14 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 76:89]
|
|
||||||
wire [30:0] _T_20 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
|
wire [30:0] _T_20 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
|
||||||
wire [30:0] _T_21 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
|
wire [30:0] _T_21 = io_sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
|
||||||
wire [30:0] _T_22 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
|
wire [30:0] _T_22 = io_sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
|
||||||
wire [29:0] _T_30 = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctrl.scala 88:52]
|
wire [29:0] _T_30 = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctrl.scala 90:52]
|
||||||
wire [29:0] _GEN_1 = {{29'd0}, io_ifc_fetch_addr_f[0]}; // @[el2_ifu_ifc_ctrl.scala 88:58]
|
wire [29:0] _GEN_1 = {{29'd0}, io_ifc_fetch_addr_f[0]}; // @[el2_ifu_ifc_ctrl.scala 90:58]
|
||||||
wire [29:0] _T_34 = _T_30 | _GEN_1; // @[el2_ifu_ifc_ctrl.scala 88:58]
|
wire [29:0] _T_34 = _T_30 | _GEN_1; // @[el2_ifu_ifc_ctrl.scala 90:58]
|
||||||
wire [31:0] fetch_addr_next = {{2'd0}, _T_34}; // @[el2_ifu_ifc_ctrl.scala 88:19]
|
wire [31:0] fetch_addr_next = {{2'd0}, _T_34}; // @[el2_ifu_ifc_ctrl.scala 90:19]
|
||||||
wire [31:0] _T_23 = sel_next_addr_bf ? fetch_addr_next : 32'h0; // @[Mux.scala 27:72]
|
wire [31:0] _T_23 = io_sel_next_addr_bf ? fetch_addr_next : 32'h0; // @[Mux.scala 27:72]
|
||||||
wire [30:0] _T_24 = _T_20 | _T_21; // @[Mux.scala 27:72]
|
wire [30:0] _T_24 = _T_20 | _T_21; // @[Mux.scala 27:72]
|
||||||
wire [30:0] _T_25 = _T_24 | _T_22; // @[Mux.scala 27:72]
|
wire [30:0] _T_25 = _T_24 | _T_22; // @[Mux.scala 27:72]
|
||||||
wire [31:0] _GEN_2 = {{1'd0}, _T_25}; // @[Mux.scala 27:72]
|
wire [31:0] _GEN_2 = {{1'd0}, _T_25}; // @[Mux.scala 27:72]
|
||||||
wire [31:0] _T_26 = _GEN_2 | _T_23; // @[Mux.scala 27:72]
|
wire [31:0] _T_26 = _GEN_2 | _T_23; // @[Mux.scala 27:72]
|
||||||
reg [1:0] state; // @[el2_ifu_ifc_ctrl.scala 113:19]
|
reg [1:0] state; // @[el2_ifu_ifc_ctrl.scala 113:19]
|
||||||
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctrl.scala 136:17]
|
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctrl.scala 135:17]
|
||||||
wire _T_36 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctrl.scala 95:91]
|
wire _T_36 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctrl.scala 95:91]
|
||||||
wire _T_37 = ~_T_36; // @[el2_ifu_ifc_ctrl.scala 95:70]
|
wire _T_37 = ~_T_36; // @[el2_ifu_ifc_ctrl.scala 95:70]
|
||||||
wire [3:0] _T_122 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
|
wire [3:0] _T_122 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
|
||||||
wire _T_82 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 121:38]
|
wire _T_82 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 120:38]
|
||||||
wire _T_83 = io_ifu_fb_consume1 & _T_82; // @[el2_ifu_ifc_ctrl.scala 121:36]
|
wire _T_83 = io_ifu_fb_consume1 & _T_82; // @[el2_ifu_ifc_ctrl.scala 120:36]
|
||||||
wire _T_49 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctrl.scala 100:32]
|
wire _T_49 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctrl.scala 100:32]
|
||||||
wire miss_f = _T_49 & _T_2; // @[el2_ifu_ifc_ctrl.scala 100:47]
|
wire miss_f = _T_49 & _T_2; // @[el2_ifu_ifc_ctrl.scala 100:47]
|
||||||
wire _T_85 = _T_3 | miss_f; // @[el2_ifu_ifc_ctrl.scala 121:81]
|
wire _T_85 = _T_3 | miss_f; // @[el2_ifu_ifc_ctrl.scala 120:81]
|
||||||
wire _T_86 = _T_83 & _T_85; // @[el2_ifu_ifc_ctrl.scala 121:58]
|
wire _T_86 = _T_83 & _T_85; // @[el2_ifu_ifc_ctrl.scala 120:58]
|
||||||
wire _T_87 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 122:25]
|
wire _T_87 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 121:25]
|
||||||
wire fb_right = _T_86 | _T_87; // @[el2_ifu_ifc_ctrl.scala 121:92]
|
wire fb_right = _T_86 | _T_87; // @[el2_ifu_ifc_ctrl.scala 120:92]
|
||||||
wire _T_99 = _T_2 & fb_right; // @[el2_ifu_ifc_ctrl.scala 128:16]
|
wire _T_99 = _T_2 & fb_right; // @[el2_ifu_ifc_ctrl.scala 127:16]
|
||||||
reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctrl.scala 141:24]
|
reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctrl.scala 140:24]
|
||||||
wire [3:0] _T_102 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
|
wire [3:0] _T_102 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
|
||||||
wire [3:0] _T_123 = _T_99 ? _T_102 : 4'h0; // @[Mux.scala 27:72]
|
wire [3:0] _T_123 = _T_99 ? _T_102 : 4'h0; // @[Mux.scala 27:72]
|
||||||
wire [3:0] _T_127 = _T_122 | _T_123; // @[Mux.scala 27:72]
|
wire [3:0] _T_127 = _T_122 | _T_123; // @[Mux.scala 27:72]
|
||||||
wire fb_right2 = io_ifu_fb_consume2 & _T_85; // @[el2_ifu_ifc_ctrl.scala 124:36]
|
wire fb_right2 = io_ifu_fb_consume2 & _T_85; // @[el2_ifu_ifc_ctrl.scala 123:36]
|
||||||
wire _T_104 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctrl.scala 129:16]
|
wire _T_104 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctrl.scala 128:16]
|
||||||
wire [3:0] _T_107 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
|
wire [3:0] _T_107 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
|
||||||
wire [3:0] _T_124 = _T_104 ? _T_107 : 4'h0; // @[Mux.scala 27:72]
|
wire [3:0] _T_124 = _T_104 ? _T_107 : 4'h0; // @[Mux.scala 27:72]
|
||||||
wire [3:0] _T_128 = _T_127 | _T_124; // @[Mux.scala 27:72]
|
wire [3:0] _T_128 = _T_127 | _T_124; // @[Mux.scala 27:72]
|
||||||
wire _T_92 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 125:56]
|
wire _T_92 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 124:56]
|
||||||
wire _T_93 = ~_T_92; // @[el2_ifu_ifc_ctrl.scala 125:35]
|
wire _T_93 = ~_T_92; // @[el2_ifu_ifc_ctrl.scala 124:35]
|
||||||
wire _T_94 = io_ifc_fetch_req_f & _T_93; // @[el2_ifu_ifc_ctrl.scala 125:33]
|
wire _T_94 = io_ifc_fetch_req_f & _T_93; // @[el2_ifu_ifc_ctrl.scala 124:33]
|
||||||
wire _T_95 = ~miss_f; // @[el2_ifu_ifc_ctrl.scala 125:80]
|
wire _T_95 = ~miss_f; // @[el2_ifu_ifc_ctrl.scala 124:80]
|
||||||
wire fb_left = _T_94 & _T_95; // @[el2_ifu_ifc_ctrl.scala 125:78]
|
wire fb_left = _T_94 & _T_95; // @[el2_ifu_ifc_ctrl.scala 124:78]
|
||||||
wire _T_109 = _T_2 & fb_left; // @[el2_ifu_ifc_ctrl.scala 130:16]
|
wire _T_109 = _T_2 & fb_left; // @[el2_ifu_ifc_ctrl.scala 129:16]
|
||||||
wire [3:0] _T_112 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
|
wire [3:0] _T_112 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
|
||||||
wire [3:0] _T_125 = _T_109 ? _T_112 : 4'h0; // @[Mux.scala 27:72]
|
wire [3:0] _T_125 = _T_109 ? _T_112 : 4'h0; // @[Mux.scala 27:72]
|
||||||
wire [3:0] _T_129 = _T_128 | _T_125; // @[Mux.scala 27:72]
|
wire [3:0] _T_129 = _T_128 | _T_125; // @[Mux.scala 27:72]
|
||||||
wire _T_114 = ~fb_right; // @[el2_ifu_ifc_ctrl.scala 131:18]
|
wire _T_114 = ~fb_right; // @[el2_ifu_ifc_ctrl.scala 130:18]
|
||||||
wire _T_115 = _T_2 & _T_114; // @[el2_ifu_ifc_ctrl.scala 131:16]
|
wire _T_115 = _T_2 & _T_114; // @[el2_ifu_ifc_ctrl.scala 130:16]
|
||||||
wire _T_116 = ~fb_right2; // @[el2_ifu_ifc_ctrl.scala 131:30]
|
wire _T_116 = ~fb_right2; // @[el2_ifu_ifc_ctrl.scala 130:30]
|
||||||
wire _T_117 = _T_115 & _T_116; // @[el2_ifu_ifc_ctrl.scala 131:28]
|
wire _T_117 = _T_115 & _T_116; // @[el2_ifu_ifc_ctrl.scala 130:28]
|
||||||
wire _T_118 = ~fb_left; // @[el2_ifu_ifc_ctrl.scala 131:43]
|
wire _T_118 = ~fb_left; // @[el2_ifu_ifc_ctrl.scala 130:43]
|
||||||
wire _T_119 = _T_117 & _T_118; // @[el2_ifu_ifc_ctrl.scala 131:41]
|
wire _T_119 = _T_117 & _T_118; // @[el2_ifu_ifc_ctrl.scala 130:41]
|
||||||
wire [3:0] _T_126 = _T_119 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
|
wire [3:0] _T_126 = _T_119 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
|
||||||
wire [3:0] fb_write_ns = _T_129 | _T_126; // @[Mux.scala 27:72]
|
wire [3:0] fb_write_ns = _T_129 | _T_126; // @[Mux.scala 27:72]
|
||||||
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctrl.scala 139:30]
|
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctrl.scala 138:30]
|
||||||
wire _T_38 = fb_full_f_ns & _T_37; // @[el2_ifu_ifc_ctrl.scala 95:68]
|
wire _T_38 = fb_full_f_ns & _T_37; // @[el2_ifu_ifc_ctrl.scala 95:68]
|
||||||
wire _T_39 = ~_T_38; // @[el2_ifu_ifc_ctrl.scala 95:53]
|
wire _T_39 = ~_T_38; // @[el2_ifu_ifc_ctrl.scala 95:53]
|
||||||
wire _T_40 = io_ifc_fetch_req_bf_raw & _T_39; // @[el2_ifu_ifc_ctrl.scala 95:51]
|
wire _T_40 = io_ifc_fetch_req_bf_raw & _T_39; // @[el2_ifu_ifc_ctrl.scala 95:51]
|
||||||
|
|
@ -121,29 +120,31 @@ module el2_ifu_ifc_ctrl(
|
||||||
wire _T_79 = state[0] & _T_68; // @[el2_ifu_ifc_ctrl.scala 111:60]
|
wire _T_79 = state[0] & _T_68; // @[el2_ifu_ifc_ctrl.scala 111:60]
|
||||||
wire next_state_0 = _T_76 | _T_79; // @[el2_ifu_ifc_ctrl.scala 111:48]
|
wire next_state_0 = _T_76 | _T_79; // @[el2_ifu_ifc_ctrl.scala 111:48]
|
||||||
wire [1:0] _T_80 = {next_state_0,next_state_0}; // @[Cat.scala 29:58]
|
wire [1:0] _T_80 = {next_state_0,next_state_0}; // @[Cat.scala 29:58]
|
||||||
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctrl.scala 137:16]
|
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctrl.scala 136:16]
|
||||||
reg fb_full_f; // @[el2_ifu_ifc_ctrl.scala 140:26]
|
reg fb_full_f; // @[el2_ifu_ifc_ctrl.scala 139:26]
|
||||||
wire _T_139 = _T_36 | io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 144:47]
|
wire _T_139 = _T_36 | io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 143:47]
|
||||||
wire _T_140 = ~_T_139; // @[el2_ifu_ifc_ctrl.scala 144:5]
|
wire _T_140 = ~_T_139; // @[el2_ifu_ifc_ctrl.scala 143:5]
|
||||||
wire _T_141 = fb_full_f & _T_140; // @[el2_ifu_ifc_ctrl.scala 143:75]
|
wire _T_141 = fb_full_f & _T_140; // @[el2_ifu_ifc_ctrl.scala 142:75]
|
||||||
wire _T_142 = _T_141 | dma_stall; // @[el2_ifu_ifc_ctrl.scala 144:70]
|
wire _T_142 = _T_141 | dma_stall; // @[el2_ifu_ifc_ctrl.scala 143:70]
|
||||||
wire _T_143 = io_ifc_fetch_req_bf_raw & _T_142; // @[el2_ifu_ifc_ctrl.scala 143:60]
|
wire _T_143 = io_ifc_fetch_req_bf_raw & _T_142; // @[el2_ifu_ifc_ctrl.scala 142:60]
|
||||||
wire [31:0] _T_145 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
|
wire [31:0] _T_145 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
|
||||||
wire [4:0] _T_149 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
|
wire [4:0] _T_149 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
|
||||||
wire [31:0] _T_150 = io_dec_tlu_mrac_ff >> _T_149; // @[el2_ifu_ifc_ctrl.scala 151:53]
|
wire [31:0] _T_150 = io_dec_tlu_mrac_ff >> _T_149; // @[el2_ifu_ifc_ctrl.scala 150:53]
|
||||||
reg _T_153; // @[el2_ifu_ifc_ctrl.scala 155:32]
|
reg _T_153; // @[el2_ifu_ifc_ctrl.scala 154:32]
|
||||||
reg [30:0] _T_155; // @[Reg.scala 27:20]
|
reg [30:0] _T_155; // @[Reg.scala 27:20]
|
||||||
assign io_ifc_fetch_addr_f = _T_155; // @[el2_ifu_ifc_ctrl.scala 158:23]
|
assign io_ifc_fetch_addr_f = _T_155; // @[el2_ifu_ifc_ctrl.scala 157:23]
|
||||||
assign io_ifc_fetch_addr_bf = _T_26[30:0]; // @[el2_ifu_ifc_ctrl.scala 79:24]
|
assign io_ifc_fetch_addr_bf = _T_26[30:0]; // @[el2_ifu_ifc_ctrl.scala 81:24]
|
||||||
assign io_ifc_fetch_req_f = _T_153; // @[el2_ifu_ifc_ctrl.scala 155:22]
|
assign io_ifc_fetch_req_f = _T_153; // @[el2_ifu_ifc_ctrl.scala 154:22]
|
||||||
assign io_ifu_pmu_fetch_stall = wfm | _T_143; // @[el2_ifu_ifc_ctrl.scala 143:26]
|
assign io_ifu_pmu_fetch_stall = wfm | _T_143; // @[el2_ifu_ifc_ctrl.scala 142:26]
|
||||||
assign io_ifc_fetch_uncacheable_bf = ~_T_150[0]; // @[el2_ifu_ifc_ctrl.scala 151:31]
|
assign io_ifc_fetch_uncacheable_bf = ~_T_150[0]; // @[el2_ifu_ifc_ctrl.scala 150:31]
|
||||||
assign io_ifc_fetch_req_bf = _T_44 & _T_45; // @[el2_ifu_ifc_ctrl.scala 95:23]
|
assign io_ifc_fetch_req_bf = _T_44 & _T_45; // @[el2_ifu_ifc_ctrl.scala 95:23]
|
||||||
assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctrl.scala 93:27]
|
assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctrl.scala 93:27]
|
||||||
assign io_ifc_iccm_access_bf = _T_145[31:16] == 16'hee00; // @[el2_ifu_ifc_ctrl.scala 150:25]
|
assign io_ifc_iccm_access_bf = _T_145[31:16] == 16'hee00; // @[el2_ifu_ifc_ctrl.scala 149:25]
|
||||||
assign io_ifc_region_acc_fault_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 40:30]
|
assign io_ifc_region_acc_fault_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 42:30]
|
||||||
assign io_ifc_dma_access_ok = 1'h0; // @[el2_ifu_ifc_ctrl.scala 41:24]
|
assign io_ifc_dma_access_ok = 1'h0; // @[el2_ifu_ifc_ctrl.scala 43:24]
|
||||||
assign io_test_out = io_ifc_fetch_addr_bf; // @[el2_ifu_ifc_ctrl.scala 84:15]
|
assign io_sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctrl.scala 76:23]
|
||||||
|
assign io_sel_btb_addr_bf = _T_9 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 77:23]
|
||||||
|
assign io_sel_next_addr_bf = _T_14 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 78:23]
|
||||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||||
`define RANDOMIZE
|
`define RANDOMIZE
|
||||||
`endif
|
`endif
|
||||||
|
|
|
||||||
|
|
@ -13,19 +13,14 @@ class el2_ifu_compress_ctl extends Module {
|
||||||
val legal = Output(Bool())
|
val legal = Output(Bool())
|
||||||
val o = Output(UInt(32.W))
|
val o = Output(UInt(32.W))
|
||||||
val sluimmd = Output(UInt())
|
val sluimmd = Output(UInt())
|
||||||
// val simm5_0 = Output(Bool())
|
|
||||||
// val uimm9_2 = Output(Bool())
|
|
||||||
// val simm9_4 = Output(Bool())
|
|
||||||
// val ulwimm6_2 = Output(Bool())
|
|
||||||
// val ulwspimm7_2 = Output(Bool())
|
|
||||||
// val uimm5_0 = Output(Bool())
|
|
||||||
val uimm5d = Output(UInt())
|
val uimm5d = Output(UInt())
|
||||||
val ulwspimm7d = Output(UInt())
|
val ulwspimm7d = Output(UInt())
|
||||||
val ulwimm6d = Output(UInt())
|
val ulwimm6d = Output(UInt())
|
||||||
val simm9d = Output(UInt())
|
val simm9d = Output(UInt())
|
||||||
val uimm9d = Output(UInt())
|
val uimm9d = Output(UInt())
|
||||||
val simm5d = Output(UInt())
|
val simm5d = Output(UInt())
|
||||||
|
val sjald = Output(UInt())
|
||||||
})
|
})
|
||||||
|
|
||||||
//io.dout := (0 until 32).map(i=> 0.U.asBool)
|
//io.dout := (0 until 32).map(i=> 0.U.asBool)
|
||||||
|
|
@ -152,18 +147,19 @@ class el2_ifu_compress_ctl extends Module {
|
||||||
val sjald = Cat(sjald_12,sjald_1)
|
val sjald = Cat(sjald_12,sjald_1)
|
||||||
val sluimmd = Cat(Fill(15, io.din(12)), io.din(6,2))
|
val sluimmd = Cat(Fill(15, io.din(12)), io.din(6,2))
|
||||||
io.sluimmd := sluimmd
|
io.sluimmd := sluimmd
|
||||||
|
|
||||||
val l2_31 = l1(31,20) |
|
val l2_31 = l1(31,20) |
|
||||||
Mux1H(Seq(simm5_0.asBool->Cat(Fill(7, simm5d(5)),simm5d(4,0)),
|
Mux1H(Seq(simm5_0.asBool->Cat(Fill(7, simm5d(5)), simm5d(4,0)),
|
||||||
uimm9_2.asBool->Cat(0.U(2.W),uimm9d,0.U(2.W)),
|
uimm9_2.asBool->Cat(0.U(2.W), uimm9d, 0.U(2.W)),
|
||||||
simm9_4.asBool->Cat(Fill(3, simm9d(5)),simm9d(4,0),0.U(4.W)),
|
simm9_4.asBool->Cat(Fill(3, simm9d(5)), simm9d(4,0), 0.U(4.W)),
|
||||||
ulwimm6_2.asBool->Cat(0.U(5.W),ulwimm6d,0.U(2.W)),
|
ulwimm6_2.asBool->Cat(0.U(5.W), ulwimm6d, 0.U(2.W)),
|
||||||
ulwspimm7_2.asBool->Cat(0.U(4.W),ulwspimm7d,0.U(2.W)),
|
ulwspimm7_2.asBool->Cat(0.U(4.W), ulwspimm7d, 0.U(2.W)),
|
||||||
uimm5_0.asBool->Cat(0.U(6.W),uimm5d),
|
uimm5_0.asBool->Cat(0.U(6.W), uimm5d),
|
||||||
sjaloffset11_1->Cat(sjald(19),sjald(9,0),sjald(10)),
|
sjaloffset11_1->Cat(sjald(19), sjald(9,0), sjald(10)),
|
||||||
sluimm17_12->sluimmd(19,8)))
|
sluimm17_12->sluimmd(19,8)))
|
||||||
|
|
||||||
val l2_19 = l1(19,12) | Mux1H(Seq(sjaloffset11_1.asBool->sjald(19,11),
|
val l2_19 = l1(19,12) | Mux1H(Seq(sjaloffset11_1.asBool->sjald(19,11),
|
||||||
sluimm17_12.asBool->sluimmd(7,0)))
|
sluimm17_12.asBool->sluimmd(7,0)))
|
||||||
val l2 = Cat(l2_31, l2_19, l1(11,0))
|
val l2 = Cat(l2_31, l2_19, l1(11,0))
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -204,7 +200,7 @@ class el2_ifu_compress_ctl extends Module {
|
||||||
// io.ulwspimm7_2 := ulwspimm7_2
|
// io.ulwspimm7_2 := ulwspimm7_2
|
||||||
// io.uimm5_0 := uimm5_0
|
// io.uimm5_0 := uimm5_0
|
||||||
//
|
//
|
||||||
|
io.sjald := sjald
|
||||||
io.uimm5d := uimm5d
|
io.uimm5d := uimm5d
|
||||||
io.ulwspimm7d := ulwspimm7d
|
io.ulwspimm7d := ulwspimm7d
|
||||||
io.ulwimm6d := ulwimm6d//Output(UInt())
|
io.ulwimm6d := ulwimm6d//Output(UInt())
|
||||||
|
|
@ -214,6 +210,11 @@ class el2_ifu_compress_ctl extends Module {
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
object ifu_compress extends App {
|
||||||
|
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress_ctl()))
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
class ExpandedInstruction extends Bundle {
|
class ExpandedInstruction extends Bundle {
|
||||||
val bits = UInt(32.W)
|
val bits = UInt(32.W)
|
||||||
|
|
@ -437,6 +438,3 @@ class el2_ifu_compress_ctl( val XLen: Int, val usingCompressed: Boolean) extends
|
||||||
}
|
}
|
||||||
}*/
|
}*/
|
||||||
|
|
||||||
object ifu_compress extends App {
|
|
||||||
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress_ctl()))
|
|
||||||
}
|
|
||||||
|
|
|
||||||
|
|
@ -34,7 +34,9 @@ val io = IO(new Bundle{
|
||||||
val ifc_iccm_access_bf = Output(Bool())
|
val ifc_iccm_access_bf = Output(Bool())
|
||||||
val ifc_region_acc_fault_bf = Output(Bool())
|
val ifc_region_acc_fault_bf = Output(Bool())
|
||||||
val ifc_dma_access_ok = Output(Bool())
|
val ifc_dma_access_ok = Output(Bool())
|
||||||
val test_out = Output(UInt())
|
val sel_last_addr_bf = Output(Bool())
|
||||||
|
val sel_btb_addr_bf = Output(Bool())
|
||||||
|
val sel_next_addr_bf = Output(Bool())
|
||||||
})
|
})
|
||||||
|
|
||||||
io.ifc_region_acc_fault_bf := 0.U
|
io.ifc_region_acc_fault_bf := 0.U
|
||||||
|
|
@ -49,9 +51,9 @@ val io = IO(new Bundle{
|
||||||
val fb_left = WireInit(Bool(), init = 0.U)
|
val fb_left = WireInit(Bool(), init = 0.U)
|
||||||
val wfm = WireInit(Bool(), init = 0.U)
|
val wfm = WireInit(Bool(), init = 0.U)
|
||||||
val idle = WireInit(Bool(), init = 0.U)
|
val idle = WireInit(Bool(), init = 0.U)
|
||||||
val sel_last_addr_bf = WireInit(Bool(), init = 0.U)
|
// val sel_last_addr_bf = WireInit(Bool(), init = 0.U)
|
||||||
val sel_btb_addr_bf = WireInit(Bool(), init = 0.U)
|
// val sel_btb_addr_bf = WireInit(Bool(), init = 0.U)
|
||||||
val sel_next_addr_bf = WireInit(Bool(), init = 0.U)
|
// val sel_next_addr_bf = WireInit(Bool(), init = 0.U)
|
||||||
val miss_f = WireInit(Bool(), init = 0.U)
|
val miss_f = WireInit(Bool(), init = 0.U)
|
||||||
val miss_a = WireInit(Bool(), init = 0.U)
|
val miss_a = WireInit(Bool(), init = 0.U)
|
||||||
val flush_fb = WireInit(Bool(), init = 0.U)
|
val flush_fb = WireInit(Bool(), init = 0.U)
|
||||||
|
|
@ -71,17 +73,17 @@ val io = IO(new Bundle{
|
||||||
|
|
||||||
miss_a := RegNext(miss_f, init=0.U)
|
miss_a := RegNext(miss_f, init=0.U)
|
||||||
|
|
||||||
sel_last_addr_bf := ~io.exu_flush_final & (~io.ifc_fetch_req_f | ~io.ic_hit_f)
|
io.sel_last_addr_bf := ~io.exu_flush_final & (~io.ifc_fetch_req_f | ~io.ic_hit_f)
|
||||||
sel_btb_addr_bf := ~io.exu_flush_final & io.ifc_fetch_req_f & io.ifu_bp_hit_taken_f & io.ic_hit_f
|
io.sel_btb_addr_bf := ~io.exu_flush_final & io.ifc_fetch_req_f & io.ifu_bp_hit_taken_f & io.ic_hit_f
|
||||||
sel_next_addr_bf := ~io.exu_flush_final & io.ifc_fetch_req_f & ~io.ifu_bp_hit_taken_f & io.ic_hit_f
|
io.sel_next_addr_bf := ~io.exu_flush_final & io.ifc_fetch_req_f & ~io.ifu_bp_hit_taken_f & io.ic_hit_f
|
||||||
|
|
||||||
// TODO: Make an assertion for the 1H-Mux under here
|
// TODO: Make an assertion for the 1H-Mux under here
|
||||||
io.ifc_fetch_addr_bf := Mux1H(Seq(io.exu_flush_final.asBool -> io.exu_flush_path_final, // Replay PC
|
io.ifc_fetch_addr_bf := Mux1H(Seq(io.exu_flush_final.asBool -> io.exu_flush_path_final, // Replay PC
|
||||||
sel_last_addr_bf.asBool -> io.ifc_fetch_addr_f, // Hold the current PC
|
io.sel_last_addr_bf.asBool -> io.ifc_fetch_addr_f, // Hold the current PC
|
||||||
sel_btb_addr_bf.asBool -> io.ifu_bp_btb_target_f, // Take the predicted PC
|
io.sel_btb_addr_bf.asBool -> io.ifu_bp_btb_target_f, // Take the predicted PC
|
||||||
sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4
|
io.sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4
|
||||||
|
|
||||||
io.test_out := io.ifc_fetch_addr_bf
|
//io.test_out := io.ifc_fetch_addr_bf
|
||||||
|
|
||||||
line_wrap := 0.U//fetch_addr_next(ICACHE_TAG_INDEX_LO) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO)
|
line_wrap := 0.U//fetch_addr_next(ICACHE_TAG_INDEX_LO) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO)
|
||||||
|
|
||||||
|
|
@ -154,7 +156,7 @@ val io = IO(new Bundle{
|
||||||
|
|
||||||
io.ifc_fetch_addr_f := RegEnable(io.ifc_fetch_addr_bf, init = 0.U, io.exu_flush_final|io.ifc_fetch_req_f)
|
io.ifc_fetch_addr_f := RegEnable(io.ifc_fetch_addr_bf, init = 0.U, io.exu_flush_final|io.ifc_fetch_req_f)
|
||||||
}
|
}
|
||||||
/*
|
|
||||||
object ifu_ifc extends App {
|
object ifu_ifc extends App {
|
||||||
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ifc_ctrl()))
|
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ifc_ctrl()))
|
||||||
}*/
|
}
|
||||||
|
|
|
||||||
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Reference in New Issue